Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 00:39:24.102113 lava-dispatcher, installed at version: 2024.03
2 00:39:24.102355 start: 0 validate
3 00:39:24.102473 Start time: 2024-06-16 00:39:24.102468+00:00 (UTC)
4 00:39:24.102608 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:39:24.102743 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:39:24.355587 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:39:24.356319 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:40:15.136524 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:40:15.136988 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:40:15.389260 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:40:15.389905 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:40:15.885610 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:40:15.886288 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:40:18.392282 validate duration: 54.29
16 00:40:18.392581 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:40:18.392710 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:40:18.392798 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:40:18.392986 Not decompressing ramdisk as can be used compressed.
20 00:40:18.393076 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:40:18.393139 saving as /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/ramdisk/initrd.cpio.gz
22 00:40:18.393196 total size: 5628169 (5 MB)
23 00:40:18.642633 progress 0 % (0 MB)
24 00:40:18.644639 progress 5 % (0 MB)
25 00:40:18.646274 progress 10 % (0 MB)
26 00:40:18.647651 progress 15 % (0 MB)
27 00:40:18.649168 progress 20 % (1 MB)
28 00:40:18.650507 progress 25 % (1 MB)
29 00:40:18.652066 progress 30 % (1 MB)
30 00:40:18.653577 progress 35 % (1 MB)
31 00:40:18.654914 progress 40 % (2 MB)
32 00:40:18.656397 progress 45 % (2 MB)
33 00:40:18.657739 progress 50 % (2 MB)
34 00:40:18.659277 progress 55 % (2 MB)
35 00:40:18.660802 progress 60 % (3 MB)
36 00:40:18.662136 progress 65 % (3 MB)
37 00:40:18.663625 progress 70 % (3 MB)
38 00:40:18.664980 progress 75 % (4 MB)
39 00:40:18.666581 progress 80 % (4 MB)
40 00:40:18.667911 progress 85 % (4 MB)
41 00:40:18.669448 progress 90 % (4 MB)
42 00:40:18.671017 progress 95 % (5 MB)
43 00:40:18.672363 progress 100 % (5 MB)
44 00:40:18.672585 5 MB downloaded in 0.28 s (19.21 MB/s)
45 00:40:18.672747 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:40:18.672971 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:40:18.673050 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:40:18.673125 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:40:18.673239 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:40:18.673300 saving as /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/kernel/Image
52 00:40:18.673353 total size: 54813184 (52 MB)
53 00:40:18.673414 No compression specified
54 00:40:18.675263 progress 0 % (0 MB)
55 00:40:18.689365 progress 5 % (2 MB)
56 00:40:18.703389 progress 10 % (5 MB)
57 00:40:18.717337 progress 15 % (7 MB)
58 00:40:18.731149 progress 20 % (10 MB)
59 00:40:18.745122 progress 25 % (13 MB)
60 00:40:18.759464 progress 30 % (15 MB)
61 00:40:18.773385 progress 35 % (18 MB)
62 00:40:18.787288 progress 40 % (20 MB)
63 00:40:18.801321 progress 45 % (23 MB)
64 00:40:18.815473 progress 50 % (26 MB)
65 00:40:18.829733 progress 55 % (28 MB)
66 00:40:18.843597 progress 60 % (31 MB)
67 00:40:18.857562 progress 65 % (34 MB)
68 00:40:18.871382 progress 70 % (36 MB)
69 00:40:18.885321 progress 75 % (39 MB)
70 00:40:18.899272 progress 80 % (41 MB)
71 00:40:18.913150 progress 85 % (44 MB)
72 00:40:18.927016 progress 90 % (47 MB)
73 00:40:18.940775 progress 95 % (49 MB)
74 00:40:18.955036 progress 100 % (52 MB)
75 00:40:18.955284 52 MB downloaded in 0.28 s (185.42 MB/s)
76 00:40:18.955428 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:40:18.955634 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:40:18.955715 start: 1.3 download-retry (timeout 00:09:59) [common]
80 00:40:18.955791 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 00:40:18.955917 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:40:18.955979 saving as /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/dtb/mt8192-asurada-spherion-r0.dtb
83 00:40:18.956032 total size: 47258 (0 MB)
84 00:40:18.956086 No compression specified
85 00:40:18.957292 progress 69 % (0 MB)
86 00:40:18.957548 progress 100 % (0 MB)
87 00:40:18.957699 0 MB downloaded in 0.00 s (27.07 MB/s)
88 00:40:18.957810 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:40:18.958008 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:40:18.958084 start: 1.4 download-retry (timeout 00:09:59) [common]
92 00:40:18.958160 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 00:40:18.958262 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:40:18.958322 saving as /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/nfsrootfs/full.rootfs.tar
95 00:40:18.958374 total size: 120894716 (115 MB)
96 00:40:18.958428 Using unxz to decompress xz
97 00:40:18.959691 progress 0 % (0 MB)
98 00:40:19.298681 progress 5 % (5 MB)
99 00:40:19.649487 progress 10 % (11 MB)
100 00:40:19.989799 progress 15 % (17 MB)
101 00:40:20.310787 progress 20 % (23 MB)
102 00:40:20.617382 progress 25 % (28 MB)
103 00:40:20.973597 progress 30 % (34 MB)
104 00:40:21.296763 progress 35 % (40 MB)
105 00:40:21.469552 progress 40 % (46 MB)
106 00:40:21.650678 progress 45 % (51 MB)
107 00:40:21.957249 progress 50 % (57 MB)
108 00:40:22.310512 progress 55 % (63 MB)
109 00:40:22.644596 progress 60 % (69 MB)
110 00:40:22.979798 progress 65 % (74 MB)
111 00:40:23.328156 progress 70 % (80 MB)
112 00:40:23.671073 progress 75 % (86 MB)
113 00:40:24.002196 progress 80 % (92 MB)
114 00:40:24.344762 progress 85 % (98 MB)
115 00:40:24.686182 progress 90 % (103 MB)
116 00:40:25.009335 progress 95 % (109 MB)
117 00:40:25.369309 progress 100 % (115 MB)
118 00:40:25.374709 115 MB downloaded in 6.42 s (17.97 MB/s)
119 00:40:25.374863 end: 1.4.1 http-download (duration 00:00:06) [common]
121 00:40:25.375075 end: 1.4 download-retry (duration 00:00:06) [common]
122 00:40:25.375154 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:40:25.375229 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:40:25.375358 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:40:25.375421 saving as /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/modules/modules.tar
126 00:40:25.375474 total size: 8608736 (8 MB)
127 00:40:25.375527 Using unxz to decompress xz
128 00:40:25.376828 progress 0 % (0 MB)
129 00:40:25.395744 progress 5 % (0 MB)
130 00:40:25.422706 progress 10 % (0 MB)
131 00:40:25.450844 progress 15 % (1 MB)
132 00:40:25.474420 progress 20 % (1 MB)
133 00:40:25.497587 progress 25 % (2 MB)
134 00:40:25.521150 progress 30 % (2 MB)
135 00:40:25.545452 progress 35 % (2 MB)
136 00:40:25.571268 progress 40 % (3 MB)
137 00:40:25.593678 progress 45 % (3 MB)
138 00:40:25.617572 progress 50 % (4 MB)
139 00:40:25.643828 progress 55 % (4 MB)
140 00:40:25.667530 progress 60 % (4 MB)
141 00:40:25.690913 progress 65 % (5 MB)
142 00:40:25.715100 progress 70 % (5 MB)
143 00:40:25.740434 progress 75 % (6 MB)
144 00:40:25.765500 progress 80 % (6 MB)
145 00:40:25.788921 progress 85 % (7 MB)
146 00:40:25.813488 progress 90 % (7 MB)
147 00:40:25.837874 progress 95 % (7 MB)
148 00:40:25.862091 progress 100 % (8 MB)
149 00:40:25.867330 8 MB downloaded in 0.49 s (16.69 MB/s)
150 00:40:25.867484 end: 1.5.1 http-download (duration 00:00:00) [common]
152 00:40:25.867693 end: 1.5 download-retry (duration 00:00:00) [common]
153 00:40:25.867772 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 00:40:25.867848 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 00:40:29.331100 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368360/extract-nfsrootfs-o5lwayju
156 00:40:29.331288 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 00:40:29.331379 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 00:40:29.331549 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4
159 00:40:29.331667 makedir: /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin
160 00:40:29.331759 makedir: /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/tests
161 00:40:29.331848 makedir: /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/results
162 00:40:29.331932 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-add-keys
163 00:40:29.332062 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-add-sources
164 00:40:29.332180 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-background-process-start
165 00:40:29.332298 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-background-process-stop
166 00:40:29.332423 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-common-functions
167 00:40:29.332538 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-echo-ipv4
168 00:40:29.332678 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-install-packages
169 00:40:29.332808 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-installed-packages
170 00:40:29.332920 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-os-build
171 00:40:29.333032 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-probe-channel
172 00:40:29.333144 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-probe-ip
173 00:40:29.333257 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-target-ip
174 00:40:29.333369 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-target-mac
175 00:40:29.333486 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-target-storage
176 00:40:29.333602 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-test-case
177 00:40:29.333716 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-test-event
178 00:40:29.333827 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-test-feedback
179 00:40:29.333939 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-test-raise
180 00:40:29.334049 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-test-reference
181 00:40:29.334161 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-test-runner
182 00:40:29.334272 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-test-set
183 00:40:29.334383 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-test-shell
184 00:40:29.334497 Updating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-add-keys (debian)
185 00:40:29.334640 Updating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-add-sources (debian)
186 00:40:29.334767 Updating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-install-packages (debian)
187 00:40:29.334891 Updating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-installed-packages (debian)
188 00:40:29.335015 Updating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/bin/lava-os-build (debian)
189 00:40:29.335123 Creating /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/environment
190 00:40:29.335209 LAVA metadata
191 00:40:29.335275 - LAVA_JOB_ID=14368360
192 00:40:29.335332 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:40:29.335426 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 00:40:29.335483 skipped lava-vland-overlay
195 00:40:29.335552 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:40:29.335623 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 00:40:29.335676 skipped lava-multinode-overlay
198 00:40:29.335740 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:40:29.335809 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 00:40:29.335884 Loading test definitions
201 00:40:29.335962 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 00:40:29.336021 Using /lava-14368360 at stage 0
203 00:40:29.336296 uuid=14368360_1.6.2.3.1 testdef=None
204 00:40:29.336376 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:40:29.336452 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 00:40:29.336885 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:40:29.337087 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 00:40:29.337596 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:40:29.337803 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 00:40:29.338293 runner path: /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/0/tests/0_timesync-off test_uuid 14368360_1.6.2.3.1
213 00:40:29.338437 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:40:29.338641 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 00:40:29.338708 Using /lava-14368360 at stage 0
217 00:40:29.338795 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:40:29.338870 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/0/tests/1_kselftest-dt'
219 00:40:31.986703 Running '/usr/bin/git checkout kernelci.org
220 00:40:32.134397 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 00:40:32.134762 uuid=14368360_1.6.2.3.5 testdef=None
222 00:40:32.134866 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 00:40:32.135063 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 00:40:32.135703 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:40:32.135908 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 00:40:32.136830 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:40:32.137048 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 00:40:32.137888 runner path: /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/0/tests/1_kselftest-dt test_uuid 14368360_1.6.2.3.5
232 00:40:32.137971 BOARD='mt8192-asurada-spherion-r0'
233 00:40:32.138030 BRANCH='cip'
234 00:40:32.138084 SKIPFILE='/dev/null'
235 00:40:32.138134 SKIP_INSTALL='True'
236 00:40:32.138182 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:40:32.138233 TST_CASENAME=''
238 00:40:32.138283 TST_CMDFILES='dt'
239 00:40:32.138415 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:40:32.138597 Creating lava-test-runner.conf files
242 00:40:32.138651 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368360/lava-overlay-68bzgov4/lava-14368360/0 for stage 0
243 00:40:32.138732 - 0_timesync-off
244 00:40:32.138791 - 1_kselftest-dt
245 00:40:32.138878 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 00:40:32.138956 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 00:40:39.303185 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:40:39.303332 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 00:40:39.303434 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:40:39.303534 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 00:40:39.303629 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 00:40:39.461570 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:40:39.461726 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 00:40:39.461838 extracting modules file /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368360/extract-nfsrootfs-o5lwayju
255 00:40:39.687447 extracting modules file /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368360/extract-overlay-ramdisk-4u50yniu/ramdisk
256 00:40:39.909602 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:40:39.909743 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 00:40:39.909821 [common] Applying overlay to NFS
259 00:40:39.909881 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368360/compress-overlay-syhy0hbb/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368360/extract-nfsrootfs-o5lwayju
260 00:40:40.737462 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:40:40.737629 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 00:40:40.737737 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:40:40.737843 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 00:40:40.737939 Building ramdisk /var/lib/lava/dispatcher/tmp/14368360/extract-overlay-ramdisk-4u50yniu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368360/extract-overlay-ramdisk-4u50yniu/ramdisk
265 00:40:41.067143 >> 130405 blocks
266 00:40:43.135100 rename /var/lib/lava/dispatcher/tmp/14368360/extract-overlay-ramdisk-4u50yniu/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/ramdisk/ramdisk.cpio.gz
267 00:40:43.135330 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:40:43.135454 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 00:40:43.135567 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 00:40:43.135682 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/kernel/Image']
271 00:40:56.974600 Returned 0 in 13 seconds
272 00:40:57.075142 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/kernel/image.itb
273 00:40:57.469372 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:40:57.469588 output: Created: Sun Jun 16 01:40:57 2024
275 00:40:57.469737 output: Image 0 (kernel-1)
276 00:40:57.469852 output: Description:
277 00:40:57.469938 output: Created: Sun Jun 16 01:40:57 2024
278 00:40:57.470027 output: Type: Kernel Image
279 00:40:57.470115 output: Compression: lzma compressed
280 00:40:57.470203 output: Data Size: 13126376 Bytes = 12818.73 KiB = 12.52 MiB
281 00:40:57.470288 output: Architecture: AArch64
282 00:40:57.470372 output: OS: Linux
283 00:40:57.470455 output: Load Address: 0x00000000
284 00:40:57.470539 output: Entry Point: 0x00000000
285 00:40:57.470622 output: Hash algo: crc32
286 00:40:57.470701 output: Hash value: c791a20a
287 00:40:57.470783 output: Image 1 (fdt-1)
288 00:40:57.470859 output: Description: mt8192-asurada-spherion-r0
289 00:40:57.470939 output: Created: Sun Jun 16 01:40:57 2024
290 00:40:57.471017 output: Type: Flat Device Tree
291 00:40:57.471096 output: Compression: uncompressed
292 00:40:57.471231 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:40:57.471354 output: Architecture: AArch64
294 00:40:57.471431 output: Hash algo: crc32
295 00:40:57.471505 output: Hash value: 0f8e4d2e
296 00:40:57.471580 output: Image 2 (ramdisk-1)
297 00:40:57.471655 output: Description: unavailable
298 00:40:57.471729 output: Created: Sun Jun 16 01:40:57 2024
299 00:40:57.471804 output: Type: RAMDisk Image
300 00:40:57.471879 output: Compression: uncompressed
301 00:40:57.471953 output: Data Size: 18735270 Bytes = 18296.16 KiB = 17.87 MiB
302 00:40:57.472027 output: Architecture: AArch64
303 00:40:57.472117 output: OS: Linux
304 00:40:57.472206 output: Load Address: unavailable
305 00:40:57.472296 output: Entry Point: unavailable
306 00:40:57.472385 output: Hash algo: crc32
307 00:40:57.472459 output: Hash value: 9c49befd
308 00:40:57.472534 output: Default Configuration: 'conf-1'
309 00:40:57.472608 output: Configuration 0 (conf-1)
310 00:40:57.472723 output: Description: mt8192-asurada-spherion-r0
311 00:40:57.472798 output: Kernel: kernel-1
312 00:40:57.472874 output: Init Ramdisk: ramdisk-1
313 00:40:57.472956 output: FDT: fdt-1
314 00:40:57.473038 output: Loadables: kernel-1
315 00:40:57.473103 output:
316 00:40:57.473268 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 00:40:57.473394 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 00:40:57.473524 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 00:40:57.473643 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 00:40:57.473740 No LXC device requested
321 00:40:57.473828 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:40:57.473921 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 00:40:57.474003 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:40:57.474073 Checking files for TFTP limit of 4294967296 bytes.
325 00:40:57.474670 end: 1 tftp-deploy (duration 00:00:39) [common]
326 00:40:57.474800 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:40:57.474918 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:40:57.475078 substitutions:
329 00:40:57.475166 - {DTB}: 14368360/tftp-deploy-nxziam0o/dtb/mt8192-asurada-spherion-r0.dtb
330 00:40:57.475260 - {INITRD}: 14368360/tftp-deploy-nxziam0o/ramdisk/ramdisk.cpio.gz
331 00:40:57.475350 - {KERNEL}: 14368360/tftp-deploy-nxziam0o/kernel/Image
332 00:40:57.475437 - {LAVA_MAC}: None
333 00:40:57.475524 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368360/extract-nfsrootfs-o5lwayju
334 00:40:57.475611 - {NFS_SERVER_IP}: 192.168.201.1
335 00:40:57.475696 - {PRESEED_CONFIG}: None
336 00:40:57.475790 - {PRESEED_LOCAL}: None
337 00:40:57.475874 - {RAMDISK}: 14368360/tftp-deploy-nxziam0o/ramdisk/ramdisk.cpio.gz
338 00:40:57.475959 - {ROOT_PART}: None
339 00:40:57.476043 - {ROOT}: None
340 00:40:57.476126 - {SERVER_IP}: 192.168.201.1
341 00:40:57.476210 - {TEE}: None
342 00:40:57.476294 Parsed boot commands:
343 00:40:57.476396 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:40:57.476619 Parsed boot commands: tftpboot 192.168.201.1 14368360/tftp-deploy-nxziam0o/kernel/image.itb 14368360/tftp-deploy-nxziam0o/kernel/cmdline
345 00:40:57.476774 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:40:57.476888 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:40:57.477005 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:40:57.477116 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:40:57.477208 Not connected, no need to disconnect.
350 00:40:57.477323 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:40:57.477438 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:40:57.477530 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 00:40:57.481047 Setting prompt string to ['lava-test: # ']
354 00:40:57.481388 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:40:57.481502 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:40:57.481609 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:40:57.481709 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:40:57.481890 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-8']
359 00:41:11.331535 Returned 0 in 13 seconds
360 00:41:11.432500 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 00:41:11.433961 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 00:41:11.434507 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 00:41:11.434980 Setting prompt string to 'Starting depthcharge on Spherion...'
365 00:41:11.435323 Changing prompt to 'Starting depthcharge on Spherion...'
366 00:41:11.435681 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 00:41:11.437490 [Enter `^Ec?' for help]
368 00:41:11.437564
369 00:41:11.437623
370 00:41:11.437680 F0: 102B 0000
371 00:41:11.437737
372 00:41:11.437791 F3: 1001 0000 [0200]
373 00:41:11.437848
374 00:41:11.437906 F3: 1001 0000
375 00:41:11.437961
376 00:41:11.438017 F7: 102D 0000
377 00:41:11.438072
378 00:41:11.438129 F1: 0000 0000
379 00:41:11.438184
380 00:41:11.438238 V0: 0000 0000 [0001]
381 00:41:11.438293
382 00:41:11.438414 00: 0007 8000
383 00:41:11.438468
384 00:41:11.438517 01: 0000 0000
385 00:41:11.438567
386 00:41:11.438615 BP: 0C00 0209 [0000]
387 00:41:11.438665
388 00:41:11.438712 G0: 1182 0000
389 00:41:11.438760
390 00:41:11.438809 EC: 0000 0021 [4000]
391 00:41:11.438856
392 00:41:11.438905 S7: 0000 0000 [0000]
393 00:41:11.438953
394 00:41:11.439001 CC: 0000 0000 [0001]
395 00:41:11.439048
396 00:41:11.439096 T0: 0000 0040 [010F]
397 00:41:11.439144
398 00:41:11.439191 Jump to BL
399 00:41:11.439239
400 00:41:11.439288
401 00:41:11.439336
402 00:41:11.439385 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 00:41:11.439437 ARM64: Exception handlers installed.
404 00:41:11.439486 ARM64: Testing exception
405 00:41:11.439535 ARM64: Done test exception
406 00:41:11.439584 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 00:41:11.439633 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 00:41:11.439684 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 00:41:11.439734 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 00:41:11.439784 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 00:41:11.439833 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 00:41:11.439882 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 00:41:11.439931 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 00:41:11.439979 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 00:41:11.440029 WDT: Last reset was cold boot
416 00:41:11.440078 SPI1(PAD0) initialized at 2873684 Hz
417 00:41:11.440127 SPI5(PAD0) initialized at 992727 Hz
418 00:41:11.440175 VBOOT: Loading verstage.
419 00:41:11.440223 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 00:41:11.440273 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 00:41:11.440330 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 00:41:11.440414 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 00:41:11.440473 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 00:41:11.440555 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 00:41:11.440605 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 00:41:11.440659
427 00:41:11.440708
428 00:41:11.440756 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 00:41:11.440807 ARM64: Exception handlers installed.
430 00:41:11.440856 ARM64: Testing exception
431 00:41:11.440905 ARM64: Done test exception
432 00:41:11.440954 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 00:41:11.441003 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 00:41:11.441052 Probing TPM: . done!
435 00:41:11.441101 TPM ready after 0 ms
436 00:41:11.441150 Connected to device vid:did:rid of 1ae0:0028:00
437 00:41:11.441199 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
438 00:41:11.441249 Initialized TPM device CR50 revision 0
439 00:41:11.441297 tlcl_send_startup: Startup return code is 0
440 00:41:11.441346 TPM: setup succeeded
441 00:41:11.441395 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 00:41:11.441445 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 00:41:11.441494 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 00:41:11.441543 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 00:41:11.441592 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 00:41:11.441642 in-header: 03 07 00 00 08 00 00 00
447 00:41:11.441690 in-data: aa e4 47 04 13 02 00 00
448 00:41:11.441738 Chrome EC: UHEPI supported
449 00:41:11.441787 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 00:41:11.441837 in-header: 03 a9 00 00 08 00 00 00
451 00:41:11.441885 in-data: 84 60 60 08 00 00 00 00
452 00:41:11.441933 Phase 1
453 00:41:11.441981 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 00:41:11.442030 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 00:41:11.442080 VB2:vb2_check_recovery() Recovery was requested manually
456 00:41:11.442129 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 00:41:11.442179 Recovery requested (1009000e)
458 00:41:11.442227 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 00:41:11.442276 tlcl_extend: response is 0
460 00:41:11.442324 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 00:41:11.442373 tlcl_extend: response is 0
462 00:41:11.442421 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 00:41:11.442471 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 00:41:11.442520 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 00:41:11.442569
466 00:41:11.442617
467 00:41:11.442665 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 00:41:11.442715 ARM64: Exception handlers installed.
469 00:41:11.442763 ARM64: Testing exception
470 00:41:11.442811 ARM64: Done test exception
471 00:41:11.442860 pmic_efuse_setting: Set efuses in 11 msecs
472 00:41:11.442909 pmwrap_interface_init: Select PMIF_VLD_RDY
473 00:41:11.442957 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 00:41:11.443006 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 00:41:11.443250 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 00:41:11.443307 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 00:41:11.443358 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 00:41:11.443408 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 00:41:11.443457 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 00:41:11.443506 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 00:41:11.443555 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 00:41:11.443604 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 00:41:11.443652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 00:41:11.443700 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 00:41:11.443749 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 00:41:11.443798 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 00:41:11.443847 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 00:41:11.443897 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 00:41:11.443945 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 00:41:11.443994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 00:41:11.444043 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 00:41:11.444091 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 00:41:11.444140 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 00:41:11.444189 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 00:41:11.444239 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 00:41:11.444287 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 00:41:11.444336 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 00:41:11.444385 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 00:41:11.444435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 00:41:11.444484 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 00:41:11.444533 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 00:41:11.444582 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 00:41:11.444631 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 00:41:11.444718 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 00:41:11.444767 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 00:41:11.444816 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 00:41:11.444864 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 00:41:11.444913 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 00:41:11.444962 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 00:41:11.445010 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 00:41:11.445061 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 00:41:11.445110 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 00:41:11.445159 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 00:41:11.445208 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 00:41:11.445256 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 00:41:11.445304 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 00:41:11.445352 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 00:41:11.445402 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 00:41:11.445450 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 00:41:11.445498 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 00:41:11.445547 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 00:41:11.445595 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 00:41:11.445643 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 00:41:11.445692 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 00:41:11.445741 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 00:41:11.445790 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 00:41:11.445840 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 00:41:11.445890 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 00:41:11.445940 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 00:41:11.445988 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:41:11.446037 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:41:11.446085 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x5
533 00:41:11.446135 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 00:41:11.446185 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
535 00:41:11.446234 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 00:41:11.446283 [RTC]rtc_get_frequency_meter,154: input=15, output=795
537 00:41:11.446332 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
538 00:41:11.446382 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
539 00:41:11.446430 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
540 00:41:11.446479 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
541 00:41:11.446528 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
542 00:41:11.446576 ADC[4]: Raw value=894821 ID=7
543 00:41:11.446624 ADC[3]: Raw value=212700 ID=1
544 00:41:11.446672 RAM Code: 0x71
545 00:41:11.446721 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
546 00:41:11.446771 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
547 00:41:11.447009 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
548 00:41:11.447127 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
549 00:41:11.447239 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
550 00:41:11.447351 in-header: 03 07 00 00 08 00 00 00
551 00:41:11.447497 in-data: aa e4 47 04 13 02 00 00
552 00:41:11.447606 Chrome EC: UHEPI supported
553 00:41:11.447718 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
554 00:41:11.447828 in-header: 03 a9 00 00 08 00 00 00
555 00:41:11.447937 in-data: 84 60 60 08 00 00 00 00
556 00:41:11.448042 MRC: failed to locate region type 0.
557 00:41:11.448150 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
558 00:41:11.448260 DRAM-K: Running full calibration
559 00:41:11.448321 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
560 00:41:11.448372 header.status = 0x0
561 00:41:11.448422 header.version = 0x6 (expected: 0x6)
562 00:41:11.448470 header.size = 0xd00 (expected: 0xd00)
563 00:41:11.448519 header.flags = 0x0
564 00:41:11.448568 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
565 00:41:11.448617 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
566 00:41:11.448702 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
567 00:41:11.448752 dram_init: ddr_geometry: 2
568 00:41:11.448801 [EMI] MDL number = 2
569 00:41:11.448850 [EMI] Get MDL freq = 0
570 00:41:11.448898 dram_init: ddr_type: 0
571 00:41:11.448946 is_discrete_lpddr4: 1
572 00:41:11.448994 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
573 00:41:11.449042
574 00:41:11.449090
575 00:41:11.449160 [Bian_co] ETT version 0.0.0.1
576 00:41:11.449211 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
577 00:41:11.449260
578 00:41:11.449308 dramc_set_vcore_voltage set vcore to 650000
579 00:41:11.449358 Read voltage for 800, 4
580 00:41:11.449406 Vio18 = 0
581 00:41:11.449455 Vcore = 650000
582 00:41:11.449503 Vdram = 0
583 00:41:11.449552 Vddq = 0
584 00:41:11.449600 Vmddr = 0
585 00:41:11.449648 dram_init: config_dvfs: 1
586 00:41:11.449698 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
587 00:41:11.449748 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
588 00:41:11.449797 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
589 00:41:11.449846 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
590 00:41:11.449896 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
591 00:41:11.449945 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
592 00:41:11.449994 MEM_TYPE=3, freq_sel=18
593 00:41:11.450043 sv_algorithm_assistance_LP4_1600
594 00:41:11.450091 ============ PULL DRAM RESETB DOWN ============
595 00:41:11.450144 ========== PULL DRAM RESETB DOWN end =========
596 00:41:11.450194 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
597 00:41:11.450244 ===================================
598 00:41:11.450292 LPDDR4 DRAM CONFIGURATION
599 00:41:11.450341 ===================================
600 00:41:11.450390 EX_ROW_EN[0] = 0x0
601 00:41:11.450438 EX_ROW_EN[1] = 0x0
602 00:41:11.450486 LP4Y_EN = 0x0
603 00:41:11.450534 WORK_FSP = 0x0
604 00:41:11.450582 WL = 0x2
605 00:41:11.450631 RL = 0x2
606 00:41:11.450679 BL = 0x2
607 00:41:11.450727 RPST = 0x0
608 00:41:11.450776 RD_PRE = 0x0
609 00:41:11.450824 WR_PRE = 0x1
610 00:41:11.450872 WR_PST = 0x0
611 00:41:11.450920 DBI_WR = 0x0
612 00:41:11.450968 DBI_RD = 0x0
613 00:41:11.451016 OTF = 0x1
614 00:41:11.451064 ===================================
615 00:41:11.451113 ===================================
616 00:41:11.451162 ANA top config
617 00:41:11.451211 ===================================
618 00:41:11.451260 DLL_ASYNC_EN = 0
619 00:41:11.451308 ALL_SLAVE_EN = 1
620 00:41:11.451356 NEW_RANK_MODE = 1
621 00:41:11.451406 DLL_IDLE_MODE = 1
622 00:41:11.451454 LP45_APHY_COMB_EN = 1
623 00:41:11.451502 TX_ODT_DIS = 1
624 00:41:11.451551 NEW_8X_MODE = 1
625 00:41:11.451600 ===================================
626 00:41:11.451648 ===================================
627 00:41:11.451697 data_rate = 1600
628 00:41:11.451746 CKR = 1
629 00:41:11.451795 DQ_P2S_RATIO = 8
630 00:41:11.451843 ===================================
631 00:41:11.451892 CA_P2S_RATIO = 8
632 00:41:11.451940 DQ_CA_OPEN = 0
633 00:41:11.451989 DQ_SEMI_OPEN = 0
634 00:41:11.452037 CA_SEMI_OPEN = 0
635 00:41:11.452085 CA_FULL_RATE = 0
636 00:41:11.452133 DQ_CKDIV4_EN = 1
637 00:41:11.452182 CA_CKDIV4_EN = 1
638 00:41:11.452230 CA_PREDIV_EN = 0
639 00:41:11.452278 PH8_DLY = 0
640 00:41:11.452326 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
641 00:41:11.452374 DQ_AAMCK_DIV = 4
642 00:41:11.452422 CA_AAMCK_DIV = 4
643 00:41:11.452471 CA_ADMCK_DIV = 4
644 00:41:11.452519 DQ_TRACK_CA_EN = 0
645 00:41:11.452567 CA_PICK = 800
646 00:41:11.452615 CA_MCKIO = 800
647 00:41:11.452690 MCKIO_SEMI = 0
648 00:41:11.452743 PLL_FREQ = 3068
649 00:41:11.452791 DQ_UI_PI_RATIO = 32
650 00:41:11.452839 CA_UI_PI_RATIO = 0
651 00:41:11.452888 ===================================
652 00:41:11.452937 ===================================
653 00:41:11.452986 memory_type:LPDDR4
654 00:41:11.453034 GP_NUM : 10
655 00:41:11.453083 SRAM_EN : 1
656 00:41:11.453131 MD32_EN : 0
657 00:41:11.453179 ===================================
658 00:41:11.453227 [ANA_INIT] >>>>>>>>>>>>>>
659 00:41:11.453275 <<<<<< [CONFIGURE PHASE]: ANA_TX
660 00:41:11.453327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
661 00:41:11.453376 ===================================
662 00:41:11.453425 data_rate = 1600,PCW = 0X7600
663 00:41:11.453473 ===================================
664 00:41:11.453522 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
665 00:41:11.453571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
666 00:41:11.453620 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 00:41:11.453876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
668 00:41:11.453935 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
669 00:41:11.453986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
670 00:41:11.454035 [ANA_INIT] flow start
671 00:41:11.454084 [ANA_INIT] PLL >>>>>>>>
672 00:41:11.454132 [ANA_INIT] PLL <<<<<<<<
673 00:41:11.454180 [ANA_INIT] MIDPI >>>>>>>>
674 00:41:11.454228 [ANA_INIT] MIDPI <<<<<<<<
675 00:41:11.454277 [ANA_INIT] DLL >>>>>>>>
676 00:41:11.454326 [ANA_INIT] flow end
677 00:41:11.454375 ============ LP4 DIFF to SE enter ============
678 00:41:11.454424 ============ LP4 DIFF to SE exit ============
679 00:41:11.454472 [ANA_INIT] <<<<<<<<<<<<<
680 00:41:11.454520 [Flow] Enable top DCM control >>>>>
681 00:41:11.454569 [Flow] Enable top DCM control <<<<<
682 00:41:11.454617 Enable DLL master slave shuffle
683 00:41:11.454665 ==============================================================
684 00:41:11.454713 Gating Mode config
685 00:41:11.454762 ==============================================================
686 00:41:11.454810 Config description:
687 00:41:11.454859 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
688 00:41:11.454909 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
689 00:41:11.454958 SELPH_MODE 0: By rank 1: By Phase
690 00:41:11.455007 ==============================================================
691 00:41:11.455056 GAT_TRACK_EN = 1
692 00:41:11.455105 RX_GATING_MODE = 2
693 00:41:11.455154 RX_GATING_TRACK_MODE = 2
694 00:41:11.455202 SELPH_MODE = 1
695 00:41:11.455251 PICG_EARLY_EN = 1
696 00:41:11.455299 VALID_LAT_VALUE = 1
697 00:41:11.455347 ==============================================================
698 00:41:11.455396 Enter into Gating configuration >>>>
699 00:41:11.455444 Exit from Gating configuration <<<<
700 00:41:11.455492 Enter into DVFS_PRE_config >>>>>
701 00:41:11.455541 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
702 00:41:11.455593 Exit from DVFS_PRE_config <<<<<
703 00:41:11.455642 Enter into PICG configuration >>>>
704 00:41:11.455690 Exit from PICG configuration <<<<
705 00:41:11.455739 [RX_INPUT] configuration >>>>>
706 00:41:11.455788 [RX_INPUT] configuration <<<<<
707 00:41:11.455836 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
708 00:41:11.455885 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
709 00:41:11.455934 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
710 00:41:11.455984 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
711 00:41:11.456033 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
712 00:41:11.456082 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
713 00:41:11.456154 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
714 00:41:11.456206 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
715 00:41:11.456255 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
716 00:41:11.456304 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
717 00:41:11.456352 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
718 00:41:11.456401 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
719 00:41:11.456450 ===================================
720 00:41:11.456499 LPDDR4 DRAM CONFIGURATION
721 00:41:11.456547 ===================================
722 00:41:11.456595 EX_ROW_EN[0] = 0x0
723 00:41:11.456655 EX_ROW_EN[1] = 0x0
724 00:41:11.456706 LP4Y_EN = 0x0
725 00:41:11.456754 WORK_FSP = 0x0
726 00:41:11.456802 WL = 0x2
727 00:41:11.456851 RL = 0x2
728 00:41:11.456898 BL = 0x2
729 00:41:11.456947 RPST = 0x0
730 00:41:11.456995 RD_PRE = 0x0
731 00:41:11.457043 WR_PRE = 0x1
732 00:41:11.457091 WR_PST = 0x0
733 00:41:11.457138 DBI_WR = 0x0
734 00:41:11.457186 DBI_RD = 0x0
735 00:41:11.457233 OTF = 0x1
736 00:41:11.457281 ===================================
737 00:41:11.457331 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
738 00:41:11.457379 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
739 00:41:11.457428 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
740 00:41:11.457476 ===================================
741 00:41:11.457525 LPDDR4 DRAM CONFIGURATION
742 00:41:11.457573 ===================================
743 00:41:11.457622 EX_ROW_EN[0] = 0x10
744 00:41:11.457670 EX_ROW_EN[1] = 0x0
745 00:41:11.457719 LP4Y_EN = 0x0
746 00:41:11.457767 WORK_FSP = 0x0
747 00:41:11.457815 WL = 0x2
748 00:41:11.457862 RL = 0x2
749 00:41:11.457910 BL = 0x2
750 00:41:11.457958 RPST = 0x0
751 00:41:11.458007 RD_PRE = 0x0
752 00:41:11.458056 WR_PRE = 0x1
753 00:41:11.458104 WR_PST = 0x0
754 00:41:11.458152 DBI_WR = 0x0
755 00:41:11.458199 DBI_RD = 0x0
756 00:41:11.458247 OTF = 0x1
757 00:41:11.458296 ===================================
758 00:41:11.458345 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
759 00:41:11.458395 nWR fixed to 40
760 00:41:11.458444 [ModeRegInit_LP4] CH0 RK0
761 00:41:11.458492 [ModeRegInit_LP4] CH0 RK1
762 00:41:11.458541 [ModeRegInit_LP4] CH1 RK0
763 00:41:11.458588 [ModeRegInit_LP4] CH1 RK1
764 00:41:11.458636 match AC timing 13
765 00:41:11.458684 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
766 00:41:11.458733 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
767 00:41:11.458783 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
768 00:41:11.458831 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
769 00:41:11.458880 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
770 00:41:11.458929 [EMI DOE] emi_dcm 0
771 00:41:11.458983 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
772 00:41:11.459045 ==
773 00:41:11.459095 Dram Type= 6, Freq= 0, CH_0, rank 0
774 00:41:11.459144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 00:41:11.459193 ==
776 00:41:11.459437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
777 00:41:11.459550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
778 00:41:11.459662 [CA 0] Center 38 (7~69) winsize 63
779 00:41:11.459801 [CA 1] Center 37 (7~68) winsize 62
780 00:41:11.459910 [CA 2] Center 36 (6~66) winsize 61
781 00:41:11.460033 [CA 3] Center 35 (5~66) winsize 62
782 00:41:11.460156 [CA 4] Center 34 (4~65) winsize 62
783 00:41:11.460264 [CA 5] Center 34 (4~65) winsize 62
784 00:41:11.460385
785 00:41:11.460508 [CmdBusTrainingLP45] Vref(ca) range 1: 32
786 00:41:11.460617
787 00:41:11.460764 [CATrainingPosCal] consider 1 rank data
788 00:41:11.460833 u2DelayCellTimex100 = 270/100 ps
789 00:41:11.460883 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
790 00:41:11.460932 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
791 00:41:11.460980 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
792 00:41:11.461028 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
793 00:41:11.461077 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
794 00:41:11.461143 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
795 00:41:11.461205
796 00:41:11.461252 CA PerBit enable=1, Macro0, CA PI delay=34
797 00:41:11.461301
798 00:41:11.461348 [CBTSetCACLKResult] CA Dly = 34
799 00:41:11.461397 CS Dly: 6 (0~37)
800 00:41:11.461445 ==
801 00:41:11.461508 Dram Type= 6, Freq= 0, CH_0, rank 1
802 00:41:11.461572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
803 00:41:11.461621 ==
804 00:41:11.461670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
805 00:41:11.461718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
806 00:41:11.461782 [CA 0] Center 38 (7~69) winsize 63
807 00:41:11.461845 [CA 1] Center 38 (7~69) winsize 63
808 00:41:11.461907 [CA 2] Center 35 (5~66) winsize 62
809 00:41:11.461968 [CA 3] Center 35 (5~66) winsize 62
810 00:41:11.462016 [CA 4] Center 34 (4~65) winsize 62
811 00:41:11.462065 [CA 5] Center 34 (4~65) winsize 62
812 00:41:11.462114
813 00:41:11.462176 [CmdBusTrainingLP45] Vref(ca) range 1: 34
814 00:41:11.462253
815 00:41:11.462316 [CATrainingPosCal] consider 2 rank data
816 00:41:11.462403 u2DelayCellTimex100 = 270/100 ps
817 00:41:11.462461 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
818 00:41:11.462510 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
819 00:41:11.462559 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
820 00:41:11.462621 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
821 00:41:11.462685 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
822 00:41:11.462733 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
823 00:41:11.462782
824 00:41:11.462830 CA PerBit enable=1, Macro0, CA PI delay=34
825 00:41:11.462892
826 00:41:11.462953 [CBTSetCACLKResult] CA Dly = 34
827 00:41:11.463002 CS Dly: 6 (0~37)
828 00:41:11.463050
829 00:41:11.463098 ----->DramcWriteLeveling(PI) begin...
830 00:41:11.463147 ==
831 00:41:11.463196 Dram Type= 6, Freq= 0, CH_0, rank 0
832 00:41:11.463258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
833 00:41:11.463321 ==
834 00:41:11.463370 Write leveling (Byte 0): 32 => 32
835 00:41:11.463419 Write leveling (Byte 1): 28 => 28
836 00:41:11.463468 DramcWriteLeveling(PI) end<-----
837 00:41:11.463531
838 00:41:11.463592 ==
839 00:41:11.463640 Dram Type= 6, Freq= 0, CH_0, rank 0
840 00:41:11.463690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 00:41:11.463739 ==
842 00:41:11.463787 [Gating] SW mode calibration
843 00:41:11.463837 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
844 00:41:11.463901 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
845 00:41:11.463963 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
846 00:41:11.464011 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 00:41:11.464060 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
848 00:41:11.464108 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
849 00:41:11.464172 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 00:41:11.464263 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 00:41:11.464312 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 00:41:11.464360 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 00:41:11.464408 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 00:41:11.464457 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:41:11.464505 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:41:11.464554 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:41:11.464602 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:41:11.464687 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:41:11.464737 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:41:11.464786 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:41:11.464834 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:41:11.464882 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:41:11.464931 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
864 00:41:11.464980 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:41:11.465029 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:41:11.465078 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 00:41:11.465127 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 00:41:11.465176 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 00:41:11.465224 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 00:41:11.465273 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 00:41:11.465321 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:41:11.465369 0 9 12 | B1->B0 | 2828 3232 | 0 1 | (0 0) (1 1)
873 00:41:11.465418 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
874 00:41:11.465467 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 00:41:11.465515 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 00:41:11.465564 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 00:41:11.465613 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 00:41:11.465662 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 00:41:11.465730 0 10 8 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 1)
880 00:41:11.465783 0 10 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
881 00:41:11.465832 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
882 00:41:11.466082 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 00:41:11.466139 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 00:41:11.466189 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 00:41:11.466239 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 00:41:11.466289 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 00:41:11.466337 0 11 8 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
888 00:41:11.466386 0 11 12 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
889 00:41:11.466435 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 00:41:11.466483 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 00:41:11.466532 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 00:41:11.466581 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 00:41:11.466629 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 00:41:11.466678 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 00:41:11.466726 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
896 00:41:11.466775 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
897 00:41:11.466824 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 00:41:11.466872 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 00:41:11.466921 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 00:41:11.466969 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 00:41:11.467017 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 00:41:11.467066 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 00:41:11.467115 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:41:11.467163 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:41:11.467212 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:41:11.467260 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:41:11.467308 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:41:11.467356 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:41:11.467404 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:41:11.467452 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:41:11.467500 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
912 00:41:11.467549 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
913 00:41:11.467597 Total UI for P1: 0, mck2ui 16
914 00:41:11.467645 best dqsien dly found for B0: ( 0, 14, 8)
915 00:41:11.467695 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
916 00:41:11.467743 Total UI for P1: 0, mck2ui 16
917 00:41:11.467791 best dqsien dly found for B1: ( 0, 14, 12)
918 00:41:11.467840 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
919 00:41:11.467889 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
920 00:41:11.467938
921 00:41:11.467987 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
922 00:41:11.468035 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
923 00:41:11.468084 [Gating] SW calibration Done
924 00:41:11.468132 ==
925 00:41:11.468180 Dram Type= 6, Freq= 0, CH_0, rank 0
926 00:41:11.468229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 00:41:11.468277 ==
928 00:41:11.468326 RX Vref Scan: 0
929 00:41:11.468375
930 00:41:11.468423 RX Vref 0 -> 0, step: 1
931 00:41:11.468471
932 00:41:11.468518 RX Delay -130 -> 252, step: 16
933 00:41:11.468567 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
934 00:41:11.468616 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
935 00:41:11.468674 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
936 00:41:11.468724 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
937 00:41:11.468772 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
938 00:41:11.468821 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
939 00:41:11.468869 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
940 00:41:11.468918 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
941 00:41:11.468984 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
942 00:41:11.469037 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
943 00:41:11.469086 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
944 00:41:11.469135 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
945 00:41:11.469183 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
946 00:41:11.469231 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
947 00:41:11.469281 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
948 00:41:11.469330 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
949 00:41:11.469379 ==
950 00:41:11.469428 Dram Type= 6, Freq= 0, CH_0, rank 0
951 00:41:11.469477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
952 00:41:11.469526 ==
953 00:41:11.469573 DQS Delay:
954 00:41:11.469622 DQS0 = 0, DQS1 = 0
955 00:41:11.469670 DQM Delay:
956 00:41:11.469719 DQM0 = 80, DQM1 = 69
957 00:41:11.469768 DQ Delay:
958 00:41:11.469816 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
959 00:41:11.469864 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
960 00:41:11.469913 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
961 00:41:11.469961 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
962 00:41:11.470009
963 00:41:11.470057
964 00:41:11.470105 ==
965 00:41:11.470153 Dram Type= 6, Freq= 0, CH_0, rank 0
966 00:41:11.470202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 00:41:11.470250 ==
968 00:41:11.470299
969 00:41:11.470347
970 00:41:11.470395 TX Vref Scan disable
971 00:41:11.470443 == TX Byte 0 ==
972 00:41:11.470491 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
973 00:41:11.470540 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
974 00:41:11.470588 == TX Byte 1 ==
975 00:41:11.470636 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
976 00:41:11.470685 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
977 00:41:11.470733 ==
978 00:41:11.470781 Dram Type= 6, Freq= 0, CH_0, rank 0
979 00:41:11.470830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 00:41:11.470878 ==
981 00:41:11.470926 TX Vref=22, minBit 5, minWin=26, winSum=434
982 00:41:11.470975 TX Vref=24, minBit 1, minWin=27, winSum=436
983 00:41:11.471023 TX Vref=26, minBit 1, minWin=27, winSum=443
984 00:41:11.471072 TX Vref=28, minBit 12, minWin=27, winSum=448
985 00:41:11.471120 TX Vref=30, minBit 1, minWin=27, winSum=446
986 00:41:11.471168 TX Vref=32, minBit 1, minWin=27, winSum=442
987 00:41:11.471216 [TxChooseVref] Worse bit 12, Min win 27, Win sum 448, Final Vref 28
988 00:41:11.471265
989 00:41:11.471313 Final TX Range 1 Vref 28
990 00:41:11.471360
991 00:41:11.471407 ==
992 00:41:11.471455 Dram Type= 6, Freq= 0, CH_0, rank 0
993 00:41:11.471696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
994 00:41:11.471812 ==
995 00:41:11.471922
996 00:41:11.472029
997 00:41:11.472136 TX Vref Scan disable
998 00:41:11.472288 == TX Byte 0 ==
999 00:41:11.472469 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1000 00:41:11.472597 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1001 00:41:11.472735 == TX Byte 1 ==
1002 00:41:11.472898 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1003 00:41:11.473039 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1004 00:41:11.473170
1005 00:41:11.473238 [DATLAT]
1006 00:41:11.473319 Freq=800, CH0 RK0
1007 00:41:11.473368
1008 00:41:11.473416 DATLAT Default: 0xa
1009 00:41:11.473466 0, 0xFFFF, sum = 0
1010 00:41:11.473515 1, 0xFFFF, sum = 0
1011 00:41:11.473565 2, 0xFFFF, sum = 0
1012 00:41:11.473629 3, 0xFFFF, sum = 0
1013 00:41:11.473695 4, 0xFFFF, sum = 0
1014 00:41:11.473744 5, 0xFFFF, sum = 0
1015 00:41:11.473792 6, 0xFFFF, sum = 0
1016 00:41:11.473841 7, 0xFFFF, sum = 0
1017 00:41:11.473891 8, 0xFFFF, sum = 0
1018 00:41:11.473940 9, 0x0, sum = 1
1019 00:41:11.474002 10, 0x0, sum = 2
1020 00:41:11.474066 11, 0x0, sum = 3
1021 00:41:11.474115 12, 0x0, sum = 4
1022 00:41:11.474166 best_step = 10
1023 00:41:11.474215
1024 00:41:11.474276 ==
1025 00:41:11.474338 Dram Type= 6, Freq= 0, CH_0, rank 0
1026 00:41:11.474386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1027 00:41:11.474435 ==
1028 00:41:11.474483 RX Vref Scan: 1
1029 00:41:11.474531
1030 00:41:11.474579 Set Vref Range= 32 -> 127
1031 00:41:11.474642
1032 00:41:11.474704 RX Vref 32 -> 127, step: 1
1033 00:41:11.474753
1034 00:41:11.474801 RX Delay -111 -> 252, step: 8
1035 00:41:11.474850
1036 00:41:11.474897 Set Vref, RX VrefLevel [Byte0]: 32
1037 00:41:11.474946 [Byte1]: 32
1038 00:41:11.475008
1039 00:41:11.475071 Set Vref, RX VrefLevel [Byte0]: 33
1040 00:41:11.475119 [Byte1]: 33
1041 00:41:11.475168
1042 00:41:11.475216 Set Vref, RX VrefLevel [Byte0]: 34
1043 00:41:11.475264 [Byte1]: 34
1044 00:41:11.475313
1045 00:41:11.475375 Set Vref, RX VrefLevel [Byte0]: 35
1046 00:41:11.475437 [Byte1]: 35
1047 00:41:11.475486
1048 00:41:11.475533 Set Vref, RX VrefLevel [Byte0]: 36
1049 00:41:11.475582 [Byte1]: 36
1050 00:41:11.475630
1051 00:41:11.475705 Set Vref, RX VrefLevel [Byte0]: 37
1052 00:41:11.475783 [Byte1]: 37
1053 00:41:11.475832
1054 00:41:11.475880 Set Vref, RX VrefLevel [Byte0]: 38
1055 00:41:11.475928 [Byte1]: 38
1056 00:41:11.475991
1057 00:41:11.476053 Set Vref, RX VrefLevel [Byte0]: 39
1058 00:41:11.476101 [Byte1]: 39
1059 00:41:11.476150
1060 00:41:11.476198 Set Vref, RX VrefLevel [Byte0]: 40
1061 00:41:11.476246 [Byte1]: 40
1062 00:41:11.476321
1063 00:41:11.476369 Set Vref, RX VrefLevel [Byte0]: 41
1064 00:41:11.476417 [Byte1]: 41
1065 00:41:11.476465
1066 00:41:11.476513 Set Vref, RX VrefLevel [Byte0]: 42
1067 00:41:11.476561 [Byte1]: 42
1068 00:41:11.476622
1069 00:41:11.476694 Set Vref, RX VrefLevel [Byte0]: 43
1070 00:41:11.476743 [Byte1]: 43
1071 00:41:11.476792
1072 00:41:11.476840 Set Vref, RX VrefLevel [Byte0]: 44
1073 00:41:11.476889 [Byte1]: 44
1074 00:41:11.476936
1075 00:41:11.476983 Set Vref, RX VrefLevel [Byte0]: 45
1076 00:41:11.477031 [Byte1]: 45
1077 00:41:11.477079
1078 00:41:11.477127 Set Vref, RX VrefLevel [Byte0]: 46
1079 00:41:11.477176 [Byte1]: 46
1080 00:41:11.477223
1081 00:41:11.477271 Set Vref, RX VrefLevel [Byte0]: 47
1082 00:41:11.477319 [Byte1]: 47
1083 00:41:11.477367
1084 00:41:11.477416 Set Vref, RX VrefLevel [Byte0]: 48
1085 00:41:11.477464 [Byte1]: 48
1086 00:41:11.477511
1087 00:41:11.477560 Set Vref, RX VrefLevel [Byte0]: 49
1088 00:41:11.477608 [Byte1]: 49
1089 00:41:11.477657
1090 00:41:11.477705 Set Vref, RX VrefLevel [Byte0]: 50
1091 00:41:11.477753 [Byte1]: 50
1092 00:41:11.477800
1093 00:41:11.477849 Set Vref, RX VrefLevel [Byte0]: 51
1094 00:41:11.477896 [Byte1]: 51
1095 00:41:11.477944
1096 00:41:11.477993 Set Vref, RX VrefLevel [Byte0]: 52
1097 00:41:11.478041 [Byte1]: 52
1098 00:41:11.478088
1099 00:41:11.478136 Set Vref, RX VrefLevel [Byte0]: 53
1100 00:41:11.478185 [Byte1]: 53
1101 00:41:11.478233
1102 00:41:11.478282 Set Vref, RX VrefLevel [Byte0]: 54
1103 00:41:11.478330 [Byte1]: 54
1104 00:41:11.478378
1105 00:41:11.478425 Set Vref, RX VrefLevel [Byte0]: 55
1106 00:41:11.478474 [Byte1]: 55
1107 00:41:11.478522
1108 00:41:11.478570 Set Vref, RX VrefLevel [Byte0]: 56
1109 00:41:11.478618 [Byte1]: 56
1110 00:41:11.478666
1111 00:41:11.478713 Set Vref, RX VrefLevel [Byte0]: 57
1112 00:41:11.478761 [Byte1]: 57
1113 00:41:11.478809
1114 00:41:11.478857 Set Vref, RX VrefLevel [Byte0]: 58
1115 00:41:11.478905 [Byte1]: 58
1116 00:41:11.478953
1117 00:41:11.479001 Set Vref, RX VrefLevel [Byte0]: 59
1118 00:41:11.479050 [Byte1]: 59
1119 00:41:11.479098
1120 00:41:11.479146 Set Vref, RX VrefLevel [Byte0]: 60
1121 00:41:11.479195 [Byte1]: 60
1122 00:41:11.479243
1123 00:41:11.479291 Set Vref, RX VrefLevel [Byte0]: 61
1124 00:41:11.479339 [Byte1]: 61
1125 00:41:11.479387
1126 00:41:11.479435 Set Vref, RX VrefLevel [Byte0]: 62
1127 00:41:11.479483 [Byte1]: 62
1128 00:41:11.479532
1129 00:41:11.479580 Set Vref, RX VrefLevel [Byte0]: 63
1130 00:41:11.479629 [Byte1]: 63
1131 00:41:11.479677
1132 00:41:11.479725 Set Vref, RX VrefLevel [Byte0]: 64
1133 00:41:11.479773 [Byte1]: 64
1134 00:41:11.479821
1135 00:41:11.479868 Set Vref, RX VrefLevel [Byte0]: 65
1136 00:41:11.479917 [Byte1]: 65
1137 00:41:11.479966
1138 00:41:11.480014 Set Vref, RX VrefLevel [Byte0]: 66
1139 00:41:11.480062 [Byte1]: 66
1140 00:41:11.480110
1141 00:41:11.480158 Set Vref, RX VrefLevel [Byte0]: 67
1142 00:41:11.480206 [Byte1]: 67
1143 00:41:11.480254
1144 00:41:11.480302 Set Vref, RX VrefLevel [Byte0]: 68
1145 00:41:11.480350 [Byte1]: 68
1146 00:41:11.480397
1147 00:41:11.480447 Set Vref, RX VrefLevel [Byte0]: 69
1148 00:41:11.480529 [Byte1]: 69
1149 00:41:11.480609
1150 00:41:11.480728 Set Vref, RX VrefLevel [Byte0]: 70
1151 00:41:11.480809 [Byte1]: 70
1152 00:41:11.480888
1153 00:41:11.480967 Set Vref, RX VrefLevel [Byte0]: 71
1154 00:41:11.481077 [Byte1]: 71
1155 00:41:11.481156
1156 00:41:11.481232 Set Vref, RX VrefLevel [Byte0]: 72
1157 00:41:11.481309 [Byte1]: 72
1158 00:41:11.481385
1159 00:41:11.481460 Set Vref, RX VrefLevel [Byte0]: 73
1160 00:41:11.481536 [Byte1]: 73
1161 00:41:11.481612
1162 00:41:11.481687 Set Vref, RX VrefLevel [Byte0]: 74
1163 00:41:11.481764 [Byte1]: 74
1164 00:41:11.481839
1165 00:41:11.482107 Set Vref, RX VrefLevel [Byte0]: 75
1166 00:41:11.482189 [Byte1]: 75
1167 00:41:11.482266
1168 00:41:11.482341 Set Vref, RX VrefLevel [Byte0]: 76
1169 00:41:11.482418 [Byte1]: 76
1170 00:41:11.482494
1171 00:41:11.482571 Set Vref, RX VrefLevel [Byte0]: 77
1172 00:41:11.482647 [Byte1]: 77
1173 00:41:11.482723
1174 00:41:11.482799 Final RX Vref Byte 0 = 61 to rank0
1175 00:41:11.482876 Final RX Vref Byte 1 = 56 to rank0
1176 00:41:11.482953 Final RX Vref Byte 0 = 61 to rank1
1177 00:41:11.483029 Final RX Vref Byte 1 = 56 to rank1==
1178 00:41:11.483106 Dram Type= 6, Freq= 0, CH_0, rank 0
1179 00:41:11.483183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1180 00:41:11.483259 ==
1181 00:41:11.483335 DQS Delay:
1182 00:41:11.483410 DQS0 = 0, DQS1 = 0
1183 00:41:11.483485 DQM Delay:
1184 00:41:11.483561 DQM0 = 81, DQM1 = 68
1185 00:41:11.483637 DQ Delay:
1186 00:41:11.483713 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1187 00:41:11.483789 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1188 00:41:11.483866 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1189 00:41:11.483942 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =76
1190 00:41:11.484018
1191 00:41:11.484093
1192 00:41:11.484170 [DQSOSCAuto] RK0, (LSB)MR18= 0x3130, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1193 00:41:11.484247 CH0 RK0: MR19=606, MR18=3130
1194 00:41:11.484324 CH0_RK0: MR19=0x606, MR18=0x3130, DQSOSC=397, MR23=63, INC=93, DEC=62
1195 00:41:11.484400
1196 00:41:11.484476 ----->DramcWriteLeveling(PI) begin...
1197 00:41:11.484552 ==
1198 00:41:11.484629 Dram Type= 6, Freq= 0, CH_0, rank 1
1199 00:41:11.484751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1200 00:41:11.484828 ==
1201 00:41:11.484904 Write leveling (Byte 0): 31 => 31
1202 00:41:11.484981 Write leveling (Byte 1): 30 => 30
1203 00:41:11.485057 DramcWriteLeveling(PI) end<-----
1204 00:41:11.485132
1205 00:41:11.485208 ==
1206 00:41:11.485284 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 00:41:11.485360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1208 00:41:11.485436 ==
1209 00:41:11.485512 [Gating] SW mode calibration
1210 00:41:11.485590 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1211 00:41:11.485682 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1212 00:41:11.485773 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1213 00:41:11.485850 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1214 00:41:11.485927 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1215 00:41:11.486004 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 00:41:11.486081 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 00:41:11.486157 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 00:41:11.486234 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 00:41:11.486311 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 00:41:11.486388 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 00:41:11.486464 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 00:41:11.486541 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 00:41:11.486618 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 00:41:11.486695 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 00:41:11.486771 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 00:41:11.486847 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 00:41:11.486924 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 00:41:11.487001 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 00:41:11.487077 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1230 00:41:11.487154 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1231 00:41:11.487230 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 00:41:11.487307 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:41:11.487383 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:41:11.487460 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:41:11.487537 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:41:11.487613 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:41:11.487689 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 00:41:11.487766 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
1239 00:41:11.487843 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1240 00:41:11.487919 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 00:41:11.487996 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 00:41:11.488073 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 00:41:11.488149 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 00:41:11.488226 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 00:41:11.488303 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
1246 00:41:11.488379 0 10 8 | B1->B0 | 3030 2626 | 1 0 | (1 0) (1 0)
1247 00:41:11.488456 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 00:41:11.488532 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 00:41:11.488609 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 00:41:11.488713 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 00:41:11.488764 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 00:41:11.488814 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 00:41:11.488863 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1254 00:41:11.488912 0 11 8 | B1->B0 | 3232 4141 | 0 0 | (0 0) (0 0)
1255 00:41:11.488961 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 00:41:11.489009 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 00:41:11.489058 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 00:41:11.489107 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 00:41:11.489155 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 00:41:11.489203 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 00:41:11.489252 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1262 00:41:11.489331 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1263 00:41:11.489380 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1264 00:41:11.489429 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 00:41:11.489687 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 00:41:11.489881 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 00:41:11.489990 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 00:41:11.490099 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 00:41:11.490210 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 00:41:11.490322 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 00:41:11.490433 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 00:41:11.490544 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 00:41:11.490652 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 00:41:11.490761 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 00:41:11.490870 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 00:41:11.490979 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 00:41:11.491059 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1278 00:41:11.491111 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1279 00:41:11.491160 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 00:41:11.491208 Total UI for P1: 0, mck2ui 16
1281 00:41:11.491257 best dqsien dly found for B0: ( 0, 14, 6)
1282 00:41:11.491306 Total UI for P1: 0, mck2ui 16
1283 00:41:11.491356 best dqsien dly found for B1: ( 0, 14, 10)
1284 00:41:11.491405 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1285 00:41:11.491454 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1286 00:41:11.491502
1287 00:41:11.491551 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1288 00:41:11.491599 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1289 00:41:11.491648 [Gating] SW calibration Done
1290 00:41:11.491696 ==
1291 00:41:11.491745 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 00:41:11.491794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 00:41:11.491844 ==
1294 00:41:11.491892 RX Vref Scan: 0
1295 00:41:11.491939
1296 00:41:11.491988 RX Vref 0 -> 0, step: 1
1297 00:41:11.492037
1298 00:41:11.492085 RX Delay -130 -> 252, step: 16
1299 00:41:11.492133 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1300 00:41:11.492182 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1301 00:41:11.492230 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1302 00:41:11.492278 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1303 00:41:11.492327 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1304 00:41:11.492375 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1305 00:41:11.492454 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1306 00:41:11.492503 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1307 00:41:11.492551 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1308 00:41:11.492600 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1309 00:41:11.492655 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1310 00:41:11.492734 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1311 00:41:11.492783 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1312 00:41:11.492831 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1313 00:41:11.492879 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1314 00:41:11.492928 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1315 00:41:11.492976 ==
1316 00:41:11.493024 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 00:41:11.493072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 00:41:11.493120 ==
1319 00:41:11.493169 DQS Delay:
1320 00:41:11.493217 DQS0 = 0, DQS1 = 0
1321 00:41:11.493265 DQM Delay:
1322 00:41:11.493313 DQM0 = 77, DQM1 = 72
1323 00:41:11.493361 DQ Delay:
1324 00:41:11.493430 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1325 00:41:11.493481 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
1326 00:41:11.493530 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
1327 00:41:11.493578 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1328 00:41:11.493626
1329 00:41:11.493674
1330 00:41:11.493795 ==
1331 00:41:11.493845 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 00:41:11.493894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 00:41:11.493944 ==
1334 00:41:11.493991
1335 00:41:11.494039
1336 00:41:11.494086 TX Vref Scan disable
1337 00:41:11.494135 == TX Byte 0 ==
1338 00:41:11.494183 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1339 00:41:11.494233 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1340 00:41:11.494282 == TX Byte 1 ==
1341 00:41:11.494331 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1342 00:41:11.494392 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1343 00:41:11.494445 ==
1344 00:41:11.494493 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 00:41:11.494542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 00:41:11.494591 ==
1347 00:41:11.494640 TX Vref=22, minBit 1, minWin=27, winSum=438
1348 00:41:11.494690 TX Vref=24, minBit 1, minWin=27, winSum=437
1349 00:41:11.494738 TX Vref=26, minBit 1, minWin=27, winSum=442
1350 00:41:11.494786 TX Vref=28, minBit 1, minWin=27, winSum=443
1351 00:41:11.494835 TX Vref=30, minBit 1, minWin=27, winSum=444
1352 00:41:11.494884 TX Vref=32, minBit 1, minWin=27, winSum=445
1353 00:41:11.494933 [TxChooseVref] Worse bit 1, Min win 27, Win sum 445, Final Vref 32
1354 00:41:11.494982
1355 00:41:11.495030 Final TX Range 1 Vref 32
1356 00:41:11.495079
1357 00:41:11.495127 ==
1358 00:41:11.495175 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 00:41:11.495225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 00:41:11.495274 ==
1361 00:41:11.495322
1362 00:41:11.495369
1363 00:41:11.495416 TX Vref Scan disable
1364 00:41:11.495463 == TX Byte 0 ==
1365 00:41:11.495510 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1366 00:41:11.495558 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1367 00:41:11.495606 == TX Byte 1 ==
1368 00:41:11.495653 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1369 00:41:11.495701 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1370 00:41:11.495749
1371 00:41:11.495795 [DATLAT]
1372 00:41:11.495842 Freq=800, CH0 RK1
1373 00:41:11.495890
1374 00:41:11.495937 DATLAT Default: 0xa
1375 00:41:11.495984 0, 0xFFFF, sum = 0
1376 00:41:11.496034 1, 0xFFFF, sum = 0
1377 00:41:11.496082 2, 0xFFFF, sum = 0
1378 00:41:11.496130 3, 0xFFFF, sum = 0
1379 00:41:11.496178 4, 0xFFFF, sum = 0
1380 00:41:11.496225 5, 0xFFFF, sum = 0
1381 00:41:11.496273 6, 0xFFFF, sum = 0
1382 00:41:11.496321 7, 0xFFFF, sum = 0
1383 00:41:11.496368 8, 0xFFFF, sum = 0
1384 00:41:11.496417 9, 0x0, sum = 1
1385 00:41:11.496465 10, 0x0, sum = 2
1386 00:41:11.496513 11, 0x0, sum = 3
1387 00:41:11.496562 12, 0x0, sum = 4
1388 00:41:11.496610 best_step = 10
1389 00:41:11.496679
1390 00:41:11.496742 ==
1391 00:41:11.496790 Dram Type= 6, Freq= 0, CH_0, rank 1
1392 00:41:11.496838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 00:41:11.496886 ==
1394 00:41:11.496933 RX Vref Scan: 0
1395 00:41:11.496981
1396 00:41:11.497028 RX Vref 0 -> 0, step: 1
1397 00:41:11.497075
1398 00:41:11.497122 RX Delay -111 -> 252, step: 8
1399 00:41:11.497170 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1400 00:41:11.497408 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1401 00:41:11.497466 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1402 00:41:11.497516 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1403 00:41:11.497565 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1404 00:41:11.497613 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1405 00:41:11.497662 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1406 00:41:11.497710 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1407 00:41:11.497758 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1408 00:41:11.497806 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1409 00:41:11.497855 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1410 00:41:11.497903 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1411 00:41:11.497951 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1412 00:41:11.497999 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1413 00:41:11.498046 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1414 00:41:11.498094 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1415 00:41:11.498141 ==
1416 00:41:11.498189 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 00:41:11.498238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 00:41:11.498286 ==
1419 00:41:11.498334 DQS Delay:
1420 00:41:11.498383 DQS0 = 0, DQS1 = 0
1421 00:41:11.498431 DQM Delay:
1422 00:41:11.498479 DQM0 = 78, DQM1 = 69
1423 00:41:11.498528 DQ Delay:
1424 00:41:11.498576 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1425 00:41:11.498624 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =88
1426 00:41:11.498672 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1427 00:41:11.498720 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1428 00:41:11.498783
1429 00:41:11.498871
1430 00:41:11.498924 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
1431 00:41:11.498974 CH0 RK1: MR19=606, MR18=4F2A
1432 00:41:11.499052 CH0_RK1: MR19=0x606, MR18=0x4F2A, DQSOSC=390, MR23=63, INC=97, DEC=64
1433 00:41:11.499101 [RxdqsGatingPostProcess] freq 800
1434 00:41:11.499149 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1435 00:41:11.499196 Pre-setting of DQS Precalculation
1436 00:41:11.499244 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1437 00:41:11.499293 ==
1438 00:41:11.499341 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 00:41:11.499389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 00:41:11.499437 ==
1441 00:41:11.499485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1442 00:41:11.499534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1443 00:41:11.499584 [CA 0] Center 36 (6~66) winsize 61
1444 00:41:11.499632 [CA 1] Center 36 (6~67) winsize 62
1445 00:41:11.499681 [CA 2] Center 34 (5~64) winsize 60
1446 00:41:11.499729 [CA 3] Center 34 (4~64) winsize 61
1447 00:41:11.499776 [CA 4] Center 34 (4~64) winsize 61
1448 00:41:11.499823 [CA 5] Center 34 (4~64) winsize 61
1449 00:41:11.499870
1450 00:41:11.499917 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1451 00:41:11.499992
1452 00:41:11.500070 [CATrainingPosCal] consider 1 rank data
1453 00:41:11.500122 u2DelayCellTimex100 = 270/100 ps
1454 00:41:11.500170 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1455 00:41:11.500219 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1456 00:41:11.500267 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1457 00:41:11.500316 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1458 00:41:11.500364 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1459 00:41:11.500412 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1460 00:41:11.500460
1461 00:41:11.500508 CA PerBit enable=1, Macro0, CA PI delay=34
1462 00:41:11.500579
1463 00:41:11.500627 [CBTSetCACLKResult] CA Dly = 34
1464 00:41:11.500699 CS Dly: 5 (0~36)
1465 00:41:11.500748 ==
1466 00:41:11.500796 Dram Type= 6, Freq= 0, CH_1, rank 1
1467 00:41:11.500845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1468 00:41:11.500908 ==
1469 00:41:11.500970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1470 00:41:11.501018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1471 00:41:11.501068 [CA 0] Center 36 (6~66) winsize 61
1472 00:41:11.501116 [CA 1] Center 36 (6~67) winsize 62
1473 00:41:11.501163 [CA 2] Center 34 (4~65) winsize 62
1474 00:41:11.501212 [CA 3] Center 34 (4~64) winsize 61
1475 00:41:11.501260 [CA 4] Center 34 (4~65) winsize 62
1476 00:41:11.501308 [CA 5] Center 34 (4~64) winsize 61
1477 00:41:11.501355
1478 00:41:11.501421 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1479 00:41:11.501505
1480 00:41:11.501557 [CATrainingPosCal] consider 2 rank data
1481 00:41:11.501606 u2DelayCellTimex100 = 270/100 ps
1482 00:41:11.501657 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1483 00:41:11.501705 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1484 00:41:11.501775 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1485 00:41:11.501857 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1486 00:41:11.501937 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1487 00:41:11.502027 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1488 00:41:11.502160
1489 00:41:11.502219 CA PerBit enable=1, Macro0, CA PI delay=34
1490 00:41:11.502268
1491 00:41:11.502316 [CBTSetCACLKResult] CA Dly = 34
1492 00:41:11.502364 CS Dly: 5 (0~37)
1493 00:41:11.502413
1494 00:41:11.502461 ----->DramcWriteLeveling(PI) begin...
1495 00:41:11.502510 ==
1496 00:41:11.502558 Dram Type= 6, Freq= 0, CH_1, rank 0
1497 00:41:11.502606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1498 00:41:11.502655 ==
1499 00:41:11.502702 Write leveling (Byte 0): 27 => 27
1500 00:41:11.502750 Write leveling (Byte 1): 27 => 27
1501 00:41:11.502814 DramcWriteLeveling(PI) end<-----
1502 00:41:11.502893
1503 00:41:11.502972 ==
1504 00:41:11.503052 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 00:41:11.503132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 00:41:11.503211 ==
1507 00:41:11.503292 [Gating] SW mode calibration
1508 00:41:11.503370 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1509 00:41:11.503447 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1510 00:41:11.503524 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1511 00:41:11.503600 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1512 00:41:11.503677 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1513 00:41:11.503753 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 00:41:11.503829 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 00:41:11.503905 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 00:41:11.503982 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 00:41:11.504254 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 00:41:11.504368 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 00:41:11.504479 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 00:41:11.504590 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 00:41:11.504723 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 00:41:11.504840 0 7 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1523 00:41:11.504953 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 00:41:11.505063 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 00:41:11.505173 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 00:41:11.505282 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 00:41:11.505391 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1528 00:41:11.505487 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1529 00:41:11.505565 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:41:11.505641 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 00:41:11.505718 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 00:41:11.505794 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 00:41:11.505870 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:41:11.505946 0 9 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1535 00:41:11.506022 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 00:41:11.506098 0 9 8 | B1->B0 | 2a2a 2c2c | 1 1 | (1 1) (0 0)
1537 00:41:11.506175 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 00:41:11.506251 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 00:41:11.506327 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 00:41:11.506404 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 00:41:11.506480 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 00:41:11.506556 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 00:41:11.506633 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 0)
1544 00:41:11.506709 0 10 8 | B1->B0 | 2e2e 2a2a | 0 0 | (0 1) (0 0)
1545 00:41:11.506785 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 00:41:11.506861 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 00:41:11.506936 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 00:41:11.507012 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 00:41:11.507089 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 00:41:11.507165 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 00:41:11.507241 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1552 00:41:11.507317 0 11 8 | B1->B0 | 3a3a 3838 | 1 0 | (0 0) (0 0)
1553 00:41:11.507394 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 00:41:11.507470 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 00:41:11.507546 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 00:41:11.507623 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 00:41:11.507699 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 00:41:11.507775 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 00:41:11.507851 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 00:41:11.507927 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1561 00:41:11.508003 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1562 00:41:11.508079 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 00:41:11.508155 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 00:41:11.508231 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 00:41:11.508307 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 00:41:11.508383 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 00:41:11.508459 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 00:41:11.508535 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 00:41:11.508611 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 00:41:11.508711 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 00:41:11.508761 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 00:41:11.508809 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 00:41:11.508858 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 00:41:11.508906 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 00:41:11.508954 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 00:41:11.509001 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 00:41:11.509049 Total UI for P1: 0, mck2ui 16
1578 00:41:11.509097 best dqsien dly found for B0: ( 0, 14, 6)
1579 00:41:11.509145 Total UI for P1: 0, mck2ui 16
1580 00:41:11.509194 best dqsien dly found for B1: ( 0, 14, 6)
1581 00:41:11.509242 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1582 00:41:11.509290 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1583 00:41:11.509337
1584 00:41:11.509385 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1585 00:41:11.509433 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1586 00:41:11.509480 [Gating] SW calibration Done
1587 00:41:11.509544 ==
1588 00:41:11.509595 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 00:41:11.509644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 00:41:11.509692 ==
1591 00:41:11.509741 RX Vref Scan: 0
1592 00:41:11.509789
1593 00:41:11.509837 RX Vref 0 -> 0, step: 1
1594 00:41:11.509884
1595 00:41:11.509932 RX Delay -130 -> 252, step: 16
1596 00:41:11.509980 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1597 00:41:11.510029 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1598 00:41:11.510077 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1599 00:41:11.510125 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1600 00:41:11.510174 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1601 00:41:11.510221 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1602 00:41:11.510269 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1603 00:41:11.510316 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1604 00:41:11.510364 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1605 00:41:11.510412 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1606 00:41:11.510459 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1607 00:41:11.510698 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1608 00:41:11.510754 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1609 00:41:11.510803 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1610 00:41:11.510852 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1611 00:41:11.510901 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1612 00:41:11.510948 ==
1613 00:41:11.510997 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 00:41:11.511045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 00:41:11.511094 ==
1616 00:41:11.511141 DQS Delay:
1617 00:41:11.511189 DQS0 = 0, DQS1 = 0
1618 00:41:11.511237 DQM Delay:
1619 00:41:11.511284 DQM0 = 82, DQM1 = 74
1620 00:41:11.511332 DQ Delay:
1621 00:41:11.511379 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1622 00:41:11.511427 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1623 00:41:11.511476 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1624 00:41:11.511524 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1625 00:41:11.511572
1626 00:41:11.511619
1627 00:41:11.511666 ==
1628 00:41:11.511714 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 00:41:11.511763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 00:41:11.511811 ==
1631 00:41:11.511858
1632 00:41:11.511905
1633 00:41:11.511954 TX Vref Scan disable
1634 00:41:11.512002 == TX Byte 0 ==
1635 00:41:11.512049 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1636 00:41:11.512098 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1637 00:41:11.512146 == TX Byte 1 ==
1638 00:41:11.512193 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1639 00:41:11.512241 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1640 00:41:11.512288 ==
1641 00:41:11.512336 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 00:41:11.512383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 00:41:11.512432 ==
1644 00:41:11.512480 TX Vref=22, minBit 1, minWin=27, winSum=442
1645 00:41:11.512528 TX Vref=24, minBit 0, minWin=27, winSum=442
1646 00:41:11.512576 TX Vref=26, minBit 1, minWin=27, winSum=446
1647 00:41:11.512625 TX Vref=28, minBit 1, minWin=27, winSum=449
1648 00:41:11.512712 TX Vref=30, minBit 5, minWin=27, winSum=450
1649 00:41:11.512761 TX Vref=32, minBit 6, minWin=27, winSum=447
1650 00:41:11.512810 [TxChooseVref] Worse bit 5, Min win 27, Win sum 450, Final Vref 30
1651 00:41:11.512859
1652 00:41:11.512907 Final TX Range 1 Vref 30
1653 00:41:11.512954
1654 00:41:11.513002 ==
1655 00:41:11.513049 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 00:41:11.513098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 00:41:11.513146 ==
1658 00:41:11.513193
1659 00:41:11.513239
1660 00:41:11.513285 TX Vref Scan disable
1661 00:41:11.513333 == TX Byte 0 ==
1662 00:41:11.513381 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1663 00:41:11.513429 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1664 00:41:11.513476 == TX Byte 1 ==
1665 00:41:11.513523 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1666 00:41:11.513570 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1667 00:41:11.513618
1668 00:41:11.513664 [DATLAT]
1669 00:41:11.513713 Freq=800, CH1 RK0
1670 00:41:11.513761
1671 00:41:11.513808 DATLAT Default: 0xa
1672 00:41:11.513856 0, 0xFFFF, sum = 0
1673 00:41:11.513906 1, 0xFFFF, sum = 0
1674 00:41:11.513955 2, 0xFFFF, sum = 0
1675 00:41:11.514004 3, 0xFFFF, sum = 0
1676 00:41:11.514052 4, 0xFFFF, sum = 0
1677 00:41:11.514100 5, 0xFFFF, sum = 0
1678 00:41:11.514148 6, 0xFFFF, sum = 0
1679 00:41:11.514197 7, 0xFFFF, sum = 0
1680 00:41:11.514245 8, 0xFFFF, sum = 0
1681 00:41:11.514293 9, 0x0, sum = 1
1682 00:41:11.514341 10, 0x0, sum = 2
1683 00:41:11.514390 11, 0x0, sum = 3
1684 00:41:11.514438 12, 0x0, sum = 4
1685 00:41:11.514486 best_step = 10
1686 00:41:11.514533
1687 00:41:11.514581 ==
1688 00:41:11.514629 Dram Type= 6, Freq= 0, CH_1, rank 0
1689 00:41:11.514678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1690 00:41:11.514726 ==
1691 00:41:11.514774 RX Vref Scan: 1
1692 00:41:11.514821
1693 00:41:11.514868 Set Vref Range= 32 -> 127
1694 00:41:11.514915
1695 00:41:11.514962 RX Vref 32 -> 127, step: 1
1696 00:41:11.515009
1697 00:41:11.515056 RX Delay -111 -> 252, step: 8
1698 00:41:11.515104
1699 00:41:11.515151 Set Vref, RX VrefLevel [Byte0]: 32
1700 00:41:11.515199 [Byte1]: 32
1701 00:41:11.515247
1702 00:41:11.515295 Set Vref, RX VrefLevel [Byte0]: 33
1703 00:41:11.515344 [Byte1]: 33
1704 00:41:11.515391
1705 00:41:11.515438 Set Vref, RX VrefLevel [Byte0]: 34
1706 00:41:11.515486 [Byte1]: 34
1707 00:41:11.515533
1708 00:41:11.515581 Set Vref, RX VrefLevel [Byte0]: 35
1709 00:41:11.515629 [Byte1]: 35
1710 00:41:11.515676
1711 00:41:11.515724 Set Vref, RX VrefLevel [Byte0]: 36
1712 00:41:11.515772 [Byte1]: 36
1713 00:41:11.515820
1714 00:41:11.515867 Set Vref, RX VrefLevel [Byte0]: 37
1715 00:41:11.515915 [Byte1]: 37
1716 00:41:11.515962
1717 00:41:11.516009 Set Vref, RX VrefLevel [Byte0]: 38
1718 00:41:11.516057 [Byte1]: 38
1719 00:41:11.516105
1720 00:41:11.516152 Set Vref, RX VrefLevel [Byte0]: 39
1721 00:41:11.516200 [Byte1]: 39
1722 00:41:11.516247
1723 00:41:11.516294 Set Vref, RX VrefLevel [Byte0]: 40
1724 00:41:11.516342 [Byte1]: 40
1725 00:41:11.516389
1726 00:41:11.516436 Set Vref, RX VrefLevel [Byte0]: 41
1727 00:41:11.516484 [Byte1]: 41
1728 00:41:11.516531
1729 00:41:11.516578 Set Vref, RX VrefLevel [Byte0]: 42
1730 00:41:11.516626 [Byte1]: 42
1731 00:41:11.516682
1732 00:41:11.516730 Set Vref, RX VrefLevel [Byte0]: 43
1733 00:41:11.516778 [Byte1]: 43
1734 00:41:11.516824
1735 00:41:11.516871 Set Vref, RX VrefLevel [Byte0]: 44
1736 00:41:11.516919 [Byte1]: 44
1737 00:41:11.516967
1738 00:41:11.517014 Set Vref, RX VrefLevel [Byte0]: 45
1739 00:41:11.517062 [Byte1]: 45
1740 00:41:11.517110
1741 00:41:11.517157 Set Vref, RX VrefLevel [Byte0]: 46
1742 00:41:11.517205 [Byte1]: 46
1743 00:41:11.517252
1744 00:41:11.517299 Set Vref, RX VrefLevel [Byte0]: 47
1745 00:41:11.517347 [Byte1]: 47
1746 00:41:11.517394
1747 00:41:11.517441 Set Vref, RX VrefLevel [Byte0]: 48
1748 00:41:11.517489 [Byte1]: 48
1749 00:41:11.517536
1750 00:41:11.517583 Set Vref, RX VrefLevel [Byte0]: 49
1751 00:41:11.517630 [Byte1]: 49
1752 00:41:11.517678
1753 00:41:11.517725 Set Vref, RX VrefLevel [Byte0]: 50
1754 00:41:11.517773 [Byte1]: 50
1755 00:41:11.517820
1756 00:41:11.517867 Set Vref, RX VrefLevel [Byte0]: 51
1757 00:41:11.517916 [Byte1]: 51
1758 00:41:11.517964
1759 00:41:11.518012 Set Vref, RX VrefLevel [Byte0]: 52
1760 00:41:11.518060 [Byte1]: 52
1761 00:41:11.518107
1762 00:41:11.518154 Set Vref, RX VrefLevel [Byte0]: 53
1763 00:41:11.518202 [Byte1]: 53
1764 00:41:11.518249
1765 00:41:11.518296 Set Vref, RX VrefLevel [Byte0]: 54
1766 00:41:11.518344 [Byte1]: 54
1767 00:41:11.518392
1768 00:41:11.518440 Set Vref, RX VrefLevel [Byte0]: 55
1769 00:41:11.518487 [Byte1]: 55
1770 00:41:11.518534
1771 00:41:11.518581 Set Vref, RX VrefLevel [Byte0]: 56
1772 00:41:11.518821 [Byte1]: 56
1773 00:41:11.518935
1774 00:41:11.519044 Set Vref, RX VrefLevel [Byte0]: 57
1775 00:41:11.519152 [Byte1]: 57
1776 00:41:11.519260
1777 00:41:11.519368 Set Vref, RX VrefLevel [Byte0]: 58
1778 00:41:11.519477 [Byte1]: 58
1779 00:41:11.519584
1780 00:41:11.519693 Set Vref, RX VrefLevel [Byte0]: 59
1781 00:41:11.519801 [Byte1]: 59
1782 00:41:11.519908
1783 00:41:11.520016 Set Vref, RX VrefLevel [Byte0]: 60
1784 00:41:11.520108 [Byte1]: 60
1785 00:41:11.520159
1786 00:41:11.520208 Set Vref, RX VrefLevel [Byte0]: 61
1787 00:41:11.520257 [Byte1]: 61
1788 00:41:11.520306
1789 00:41:11.520354 Set Vref, RX VrefLevel [Byte0]: 62
1790 00:41:11.520402 [Byte1]: 62
1791 00:41:11.520450
1792 00:41:11.520497 Set Vref, RX VrefLevel [Byte0]: 63
1793 00:41:11.520546 [Byte1]: 63
1794 00:41:11.520593
1795 00:41:11.520641 Set Vref, RX VrefLevel [Byte0]: 64
1796 00:41:11.520732 [Byte1]: 64
1797 00:41:11.520779
1798 00:41:11.520826 Set Vref, RX VrefLevel [Byte0]: 65
1799 00:41:11.520875 [Byte1]: 65
1800 00:41:11.520923
1801 00:41:11.520970 Set Vref, RX VrefLevel [Byte0]: 66
1802 00:41:11.521018 [Byte1]: 66
1803 00:41:11.521066
1804 00:41:11.521113 Set Vref, RX VrefLevel [Byte0]: 67
1805 00:41:11.521161 [Byte1]: 67
1806 00:41:11.521208
1807 00:41:11.521255 Set Vref, RX VrefLevel [Byte0]: 68
1808 00:41:11.521302 [Byte1]: 68
1809 00:41:11.521350
1810 00:41:11.521397 Set Vref, RX VrefLevel [Byte0]: 69
1811 00:41:11.521445 [Byte1]: 69
1812 00:41:11.521492
1813 00:41:11.521539 Set Vref, RX VrefLevel [Byte0]: 70
1814 00:41:11.521586 [Byte1]: 70
1815 00:41:11.521633
1816 00:41:11.521680 Set Vref, RX VrefLevel [Byte0]: 71
1817 00:41:11.521727 [Byte1]: 71
1818 00:41:11.521774
1819 00:41:11.521821 Set Vref, RX VrefLevel [Byte0]: 72
1820 00:41:11.521868 [Byte1]: 72
1821 00:41:11.521916
1822 00:41:11.521963 Set Vref, RX VrefLevel [Byte0]: 73
1823 00:41:11.522011 [Byte1]: 73
1824 00:41:11.522058
1825 00:41:11.522105 Final RX Vref Byte 0 = 62 to rank0
1826 00:41:11.522153 Final RX Vref Byte 1 = 57 to rank0
1827 00:41:11.522200 Final RX Vref Byte 0 = 62 to rank1
1828 00:41:11.522248 Final RX Vref Byte 1 = 57 to rank1==
1829 00:41:11.522296 Dram Type= 6, Freq= 0, CH_1, rank 0
1830 00:41:11.522344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 00:41:11.522392 ==
1832 00:41:11.522439 DQS Delay:
1833 00:41:11.522487 DQS0 = 0, DQS1 = 0
1834 00:41:11.522534 DQM Delay:
1835 00:41:11.522582 DQM0 = 80, DQM1 = 71
1836 00:41:11.522629 DQ Delay:
1837 00:41:11.522676 DQ0 =88, DQ1 =72, DQ2 =68, DQ3 =76
1838 00:41:11.522724 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1839 00:41:11.522772 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1840 00:41:11.522819 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1841 00:41:11.522867
1842 00:41:11.522915
1843 00:41:11.522963 [DQSOSCAuto] RK0, (LSB)MR18= 0x151e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1844 00:41:11.523012 CH1 RK0: MR19=606, MR18=151E
1845 00:41:11.523061 CH1_RK0: MR19=0x606, MR18=0x151E, DQSOSC=402, MR23=63, INC=91, DEC=60
1846 00:41:11.523108
1847 00:41:11.523156 ----->DramcWriteLeveling(PI) begin...
1848 00:41:11.523205 ==
1849 00:41:11.523252 Dram Type= 6, Freq= 0, CH_1, rank 1
1850 00:41:11.523300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1851 00:41:11.523348 ==
1852 00:41:11.523396 Write leveling (Byte 0): 29 => 29
1853 00:41:11.523443 Write leveling (Byte 1): 29 => 29
1854 00:41:11.523491 DramcWriteLeveling(PI) end<-----
1855 00:41:11.523538
1856 00:41:11.523585 ==
1857 00:41:11.523633 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 00:41:11.523680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 00:41:11.523728 ==
1860 00:41:11.523776 [Gating] SW mode calibration
1861 00:41:11.523823 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1862 00:41:11.523871 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1863 00:41:11.523920 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1864 00:41:11.523968 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1865 00:41:11.524016 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1866 00:41:11.524064 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 00:41:11.524112 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 00:41:11.524160 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 00:41:11.524207 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 00:41:11.524254 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 00:41:11.524302 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 00:41:11.524350 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 00:41:11.524397 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 00:41:11.524445 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 00:41:11.524493 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 00:41:11.524540 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 00:41:11.524588 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 00:41:11.524637 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 00:41:11.524722 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 00:41:11.524771 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1881 00:41:11.524818 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1882 00:41:11.524866 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 00:41:11.524914 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 00:41:11.524962 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 00:41:11.525010 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 00:41:11.525058 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 00:41:11.525105 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:41:11.525153 0 9 4 | B1->B0 | 2323 3231 | 0 1 | (0 0) (1 1)
1889 00:41:11.525201 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1890 00:41:11.525248 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 00:41:11.525296 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 00:41:11.525344 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 00:41:11.525392 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 00:41:11.525632 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 00:41:11.525687 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1896 00:41:11.525736 0 10 4 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (1 0)
1897 00:41:11.525784 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1898 00:41:11.525833 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 00:41:11.525881 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 00:41:11.525929 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:41:11.525977 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:41:11.526025 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:41:11.526073 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1904 00:41:11.526121 0 11 4 | B1->B0 | 2828 3a3a | 0 0 | (0 0) (0 0)
1905 00:41:11.526169 0 11 8 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
1906 00:41:11.526217 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 00:41:11.526265 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 00:41:11.526314 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 00:41:11.526362 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 00:41:11.526409 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 00:41:11.526458 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 00:41:11.526506 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1913 00:41:11.526554 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 00:41:11.526602 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 00:41:11.526649 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 00:41:11.526698 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 00:41:11.526745 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 00:41:11.526793 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 00:41:11.526841 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 00:41:11.526889 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 00:41:11.526936 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 00:41:11.526984 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 00:41:11.527032 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 00:41:11.527080 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 00:41:11.527128 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 00:41:11.527176 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 00:41:11.527224 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 00:41:11.527273 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1929 00:41:11.527320 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1930 00:41:11.527368 Total UI for P1: 0, mck2ui 16
1931 00:41:11.527417 best dqsien dly found for B0: ( 0, 14, 4)
1932 00:41:11.527465 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 00:41:11.527513 Total UI for P1: 0, mck2ui 16
1934 00:41:11.527560 best dqsien dly found for B1: ( 0, 14, 6)
1935 00:41:11.527608 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1936 00:41:11.527656 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1937 00:41:11.527704
1938 00:41:11.527751 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1939 00:41:11.527815 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1940 00:41:11.527864 [Gating] SW calibration Done
1941 00:41:11.527913 ==
1942 00:41:11.527962 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 00:41:11.528010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 00:41:11.528058 ==
1945 00:41:11.528107 RX Vref Scan: 0
1946 00:41:11.528155
1947 00:41:11.528203 RX Vref 0 -> 0, step: 1
1948 00:41:11.528251
1949 00:41:11.528299 RX Delay -130 -> 252, step: 16
1950 00:41:11.528347 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1951 00:41:11.528395 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1952 00:41:11.528443 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1953 00:41:11.528491 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1954 00:41:11.528539 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1955 00:41:11.528587 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1956 00:41:11.528634 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1957 00:41:11.528723 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1958 00:41:11.528771 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1959 00:41:11.528819 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1960 00:41:11.528867 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1961 00:41:11.528915 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1962 00:41:11.528963 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1963 00:41:11.529010 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1964 00:41:11.529058 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1965 00:41:11.529105 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1966 00:41:11.529153 ==
1967 00:41:11.529200 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 00:41:11.529248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 00:41:11.529297 ==
1970 00:41:11.529345 DQS Delay:
1971 00:41:11.529393 DQS0 = 0, DQS1 = 0
1972 00:41:11.529441 DQM Delay:
1973 00:41:11.529489 DQM0 = 77, DQM1 = 73
1974 00:41:11.529536 DQ Delay:
1975 00:41:11.529583 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1976 00:41:11.529631 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1977 00:41:11.529680 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1978 00:41:11.529728 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1979 00:41:11.529776
1980 00:41:11.529823
1981 00:41:11.529870 ==
1982 00:41:11.529917 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 00:41:11.529966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 00:41:11.530014 ==
1985 00:41:11.530062
1986 00:41:11.530108
1987 00:41:11.530156 TX Vref Scan disable
1988 00:41:11.754629 == TX Byte 0 ==
1989 00:41:11.754739 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1990 00:41:11.754800 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1991 00:41:11.754855 == TX Byte 1 ==
1992 00:41:11.754907 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1993 00:41:11.754959 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1994 00:41:11.755009 ==
1995 00:41:11.755059 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 00:41:11.755108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 00:41:11.755159 ==
1998 00:41:11.755209 TX Vref=22, minBit 5, minWin=27, winSum=449
1999 00:41:11.755259 TX Vref=24, minBit 0, minWin=28, winSum=453
2000 00:41:11.755308 TX Vref=26, minBit 0, minWin=28, winSum=456
2001 00:41:11.755357 TX Vref=28, minBit 1, minWin=27, winSum=456
2002 00:41:11.755611 TX Vref=30, minBit 1, minWin=27, winSum=456
2003 00:41:11.755753 TX Vref=32, minBit 1, minWin=27, winSum=457
2004 00:41:11.755865 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 26
2005 00:41:11.755976
2006 00:41:11.756189 Final TX Range 1 Vref 26
2007 00:41:11.756302
2008 00:41:11.756428 ==
2009 00:41:11.756538 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 00:41:11.756657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 00:41:11.756816 ==
2012 00:41:11.756925
2013 00:41:11.757030
2014 00:41:11.757083 TX Vref Scan disable
2015 00:41:11.757133 == TX Byte 0 ==
2016 00:41:11.757182 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2017 00:41:11.757232 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2018 00:41:11.757281 == TX Byte 1 ==
2019 00:41:11.757329 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2020 00:41:11.757378 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2021 00:41:11.757426
2022 00:41:11.757473 [DATLAT]
2023 00:41:11.757520 Freq=800, CH1 RK1
2024 00:41:11.757568
2025 00:41:11.757617 DATLAT Default: 0xa
2026 00:41:11.757665 0, 0xFFFF, sum = 0
2027 00:41:11.757715 1, 0xFFFF, sum = 0
2028 00:41:11.757764 2, 0xFFFF, sum = 0
2029 00:41:11.757813 3, 0xFFFF, sum = 0
2030 00:41:11.757862 4, 0xFFFF, sum = 0
2031 00:41:11.757910 5, 0xFFFF, sum = 0
2032 00:41:11.757959 6, 0xFFFF, sum = 0
2033 00:41:11.758008 7, 0xFFFF, sum = 0
2034 00:41:11.758056 8, 0xFFFF, sum = 0
2035 00:41:11.758105 9, 0x0, sum = 1
2036 00:41:11.758153 10, 0x0, sum = 2
2037 00:41:11.758202 11, 0x0, sum = 3
2038 00:41:11.758250 12, 0x0, sum = 4
2039 00:41:11.758299 best_step = 10
2040 00:41:11.758345
2041 00:41:11.758393 ==
2042 00:41:11.758441 Dram Type= 6, Freq= 0, CH_1, rank 1
2043 00:41:11.758519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2044 00:41:11.758567 ==
2045 00:41:11.758618 RX Vref Scan: 0
2046 00:41:11.758667
2047 00:41:11.758715 RX Vref 0 -> 0, step: 1
2048 00:41:11.758762
2049 00:41:11.758830 RX Delay -111 -> 252, step: 8
2050 00:41:11.758928 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2051 00:41:11.759057 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2052 00:41:11.759110 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2053 00:41:11.759160 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2054 00:41:11.759213 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2055 00:41:11.759262 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2056 00:41:11.759309 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2057 00:41:11.759357 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2058 00:41:11.759405 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2059 00:41:11.759454 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2060 00:41:11.759507 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2061 00:41:11.759560 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2062 00:41:11.759612 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2063 00:41:11.759662 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2064 00:41:11.759738 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2065 00:41:11.759814 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2066 00:41:11.759890 ==
2067 00:41:11.759967 Dram Type= 6, Freq= 0, CH_1, rank 1
2068 00:41:11.760044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2069 00:41:11.760121 ==
2070 00:41:11.760228 DQS Delay:
2071 00:41:11.760303 DQS0 = 0, DQS1 = 0
2072 00:41:11.760380 DQM Delay:
2073 00:41:11.760455 DQM0 = 77, DQM1 = 74
2074 00:41:11.760531 DQ Delay:
2075 00:41:11.760607 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2076 00:41:11.760724 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2077 00:41:11.760801 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2078 00:41:11.760878 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2079 00:41:11.760953
2080 00:41:11.761028
2081 00:41:11.761106 [DQSOSCAuto] RK1, (LSB)MR18= 0x2841, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
2082 00:41:11.761183 CH1 RK1: MR19=606, MR18=2841
2083 00:41:11.761260 CH1_RK1: MR19=0x606, MR18=0x2841, DQSOSC=393, MR23=63, INC=95, DEC=63
2084 00:41:11.761337 [RxdqsGatingPostProcess] freq 800
2085 00:41:11.761414 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2086 00:41:11.761490 Pre-setting of DQS Precalculation
2087 00:41:11.761567 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2088 00:41:11.761645 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2089 00:41:11.761723 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2090 00:41:11.761799
2091 00:41:11.761875
2092 00:41:11.761950 [Calibration Summary] 1600 Mbps
2093 00:41:11.762026 CH 0, Rank 0
2094 00:41:11.762102 SW Impedance : PASS
2095 00:41:11.762179 DUTY Scan : NO K
2096 00:41:11.762255 ZQ Calibration : PASS
2097 00:41:11.762331 Jitter Meter : NO K
2098 00:41:11.762407 CBT Training : PASS
2099 00:41:11.762483 Write leveling : PASS
2100 00:41:11.762559 RX DQS gating : PASS
2101 00:41:11.762635 RX DQ/DQS(RDDQC) : PASS
2102 00:41:11.762710 TX DQ/DQS : PASS
2103 00:41:11.762787 RX DATLAT : PASS
2104 00:41:11.762863 RX DQ/DQS(Engine): PASS
2105 00:41:11.762938 TX OE : NO K
2106 00:41:11.763014 All Pass.
2107 00:41:11.763089
2108 00:41:11.763164 CH 0, Rank 1
2109 00:41:11.763241 SW Impedance : PASS
2110 00:41:11.763317 DUTY Scan : NO K
2111 00:41:11.763393 ZQ Calibration : PASS
2112 00:41:11.763469 Jitter Meter : NO K
2113 00:41:11.763545 CBT Training : PASS
2114 00:41:11.763621 Write leveling : PASS
2115 00:41:11.763697 RX DQS gating : PASS
2116 00:41:11.763805 RX DQ/DQS(RDDQC) : PASS
2117 00:41:11.763881 TX DQ/DQS : PASS
2118 00:41:11.763957 RX DATLAT : PASS
2119 00:41:11.764033 RX DQ/DQS(Engine): PASS
2120 00:41:11.764108 TX OE : NO K
2121 00:41:11.764184 All Pass.
2122 00:41:11.764259
2123 00:41:11.764335 CH 1, Rank 0
2124 00:41:11.764411 SW Impedance : PASS
2125 00:41:11.764486 DUTY Scan : NO K
2126 00:41:11.764562 ZQ Calibration : PASS
2127 00:41:11.764638 Jitter Meter : NO K
2128 00:41:11.764728 CBT Training : PASS
2129 00:41:11.764777 Write leveling : PASS
2130 00:41:11.764826 RX DQS gating : PASS
2131 00:41:11.764875 RX DQ/DQS(RDDQC) : PASS
2132 00:41:11.764922 TX DQ/DQS : PASS
2133 00:41:11.764970 RX DATLAT : PASS
2134 00:41:11.765018 RX DQ/DQS(Engine): PASS
2135 00:41:11.765069 TX OE : NO K
2136 00:41:11.765140 All Pass.
2137 00:41:11.765192
2138 00:41:11.765241 CH 1, Rank 1
2139 00:41:11.765301 SW Impedance : PASS
2140 00:41:11.765361 DUTY Scan : NO K
2141 00:41:11.765410 ZQ Calibration : PASS
2142 00:41:11.765459 Jitter Meter : NO K
2143 00:41:11.765508 CBT Training : PASS
2144 00:41:11.765557 Write leveling : PASS
2145 00:41:11.765610 RX DQS gating : PASS
2146 00:41:11.765660 RX DQ/DQS(RDDQC) : PASS
2147 00:41:11.765709 TX DQ/DQS : PASS
2148 00:41:11.765815 RX DATLAT : PASS
2149 00:41:11.765866 RX DQ/DQS(Engine): PASS
2150 00:41:11.765914 TX OE : NO K
2151 00:41:11.765963 All Pass.
2152 00:41:11.766012
2153 00:41:11.766065 DramC Write-DBI off
2154 00:41:11.766117 PER_BANK_REFRESH: Hybrid Mode
2155 00:41:11.766179 TX_TRACKING: ON
2156 00:41:11.766254 [GetDramInforAfterCalByMRR] Vendor 6.
2157 00:41:11.766499 [GetDramInforAfterCalByMRR] Revision 606.
2158 00:41:11.766619 [GetDramInforAfterCalByMRR] Revision 2 0.
2159 00:41:11.766696 MR0 0x3b3b
2160 00:41:11.766772 MR8 0x5151
2161 00:41:11.766848 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2162 00:41:11.766924
2163 00:41:11.766999 MR0 0x3b3b
2164 00:41:11.767104 MR8 0x5151
2165 00:41:11.767180 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 00:41:11.767256
2167 00:41:11.767334 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2168 00:41:11.767412 [FAST_K] Save calibration result to emmc
2169 00:41:11.767489 [FAST_K] Save calibration result to emmc
2170 00:41:11.767565 dram_init: config_dvfs: 1
2171 00:41:11.767641 dramc_set_vcore_voltage set vcore to 662500
2172 00:41:11.767718 Read voltage for 1200, 2
2173 00:41:11.767793 Vio18 = 0
2174 00:41:11.767869 Vcore = 662500
2175 00:41:11.767944 Vdram = 0
2176 00:41:11.768020 Vddq = 0
2177 00:41:11.768095 Vmddr = 0
2178 00:41:11.768171 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2179 00:41:11.768226 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2180 00:41:11.768277 MEM_TYPE=3, freq_sel=15
2181 00:41:11.768356 sv_algorithm_assistance_LP4_1600
2182 00:41:11.768447 ============ PULL DRAM RESETB DOWN ============
2183 00:41:11.768540 ========== PULL DRAM RESETB DOWN end =========
2184 00:41:11.768619 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2185 00:41:11.768706 ===================================
2186 00:41:11.768759 LPDDR4 DRAM CONFIGURATION
2187 00:41:11.768813 ===================================
2188 00:41:11.768866 EX_ROW_EN[0] = 0x0
2189 00:41:11.768916 EX_ROW_EN[1] = 0x0
2190 00:41:11.768964 LP4Y_EN = 0x0
2191 00:41:11.769013 WORK_FSP = 0x0
2192 00:41:11.769061 WL = 0x4
2193 00:41:11.769110 RL = 0x4
2194 00:41:11.769158 BL = 0x2
2195 00:41:11.769206 RPST = 0x0
2196 00:41:11.769254 RD_PRE = 0x0
2197 00:41:11.769303 WR_PRE = 0x1
2198 00:41:11.769351 WR_PST = 0x0
2199 00:41:11.769400 DBI_WR = 0x0
2200 00:41:11.769448 DBI_RD = 0x0
2201 00:41:11.769497 OTF = 0x1
2202 00:41:11.769545 ===================================
2203 00:41:11.769594 ===================================
2204 00:41:11.769643 ANA top config
2205 00:41:11.769691 ===================================
2206 00:41:11.769740 DLL_ASYNC_EN = 0
2207 00:41:11.769789 ALL_SLAVE_EN = 0
2208 00:41:11.769838 NEW_RANK_MODE = 1
2209 00:41:11.769887 DLL_IDLE_MODE = 1
2210 00:41:11.769936 LP45_APHY_COMB_EN = 1
2211 00:41:11.769985 TX_ODT_DIS = 1
2212 00:41:11.770034 NEW_8X_MODE = 1
2213 00:41:11.770083 ===================================
2214 00:41:11.770132 ===================================
2215 00:41:11.770181 data_rate = 2400
2216 00:41:11.770231 CKR = 1
2217 00:41:11.770280 DQ_P2S_RATIO = 8
2218 00:41:11.770328 ===================================
2219 00:41:11.770377 CA_P2S_RATIO = 8
2220 00:41:11.770425 DQ_CA_OPEN = 0
2221 00:41:11.770474 DQ_SEMI_OPEN = 0
2222 00:41:11.770523 CA_SEMI_OPEN = 0
2223 00:41:11.770571 CA_FULL_RATE = 0
2224 00:41:11.770620 DQ_CKDIV4_EN = 0
2225 00:41:11.770668 CA_CKDIV4_EN = 0
2226 00:41:11.770716 CA_PREDIV_EN = 0
2227 00:41:11.770765 PH8_DLY = 17
2228 00:41:11.770814 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2229 00:41:11.770862 DQ_AAMCK_DIV = 4
2230 00:41:11.770910 CA_AAMCK_DIV = 4
2231 00:41:11.770958 CA_ADMCK_DIV = 4
2232 00:41:11.771007 DQ_TRACK_CA_EN = 0
2233 00:41:11.771058 CA_PICK = 1200
2234 00:41:11.771149 CA_MCKIO = 1200
2235 00:41:11.771199 MCKIO_SEMI = 0
2236 00:41:11.771248 PLL_FREQ = 2366
2237 00:41:11.771296 DQ_UI_PI_RATIO = 32
2238 00:41:11.771345 CA_UI_PI_RATIO = 0
2239 00:41:11.771392 ===================================
2240 00:41:11.771441 ===================================
2241 00:41:11.771490 memory_type:LPDDR4
2242 00:41:11.771540 GP_NUM : 10
2243 00:41:11.771588 SRAM_EN : 1
2244 00:41:11.771636 MD32_EN : 0
2245 00:41:11.771685 ===================================
2246 00:41:11.771734 [ANA_INIT] >>>>>>>>>>>>>>
2247 00:41:11.771782 <<<<<< [CONFIGURE PHASE]: ANA_TX
2248 00:41:11.771831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2249 00:41:11.771879 ===================================
2250 00:41:11.771928 data_rate = 2400,PCW = 0X5b00
2251 00:41:11.771976 ===================================
2252 00:41:11.772025 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2253 00:41:11.772074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2254 00:41:11.772123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2255 00:41:11.772173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2256 00:41:11.772222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2257 00:41:11.772270 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2258 00:41:11.772318 [ANA_INIT] flow start
2259 00:41:11.772367 [ANA_INIT] PLL >>>>>>>>
2260 00:41:11.772415 [ANA_INIT] PLL <<<<<<<<
2261 00:41:11.772463 [ANA_INIT] MIDPI >>>>>>>>
2262 00:41:11.772510 [ANA_INIT] MIDPI <<<<<<<<
2263 00:41:11.772560 [ANA_INIT] DLL >>>>>>>>
2264 00:41:11.772608 [ANA_INIT] DLL <<<<<<<<
2265 00:41:11.772701 [ANA_INIT] flow end
2266 00:41:11.772752 ============ LP4 DIFF to SE enter ============
2267 00:41:11.772801 ============ LP4 DIFF to SE exit ============
2268 00:41:11.772850 [ANA_INIT] <<<<<<<<<<<<<
2269 00:41:11.772898 [Flow] Enable top DCM control >>>>>
2270 00:41:11.772947 [Flow] Enable top DCM control <<<<<
2271 00:41:11.772995 Enable DLL master slave shuffle
2272 00:41:11.773044 ==============================================================
2273 00:41:11.773093 Gating Mode config
2274 00:41:11.773142 ==============================================================
2275 00:41:11.773191 Config description:
2276 00:41:11.773239 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2277 00:41:11.773289 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2278 00:41:11.773338 SELPH_MODE 0: By rank 1: By Phase
2279 00:41:11.773579 ==============================================================
2280 00:41:11.773693 GAT_TRACK_EN = 1
2281 00:41:11.773865 RX_GATING_MODE = 2
2282 00:41:11.773974 RX_GATING_TRACK_MODE = 2
2283 00:41:11.774112 SELPH_MODE = 1
2284 00:41:11.774222 PICG_EARLY_EN = 1
2285 00:41:11.774331 VALID_LAT_VALUE = 1
2286 00:41:11.774471 ==============================================================
2287 00:41:11.774582 Enter into Gating configuration >>>>
2288 00:41:11.774720 Exit from Gating configuration <<<<
2289 00:41:11.774828 Enter into DVFS_PRE_config >>>>>
2290 00:41:11.774937 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2291 00:41:11.775072 Exit from DVFS_PRE_config <<<<<
2292 00:41:11.775141 Enter into PICG configuration >>>>
2293 00:41:11.775191 Exit from PICG configuration <<<<
2294 00:41:11.775256 [RX_INPUT] configuration >>>>>
2295 00:41:11.775321 [RX_INPUT] configuration <<<<<
2296 00:41:11.775370 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2297 00:41:11.775420 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2298 00:41:11.775469 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2299 00:41:11.775562 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2300 00:41:11.775643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 00:41:11.775722 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 00:41:11.775828 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2303 00:41:11.775905 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2304 00:41:11.775982 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2305 00:41:11.776059 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2306 00:41:11.776151 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2307 00:41:11.776285 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2308 00:41:11.776392 ===================================
2309 00:41:11.776470 LPDDR4 DRAM CONFIGURATION
2310 00:41:11.776548 ===================================
2311 00:41:11.776627 EX_ROW_EN[0] = 0x0
2312 00:41:11.776744 EX_ROW_EN[1] = 0x0
2313 00:41:11.776799 LP4Y_EN = 0x0
2314 00:41:11.776879 WORK_FSP = 0x0
2315 00:41:11.776929 WL = 0x4
2316 00:41:11.777035 RL = 0x4
2317 00:41:11.777221 BL = 0x2
2318 00:41:11.777350 RPST = 0x0
2319 00:41:11.777433 RD_PRE = 0x0
2320 00:41:11.777514 WR_PRE = 0x1
2321 00:41:11.777578 WR_PST = 0x0
2322 00:41:11.777626 DBI_WR = 0x0
2323 00:41:11.777674 DBI_RD = 0x0
2324 00:41:11.777723 OTF = 0x1
2325 00:41:11.777772 ===================================
2326 00:41:11.777821 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2327 00:41:11.777870 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2328 00:41:11.777918 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2329 00:41:11.777968 ===================================
2330 00:41:11.778017 LPDDR4 DRAM CONFIGURATION
2331 00:41:11.778065 ===================================
2332 00:41:11.778114 EX_ROW_EN[0] = 0x10
2333 00:41:11.778163 EX_ROW_EN[1] = 0x0
2334 00:41:11.778212 LP4Y_EN = 0x0
2335 00:41:11.778261 WORK_FSP = 0x0
2336 00:41:11.778309 WL = 0x4
2337 00:41:11.778357 RL = 0x4
2338 00:41:11.778405 BL = 0x2
2339 00:41:11.778454 RPST = 0x0
2340 00:41:11.778503 RD_PRE = 0x0
2341 00:41:11.778551 WR_PRE = 0x1
2342 00:41:11.778598 WR_PST = 0x0
2343 00:41:11.778647 DBI_WR = 0x0
2344 00:41:11.778695 DBI_RD = 0x0
2345 00:41:11.778743 OTF = 0x1
2346 00:41:11.778791 ===================================
2347 00:41:11.778841 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2348 00:41:11.778891 ==
2349 00:41:11.778940 Dram Type= 6, Freq= 0, CH_0, rank 0
2350 00:41:11.778990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2351 00:41:11.779039 ==
2352 00:41:11.779087 [Duty_Offset_Calibration]
2353 00:41:11.779135 B0:2 B1:0 CA:3
2354 00:41:11.779184
2355 00:41:11.779232 [DutyScan_Calibration_Flow] k_type=0
2356 00:41:11.779280
2357 00:41:11.779328 ==CLK 0==
2358 00:41:11.779377 Final CLK duty delay cell = 0
2359 00:41:11.779426 [0] MAX Duty = 5062%(X100), DQS PI = 12
2360 00:41:11.779475 [0] MIN Duty = 4906%(X100), DQS PI = 54
2361 00:41:11.779524 [0] AVG Duty = 4984%(X100)
2362 00:41:11.779572
2363 00:41:11.779620 CH0 CLK Duty spec in!! Max-Min= 156%
2364 00:41:11.779668 [DutyScan_Calibration_Flow] ====Done====
2365 00:41:11.779716
2366 00:41:11.779763 [DutyScan_Calibration_Flow] k_type=1
2367 00:41:11.779811
2368 00:41:11.779859 ==DQS 0 ==
2369 00:41:11.779908 Final DQS duty delay cell = 0
2370 00:41:11.779978 [0] MAX Duty = 5062%(X100), DQS PI = 16
2371 00:41:11.780028 [0] MIN Duty = 4907%(X100), DQS PI = 2
2372 00:41:11.780077 [0] AVG Duty = 4984%(X100)
2373 00:41:11.780125
2374 00:41:11.780172 ==DQS 1 ==
2375 00:41:11.780221 Final DQS duty delay cell = -4
2376 00:41:11.780269 [-4] MAX Duty = 4969%(X100), DQS PI = 6
2377 00:41:11.780318 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2378 00:41:11.780367 [-4] AVG Duty = 4922%(X100)
2379 00:41:11.780414
2380 00:41:11.780462 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2381 00:41:11.780511
2382 00:41:11.780559 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2383 00:41:11.780607 [DutyScan_Calibration_Flow] ====Done====
2384 00:41:11.780664
2385 00:41:11.780751 [DutyScan_Calibration_Flow] k_type=3
2386 00:41:11.780798
2387 00:41:11.780846 ==DQM 0 ==
2388 00:41:11.780895 Final DQM duty delay cell = 0
2389 00:41:11.780943 [0] MAX Duty = 5124%(X100), DQS PI = 28
2390 00:41:11.781016 [0] MIN Duty = 4876%(X100), DQS PI = 0
2391 00:41:11.781078 [0] AVG Duty = 5000%(X100)
2392 00:41:11.781126
2393 00:41:11.781173 ==DQM 1 ==
2394 00:41:11.781221 Final DQM duty delay cell = 4
2395 00:41:11.781269 [4] MAX Duty = 5093%(X100), DQS PI = 50
2396 00:41:11.781317 [4] MIN Duty = 5000%(X100), DQS PI = 12
2397 00:41:11.781366 [4] AVG Duty = 5046%(X100)
2398 00:41:11.781413
2399 00:41:11.781461 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2400 00:41:11.781509
2401 00:41:11.781556 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2402 00:41:11.781604 [DutyScan_Calibration_Flow] ====Done====
2403 00:41:11.781653
2404 00:41:11.781701 [DutyScan_Calibration_Flow] k_type=2
2405 00:41:11.781753
2406 00:41:11.781803 ==DQ 0 ==
2407 00:41:11.781870 Final DQ duty delay cell = -4
2408 00:41:11.781936 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2409 00:41:11.781985 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2410 00:41:11.782033 [-4] AVG Duty = 4969%(X100)
2411 00:41:11.782081
2412 00:41:11.782129 ==DQ 1 ==
2413 00:41:11.782369 Final DQ duty delay cell = -4
2414 00:41:11.782425 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2415 00:41:11.782474 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2416 00:41:11.782523 [-4] AVG Duty = 4922%(X100)
2417 00:41:11.782571
2418 00:41:11.782619 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2419 00:41:11.782689
2420 00:41:11.782750 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2421 00:41:11.782797 [DutyScan_Calibration_Flow] ====Done====
2422 00:41:11.782844 ==
2423 00:41:11.782892 Dram Type= 6, Freq= 0, CH_1, rank 0
2424 00:41:11.782940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2425 00:41:11.782989 ==
2426 00:41:11.783036 [Duty_Offset_Calibration]
2427 00:41:11.783084 B0:1 B1:-2 CA:0
2428 00:41:11.783131
2429 00:41:11.783178 [DutyScan_Calibration_Flow] k_type=0
2430 00:41:11.783226
2431 00:41:11.783273 ==CLK 0==
2432 00:41:11.783321 Final CLK duty delay cell = 0
2433 00:41:11.783383 [0] MAX Duty = 5031%(X100), DQS PI = 18
2434 00:41:11.783437 [0] MIN Duty = 4875%(X100), DQS PI = 58
2435 00:41:11.783486 [0] AVG Duty = 4953%(X100)
2436 00:41:11.783534
2437 00:41:11.783583 CH1 CLK Duty spec in!! Max-Min= 156%
2438 00:41:11.783631 [DutyScan_Calibration_Flow] ====Done====
2439 00:41:11.783680
2440 00:41:11.783728 [DutyScan_Calibration_Flow] k_type=1
2441 00:41:11.783775
2442 00:41:11.783823 ==DQS 0 ==
2443 00:41:11.783871 Final DQS duty delay cell = -4
2444 00:41:11.783920 [-4] MAX Duty = 5000%(X100), DQS PI = 22
2445 00:41:11.783968 [-4] MIN Duty = 4876%(X100), DQS PI = 52
2446 00:41:11.784016 [-4] AVG Duty = 4938%(X100)
2447 00:41:11.784064
2448 00:41:11.784111 ==DQS 1 ==
2449 00:41:11.784158 Final DQS duty delay cell = 0
2450 00:41:11.784206 [0] MAX Duty = 5062%(X100), DQS PI = 0
2451 00:41:11.784254 [0] MIN Duty = 4875%(X100), DQS PI = 26
2452 00:41:11.784302 [0] AVG Duty = 4968%(X100)
2453 00:41:11.784349
2454 00:41:11.784411 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2455 00:41:11.784460
2456 00:41:11.784548 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2457 00:41:11.784628 [DutyScan_Calibration_Flow] ====Done====
2458 00:41:11.784706
2459 00:41:11.784755 [DutyScan_Calibration_Flow] k_type=3
2460 00:41:11.784803
2461 00:41:11.784851 ==DQM 0 ==
2462 00:41:11.784899 Final DQM duty delay cell = 0
2463 00:41:11.784948 [0] MAX Duty = 5000%(X100), DQS PI = 22
2464 00:41:11.785006 [0] MIN Duty = 4844%(X100), DQS PI = 54
2465 00:41:11.785064 [0] AVG Duty = 4922%(X100)
2466 00:41:11.785113
2467 00:41:11.785160 ==DQM 1 ==
2468 00:41:11.785208 Final DQM duty delay cell = 0
2469 00:41:11.785259 [0] MAX Duty = 5031%(X100), DQS PI = 36
2470 00:41:11.785309 [0] MIN Duty = 4907%(X100), DQS PI = 0
2471 00:41:11.785358 [0] AVG Duty = 4969%(X100)
2472 00:41:11.785405
2473 00:41:11.785453 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2474 00:41:11.785502
2475 00:41:11.785554 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2476 00:41:11.785606 [DutyScan_Calibration_Flow] ====Done====
2477 00:41:11.785654
2478 00:41:11.785701 [DutyScan_Calibration_Flow] k_type=2
2479 00:41:11.785753
2480 00:41:11.785805 ==DQ 0 ==
2481 00:41:11.785855 Final DQ duty delay cell = 0
2482 00:41:11.785903 [0] MAX Duty = 5062%(X100), DQS PI = 16
2483 00:41:11.785951 [0] MIN Duty = 4938%(X100), DQS PI = 54
2484 00:41:11.785998 [0] AVG Duty = 5000%(X100)
2485 00:41:11.786045
2486 00:41:11.786092 ==DQ 1 ==
2487 00:41:11.786140 Final DQ duty delay cell = 0
2488 00:41:11.786188 [0] MAX Duty = 5093%(X100), DQS PI = 20
2489 00:41:11.786237 [0] MIN Duty = 4969%(X100), DQS PI = 26
2490 00:41:11.786286 [0] AVG Duty = 5031%(X100)
2491 00:41:11.786333
2492 00:41:11.786381 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2493 00:41:11.786429
2494 00:41:11.786476 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2495 00:41:11.786525 [DutyScan_Calibration_Flow] ====Done====
2496 00:41:11.786591 nWR fixed to 30
2497 00:41:11.786644 [ModeRegInit_LP4] CH0 RK0
2498 00:41:11.786692 [ModeRegInit_LP4] CH0 RK1
2499 00:41:11.786739 [ModeRegInit_LP4] CH1 RK0
2500 00:41:11.786787 [ModeRegInit_LP4] CH1 RK1
2501 00:41:11.786835 match AC timing 7
2502 00:41:11.786882 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2503 00:41:11.786930 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2504 00:41:11.786979 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2505 00:41:11.787026 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2506 00:41:11.787075 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2507 00:41:11.787122 ==
2508 00:41:11.787170 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 00:41:11.787219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 00:41:11.787267 ==
2511 00:41:11.787315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2512 00:41:11.787363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2513 00:41:11.787412 [CA 0] Center 40 (10~71) winsize 62
2514 00:41:11.787459 [CA 1] Center 39 (9~70) winsize 62
2515 00:41:11.787508 [CA 2] Center 36 (6~66) winsize 61
2516 00:41:11.787556 [CA 3] Center 35 (5~66) winsize 62
2517 00:41:11.787605 [CA 4] Center 34 (4~65) winsize 62
2518 00:41:11.787653 [CA 5] Center 33 (3~63) winsize 61
2519 00:41:11.787700
2520 00:41:11.787747 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2521 00:41:11.787795
2522 00:41:11.787842 [CATrainingPosCal] consider 1 rank data
2523 00:41:11.787890 u2DelayCellTimex100 = 270/100 ps
2524 00:41:11.787938 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2525 00:41:11.787986 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2526 00:41:11.788034 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2527 00:41:11.788082 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2528 00:41:11.788131 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2529 00:41:11.788179 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2530 00:41:11.788227
2531 00:41:11.788275 CA PerBit enable=1, Macro0, CA PI delay=33
2532 00:41:11.788323
2533 00:41:11.788369 [CBTSetCACLKResult] CA Dly = 33
2534 00:41:11.788417 CS Dly: 7 (0~38)
2535 00:41:11.788464 ==
2536 00:41:11.788512 Dram Type= 6, Freq= 0, CH_0, rank 1
2537 00:41:11.788560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 00:41:11.788608 ==
2539 00:41:11.788686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2540 00:41:11.788749 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2541 00:41:11.788798 [CA 0] Center 40 (10~70) winsize 61
2542 00:41:11.788846 [CA 1] Center 39 (9~70) winsize 62
2543 00:41:11.788894 [CA 2] Center 35 (5~66) winsize 62
2544 00:41:11.788941 [CA 3] Center 35 (5~66) winsize 62
2545 00:41:11.788989 [CA 4] Center 34 (4~65) winsize 62
2546 00:41:11.789037 [CA 5] Center 33 (3~63) winsize 61
2547 00:41:11.789084
2548 00:41:11.789131 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2549 00:41:11.789179
2550 00:41:11.789227 [CATrainingPosCal] consider 2 rank data
2551 00:41:11.789275 u2DelayCellTimex100 = 270/100 ps
2552 00:41:11.789323 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2553 00:41:11.789371 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2554 00:41:11.789419 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2555 00:41:11.789658 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2556 00:41:11.789769 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2557 00:41:11.789880 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2558 00:41:11.789987
2559 00:41:11.790095 CA PerBit enable=1, Macro0, CA PI delay=33
2560 00:41:11.790203
2561 00:41:11.790311 [CBTSetCACLKResult] CA Dly = 33
2562 00:41:11.790419 CS Dly: 7 (0~39)
2563 00:41:11.790527
2564 00:41:11.790635 ----->DramcWriteLeveling(PI) begin...
2565 00:41:11.790746 ==
2566 00:41:11.790855 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 00:41:11.790933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 00:41:11.790986 ==
2569 00:41:11.791035 Write leveling (Byte 0): 32 => 32
2570 00:41:11.791084 Write leveling (Byte 1): 30 => 30
2571 00:41:11.791132 DramcWriteLeveling(PI) end<-----
2572 00:41:11.791180
2573 00:41:11.791227 ==
2574 00:41:11.791275 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 00:41:11.791323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 00:41:11.791370 ==
2577 00:41:11.791418 [Gating] SW mode calibration
2578 00:41:11.791466 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2579 00:41:11.791515 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2580 00:41:11.791563 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 00:41:11.791611 0 15 4 | B1->B0 | 2c2c 3333 | 0 1 | (0 0) (1 1)
2582 00:41:11.791659 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 00:41:11.791707 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 00:41:11.791755 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 00:41:11.791802 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 00:41:11.791849 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 00:41:11.791897 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2588 00:41:11.791945 1 0 0 | B1->B0 | 3030 2424 | 0 0 | (0 0) (1 0)
2589 00:41:11.791992 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2590 00:41:11.792040 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 00:41:11.792088 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 00:41:11.792136 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 00:41:11.792183 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 00:41:11.792232 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 00:41:11.792279 1 0 28 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
2596 00:41:11.792327 1 1 0 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
2597 00:41:11.792375 1 1 4 | B1->B0 | 4241 4646 | 1 0 | (0 0) (0 0)
2598 00:41:11.792423 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 00:41:11.792472 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 00:41:11.792520 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 00:41:11.792567 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 00:41:11.792615 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 00:41:11.792705 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2604 00:41:11.792755 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2605 00:41:11.792803 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 00:41:11.792851 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 00:41:11.792899 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 00:41:11.792947 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 00:41:11.792995 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 00:41:11.793043 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 00:41:11.793091 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 00:41:11.793138 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 00:41:11.793187 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 00:41:11.793235 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 00:41:11.793283 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 00:41:11.793331 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 00:41:11.793379 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 00:41:11.793427 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 00:41:11.793474 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2620 00:41:11.793522 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2621 00:41:11.793570 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2622 00:41:11.793618 Total UI for P1: 0, mck2ui 16
2623 00:41:11.793667 best dqsien dly found for B0: ( 1, 3, 30)
2624 00:41:11.793715 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 00:41:11.793762 Total UI for P1: 0, mck2ui 16
2626 00:41:11.793810 best dqsien dly found for B1: ( 1, 4, 2)
2627 00:41:11.793863 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2628 00:41:11.793924 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2629 00:41:11.793973
2630 00:41:11.794021 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2631 00:41:11.794070 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2632 00:41:11.794119 [Gating] SW calibration Done
2633 00:41:11.794167 ==
2634 00:41:11.794215 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 00:41:11.794263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 00:41:11.794311 ==
2637 00:41:11.794359 RX Vref Scan: 0
2638 00:41:11.794406
2639 00:41:11.794454 RX Vref 0 -> 0, step: 1
2640 00:41:11.794502
2641 00:41:11.794550 RX Delay -40 -> 252, step: 8
2642 00:41:11.794598 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2643 00:41:11.794646 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2644 00:41:11.794697 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2645 00:41:11.794746 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2646 00:41:11.794810 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2647 00:41:11.794859 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2648 00:41:11.794908 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2649 00:41:11.794957 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2650 00:41:11.795004 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2651 00:41:11.795052 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2652 00:41:11.795101 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2653 00:41:11.795149 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2654 00:41:11.795196 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2655 00:41:11.795245 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2656 00:41:11.795484 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2657 00:41:11.795539 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2658 00:41:11.795588 ==
2659 00:41:11.795636 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 00:41:11.795684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 00:41:11.795732 ==
2662 00:41:11.795780 DQS Delay:
2663 00:41:11.795828 DQS0 = 0, DQS1 = 0
2664 00:41:11.795876 DQM Delay:
2665 00:41:11.795924 DQM0 = 112, DQM1 = 102
2666 00:41:11.795972 DQ Delay:
2667 00:41:11.796019 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2668 00:41:11.796067 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2669 00:41:11.796115 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2670 00:41:11.796162 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2671 00:41:11.796209
2672 00:41:11.796256
2673 00:41:11.796303 ==
2674 00:41:11.796351 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 00:41:11.796399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 00:41:11.796447 ==
2677 00:41:11.796495
2678 00:41:11.796541
2679 00:41:11.796589 TX Vref Scan disable
2680 00:41:11.796637 == TX Byte 0 ==
2681 00:41:11.796722 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2682 00:41:11.796771 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2683 00:41:11.796820 == TX Byte 1 ==
2684 00:41:11.796868 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2685 00:41:11.796917 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2686 00:41:11.796965 ==
2687 00:41:11.797013 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 00:41:11.797061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 00:41:11.797109 ==
2690 00:41:11.797157 TX Vref=22, minBit 4, minWin=25, winSum=415
2691 00:41:11.797205 TX Vref=24, minBit 0, minWin=26, winSum=421
2692 00:41:11.797253 TX Vref=26, minBit 7, minWin=26, winSum=430
2693 00:41:11.797300 TX Vref=28, minBit 10, minWin=26, winSum=435
2694 00:41:11.797348 TX Vref=30, minBit 10, minWin=26, winSum=434
2695 00:41:11.797395 TX Vref=32, minBit 0, minWin=26, winSum=432
2696 00:41:11.797444 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 28
2697 00:41:11.797493
2698 00:41:11.797541 Final TX Range 1 Vref 28
2699 00:41:11.797588
2700 00:41:11.797635 ==
2701 00:41:11.797682 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 00:41:11.797730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 00:41:11.797778 ==
2704 00:41:11.797825
2705 00:41:11.797872
2706 00:41:11.797920 TX Vref Scan disable
2707 00:41:11.797968 == TX Byte 0 ==
2708 00:41:11.798016 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2709 00:41:11.798064 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2710 00:41:11.798111 == TX Byte 1 ==
2711 00:41:11.798159 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2712 00:41:11.798207 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2713 00:41:11.798255
2714 00:41:11.798302 [DATLAT]
2715 00:41:11.798349 Freq=1200, CH0 RK0
2716 00:41:11.798397
2717 00:41:11.798444 DATLAT Default: 0xd
2718 00:41:11.798492 0, 0xFFFF, sum = 0
2719 00:41:11.798541 1, 0xFFFF, sum = 0
2720 00:41:11.798590 2, 0xFFFF, sum = 0
2721 00:41:11.798639 3, 0xFFFF, sum = 0
2722 00:41:11.798687 4, 0xFFFF, sum = 0
2723 00:41:11.798735 5, 0xFFFF, sum = 0
2724 00:41:11.798783 6, 0xFFFF, sum = 0
2725 00:41:11.798832 7, 0xFFFF, sum = 0
2726 00:41:11.798880 8, 0xFFFF, sum = 0
2727 00:41:11.798928 9, 0xFFFF, sum = 0
2728 00:41:11.798976 10, 0xFFFF, sum = 0
2729 00:41:11.799025 11, 0xFFFF, sum = 0
2730 00:41:11.799073 12, 0x0, sum = 1
2731 00:41:11.799122 13, 0x0, sum = 2
2732 00:41:11.799170 14, 0x0, sum = 3
2733 00:41:11.799219 15, 0x0, sum = 4
2734 00:41:11.799301 best_step = 13
2735 00:41:11.799374
2736 00:41:11.799424 ==
2737 00:41:11.799472 Dram Type= 6, Freq= 0, CH_0, rank 0
2738 00:41:11.799521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2739 00:41:11.799570 ==
2740 00:41:11.799618 RX Vref Scan: 1
2741 00:41:11.799666
2742 00:41:11.799713 Set Vref Range= 32 -> 127
2743 00:41:11.799760
2744 00:41:11.799808 RX Vref 32 -> 127, step: 1
2745 00:41:11.799856
2746 00:41:11.799903 RX Delay -37 -> 252, step: 4
2747 00:41:11.799950
2748 00:41:11.799997 Set Vref, RX VrefLevel [Byte0]: 32
2749 00:41:11.800045 [Byte1]: 32
2750 00:41:11.800092
2751 00:41:11.800139 Set Vref, RX VrefLevel [Byte0]: 33
2752 00:41:11.800187 [Byte1]: 33
2753 00:41:11.800235
2754 00:41:11.800283 Set Vref, RX VrefLevel [Byte0]: 34
2755 00:41:11.800331 [Byte1]: 34
2756 00:41:11.800378
2757 00:41:11.800434 Set Vref, RX VrefLevel [Byte0]: 35
2758 00:41:11.800521 [Byte1]: 35
2759 00:41:11.800601
2760 00:41:11.800710 Set Vref, RX VrefLevel [Byte0]: 36
2761 00:41:11.800761 [Byte1]: 36
2762 00:41:11.800810
2763 00:41:11.800857 Set Vref, RX VrefLevel [Byte0]: 37
2764 00:41:11.800906 [Byte1]: 37
2765 00:41:11.800954
2766 00:41:11.801002 Set Vref, RX VrefLevel [Byte0]: 38
2767 00:41:11.801050 [Byte1]: 38
2768 00:41:11.801099
2769 00:41:11.801146 Set Vref, RX VrefLevel [Byte0]: 39
2770 00:41:11.801195 [Byte1]: 39
2771 00:41:11.801243
2772 00:41:11.801290 Set Vref, RX VrefLevel [Byte0]: 40
2773 00:41:11.801337 [Byte1]: 40
2774 00:41:11.801385
2775 00:41:11.801433 Set Vref, RX VrefLevel [Byte0]: 41
2776 00:41:11.801480 [Byte1]: 41
2777 00:41:11.801528
2778 00:41:11.801575 Set Vref, RX VrefLevel [Byte0]: 42
2779 00:41:11.801623 [Byte1]: 42
2780 00:41:11.801671
2781 00:41:11.801719 Set Vref, RX VrefLevel [Byte0]: 43
2782 00:41:11.801766 [Byte1]: 43
2783 00:41:11.801814
2784 00:41:11.801885 Set Vref, RX VrefLevel [Byte0]: 44
2785 00:41:11.801965 [Byte1]: 44
2786 00:41:11.802016
2787 00:41:11.802064 Set Vref, RX VrefLevel [Byte0]: 45
2788 00:41:11.802113 [Byte1]: 45
2789 00:41:11.802161
2790 00:41:11.802209 Set Vref, RX VrefLevel [Byte0]: 46
2791 00:41:11.802257 [Byte1]: 46
2792 00:41:11.802304
2793 00:41:11.802351 Set Vref, RX VrefLevel [Byte0]: 47
2794 00:41:11.802433 [Byte1]: 47
2795 00:41:11.802498
2796 00:41:11.802560 Set Vref, RX VrefLevel [Byte0]: 48
2797 00:41:11.802609 [Byte1]: 48
2798 00:41:11.802657
2799 00:41:11.802705 Set Vref, RX VrefLevel [Byte0]: 49
2800 00:41:11.802753 [Byte1]: 49
2801 00:41:11.802801
2802 00:41:11.802848 Set Vref, RX VrefLevel [Byte0]: 50
2803 00:41:11.802896 [Byte1]: 50
2804 00:41:11.802944
2805 00:41:11.802992 Set Vref, RX VrefLevel [Byte0]: 51
2806 00:41:11.803040 [Byte1]: 51
2807 00:41:11.803089
2808 00:41:11.803136 Set Vref, RX VrefLevel [Byte0]: 52
2809 00:41:11.803185 [Byte1]: 52
2810 00:41:11.803232
2811 00:41:11.803279 Set Vref, RX VrefLevel [Byte0]: 53
2812 00:41:11.803326 [Byte1]: 53
2813 00:41:11.803374
2814 00:41:11.803422 Set Vref, RX VrefLevel [Byte0]: 54
2815 00:41:11.803470 [Byte1]: 54
2816 00:41:11.803534
2817 00:41:11.803595 Set Vref, RX VrefLevel [Byte0]: 55
2818 00:41:11.803643 [Byte1]: 55
2819 00:41:11.803691
2820 00:41:11.803738 Set Vref, RX VrefLevel [Byte0]: 56
2821 00:41:11.803786 [Byte1]: 56
2822 00:41:11.803833
2823 00:41:11.804072 Set Vref, RX VrefLevel [Byte0]: 57
2824 00:41:11.804183 [Byte1]: 57
2825 00:41:11.804291
2826 00:41:11.804398 Set Vref, RX VrefLevel [Byte0]: 58
2827 00:41:11.804526 [Byte1]: 58
2828 00:41:11.804636
2829 00:41:11.804767 Set Vref, RX VrefLevel [Byte0]: 59
2830 00:41:11.804877 [Byte1]: 59
2831 00:41:11.804985
2832 00:41:11.805091 Set Vref, RX VrefLevel [Byte0]: 60
2833 00:41:11.805200 [Byte1]: 60
2834 00:41:11.805298
2835 00:41:11.805350 Set Vref, RX VrefLevel [Byte0]: 61
2836 00:41:11.805399 [Byte1]: 61
2837 00:41:11.805447
2838 00:41:11.805495 Set Vref, RX VrefLevel [Byte0]: 62
2839 00:41:11.805543 [Byte1]: 62
2840 00:41:11.805591
2841 00:41:11.805638 Set Vref, RX VrefLevel [Byte0]: 63
2842 00:41:11.805685 [Byte1]: 63
2843 00:41:11.805732
2844 00:41:11.805779 Set Vref, RX VrefLevel [Byte0]: 64
2845 00:41:11.805827 [Byte1]: 64
2846 00:41:11.805875
2847 00:41:11.805922 Set Vref, RX VrefLevel [Byte0]: 65
2848 00:41:11.805970 [Byte1]: 65
2849 00:41:11.806018
2850 00:41:11.806065 Set Vref, RX VrefLevel [Byte0]: 66
2851 00:41:11.806115 [Byte1]: 66
2852 00:41:11.806162
2853 00:41:11.806209 Set Vref, RX VrefLevel [Byte0]: 67
2854 00:41:11.806257 [Byte1]: 67
2855 00:41:11.806305
2856 00:41:11.806352 Set Vref, RX VrefLevel [Byte0]: 68
2857 00:41:11.806399 [Byte1]: 68
2858 00:41:11.806446
2859 00:41:11.806494 Set Vref, RX VrefLevel [Byte0]: 69
2860 00:41:11.806542 [Byte1]: 69
2861 00:41:11.806589
2862 00:41:11.806636 Set Vref, RX VrefLevel [Byte0]: 70
2863 00:41:11.806682 [Byte1]: 70
2864 00:41:11.806730
2865 00:41:11.806777 Set Vref, RX VrefLevel [Byte0]: 71
2866 00:41:11.806826 [Byte1]: 71
2867 00:41:11.806874
2868 00:41:11.806921 Set Vref, RX VrefLevel [Byte0]: 72
2869 00:41:11.806969 [Byte1]: 72
2870 00:41:11.807016
2871 00:41:11.807062 Set Vref, RX VrefLevel [Byte0]: 73
2872 00:41:11.807109 [Byte1]: 73
2873 00:41:11.807157
2874 00:41:11.807203 Set Vref, RX VrefLevel [Byte0]: 74
2875 00:41:11.807251 [Byte1]: 74
2876 00:41:11.807298
2877 00:41:11.807345 Set Vref, RX VrefLevel [Byte0]: 75
2878 00:41:11.807393 [Byte1]: 75
2879 00:41:11.807440
2880 00:41:11.807488 Final RX Vref Byte 0 = 62 to rank0
2881 00:41:11.807535 Final RX Vref Byte 1 = 52 to rank0
2882 00:41:11.807583 Final RX Vref Byte 0 = 62 to rank1
2883 00:41:11.807631 Final RX Vref Byte 1 = 52 to rank1==
2884 00:41:11.807679 Dram Type= 6, Freq= 0, CH_0, rank 0
2885 00:41:11.807727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 00:41:11.807776 ==
2887 00:41:11.807823 DQS Delay:
2888 00:41:11.807871 DQS0 = 0, DQS1 = 0
2889 00:41:11.807918 DQM Delay:
2890 00:41:11.807965 DQM0 = 112, DQM1 = 101
2891 00:41:11.808013 DQ Delay:
2892 00:41:11.808060 DQ0 =110, DQ1 =112, DQ2 =114, DQ3 =108
2893 00:41:11.808108 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2894 00:41:11.808156 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2895 00:41:11.808204 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2896 00:41:11.808251
2897 00:41:11.808299
2898 00:41:11.808346 [DQSOSCAuto] RK0, (LSB)MR18= 0xffff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2899 00:41:11.808395 CH0 RK0: MR19=303, MR18=FFFF
2900 00:41:11.808443 CH0_RK0: MR19=0x303, MR18=0xFFFF, DQSOSC=410, MR23=63, INC=39, DEC=26
2901 00:41:11.808491
2902 00:41:11.808538 ----->DramcWriteLeveling(PI) begin...
2903 00:41:11.808588 ==
2904 00:41:11.808660 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 00:41:11.808723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 00:41:11.808771 ==
2907 00:41:11.808819 Write leveling (Byte 0): 32 => 32
2908 00:41:11.808867 Write leveling (Byte 1): 29 => 29
2909 00:41:11.808914 DramcWriteLeveling(PI) end<-----
2910 00:41:11.808961
2911 00:41:11.809008 ==
2912 00:41:11.809056 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 00:41:11.809104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 00:41:11.809152 ==
2915 00:41:11.809199 [Gating] SW mode calibration
2916 00:41:11.809246 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2917 00:41:11.809295 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2918 00:41:11.809343 0 15 0 | B1->B0 | 2929 3434 | 0 0 | (0 0) (0 0)
2919 00:41:11.809391 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 00:41:11.809439 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 00:41:11.809487 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 00:41:11.809534 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 00:41:11.809581 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 00:41:11.809629 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
2925 00:41:11.809676 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2926 00:41:11.809724 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2927 00:41:11.809771 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 00:41:11.809819 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 00:41:11.809867 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 00:41:11.809915 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 00:41:11.809971 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 00:41:11.810027 1 0 24 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
2933 00:41:11.810075 1 0 28 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
2934 00:41:11.810123 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2935 00:41:11.810172 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 00:41:11.810220 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 00:41:11.810268 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 00:41:11.810316 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 00:41:11.810364 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 00:41:11.810412 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2941 00:41:11.810460 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2942 00:41:11.810507 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2943 00:41:11.810556 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 00:41:11.810603 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 00:41:11.810650 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 00:41:11.810892 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 00:41:11.811004 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 00:41:11.811114 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 00:41:11.811222 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 00:41:11.811331 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 00:41:11.811440 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 00:41:11.811515 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 00:41:11.811566 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 00:41:11.811614 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 00:41:11.811663 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 00:41:11.811712 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2957 00:41:11.811760 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2958 00:41:11.811809 Total UI for P1: 0, mck2ui 16
2959 00:41:11.811857 best dqsien dly found for B0: ( 1, 3, 24)
2960 00:41:11.811905 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 00:41:11.811953 Total UI for P1: 0, mck2ui 16
2962 00:41:11.812000 best dqsien dly found for B1: ( 1, 3, 28)
2963 00:41:11.812050 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2964 00:41:11.812098 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2965 00:41:11.812146
2966 00:41:11.812193 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2967 00:41:11.812241 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2968 00:41:11.812289 [Gating] SW calibration Done
2969 00:41:11.812337 ==
2970 00:41:11.812385 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 00:41:11.812433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 00:41:11.812481 ==
2973 00:41:11.812529 RX Vref Scan: 0
2974 00:41:11.812577
2975 00:41:11.812624 RX Vref 0 -> 0, step: 1
2976 00:41:11.812702
2977 00:41:11.812764 RX Delay -40 -> 252, step: 8
2978 00:41:11.812813 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2979 00:41:11.812862 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2980 00:41:11.812910 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2981 00:41:11.812957 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2982 00:41:11.813005 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
2983 00:41:11.813053 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2984 00:41:11.813115 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2985 00:41:11.813164 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2986 00:41:11.813223 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2987 00:41:11.813282 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2988 00:41:11.813331 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2989 00:41:11.813379 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2990 00:41:11.813427 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2991 00:41:11.813476 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2992 00:41:11.813524 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2993 00:41:11.813577 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2994 00:41:11.813638 ==
2995 00:41:11.813693 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 00:41:11.813742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 00:41:11.813790 ==
2998 00:41:11.813837 DQS Delay:
2999 00:41:11.813885 DQS0 = 0, DQS1 = 0
3000 00:41:11.813933 DQM Delay:
3001 00:41:11.813980 DQM0 = 111, DQM1 = 102
3002 00:41:11.926326 DQ Delay:
3003 00:41:11.926424 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3004 00:41:11.926484 DQ4 =111, DQ5 =99, DQ6 =119, DQ7 =123
3005 00:41:11.926539 DQ8 =91, DQ9 =83, DQ10 =107, DQ11 =95
3006 00:41:11.926592 DQ12 =107, DQ13 =111, DQ14 =115, DQ15 =107
3007 00:41:11.926643
3008 00:41:11.926693
3009 00:41:11.926765 ==
3010 00:41:11.926828 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 00:41:11.926876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 00:41:11.926926 ==
3013 00:41:11.926974
3014 00:41:11.927022
3015 00:41:11.927070 TX Vref Scan disable
3016 00:41:11.927119 == TX Byte 0 ==
3017 00:41:11.927167 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3018 00:41:11.927215 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3019 00:41:11.927264 == TX Byte 1 ==
3020 00:41:11.927312 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3021 00:41:11.927360 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3022 00:41:11.927408 ==
3023 00:41:11.927456 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 00:41:11.927506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 00:41:11.927554 ==
3026 00:41:11.927602 TX Vref=22, minBit 1, minWin=25, winSum=425
3027 00:41:11.927651 TX Vref=24, minBit 1, minWin=26, winSum=432
3028 00:41:11.927699 TX Vref=26, minBit 5, minWin=26, winSum=435
3029 00:41:11.927747 TX Vref=28, minBit 1, minWin=26, winSum=437
3030 00:41:11.927794 TX Vref=30, minBit 2, minWin=27, winSum=441
3031 00:41:11.927842 TX Vref=32, minBit 8, minWin=26, winSum=438
3032 00:41:11.927890 [TxChooseVref] Worse bit 2, Min win 27, Win sum 441, Final Vref 30
3033 00:41:11.927939
3034 00:41:11.927987 Final TX Range 1 Vref 30
3035 00:41:11.928035
3036 00:41:11.928082 ==
3037 00:41:11.928129 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 00:41:11.928177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 00:41:11.928224 ==
3040 00:41:11.928272
3041 00:41:11.928319
3042 00:41:11.928398 TX Vref Scan disable
3043 00:41:11.928474 == TX Byte 0 ==
3044 00:41:11.928551 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3045 00:41:11.928627 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3046 00:41:11.928693 == TX Byte 1 ==
3047 00:41:11.928743 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3048 00:41:11.928792 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3049 00:41:11.928841
3050 00:41:11.928889 [DATLAT]
3051 00:41:11.928937 Freq=1200, CH0 RK1
3052 00:41:11.928986
3053 00:41:11.929034 DATLAT Default: 0xd
3054 00:41:11.929082 0, 0xFFFF, sum = 0
3055 00:41:11.929131 1, 0xFFFF, sum = 0
3056 00:41:11.929180 2, 0xFFFF, sum = 0
3057 00:41:11.929236 3, 0xFFFF, sum = 0
3058 00:41:11.929318 4, 0xFFFF, sum = 0
3059 00:41:11.929399 5, 0xFFFF, sum = 0
3060 00:41:11.929477 6, 0xFFFF, sum = 0
3061 00:41:11.929529 7, 0xFFFF, sum = 0
3062 00:41:11.929578 8, 0xFFFF, sum = 0
3063 00:41:11.929628 9, 0xFFFF, sum = 0
3064 00:41:11.929677 10, 0xFFFF, sum = 0
3065 00:41:11.929727 11, 0xFFFF, sum = 0
3066 00:41:11.929776 12, 0x0, sum = 1
3067 00:41:11.929824 13, 0x0, sum = 2
3068 00:41:11.929874 14, 0x0, sum = 3
3069 00:41:11.929923 15, 0x0, sum = 4
3070 00:41:11.929971 best_step = 13
3071 00:41:11.930019
3072 00:41:11.930068 ==
3073 00:41:11.930116 Dram Type= 6, Freq= 0, CH_0, rank 1
3074 00:41:11.930164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 00:41:11.930212 ==
3076 00:41:11.930260 RX Vref Scan: 0
3077 00:41:11.930307
3078 00:41:11.930356 RX Vref 0 -> 0, step: 1
3079 00:41:11.930403
3080 00:41:11.930450 RX Delay -37 -> 252, step: 4
3081 00:41:11.930497 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3082 00:41:11.930545 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3083 00:41:11.930593 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3084 00:41:11.930843 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3085 00:41:11.930900 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3086 00:41:11.930950 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3087 00:41:11.930998 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3088 00:41:11.931046 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3089 00:41:11.931095 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3090 00:41:11.931143 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3091 00:41:11.931191 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3092 00:41:11.931238 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3093 00:41:11.931286 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3094 00:41:11.931333 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3095 00:41:11.931381 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3096 00:41:11.931428 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3097 00:41:11.931475 ==
3098 00:41:11.931523 Dram Type= 6, Freq= 0, CH_0, rank 1
3099 00:41:11.931571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 00:41:11.931619 ==
3101 00:41:11.931666 DQS Delay:
3102 00:41:11.931713 DQS0 = 0, DQS1 = 0
3103 00:41:11.931762 DQM Delay:
3104 00:41:11.931809 DQM0 = 111, DQM1 = 100
3105 00:41:11.931857 DQ Delay:
3106 00:41:11.931904 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3107 00:41:11.931952 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3108 00:41:11.931999 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =92
3109 00:41:11.932046 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =108
3110 00:41:11.932094
3111 00:41:11.932142
3112 00:41:11.932190 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3113 00:41:11.932239 CH0 RK1: MR19=403, MR18=13FB
3114 00:41:11.932287 CH0_RK1: MR19=0x403, MR18=0x13FB, DQSOSC=402, MR23=63, INC=40, DEC=27
3115 00:41:11.932335 [RxdqsGatingPostProcess] freq 1200
3116 00:41:11.932383 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3117 00:41:11.932432 best DQS0 dly(2T, 0.5T) = (0, 11)
3118 00:41:11.932480 best DQS1 dly(2T, 0.5T) = (0, 12)
3119 00:41:11.932528 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3120 00:41:11.932575 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3121 00:41:11.932623 best DQS0 dly(2T, 0.5T) = (0, 11)
3122 00:41:11.932710 best DQS1 dly(2T, 0.5T) = (0, 11)
3123 00:41:11.932759 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3124 00:41:11.932806 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3125 00:41:11.932854 Pre-setting of DQS Precalculation
3126 00:41:11.932902 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3127 00:41:11.932950 ==
3128 00:41:11.932998 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 00:41:11.933045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 00:41:11.933093 ==
3131 00:41:11.933141 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3132 00:41:11.933189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3133 00:41:11.933237 [CA 0] Center 37 (7~67) winsize 61
3134 00:41:11.933284 [CA 1] Center 37 (7~68) winsize 62
3135 00:41:11.933331 [CA 2] Center 34 (4~64) winsize 61
3136 00:41:11.933378 [CA 3] Center 34 (4~64) winsize 61
3137 00:41:11.933426 [CA 4] Center 34 (4~64) winsize 61
3138 00:41:11.933494 [CA 5] Center 33 (3~63) winsize 61
3139 00:41:11.933544
3140 00:41:11.933592 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3141 00:41:11.933641
3142 00:41:11.933688 [CATrainingPosCal] consider 1 rank data
3143 00:41:11.933736 u2DelayCellTimex100 = 270/100 ps
3144 00:41:11.933784 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3145 00:41:11.933833 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3146 00:41:11.933881 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3147 00:41:11.933928 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3148 00:41:11.933976 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3149 00:41:11.934023 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3150 00:41:11.934071
3151 00:41:11.934119 CA PerBit enable=1, Macro0, CA PI delay=33
3152 00:41:11.934168
3153 00:41:11.934215 [CBTSetCACLKResult] CA Dly = 33
3154 00:41:11.934263 CS Dly: 6 (0~37)
3155 00:41:11.934311 ==
3156 00:41:11.934360 Dram Type= 6, Freq= 0, CH_1, rank 1
3157 00:41:11.934409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3158 00:41:11.934458 ==
3159 00:41:11.934506 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3160 00:41:11.934555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3161 00:41:11.934603 [CA 0] Center 37 (8~67) winsize 60
3162 00:41:11.934651 [CA 1] Center 37 (7~68) winsize 62
3163 00:41:11.934699 [CA 2] Center 34 (4~65) winsize 62
3164 00:41:11.934747 [CA 3] Center 33 (3~64) winsize 62
3165 00:41:11.934796 [CA 4] Center 34 (4~65) winsize 62
3166 00:41:11.934844 [CA 5] Center 32 (2~63) winsize 62
3167 00:41:11.934891
3168 00:41:11.934939 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3169 00:41:11.934987
3170 00:41:11.935035 [CATrainingPosCal] consider 2 rank data
3171 00:41:11.935083 u2DelayCellTimex100 = 270/100 ps
3172 00:41:11.935131 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3173 00:41:11.935179 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3174 00:41:11.935228 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3175 00:41:11.935276 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3176 00:41:11.935324 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3177 00:41:11.935372 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3178 00:41:11.935420
3179 00:41:11.935468 CA PerBit enable=1, Macro0, CA PI delay=33
3180 00:41:11.935516
3181 00:41:11.935564 [CBTSetCACLKResult] CA Dly = 33
3182 00:41:11.935612 CS Dly: 7 (0~39)
3183 00:41:11.935659
3184 00:41:11.935707 ----->DramcWriteLeveling(PI) begin...
3185 00:41:11.935756 ==
3186 00:41:11.935804 Dram Type= 6, Freq= 0, CH_1, rank 0
3187 00:41:11.935853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3188 00:41:11.935902 ==
3189 00:41:11.935951 Write leveling (Byte 0): 25 => 25
3190 00:41:11.935999 Write leveling (Byte 1): 29 => 29
3191 00:41:11.936047 DramcWriteLeveling(PI) end<-----
3192 00:41:11.936094
3193 00:41:11.936142 ==
3194 00:41:11.936190 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 00:41:11.936239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 00:41:11.936288 ==
3197 00:41:11.936336 [Gating] SW mode calibration
3198 00:41:11.936385 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3199 00:41:11.936435 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3200 00:41:11.936483 0 15 0 | B1->B0 | 2f2f 2828 | 0 0 | (0 0) (0 0)
3201 00:41:11.936532 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 00:41:11.936581 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 00:41:11.936824 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 00:41:11.936937 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 00:41:11.937048 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 00:41:11.937158 0 15 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
3207 00:41:11.937268 0 15 28 | B1->B0 | 2e2e 2d2d | 1 1 | (0 0) (0 0)
3208 00:41:11.937377 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3209 00:41:11.937486 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 00:41:11.937580 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 00:41:11.937633 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 00:41:11.937683 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 00:41:11.937732 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 00:41:11.937781 1 0 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3215 00:41:11.937831 1 0 28 | B1->B0 | 3d3d 3e3e | 0 1 | (0 0) (0 0)
3216 00:41:11.937879 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3217 00:41:11.937928 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 00:41:11.937976 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 00:41:11.938025 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 00:41:11.938073 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 00:41:11.938122 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 00:41:11.938171 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 00:41:11.938220 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3224 00:41:11.938270 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 00:41:11.938319 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 00:41:11.938385 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 00:41:11.938447 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 00:41:11.938496 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 00:41:11.938546 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 00:41:11.938594 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 00:41:11.938643 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 00:41:11.938691 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 00:41:11.938740 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 00:41:11.938788 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 00:41:11.938836 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 00:41:11.938885 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 00:41:11.938934 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 00:41:11.938983 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 00:41:11.939031 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3240 00:41:11.939084 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3241 00:41:11.939158 Total UI for P1: 0, mck2ui 16
3242 00:41:11.939209 best dqsien dly found for B1: ( 1, 3, 28)
3243 00:41:11.939259 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 00:41:11.939308 Total UI for P1: 0, mck2ui 16
3245 00:41:11.939357 best dqsien dly found for B0: ( 1, 3, 30)
3246 00:41:11.939406 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3247 00:41:11.939455 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3248 00:41:11.939504
3249 00:41:11.939552 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3250 00:41:11.939601 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3251 00:41:11.939649 [Gating] SW calibration Done
3252 00:41:11.939697 ==
3253 00:41:11.939746 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 00:41:11.939795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 00:41:11.939843 ==
3256 00:41:11.939892 RX Vref Scan: 0
3257 00:41:11.939941
3258 00:41:11.939989 RX Vref 0 -> 0, step: 1
3259 00:41:11.940037
3260 00:41:11.940085 RX Delay -40 -> 252, step: 8
3261 00:41:11.940133 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3262 00:41:11.940182 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3263 00:41:11.940230 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3264 00:41:11.940278 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3265 00:41:11.940327 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3266 00:41:11.940375 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3267 00:41:11.940454 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3268 00:41:11.940501 iDelay=200, Bit 7, Center 111 (32 ~ 191) 160
3269 00:41:11.940549 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3270 00:41:11.940598 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3271 00:41:11.940666 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3272 00:41:11.940731 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3273 00:41:11.940780 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3274 00:41:11.940828 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3275 00:41:11.940876 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3276 00:41:11.940924 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3277 00:41:11.940972 ==
3278 00:41:11.941021 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 00:41:11.941069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 00:41:11.941118 ==
3281 00:41:11.941167 DQS Delay:
3282 00:41:11.941215 DQS0 = 0, DQS1 = 0
3283 00:41:11.941263 DQM Delay:
3284 00:41:11.941310 DQM0 = 114, DQM1 = 107
3285 00:41:11.941359 DQ Delay:
3286 00:41:11.941407 DQ0 =123, DQ1 =107, DQ2 =103, DQ3 =111
3287 00:41:11.941456 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3288 00:41:11.941504 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =103
3289 00:41:11.941552 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3290 00:41:11.941600
3291 00:41:11.941648
3292 00:41:11.941695 ==
3293 00:41:11.941743 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 00:41:11.941792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 00:41:11.941841 ==
3296 00:41:11.941889
3297 00:41:11.941936
3298 00:41:11.941984 TX Vref Scan disable
3299 00:41:11.942033 == TX Byte 0 ==
3300 00:41:11.942081 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3301 00:41:11.942130 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3302 00:41:11.942178 == TX Byte 1 ==
3303 00:41:11.942226 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3304 00:41:11.942274 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3305 00:41:11.942323 ==
3306 00:41:11.942371 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 00:41:11.942419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 00:41:11.942484 ==
3309 00:41:11.942542 TX Vref=22, minBit 11, minWin=24, winSum=412
3310 00:41:11.942779 TX Vref=24, minBit 8, minWin=24, winSum=414
3311 00:41:11.942834 TX Vref=26, minBit 8, minWin=25, winSum=423
3312 00:41:11.942884 TX Vref=28, minBit 9, minWin=25, winSum=422
3313 00:41:11.942933 TX Vref=30, minBit 9, minWin=25, winSum=428
3314 00:41:11.942983 TX Vref=32, minBit 9, minWin=25, winSum=421
3315 00:41:11.943032 [TxChooseVref] Worse bit 9, Min win 25, Win sum 428, Final Vref 30
3316 00:41:11.943082
3317 00:41:11.943130 Final TX Range 1 Vref 30
3318 00:41:11.943179
3319 00:41:11.943227 ==
3320 00:41:11.943276 Dram Type= 6, Freq= 0, CH_1, rank 0
3321 00:41:11.943324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3322 00:41:11.943373 ==
3323 00:41:11.943421
3324 00:41:11.943468
3325 00:41:11.943517 TX Vref Scan disable
3326 00:41:11.943565 == TX Byte 0 ==
3327 00:41:11.943615 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3328 00:41:11.943664 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3329 00:41:11.943712 == TX Byte 1 ==
3330 00:41:11.943760 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3331 00:41:11.943808 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3332 00:41:11.943856
3333 00:41:11.943904 [DATLAT]
3334 00:41:11.943953 Freq=1200, CH1 RK0
3335 00:41:11.944001
3336 00:41:11.944049 DATLAT Default: 0xd
3337 00:41:11.944097 0, 0xFFFF, sum = 0
3338 00:41:11.944146 1, 0xFFFF, sum = 0
3339 00:41:11.944195 2, 0xFFFF, sum = 0
3340 00:41:11.944244 3, 0xFFFF, sum = 0
3341 00:41:11.944293 4, 0xFFFF, sum = 0
3342 00:41:11.944341 5, 0xFFFF, sum = 0
3343 00:41:11.944390 6, 0xFFFF, sum = 0
3344 00:41:11.944439 7, 0xFFFF, sum = 0
3345 00:41:11.944488 8, 0xFFFF, sum = 0
3346 00:41:11.944537 9, 0xFFFF, sum = 0
3347 00:41:11.944587 10, 0xFFFF, sum = 0
3348 00:41:11.944635 11, 0xFFFF, sum = 0
3349 00:41:11.944721 12, 0x0, sum = 1
3350 00:41:11.944771 13, 0x0, sum = 2
3351 00:41:11.944820 14, 0x0, sum = 3
3352 00:41:11.944868 15, 0x0, sum = 4
3353 00:41:11.944917 best_step = 13
3354 00:41:11.944965
3355 00:41:11.945014 ==
3356 00:41:11.945062 Dram Type= 6, Freq= 0, CH_1, rank 0
3357 00:41:11.945111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3358 00:41:11.945160 ==
3359 00:41:11.945208 RX Vref Scan: 1
3360 00:41:11.945257
3361 00:41:11.945305 Set Vref Range= 32 -> 127
3362 00:41:11.945352
3363 00:41:11.945400 RX Vref 32 -> 127, step: 1
3364 00:41:11.945449
3365 00:41:11.945496 RX Delay -21 -> 252, step: 4
3366 00:41:11.945543
3367 00:41:11.945590 Set Vref, RX VrefLevel [Byte0]: 32
3368 00:41:11.945637 [Byte1]: 32
3369 00:41:11.945685
3370 00:41:11.945733 Set Vref, RX VrefLevel [Byte0]: 33
3371 00:41:11.945781 [Byte1]: 33
3372 00:41:11.945836
3373 00:41:11.945902 Set Vref, RX VrefLevel [Byte0]: 34
3374 00:41:11.945952 [Byte1]: 34
3375 00:41:11.946000
3376 00:41:11.946048 Set Vref, RX VrefLevel [Byte0]: 35
3377 00:41:11.946096 [Byte1]: 35
3378 00:41:11.946145
3379 00:41:11.946193 Set Vref, RX VrefLevel [Byte0]: 36
3380 00:41:11.946241 [Byte1]: 36
3381 00:41:11.946288
3382 00:41:11.946336 Set Vref, RX VrefLevel [Byte0]: 37
3383 00:41:11.946383 [Byte1]: 37
3384 00:41:11.946432
3385 00:41:11.946479 Set Vref, RX VrefLevel [Byte0]: 38
3386 00:41:11.946526 [Byte1]: 38
3387 00:41:11.946574
3388 00:41:11.946622 Set Vref, RX VrefLevel [Byte0]: 39
3389 00:41:11.946670 [Byte1]: 39
3390 00:41:11.946718
3391 00:41:11.946765 Set Vref, RX VrefLevel [Byte0]: 40
3392 00:41:11.946813 [Byte1]: 40
3393 00:41:11.946861
3394 00:41:11.946908 Set Vref, RX VrefLevel [Byte0]: 41
3395 00:41:11.946955 [Byte1]: 41
3396 00:41:11.947003
3397 00:41:11.947050 Set Vref, RX VrefLevel [Byte0]: 42
3398 00:41:11.947098 [Byte1]: 42
3399 00:41:11.947146
3400 00:41:11.947193 Set Vref, RX VrefLevel [Byte0]: 43
3401 00:41:11.947242 [Byte1]: 43
3402 00:41:11.947289
3403 00:41:11.947337 Set Vref, RX VrefLevel [Byte0]: 44
3404 00:41:11.947386 [Byte1]: 44
3405 00:41:11.947434
3406 00:41:11.947481 Set Vref, RX VrefLevel [Byte0]: 45
3407 00:41:11.947529 [Byte1]: 45
3408 00:41:11.947577
3409 00:41:11.947624 Set Vref, RX VrefLevel [Byte0]: 46
3410 00:41:11.947671 [Byte1]: 46
3411 00:41:11.947719
3412 00:41:11.947766 Set Vref, RX VrefLevel [Byte0]: 47
3413 00:41:11.947813 [Byte1]: 47
3414 00:41:11.947860
3415 00:41:11.947908 Set Vref, RX VrefLevel [Byte0]: 48
3416 00:41:11.947956 [Byte1]: 48
3417 00:41:11.948003
3418 00:41:11.948051 Set Vref, RX VrefLevel [Byte0]: 49
3419 00:41:11.948098 [Byte1]: 49
3420 00:41:11.948146
3421 00:41:11.948193 Set Vref, RX VrefLevel [Byte0]: 50
3422 00:41:11.948240 [Byte1]: 50
3423 00:41:11.948287
3424 00:41:11.948335 Set Vref, RX VrefLevel [Byte0]: 51
3425 00:41:11.948383 [Byte1]: 51
3426 00:41:11.948430
3427 00:41:11.948477 Set Vref, RX VrefLevel [Byte0]: 52
3428 00:41:11.948525 [Byte1]: 52
3429 00:41:11.948572
3430 00:41:11.948620 Set Vref, RX VrefLevel [Byte0]: 53
3431 00:41:11.948675 [Byte1]: 53
3432 00:41:11.948723
3433 00:41:11.948771 Set Vref, RX VrefLevel [Byte0]: 54
3434 00:41:11.948819 [Byte1]: 54
3435 00:41:11.948866
3436 00:41:11.948913 Set Vref, RX VrefLevel [Byte0]: 55
3437 00:41:11.948960 [Byte1]: 55
3438 00:41:11.949007
3439 00:41:11.949056 Set Vref, RX VrefLevel [Byte0]: 56
3440 00:41:11.949129 [Byte1]: 56
3441 00:41:11.949183
3442 00:41:11.949231 Set Vref, RX VrefLevel [Byte0]: 57
3443 00:41:11.949279 [Byte1]: 57
3444 00:41:11.949326
3445 00:41:11.949374 Set Vref, RX VrefLevel [Byte0]: 58
3446 00:41:11.949422 [Byte1]: 58
3447 00:41:11.949470
3448 00:41:11.949519 Set Vref, RX VrefLevel [Byte0]: 59
3449 00:41:11.949566 [Byte1]: 59
3450 00:41:11.949614
3451 00:41:11.949662 Set Vref, RX VrefLevel [Byte0]: 60
3452 00:41:11.949710 [Byte1]: 60
3453 00:41:11.949758
3454 00:41:11.949805 Set Vref, RX VrefLevel [Byte0]: 61
3455 00:41:11.949852 [Byte1]: 61
3456 00:41:11.949900
3457 00:41:11.949948 Set Vref, RX VrefLevel [Byte0]: 62
3458 00:41:11.949995 [Byte1]: 62
3459 00:41:11.950043
3460 00:41:11.950090 Set Vref, RX VrefLevel [Byte0]: 63
3461 00:41:11.950138 [Byte1]: 63
3462 00:41:11.950185
3463 00:41:11.950232 Set Vref, RX VrefLevel [Byte0]: 64
3464 00:41:11.950280 [Byte1]: 64
3465 00:41:11.950327
3466 00:41:11.950385 Set Vref, RX VrefLevel [Byte0]: 65
3467 00:41:11.950435 [Byte1]: 65
3468 00:41:11.950483
3469 00:41:11.950531 Final RX Vref Byte 0 = 54 to rank0
3470 00:41:11.950580 Final RX Vref Byte 1 = 54 to rank0
3471 00:41:11.950628 Final RX Vref Byte 0 = 54 to rank1
3472 00:41:11.950677 Final RX Vref Byte 1 = 54 to rank1==
3473 00:41:11.950725 Dram Type= 6, Freq= 0, CH_1, rank 0
3474 00:41:11.950773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 00:41:11.950822 ==
3476 00:41:11.950870 DQS Delay:
3477 00:41:11.951108 DQS0 = 0, DQS1 = 0
3478 00:41:11.951164 DQM Delay:
3479 00:41:11.951214 DQM0 = 113, DQM1 = 107
3480 00:41:11.951262 DQ Delay:
3481 00:41:11.951311 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =110
3482 00:41:11.951360 DQ4 =108, DQ5 =122, DQ6 =124, DQ7 =112
3483 00:41:11.951409 DQ8 =92, DQ9 =96, DQ10 =106, DQ11 =100
3484 00:41:11.951458 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3485 00:41:11.951506
3486 00:41:11.951554
3487 00:41:11.951602 [DQSOSCAuto] RK0, (LSB)MR18= 0xeff6, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3488 00:41:11.951653 CH1 RK0: MR19=303, MR18=EFF6
3489 00:41:11.951702 CH1_RK0: MR19=0x303, MR18=0xEFF6, DQSOSC=414, MR23=63, INC=38, DEC=25
3490 00:41:11.951750
3491 00:41:11.951797 ----->DramcWriteLeveling(PI) begin...
3492 00:41:11.951846 ==
3493 00:41:11.951894 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 00:41:11.951943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 00:41:11.951992 ==
3496 00:41:11.952040 Write leveling (Byte 0): 23 => 23
3497 00:41:11.952088 Write leveling (Byte 1): 28 => 28
3498 00:41:11.952136 DramcWriteLeveling(PI) end<-----
3499 00:41:11.952184
3500 00:41:11.952231 ==
3501 00:41:11.952279 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 00:41:11.952327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 00:41:11.952413 ==
3504 00:41:11.952460 [Gating] SW mode calibration
3505 00:41:11.952508 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3506 00:41:11.952556 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3507 00:41:11.952614 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 00:41:11.952713 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 00:41:11.952763 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 00:41:11.952812 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 00:41:11.952860 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 00:41:11.952908 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3513 00:41:11.952956 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
3514 00:41:11.953004 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3515 00:41:11.953053 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 00:41:11.953100 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 00:41:11.953148 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 00:41:11.953196 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 00:41:11.953244 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 00:41:11.953292 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3521 00:41:11.953340 1 0 24 | B1->B0 | 2a2a 4444 | 0 0 | (0 0) (0 0)
3522 00:41:11.953388 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3523 00:41:11.953437 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 00:41:11.953487 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 00:41:11.953535 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 00:41:11.953583 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 00:41:11.953631 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 00:41:11.953680 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3529 00:41:11.953728 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3530 00:41:11.953776 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3531 00:41:11.953824 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 00:41:11.953873 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 00:41:11.953921 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 00:41:11.953968 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 00:41:11.954016 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 00:41:11.954063 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 00:41:11.954112 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 00:41:11.954160 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 00:41:11.954208 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 00:41:11.954255 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 00:41:11.954303 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 00:41:11.954351 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 00:41:11.954398 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 00:41:11.954447 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3545 00:41:11.954495 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3546 00:41:11.954543 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3547 00:41:11.954591 Total UI for P1: 0, mck2ui 16
3548 00:41:11.954640 best dqsien dly found for B0: ( 1, 3, 22)
3549 00:41:11.954688 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 00:41:11.954736 Total UI for P1: 0, mck2ui 16
3551 00:41:11.954784 best dqsien dly found for B1: ( 1, 3, 26)
3552 00:41:11.954832 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3553 00:41:11.954881 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3554 00:41:11.954929
3555 00:41:11.954977 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3556 00:41:11.955025 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3557 00:41:11.955073 [Gating] SW calibration Done
3558 00:41:11.955120 ==
3559 00:41:11.955169 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 00:41:11.955216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 00:41:11.955264 ==
3562 00:41:11.955312 RX Vref Scan: 0
3563 00:41:11.955360
3564 00:41:11.955407 RX Vref 0 -> 0, step: 1
3565 00:41:11.955455
3566 00:41:11.955503 RX Delay -40 -> 252, step: 8
3567 00:41:11.955554 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3568 00:41:11.955627 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3569 00:41:11.955677 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3570 00:41:11.955726 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3571 00:41:11.955775 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3572 00:41:11.955823 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3573 00:41:11.955871 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3574 00:41:11.955919 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3575 00:41:11.955967 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3576 00:41:11.956015 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3577 00:41:11.956063 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3578 00:41:11.956110 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3579 00:41:11.956365 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3580 00:41:11.956435 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3581 00:41:11.956484 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3582 00:41:11.956532 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3583 00:41:11.956580 ==
3584 00:41:11.956628 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 00:41:11.956712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 00:41:11.956760 ==
3587 00:41:11.956808 DQS Delay:
3588 00:41:11.956856 DQS0 = 0, DQS1 = 0
3589 00:41:11.956903 DQM Delay:
3590 00:41:11.956951 DQM0 = 110, DQM1 = 109
3591 00:41:11.956998 DQ Delay:
3592 00:41:11.957045 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3593 00:41:11.957094 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3594 00:41:11.957141 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3595 00:41:11.957188 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =115
3596 00:41:11.957236
3597 00:41:11.957283
3598 00:41:11.957330 ==
3599 00:41:11.957378 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 00:41:11.957426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 00:41:11.957474 ==
3602 00:41:11.957520
3603 00:41:11.957568
3604 00:41:11.957614 TX Vref Scan disable
3605 00:41:11.957661 == TX Byte 0 ==
3606 00:41:11.957708 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3607 00:41:11.957757 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3608 00:41:11.957805 == TX Byte 1 ==
3609 00:41:11.957853 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3610 00:41:11.957900 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3611 00:41:11.957948 ==
3612 00:41:11.957995 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 00:41:11.958044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 00:41:11.958091 ==
3615 00:41:11.958138 TX Vref=22, minBit 9, minWin=25, winSum=422
3616 00:41:11.958186 TX Vref=24, minBit 9, minWin=25, winSum=426
3617 00:41:11.958234 TX Vref=26, minBit 0, minWin=26, winSum=434
3618 00:41:11.958282 TX Vref=28, minBit 0, minWin=26, winSum=430
3619 00:41:11.958330 TX Vref=30, minBit 1, minWin=26, winSum=434
3620 00:41:11.958428 TX Vref=32, minBit 8, minWin=25, winSum=429
3621 00:41:11.958501 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 26
3622 00:41:11.958570
3623 00:41:11.958620 Final TX Range 1 Vref 26
3624 00:41:11.958669
3625 00:41:11.958716 ==
3626 00:41:11.958764 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 00:41:11.958813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 00:41:11.958861 ==
3629 00:41:11.958934
3630 00:41:11.958986
3631 00:41:11.959035 TX Vref Scan disable
3632 00:41:11.959084 == TX Byte 0 ==
3633 00:41:11.959132 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3634 00:41:11.959181 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3635 00:41:11.959229 == TX Byte 1 ==
3636 00:41:11.959277 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3637 00:41:11.959325 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3638 00:41:11.959373
3639 00:41:11.959420 [DATLAT]
3640 00:41:11.959469 Freq=1200, CH1 RK1
3641 00:41:11.959518
3642 00:41:11.959566 DATLAT Default: 0xd
3643 00:41:11.959614 0, 0xFFFF, sum = 0
3644 00:41:11.959663 1, 0xFFFF, sum = 0
3645 00:41:11.959711 2, 0xFFFF, sum = 0
3646 00:41:11.959759 3, 0xFFFF, sum = 0
3647 00:41:11.959807 4, 0xFFFF, sum = 0
3648 00:41:11.959855 5, 0xFFFF, sum = 0
3649 00:41:11.959904 6, 0xFFFF, sum = 0
3650 00:41:11.959952 7, 0xFFFF, sum = 0
3651 00:41:11.960001 8, 0xFFFF, sum = 0
3652 00:41:11.960049 9, 0xFFFF, sum = 0
3653 00:41:11.960098 10, 0xFFFF, sum = 0
3654 00:41:11.960145 11, 0xFFFF, sum = 0
3655 00:41:11.960194 12, 0x0, sum = 1
3656 00:41:11.960242 13, 0x0, sum = 2
3657 00:41:11.960291 14, 0x0, sum = 3
3658 00:41:11.960340 15, 0x0, sum = 4
3659 00:41:11.960388 best_step = 13
3660 00:41:11.960436
3661 00:41:11.960483 ==
3662 00:41:11.960531 Dram Type= 6, Freq= 0, CH_1, rank 1
3663 00:41:11.960579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3664 00:41:11.960627 ==
3665 00:41:11.960703 RX Vref Scan: 0
3666 00:41:11.960765
3667 00:41:11.960812 RX Vref 0 -> 0, step: 1
3668 00:41:11.960859
3669 00:41:11.960907 RX Delay -21 -> 252, step: 4
3670 00:41:11.960954 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3671 00:41:11.961002 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3672 00:41:11.961050 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3673 00:41:11.961097 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3674 00:41:11.961144 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3675 00:41:11.961192 iDelay=195, Bit 5, Center 118 (47 ~ 190) 144
3676 00:41:11.961239 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3677 00:41:11.961287 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3678 00:41:11.961334 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3679 00:41:11.961382 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3680 00:41:11.961430 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3681 00:41:11.961477 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3682 00:41:11.961525 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3683 00:41:11.961573 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3684 00:41:11.961621 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3685 00:41:11.961668 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3686 00:41:11.961715 ==
3687 00:41:11.961762 Dram Type= 6, Freq= 0, CH_1, rank 1
3688 00:41:11.961810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3689 00:41:11.961858 ==
3690 00:41:11.961905 DQS Delay:
3691 00:41:11.961952 DQS0 = 0, DQS1 = 0
3692 00:41:11.962001 DQM Delay:
3693 00:41:11.962049 DQM0 = 111, DQM1 = 110
3694 00:41:11.962097 DQ Delay:
3695 00:41:11.962153 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3696 00:41:11.962220 DQ4 =110, DQ5 =118, DQ6 =120, DQ7 =110
3697 00:41:11.962270 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =106
3698 00:41:11.962319 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3699 00:41:11.962367
3700 00:41:11.962415
3701 00:41:11.962463 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc0b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3702 00:41:11.962513 CH1 RK1: MR19=304, MR18=FC0B
3703 00:41:11.962561 CH1_RK1: MR19=0x304, MR18=0xFC0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3704 00:41:11.962610 [RxdqsGatingPostProcess] freq 1200
3705 00:41:11.962659 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3706 00:41:11.962707 best DQS0 dly(2T, 0.5T) = (0, 11)
3707 00:41:11.962755 best DQS1 dly(2T, 0.5T) = (0, 11)
3708 00:41:11.962803 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3709 00:41:11.962851 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3710 00:41:11.962899 best DQS0 dly(2T, 0.5T) = (0, 11)
3711 00:41:11.962947 best DQS1 dly(2T, 0.5T) = (0, 11)
3712 00:41:11.962995 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3713 00:41:11.963043 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3714 00:41:11.963091 Pre-setting of DQS Precalculation
3715 00:41:11.963138 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3716 00:41:11.963187 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3717 00:41:11.963423 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3718 00:41:11.963478
3719 00:41:11.963527
3720 00:41:11.963576 [Calibration Summary] 2400 Mbps
3721 00:41:11.963625 CH 0, Rank 0
3722 00:41:11.963673 SW Impedance : PASS
3723 00:41:11.963721 DUTY Scan : NO K
3724 00:41:11.963769 ZQ Calibration : PASS
3725 00:41:11.963816 Jitter Meter : NO K
3726 00:41:11.963865 CBT Training : PASS
3727 00:41:11.963913 Write leveling : PASS
3728 00:41:11.963961 RX DQS gating : PASS
3729 00:41:11.964010 RX DQ/DQS(RDDQC) : PASS
3730 00:41:11.964058 TX DQ/DQS : PASS
3731 00:41:11.964105 RX DATLAT : PASS
3732 00:41:11.964153 RX DQ/DQS(Engine): PASS
3733 00:41:11.964201 TX OE : NO K
3734 00:41:11.964248 All Pass.
3735 00:41:11.964295
3736 00:41:11.964342 CH 0, Rank 1
3737 00:41:11.964390 SW Impedance : PASS
3738 00:41:11.964438 DUTY Scan : NO K
3739 00:41:11.964486 ZQ Calibration : PASS
3740 00:41:11.964533 Jitter Meter : NO K
3741 00:41:11.964581 CBT Training : PASS
3742 00:41:11.964629 Write leveling : PASS
3743 00:41:11.964716 RX DQS gating : PASS
3744 00:41:11.964763 RX DQ/DQS(RDDQC) : PASS
3745 00:41:11.964811 TX DQ/DQS : PASS
3746 00:41:11.964859 RX DATLAT : PASS
3747 00:41:11.964907 RX DQ/DQS(Engine): PASS
3748 00:41:11.964954 TX OE : NO K
3749 00:41:11.965001 All Pass.
3750 00:41:11.965048
3751 00:41:11.965095 CH 1, Rank 0
3752 00:41:11.965143 SW Impedance : PASS
3753 00:41:11.965190 DUTY Scan : NO K
3754 00:41:11.965237 ZQ Calibration : PASS
3755 00:41:11.965284 Jitter Meter : NO K
3756 00:41:11.965331 CBT Training : PASS
3757 00:41:11.965379 Write leveling : PASS
3758 00:41:11.965426 RX DQS gating : PASS
3759 00:41:11.965473 RX DQ/DQS(RDDQC) : PASS
3760 00:41:11.965521 TX DQ/DQS : PASS
3761 00:41:11.965598 RX DATLAT : PASS
3762 00:41:11.965648 RX DQ/DQS(Engine): PASS
3763 00:41:11.965696 TX OE : NO K
3764 00:41:11.965745 All Pass.
3765 00:41:11.965793
3766 00:41:11.965841 CH 1, Rank 1
3767 00:41:11.965889 SW Impedance : PASS
3768 00:41:11.965937 DUTY Scan : NO K
3769 00:41:11.965985 ZQ Calibration : PASS
3770 00:41:11.966033 Jitter Meter : NO K
3771 00:41:11.966081 CBT Training : PASS
3772 00:41:11.966129 Write leveling : PASS
3773 00:41:11.966176 RX DQS gating : PASS
3774 00:41:11.966223 RX DQ/DQS(RDDQC) : PASS
3775 00:41:11.966271 TX DQ/DQS : PASS
3776 00:41:11.966320 RX DATLAT : PASS
3777 00:41:11.966368 RX DQ/DQS(Engine): PASS
3778 00:41:11.966416 TX OE : NO K
3779 00:41:11.966464 All Pass.
3780 00:41:11.966511
3781 00:41:11.966559 DramC Write-DBI off
3782 00:41:11.966606 PER_BANK_REFRESH: Hybrid Mode
3783 00:41:11.966653 TX_TRACKING: ON
3784 00:41:11.966701 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3785 00:41:11.966751 [FAST_K] Save calibration result to emmc
3786 00:41:11.966799 dramc_set_vcore_voltage set vcore to 650000
3787 00:41:11.966847 Read voltage for 600, 5
3788 00:41:11.966894 Vio18 = 0
3789 00:41:11.966942 Vcore = 650000
3790 00:41:11.966990 Vdram = 0
3791 00:41:11.967038 Vddq = 0
3792 00:41:11.967085 Vmddr = 0
3793 00:41:11.967133 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3794 00:41:11.967182 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3795 00:41:11.967230 MEM_TYPE=3, freq_sel=19
3796 00:41:11.967279 sv_algorithm_assistance_LP4_1600
3797 00:41:11.967327 ============ PULL DRAM RESETB DOWN ============
3798 00:41:11.967375 ========== PULL DRAM RESETB DOWN end =========
3799 00:41:11.967424 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3800 00:41:11.967472 ===================================
3801 00:41:11.967520 LPDDR4 DRAM CONFIGURATION
3802 00:41:11.967567 ===================================
3803 00:41:11.967616 EX_ROW_EN[0] = 0x0
3804 00:41:11.967665 EX_ROW_EN[1] = 0x0
3805 00:41:11.967713 LP4Y_EN = 0x0
3806 00:41:11.967761 WORK_FSP = 0x0
3807 00:41:11.967809 WL = 0x2
3808 00:41:11.967857 RL = 0x2
3809 00:41:11.967905 BL = 0x2
3810 00:41:11.967952 RPST = 0x0
3811 00:41:11.968000 RD_PRE = 0x0
3812 00:41:11.968047 WR_PRE = 0x1
3813 00:41:11.968095 WR_PST = 0x0
3814 00:41:11.968143 DBI_WR = 0x0
3815 00:41:11.968191 DBI_RD = 0x0
3816 00:41:11.968238 OTF = 0x1
3817 00:41:11.968287 ===================================
3818 00:41:11.968335 ===================================
3819 00:41:11.968384 ANA top config
3820 00:41:11.968432 ===================================
3821 00:41:11.968480 DLL_ASYNC_EN = 0
3822 00:41:11.968528 ALL_SLAVE_EN = 1
3823 00:41:11.968575 NEW_RANK_MODE = 1
3824 00:41:11.968624 DLL_IDLE_MODE = 1
3825 00:41:11.968677 LP45_APHY_COMB_EN = 1
3826 00:41:11.968726 TX_ODT_DIS = 1
3827 00:41:11.968774 NEW_8X_MODE = 1
3828 00:41:11.968830 ===================================
3829 00:41:11.968897 ===================================
3830 00:41:11.968947 data_rate = 1200
3831 00:41:11.968996 CKR = 1
3832 00:41:11.969044 DQ_P2S_RATIO = 8
3833 00:41:11.969093 ===================================
3834 00:41:11.969141 CA_P2S_RATIO = 8
3835 00:41:11.969189 DQ_CA_OPEN = 0
3836 00:41:11.969237 DQ_SEMI_OPEN = 0
3837 00:41:11.969285 CA_SEMI_OPEN = 0
3838 00:41:11.969332 CA_FULL_RATE = 0
3839 00:41:11.969380 DQ_CKDIV4_EN = 1
3840 00:41:11.969428 CA_CKDIV4_EN = 1
3841 00:41:11.969477 CA_PREDIV_EN = 0
3842 00:41:11.969525 PH8_DLY = 0
3843 00:41:11.969573 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3844 00:41:11.969620 DQ_AAMCK_DIV = 4
3845 00:41:11.969669 CA_AAMCK_DIV = 4
3846 00:41:11.969718 CA_ADMCK_DIV = 4
3847 00:41:11.969765 DQ_TRACK_CA_EN = 0
3848 00:41:11.969813 CA_PICK = 600
3849 00:41:11.969861 CA_MCKIO = 600
3850 00:41:11.969909 MCKIO_SEMI = 0
3851 00:41:11.969956 PLL_FREQ = 2288
3852 00:41:11.970004 DQ_UI_PI_RATIO = 32
3853 00:41:11.970052 CA_UI_PI_RATIO = 0
3854 00:41:11.970100 ===================================
3855 00:41:11.970148 ===================================
3856 00:41:11.970196 memory_type:LPDDR4
3857 00:41:11.970243 GP_NUM : 10
3858 00:41:11.970291 SRAM_EN : 1
3859 00:41:11.970340 MD32_EN : 0
3860 00:41:11.970388 ===================================
3861 00:41:11.970436 [ANA_INIT] >>>>>>>>>>>>>>
3862 00:41:11.970483 <<<<<< [CONFIGURE PHASE]: ANA_TX
3863 00:41:11.970532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3864 00:41:11.970580 ===================================
3865 00:41:11.970628 data_rate = 1200,PCW = 0X5800
3866 00:41:11.970863 ===================================
3867 00:41:11.970920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3868 00:41:11.970970 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 00:41:11.971018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3870 00:41:11.971067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3871 00:41:11.971116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3872 00:41:11.971164 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3873 00:41:11.971213 [ANA_INIT] flow start
3874 00:41:11.971260 [ANA_INIT] PLL >>>>>>>>
3875 00:41:11.971308 [ANA_INIT] PLL <<<<<<<<
3876 00:41:11.971356 [ANA_INIT] MIDPI >>>>>>>>
3877 00:41:11.971404 [ANA_INIT] MIDPI <<<<<<<<
3878 00:41:11.971452 [ANA_INIT] DLL >>>>>>>>
3879 00:41:11.971500 [ANA_INIT] flow end
3880 00:41:11.971572 ============ LP4 DIFF to SE enter ============
3881 00:41:11.971666 ============ LP4 DIFF to SE exit ============
3882 00:41:11.971742 [ANA_INIT] <<<<<<<<<<<<<
3883 00:41:11.972637 [Flow] Enable top DCM control >>>>>
3884 00:41:11.975591 [Flow] Enable top DCM control <<<<<
3885 00:41:11.979141 Enable DLL master slave shuffle
3886 00:41:11.985437 ==============================================================
3887 00:41:11.985515 Gating Mode config
3888 00:41:11.992428 ==============================================================
3889 00:41:11.995687 Config description:
3890 00:41:12.005603 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3891 00:41:12.012372 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3892 00:41:12.015392 SELPH_MODE 0: By rank 1: By Phase
3893 00:41:12.022162 ==============================================================
3894 00:41:12.025763 GAT_TRACK_EN = 1
3895 00:41:12.025840 RX_GATING_MODE = 2
3896 00:41:12.029089 RX_GATING_TRACK_MODE = 2
3897 00:41:12.032370 SELPH_MODE = 1
3898 00:41:12.035505 PICG_EARLY_EN = 1
3899 00:41:12.038816 VALID_LAT_VALUE = 1
3900 00:41:12.045503 ==============================================================
3901 00:41:12.048624 Enter into Gating configuration >>>>
3902 00:41:12.052001 Exit from Gating configuration <<<<
3903 00:41:12.055368 Enter into DVFS_PRE_config >>>>>
3904 00:41:12.065050 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3905 00:41:12.068626 Exit from DVFS_PRE_config <<<<<
3906 00:41:12.072047 Enter into PICG configuration >>>>
3907 00:41:12.075051 Exit from PICG configuration <<<<
3908 00:41:12.078610 [RX_INPUT] configuration >>>>>
3909 00:41:12.081735 [RX_INPUT] configuration <<<<<
3910 00:41:12.085422 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3911 00:41:12.091864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3912 00:41:12.098518 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3913 00:41:12.104747 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3914 00:41:12.108606 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3915 00:41:12.115192 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3916 00:41:12.118572 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3917 00:41:12.124849 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3918 00:41:12.128305 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3919 00:41:12.131872 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3920 00:41:12.135069 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3921 00:41:12.141643 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3922 00:41:12.145208 ===================================
3923 00:41:12.145303 LPDDR4 DRAM CONFIGURATION
3924 00:41:12.148032 ===================================
3925 00:41:12.151350 EX_ROW_EN[0] = 0x0
3926 00:41:12.154998 EX_ROW_EN[1] = 0x0
3927 00:41:12.155111 LP4Y_EN = 0x0
3928 00:41:12.159017 WORK_FSP = 0x0
3929 00:41:12.159143 WL = 0x2
3930 00:41:12.161784 RL = 0x2
3931 00:41:12.161926 BL = 0x2
3932 00:41:12.164756 RPST = 0x0
3933 00:41:12.164898 RD_PRE = 0x0
3934 00:41:12.167976 WR_PRE = 0x1
3935 00:41:12.168135 WR_PST = 0x0
3936 00:41:12.171346 DBI_WR = 0x0
3937 00:41:12.171534 DBI_RD = 0x0
3938 00:41:12.174681 OTF = 0x1
3939 00:41:12.177827 ===================================
3940 00:41:12.181213 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3941 00:41:12.184693 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3942 00:41:12.191750 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3943 00:41:12.194557 ===================================
3944 00:41:12.194954 LPDDR4 DRAM CONFIGURATION
3945 00:41:12.198199 ===================================
3946 00:41:12.201560 EX_ROW_EN[0] = 0x10
3947 00:41:12.204985 EX_ROW_EN[1] = 0x0
3948 00:41:12.205417 LP4Y_EN = 0x0
3949 00:41:12.207819 WORK_FSP = 0x0
3950 00:41:12.208248 WL = 0x2
3951 00:41:12.211241 RL = 0x2
3952 00:41:12.211677 BL = 0x2
3953 00:41:12.214545 RPST = 0x0
3954 00:41:12.214979 RD_PRE = 0x0
3955 00:41:12.217501 WR_PRE = 0x1
3956 00:41:12.217589 WR_PST = 0x0
3957 00:41:12.220904 DBI_WR = 0x0
3958 00:41:12.220981 DBI_RD = 0x0
3959 00:41:12.224144 OTF = 0x1
3960 00:41:12.227712 ===================================
3961 00:41:12.234146 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3962 00:41:12.237615 nWR fixed to 30
3963 00:41:12.241104 [ModeRegInit_LP4] CH0 RK0
3964 00:41:12.241201 [ModeRegInit_LP4] CH0 RK1
3965 00:41:12.244425 [ModeRegInit_LP4] CH1 RK0
3966 00:41:12.247818 [ModeRegInit_LP4] CH1 RK1
3967 00:41:12.247932 match AC timing 17
3968 00:41:12.254063 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3969 00:41:12.257512 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3970 00:41:12.260780 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3971 00:41:12.267406 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3972 00:41:12.270932 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3973 00:41:12.271010 ==
3974 00:41:12.274010 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 00:41:12.276999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 00:41:12.277076 ==
3977 00:41:12.284402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3978 00:41:12.290519 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3979 00:41:12.293501 [CA 0] Center 37 (7~67) winsize 61
3980 00:41:12.296862 [CA 1] Center 37 (7~67) winsize 61
3981 00:41:12.300115 [CA 2] Center 35 (5~65) winsize 61
3982 00:41:12.303764 [CA 3] Center 35 (5~65) winsize 61
3983 00:41:12.307092 [CA 4] Center 34 (4~65) winsize 62
3984 00:41:12.310535 [CA 5] Center 34 (3~65) winsize 63
3985 00:41:12.310624
3986 00:41:12.313913 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3987 00:41:12.314010
3988 00:41:12.317236 [CATrainingPosCal] consider 1 rank data
3989 00:41:12.320562 u2DelayCellTimex100 = 270/100 ps
3990 00:41:12.323460 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3991 00:41:12.326895 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3992 00:41:12.330291 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3993 00:41:12.333681 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3994 00:41:12.336730 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3995 00:41:12.340284 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
3996 00:41:12.343632
3997 00:41:12.346920 CA PerBit enable=1, Macro0, CA PI delay=34
3998 00:41:12.346998
3999 00:41:12.350169 [CBTSetCACLKResult] CA Dly = 34
4000 00:41:12.350247 CS Dly: 6 (0~37)
4001 00:41:12.350324 ==
4002 00:41:12.353647 Dram Type= 6, Freq= 0, CH_0, rank 1
4003 00:41:12.356992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 00:41:12.357071 ==
4005 00:41:12.363428 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4006 00:41:12.369844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4007 00:41:12.373620 [CA 0] Center 37 (7~67) winsize 61
4008 00:41:12.376541 [CA 1] Center 36 (6~67) winsize 62
4009 00:41:12.380071 [CA 2] Center 35 (5~65) winsize 61
4010 00:41:12.383294 [CA 3] Center 35 (5~65) winsize 61
4011 00:41:12.386655 [CA 4] Center 34 (4~65) winsize 62
4012 00:41:12.390327 [CA 5] Center 34 (3~65) winsize 63
4013 00:41:12.390406
4014 00:41:12.393421 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4015 00:41:12.393499
4016 00:41:12.396814 [CATrainingPosCal] consider 2 rank data
4017 00:41:12.399970 u2DelayCellTimex100 = 270/100 ps
4018 00:41:12.403499 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4019 00:41:12.406473 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4020 00:41:12.410165 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4021 00:41:12.413248 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4022 00:41:12.416932 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4023 00:41:12.423129 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4024 00:41:12.423208
4025 00:41:12.426475 CA PerBit enable=1, Macro0, CA PI delay=34
4026 00:41:12.426554
4027 00:41:12.430005 [CBTSetCACLKResult] CA Dly = 34
4028 00:41:12.430085 CS Dly: 6 (0~38)
4029 00:41:12.430163
4030 00:41:12.433378 ----->DramcWriteLeveling(PI) begin...
4031 00:41:12.433458 ==
4032 00:41:12.436816 Dram Type= 6, Freq= 0, CH_0, rank 0
4033 00:41:12.443296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4034 00:41:12.443376 ==
4035 00:41:12.446643 Write leveling (Byte 0): 32 => 32
4036 00:41:12.446721 Write leveling (Byte 1): 31 => 31
4037 00:41:12.449762 DramcWriteLeveling(PI) end<-----
4038 00:41:12.449873
4039 00:41:12.449966 ==
4040 00:41:12.453291 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 00:41:12.459918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 00:41:12.460028 ==
4043 00:41:12.462930 [Gating] SW mode calibration
4044 00:41:12.469618 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4045 00:41:12.473110 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4046 00:41:12.479621 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 00:41:12.483151 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 00:41:12.485987 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 00:41:12.492729 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4050 00:41:12.496104 0 9 16 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
4051 00:41:12.499515 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 00:41:12.505680 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 00:41:12.509407 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 00:41:12.512349 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 00:41:12.519024 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 00:41:12.523413 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 00:41:12.525921 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4058 00:41:12.532379 0 10 16 | B1->B0 | 3232 3b3b | 0 0 | (0 0) (1 1)
4059 00:41:12.535922 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 00:41:12.539046 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 00:41:12.546169 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 00:41:12.549393 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 00:41:12.552197 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 00:41:12.559213 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 00:41:12.562514 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4066 00:41:12.565805 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4067 00:41:12.569098 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 00:41:12.575655 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 00:41:12.579031 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 00:41:12.582363 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 00:41:12.588703 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 00:41:12.592161 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 00:41:12.595423 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 00:41:12.602331 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 00:41:12.605300 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 00:41:12.608932 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 00:41:12.615548 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 00:41:12.618980 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 00:41:12.622254 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 00:41:12.628732 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 00:41:12.632016 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 00:41:12.635345 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4083 00:41:12.638709 Total UI for P1: 0, mck2ui 16
4084 00:41:12.641738 best dqsien dly found for B0: ( 0, 13, 14)
4085 00:41:12.648336 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 00:41:12.648416 Total UI for P1: 0, mck2ui 16
4087 00:41:12.655663 best dqsien dly found for B1: ( 0, 13, 16)
4088 00:41:12.658456 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4089 00:41:12.661639 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4090 00:41:12.661716
4091 00:41:12.665068 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4092 00:41:12.668573 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4093 00:41:12.671438 [Gating] SW calibration Done
4094 00:41:12.671515 ==
4095 00:41:12.674987 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 00:41:12.678274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 00:41:12.678352 ==
4098 00:41:12.681814 RX Vref Scan: 0
4099 00:41:12.681891
4100 00:41:12.684771 RX Vref 0 -> 0, step: 1
4101 00:41:12.684849
4102 00:41:12.684927 RX Delay -230 -> 252, step: 16
4103 00:41:12.691173 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4104 00:41:12.695194 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4105 00:41:12.697921 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4106 00:41:12.701225 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4107 00:41:12.708141 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4108 00:41:12.711556 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4109 00:41:12.714953 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4110 00:41:12.717827 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4111 00:41:12.721389 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4112 00:41:12.728033 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4113 00:41:12.731399 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4114 00:41:12.734323 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4115 00:41:12.737673 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4116 00:41:12.744679 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4117 00:41:12.747604 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4118 00:41:12.750958 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4119 00:41:12.751038 ==
4120 00:41:12.754262 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 00:41:12.758003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 00:41:12.760909 ==
4123 00:41:12.760989 DQS Delay:
4124 00:41:12.761066 DQS0 = 0, DQS1 = 0
4125 00:41:12.764283 DQM Delay:
4126 00:41:12.764362 DQM0 = 38, DQM1 = 31
4127 00:41:12.767801 DQ Delay:
4128 00:41:12.770968 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4129 00:41:12.771048 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4130 00:41:12.774526 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4131 00:41:12.777996 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4132 00:41:12.780942
4133 00:41:12.781021
4134 00:41:12.781097 ==
4135 00:41:12.784358 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 00:41:12.787191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 00:41:12.787271 ==
4138 00:41:12.787349
4139 00:41:12.787421
4140 00:41:12.790665 TX Vref Scan disable
4141 00:41:12.790744 == TX Byte 0 ==
4142 00:41:12.797079 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4143 00:41:12.800592 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4144 00:41:12.800708 == TX Byte 1 ==
4145 00:41:12.807142 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4146 00:41:12.810458 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4147 00:41:12.810576 ==
4148 00:41:12.813903 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 00:41:12.817353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 00:41:12.817433 ==
4151 00:41:12.817493
4152 00:41:12.817547
4153 00:41:12.820308 TX Vref Scan disable
4154 00:41:12.823679 == TX Byte 0 ==
4155 00:41:12.827129 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4156 00:41:12.833803 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4157 00:41:12.833907 == TX Byte 1 ==
4158 00:41:12.837110 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4159 00:41:12.843437 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4160 00:41:12.843517
4161 00:41:12.843592 [DATLAT]
4162 00:41:12.843662 Freq=600, CH0 RK0
4163 00:41:12.843716
4164 00:41:12.846937 DATLAT Default: 0x9
4165 00:41:12.847014 0, 0xFFFF, sum = 0
4166 00:41:12.850370 1, 0xFFFF, sum = 0
4167 00:41:12.853684 2, 0xFFFF, sum = 0
4168 00:41:12.853763 3, 0xFFFF, sum = 0
4169 00:41:12.856929 4, 0xFFFF, sum = 0
4170 00:41:12.857007 5, 0xFFFF, sum = 0
4171 00:41:12.860248 6, 0xFFFF, sum = 0
4172 00:41:12.860328 7, 0xFFFF, sum = 0
4173 00:41:12.863700 8, 0x0, sum = 1
4174 00:41:12.863778 9, 0x0, sum = 2
4175 00:41:12.863839 10, 0x0, sum = 3
4176 00:41:12.866946 11, 0x0, sum = 4
4177 00:41:12.867024 best_step = 9
4178 00:41:12.867083
4179 00:41:12.867138 ==
4180 00:41:12.870365 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 00:41:12.877047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 00:41:12.877129 ==
4183 00:41:12.877189 RX Vref Scan: 1
4184 00:41:12.877246
4185 00:41:12.879953 RX Vref 0 -> 0, step: 1
4186 00:41:12.880030
4187 00:41:12.883635 RX Delay -195 -> 252, step: 8
4188 00:41:12.883711
4189 00:41:12.887220 Set Vref, RX VrefLevel [Byte0]: 62
4190 00:41:12.890119 [Byte1]: 52
4191 00:41:12.890196
4192 00:41:12.893257 Final RX Vref Byte 0 = 62 to rank0
4193 00:41:12.896779 Final RX Vref Byte 1 = 52 to rank0
4194 00:41:12.900320 Final RX Vref Byte 0 = 62 to rank1
4195 00:41:12.903161 Final RX Vref Byte 1 = 52 to rank1==
4196 00:41:12.906616 Dram Type= 6, Freq= 0, CH_0, rank 0
4197 00:41:12.909966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 00:41:12.910044 ==
4199 00:41:12.913194 DQS Delay:
4200 00:41:12.913271 DQS0 = 0, DQS1 = 0
4201 00:41:12.916548 DQM Delay:
4202 00:41:12.916625 DQM0 = 33, DQM1 = 29
4203 00:41:12.916723 DQ Delay:
4204 00:41:12.919687 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4205 00:41:12.923050 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4206 00:41:12.926570 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4207 00:41:12.929743 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4208 00:41:12.929822
4209 00:41:12.929882
4210 00:41:12.939474 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a49, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4211 00:41:12.942791 CH0 RK0: MR19=808, MR18=4A49
4212 00:41:12.949819 CH0_RK0: MR19=0x808, MR18=0x4A49, DQSOSC=395, MR23=63, INC=168, DEC=112
4213 00:41:12.949901
4214 00:41:12.952786 ----->DramcWriteLeveling(PI) begin...
4215 00:41:12.952864 ==
4216 00:41:12.956284 Dram Type= 6, Freq= 0, CH_0, rank 1
4217 00:41:12.959552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 00:41:12.959630 ==
4219 00:41:12.962825 Write leveling (Byte 0): 32 => 32
4220 00:41:12.966350 Write leveling (Byte 1): 30 => 30
4221 00:41:12.969658 DramcWriteLeveling(PI) end<-----
4222 00:41:12.969735
4223 00:41:12.969795 ==
4224 00:41:12.972572 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 00:41:12.975916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 00:41:12.975994 ==
4227 00:41:12.980014 [Gating] SW mode calibration
4228 00:41:12.986142 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4229 00:41:12.992512 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4230 00:41:12.996386 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 00:41:12.999103 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 00:41:13.005842 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 00:41:13.009426 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4234 00:41:13.012507 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4235 00:41:13.018939 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 00:41:13.022282 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 00:41:13.025564 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 00:41:13.032378 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 00:41:13.035605 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 00:41:13.038812 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 00:41:13.045886 0 10 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
4242 00:41:13.049071 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4243 00:41:13.052091 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 00:41:13.058800 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 00:41:13.062483 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 00:41:13.065661 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 00:41:13.072467 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 00:41:13.075322 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 00:41:13.078726 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4250 00:41:13.085594 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 00:41:13.088484 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 00:41:13.091800 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 00:41:13.098568 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 00:41:13.101999 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 00:41:13.105418 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 00:41:13.111683 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 00:41:13.115310 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 00:41:13.118693 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 00:41:13.124882 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 00:41:13.128192 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 00:41:13.131912 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 00:41:13.138639 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 00:41:13.141882 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 00:41:13.145407 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 00:41:13.148286 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4266 00:41:13.154916 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 00:41:13.158255 Total UI for P1: 0, mck2ui 16
4268 00:41:13.161755 best dqsien dly found for B0: ( 0, 13, 12)
4269 00:41:13.165171 Total UI for P1: 0, mck2ui 16
4270 00:41:13.168528 best dqsien dly found for B1: ( 0, 13, 14)
4271 00:41:13.171811 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4272 00:41:13.174921 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4273 00:41:13.175008
4274 00:41:13.178293 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4275 00:41:13.181720 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4276 00:41:13.185083 [Gating] SW calibration Done
4277 00:41:13.185160 ==
4278 00:41:13.188270 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 00:41:13.191626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 00:41:13.191703 ==
4281 00:41:13.195133 RX Vref Scan: 0
4282 00:41:13.195210
4283 00:41:13.197965 RX Vref 0 -> 0, step: 1
4284 00:41:13.198042
4285 00:41:13.198102 RX Delay -230 -> 252, step: 16
4286 00:41:13.204869 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4287 00:41:13.208337 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4288 00:41:13.211291 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4289 00:41:13.214733 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4290 00:41:13.221669 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4291 00:41:13.225080 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4292 00:41:13.227866 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4293 00:41:13.231309 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4294 00:41:13.234766 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4295 00:41:13.241645 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4296 00:41:13.244489 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4297 00:41:13.248171 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4298 00:41:13.251150 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4299 00:41:13.257817 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4300 00:41:13.261290 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4301 00:41:13.264846 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4302 00:41:13.264923 ==
4303 00:41:13.268239 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 00:41:13.270898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 00:41:13.274297 ==
4306 00:41:13.274374 DQS Delay:
4307 00:41:13.274435 DQS0 = 0, DQS1 = 0
4308 00:41:13.277707 DQM Delay:
4309 00:41:13.277784 DQM0 = 35, DQM1 = 29
4310 00:41:13.281134 DQ Delay:
4311 00:41:13.284261 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4312 00:41:13.284338 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4313 00:41:13.287865 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4314 00:41:13.290866 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4315 00:41:13.294131
4316 00:41:13.294208
4317 00:41:13.294268 ==
4318 00:41:13.297692 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 00:41:13.300971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 00:41:13.301048 ==
4321 00:41:13.301109
4322 00:41:13.301164
4323 00:41:13.304171 TX Vref Scan disable
4324 00:41:13.304263 == TX Byte 0 ==
4325 00:41:13.311183 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4326 00:41:13.314655 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4327 00:41:13.314732 == TX Byte 1 ==
4328 00:41:13.320771 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4329 00:41:13.324305 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4330 00:41:13.324381 ==
4331 00:41:13.327268 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 00:41:13.330773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 00:41:13.330851 ==
4334 00:41:13.330909
4335 00:41:13.330964
4336 00:41:13.334067 TX Vref Scan disable
4337 00:41:13.337855 == TX Byte 0 ==
4338 00:41:13.340585 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4339 00:41:13.344022 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4340 00:41:13.347370 == TX Byte 1 ==
4341 00:41:13.350792 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4342 00:41:13.354242 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4343 00:41:13.357488
4344 00:41:13.357564 [DATLAT]
4345 00:41:13.357623 Freq=600, CH0 RK1
4346 00:41:13.357679
4347 00:41:13.360715 DATLAT Default: 0x9
4348 00:41:13.360791 0, 0xFFFF, sum = 0
4349 00:41:13.364168 1, 0xFFFF, sum = 0
4350 00:41:13.364245 2, 0xFFFF, sum = 0
4351 00:41:13.367293 3, 0xFFFF, sum = 0
4352 00:41:13.367370 4, 0xFFFF, sum = 0
4353 00:41:13.370699 5, 0xFFFF, sum = 0
4354 00:41:13.374271 6, 0xFFFF, sum = 0
4355 00:41:13.374349 7, 0xFFFF, sum = 0
4356 00:41:13.374409 8, 0x0, sum = 1
4357 00:41:13.377752 9, 0x0, sum = 2
4358 00:41:13.377829 10, 0x0, sum = 3
4359 00:41:13.380671 11, 0x0, sum = 4
4360 00:41:13.380749 best_step = 9
4361 00:41:13.380808
4362 00:41:13.380862 ==
4363 00:41:13.384078 Dram Type= 6, Freq= 0, CH_0, rank 1
4364 00:41:13.390850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 00:41:13.390927 ==
4366 00:41:13.390986 RX Vref Scan: 0
4367 00:41:13.391041
4368 00:41:13.393756 RX Vref 0 -> 0, step: 1
4369 00:41:13.393832
4370 00:41:13.397040 RX Delay -195 -> 252, step: 8
4371 00:41:13.400588 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4372 00:41:13.407177 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4373 00:41:13.410424 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4374 00:41:13.413866 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4375 00:41:13.417114 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4376 00:41:13.423521 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4377 00:41:13.426953 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4378 00:41:13.430307 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4379 00:41:13.433651 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4380 00:41:13.437201 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4381 00:41:13.443616 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4382 00:41:13.447098 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4383 00:41:13.450475 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4384 00:41:13.453836 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4385 00:41:13.460595 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4386 00:41:13.464023 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4387 00:41:13.464121 ==
4388 00:41:13.466801 Dram Type= 6, Freq= 0, CH_0, rank 1
4389 00:41:13.470207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 00:41:13.470284 ==
4391 00:41:13.473487 DQS Delay:
4392 00:41:13.473563 DQS0 = 0, DQS1 = 0
4393 00:41:13.473622 DQM Delay:
4394 00:41:13.477143 DQM0 = 33, DQM1 = 27
4395 00:41:13.477219 DQ Delay:
4396 00:41:13.480284 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4397 00:41:13.483717 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4398 00:41:13.486892 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4399 00:41:13.490370 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4400 00:41:13.490446
4401 00:41:13.490506
4402 00:41:13.500262 [DQSOSCAuto] RK1, (LSB)MR18= 0x7846, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
4403 00:41:13.500339 CH0 RK1: MR19=808, MR18=7846
4404 00:41:13.506598 CH0_RK1: MR19=0x808, MR18=0x7846, DQSOSC=387, MR23=63, INC=175, DEC=116
4405 00:41:13.510043 [RxdqsGatingPostProcess] freq 600
4406 00:41:13.516800 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4407 00:41:13.520176 Pre-setting of DQS Precalculation
4408 00:41:13.523547 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4409 00:41:13.523624 ==
4410 00:41:13.526909 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 00:41:13.533448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 00:41:13.533525 ==
4413 00:41:13.536506 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4414 00:41:13.543638 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4415 00:41:13.546732 [CA 0] Center 35 (5~66) winsize 62
4416 00:41:13.550109 [CA 1] Center 36 (6~66) winsize 61
4417 00:41:13.553744 [CA 2] Center 34 (4~65) winsize 62
4418 00:41:13.556877 [CA 3] Center 34 (4~65) winsize 62
4419 00:41:13.560385 [CA 4] Center 34 (4~65) winsize 62
4420 00:41:13.563797 [CA 5] Center 33 (3~64) winsize 62
4421 00:41:13.563874
4422 00:41:13.567054 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4423 00:41:13.567130
4424 00:41:13.569912 [CATrainingPosCal] consider 1 rank data
4425 00:41:13.573361 u2DelayCellTimex100 = 270/100 ps
4426 00:41:13.576613 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4427 00:41:13.580182 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4428 00:41:13.583543 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4429 00:41:13.590300 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 00:41:13.593438 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4431 00:41:13.596578 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 00:41:13.596678
4433 00:41:13.600024 CA PerBit enable=1, Macro0, CA PI delay=33
4434 00:41:13.600100
4435 00:41:13.603197 [CBTSetCACLKResult] CA Dly = 33
4436 00:41:13.603274 CS Dly: 4 (0~35)
4437 00:41:13.603333 ==
4438 00:41:13.606844 Dram Type= 6, Freq= 0, CH_1, rank 1
4439 00:41:13.613078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 00:41:13.613157 ==
4441 00:41:13.616392 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4442 00:41:13.622727 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4443 00:41:13.626725 [CA 0] Center 36 (6~66) winsize 61
4444 00:41:13.629848 [CA 1] Center 35 (5~66) winsize 62
4445 00:41:13.632916 [CA 2] Center 34 (4~65) winsize 62
4446 00:41:13.636601 [CA 3] Center 34 (3~65) winsize 63
4447 00:41:13.640011 [CA 4] Center 34 (4~65) winsize 62
4448 00:41:13.643277 [CA 5] Center 33 (3~64) winsize 62
4449 00:41:13.643353
4450 00:41:13.646812 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4451 00:41:13.646889
4452 00:41:13.649548 [CATrainingPosCal] consider 2 rank data
4453 00:41:13.652749 u2DelayCellTimex100 = 270/100 ps
4454 00:41:13.656193 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4455 00:41:13.662534 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4456 00:41:13.666009 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4457 00:41:13.669541 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4458 00:41:13.672714 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4459 00:41:13.676119 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4460 00:41:13.676196
4461 00:41:13.679480 CA PerBit enable=1, Macro0, CA PI delay=33
4462 00:41:13.679557
4463 00:41:13.682826 [CBTSetCACLKResult] CA Dly = 33
4464 00:41:13.685833 CS Dly: 4 (0~36)
4465 00:41:13.685910
4466 00:41:13.689293 ----->DramcWriteLeveling(PI) begin...
4467 00:41:13.689373 ==
4468 00:41:13.692658 Dram Type= 6, Freq= 0, CH_1, rank 0
4469 00:41:13.696058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 00:41:13.696136 ==
4471 00:41:13.699527 Write leveling (Byte 0): 29 => 29
4472 00:41:13.702893 Write leveling (Byte 1): 31 => 31
4473 00:41:13.705660 DramcWriteLeveling(PI) end<-----
4474 00:41:13.705737
4475 00:41:13.705798 ==
4476 00:41:13.709279 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 00:41:13.712489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 00:41:13.712567 ==
4479 00:41:13.716098 [Gating] SW mode calibration
4480 00:41:13.722339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4481 00:41:13.729353 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4482 00:41:13.732213 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4483 00:41:13.735748 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4484 00:41:13.742518 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4485 00:41:13.745905 0 9 12 | B1->B0 | 3333 3131 | 1 1 | (1 0) (1 1)
4486 00:41:13.749155 0 9 16 | B1->B0 | 2a2a 2929 | 0 0 | (0 0) (0 0)
4487 00:41:13.755673 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 00:41:13.759054 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 00:41:13.762381 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 00:41:13.769124 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 00:41:13.772280 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 00:41:13.775398 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 00:41:13.782144 0 10 12 | B1->B0 | 3030 3030 | 0 0 | (1 1) (1 1)
4494 00:41:13.785538 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4495 00:41:13.788609 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 00:41:13.795600 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 00:41:13.798800 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 00:41:13.802162 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 00:41:13.808632 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 00:41:13.811855 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 00:41:13.815170 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4502 00:41:13.818622 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 00:41:13.825525 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 00:41:13.828994 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 00:41:13.832124 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 00:41:13.838733 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 00:41:13.841663 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 00:41:13.844900 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 00:41:13.851698 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 00:41:13.855147 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 00:41:13.858674 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 00:41:13.865012 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 00:41:13.868499 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 00:41:13.871969 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 00:41:13.878132 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 00:41:13.881626 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 00:41:13.885059 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4518 00:41:13.891799 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4519 00:41:13.895173 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 00:41:13.898172 Total UI for P1: 0, mck2ui 16
4521 00:41:13.901470 best dqsien dly found for B0: ( 0, 13, 14)
4522 00:41:13.904815 Total UI for P1: 0, mck2ui 16
4523 00:41:13.908098 best dqsien dly found for B1: ( 0, 13, 14)
4524 00:41:13.911615 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4525 00:41:13.914819 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4526 00:41:13.914896
4527 00:41:13.918209 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4528 00:41:13.921202 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4529 00:41:13.924657 [Gating] SW calibration Done
4530 00:41:13.924764 ==
4531 00:41:13.928120 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 00:41:13.931506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 00:41:13.934441 ==
4534 00:41:13.934517 RX Vref Scan: 0
4535 00:41:13.934576
4536 00:41:13.938266 RX Vref 0 -> 0, step: 1
4537 00:41:13.938343
4538 00:41:13.941491 RX Delay -230 -> 252, step: 16
4539 00:41:13.944774 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4540 00:41:13.948022 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4541 00:41:13.951449 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4542 00:41:13.957716 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4543 00:41:13.961238 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4544 00:41:13.965047 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4545 00:41:13.967898 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4546 00:41:13.971307 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4547 00:41:13.977673 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4548 00:41:13.981094 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4549 00:41:13.984513 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4550 00:41:13.987969 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4551 00:41:13.994277 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4552 00:41:13.997749 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4553 00:41:14.001091 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4554 00:41:14.004355 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4555 00:41:14.004432 ==
4556 00:41:14.007864 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 00:41:14.014296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 00:41:14.014374 ==
4559 00:41:14.014433 DQS Delay:
4560 00:41:14.018065 DQS0 = 0, DQS1 = 0
4561 00:41:14.018143 DQM Delay:
4562 00:41:14.018203 DQM0 = 38, DQM1 = 28
4563 00:41:14.021195 DQ Delay:
4564 00:41:14.024539 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4565 00:41:14.027877 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4566 00:41:14.030841 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4567 00:41:14.034617 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4568 00:41:14.034694
4569 00:41:14.034753
4570 00:41:14.034808 ==
4571 00:41:14.037866 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 00:41:14.041323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 00:41:14.041401 ==
4574 00:41:14.041461
4575 00:41:14.041515
4576 00:41:14.044305 TX Vref Scan disable
4577 00:41:14.047651 == TX Byte 0 ==
4578 00:41:14.050969 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4579 00:41:14.054338 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4580 00:41:14.057748 == TX Byte 1 ==
4581 00:41:14.060977 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4582 00:41:14.064324 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4583 00:41:14.064401 ==
4584 00:41:14.067428 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 00:41:14.070877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 00:41:14.070954 ==
4587 00:41:14.074169
4588 00:41:14.074245
4589 00:41:14.074304 TX Vref Scan disable
4590 00:41:14.077694 == TX Byte 0 ==
4591 00:41:14.081150 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4592 00:41:14.087915 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4593 00:41:14.087992 == TX Byte 1 ==
4594 00:41:14.091153 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4595 00:41:14.097841 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4596 00:41:14.097926
4597 00:41:14.097988 [DATLAT]
4598 00:41:14.098043 Freq=600, CH1 RK0
4599 00:41:14.098099
4600 00:41:14.101242 DATLAT Default: 0x9
4601 00:41:14.101319 0, 0xFFFF, sum = 0
4602 00:41:14.104108 1, 0xFFFF, sum = 0
4603 00:41:14.104186 2, 0xFFFF, sum = 0
4604 00:41:14.107805 3, 0xFFFF, sum = 0
4605 00:41:14.111176 4, 0xFFFF, sum = 0
4606 00:41:14.111254 5, 0xFFFF, sum = 0
4607 00:41:14.114613 6, 0xFFFF, sum = 0
4608 00:41:14.114691 7, 0xFFFF, sum = 0
4609 00:41:14.118016 8, 0x0, sum = 1
4610 00:41:14.118094 9, 0x0, sum = 2
4611 00:41:14.118156 10, 0x0, sum = 3
4612 00:41:14.120842 11, 0x0, sum = 4
4613 00:41:14.120920 best_step = 9
4614 00:41:14.120979
4615 00:41:14.121035 ==
4616 00:41:14.124253 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 00:41:14.130991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 00:41:14.131072 ==
4619 00:41:14.131133 RX Vref Scan: 1
4620 00:41:14.131189
4621 00:41:14.134314 RX Vref 0 -> 0, step: 1
4622 00:41:14.134391
4623 00:41:14.137641 RX Delay -195 -> 252, step: 8
4624 00:41:14.137718
4625 00:41:14.141013 Set Vref, RX VrefLevel [Byte0]: 54
4626 00:41:14.144444 [Byte1]: 54
4627 00:41:14.144521
4628 00:41:14.147522 Final RX Vref Byte 0 = 54 to rank0
4629 00:41:14.150991 Final RX Vref Byte 1 = 54 to rank0
4630 00:41:14.154106 Final RX Vref Byte 0 = 54 to rank1
4631 00:41:14.157441 Final RX Vref Byte 1 = 54 to rank1==
4632 00:41:14.160851 Dram Type= 6, Freq= 0, CH_1, rank 0
4633 00:41:14.164395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 00:41:14.164473 ==
4635 00:41:14.167405 DQS Delay:
4636 00:41:14.167481 DQS0 = 0, DQS1 = 0
4637 00:41:14.170864 DQM Delay:
4638 00:41:14.170941 DQM0 = 38, DQM1 = 27
4639 00:41:14.171000 DQ Delay:
4640 00:41:14.174046 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4641 00:41:14.177624 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =36
4642 00:41:14.180508 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4643 00:41:14.183919 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4644 00:41:14.183996
4645 00:41:14.184056
4646 00:41:14.194262 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b37, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
4647 00:41:14.197196 CH1 RK0: MR19=808, MR18=2B37
4648 00:41:14.204114 CH1_RK0: MR19=0x808, MR18=0x2B37, DQSOSC=399, MR23=63, INC=164, DEC=109
4649 00:41:14.204199
4650 00:41:14.206932 ----->DramcWriteLeveling(PI) begin...
4651 00:41:14.207025 ==
4652 00:41:14.210550 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 00:41:14.213857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 00:41:14.213935 ==
4655 00:41:14.217267 Write leveling (Byte 0): 30 => 30
4656 00:41:14.220685 Write leveling (Byte 1): 30 => 30
4657 00:41:14.223600 DramcWriteLeveling(PI) end<-----
4658 00:41:14.223677
4659 00:41:14.223737 ==
4660 00:41:14.226940 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 00:41:14.230392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 00:41:14.230469 ==
4663 00:41:14.234002 [Gating] SW mode calibration
4664 00:41:14.240234 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4665 00:41:14.247109 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4666 00:41:14.250668 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 00:41:14.253974 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4668 00:41:14.260060 0 9 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4669 00:41:14.263475 0 9 12 | B1->B0 | 3030 2c2c | 1 0 | (1 1) (1 1)
4670 00:41:14.266882 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4671 00:41:14.273484 0 9 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4672 00:41:14.276952 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 00:41:14.280078 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 00:41:14.286715 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 00:41:14.290108 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 00:41:14.293205 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4677 00:41:14.300012 0 10 12 | B1->B0 | 3434 3939 | 0 1 | (0 0) (0 0)
4678 00:41:14.303112 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4679 00:41:14.306627 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 00:41:14.313396 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 00:41:14.316303 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 00:41:14.319843 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 00:41:14.323116 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 00:41:14.330101 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 00:41:14.333416 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4686 00:41:14.336395 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 00:41:14.343191 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 00:41:14.346653 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 00:41:14.350144 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 00:41:14.356322 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 00:41:14.359845 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 00:41:14.363157 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 00:41:14.369999 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 00:41:14.373330 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 00:41:14.376507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 00:41:14.382673 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 00:41:14.386431 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 00:41:14.389573 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 00:41:14.396235 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 00:41:14.399574 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 00:41:14.402865 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 00:41:14.406100 Total UI for P1: 0, mck2ui 16
4703 00:41:14.409317 best dqsien dly found for B0: ( 0, 13, 10)
4704 00:41:14.412929 Total UI for P1: 0, mck2ui 16
4705 00:41:14.415933 best dqsien dly found for B1: ( 0, 13, 10)
4706 00:41:14.419281 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4707 00:41:14.422381 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4708 00:41:14.426161
4709 00:41:14.429291 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4710 00:41:14.432567 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4711 00:41:14.435622 [Gating] SW calibration Done
4712 00:41:14.435701 ==
4713 00:41:14.439083 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 00:41:14.442478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 00:41:14.442558 ==
4716 00:41:14.442652 RX Vref Scan: 0
4717 00:41:14.445935
4718 00:41:14.446013 RX Vref 0 -> 0, step: 1
4719 00:41:14.446090
4720 00:41:14.448820 RX Delay -230 -> 252, step: 16
4721 00:41:14.452166 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4722 00:41:14.459281 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4723 00:41:14.462056 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4724 00:41:14.465466 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4725 00:41:14.468759 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4726 00:41:14.472159 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4727 00:41:14.478841 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4728 00:41:14.482256 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4729 00:41:14.485663 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4730 00:41:14.488557 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4731 00:41:14.495790 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4732 00:41:14.498855 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4733 00:41:14.502028 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4734 00:41:14.505215 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4735 00:41:14.512035 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4736 00:41:14.515104 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4737 00:41:14.515183 ==
4738 00:41:14.518878 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 00:41:14.522305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 00:41:14.522384 ==
4741 00:41:14.525339 DQS Delay:
4742 00:41:14.525439 DQS0 = 0, DQS1 = 0
4743 00:41:14.525533 DQM Delay:
4744 00:41:14.528395 DQM0 = 36, DQM1 = 30
4745 00:41:14.528486 DQ Delay:
4746 00:41:14.531910 DQ0 =33, DQ1 =33, DQ2 =25, DQ3 =33
4747 00:41:14.534972 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4748 00:41:14.538717 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4749 00:41:14.541650 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =33
4750 00:41:14.541729
4751 00:41:14.541805
4752 00:41:14.541877 ==
4753 00:41:14.544945 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 00:41:14.551949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 00:41:14.552029 ==
4756 00:41:14.552107
4757 00:41:14.552178
4758 00:41:14.552248 TX Vref Scan disable
4759 00:41:14.555332 == TX Byte 0 ==
4760 00:41:14.558800 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4761 00:41:14.562182 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4762 00:41:14.565145 == TX Byte 1 ==
4763 00:41:14.568667 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4764 00:41:14.571851 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4765 00:41:14.575299 ==
4766 00:41:14.578211 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 00:41:14.581585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 00:41:14.581664 ==
4769 00:41:14.581740
4770 00:41:14.581812
4771 00:41:14.584914 TX Vref Scan disable
4772 00:41:14.584992 == TX Byte 0 ==
4773 00:41:14.591850 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4774 00:41:14.595256 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4775 00:41:14.598122 == TX Byte 1 ==
4776 00:41:14.601690 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4777 00:41:14.605067 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4778 00:41:14.605167
4779 00:41:14.605261 [DATLAT]
4780 00:41:14.608201 Freq=600, CH1 RK1
4781 00:41:14.608278
4782 00:41:14.608337 DATLAT Default: 0x9
4783 00:41:14.611730 0, 0xFFFF, sum = 0
4784 00:41:14.611809 1, 0xFFFF, sum = 0
4785 00:41:14.615013 2, 0xFFFF, sum = 0
4786 00:41:14.618542 3, 0xFFFF, sum = 0
4787 00:41:14.618622 4, 0xFFFF, sum = 0
4788 00:41:14.621704 5, 0xFFFF, sum = 0
4789 00:41:14.621784 6, 0xFFFF, sum = 0
4790 00:41:14.624784 7, 0xFFFF, sum = 0
4791 00:41:14.624864 8, 0x0, sum = 1
4792 00:41:14.624943 9, 0x0, sum = 2
4793 00:41:14.628502 10, 0x0, sum = 3
4794 00:41:14.628582 11, 0x0, sum = 4
4795 00:41:14.631704 best_step = 9
4796 00:41:14.631782
4797 00:41:14.631859 ==
4798 00:41:14.634951 Dram Type= 6, Freq= 0, CH_1, rank 1
4799 00:41:14.638385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4800 00:41:14.638464 ==
4801 00:41:14.641620 RX Vref Scan: 0
4802 00:41:14.641698
4803 00:41:14.641776 RX Vref 0 -> 0, step: 1
4804 00:41:14.641849
4805 00:41:14.644793 RX Delay -195 -> 252, step: 8
4806 00:41:14.652504 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4807 00:41:14.655378 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4808 00:41:14.658675 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4809 00:41:14.661996 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4810 00:41:14.668847 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4811 00:41:14.672420 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4812 00:41:14.675737 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4813 00:41:14.679066 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4814 00:41:14.682004 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4815 00:41:14.688657 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4816 00:41:14.692045 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4817 00:41:14.695553 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4818 00:41:14.698899 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4819 00:41:14.705602 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4820 00:41:14.709154 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4821 00:41:14.712031 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4822 00:41:14.712108 ==
4823 00:41:14.715553 Dram Type= 6, Freq= 0, CH_1, rank 1
4824 00:41:14.718920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4825 00:41:14.722121 ==
4826 00:41:14.722197 DQS Delay:
4827 00:41:14.722257 DQS0 = 0, DQS1 = 0
4828 00:41:14.725632 DQM Delay:
4829 00:41:14.725708 DQM0 = 36, DQM1 = 29
4830 00:41:14.728476 DQ Delay:
4831 00:41:14.728553 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4832 00:41:14.731997 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4833 00:41:14.735118 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =24
4834 00:41:14.738803 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4835 00:41:14.738880
4836 00:41:14.741802
4837 00:41:14.749012 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4838 00:41:14.751979 CH1 RK1: MR19=808, MR18=3E5E
4839 00:41:14.758627 CH1_RK1: MR19=0x808, MR18=0x3E5E, DQSOSC=392, MR23=63, INC=170, DEC=113
4840 00:41:14.762263 [RxdqsGatingPostProcess] freq 600
4841 00:41:14.765614 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4842 00:41:14.768698 Pre-setting of DQS Precalculation
4843 00:41:14.772291 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4844 00:41:14.782391 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4845 00:41:14.788543 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4846 00:41:14.788620
4847 00:41:14.788714
4848 00:41:14.791892 [Calibration Summary] 1200 Mbps
4849 00:41:14.791968 CH 0, Rank 0
4850 00:41:14.795390 SW Impedance : PASS
4851 00:41:14.795466 DUTY Scan : NO K
4852 00:41:14.798847 ZQ Calibration : PASS
4853 00:41:14.801806 Jitter Meter : NO K
4854 00:41:14.801883 CBT Training : PASS
4855 00:41:14.805279 Write leveling : PASS
4856 00:41:14.808804 RX DQS gating : PASS
4857 00:41:14.808881 RX DQ/DQS(RDDQC) : PASS
4858 00:41:14.811663 TX DQ/DQS : PASS
4859 00:41:14.815172 RX DATLAT : PASS
4860 00:41:14.815249 RX DQ/DQS(Engine): PASS
4861 00:41:14.818581 TX OE : NO K
4862 00:41:14.818658 All Pass.
4863 00:41:14.818718
4864 00:41:14.822014 CH 0, Rank 1
4865 00:41:14.822091 SW Impedance : PASS
4866 00:41:14.825420 DUTY Scan : NO K
4867 00:41:14.828299 ZQ Calibration : PASS
4868 00:41:14.828376 Jitter Meter : NO K
4869 00:41:14.831721 CBT Training : PASS
4870 00:41:14.835034 Write leveling : PASS
4871 00:41:14.835112 RX DQS gating : PASS
4872 00:41:14.838263 RX DQ/DQS(RDDQC) : PASS
4873 00:41:14.841824 TX DQ/DQS : PASS
4874 00:41:14.841901 RX DATLAT : PASS
4875 00:41:14.844714 RX DQ/DQS(Engine): PASS
4876 00:41:14.848215 TX OE : NO K
4877 00:41:14.848292 All Pass.
4878 00:41:14.848351
4879 00:41:14.848406 CH 1, Rank 0
4880 00:41:14.851314 SW Impedance : PASS
4881 00:41:14.854705 DUTY Scan : NO K
4882 00:41:14.854781 ZQ Calibration : PASS
4883 00:41:14.858181 Jitter Meter : NO K
4884 00:41:14.858265 CBT Training : PASS
4885 00:41:14.861218 Write leveling : PASS
4886 00:41:14.864600 RX DQS gating : PASS
4887 00:41:14.864683 RX DQ/DQS(RDDQC) : PASS
4888 00:41:14.867989 TX DQ/DQS : PASS
4889 00:41:14.870992 RX DATLAT : PASS
4890 00:41:14.871070 RX DQ/DQS(Engine): PASS
4891 00:41:14.874590 TX OE : NO K
4892 00:41:14.874667 All Pass.
4893 00:41:14.874727
4894 00:41:14.877667 CH 1, Rank 1
4895 00:41:14.877744 SW Impedance : PASS
4896 00:41:14.881010 DUTY Scan : NO K
4897 00:41:14.884997 ZQ Calibration : PASS
4898 00:41:14.885074 Jitter Meter : NO K
4899 00:41:14.888060 CBT Training : PASS
4900 00:41:14.891334 Write leveling : PASS
4901 00:41:14.891412 RX DQS gating : PASS
4902 00:41:14.894739 RX DQ/DQS(RDDQC) : PASS
4903 00:41:14.898095 TX DQ/DQS : PASS
4904 00:41:14.898172 RX DATLAT : PASS
4905 00:41:14.900963 RX DQ/DQS(Engine): PASS
4906 00:41:14.904405 TX OE : NO K
4907 00:41:14.904507 All Pass.
4908 00:41:14.904592
4909 00:41:14.904712 DramC Write-DBI off
4910 00:41:14.907828 PER_BANK_REFRESH: Hybrid Mode
4911 00:41:14.911285 TX_TRACKING: ON
4912 00:41:14.917610 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4913 00:41:14.921160 [FAST_K] Save calibration result to emmc
4914 00:41:14.927924 dramc_set_vcore_voltage set vcore to 662500
4915 00:41:14.928001 Read voltage for 933, 3
4916 00:41:14.930758 Vio18 = 0
4917 00:41:14.930834 Vcore = 662500
4918 00:41:14.930894 Vdram = 0
4919 00:41:14.930951 Vddq = 0
4920 00:41:14.934181 Vmddr = 0
4921 00:41:14.937634 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4922 00:41:14.944335 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4923 00:41:14.947691 MEM_TYPE=3, freq_sel=17
4924 00:41:14.947767 sv_algorithm_assistance_LP4_1600
4925 00:41:14.954320 ============ PULL DRAM RESETB DOWN ============
4926 00:41:14.957620 ========== PULL DRAM RESETB DOWN end =========
4927 00:41:14.960922 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4928 00:41:14.964261 ===================================
4929 00:41:14.967179 LPDDR4 DRAM CONFIGURATION
4930 00:41:14.970376 ===================================
4931 00:41:14.974032 EX_ROW_EN[0] = 0x0
4932 00:41:14.974109 EX_ROW_EN[1] = 0x0
4933 00:41:14.977053 LP4Y_EN = 0x0
4934 00:41:14.977130 WORK_FSP = 0x0
4935 00:41:14.980233 WL = 0x3
4936 00:41:14.980309 RL = 0x3
4937 00:41:14.983696 BL = 0x2
4938 00:41:14.983773 RPST = 0x0
4939 00:41:14.987367 RD_PRE = 0x0
4940 00:41:14.987444 WR_PRE = 0x1
4941 00:41:14.990662 WR_PST = 0x0
4942 00:41:14.993952 DBI_WR = 0x0
4943 00:41:14.994029 DBI_RD = 0x0
4944 00:41:14.997039 OTF = 0x1
4945 00:41:15.000289 ===================================
4946 00:41:15.003654 ===================================
4947 00:41:15.003731 ANA top config
4948 00:41:15.006744 ===================================
4949 00:41:15.010338 DLL_ASYNC_EN = 0
4950 00:41:15.013304 ALL_SLAVE_EN = 1
4951 00:41:15.013384 NEW_RANK_MODE = 1
4952 00:41:15.016855 DLL_IDLE_MODE = 1
4953 00:41:15.020238 LP45_APHY_COMB_EN = 1
4954 00:41:15.023787 TX_ODT_DIS = 1
4955 00:41:15.023866 NEW_8X_MODE = 1
4956 00:41:15.026673 ===================================
4957 00:41:15.030004 ===================================
4958 00:41:15.033432 data_rate = 1866
4959 00:41:15.036930 CKR = 1
4960 00:41:15.039931 DQ_P2S_RATIO = 8
4961 00:41:15.043398 ===================================
4962 00:41:15.046806 CA_P2S_RATIO = 8
4963 00:41:15.050297 DQ_CA_OPEN = 0
4964 00:41:15.050374 DQ_SEMI_OPEN = 0
4965 00:41:15.053673 CA_SEMI_OPEN = 0
4966 00:41:15.056818 CA_FULL_RATE = 0
4967 00:41:15.059868 DQ_CKDIV4_EN = 1
4968 00:41:15.063301 CA_CKDIV4_EN = 1
4969 00:41:15.066638 CA_PREDIV_EN = 0
4970 00:41:15.066715 PH8_DLY = 0
4971 00:41:15.069871 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4972 00:41:15.073069 DQ_AAMCK_DIV = 4
4973 00:41:15.077024 CA_AAMCK_DIV = 4
4974 00:41:15.079692 CA_ADMCK_DIV = 4
4975 00:41:15.083304 DQ_TRACK_CA_EN = 0
4976 00:41:15.083381 CA_PICK = 933
4977 00:41:15.086407 CA_MCKIO = 933
4978 00:41:15.089936 MCKIO_SEMI = 0
4979 00:41:15.093640 PLL_FREQ = 3732
4980 00:41:15.096834 DQ_UI_PI_RATIO = 32
4981 00:41:15.100215 CA_UI_PI_RATIO = 0
4982 00:41:15.103576 ===================================
4983 00:41:15.106811 ===================================
4984 00:41:15.106889 memory_type:LPDDR4
4985 00:41:15.110007 GP_NUM : 10
4986 00:41:15.113451 SRAM_EN : 1
4987 00:41:15.113528 MD32_EN : 0
4988 00:41:15.116386 ===================================
4989 00:41:15.119602 [ANA_INIT] >>>>>>>>>>>>>>
4990 00:41:15.123070 <<<<<< [CONFIGURE PHASE]: ANA_TX
4991 00:41:15.126493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4992 00:41:15.129927 ===================================
4993 00:41:15.132803 data_rate = 1866,PCW = 0X8f00
4994 00:41:15.136319 ===================================
4995 00:41:15.139731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4996 00:41:15.143175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4997 00:41:15.150021 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4998 00:41:15.152911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4999 00:41:15.156385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5000 00:41:15.162799 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5001 00:41:15.162877 [ANA_INIT] flow start
5002 00:41:15.166285 [ANA_INIT] PLL >>>>>>>>
5003 00:41:15.169665 [ANA_INIT] PLL <<<<<<<<
5004 00:41:15.169742 [ANA_INIT] MIDPI >>>>>>>>
5005 00:41:15.172950 [ANA_INIT] MIDPI <<<<<<<<
5006 00:41:15.175966 [ANA_INIT] DLL >>>>>>>>
5007 00:41:15.176043 [ANA_INIT] flow end
5008 00:41:15.179646 ============ LP4 DIFF to SE enter ============
5009 00:41:15.186082 ============ LP4 DIFF to SE exit ============
5010 00:41:15.186159 [ANA_INIT] <<<<<<<<<<<<<
5011 00:41:15.189552 [Flow] Enable top DCM control >>>>>
5012 00:41:15.192828 [Flow] Enable top DCM control <<<<<
5013 00:41:15.195766 Enable DLL master slave shuffle
5014 00:41:15.202716 ==============================================================
5015 00:41:15.205879 Gating Mode config
5016 00:41:15.208977 ==============================================================
5017 00:41:15.212441 Config description:
5018 00:41:15.222652 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5019 00:41:15.228790 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5020 00:41:15.232439 SELPH_MODE 0: By rank 1: By Phase
5021 00:41:15.239198 ==============================================================
5022 00:41:15.242065 GAT_TRACK_EN = 1
5023 00:41:15.245349 RX_GATING_MODE = 2
5024 00:41:15.248804 RX_GATING_TRACK_MODE = 2
5025 00:41:15.248918 SELPH_MODE = 1
5026 00:41:15.252386 PICG_EARLY_EN = 1
5027 00:41:15.255325 VALID_LAT_VALUE = 1
5028 00:41:15.262165 ==============================================================
5029 00:41:15.265583 Enter into Gating configuration >>>>
5030 00:41:15.268557 Exit from Gating configuration <<<<
5031 00:41:15.271955 Enter into DVFS_PRE_config >>>>>
5032 00:41:15.282115 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5033 00:41:15.285514 Exit from DVFS_PRE_config <<<<<
5034 00:41:15.288772 Enter into PICG configuration >>>>
5035 00:41:15.291815 Exit from PICG configuration <<<<
5036 00:41:15.295569 [RX_INPUT] configuration >>>>>
5037 00:41:15.298423 [RX_INPUT] configuration <<<<<
5038 00:41:15.302134 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5039 00:41:15.308604 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5040 00:41:15.315112 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5041 00:41:15.321808 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5042 00:41:15.328554 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5043 00:41:15.331675 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5044 00:41:15.338962 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5045 00:41:15.341813 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5046 00:41:15.345182 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5047 00:41:15.348610 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5048 00:41:15.351579 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5049 00:41:15.358348 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5050 00:41:15.361838 ===================================
5051 00:41:15.364835 LPDDR4 DRAM CONFIGURATION
5052 00:41:15.368316 ===================================
5053 00:41:15.368395 EX_ROW_EN[0] = 0x0
5054 00:41:15.371754 EX_ROW_EN[1] = 0x0
5055 00:41:15.371855 LP4Y_EN = 0x0
5056 00:41:15.375211 WORK_FSP = 0x0
5057 00:41:15.375291 WL = 0x3
5058 00:41:15.378048 RL = 0x3
5059 00:41:15.378161 BL = 0x2
5060 00:41:15.381308 RPST = 0x0
5061 00:41:15.381425 RD_PRE = 0x0
5062 00:41:15.384606 WR_PRE = 0x1
5063 00:41:15.384742 WR_PST = 0x0
5064 00:41:15.388027 DBI_WR = 0x0
5065 00:41:15.388119 DBI_RD = 0x0
5066 00:41:15.391679 OTF = 0x1
5067 00:41:15.395091 ===================================
5068 00:41:15.398045 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5069 00:41:15.401280 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5070 00:41:15.408345 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5071 00:41:15.411565 ===================================
5072 00:41:15.411645 LPDDR4 DRAM CONFIGURATION
5073 00:41:15.414627 ===================================
5074 00:41:15.418246 EX_ROW_EN[0] = 0x10
5075 00:41:15.421486 EX_ROW_EN[1] = 0x0
5076 00:41:15.421564 LP4Y_EN = 0x0
5077 00:41:15.424587 WORK_FSP = 0x0
5078 00:41:15.424705 WL = 0x3
5079 00:41:15.427718 RL = 0x3
5080 00:41:15.427794 BL = 0x2
5081 00:41:15.431082 RPST = 0x0
5082 00:41:15.431159 RD_PRE = 0x0
5083 00:41:15.434389 WR_PRE = 0x1
5084 00:41:15.434466 WR_PST = 0x0
5085 00:41:15.438083 DBI_WR = 0x0
5086 00:41:15.438160 DBI_RD = 0x0
5087 00:41:15.441069 OTF = 0x1
5088 00:41:15.444594 ===================================
5089 00:41:15.451094 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5090 00:41:15.454224 nWR fixed to 30
5091 00:41:15.457534 [ModeRegInit_LP4] CH0 RK0
5092 00:41:15.457613 [ModeRegInit_LP4] CH0 RK1
5093 00:41:15.460999 [ModeRegInit_LP4] CH1 RK0
5094 00:41:15.464344 [ModeRegInit_LP4] CH1 RK1
5095 00:41:15.464446 match AC timing 9
5096 00:41:15.471298 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5097 00:41:15.474295 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5098 00:41:15.477739 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5099 00:41:15.484612 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5100 00:41:15.487801 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5101 00:41:15.487878 ==
5102 00:41:15.490718 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 00:41:15.494250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 00:41:15.494328 ==
5105 00:41:15.501160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5106 00:41:15.507791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5107 00:41:15.510872 [CA 0] Center 38 (8~69) winsize 62
5108 00:41:15.514222 [CA 1] Center 38 (7~69) winsize 63
5109 00:41:15.517472 [CA 2] Center 36 (6~66) winsize 61
5110 00:41:15.520615 [CA 3] Center 35 (4~66) winsize 63
5111 00:41:15.524115 [CA 4] Center 34 (4~65) winsize 62
5112 00:41:15.527237 [CA 5] Center 33 (3~64) winsize 62
5113 00:41:15.527316
5114 00:41:15.531065 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5115 00:41:15.531143
5116 00:41:15.533924 [CATrainingPosCal] consider 1 rank data
5117 00:41:15.537238 u2DelayCellTimex100 = 270/100 ps
5118 00:41:15.541140 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5119 00:41:15.544181 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5120 00:41:15.547260 CA2 delay=36 (6~66),Diff = 3 PI (18 cell)
5121 00:41:15.551164 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5122 00:41:15.553900 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5123 00:41:15.557190 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5124 00:41:15.560811
5125 00:41:15.564304 CA PerBit enable=1, Macro0, CA PI delay=33
5126 00:41:15.564381
5127 00:41:15.567197 [CBTSetCACLKResult] CA Dly = 33
5128 00:41:15.567274 CS Dly: 6 (0~37)
5129 00:41:15.567334 ==
5130 00:41:15.570638 Dram Type= 6, Freq= 0, CH_0, rank 1
5131 00:41:15.574096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 00:41:15.574176 ==
5133 00:41:15.580379 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5134 00:41:15.587089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5135 00:41:15.590415 [CA 0] Center 38 (8~69) winsize 62
5136 00:41:15.593782 [CA 1] Center 38 (7~69) winsize 63
5137 00:41:15.597343 [CA 2] Center 35 (5~66) winsize 62
5138 00:41:15.600254 [CA 3] Center 35 (5~66) winsize 62
5139 00:41:15.603707 [CA 4] Center 34 (3~65) winsize 63
5140 00:41:15.607213 [CA 5] Center 33 (3~64) winsize 62
5141 00:41:15.607319
5142 00:41:15.610593 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5143 00:41:15.610670
5144 00:41:15.613851 [CATrainingPosCal] consider 2 rank data
5145 00:41:15.616974 u2DelayCellTimex100 = 270/100 ps
5146 00:41:15.620348 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5147 00:41:15.623774 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5148 00:41:15.627343 CA2 delay=36 (6~66),Diff = 3 PI (18 cell)
5149 00:41:15.630603 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5150 00:41:15.633677 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5151 00:41:15.640839 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5152 00:41:15.640922
5153 00:41:15.643698 CA PerBit enable=1, Macro0, CA PI delay=33
5154 00:41:15.643775
5155 00:41:15.646890 [CBTSetCACLKResult] CA Dly = 33
5156 00:41:15.646966 CS Dly: 6 (0~38)
5157 00:41:15.647029
5158 00:41:15.650239 ----->DramcWriteLeveling(PI) begin...
5159 00:41:15.650319 ==
5160 00:41:15.653657 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 00:41:15.660185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 00:41:15.660263 ==
5163 00:41:15.663589 Write leveling (Byte 0): 32 => 32
5164 00:41:15.663657 Write leveling (Byte 1): 31 => 31
5165 00:41:15.667038 DramcWriteLeveling(PI) end<-----
5166 00:41:15.667118
5167 00:41:15.667196 ==
5168 00:41:15.670350 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 00:41:15.677363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 00:41:15.677440 ==
5171 00:41:15.681097 [Gating] SW mode calibration
5172 00:41:15.686900 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5173 00:41:15.690274 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5174 00:41:15.696961 0 14 0 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
5175 00:41:15.699901 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5176 00:41:15.703428 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 00:41:15.710405 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 00:41:15.713333 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 00:41:15.716677 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 00:41:15.723716 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 00:41:15.726983 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5182 00:41:15.730268 0 15 0 | B1->B0 | 3333 2c2c | 1 0 | (1 1) (1 0)
5183 00:41:15.736915 0 15 4 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
5184 00:41:15.740059 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 00:41:15.743095 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 00:41:15.747087 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 00:41:15.753585 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 00:41:15.756832 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 00:41:15.760077 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 00:41:15.766509 1 0 0 | B1->B0 | 2f2f 4545 | 1 0 | (0 0) (0 0)
5191 00:41:15.769833 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5192 00:41:15.773307 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 00:41:15.779559 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 00:41:15.783522 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 00:41:15.786633 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 00:41:15.792891 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 00:41:15.796256 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 00:41:15.799678 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5199 00:41:15.806057 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 00:41:15.809600 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 00:41:15.812983 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 00:41:15.819296 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 00:41:15.822758 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 00:41:15.825727 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 00:41:15.832615 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 00:41:15.835881 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 00:41:15.839370 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 00:41:15.845950 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 00:41:15.849485 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 00:41:15.852337 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 00:41:15.859084 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 00:41:15.862394 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 00:41:15.865241 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5214 00:41:15.872159 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5215 00:41:15.875447 Total UI for P1: 0, mck2ui 16
5216 00:41:15.878872 best dqsien dly found for B0: ( 1, 2, 28)
5217 00:41:15.882409 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5218 00:41:15.885759 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 00:41:15.888629 Total UI for P1: 0, mck2ui 16
5220 00:41:15.892156 best dqsien dly found for B1: ( 1, 3, 2)
5221 00:41:15.895131 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5222 00:41:15.898585 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5223 00:41:15.901698
5224 00:41:15.905024 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5225 00:41:15.908733 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5226 00:41:15.911829 [Gating] SW calibration Done
5227 00:41:15.911905 ==
5228 00:41:15.914907 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 00:41:15.918485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 00:41:15.918562 ==
5231 00:41:15.918623 RX Vref Scan: 0
5232 00:41:15.918678
5233 00:41:15.921463 RX Vref 0 -> 0, step: 1
5234 00:41:15.921539
5235 00:41:15.924912 RX Delay -80 -> 252, step: 8
5236 00:41:15.928440 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5237 00:41:15.931853 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5238 00:41:15.934765 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5239 00:41:15.941448 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5240 00:41:15.944744 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5241 00:41:15.948211 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5242 00:41:15.951607 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5243 00:41:15.954801 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5244 00:41:15.958190 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5245 00:41:15.964781 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5246 00:41:15.968075 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5247 00:41:15.971756 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5248 00:41:15.975133 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5249 00:41:15.981392 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5250 00:41:15.985174 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5251 00:41:15.988160 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5252 00:41:15.988254 ==
5253 00:41:15.991554 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 00:41:15.994956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 00:41:15.995034 ==
5256 00:41:15.997924 DQS Delay:
5257 00:41:15.998000 DQS0 = 0, DQS1 = 0
5258 00:41:15.998060 DQM Delay:
5259 00:41:16.001496 DQM0 = 95, DQM1 = 83
5260 00:41:16.001571 DQ Delay:
5261 00:41:16.004737 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5262 00:41:16.008515 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5263 00:41:16.011897 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5264 00:41:16.014636 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5265 00:41:16.014712
5266 00:41:16.014771
5267 00:41:16.014825 ==
5268 00:41:16.018132 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 00:41:16.024852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 00:41:16.024928 ==
5271 00:41:16.024987
5272 00:41:16.025041
5273 00:41:16.028119 TX Vref Scan disable
5274 00:41:16.028209 == TX Byte 0 ==
5275 00:41:16.031415 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5276 00:41:16.037777 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5277 00:41:16.037854 == TX Byte 1 ==
5278 00:41:16.041153 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5279 00:41:16.048200 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5280 00:41:16.048277 ==
5281 00:41:16.051199 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 00:41:16.054690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 00:41:16.054767 ==
5284 00:41:16.054826
5285 00:41:16.054881
5286 00:41:16.058038 TX Vref Scan disable
5287 00:41:16.061413 == TX Byte 0 ==
5288 00:41:16.064835 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5289 00:41:16.067658 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5290 00:41:16.071071 == TX Byte 1 ==
5291 00:41:16.074844 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5292 00:41:16.077689 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5293 00:41:16.077766
5294 00:41:16.077825 [DATLAT]
5295 00:41:16.080951 Freq=933, CH0 RK0
5296 00:41:16.081027
5297 00:41:16.084441 DATLAT Default: 0xd
5298 00:41:16.084516 0, 0xFFFF, sum = 0
5299 00:41:16.087592 1, 0xFFFF, sum = 0
5300 00:41:16.087670 2, 0xFFFF, sum = 0
5301 00:41:16.091207 3, 0xFFFF, sum = 0
5302 00:41:16.091284 4, 0xFFFF, sum = 0
5303 00:41:16.094585 5, 0xFFFF, sum = 0
5304 00:41:16.094662 6, 0xFFFF, sum = 0
5305 00:41:16.097632 7, 0xFFFF, sum = 0
5306 00:41:16.097710 8, 0xFFFF, sum = 0
5307 00:41:16.100994 9, 0xFFFF, sum = 0
5308 00:41:16.101071 10, 0x0, sum = 1
5309 00:41:16.104277 11, 0x0, sum = 2
5310 00:41:16.104355 12, 0x0, sum = 3
5311 00:41:16.107713 13, 0x0, sum = 4
5312 00:41:16.107790 best_step = 11
5313 00:41:16.107850
5314 00:41:16.107913 ==
5315 00:41:16.111345 Dram Type= 6, Freq= 0, CH_0, rank 0
5316 00:41:16.114062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 00:41:16.114162 ==
5318 00:41:16.117411 RX Vref Scan: 1
5319 00:41:16.117480
5320 00:41:16.120881 RX Vref 0 -> 0, step: 1
5321 00:41:16.120957
5322 00:41:16.121023 RX Delay -69 -> 252, step: 4
5323 00:41:16.121098
5324 00:41:16.124234 Set Vref, RX VrefLevel [Byte0]: 62
5325 00:41:16.127660 [Byte1]: 52
5326 00:41:16.132192
5327 00:41:16.132285 Final RX Vref Byte 0 = 62 to rank0
5328 00:41:16.136001 Final RX Vref Byte 1 = 52 to rank0
5329 00:41:16.138951 Final RX Vref Byte 0 = 62 to rank1
5330 00:41:16.142764 Final RX Vref Byte 1 = 52 to rank1==
5331 00:41:16.145752 Dram Type= 6, Freq= 0, CH_0, rank 0
5332 00:41:16.152739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 00:41:16.152811 ==
5334 00:41:16.152869 DQS Delay:
5335 00:41:16.152933 DQS0 = 0, DQS1 = 0
5336 00:41:16.155844 DQM Delay:
5337 00:41:16.155933 DQM0 = 95, DQM1 = 83
5338 00:41:16.159300 DQ Delay:
5339 00:41:16.162681 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =94
5340 00:41:16.166024 DQ4 =94, DQ5 =84, DQ6 =102, DQ7 =108
5341 00:41:16.169361 DQ8 =78, DQ9 =70, DQ10 =82, DQ11 =78
5342 00:41:16.172775 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =90
5343 00:41:16.172844
5344 00:41:16.172899
5345 00:41:16.179128 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 413 ps
5346 00:41:16.182554 CH0 RK0: MR19=505, MR18=1B1A
5347 00:41:16.189100 CH0_RK0: MR19=0x505, MR18=0x1B1A, DQSOSC=413, MR23=63, INC=63, DEC=42
5348 00:41:16.189178
5349 00:41:16.192159 ----->DramcWriteLeveling(PI) begin...
5350 00:41:16.192239 ==
5351 00:41:16.195556 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 00:41:16.198843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 00:41:16.198920 ==
5354 00:41:16.202172 Write leveling (Byte 0): 34 => 34
5355 00:41:16.205219 Write leveling (Byte 1): 30 => 30
5356 00:41:16.208553 DramcWriteLeveling(PI) end<-----
5357 00:41:16.208632
5358 00:41:16.208715 ==
5359 00:41:16.212003 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 00:41:16.215431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 00:41:16.215508 ==
5362 00:41:16.218667 [Gating] SW mode calibration
5363 00:41:16.225254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5364 00:41:16.232034 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5365 00:41:16.235401 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5366 00:41:16.242316 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 00:41:16.245151 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 00:41:16.248532 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 00:41:16.255129 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 00:41:16.258788 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 00:41:16.261634 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5372 00:41:16.268392 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (1 1)
5373 00:41:16.271632 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5374 00:41:16.275034 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 00:41:16.278409 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 00:41:16.284961 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 00:41:16.288427 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 00:41:16.291873 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 00:41:16.298182 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 00:41:16.301701 0 15 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
5381 00:41:16.304986 1 0 0 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5382 00:41:16.311454 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 00:41:16.315046 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 00:41:16.318417 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 00:41:16.324871 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 00:41:16.328262 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 00:41:16.331638 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 00:41:16.338189 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 00:41:16.341618 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5390 00:41:16.344886 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 00:41:16.351424 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 00:41:16.354779 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 00:41:16.358155 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 00:41:16.364996 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 00:41:16.367711 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 00:41:16.371083 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 00:41:16.377941 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 00:41:16.381227 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 00:41:16.384603 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 00:41:16.390641 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 00:41:16.394171 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 00:41:16.397612 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 00:41:16.404433 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 00:41:16.407234 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5405 00:41:16.410625 Total UI for P1: 0, mck2ui 16
5406 00:41:16.414150 best dqsien dly found for B0: ( 1, 2, 26)
5407 00:41:16.417447 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5408 00:41:16.424007 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 00:41:16.424154 Total UI for P1: 0, mck2ui 16
5410 00:41:16.430419 best dqsien dly found for B1: ( 1, 2, 30)
5411 00:41:16.433688 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5412 00:41:16.436918 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5413 00:41:16.436987
5414 00:41:16.440577 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5415 00:41:16.443745 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5416 00:41:16.447106 [Gating] SW calibration Done
5417 00:41:16.447197 ==
5418 00:41:16.450640 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 00:41:16.453512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 00:41:16.453595 ==
5421 00:41:16.457047 RX Vref Scan: 0
5422 00:41:16.457114
5423 00:41:16.457169 RX Vref 0 -> 0, step: 1
5424 00:41:16.460479
5425 00:41:16.460566 RX Delay -80 -> 252, step: 8
5426 00:41:16.466719 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5427 00:41:16.469934 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5428 00:41:16.473405 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5429 00:41:16.476835 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5430 00:41:16.480015 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5431 00:41:16.483364 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5432 00:41:16.490198 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5433 00:41:16.493111 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5434 00:41:16.496338 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5435 00:41:16.499942 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5436 00:41:16.503401 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5437 00:41:16.509595 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5438 00:41:16.513035 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5439 00:41:16.516495 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5440 00:41:16.519966 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5441 00:41:16.523375 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5442 00:41:16.523468 ==
5443 00:41:16.526288 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 00:41:16.533016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 00:41:16.533091 ==
5446 00:41:16.533149 DQS Delay:
5447 00:41:16.536241 DQS0 = 0, DQS1 = 0
5448 00:41:16.536340 DQM Delay:
5449 00:41:16.536421 DQM0 = 92, DQM1 = 83
5450 00:41:16.540019 DQ Delay:
5451 00:41:16.543142 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87
5452 00:41:16.546568 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =107
5453 00:41:16.549886 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =79
5454 00:41:16.552964 DQ12 =91, DQ13 =87, DQ14 =95, DQ15 =87
5455 00:41:16.553059
5456 00:41:16.553147
5457 00:41:16.553235 ==
5458 00:41:16.556568 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 00:41:16.559898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 00:41:16.560027 ==
5461 00:41:16.560153
5462 00:41:16.560247
5463 00:41:16.562883 TX Vref Scan disable
5464 00:41:16.566347 == TX Byte 0 ==
5465 00:41:16.569841 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5466 00:41:16.573299 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5467 00:41:16.576107 == TX Byte 1 ==
5468 00:41:16.579486 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5469 00:41:16.583354 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5470 00:41:16.583448 ==
5471 00:41:16.586193 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 00:41:16.589497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 00:41:16.589569 ==
5474 00:41:16.592925
5475 00:41:16.593039
5476 00:41:16.593174 TX Vref Scan disable
5477 00:41:16.596161 == TX Byte 0 ==
5478 00:41:16.599673 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5479 00:41:16.606492 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5480 00:41:16.606640 == TX Byte 1 ==
5481 00:41:16.609723 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5482 00:41:16.616423 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5483 00:41:16.616520
5484 00:41:16.616605 [DATLAT]
5485 00:41:16.616721 Freq=933, CH0 RK1
5486 00:41:16.616803
5487 00:41:16.619376 DATLAT Default: 0xb
5488 00:41:16.619463 0, 0xFFFF, sum = 0
5489 00:41:16.623165 1, 0xFFFF, sum = 0
5490 00:41:16.623264 2, 0xFFFF, sum = 0
5491 00:41:16.626043 3, 0xFFFF, sum = 0
5492 00:41:16.629574 4, 0xFFFF, sum = 0
5493 00:41:16.629639 5, 0xFFFF, sum = 0
5494 00:41:16.632812 6, 0xFFFF, sum = 0
5495 00:41:16.632881 7, 0xFFFF, sum = 0
5496 00:41:16.636226 8, 0xFFFF, sum = 0
5497 00:41:16.636321 9, 0xFFFF, sum = 0
5498 00:41:16.639659 10, 0x0, sum = 1
5499 00:41:16.639752 11, 0x0, sum = 2
5500 00:41:16.642882 12, 0x0, sum = 3
5501 00:41:16.642971 13, 0x0, sum = 4
5502 00:41:16.643055 best_step = 11
5503 00:41:16.643137
5504 00:41:16.646322 ==
5505 00:41:16.649653 Dram Type= 6, Freq= 0, CH_0, rank 1
5506 00:41:16.653028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 00:41:16.653099 ==
5508 00:41:16.653155 RX Vref Scan: 0
5509 00:41:16.653208
5510 00:41:16.655878 RX Vref 0 -> 0, step: 1
5511 00:41:16.655942
5512 00:41:16.659548 RX Delay -77 -> 252, step: 4
5513 00:41:16.662554 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5514 00:41:16.669450 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5515 00:41:16.672899 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5516 00:41:16.675933 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5517 00:41:16.679223 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5518 00:41:16.682518 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5519 00:41:16.686045 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5520 00:41:16.693034 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5521 00:41:16.696237 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5522 00:41:16.699400 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5523 00:41:16.702894 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5524 00:41:16.709342 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5525 00:41:16.712231 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5526 00:41:16.715626 iDelay=199, Bit 13, Center 90 (-5 ~ 186) 192
5527 00:41:16.719118 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5528 00:41:16.722469 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5529 00:41:16.722547 ==
5530 00:41:16.725650 Dram Type= 6, Freq= 0, CH_0, rank 1
5531 00:41:16.732380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 00:41:16.732473 ==
5533 00:41:16.732533 DQS Delay:
5534 00:41:16.732588 DQS0 = 0, DQS1 = 0
5535 00:41:16.735725 DQM Delay:
5536 00:41:16.735802 DQM0 = 92, DQM1 = 84
5537 00:41:16.738991 DQ Delay:
5538 00:41:16.742579 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5539 00:41:16.745786 DQ4 =90, DQ5 =82, DQ6 =104, DQ7 =104
5540 00:41:16.749074 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =76
5541 00:41:16.752612 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5542 00:41:16.752694
5543 00:41:16.752754
5544 00:41:16.758962 [DQSOSCAuto] RK1, (LSB)MR18= 0x3415, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
5545 00:41:16.762313 CH0 RK1: MR19=505, MR18=3415
5546 00:41:16.768869 CH0_RK1: MR19=0x505, MR18=0x3415, DQSOSC=405, MR23=63, INC=66, DEC=44
5547 00:41:16.772148 [RxdqsGatingPostProcess] freq 933
5548 00:41:16.775360 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5549 00:41:16.778926 best DQS0 dly(2T, 0.5T) = (0, 10)
5550 00:41:16.782147 best DQS1 dly(2T, 0.5T) = (0, 11)
5551 00:41:16.785512 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5552 00:41:16.788722 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5553 00:41:16.792510 best DQS0 dly(2T, 0.5T) = (0, 10)
5554 00:41:16.795399 best DQS1 dly(2T, 0.5T) = (0, 10)
5555 00:41:16.798687 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5556 00:41:16.802011 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5557 00:41:16.805599 Pre-setting of DQS Precalculation
5558 00:41:16.808824 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5559 00:41:16.808924 ==
5560 00:41:16.812059 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 00:41:16.818626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 00:41:16.818703 ==
5563 00:41:16.821911 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5564 00:41:16.828370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5565 00:41:16.831799 [CA 0] Center 37 (7~67) winsize 61
5566 00:41:16.835127 [CA 1] Center 37 (7~68) winsize 62
5567 00:41:16.838350 [CA 2] Center 34 (5~64) winsize 60
5568 00:41:16.841919 [CA 3] Center 34 (5~64) winsize 60
5569 00:41:16.845313 [CA 4] Center 35 (5~65) winsize 61
5570 00:41:16.848775 [CA 5] Center 33 (4~63) winsize 60
5571 00:41:16.848845
5572 00:41:16.851807 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5573 00:41:16.851874
5574 00:41:16.855226 [CATrainingPosCal] consider 1 rank data
5575 00:41:16.858776 u2DelayCellTimex100 = 270/100 ps
5576 00:41:16.861534 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5577 00:41:16.868579 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5578 00:41:16.871943 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5579 00:41:16.875320 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5580 00:41:16.878284 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5581 00:41:16.881669 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5582 00:41:16.881745
5583 00:41:16.885071 CA PerBit enable=1, Macro0, CA PI delay=33
5584 00:41:16.885147
5585 00:41:16.888354 [CBTSetCACLKResult] CA Dly = 33
5586 00:41:16.888430 CS Dly: 6 (0~37)
5587 00:41:16.891758 ==
5588 00:41:16.894654 Dram Type= 6, Freq= 0, CH_1, rank 1
5589 00:41:16.898136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5590 00:41:16.898212 ==
5591 00:41:16.901734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5592 00:41:16.908091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5593 00:41:16.911911 [CA 0] Center 38 (8~68) winsize 61
5594 00:41:16.915300 [CA 1] Center 37 (7~68) winsize 62
5595 00:41:16.918723 [CA 2] Center 35 (5~65) winsize 61
5596 00:41:16.922052 [CA 3] Center 34 (4~64) winsize 61
5597 00:41:16.924932 [CA 4] Center 34 (4~65) winsize 62
5598 00:41:16.929042 [CA 5] Center 33 (3~64) winsize 62
5599 00:41:16.929118
5600 00:41:16.931698 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5601 00:41:16.931774
5602 00:41:16.935579 [CATrainingPosCal] consider 2 rank data
5603 00:41:16.938601 u2DelayCellTimex100 = 270/100 ps
5604 00:41:16.941929 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5605 00:41:16.948893 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5606 00:41:16.951893 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5607 00:41:16.955043 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5608 00:41:16.958432 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5609 00:41:16.961771 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5610 00:41:16.961870
5611 00:41:16.965047 CA PerBit enable=1, Macro0, CA PI delay=33
5612 00:41:16.965123
5613 00:41:16.968776 [CBTSetCACLKResult] CA Dly = 33
5614 00:41:16.968852 CS Dly: 7 (0~39)
5615 00:41:16.971754
5616 00:41:16.975185 ----->DramcWriteLeveling(PI) begin...
5617 00:41:16.975263 ==
5618 00:41:16.978202 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 00:41:16.981706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 00:41:16.981784 ==
5621 00:41:16.985084 Write leveling (Byte 0): 24 => 24
5622 00:41:16.988595 Write leveling (Byte 1): 28 => 28
5623 00:41:16.991605 DramcWriteLeveling(PI) end<-----
5624 00:41:16.991675
5625 00:41:16.991732 ==
5626 00:41:16.994816 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 00:41:16.998065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 00:41:16.998134 ==
5629 00:41:17.001309 [Gating] SW mode calibration
5630 00:41:17.008217 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5631 00:41:17.014569 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5632 00:41:17.017956 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 00:41:17.021338 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 00:41:17.028121 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 00:41:17.031756 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 00:41:17.035088 0 14 16 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
5637 00:41:17.041126 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 00:41:17.044844 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 00:41:17.048099 0 14 28 | B1->B0 | 2d2d 2a2a | 0 0 | (0 1) (0 0)
5640 00:41:17.054439 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5641 00:41:17.057943 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 00:41:17.061364 0 15 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5643 00:41:17.067675 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 00:41:17.071343 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 00:41:17.074176 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 00:41:17.080780 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 00:41:17.084148 0 15 28 | B1->B0 | 3232 3030 | 0 1 | (0 0) (0 0)
5648 00:41:17.087545 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 00:41:17.093899 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 00:41:17.097290 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 00:41:17.100581 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 00:41:17.107693 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 00:41:17.110518 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 00:41:17.113973 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 00:41:17.120657 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5656 00:41:17.123740 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 00:41:17.127070 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 00:41:17.133518 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 00:41:17.136838 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 00:41:17.140422 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 00:41:17.147151 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 00:41:17.150094 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 00:41:17.153295 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 00:41:17.160022 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 00:41:17.163263 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 00:41:17.166626 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 00:41:17.173210 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 00:41:17.176585 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 00:41:17.180067 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 00:41:17.183282 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 00:41:17.189922 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5672 00:41:17.193015 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5673 00:41:17.196801 Total UI for P1: 0, mck2ui 16
5674 00:41:17.199610 best dqsien dly found for B0: ( 1, 2, 28)
5675 00:41:17.203192 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 00:41:17.206441 Total UI for P1: 0, mck2ui 16
5677 00:41:17.209762 best dqsien dly found for B1: ( 1, 2, 30)
5678 00:41:17.213053 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5679 00:41:17.219838 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5680 00:41:17.219915
5681 00:41:17.223117 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5682 00:41:17.226321 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5683 00:41:17.229907 [Gating] SW calibration Done
5684 00:41:17.229983 ==
5685 00:41:17.233268 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 00:41:17.236293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 00:41:17.236370 ==
5688 00:41:17.236429 RX Vref Scan: 0
5689 00:41:17.236484
5690 00:41:17.239945 RX Vref 0 -> 0, step: 1
5691 00:41:17.240022
5692 00:41:17.243310 RX Delay -80 -> 252, step: 8
5693 00:41:17.246349 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5694 00:41:17.249714 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5695 00:41:17.256648 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5696 00:41:17.259966 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5697 00:41:17.262992 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5698 00:41:17.266301 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5699 00:41:17.269521 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5700 00:41:17.273385 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5701 00:41:17.279586 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5702 00:41:17.283241 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5703 00:41:17.286494 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5704 00:41:17.289407 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5705 00:41:17.292844 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5706 00:41:17.299526 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5707 00:41:17.302755 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5708 00:41:17.306118 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5709 00:41:17.306195 ==
5710 00:41:17.309304 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 00:41:17.312998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 00:41:17.313075 ==
5713 00:41:17.316193 DQS Delay:
5714 00:41:17.316270 DQS0 = 0, DQS1 = 0
5715 00:41:17.319290 DQM Delay:
5716 00:41:17.319367 DQM0 = 94, DQM1 = 87
5717 00:41:17.319427 DQ Delay:
5718 00:41:17.322756 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5719 00:41:17.326112 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5720 00:41:17.329656 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5721 00:41:17.332921 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5722 00:41:17.332984
5723 00:41:17.333040
5724 00:41:17.335968 ==
5725 00:41:17.339228 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 00:41:17.342521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 00:41:17.342602 ==
5728 00:41:17.342661
5729 00:41:17.342748
5730 00:41:17.345720 TX Vref Scan disable
5731 00:41:17.345796 == TX Byte 0 ==
5732 00:41:17.349372 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5733 00:41:17.355613 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5734 00:41:17.355683 == TX Byte 1 ==
5735 00:41:17.359126 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5736 00:41:17.365848 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5737 00:41:17.365919 ==
5738 00:41:17.369242 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 00:41:17.372118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 00:41:17.372195 ==
5741 00:41:17.372255
5742 00:41:17.372309
5743 00:41:17.375556 TX Vref Scan disable
5744 00:41:17.379200 == TX Byte 0 ==
5745 00:41:17.382457 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5746 00:41:17.385849 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5747 00:41:17.388953 == TX Byte 1 ==
5748 00:41:17.392182 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5749 00:41:17.395911 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5750 00:41:17.395987
5751 00:41:17.399025 [DATLAT]
5752 00:41:17.399101 Freq=933, CH1 RK0
5753 00:41:17.399160
5754 00:41:17.402350 DATLAT Default: 0xd
5755 00:41:17.402440 0, 0xFFFF, sum = 0
5756 00:41:17.405476 1, 0xFFFF, sum = 0
5757 00:41:17.405554 2, 0xFFFF, sum = 0
5758 00:41:17.408811 3, 0xFFFF, sum = 0
5759 00:41:17.408890 4, 0xFFFF, sum = 0
5760 00:41:17.412313 5, 0xFFFF, sum = 0
5761 00:41:17.412391 6, 0xFFFF, sum = 0
5762 00:41:17.415663 7, 0xFFFF, sum = 0
5763 00:41:17.415741 8, 0xFFFF, sum = 0
5764 00:41:17.418711 9, 0xFFFF, sum = 0
5765 00:41:17.418789 10, 0x0, sum = 1
5766 00:41:17.422327 11, 0x0, sum = 2
5767 00:41:17.422405 12, 0x0, sum = 3
5768 00:41:17.425388 13, 0x0, sum = 4
5769 00:41:17.425465 best_step = 11
5770 00:41:17.425524
5771 00:41:17.425578 ==
5772 00:41:17.428649 Dram Type= 6, Freq= 0, CH_1, rank 0
5773 00:41:17.435199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 00:41:17.435293 ==
5775 00:41:17.435368 RX Vref Scan: 1
5776 00:41:17.435422
5777 00:41:17.438690 RX Vref 0 -> 0, step: 1
5778 00:41:17.438765
5779 00:41:17.441921 RX Delay -61 -> 252, step: 4
5780 00:41:17.441997
5781 00:41:17.445621 Set Vref, RX VrefLevel [Byte0]: 54
5782 00:41:17.448585 [Byte1]: 54
5783 00:41:17.448681
5784 00:41:17.451985 Final RX Vref Byte 0 = 54 to rank0
5785 00:41:17.455650 Final RX Vref Byte 1 = 54 to rank0
5786 00:41:17.458567 Final RX Vref Byte 0 = 54 to rank1
5787 00:41:17.462034 Final RX Vref Byte 1 = 54 to rank1==
5788 00:41:17.465522 Dram Type= 6, Freq= 0, CH_1, rank 0
5789 00:41:17.468749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 00:41:17.468833 ==
5791 00:41:17.471612 DQS Delay:
5792 00:41:17.471703 DQS0 = 0, DQS1 = 0
5793 00:41:17.471788 DQM Delay:
5794 00:41:17.474878 DQM0 = 96, DQM1 = 88
5795 00:41:17.474952 DQ Delay:
5796 00:41:17.478361 DQ0 =102, DQ1 =90, DQ2 =84, DQ3 =94
5797 00:41:17.481750 DQ4 =92, DQ5 =106, DQ6 =106, DQ7 =94
5798 00:41:17.485118 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =82
5799 00:41:17.488580 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5800 00:41:17.488709
5801 00:41:17.488792
5802 00:41:17.498557 [DQSOSCAuto] RK0, (LSB)MR18= 0x60e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5803 00:41:17.498629 CH1 RK0: MR19=505, MR18=60E
5804 00:41:17.505387 CH1_RK0: MR19=0x505, MR18=0x60E, DQSOSC=417, MR23=63, INC=62, DEC=41
5805 00:41:17.505457
5806 00:41:17.508380 ----->DramcWriteLeveling(PI) begin...
5807 00:41:17.508450 ==
5808 00:41:17.511739 Dram Type= 6, Freq= 0, CH_1, rank 1
5809 00:41:17.518165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 00:41:17.518236 ==
5811 00:41:17.521673 Write leveling (Byte 0): 28 => 28
5812 00:41:17.525153 Write leveling (Byte 1): 28 => 28
5813 00:41:17.525219 DramcWriteLeveling(PI) end<-----
5814 00:41:17.528614
5815 00:41:17.528692 ==
5816 00:41:17.531521 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 00:41:17.535047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 00:41:17.535110 ==
5819 00:41:17.538168 [Gating] SW mode calibration
5820 00:41:17.545044 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5821 00:41:17.548227 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5822 00:41:17.554854 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5823 00:41:17.558442 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 00:41:17.561460 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 00:41:17.568383 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 00:41:17.571822 0 14 16 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
5827 00:41:17.574616 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5828 00:41:17.581307 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 0)
5829 00:41:17.584726 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
5830 00:41:17.588151 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 00:41:17.594655 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 00:41:17.597957 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 00:41:17.601339 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 00:41:17.608216 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 00:41:17.611545 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 00:41:17.615121 0 15 24 | B1->B0 | 2525 3434 | 1 0 | (0 0) (0 0)
5837 00:41:17.621146 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5838 00:41:17.624509 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 00:41:17.628081 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 00:41:17.634447 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 00:41:17.637847 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 00:41:17.641318 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 00:41:17.647502 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 00:41:17.651206 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5845 00:41:17.654487 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5846 00:41:17.660857 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 00:41:17.663970 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 00:41:17.667387 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 00:41:17.674151 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 00:41:17.677682 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 00:41:17.680576 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 00:41:17.687810 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 00:41:17.690883 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 00:41:17.693942 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 00:41:17.697438 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 00:41:17.704190 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 00:41:17.707601 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 00:41:17.710470 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 00:41:17.717166 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 00:41:17.720670 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5861 00:41:17.723980 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 00:41:17.727678 Total UI for P1: 0, mck2ui 16
5863 00:41:17.730420 best dqsien dly found for B0: ( 1, 2, 24)
5864 00:41:17.733953 Total UI for P1: 0, mck2ui 16
5865 00:41:17.737167 best dqsien dly found for B1: ( 1, 2, 26)
5866 00:41:17.740457 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5867 00:41:17.744025 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5868 00:41:17.747379
5869 00:41:17.750789 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5870 00:41:17.754056 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5871 00:41:17.757332 [Gating] SW calibration Done
5872 00:41:17.757415 ==
5873 00:41:17.760589 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 00:41:17.763788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 00:41:17.763880 ==
5876 00:41:17.763949 RX Vref Scan: 0
5877 00:41:17.767146
5878 00:41:17.767241 RX Vref 0 -> 0, step: 1
5879 00:41:17.767316
5880 00:41:17.770493 RX Delay -80 -> 252, step: 8
5881 00:41:17.773650 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5882 00:41:17.776634 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5883 00:41:17.783960 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5884 00:41:17.786750 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5885 00:41:17.790602 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5886 00:41:17.793719 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5887 00:41:17.796831 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5888 00:41:17.800047 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5889 00:41:17.807553 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5890 00:41:17.810368 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5891 00:41:17.813907 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5892 00:41:17.816925 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5893 00:41:17.820418 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5894 00:41:17.827156 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5895 00:41:17.830634 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5896 00:41:17.833895 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5897 00:41:17.834294 ==
5898 00:41:17.837103 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 00:41:17.840447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 00:41:17.840876 ==
5901 00:41:17.843799 DQS Delay:
5902 00:41:17.844193 DQS0 = 0, DQS1 = 0
5903 00:41:17.847055 DQM Delay:
5904 00:41:17.847452 DQM0 = 93, DQM1 = 88
5905 00:41:17.847758 DQ Delay:
5906 00:41:17.850243 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5907 00:41:17.853624 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5908 00:41:17.857081 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83
5909 00:41:17.860283 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5910 00:41:17.860707
5911 00:41:17.861027
5912 00:41:17.863860 ==
5913 00:41:17.867073 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 00:41:17.870288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 00:41:17.870745 ==
5916 00:41:17.871082
5917 00:41:17.871408
5918 00:41:17.873488 TX Vref Scan disable
5919 00:41:17.873884 == TX Byte 0 ==
5920 00:41:17.880236 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5921 00:41:17.883372 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5922 00:41:17.883773 == TX Byte 1 ==
5923 00:41:17.890146 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5924 00:41:17.893715 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5925 00:41:17.894156 ==
5926 00:41:17.896412 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 00:41:17.899780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 00:41:17.900176 ==
5929 00:41:17.900483
5930 00:41:17.900815
5931 00:41:17.903210 TX Vref Scan disable
5932 00:41:17.906475 == TX Byte 0 ==
5933 00:41:17.910219 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5934 00:41:17.913165 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5935 00:41:17.916497 == TX Byte 1 ==
5936 00:41:17.919676 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5937 00:41:17.923482 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5938 00:41:17.923878
5939 00:41:17.926865 [DATLAT]
5940 00:41:17.927259 Freq=933, CH1 RK1
5941 00:41:17.927569
5942 00:41:17.929799 DATLAT Default: 0xb
5943 00:41:17.930195 0, 0xFFFF, sum = 0
5944 00:41:17.933241 1, 0xFFFF, sum = 0
5945 00:41:17.933648 2, 0xFFFF, sum = 0
5946 00:41:17.936315 3, 0xFFFF, sum = 0
5947 00:41:17.936763 4, 0xFFFF, sum = 0
5948 00:41:17.939706 5, 0xFFFF, sum = 0
5949 00:41:17.940109 6, 0xFFFF, sum = 0
5950 00:41:17.943370 7, 0xFFFF, sum = 0
5951 00:41:17.943774 8, 0xFFFF, sum = 0
5952 00:41:17.946208 9, 0xFFFF, sum = 0
5953 00:41:17.946614 10, 0x0, sum = 1
5954 00:41:17.949137 11, 0x0, sum = 2
5955 00:41:17.949215 12, 0x0, sum = 3
5956 00:41:17.952783 13, 0x0, sum = 4
5957 00:41:17.952861 best_step = 11
5958 00:41:17.952920
5959 00:41:17.952976 ==
5960 00:41:17.956318 Dram Type= 6, Freq= 0, CH_1, rank 1
5961 00:41:17.962937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5962 00:41:17.963014 ==
5963 00:41:17.963074 RX Vref Scan: 0
5964 00:41:17.963129
5965 00:41:17.966189 RX Vref 0 -> 0, step: 1
5966 00:41:17.966266
5967 00:41:17.968976 RX Delay -69 -> 252, step: 4
5968 00:41:17.972351 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5969 00:41:17.978764 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5970 00:41:17.982406 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5971 00:41:17.985773 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5972 00:41:17.989053 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5973 00:41:17.992329 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5974 00:41:17.995345 iDelay=203, Bit 6, Center 100 (-1 ~ 202) 204
5975 00:41:18.002001 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5976 00:41:18.005500 iDelay=203, Bit 8, Center 78 (-17 ~ 174) 192
5977 00:41:18.008810 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5978 00:41:18.012021 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5979 00:41:18.015839 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5980 00:41:18.021965 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5981 00:41:18.025088 iDelay=203, Bit 13, Center 98 (3 ~ 194) 192
5982 00:41:18.028348 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5983 00:41:18.032046 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5984 00:41:18.032123 ==
5985 00:41:18.035317 Dram Type= 6, Freq= 0, CH_1, rank 1
5986 00:41:18.038287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5987 00:41:18.038365 ==
5988 00:41:18.041607 DQS Delay:
5989 00:41:18.041684 DQS0 = 0, DQS1 = 0
5990 00:41:18.045104 DQM Delay:
5991 00:41:18.045182 DQM0 = 91, DQM1 = 90
5992 00:41:18.045242 DQ Delay:
5993 00:41:18.048526 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5994 00:41:18.051942 DQ4 =90, DQ5 =102, DQ6 =100, DQ7 =88
5995 00:41:18.054925 DQ8 =78, DQ9 =82, DQ10 =92, DQ11 =84
5996 00:41:18.058151 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5997 00:41:18.058227
5998 00:41:18.061616
5999 00:41:18.068066 [DQSOSCAuto] RK1, (LSB)MR18= 0x162a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 414 ps
6000 00:41:18.071277 CH1 RK1: MR19=505, MR18=162A
6001 00:41:18.078027 CH1_RK1: MR19=0x505, MR18=0x162A, DQSOSC=408, MR23=63, INC=65, DEC=43
6002 00:41:18.081448 [RxdqsGatingPostProcess] freq 933
6003 00:41:18.084971 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6004 00:41:18.087728 best DQS0 dly(2T, 0.5T) = (0, 10)
6005 00:41:18.091597 best DQS1 dly(2T, 0.5T) = (0, 10)
6006 00:41:18.094459 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6007 00:41:18.097799 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6008 00:41:18.101262 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 00:41:18.104732 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 00:41:18.107786 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 00:41:18.111125 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 00:41:18.114443 Pre-setting of DQS Precalculation
6013 00:41:18.117749 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6014 00:41:18.124145 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6015 00:41:18.134442 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6016 00:41:18.134515
6017 00:41:18.134573
6018 00:41:18.138054 [Calibration Summary] 1866 Mbps
6019 00:41:18.138119 CH 0, Rank 0
6020 00:41:18.140764 SW Impedance : PASS
6021 00:41:18.140832 DUTY Scan : NO K
6022 00:41:18.144160 ZQ Calibration : PASS
6023 00:41:18.147670 Jitter Meter : NO K
6024 00:41:18.147731 CBT Training : PASS
6025 00:41:18.150910 Write leveling : PASS
6026 00:41:18.153857 RX DQS gating : PASS
6027 00:41:18.153924 RX DQ/DQS(RDDQC) : PASS
6028 00:41:18.157320 TX DQ/DQS : PASS
6029 00:41:18.157382 RX DATLAT : PASS
6030 00:41:18.160719 RX DQ/DQS(Engine): PASS
6031 00:41:18.163819 TX OE : NO K
6032 00:41:18.163879 All Pass.
6033 00:41:18.163930
6034 00:41:18.163980 CH 0, Rank 1
6035 00:41:18.167268 SW Impedance : PASS
6036 00:41:18.170560 DUTY Scan : NO K
6037 00:41:18.170621 ZQ Calibration : PASS
6038 00:41:18.174021 Jitter Meter : NO K
6039 00:41:18.177421 CBT Training : PASS
6040 00:41:18.177480 Write leveling : PASS
6041 00:41:18.180599 RX DQS gating : PASS
6042 00:41:18.183907 RX DQ/DQS(RDDQC) : PASS
6043 00:41:18.183976 TX DQ/DQS : PASS
6044 00:41:18.187169 RX DATLAT : PASS
6045 00:41:18.190310 RX DQ/DQS(Engine): PASS
6046 00:41:18.190373 TX OE : NO K
6047 00:41:18.193795 All Pass.
6048 00:41:18.193857
6049 00:41:18.193915 CH 1, Rank 0
6050 00:41:18.197097 SW Impedance : PASS
6051 00:41:18.197170 DUTY Scan : NO K
6052 00:41:18.200827 ZQ Calibration : PASS
6053 00:41:18.203512 Jitter Meter : NO K
6054 00:41:18.203600 CBT Training : PASS
6055 00:41:18.206996 Write leveling : PASS
6056 00:41:18.210027 RX DQS gating : PASS
6057 00:41:18.210098 RX DQ/DQS(RDDQC) : PASS
6058 00:41:18.213685 TX DQ/DQS : PASS
6059 00:41:18.213756 RX DATLAT : PASS
6060 00:41:18.216653 RX DQ/DQS(Engine): PASS
6061 00:41:18.220115 TX OE : NO K
6062 00:41:18.220184 All Pass.
6063 00:41:18.220240
6064 00:41:18.220292 CH 1, Rank 1
6065 00:41:18.223270 SW Impedance : PASS
6066 00:41:18.226668 DUTY Scan : NO K
6067 00:41:18.226732 ZQ Calibration : PASS
6068 00:41:18.230077 Jitter Meter : NO K
6069 00:41:18.233710 CBT Training : PASS
6070 00:41:18.233792 Write leveling : PASS
6071 00:41:18.236983 RX DQS gating : PASS
6072 00:41:18.240422 RX DQ/DQS(RDDQC) : PASS
6073 00:41:18.240488 TX DQ/DQS : PASS
6074 00:41:18.243233 RX DATLAT : PASS
6075 00:41:18.246909 RX DQ/DQS(Engine): PASS
6076 00:41:18.246972 TX OE : NO K
6077 00:41:18.249861 All Pass.
6078 00:41:18.249929
6079 00:41:18.249982 DramC Write-DBI off
6080 00:41:18.253227 PER_BANK_REFRESH: Hybrid Mode
6081 00:41:18.253288 TX_TRACKING: ON
6082 00:41:18.263123 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6083 00:41:18.266675 [FAST_K] Save calibration result to emmc
6084 00:41:18.270036 dramc_set_vcore_voltage set vcore to 650000
6085 00:41:18.273511 Read voltage for 400, 6
6086 00:41:18.273578 Vio18 = 0
6087 00:41:18.276869 Vcore = 650000
6088 00:41:18.276929 Vdram = 0
6089 00:41:18.276980 Vddq = 0
6090 00:41:18.279698 Vmddr = 0
6091 00:41:18.283422 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6092 00:41:18.290016 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6093 00:41:18.290083 MEM_TYPE=3, freq_sel=20
6094 00:41:18.293359 sv_algorithm_assistance_LP4_800
6095 00:41:18.296592 ============ PULL DRAM RESETB DOWN ============
6096 00:41:18.303463 ========== PULL DRAM RESETB DOWN end =========
6097 00:41:18.306343 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6098 00:41:18.309542 ===================================
6099 00:41:18.313064 LPDDR4 DRAM CONFIGURATION
6100 00:41:18.316302 ===================================
6101 00:41:18.316395 EX_ROW_EN[0] = 0x0
6102 00:41:18.320022 EX_ROW_EN[1] = 0x0
6103 00:41:18.323244 LP4Y_EN = 0x0
6104 00:41:18.323319 WORK_FSP = 0x0
6105 00:41:18.326288 WL = 0x2
6106 00:41:18.326353 RL = 0x2
6107 00:41:18.329803 BL = 0x2
6108 00:41:18.329865 RPST = 0x0
6109 00:41:18.333277 RD_PRE = 0x0
6110 00:41:18.333338 WR_PRE = 0x1
6111 00:41:18.336378 WR_PST = 0x0
6112 00:41:18.336440 DBI_WR = 0x0
6113 00:41:18.339631 DBI_RD = 0x0
6114 00:41:18.339696 OTF = 0x1
6115 00:41:18.342770 ===================================
6116 00:41:18.346676 ===================================
6117 00:41:18.349836 ANA top config
6118 00:41:18.353073 ===================================
6119 00:41:18.353138 DLL_ASYNC_EN = 0
6120 00:41:18.356362 ALL_SLAVE_EN = 1
6121 00:41:18.359817 NEW_RANK_MODE = 1
6122 00:41:18.362760 DLL_IDLE_MODE = 1
6123 00:41:18.366032 LP45_APHY_COMB_EN = 1
6124 00:41:18.366094 TX_ODT_DIS = 1
6125 00:41:18.369511 NEW_8X_MODE = 1
6126 00:41:18.372996 ===================================
6127 00:41:18.376413 ===================================
6128 00:41:18.379358 data_rate = 800
6129 00:41:18.382757 CKR = 1
6130 00:41:18.386166 DQ_P2S_RATIO = 4
6131 00:41:18.389594 ===================================
6132 00:41:18.389655 CA_P2S_RATIO = 4
6133 00:41:18.393024 DQ_CA_OPEN = 0
6134 00:41:18.395786 DQ_SEMI_OPEN = 1
6135 00:41:18.399141 CA_SEMI_OPEN = 1
6136 00:41:18.402659 CA_FULL_RATE = 0
6137 00:41:18.406193 DQ_CKDIV4_EN = 0
6138 00:41:18.406263 CA_CKDIV4_EN = 1
6139 00:41:18.409478 CA_PREDIV_EN = 0
6140 00:41:18.412931 PH8_DLY = 0
6141 00:41:18.416388 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6142 00:41:18.419600 DQ_AAMCK_DIV = 0
6143 00:41:18.422696 CA_AAMCK_DIV = 0
6144 00:41:18.422767 CA_ADMCK_DIV = 4
6145 00:41:18.426253 DQ_TRACK_CA_EN = 0
6146 00:41:18.429346 CA_PICK = 800
6147 00:41:18.432994 CA_MCKIO = 400
6148 00:41:18.435999 MCKIO_SEMI = 400
6149 00:41:18.439109 PLL_FREQ = 3016
6150 00:41:18.442671 DQ_UI_PI_RATIO = 32
6151 00:41:18.442735 CA_UI_PI_RATIO = 32
6152 00:41:18.446242 ===================================
6153 00:41:18.449724 ===================================
6154 00:41:18.452710 memory_type:LPDDR4
6155 00:41:18.456134 GP_NUM : 10
6156 00:41:18.456204 SRAM_EN : 1
6157 00:41:18.459550 MD32_EN : 0
6158 00:41:18.462597 ===================================
6159 00:41:18.465590 [ANA_INIT] >>>>>>>>>>>>>>
6160 00:41:18.469244 <<<<<< [CONFIGURE PHASE]: ANA_TX
6161 00:41:18.472320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6162 00:41:18.475595 ===================================
6163 00:41:18.475660 data_rate = 800,PCW = 0X7400
6164 00:41:18.479080 ===================================
6165 00:41:18.482359 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6166 00:41:18.489363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6167 00:41:18.502440 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6168 00:41:18.505874 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6169 00:41:18.509249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6170 00:41:18.512612 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6171 00:41:18.515462 [ANA_INIT] flow start
6172 00:41:18.515528 [ANA_INIT] PLL >>>>>>>>
6173 00:41:18.518900 [ANA_INIT] PLL <<<<<<<<
6174 00:41:18.522409 [ANA_INIT] MIDPI >>>>>>>>
6175 00:41:18.522473 [ANA_INIT] MIDPI <<<<<<<<
6176 00:41:18.525872 [ANA_INIT] DLL >>>>>>>>
6177 00:41:18.528843 [ANA_INIT] flow end
6178 00:41:18.532099 ============ LP4 DIFF to SE enter ============
6179 00:41:18.535236 ============ LP4 DIFF to SE exit ============
6180 00:41:18.539190 [ANA_INIT] <<<<<<<<<<<<<
6181 00:41:18.542094 [Flow] Enable top DCM control >>>>>
6182 00:41:18.545446 [Flow] Enable top DCM control <<<<<
6183 00:41:18.548807 Enable DLL master slave shuffle
6184 00:41:18.552209 ==============================================================
6185 00:41:18.555200 Gating Mode config
6186 00:41:18.562201 ==============================================================
6187 00:41:18.562276 Config description:
6188 00:41:18.572083 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6189 00:41:18.578676 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6190 00:41:18.585143 SELPH_MODE 0: By rank 1: By Phase
6191 00:41:18.588725 ==============================================================
6192 00:41:18.592178 GAT_TRACK_EN = 0
6193 00:41:18.595189 RX_GATING_MODE = 2
6194 00:41:18.598741 RX_GATING_TRACK_MODE = 2
6195 00:41:18.601988 SELPH_MODE = 1
6196 00:41:18.605312 PICG_EARLY_EN = 1
6197 00:41:18.608848 VALID_LAT_VALUE = 1
6198 00:41:18.611745 ==============================================================
6199 00:41:18.615298 Enter into Gating configuration >>>>
6200 00:41:18.618297 Exit from Gating configuration <<<<
6201 00:41:18.621607 Enter into DVFS_PRE_config >>>>>
6202 00:41:18.634921 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6203 00:41:18.638793 Exit from DVFS_PRE_config <<<<<
6204 00:41:18.638862 Enter into PICG configuration >>>>
6205 00:41:18.641768 Exit from PICG configuration <<<<
6206 00:41:18.645047 [RX_INPUT] configuration >>>>>
6207 00:41:18.648405 [RX_INPUT] configuration <<<<<
6208 00:41:18.654528 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6209 00:41:18.657847 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6210 00:41:18.664729 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6211 00:41:18.671254 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6212 00:41:18.678105 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6213 00:41:18.684471 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6214 00:41:18.687723 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6215 00:41:18.691256 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6216 00:41:18.694908 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6217 00:41:18.701496 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6218 00:41:18.704714 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6219 00:41:18.707825 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6220 00:41:18.711121 ===================================
6221 00:41:18.714597 LPDDR4 DRAM CONFIGURATION
6222 00:41:18.718143 ===================================
6223 00:41:18.720866 EX_ROW_EN[0] = 0x0
6224 00:41:18.720957 EX_ROW_EN[1] = 0x0
6225 00:41:18.724205 LP4Y_EN = 0x0
6226 00:41:18.724270 WORK_FSP = 0x0
6227 00:41:18.727770 WL = 0x2
6228 00:41:18.727832 RL = 0x2
6229 00:41:18.730989 BL = 0x2
6230 00:41:18.731050 RPST = 0x0
6231 00:41:18.734473 RD_PRE = 0x0
6232 00:41:18.734534 WR_PRE = 0x1
6233 00:41:18.737780 WR_PST = 0x0
6234 00:41:18.737841 DBI_WR = 0x0
6235 00:41:18.741225 DBI_RD = 0x0
6236 00:41:18.741285 OTF = 0x1
6237 00:41:18.744588 ===================================
6238 00:41:18.750956 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6239 00:41:18.754245 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6240 00:41:18.757661 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6241 00:41:18.761140 ===================================
6242 00:41:18.764447 LPDDR4 DRAM CONFIGURATION
6243 00:41:18.767765 ===================================
6244 00:41:18.770750 EX_ROW_EN[0] = 0x10
6245 00:41:18.770812 EX_ROW_EN[1] = 0x0
6246 00:41:18.774094 LP4Y_EN = 0x0
6247 00:41:18.774156 WORK_FSP = 0x0
6248 00:41:18.777697 WL = 0x2
6249 00:41:18.777759 RL = 0x2
6250 00:41:18.781163 BL = 0x2
6251 00:41:18.781223 RPST = 0x0
6252 00:41:18.784586 RD_PRE = 0x0
6253 00:41:18.784681 WR_PRE = 0x1
6254 00:41:18.787383 WR_PST = 0x0
6255 00:41:18.787445 DBI_WR = 0x0
6256 00:41:18.790923 DBI_RD = 0x0
6257 00:41:18.790983 OTF = 0x1
6258 00:41:18.794189 ===================================
6259 00:41:18.800593 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6260 00:41:18.805269 nWR fixed to 30
6261 00:41:18.808646 [ModeRegInit_LP4] CH0 RK0
6262 00:41:18.808745 [ModeRegInit_LP4] CH0 RK1
6263 00:41:18.812038 [ModeRegInit_LP4] CH1 RK0
6264 00:41:18.815198 [ModeRegInit_LP4] CH1 RK1
6265 00:41:18.815271 match AC timing 19
6266 00:41:18.821807 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6267 00:41:18.825081 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6268 00:41:18.828375 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6269 00:41:18.834621 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6270 00:41:18.837868 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6271 00:41:18.837938 ==
6272 00:41:18.841205 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 00:41:18.844777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 00:41:18.844845 ==
6275 00:41:18.851418 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6276 00:41:18.858154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6277 00:41:18.861510 [CA 0] Center 36 (8~64) winsize 57
6278 00:41:18.864980 [CA 1] Center 36 (8~64) winsize 57
6279 00:41:18.867794 [CA 2] Center 36 (8~64) winsize 57
6280 00:41:18.871106 [CA 3] Center 36 (8~64) winsize 57
6281 00:41:18.874659 [CA 4] Center 36 (8~64) winsize 57
6282 00:41:18.877525 [CA 5] Center 36 (8~64) winsize 57
6283 00:41:18.877602
6284 00:41:18.880996 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6285 00:41:18.881072
6286 00:41:18.884312 [CATrainingPosCal] consider 1 rank data
6287 00:41:18.887660 u2DelayCellTimex100 = 270/100 ps
6288 00:41:18.891006 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 00:41:18.895223 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 00:41:18.897922 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 00:41:18.900848 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 00:41:18.904215 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 00:41:18.907589 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 00:41:18.907666
6295 00:41:18.911088 CA PerBit enable=1, Macro0, CA PI delay=36
6296 00:41:18.911198
6297 00:41:18.914579 [CBTSetCACLKResult] CA Dly = 36
6298 00:41:18.917723 CS Dly: 1 (0~32)
6299 00:41:18.917800 ==
6300 00:41:18.920887 Dram Type= 6, Freq= 0, CH_0, rank 1
6301 00:41:18.924216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 00:41:18.924294 ==
6303 00:41:18.931045 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6304 00:41:18.937516 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6305 00:41:18.940984 [CA 0] Center 36 (8~64) winsize 57
6306 00:41:18.943982 [CA 1] Center 36 (8~64) winsize 57
6307 00:41:18.944059 [CA 2] Center 36 (8~64) winsize 57
6308 00:41:18.947400 [CA 3] Center 36 (8~64) winsize 57
6309 00:41:18.950976 [CA 4] Center 36 (8~64) winsize 57
6310 00:41:18.954205 [CA 5] Center 36 (8~64) winsize 57
6311 00:41:18.954282
6312 00:41:18.957680 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6313 00:41:18.957758
6314 00:41:18.964205 [CATrainingPosCal] consider 2 rank data
6315 00:41:18.964283 u2DelayCellTimex100 = 270/100 ps
6316 00:41:18.970429 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 00:41:18.973791 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 00:41:18.977265 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 00:41:18.980579 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 00:41:18.984017 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 00:41:18.986897 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 00:41:18.986974
6323 00:41:18.990448 CA PerBit enable=1, Macro0, CA PI delay=36
6324 00:41:18.990524
6325 00:41:18.993889 [CBTSetCACLKResult] CA Dly = 36
6326 00:41:18.997210 CS Dly: 1 (0~32)
6327 00:41:18.997288
6328 00:41:19.000199 ----->DramcWriteLeveling(PI) begin...
6329 00:41:19.000277 ==
6330 00:41:19.003432 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 00:41:19.006807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 00:41:19.006885 ==
6333 00:41:19.010098 Write leveling (Byte 0): 40 => 8
6334 00:41:19.013584 Write leveling (Byte 1): 32 => 0
6335 00:41:19.017104 DramcWriteLeveling(PI) end<-----
6336 00:41:19.017183
6337 00:41:19.017244 ==
6338 00:41:19.020174 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 00:41:19.023424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 00:41:19.023499 ==
6341 00:41:19.026883 [Gating] SW mode calibration
6342 00:41:19.033623 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6343 00:41:19.039993 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6344 00:41:19.043326 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6345 00:41:19.046712 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6346 00:41:19.053009 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 00:41:19.056722 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6348 00:41:19.060125 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 00:41:19.066679 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 00:41:19.069775 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 00:41:19.072958 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 00:41:19.079758 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 00:41:19.079822 Total UI for P1: 0, mck2ui 16
6354 00:41:19.086136 best dqsien dly found for B0: ( 0, 14, 24)
6355 00:41:19.086206 Total UI for P1: 0, mck2ui 16
6356 00:41:19.093076 best dqsien dly found for B1: ( 0, 14, 24)
6357 00:41:19.096666 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6358 00:41:19.100085 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6359 00:41:19.100152
6360 00:41:19.103274 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6361 00:41:19.106339 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6362 00:41:19.109708 [Gating] SW calibration Done
6363 00:41:19.109772 ==
6364 00:41:19.113098 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 00:41:19.116551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 00:41:19.116663 ==
6367 00:41:19.119941 RX Vref Scan: 0
6368 00:41:19.120009
6369 00:41:19.120063 RX Vref 0 -> 0, step: 1
6370 00:41:19.120115
6371 00:41:19.123083 RX Delay -410 -> 252, step: 16
6372 00:41:19.129920 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6373 00:41:19.132896 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6374 00:41:19.136666 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6375 00:41:19.139507 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6376 00:41:19.146219 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6377 00:41:19.149544 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6378 00:41:19.152989 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6379 00:41:19.156925 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6380 00:41:19.162715 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6381 00:41:19.166677 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6382 00:41:19.169391 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6383 00:41:19.172592 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6384 00:41:19.179571 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6385 00:41:19.182891 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6386 00:41:19.186143 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6387 00:41:19.189208 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6388 00:41:19.192934 ==
6389 00:41:19.193012 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 00:41:19.199173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 00:41:19.199249 ==
6392 00:41:19.199309 DQS Delay:
6393 00:41:19.202547 DQS0 = 59, DQS1 = 67
6394 00:41:19.202623 DQM Delay:
6395 00:41:19.206038 DQM0 = 18, DQM1 = 17
6396 00:41:19.206113 DQ Delay:
6397 00:41:19.209388 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6398 00:41:19.212759 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6399 00:41:19.215791 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6400 00:41:19.219311 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6401 00:41:19.219387
6402 00:41:19.219445
6403 00:41:19.219499 ==
6404 00:41:19.222684 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 00:41:19.225658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 00:41:19.225735 ==
6407 00:41:19.225794
6408 00:41:19.225847
6409 00:41:19.229060 TX Vref Scan disable
6410 00:41:19.229136 == TX Byte 0 ==
6411 00:41:19.235821 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6412 00:41:19.239122 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6413 00:41:19.239200 == TX Byte 1 ==
6414 00:41:19.245703 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6415 00:41:19.248631 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6416 00:41:19.248748 ==
6417 00:41:19.252015 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 00:41:19.255810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 00:41:19.255886 ==
6420 00:41:19.255945
6421 00:41:19.258631
6422 00:41:19.258706 TX Vref Scan disable
6423 00:41:19.262076 == TX Byte 0 ==
6424 00:41:19.265544 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6425 00:41:19.268879 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6426 00:41:19.272364 == TX Byte 1 ==
6427 00:41:19.275751 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6428 00:41:19.279031 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6429 00:41:19.279108
6430 00:41:19.279168 [DATLAT]
6431 00:41:19.282057 Freq=400, CH0 RK0
6432 00:41:19.282134
6433 00:41:19.285615 DATLAT Default: 0xf
6434 00:41:19.285692 0, 0xFFFF, sum = 0
6435 00:41:19.289042 1, 0xFFFF, sum = 0
6436 00:41:19.289119 2, 0xFFFF, sum = 0
6437 00:41:19.291962 3, 0xFFFF, sum = 0
6438 00:41:19.292039 4, 0xFFFF, sum = 0
6439 00:41:19.295296 5, 0xFFFF, sum = 0
6440 00:41:19.295379 6, 0xFFFF, sum = 0
6441 00:41:19.298736 7, 0xFFFF, sum = 0
6442 00:41:19.298813 8, 0xFFFF, sum = 0
6443 00:41:19.301958 9, 0xFFFF, sum = 0
6444 00:41:19.302039 10, 0xFFFF, sum = 0
6445 00:41:19.305549 11, 0xFFFF, sum = 0
6446 00:41:19.305628 12, 0xFFFF, sum = 0
6447 00:41:19.308796 13, 0x0, sum = 1
6448 00:41:19.308874 14, 0x0, sum = 2
6449 00:41:19.312558 15, 0x0, sum = 3
6450 00:41:19.312713 16, 0x0, sum = 4
6451 00:41:19.315425 best_step = 14
6452 00:41:19.315501
6453 00:41:19.315559 ==
6454 00:41:19.318953 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 00:41:19.321809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 00:41:19.321886 ==
6457 00:41:19.325117 RX Vref Scan: 1
6458 00:41:19.325193
6459 00:41:19.325253 RX Vref 0 -> 0, step: 1
6460 00:41:19.325309
6461 00:41:19.328539 RX Delay -375 -> 252, step: 8
6462 00:41:19.328616
6463 00:41:19.332094 Set Vref, RX VrefLevel [Byte0]: 62
6464 00:41:19.334890 [Byte1]: 52
6465 00:41:19.339799
6466 00:41:19.339875 Final RX Vref Byte 0 = 62 to rank0
6467 00:41:19.343066 Final RX Vref Byte 1 = 52 to rank0
6468 00:41:19.346194 Final RX Vref Byte 0 = 62 to rank1
6469 00:41:19.349412 Final RX Vref Byte 1 = 52 to rank1==
6470 00:41:19.353054 Dram Type= 6, Freq= 0, CH_0, rank 0
6471 00:41:19.359944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 00:41:19.360023 ==
6473 00:41:19.360083 DQS Delay:
6474 00:41:19.362737 DQS0 = 60, DQS1 = 68
6475 00:41:19.362814 DQM Delay:
6476 00:41:19.362874 DQM0 = 13, DQM1 = 14
6477 00:41:19.366172 DQ Delay:
6478 00:41:19.369605 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6479 00:41:19.373110 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6480 00:41:19.373187 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6481 00:41:19.375939 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6482 00:41:19.379467
6483 00:41:19.379543
6484 00:41:19.386169 [DQSOSCAuto] RK0, (LSB)MR18= 0x8986, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6485 00:41:19.389251 CH0 RK0: MR19=C0C, MR18=8986
6486 00:41:19.396203 CH0_RK0: MR19=0xC0C, MR18=0x8986, DQSOSC=392, MR23=63, INC=384, DEC=256
6487 00:41:19.396280 ==
6488 00:41:19.399127 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 00:41:19.402588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 00:41:19.402665 ==
6491 00:41:19.406081 [Gating] SW mode calibration
6492 00:41:19.412330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6493 00:41:19.419217 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6494 00:41:19.422547 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 00:41:19.425699 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6496 00:41:19.432531 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 00:41:19.435849 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6498 00:41:19.439197 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 00:41:19.445383 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 00:41:19.449091 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 00:41:19.452361 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 00:41:19.458830 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 00:41:19.458908 Total UI for P1: 0, mck2ui 16
6504 00:41:19.465609 best dqsien dly found for B0: ( 0, 14, 24)
6505 00:41:19.465687 Total UI for P1: 0, mck2ui 16
6506 00:41:19.468870 best dqsien dly found for B1: ( 0, 14, 24)
6507 00:41:19.475143 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6508 00:41:19.478689 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6509 00:41:19.478766
6510 00:41:19.482119 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6511 00:41:19.485537 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6512 00:41:19.488867 [Gating] SW calibration Done
6513 00:41:19.488943 ==
6514 00:41:19.491736 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 00:41:19.495094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 00:41:19.495171 ==
6517 00:41:19.498813 RX Vref Scan: 0
6518 00:41:19.498889
6519 00:41:19.498950 RX Vref 0 -> 0, step: 1
6520 00:41:19.499005
6521 00:41:19.501796 RX Delay -410 -> 252, step: 16
6522 00:41:19.508680 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6523 00:41:19.512146 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6524 00:41:19.514983 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6525 00:41:19.518312 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6526 00:41:19.524983 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6527 00:41:19.527989 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6528 00:41:19.531547 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6529 00:41:19.534861 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6530 00:41:19.541535 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6531 00:41:19.544939 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6532 00:41:19.548282 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6533 00:41:19.551215 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6534 00:41:19.558299 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6535 00:41:19.561393 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6536 00:41:19.564739 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6537 00:41:19.568045 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6538 00:41:19.571375 ==
6539 00:41:19.574835 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 00:41:19.577852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 00:41:19.577930 ==
6542 00:41:19.577990 DQS Delay:
6543 00:41:19.581159 DQS0 = 59, DQS1 = 59
6544 00:41:19.581236 DQM Delay:
6545 00:41:19.584615 DQM0 = 15, DQM1 = 10
6546 00:41:19.584729 DQ Delay:
6547 00:41:19.588147 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6548 00:41:19.591034 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6549 00:41:19.594396 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6550 00:41:19.597858 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6551 00:41:19.597935
6552 00:41:19.597994
6553 00:41:19.598049 ==
6554 00:41:19.601248 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 00:41:19.604401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 00:41:19.604479 ==
6557 00:41:19.604539
6558 00:41:19.604594
6559 00:41:19.607580 TX Vref Scan disable
6560 00:41:19.607657 == TX Byte 0 ==
6561 00:41:19.614635 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6562 00:41:19.617671 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6563 00:41:19.617749 == TX Byte 1 ==
6564 00:41:19.624541 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6565 00:41:19.627387 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6566 00:41:19.627463 ==
6567 00:41:19.630795 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 00:41:19.633979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 00:41:19.634057 ==
6570 00:41:19.634116
6571 00:41:19.634171
6572 00:41:19.637776 TX Vref Scan disable
6573 00:41:19.641003 == TX Byte 0 ==
6574 00:41:19.644286 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6575 00:41:19.647511 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6576 00:41:19.650993 == TX Byte 1 ==
6577 00:41:19.654248 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6578 00:41:19.657252 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6579 00:41:19.657329
6580 00:41:19.657389 [DATLAT]
6581 00:41:19.660376 Freq=400, CH0 RK1
6582 00:41:19.660453
6583 00:41:19.660513 DATLAT Default: 0xe
6584 00:41:19.663734 0, 0xFFFF, sum = 0
6585 00:41:19.663812 1, 0xFFFF, sum = 0
6586 00:41:19.667115 2, 0xFFFF, sum = 0
6587 00:41:19.670368 3, 0xFFFF, sum = 0
6588 00:41:19.670446 4, 0xFFFF, sum = 0
6589 00:41:19.673975 5, 0xFFFF, sum = 0
6590 00:41:19.674053 6, 0xFFFF, sum = 0
6591 00:41:19.676937 7, 0xFFFF, sum = 0
6592 00:41:19.677015 8, 0xFFFF, sum = 0
6593 00:41:19.680562 9, 0xFFFF, sum = 0
6594 00:41:19.680641 10, 0xFFFF, sum = 0
6595 00:41:19.683689 11, 0xFFFF, sum = 0
6596 00:41:19.683768 12, 0xFFFF, sum = 0
6597 00:41:19.686888 13, 0x0, sum = 1
6598 00:41:19.686966 14, 0x0, sum = 2
6599 00:41:19.690468 15, 0x0, sum = 3
6600 00:41:19.690546 16, 0x0, sum = 4
6601 00:41:19.693717 best_step = 14
6602 00:41:19.693794
6603 00:41:19.693853 ==
6604 00:41:19.697030 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 00:41:19.700500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 00:41:19.700577 ==
6607 00:41:19.700637 RX Vref Scan: 0
6608 00:41:19.703847
6609 00:41:19.703923 RX Vref 0 -> 0, step: 1
6610 00:41:19.703983
6611 00:41:19.706762 RX Delay -359 -> 252, step: 8
6612 00:41:19.714585 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6613 00:41:19.717610 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6614 00:41:19.721423 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6615 00:41:19.724429 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6616 00:41:19.731314 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6617 00:41:19.734602 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6618 00:41:19.737413 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6619 00:41:19.740766 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6620 00:41:19.747310 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6621 00:41:19.750722 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6622 00:41:19.754363 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6623 00:41:19.760779 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6624 00:41:19.764250 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6625 00:41:19.767586 iDelay=217, Bit 13, Center -52 (-303 ~ 200) 504
6626 00:41:19.770891 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6627 00:41:19.777187 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6628 00:41:19.777264 ==
6629 00:41:19.780536 Dram Type= 6, Freq= 0, CH_0, rank 1
6630 00:41:19.783769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 00:41:19.783848 ==
6632 00:41:19.783907 DQS Delay:
6633 00:41:19.787110 DQS0 = 60, DQS1 = 72
6634 00:41:19.787187 DQM Delay:
6635 00:41:19.790621 DQM0 = 11, DQM1 = 17
6636 00:41:19.790698 DQ Delay:
6637 00:41:19.794080 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6638 00:41:19.797348 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6639 00:41:19.800506 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6640 00:41:19.803947 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6641 00:41:19.804024
6642 00:41:19.804083
6643 00:41:19.810263 [DQSOSCAuto] RK1, (LSB)MR18= 0xd388, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 383 ps
6644 00:41:19.813592 CH0 RK1: MR19=C0C, MR18=D388
6645 00:41:19.820528 CH0_RK1: MR19=0xC0C, MR18=0xD388, DQSOSC=383, MR23=63, INC=402, DEC=268
6646 00:41:19.823782 [RxdqsGatingPostProcess] freq 400
6647 00:41:19.830806 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6648 00:41:19.833604 best DQS0 dly(2T, 0.5T) = (0, 10)
6649 00:41:19.833682 best DQS1 dly(2T, 0.5T) = (0, 10)
6650 00:41:19.837026 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6651 00:41:19.840321 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6652 00:41:19.843756 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 00:41:19.846944 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 00:41:19.850507 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 00:41:19.853849 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 00:41:19.857312 Pre-setting of DQS Precalculation
6657 00:41:19.863621 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6658 00:41:19.863721 ==
6659 00:41:19.867083 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 00:41:19.870547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 00:41:19.870624 ==
6662 00:41:19.876708 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6663 00:41:19.880221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6664 00:41:19.883671 [CA 0] Center 36 (8~64) winsize 57
6665 00:41:19.886849 [CA 1] Center 36 (8~64) winsize 57
6666 00:41:19.890019 [CA 2] Center 36 (8~64) winsize 57
6667 00:41:19.893664 [CA 3] Center 36 (8~64) winsize 57
6668 00:41:19.897052 [CA 4] Center 36 (8~64) winsize 57
6669 00:41:19.900256 [CA 5] Center 36 (8~64) winsize 57
6670 00:41:19.900334
6671 00:41:19.903342 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6672 00:41:19.903419
6673 00:41:19.906782 [CATrainingPosCal] consider 1 rank data
6674 00:41:19.910122 u2DelayCellTimex100 = 270/100 ps
6675 00:41:19.913437 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 00:41:19.916914 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 00:41:19.919978 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 00:41:19.927088 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 00:41:19.930218 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 00:41:19.933448 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 00:41:19.933526
6682 00:41:19.936449 CA PerBit enable=1, Macro0, CA PI delay=36
6683 00:41:19.936527
6684 00:41:19.940367 [CBTSetCACLKResult] CA Dly = 36
6685 00:41:19.940443 CS Dly: 1 (0~32)
6686 00:41:19.940504 ==
6687 00:41:19.943235 Dram Type= 6, Freq= 0, CH_1, rank 1
6688 00:41:19.950074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 00:41:19.950153 ==
6690 00:41:19.953458 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6691 00:41:19.959815 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6692 00:41:19.963302 [CA 0] Center 36 (8~64) winsize 57
6693 00:41:19.966550 [CA 1] Center 36 (8~64) winsize 57
6694 00:41:19.970154 [CA 2] Center 36 (8~64) winsize 57
6695 00:41:19.973001 [CA 3] Center 36 (8~64) winsize 57
6696 00:41:19.977000 [CA 4] Center 36 (8~64) winsize 57
6697 00:41:19.979824 [CA 5] Center 36 (8~64) winsize 57
6698 00:41:19.979900
6699 00:41:19.983306 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6700 00:41:19.983383
6701 00:41:19.986275 [CATrainingPosCal] consider 2 rank data
6702 00:41:19.989774 u2DelayCellTimex100 = 270/100 ps
6703 00:41:19.993224 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 00:41:19.996685 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 00:41:19.999655 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 00:41:20.002872 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 00:41:20.006358 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 00:41:20.009780 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 00:41:20.013065
6710 00:41:20.016285 CA PerBit enable=1, Macro0, CA PI delay=36
6711 00:41:20.016362
6712 00:41:20.019497 [CBTSetCACLKResult] CA Dly = 36
6713 00:41:20.019590 CS Dly: 1 (0~32)
6714 00:41:20.019653
6715 00:41:20.023248 ----->DramcWriteLeveling(PI) begin...
6716 00:41:20.023350 ==
6717 00:41:20.026348 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 00:41:20.030155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 00:41:20.030233 ==
6720 00:41:20.033139 Write leveling (Byte 0): 40 => 8
6721 00:41:20.036446 Write leveling (Byte 1): 40 => 8
6722 00:41:20.040504 DramcWriteLeveling(PI) end<-----
6723 00:41:20.040582
6724 00:41:20.040642 ==
6725 00:41:20.043141 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 00:41:20.049792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 00:41:20.049870 ==
6728 00:41:20.049931 [Gating] SW mode calibration
6729 00:41:20.059739 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6730 00:41:20.062916 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6731 00:41:20.066020 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6732 00:41:20.072799 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6733 00:41:20.075958 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 00:41:20.079594 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6735 00:41:20.086010 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 00:41:20.089474 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 00:41:20.093017 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 00:41:20.099339 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 00:41:20.102572 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 00:41:20.105779 Total UI for P1: 0, mck2ui 16
6741 00:41:20.109112 best dqsien dly found for B0: ( 0, 14, 24)
6742 00:41:20.112519 Total UI for P1: 0, mck2ui 16
6743 00:41:20.115931 best dqsien dly found for B1: ( 0, 14, 24)
6744 00:41:20.119352 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6745 00:41:20.122400 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6746 00:41:20.122477
6747 00:41:20.126076 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6748 00:41:20.129410 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6749 00:41:20.132839 [Gating] SW calibration Done
6750 00:41:20.132939 ==
6751 00:41:20.135744 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 00:41:20.142698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 00:41:20.142776 ==
6754 00:41:20.142836 RX Vref Scan: 0
6755 00:41:20.142899
6756 00:41:20.145699 RX Vref 0 -> 0, step: 1
6757 00:41:20.145800
6758 00:41:20.149235 RX Delay -410 -> 252, step: 16
6759 00:41:20.152320 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6760 00:41:20.155733 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6761 00:41:20.159010 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6762 00:41:20.165863 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6763 00:41:20.169001 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6764 00:41:20.172208 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6765 00:41:20.175818 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6766 00:41:20.182403 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6767 00:41:20.185578 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6768 00:41:20.188999 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6769 00:41:20.192437 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6770 00:41:20.198742 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6771 00:41:20.202226 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6772 00:41:20.205678 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6773 00:41:20.212321 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6774 00:41:20.215596 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6775 00:41:20.215675 ==
6776 00:41:20.218396 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 00:41:20.221905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 00:41:20.222006 ==
6779 00:41:20.225359 DQS Delay:
6780 00:41:20.225436 DQS0 = 51, DQS1 = 67
6781 00:41:20.225497 DQM Delay:
6782 00:41:20.228615 DQM0 = 13, DQM1 = 18
6783 00:41:20.228706 DQ Delay:
6784 00:41:20.231692 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6785 00:41:20.235135 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6786 00:41:20.238521 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6787 00:41:20.242022 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6788 00:41:20.242100
6789 00:41:20.242159
6790 00:41:20.242214 ==
6791 00:41:20.245415 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 00:41:20.248704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 00:41:20.252053 ==
6794 00:41:20.252160
6795 00:41:20.252248
6796 00:41:20.252332 TX Vref Scan disable
6797 00:41:20.255438 == TX Byte 0 ==
6798 00:41:20.258766 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6799 00:41:20.261828 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6800 00:41:20.265286 == TX Byte 1 ==
6801 00:41:20.268789 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 00:41:20.271652 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 00:41:20.271729 ==
6804 00:41:20.274851 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 00:41:20.281630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 00:41:20.281708 ==
6807 00:41:20.281768
6808 00:41:20.281824
6809 00:41:20.281876 TX Vref Scan disable
6810 00:41:20.284952 == TX Byte 0 ==
6811 00:41:20.288407 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 00:41:20.291533 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 00:41:20.294675 == TX Byte 1 ==
6814 00:41:20.298264 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 00:41:20.301151 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 00:41:20.301229
6817 00:41:20.305253 [DATLAT]
6818 00:41:20.305330 Freq=400, CH1 RK0
6819 00:41:20.305390
6820 00:41:20.308113 DATLAT Default: 0xf
6821 00:41:20.308190 0, 0xFFFF, sum = 0
6822 00:41:20.311327 1, 0xFFFF, sum = 0
6823 00:41:20.311430 2, 0xFFFF, sum = 0
6824 00:41:20.314875 3, 0xFFFF, sum = 0
6825 00:41:20.314987 4, 0xFFFF, sum = 0
6826 00:41:20.318109 5, 0xFFFF, sum = 0
6827 00:41:20.318188 6, 0xFFFF, sum = 0
6828 00:41:20.321458 7, 0xFFFF, sum = 0
6829 00:41:20.321537 8, 0xFFFF, sum = 0
6830 00:41:20.324671 9, 0xFFFF, sum = 0
6831 00:41:20.324763 10, 0xFFFF, sum = 0
6832 00:41:20.328252 11, 0xFFFF, sum = 0
6833 00:41:20.331235 12, 0xFFFF, sum = 0
6834 00:41:20.331302 13, 0x0, sum = 1
6835 00:41:20.331359 14, 0x0, sum = 2
6836 00:41:20.334693 15, 0x0, sum = 3
6837 00:41:20.334758 16, 0x0, sum = 4
6838 00:41:20.338143 best_step = 14
6839 00:41:20.338219
6840 00:41:20.338279 ==
6841 00:41:20.341220 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 00:41:20.344614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 00:41:20.344730 ==
6844 00:41:20.347827 RX Vref Scan: 1
6845 00:41:20.347903
6846 00:41:20.347962 RX Vref 0 -> 0, step: 1
6847 00:41:20.348017
6848 00:41:20.351185 RX Delay -375 -> 252, step: 8
6849 00:41:20.351261
6850 00:41:20.354538 Set Vref, RX VrefLevel [Byte0]: 54
6851 00:41:20.358005 [Byte1]: 54
6852 00:41:20.363079
6853 00:41:20.363154 Final RX Vref Byte 0 = 54 to rank0
6854 00:41:20.366376 Final RX Vref Byte 1 = 54 to rank0
6855 00:41:20.369787 Final RX Vref Byte 0 = 54 to rank1
6856 00:41:20.373236 Final RX Vref Byte 1 = 54 to rank1==
6857 00:41:20.376449 Dram Type= 6, Freq= 0, CH_1, rank 0
6858 00:41:20.382933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 00:41:20.383010 ==
6860 00:41:20.383069 DQS Delay:
6861 00:41:20.386301 DQS0 = 52, DQS1 = 68
6862 00:41:20.386377 DQM Delay:
6863 00:41:20.386436 DQM0 = 9, DQM1 = 13
6864 00:41:20.389433 DQ Delay:
6865 00:41:20.393198 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6866 00:41:20.393274 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6867 00:41:20.396430 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6868 00:41:20.399186 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6869 00:41:20.399263
6870 00:41:20.399322
6871 00:41:20.409374 [DQSOSCAuto] RK0, (LSB)MR18= 0x6476, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 397 ps
6872 00:41:20.412909 CH1 RK0: MR19=C0C, MR18=6476
6873 00:41:20.419451 CH1_RK0: MR19=0xC0C, MR18=0x6476, DQSOSC=394, MR23=63, INC=380, DEC=253
6874 00:41:20.419530 ==
6875 00:41:20.422905 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 00:41:20.426170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 00:41:20.426269 ==
6878 00:41:20.429146 [Gating] SW mode calibration
6879 00:41:20.436101 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6880 00:41:20.439694 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6881 00:41:20.445964 0 11 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
6882 00:41:20.449290 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6883 00:41:20.452623 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 00:41:20.459305 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6885 00:41:20.462634 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 00:41:20.465835 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 00:41:20.472747 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 00:41:20.476167 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 00:41:20.479163 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 00:41:20.482656 Total UI for P1: 0, mck2ui 16
6891 00:41:20.485959 best dqsien dly found for B0: ( 0, 14, 24)
6892 00:41:20.489368 Total UI for P1: 0, mck2ui 16
6893 00:41:20.492911 best dqsien dly found for B1: ( 0, 14, 24)
6894 00:41:20.495724 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6895 00:41:20.499051 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6896 00:41:20.499159
6897 00:41:20.505831 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6898 00:41:20.509248 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6899 00:41:20.512665 [Gating] SW calibration Done
6900 00:41:20.512815 ==
6901 00:41:20.515921 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 00:41:20.519263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 00:41:20.519435 ==
6904 00:41:20.519566 RX Vref Scan: 0
6905 00:41:20.519688
6906 00:41:20.522407 RX Vref 0 -> 0, step: 1
6907 00:41:20.522484
6908 00:41:20.525926 RX Delay -410 -> 252, step: 16
6909 00:41:20.529252 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6910 00:41:20.535756 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6911 00:41:20.539175 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6912 00:41:20.542624 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6913 00:41:20.546097 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6914 00:41:20.552407 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6915 00:41:20.555837 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6916 00:41:20.559127 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6917 00:41:20.562232 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6918 00:41:20.569289 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6919 00:41:20.572428 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6920 00:41:20.575843 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6921 00:41:20.578610 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6922 00:41:20.585148 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6923 00:41:20.588707 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6924 00:41:20.591956 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6925 00:41:20.592039 ==
6926 00:41:20.595471 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 00:41:20.602292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 00:41:20.602443 ==
6929 00:41:20.602523 DQS Delay:
6930 00:41:20.605760 DQS0 = 59, DQS1 = 67
6931 00:41:20.605888 DQM Delay:
6932 00:41:20.605968 DQM0 = 19, DQM1 = 23
6933 00:41:20.608506 DQ Delay:
6934 00:41:20.612431 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6935 00:41:20.615569 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6936 00:41:20.615714 DQ8 =0, DQ9 =16, DQ10 =24, DQ11 =16
6937 00:41:20.622097 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6938 00:41:20.622225
6939 00:41:20.622326
6940 00:41:20.622418 ==
6941 00:41:20.625175 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 00:41:20.628634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 00:41:20.628789 ==
6944 00:41:20.628902
6945 00:41:20.629003
6946 00:41:20.631767 TX Vref Scan disable
6947 00:41:20.631931 == TX Byte 0 ==
6948 00:41:20.634934 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6949 00:41:20.641633 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6950 00:41:20.641711 == TX Byte 1 ==
6951 00:41:20.644980 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6952 00:41:20.651247 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6953 00:41:20.651325 ==
6954 00:41:20.654737 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 00:41:20.658060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 00:41:20.658137 ==
6957 00:41:20.658197
6958 00:41:20.658251
6959 00:41:20.661497 TX Vref Scan disable
6960 00:41:20.661573 == TX Byte 0 ==
6961 00:41:20.668207 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6962 00:41:20.671603 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6963 00:41:20.671681 == TX Byte 1 ==
6964 00:41:20.677764 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6965 00:41:20.681243 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6966 00:41:20.681323
6967 00:41:20.681383 [DATLAT]
6968 00:41:20.684166 Freq=400, CH1 RK1
6969 00:41:20.684243
6970 00:41:20.684302 DATLAT Default: 0xe
6971 00:41:20.687885 0, 0xFFFF, sum = 0
6972 00:41:20.687994 1, 0xFFFF, sum = 0
6973 00:41:20.691384 2, 0xFFFF, sum = 0
6974 00:41:20.691461 3, 0xFFFF, sum = 0
6975 00:41:20.694323 4, 0xFFFF, sum = 0
6976 00:41:20.694401 5, 0xFFFF, sum = 0
6977 00:41:20.697691 6, 0xFFFF, sum = 0
6978 00:41:20.697769 7, 0xFFFF, sum = 0
6979 00:41:20.701167 8, 0xFFFF, sum = 0
6980 00:41:20.701246 9, 0xFFFF, sum = 0
6981 00:41:20.704345 10, 0xFFFF, sum = 0
6982 00:41:20.707510 11, 0xFFFF, sum = 0
6983 00:41:20.707588 12, 0xFFFF, sum = 0
6984 00:41:20.710908 13, 0x0, sum = 1
6985 00:41:20.710986 14, 0x0, sum = 2
6986 00:41:20.711047 15, 0x0, sum = 3
6987 00:41:20.714208 16, 0x0, sum = 4
6988 00:41:20.714290 best_step = 14
6989 00:41:20.714350
6990 00:41:20.717543 ==
6991 00:41:20.717621 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 00:41:20.724160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 00:41:20.724238 ==
6994 00:41:20.724297 RX Vref Scan: 0
6995 00:41:20.724354
6996 00:41:20.727535 RX Vref 0 -> 0, step: 1
6997 00:41:20.727612
6998 00:41:20.730933 RX Delay -375 -> 252, step: 8
6999 00:41:20.737728 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7000 00:41:20.740997 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7001 00:41:20.744453 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7002 00:41:20.750590 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7003 00:41:20.754165 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
7004 00:41:20.757301 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7005 00:41:20.760862 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7006 00:41:20.767211 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7007 00:41:20.770392 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7008 00:41:20.773852 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7009 00:41:20.777387 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7010 00:41:20.783684 iDelay=217, Bit 11, Center -60 (-319 ~ 200) 520
7011 00:41:20.787285 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7012 00:41:20.790518 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7013 00:41:20.793607 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7014 00:41:20.800526 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7015 00:41:20.800603 ==
7016 00:41:20.803928 Dram Type= 6, Freq= 0, CH_1, rank 1
7017 00:41:20.807322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7018 00:41:20.807409 ==
7019 00:41:20.807470 DQS Delay:
7020 00:41:20.810271 DQS0 = 60, DQS1 = 64
7021 00:41:20.810347 DQM Delay:
7022 00:41:20.813842 DQM0 = 13, DQM1 = 10
7023 00:41:20.813919 DQ Delay:
7024 00:41:20.816984 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7025 00:41:20.820288 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7026 00:41:20.823608 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7027 00:41:20.826858 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7028 00:41:20.826934
7029 00:41:20.826993
7030 00:41:20.833757 [DQSOSCAuto] RK1, (LSB)MR18= 0x80b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
7031 00:41:20.837259 CH1 RK1: MR19=C0C, MR18=80B0
7032 00:41:20.843955 CH1_RK1: MR19=0xC0C, MR18=0x80B0, DQSOSC=387, MR23=63, INC=394, DEC=262
7033 00:41:20.847183 [RxdqsGatingPostProcess] freq 400
7034 00:41:20.853401 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7035 00:41:20.856528 best DQS0 dly(2T, 0.5T) = (0, 10)
7036 00:41:20.860177 best DQS1 dly(2T, 0.5T) = (0, 10)
7037 00:41:20.860256 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7038 00:41:20.863388 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7039 00:41:20.866609 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 00:41:20.870216 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 00:41:20.873645 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 00:41:20.876920 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 00:41:20.880353 Pre-setting of DQS Precalculation
7044 00:41:20.886712 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7045 00:41:20.893282 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7046 00:41:20.900100 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7047 00:41:20.900177
7048 00:41:20.900236
7049 00:41:20.903204 [Calibration Summary] 800 Mbps
7050 00:41:20.903280 CH 0, Rank 0
7051 00:41:20.906731 SW Impedance : PASS
7052 00:41:20.910101 DUTY Scan : NO K
7053 00:41:20.910179 ZQ Calibration : PASS
7054 00:41:20.913028 Jitter Meter : NO K
7055 00:41:20.916389 CBT Training : PASS
7056 00:41:20.916465 Write leveling : PASS
7057 00:41:20.919882 RX DQS gating : PASS
7058 00:41:20.923048 RX DQ/DQS(RDDQC) : PASS
7059 00:41:20.923125 TX DQ/DQS : PASS
7060 00:41:20.926289 RX DATLAT : PASS
7061 00:41:20.926366 RX DQ/DQS(Engine): PASS
7062 00:41:20.929930 TX OE : NO K
7063 00:41:20.930007 All Pass.
7064 00:41:20.930066
7065 00:41:20.933206 CH 0, Rank 1
7066 00:41:20.933282 SW Impedance : PASS
7067 00:41:20.936663 DUTY Scan : NO K
7068 00:41:20.939503 ZQ Calibration : PASS
7069 00:41:20.939579 Jitter Meter : NO K
7070 00:41:20.942975 CBT Training : PASS
7071 00:41:20.946356 Write leveling : NO K
7072 00:41:20.946432 RX DQS gating : PASS
7073 00:41:20.949791 RX DQ/DQS(RDDQC) : PASS
7074 00:41:20.953110 TX DQ/DQS : PASS
7075 00:41:20.953187 RX DATLAT : PASS
7076 00:41:20.956538 RX DQ/DQS(Engine): PASS
7077 00:41:20.959906 TX OE : NO K
7078 00:41:20.959982 All Pass.
7079 00:41:20.960051
7080 00:41:20.960107 CH 1, Rank 0
7081 00:41:20.963078 SW Impedance : PASS
7082 00:41:20.966326 DUTY Scan : NO K
7083 00:41:20.966403 ZQ Calibration : PASS
7084 00:41:20.969813 Jitter Meter : NO K
7085 00:41:20.973126 CBT Training : PASS
7086 00:41:20.973203 Write leveling : PASS
7087 00:41:20.976416 RX DQS gating : PASS
7088 00:41:20.979672 RX DQ/DQS(RDDQC) : PASS
7089 00:41:20.979749 TX DQ/DQS : PASS
7090 00:41:20.983046 RX DATLAT : PASS
7091 00:41:20.983123 RX DQ/DQS(Engine): PASS
7092 00:41:20.986286 TX OE : NO K
7093 00:41:20.986363 All Pass.
7094 00:41:20.986422
7095 00:41:20.989229 CH 1, Rank 1
7096 00:41:20.989305 SW Impedance : PASS
7097 00:41:20.992721 DUTY Scan : NO K
7098 00:41:20.996009 ZQ Calibration : PASS
7099 00:41:20.996086 Jitter Meter : NO K
7100 00:41:20.999415 CBT Training : PASS
7101 00:41:21.002947 Write leveling : NO K
7102 00:41:21.003023 RX DQS gating : PASS
7103 00:41:21.006297 RX DQ/DQS(RDDQC) : PASS
7104 00:41:21.009335 TX DQ/DQS : PASS
7105 00:41:21.009411 RX DATLAT : PASS
7106 00:41:21.012558 RX DQ/DQS(Engine): PASS
7107 00:41:21.016165 TX OE : NO K
7108 00:41:21.016242 All Pass.
7109 00:41:21.016312
7110 00:41:21.016368 DramC Write-DBI off
7111 00:41:21.019712 PER_BANK_REFRESH: Hybrid Mode
7112 00:41:21.023054 TX_TRACKING: ON
7113 00:41:21.029090 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7114 00:41:21.032584 [FAST_K] Save calibration result to emmc
7115 00:41:21.039367 dramc_set_vcore_voltage set vcore to 725000
7116 00:41:21.039444 Read voltage for 1600, 0
7117 00:41:21.042666 Vio18 = 0
7118 00:41:21.042742 Vcore = 725000
7119 00:41:21.042801 Vdram = 0
7120 00:41:21.046138 Vddq = 0
7121 00:41:21.046214 Vmddr = 0
7122 00:41:21.049012 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7123 00:41:21.055892 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7124 00:41:21.059292 MEM_TYPE=3, freq_sel=13
7125 00:41:21.062615 sv_algorithm_assistance_LP4_3733
7126 00:41:21.066123 ============ PULL DRAM RESETB DOWN ============
7127 00:41:21.069373 ========== PULL DRAM RESETB DOWN end =========
7128 00:41:21.072438 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7129 00:41:21.075858 ===================================
7130 00:41:21.079383 LPDDR4 DRAM CONFIGURATION
7131 00:41:21.082232 ===================================
7132 00:41:21.085970 EX_ROW_EN[0] = 0x0
7133 00:41:21.086047 EX_ROW_EN[1] = 0x0
7134 00:41:21.089168 LP4Y_EN = 0x0
7135 00:41:21.089245 WORK_FSP = 0x1
7136 00:41:21.092565 WL = 0x5
7137 00:41:21.092642 RL = 0x5
7138 00:41:21.095955 BL = 0x2
7139 00:41:21.096031 RPST = 0x0
7140 00:41:21.099200 RD_PRE = 0x0
7141 00:41:21.099277 WR_PRE = 0x1
7142 00:41:21.102568 WR_PST = 0x1
7143 00:41:21.105610 DBI_WR = 0x0
7144 00:41:21.105686 DBI_RD = 0x0
7145 00:41:21.108998 OTF = 0x1
7146 00:41:21.112406 ===================================
7147 00:41:21.115908 ===================================
7148 00:41:21.115985 ANA top config
7149 00:41:21.118749 ===================================
7150 00:41:21.122284 DLL_ASYNC_EN = 0
7151 00:41:21.125591 ALL_SLAVE_EN = 0
7152 00:41:21.125667 NEW_RANK_MODE = 1
7153 00:41:21.128759 DLL_IDLE_MODE = 1
7154 00:41:21.132114 LP45_APHY_COMB_EN = 1
7155 00:41:21.135610 TX_ODT_DIS = 0
7156 00:41:21.135687 NEW_8X_MODE = 1
7157 00:41:21.138699 ===================================
7158 00:41:21.142229 ===================================
7159 00:41:21.145262 data_rate = 3200
7160 00:41:21.148868 CKR = 1
7161 00:41:21.152202 DQ_P2S_RATIO = 8
7162 00:41:21.155109 ===================================
7163 00:41:21.158420 CA_P2S_RATIO = 8
7164 00:41:21.161804 DQ_CA_OPEN = 0
7165 00:41:21.161880 DQ_SEMI_OPEN = 0
7166 00:41:21.165115 CA_SEMI_OPEN = 0
7167 00:41:21.168614 CA_FULL_RATE = 0
7168 00:41:21.172086 DQ_CKDIV4_EN = 0
7169 00:41:21.175444 CA_CKDIV4_EN = 0
7170 00:41:21.178566 CA_PREDIV_EN = 0
7171 00:41:21.178643 PH8_DLY = 12
7172 00:41:21.181778 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7173 00:41:21.185311 DQ_AAMCK_DIV = 4
7174 00:41:21.188745 CA_AAMCK_DIV = 4
7175 00:41:21.191590 CA_ADMCK_DIV = 4
7176 00:41:21.195031 DQ_TRACK_CA_EN = 0
7177 00:41:21.198425 CA_PICK = 1600
7178 00:41:21.198502 CA_MCKIO = 1600
7179 00:41:21.201777 MCKIO_SEMI = 0
7180 00:41:21.204920 PLL_FREQ = 3068
7181 00:41:21.208517 DQ_UI_PI_RATIO = 32
7182 00:41:21.211453 CA_UI_PI_RATIO = 0
7183 00:41:21.215032 ===================================
7184 00:41:21.218528 ===================================
7185 00:41:21.221479 memory_type:LPDDR4
7186 00:41:21.221556 GP_NUM : 10
7187 00:41:21.224963 SRAM_EN : 1
7188 00:41:21.225039 MD32_EN : 0
7189 00:41:21.228424 ===================================
7190 00:41:21.231280 [ANA_INIT] >>>>>>>>>>>>>>
7191 00:41:21.235103 <<<<<< [CONFIGURE PHASE]: ANA_TX
7192 00:41:21.237891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7193 00:41:21.241483 ===================================
7194 00:41:21.245336 data_rate = 3200,PCW = 0X7600
7195 00:41:21.248351 ===================================
7196 00:41:21.251459 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7197 00:41:21.258538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7198 00:41:21.261626 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7199 00:41:21.268370 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7200 00:41:21.271822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7201 00:41:21.274724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7202 00:41:21.274806 [ANA_INIT] flow start
7203 00:41:21.278209 [ANA_INIT] PLL >>>>>>>>
7204 00:41:21.281564 [ANA_INIT] PLL <<<<<<<<
7205 00:41:21.281640 [ANA_INIT] MIDPI >>>>>>>>
7206 00:41:21.284881 [ANA_INIT] MIDPI <<<<<<<<
7207 00:41:21.287956 [ANA_INIT] DLL >>>>>>>>
7208 00:41:21.288032 [ANA_INIT] DLL <<<<<<<<
7209 00:41:21.291252 [ANA_INIT] flow end
7210 00:41:21.294675 ============ LP4 DIFF to SE enter ============
7211 00:41:21.298107 ============ LP4 DIFF to SE exit ============
7212 00:41:21.301514 [ANA_INIT] <<<<<<<<<<<<<
7213 00:41:21.304949 [Flow] Enable top DCM control >>>>>
7214 00:41:21.308350 [Flow] Enable top DCM control <<<<<
7215 00:41:21.311223 Enable DLL master slave shuffle
7216 00:41:21.317870 ==============================================================
7217 00:41:21.317948 Gating Mode config
7218 00:41:21.324601 ==============================================================
7219 00:41:21.324726 Config description:
7220 00:41:21.334964 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7221 00:41:21.341206 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7222 00:41:21.347644 SELPH_MODE 0: By rank 1: By Phase
7223 00:41:21.354708 ==============================================================
7224 00:41:21.354809 GAT_TRACK_EN = 1
7225 00:41:21.357891 RX_GATING_MODE = 2
7226 00:41:21.361179 RX_GATING_TRACK_MODE = 2
7227 00:41:21.364610 SELPH_MODE = 1
7228 00:41:21.367644 PICG_EARLY_EN = 1
7229 00:41:21.371187 VALID_LAT_VALUE = 1
7230 00:41:21.377729 ==============================================================
7231 00:41:21.381123 Enter into Gating configuration >>>>
7232 00:41:21.384120 Exit from Gating configuration <<<<
7233 00:41:21.387600 Enter into DVFS_PRE_config >>>>>
7234 00:41:21.397876 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7235 00:41:21.400887 Exit from DVFS_PRE_config <<<<<
7236 00:41:21.404264 Enter into PICG configuration >>>>
7237 00:41:21.407792 Exit from PICG configuration <<<<
7238 00:41:21.411281 [RX_INPUT] configuration >>>>>
7239 00:41:21.411359 [RX_INPUT] configuration <<<<<
7240 00:41:21.417532 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7241 00:41:21.424353 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7242 00:41:21.427605 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7243 00:41:21.434136 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7244 00:41:21.440973 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7245 00:41:21.447309 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7246 00:41:21.450675 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7247 00:41:21.453833 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7248 00:41:21.460827 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7249 00:41:21.464108 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7250 00:41:21.467427 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7251 00:41:21.473719 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7252 00:41:21.477120 ===================================
7253 00:41:21.477198 LPDDR4 DRAM CONFIGURATION
7254 00:41:21.480660 ===================================
7255 00:41:21.483733 EX_ROW_EN[0] = 0x0
7256 00:41:21.483832 EX_ROW_EN[1] = 0x0
7257 00:41:21.487347 LP4Y_EN = 0x0
7258 00:41:21.487423 WORK_FSP = 0x1
7259 00:41:21.490866 WL = 0x5
7260 00:41:21.493724 RL = 0x5
7261 00:41:21.493801 BL = 0x2
7262 00:41:21.497219 RPST = 0x0
7263 00:41:21.497295 RD_PRE = 0x0
7264 00:41:21.500517 WR_PRE = 0x1
7265 00:41:21.500593 WR_PST = 0x1
7266 00:41:21.503614 DBI_WR = 0x0
7267 00:41:21.503690 DBI_RD = 0x0
7268 00:41:21.507340 OTF = 0x1
7269 00:41:21.510310 ===================================
7270 00:41:21.513691 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7271 00:41:21.516864 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7272 00:41:21.523847 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7273 00:41:21.523926 ===================================
7274 00:41:21.526745 LPDDR4 DRAM CONFIGURATION
7275 00:41:21.530165 ===================================
7276 00:41:21.533392 EX_ROW_EN[0] = 0x10
7277 00:41:21.533468 EX_ROW_EN[1] = 0x0
7278 00:41:21.536840 LP4Y_EN = 0x0
7279 00:41:21.536917 WORK_FSP = 0x1
7280 00:41:21.540384 WL = 0x5
7281 00:41:21.540461 RL = 0x5
7282 00:41:21.543389 BL = 0x2
7283 00:41:21.546635 RPST = 0x0
7284 00:41:21.546735 RD_PRE = 0x0
7285 00:41:21.550008 WR_PRE = 0x1
7286 00:41:21.550084 WR_PST = 0x1
7287 00:41:21.553275 DBI_WR = 0x0
7288 00:41:21.553374 DBI_RD = 0x0
7289 00:41:21.556745 OTF = 0x1
7290 00:41:21.560078 ===================================
7291 00:41:21.563139 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7292 00:41:21.566901 ==
7293 00:41:21.569988 Dram Type= 6, Freq= 0, CH_0, rank 0
7294 00:41:21.573166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 00:41:21.573243 ==
7296 00:41:21.576454 [Duty_Offset_Calibration]
7297 00:41:21.576531 B0:2 B1:0 CA:3
7298 00:41:21.576590
7299 00:41:21.580011 [DutyScan_Calibration_Flow] k_type=0
7300 00:41:21.589769
7301 00:41:21.589845 ==CLK 0==
7302 00:41:21.592957 Final CLK duty delay cell = 0
7303 00:41:21.596558 [0] MAX Duty = 5031%(X100), DQS PI = 12
7304 00:41:21.600134 [0] MIN Duty = 4907%(X100), DQS PI = 6
7305 00:41:21.600212 [0] AVG Duty = 4969%(X100)
7306 00:41:21.603551
7307 00:41:21.606232 CH0 CLK Duty spec in!! Max-Min= 124%
7308 00:41:21.609441 [DutyScan_Calibration_Flow] ====Done====
7309 00:41:21.609543
7310 00:41:21.613000 [DutyScan_Calibration_Flow] k_type=1
7311 00:41:21.629701
7312 00:41:21.629807 ==DQS 0 ==
7313 00:41:21.633136 Final DQS duty delay cell = 0
7314 00:41:21.636530 [0] MAX Duty = 5125%(X100), DQS PI = 30
7315 00:41:21.639881 [0] MIN Duty = 4875%(X100), DQS PI = 52
7316 00:41:21.643345 [0] AVG Duty = 5000%(X100)
7317 00:41:21.643423
7318 00:41:21.643482 ==DQS 1 ==
7319 00:41:21.646208 Final DQS duty delay cell = 0
7320 00:41:21.649704 [0] MAX Duty = 5156%(X100), DQS PI = 32
7321 00:41:21.653123 [0] MIN Duty = 5062%(X100), DQS PI = 0
7322 00:41:21.656572 [0] AVG Duty = 5109%(X100)
7323 00:41:21.656655
7324 00:41:21.659996 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7325 00:41:21.660073
7326 00:41:21.663136 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7327 00:41:21.666727 [DutyScan_Calibration_Flow] ====Done====
7328 00:41:21.666804
7329 00:41:21.669776 [DutyScan_Calibration_Flow] k_type=3
7330 00:41:21.687561
7331 00:41:21.687639 ==DQM 0 ==
7332 00:41:21.690948 Final DQM duty delay cell = 0
7333 00:41:21.694301 [0] MAX Duty = 5187%(X100), DQS PI = 30
7334 00:41:21.697915 [0] MIN Duty = 4844%(X100), DQS PI = 52
7335 00:41:21.700885 [0] AVG Duty = 5015%(X100)
7336 00:41:21.700962
7337 00:41:21.701022 ==DQM 1 ==
7338 00:41:21.704362 Final DQM duty delay cell = 4
7339 00:41:21.707269 [4] MAX Duty = 5156%(X100), DQS PI = 52
7340 00:41:21.710951 [4] MIN Duty = 5000%(X100), DQS PI = 14
7341 00:41:21.714278 [4] AVG Duty = 5078%(X100)
7342 00:41:21.714355
7343 00:41:21.717606 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7344 00:41:21.717708
7345 00:41:21.721060 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7346 00:41:21.724398 [DutyScan_Calibration_Flow] ====Done====
7347 00:41:21.724475
7348 00:41:21.727773 [DutyScan_Calibration_Flow] k_type=2
7349 00:41:21.744122
7350 00:41:21.744199 ==DQ 0 ==
7351 00:41:21.747609 Final DQ duty delay cell = -4
7352 00:41:21.751052 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7353 00:41:21.754478 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7354 00:41:21.757340 [-4] AVG Duty = 4938%(X100)
7355 00:41:21.757417
7356 00:41:21.757477 ==DQ 1 ==
7357 00:41:21.760658 Final DQ duty delay cell = 0
7358 00:41:21.764063 [0] MAX Duty = 5156%(X100), DQS PI = 60
7359 00:41:21.767643 [0] MIN Duty = 5000%(X100), DQS PI = 16
7360 00:41:21.767720 [0] AVG Duty = 5078%(X100)
7361 00:41:21.771130
7362 00:41:21.774219 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7363 00:41:21.774297
7364 00:41:21.778092 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7365 00:41:21.780876 [DutyScan_Calibration_Flow] ====Done====
7366 00:41:21.780952 ==
7367 00:41:21.784352 Dram Type= 6, Freq= 0, CH_1, rank 0
7368 00:41:21.787574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7369 00:41:21.787651 ==
7370 00:41:21.791019 [Duty_Offset_Calibration]
7371 00:41:21.791095 B0:1 B1:-2 CA:1
7372 00:41:21.791153
7373 00:41:21.793880 [DutyScan_Calibration_Flow] k_type=0
7374 00:41:21.804733
7375 00:41:21.804814 ==CLK 0==
7376 00:41:21.808007 Final CLK duty delay cell = 0
7377 00:41:21.811327 [0] MAX Duty = 5062%(X100), DQS PI = 20
7378 00:41:21.814423 [0] MIN Duty = 4844%(X100), DQS PI = 2
7379 00:41:21.814518 [0] AVG Duty = 4953%(X100)
7380 00:41:21.817852
7381 00:41:21.821206 CH1 CLK Duty spec in!! Max-Min= 218%
7382 00:41:21.824495 [DutyScan_Calibration_Flow] ====Done====
7383 00:41:21.824587
7384 00:41:21.827676 [DutyScan_Calibration_Flow] k_type=1
7385 00:41:21.844091
7386 00:41:21.844183 ==DQS 0 ==
7387 00:41:21.847630 Final DQS duty delay cell = 0
7388 00:41:21.851041 [0] MAX Duty = 5187%(X100), DQS PI = 24
7389 00:41:21.854498 [0] MIN Duty = 5031%(X100), DQS PI = 54
7390 00:41:21.857904 [0] AVG Duty = 5109%(X100)
7391 00:41:21.857987
7392 00:41:21.858071 ==DQS 1 ==
7393 00:41:21.860717 Final DQS duty delay cell = 0
7394 00:41:21.864225 [0] MAX Duty = 5093%(X100), DQS PI = 60
7395 00:41:21.867663 [0] MIN Duty = 4844%(X100), DQS PI = 24
7396 00:41:21.871034 [0] AVG Duty = 4968%(X100)
7397 00:41:21.871132
7398 00:41:21.874596 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7399 00:41:21.874685
7400 00:41:21.877424 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7401 00:41:21.880895 [DutyScan_Calibration_Flow] ====Done====
7402 00:41:21.880962
7403 00:41:21.884365 [DutyScan_Calibration_Flow] k_type=3
7404 00:41:21.901551
7405 00:41:21.901656 ==DQM 0 ==
7406 00:41:21.904702 Final DQM duty delay cell = 0
7407 00:41:21.908157 [0] MAX Duty = 5031%(X100), DQS PI = 24
7408 00:41:21.911454 [0] MIN Duty = 4813%(X100), DQS PI = 54
7409 00:41:21.914528 [0] AVG Duty = 4922%(X100)
7410 00:41:21.914604
7411 00:41:21.914663 ==DQM 1 ==
7412 00:41:21.918006 Final DQM duty delay cell = 0
7413 00:41:21.921170 [0] MAX Duty = 5094%(X100), DQS PI = 36
7414 00:41:21.924801 [0] MIN Duty = 4875%(X100), DQS PI = 24
7415 00:41:21.927756 [0] AVG Duty = 4984%(X100)
7416 00:41:21.927856
7417 00:41:21.930932 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7418 00:41:21.931032
7419 00:41:21.934409 CH1 DQM 1 Duty spec in!! Max-Min= 219%
7420 00:41:21.937665 [DutyScan_Calibration_Flow] ====Done====
7421 00:41:21.937756
7422 00:41:21.940754 [DutyScan_Calibration_Flow] k_type=2
7423 00:41:21.958601
7424 00:41:21.958696 ==DQ 0 ==
7425 00:41:21.961398 Final DQ duty delay cell = 0
7426 00:41:21.964848 [0] MAX Duty = 5093%(X100), DQS PI = 22
7427 00:41:21.968310 [0] MIN Duty = 4907%(X100), DQS PI = 58
7428 00:41:21.968401 [0] AVG Duty = 5000%(X100)
7429 00:41:21.971718
7430 00:41:21.971808 ==DQ 1 ==
7431 00:41:21.974569 Final DQ duty delay cell = 0
7432 00:41:21.978078 [0] MAX Duty = 5125%(X100), DQS PI = 34
7433 00:41:21.981479 [0] MIN Duty = 4969%(X100), DQS PI = 24
7434 00:41:21.981546 [0] AVG Duty = 5047%(X100)
7435 00:41:21.984864
7436 00:41:21.988191 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7437 00:41:21.988280
7438 00:41:21.991574 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7439 00:41:21.994522 [DutyScan_Calibration_Flow] ====Done====
7440 00:41:21.998345 nWR fixed to 30
7441 00:41:21.998436 [ModeRegInit_LP4] CH0 RK0
7442 00:41:22.000983 [ModeRegInit_LP4] CH0 RK1
7443 00:41:22.004323 [ModeRegInit_LP4] CH1 RK0
7444 00:41:22.007771 [ModeRegInit_LP4] CH1 RK1
7445 00:41:22.007863 match AC timing 5
7446 00:41:22.014597 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7447 00:41:22.017906 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7448 00:41:22.021185 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7449 00:41:22.027982 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7450 00:41:22.030948 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7451 00:41:22.031017 [MiockJmeterHQA]
7452 00:41:22.031075
7453 00:41:22.034650 [DramcMiockJmeter] u1RxGatingPI = 0
7454 00:41:22.038020 0 : 4253, 4026
7455 00:41:22.038112 4 : 4252, 4026
7456 00:41:22.038198 8 : 4363, 4137
7457 00:41:22.041504 12 : 4252, 4027
7458 00:41:22.041573 16 : 4258, 4032
7459 00:41:22.044361 20 : 4363, 4137
7460 00:41:22.044452 24 : 4252, 4027
7461 00:41:22.047825 28 : 4252, 4027
7462 00:41:22.047897 32 : 4253, 4026
7463 00:41:22.051242 36 : 4255, 4029
7464 00:41:22.051340 40 : 4252, 4027
7465 00:41:22.051427 44 : 4252, 4027
7466 00:41:22.054273 48 : 4365, 4140
7467 00:41:22.054343 52 : 4252, 4027
7468 00:41:22.057769 56 : 4254, 4029
7469 00:41:22.057848 60 : 4250, 4026
7470 00:41:22.061079 64 : 4361, 4137
7471 00:41:22.061146 68 : 4250, 4027
7472 00:41:22.064396 72 : 4361, 4137
7473 00:41:22.064489 76 : 4250, 4027
7474 00:41:22.064573 80 : 4250, 4026
7475 00:41:22.067634 84 : 4250, 4027
7476 00:41:22.067756 88 : 4252, 4029
7477 00:41:22.071029 92 : 4361, 4137
7478 00:41:22.071095 96 : 4250, 4027
7479 00:41:22.074381 100 : 4360, 4137
7480 00:41:22.074471 104 : 4361, 3792
7481 00:41:22.077826 108 : 4250, 0
7482 00:41:22.077891 112 : 4250, 0
7483 00:41:22.077946 116 : 4252, 0
7484 00:41:22.081136 120 : 4361, 0
7485 00:41:22.081203 124 : 4250, 0
7486 00:41:22.081297 128 : 4250, 0
7487 00:41:22.084606 132 : 4250, 0
7488 00:41:22.084720 136 : 4360, 0
7489 00:41:22.087428 140 : 4360, 0
7490 00:41:22.087491 144 : 4250, 0
7491 00:41:22.087545 148 : 4250, 0
7492 00:41:22.091277 152 : 4363, 0
7493 00:41:22.091368 156 : 4250, 0
7494 00:41:22.094158 160 : 4250, 0
7495 00:41:22.094247 164 : 4250, 0
7496 00:41:22.094328 168 : 4252, 0
7497 00:41:22.097544 172 : 4361, 0
7498 00:41:22.097607 176 : 4250, 0
7499 00:41:22.100886 180 : 4250, 0
7500 00:41:22.100954 184 : 4250, 0
7501 00:41:22.101007 188 : 4360, 0
7502 00:41:22.104241 192 : 4361, 0
7503 00:41:22.104331 196 : 4250, 0
7504 00:41:22.107588 200 : 4250, 0
7505 00:41:22.107680 204 : 4250, 0
7506 00:41:22.107774 208 : 4252, 0
7507 00:41:22.110665 212 : 4250, 0
7508 00:41:22.110729 216 : 4250, 0
7509 00:41:22.110813 220 : 4252, 0
7510 00:41:22.114043 224 : 4361, 0
7511 00:41:22.114135 228 : 4250, 0
7512 00:41:22.117509 232 : 4361, 0
7513 00:41:22.117592 236 : 4250, 846
7514 00:41:22.120993 240 : 4361, 4137
7515 00:41:22.121062 244 : 4253, 4029
7516 00:41:22.121117 248 : 4250, 4026
7517 00:41:22.123834 252 : 4250, 4027
7518 00:41:22.123926 256 : 4252, 4030
7519 00:41:22.127180 260 : 4250, 4027
7520 00:41:22.127268 264 : 4250, 4027
7521 00:41:22.130534 268 : 4250, 4027
7522 00:41:22.130623 272 : 4252, 4029
7523 00:41:22.133949 276 : 4250, 4027
7524 00:41:22.134013 280 : 4361, 4137
7525 00:41:22.137256 284 : 4361, 4137
7526 00:41:22.137321 288 : 4250, 4026
7527 00:41:22.140536 292 : 4363, 4140
7528 00:41:22.140625 296 : 4361, 4137
7529 00:41:22.143984 300 : 4250, 4026
7530 00:41:22.144075 304 : 4250, 4027
7531 00:41:22.147019 308 : 4252, 4029
7532 00:41:22.147084 312 : 4250, 4027
7533 00:41:22.147138 316 : 4250, 4027
7534 00:41:22.150445 320 : 4250, 4027
7535 00:41:22.150510 324 : 4252, 4030
7536 00:41:22.153656 328 : 4250, 4027
7537 00:41:22.153720 332 : 4361, 4137
7538 00:41:22.157073 336 : 4361, 4137
7539 00:41:22.157141 340 : 4250, 4026
7540 00:41:22.160511 344 : 4363, 4140
7541 00:41:22.160600 348 : 4361, 4137
7542 00:41:22.164075 352 : 4250, 4020
7543 00:41:22.164166 356 : 4250, 2705
7544 00:41:22.167033 360 : 4252, 1
7545 00:41:22.167121
7546 00:41:22.167201 MIOCK jitter meter ch=0
7547 00:41:22.167281
7548 00:41:22.170420 1T = (360-108) = 252 dly cells
7549 00:41:22.176840 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7550 00:41:22.176907 ==
7551 00:41:22.180126 Dram Type= 6, Freq= 0, CH_0, rank 0
7552 00:41:22.183425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 00:41:22.183517 ==
7554 00:41:22.189994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7555 00:41:22.193518 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7556 00:41:22.196778 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7557 00:41:22.203287 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7558 00:41:22.213053 [CA 0] Center 43 (13~74) winsize 62
7559 00:41:22.216339 [CA 1] Center 43 (13~74) winsize 62
7560 00:41:22.219570 [CA 2] Center 39 (10~68) winsize 59
7561 00:41:22.222841 [CA 3] Center 39 (10~68) winsize 59
7562 00:41:22.226291 [CA 4] Center 36 (7~66) winsize 60
7563 00:41:22.229779 [CA 5] Center 36 (7~66) winsize 60
7564 00:41:22.229871
7565 00:41:22.233198 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7566 00:41:22.233265
7567 00:41:22.239432 [CATrainingPosCal] consider 1 rank data
7568 00:41:22.239501 u2DelayCellTimex100 = 258/100 ps
7569 00:41:22.246106 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7570 00:41:22.249741 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7571 00:41:22.252785 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7572 00:41:22.256165 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7573 00:41:22.259735 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7574 00:41:22.262758 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7575 00:41:22.262847
7576 00:41:22.266116 CA PerBit enable=1, Macro0, CA PI delay=36
7577 00:41:22.266208
7578 00:41:22.269626 [CBTSetCACLKResult] CA Dly = 36
7579 00:41:22.272526 CS Dly: 11 (0~42)
7580 00:41:22.275819 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7581 00:41:22.279337 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7582 00:41:22.279436 ==
7583 00:41:22.282634 Dram Type= 6, Freq= 0, CH_0, rank 1
7584 00:41:22.289031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 00:41:22.289101 ==
7586 00:41:22.292382 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7587 00:41:22.299037 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7588 00:41:22.302381 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7589 00:41:22.308722 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7590 00:41:22.317062 [CA 0] Center 44 (14~75) winsize 62
7591 00:41:22.320416 [CA 1] Center 43 (13~74) winsize 62
7592 00:41:22.323762 [CA 2] Center 39 (10~69) winsize 60
7593 00:41:22.326903 [CA 3] Center 39 (10~69) winsize 60
7594 00:41:22.330795 [CA 4] Center 37 (8~67) winsize 60
7595 00:41:22.333831 [CA 5] Center 37 (7~67) winsize 61
7596 00:41:22.333931
7597 00:41:22.337106 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7598 00:41:22.337173
7599 00:41:22.340447 [CATrainingPosCal] consider 2 rank data
7600 00:41:22.343866 u2DelayCellTimex100 = 258/100 ps
7601 00:41:22.350210 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7602 00:41:22.353702 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7603 00:41:22.357066 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7604 00:41:22.360112 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7605 00:41:22.363757 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7606 00:41:22.366588 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7607 00:41:22.366656
7608 00:41:22.370283 CA PerBit enable=1, Macro0, CA PI delay=36
7609 00:41:22.370351
7610 00:41:22.373590 [CBTSetCACLKResult] CA Dly = 36
7611 00:41:22.377515 CS Dly: 11 (0~42)
7612 00:41:22.380157 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7613 00:41:22.383507 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7614 00:41:22.383603
7615 00:41:22.386734 ----->DramcWriteLeveling(PI) begin...
7616 00:41:22.386826 ==
7617 00:41:22.390110 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 00:41:22.396997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 00:41:22.397082 ==
7620 00:41:22.399881 Write leveling (Byte 0): 35 => 35
7621 00:41:22.403785 Write leveling (Byte 1): 28 => 28
7622 00:41:22.403885 DramcWriteLeveling(PI) end<-----
7623 00:41:22.403968
7624 00:41:22.406634 ==
7625 00:41:22.409972 Dram Type= 6, Freq= 0, CH_0, rank 0
7626 00:41:22.413146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 00:41:22.413215 ==
7628 00:41:22.416771 [Gating] SW mode calibration
7629 00:41:22.423168 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7630 00:41:22.426857 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7631 00:41:22.433489 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 00:41:22.436734 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 00:41:22.439650 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 00:41:22.446726 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 00:41:22.449714 1 4 16 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7636 00:41:22.453042 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7637 00:41:22.459527 1 4 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7638 00:41:22.463041 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 00:41:22.466402 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7640 00:41:22.473137 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7641 00:41:22.476088 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7642 00:41:22.479731 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7643 00:41:22.486012 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7644 00:41:22.489675 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7645 00:41:22.493120 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7646 00:41:22.499396 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 00:41:22.502830 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 00:41:22.506374 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 00:41:22.512736 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 00:41:22.515962 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7651 00:41:22.519434 1 6 16 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7652 00:41:22.526252 1 6 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7653 00:41:22.529596 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7654 00:41:22.532776 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 00:41:22.539529 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 00:41:22.542751 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 00:41:22.545828 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 00:41:22.552657 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7659 00:41:22.556822 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7660 00:41:22.559382 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7661 00:41:22.562370 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7662 00:41:22.569238 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7663 00:41:22.572695 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 00:41:22.575564 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 00:41:22.582603 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 00:41:22.585484 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 00:41:22.589376 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 00:41:22.595807 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 00:41:22.598980 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 00:41:22.602420 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 00:41:22.608738 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 00:41:22.612295 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 00:41:22.615257 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 00:41:22.622155 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7675 00:41:22.625675 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7676 00:41:22.628591 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7677 00:41:22.632249 Total UI for P1: 0, mck2ui 16
7678 00:41:22.635550 best dqsien dly found for B0: ( 1, 9, 14)
7679 00:41:22.642143 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7680 00:41:22.645206 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 00:41:22.648526 Total UI for P1: 0, mck2ui 16
7682 00:41:22.652224 best dqsien dly found for B1: ( 1, 9, 22)
7683 00:41:22.655243 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7684 00:41:22.658971 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7685 00:41:22.659049
7686 00:41:22.662094 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7687 00:41:22.665546 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7688 00:41:22.668529 [Gating] SW calibration Done
7689 00:41:22.668630 ==
7690 00:41:22.671893 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 00:41:22.675901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 00:41:22.678983 ==
7693 00:41:22.679061 RX Vref Scan: 0
7694 00:41:22.679121
7695 00:41:22.682228 RX Vref 0 -> 0, step: 1
7696 00:41:22.682306
7697 00:41:22.685161 RX Delay 0 -> 252, step: 8
7698 00:41:22.688504 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7699 00:41:22.692134 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7700 00:41:22.695119 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7701 00:41:22.698542 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7702 00:41:22.705166 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7703 00:41:22.708801 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7704 00:41:22.711695 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7705 00:41:22.715284 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7706 00:41:22.718650 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7707 00:41:22.725153 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7708 00:41:22.728489 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7709 00:41:22.731889 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7710 00:41:22.734785 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7711 00:41:22.738130 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7712 00:41:22.744829 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7713 00:41:22.748248 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7714 00:41:22.748347 ==
7715 00:41:22.751704 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 00:41:22.754604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 00:41:22.754694 ==
7718 00:41:22.758008 DQS Delay:
7719 00:41:22.758103 DQS0 = 0, DQS1 = 0
7720 00:41:22.758185 DQM Delay:
7721 00:41:22.761205 DQM0 = 128, DQM1 = 124
7722 00:41:22.761269 DQ Delay:
7723 00:41:22.764840 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7724 00:41:22.768268 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7725 00:41:22.774619 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7726 00:41:22.778247 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7727 00:41:22.778313
7728 00:41:22.778381
7729 00:41:22.778434 ==
7730 00:41:22.781441 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 00:41:22.784884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 00:41:22.784950 ==
7733 00:41:22.785004
7734 00:41:22.785070
7735 00:41:22.788030 TX Vref Scan disable
7736 00:41:22.788116 == TX Byte 0 ==
7737 00:41:22.795005 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7738 00:41:22.797713 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7739 00:41:22.797780 == TX Byte 1 ==
7740 00:41:22.804426 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7741 00:41:22.807987 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7742 00:41:22.808057 ==
7743 00:41:22.811357 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 00:41:22.814294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 00:41:22.814388 ==
7746 00:41:22.829462
7747 00:41:22.832857 TX Vref early break, caculate TX vref
7748 00:41:22.835691 TX Vref=16, minBit 8, minWin=21, winSum=354
7749 00:41:22.839113 TX Vref=18, minBit 8, minWin=22, winSum=368
7750 00:41:22.842388 TX Vref=20, minBit 8, minWin=22, winSum=374
7751 00:41:22.846130 TX Vref=22, minBit 8, minWin=23, winSum=389
7752 00:41:22.848966 TX Vref=24, minBit 1, minWin=24, winSum=395
7753 00:41:22.855573 TX Vref=26, minBit 4, minWin=24, winSum=401
7754 00:41:22.858996 TX Vref=28, minBit 8, minWin=23, winSum=405
7755 00:41:22.862310 TX Vref=30, minBit 8, minWin=23, winSum=400
7756 00:41:22.865716 TX Vref=32, minBit 8, minWin=23, winSum=388
7757 00:41:22.868902 TX Vref=34, minBit 0, minWin=23, winSum=379
7758 00:41:22.875585 [TxChooseVref] Worse bit 4, Min win 24, Win sum 401, Final Vref 26
7759 00:41:22.875678
7760 00:41:22.878874 Final TX Range 0 Vref 26
7761 00:41:22.878940
7762 00:41:22.878994 ==
7763 00:41:22.882070 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 00:41:22.885815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 00:41:22.885882 ==
7766 00:41:22.885945
7767 00:41:22.886000
7768 00:41:22.889138 TX Vref Scan disable
7769 00:41:22.895516 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7770 00:41:22.895591 == TX Byte 0 ==
7771 00:41:22.898848 u2DelayCellOfst[0]=15 cells (4 PI)
7772 00:41:22.902334 u2DelayCellOfst[1]=18 cells (5 PI)
7773 00:41:22.905522 u2DelayCellOfst[2]=11 cells (3 PI)
7774 00:41:22.908801 u2DelayCellOfst[3]=11 cells (3 PI)
7775 00:41:22.912160 u2DelayCellOfst[4]=7 cells (2 PI)
7776 00:41:22.915184 u2DelayCellOfst[5]=0 cells (0 PI)
7777 00:41:22.918638 u2DelayCellOfst[6]=22 cells (6 PI)
7778 00:41:22.922448 u2DelayCellOfst[7]=22 cells (6 PI)
7779 00:41:22.925334 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7780 00:41:22.928479 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7781 00:41:22.931874 == TX Byte 1 ==
7782 00:41:22.935376 u2DelayCellOfst[8]=0 cells (0 PI)
7783 00:41:22.935453 u2DelayCellOfst[9]=0 cells (0 PI)
7784 00:41:22.938668 u2DelayCellOfst[10]=7 cells (2 PI)
7785 00:41:22.942130 u2DelayCellOfst[11]=3 cells (1 PI)
7786 00:41:22.945029 u2DelayCellOfst[12]=11 cells (3 PI)
7787 00:41:22.948414 u2DelayCellOfst[13]=11 cells (3 PI)
7788 00:41:22.951855 u2DelayCellOfst[14]=15 cells (4 PI)
7789 00:41:22.955186 u2DelayCellOfst[15]=11 cells (3 PI)
7790 00:41:22.958832 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7791 00:41:22.965156 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7792 00:41:22.965233 DramC Write-DBI on
7793 00:41:22.965293 ==
7794 00:41:22.968683 Dram Type= 6, Freq= 0, CH_0, rank 0
7795 00:41:22.975234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7796 00:41:22.975311 ==
7797 00:41:22.975371
7798 00:41:22.975425
7799 00:41:22.975478 TX Vref Scan disable
7800 00:41:22.978974 == TX Byte 0 ==
7801 00:41:22.982433 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7802 00:41:22.985664 == TX Byte 1 ==
7803 00:41:22.988792 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7804 00:41:22.992001 DramC Write-DBI off
7805 00:41:22.992096
7806 00:41:22.992180 [DATLAT]
7807 00:41:22.992265 Freq=1600, CH0 RK0
7808 00:41:22.992346
7809 00:41:22.995319 DATLAT Default: 0xf
7810 00:41:22.995387 0, 0xFFFF, sum = 0
7811 00:41:22.998778 1, 0xFFFF, sum = 0
7812 00:41:23.002190 2, 0xFFFF, sum = 0
7813 00:41:23.002258 3, 0xFFFF, sum = 0
7814 00:41:23.005605 4, 0xFFFF, sum = 0
7815 00:41:23.005704 5, 0xFFFF, sum = 0
7816 00:41:23.008629 6, 0xFFFF, sum = 0
7817 00:41:23.008764 7, 0xFFFF, sum = 0
7818 00:41:23.012073 8, 0xFFFF, sum = 0
7819 00:41:23.012159 9, 0xFFFF, sum = 0
7820 00:41:23.015310 10, 0xFFFF, sum = 0
7821 00:41:23.015406 11, 0xFFFF, sum = 0
7822 00:41:23.018771 12, 0xFFFF, sum = 0
7823 00:41:23.018848 13, 0xEFFF, sum = 0
7824 00:41:23.022013 14, 0x0, sum = 1
7825 00:41:23.022080 15, 0x0, sum = 2
7826 00:41:23.025067 16, 0x0, sum = 3
7827 00:41:23.025147 17, 0x0, sum = 4
7828 00:41:23.028582 best_step = 15
7829 00:41:23.028703
7830 00:41:23.028787 ==
7831 00:41:23.032226 Dram Type= 6, Freq= 0, CH_0, rank 0
7832 00:41:23.035600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7833 00:41:23.035700 ==
7834 00:41:23.038750 RX Vref Scan: 1
7835 00:41:23.038828
7836 00:41:23.038912 Set Vref Range= 24 -> 127
7837 00:41:23.038992
7838 00:41:23.041734 RX Vref 24 -> 127, step: 1
7839 00:41:23.041800
7840 00:41:23.045595 RX Delay 11 -> 252, step: 4
7841 00:41:23.045663
7842 00:41:23.048604 Set Vref, RX VrefLevel [Byte0]: 24
7843 00:41:23.051983 [Byte1]: 24
7844 00:41:23.052072
7845 00:41:23.055293 Set Vref, RX VrefLevel [Byte0]: 25
7846 00:41:23.058823 [Byte1]: 25
7847 00:41:23.058917
7848 00:41:23.061711 Set Vref, RX VrefLevel [Byte0]: 26
7849 00:41:23.065208 [Byte1]: 26
7850 00:41:23.069233
7851 00:41:23.069301 Set Vref, RX VrefLevel [Byte0]: 27
7852 00:41:23.072738 [Byte1]: 27
7853 00:41:23.076732
7854 00:41:23.076823 Set Vref, RX VrefLevel [Byte0]: 28
7855 00:41:23.080023 [Byte1]: 28
7856 00:41:23.084510
7857 00:41:23.084602 Set Vref, RX VrefLevel [Byte0]: 29
7858 00:41:23.087496 [Byte1]: 29
7859 00:41:23.092307
7860 00:41:23.092397 Set Vref, RX VrefLevel [Byte0]: 30
7861 00:41:23.095627 [Byte1]: 30
7862 00:41:23.099820
7863 00:41:23.099897 Set Vref, RX VrefLevel [Byte0]: 31
7864 00:41:23.103135 [Byte1]: 31
7865 00:41:23.107159
7866 00:41:23.107235 Set Vref, RX VrefLevel [Byte0]: 32
7867 00:41:23.110646 [Byte1]: 32
7868 00:41:23.115169
7869 00:41:23.115269 Set Vref, RX VrefLevel [Byte0]: 33
7870 00:41:23.118449 [Byte1]: 33
7871 00:41:23.122546
7872 00:41:23.122622 Set Vref, RX VrefLevel [Byte0]: 34
7873 00:41:23.126225 [Byte1]: 34
7874 00:41:23.130077
7875 00:41:23.130153 Set Vref, RX VrefLevel [Byte0]: 35
7876 00:41:23.133415 [Byte1]: 35
7877 00:41:23.137621
7878 00:41:23.137697 Set Vref, RX VrefLevel [Byte0]: 36
7879 00:41:23.141007 [Byte1]: 36
7880 00:41:23.145302
7881 00:41:23.145378 Set Vref, RX VrefLevel [Byte0]: 37
7882 00:41:23.148422 [Byte1]: 37
7883 00:41:23.152748
7884 00:41:23.152825 Set Vref, RX VrefLevel [Byte0]: 38
7885 00:41:23.156799 [Byte1]: 38
7886 00:41:23.161107
7887 00:41:23.161214 Set Vref, RX VrefLevel [Byte0]: 39
7888 00:41:23.163816 [Byte1]: 39
7889 00:41:23.168251
7890 00:41:23.168327 Set Vref, RX VrefLevel [Byte0]: 40
7891 00:41:23.171682 [Byte1]: 40
7892 00:41:23.175718
7893 00:41:23.175795 Set Vref, RX VrefLevel [Byte0]: 41
7894 00:41:23.179137 [Byte1]: 41
7895 00:41:23.183753
7896 00:41:23.183829 Set Vref, RX VrefLevel [Byte0]: 42
7897 00:41:23.186721 [Byte1]: 42
7898 00:41:23.191023
7899 00:41:23.191100 Set Vref, RX VrefLevel [Byte0]: 43
7900 00:41:23.194124 [Byte1]: 43
7901 00:41:23.198551
7902 00:41:23.198627 Set Vref, RX VrefLevel [Byte0]: 44
7903 00:41:23.201892 [Byte1]: 44
7904 00:41:23.206301
7905 00:41:23.206377 Set Vref, RX VrefLevel [Byte0]: 45
7906 00:41:23.209420 [Byte1]: 45
7907 00:41:23.214008
7908 00:41:23.214084 Set Vref, RX VrefLevel [Byte0]: 46
7909 00:41:23.217479 [Byte1]: 46
7910 00:41:23.221543
7911 00:41:23.221619 Set Vref, RX VrefLevel [Byte0]: 47
7912 00:41:23.224889 [Byte1]: 47
7913 00:41:23.229368
7914 00:41:23.229444 Set Vref, RX VrefLevel [Byte0]: 48
7915 00:41:23.232464 [Byte1]: 48
7916 00:41:23.236831
7917 00:41:23.236907 Set Vref, RX VrefLevel [Byte0]: 49
7918 00:41:23.240356 [Byte1]: 49
7919 00:41:23.244367
7920 00:41:23.244442 Set Vref, RX VrefLevel [Byte0]: 50
7921 00:41:23.247627 [Byte1]: 50
7922 00:41:23.251761
7923 00:41:23.251837 Set Vref, RX VrefLevel [Byte0]: 51
7924 00:41:23.255459 [Byte1]: 51
7925 00:41:23.259567
7926 00:41:23.259644 Set Vref, RX VrefLevel [Byte0]: 52
7927 00:41:23.263158 [Byte1]: 52
7928 00:41:23.267204
7929 00:41:23.267280 Set Vref, RX VrefLevel [Byte0]: 53
7930 00:41:23.270563 [Byte1]: 53
7931 00:41:23.275161
7932 00:41:23.275242 Set Vref, RX VrefLevel [Byte0]: 54
7933 00:41:23.277992 [Byte1]: 54
7934 00:41:23.282449
7935 00:41:23.282525 Set Vref, RX VrefLevel [Byte0]: 55
7936 00:41:23.285913 [Byte1]: 55
7937 00:41:23.289909
7938 00:41:23.289986 Set Vref, RX VrefLevel [Byte0]: 56
7939 00:41:23.293525 [Byte1]: 56
7940 00:41:23.297732
7941 00:41:23.297808 Set Vref, RX VrefLevel [Byte0]: 57
7942 00:41:23.301045 [Byte1]: 57
7943 00:41:23.305325
7944 00:41:23.305401 Set Vref, RX VrefLevel [Byte0]: 58
7945 00:41:23.308402 [Byte1]: 58
7946 00:41:23.312877
7947 00:41:23.312953 Set Vref, RX VrefLevel [Byte0]: 59
7948 00:41:23.316150 [Byte1]: 59
7949 00:41:23.320403
7950 00:41:23.320500 Set Vref, RX VrefLevel [Byte0]: 60
7951 00:41:23.324057 [Byte1]: 60
7952 00:41:23.327991
7953 00:41:23.328067 Set Vref, RX VrefLevel [Byte0]: 61
7954 00:41:23.331406 [Byte1]: 61
7955 00:41:23.335946
7956 00:41:23.336022 Set Vref, RX VrefLevel [Byte0]: 62
7957 00:41:23.338780 [Byte1]: 62
7958 00:41:23.344100
7959 00:41:23.344193 Set Vref, RX VrefLevel [Byte0]: 63
7960 00:41:23.346447 [Byte1]: 63
7961 00:41:23.351277
7962 00:41:23.351369 Set Vref, RX VrefLevel [Byte0]: 64
7963 00:41:23.354483 [Byte1]: 64
7964 00:41:23.358869
7965 00:41:23.358939 Set Vref, RX VrefLevel [Byte0]: 65
7966 00:41:23.362061 [Byte1]: 65
7967 00:41:23.366257
7968 00:41:23.366329 Set Vref, RX VrefLevel [Byte0]: 66
7969 00:41:23.369353 [Byte1]: 66
7970 00:41:23.373488
7971 00:41:23.373556 Set Vref, RX VrefLevel [Byte0]: 67
7972 00:41:23.377205 [Byte1]: 67
7973 00:41:23.381075
7974 00:41:23.381143 Set Vref, RX VrefLevel [Byte0]: 68
7975 00:41:23.384547 [Byte1]: 68
7976 00:41:23.389134
7977 00:41:23.389206 Set Vref, RX VrefLevel [Byte0]: 69
7978 00:41:23.392470 [Byte1]: 69
7979 00:41:23.396499
7980 00:41:23.396566 Set Vref, RX VrefLevel [Byte0]: 70
7981 00:41:23.399825 [Byte1]: 70
7982 00:41:23.404375
7983 00:41:23.404449 Set Vref, RX VrefLevel [Byte0]: 71
7984 00:41:23.407330 [Byte1]: 71
7985 00:41:23.411736
7986 00:41:23.411805 Set Vref, RX VrefLevel [Byte0]: 72
7987 00:41:23.415410 [Byte1]: 72
7988 00:41:23.419273
7989 00:41:23.419365 Set Vref, RX VrefLevel [Byte0]: 73
7990 00:41:23.422569 [Byte1]: 73
7991 00:41:23.426830
7992 00:41:23.426907 Set Vref, RX VrefLevel [Byte0]: 74
7993 00:41:23.430269 [Byte1]: 74
7994 00:41:23.434877
7995 00:41:23.434954 Set Vref, RX VrefLevel [Byte0]: 75
7996 00:41:23.438266 [Byte1]: 75
7997 00:41:23.442186
7998 00:41:23.442261 Set Vref, RX VrefLevel [Byte0]: 76
7999 00:41:23.445628 [Byte1]: 76
8000 00:41:23.450184
8001 00:41:23.450260 Set Vref, RX VrefLevel [Byte0]: 77
8002 00:41:23.453027 [Byte1]: 77
8003 00:41:23.457697
8004 00:41:23.457773 Set Vref, RX VrefLevel [Byte0]: 78
8005 00:41:23.460689 [Byte1]: 78
8006 00:41:23.465641
8007 00:41:23.465718 Final RX Vref Byte 0 = 64 to rank0
8008 00:41:23.468261 Final RX Vref Byte 1 = 60 to rank0
8009 00:41:23.471549 Final RX Vref Byte 0 = 64 to rank1
8010 00:41:23.474701 Final RX Vref Byte 1 = 60 to rank1==
8011 00:41:23.478365 Dram Type= 6, Freq= 0, CH_0, rank 0
8012 00:41:23.485065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8013 00:41:23.485139 ==
8014 00:41:23.485213 DQS Delay:
8015 00:41:23.485288 DQS0 = 0, DQS1 = 0
8016 00:41:23.488361 DQM Delay:
8017 00:41:23.488430 DQM0 = 126, DQM1 = 119
8018 00:41:23.491819 DQ Delay:
8019 00:41:23.494791 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8020 00:41:23.497928 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8021 00:41:23.501395 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8022 00:41:23.504789 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8023 00:41:23.504863
8024 00:41:23.504935
8025 00:41:23.505004
8026 00:41:23.508105 [DramC_TX_OE_Calibration] TA2
8027 00:41:23.511564 Original DQ_B0 (3 6) =30, OEN = 27
8028 00:41:23.514638 Original DQ_B1 (3 6) =30, OEN = 27
8029 00:41:23.517997 24, 0x0, End_B0=24 End_B1=24
8030 00:41:23.518071 25, 0x0, End_B0=25 End_B1=25
8031 00:41:23.521644 26, 0x0, End_B0=26 End_B1=26
8032 00:41:23.524725 27, 0x0, End_B0=27 End_B1=27
8033 00:41:23.528135 28, 0x0, End_B0=28 End_B1=28
8034 00:41:23.531330 29, 0x0, End_B0=29 End_B1=29
8035 00:41:23.531401 30, 0x0, End_B0=30 End_B1=30
8036 00:41:23.534664 31, 0x4141, End_B0=30 End_B1=30
8037 00:41:23.538054 Byte0 end_step=30 best_step=27
8038 00:41:23.541410 Byte1 end_step=30 best_step=27
8039 00:41:23.544281 Byte0 TX OE(2T, 0.5T) = (3, 3)
8040 00:41:23.547737 Byte1 TX OE(2T, 0.5T) = (3, 3)
8041 00:41:23.547806
8042 00:41:23.547881
8043 00:41:23.554565 [DQSOSCAuto] RK0, (LSB)MR18= 0x1514, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8044 00:41:23.558035 CH0 RK0: MR19=303, MR18=1514
8045 00:41:23.564442 CH0_RK0: MR19=0x303, MR18=0x1514, DQSOSC=399, MR23=63, INC=23, DEC=15
8046 00:41:23.564512
8047 00:41:23.567761 ----->DramcWriteLeveling(PI) begin...
8048 00:41:23.567834 ==
8049 00:41:23.571108 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 00:41:23.574439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 00:41:23.574509 ==
8052 00:41:23.577789 Write leveling (Byte 0): 34 => 34
8053 00:41:23.580725 Write leveling (Byte 1): 30 => 30
8054 00:41:23.584080 DramcWriteLeveling(PI) end<-----
8055 00:41:23.584153
8056 00:41:23.584224 ==
8057 00:41:23.587616 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 00:41:23.590822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 00:41:23.590894 ==
8060 00:41:23.594231 [Gating] SW mode calibration
8061 00:41:23.600983 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8062 00:41:23.607333 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8063 00:41:23.610529 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 00:41:23.617396 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 00:41:23.620767 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 00:41:23.624330 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8067 00:41:23.630645 1 4 16 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
8068 00:41:23.633844 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 00:41:23.637284 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 00:41:23.644163 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 00:41:23.647714 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 00:41:23.650595 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 00:41:23.653927 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8074 00:41:23.660940 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
8075 00:41:23.663809 1 5 16 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8076 00:41:23.667341 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
8077 00:41:23.674178 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 00:41:23.677166 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 00:41:23.680740 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 00:41:23.687188 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 00:41:23.690455 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
8082 00:41:23.693757 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8083 00:41:23.700630 1 6 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8084 00:41:23.703706 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 00:41:23.706812 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 00:41:23.713790 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 00:41:23.716873 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 00:41:23.720138 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 00:41:23.727023 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8090 00:41:23.730174 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8091 00:41:23.733687 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8092 00:41:23.739960 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8093 00:41:23.743319 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 00:41:23.746669 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 00:41:23.753776 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 00:41:23.756597 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 00:41:23.760016 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 00:41:23.766735 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 00:41:23.770118 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 00:41:23.773699 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 00:41:23.779928 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 00:41:23.783305 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 00:41:23.786644 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 00:41:23.793067 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 00:41:23.796526 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8106 00:41:23.800013 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8107 00:41:23.806294 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8108 00:41:23.806363 Total UI for P1: 0, mck2ui 16
8109 00:41:23.813150 best dqsien dly found for B0: ( 1, 9, 10)
8110 00:41:23.816750 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8111 00:41:23.819959 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8112 00:41:23.822942 Total UI for P1: 0, mck2ui 16
8113 00:41:23.826087 best dqsien dly found for B1: ( 1, 9, 18)
8114 00:41:23.829800 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8115 00:41:23.832847 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8116 00:41:23.832915
8117 00:41:23.836264 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8118 00:41:23.843233 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8119 00:41:23.843307 [Gating] SW calibration Done
8120 00:41:23.846006 ==
8121 00:41:23.849434 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 00:41:23.852743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 00:41:23.852815 ==
8124 00:41:23.852888 RX Vref Scan: 0
8125 00:41:23.852961
8126 00:41:23.855795 RX Vref 0 -> 0, step: 1
8127 00:41:23.855866
8128 00:41:23.859289 RX Delay 0 -> 252, step: 8
8129 00:41:23.862478 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8130 00:41:23.865768 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8131 00:41:23.869009 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8132 00:41:23.876077 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8133 00:41:23.878894 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8134 00:41:23.882296 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8135 00:41:23.885783 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8136 00:41:23.889085 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8137 00:41:23.896008 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8138 00:41:23.898892 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8139 00:41:23.902345 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8140 00:41:23.905787 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8141 00:41:23.909349 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8142 00:41:23.915507 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8143 00:41:23.918752 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8144 00:41:23.922193 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8145 00:41:23.922263 ==
8146 00:41:23.925577 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 00:41:23.929057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 00:41:23.932042 ==
8149 00:41:23.932131 DQS Delay:
8150 00:41:23.932224 DQS0 = 0, DQS1 = 0
8151 00:41:23.935497 DQM Delay:
8152 00:41:23.935562 DQM0 = 127, DQM1 = 121
8153 00:41:23.938856 DQ Delay:
8154 00:41:23.942257 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8155 00:41:23.945508 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8156 00:41:23.948621 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8157 00:41:23.952397 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8158 00:41:23.952466
8159 00:41:23.952556
8160 00:41:23.952648 ==
8161 00:41:23.955422 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 00:41:23.958902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 00:41:23.958968 ==
8164 00:41:23.959042
8165 00:41:23.959108
8166 00:41:23.962160 TX Vref Scan disable
8167 00:41:23.965236 == TX Byte 0 ==
8168 00:41:23.968809 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8169 00:41:23.972333 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8170 00:41:23.975305 == TX Byte 1 ==
8171 00:41:23.978653 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8172 00:41:23.982055 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8173 00:41:23.982125 ==
8174 00:41:23.985236 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 00:41:23.991774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 00:41:23.991843 ==
8177 00:41:24.004830
8178 00:41:24.008203 TX Vref early break, caculate TX vref
8179 00:41:24.011658 TX Vref=16, minBit 0, minWin=22, winSum=374
8180 00:41:24.015090 TX Vref=18, minBit 8, minWin=22, winSum=381
8181 00:41:24.018410 TX Vref=20, minBit 0, minWin=23, winSum=388
8182 00:41:24.021759 TX Vref=22, minBit 0, minWin=23, winSum=396
8183 00:41:24.024602 TX Vref=24, minBit 2, minWin=24, winSum=407
8184 00:41:24.031411 TX Vref=26, minBit 0, minWin=25, winSum=412
8185 00:41:24.034939 TX Vref=28, minBit 0, minWin=25, winSum=419
8186 00:41:24.037786 TX Vref=30, minBit 2, minWin=25, winSum=414
8187 00:41:24.041290 TX Vref=32, minBit 3, minWin=25, winSum=407
8188 00:41:24.044793 TX Vref=34, minBit 8, minWin=23, winSum=398
8189 00:41:24.048180 TX Vref=36, minBit 3, minWin=23, winSum=386
8190 00:41:24.054785 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
8191 00:41:24.054863
8192 00:41:24.058101 Final TX Range 0 Vref 28
8193 00:41:24.058178
8194 00:41:24.058237 ==
8195 00:41:24.061356 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 00:41:24.064793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 00:41:24.064870 ==
8198 00:41:24.064929
8199 00:41:24.068123
8200 00:41:24.068229 TX Vref Scan disable
8201 00:41:24.074715 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8202 00:41:24.074807 == TX Byte 0 ==
8203 00:41:24.078040 u2DelayCellOfst[0]=15 cells (4 PI)
8204 00:41:24.080941 u2DelayCellOfst[1]=22 cells (6 PI)
8205 00:41:24.084313 u2DelayCellOfst[2]=15 cells (4 PI)
8206 00:41:24.087756 u2DelayCellOfst[3]=15 cells (4 PI)
8207 00:41:24.091156 u2DelayCellOfst[4]=11 cells (3 PI)
8208 00:41:24.094513 u2DelayCellOfst[5]=0 cells (0 PI)
8209 00:41:24.097569 u2DelayCellOfst[6]=22 cells (6 PI)
8210 00:41:24.101023 u2DelayCellOfst[7]=18 cells (5 PI)
8211 00:41:24.104305 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8212 00:41:24.107956 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8213 00:41:24.110733 == TX Byte 1 ==
8214 00:41:24.114295 u2DelayCellOfst[8]=0 cells (0 PI)
8215 00:41:24.118437 u2DelayCellOfst[9]=0 cells (0 PI)
8216 00:41:24.120833 u2DelayCellOfst[10]=3 cells (1 PI)
8217 00:41:24.120903 u2DelayCellOfst[11]=3 cells (1 PI)
8218 00:41:24.124641 u2DelayCellOfst[12]=11 cells (3 PI)
8219 00:41:24.127503 u2DelayCellOfst[13]=11 cells (3 PI)
8220 00:41:24.130943 u2DelayCellOfst[14]=15 cells (4 PI)
8221 00:41:24.134307 u2DelayCellOfst[15]=11 cells (3 PI)
8222 00:41:24.140630 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8223 00:41:24.144039 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8224 00:41:24.144106 DramC Write-DBI on
8225 00:41:24.144171 ==
8226 00:41:24.147556 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 00:41:24.154260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 00:41:24.154340 ==
8229 00:41:24.154396
8230 00:41:24.154449
8231 00:41:24.154501 TX Vref Scan disable
8232 00:41:24.158290 == TX Byte 0 ==
8233 00:41:24.161745 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8234 00:41:24.165188 == TX Byte 1 ==
8235 00:41:24.168009 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8236 00:41:24.171781 DramC Write-DBI off
8237 00:41:24.171868
8238 00:41:24.171949 [DATLAT]
8239 00:41:24.172028 Freq=1600, CH0 RK1
8240 00:41:24.172147
8241 00:41:24.175189 DATLAT Default: 0xf
8242 00:41:24.175275 0, 0xFFFF, sum = 0
8243 00:41:24.178085 1, 0xFFFF, sum = 0
8244 00:41:24.181528 2, 0xFFFF, sum = 0
8245 00:41:24.181597 3, 0xFFFF, sum = 0
8246 00:41:24.184727 4, 0xFFFF, sum = 0
8247 00:41:24.184804 5, 0xFFFF, sum = 0
8248 00:41:24.188229 6, 0xFFFF, sum = 0
8249 00:41:24.188318 7, 0xFFFF, sum = 0
8250 00:41:24.191650 8, 0xFFFF, sum = 0
8251 00:41:24.191715 9, 0xFFFF, sum = 0
8252 00:41:24.194574 10, 0xFFFF, sum = 0
8253 00:41:24.194668 11, 0xFFFF, sum = 0
8254 00:41:24.198094 12, 0xFFFF, sum = 0
8255 00:41:24.198166 13, 0xCFFF, sum = 0
8256 00:41:24.201523 14, 0x0, sum = 1
8257 00:41:24.201586 15, 0x0, sum = 2
8258 00:41:24.204400 16, 0x0, sum = 3
8259 00:41:24.204463 17, 0x0, sum = 4
8260 00:41:24.207936 best_step = 15
8261 00:41:24.208041
8262 00:41:24.208123 ==
8263 00:41:24.211376 Dram Type= 6, Freq= 0, CH_0, rank 1
8264 00:41:24.214561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 00:41:24.214649 ==
8266 00:41:24.218109 RX Vref Scan: 0
8267 00:41:24.218197
8268 00:41:24.218280 RX Vref 0 -> 0, step: 1
8269 00:41:24.218360
8270 00:41:24.221006 RX Delay 3 -> 252, step: 4
8271 00:41:24.224626 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8272 00:41:24.231269 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8273 00:41:24.235046 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8274 00:41:24.237664 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8275 00:41:24.240875 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8276 00:41:24.244257 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8277 00:41:24.250652 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8278 00:41:24.254164 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8279 00:41:24.257535 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8280 00:41:24.260885 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8281 00:41:24.264123 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8282 00:41:24.270877 iDelay=191, Bit 11, Center 108 (51 ~ 166) 116
8283 00:41:24.274314 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8284 00:41:24.277182 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8285 00:41:24.280581 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8286 00:41:24.287548 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8287 00:41:24.287618 ==
8288 00:41:24.290583 Dram Type= 6, Freq= 0, CH_0, rank 1
8289 00:41:24.294325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 00:41:24.294401 ==
8291 00:41:24.294474 DQS Delay:
8292 00:41:24.297171 DQS0 = 0, DQS1 = 0
8293 00:41:24.297236 DQM Delay:
8294 00:41:24.300605 DQM0 = 124, DQM1 = 117
8295 00:41:24.300707 DQ Delay:
8296 00:41:24.304290 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8297 00:41:24.307470 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8298 00:41:24.310966 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =108
8299 00:41:24.313837 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8300 00:41:24.313904
8301 00:41:24.313992
8302 00:41:24.317281
8303 00:41:24.317348 [DramC_TX_OE_Calibration] TA2
8304 00:41:24.320863 Original DQ_B0 (3 6) =30, OEN = 27
8305 00:41:24.323740 Original DQ_B1 (3 6) =30, OEN = 27
8306 00:41:24.327067 24, 0x0, End_B0=24 End_B1=24
8307 00:41:24.330366 25, 0x0, End_B0=25 End_B1=25
8308 00:41:24.334324 26, 0x0, End_B0=26 End_B1=26
8309 00:41:24.334393 27, 0x0, End_B0=27 End_B1=27
8310 00:41:24.337066 28, 0x0, End_B0=28 End_B1=28
8311 00:41:24.340795 29, 0x0, End_B0=29 End_B1=29
8312 00:41:24.344096 30, 0x0, End_B0=30 End_B1=30
8313 00:41:24.347457 31, 0x4545, End_B0=30 End_B1=30
8314 00:41:24.347529 Byte0 end_step=30 best_step=27
8315 00:41:24.350596 Byte1 end_step=30 best_step=27
8316 00:41:24.353658 Byte0 TX OE(2T, 0.5T) = (3, 3)
8317 00:41:24.357206 Byte1 TX OE(2T, 0.5T) = (3, 3)
8318 00:41:24.357283
8319 00:41:24.357344
8320 00:41:24.363956 [DQSOSCAuto] RK1, (LSB)MR18= 0x2412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8321 00:41:24.367235 CH0 RK1: MR19=303, MR18=2412
8322 00:41:24.373944 CH0_RK1: MR19=0x303, MR18=0x2412, DQSOSC=391, MR23=63, INC=24, DEC=16
8323 00:41:24.377309 [RxdqsGatingPostProcess] freq 1600
8324 00:41:24.383585 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8325 00:41:24.387129 best DQS0 dly(2T, 0.5T) = (1, 1)
8326 00:41:24.387206 best DQS1 dly(2T, 0.5T) = (1, 1)
8327 00:41:24.389943 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8328 00:41:24.393205 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8329 00:41:24.396635 best DQS0 dly(2T, 0.5T) = (1, 1)
8330 00:41:24.399972 best DQS1 dly(2T, 0.5T) = (1, 1)
8331 00:41:24.403220 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8332 00:41:24.406401 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8333 00:41:24.409908 Pre-setting of DQS Precalculation
8334 00:41:24.416875 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8335 00:41:24.416954 ==
8336 00:41:24.420187 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 00:41:24.423119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 00:41:24.423196 ==
8339 00:41:24.429854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8340 00:41:24.433203 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8341 00:41:24.436351 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8342 00:41:24.443117 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8343 00:41:24.451625 [CA 0] Center 41 (12~71) winsize 60
8344 00:41:24.454615 [CA 1] Center 42 (12~72) winsize 61
8345 00:41:24.457806 [CA 2] Center 38 (9~67) winsize 59
8346 00:41:24.461577 [CA 3] Center 37 (8~66) winsize 59
8347 00:41:24.464555 [CA 4] Center 38 (9~67) winsize 59
8348 00:41:24.467990 [CA 5] Center 36 (7~66) winsize 60
8349 00:41:24.468060
8350 00:41:24.471534 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8351 00:41:24.471602
8352 00:41:24.475181 [CATrainingPosCal] consider 1 rank data
8353 00:41:24.478453 u2DelayCellTimex100 = 258/100 ps
8354 00:41:24.481446 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8355 00:41:24.488080 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8356 00:41:24.491046 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8357 00:41:24.494465 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8358 00:41:24.497909 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8359 00:41:24.501222 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8360 00:41:24.501317
8361 00:41:24.504247 CA PerBit enable=1, Macro0, CA PI delay=36
8362 00:41:24.504350
8363 00:41:24.507647 [CBTSetCACLKResult] CA Dly = 36
8364 00:41:24.510792 CS Dly: 9 (0~40)
8365 00:41:24.514544 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8366 00:41:24.517623 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8367 00:41:24.517695 ==
8368 00:41:24.521087 Dram Type= 6, Freq= 0, CH_1, rank 1
8369 00:41:24.524407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 00:41:24.527895 ==
8371 00:41:24.530687 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8372 00:41:24.534482 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8373 00:41:24.540739 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8374 00:41:24.544142 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8375 00:41:24.554276 [CA 0] Center 42 (13~72) winsize 60
8376 00:41:24.558113 [CA 1] Center 42 (12~72) winsize 61
8377 00:41:24.561256 [CA 2] Center 38 (9~67) winsize 59
8378 00:41:24.564608 [CA 3] Center 36 (7~66) winsize 60
8379 00:41:24.567761 [CA 4] Center 38 (8~68) winsize 61
8380 00:41:24.571216 [CA 5] Center 36 (6~67) winsize 62
8381 00:41:24.571283
8382 00:41:24.574220 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8383 00:41:24.574294
8384 00:41:24.577653 [CATrainingPosCal] consider 2 rank data
8385 00:41:24.580931 u2DelayCellTimex100 = 258/100 ps
8386 00:41:24.584795 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8387 00:41:24.591218 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8388 00:41:24.594709 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8389 00:41:24.597881 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8390 00:41:24.601340 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8391 00:41:24.604206 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8392 00:41:24.604283
8393 00:41:24.607561 CA PerBit enable=1, Macro0, CA PI delay=36
8394 00:41:24.607637
8395 00:41:24.610940 [CBTSetCACLKResult] CA Dly = 36
8396 00:41:24.614354 CS Dly: 10 (0~43)
8397 00:41:24.617801 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8398 00:41:24.620841 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8399 00:41:24.620949
8400 00:41:24.624364 ----->DramcWriteLeveling(PI) begin...
8401 00:41:24.624464 ==
8402 00:41:24.627651 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 00:41:24.630766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 00:41:24.634096 ==
8405 00:41:24.634172 Write leveling (Byte 0): 25 => 25
8406 00:41:24.637499 Write leveling (Byte 1): 28 => 28
8407 00:41:24.640787 DramcWriteLeveling(PI) end<-----
8408 00:41:24.640862
8409 00:41:24.640922 ==
8410 00:41:24.644042 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 00:41:24.650729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 00:41:24.650806 ==
8413 00:41:24.654040 [Gating] SW mode calibration
8414 00:41:24.661085 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8415 00:41:24.663899 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8416 00:41:24.670404 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 00:41:24.673741 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 00:41:24.677308 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 00:41:24.683904 1 4 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8420 00:41:24.687264 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8421 00:41:24.690124 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 00:41:24.697091 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 00:41:24.700531 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 00:41:24.703667 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 00:41:24.710462 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 00:41:24.713422 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 00:41:24.716908 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8428 00:41:24.723350 1 5 16 | B1->B0 | 2828 2b2b | 0 0 | (1 0) (1 0)
8429 00:41:24.726704 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8430 00:41:24.730104 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 00:41:24.736792 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 00:41:24.740029 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 00:41:24.743100 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 00:41:24.749693 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 00:41:24.753138 1 6 12 | B1->B0 | 2b2b 2a2a | 0 0 | (0 0) (0 0)
8436 00:41:24.756455 1 6 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8437 00:41:24.763071 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 00:41:24.766377 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 00:41:24.769550 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 00:41:24.776598 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 00:41:24.779414 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 00:41:24.782940 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 00:41:24.785951 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 00:41:24.792900 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8445 00:41:24.796243 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8446 00:41:24.799735 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 00:41:24.806044 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 00:41:24.809546 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 00:41:24.812724 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 00:41:24.819233 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 00:41:24.822749 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 00:41:24.826387 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 00:41:24.832453 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 00:41:24.835973 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 00:41:24.839272 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 00:41:24.845695 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 00:41:24.848856 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 00:41:24.852395 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 00:41:24.858821 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8460 00:41:24.862520 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8461 00:41:24.865341 Total UI for P1: 0, mck2ui 16
8462 00:41:24.868856 best dqsien dly found for B1: ( 1, 9, 14)
8463 00:41:24.872319 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8464 00:41:24.875789 Total UI for P1: 0, mck2ui 16
8465 00:41:24.878766 best dqsien dly found for B0: ( 1, 9, 14)
8466 00:41:24.882228 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8467 00:41:24.885806 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8468 00:41:24.885874
8469 00:41:24.891956 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8470 00:41:24.895563 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8471 00:41:24.898554 [Gating] SW calibration Done
8472 00:41:24.898623 ==
8473 00:41:24.901871 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 00:41:24.905338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 00:41:24.905415 ==
8476 00:41:24.905475 RX Vref Scan: 0
8477 00:41:24.908824
8478 00:41:24.908901 RX Vref 0 -> 0, step: 1
8479 00:41:24.908962
8480 00:41:24.911789 RX Delay 0 -> 252, step: 8
8481 00:41:24.915249 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8482 00:41:24.918549 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8483 00:41:24.925247 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8484 00:41:24.928731 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8485 00:41:24.931953 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8486 00:41:24.935226 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8487 00:41:24.938749 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8488 00:41:24.945118 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8489 00:41:24.948424 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8490 00:41:24.951622 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8491 00:41:24.954986 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8492 00:41:24.958247 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8493 00:41:24.964905 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8494 00:41:24.968342 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8495 00:41:24.971614 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8496 00:41:24.974818 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8497 00:41:24.974896 ==
8498 00:41:24.978276 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 00:41:24.985213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 00:41:24.985291 ==
8501 00:41:24.985351 DQS Delay:
8502 00:41:24.988076 DQS0 = 0, DQS1 = 0
8503 00:41:24.988153 DQM Delay:
8504 00:41:24.988212 DQM0 = 132, DQM1 = 126
8505 00:41:24.991293 DQ Delay:
8506 00:41:24.994646 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8507 00:41:24.998090 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8508 00:41:25.001791 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8509 00:41:25.005016 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8510 00:41:25.005094
8511 00:41:25.005154
8512 00:41:25.005210 ==
8513 00:41:25.008056 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 00:41:25.014762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 00:41:25.014840 ==
8516 00:41:25.014900
8517 00:41:25.014955
8518 00:41:25.015008 TX Vref Scan disable
8519 00:41:25.018224 == TX Byte 0 ==
8520 00:41:25.021498 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8521 00:41:25.024897 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8522 00:41:25.027736 == TX Byte 1 ==
8523 00:41:25.031525 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8524 00:41:25.034339 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8525 00:41:25.037898 ==
8526 00:41:25.041419 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 00:41:25.044339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 00:41:25.044416 ==
8529 00:41:25.057474
8530 00:41:25.061248 TX Vref early break, caculate TX vref
8531 00:41:25.064148 TX Vref=16, minBit 9, minWin=21, winSum=365
8532 00:41:25.067681 TX Vref=18, minBit 11, minWin=21, winSum=374
8533 00:41:25.071138 TX Vref=20, minBit 11, minWin=21, winSum=385
8534 00:41:25.074389 TX Vref=22, minBit 5, minWin=24, winSum=401
8535 00:41:25.080966 TX Vref=24, minBit 10, minWin=24, winSum=407
8536 00:41:25.084183 TX Vref=26, minBit 5, minWin=25, winSum=416
8537 00:41:25.087384 TX Vref=28, minBit 5, minWin=25, winSum=419
8538 00:41:25.091007 TX Vref=30, minBit 0, minWin=25, winSum=416
8539 00:41:25.094148 TX Vref=32, minBit 0, minWin=25, winSum=411
8540 00:41:25.097518 TX Vref=34, minBit 6, minWin=23, winSum=398
8541 00:41:25.103916 TX Vref=36, minBit 1, minWin=23, winSum=386
8542 00:41:25.107286 [TxChooseVref] Worse bit 5, Min win 25, Win sum 419, Final Vref 28
8543 00:41:25.107363
8544 00:41:25.110530 Final TX Range 0 Vref 28
8545 00:41:25.110608
8546 00:41:25.110667 ==
8547 00:41:25.114235 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 00:41:25.117141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 00:41:25.117220 ==
8550 00:41:25.120560
8551 00:41:25.120637
8552 00:41:25.120741 TX Vref Scan disable
8553 00:41:25.127210 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8554 00:41:25.127287 == TX Byte 0 ==
8555 00:41:25.130762 u2DelayCellOfst[0]=18 cells (5 PI)
8556 00:41:25.134125 u2DelayCellOfst[1]=11 cells (3 PI)
8557 00:41:25.137383 u2DelayCellOfst[2]=0 cells (0 PI)
8558 00:41:25.140808 u2DelayCellOfst[3]=7 cells (2 PI)
8559 00:41:25.143637 u2DelayCellOfst[4]=7 cells (2 PI)
8560 00:41:25.147118 u2DelayCellOfst[5]=22 cells (6 PI)
8561 00:41:25.150584 u2DelayCellOfst[6]=22 cells (6 PI)
8562 00:41:25.153870 u2DelayCellOfst[7]=3 cells (1 PI)
8563 00:41:25.157403 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8564 00:41:25.160638 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8565 00:41:25.163657 == TX Byte 1 ==
8566 00:41:25.167107 u2DelayCellOfst[8]=0 cells (0 PI)
8567 00:41:25.170555 u2DelayCellOfst[9]=7 cells (2 PI)
8568 00:41:25.173948 u2DelayCellOfst[10]=15 cells (4 PI)
8569 00:41:25.174024 u2DelayCellOfst[11]=7 cells (2 PI)
8570 00:41:25.176881 u2DelayCellOfst[12]=15 cells (4 PI)
8571 00:41:25.180375 u2DelayCellOfst[13]=22 cells (6 PI)
8572 00:41:25.183656 u2DelayCellOfst[14]=22 cells (6 PI)
8573 00:41:25.187308 u2DelayCellOfst[15]=22 cells (6 PI)
8574 00:41:25.193586 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8575 00:41:25.197228 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8576 00:41:25.197305 DramC Write-DBI on
8577 00:41:25.197365 ==
8578 00:41:25.200607 Dram Type= 6, Freq= 0, CH_1, rank 0
8579 00:41:25.207172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8580 00:41:25.207249 ==
8581 00:41:25.207309
8582 00:41:25.207363
8583 00:41:25.207415 TX Vref Scan disable
8584 00:41:25.211099 == TX Byte 0 ==
8585 00:41:25.214647 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8586 00:41:25.218059 == TX Byte 1 ==
8587 00:41:25.220952 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8588 00:41:25.224227 DramC Write-DBI off
8589 00:41:25.224318
8590 00:41:25.224377 [DATLAT]
8591 00:41:25.224433 Freq=1600, CH1 RK0
8592 00:41:25.224486
8593 00:41:25.227717 DATLAT Default: 0xf
8594 00:41:25.227793 0, 0xFFFF, sum = 0
8595 00:41:25.231077 1, 0xFFFF, sum = 0
8596 00:41:25.234317 2, 0xFFFF, sum = 0
8597 00:41:25.234395 3, 0xFFFF, sum = 0
8598 00:41:25.237623 4, 0xFFFF, sum = 0
8599 00:41:25.237701 5, 0xFFFF, sum = 0
8600 00:41:25.240802 6, 0xFFFF, sum = 0
8601 00:41:25.240880 7, 0xFFFF, sum = 0
8602 00:41:25.244289 8, 0xFFFF, sum = 0
8603 00:41:25.244366 9, 0xFFFF, sum = 0
8604 00:41:25.247676 10, 0xFFFF, sum = 0
8605 00:41:25.247754 11, 0xFFFF, sum = 0
8606 00:41:25.251116 12, 0xFFFF, sum = 0
8607 00:41:25.251194 13, 0x8FFF, sum = 0
8608 00:41:25.254853 14, 0x0, sum = 1
8609 00:41:25.254931 15, 0x0, sum = 2
8610 00:41:25.257422 16, 0x0, sum = 3
8611 00:41:25.257499 17, 0x0, sum = 4
8612 00:41:25.260734 best_step = 15
8613 00:41:25.260809
8614 00:41:25.260868 ==
8615 00:41:25.264156 Dram Type= 6, Freq= 0, CH_1, rank 0
8616 00:41:25.267351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8617 00:41:25.267428 ==
8618 00:41:25.270846 RX Vref Scan: 1
8619 00:41:25.270922
8620 00:41:25.270981 Set Vref Range= 24 -> 127
8621 00:41:25.271036
8622 00:41:25.273845 RX Vref 24 -> 127, step: 1
8623 00:41:25.273966
8624 00:41:25.277280 RX Delay 11 -> 252, step: 4
8625 00:41:25.277370
8626 00:41:25.280469 Set Vref, RX VrefLevel [Byte0]: 24
8627 00:41:25.283855 [Byte1]: 24
8628 00:41:25.283930
8629 00:41:25.287254 Set Vref, RX VrefLevel [Byte0]: 25
8630 00:41:25.290766 [Byte1]: 25
8631 00:41:25.293634
8632 00:41:25.293709 Set Vref, RX VrefLevel [Byte0]: 26
8633 00:41:25.297056 [Byte1]: 26
8634 00:41:25.301443
8635 00:41:25.301519 Set Vref, RX VrefLevel [Byte0]: 27
8636 00:41:25.304805 [Byte1]: 27
8637 00:41:25.309247
8638 00:41:25.309322 Set Vref, RX VrefLevel [Byte0]: 28
8639 00:41:25.312234 [Byte1]: 28
8640 00:41:25.316571
8641 00:41:25.316657 Set Vref, RX VrefLevel [Byte0]: 29
8642 00:41:25.319930 [Byte1]: 29
8643 00:41:25.324568
8644 00:41:25.324654 Set Vref, RX VrefLevel [Byte0]: 30
8645 00:41:25.327531 [Byte1]: 30
8646 00:41:25.332032
8647 00:41:25.332126 Set Vref, RX VrefLevel [Byte0]: 31
8648 00:41:25.335464 [Byte1]: 31
8649 00:41:25.339624
8650 00:41:25.339703 Set Vref, RX VrefLevel [Byte0]: 32
8651 00:41:25.342535 [Byte1]: 32
8652 00:41:25.347190
8653 00:41:25.347267 Set Vref, RX VrefLevel [Byte0]: 33
8654 00:41:25.350607 [Byte1]: 33
8655 00:41:25.354877
8656 00:41:25.354953 Set Vref, RX VrefLevel [Byte0]: 34
8657 00:41:25.358310 [Byte1]: 34
8658 00:41:25.362320
8659 00:41:25.362396 Set Vref, RX VrefLevel [Byte0]: 35
8660 00:41:25.365750 [Byte1]: 35
8661 00:41:25.370314
8662 00:41:25.370391 Set Vref, RX VrefLevel [Byte0]: 36
8663 00:41:25.373580 [Byte1]: 36
8664 00:41:25.377374
8665 00:41:25.377450 Set Vref, RX VrefLevel [Byte0]: 37
8666 00:41:25.380828 [Byte1]: 37
8667 00:41:25.385166
8668 00:41:25.385243 Set Vref, RX VrefLevel [Byte0]: 38
8669 00:41:25.388355 [Byte1]: 38
8670 00:41:25.392631
8671 00:41:25.392715 Set Vref, RX VrefLevel [Byte0]: 39
8672 00:41:25.396341 [Byte1]: 39
8673 00:41:25.400370
8674 00:41:25.400446 Set Vref, RX VrefLevel [Byte0]: 40
8675 00:41:25.403762 [Byte1]: 40
8676 00:41:25.407781
8677 00:41:25.407857 Set Vref, RX VrefLevel [Byte0]: 41
8678 00:41:25.411220 [Byte1]: 41
8679 00:41:25.415905
8680 00:41:25.415981 Set Vref, RX VrefLevel [Byte0]: 42
8681 00:41:25.418713 [Byte1]: 42
8682 00:41:25.423112
8683 00:41:25.423195 Set Vref, RX VrefLevel [Byte0]: 43
8684 00:41:25.426809 [Byte1]: 43
8685 00:41:25.431077
8686 00:41:25.431154 Set Vref, RX VrefLevel [Byte0]: 44
8687 00:41:25.433998 [Byte1]: 44
8688 00:41:25.438347
8689 00:41:25.438424 Set Vref, RX VrefLevel [Byte0]: 45
8690 00:41:25.441779 [Byte1]: 45
8691 00:41:25.446256
8692 00:41:25.446333 Set Vref, RX VrefLevel [Byte0]: 46
8693 00:41:25.449093 [Byte1]: 46
8694 00:41:25.453580
8695 00:41:25.453656 Set Vref, RX VrefLevel [Byte0]: 47
8696 00:41:25.457151 [Byte1]: 47
8697 00:41:25.461021
8698 00:41:25.461097 Set Vref, RX VrefLevel [Byte0]: 48
8699 00:41:25.464711 [Byte1]: 48
8700 00:41:25.468979
8701 00:41:25.469055 Set Vref, RX VrefLevel [Byte0]: 49
8702 00:41:25.472228 [Byte1]: 49
8703 00:41:25.476258
8704 00:41:25.476334 Set Vref, RX VrefLevel [Byte0]: 50
8705 00:41:25.480047 [Byte1]: 50
8706 00:41:25.483922
8707 00:41:25.483999 Set Vref, RX VrefLevel [Byte0]: 51
8708 00:41:25.487346 [Byte1]: 51
8709 00:41:25.491910
8710 00:41:25.491986 Set Vref, RX VrefLevel [Byte0]: 52
8711 00:41:25.495276 [Byte1]: 52
8712 00:41:25.499551
8713 00:41:25.499631 Set Vref, RX VrefLevel [Byte0]: 53
8714 00:41:25.502629 [Byte1]: 53
8715 00:41:25.507129
8716 00:41:25.507205 Set Vref, RX VrefLevel [Byte0]: 54
8717 00:41:25.510188 [Byte1]: 54
8718 00:41:25.514770
8719 00:41:25.514849 Set Vref, RX VrefLevel [Byte0]: 55
8720 00:41:25.517626 [Byte1]: 55
8721 00:41:25.522264
8722 00:41:25.522343 Set Vref, RX VrefLevel [Byte0]: 56
8723 00:41:25.525687 [Byte1]: 56
8724 00:41:25.529696
8725 00:41:25.529773 Set Vref, RX VrefLevel [Byte0]: 57
8726 00:41:25.533116 [Byte1]: 57
8727 00:41:25.537611
8728 00:41:25.537688 Set Vref, RX VrefLevel [Byte0]: 58
8729 00:41:25.540910 [Byte1]: 58
8730 00:41:25.544968
8731 00:41:25.545046 Set Vref, RX VrefLevel [Byte0]: 59
8732 00:41:25.548249 [Byte1]: 59
8733 00:41:25.552910
8734 00:41:25.552982 Set Vref, RX VrefLevel [Byte0]: 60
8735 00:41:25.555827 [Byte1]: 60
8736 00:41:25.560402
8737 00:41:25.560479 Set Vref, RX VrefLevel [Byte0]: 61
8738 00:41:25.563838 [Byte1]: 61
8739 00:41:25.568096
8740 00:41:25.568174 Set Vref, RX VrefLevel [Byte0]: 62
8741 00:41:25.571189 [Byte1]: 62
8742 00:41:25.575577
8743 00:41:25.575654 Set Vref, RX VrefLevel [Byte0]: 63
8744 00:41:25.578522 [Byte1]: 63
8745 00:41:25.582874
8746 00:41:25.582951 Set Vref, RX VrefLevel [Byte0]: 64
8747 00:41:25.586260 [Byte1]: 64
8748 00:41:25.590539
8749 00:41:25.590617 Set Vref, RX VrefLevel [Byte0]: 65
8750 00:41:25.593949 [Byte1]: 65
8751 00:41:25.598525
8752 00:41:25.598602 Set Vref, RX VrefLevel [Byte0]: 66
8753 00:41:25.601346 [Byte1]: 66
8754 00:41:25.605719
8755 00:41:25.605797 Set Vref, RX VrefLevel [Byte0]: 67
8756 00:41:25.609316 [Byte1]: 67
8757 00:41:25.613549
8758 00:41:25.613626 Set Vref, RX VrefLevel [Byte0]: 68
8759 00:41:25.616667 [Byte1]: 68
8760 00:41:25.621508
8761 00:41:25.621590 Set Vref, RX VrefLevel [Byte0]: 69
8762 00:41:25.624340 [Byte1]: 69
8763 00:41:25.628945
8764 00:41:25.629021 Set Vref, RX VrefLevel [Byte0]: 70
8765 00:41:25.631901 [Byte1]: 70
8766 00:41:25.636382
8767 00:41:25.636459 Set Vref, RX VrefLevel [Byte0]: 71
8768 00:41:25.639675 [Byte1]: 71
8769 00:41:25.644340
8770 00:41:25.644440 Set Vref, RX VrefLevel [Byte0]: 72
8771 00:41:25.647155 [Byte1]: 72
8772 00:41:25.651908
8773 00:41:25.651986 Final RX Vref Byte 0 = 60 to rank0
8774 00:41:25.655004 Final RX Vref Byte 1 = 53 to rank0
8775 00:41:25.658467 Final RX Vref Byte 0 = 60 to rank1
8776 00:41:25.661439 Final RX Vref Byte 1 = 53 to rank1==
8777 00:41:25.664918 Dram Type= 6, Freq= 0, CH_1, rank 0
8778 00:41:25.671348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 00:41:25.671427 ==
8780 00:41:25.671488 DQS Delay:
8781 00:41:25.671544 DQS0 = 0, DQS1 = 0
8782 00:41:25.674817 DQM Delay:
8783 00:41:25.674893 DQM0 = 131, DQM1 = 123
8784 00:41:25.678231 DQ Delay:
8785 00:41:25.681327 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =126
8786 00:41:25.684780 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8787 00:41:25.688105 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8788 00:41:25.691825 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8789 00:41:25.691902
8790 00:41:25.691961
8791 00:41:25.692016
8792 00:41:25.694794 [DramC_TX_OE_Calibration] TA2
8793 00:41:25.698101 Original DQ_B0 (3 6) =30, OEN = 27
8794 00:41:25.701162 Original DQ_B1 (3 6) =30, OEN = 27
8795 00:41:25.704527 24, 0x0, End_B0=24 End_B1=24
8796 00:41:25.704630 25, 0x0, End_B0=25 End_B1=25
8797 00:41:25.708094 26, 0x0, End_B0=26 End_B1=26
8798 00:41:25.711563 27, 0x0, End_B0=27 End_B1=27
8799 00:41:25.714706 28, 0x0, End_B0=28 End_B1=28
8800 00:41:25.717809 29, 0x0, End_B0=29 End_B1=29
8801 00:41:25.717888 30, 0x0, End_B0=30 End_B1=30
8802 00:41:25.721381 31, 0x4141, End_B0=30 End_B1=30
8803 00:41:25.724587 Byte0 end_step=30 best_step=27
8804 00:41:25.728387 Byte1 end_step=30 best_step=27
8805 00:41:25.731267 Byte0 TX OE(2T, 0.5T) = (3, 3)
8806 00:41:25.734776 Byte1 TX OE(2T, 0.5T) = (3, 3)
8807 00:41:25.734854
8808 00:41:25.734913
8809 00:41:25.741533 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8810 00:41:25.744316 CH1 RK0: MR19=303, MR18=A0E
8811 00:41:25.751389 CH1_RK0: MR19=0x303, MR18=0xA0E, DQSOSC=402, MR23=63, INC=22, DEC=15
8812 00:41:25.751467
8813 00:41:25.754204 ----->DramcWriteLeveling(PI) begin...
8814 00:41:25.754282 ==
8815 00:41:25.757701 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 00:41:25.761119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 00:41:25.761197 ==
8818 00:41:25.764268 Write leveling (Byte 0): 23 => 23
8819 00:41:25.767778 Write leveling (Byte 1): 28 => 28
8820 00:41:25.771132 DramcWriteLeveling(PI) end<-----
8821 00:41:25.771250
8822 00:41:25.771311 ==
8823 00:41:25.774454 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 00:41:25.778010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 00:41:25.778088 ==
8826 00:41:25.780825 [Gating] SW mode calibration
8827 00:41:25.787834 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8828 00:41:25.794582 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8829 00:41:25.798065 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 00:41:25.800761 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 00:41:25.807437 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8832 00:41:25.811033 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8833 00:41:25.814395 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 00:41:25.820636 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 00:41:25.824222 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 00:41:25.827832 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 00:41:25.834518 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 00:41:25.837990 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 00:41:25.840756 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8840 00:41:25.847685 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8841 00:41:25.850624 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 00:41:25.854064 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 00:41:25.860833 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 00:41:25.864294 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 00:41:25.867165 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 00:41:25.873741 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8847 00:41:25.877376 1 6 8 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8848 00:41:25.880552 1 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8849 00:41:25.887178 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 00:41:25.890755 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 00:41:25.893859 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 00:41:25.900377 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 00:41:25.903817 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 00:41:25.907243 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 00:41:25.913911 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8856 00:41:25.917021 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8857 00:41:25.920155 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 00:41:25.927123 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 00:41:25.930480 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 00:41:25.933839 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 00:41:25.940074 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 00:41:25.943275 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 00:41:25.946725 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 00:41:25.950147 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 00:41:25.956957 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 00:41:25.959787 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 00:41:25.963241 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 00:41:25.970100 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 00:41:25.973556 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 00:41:25.976921 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 00:41:25.983069 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8872 00:41:25.986483 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8873 00:41:25.989662 Total UI for P1: 0, mck2ui 16
8874 00:41:25.993627 best dqsien dly found for B0: ( 1, 9, 8)
8875 00:41:25.996427 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 00:41:26.000117 Total UI for P1: 0, mck2ui 16
8877 00:41:26.003092 best dqsien dly found for B1: ( 1, 9, 10)
8878 00:41:26.006543 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8879 00:41:26.010199 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8880 00:41:26.010269
8881 00:41:26.016315 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8882 00:41:26.019650 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8883 00:41:26.023017 [Gating] SW calibration Done
8884 00:41:26.023088 ==
8885 00:41:26.026578 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 00:41:26.029683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 00:41:26.029762 ==
8888 00:41:26.029822 RX Vref Scan: 0
8889 00:41:26.029879
8890 00:41:26.033178 RX Vref 0 -> 0, step: 1
8891 00:41:26.033255
8892 00:41:26.036496 RX Delay 0 -> 252, step: 8
8893 00:41:26.039642 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8894 00:41:26.042924 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8895 00:41:26.046676 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8896 00:41:26.052679 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8897 00:41:26.056608 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8898 00:41:26.059467 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8899 00:41:26.062932 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8900 00:41:26.069197 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8901 00:41:26.072542 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8902 00:41:26.076019 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8903 00:41:26.079517 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8904 00:41:26.082764 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8905 00:41:26.089011 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8906 00:41:26.092366 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8907 00:41:26.096122 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8908 00:41:26.099348 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8909 00:41:26.099445 ==
8910 00:41:26.102790 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 00:41:26.109586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 00:41:26.109683 ==
8913 00:41:26.109768 DQS Delay:
8914 00:41:26.109858 DQS0 = 0, DQS1 = 0
8915 00:41:26.112287 DQM Delay:
8916 00:41:26.112376 DQM0 = 133, DQM1 = 127
8917 00:41:26.115780 DQ Delay:
8918 00:41:26.119095 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =131
8919 00:41:26.122244 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8920 00:41:26.125637 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8921 00:41:26.128964 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8922 00:41:26.129037
8923 00:41:26.129095
8924 00:41:26.129150 ==
8925 00:41:26.132301 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 00:41:26.135868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 00:41:26.139178 ==
8928 00:41:26.139254
8929 00:41:26.139314
8930 00:41:26.139369 TX Vref Scan disable
8931 00:41:26.142540 == TX Byte 0 ==
8932 00:41:26.145834 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8933 00:41:26.148599 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8934 00:41:26.152296 == TX Byte 1 ==
8935 00:41:26.155359 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8936 00:41:26.158734 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8937 00:41:26.162121 ==
8938 00:41:26.162214 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 00:41:26.168993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 00:41:26.169074 ==
8941 00:41:26.182285
8942 00:41:26.185594 TX Vref early break, caculate TX vref
8943 00:41:26.188868 TX Vref=16, minBit 0, minWin=22, winSum=375
8944 00:41:26.192233 TX Vref=18, minBit 0, minWin=23, winSum=387
8945 00:41:26.195656 TX Vref=20, minBit 0, minWin=23, winSum=395
8946 00:41:26.199000 TX Vref=22, minBit 0, minWin=23, winSum=407
8947 00:41:26.202204 TX Vref=24, minBit 0, minWin=24, winSum=412
8948 00:41:26.208964 TX Vref=26, minBit 5, minWin=24, winSum=415
8949 00:41:26.212181 TX Vref=28, minBit 5, minWin=24, winSum=418
8950 00:41:26.215332 TX Vref=30, minBit 5, minWin=24, winSum=415
8951 00:41:26.218662 TX Vref=32, minBit 5, minWin=24, winSum=409
8952 00:41:26.222282 TX Vref=34, minBit 5, minWin=23, winSum=402
8953 00:41:26.225091 TX Vref=36, minBit 5, minWin=22, winSum=390
8954 00:41:26.232043 [TxChooseVref] Worse bit 5, Min win 24, Win sum 418, Final Vref 28
8955 00:41:26.232130
8956 00:41:26.234930 Final TX Range 0 Vref 28
8957 00:41:26.234998
8958 00:41:26.235059 ==
8959 00:41:26.238659 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 00:41:26.242054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 00:41:26.242149 ==
8962 00:41:26.242232
8963 00:41:26.245100
8964 00:41:26.245165 TX Vref Scan disable
8965 00:41:26.251989 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8966 00:41:26.252066 == TX Byte 0 ==
8967 00:41:26.255122 u2DelayCellOfst[0]=18 cells (5 PI)
8968 00:41:26.258274 u2DelayCellOfst[1]=11 cells (3 PI)
8969 00:41:26.261587 u2DelayCellOfst[2]=0 cells (0 PI)
8970 00:41:26.265167 u2DelayCellOfst[3]=3 cells (1 PI)
8971 00:41:26.268045 u2DelayCellOfst[4]=7 cells (2 PI)
8972 00:41:26.271527 u2DelayCellOfst[5]=18 cells (5 PI)
8973 00:41:26.274937 u2DelayCellOfst[6]=18 cells (5 PI)
8974 00:41:26.277862 u2DelayCellOfst[7]=3 cells (1 PI)
8975 00:41:26.281198 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8976 00:41:26.284603 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8977 00:41:26.288035 == TX Byte 1 ==
8978 00:41:26.291306 u2DelayCellOfst[8]=0 cells (0 PI)
8979 00:41:26.294772 u2DelayCellOfst[9]=7 cells (2 PI)
8980 00:41:26.297727 u2DelayCellOfst[10]=15 cells (4 PI)
8981 00:41:26.297804 u2DelayCellOfst[11]=7 cells (2 PI)
8982 00:41:26.301192 u2DelayCellOfst[12]=18 cells (5 PI)
8983 00:41:26.304633 u2DelayCellOfst[13]=18 cells (5 PI)
8984 00:41:26.307926 u2DelayCellOfst[14]=18 cells (5 PI)
8985 00:41:26.311109 u2DelayCellOfst[15]=18 cells (5 PI)
8986 00:41:26.317904 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8987 00:41:26.321216 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8988 00:41:26.321294 DramC Write-DBI on
8989 00:41:26.321354 ==
8990 00:41:26.324481 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 00:41:26.331181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 00:41:26.331261 ==
8993 00:41:26.331321
8994 00:41:26.331376
8995 00:41:26.334063 TX Vref Scan disable
8996 00:41:26.334140 == TX Byte 0 ==
8997 00:41:26.340731 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8998 00:41:26.340809 == TX Byte 1 ==
8999 00:41:26.344439 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9000 00:41:26.347543 DramC Write-DBI off
9001 00:41:26.347620
9002 00:41:26.347680 [DATLAT]
9003 00:41:26.351020 Freq=1600, CH1 RK1
9004 00:41:26.351097
9005 00:41:26.351158 DATLAT Default: 0xf
9006 00:41:26.354019 0, 0xFFFF, sum = 0
9007 00:41:26.354098 1, 0xFFFF, sum = 0
9008 00:41:26.357656 2, 0xFFFF, sum = 0
9009 00:41:26.357734 3, 0xFFFF, sum = 0
9010 00:41:26.361155 4, 0xFFFF, sum = 0
9011 00:41:26.361233 5, 0xFFFF, sum = 0
9012 00:41:26.364065 6, 0xFFFF, sum = 0
9013 00:41:26.364143 7, 0xFFFF, sum = 0
9014 00:41:26.367423 8, 0xFFFF, sum = 0
9015 00:41:26.367515 9, 0xFFFF, sum = 0
9016 00:41:26.370927 10, 0xFFFF, sum = 0
9017 00:41:26.374029 11, 0xFFFF, sum = 0
9018 00:41:26.374107 12, 0xFFFF, sum = 0
9019 00:41:26.377324 13, 0x8FFF, sum = 0
9020 00:41:26.377402 14, 0x0, sum = 1
9021 00:41:26.380848 15, 0x0, sum = 2
9022 00:41:26.380926 16, 0x0, sum = 3
9023 00:41:26.383780 17, 0x0, sum = 4
9024 00:41:26.383859 best_step = 15
9025 00:41:26.383918
9026 00:41:26.383974 ==
9027 00:41:26.387085 Dram Type= 6, Freq= 0, CH_1, rank 1
9028 00:41:26.390602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9029 00:41:26.390680 ==
9030 00:41:26.394158 RX Vref Scan: 0
9031 00:41:26.394235
9032 00:41:26.397309 RX Vref 0 -> 0, step: 1
9033 00:41:26.397388
9034 00:41:26.397448 RX Delay 3 -> 252, step: 4
9035 00:41:26.404172 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9036 00:41:26.407656 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9037 00:41:26.410954 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9038 00:41:26.414309 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9039 00:41:26.417499 iDelay=195, Bit 4, Center 124 (71 ~ 178) 108
9040 00:41:26.424205 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9041 00:41:26.427629 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9042 00:41:26.430624 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9043 00:41:26.434169 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9044 00:41:26.437484 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9045 00:41:26.443788 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9046 00:41:26.447670 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9047 00:41:26.450545 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9048 00:41:26.453836 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9049 00:41:26.460653 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9050 00:41:26.463911 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9051 00:41:26.463988 ==
9052 00:41:26.467186 Dram Type= 6, Freq= 0, CH_1, rank 1
9053 00:41:26.470477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9054 00:41:26.470554 ==
9055 00:41:26.470614 DQS Delay:
9056 00:41:26.473844 DQS0 = 0, DQS1 = 0
9057 00:41:26.473920 DQM Delay:
9058 00:41:26.476931 DQM0 = 129, DQM1 = 125
9059 00:41:26.477008 DQ Delay:
9060 00:41:26.480672 DQ0 =134, DQ1 =128, DQ2 =116, DQ3 =126
9061 00:41:26.484458 DQ4 =124, DQ5 =140, DQ6 =142, DQ7 =128
9062 00:41:26.487397 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
9063 00:41:26.493718 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =136
9064 00:41:26.493810
9065 00:41:26.493903
9066 00:41:26.493985
9067 00:41:26.494065 [DramC_TX_OE_Calibration] TA2
9068 00:41:26.497152 Original DQ_B0 (3 6) =30, OEN = 27
9069 00:41:26.500444 Original DQ_B1 (3 6) =30, OEN = 27
9070 00:41:26.503913 24, 0x0, End_B0=24 End_B1=24
9071 00:41:26.507303 25, 0x0, End_B0=25 End_B1=25
9072 00:41:26.510249 26, 0x0, End_B0=26 End_B1=26
9073 00:41:26.510328 27, 0x0, End_B0=27 End_B1=27
9074 00:41:26.513639 28, 0x0, End_B0=28 End_B1=28
9075 00:41:26.517041 29, 0x0, End_B0=29 End_B1=29
9076 00:41:26.520435 30, 0x0, End_B0=30 End_B1=30
9077 00:41:26.523713 31, 0x4141, End_B0=30 End_B1=30
9078 00:41:26.523795 Byte0 end_step=30 best_step=27
9079 00:41:26.527403 Byte1 end_step=30 best_step=27
9080 00:41:26.530443 Byte0 TX OE(2T, 0.5T) = (3, 3)
9081 00:41:26.534051 Byte1 TX OE(2T, 0.5T) = (3, 3)
9082 00:41:26.534128
9083 00:41:26.534190
9084 00:41:26.543598 [DQSOSCAuto] RK1, (LSB)MR18= 0x1320, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
9085 00:41:26.543678 CH1 RK1: MR19=303, MR18=1320
9086 00:41:26.550331 CH1_RK1: MR19=0x303, MR18=0x1320, DQSOSC=393, MR23=63, INC=23, DEC=15
9087 00:41:26.553822 [RxdqsGatingPostProcess] freq 1600
9088 00:41:26.560105 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9089 00:41:26.563370 best DQS0 dly(2T, 0.5T) = (1, 1)
9090 00:41:26.566995 best DQS1 dly(2T, 0.5T) = (1, 1)
9091 00:41:26.570194 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9092 00:41:26.573365 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9093 00:41:26.573442 best DQS0 dly(2T, 0.5T) = (1, 1)
9094 00:41:26.577059 best DQS1 dly(2T, 0.5T) = (1, 1)
9095 00:41:26.580341 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9096 00:41:26.583212 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9097 00:41:26.586608 Pre-setting of DQS Precalculation
9098 00:41:26.593344 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9099 00:41:26.599854 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9100 00:41:26.606951 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9101 00:41:26.607029
9102 00:41:26.607089
9103 00:41:26.609801 [Calibration Summary] 3200 Mbps
9104 00:41:26.609921 CH 0, Rank 0
9105 00:41:26.613210 SW Impedance : PASS
9106 00:41:26.616677 DUTY Scan : NO K
9107 00:41:26.616783 ZQ Calibration : PASS
9108 00:41:26.619659 Jitter Meter : NO K
9109 00:41:26.623038 CBT Training : PASS
9110 00:41:26.623122 Write leveling : PASS
9111 00:41:26.626512 RX DQS gating : PASS
9112 00:41:26.629730 RX DQ/DQS(RDDQC) : PASS
9113 00:41:26.629818 TX DQ/DQS : PASS
9114 00:41:26.632952 RX DATLAT : PASS
9115 00:41:26.633030 RX DQ/DQS(Engine): PASS
9116 00:41:26.636285 TX OE : PASS
9117 00:41:26.636363 All Pass.
9118 00:41:26.636423
9119 00:41:26.639737 CH 0, Rank 1
9120 00:41:26.639814 SW Impedance : PASS
9121 00:41:26.642853 DUTY Scan : NO K
9122 00:41:26.646196 ZQ Calibration : PASS
9123 00:41:26.646274 Jitter Meter : NO K
9124 00:41:26.649664 CBT Training : PASS
9125 00:41:26.652927 Write leveling : PASS
9126 00:41:26.653004 RX DQS gating : PASS
9127 00:41:26.656272 RX DQ/DQS(RDDQC) : PASS
9128 00:41:26.659676 TX DQ/DQS : PASS
9129 00:41:26.659754 RX DATLAT : PASS
9130 00:41:26.663050 RX DQ/DQS(Engine): PASS
9131 00:41:26.666528 TX OE : PASS
9132 00:41:26.666622 All Pass.
9133 00:41:26.666706
9134 00:41:26.666790 CH 1, Rank 0
9135 00:41:26.669718 SW Impedance : PASS
9136 00:41:26.673184 DUTY Scan : NO K
9137 00:41:26.673263 ZQ Calibration : PASS
9138 00:41:26.676271 Jitter Meter : NO K
9139 00:41:26.679752 CBT Training : PASS
9140 00:41:26.679829 Write leveling : PASS
9141 00:41:26.682755 RX DQS gating : PASS
9142 00:41:26.686400 RX DQ/DQS(RDDQC) : PASS
9143 00:41:26.686477 TX DQ/DQS : PASS
9144 00:41:26.689752 RX DATLAT : PASS
9145 00:41:26.689830 RX DQ/DQS(Engine): PASS
9146 00:41:26.693041 TX OE : PASS
9147 00:41:26.693118 All Pass.
9148 00:41:26.693178
9149 00:41:26.696431 CH 1, Rank 1
9150 00:41:26.696507 SW Impedance : PASS
9151 00:41:26.699241 DUTY Scan : NO K
9152 00:41:26.702727 ZQ Calibration : PASS
9153 00:41:26.702805 Jitter Meter : NO K
9154 00:41:26.706156 CBT Training : PASS
9155 00:41:26.709536 Write leveling : PASS
9156 00:41:26.709613 RX DQS gating : PASS
9157 00:41:26.712769 RX DQ/DQS(RDDQC) : PASS
9158 00:41:26.716015 TX DQ/DQS : PASS
9159 00:41:26.716093 RX DATLAT : PASS
9160 00:41:26.719160 RX DQ/DQS(Engine): PASS
9161 00:41:26.722385 TX OE : PASS
9162 00:41:26.722495 All Pass.
9163 00:41:26.722568
9164 00:41:26.722626 DramC Write-DBI on
9165 00:41:26.725644 PER_BANK_REFRESH: Hybrid Mode
9166 00:41:26.728960 TX_TRACKING: ON
9167 00:41:26.735838 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9168 00:41:26.746121 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9169 00:41:26.752178 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9170 00:41:26.755591 [FAST_K] Save calibration result to emmc
9171 00:41:26.758923 sync common calibartion params.
9172 00:41:26.762293 sync cbt_mode0:1, 1:1
9173 00:41:26.762370 dram_init: ddr_geometry: 2
9174 00:41:26.765831 dram_init: ddr_geometry: 2
9175 00:41:26.768794 dram_init: ddr_geometry: 2
9176 00:41:26.768872 0:dram_rank_size:100000000
9177 00:41:26.772122 1:dram_rank_size:100000000
9178 00:41:26.778857 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9179 00:41:26.782140 DFS_SHUFFLE_HW_MODE: ON
9180 00:41:26.785592 dramc_set_vcore_voltage set vcore to 725000
9181 00:41:26.785670 Read voltage for 1600, 0
9182 00:41:26.789173 Vio18 = 0
9183 00:41:26.789250 Vcore = 725000
9184 00:41:26.789310 Vdram = 0
9185 00:41:26.792162 Vddq = 0
9186 00:41:26.792238 Vmddr = 0
9187 00:41:26.795853 switch to 3200 Mbps bootup
9188 00:41:26.795930 [DramcRunTimeConfig]
9189 00:41:26.795990 PHYPLL
9190 00:41:26.798624 DPM_CONTROL_AFTERK: ON
9191 00:41:26.801948 PER_BANK_REFRESH: ON
9192 00:41:26.802025 REFRESH_OVERHEAD_REDUCTION: ON
9193 00:41:26.805376 CMD_PICG_NEW_MODE: OFF
9194 00:41:26.808782 XRTWTW_NEW_MODE: ON
9195 00:41:26.808859 XRTRTR_NEW_MODE: ON
9196 00:41:26.812099 TX_TRACKING: ON
9197 00:41:26.812195 RDSEL_TRACKING: OFF
9198 00:41:26.815474 DQS Precalculation for DVFS: ON
9199 00:41:26.818807 RX_TRACKING: OFF
9200 00:41:26.818941 HW_GATING DBG: ON
9201 00:41:26.822181 ZQCS_ENABLE_LP4: ON
9202 00:41:26.822257 RX_PICG_NEW_MODE: ON
9203 00:41:26.825130 TX_PICG_NEW_MODE: ON
9204 00:41:26.825208 ENABLE_RX_DCM_DPHY: ON
9205 00:41:26.828339 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9206 00:41:26.831616 DUMMY_READ_FOR_TRACKING: OFF
9207 00:41:26.835119 !!! SPM_CONTROL_AFTERK: OFF
9208 00:41:26.838593 !!! SPM could not control APHY
9209 00:41:26.838671 IMPEDANCE_TRACKING: ON
9210 00:41:26.841840 TEMP_SENSOR: ON
9211 00:41:26.841917 HW_SAVE_FOR_SR: OFF
9212 00:41:26.845059 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9213 00:41:26.848232 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9214 00:41:26.851614 Read ODT Tracking: ON
9215 00:41:26.855508 Refresh Rate DeBounce: ON
9216 00:41:26.855586 DFS_NO_QUEUE_FLUSH: ON
9217 00:41:26.858574 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9218 00:41:26.861834 ENABLE_DFS_RUNTIME_MRW: OFF
9219 00:41:26.865284 DDR_RESERVE_NEW_MODE: ON
9220 00:41:26.865361 MR_CBT_SWITCH_FREQ: ON
9221 00:41:26.868120 =========================
9222 00:41:26.886767 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9223 00:41:26.890046 dram_init: ddr_geometry: 2
9224 00:41:26.908377 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9225 00:41:26.911926 dram_init: dram init end (result: 0)
9226 00:41:26.918166 DRAM-K: Full calibration passed in 24569 msecs
9227 00:41:26.921655 MRC: failed to locate region type 0.
9228 00:41:26.921733 DRAM rank0 size:0x100000000,
9229 00:41:26.925123 DRAM rank1 size=0x100000000
9230 00:41:26.934733 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9231 00:41:26.941628 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9232 00:41:26.948316 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9233 00:41:26.955322 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9234 00:41:26.958087 DRAM rank0 size:0x100000000,
9235 00:41:26.961214 DRAM rank1 size=0x100000000
9236 00:41:26.961292 CBMEM:
9237 00:41:26.964626 IMD: root @ 0xfffff000 254 entries.
9238 00:41:26.968175 IMD: root @ 0xffffec00 62 entries.
9239 00:41:26.971102 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9240 00:41:26.974568 WARNING: RO_VPD is uninitialized or empty.
9241 00:41:26.981392 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9242 00:41:26.988588 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9243 00:41:27.001607 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9244 00:41:27.012561 BS: romstage times (exec / console): total (unknown) / 24033 ms
9245 00:41:27.012639
9246 00:41:27.012737
9247 00:41:27.022507 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9248 00:41:27.026067 ARM64: Exception handlers installed.
9249 00:41:27.029018 ARM64: Testing exception
9250 00:41:27.032407 ARM64: Done test exception
9251 00:41:27.032484 Enumerating buses...
9252 00:41:27.035710 Show all devs... Before device enumeration.
9253 00:41:27.039033 Root Device: enabled 1
9254 00:41:27.042378 CPU_CLUSTER: 0: enabled 1
9255 00:41:27.042456 CPU: 00: enabled 1
9256 00:41:27.045871 Compare with tree...
9257 00:41:27.045948 Root Device: enabled 1
9258 00:41:27.048757 CPU_CLUSTER: 0: enabled 1
9259 00:41:27.052209 CPU: 00: enabled 1
9260 00:41:27.052286 Root Device scanning...
9261 00:41:27.055576 scan_static_bus for Root Device
9262 00:41:27.059248 CPU_CLUSTER: 0 enabled
9263 00:41:27.061942 scan_static_bus for Root Device done
9264 00:41:27.065458 scan_bus: bus Root Device finished in 8 msecs
9265 00:41:27.065536 done
9266 00:41:27.072301 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9267 00:41:27.075130 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9268 00:41:27.082093 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9269 00:41:27.085562 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9270 00:41:27.088978 Allocating resources...
9271 00:41:27.091904 Reading resources...
9272 00:41:27.095293 Root Device read_resources bus 0 link: 0
9273 00:41:27.095370 DRAM rank0 size:0x100000000,
9274 00:41:27.098598 DRAM rank1 size=0x100000000
9275 00:41:27.102048 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9276 00:41:27.105418 CPU: 00 missing read_resources
9277 00:41:27.112195 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9278 00:41:27.115076 Root Device read_resources bus 0 link: 0 done
9279 00:41:27.115153 Done reading resources.
9280 00:41:27.122001 Show resources in subtree (Root Device)...After reading.
9281 00:41:27.125024 Root Device child on link 0 CPU_CLUSTER: 0
9282 00:41:27.128498 CPU_CLUSTER: 0 child on link 0 CPU: 00
9283 00:41:27.138521 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9284 00:41:27.138600 CPU: 00
9285 00:41:27.141829 Root Device assign_resources, bus 0 link: 0
9286 00:41:27.145252 CPU_CLUSTER: 0 missing set_resources
9287 00:41:27.151603 Root Device assign_resources, bus 0 link: 0 done
9288 00:41:27.151680 Done setting resources.
9289 00:41:27.158528 Show resources in subtree (Root Device)...After assigning values.
9290 00:41:27.161853 Root Device child on link 0 CPU_CLUSTER: 0
9291 00:41:27.165295 CPU_CLUSTER: 0 child on link 0 CPU: 00
9292 00:41:27.175384 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9293 00:41:27.175463 CPU: 00
9294 00:41:27.178307 Done allocating resources.
9295 00:41:27.181667 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9296 00:41:27.184687 Enabling resources...
9297 00:41:27.184764 done.
9298 00:41:27.191390 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9299 00:41:27.191468 Initializing devices...
9300 00:41:27.194567 Root Device init
9301 00:41:27.194659 init hardware done!
9302 00:41:27.197943 0x00000018: ctrlr->caps
9303 00:41:27.201343 52.000 MHz: ctrlr->f_max
9304 00:41:27.201421 0.400 MHz: ctrlr->f_min
9305 00:41:27.204870 0x40ff8080: ctrlr->voltages
9306 00:41:27.208053 sclk: 390625
9307 00:41:27.208130 Bus Width = 1
9308 00:41:27.208190 sclk: 390625
9309 00:41:27.211357 Bus Width = 1
9310 00:41:27.211434 Early init status = 3
9311 00:41:27.218040 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9312 00:41:27.221642 in-header: 03 fc 00 00 01 00 00 00
9313 00:41:27.221719 in-data: 00
9314 00:41:27.227930 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9315 00:41:27.231718 in-header: 03 fd 00 00 00 00 00 00
9316 00:41:27.235300 in-data:
9317 00:41:27.238209 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9318 00:41:27.242705 in-header: 03 fc 00 00 01 00 00 00
9319 00:41:27.246258 in-data: 00
9320 00:41:27.249648 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9321 00:41:27.255344 in-header: 03 fd 00 00 00 00 00 00
9322 00:41:27.258158 in-data:
9323 00:41:27.261562 [SSUSB] Setting up USB HOST controller...
9324 00:41:27.265052 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9325 00:41:27.268455 [SSUSB] phy power-on done.
9326 00:41:27.271443 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9327 00:41:27.278198 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9328 00:41:27.281793 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9329 00:41:27.288126 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9330 00:41:27.294997 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9331 00:41:27.301647 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9332 00:41:27.308091 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9333 00:41:27.314779 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9334 00:41:27.317947 SPM: binary array size = 0x9dc
9335 00:41:27.321330 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9336 00:41:27.327962 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9337 00:41:27.334799 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9338 00:41:27.337675 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9339 00:41:27.344665 configure_display: Starting display init
9340 00:41:27.378321 anx7625_power_on_init: Init interface.
9341 00:41:27.381739 anx7625_disable_pd_protocol: Disabled PD feature.
9342 00:41:27.385148 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9343 00:41:27.412596 anx7625_start_dp_work: Secure OCM version=00
9344 00:41:27.415858 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9345 00:41:27.430513 sp_tx_get_edid_block: EDID Block = 1
9346 00:41:27.533624 Extracted contents:
9347 00:41:27.536497 header: 00 ff ff ff ff ff ff 00
9348 00:41:27.540005 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9349 00:41:27.543189 version: 01 04
9350 00:41:27.546525 basic params: 95 1f 11 78 0a
9351 00:41:27.549579 chroma info: 76 90 94 55 54 90 27 21 50 54
9352 00:41:27.553043 established: 00 00 00
9353 00:41:27.559703 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9354 00:41:27.563378 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9355 00:41:27.570037 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9356 00:41:27.576354 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9357 00:41:27.582844 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9358 00:41:27.586207 extensions: 00
9359 00:41:27.586285 checksum: fb
9360 00:41:27.586345
9361 00:41:27.589666 Manufacturer: IVO Model 57d Serial Number 0
9362 00:41:27.592623 Made week 0 of 2020
9363 00:41:27.592722 EDID version: 1.4
9364 00:41:27.596482 Digital display
9365 00:41:27.599481 6 bits per primary color channel
9366 00:41:27.599569 DisplayPort interface
9367 00:41:27.602618 Maximum image size: 31 cm x 17 cm
9368 00:41:27.606063 Gamma: 220%
9369 00:41:27.606140 Check DPMS levels
9370 00:41:27.609509 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9371 00:41:27.616135 First detailed timing is preferred timing
9372 00:41:27.616212 Established timings supported:
9373 00:41:27.619353 Standard timings supported:
9374 00:41:27.622846 Detailed timings
9375 00:41:27.626181 Hex of detail: 383680a07038204018303c0035ae10000019
9376 00:41:27.629504 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9377 00:41:27.635950 0780 0798 07c8 0820 hborder 0
9378 00:41:27.639227 0438 043b 0447 0458 vborder 0
9379 00:41:27.642678 -hsync -vsync
9380 00:41:27.642755 Did detailed timing
9381 00:41:27.649401 Hex of detail: 000000000000000000000000000000000000
9382 00:41:27.652106 Manufacturer-specified data, tag 0
9383 00:41:27.655358 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9384 00:41:27.658840 ASCII string: InfoVision
9385 00:41:27.662190 Hex of detail: 000000fe00523134304e574635205248200a
9386 00:41:27.665721 ASCII string: R140NWF5 RH
9387 00:41:27.665793 Checksum
9388 00:41:27.668927 Checksum: 0xfb (valid)
9389 00:41:27.672064 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9390 00:41:27.675578 DSI data_rate: 832800000 bps
9391 00:41:27.682317 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9392 00:41:27.685399 anx7625_parse_edid: pixelclock(138800).
9393 00:41:27.688842 hactive(1920), hsync(48), hfp(24), hbp(88)
9394 00:41:27.692270 vactive(1080), vsync(12), vfp(3), vbp(17)
9395 00:41:27.695520 anx7625_dsi_config: config dsi.
9396 00:41:27.702274 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9397 00:41:27.715183 anx7625_dsi_config: success to config DSI
9398 00:41:27.718569 anx7625_dp_start: MIPI phy setup OK.
9399 00:41:27.721946 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9400 00:41:27.725172 mtk_ddp_mode_set invalid vrefresh 60
9401 00:41:27.728503 main_disp_path_setup
9402 00:41:27.728579 ovl_layer_smi_id_en
9403 00:41:27.731844 ovl_layer_smi_id_en
9404 00:41:27.731922 ccorr_config
9405 00:41:27.731981 aal_config
9406 00:41:27.735269 gamma_config
9407 00:41:27.735345 postmask_config
9408 00:41:27.738611 dither_config
9409 00:41:27.742055 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9410 00:41:27.748667 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9411 00:41:27.751537 Root Device init finished in 554 msecs
9412 00:41:27.754902 CPU_CLUSTER: 0 init
9413 00:41:27.761719 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9414 00:41:27.765108 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9415 00:41:27.768512 APU_MBOX 0x190000b0 = 0x10001
9416 00:41:27.771452 APU_MBOX 0x190001b0 = 0x10001
9417 00:41:27.774955 APU_MBOX 0x190005b0 = 0x10001
9418 00:41:27.778349 APU_MBOX 0x190006b0 = 0x10001
9419 00:41:27.784873 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9420 00:41:27.794472 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9421 00:41:27.806621 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9422 00:41:27.813425 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9423 00:41:27.825479 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9424 00:41:27.834451 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9425 00:41:27.837740 CPU_CLUSTER: 0 init finished in 81 msecs
9426 00:41:27.841183 Devices initialized
9427 00:41:27.843991 Show all devs... After init.
9428 00:41:27.844068 Root Device: enabled 1
9429 00:41:27.847302 CPU_CLUSTER: 0: enabled 1
9430 00:41:27.850760 CPU: 00: enabled 1
9431 00:41:27.854127 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9432 00:41:27.857473 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9433 00:41:27.860857 ELOG: NV offset 0x57f000 size 0x1000
9434 00:41:27.867463 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9435 00:41:27.873800 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9436 00:41:27.877252 ELOG: Event(17) added with size 13 at 2024-06-16 00:41:27 UTC
9437 00:41:27.883527 out: cmd=0x121: 03 db 21 01 00 00 00 00
9438 00:41:27.887294 in-header: 03 86 00 00 2c 00 00 00
9439 00:41:27.896796 in-data: b7 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9440 00:41:27.903682 ELOG: Event(A1) added with size 10 at 2024-06-16 00:41:27 UTC
9441 00:41:27.909956 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9442 00:41:27.916931 ELOG: Event(A0) added with size 9 at 2024-06-16 00:41:27 UTC
9443 00:41:27.920221 elog_add_boot_reason: Logged dev mode boot
9444 00:41:27.923576 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9445 00:41:27.926651 Finalize devices...
9446 00:41:27.930449 Devices finalized
9447 00:41:27.933387 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9448 00:41:27.936660 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9449 00:41:27.940461 in-header: 03 07 00 00 08 00 00 00
9450 00:41:27.943965 in-data: aa e4 47 04 13 02 00 00
9451 00:41:27.946464 Chrome EC: UHEPI supported
9452 00:41:27.953375 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9453 00:41:27.956610 in-header: 03 a9 00 00 08 00 00 00
9454 00:41:27.959809 in-data: 84 60 60 08 00 00 00 00
9455 00:41:27.963560 ELOG: Event(91) added with size 10 at 2024-06-16 00:41:27 UTC
9456 00:41:27.970152 Chrome EC: clear events_b mask to 0x0000000020004000
9457 00:41:27.976495 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9458 00:41:27.979939 in-header: 03 fd 00 00 00 00 00 00
9459 00:41:27.980040 in-data:
9460 00:41:27.986857 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9461 00:41:27.990274 Writing coreboot table at 0xffe64000
9462 00:41:27.993552 0. 000000000010a000-0000000000113fff: RAMSTAGE
9463 00:41:27.997002 1. 0000000040000000-00000000400fffff: RAM
9464 00:41:28.003491 2. 0000000040100000-000000004032afff: RAMSTAGE
9465 00:41:28.006585 3. 000000004032b000-00000000545fffff: RAM
9466 00:41:28.009894 4. 0000000054600000-000000005465ffff: BL31
9467 00:41:28.013380 5. 0000000054660000-00000000ffe63fff: RAM
9468 00:41:28.019744 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9469 00:41:28.023226 7. 0000000100000000-000000023fffffff: RAM
9470 00:41:28.026717 Passing 5 GPIOs to payload:
9471 00:41:28.030165 NAME | PORT | POLARITY | VALUE
9472 00:41:28.033393 EC in RW | 0x000000aa | low | undefined
9473 00:41:28.039652 EC interrupt | 0x00000005 | low | undefined
9474 00:41:28.043134 TPM interrupt | 0x000000ab | high | undefined
9475 00:41:28.049982 SD card detect | 0x00000011 | high | undefined
9476 00:41:28.052848 speaker enable | 0x00000093 | high | undefined
9477 00:41:28.056045 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9478 00:41:28.059755 in-header: 03 f9 00 00 02 00 00 00
9479 00:41:28.063274 in-data: 02 00
9480 00:41:28.063351 ADC[4]: Raw value=896670 ID=7
9481 00:41:28.066300 ADC[3]: Raw value=211960 ID=1
9482 00:41:28.069787 RAM Code: 0x71
9483 00:41:28.069864 ADC[6]: Raw value=74722 ID=0
9484 00:41:28.073046 ADC[5]: Raw value=211590 ID=1
9485 00:41:28.076520 SKU Code: 0x1
9486 00:41:28.079889 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2329
9487 00:41:28.083046 coreboot table: 964 bytes.
9488 00:41:28.087011 IMD ROOT 0. 0xfffff000 0x00001000
9489 00:41:28.089359 IMD SMALL 1. 0xffffe000 0x00001000
9490 00:41:28.092748 RO MCACHE 2. 0xffffc000 0x00001104
9491 00:41:28.096204 CONSOLE 3. 0xfff7c000 0x00080000
9492 00:41:28.099522 FMAP 4. 0xfff7b000 0x00000452
9493 00:41:28.102890 TIME STAMP 5. 0xfff7a000 0x00000910
9494 00:41:28.106288 VBOOT WORK 6. 0xfff66000 0x00014000
9495 00:41:28.109605 RAMOOPS 7. 0xffe66000 0x00100000
9496 00:41:28.112755 COREBOOT 8. 0xffe64000 0x00002000
9497 00:41:28.112846 IMD small region:
9498 00:41:28.116355 IMD ROOT 0. 0xffffec00 0x00000400
9499 00:41:28.119270 VPD 1. 0xffffeb80 0x0000006c
9500 00:41:28.125639 MMC STATUS 2. 0xffffeb60 0x00000004
9501 00:41:28.129052 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9502 00:41:28.135884 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9503 00:41:28.176041 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9504 00:41:28.179350 Checking segment from ROM address 0x40100000
9505 00:41:28.182637 Checking segment from ROM address 0x4010001c
9506 00:41:28.189374 Loading segment from ROM address 0x40100000
9507 00:41:28.189451 code (compression=0)
9508 00:41:28.199260 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9509 00:41:28.206190 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9510 00:41:28.206298 it's not compressed!
9511 00:41:28.212731 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9512 00:41:28.219138 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9513 00:41:28.236682 Loading segment from ROM address 0x4010001c
9514 00:41:28.236787 Entry Point 0x80000000
9515 00:41:28.239613 Loaded segments
9516 00:41:28.243020 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9517 00:41:28.249936 Jumping to boot code at 0x80000000(0xffe64000)
9518 00:41:28.256134 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9519 00:41:28.263001 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9520 00:41:28.270860 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9521 00:41:28.274280 Checking segment from ROM address 0x40100000
9522 00:41:28.277869 Checking segment from ROM address 0x4010001c
9523 00:41:28.284017 Loading segment from ROM address 0x40100000
9524 00:41:28.284088 code (compression=1)
9525 00:41:28.290904 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9526 00:41:28.300654 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9527 00:41:28.300775 using LZMA
9528 00:41:28.309021 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9529 00:41:28.315645 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9530 00:41:28.319136 Loading segment from ROM address 0x4010001c
9531 00:41:28.319229 Entry Point 0x54601000
9532 00:41:28.322378 Loaded segments
9533 00:41:28.325704 NOTICE: MT8192 bl31_setup
9534 00:41:28.332569 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9535 00:41:28.336016 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9536 00:41:28.339628 WARNING: region 0:
9537 00:41:28.342920 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9538 00:41:28.342989 WARNING: region 1:
9539 00:41:28.349218 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9540 00:41:28.352601 WARNING: region 2:
9541 00:41:28.356106 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9542 00:41:28.359527 WARNING: region 3:
9543 00:41:28.362444 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9544 00:41:28.365917 WARNING: region 4:
9545 00:41:28.372506 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9546 00:41:28.372584 WARNING: region 5:
9547 00:41:28.376134 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 00:41:28.379576 WARNING: region 6:
9549 00:41:28.382692 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9550 00:41:28.385972 WARNING: region 7:
9551 00:41:28.389193 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9552 00:41:28.395937 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9553 00:41:28.399200 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9554 00:41:28.402254 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9555 00:41:28.409362 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9556 00:41:28.412225 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9557 00:41:28.418984 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9558 00:41:28.422416 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9559 00:41:28.425700 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9560 00:41:28.432370 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9561 00:41:28.435651 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9562 00:41:28.441985 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9563 00:41:28.445488 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9564 00:41:28.448942 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9565 00:41:28.455160 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9566 00:41:28.458640 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9567 00:41:28.462006 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9568 00:41:28.468689 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9569 00:41:28.472031 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9570 00:41:28.478273 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9571 00:41:28.481651 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9572 00:41:28.485550 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9573 00:41:28.491616 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9574 00:41:28.494987 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9575 00:41:28.498605 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9576 00:41:28.504942 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9577 00:41:28.508524 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9578 00:41:28.514823 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9579 00:41:28.518062 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9580 00:41:28.524891 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9581 00:41:28.528336 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9582 00:41:28.531553 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9583 00:41:28.538357 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9584 00:41:28.541482 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9585 00:41:28.544818 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9586 00:41:28.548003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9587 00:41:28.554809 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9588 00:41:28.558267 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9589 00:41:28.561655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9590 00:41:28.564526 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9591 00:41:28.571480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9592 00:41:28.574829 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9593 00:41:28.577798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9594 00:41:28.581256 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9595 00:41:28.588006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9596 00:41:28.591554 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9597 00:41:28.594281 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9598 00:41:28.601152 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9599 00:41:28.604522 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9600 00:41:28.607529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9601 00:41:28.614463 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9602 00:41:28.617834 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9603 00:41:28.624383 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9604 00:41:28.627562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9605 00:41:28.630785 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9606 00:41:28.637648 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9607 00:41:28.641137 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9608 00:41:28.647482 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9609 00:41:28.651234 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9610 00:41:28.657346 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9611 00:41:28.660577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9612 00:41:28.667260 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9613 00:41:28.670498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9614 00:41:28.673852 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9615 00:41:28.680799 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9616 00:41:28.683702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9617 00:41:28.690481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9618 00:41:28.694001 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9619 00:41:28.700288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9620 00:41:28.703715 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9621 00:41:28.707180 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9622 00:41:28.713495 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9623 00:41:28.716907 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9624 00:41:28.723661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9625 00:41:28.727058 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9626 00:41:28.733390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9627 00:41:28.736516 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9628 00:41:28.743326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9629 00:41:28.746568 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9630 00:41:28.753286 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9631 00:41:28.756394 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9632 00:41:28.759994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9633 00:41:28.766929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9634 00:41:28.769756 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9635 00:41:28.776959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9636 00:41:28.779789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9637 00:41:28.786655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9638 00:41:28.789618 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9639 00:41:28.793013 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9640 00:41:28.799455 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9641 00:41:28.802829 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9642 00:41:28.809692 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9643 00:41:28.813148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9644 00:41:28.819302 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9645 00:41:28.822615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9646 00:41:28.829340 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9647 00:41:28.832773 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9648 00:41:28.836441 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9649 00:41:28.842545 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9650 00:41:28.846043 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9651 00:41:28.849255 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9652 00:41:28.852592 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9653 00:41:28.859321 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9654 00:41:28.862480 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9655 00:41:28.869227 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9656 00:41:28.872402 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9657 00:41:28.875652 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9658 00:41:28.882272 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9659 00:41:28.885728 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9660 00:41:28.892587 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9661 00:41:28.895809 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9662 00:41:28.898885 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9663 00:41:28.905153 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9664 00:41:28.908606 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9665 00:41:28.915552 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9666 00:41:28.918465 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9667 00:41:28.921787 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9668 00:41:28.928515 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9669 00:41:28.931878 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9670 00:41:28.935462 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9671 00:41:28.941619 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9672 00:41:28.945044 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9673 00:41:28.948017 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9674 00:41:28.951356 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9675 00:41:28.958126 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9676 00:41:28.961334 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9677 00:41:28.967855 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9678 00:41:28.971273 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9679 00:41:28.974505 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9680 00:41:28.981441 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9681 00:41:28.984523 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9682 00:41:28.987491 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9683 00:41:28.994239 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9684 00:41:28.997904 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9685 00:41:29.004070 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9686 00:41:29.007576 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9687 00:41:29.014144 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9688 00:41:29.017550 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9689 00:41:29.020947 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9690 00:41:29.027172 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9691 00:41:29.030608 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9692 00:41:29.034038 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9693 00:41:29.040669 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9694 00:41:29.043992 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9695 00:41:29.050579 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9696 00:41:29.054041 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9697 00:41:29.057355 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9698 00:41:29.063721 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9699 00:41:29.067106 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9700 00:41:29.073905 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9701 00:41:29.077358 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9702 00:41:29.080188 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9703 00:41:29.087019 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9704 00:41:29.090349 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9705 00:41:29.096982 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9706 00:41:29.100343 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9707 00:41:29.103655 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9708 00:41:29.110362 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9709 00:41:29.113514 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9710 00:41:29.120321 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9711 00:41:29.123577 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9712 00:41:29.126500 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9713 00:41:29.133163 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9714 00:41:29.136529 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9715 00:41:29.143287 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9716 00:41:29.146245 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9717 00:41:29.149692 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9718 00:41:29.156513 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9719 00:41:29.159707 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9720 00:41:29.166627 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9721 00:41:29.169478 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9722 00:41:29.173087 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9723 00:41:29.179499 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9724 00:41:29.182716 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9725 00:41:29.189341 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9726 00:41:29.192828 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9727 00:41:29.196228 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9728 00:41:29.202931 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9729 00:41:29.206053 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9730 00:41:29.212598 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9731 00:41:29.215861 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9732 00:41:29.219609 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9733 00:41:29.225629 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9734 00:41:29.229029 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9735 00:41:29.235940 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9736 00:41:29.238748 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9737 00:41:29.242140 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9738 00:41:29.248689 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9739 00:41:29.252189 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9740 00:41:29.258950 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9741 00:41:29.262331 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9742 00:41:29.265651 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9743 00:41:29.272165 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9744 00:41:29.275588 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9745 00:41:29.282383 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9746 00:41:29.285554 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9747 00:41:29.288623 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9748 00:41:29.295627 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9749 00:41:29.298686 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9750 00:41:29.305125 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9751 00:41:29.308385 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9752 00:41:29.315152 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9753 00:41:29.318497 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9754 00:41:29.321969 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9755 00:41:29.328182 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9756 00:41:29.331525 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9757 00:41:29.338199 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9758 00:41:29.341813 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9759 00:41:29.345144 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9760 00:41:29.351408 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9761 00:41:29.354737 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9762 00:41:29.361705 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9763 00:41:29.364568 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9764 00:41:29.371322 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9765 00:41:29.374770 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9766 00:41:29.377721 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9767 00:41:29.384618 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9768 00:41:29.388146 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9769 00:41:29.394377 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9770 00:41:29.397567 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9771 00:41:29.404230 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9772 00:41:29.407594 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9773 00:41:29.411322 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9774 00:41:29.417892 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9775 00:41:29.420842 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9776 00:41:29.427632 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9777 00:41:29.430993 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9778 00:41:29.437549 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9779 00:41:29.440588 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9780 00:41:29.444385 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9781 00:41:29.451032 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9782 00:41:29.453984 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9783 00:41:29.457407 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9784 00:41:29.460599 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9785 00:41:29.464147 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9786 00:41:29.470831 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9787 00:41:29.473868 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9788 00:41:29.480373 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9789 00:41:29.483733 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9790 00:41:29.487150 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9791 00:41:29.494034 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9792 00:41:29.497381 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9793 00:41:29.500772 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9794 00:41:29.507303 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9795 00:41:29.510332 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9796 00:41:29.517216 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9797 00:41:29.520618 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9798 00:41:29.523547 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9799 00:41:29.530371 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9800 00:41:29.533761 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9801 00:41:29.537018 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9802 00:41:29.543650 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9803 00:41:29.547141 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9804 00:41:29.553536 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9805 00:41:29.556724 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9806 00:41:29.560175 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9807 00:41:29.566958 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9808 00:41:29.570315 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9809 00:41:29.573772 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9810 00:41:29.579968 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9811 00:41:29.583519 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9812 00:41:29.586594 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9813 00:41:29.593217 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9814 00:41:29.596508 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9815 00:41:29.599811 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9816 00:41:29.606664 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9817 00:41:29.610013 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9818 00:41:29.616188 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9819 00:41:29.619875 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9820 00:41:29.623397 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9821 00:41:29.629999 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9822 00:41:29.632896 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9823 00:41:29.636334 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9824 00:41:29.639879 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9825 00:41:29.643394 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9826 00:41:29.649647 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9827 00:41:29.653110 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9828 00:41:29.656447 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9829 00:41:29.659681 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9830 00:41:29.666491 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9831 00:41:29.669826 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9832 00:41:29.673163 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9833 00:41:29.679553 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9834 00:41:29.682906 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9835 00:41:29.686480 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9836 00:41:29.692653 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9837 00:41:29.696031 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9838 00:41:29.703058 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9839 00:41:29.706154 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9840 00:41:29.712921 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9841 00:41:29.716448 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9842 00:41:29.719302 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9843 00:41:29.725725 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9844 00:41:29.729037 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9845 00:41:29.736007 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9846 00:41:29.738956 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9847 00:41:29.742755 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9848 00:41:29.749114 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9849 00:41:29.752535 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9850 00:41:29.759076 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9851 00:41:29.762390 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9852 00:41:29.765685 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9853 00:41:29.772676 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9854 00:41:29.775747 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9855 00:41:29.782043 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9856 00:41:29.785454 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9857 00:41:29.789068 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9858 00:41:29.795995 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9859 00:41:29.798772 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9860 00:41:29.805608 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9861 00:41:29.809167 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9862 00:41:29.812545 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9863 00:41:29.819090 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9864 00:41:29.822000 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9865 00:41:29.828630 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9866 00:41:29.831736 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9867 00:41:29.838529 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9868 00:41:29.841997 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9869 00:41:29.845098 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9870 00:41:29.851895 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9871 00:41:29.855306 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9872 00:41:29.862027 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9873 00:41:29.865210 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9874 00:41:29.868493 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9875 00:41:29.875133 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9876 00:41:29.878754 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9877 00:41:29.885651 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9878 00:41:29.889049 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9879 00:41:29.891912 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9880 00:41:29.898226 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9881 00:41:29.901875 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9882 00:41:29.908395 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9883 00:41:29.911808 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9884 00:41:29.918760 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9885 00:41:29.921643 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9886 00:41:29.924861 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9887 00:41:29.931235 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9888 00:41:29.935004 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9889 00:41:29.941333 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9890 00:41:29.944529 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9891 00:41:29.947576 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9892 00:41:29.954516 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9893 00:41:29.957735 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9894 00:41:29.964492 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9895 00:41:29.967777 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9896 00:41:29.974287 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9897 00:41:29.977726 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9898 00:41:29.981102 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9899 00:41:29.987228 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9900 00:41:29.990912 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9901 00:41:29.997568 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9902 00:41:30.001114 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9903 00:41:30.003892 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9904 00:41:30.010523 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9905 00:41:30.013854 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9906 00:41:30.020774 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9907 00:41:30.024173 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9908 00:41:30.030476 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9909 00:41:30.033580 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9910 00:41:30.037089 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9911 00:41:30.043973 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9912 00:41:30.047335 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9913 00:41:30.053540 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9914 00:41:30.056922 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9915 00:41:30.063479 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9916 00:41:30.066811 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9917 00:41:30.073464 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9918 00:41:30.076825 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9919 00:41:30.080035 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9920 00:41:30.086710 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9921 00:41:30.090010 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9922 00:41:30.096610 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9923 00:41:30.099934 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9924 00:41:30.106247 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9925 00:41:30.109621 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9926 00:41:30.116197 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9927 00:41:30.119644 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9928 00:41:30.123277 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9929 00:41:30.129568 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9930 00:41:30.133083 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9931 00:41:30.139681 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9932 00:41:30.142889 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9933 00:41:30.149815 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9934 00:41:30.152631 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9935 00:41:30.156222 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9936 00:41:30.162852 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9937 00:41:30.165942 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9938 00:41:30.172846 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9939 00:41:30.176191 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9940 00:41:30.182487 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9941 00:41:30.186197 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9942 00:41:30.192409 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9943 00:41:30.195933 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9944 00:41:30.199191 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9945 00:41:30.205947 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9946 00:41:30.209102 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9947 00:41:30.216039 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9948 00:41:30.219031 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9949 00:41:30.225948 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9950 00:41:30.228904 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9951 00:41:30.232289 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9952 00:41:30.239059 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9953 00:41:30.242306 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9954 00:41:30.248877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9955 00:41:30.252390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9956 00:41:30.255825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9957 00:41:30.262260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9958 00:41:30.265740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9959 00:41:30.272038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9960 00:41:30.275320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9961 00:41:30.282174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9962 00:41:30.285266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9963 00:41:30.292123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9964 00:41:30.295507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9965 00:41:30.301948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9966 00:41:30.304935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9967 00:41:30.312130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9968 00:41:30.315040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9969 00:41:30.321596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9970 00:41:30.325058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9971 00:41:30.331909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9972 00:41:30.334977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9973 00:41:30.341308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9974 00:41:30.344808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9975 00:41:30.351531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9976 00:41:30.354861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9977 00:41:30.361692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9978 00:41:30.365049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9979 00:41:30.371416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9980 00:41:30.374747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9981 00:41:30.381084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9982 00:41:30.384514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9983 00:41:30.391324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9984 00:41:30.394601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9985 00:41:30.401189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9986 00:41:30.404363 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9987 00:41:30.407603 INFO: [APUAPC] vio 0
9988 00:41:30.411065 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9989 00:41:30.418076 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9990 00:41:30.420865 INFO: [APUAPC] D0_APC_0: 0x400510
9991 00:41:30.420935 INFO: [APUAPC] D0_APC_1: 0x0
9992 00:41:30.424099 INFO: [APUAPC] D0_APC_2: 0x1540
9993 00:41:30.427754 INFO: [APUAPC] D0_APC_3: 0x0
9994 00:41:30.431053 INFO: [APUAPC] D1_APC_0: 0xffffffff
9995 00:41:30.434225 INFO: [APUAPC] D1_APC_1: 0xffffffff
9996 00:41:30.437383 INFO: [APUAPC] D1_APC_2: 0x3fffff
9997 00:41:30.440915 INFO: [APUAPC] D1_APC_3: 0x0
9998 00:41:30.443865 INFO: [APUAPC] D2_APC_0: 0xffffffff
9999 00:41:30.447165 INFO: [APUAPC] D2_APC_1: 0xffffffff
10000 00:41:30.450484 INFO: [APUAPC] D2_APC_2: 0x3fffff
10001 00:41:30.453803 INFO: [APUAPC] D2_APC_3: 0x0
10002 00:41:30.457324 INFO: [APUAPC] D3_APC_0: 0xffffffff
10003 00:41:30.460772 INFO: [APUAPC] D3_APC_1: 0xffffffff
10004 00:41:30.464204 INFO: [APUAPC] D3_APC_2: 0x3fffff
10005 00:41:30.467493 INFO: [APUAPC] D3_APC_3: 0x0
10006 00:41:30.470659 INFO: [APUAPC] D4_APC_0: 0xffffffff
10007 00:41:30.474141 INFO: [APUAPC] D4_APC_1: 0xffffffff
10008 00:41:30.477015 INFO: [APUAPC] D4_APC_2: 0x3fffff
10009 00:41:30.480448 INFO: [APUAPC] D4_APC_3: 0x0
10010 00:41:30.483949 INFO: [APUAPC] D5_APC_0: 0xffffffff
10011 00:41:30.487282 INFO: [APUAPC] D5_APC_1: 0xffffffff
10012 00:41:30.490734 INFO: [APUAPC] D5_APC_2: 0x3fffff
10013 00:41:30.493598 INFO: [APUAPC] D5_APC_3: 0x0
10014 00:41:30.497285 INFO: [APUAPC] D6_APC_0: 0xffffffff
10015 00:41:30.500766 INFO: [APUAPC] D6_APC_1: 0xffffffff
10016 00:41:30.503389 INFO: [APUAPC] D6_APC_2: 0x3fffff
10017 00:41:30.506935 INFO: [APUAPC] D6_APC_3: 0x0
10018 00:41:30.510495 INFO: [APUAPC] D7_APC_0: 0xffffffff
10019 00:41:30.513511 INFO: [APUAPC] D7_APC_1: 0xffffffff
10020 00:41:30.517117 INFO: [APUAPC] D7_APC_2: 0x3fffff
10021 00:41:30.520061 INFO: [APUAPC] D7_APC_3: 0x0
10022 00:41:30.523557 INFO: [APUAPC] D8_APC_0: 0xffffffff
10023 00:41:30.526947 INFO: [APUAPC] D8_APC_1: 0xffffffff
10024 00:41:30.530177 INFO: [APUAPC] D8_APC_2: 0x3fffff
10025 00:41:30.533601 INFO: [APUAPC] D8_APC_3: 0x0
10026 00:41:30.536572 INFO: [APUAPC] D9_APC_0: 0xffffffff
10027 00:41:30.539762 INFO: [APUAPC] D9_APC_1: 0xffffffff
10028 00:41:30.543176 INFO: [APUAPC] D9_APC_2: 0x3fffff
10029 00:41:30.546544 INFO: [APUAPC] D9_APC_3: 0x0
10030 00:41:30.549730 INFO: [APUAPC] D10_APC_0: 0xffffffff
10031 00:41:30.553207 INFO: [APUAPC] D10_APC_1: 0xffffffff
10032 00:41:30.556509 INFO: [APUAPC] D10_APC_2: 0x3fffff
10033 00:41:30.560122 INFO: [APUAPC] D10_APC_3: 0x0
10034 00:41:30.563349 INFO: [APUAPC] D11_APC_0: 0xffffffff
10035 00:41:30.566334 INFO: [APUAPC] D11_APC_1: 0xffffffff
10036 00:41:30.569621 INFO: [APUAPC] D11_APC_2: 0x3fffff
10037 00:41:30.573105 INFO: [APUAPC] D11_APC_3: 0x0
10038 00:41:30.576365 INFO: [APUAPC] D12_APC_0: 0xffffffff
10039 00:41:30.579671 INFO: [APUAPC] D12_APC_1: 0xffffffff
10040 00:41:30.583021 INFO: [APUAPC] D12_APC_2: 0x3fffff
10041 00:41:30.586478 INFO: [APUAPC] D12_APC_3: 0x0
10042 00:41:30.589331 INFO: [APUAPC] D13_APC_0: 0xffffffff
10043 00:41:30.592761 INFO: [APUAPC] D13_APC_1: 0xffffffff
10044 00:41:30.596062 INFO: [APUAPC] D13_APC_2: 0x3fffff
10045 00:41:30.599567 INFO: [APUAPC] D13_APC_3: 0x0
10046 00:41:30.602911 INFO: [APUAPC] D14_APC_0: 0xffffffff
10047 00:41:30.606239 INFO: [APUAPC] D14_APC_1: 0xffffffff
10048 00:41:30.609677 INFO: [APUAPC] D14_APC_2: 0x3fffff
10049 00:41:30.612945 INFO: [APUAPC] D14_APC_3: 0x0
10050 00:41:30.616234 INFO: [APUAPC] D15_APC_0: 0xffffffff
10051 00:41:30.619539 INFO: [APUAPC] D15_APC_1: 0xffffffff
10052 00:41:30.622937 INFO: [APUAPC] D15_APC_2: 0x3fffff
10053 00:41:30.625825 INFO: [APUAPC] D15_APC_3: 0x0
10054 00:41:30.629186 INFO: [APUAPC] APC_CON: 0x4
10055 00:41:30.632592 INFO: [NOCDAPC] D0_APC_0: 0x0
10056 00:41:30.636103 INFO: [NOCDAPC] D0_APC_1: 0x0
10057 00:41:30.636202 INFO: [NOCDAPC] D1_APC_0: 0x0
10058 00:41:30.639394 INFO: [NOCDAPC] D1_APC_1: 0xfff
10059 00:41:30.642676 INFO: [NOCDAPC] D2_APC_0: 0x0
10060 00:41:30.645799 INFO: [NOCDAPC] D2_APC_1: 0xfff
10061 00:41:30.649057 INFO: [NOCDAPC] D3_APC_0: 0x0
10062 00:41:30.652324 INFO: [NOCDAPC] D3_APC_1: 0xfff
10063 00:41:30.655860 INFO: [NOCDAPC] D4_APC_0: 0x0
10064 00:41:30.659252 INFO: [NOCDAPC] D4_APC_1: 0xfff
10065 00:41:30.662376 INFO: [NOCDAPC] D5_APC_0: 0x0
10066 00:41:30.665758 INFO: [NOCDAPC] D5_APC_1: 0xfff
10067 00:41:30.669223 INFO: [NOCDAPC] D6_APC_0: 0x0
10068 00:41:30.669298 INFO: [NOCDAPC] D6_APC_1: 0xfff
10069 00:41:30.672594 INFO: [NOCDAPC] D7_APC_0: 0x0
10070 00:41:30.675633 INFO: [NOCDAPC] D7_APC_1: 0xfff
10071 00:41:30.679122 INFO: [NOCDAPC] D8_APC_0: 0x0
10072 00:41:30.682175 INFO: [NOCDAPC] D8_APC_1: 0xfff
10073 00:41:30.685627 INFO: [NOCDAPC] D9_APC_0: 0x0
10074 00:41:30.688900 INFO: [NOCDAPC] D9_APC_1: 0xfff
10075 00:41:30.692393 INFO: [NOCDAPC] D10_APC_0: 0x0
10076 00:41:30.695841 INFO: [NOCDAPC] D10_APC_1: 0xfff
10077 00:41:30.698629 INFO: [NOCDAPC] D11_APC_0: 0x0
10078 00:41:30.702055 INFO: [NOCDAPC] D11_APC_1: 0xfff
10079 00:41:30.705344 INFO: [NOCDAPC] D12_APC_0: 0x0
10080 00:41:30.708868 INFO: [NOCDAPC] D12_APC_1: 0xfff
10081 00:41:30.708928 INFO: [NOCDAPC] D13_APC_0: 0x0
10082 00:41:30.711769 INFO: [NOCDAPC] D13_APC_1: 0xfff
10083 00:41:30.715115 INFO: [NOCDAPC] D14_APC_0: 0x0
10084 00:41:30.718599 INFO: [NOCDAPC] D14_APC_1: 0xfff
10085 00:41:30.722034 INFO: [NOCDAPC] D15_APC_0: 0x0
10086 00:41:30.725334 INFO: [NOCDAPC] D15_APC_1: 0xfff
10087 00:41:30.728706 INFO: [NOCDAPC] APC_CON: 0x4
10088 00:41:30.731785 INFO: [APUAPC] set_apusys_apc done
10089 00:41:30.735003 INFO: [DEVAPC] devapc_init done
10090 00:41:30.738580 INFO: GICv3 without legacy support detected.
10091 00:41:30.741486 INFO: ARM GICv3 driver initialized in EL3
10092 00:41:30.748524 INFO: Maximum SPI INTID supported: 639
10093 00:41:30.751626 INFO: BL31: Initializing runtime services
10094 00:41:30.758204 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10095 00:41:30.758276 INFO: SPM: enable CPC mode
10096 00:41:30.764962 INFO: mcdi ready for mcusys-off-idle and system suspend
10097 00:41:30.768721 INFO: BL31: Preparing for EL3 exit to normal world
10098 00:41:30.774714 INFO: Entry point address = 0x80000000
10099 00:41:30.774783 INFO: SPSR = 0x8
10100 00:41:30.780970
10101 00:41:30.781035
10102 00:41:30.781089
10103 00:41:30.784104 Starting depthcharge on Spherion...
10104 00:41:30.784166
10105 00:41:30.784219 Wipe memory regions:
10106 00:41:30.784300
10107 00:41:30.784927 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10108 00:41:30.785027 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10109 00:41:30.785102 Setting prompt string to ['asurada:']
10110 00:41:30.785172 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10111 00:41:30.787170 [0x00000040000000, 0x00000054600000)
10112 00:41:30.909550
10113 00:41:30.909681 [0x00000054660000, 0x00000080000000)
10114 00:41:31.170625
10115 00:41:31.170742 [0x000000821a7280, 0x000000ffe64000)
10116 00:41:31.915179
10117 00:41:31.915303 [0x00000100000000, 0x00000240000000)
10118 00:41:33.805525
10119 00:41:33.808565 Initializing XHCI USB controller at 0x11200000.
10120 00:41:34.847105
10121 00:41:34.850338 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10122 00:41:34.850422
10123 00:41:34.850482
10124 00:41:34.850758 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10126 00:41:34.951101 asurada: tftpboot 192.168.201.1 14368360/tftp-deploy-nxziam0o/kernel/image.itb 14368360/tftp-deploy-nxziam0o/kernel/cmdline
10127 00:41:34.951274 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10128 00:41:34.951351 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10129 00:41:34.955326 tftpboot 192.168.201.1 14368360/tftp-deploy-nxziam0o/kernel/image.ittp-deploy-nxziam0o/kernel/cmdline
10130 00:41:34.955405
10131 00:41:34.955466 Waiting for link
10132 00:41:35.113603
10133 00:41:35.113711 R8152: Initializing
10134 00:41:35.113773
10135 00:41:35.116935 Version 6 (ocp_data = 5c30)
10136 00:41:35.117012
10137 00:41:35.119794 R8152: Done initializing
10138 00:41:35.119871
10139 00:41:35.119930 Adding net device
10140 00:41:37.167898
10141 00:41:37.168016 done.
10142 00:41:37.168076
10143 00:41:37.168132 MAC: 00:24:32:30:78:ff
10144 00:41:37.168186
10145 00:41:37.171472 Sending DHCP discover... done.
10146 00:41:37.171550
10147 00:41:37.174962 Waiting for reply... done.
10148 00:41:37.175056
10149 00:41:37.177869 Sending DHCP request... done.
10150 00:41:37.177946
10151 00:41:37.182261 Waiting for reply... done.
10152 00:41:37.182356
10153 00:41:37.182450 My ip is 192.168.201.21
10154 00:41:37.182521
10155 00:41:37.185616 The DHCP server ip is 192.168.201.1
10156 00:41:37.185694
10157 00:41:37.192673 TFTP server IP predefined by user: 192.168.201.1
10158 00:41:37.192783
10159 00:41:37.198924 Bootfile predefined by user: 14368360/tftp-deploy-nxziam0o/kernel/image.itb
10160 00:41:37.199019
10161 00:41:37.199113 Sending tftp read request... done.
10162 00:41:37.202338
10163 00:41:37.206197 Waiting for the transfer...
10164 00:41:37.206290
10165 00:41:37.771586 00000000 ################################################################
10166 00:41:37.771725
10167 00:41:38.347153 00080000 ################################################################
10168 00:41:38.347280
10169 00:41:38.933088 00100000 ################################################################
10170 00:41:38.933213
10171 00:41:39.509623 00180000 ################################################################
10172 00:41:39.509748
10173 00:41:40.075527 00200000 ################################################################
10174 00:41:40.075639
10175 00:41:40.617680 00280000 ################################################################
10176 00:41:40.617792
10177 00:41:41.169800 00300000 ################################################################
10178 00:41:41.169914
10179 00:41:41.740943 00380000 ################################################################
10180 00:41:41.741067
10181 00:41:42.321638 00400000 ################################################################
10182 00:41:42.322172
10183 00:41:42.993352 00480000 ################################################################
10184 00:41:42.993602
10185 00:41:43.674550 00500000 ################################################################
10186 00:41:43.675086
10187 00:41:44.401154 00580000 ################################################################
10188 00:41:44.401676
10189 00:41:45.101336 00600000 ################################################################
10190 00:41:45.101834
10191 00:41:45.747646 00680000 ################################################################
10192 00:41:45.747835
10193 00:41:46.357374 00700000 ################################################################
10194 00:41:46.357487
10195 00:41:46.967606 00780000 ################################################################
10196 00:41:46.967818
10197 00:41:47.672074 00800000 ################################################################
10198 00:41:47.672557
10199 00:41:48.374865 00880000 ################################################################
10200 00:41:48.375395
10201 00:41:49.041460 00900000 ################################################################
10202 00:41:49.041579
10203 00:41:49.609379 00980000 ################################################################
10204 00:41:49.609493
10205 00:41:50.297040 00a00000 ################################################################
10206 00:41:50.297590
10207 00:41:51.013207 00a80000 ################################################################
10208 00:41:51.013737
10209 00:41:51.712419 00b00000 ################################################################
10210 00:41:51.712927
10211 00:41:52.369857 00b80000 ################################################################
10212 00:41:52.370348
10213 00:41:52.978289 00c00000 ################################################################
10214 00:41:52.978426
10215 00:41:53.622790 00c80000 ################################################################
10216 00:41:53.623271
10217 00:41:54.306313 00d00000 ################################################################
10218 00:41:54.306807
10219 00:41:54.974201 00d80000 ################################################################
10220 00:41:54.974342
10221 00:41:55.614450 00e00000 ################################################################
10222 00:41:55.614565
10223 00:41:56.224812 00e80000 ################################################################
10224 00:41:56.225265
10225 00:41:56.828087 00f00000 ################################################################
10226 00:41:56.828230
10227 00:41:57.454656 00f80000 ################################################################
10228 00:41:57.454779
10229 00:41:58.149222 01000000 ################################################################
10230 00:41:58.149365
10231 00:41:58.811267 01080000 ################################################################
10232 00:41:58.811381
10233 00:41:59.375446 01100000 ################################################################
10234 00:41:59.375565
10235 00:41:59.953005 01180000 ################################################################
10236 00:41:59.953124
10237 00:42:00.545156 01200000 ################################################################
10238 00:42:00.545298
10239 00:42:01.180502 01280000 ################################################################
10240 00:42:01.181088
10241 00:42:01.837460 01300000 ################################################################
10242 00:42:01.838065
10243 00:42:02.526777 01380000 ################################################################
10244 00:42:02.527431
10245 00:42:03.204150 01400000 ################################################################
10246 00:42:03.204348
10247 00:42:03.847960 01480000 ################################################################
10248 00:42:03.848075
10249 00:42:04.422904 01500000 ################################################################
10250 00:42:04.423038
10251 00:42:05.111759 01580000 ################################################################
10252 00:42:05.111912
10253 00:42:05.820535 01600000 ################################################################
10254 00:42:05.820709
10255 00:42:06.434554 01680000 ################################################################
10256 00:42:06.434685
10257 00:42:07.059558 01700000 ################################################################
10258 00:42:07.060031
10259 00:42:07.741972 01780000 ################################################################
10260 00:42:07.742100
10261 00:42:08.456217 01800000 ################################################################
10262 00:42:08.456345
10263 00:42:09.109739 01880000 ################################################################
10264 00:42:09.109870
10265 00:42:09.687161 01900000 ################################################################
10266 00:42:09.687293
10267 00:42:10.278807 01980000 ################################################################
10268 00:42:10.278974
10269 00:42:10.892857 01a00000 ################################################################
10270 00:42:10.893016
10271 00:42:11.464070 01a80000 ################################################################
10272 00:42:11.464194
10273 00:42:12.017393 01b00000 ################################################################
10274 00:42:12.017521
10275 00:42:12.670903 01b80000 ################################################################
10276 00:42:12.671425
10277 00:42:13.371323 01c00000 ################################################################
10278 00:42:13.371836
10279 00:42:13.950157 01c80000 ################################################################
10280 00:42:13.950278
10281 00:42:14.494295 01d00000 ################################################################
10282 00:42:14.494443
10283 00:42:15.144889 01d80000 ################################################################
10284 00:42:15.145394
10285 00:42:15.734155 01e00000 ######################################################## done.
10286 00:42:15.734678
10287 00:42:15.736641 The bootfile was 31910930 bytes long.
10288 00:42:15.737130
10289 00:42:15.740226 Sending tftp read request... done.
10290 00:42:15.740708
10291 00:42:15.745361 Waiting for the transfer...
10292 00:42:15.745841
10293 00:42:15.746376 00000000 # done.
10294 00:42:15.746724
10295 00:42:15.752054 Command line loaded dynamically from TFTP file: 14368360/tftp-deploy-nxziam0o/kernel/cmdline
10296 00:42:15.752498
10297 00:42:15.775386 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368360/extract-nfsrootfs-o5lwayju,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10298 00:42:15.775950
10299 00:42:15.776296 Loading FIT.
10300 00:42:15.777915
10301 00:42:15.778289 Image ramdisk-1 has 18735270 bytes.
10302 00:42:15.781284
10303 00:42:15.781723 Image fdt-1 has 47258 bytes.
10304 00:42:15.782069
10305 00:42:15.784673 Image kernel-1 has 13126376 bytes.
10306 00:42:15.785116
10307 00:42:15.795270 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10308 00:42:15.795787
10309 00:42:15.811804 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10310 00:42:15.812332
10311 00:42:15.818098 Choosing best match conf-1 for compat google,spherion-rev2.
10312 00:42:15.821534
10313 00:42:15.826089 Connected to device vid:did:rid of 1ae0:0028:00
10314 00:42:15.832853
10315 00:42:15.836815 tpm_get_response: command 0x17b, return code 0x0
10316 00:42:15.837466
10317 00:42:15.839311 ec_init: CrosEC protocol v3 supported (256, 248)
10318 00:42:15.844189
10319 00:42:15.846793 tpm_cleanup: add release locality here.
10320 00:42:15.847229
10321 00:42:15.847565 Shutting down all USB controllers.
10322 00:42:15.850109
10323 00:42:15.850544 Removing current net device
10324 00:42:15.850888
10325 00:42:15.856951 Exiting depthcharge with code 4 at timestamp: 74421442
10326 00:42:15.857392
10327 00:42:15.860399 LZMA decompressing kernel-1 to 0x821a6718
10328 00:42:15.860874
10329 00:42:15.863832 LZMA decompressing kernel-1 to 0x40000000
10330 00:42:17.480231
10331 00:42:17.480411 jumping to kernel
10332 00:42:17.480975 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10333 00:42:17.481126 start: 2.2.5 auto-login-action (timeout 00:03:40) [common]
10334 00:42:17.481219 Setting prompt string to ['Linux version [0-9]']
10335 00:42:17.481303 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10336 00:42:17.481390 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10337 00:42:17.561793
10338 00:42:17.565265 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10339 00:42:17.568989 start: 2.2.5.1 login-action (timeout 00:03:40) [common]
10340 00:42:17.569147 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10341 00:42:17.569233 Setting prompt string to []
10342 00:42:17.569320 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10343 00:42:17.569399 Using line separator: #'\n'#
10344 00:42:17.569464 No login prompt set.
10345 00:42:17.569529 Parsing kernel messages
10346 00:42:17.569583 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10347 00:42:17.569691 [login-action] Waiting for messages, (timeout 00:03:40)
10348 00:42:17.569760 Waiting using forced prompt support (timeout 00:01:50)
10349 00:42:17.588994 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232175-arm64-gcc-10-defconfig-arm64-chromebook-7lg8d) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024
10350 00:42:17.592181 [ 0.000000] random: crng init done
10351 00:42:17.599096 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10352 00:42:17.602385 [ 0.000000] efi: UEFI not found.
10353 00:42:17.608870 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10354 00:42:17.615039 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10355 00:42:17.625346 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10356 00:42:17.635069 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10357 00:42:17.641848 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10358 00:42:17.648740 [ 0.000000] printk: bootconsole [mtk8250] enabled
10359 00:42:17.655457 [ 0.000000] NUMA: No NUMA configuration found
10360 00:42:17.661820 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10361 00:42:17.665055 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10362 00:42:17.668805 [ 0.000000] Zone ranges:
10363 00:42:17.675328 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10364 00:42:17.678067 [ 0.000000] DMA32 empty
10365 00:42:17.684826 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10366 00:42:17.687825 [ 0.000000] Movable zone start for each node
10367 00:42:17.691292 [ 0.000000] Early memory node ranges
10368 00:42:17.697991 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10369 00:42:17.704748 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10370 00:42:17.711353 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10371 00:42:17.718174 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10372 00:42:17.724732 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10373 00:42:17.731300 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10374 00:42:17.787071 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10375 00:42:17.793953 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10376 00:42:17.800145 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10377 00:42:17.803451 [ 0.000000] psci: probing for conduit method from DT.
10378 00:42:17.810410 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10379 00:42:17.813613 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10380 00:42:17.820113 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10381 00:42:17.823635 [ 0.000000] psci: SMC Calling Convention v1.2
10382 00:42:17.830692 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10383 00:42:17.833538 [ 0.000000] Detected VIPT I-cache on CPU0
10384 00:42:17.840342 [ 0.000000] CPU features: detected: GIC system register CPU interface
10385 00:42:17.846863 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10386 00:42:17.853468 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10387 00:42:17.859936 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10388 00:42:17.866730 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10389 00:42:17.876246 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10390 00:42:17.879923 [ 0.000000] alternatives: applying boot alternatives
10391 00:42:17.886550 [ 0.000000] Fallback order for Node 0: 0
10392 00:42:17.892568 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10393 00:42:17.896050 [ 0.000000] Policy zone: Normal
10394 00:42:17.919090 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368360/extract-nfsrootfs-o5lwayju,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10395 00:42:17.928639 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10396 00:42:17.939128 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10397 00:42:17.949196 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10398 00:42:17.955127 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10399 00:42:17.958782 <6>[ 0.000000] software IO TLB: area num 8.
10400 00:42:18.015441 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10401 00:42:18.164594 <6>[ 0.000000] Memory: 7945764K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407004K reserved, 32768K cma-reserved)
10402 00:42:18.171262 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10403 00:42:18.178005 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10404 00:42:18.181124 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10405 00:42:18.188140 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10406 00:42:18.194398 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10407 00:42:18.197453 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10408 00:42:18.207412 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10409 00:42:18.214354 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10410 00:42:18.220979 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10411 00:42:18.227322 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10412 00:42:18.230689 <6>[ 0.000000] GICv3: 608 SPIs implemented
10413 00:42:18.233962 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10414 00:42:18.240744 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10415 00:42:18.243938 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10416 00:42:18.250516 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10417 00:42:18.264681 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10418 00:42:18.273992 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10419 00:42:18.284255 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10420 00:42:18.291024 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10421 00:42:18.304610 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10422 00:42:18.311185 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10423 00:42:18.317845 <6>[ 0.009187] Console: colour dummy device 80x25
10424 00:42:18.328162 <6>[ 0.013917] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10425 00:42:18.334227 <6>[ 0.024358] pid_max: default: 32768 minimum: 301
10426 00:42:18.337618 <6>[ 0.029229] LSM: Security Framework initializing
10427 00:42:18.344554 <6>[ 0.034183] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10428 00:42:18.354056 <6>[ 0.042046] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10429 00:42:18.364106 <6>[ 0.051469] cblist_init_generic: Setting adjustable number of callback queues.
10430 00:42:18.367850 <6>[ 0.058914] cblist_init_generic: Setting shift to 3 and lim to 1.
10431 00:42:18.377510 <6>[ 0.065253] cblist_init_generic: Setting adjustable number of callback queues.
10432 00:42:18.384323 <6>[ 0.072726] cblist_init_generic: Setting shift to 3 and lim to 1.
10433 00:42:18.387159 <6>[ 0.079115] rcu: Hierarchical SRCU implementation.
10434 00:42:18.393783 <6>[ 0.084161] rcu: Max phase no-delay instances is 1000.
10435 00:42:18.400802 <6>[ 0.091198] EFI services will not be available.
10436 00:42:18.403751 <6>[ 0.096129] smp: Bringing up secondary CPUs ...
10437 00:42:18.412390 <6>[ 0.101180] Detected VIPT I-cache on CPU1
10438 00:42:18.418529 <6>[ 0.101254] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10439 00:42:18.425562 <6>[ 0.101287] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10440 00:42:18.429004 <6>[ 0.101617] Detected VIPT I-cache on CPU2
10441 00:42:18.435409 <6>[ 0.101665] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10442 00:42:18.445655 <6>[ 0.101681] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10443 00:42:18.448619 <6>[ 0.101936] Detected VIPT I-cache on CPU3
10444 00:42:18.455400 <6>[ 0.101982] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10445 00:42:18.461888 <6>[ 0.101996] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10446 00:42:18.464850 <6>[ 0.102298] CPU features: detected: Spectre-v4
10447 00:42:18.471810 <6>[ 0.102304] CPU features: detected: Spectre-BHB
10448 00:42:18.475087 <6>[ 0.102309] Detected PIPT I-cache on CPU4
10449 00:42:18.481615 <6>[ 0.102368] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10450 00:42:18.488576 <6>[ 0.102384] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10451 00:42:18.494935 <6>[ 0.102675] Detected PIPT I-cache on CPU5
10452 00:42:18.501441 <6>[ 0.102738] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10453 00:42:18.508046 <6>[ 0.102754] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10454 00:42:18.511194 <6>[ 0.103034] Detected PIPT I-cache on CPU6
10455 00:42:18.518088 <6>[ 0.103098] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10456 00:42:18.524668 <6>[ 0.103114] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10457 00:42:18.531293 <6>[ 0.103411] Detected PIPT I-cache on CPU7
10458 00:42:18.538100 <6>[ 0.103476] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10459 00:42:18.544911 <6>[ 0.103491] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10460 00:42:18.548271 <6>[ 0.103538] smp: Brought up 1 node, 8 CPUs
10461 00:42:18.554221 <6>[ 0.244875] SMP: Total of 8 processors activated.
10462 00:42:18.557599 <6>[ 0.249797] CPU features: detected: 32-bit EL0 Support
10463 00:42:18.567833 <6>[ 0.255160] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10464 00:42:18.574729 <6>[ 0.263960] CPU features: detected: Common not Private translations
10465 00:42:18.580967 <6>[ 0.270436] CPU features: detected: CRC32 instructions
10466 00:42:18.584776 <6>[ 0.275787] CPU features: detected: RCpc load-acquire (LDAPR)
10467 00:42:18.590958 <6>[ 0.281748] CPU features: detected: LSE atomic instructions
10468 00:42:18.597740 <6>[ 0.287529] CPU features: detected: Privileged Access Never
10469 00:42:18.601242 <6>[ 0.293309] CPU features: detected: RAS Extension Support
10470 00:42:18.611114 <6>[ 0.298952] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10471 00:42:18.614061 <6>[ 0.306171] CPU: All CPU(s) started at EL2
10472 00:42:18.620809 <6>[ 0.310488] alternatives: applying system-wide alternatives
10473 00:42:18.629595 <6>[ 0.321326] devtmpfs: initialized
10474 00:42:18.645577 <6>[ 0.330167] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10475 00:42:18.652109 <6>[ 0.340130] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10476 00:42:18.655488 <6>[ 0.347856] pinctrl core: initialized pinctrl subsystem
10477 00:42:18.663045 <6>[ 0.354538] DMI not present or invalid.
10478 00:42:18.669882 <6>[ 0.358947] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10479 00:42:18.676636 <6>[ 0.365801] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10480 00:42:18.686569 <6>[ 0.373390] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10481 00:42:18.693134 <6>[ 0.381608] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10482 00:42:18.699713 <6>[ 0.389851] audit: initializing netlink subsys (disabled)
10483 00:42:18.706432 <5>[ 0.395542] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10484 00:42:18.712517 <6>[ 0.396272] thermal_sys: Registered thermal governor 'step_wise'
10485 00:42:18.719408 <6>[ 0.403510] thermal_sys: Registered thermal governor 'power_allocator'
10486 00:42:18.726193 <6>[ 0.409764] cpuidle: using governor menu
10487 00:42:18.729399 <6>[ 0.420728] NET: Registered PF_QIPCRTR protocol family
10488 00:42:18.736018 <6>[ 0.426214] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10489 00:42:18.742692 <6>[ 0.433317] ASID allocator initialised with 32768 entries
10490 00:42:18.748754 <6>[ 0.439900] Serial: AMBA PL011 UART driver
10491 00:42:18.757229 <4>[ 0.448759] Trying to register duplicate clock ID: 134
10492 00:42:18.816085 <6>[ 0.510410] KASLR enabled
10493 00:42:18.829773 <6>[ 0.518123] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10494 00:42:18.836557 <6>[ 0.525137] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10495 00:42:18.843304 <6>[ 0.531628] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10496 00:42:18.850042 <6>[ 0.538634] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10497 00:42:18.856327 <6>[ 0.545120] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10498 00:42:18.862869 <6>[ 0.552125] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10499 00:42:18.869427 <6>[ 0.558609] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10500 00:42:18.876165 <6>[ 0.565616] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10501 00:42:18.879968 <6>[ 0.573140] ACPI: Interpreter disabled.
10502 00:42:18.888172 <6>[ 0.579573] iommu: Default domain type: Translated
10503 00:42:18.894971 <6>[ 0.584684] iommu: DMA domain TLB invalidation policy: strict mode
10504 00:42:18.898079 <5>[ 0.591348] SCSI subsystem initialized
10505 00:42:18.904695 <6>[ 0.595514] usbcore: registered new interface driver usbfs
10506 00:42:18.911083 <6>[ 0.601246] usbcore: registered new interface driver hub
10507 00:42:18.914729 <6>[ 0.606798] usbcore: registered new device driver usb
10508 00:42:18.921312 <6>[ 0.612901] pps_core: LinuxPPS API ver. 1 registered
10509 00:42:18.931380 <6>[ 0.618094] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10510 00:42:18.934340 <6>[ 0.627443] PTP clock support registered
10511 00:42:18.937651 <6>[ 0.631685] EDAC MC: Ver: 3.0.0
10512 00:42:18.945383 <6>[ 0.636838] FPGA manager framework
10513 00:42:18.952116 <6>[ 0.640527] Advanced Linux Sound Architecture Driver Initialized.
10514 00:42:18.955395 <6>[ 0.647311] vgaarb: loaded
10515 00:42:18.961882 <6>[ 0.650466] clocksource: Switched to clocksource arch_sys_counter
10516 00:42:18.965383 <5>[ 0.656906] VFS: Disk quotas dquot_6.6.0
10517 00:42:18.971838 <6>[ 0.661092] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10518 00:42:18.975255 <6>[ 0.668281] pnp: PnP ACPI: disabled
10519 00:42:18.983702 <6>[ 0.675012] NET: Registered PF_INET protocol family
10520 00:42:18.993465 <6>[ 0.680607] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10521 00:42:19.005085 <6>[ 0.692930] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10522 00:42:19.014868 <6>[ 0.701745] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10523 00:42:19.021226 <6>[ 0.709719] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10524 00:42:19.030849 <6>[ 0.718419] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10525 00:42:19.037560 <6>[ 0.728174] TCP: Hash tables configured (established 65536 bind 65536)
10526 00:42:19.044275 <6>[ 0.735040] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10527 00:42:19.054326 <6>[ 0.742239] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10528 00:42:19.061315 <6>[ 0.749944] NET: Registered PF_UNIX/PF_LOCAL protocol family
10529 00:42:19.064557 <6>[ 0.756102] RPC: Registered named UNIX socket transport module.
10530 00:42:19.070725 <6>[ 0.762254] RPC: Registered udp transport module.
10531 00:42:19.073763 <6>[ 0.767187] RPC: Registered tcp transport module.
10532 00:42:19.083785 <6>[ 0.772118] RPC: Registered tcp NFSv4.1 backchannel transport module.
10533 00:42:19.087834 <6>[ 0.778785] PCI: CLS 0 bytes, default 64
10534 00:42:19.090275 <6>[ 0.783060] Unpacking initramfs...
10535 00:42:19.114593 <6>[ 0.802573] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10536 00:42:19.124158 <6>[ 0.811227] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10537 00:42:19.127656 <6>[ 0.820083] kvm [1]: IPA Size Limit: 40 bits
10538 00:42:19.134263 <6>[ 0.824614] kvm [1]: GICv3: no GICV resource entry
10539 00:42:19.137487 <6>[ 0.829635] kvm [1]: disabling GICv2 emulation
10540 00:42:19.144074 <6>[ 0.834322] kvm [1]: GIC system register CPU interface enabled
10541 00:42:19.147602 <6>[ 0.840479] kvm [1]: vgic interrupt IRQ18
10542 00:42:19.154121 <6>[ 0.844834] kvm [1]: VHE mode initialized successfully
10543 00:42:19.160702 <5>[ 0.851278] Initialise system trusted keyrings
10544 00:42:19.166713 <6>[ 0.856126] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10545 00:42:19.174569 <6>[ 0.866090] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10546 00:42:19.181288 <5>[ 0.872483] NFS: Registering the id_resolver key type
10547 00:42:19.184380 <5>[ 0.877783] Key type id_resolver registered
10548 00:42:19.191146 <5>[ 0.882199] Key type id_legacy registered
10549 00:42:19.197739 <6>[ 0.886490] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10550 00:42:19.204486 <6>[ 0.893412] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10551 00:42:19.211153 <6>[ 0.901125] 9p: Installing v9fs 9p2000 file system support
10552 00:42:19.247182 <5>[ 0.938330] Key type asymmetric registered
10553 00:42:19.250639 <5>[ 0.942661] Asymmetric key parser 'x509' registered
10554 00:42:19.260134 <6>[ 0.947811] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10555 00:42:19.263485 <6>[ 0.955426] io scheduler mq-deadline registered
10556 00:42:19.266279 <6>[ 0.960205] io scheduler kyber registered
10557 00:42:19.286195 <6>[ 0.977605] EINJ: ACPI disabled.
10558 00:42:19.318944 <4>[ 1.003971] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10559 00:42:19.329282 <4>[ 1.014599] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10560 00:42:19.344215 <6>[ 1.035592] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10561 00:42:19.351826 <6>[ 1.043652] printk: console [ttyS0] disabled
10562 00:42:19.379894 <6>[ 1.068282] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10563 00:42:19.386813 <6>[ 1.077763] printk: console [ttyS0] enabled
10564 00:42:19.390184 <6>[ 1.077763] printk: console [ttyS0] enabled
10565 00:42:19.396481 <6>[ 1.086660] printk: bootconsole [mtk8250] disabled
10566 00:42:19.399878 <6>[ 1.086660] printk: bootconsole [mtk8250] disabled
10567 00:42:19.406332 <6>[ 1.097959] SuperH (H)SCI(F) driver initialized
10568 00:42:19.409781 <6>[ 1.103259] msm_serial: driver initialized
10569 00:42:19.424535 <6>[ 1.112282] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10570 00:42:19.434106 <6>[ 1.120832] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10571 00:42:19.440777 <6>[ 1.129375] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10572 00:42:19.450788 <6>[ 1.138006] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10573 00:42:19.460829 <6>[ 1.146713] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10574 00:42:19.467154 <6>[ 1.155428] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10575 00:42:19.477176 <6>[ 1.163978] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10576 00:42:19.483680 <6>[ 1.172791] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10577 00:42:19.493285 <6>[ 1.181339] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10578 00:42:19.505477 <6>[ 1.197157] loop: module loaded
10579 00:42:19.512169 <6>[ 1.203126] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10580 00:42:19.535406 <4>[ 1.226543] mtk-pmic-keys: Failed to locate of_node [id: -1]
10581 00:42:19.541980 <6>[ 1.233491] megasas: 07.719.03.00-rc1
10582 00:42:19.551553 <6>[ 1.243039] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10583 00:42:19.558515 <6>[ 1.249861] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10584 00:42:19.575469 <6>[ 1.266539] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10585 00:42:19.631741 <6>[ 1.316491] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10586 00:42:19.880023 <6>[ 1.571016] Freeing initrd memory: 18292K
10587 00:42:19.890478 <6>[ 1.582572] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10588 00:42:19.901657 <6>[ 1.593444] tun: Universal TUN/TAP device driver, 1.6
10589 00:42:19.904981 <6>[ 1.599497] thunder_xcv, ver 1.0
10590 00:42:19.908223 <6>[ 1.603011] thunder_bgx, ver 1.0
10591 00:42:19.911998 <6>[ 1.606506] nicpf, ver 1.0
10592 00:42:19.922030 <6>[ 1.610505] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10593 00:42:19.925569 <6>[ 1.617979] hns3: Copyright (c) 2017 Huawei Corporation.
10594 00:42:19.932433 <6>[ 1.623568] hclge is initializing
10595 00:42:19.935584 <6>[ 1.627147] e1000: Intel(R) PRO/1000 Network Driver
10596 00:42:19.942275 <6>[ 1.632276] e1000: Copyright (c) 1999-2006 Intel Corporation.
10597 00:42:19.945604 <6>[ 1.638288] e1000e: Intel(R) PRO/1000 Network Driver
10598 00:42:19.952076 <6>[ 1.643503] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10599 00:42:19.958889 <6>[ 1.649690] igb: Intel(R) Gigabit Ethernet Network Driver
10600 00:42:19.965932 <6>[ 1.655341] igb: Copyright (c) 2007-2014 Intel Corporation.
10601 00:42:19.972167 <6>[ 1.661180] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10602 00:42:19.979073 <6>[ 1.667697] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10603 00:42:19.982033 <6>[ 1.674154] sky2: driver version 1.30
10604 00:42:19.988288 <6>[ 1.679081] usbcore: registered new device driver r8152-cfgselector
10605 00:42:19.995248 <6>[ 1.685615] usbcore: registered new interface driver r8152
10606 00:42:20.002188 <6>[ 1.691426] VFIO - User Level meta-driver version: 0.3
10607 00:42:20.008434 <6>[ 1.699645] usbcore: registered new interface driver usb-storage
10608 00:42:20.015126 <6>[ 1.706086] usbcore: registered new device driver onboard-usb-hub
10609 00:42:20.023449 <6>[ 1.715239] mt6397-rtc mt6359-rtc: registered as rtc0
10610 00:42:20.033898 <6>[ 1.720715] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:42:19 UTC (1718498539)
10611 00:42:20.037155 <6>[ 1.730312] i2c_dev: i2c /dev entries driver
10612 00:42:20.051190 <4>[ 1.742365] cpu cpu0: supply cpu not found, using dummy regulator
10613 00:42:20.057615 <4>[ 1.748797] cpu cpu1: supply cpu not found, using dummy regulator
10614 00:42:20.064160 <4>[ 1.755197] cpu cpu2: supply cpu not found, using dummy regulator
10615 00:42:20.070872 <4>[ 1.761613] cpu cpu3: supply cpu not found, using dummy regulator
10616 00:42:20.077136 <4>[ 1.768009] cpu cpu4: supply cpu not found, using dummy regulator
10617 00:42:20.084003 <4>[ 1.774404] cpu cpu5: supply cpu not found, using dummy regulator
10618 00:42:20.090702 <4>[ 1.780814] cpu cpu6: supply cpu not found, using dummy regulator
10619 00:42:20.097442 <4>[ 1.787207] cpu cpu7: supply cpu not found, using dummy regulator
10620 00:42:20.116509 <6>[ 1.807868] cpu cpu0: EM: created perf domain
10621 00:42:20.119884 <6>[ 1.812809] cpu cpu4: EM: created perf domain
10622 00:42:20.127069 <6>[ 1.818386] sdhci: Secure Digital Host Controller Interface driver
10623 00:42:20.133382 <6>[ 1.824818] sdhci: Copyright(c) Pierre Ossman
10624 00:42:20.140154 <6>[ 1.829778] Synopsys Designware Multimedia Card Interface Driver
10625 00:42:20.147288 <6>[ 1.836417] sdhci-pltfm: SDHCI platform and OF driver helper
10626 00:42:20.150529 <6>[ 1.836477] mmc0: CQHCI version 5.10
10627 00:42:20.157070 <6>[ 1.846537] ledtrig-cpu: registered to indicate activity on CPUs
10628 00:42:20.163556 <6>[ 1.853545] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10629 00:42:20.170505 <6>[ 1.860604] usbcore: registered new interface driver usbhid
10630 00:42:20.173477 <6>[ 1.866425] usbhid: USB HID core driver
10631 00:42:20.180065 <6>[ 1.870623] spi_master spi0: will run message pump with realtime priority
10632 00:42:20.227706 <6>[ 1.912705] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10633 00:42:20.246304 <6>[ 1.927713] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10634 00:42:20.249049 <6>[ 1.940318] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10635 00:42:20.257403 <6>[ 1.948738] cros-ec-spi spi0.0: Chrome EC device registered
10636 00:42:20.263926 <6>[ 1.954737] mmc0: Command Queue Engine enabled
10637 00:42:20.271171 <6>[ 1.959492] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10638 00:42:20.273709 <6>[ 1.967363] mmcblk0: mmc0:0001 DA4128 116 GiB
10639 00:42:20.285117 <6>[ 1.976398] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10640 00:42:20.292455 <6>[ 1.983764] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10641 00:42:20.299076 <6>[ 1.989705] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10642 00:42:20.308801 <6>[ 1.994711] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10643 00:42:20.315349 <6>[ 1.995840] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10644 00:42:20.318420 <6>[ 2.005600] NET: Registered PF_PACKET protocol family
10645 00:42:20.325305 <6>[ 2.016200] 9pnet: Installing 9P2000 support
10646 00:42:20.328915 <5>[ 2.020778] Key type dns_resolver registered
10647 00:42:20.332352 <6>[ 2.025869] registered taskstats version 1
10648 00:42:20.338661 <5>[ 2.030295] Loading compiled-in X.509 certificates
10649 00:42:20.368844 <4>[ 2.053676] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10650 00:42:20.378320 <4>[ 2.064494] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10651 00:42:20.393154 <6>[ 2.084629] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10652 00:42:20.400146 <6>[ 2.091605] xhci-mtk 11200000.usb: xHCI Host Controller
10653 00:42:20.406755 <6>[ 2.097111] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10654 00:42:20.417034 <6>[ 2.104966] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10655 00:42:20.423313 <6>[ 2.114417] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10656 00:42:20.430152 <6>[ 2.120514] xhci-mtk 11200000.usb: xHCI Host Controller
10657 00:42:20.436791 <6>[ 2.125999] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10658 00:42:20.443275 <6>[ 2.133746] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10659 00:42:20.449779 <6>[ 2.141573] hub 1-0:1.0: USB hub found
10660 00:42:20.453552 <6>[ 2.145608] hub 1-0:1.0: 1 port detected
10661 00:42:20.463356 <6>[ 2.149905] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10662 00:42:20.466391 <6>[ 2.158673] hub 2-0:1.0: USB hub found
10663 00:42:20.470069 <6>[ 2.162694] hub 2-0:1.0: 1 port detected
10664 00:42:20.477542 <6>[ 2.169354] mtk-msdc 11f70000.mmc: Got CD GPIO
10665 00:42:20.489461 <6>[ 2.177780] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10666 00:42:20.499316 <6>[ 2.186150] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10667 00:42:20.505857 <6>[ 2.194492] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10668 00:42:20.515786 <6>[ 2.202835] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10669 00:42:20.522255 <6>[ 2.211174] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10670 00:42:20.532190 <6>[ 2.219515] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10671 00:42:20.539245 <6>[ 2.227853] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10672 00:42:20.549218 <6>[ 2.236190] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10673 00:42:20.555538 <6>[ 2.244528] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10674 00:42:20.565320 <6>[ 2.252873] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10675 00:42:20.572425 <6>[ 2.261211] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10676 00:42:20.582091 <6>[ 2.269549] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10677 00:42:20.588904 <6>[ 2.277889] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10678 00:42:20.599051 <6>[ 2.286227] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10679 00:42:20.605292 <6>[ 2.294566] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10680 00:42:20.612259 <6>[ 2.303260] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10681 00:42:20.619200 <6>[ 2.310449] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10682 00:42:20.625637 <6>[ 2.317229] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10683 00:42:20.635496 <6>[ 2.323996] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10684 00:42:20.642345 <6>[ 2.330927] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10685 00:42:20.649071 <6>[ 2.337779] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10686 00:42:20.658805 <6>[ 2.346911] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10687 00:42:20.668862 <6>[ 2.356034] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10688 00:42:20.678802 <6>[ 2.365329] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10689 00:42:20.688730 <6>[ 2.374796] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10690 00:42:20.694935 <6>[ 2.384263] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10691 00:42:20.705081 <6>[ 2.393383] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10692 00:42:20.714932 <6>[ 2.402850] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10693 00:42:20.724846 <6>[ 2.411969] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10694 00:42:20.734827 <6>[ 2.421263] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10695 00:42:20.744788 <6>[ 2.431423] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10696 00:42:20.754500 <6>[ 2.442820] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10697 00:42:20.762429 <6>[ 2.453947] Trying to probe devices needed for running init ...
10698 00:42:20.772846 <3>[ 2.461202] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10699 00:42:20.870983 <6>[ 2.558756] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10700 00:42:21.024217 <6>[ 2.715529] hub 1-1:1.0: USB hub found
10701 00:42:21.027041 <6>[ 2.719925] hub 1-1:1.0: 4 ports detected
10702 00:42:21.036095 <6>[ 2.728117] hub 1-1:1.0: USB hub found
10703 00:42:21.040155 <6>[ 2.732454] hub 1-1:1.0: 4 ports detected
10704 00:42:21.150958 <6>[ 2.838930] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10705 00:42:21.176397 <6>[ 2.867741] hub 2-1:1.0: USB hub found
10706 00:42:21.179405 <6>[ 2.872150] hub 2-1:1.0: 3 ports detected
10707 00:42:21.191470 <6>[ 2.882631] hub 2-1:1.0: USB hub found
10708 00:42:21.193984 <6>[ 2.887109] hub 2-1:1.0: 3 ports detected
10709 00:42:21.362471 <6>[ 3.050785] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10710 00:42:21.495085 <6>[ 3.186546] hub 1-1.4:1.0: USB hub found
10711 00:42:21.497929 <6>[ 3.191197] hub 1-1.4:1.0: 2 ports detected
10712 00:42:21.510017 <6>[ 3.201863] hub 1-1.4:1.0: USB hub found
10713 00:42:21.513640 <6>[ 3.206375] hub 1-1.4:1.0: 2 ports detected
10714 00:42:21.582208 <6>[ 3.270868] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10715 00:42:21.690985 <6>[ 3.379411] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10716 00:42:21.727373 <4>[ 3.415386] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10717 00:42:21.736606 <4>[ 3.424480] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10718 00:42:21.772365 <6>[ 3.464317] r8152 2-1.3:1.0 eth0: v1.12.13
10719 00:42:21.810444 <6>[ 3.498785] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10720 00:42:22.002130 <6>[ 3.690783] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10721 00:42:23.379896 <6>[ 5.071698] r8152 2-1.3:1.0 eth0: carrier on
10722 00:42:25.762856 <5>[ 5.102577] Sending DHCP requests .., OK
10723 00:42:25.768893 <6>[ 7.458925] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10724 00:42:25.772676 <6>[ 7.467215] IP-Config: Complete:
10725 00:42:25.785786 <6>[ 7.470714] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10726 00:42:25.792896 <6>[ 7.481420] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10727 00:42:25.798840 <6>[ 7.490036] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10728 00:42:25.805588 <6>[ 7.490045] nameserver0=192.168.201.1
10729 00:42:25.808939 <6>[ 7.502193] clk: Disabling unused clocks
10730 00:42:25.812438 <6>[ 7.507705] ALSA device list:
10731 00:42:25.818725 <6>[ 7.510971] No soundcards found.
10732 00:42:25.825952 <6>[ 7.518185] Freeing unused kernel memory: 8512K
10733 00:42:25.829519 <6>[ 7.523115] Run /init as init process
10734 00:42:25.838798 Loading, please wait...
10735 00:42:25.866878 Starting systemd-udevd version 252.22-1~deb12u1
10736 00:42:26.104248 <6>[ 7.793278] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10737 00:42:26.115104 <6>[ 7.804182] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10738 00:42:26.128218 <6>[ 7.817325] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10739 00:42:26.149454 <3>[ 7.837770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 00:42:26.156167 <6>[ 7.838014] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10741 00:42:26.165838 <3>[ 7.846160] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 00:42:26.172349 <6>[ 7.852852] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10743 00:42:26.179206 <6>[ 7.854827] mc: Linux media interface: v0.10
10744 00:42:26.185167 <6>[ 7.856896] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10745 00:42:26.192245 <6>[ 7.857643] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10746 00:42:26.199214 <6>[ 7.857648] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10747 00:42:26.208326 <4>[ 7.857817] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10748 00:42:26.218297 <6>[ 7.858451] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10749 00:42:26.225303 <6>[ 7.858633] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10750 00:42:26.235285 <6>[ 7.858895] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10751 00:42:26.242138 <6>[ 7.858907] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10752 00:42:26.248562 <6>[ 7.858911] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10753 00:42:26.258048 <6>[ 7.858917] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10754 00:42:26.264717 <6>[ 7.859678] remoteproc remoteproc0: scp is available
10755 00:42:26.268316 <6>[ 7.859726] remoteproc remoteproc0: powering up scp
10756 00:42:26.278554 <6>[ 7.859731] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10757 00:42:26.281763 <6>[ 7.859742] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10758 00:42:26.291179 <3>[ 7.862166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 00:42:26.297955 <3>[ 7.862270] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 00:42:26.304378 <4>[ 7.864700] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10761 00:42:26.314477 <4>[ 7.864890] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10762 00:42:26.317840 <6>[ 7.898698] videodev: Linux video capture interface: v2.00
10763 00:42:26.327897 <3>[ 7.906712] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 00:42:26.334842 <3>[ 7.906792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 00:42:26.340953 <6>[ 7.948594] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10766 00:42:26.351030 <3>[ 7.955463] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10767 00:42:26.357540 <6>[ 7.960668] pci_bus 0000:00: root bus resource [bus 00-ff]
10768 00:42:26.364205 <3>[ 7.965819] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10769 00:42:26.371196 <6>[ 7.974448] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10770 00:42:26.380723 <3>[ 7.979939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 00:42:26.387724 <6>[ 7.983110] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10772 00:42:26.397554 <6>[ 7.985419] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10773 00:42:26.403619 <6>[ 7.985451] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10774 00:42:26.410277 <6>[ 7.985459] remoteproc remoteproc0: remote processor scp is now up
10775 00:42:26.420567 <6>[ 7.987515] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10776 00:42:26.430756 <6>[ 7.987791] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10777 00:42:26.440947 <6>[ 8.010967] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10778 00:42:26.447175 <6>[ 8.015089] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10779 00:42:26.457191 <3>[ 8.016727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 00:42:26.463558 <6>[ 8.021500] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10781 00:42:26.470206 <6>[ 8.024601] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10782 00:42:26.480391 <3>[ 8.032669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 00:42:26.483289 <6>[ 8.033193] Bluetooth: Core ver 2.22
10784 00:42:26.486768 <6>[ 8.033263] NET: Registered PF_BLUETOOTH protocol family
10785 00:42:26.493289 <6>[ 8.033266] Bluetooth: HCI device and connection manager initialized
10786 00:42:26.499734 <6>[ 8.033293] Bluetooth: HCI socket layer initialized
10787 00:42:26.502980 <6>[ 8.033318] Bluetooth: L2CAP socket layer initialized
10788 00:42:26.509657 <6>[ 8.033356] Bluetooth: SCO socket layer initialized
10789 00:42:26.516464 <6>[ 8.039552] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10790 00:42:26.526425 <3>[ 8.047625] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 00:42:26.533231 <6>[ 8.048828] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10792 00:42:26.546778 <6>[ 8.050117] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10793 00:42:26.550106 <6>[ 8.050305] usbcore: registered new interface driver uvcvideo
10794 00:42:26.556224 <6>[ 8.053422] pci 0000:00:00.0: supports D1 D2
10795 00:42:26.563220 <3>[ 8.061458] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 00:42:26.569469 <6>[ 8.068535] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10797 00:42:26.579351 <3>[ 8.076633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 00:42:26.586245 <6>[ 8.087311] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10799 00:42:26.592396 <6>[ 8.087455] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10800 00:42:26.602374 <3>[ 8.092954] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10801 00:42:26.608704 <6>[ 8.101571] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10802 00:42:26.612100 <6>[ 8.101957] usbcore: registered new interface driver btusb
10803 00:42:26.621979 <4>[ 8.103006] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10804 00:42:26.628898 <3>[ 8.103018] Bluetooth: hci0: Failed to load firmware file (-2)
10805 00:42:26.635304 <3>[ 8.103022] Bluetooth: hci0: Failed to set up firmware (-2)
10806 00:42:26.645559 <4>[ 8.103027] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10807 00:42:26.655218 <3>[ 8.107899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10808 00:42:26.662046 <6>[ 8.118007] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10809 00:42:26.668273 <3>[ 8.127000] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10810 00:42:26.678441 <6>[ 8.136910] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10811 00:42:26.685031 <3>[ 8.145165] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10812 00:42:26.691838 <6>[ 8.153229] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10813 00:42:26.698600 <6>[ 8.390355] pci 0000:01:00.0: supports D1 D2
10814 00:42:26.705141 <6>[ 8.394910] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10815 00:42:26.716176 <4>[ 8.405118] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10816 00:42:26.722572 <4>[ 8.405118] Fallback method does not support PEC.
10817 00:42:26.729375 <6>[ 8.410608] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10818 00:42:26.736731 <6>[ 8.425642] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10819 00:42:26.743054 <6>[ 8.433722] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10820 00:42:26.753172 <3>[ 8.434246] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10821 00:42:26.759749 <6>[ 8.441717] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10822 00:42:26.769870 <6>[ 8.458484] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10823 00:42:26.776588 <6>[ 8.466485] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10824 00:42:26.787214 <3>[ 8.473815] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10825 00:42:26.790109 <6>[ 8.474485] pci 0000:00:00.0: PCI bridge to [bus 01]
10826 00:42:26.800441 <6>[ 8.488465] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10827 00:42:26.806365 <6>[ 8.496596] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10828 00:42:26.812981 <6>[ 8.503439] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10829 00:42:26.819620 <6>[ 8.509801] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10830 00:42:26.839818 <5>[ 8.528774] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10831 00:42:26.861037 <5>[ 8.549689] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10832 00:42:26.867211 <5>[ 8.557675] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10833 00:42:26.877570 <4>[ 8.566303] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10834 00:42:26.883680 <6>[ 8.575230] cfg80211: failed to load regulatory.db
10835 00:42:26.942967 <6>[ 8.631847] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10836 00:42:26.949429 <6>[ 8.639418] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10837 00:42:26.973976 <6>[ 8.666269] mt7921e 0000:01:00.0: ASIC revision: 79610010
10838 00:42:27.078227 <6>[ 8.767255] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10839 00:42:27.081331 <6>[ 8.767255]
10840 00:42:27.084794 Begin: Loading essential drivers ... done.
10841 00:42:27.088325 Begin: Running /scripts/init-premount ... done.
10842 00:42:27.094848 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10843 00:42:27.105085 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10844 00:42:27.107928 Device /sys/class/net/eth0 found
10845 00:42:27.108394 done.
10846 00:42:27.114955 Begin: Waiting up to 180 secs for any network device to become available ... done.
10847 00:42:27.178193 IP-Config: eth0 hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10848 00:42:27.187416 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10849 00:42:27.193396 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10850 00:42:27.200323 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10851 00:42:27.206405 host : mt8192-asurada-spherion-r0-cbg-8
10852 00:42:27.212998 domain : lava-rack
10853 00:42:27.216824 rootserver: 192.168.201.1 rootpath:
10854 00:42:27.220000 filename :
10855 00:42:27.242737 done.
10856 00:42:27.252609 Begin: Running /scripts/nfs-bottom ... done.
10857 00:42:27.277585 Begin: Running /scripts/init-bottom ... done.
10858 00:42:27.345360 <6>[ 9.034107] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10859 00:42:28.666183 <6>[ 10.359051] NET: Registered PF_INET6 protocol family
10860 00:42:28.673250 <6>[ 10.366111] Segment Routing with IPv6
10861 00:42:28.676695 <6>[ 10.370059] In-situ OAM (IOAM) with IPv6
10862 00:42:28.861886 <30>[ 10.528158] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10863 00:42:28.868898 <30>[ 10.561315] systemd[1]: Detected architecture arm64.
10864 00:42:28.879776
10865 00:42:28.882790 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10866 00:42:28.883238
10867 00:42:28.908374 <30>[ 10.601172] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10868 00:42:30.114519 <30>[ 11.804051] systemd[1]: Queued start job for default target graphical.target.
10869 00:42:30.149501 <30>[ 11.839216] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10870 00:42:30.156579 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10871 00:42:30.175026 <30>[ 11.864313] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10872 00:42:30.184787 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10873 00:42:30.203264 <30>[ 11.892340] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10874 00:42:30.212613 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10875 00:42:30.230517 <30>[ 11.919952] systemd[1]: Created slice user.slice - User and Session Slice.
10876 00:42:30.237014 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10877 00:42:30.256609 <30>[ 11.942985] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10878 00:42:30.263597 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10879 00:42:30.284780 <30>[ 11.970925] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10880 00:42:30.291329 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10881 00:42:30.319517 <30>[ 11.999360] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10882 00:42:30.329950 <30>[ 12.019228] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10883 00:42:30.336294 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10884 00:42:30.353217 <30>[ 12.042726] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10885 00:42:30.360000 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10886 00:42:30.377437 <30>[ 12.066784] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10887 00:42:30.387259 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10888 00:42:30.402370 <30>[ 12.094826] systemd[1]: Reached target paths.target - Path Units.
10889 00:42:30.411985 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10890 00:42:30.429185 <30>[ 12.118876] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10891 00:42:30.436234 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10892 00:42:30.449666 <30>[ 12.142736] systemd[1]: Reached target slices.target - Slice Units.
10893 00:42:30.460435 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10894 00:42:30.474794 <30>[ 12.167260] systemd[1]: Reached target swap.target - Swaps.
10895 00:42:30.481442 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10896 00:42:30.502036 <30>[ 12.191252] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10897 00:42:30.511450 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10898 00:42:30.529919 <30>[ 12.219234] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10899 00:42:30.539394 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10900 00:42:30.560524 <30>[ 12.249774] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10901 00:42:30.570133 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10902 00:42:30.587321 <30>[ 12.276484] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10903 00:42:30.597055 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10904 00:42:30.613762 <30>[ 12.303453] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10905 00:42:30.620533 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10906 00:42:30.639256 <30>[ 12.328675] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10907 00:42:30.648841 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10908 00:42:30.670492 <30>[ 12.359624] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10909 00:42:30.679984 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10910 00:42:30.697918 <30>[ 12.387255] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10911 00:42:30.707525 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10912 00:42:30.765115 <30>[ 12.454973] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10913 00:42:30.771805 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10914 00:42:30.794423 <30>[ 12.483811] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10915 00:42:30.800427 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10916 00:42:30.825389 <30>[ 12.514859] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10917 00:42:30.832224 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10918 00:42:30.860075 <30>[ 12.543280] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10919 00:42:30.893907 <30>[ 12.583253] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10920 00:42:30.903402 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10921 00:42:30.926750 <30>[ 12.616493] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10922 00:42:30.933860 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10923 00:42:30.957920 <30>[ 12.647151] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10924 00:42:30.967378 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10925 00:42:30.990954 <30>[ 12.680234] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10926 00:42:30.997432 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10927 00:42:31.007661 <6>[ 12.696625] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10928 00:42:31.022362 <30>[ 12.711856] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10929 00:42:31.031854 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10930 00:42:31.077781 <30>[ 12.767360] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10931 00:42:31.084520 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10932 00:42:31.110757 <30>[ 12.800431] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10933 00:42:31.117191 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10934 00:42:31.133240 <6>[ 12.826366] fuse: init (API version 7.37)
10935 00:42:31.151026 <30>[ 12.840462] systemd[1]: Starting systemd-journald.service - Journal Service...
10936 00:42:31.157559 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10937 00:42:31.197972 <30>[ 12.887585] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10938 00:42:31.204248 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10939 00:42:31.232050 <30>[ 12.918622] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10940 00:42:31.238756 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10941 00:42:31.261119 <30>[ 12.950623] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10942 00:42:31.271026 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10943 00:42:31.318338 <30>[ 13.007846] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10944 00:42:31.325012 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10945 00:42:31.340489 <3>[ 13.029864] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 00:42:31.358164 <30>[ 13.047068] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10947 00:42:31.371151 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - H<3>[ 13.059636] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 00:42:31.374371 uge Pages File System.
10949 00:42:31.389893 <30>[ 13.079238] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10950 00:42:31.396553 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10951 00:42:31.407975 <3>[ 13.097836] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 00:42:31.418217 <30>[ 13.107226] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10953 00:42:31.424549 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10954 00:42:31.439890 <3>[ 13.129697] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 00:42:31.450530 <30>[ 13.140236] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10956 00:42:31.460764 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10957 00:42:31.470612 <3>[ 13.160158] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 00:42:31.481371 <30>[ 13.171014] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10959 00:42:31.491738 <30>[ 13.179572] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10960 00:42:31.498751 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10961 00:42:31.508785 <3>[ 13.195352] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 00:42:31.515204 <30>[ 13.207475] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10963 00:42:31.525834 <30>[ 13.215579] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10964 00:42:31.532976 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10965 00:42:31.543297 <3>[ 13.232789] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 00:42:31.553890 <30>[ 13.243846] systemd[1]: modprobe@drm.service: Deactivated successfully.
10967 00:42:31.561253 <30>[ 13.251478] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10968 00:42:31.577573 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Mod<3>[ 13.265147] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 00:42:31.578047 ule drm.
10970 00:42:31.599492 <30>[ 13.289155] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10971 00:42:31.610316 <30>[ 13.297623] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10972 00:42:31.616604 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10973 00:42:31.634972 <30>[ 13.324744] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10974 00:42:31.642157 <30>[ 13.332971] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10975 00:42:31.651913 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10976 00:42:31.670233 <30>[ 13.359534] systemd[1]: Started systemd-journald.service - Journal Service.
10977 00:42:31.676812 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10978 00:42:31.698312 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10979 00:42:31.718803 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10980 00:42:31.739558 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10981 00:42:31.763032 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount R<4>[ 13.453523] power_supply_show_property: 2 callbacks suppressed
10982 00:42:31.773176 oot and Kernel F<3>[ 13.453533] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 00:42:31.773689 ile Systems.
10984 00:42:31.790240 <4>[ 13.470424] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10985 00:42:31.797218 <3>[ 13.484195] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 00:42:31.807309 <3>[ 13.487345] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10987 00:42:31.813980 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10988 00:42:31.841068 <3>[ 13.530833] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 00:42:31.873675 Mounting [0;1;39msys-fs-fuse-conne…<3>[ 13.563332] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 00:42:31.876835 [0m - FUSE Control File System...
10991 00:42:31.906147 Mounting [0;1;39msys-kernel-config…e<3>[ 13.595720] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 00:42:31.909530 rnel Configuration File System...
10993 00:42:31.938682 Starting [0;1;39msystemd-journal-f…h<3>[ 13.627306] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 00:42:31.941752 Journal to Persistent Storage...
10995 00:42:31.969450 <3>[ 13.658954] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 00:42:31.992053 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10997 00:42:32.001824 <3>[ 13.691152] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 00:42:32.022900 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10999 00:42:32.033096 <3>[ 13.722991] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 00:42:32.056131 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11001 00:42:32.066322 <3>[ 13.755384] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11002 00:42:32.100179 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11003 00:42:32.122197 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse<46>[ 13.812635] systemd-journald[311]: Received client request to flush runtime journal.
11004 00:42:32.125789 -connec…nt[0m - FUSE Control File System.
11005 00:42:32.149399 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11006 00:42:32.166954 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11007 00:42:32.191337 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11008 00:42:32.210462 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11009 00:42:32.265632 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11010 00:42:33.547355 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11011 00:42:33.596055 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11012 00:42:33.617655 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11013 00:42:33.633339 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11014 00:42:33.706035 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11015 00:42:33.729118 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11016 00:42:34.034547 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11017 00:42:34.094892 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11018 00:42:34.163126 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11019 00:42:34.419838 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11020 00:42:34.474030 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11021 00:42:34.501694 <6>[ 16.195082] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11022 00:42:34.533945 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11023 00:42:34.617544 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11024 00:42:34.637024 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11025 00:42:34.701309 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11026 00:42:34.728555 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11027 00:42:34.750213 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11028 00:42:34.774157 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11029 00:42:34.821509 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11030 00:42:34.882079 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11031 00:42:34.924593 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11032 00:42:34.941554 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11033 00:42:34.965592 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11034 00:42:34.990464 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11035 00:42:35.010019 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11036 00:42:35.030786 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11037 00:42:35.066934 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11038 00:42:35.089237 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11039 00:42:35.105354 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11040 00:42:35.129527 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11041 00:42:35.149232 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11042 00:42:35.169345 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11043 00:42:35.187843 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11044 00:42:35.205341 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11045 00:42:35.222272 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11046 00:42:35.262824 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11047 00:42:35.301716 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11048 00:42:35.412476 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11049 00:42:35.438690 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11050 00:42:35.486323 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11051 00:42:35.532939 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11052 00:42:35.589528 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11053 00:42:35.609003 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11054 00:42:35.629696 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11055 00:42:35.666641 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11056 00:42:35.761179 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11057 00:42:35.780541 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11058 00:42:35.797497 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11059 00:42:35.842686 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11060 00:42:35.895971 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11061 00:42:35.974730
11062 00:42:35.978066 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11063 00:42:35.978148
11064 00:42:35.981378 debian-bookworm-arm64 login: root (automatic login)
11065 00:42:35.981466
11066 00:42:36.325359 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024 aarch64
11067 00:42:36.325812
11068 00:42:36.332067 The programs included with the Debian GNU/Linux system are free software;
11069 00:42:36.338404 the exact distribution terms for each program are described in the
11070 00:42:36.341640 individual files in /usr/share/doc/*/copyright.
11071 00:42:36.342039
11072 00:42:36.348515 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11073 00:42:36.351691 permitted by applicable law.
11074 00:42:37.497718 Matched prompt #10: / #
11076 00:42:37.497977 Setting prompt string to ['/ #']
11077 00:42:37.498068 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11079 00:42:37.498292 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11080 00:42:37.498375 start: 2.2.6 expect-shell-connection (timeout 00:03:20) [common]
11081 00:42:37.498442 Setting prompt string to ['/ #']
11082 00:42:37.498504 Forcing a shell prompt, looking for ['/ #']
11084 00:42:37.548684 / #
11085 00:42:37.548947 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11086 00:42:37.549065 Waiting using forced prompt support (timeout 00:02:30)
11087 00:42:37.553578
11088 00:42:37.553959 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11089 00:42:37.554160 start: 2.2.7 export-device-env (timeout 00:03:20) [common]
11091 00:42:37.654874 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368360/extract-nfsrootfs-o5lwayju'
11092 00:42:37.661513 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368360/extract-nfsrootfs-o5lwayju'
11094 00:42:37.763234 / # export NFS_SERVER_IP='192.168.201.1'
11095 00:42:37.769638 export NFS_SERVER_IP='192.168.201.1'
11096 00:42:37.770524 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11097 00:42:37.771009 end: 2.2 depthcharge-retry (duration 00:01:40) [common]
11098 00:42:37.771499 end: 2 depthcharge-action (duration 00:01:40) [common]
11099 00:42:37.771967 start: 3 lava-test-retry (timeout 00:07:41) [common]
11100 00:42:37.772424 start: 3.1 lava-test-shell (timeout 00:07:41) [common]
11101 00:42:37.772850 Using namespace: common
11103 00:42:37.873964 / # #
11104 00:42:37.874676 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11105 00:42:37.880357 #
11106 00:42:37.881126 Using /lava-14368360
11108 00:42:37.982177 / # export SHELL=/bin/bash
11109 00:42:37.988880 export SHELL=/bin/bash
11111 00:42:38.090628 / # . /lava-14368360/environment
11112 00:42:38.097442 . /lava-14368360/environment
11114 00:42:38.206377 / # /lava-14368360/bin/lava-test-runner /lava-14368360/0
11115 00:42:38.207029 Test shell timeout: 10s (minimum of the action and connection timeout)
11116 00:42:38.212591 /lava-14368360/bin/lava-test-runner /lava-14368360/0
11117 00:42:38.537793 + export TESTRUN_ID=0_timesync-off
11118 00:42:38.541026 + TESTRUN_ID=0_timesync-off
11119 00:42:38.543866 + cd /lava-14368360/0/tests/0_timesync-off
11120 00:42:38.547191 ++ cat uuid
11121 00:42:38.558858 + UUID=14368360_1.6.2.3.1
11122 00:42:38.559260 + set +x
11123 00:42:38.565692 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14368360_1.6.2.3.1>
11124 00:42:38.566373 Received signal: <STARTRUN> 0_timesync-off 14368360_1.6.2.3.1
11125 00:42:38.566726 Starting test lava.0_timesync-off (14368360_1.6.2.3.1)
11126 00:42:38.567116 Skipping test definition patterns.
11127 00:42:38.569088 + systemctl stop systemd-timesyncd
11128 00:42:38.644096 + set +x
11129 00:42:38.647706 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14368360_1.6.2.3.1>
11130 00:42:38.648403 Received signal: <ENDRUN> 0_timesync-off 14368360_1.6.2.3.1
11131 00:42:38.648939 Ending use of test pattern.
11132 00:42:38.649249 Ending test lava.0_timesync-off (14368360_1.6.2.3.1), duration 0.08
11134 00:42:38.742162 + export TESTRUN_ID=1_kselftest-dt
11135 00:42:38.745894 + TESTRUN_ID=1_kselftest-dt
11136 00:42:38.748915 + cd /lava-14368360/0/tests/1_kselftest-dt
11137 00:42:38.752087 ++ cat uuid
11138 00:42:38.760596 + UUID=14368360_1.6.2.3.5
11139 00:42:38.760714 + set +x
11140 00:42:38.767395 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 14368360_1.6.2.3.5>
11141 00:42:38.767648 Received signal: <STARTRUN> 1_kselftest-dt 14368360_1.6.2.3.5
11142 00:42:38.767720 Starting test lava.1_kselftest-dt (14368360_1.6.2.3.5)
11143 00:42:38.767808 Skipping test definition patterns.
11144 00:42:38.771027 + cd ./automated/linux/kselftest/
11145 00:42:38.796829 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11146 00:42:38.855344 INFO: install_deps skipped
11147 00:42:39.379478 --2024-06-16 00:42:39-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11148 00:42:39.390255 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11149 00:42:39.519170 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11150 00:42:39.648098 HTTP request sent, awaiting response... 200 OK
11151 00:42:39.651442 Length: 1647580 (1.6M) [application/octet-stream]
11152 00:42:39.654709 Saving to: 'kselftest_armhf.tar.gz'
11153 00:42:39.655107
11154 00:42:39.655415
11155 00:42:39.903834 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11156 00:42:40.160106 kselftest_armhf.tar 2%[ ] 47.81K 187KB/s
11157 00:42:40.417197 kselftest_armhf.tar 13%[=> ] 214.67K 420KB/s
11158 00:42:40.721803 kselftest_armhf.tar 55%[==========> ] 898.59K 1.14MB/s
11159 00:42:40.728263 kselftest_armhf.tar 97%[==================> ] 1.53M 1.43MB/s
11160 00:42:40.734836 kselftest_armhf.tar 100%[===================>] 1.57M 1.46MB/s in 1.1s
11161 00:42:40.735281
11162 00:42:40.874860 2024-06-16 00:42:40 (1.46 MB/s) - 'kselftest_armhf.tar.gz' saved [1647580/1647580]
11163 00:42:40.875000
11164 00:42:46.214048 skiplist:
11165 00:42:46.217389 ========================================
11166 00:42:46.220186 ========================================
11167 00:42:46.297757 ============== Tests to run ===============
11168 00:42:46.304249 ===========End Tests to run ===============
11169 00:42:46.309464 shardfile-dt fail
11170 00:42:46.334661 ./kselftest.sh: 131: cannot open /lava-14368360/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11171 00:42:46.338075 + ../../utils/send-to-lava.sh ./output/result.txt
11172 00:42:46.409820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11173 00:42:46.409935 + set +x
11174 00:42:46.410172 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11176 00:42:46.416146 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 14368360_1.6.2.3.5>
11177 00:42:46.416393 Received signal: <ENDRUN> 1_kselftest-dt 14368360_1.6.2.3.5
11178 00:42:46.416462 Ending use of test pattern.
11179 00:42:46.416521 Ending test lava.1_kselftest-dt (14368360_1.6.2.3.5), duration 7.65
11181 00:42:46.416756 ok: lava_test_shell seems to have completed
11182 00:42:46.416841 shardfile-dt: fail
11183 00:42:46.416960 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11184 00:42:46.417040 end: 3 lava-test-retry (duration 00:00:09) [common]
11185 00:42:46.417166 start: 4 finalize (timeout 00:07:32) [common]
11186 00:42:46.417246 start: 4.1 power-off (timeout 00:00:30) [common]
11187 00:42:46.417380 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11188 00:42:46.602822 >> Command sent successfully.
11189 00:42:46.606116 Returned 0 in 0 seconds
11190 00:42:46.706493 end: 4.1 power-off (duration 00:00:00) [common]
11192 00:42:46.706775 start: 4.2 read-feedback (timeout 00:07:32) [common]
11194 00:42:46.707293 Listened to connection for namespace 'common' for up to 1s
11195 00:42:47.707973 Finalising connection for namespace 'common'
11196 00:42:47.708135 Disconnecting from shell: Finalise
11197 00:42:47.708203 / #
11198 00:42:47.808477 end: 4.2 read-feedback (duration 00:00:01) [common]
11199 00:42:47.808640 end: 4 finalize (duration 00:00:01) [common]
11200 00:42:47.808796 Cleaning after the job
11201 00:42:47.808896 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/ramdisk
11202 00:42:47.810959 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/kernel
11203 00:42:47.821688 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/dtb
11204 00:42:47.821858 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/nfsrootfs
11205 00:42:47.885927 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368360/tftp-deploy-nxziam0o/modules
11206 00:42:47.891533 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368360
11207 00:42:48.449822 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368360
11208 00:42:48.449975 Job finished correctly