Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 00:42:32.460482 lava-dispatcher, installed at version: 2024.03
2 00:42:32.460715 start: 0 validate
3 00:42:32.460835 Start time: 2024-06-16 00:42:32.460827+00:00 (UTC)
4 00:42:32.460972 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:42:32.461119 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:42:32.711977 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:42:32.712141 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:42:32.961457 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:42:32.961711 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:42:33.209825 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:42:33.209974 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:42:33.465199 validate duration: 1.00
14 00:42:33.465469 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:42:33.465621 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:42:33.465719 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:42:33.465880 Not decompressing ramdisk as can be used compressed.
18 00:42:33.465973 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 00:42:33.466046 saving as /var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/ramdisk/rootfs.cpio.gz
20 00:42:33.466116 total size: 28105535 (26 MB)
21 00:42:33.467116 progress 0 % (0 MB)
22 00:42:33.474420 progress 5 % (1 MB)
23 00:42:33.481506 progress 10 % (2 MB)
24 00:42:33.488582 progress 15 % (4 MB)
25 00:42:33.495630 progress 20 % (5 MB)
26 00:42:33.503084 progress 25 % (6 MB)
27 00:42:33.510458 progress 30 % (8 MB)
28 00:42:33.518478 progress 35 % (9 MB)
29 00:42:33.526517 progress 40 % (10 MB)
30 00:42:33.534762 progress 45 % (12 MB)
31 00:42:33.542086 progress 50 % (13 MB)
32 00:42:33.549293 progress 55 % (14 MB)
33 00:42:33.556413 progress 60 % (16 MB)
34 00:42:33.563648 progress 65 % (17 MB)
35 00:42:33.570808 progress 70 % (18 MB)
36 00:42:33.577926 progress 75 % (20 MB)
37 00:42:33.584933 progress 80 % (21 MB)
38 00:42:33.592012 progress 85 % (22 MB)
39 00:42:33.598807 progress 90 % (24 MB)
40 00:42:33.605718 progress 95 % (25 MB)
41 00:42:33.612649 progress 100 % (26 MB)
42 00:42:33.612863 26 MB downloaded in 0.15 s (182.66 MB/s)
43 00:42:33.613018 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:42:33.613241 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:42:33.613320 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:42:33.613395 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:42:33.613530 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:42:33.613630 saving as /var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/kernel/Image
50 00:42:33.613684 total size: 54813184 (52 MB)
51 00:42:33.613737 No compression specified
52 00:42:33.614747 progress 0 % (0 MB)
53 00:42:33.628307 progress 5 % (2 MB)
54 00:42:33.641980 progress 10 % (5 MB)
55 00:42:33.655500 progress 15 % (7 MB)
56 00:42:33.669518 progress 20 % (10 MB)
57 00:42:33.683405 progress 25 % (13 MB)
58 00:42:33.696964 progress 30 % (15 MB)
59 00:42:33.710710 progress 35 % (18 MB)
60 00:42:33.724279 progress 40 % (20 MB)
61 00:42:33.737843 progress 45 % (23 MB)
62 00:42:33.751597 progress 50 % (26 MB)
63 00:42:33.765404 progress 55 % (28 MB)
64 00:42:33.779452 progress 60 % (31 MB)
65 00:42:33.793127 progress 65 % (34 MB)
66 00:42:33.806693 progress 70 % (36 MB)
67 00:42:33.820351 progress 75 % (39 MB)
68 00:42:33.833900 progress 80 % (41 MB)
69 00:42:33.847386 progress 85 % (44 MB)
70 00:42:33.861055 progress 90 % (47 MB)
71 00:42:33.874876 progress 95 % (49 MB)
72 00:42:33.888278 progress 100 % (52 MB)
73 00:42:33.888525 52 MB downloaded in 0.27 s (190.20 MB/s)
74 00:42:33.888674 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:42:33.888882 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:42:33.888963 start: 1.3 download-retry (timeout 00:10:00) [common]
78 00:42:33.889038 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 00:42:33.889165 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:42:33.889226 saving as /var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/dtb/mt8192-asurada-spherion-r0.dtb
81 00:42:33.889279 total size: 47258 (0 MB)
82 00:42:33.889332 No compression specified
83 00:42:33.890365 progress 69 % (0 MB)
84 00:42:33.890623 progress 100 % (0 MB)
85 00:42:33.890769 0 MB downloaded in 0.00 s (30.29 MB/s)
86 00:42:33.890881 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:42:33.891116 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:42:33.891192 start: 1.4 download-retry (timeout 00:10:00) [common]
90 00:42:33.891266 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 00:42:33.891369 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:42:33.891431 saving as /var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/modules/modules.tar
93 00:42:33.891484 total size: 8608736 (8 MB)
94 00:42:33.891538 Using unxz to decompress xz
95 00:42:33.892789 progress 0 % (0 MB)
96 00:42:33.911645 progress 5 % (0 MB)
97 00:42:33.937276 progress 10 % (0 MB)
98 00:42:33.964540 progress 15 % (1 MB)
99 00:42:33.987817 progress 20 % (1 MB)
100 00:42:34.010938 progress 25 % (2 MB)
101 00:42:34.034225 progress 30 % (2 MB)
102 00:42:34.057974 progress 35 % (2 MB)
103 00:42:34.083773 progress 40 % (3 MB)
104 00:42:34.106180 progress 45 % (3 MB)
105 00:42:34.129680 progress 50 % (4 MB)
106 00:42:34.153929 progress 55 % (4 MB)
107 00:42:34.177770 progress 60 % (4 MB)
108 00:42:34.201507 progress 65 % (5 MB)
109 00:42:34.225742 progress 70 % (5 MB)
110 00:42:34.251482 progress 75 % (6 MB)
111 00:42:34.276985 progress 80 % (6 MB)
112 00:42:34.301081 progress 85 % (7 MB)
113 00:42:34.325589 progress 90 % (7 MB)
114 00:42:34.349979 progress 95 % (7 MB)
115 00:42:34.374439 progress 100 % (8 MB)
116 00:42:34.379715 8 MB downloaded in 0.49 s (16.82 MB/s)
117 00:42:34.379882 end: 1.4.1 http-download (duration 00:00:00) [common]
119 00:42:34.380091 end: 1.4 download-retry (duration 00:00:00) [common]
120 00:42:34.380170 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:42:34.380247 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:42:34.380320 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:42:34.380390 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:42:34.380551 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p
125 00:42:34.380666 makedir: /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin
126 00:42:34.380756 makedir: /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/tests
127 00:42:34.380842 makedir: /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/results
128 00:42:34.380926 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-add-keys
129 00:42:34.381052 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-add-sources
130 00:42:34.381168 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-background-process-start
131 00:42:34.381337 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-background-process-stop
132 00:42:34.381504 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-common-functions
133 00:42:34.381690 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-echo-ipv4
134 00:42:34.381837 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-install-packages
135 00:42:34.381952 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-installed-packages
136 00:42:34.382063 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-os-build
137 00:42:34.382175 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-probe-channel
138 00:42:34.382285 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-probe-ip
139 00:42:34.382393 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-target-ip
140 00:42:34.382503 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-target-mac
141 00:42:34.382612 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-target-storage
142 00:42:34.382724 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-test-case
143 00:42:34.382833 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-test-event
144 00:42:34.382943 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-test-feedback
145 00:42:34.383051 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-test-raise
146 00:42:34.383160 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-test-reference
147 00:42:34.383300 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-test-runner
148 00:42:34.383439 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-test-set
149 00:42:34.383549 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-test-shell
150 00:42:34.383659 Updating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-install-packages (oe)
151 00:42:34.383795 Updating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/bin/lava-installed-packages (oe)
152 00:42:34.383902 Creating /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/environment
153 00:42:34.383985 LAVA metadata
154 00:42:34.384049 - LAVA_JOB_ID=14368394
155 00:42:34.384106 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:42:34.384196 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:42:34.384267 skipped lava-vland-overlay
158 00:42:34.384346 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:42:34.384414 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:42:34.384466 skipped lava-multinode-overlay
161 00:42:34.384528 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:42:34.384596 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:42:34.384657 Loading test definitions
164 00:42:34.384731 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:42:34.384788 Using /lava-14368394 at stage 0
166 00:42:34.385085 uuid=14368394_1.5.2.3.1 testdef=None
167 00:42:34.385165 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:42:34.385240 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:42:34.385706 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:42:34.385907 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:42:34.386455 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:42:34.386663 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:42:34.387195 runner path: /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 14368394_1.5.2.3.1
176 00:42:34.387341 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:42:34.387527 Creating lava-test-runner.conf files
179 00:42:34.387582 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368394/lava-overlay-g45ynf2p/lava-14368394/0 for stage 0
180 00:42:34.387662 - 0_v4l2-compliance-mtk-vcodec-enc
181 00:42:34.387749 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:42:34.387824 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:42:34.394030 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:42:34.394132 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:42:34.394211 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:42:34.394286 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:42:34.394362 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:42:35.266297 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:42:35.266445 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 00:42:35.266518 extracting modules file /var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368394/extract-overlay-ramdisk-n25ihhpz/ramdisk
191 00:42:35.494437 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:42:35.494579 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 00:42:35.494657 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368394/compress-overlay-_3eukt7t/overlay-1.5.2.4.tar.gz to ramdisk
194 00:42:35.494718 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368394/compress-overlay-_3eukt7t/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368394/extract-overlay-ramdisk-n25ihhpz/ramdisk
195 00:42:35.500985 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:42:35.501084 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 00:42:35.501163 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:42:35.501241 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 00:42:35.501307 Building ramdisk /var/lib/lava/dispatcher/tmp/14368394/extract-overlay-ramdisk-n25ihhpz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368394/extract-overlay-ramdisk-n25ihhpz/ramdisk
200 00:42:36.198213 >> 275951 blocks
201 00:42:40.392808 rename /var/lib/lava/dispatcher/tmp/14368394/extract-overlay-ramdisk-n25ihhpz/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/ramdisk/ramdisk.cpio.gz
202 00:42:40.392982 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 00:42:40.393071 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 00:42:40.393150 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 00:42:40.393228 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/kernel/Image']
206 00:42:53.733334 Returned 0 in 13 seconds
207 00:42:53.834210 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/kernel/image.itb
208 00:42:54.511261 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:42:54.511380 output: Created: Sun Jun 16 01:42:54 2024
210 00:42:54.511446 output: Image 0 (kernel-1)
211 00:42:54.511503 output: Description:
212 00:42:54.511560 output: Created: Sun Jun 16 01:42:54 2024
213 00:42:54.511615 output: Type: Kernel Image
214 00:42:54.511672 output: Compression: lzma compressed
215 00:42:54.511778 output: Data Size: 13126376 Bytes = 12818.73 KiB = 12.52 MiB
216 00:42:54.511855 output: Architecture: AArch64
217 00:42:54.511938 output: OS: Linux
218 00:42:54.511994 output: Load Address: 0x00000000
219 00:42:54.512048 output: Entry Point: 0x00000000
220 00:42:54.512105 output: Hash algo: crc32
221 00:42:54.512160 output: Hash value: c791a20a
222 00:42:54.512212 output: Image 1 (fdt-1)
223 00:42:54.512265 output: Description: mt8192-asurada-spherion-r0
224 00:42:54.512317 output: Created: Sun Jun 16 01:42:54 2024
225 00:42:54.512371 output: Type: Flat Device Tree
226 00:42:54.512422 output: Compression: uncompressed
227 00:42:54.512475 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:42:54.512528 output: Architecture: AArch64
229 00:42:54.512578 output: Hash algo: crc32
230 00:42:54.512627 output: Hash value: 0f8e4d2e
231 00:42:54.512675 output: Image 2 (ramdisk-1)
232 00:42:54.512722 output: Description: unavailable
233 00:42:54.512769 output: Created: Sun Jun 16 01:42:54 2024
234 00:42:54.512817 output: Type: RAMDisk Image
235 00:42:54.512864 output: Compression: uncompressed
236 00:42:54.512912 output: Data Size: 41210682 Bytes = 40244.81 KiB = 39.30 MiB
237 00:42:54.512960 output: Architecture: AArch64
238 00:42:54.513006 output: OS: Linux
239 00:42:54.513054 output: Load Address: unavailable
240 00:42:54.513108 output: Entry Point: unavailable
241 00:42:54.513165 output: Hash algo: crc32
242 00:42:54.513213 output: Hash value: 4a70211c
243 00:42:54.513261 output: Default Configuration: 'conf-1'
244 00:42:54.513309 output: Configuration 0 (conf-1)
245 00:42:54.513357 output: Description: mt8192-asurada-spherion-r0
246 00:42:54.513405 output: Kernel: kernel-1
247 00:42:54.513452 output: Init Ramdisk: ramdisk-1
248 00:42:54.513500 output: FDT: fdt-1
249 00:42:54.513553 output: Loadables: kernel-1
250 00:42:54.513642 output:
251 00:42:54.513776 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 00:42:54.513862 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 00:42:54.513951 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 00:42:54.514032 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 00:42:54.514100 No LXC device requested
256 00:42:54.514170 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:42:54.514245 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 00:42:54.514313 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:42:54.514371 Checking files for TFTP limit of 4294967296 bytes.
260 00:42:54.514818 end: 1 tftp-deploy (duration 00:00:21) [common]
261 00:42:54.514918 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:42:54.515015 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:42:54.515129 substitutions:
264 00:42:54.515191 - {DTB}: 14368394/tftp-deploy-qtxpfq2e/dtb/mt8192-asurada-spherion-r0.dtb
265 00:42:54.515251 - {INITRD}: 14368394/tftp-deploy-qtxpfq2e/ramdisk/ramdisk.cpio.gz
266 00:42:54.515304 - {KERNEL}: 14368394/tftp-deploy-qtxpfq2e/kernel/Image
267 00:42:54.515355 - {LAVA_MAC}: None
268 00:42:54.515405 - {PRESEED_CONFIG}: None
269 00:42:54.515456 - {PRESEED_LOCAL}: None
270 00:42:54.515505 - {RAMDISK}: 14368394/tftp-deploy-qtxpfq2e/ramdisk/ramdisk.cpio.gz
271 00:42:54.515562 - {ROOT_PART}: None
272 00:42:54.515612 - {ROOT}: None
273 00:42:54.515661 - {SERVER_IP}: 192.168.201.1
274 00:42:54.515709 - {TEE}: None
275 00:42:54.515758 Parsed boot commands:
276 00:42:54.515806 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:42:54.515953 Parsed boot commands: tftpboot 192.168.201.1 14368394/tftp-deploy-qtxpfq2e/kernel/image.itb 14368394/tftp-deploy-qtxpfq2e/kernel/cmdline
278 00:42:54.516035 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:42:54.516111 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:42:54.516191 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:42:54.516268 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:42:54.516329 Not connected, no need to disconnect.
283 00:42:54.516396 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:42:54.516469 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:42:54.516527 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 00:42:54.519787 Setting prompt string to ['lava-test: # ']
287 00:42:54.520104 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:42:54.520204 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:42:54.520296 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:42:54.520379 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:42:54.520596 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
292 00:43:03.675110 >> Command sent successfully.
293 00:43:03.678245 Returned 0 in 9 seconds
294 00:43:03.778600 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 00:43:03.778879 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 00:43:03.778976 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 00:43:03.779070 Setting prompt string to 'Starting depthcharge on Spherion...'
299 00:43:03.779137 Changing prompt to 'Starting depthcharge on Spherion...'
300 00:43:03.779200 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 00:43:03.779556 [Enter `^Ec?' for help]
302 00:43:05.242313
303 00:43:05.242490
304 00:43:05.242554 F0: 102B 0000
305 00:43:05.242614
306 00:43:05.242669 F3: 1001 0000 [0200]
307 00:43:05.246074
308 00:43:05.246154 F3: 1001 0000
309 00:43:05.246215
310 00:43:05.246273 F7: 102D 0000
311 00:43:05.246331
312 00:43:05.250154 F1: 0000 0000
313 00:43:05.250235
314 00:43:05.250299 V0: 0000 0000 [0001]
315 00:43:05.250357
316 00:43:05.250408 00: 0007 8000
317 00:43:05.250462
318 00:43:05.253511 01: 0000 0000
319 00:43:05.253620
320 00:43:05.253680 BP: 0C00 0209 [0000]
321 00:43:05.253734
322 00:43:05.257321 G0: 1182 0000
323 00:43:05.257396
324 00:43:05.257455 EC: 0000 0021 [4000]
325 00:43:05.257526
326 00:43:05.260952 S7: 0000 0000 [0000]
327 00:43:05.261042
328 00:43:05.261115 CC: 0000 0000 [0001]
329 00:43:05.261168
330 00:43:05.264356 T0: 0000 0040 [010F]
331 00:43:05.264435
332 00:43:05.264494 Jump to BL
333 00:43:05.264577
334 00:43:05.289948
335 00:43:05.290043
336 00:43:05.298098 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 00:43:05.301466 ARM64: Exception handlers installed.
338 00:43:05.304822 ARM64: Testing exception
339 00:43:05.304913 ARM64: Done test exception
340 00:43:05.312451 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 00:43:05.323053 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 00:43:05.332886 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 00:43:05.342697 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 00:43:05.349237 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 00:43:05.355784 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 00:43:05.365922 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 00:43:05.372639 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 00:43:05.392081 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 00:43:05.395706 WDT: Last reset was cold boot
350 00:43:05.399040 SPI1(PAD0) initialized at 2873684 Hz
351 00:43:05.402410 SPI5(PAD0) initialized at 992727 Hz
352 00:43:05.405730 VBOOT: Loading verstage.
353 00:43:05.412444 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 00:43:05.415616 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 00:43:05.418776 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 00:43:05.422079 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 00:43:05.429525 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 00:43:05.436641 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 00:43:05.447204 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 00:43:05.447283
361 00:43:05.447344
362 00:43:05.457462 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 00:43:05.460734 ARM64: Exception handlers installed.
364 00:43:05.463880 ARM64: Testing exception
365 00:43:05.463960 ARM64: Done test exception
366 00:43:05.470696 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 00:43:05.474104 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 00:43:05.488152 Probing TPM: . done!
369 00:43:05.488234 TPM ready after 0 ms
370 00:43:05.495249 Connected to device vid:did:rid of 1ae0:0028:00
371 00:43:05.501703 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 00:43:05.541987 Initialized TPM device CR50 revision 0
373 00:43:05.553881 tlcl_send_startup: Startup return code is 0
374 00:43:05.553970 TPM: setup succeeded
375 00:43:05.565184 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 00:43:05.574141 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 00:43:05.584512 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 00:43:05.593364 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 00:43:05.596394 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 00:43:05.600364 in-header: 03 07 00 00 08 00 00 00
381 00:43:05.603740 in-data: aa e4 47 04 13 02 00 00
382 00:43:05.606936 Chrome EC: UHEPI supported
383 00:43:05.613298 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 00:43:05.616625 in-header: 03 a9 00 00 08 00 00 00
385 00:43:05.620357 in-data: 84 60 60 08 00 00 00 00
386 00:43:05.620435 Phase 1
387 00:43:05.623330 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 00:43:05.630003 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 00:43:05.636913 VB2:vb2_check_recovery() Recovery was requested manually
390 00:43:05.640273 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 00:43:05.643557 Recovery requested (1009000e)
392 00:43:05.652230 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 00:43:05.657451 tlcl_extend: response is 0
394 00:43:05.665342 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 00:43:05.670682 tlcl_extend: response is 0
396 00:43:05.677445 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 00:43:05.698596 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 00:43:05.704757 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 00:43:05.704830
400 00:43:05.704890
401 00:43:05.715586 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 00:43:05.718289 ARM64: Exception handlers installed.
403 00:43:05.721715 ARM64: Testing exception
404 00:43:05.721804 ARM64: Done test exception
405 00:43:05.743985 pmic_efuse_setting: Set efuses in 11 msecs
406 00:43:05.747588 pmwrap_interface_init: Select PMIF_VLD_RDY
407 00:43:05.754547 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 00:43:05.758524 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 00:43:05.762343 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 00:43:05.768292 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 00:43:05.771678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 00:43:05.775699 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 00:43:05.783167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 00:43:05.786584 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 00:43:05.793052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 00:43:05.796359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 00:43:05.799704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 00:43:05.806395 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 00:43:05.809763 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 00:43:05.816275 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 00:43:05.822885 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 00:43:05.826510 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 00:43:05.832922 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 00:43:05.839410 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 00:43:05.842951 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 00:43:05.849612 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 00:43:05.856372 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 00:43:05.859460 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 00:43:05.865963 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 00:43:05.872890 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 00:43:05.876555 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 00:43:05.883207 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 00:43:05.889785 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 00:43:05.893188 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 00:43:05.896301 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 00:43:05.903107 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 00:43:05.906559 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 00:43:05.913386 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 00:43:05.916567 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 00:43:05.923710 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 00:43:05.927015 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 00:43:05.933689 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 00:43:05.937034 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 00:43:05.944315 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 00:43:05.947607 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 00:43:05.951007 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 00:43:05.957322 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 00:43:05.960593 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 00:43:05.964202 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 00:43:05.967436 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 00:43:05.974271 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 00:43:05.977673 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 00:43:05.981146 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 00:43:05.987546 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 00:43:05.991062 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 00:43:05.994309 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 00:43:05.997705 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 00:43:06.007928 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 00:43:06.014567 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 00:43:06.021182 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 00:43:06.027866 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 00:43:06.037417 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 00:43:06.040939 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 00:43:06.044333 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:43:06.050991 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 00:43:06.057842 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x25
467 00:43:06.061055 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 00:43:06.068861 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 00:43:06.071990 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 00:43:06.081139 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 00:43:06.090364 [RTC]rtc_get_frequency_meter,154: input=23, output=943
472 00:43:06.100226 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 00:43:06.109743 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 00:43:06.119244 [RTC]rtc_get_frequency_meter,154: input=16, output=780
475 00:43:06.128540 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 00:43:06.138524 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 00:43:06.141861 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 00:43:06.148373 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 00:43:06.152345 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 00:43:06.155072 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 00:43:06.162306 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 00:43:06.165470 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 00:43:06.168864 ADC[4]: Raw value=906573 ID=7
484 00:43:06.168957 ADC[3]: Raw value=213441 ID=1
485 00:43:06.172158 RAM Code: 0x71
486 00:43:06.175411 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 00:43:06.182048 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 00:43:06.189038 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 00:43:06.195189 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 00:43:06.198760 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 00:43:06.201921 in-header: 03 07 00 00 08 00 00 00
492 00:43:06.205296 in-data: aa e4 47 04 13 02 00 00
493 00:43:06.208549 Chrome EC: UHEPI supported
494 00:43:06.215119 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 00:43:06.218441 in-header: 03 a9 00 00 08 00 00 00
496 00:43:06.221848 in-data: 84 60 60 08 00 00 00 00
497 00:43:06.225157 MRC: failed to locate region type 0.
498 00:43:06.231828 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 00:43:06.234963 DRAM-K: Running full calibration
500 00:43:06.241886 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 00:43:06.245189 header.status = 0x0
502 00:43:06.248530 header.version = 0x6 (expected: 0x6)
503 00:43:06.251949 header.size = 0xd00 (expected: 0xd00)
504 00:43:06.252035 header.flags = 0x0
505 00:43:06.258405 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 00:43:06.275713 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 00:43:06.282288 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 00:43:06.285769 dram_init: ddr_geometry: 2
509 00:43:06.289064 [EMI] MDL number = 2
510 00:43:06.289155 [EMI] Get MDL freq = 0
511 00:43:06.292188 dram_init: ddr_type: 0
512 00:43:06.292279 is_discrete_lpddr4: 1
513 00:43:06.295525 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 00:43:06.295589
515 00:43:06.295659
516 00:43:06.298895 [Bian_co] ETT version 0.0.0.1
517 00:43:06.305812 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 00:43:06.305879
519 00:43:06.309391 dramc_set_vcore_voltage set vcore to 650000
520 00:43:06.309480 Read voltage for 800, 4
521 00:43:06.312555 Vio18 = 0
522 00:43:06.312645 Vcore = 650000
523 00:43:06.312727 Vdram = 0
524 00:43:06.316113 Vddq = 0
525 00:43:06.316203 Vmddr = 0
526 00:43:06.318813 dram_init: config_dvfs: 1
527 00:43:06.322304 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 00:43:06.328972 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 00:43:06.332244 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 00:43:06.336019 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 00:43:06.339085 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 00:43:06.342458 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 00:43:06.345744 MEM_TYPE=3, freq_sel=18
534 00:43:06.349178 sv_algorithm_assistance_LP4_1600
535 00:43:06.352570 ============ PULL DRAM RESETB DOWN ============
536 00:43:06.355982 ========== PULL DRAM RESETB DOWN end =========
537 00:43:06.362497 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 00:43:06.366327 ===================================
539 00:43:06.366397 LPDDR4 DRAM CONFIGURATION
540 00:43:06.369328 ===================================
541 00:43:06.372711 EX_ROW_EN[0] = 0x0
542 00:43:06.375799 EX_ROW_EN[1] = 0x0
543 00:43:06.375888 LP4Y_EN = 0x0
544 00:43:06.379573 WORK_FSP = 0x0
545 00:43:06.379660 WL = 0x2
546 00:43:06.382606 RL = 0x2
547 00:43:06.382672 BL = 0x2
548 00:43:06.386135 RPST = 0x0
549 00:43:06.386201 RD_PRE = 0x0
550 00:43:06.389443 WR_PRE = 0x1
551 00:43:06.389535 WR_PST = 0x0
552 00:43:06.392568 DBI_WR = 0x0
553 00:43:06.392658 DBI_RD = 0x0
554 00:43:06.395901 OTF = 0x1
555 00:43:06.399173 ===================================
556 00:43:06.402522 ===================================
557 00:43:06.402583 ANA top config
558 00:43:06.405897 ===================================
559 00:43:06.409307 DLL_ASYNC_EN = 0
560 00:43:06.413133 ALL_SLAVE_EN = 1
561 00:43:06.413219 NEW_RANK_MODE = 1
562 00:43:06.416413 DLL_IDLE_MODE = 1
563 00:43:06.420476 LP45_APHY_COMB_EN = 1
564 00:43:06.420541 TX_ODT_DIS = 1
565 00:43:06.424560 NEW_8X_MODE = 1
566 00:43:06.428127 ===================================
567 00:43:06.432001 ===================================
568 00:43:06.435860 data_rate = 1600
569 00:43:06.435946 CKR = 1
570 00:43:06.439106 DQ_P2S_RATIO = 8
571 00:43:06.442865 ===================================
572 00:43:06.446756 CA_P2S_RATIO = 8
573 00:43:06.446817 DQ_CA_OPEN = 0
574 00:43:06.450057 DQ_SEMI_OPEN = 0
575 00:43:06.453374 CA_SEMI_OPEN = 0
576 00:43:06.456774 CA_FULL_RATE = 0
577 00:43:06.460002 DQ_CKDIV4_EN = 1
578 00:43:06.463345 CA_CKDIV4_EN = 1
579 00:43:06.463432 CA_PREDIV_EN = 0
580 00:43:06.467374 PH8_DLY = 0
581 00:43:06.470725 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 00:43:06.473385 DQ_AAMCK_DIV = 4
583 00:43:06.477260 CA_AAMCK_DIV = 4
584 00:43:06.480569 CA_ADMCK_DIV = 4
585 00:43:06.480662 DQ_TRACK_CA_EN = 0
586 00:43:06.483349 CA_PICK = 800
587 00:43:06.486759 CA_MCKIO = 800
588 00:43:06.490003 MCKIO_SEMI = 0
589 00:43:06.493741 PLL_FREQ = 3068
590 00:43:06.497120 DQ_UI_PI_RATIO = 32
591 00:43:06.500541 CA_UI_PI_RATIO = 0
592 00:43:06.503957 ===================================
593 00:43:06.507223 ===================================
594 00:43:06.507309 memory_type:LPDDR4
595 00:43:06.510406 GP_NUM : 10
596 00:43:06.510494 SRAM_EN : 1
597 00:43:06.513979 MD32_EN : 0
598 00:43:06.517177 ===================================
599 00:43:06.520878 [ANA_INIT] >>>>>>>>>>>>>>
600 00:43:06.524024 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 00:43:06.527245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 00:43:06.530392 ===================================
603 00:43:06.530461 data_rate = 1600,PCW = 0X7600
604 00:43:06.534046 ===================================
605 00:43:06.537091 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 00:43:06.543699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:43:06.550455 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 00:43:06.554102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 00:43:06.557014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:43:06.560295 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 00:43:06.563657 [ANA_INIT] flow start
612 00:43:06.566988 [ANA_INIT] PLL >>>>>>>>
613 00:43:06.567078 [ANA_INIT] PLL <<<<<<<<
614 00:43:06.570402 [ANA_INIT] MIDPI >>>>>>>>
615 00:43:06.573721 [ANA_INIT] MIDPI <<<<<<<<
616 00:43:06.573787 [ANA_INIT] DLL >>>>>>>>
617 00:43:06.577137 [ANA_INIT] flow end
618 00:43:06.580548 ============ LP4 DIFF to SE enter ============
619 00:43:06.583885 ============ LP4 DIFF to SE exit ============
620 00:43:06.587287 [ANA_INIT] <<<<<<<<<<<<<
621 00:43:06.590612 [Flow] Enable top DCM control >>>>>
622 00:43:06.594053 [Flow] Enable top DCM control <<<<<
623 00:43:06.597458 Enable DLL master slave shuffle
624 00:43:06.600769 ==============================================================
625 00:43:06.604065 Gating Mode config
626 00:43:06.610675 ==============================================================
627 00:43:06.610745 Config description:
628 00:43:06.620747 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 00:43:06.627943 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 00:43:06.634461 SELPH_MODE 0: By rank 1: By Phase
631 00:43:06.637604 ==============================================================
632 00:43:06.640653 GAT_TRACK_EN = 1
633 00:43:06.644176 RX_GATING_MODE = 2
634 00:43:06.647437 RX_GATING_TRACK_MODE = 2
635 00:43:06.650686 SELPH_MODE = 1
636 00:43:06.653962 PICG_EARLY_EN = 1
637 00:43:06.657500 VALID_LAT_VALUE = 1
638 00:43:06.660859 ==============================================================
639 00:43:06.664331 Enter into Gating configuration >>>>
640 00:43:06.667497 Exit from Gating configuration <<<<
641 00:43:06.671262 Enter into DVFS_PRE_config >>>>>
642 00:43:06.680974 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 00:43:06.684305 Exit from DVFS_PRE_config <<<<<
644 00:43:06.687590 Enter into PICG configuration >>>>
645 00:43:06.690953 Exit from PICG configuration <<<<
646 00:43:06.694330 [RX_INPUT] configuration >>>>>
647 00:43:06.697719 [RX_INPUT] configuration <<<<<
648 00:43:06.704317 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 00:43:06.707685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 00:43:06.714349 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 00:43:06.721003 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 00:43:06.727944 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 00:43:06.734846 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 00:43:06.738076 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 00:43:06.741460 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 00:43:06.744745 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 00:43:06.748150 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 00:43:06.754519 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 00:43:06.758094 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 00:43:06.761446 ===================================
661 00:43:06.764776 LPDDR4 DRAM CONFIGURATION
662 00:43:06.767907 ===================================
663 00:43:06.768005 EX_ROW_EN[0] = 0x0
664 00:43:06.771089 EX_ROW_EN[1] = 0x0
665 00:43:06.771180 LP4Y_EN = 0x0
666 00:43:06.774339 WORK_FSP = 0x0
667 00:43:06.774433 WL = 0x2
668 00:43:06.777762 RL = 0x2
669 00:43:06.777834 BL = 0x2
670 00:43:06.781405 RPST = 0x0
671 00:43:06.781500 RD_PRE = 0x0
672 00:43:06.784528 WR_PRE = 0x1
673 00:43:06.784620 WR_PST = 0x0
674 00:43:06.787774 DBI_WR = 0x0
675 00:43:06.787868 DBI_RD = 0x0
676 00:43:06.791312 OTF = 0x1
677 00:43:06.794468 ===================================
678 00:43:06.797682 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 00:43:06.801469 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 00:43:06.808063 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 00:43:06.811352 ===================================
682 00:43:06.811425 LPDDR4 DRAM CONFIGURATION
683 00:43:06.814698 ===================================
684 00:43:06.818073 EX_ROW_EN[0] = 0x10
685 00:43:06.821463 EX_ROW_EN[1] = 0x0
686 00:43:06.821541 LP4Y_EN = 0x0
687 00:43:06.824828 WORK_FSP = 0x0
688 00:43:06.824905 WL = 0x2
689 00:43:06.828140 RL = 0x2
690 00:43:06.828218 BL = 0x2
691 00:43:06.831379 RPST = 0x0
692 00:43:06.831456 RD_PRE = 0x0
693 00:43:06.835096 WR_PRE = 0x1
694 00:43:06.835174 WR_PST = 0x0
695 00:43:06.838560 DBI_WR = 0x0
696 00:43:06.838638 DBI_RD = 0x0
697 00:43:06.841797 OTF = 0x1
698 00:43:06.845138 ===================================
699 00:43:06.851717 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 00:43:06.855062 nWR fixed to 40
701 00:43:06.855162 [ModeRegInit_LP4] CH0 RK0
702 00:43:06.858425 [ModeRegInit_LP4] CH0 RK1
703 00:43:06.861826 [ModeRegInit_LP4] CH1 RK0
704 00:43:06.861898 [ModeRegInit_LP4] CH1 RK1
705 00:43:06.865300 match AC timing 13
706 00:43:06.868714 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 00:43:06.871407 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 00:43:06.878643 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 00:43:06.881821 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 00:43:06.888624 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 00:43:06.888724 [EMI DOE] emi_dcm 0
712 00:43:06.891709 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 00:43:06.895359 ==
714 00:43:06.898173 Dram Type= 6, Freq= 0, CH_0, rank 0
715 00:43:06.901529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 00:43:06.901612 ==
717 00:43:06.905312 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 00:43:06.911503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 00:43:06.921539 [CA 0] Center 36 (6~67) winsize 62
720 00:43:06.924984 [CA 1] Center 36 (6~67) winsize 62
721 00:43:06.928082 [CA 2] Center 34 (4~65) winsize 62
722 00:43:06.931335 [CA 3] Center 34 (4~64) winsize 61
723 00:43:06.935154 [CA 4] Center 32 (2~63) winsize 62
724 00:43:06.938900 [CA 5] Center 32 (2~62) winsize 61
725 00:43:06.938980
726 00:43:06.942189 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 00:43:06.942266
728 00:43:06.945321 [CATrainingPosCal] consider 1 rank data
729 00:43:06.948711 u2DelayCellTimex100 = 270/100 ps
730 00:43:06.952571 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 00:43:06.955858 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 00:43:06.959173 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 00:43:06.962525 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 00:43:06.969344 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
735 00:43:06.972780 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 00:43:06.972859
737 00:43:06.975493 CA PerBit enable=1, Macro0, CA PI delay=32
738 00:43:06.975572
739 00:43:06.978877 [CBTSetCACLKResult] CA Dly = 32
740 00:43:06.978955 CS Dly: 4 (0~35)
741 00:43:06.979016 ==
742 00:43:06.982839 Dram Type= 6, Freq= 0, CH_0, rank 1
743 00:43:06.985477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 00:43:06.988822 ==
745 00:43:06.992673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 00:43:06.999657 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 00:43:07.007677 [CA 0] Center 36 (6~67) winsize 62
748 00:43:07.011693 [CA 1] Center 36 (6~67) winsize 62
749 00:43:07.014529 [CA 2] Center 34 (4~65) winsize 62
750 00:43:07.017878 [CA 3] Center 34 (3~65) winsize 63
751 00:43:07.021743 [CA 4] Center 33 (3~63) winsize 61
752 00:43:07.024876 [CA 5] Center 32 (2~63) winsize 62
753 00:43:07.024955
754 00:43:07.028150 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 00:43:07.028228
756 00:43:07.031321 [CATrainingPosCal] consider 2 rank data
757 00:43:07.034526 u2DelayCellTimex100 = 270/100 ps
758 00:43:07.038126 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 00:43:07.041866 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 00:43:07.047844 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 00:43:07.051502 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 00:43:07.054325 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 00:43:07.057815 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 00:43:07.057923
765 00:43:07.061300 CA PerBit enable=1, Macro0, CA PI delay=32
766 00:43:07.061395
767 00:43:07.064403 [CBTSetCACLKResult] CA Dly = 32
768 00:43:07.064512 CS Dly: 5 (0~37)
769 00:43:07.064601
770 00:43:07.067766 ----->DramcWriteLeveling(PI) begin...
771 00:43:07.071467 ==
772 00:43:07.074265 Dram Type= 6, Freq= 0, CH_0, rank 0
773 00:43:07.077619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 00:43:07.077695 ==
775 00:43:07.081059 Write leveling (Byte 0): 33 => 33
776 00:43:07.084459 Write leveling (Byte 1): 28 => 28
777 00:43:07.087859 DramcWriteLeveling(PI) end<-----
778 00:43:07.087958
779 00:43:07.088050 ==
780 00:43:07.091177 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:43:07.094400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 00:43:07.094479 ==
783 00:43:07.097781 [Gating] SW mode calibration
784 00:43:07.104301 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 00:43:07.108145 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 00:43:07.114547 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 00:43:07.117811 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 00:43:07.121253 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 00:43:07.127869 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:43:07.131262 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:43:07.134514 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:43:07.141332 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:43:07.144657 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:43:07.148016 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:43:07.154628 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:43:07.158352 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:43:07.161805 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:43:07.164921 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:43:07.171469 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:43:07.174815 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:43:07.178191 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:43:07.185044 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 00:43:07.188744 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 00:43:07.191387 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 00:43:07.198592 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:43:07.201853 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:43:07.205033 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:43:07.211533 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:43:07.215403 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:43:07.218811 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:43:07.225353 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 00:43:07.228620 0 9 8 | B1->B0 | 2323 3333 | 1 1 | (1 1) (1 1)
813 00:43:07.231907 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
814 00:43:07.238381 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:43:07.241766 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:43:07.245234 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:43:07.248545 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:43:07.254750 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 00:43:07.258041 0 10 4 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
820 00:43:07.261957 0 10 8 | B1->B0 | 3131 2727 | 0 0 | (0 1) (0 0)
821 00:43:07.268522 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 00:43:07.271967 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:43:07.275338 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:43:07.281851 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:43:07.285143 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:43:07.288417 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:43:07.295371 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
828 00:43:07.298925 0 11 8 | B1->B0 | 2b2b 4545 | 1 0 | (0 0) (1 1)
829 00:43:07.302264 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
830 00:43:07.308783 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:43:07.311965 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:43:07.315451 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:43:07.321820 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:43:07.325248 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:43:07.329263 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 00:43:07.332300 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 00:43:07.339275 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 00:43:07.342174 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:43:07.345399 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:43:07.352060 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:43:07.355366 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:43:07.358730 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:43:07.365562 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:43:07.368637 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:43:07.371943 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:43:07.378732 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:43:07.382011 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:43:07.385369 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:43:07.392553 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:43:07.395666 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:43:07.399162 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 00:43:07.402515 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
853 00:43:07.405456 Total UI for P1: 0, mck2ui 16
854 00:43:07.409408 best dqsien dly found for B0: ( 0, 14, 6)
855 00:43:07.415963 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 00:43:07.416058 Total UI for P1: 0, mck2ui 16
857 00:43:07.422289 best dqsien dly found for B1: ( 0, 14, 10)
858 00:43:07.425622 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 00:43:07.429109 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 00:43:07.429207
861 00:43:07.432335 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 00:43:07.435450 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 00:43:07.439124 [Gating] SW calibration Done
864 00:43:07.439218 ==
865 00:43:07.442035 Dram Type= 6, Freq= 0, CH_0, rank 0
866 00:43:07.445583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 00:43:07.445653 ==
868 00:43:07.449092 RX Vref Scan: 0
869 00:43:07.449161
870 00:43:07.449236 RX Vref 0 -> 0, step: 1
871 00:43:07.449306
872 00:43:07.452494 RX Delay -130 -> 252, step: 16
873 00:43:07.455727 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
874 00:43:07.462366 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 00:43:07.465656 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
876 00:43:07.468849 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
877 00:43:07.472134 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 00:43:07.475964 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 00:43:07.482589 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 00:43:07.485907 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 00:43:07.489175 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
882 00:43:07.492465 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
883 00:43:07.496334 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
884 00:43:07.499606 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
885 00:43:07.506245 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
886 00:43:07.509337 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
887 00:43:07.512479 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
888 00:43:07.515870 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
889 00:43:07.515948 ==
890 00:43:07.519167 Dram Type= 6, Freq= 0, CH_0, rank 0
891 00:43:07.526085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 00:43:07.526190 ==
893 00:43:07.526250 DQS Delay:
894 00:43:07.529634 DQS0 = 0, DQS1 = 0
895 00:43:07.529725 DQM Delay:
896 00:43:07.529783 DQM0 = 91, DQM1 = 86
897 00:43:07.532721 DQ Delay:
898 00:43:07.535749 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
899 00:43:07.539277 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
900 00:43:07.542400 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
901 00:43:07.546167 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 00:43:07.546245
903 00:43:07.546306
904 00:43:07.546361 ==
905 00:43:07.549447 Dram Type= 6, Freq= 0, CH_0, rank 0
906 00:43:07.552625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 00:43:07.552703 ==
908 00:43:07.552763
909 00:43:07.552818
910 00:43:07.555795 TX Vref Scan disable
911 00:43:07.559530 == TX Byte 0 ==
912 00:43:07.562297 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
913 00:43:07.566162 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
914 00:43:07.569334 == TX Byte 1 ==
915 00:43:07.572447 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
916 00:43:07.576036 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
917 00:43:07.576124 ==
918 00:43:07.579328 Dram Type= 6, Freq= 0, CH_0, rank 0
919 00:43:07.582700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 00:43:07.582791 ==
921 00:43:07.597572 TX Vref=22, minBit 5, minWin=27, winSum=446
922 00:43:07.600511 TX Vref=24, minBit 10, minWin=27, winSum=455
923 00:43:07.603770 TX Vref=26, minBit 5, minWin=28, winSum=458
924 00:43:07.607260 TX Vref=28, minBit 10, minWin=28, winSum=459
925 00:43:07.610565 TX Vref=30, minBit 0, minWin=28, winSum=459
926 00:43:07.617476 TX Vref=32, minBit 6, minWin=28, winSum=455
927 00:43:07.620805 [TxChooseVref] Worse bit 10, Min win 28, Win sum 459, Final Vref 28
928 00:43:07.620873
929 00:43:07.624078 Final TX Range 1 Vref 28
930 00:43:07.624145
931 00:43:07.624219 ==
932 00:43:07.627426 Dram Type= 6, Freq= 0, CH_0, rank 0
933 00:43:07.630785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 00:43:07.630875 ==
935 00:43:07.634342
936 00:43:07.634413
937 00:43:07.634484 TX Vref Scan disable
938 00:43:07.637630 == TX Byte 0 ==
939 00:43:07.640887 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 00:43:07.644053 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 00:43:07.647501 == TX Byte 1 ==
942 00:43:07.650970 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
943 00:43:07.654054 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
944 00:43:07.657387
945 00:43:07.657484 [DATLAT]
946 00:43:07.657610 Freq=800, CH0 RK0
947 00:43:07.657688
948 00:43:07.660699 DATLAT Default: 0xa
949 00:43:07.660766 0, 0xFFFF, sum = 0
950 00:43:07.664362 1, 0xFFFF, sum = 0
951 00:43:07.664453 2, 0xFFFF, sum = 0
952 00:43:07.667678 3, 0xFFFF, sum = 0
953 00:43:07.667767 4, 0xFFFF, sum = 0
954 00:43:07.671072 5, 0xFFFF, sum = 0
955 00:43:07.671168 6, 0xFFFF, sum = 0
956 00:43:07.674528 7, 0xFFFF, sum = 0
957 00:43:07.677905 8, 0xFFFF, sum = 0
958 00:43:07.677978 9, 0x0, sum = 1
959 00:43:07.678040 10, 0x0, sum = 2
960 00:43:07.681299 11, 0x0, sum = 3
961 00:43:07.681393 12, 0x0, sum = 4
962 00:43:07.684049 best_step = 10
963 00:43:07.684136
964 00:43:07.684214 ==
965 00:43:07.687973 Dram Type= 6, Freq= 0, CH_0, rank 0
966 00:43:07.691137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 00:43:07.691205 ==
968 00:43:07.694276 RX Vref Scan: 1
969 00:43:07.694338
970 00:43:07.694390 Set Vref Range= 32 -> 127
971 00:43:07.694441
972 00:43:07.697837 RX Vref 32 -> 127, step: 1
973 00:43:07.697923
974 00:43:07.700677 RX Delay -79 -> 252, step: 8
975 00:43:07.700760
976 00:43:07.704527 Set Vref, RX VrefLevel [Byte0]: 32
977 00:43:07.707782 [Byte1]: 32
978 00:43:07.707846
979 00:43:07.710696 Set Vref, RX VrefLevel [Byte0]: 33
980 00:43:07.714300 [Byte1]: 33
981 00:43:07.717584
982 00:43:07.717659 Set Vref, RX VrefLevel [Byte0]: 34
983 00:43:07.721300 [Byte1]: 34
984 00:43:07.725327
985 00:43:07.725420 Set Vref, RX VrefLevel [Byte0]: 35
986 00:43:07.728397 [Byte1]: 35
987 00:43:07.732999
988 00:43:07.733066 Set Vref, RX VrefLevel [Byte0]: 36
989 00:43:07.736384 [Byte1]: 36
990 00:43:07.740451
991 00:43:07.740543 Set Vref, RX VrefLevel [Byte0]: 37
992 00:43:07.743823 [Byte1]: 37
993 00:43:07.747671
994 00:43:07.747737 Set Vref, RX VrefLevel [Byte0]: 38
995 00:43:07.751606 [Byte1]: 38
996 00:43:07.755526
997 00:43:07.755620 Set Vref, RX VrefLevel [Byte0]: 39
998 00:43:07.758609 [Byte1]: 39
999 00:43:07.763432
1000 00:43:07.763529 Set Vref, RX VrefLevel [Byte0]: 40
1001 00:43:07.766347 [Byte1]: 40
1002 00:43:07.770520
1003 00:43:07.770610 Set Vref, RX VrefLevel [Byte0]: 41
1004 00:43:07.773743 [Byte1]: 41
1005 00:43:07.778381
1006 00:43:07.778470 Set Vref, RX VrefLevel [Byte0]: 42
1007 00:43:07.781678 [Byte1]: 42
1008 00:43:07.785648
1009 00:43:07.785719 Set Vref, RX VrefLevel [Byte0]: 43
1010 00:43:07.789030 [Byte1]: 43
1011 00:43:07.793502
1012 00:43:07.793590 Set Vref, RX VrefLevel [Byte0]: 44
1013 00:43:07.796703 [Byte1]: 44
1014 00:43:07.800827
1015 00:43:07.800906 Set Vref, RX VrefLevel [Byte0]: 45
1016 00:43:07.804089 [Byte1]: 45
1017 00:43:07.808429
1018 00:43:07.808526 Set Vref, RX VrefLevel [Byte0]: 46
1019 00:43:07.811847 [Byte1]: 46
1020 00:43:07.815911
1021 00:43:07.815995 Set Vref, RX VrefLevel [Byte0]: 47
1022 00:43:07.819243 [Byte1]: 47
1023 00:43:07.823693
1024 00:43:07.823761 Set Vref, RX VrefLevel [Byte0]: 48
1025 00:43:07.826845 [Byte1]: 48
1026 00:43:07.830757
1027 00:43:07.830848 Set Vref, RX VrefLevel [Byte0]: 49
1028 00:43:07.834260 [Byte1]: 49
1029 00:43:07.838453
1030 00:43:07.838548 Set Vref, RX VrefLevel [Byte0]: 50
1031 00:43:07.842141 [Byte1]: 50
1032 00:43:07.846608
1033 00:43:07.846709 Set Vref, RX VrefLevel [Byte0]: 51
1034 00:43:07.849313 [Byte1]: 51
1035 00:43:07.853577
1036 00:43:07.853656 Set Vref, RX VrefLevel [Byte0]: 52
1037 00:43:07.856815 [Byte1]: 52
1038 00:43:07.861467
1039 00:43:07.861551 Set Vref, RX VrefLevel [Byte0]: 53
1040 00:43:07.864774 [Byte1]: 53
1041 00:43:07.868650
1042 00:43:07.868728 Set Vref, RX VrefLevel [Byte0]: 54
1043 00:43:07.871748 [Byte1]: 54
1044 00:43:07.876447
1045 00:43:07.876525 Set Vref, RX VrefLevel [Byte0]: 55
1046 00:43:07.879794 [Byte1]: 55
1047 00:43:07.883758
1048 00:43:07.883835 Set Vref, RX VrefLevel [Byte0]: 56
1049 00:43:07.887348 [Byte1]: 56
1050 00:43:07.891338
1051 00:43:07.891416 Set Vref, RX VrefLevel [Byte0]: 57
1052 00:43:07.894657 [Byte1]: 57
1053 00:43:07.899240
1054 00:43:07.899353 Set Vref, RX VrefLevel [Byte0]: 58
1055 00:43:07.902677 [Byte1]: 58
1056 00:43:07.906796
1057 00:43:07.906868 Set Vref, RX VrefLevel [Byte0]: 59
1058 00:43:07.910062 [Byte1]: 59
1059 00:43:07.913840
1060 00:43:07.913908 Set Vref, RX VrefLevel [Byte0]: 60
1061 00:43:07.917258 [Byte1]: 60
1062 00:43:07.921799
1063 00:43:07.921868 Set Vref, RX VrefLevel [Byte0]: 61
1064 00:43:07.925160 [Byte1]: 61
1065 00:43:07.929255
1066 00:43:07.929362 Set Vref, RX VrefLevel [Byte0]: 62
1067 00:43:07.932516 [Byte1]: 62
1068 00:43:07.936607
1069 00:43:07.936700 Set Vref, RX VrefLevel [Byte0]: 63
1070 00:43:07.939803 [Byte1]: 63
1071 00:43:07.944474
1072 00:43:07.944566 Set Vref, RX VrefLevel [Byte0]: 64
1073 00:43:07.947516 [Byte1]: 64
1074 00:43:07.951864
1075 00:43:07.951936 Set Vref, RX VrefLevel [Byte0]: 65
1076 00:43:07.955429 [Byte1]: 65
1077 00:43:07.959175
1078 00:43:07.959285 Set Vref, RX VrefLevel [Byte0]: 66
1079 00:43:07.962883 [Byte1]: 66
1080 00:43:07.966876
1081 00:43:07.966968 Set Vref, RX VrefLevel [Byte0]: 67
1082 00:43:07.970566 [Byte1]: 67
1083 00:43:07.974753
1084 00:43:07.974825 Set Vref, RX VrefLevel [Byte0]: 68
1085 00:43:07.977927 [Byte1]: 68
1086 00:43:07.982223
1087 00:43:07.982295 Set Vref, RX VrefLevel [Byte0]: 69
1088 00:43:07.985389 [Byte1]: 69
1089 00:43:07.989628
1090 00:43:07.989699 Set Vref, RX VrefLevel [Byte0]: 70
1091 00:43:07.992631 [Byte1]: 70
1092 00:43:07.997048
1093 00:43:07.997152 Set Vref, RX VrefLevel [Byte0]: 71
1094 00:43:08.000333 [Byte1]: 71
1095 00:43:08.004729
1096 00:43:08.004824 Set Vref, RX VrefLevel [Byte0]: 72
1097 00:43:08.008121 [Byte1]: 72
1098 00:43:08.012092
1099 00:43:08.012191 Set Vref, RX VrefLevel [Byte0]: 73
1100 00:43:08.018431 [Byte1]: 73
1101 00:43:08.018528
1102 00:43:08.021785 Set Vref, RX VrefLevel [Byte0]: 74
1103 00:43:08.025109 [Byte1]: 74
1104 00:43:08.025205
1105 00:43:08.028522 Set Vref, RX VrefLevel [Byte0]: 75
1106 00:43:08.031931 [Byte1]: 75
1107 00:43:08.032020
1108 00:43:08.035413 Set Vref, RX VrefLevel [Byte0]: 76
1109 00:43:08.038819 [Byte1]: 76
1110 00:43:08.042217
1111 00:43:08.042309 Set Vref, RX VrefLevel [Byte0]: 77
1112 00:43:08.046010 [Byte1]: 77
1113 00:43:08.050013
1114 00:43:08.050081 Set Vref, RX VrefLevel [Byte0]: 78
1115 00:43:08.053331 [Byte1]: 78
1116 00:43:08.057282
1117 00:43:08.057385 Set Vref, RX VrefLevel [Byte0]: 79
1118 00:43:08.060628 [Byte1]: 79
1119 00:43:08.065117
1120 00:43:08.065219 Final RX Vref Byte 0 = 54 to rank0
1121 00:43:08.068380 Final RX Vref Byte 1 = 58 to rank0
1122 00:43:08.071706 Final RX Vref Byte 0 = 54 to rank1
1123 00:43:08.074816 Final RX Vref Byte 1 = 58 to rank1==
1124 00:43:08.078373 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 00:43:08.085614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 00:43:08.085714 ==
1127 00:43:08.085811 DQS Delay:
1128 00:43:08.085895 DQS0 = 0, DQS1 = 0
1129 00:43:08.088446 DQM Delay:
1130 00:43:08.088513 DQM0 = 91, DQM1 = 85
1131 00:43:08.091524 DQ Delay:
1132 00:43:08.094807 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1133 00:43:08.098416 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1134 00:43:08.101732 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1135 00:43:08.105084 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1136 00:43:08.105183
1137 00:43:08.105278
1138 00:43:08.111633 [DQSOSCAuto] RK0, (LSB)MR18= 0x5147, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
1139 00:43:08.115261 CH0 RK0: MR19=606, MR18=5147
1140 00:43:08.122258 CH0_RK0: MR19=0x606, MR18=0x5147, DQSOSC=389, MR23=63, INC=97, DEC=65
1141 00:43:08.122336
1142 00:43:08.125223 ----->DramcWriteLeveling(PI) begin...
1143 00:43:08.125325 ==
1144 00:43:08.128556 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 00:43:08.131988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 00:43:08.132062 ==
1147 00:43:08.135352 Write leveling (Byte 0): 32 => 32
1148 00:43:08.138755 Write leveling (Byte 1): 30 => 30
1149 00:43:08.142118 DramcWriteLeveling(PI) end<-----
1150 00:43:08.142190
1151 00:43:08.142264 ==
1152 00:43:08.145367 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 00:43:08.148557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 00:43:08.148627 ==
1155 00:43:08.151926 [Gating] SW mode calibration
1156 00:43:08.158610 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 00:43:08.206331 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 00:43:08.206447 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 00:43:08.206731 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1160 00:43:08.206823 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1161 00:43:08.206934 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:43:08.207041 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:43:08.207129 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:43:08.207216 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:43:08.207313 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:43:08.207394 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:43:08.219014 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:43:08.219099 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 00:43:08.219475 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 00:43:08.222786 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:43:08.225998 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:43:08.229038 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:43:08.235841 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:43:08.239500 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:43:08.242879 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1176 00:43:08.249253 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1177 00:43:08.252463 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:43:08.255887 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:43:08.259080 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:43:08.265661 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 00:43:08.269708 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 00:43:08.272350 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 00:43:08.279622 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 00:43:08.282316 0 9 8 | B1->B0 | 2f2f 2b2b | 1 0 | (1 1) (1 1)
1185 00:43:08.285680 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 00:43:08.292520 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 00:43:08.295776 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 00:43:08.299054 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 00:43:08.306282 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 00:43:08.309717 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 00:43:08.312963 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (0 1) (0 0)
1192 00:43:08.319689 0 10 8 | B1->B0 | 2626 2929 | 0 0 | (1 0) (0 0)
1193 00:43:08.322602 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1194 00:43:08.326019 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 00:43:08.332718 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 00:43:08.336003 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 00:43:08.339775 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 00:43:08.342809 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 00:43:08.349137 0 11 4 | B1->B0 | 2626 2424 | 0 1 | (0 0) (0 0)
1200 00:43:08.352829 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1201 00:43:08.356363 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 00:43:08.362924 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 00:43:08.366054 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 00:43:08.369369 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 00:43:08.376021 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 00:43:08.379346 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 00:43:08.382524 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 00:43:08.389774 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1209 00:43:08.393072 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:43:08.396314 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:43:08.403099 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:43:08.406195 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:43:08.409361 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:43:08.416006 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:43:08.419431 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:43:08.423398 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 00:43:08.426552 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 00:43:08.432949 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 00:43:08.436381 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 00:43:08.439753 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 00:43:08.446420 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 00:43:08.449531 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 00:43:08.453020 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 00:43:08.459968 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1225 00:43:08.462972 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 00:43:08.466243 Total UI for P1: 0, mck2ui 16
1227 00:43:08.469544 best dqsien dly found for B0: ( 0, 14, 8)
1228 00:43:08.472964 Total UI for P1: 0, mck2ui 16
1229 00:43:08.476710 best dqsien dly found for B1: ( 0, 14, 8)
1230 00:43:08.480027 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1231 00:43:08.483069 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1232 00:43:08.483160
1233 00:43:08.486400 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1234 00:43:08.489772 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1235 00:43:08.493008 [Gating] SW calibration Done
1236 00:43:08.493104 ==
1237 00:43:08.496735 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 00:43:08.499605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 00:43:08.499700 ==
1240 00:43:08.503006 RX Vref Scan: 0
1241 00:43:08.503072
1242 00:43:08.506686 RX Vref 0 -> 0, step: 1
1243 00:43:08.506752
1244 00:43:08.506822 RX Delay -130 -> 252, step: 16
1245 00:43:08.512774 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1246 00:43:08.516246 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1247 00:43:08.519769 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1248 00:43:08.522797 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1249 00:43:08.526270 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1250 00:43:08.532895 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1251 00:43:08.536561 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1252 00:43:08.539851 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1253 00:43:08.543263 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1254 00:43:08.546751 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1255 00:43:08.553117 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1256 00:43:08.556462 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1257 00:43:08.559741 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1258 00:43:08.563142 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1259 00:43:08.566348 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1260 00:43:08.573360 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1261 00:43:08.573455 ==
1262 00:43:08.576736 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 00:43:08.580015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 00:43:08.580116 ==
1265 00:43:08.580200 DQS Delay:
1266 00:43:08.583388 DQS0 = 0, DQS1 = 0
1267 00:43:08.583454 DQM Delay:
1268 00:43:08.586708 DQM0 = 92, DQM1 = 83
1269 00:43:08.586775 DQ Delay:
1270 00:43:08.590138 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1271 00:43:08.593428 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109
1272 00:43:08.596398 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1273 00:43:08.600068 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1274 00:43:08.600165
1275 00:43:08.600248
1276 00:43:08.600331 ==
1277 00:43:08.603241 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 00:43:08.606349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 00:43:08.606415 ==
1280 00:43:08.609798
1281 00:43:08.609865
1282 00:43:08.609919 TX Vref Scan disable
1283 00:43:08.613346 == TX Byte 0 ==
1284 00:43:08.616624 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1285 00:43:08.620432 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1286 00:43:08.623036 == TX Byte 1 ==
1287 00:43:08.626709 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1288 00:43:08.629897 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1289 00:43:08.629992 ==
1290 00:43:08.632979 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 00:43:08.639964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 00:43:08.640066 ==
1293 00:43:08.652003 TX Vref=22, minBit 8, minWin=27, winSum=447
1294 00:43:08.655288 TX Vref=24, minBit 1, minWin=28, winSum=456
1295 00:43:08.658595 TX Vref=26, minBit 1, minWin=28, winSum=458
1296 00:43:08.661988 TX Vref=28, minBit 4, minWin=28, winSum=458
1297 00:43:08.665374 TX Vref=30, minBit 7, minWin=28, winSum=460
1298 00:43:08.668739 TX Vref=32, minBit 1, minWin=28, winSum=457
1299 00:43:08.675302 [TxChooseVref] Worse bit 7, Min win 28, Win sum 460, Final Vref 30
1300 00:43:08.675396
1301 00:43:08.678488 Final TX Range 1 Vref 30
1302 00:43:08.678584
1303 00:43:08.678667 ==
1304 00:43:08.682209 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 00:43:08.685671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 00:43:08.685750 ==
1307 00:43:08.685811
1308 00:43:08.685866
1309 00:43:08.689160 TX Vref Scan disable
1310 00:43:08.692460 == TX Byte 0 ==
1311 00:43:08.695566 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1312 00:43:08.698925 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1313 00:43:08.702176 == TX Byte 1 ==
1314 00:43:08.705849 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1315 00:43:08.708580 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1316 00:43:08.708671
1317 00:43:08.712456 [DATLAT]
1318 00:43:08.712545 Freq=800, CH0 RK1
1319 00:43:08.712635
1320 00:43:08.715703 DATLAT Default: 0xa
1321 00:43:08.715789 0, 0xFFFF, sum = 0
1322 00:43:08.718975 1, 0xFFFF, sum = 0
1323 00:43:08.719043 2, 0xFFFF, sum = 0
1324 00:43:08.722412 3, 0xFFFF, sum = 0
1325 00:43:08.722504 4, 0xFFFF, sum = 0
1326 00:43:08.725117 5, 0xFFFF, sum = 0
1327 00:43:08.725190 6, 0xFFFF, sum = 0
1328 00:43:08.729175 7, 0xFFFF, sum = 0
1329 00:43:08.729264 8, 0xFFFF, sum = 0
1330 00:43:08.731848 9, 0x0, sum = 1
1331 00:43:08.731937 10, 0x0, sum = 2
1332 00:43:08.735787 11, 0x0, sum = 3
1333 00:43:08.735877 12, 0x0, sum = 4
1334 00:43:08.738991 best_step = 10
1335 00:43:08.739079
1336 00:43:08.739166 ==
1337 00:43:08.742035 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 00:43:08.745541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 00:43:08.745633 ==
1340 00:43:08.748915 RX Vref Scan: 0
1341 00:43:08.749010
1342 00:43:08.749090 RX Vref 0 -> 0, step: 1
1343 00:43:08.749174
1344 00:43:08.752081 RX Delay -79 -> 252, step: 8
1345 00:43:08.759103 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1346 00:43:08.762275 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1347 00:43:08.765279 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1348 00:43:08.768754 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1349 00:43:08.772314 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1350 00:43:08.775748 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1351 00:43:08.782334 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1352 00:43:08.785889 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1353 00:43:08.788697 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1354 00:43:08.792504 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1355 00:43:08.795648 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1356 00:43:08.802441 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1357 00:43:08.805856 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1358 00:43:08.808672 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1359 00:43:08.812651 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1360 00:43:08.815966 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1361 00:43:08.819280 ==
1362 00:43:08.822551 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 00:43:08.825853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 00:43:08.825925 ==
1365 00:43:08.825987 DQS Delay:
1366 00:43:08.829282 DQS0 = 0, DQS1 = 0
1367 00:43:08.829373 DQM Delay:
1368 00:43:08.832733 DQM0 = 93, DQM1 = 83
1369 00:43:08.832801 DQ Delay:
1370 00:43:08.835394 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =92
1371 00:43:08.838861 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1372 00:43:08.842211 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1373 00:43:08.845460 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1374 00:43:08.845561
1375 00:43:08.845646
1376 00:43:08.852298 [DQSOSCAuto] RK1, (LSB)MR18= 0x491a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
1377 00:43:08.855635 CH0 RK1: MR19=606, MR18=491A
1378 00:43:08.862737 CH0_RK1: MR19=0x606, MR18=0x491A, DQSOSC=391, MR23=63, INC=96, DEC=64
1379 00:43:08.865980 [RxdqsGatingPostProcess] freq 800
1380 00:43:08.869011 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 00:43:08.872299 Pre-setting of DQS Precalculation
1382 00:43:08.878883 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 00:43:08.878962 ==
1384 00:43:08.882660 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 00:43:08.885746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 00:43:08.885825 ==
1387 00:43:08.892535 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 00:43:08.899043 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 00:43:08.906927 [CA 0] Center 36 (6~67) winsize 62
1390 00:43:08.910301 [CA 1] Center 36 (6~67) winsize 62
1391 00:43:08.913347 [CA 2] Center 35 (5~66) winsize 62
1392 00:43:08.917144 [CA 3] Center 34 (4~65) winsize 62
1393 00:43:08.920591 [CA 4] Center 34 (4~65) winsize 62
1394 00:43:08.923971 [CA 5] Center 34 (4~64) winsize 61
1395 00:43:08.924050
1396 00:43:08.927063 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1397 00:43:08.927141
1398 00:43:08.930633 [CATrainingPosCal] consider 1 rank data
1399 00:43:08.933919 u2DelayCellTimex100 = 270/100 ps
1400 00:43:08.937283 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1401 00:43:08.940653 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1402 00:43:08.943957 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1403 00:43:08.950628 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1404 00:43:08.953998 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1405 00:43:08.957260 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1406 00:43:08.957339
1407 00:43:08.960640 CA PerBit enable=1, Macro0, CA PI delay=34
1408 00:43:08.960719
1409 00:43:08.964003 [CBTSetCACLKResult] CA Dly = 34
1410 00:43:08.964081 CS Dly: 6 (0~37)
1411 00:43:08.964140 ==
1412 00:43:08.967026 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 00:43:08.974149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 00:43:08.974227 ==
1415 00:43:08.977354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 00:43:08.983830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 00:43:08.993119 [CA 0] Center 37 (6~68) winsize 63
1418 00:43:08.996403 [CA 1] Center 37 (6~68) winsize 63
1419 00:43:08.999698 [CA 2] Center 35 (4~66) winsize 63
1420 00:43:09.003029 [CA 3] Center 34 (4~65) winsize 62
1421 00:43:09.006293 [CA 4] Center 35 (5~65) winsize 61
1422 00:43:09.009961 [CA 5] Center 34 (4~65) winsize 62
1423 00:43:09.010038
1424 00:43:09.012764 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1425 00:43:09.012841
1426 00:43:09.016498 [CATrainingPosCal] consider 2 rank data
1427 00:43:09.019973 u2DelayCellTimex100 = 270/100 ps
1428 00:43:09.023006 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1429 00:43:09.026364 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1430 00:43:09.029674 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1431 00:43:09.036216 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1432 00:43:09.039550 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1433 00:43:09.043399 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1434 00:43:09.043477
1435 00:43:09.046461 CA PerBit enable=1, Macro0, CA PI delay=34
1436 00:43:09.046539
1437 00:43:09.049763 [CBTSetCACLKResult] CA Dly = 34
1438 00:43:09.049841 CS Dly: 6 (0~38)
1439 00:43:09.049901
1440 00:43:09.053036 ----->DramcWriteLeveling(PI) begin...
1441 00:43:09.053115 ==
1442 00:43:09.056473 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 00:43:09.063423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 00:43:09.063505 ==
1445 00:43:09.066683 Write leveling (Byte 0): 25 => 25
1446 00:43:09.069964 Write leveling (Byte 1): 29 => 29
1447 00:43:09.070041 DramcWriteLeveling(PI) end<-----
1448 00:43:09.070100
1449 00:43:09.073167 ==
1450 00:43:09.076376 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 00:43:09.079690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 00:43:09.079767 ==
1453 00:43:09.083018 [Gating] SW mode calibration
1454 00:43:09.090108 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 00:43:09.093408 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 00:43:09.100273 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1457 00:43:09.103680 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:43:09.106448 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:43:09.113115 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:43:09.116864 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:43:09.119860 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:43:09.126322 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:43:09.129775 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:43:09.133078 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:43:09.139911 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:43:09.142954 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:43:09.146656 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 00:43:09.149738 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:43:09.156382 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:43:09.160053 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:43:09.163568 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:43:09.170082 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1473 00:43:09.173516 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1474 00:43:09.176989 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:43:09.183403 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:43:09.186807 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 00:43:09.190107 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 00:43:09.197330 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 00:43:09.200705 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 00:43:09.204041 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 00:43:09.207419 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1482 00:43:09.214152 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1483 00:43:09.217376 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 00:43:09.220798 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 00:43:09.227093 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 00:43:09.230601 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 00:43:09.233582 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 00:43:09.240808 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 00:43:09.244132 0 10 4 | B1->B0 | 3232 2e2e | 0 1 | (0 1) (1 0)
1490 00:43:09.247246 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1491 00:43:09.254054 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 00:43:09.257339 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 00:43:09.260640 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 00:43:09.267244 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 00:43:09.270374 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 00:43:09.274323 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 00:43:09.277433 0 11 4 | B1->B0 | 2d2d 3838 | 0 0 | (0 0) (0 0)
1498 00:43:09.284059 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1499 00:43:09.287325 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 00:43:09.290689 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 00:43:09.297402 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 00:43:09.300726 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 00:43:09.304273 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 00:43:09.310871 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1505 00:43:09.313841 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1506 00:43:09.317084 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:43:09.323970 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:43:09.327214 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:43:09.330582 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:43:09.337560 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:43:09.340544 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:43:09.344294 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 00:43:09.351084 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 00:43:09.354066 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 00:43:09.357237 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 00:43:09.360840 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 00:43:09.367450 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 00:43:09.370708 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 00:43:09.373962 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 00:43:09.381081 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1521 00:43:09.384448 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1522 00:43:09.387760 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 00:43:09.391142 Total UI for P1: 0, mck2ui 16
1524 00:43:09.394563 best dqsien dly found for B0: ( 0, 14, 2)
1525 00:43:09.397876 Total UI for P1: 0, mck2ui 16
1526 00:43:09.401236 best dqsien dly found for B1: ( 0, 14, 2)
1527 00:43:09.404598 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1528 00:43:09.407939 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1529 00:43:09.408032
1530 00:43:09.411048 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1531 00:43:09.417447 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1532 00:43:09.417542 [Gating] SW calibration Done
1533 00:43:09.417646 ==
1534 00:43:09.420899 Dram Type= 6, Freq= 0, CH_1, rank 0
1535 00:43:09.427895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1536 00:43:09.427983 ==
1537 00:43:09.428059 RX Vref Scan: 0
1538 00:43:09.428129
1539 00:43:09.431112 RX Vref 0 -> 0, step: 1
1540 00:43:09.431180
1541 00:43:09.434482 RX Delay -130 -> 252, step: 16
1542 00:43:09.438074 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1543 00:43:09.440796 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1544 00:43:09.444591 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1545 00:43:09.451324 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1546 00:43:09.454338 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1547 00:43:09.457921 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1548 00:43:09.461035 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1549 00:43:09.464553 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1550 00:43:09.467590 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1551 00:43:09.474504 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1552 00:43:09.477761 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1553 00:43:09.481192 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1554 00:43:09.484302 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1555 00:43:09.491018 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1556 00:43:09.494302 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1557 00:43:09.497664 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1558 00:43:09.497735 ==
1559 00:43:09.501122 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 00:43:09.504434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 00:43:09.504504 ==
1562 00:43:09.507877 DQS Delay:
1563 00:43:09.507944 DQS0 = 0, DQS1 = 0
1564 00:43:09.508007 DQM Delay:
1565 00:43:09.511051 DQM0 = 94, DQM1 = 90
1566 00:43:09.511120 DQ Delay:
1567 00:43:09.514343 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1568 00:43:09.518331 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1569 00:43:09.521489 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1570 00:43:09.524635 DQ12 =101, DQ13 =101, DQ14 =93, DQ15 =101
1571 00:43:09.524703
1572 00:43:09.524765
1573 00:43:09.527962 ==
1574 00:43:09.528034 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 00:43:09.534710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 00:43:09.534781 ==
1577 00:43:09.534845
1578 00:43:09.534899
1579 00:43:09.538012 TX Vref Scan disable
1580 00:43:09.538082 == TX Byte 0 ==
1581 00:43:09.541085 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1582 00:43:09.548139 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1583 00:43:09.548236 == TX Byte 1 ==
1584 00:43:09.551548 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1585 00:43:09.557889 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1586 00:43:09.557958 ==
1587 00:43:09.561336 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 00:43:09.564459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 00:43:09.564530 ==
1590 00:43:09.577644 TX Vref=22, minBit 0, minWin=26, winSum=432
1591 00:43:09.581321 TX Vref=24, minBit 0, minWin=26, winSum=432
1592 00:43:09.584489 TX Vref=26, minBit 0, minWin=26, winSum=441
1593 00:43:09.587987 TX Vref=28, minBit 3, minWin=26, winSum=444
1594 00:43:09.590947 TX Vref=30, minBit 0, minWin=26, winSum=445
1595 00:43:09.594395 TX Vref=32, minBit 3, minWin=26, winSum=441
1596 00:43:09.601485 [TxChooseVref] Worse bit 0, Min win 26, Win sum 445, Final Vref 30
1597 00:43:09.601593
1598 00:43:09.604874 Final TX Range 1 Vref 30
1599 00:43:09.604950
1600 00:43:09.605006 ==
1601 00:43:09.608241 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 00:43:09.611669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 00:43:09.611767 ==
1604 00:43:09.611859
1605 00:43:09.611946
1606 00:43:09.614477 TX Vref Scan disable
1607 00:43:09.617867 == TX Byte 0 ==
1608 00:43:09.621245 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1609 00:43:09.624527 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1610 00:43:09.627793 == TX Byte 1 ==
1611 00:43:09.631758 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1612 00:43:09.635023 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1613 00:43:09.635095
1614 00:43:09.638406 [DATLAT]
1615 00:43:09.638475 Freq=800, CH1 RK0
1616 00:43:09.638529
1617 00:43:09.641166 DATLAT Default: 0xa
1618 00:43:09.641233 0, 0xFFFF, sum = 0
1619 00:43:09.645207 1, 0xFFFF, sum = 0
1620 00:43:09.645273 2, 0xFFFF, sum = 0
1621 00:43:09.647844 3, 0xFFFF, sum = 0
1622 00:43:09.647908 4, 0xFFFF, sum = 0
1623 00:43:09.651752 5, 0xFFFF, sum = 0
1624 00:43:09.651821 6, 0xFFFF, sum = 0
1625 00:43:09.654533 7, 0xFFFF, sum = 0
1626 00:43:09.654599 8, 0xFFFF, sum = 0
1627 00:43:09.657975 9, 0x0, sum = 1
1628 00:43:09.658042 10, 0x0, sum = 2
1629 00:43:09.661263 11, 0x0, sum = 3
1630 00:43:09.661337 12, 0x0, sum = 4
1631 00:43:09.665382 best_step = 10
1632 00:43:09.665457
1633 00:43:09.665516 ==
1634 00:43:09.667950 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 00:43:09.671636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 00:43:09.671708 ==
1637 00:43:09.674607 RX Vref Scan: 1
1638 00:43:09.674671
1639 00:43:09.674725 Set Vref Range= 32 -> 127
1640 00:43:09.674782
1641 00:43:09.678133 RX Vref 32 -> 127, step: 1
1642 00:43:09.678200
1643 00:43:09.681473 RX Delay -79 -> 252, step: 8
1644 00:43:09.681538
1645 00:43:09.684928 Set Vref, RX VrefLevel [Byte0]: 32
1646 00:43:09.688342 [Byte1]: 32
1647 00:43:09.688406
1648 00:43:09.691341 Set Vref, RX VrefLevel [Byte0]: 33
1649 00:43:09.695242 [Byte1]: 33
1650 00:43:09.695309
1651 00:43:09.698364 Set Vref, RX VrefLevel [Byte0]: 34
1652 00:43:09.701423 [Byte1]: 34
1653 00:43:09.705521
1654 00:43:09.705614 Set Vref, RX VrefLevel [Byte0]: 35
1655 00:43:09.708872 [Byte1]: 35
1656 00:43:09.713028
1657 00:43:09.713098 Set Vref, RX VrefLevel [Byte0]: 36
1658 00:43:09.716361 [Byte1]: 36
1659 00:43:09.720758
1660 00:43:09.720824 Set Vref, RX VrefLevel [Byte0]: 37
1661 00:43:09.724061 [Byte1]: 37
1662 00:43:09.728391
1663 00:43:09.728476 Set Vref, RX VrefLevel [Byte0]: 38
1664 00:43:09.731839 [Byte1]: 38
1665 00:43:09.735670
1666 00:43:09.735765 Set Vref, RX VrefLevel [Byte0]: 39
1667 00:43:09.738992 [Byte1]: 39
1668 00:43:09.743013
1669 00:43:09.743081 Set Vref, RX VrefLevel [Byte0]: 40
1670 00:43:09.746362 [Byte1]: 40
1671 00:43:09.751119
1672 00:43:09.751216 Set Vref, RX VrefLevel [Byte0]: 41
1673 00:43:09.754335 [Byte1]: 41
1674 00:43:09.758586
1675 00:43:09.758656 Set Vref, RX VrefLevel [Byte0]: 42
1676 00:43:09.761967 [Byte1]: 42
1677 00:43:09.765933
1678 00:43:09.766000 Set Vref, RX VrefLevel [Byte0]: 43
1679 00:43:09.772422 [Byte1]: 43
1680 00:43:09.772495
1681 00:43:09.775700 Set Vref, RX VrefLevel [Byte0]: 44
1682 00:43:09.779127 [Byte1]: 44
1683 00:43:09.779194
1684 00:43:09.782522 Set Vref, RX VrefLevel [Byte0]: 45
1685 00:43:09.785974 [Byte1]: 45
1686 00:43:09.786049
1687 00:43:09.789377 Set Vref, RX VrefLevel [Byte0]: 46
1688 00:43:09.792624 [Byte1]: 46
1689 00:43:09.796216
1690 00:43:09.796290 Set Vref, RX VrefLevel [Byte0]: 47
1691 00:43:09.799619 [Byte1]: 47
1692 00:43:09.803606
1693 00:43:09.803677 Set Vref, RX VrefLevel [Byte0]: 48
1694 00:43:09.807086 [Byte1]: 48
1695 00:43:09.811250
1696 00:43:09.811319 Set Vref, RX VrefLevel [Byte0]: 49
1697 00:43:09.814167 [Byte1]: 49
1698 00:43:09.818566
1699 00:43:09.818668 Set Vref, RX VrefLevel [Byte0]: 50
1700 00:43:09.822194 [Byte1]: 50
1701 00:43:09.826122
1702 00:43:09.826202 Set Vref, RX VrefLevel [Byte0]: 51
1703 00:43:09.830058 [Byte1]: 51
1704 00:43:09.833641
1705 00:43:09.833718 Set Vref, RX VrefLevel [Byte0]: 52
1706 00:43:09.836995 [Byte1]: 52
1707 00:43:09.841301
1708 00:43:09.841401 Set Vref, RX VrefLevel [Byte0]: 53
1709 00:43:09.844383 [Byte1]: 53
1710 00:43:09.849107
1711 00:43:09.849182 Set Vref, RX VrefLevel [Byte0]: 54
1712 00:43:09.852104 [Byte1]: 54
1713 00:43:09.856210
1714 00:43:09.856278 Set Vref, RX VrefLevel [Byte0]: 55
1715 00:43:09.859654 [Byte1]: 55
1716 00:43:09.864369
1717 00:43:09.864469 Set Vref, RX VrefLevel [Byte0]: 56
1718 00:43:09.867751 [Byte1]: 56
1719 00:43:09.871646
1720 00:43:09.871711 Set Vref, RX VrefLevel [Byte0]: 57
1721 00:43:09.874870 [Byte1]: 57
1722 00:43:09.878903
1723 00:43:09.879010 Set Vref, RX VrefLevel [Byte0]: 58
1724 00:43:09.882359 [Byte1]: 58
1725 00:43:09.886880
1726 00:43:09.886979 Set Vref, RX VrefLevel [Byte0]: 59
1727 00:43:09.890340 [Byte1]: 59
1728 00:43:09.894462
1729 00:43:09.894554 Set Vref, RX VrefLevel [Byte0]: 60
1730 00:43:09.897812 [Byte1]: 60
1731 00:43:09.901760
1732 00:43:09.901860 Set Vref, RX VrefLevel [Byte0]: 61
1733 00:43:09.905222 [Byte1]: 61
1734 00:43:09.909514
1735 00:43:09.909599 Set Vref, RX VrefLevel [Byte0]: 62
1736 00:43:09.912946 [Byte1]: 62
1737 00:43:09.916886
1738 00:43:09.916984 Set Vref, RX VrefLevel [Byte0]: 63
1739 00:43:09.920175 [Byte1]: 63
1740 00:43:09.924250
1741 00:43:09.924322 Set Vref, RX VrefLevel [Byte0]: 64
1742 00:43:09.927912 [Byte1]: 64
1743 00:43:09.931963
1744 00:43:09.932036 Set Vref, RX VrefLevel [Byte0]: 65
1745 00:43:09.935311 [Byte1]: 65
1746 00:43:09.939696
1747 00:43:09.939766 Set Vref, RX VrefLevel [Byte0]: 66
1748 00:43:09.943374 [Byte1]: 66
1749 00:43:09.947338
1750 00:43:09.947408 Set Vref, RX VrefLevel [Byte0]: 67
1751 00:43:09.950612 [Byte1]: 67
1752 00:43:09.954882
1753 00:43:09.954958 Set Vref, RX VrefLevel [Byte0]: 68
1754 00:43:09.957885 [Byte1]: 68
1755 00:43:09.961862
1756 00:43:09.961935 Set Vref, RX VrefLevel [Byte0]: 69
1757 00:43:09.965262 [Byte1]: 69
1758 00:43:09.969735
1759 00:43:09.969805 Set Vref, RX VrefLevel [Byte0]: 70
1760 00:43:09.973043 [Byte1]: 70
1761 00:43:09.977153
1762 00:43:09.977262 Set Vref, RX VrefLevel [Byte0]: 71
1763 00:43:09.980464 [Byte1]: 71
1764 00:43:09.985108
1765 00:43:09.985211 Set Vref, RX VrefLevel [Byte0]: 72
1766 00:43:09.987892 [Byte1]: 72
1767 00:43:09.992511
1768 00:43:09.992590 Set Vref, RX VrefLevel [Byte0]: 73
1769 00:43:09.995890 [Byte1]: 73
1770 00:43:10.000031
1771 00:43:10.000108 Final RX Vref Byte 0 = 56 to rank0
1772 00:43:10.003402 Final RX Vref Byte 1 = 56 to rank0
1773 00:43:10.006679 Final RX Vref Byte 0 = 56 to rank1
1774 00:43:10.009986 Final RX Vref Byte 1 = 56 to rank1==
1775 00:43:10.013128 Dram Type= 6, Freq= 0, CH_1, rank 0
1776 00:43:10.016601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1777 00:43:10.019968 ==
1778 00:43:10.020052 DQS Delay:
1779 00:43:10.020116 DQS0 = 0, DQS1 = 0
1780 00:43:10.023333 DQM Delay:
1781 00:43:10.023434 DQM0 = 95, DQM1 = 90
1782 00:43:10.026485 DQ Delay:
1783 00:43:10.026555 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1784 00:43:10.030339 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1785 00:43:10.033672 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1786 00:43:10.037103 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1787 00:43:10.040368
1788 00:43:10.040442
1789 00:43:10.047061 [DQSOSCAuto] RK0, (LSB)MR18= 0x304c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1790 00:43:10.049941 CH1 RK0: MR19=606, MR18=304C
1791 00:43:10.056932 CH1_RK0: MR19=0x606, MR18=0x304C, DQSOSC=390, MR23=63, INC=97, DEC=64
1792 00:43:10.057029
1793 00:43:10.060093 ----->DramcWriteLeveling(PI) begin...
1794 00:43:10.060174 ==
1795 00:43:10.063265 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 00:43:10.066607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 00:43:10.066691 ==
1798 00:43:10.070023 Write leveling (Byte 0): 28 => 28
1799 00:43:10.073350 Write leveling (Byte 1): 26 => 26
1800 00:43:10.076591 DramcWriteLeveling(PI) end<-----
1801 00:43:10.076674
1802 00:43:10.076734 ==
1803 00:43:10.080355 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 00:43:10.083284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 00:43:10.083356 ==
1806 00:43:10.086796 [Gating] SW mode calibration
1807 00:43:10.093458 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1808 00:43:10.099828 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1809 00:43:10.103647 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1810 00:43:10.106528 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1811 00:43:10.113718 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 00:43:10.117016 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 00:43:10.120279 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 00:43:10.127062 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 00:43:10.130268 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:43:10.133447 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 00:43:10.136807 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:43:10.144023 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:43:10.147336 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:43:10.150631 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:43:10.157328 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:43:10.160665 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 00:43:10.163958 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 00:43:10.170383 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 00:43:10.173742 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1826 00:43:10.176926 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1827 00:43:10.183937 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1828 00:43:10.187162 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:43:10.190582 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:43:10.197471 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:43:10.200715 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:43:10.203876 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:43:10.207385 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:43:10.214073 0 9 4 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)
1835 00:43:10.217279 0 9 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1836 00:43:10.220256 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 00:43:10.227261 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 00:43:10.230661 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 00:43:10.233888 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 00:43:10.240590 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 00:43:10.244126 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1842 00:43:10.247402 0 10 4 | B1->B0 | 2a2a 2f2f | 0 1 | (0 1) (1 0)
1843 00:43:10.253953 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 00:43:10.257193 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 00:43:10.260362 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 00:43:10.267295 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 00:43:10.270736 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 00:43:10.274175 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 00:43:10.280836 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 00:43:10.283865 0 11 4 | B1->B0 | 3838 3030 | 0 0 | (0 0) (0 0)
1851 00:43:10.287423 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
1852 00:43:10.291029 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 00:43:10.297373 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 00:43:10.300928 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 00:43:10.304265 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 00:43:10.311119 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 00:43:10.314305 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 00:43:10.317637 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1859 00:43:10.323972 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 00:43:10.327312 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 00:43:10.330813 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 00:43:10.337294 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 00:43:10.341101 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 00:43:10.344429 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 00:43:10.350717 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 00:43:10.353796 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 00:43:10.357502 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 00:43:10.364036 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 00:43:10.367509 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 00:43:10.370660 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 00:43:10.374095 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 00:43:10.380902 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 00:43:10.384201 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1874 00:43:10.387549 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1875 00:43:10.394231 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 00:43:10.397478 Total UI for P1: 0, mck2ui 16
1877 00:43:10.400783 best dqsien dly found for B0: ( 0, 14, 6)
1878 00:43:10.404506 Total UI for P1: 0, mck2ui 16
1879 00:43:10.407203 best dqsien dly found for B1: ( 0, 14, 2)
1880 00:43:10.410707 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1881 00:43:10.414187 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1882 00:43:10.414264
1883 00:43:10.417418 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1884 00:43:10.420573 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1885 00:43:10.424399 [Gating] SW calibration Done
1886 00:43:10.424476 ==
1887 00:43:10.427732 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 00:43:10.431029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1889 00:43:10.431107 ==
1890 00:43:10.434274 RX Vref Scan: 0
1891 00:43:10.434352
1892 00:43:10.434411 RX Vref 0 -> 0, step: 1
1893 00:43:10.434467
1894 00:43:10.437949 RX Delay -130 -> 252, step: 16
1895 00:43:10.441241 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1896 00:43:10.447647 iDelay=222, Bit 1, Center 93 (-2 ~ 189) 192
1897 00:43:10.451165 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1898 00:43:10.454495 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1899 00:43:10.457822 iDelay=222, Bit 4, Center 93 (-2 ~ 189) 192
1900 00:43:10.461319 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1901 00:43:10.464557 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1902 00:43:10.470983 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1903 00:43:10.474080 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1904 00:43:10.477779 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1905 00:43:10.480996 iDelay=222, Bit 10, Center 101 (-2 ~ 205) 208
1906 00:43:10.484285 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1907 00:43:10.490993 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1908 00:43:10.494377 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1909 00:43:10.497719 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1910 00:43:10.501079 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1911 00:43:10.501148 ==
1912 00:43:10.504377 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 00:43:10.511060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 00:43:10.511131 ==
1915 00:43:10.511195 DQS Delay:
1916 00:43:10.514466 DQS0 = 0, DQS1 = 0
1917 00:43:10.514535 DQM Delay:
1918 00:43:10.514591 DQM0 = 97, DQM1 = 93
1919 00:43:10.517884 DQ Delay:
1920 00:43:10.521040 DQ0 =101, DQ1 =93, DQ2 =85, DQ3 =93
1921 00:43:10.524704 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =101
1922 00:43:10.527667 DQ8 =77, DQ9 =77, DQ10 =101, DQ11 =85
1923 00:43:10.530856 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1924 00:43:10.530924
1925 00:43:10.530979
1926 00:43:10.531032 ==
1927 00:43:10.534164 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 00:43:10.537672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 00:43:10.537739 ==
1930 00:43:10.537801
1931 00:43:10.537854
1932 00:43:10.541331 TX Vref Scan disable
1933 00:43:10.544546 == TX Byte 0 ==
1934 00:43:10.547711 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1935 00:43:10.550888 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1936 00:43:10.554559 == TX Byte 1 ==
1937 00:43:10.557543 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1938 00:43:10.561377 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1939 00:43:10.561462 ==
1940 00:43:10.564705 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 00:43:10.567948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 00:43:10.571255 ==
1943 00:43:10.582691 TX Vref=22, minBit 1, minWin=27, winSum=444
1944 00:43:10.585982 TX Vref=24, minBit 1, minWin=27, winSum=449
1945 00:43:10.589358 TX Vref=26, minBit 1, minWin=27, winSum=450
1946 00:43:10.592632 TX Vref=28, minBit 1, minWin=27, winSum=454
1947 00:43:10.595874 TX Vref=30, minBit 1, minWin=27, winSum=452
1948 00:43:10.599387 TX Vref=32, minBit 0, minWin=27, winSum=448
1949 00:43:10.606151 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 28
1950 00:43:10.606228
1951 00:43:10.609299 Final TX Range 1 Vref 28
1952 00:43:10.609381
1953 00:43:10.609467 ==
1954 00:43:10.612657 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 00:43:10.615916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 00:43:10.615993 ==
1957 00:43:10.616052
1958 00:43:10.616107
1959 00:43:10.619242 TX Vref Scan disable
1960 00:43:10.622585 == TX Byte 0 ==
1961 00:43:10.625990 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1962 00:43:10.629363 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1963 00:43:10.632690 == TX Byte 1 ==
1964 00:43:10.636011 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1965 00:43:10.639358 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1966 00:43:10.642592
1967 00:43:10.642662 [DATLAT]
1968 00:43:10.642719 Freq=800, CH1 RK1
1969 00:43:10.642773
1970 00:43:10.646059 DATLAT Default: 0xa
1971 00:43:10.646121 0, 0xFFFF, sum = 0
1972 00:43:10.649124 1, 0xFFFF, sum = 0
1973 00:43:10.649189 2, 0xFFFF, sum = 0
1974 00:43:10.652763 3, 0xFFFF, sum = 0
1975 00:43:10.652825 4, 0xFFFF, sum = 0
1976 00:43:10.655973 5, 0xFFFF, sum = 0
1977 00:43:10.656035 6, 0xFFFF, sum = 0
1978 00:43:10.659250 7, 0xFFFF, sum = 0
1979 00:43:10.662432 8, 0xFFFF, sum = 0
1980 00:43:10.662497 9, 0x0, sum = 1
1981 00:43:10.662552 10, 0x0, sum = 2
1982 00:43:10.665704 11, 0x0, sum = 3
1983 00:43:10.665775 12, 0x0, sum = 4
1984 00:43:10.669154 best_step = 10
1985 00:43:10.669216
1986 00:43:10.669277 ==
1987 00:43:10.672813 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 00:43:10.675800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 00:43:10.675870 ==
1990 00:43:10.679152 RX Vref Scan: 0
1991 00:43:10.679217
1992 00:43:10.679277 RX Vref 0 -> 0, step: 1
1993 00:43:10.679331
1994 00:43:10.682303 RX Delay -79 -> 252, step: 8
1995 00:43:10.689477 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1996 00:43:10.692637 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1997 00:43:10.695950 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1998 00:43:10.699354 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1999 00:43:10.702720 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2000 00:43:10.709467 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2001 00:43:10.712789 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2002 00:43:10.715866 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2003 00:43:10.719428 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2004 00:43:10.722350 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2005 00:43:10.725691 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2006 00:43:10.732728 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2007 00:43:10.736080 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2008 00:43:10.739439 iDelay=209, Bit 13, Center 100 (1 ~ 200) 200
2009 00:43:10.742762 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2010 00:43:10.746173 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2011 00:43:10.749578 ==
2012 00:43:10.749668 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 00:43:10.756110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 00:43:10.756185 ==
2015 00:43:10.756244 DQS Delay:
2016 00:43:10.759375 DQS0 = 0, DQS1 = 0
2017 00:43:10.759451 DQM Delay:
2018 00:43:10.759509 DQM0 = 97, DQM1 = 92
2019 00:43:10.762655 DQ Delay:
2020 00:43:10.765973 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2021 00:43:10.769220 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2022 00:43:10.772697 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2023 00:43:10.776193 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =96
2024 00:43:10.776285
2025 00:43:10.776344
2026 00:43:10.782604 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
2027 00:43:10.786244 CH1 RK1: MR19=606, MR18=4D16
2028 00:43:10.792960 CH1_RK1: MR19=0x606, MR18=0x4D16, DQSOSC=390, MR23=63, INC=97, DEC=64
2029 00:43:10.796403 [RxdqsGatingPostProcess] freq 800
2030 00:43:10.799298 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2031 00:43:10.802684 Pre-setting of DQS Precalculation
2032 00:43:10.809421 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2033 00:43:10.816016 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2034 00:43:10.822781 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2035 00:43:10.822858
2036 00:43:10.822916
2037 00:43:10.826035 [Calibration Summary] 1600 Mbps
2038 00:43:10.826110 CH 0, Rank 0
2039 00:43:10.829423 SW Impedance : PASS
2040 00:43:10.832724 DUTY Scan : NO K
2041 00:43:10.832793 ZQ Calibration : PASS
2042 00:43:10.835874 Jitter Meter : NO K
2043 00:43:10.839300 CBT Training : PASS
2044 00:43:10.839361 Write leveling : PASS
2045 00:43:10.842560 RX DQS gating : PASS
2046 00:43:10.846424 RX DQ/DQS(RDDQC) : PASS
2047 00:43:10.846493 TX DQ/DQS : PASS
2048 00:43:10.849826 RX DATLAT : PASS
2049 00:43:10.853259 RX DQ/DQS(Engine): PASS
2050 00:43:10.853321 TX OE : NO K
2051 00:43:10.853393 All Pass.
2052 00:43:10.856667
2053 00:43:10.856728 CH 0, Rank 1
2054 00:43:10.859851 SW Impedance : PASS
2055 00:43:10.859913 DUTY Scan : NO K
2056 00:43:10.863068 ZQ Calibration : PASS
2057 00:43:10.863126 Jitter Meter : NO K
2058 00:43:10.866361 CBT Training : PASS
2059 00:43:10.869683 Write leveling : PASS
2060 00:43:10.869750 RX DQS gating : PASS
2061 00:43:10.873045 RX DQ/DQS(RDDQC) : PASS
2062 00:43:10.876267 TX DQ/DQS : PASS
2063 00:43:10.876334 RX DATLAT : PASS
2064 00:43:10.879824 RX DQ/DQS(Engine): PASS
2065 00:43:10.883466 TX OE : NO K
2066 00:43:10.883533 All Pass.
2067 00:43:10.883597
2068 00:43:10.883689 CH 1, Rank 0
2069 00:43:10.886681 SW Impedance : PASS
2070 00:43:10.889898 DUTY Scan : NO K
2071 00:43:10.889961 ZQ Calibration : PASS
2072 00:43:10.893151 Jitter Meter : NO K
2073 00:43:10.896448 CBT Training : PASS
2074 00:43:10.896535 Write leveling : PASS
2075 00:43:10.899707 RX DQS gating : PASS
2076 00:43:10.899794 RX DQ/DQS(RDDQC) : PASS
2077 00:43:10.902962 TX DQ/DQS : PASS
2078 00:43:10.906390 RX DATLAT : PASS
2079 00:43:10.906451 RX DQ/DQS(Engine): PASS
2080 00:43:10.910317 TX OE : NO K
2081 00:43:10.910381 All Pass.
2082 00:43:10.910441
2083 00:43:10.913424 CH 1, Rank 1
2084 00:43:10.913482 SW Impedance : PASS
2085 00:43:10.916952 DUTY Scan : NO K
2086 00:43:10.919648 ZQ Calibration : PASS
2087 00:43:10.919745 Jitter Meter : NO K
2088 00:43:10.923512 CBT Training : PASS
2089 00:43:10.926610 Write leveling : PASS
2090 00:43:10.926680 RX DQS gating : PASS
2091 00:43:10.929837 RX DQ/DQS(RDDQC) : PASS
2092 00:43:10.933239 TX DQ/DQS : PASS
2093 00:43:10.933337 RX DATLAT : PASS
2094 00:43:10.936645 RX DQ/DQS(Engine): PASS
2095 00:43:10.936767 TX OE : NO K
2096 00:43:10.939977 All Pass.
2097 00:43:10.940069
2098 00:43:10.940171 DramC Write-DBI off
2099 00:43:10.943333 PER_BANK_REFRESH: Hybrid Mode
2100 00:43:10.946626 TX_TRACKING: ON
2101 00:43:10.949938 [GetDramInforAfterCalByMRR] Vendor 6.
2102 00:43:10.953116 [GetDramInforAfterCalByMRR] Revision 606.
2103 00:43:10.956606 [GetDramInforAfterCalByMRR] Revision 2 0.
2104 00:43:10.956702 MR0 0x3b3b
2105 00:43:10.956784 MR8 0x5151
2106 00:43:10.963211 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 00:43:10.963287
2108 00:43:10.963366 MR0 0x3b3b
2109 00:43:10.963463 MR8 0x5151
2110 00:43:10.966740 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 00:43:10.966863
2112 00:43:10.976871 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2113 00:43:10.979584 [FAST_K] Save calibration result to emmc
2114 00:43:10.982928 [FAST_K] Save calibration result to emmc
2115 00:43:10.986716 dram_init: config_dvfs: 1
2116 00:43:10.989849 dramc_set_vcore_voltage set vcore to 662500
2117 00:43:10.993355 Read voltage for 1200, 2
2118 00:43:10.993443 Vio18 = 0
2119 00:43:10.993500 Vcore = 662500
2120 00:43:10.996645 Vdram = 0
2121 00:43:10.996711 Vddq = 0
2122 00:43:10.996773 Vmddr = 0
2123 00:43:11.003146 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2124 00:43:11.006364 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2125 00:43:11.009797 MEM_TYPE=3, freq_sel=15
2126 00:43:11.013122 sv_algorithm_assistance_LP4_1600
2127 00:43:11.016493 ============ PULL DRAM RESETB DOWN ============
2128 00:43:11.019850 ========== PULL DRAM RESETB DOWN end =========
2129 00:43:11.026591 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2130 00:43:11.029864 ===================================
2131 00:43:11.029933 LPDDR4 DRAM CONFIGURATION
2132 00:43:11.033193 ===================================
2133 00:43:11.037001 EX_ROW_EN[0] = 0x0
2134 00:43:11.040415 EX_ROW_EN[1] = 0x0
2135 00:43:11.040494 LP4Y_EN = 0x0
2136 00:43:11.043547 WORK_FSP = 0x0
2137 00:43:11.043624 WL = 0x4
2138 00:43:11.046779 RL = 0x4
2139 00:43:11.046857 BL = 0x2
2140 00:43:11.050377 RPST = 0x0
2141 00:43:11.050455 RD_PRE = 0x0
2142 00:43:11.053802 WR_PRE = 0x1
2143 00:43:11.053880 WR_PST = 0x0
2144 00:43:11.056782 DBI_WR = 0x0
2145 00:43:11.056859 DBI_RD = 0x0
2146 00:43:11.060527 OTF = 0x1
2147 00:43:11.063883 ===================================
2148 00:43:11.067170 ===================================
2149 00:43:11.067247 ANA top config
2150 00:43:11.070311 ===================================
2151 00:43:11.073918 DLL_ASYNC_EN = 0
2152 00:43:11.076839 ALL_SLAVE_EN = 0
2153 00:43:11.076916 NEW_RANK_MODE = 1
2154 00:43:11.080070 DLL_IDLE_MODE = 1
2155 00:43:11.083494 LP45_APHY_COMB_EN = 1
2156 00:43:11.087006 TX_ODT_DIS = 1
2157 00:43:11.090505 NEW_8X_MODE = 1
2158 00:43:11.093701 ===================================
2159 00:43:11.096955 ===================================
2160 00:43:11.097032 data_rate = 2400
2161 00:43:11.100072 CKR = 1
2162 00:43:11.103627 DQ_P2S_RATIO = 8
2163 00:43:11.107333 ===================================
2164 00:43:11.110628 CA_P2S_RATIO = 8
2165 00:43:11.114017 DQ_CA_OPEN = 0
2166 00:43:11.116771 DQ_SEMI_OPEN = 0
2167 00:43:11.116848 CA_SEMI_OPEN = 0
2168 00:43:11.120648 CA_FULL_RATE = 0
2169 00:43:11.123344 DQ_CKDIV4_EN = 0
2170 00:43:11.126813 CA_CKDIV4_EN = 0
2171 00:43:11.130063 CA_PREDIV_EN = 0
2172 00:43:11.133323 PH8_DLY = 17
2173 00:43:11.133400 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2174 00:43:11.137330 DQ_AAMCK_DIV = 4
2175 00:43:11.140546 CA_AAMCK_DIV = 4
2176 00:43:11.143634 CA_ADMCK_DIV = 4
2177 00:43:11.147072 DQ_TRACK_CA_EN = 0
2178 00:43:11.150428 CA_PICK = 1200
2179 00:43:11.150507 CA_MCKIO = 1200
2180 00:43:11.153735 MCKIO_SEMI = 0
2181 00:43:11.157158 PLL_FREQ = 2366
2182 00:43:11.160689 DQ_UI_PI_RATIO = 32
2183 00:43:11.163860 CA_UI_PI_RATIO = 0
2184 00:43:11.166864 ===================================
2185 00:43:11.170382 ===================================
2186 00:43:11.173751 memory_type:LPDDR4
2187 00:43:11.173829 GP_NUM : 10
2188 00:43:11.176860 SRAM_EN : 1
2189 00:43:11.176937 MD32_EN : 0
2190 00:43:11.180372 ===================================
2191 00:43:11.183682 [ANA_INIT] >>>>>>>>>>>>>>
2192 00:43:11.187072 <<<<<< [CONFIGURE PHASE]: ANA_TX
2193 00:43:11.190081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2194 00:43:11.193226 ===================================
2195 00:43:11.196660 data_rate = 2400,PCW = 0X5b00
2196 00:43:11.200093 ===================================
2197 00:43:11.203300 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2198 00:43:11.210514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 00:43:11.213237 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 00:43:11.220364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2201 00:43:11.223369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2202 00:43:11.226656 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2203 00:43:11.226736 [ANA_INIT] flow start
2204 00:43:11.230085 [ANA_INIT] PLL >>>>>>>>
2205 00:43:11.233423 [ANA_INIT] PLL <<<<<<<<
2206 00:43:11.233501 [ANA_INIT] MIDPI >>>>>>>>
2207 00:43:11.236722 [ANA_INIT] MIDPI <<<<<<<<
2208 00:43:11.240024 [ANA_INIT] DLL >>>>>>>>
2209 00:43:11.240103 [ANA_INIT] DLL <<<<<<<<
2210 00:43:11.243372 [ANA_INIT] flow end
2211 00:43:11.247282 ============ LP4 DIFF to SE enter ============
2212 00:43:11.250591 ============ LP4 DIFF to SE exit ============
2213 00:43:11.253922 [ANA_INIT] <<<<<<<<<<<<<
2214 00:43:11.256733 [Flow] Enable top DCM control >>>>>
2215 00:43:11.260076 [Flow] Enable top DCM control <<<<<
2216 00:43:11.263444 Enable DLL master slave shuffle
2217 00:43:11.270008 ==============================================================
2218 00:43:11.270086 Gating Mode config
2219 00:43:11.277386 ==============================================================
2220 00:43:11.277483 Config description:
2221 00:43:11.287099 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2222 00:43:11.293944 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2223 00:43:11.300498 SELPH_MODE 0: By rank 1: By Phase
2224 00:43:11.303864 ==============================================================
2225 00:43:11.306954 GAT_TRACK_EN = 1
2226 00:43:11.310291 RX_GATING_MODE = 2
2227 00:43:11.314030 RX_GATING_TRACK_MODE = 2
2228 00:43:11.317214 SELPH_MODE = 1
2229 00:43:11.320575 PICG_EARLY_EN = 1
2230 00:43:11.324030 VALID_LAT_VALUE = 1
2231 00:43:11.326926 ==============================================================
2232 00:43:11.330272 Enter into Gating configuration >>>>
2233 00:43:11.333863 Exit from Gating configuration <<<<
2234 00:43:11.337011 Enter into DVFS_PRE_config >>>>>
2235 00:43:11.350629 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2236 00:43:11.350711 Exit from DVFS_PRE_config <<<<<
2237 00:43:11.353842 Enter into PICG configuration >>>>
2238 00:43:11.357123 Exit from PICG configuration <<<<
2239 00:43:11.360462 [RX_INPUT] configuration >>>>>
2240 00:43:11.363870 [RX_INPUT] configuration <<<<<
2241 00:43:11.370706 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2242 00:43:11.374013 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2243 00:43:11.380674 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 00:43:11.387437 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 00:43:11.394100 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 00:43:11.400763 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 00:43:11.404439 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2248 00:43:11.407415 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2249 00:43:11.411007 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2250 00:43:11.417560 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2251 00:43:11.420807 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2252 00:43:11.424264 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2253 00:43:11.427730 ===================================
2254 00:43:11.431138 LPDDR4 DRAM CONFIGURATION
2255 00:43:11.434332 ===================================
2256 00:43:11.434411 EX_ROW_EN[0] = 0x0
2257 00:43:11.437635 EX_ROW_EN[1] = 0x0
2258 00:43:11.437713 LP4Y_EN = 0x0
2259 00:43:11.440745 WORK_FSP = 0x0
2260 00:43:11.440823 WL = 0x4
2261 00:43:11.444329 RL = 0x4
2262 00:43:11.444407 BL = 0x2
2263 00:43:11.447787 RPST = 0x0
2264 00:43:11.450898 RD_PRE = 0x0
2265 00:43:11.450976 WR_PRE = 0x1
2266 00:43:11.454153 WR_PST = 0x0
2267 00:43:11.454231 DBI_WR = 0x0
2268 00:43:11.457706 DBI_RD = 0x0
2269 00:43:11.457807 OTF = 0x1
2270 00:43:11.460890 ===================================
2271 00:43:11.464231 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2272 00:43:11.467622 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2273 00:43:11.473999 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2274 00:43:11.477353 ===================================
2275 00:43:11.480747 LPDDR4 DRAM CONFIGURATION
2276 00:43:11.484165 ===================================
2277 00:43:11.484235 EX_ROW_EN[0] = 0x10
2278 00:43:11.487474 EX_ROW_EN[1] = 0x0
2279 00:43:11.487562 LP4Y_EN = 0x0
2280 00:43:11.490814 WORK_FSP = 0x0
2281 00:43:11.490887 WL = 0x4
2282 00:43:11.494247 RL = 0x4
2283 00:43:11.494316 BL = 0x2
2284 00:43:11.497631 RPST = 0x0
2285 00:43:11.497700 RD_PRE = 0x0
2286 00:43:11.501103 WR_PRE = 0x1
2287 00:43:11.501175 WR_PST = 0x0
2288 00:43:11.504435 DBI_WR = 0x0
2289 00:43:11.504502 DBI_RD = 0x0
2290 00:43:11.507757 OTF = 0x1
2291 00:43:11.511001 ===================================
2292 00:43:11.517717 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2293 00:43:11.517795 ==
2294 00:43:11.520974 Dram Type= 6, Freq= 0, CH_0, rank 0
2295 00:43:11.524769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2296 00:43:11.524838 ==
2297 00:43:11.527802 [Duty_Offset_Calibration]
2298 00:43:11.527873 B0:2 B1:1 CA:1
2299 00:43:11.527928
2300 00:43:11.531217 [DutyScan_Calibration_Flow] k_type=0
2301 00:43:11.541467
2302 00:43:11.541569 ==CLK 0==
2303 00:43:11.545184 Final CLK duty delay cell = 0
2304 00:43:11.547986 [0] MAX Duty = 5218%(X100), DQS PI = 24
2305 00:43:11.551706 [0] MIN Duty = 4875%(X100), DQS PI = 0
2306 00:43:11.551810 [0] AVG Duty = 5046%(X100)
2307 00:43:11.554986
2308 00:43:11.555063 CH0 CLK Duty spec in!! Max-Min= 343%
2309 00:43:11.561413 [DutyScan_Calibration_Flow] ====Done====
2310 00:43:11.561514
2311 00:43:11.564588 [DutyScan_Calibration_Flow] k_type=1
2312 00:43:11.580086
2313 00:43:11.580164 ==DQS 0 ==
2314 00:43:11.583559 Final DQS duty delay cell = -4
2315 00:43:11.586745 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2316 00:43:11.590174 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2317 00:43:11.593124 [-4] AVG Duty = 4937%(X100)
2318 00:43:11.593201
2319 00:43:11.593261 ==DQS 1 ==
2320 00:43:11.597004 Final DQS duty delay cell = 0
2321 00:43:11.600426 [0] MAX Duty = 5156%(X100), DQS PI = 14
2322 00:43:11.603773 [0] MIN Duty = 5000%(X100), DQS PI = 34
2323 00:43:11.607215 [0] AVG Duty = 5078%(X100)
2324 00:43:11.607292
2325 00:43:11.609934 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2326 00:43:11.610012
2327 00:43:11.613285 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2328 00:43:11.617234 [DutyScan_Calibration_Flow] ====Done====
2329 00:43:11.617311
2330 00:43:11.620468 [DutyScan_Calibration_Flow] k_type=3
2331 00:43:11.637088
2332 00:43:11.637165 ==DQM 0 ==
2333 00:43:11.640344 Final DQM duty delay cell = 0
2334 00:43:11.643401 [0] MAX Duty = 5156%(X100), DQS PI = 30
2335 00:43:11.646916 [0] MIN Duty = 4906%(X100), DQS PI = 50
2336 00:43:11.646993 [0] AVG Duty = 5031%(X100)
2337 00:43:11.650190
2338 00:43:11.650266 ==DQM 1 ==
2339 00:43:11.653500 Final DQM duty delay cell = 0
2340 00:43:11.657200 [0] MAX Duty = 5093%(X100), DQS PI = 0
2341 00:43:11.660449 [0] MIN Duty = 5031%(X100), DQS PI = 14
2342 00:43:11.660528 [0] AVG Duty = 5062%(X100)
2343 00:43:11.660587
2344 00:43:11.667206 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2345 00:43:11.667283
2346 00:43:11.670578 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2347 00:43:11.673468 [DutyScan_Calibration_Flow] ====Done====
2348 00:43:11.673545
2349 00:43:11.676700 [DutyScan_Calibration_Flow] k_type=2
2350 00:43:11.693254
2351 00:43:11.693354 ==DQ 0 ==
2352 00:43:11.696630 Final DQ duty delay cell = 0
2353 00:43:11.700449 [0] MAX Duty = 5062%(X100), DQS PI = 32
2354 00:43:11.703475 [0] MIN Duty = 4875%(X100), DQS PI = 0
2355 00:43:11.703543 [0] AVG Duty = 4968%(X100)
2356 00:43:11.703605
2357 00:43:11.707013 ==DQ 1 ==
2358 00:43:11.707082 Final DQ duty delay cell = 0
2359 00:43:11.713201 [0] MAX Duty = 5093%(X100), DQS PI = 24
2360 00:43:11.716537 [0] MIN Duty = 4907%(X100), DQS PI = 36
2361 00:43:11.716611 [0] AVG Duty = 5000%(X100)
2362 00:43:11.716678
2363 00:43:11.719917 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2364 00:43:11.719991
2365 00:43:11.723121 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2366 00:43:11.729734 [DutyScan_Calibration_Flow] ====Done====
2367 00:43:11.729833 ==
2368 00:43:11.733153 Dram Type= 6, Freq= 0, CH_1, rank 0
2369 00:43:11.736649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2370 00:43:11.736717 ==
2371 00:43:11.739918 [Duty_Offset_Calibration]
2372 00:43:11.739989 B0:1 B1:0 CA:0
2373 00:43:11.740044
2374 00:43:11.743327 [DutyScan_Calibration_Flow] k_type=0
2375 00:43:11.752441
2376 00:43:11.752516 ==CLK 0==
2377 00:43:11.755539 Final CLK duty delay cell = -4
2378 00:43:11.759305 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2379 00:43:11.762376 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2380 00:43:11.765871 [-4] AVG Duty = 4937%(X100)
2381 00:43:11.765943
2382 00:43:11.769001 CH1 CLK Duty spec in!! Max-Min= 125%
2383 00:43:11.772435 [DutyScan_Calibration_Flow] ====Done====
2384 00:43:11.772513
2385 00:43:11.775674 [DutyScan_Calibration_Flow] k_type=1
2386 00:43:11.792086
2387 00:43:11.792168 ==DQS 0 ==
2388 00:43:11.795382 Final DQS duty delay cell = 0
2389 00:43:11.798666 [0] MAX Duty = 5062%(X100), DQS PI = 24
2390 00:43:11.802032 [0] MIN Duty = 4844%(X100), DQS PI = 0
2391 00:43:11.802125 [0] AVG Duty = 4953%(X100)
2392 00:43:11.805324
2393 00:43:11.805388 ==DQS 1 ==
2394 00:43:11.809050 Final DQS duty delay cell = 0
2395 00:43:11.812251 [0] MAX Duty = 5218%(X100), DQS PI = 20
2396 00:43:11.815381 [0] MIN Duty = 4969%(X100), DQS PI = 8
2397 00:43:11.815450 [0] AVG Duty = 5093%(X100)
2398 00:43:11.818847
2399 00:43:11.822351 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2400 00:43:11.822446
2401 00:43:11.825386 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2402 00:43:11.829165 [DutyScan_Calibration_Flow] ====Done====
2403 00:43:11.829237
2404 00:43:11.831981 [DutyScan_Calibration_Flow] k_type=3
2405 00:43:11.848473
2406 00:43:11.848547 ==DQM 0 ==
2407 00:43:11.852415 Final DQM duty delay cell = 0
2408 00:43:11.855695 [0] MAX Duty = 5156%(X100), DQS PI = 8
2409 00:43:11.858841 [0] MIN Duty = 5000%(X100), DQS PI = 62
2410 00:43:11.858908 [0] AVG Duty = 5078%(X100)
2411 00:43:11.858965
2412 00:43:11.861794 ==DQM 1 ==
2413 00:43:11.865198 Final DQM duty delay cell = 0
2414 00:43:11.869205 [0] MAX Duty = 5031%(X100), DQS PI = 16
2415 00:43:11.872403 [0] MIN Duty = 4875%(X100), DQS PI = 36
2416 00:43:11.872473 [0] AVG Duty = 4953%(X100)
2417 00:43:11.872531
2418 00:43:11.878925 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2419 00:43:11.879001
2420 00:43:11.881977 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2421 00:43:11.886073 [DutyScan_Calibration_Flow] ====Done====
2422 00:43:11.886147
2423 00:43:11.888585 [DutyScan_Calibration_Flow] k_type=2
2424 00:43:11.904517
2425 00:43:11.904591 ==DQ 0 ==
2426 00:43:11.907880 Final DQ duty delay cell = -4
2427 00:43:11.911175 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2428 00:43:11.914332 [-4] MIN Duty = 4906%(X100), DQS PI = 38
2429 00:43:11.917704 [-4] AVG Duty = 4984%(X100)
2430 00:43:11.917771
2431 00:43:11.917826 ==DQ 1 ==
2432 00:43:11.921739 Final DQ duty delay cell = 0
2433 00:43:11.924530 [0] MAX Duty = 5125%(X100), DQS PI = 20
2434 00:43:11.927776 [0] MIN Duty = 4938%(X100), DQS PI = 34
2435 00:43:11.927842 [0] AVG Duty = 5031%(X100)
2436 00:43:11.931549
2437 00:43:11.934751 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2438 00:43:11.934818
2439 00:43:11.938333 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2440 00:43:11.941100 [DutyScan_Calibration_Flow] ====Done====
2441 00:43:11.944552 nWR fixed to 30
2442 00:43:11.944671 [ModeRegInit_LP4] CH0 RK0
2443 00:43:11.947792 [ModeRegInit_LP4] CH0 RK1
2444 00:43:11.951288 [ModeRegInit_LP4] CH1 RK0
2445 00:43:11.954510 [ModeRegInit_LP4] CH1 RK1
2446 00:43:11.954623 match AC timing 7
2447 00:43:11.958113 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2448 00:43:11.964714 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2449 00:43:11.967904 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2450 00:43:11.971206 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2451 00:43:11.978018 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2452 00:43:11.978091 ==
2453 00:43:11.981307 Dram Type= 6, Freq= 0, CH_0, rank 0
2454 00:43:11.984592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2455 00:43:11.984660 ==
2456 00:43:11.991026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2457 00:43:11.994672 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2458 00:43:12.004522 [CA 0] Center 39 (8~70) winsize 63
2459 00:43:12.008317 [CA 1] Center 39 (8~70) winsize 63
2460 00:43:12.011303 [CA 2] Center 35 (5~66) winsize 62
2461 00:43:12.014668 [CA 3] Center 34 (4~65) winsize 62
2462 00:43:12.018528 [CA 4] Center 33 (3~64) winsize 62
2463 00:43:12.021791 [CA 5] Center 32 (3~62) winsize 60
2464 00:43:12.021892
2465 00:43:12.025222 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2466 00:43:12.025314
2467 00:43:12.028577 [CATrainingPosCal] consider 1 rank data
2468 00:43:12.031875 u2DelayCellTimex100 = 270/100 ps
2469 00:43:12.034831 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2470 00:43:12.038223 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2471 00:43:12.044847 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2472 00:43:12.048542 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2473 00:43:12.051332 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2474 00:43:12.054708 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2475 00:43:12.054780
2476 00:43:12.058406 CA PerBit enable=1, Macro0, CA PI delay=32
2477 00:43:12.058476
2478 00:43:12.061542 [CBTSetCACLKResult] CA Dly = 32
2479 00:43:12.061626 CS Dly: 6 (0~37)
2480 00:43:12.061701 ==
2481 00:43:12.064813 Dram Type= 6, Freq= 0, CH_0, rank 1
2482 00:43:12.071490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2483 00:43:12.071568 ==
2484 00:43:12.075210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2485 00:43:12.081754 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2486 00:43:12.090221 [CA 0] Center 38 (8~69) winsize 62
2487 00:43:12.093595 [CA 1] Center 38 (8~69) winsize 62
2488 00:43:12.096880 [CA 2] Center 35 (4~66) winsize 63
2489 00:43:12.100497 [CA 3] Center 34 (4~65) winsize 62
2490 00:43:12.103587 [CA 4] Center 33 (3~63) winsize 61
2491 00:43:12.106917 [CA 5] Center 32 (3~62) winsize 60
2492 00:43:12.106998
2493 00:43:12.110790 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2494 00:43:12.110866
2495 00:43:12.114029 [CATrainingPosCal] consider 2 rank data
2496 00:43:12.117298 u2DelayCellTimex100 = 270/100 ps
2497 00:43:12.120705 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2498 00:43:12.124081 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2499 00:43:12.130438 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2500 00:43:12.134181 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2501 00:43:12.136929 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2502 00:43:12.140221 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2503 00:43:12.140298
2504 00:43:12.143648 CA PerBit enable=1, Macro0, CA PI delay=32
2505 00:43:12.143725
2506 00:43:12.147006 [CBTSetCACLKResult] CA Dly = 32
2507 00:43:12.147085 CS Dly: 7 (0~39)
2508 00:43:12.147169
2509 00:43:12.150956 ----->DramcWriteLeveling(PI) begin...
2510 00:43:12.153881 ==
2511 00:43:12.153965 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 00:43:12.161132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 00:43:12.161217 ==
2514 00:43:12.164332 Write leveling (Byte 0): 34 => 34
2515 00:43:12.167628 Write leveling (Byte 1): 30 => 30
2516 00:43:12.167706 DramcWriteLeveling(PI) end<-----
2517 00:43:12.170870
2518 00:43:12.170953 ==
2519 00:43:12.174221 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 00:43:12.177558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 00:43:12.177638 ==
2522 00:43:12.180984 [Gating] SW mode calibration
2523 00:43:12.187550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2524 00:43:12.190677 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2525 00:43:12.197243 0 15 0 | B1->B0 | 2323 3333 | 1 1 | (1 1) (1 1)
2526 00:43:12.200501 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2527 00:43:12.203737 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 00:43:12.210766 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 00:43:12.213958 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 00:43:12.217351 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 00:43:12.223968 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2532 00:43:12.227338 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
2533 00:43:12.230647 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2534 00:43:12.237115 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 00:43:12.240558 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 00:43:12.243839 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 00:43:12.250851 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 00:43:12.254007 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 00:43:12.257766 1 0 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
2540 00:43:12.260810 1 0 28 | B1->B0 | 2727 4544 | 0 1 | (0 0) (0 0)
2541 00:43:12.267616 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2542 00:43:12.270838 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 00:43:12.273937 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 00:43:12.280646 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 00:43:12.284005 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 00:43:12.287340 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 00:43:12.294365 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 00:43:12.297625 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2549 00:43:12.300862 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2550 00:43:12.307246 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 00:43:12.310493 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 00:43:12.314236 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 00:43:12.320754 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 00:43:12.324086 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 00:43:12.327342 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 00:43:12.334089 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 00:43:12.337338 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 00:43:12.340685 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 00:43:12.347567 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 00:43:12.350558 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 00:43:12.353851 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 00:43:12.357490 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 00:43:12.364312 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2564 00:43:12.367659 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2565 00:43:12.370924 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2566 00:43:12.374211 Total UI for P1: 0, mck2ui 16
2567 00:43:12.377478 best dqsien dly found for B0: ( 1, 3, 26)
2568 00:43:12.383978 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 00:43:12.384062 Total UI for P1: 0, mck2ui 16
2570 00:43:12.390722 best dqsien dly found for B1: ( 1, 4, 0)
2571 00:43:12.394106 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2572 00:43:12.397473 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2573 00:43:12.397559
2574 00:43:12.400585 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2575 00:43:12.404292 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2576 00:43:12.407613 [Gating] SW calibration Done
2577 00:43:12.407686 ==
2578 00:43:12.410803 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 00:43:12.413888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 00:43:12.413961 ==
2581 00:43:12.417744 RX Vref Scan: 0
2582 00:43:12.417821
2583 00:43:12.417884 RX Vref 0 -> 0, step: 1
2584 00:43:12.417941
2585 00:43:12.421040 RX Delay -40 -> 252, step: 8
2586 00:43:12.424455 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2587 00:43:12.431125 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2588 00:43:12.434491 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2589 00:43:12.437581 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2590 00:43:12.440635 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2591 00:43:12.444610 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2592 00:43:12.447370 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2593 00:43:12.454254 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2594 00:43:12.457719 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2595 00:43:12.461028 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2596 00:43:12.464333 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2597 00:43:12.467512 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2598 00:43:12.474655 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2599 00:43:12.478077 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2600 00:43:12.481236 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2601 00:43:12.484368 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2602 00:43:12.484438 ==
2603 00:43:12.487935 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 00:43:12.494776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 00:43:12.494878 ==
2606 00:43:12.494971 DQS Delay:
2607 00:43:12.495056 DQS0 = 0, DQS1 = 0
2608 00:43:12.498164 DQM Delay:
2609 00:43:12.498232 DQM0 = 121, DQM1 = 112
2610 00:43:12.501529 DQ Delay:
2611 00:43:12.504729 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2612 00:43:12.507923 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2613 00:43:12.511159 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2614 00:43:12.514369 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2615 00:43:12.514464
2616 00:43:12.514545
2617 00:43:12.514602 ==
2618 00:43:12.517551 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 00:43:12.521280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 00:43:12.521381 ==
2621 00:43:12.524517
2622 00:43:12.524609
2623 00:43:12.524699 TX Vref Scan disable
2624 00:43:12.527927 == TX Byte 0 ==
2625 00:43:12.531320 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2626 00:43:12.534508 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2627 00:43:12.537866 == TX Byte 1 ==
2628 00:43:12.541263 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2629 00:43:12.544657 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2630 00:43:12.544726 ==
2631 00:43:12.548067 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 00:43:12.554677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 00:43:12.554755 ==
2634 00:43:12.565145 TX Vref=22, minBit 0, minWin=24, winSum=404
2635 00:43:12.568814 TX Vref=24, minBit 0, minWin=25, winSum=414
2636 00:43:12.572039 TX Vref=26, minBit 7, minWin=25, winSum=420
2637 00:43:12.575381 TX Vref=28, minBit 13, minWin=25, winSum=421
2638 00:43:12.578665 TX Vref=30, minBit 12, minWin=25, winSum=423
2639 00:43:12.585363 TX Vref=32, minBit 1, minWin=26, winSum=424
2640 00:43:12.588378 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 32
2641 00:43:12.588471
2642 00:43:12.592225 Final TX Range 1 Vref 32
2643 00:43:12.592319
2644 00:43:12.592412 ==
2645 00:43:12.594988 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 00:43:12.598790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 00:43:12.598859 ==
2648 00:43:12.602195
2649 00:43:12.602261
2650 00:43:12.602316 TX Vref Scan disable
2651 00:43:12.605582 == TX Byte 0 ==
2652 00:43:12.608825 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2653 00:43:12.611837 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2654 00:43:12.615596 == TX Byte 1 ==
2655 00:43:12.618859 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2656 00:43:12.621962 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2657 00:43:12.622036
2658 00:43:12.625110 [DATLAT]
2659 00:43:12.625215 Freq=1200, CH0 RK0
2660 00:43:12.625310
2661 00:43:12.628735 DATLAT Default: 0xd
2662 00:43:12.628825 0, 0xFFFF, sum = 0
2663 00:43:12.632085 1, 0xFFFF, sum = 0
2664 00:43:12.632180 2, 0xFFFF, sum = 0
2665 00:43:12.635477 3, 0xFFFF, sum = 0
2666 00:43:12.635567 4, 0xFFFF, sum = 0
2667 00:43:12.638914 5, 0xFFFF, sum = 0
2668 00:43:12.639011 6, 0xFFFF, sum = 0
2669 00:43:12.642282 7, 0xFFFF, sum = 0
2670 00:43:12.642348 8, 0xFFFF, sum = 0
2671 00:43:12.645632 9, 0xFFFF, sum = 0
2672 00:43:12.648975 10, 0xFFFF, sum = 0
2673 00:43:12.649071 11, 0xFFFF, sum = 0
2674 00:43:12.652381 12, 0x0, sum = 1
2675 00:43:12.652471 13, 0x0, sum = 2
2676 00:43:12.652561 14, 0x0, sum = 3
2677 00:43:12.655736 15, 0x0, sum = 4
2678 00:43:12.655826 best_step = 13
2679 00:43:12.655921
2680 00:43:12.659056 ==
2681 00:43:12.659146 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 00:43:12.665856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 00:43:12.665943 ==
2684 00:43:12.666003 RX Vref Scan: 1
2685 00:43:12.666058
2686 00:43:12.668518 Set Vref Range= 32 -> 127
2687 00:43:12.668609
2688 00:43:12.671861 RX Vref 32 -> 127, step: 1
2689 00:43:12.671951
2690 00:43:12.675600 RX Delay -13 -> 252, step: 4
2691 00:43:12.675691
2692 00:43:12.678745 Set Vref, RX VrefLevel [Byte0]: 32
2693 00:43:12.681738 [Byte1]: 32
2694 00:43:12.681810
2695 00:43:12.685452 Set Vref, RX VrefLevel [Byte0]: 33
2696 00:43:12.688985 [Byte1]: 33
2697 00:43:12.689054
2698 00:43:12.692207 Set Vref, RX VrefLevel [Byte0]: 34
2699 00:43:12.695246 [Byte1]: 34
2700 00:43:12.699333
2701 00:43:12.699399 Set Vref, RX VrefLevel [Byte0]: 35
2702 00:43:12.702879 [Byte1]: 35
2703 00:43:12.707430
2704 00:43:12.707496 Set Vref, RX VrefLevel [Byte0]: 36
2705 00:43:12.710701 [Byte1]: 36
2706 00:43:12.714973
2707 00:43:12.715040 Set Vref, RX VrefLevel [Byte0]: 37
2708 00:43:12.718779 [Byte1]: 37
2709 00:43:12.722929
2710 00:43:12.722998 Set Vref, RX VrefLevel [Byte0]: 38
2711 00:43:12.726381 [Byte1]: 38
2712 00:43:12.731307
2713 00:43:12.731375 Set Vref, RX VrefLevel [Byte0]: 39
2714 00:43:12.734332 [Byte1]: 39
2715 00:43:12.738683
2716 00:43:12.738749 Set Vref, RX VrefLevel [Byte0]: 40
2717 00:43:12.742044 [Byte1]: 40
2718 00:43:12.746790
2719 00:43:12.746858 Set Vref, RX VrefLevel [Byte0]: 41
2720 00:43:12.749895 [Byte1]: 41
2721 00:43:12.754620
2722 00:43:12.754693 Set Vref, RX VrefLevel [Byte0]: 42
2723 00:43:12.757996 [Byte1]: 42
2724 00:43:12.762727
2725 00:43:12.762800 Set Vref, RX VrefLevel [Byte0]: 43
2726 00:43:12.766085 [Byte1]: 43
2727 00:43:12.770264
2728 00:43:12.770335 Set Vref, RX VrefLevel [Byte0]: 44
2729 00:43:12.773474 [Byte1]: 44
2730 00:43:12.778303
2731 00:43:12.778375 Set Vref, RX VrefLevel [Byte0]: 45
2732 00:43:12.781629 [Byte1]: 45
2733 00:43:12.786007
2734 00:43:12.786077 Set Vref, RX VrefLevel [Byte0]: 46
2735 00:43:12.789316 [Byte1]: 46
2736 00:43:12.794245
2737 00:43:12.794312 Set Vref, RX VrefLevel [Byte0]: 47
2738 00:43:12.797285 [Byte1]: 47
2739 00:43:12.801808
2740 00:43:12.801882 Set Vref, RX VrefLevel [Byte0]: 48
2741 00:43:12.805359 [Byte1]: 48
2742 00:43:12.809869
2743 00:43:12.809935 Set Vref, RX VrefLevel [Byte0]: 49
2744 00:43:12.813422 [Byte1]: 49
2745 00:43:12.817583
2746 00:43:12.817648 Set Vref, RX VrefLevel [Byte0]: 50
2747 00:43:12.821227 [Byte1]: 50
2748 00:43:12.825909
2749 00:43:12.825978 Set Vref, RX VrefLevel [Byte0]: 51
2750 00:43:12.829225 [Byte1]: 51
2751 00:43:12.833754
2752 00:43:12.833820 Set Vref, RX VrefLevel [Byte0]: 52
2753 00:43:12.837073 [Byte1]: 52
2754 00:43:12.841668
2755 00:43:12.841733 Set Vref, RX VrefLevel [Byte0]: 53
2756 00:43:12.844810 [Byte1]: 53
2757 00:43:12.849293
2758 00:43:12.849358 Set Vref, RX VrefLevel [Byte0]: 54
2759 00:43:12.852490 [Byte1]: 54
2760 00:43:12.856954
2761 00:43:12.857017 Set Vref, RX VrefLevel [Byte0]: 55
2762 00:43:12.860861 [Byte1]: 55
2763 00:43:12.865161
2764 00:43:12.865230 Set Vref, RX VrefLevel [Byte0]: 56
2765 00:43:12.868514 [Byte1]: 56
2766 00:43:12.873050
2767 00:43:12.873124 Set Vref, RX VrefLevel [Byte0]: 57
2768 00:43:12.876461 [Byte1]: 57
2769 00:43:12.881063
2770 00:43:12.881137 Set Vref, RX VrefLevel [Byte0]: 58
2771 00:43:12.884326 [Byte1]: 58
2772 00:43:12.888983
2773 00:43:12.889050 Set Vref, RX VrefLevel [Byte0]: 59
2774 00:43:12.892256 [Byte1]: 59
2775 00:43:12.896864
2776 00:43:12.896931 Set Vref, RX VrefLevel [Byte0]: 60
2777 00:43:12.900265 [Byte1]: 60
2778 00:43:12.904640
2779 00:43:12.904704 Set Vref, RX VrefLevel [Byte0]: 61
2780 00:43:12.908353 [Byte1]: 61
2781 00:43:12.912670
2782 00:43:12.912736 Set Vref, RX VrefLevel [Byte0]: 62
2783 00:43:12.915785 [Byte1]: 62
2784 00:43:12.920161
2785 00:43:12.920231 Set Vref, RX VrefLevel [Byte0]: 63
2786 00:43:12.923888 [Byte1]: 63
2787 00:43:12.928039
2788 00:43:12.928109 Set Vref, RX VrefLevel [Byte0]: 64
2789 00:43:12.931702 [Byte1]: 64
2790 00:43:12.936485
2791 00:43:12.936554 Set Vref, RX VrefLevel [Byte0]: 65
2792 00:43:12.939702 [Byte1]: 65
2793 00:43:12.944346
2794 00:43:12.944409 Set Vref, RX VrefLevel [Byte0]: 66
2795 00:43:12.947035 [Byte1]: 66
2796 00:43:12.951755
2797 00:43:12.951818 Set Vref, RX VrefLevel [Byte0]: 67
2798 00:43:12.955165 [Byte1]: 67
2799 00:43:12.959833
2800 00:43:12.959902 Set Vref, RX VrefLevel [Byte0]: 68
2801 00:43:12.963217 [Byte1]: 68
2802 00:43:12.967946
2803 00:43:12.968014 Set Vref, RX VrefLevel [Byte0]: 69
2804 00:43:12.971238 [Byte1]: 69
2805 00:43:12.975773
2806 00:43:12.975839 Set Vref, RX VrefLevel [Byte0]: 70
2807 00:43:12.978974 [Byte1]: 70
2808 00:43:12.983709
2809 00:43:12.983778 Final RX Vref Byte 0 = 53 to rank0
2810 00:43:12.987055 Final RX Vref Byte 1 = 50 to rank0
2811 00:43:12.990323 Final RX Vref Byte 0 = 53 to rank1
2812 00:43:12.994097 Final RX Vref Byte 1 = 50 to rank1==
2813 00:43:12.997283 Dram Type= 6, Freq= 0, CH_0, rank 0
2814 00:43:13.000508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2815 00:43:13.003428 ==
2816 00:43:13.003500 DQS Delay:
2817 00:43:13.003556 DQS0 = 0, DQS1 = 0
2818 00:43:13.007025 DQM Delay:
2819 00:43:13.007098 DQM0 = 120, DQM1 = 112
2820 00:43:13.010052 DQ Delay:
2821 00:43:13.013775 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2822 00:43:13.016786 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2823 00:43:13.020313 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2824 00:43:13.023286 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2825 00:43:13.023381
2826 00:43:13.023468
2827 00:43:13.030333 [DQSOSCAuto] RK0, (LSB)MR18= 0x1711, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2828 00:43:13.033369 CH0 RK0: MR19=404, MR18=1711
2829 00:43:13.040286 CH0_RK0: MR19=0x404, MR18=0x1711, DQSOSC=401, MR23=63, INC=40, DEC=27
2830 00:43:13.040364
2831 00:43:13.044030 ----->DramcWriteLeveling(PI) begin...
2832 00:43:13.044109 ==
2833 00:43:13.047354 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 00:43:13.050725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 00:43:13.050795 ==
2836 00:43:13.053921 Write leveling (Byte 0): 33 => 33
2837 00:43:13.057395 Write leveling (Byte 1): 28 => 28
2838 00:43:13.060577 DramcWriteLeveling(PI) end<-----
2839 00:43:13.060649
2840 00:43:13.060705 ==
2841 00:43:13.063914 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 00:43:13.067270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 00:43:13.070746 ==
2844 00:43:13.070813 [Gating] SW mode calibration
2845 00:43:13.080704 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2846 00:43:13.084050 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2847 00:43:13.087554 0 15 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 0)
2848 00:43:13.094137 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 00:43:13.096744 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 00:43:13.100551 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 00:43:13.107260 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 00:43:13.110506 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 00:43:13.113987 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 00:43:13.120261 0 15 28 | B1->B0 | 3030 2b2b | 1 0 | (0 1) (0 0)
2855 00:43:13.123617 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2856 00:43:13.126746 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 00:43:13.133666 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 00:43:13.136900 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 00:43:13.140275 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 00:43:13.146968 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 00:43:13.150417 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2862 00:43:13.153620 1 0 28 | B1->B0 | 3939 3a3a | 0 0 | (1 1) (0 0)
2863 00:43:13.160593 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2864 00:43:13.164034 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 00:43:13.167276 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 00:43:13.170558 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 00:43:13.177230 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 00:43:13.180724 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 00:43:13.184004 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2870 00:43:13.190717 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2871 00:43:13.193997 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2872 00:43:13.197419 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 00:43:13.204111 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 00:43:13.207500 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 00:43:13.210728 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 00:43:13.217637 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 00:43:13.220991 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 00:43:13.223735 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 00:43:13.227706 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 00:43:13.234387 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 00:43:13.237638 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 00:43:13.241001 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 00:43:13.247409 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 00:43:13.250616 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 00:43:13.253863 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2886 00:43:13.260540 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2887 00:43:13.264048 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2888 00:43:13.267625 Total UI for P1: 0, mck2ui 16
2889 00:43:13.270719 best dqsien dly found for B1: ( 1, 3, 26)
2890 00:43:13.274170 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 00:43:13.277287 Total UI for P1: 0, mck2ui 16
2892 00:43:13.280824 best dqsien dly found for B0: ( 1, 3, 30)
2893 00:43:13.284298 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2894 00:43:13.287469 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2895 00:43:13.287547
2896 00:43:13.291025 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2897 00:43:13.297576 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2898 00:43:13.297653 [Gating] SW calibration Done
2899 00:43:13.300802 ==
2900 00:43:13.300876 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 00:43:13.307704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 00:43:13.307793 ==
2903 00:43:13.307859 RX Vref Scan: 0
2904 00:43:13.307915
2905 00:43:13.311077 RX Vref 0 -> 0, step: 1
2906 00:43:13.311144
2907 00:43:13.314432 RX Delay -40 -> 252, step: 8
2908 00:43:13.317779 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2909 00:43:13.320893 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2910 00:43:13.324402 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2911 00:43:13.331047 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2912 00:43:13.334318 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2913 00:43:13.337711 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2914 00:43:13.341048 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
2915 00:43:13.344301 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2916 00:43:13.351082 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2917 00:43:13.354491 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2918 00:43:13.357702 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2919 00:43:13.360973 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2920 00:43:13.363964 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2921 00:43:13.370931 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2922 00:43:13.374129 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2923 00:43:13.377351 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2924 00:43:13.377443 ==
2925 00:43:13.380589 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 00:43:13.383866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 00:43:13.383956 ==
2928 00:43:13.387555 DQS Delay:
2929 00:43:13.387627 DQS0 = 0, DQS1 = 0
2930 00:43:13.390514 DQM Delay:
2931 00:43:13.390585 DQM0 = 121, DQM1 = 112
2932 00:43:13.394306 DQ Delay:
2933 00:43:13.397009 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2934 00:43:13.400388 DQ4 =127, DQ5 =119, DQ6 =123, DQ7 =127
2935 00:43:13.403776 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2936 00:43:13.407134 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2937 00:43:13.407211
2938 00:43:13.407270
2939 00:43:13.407324 ==
2940 00:43:13.410269 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 00:43:13.413891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 00:43:13.413975 ==
2943 00:43:13.414035
2944 00:43:13.414088
2945 00:43:13.417090 TX Vref Scan disable
2946 00:43:13.420457 == TX Byte 0 ==
2947 00:43:13.423627 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2948 00:43:13.427302 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2949 00:43:13.430383 == TX Byte 1 ==
2950 00:43:13.433536 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2951 00:43:13.436892 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2952 00:43:13.436991 ==
2953 00:43:13.440289 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 00:43:13.446960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 00:43:13.447036 ==
2956 00:43:13.457666 TX Vref=22, minBit 3, minWin=25, winSum=416
2957 00:43:13.461042 TX Vref=24, minBit 1, minWin=25, winSum=416
2958 00:43:13.464451 TX Vref=26, minBit 0, minWin=26, winSum=423
2959 00:43:13.467689 TX Vref=28, minBit 1, minWin=26, winSum=426
2960 00:43:13.471021 TX Vref=30, minBit 1, minWin=26, winSum=431
2961 00:43:13.477343 TX Vref=32, minBit 0, minWin=26, winSum=426
2962 00:43:13.481081 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
2963 00:43:13.481155
2964 00:43:13.484011 Final TX Range 1 Vref 30
2965 00:43:13.484080
2966 00:43:13.484142 ==
2967 00:43:13.487572 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 00:43:13.490891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 00:43:13.490961 ==
2970 00:43:13.494219
2971 00:43:13.494289
2972 00:43:13.494374 TX Vref Scan disable
2973 00:43:13.497516 == TX Byte 0 ==
2974 00:43:13.500849 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2975 00:43:13.507703 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2976 00:43:13.507776 == TX Byte 1 ==
2977 00:43:13.510941 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2978 00:43:13.517470 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2979 00:43:13.517574
2980 00:43:13.517643 [DATLAT]
2981 00:43:13.517698 Freq=1200, CH0 RK1
2982 00:43:13.517751
2983 00:43:13.520474 DATLAT Default: 0xd
2984 00:43:13.520539 0, 0xFFFF, sum = 0
2985 00:43:13.524238 1, 0xFFFF, sum = 0
2986 00:43:13.527161 2, 0xFFFF, sum = 0
2987 00:43:13.527231 3, 0xFFFF, sum = 0
2988 00:43:13.530729 4, 0xFFFF, sum = 0
2989 00:43:13.530800 5, 0xFFFF, sum = 0
2990 00:43:13.533648 6, 0xFFFF, sum = 0
2991 00:43:13.533717 7, 0xFFFF, sum = 0
2992 00:43:13.537089 8, 0xFFFF, sum = 0
2993 00:43:13.537164 9, 0xFFFF, sum = 0
2994 00:43:13.540304 10, 0xFFFF, sum = 0
2995 00:43:13.540373 11, 0xFFFF, sum = 0
2996 00:43:13.543717 12, 0x0, sum = 1
2997 00:43:13.543811 13, 0x0, sum = 2
2998 00:43:13.547118 14, 0x0, sum = 3
2999 00:43:13.547222 15, 0x0, sum = 4
3000 00:43:13.550524 best_step = 13
3001 00:43:13.550602
3002 00:43:13.550660 ==
3003 00:43:13.553756 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 00:43:13.557240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 00:43:13.557309 ==
3006 00:43:13.557367 RX Vref Scan: 0
3007 00:43:13.557420
3008 00:43:13.560601 RX Vref 0 -> 0, step: 1
3009 00:43:13.560675
3010 00:43:13.564007 RX Delay -13 -> 252, step: 4
3011 00:43:13.567238 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3012 00:43:13.573966 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3013 00:43:13.577438 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3014 00:43:13.580204 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3015 00:43:13.584051 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3016 00:43:13.587096 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3017 00:43:13.593805 iDelay=195, Bit 6, Center 126 (63 ~ 190) 128
3018 00:43:13.596926 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3019 00:43:13.600529 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3020 00:43:13.604222 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3021 00:43:13.607231 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3022 00:43:13.613863 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3023 00:43:13.617046 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3024 00:43:13.620211 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3025 00:43:13.623984 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3026 00:43:13.627351 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3027 00:43:13.630713 ==
3028 00:43:13.633947 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 00:43:13.637136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 00:43:13.637205 ==
3031 00:43:13.637261 DQS Delay:
3032 00:43:13.640457 DQS0 = 0, DQS1 = 0
3033 00:43:13.640524 DQM Delay:
3034 00:43:13.643728 DQM0 = 120, DQM1 = 110
3035 00:43:13.643796 DQ Delay:
3036 00:43:13.646835 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3037 00:43:13.650246 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3038 00:43:13.653413 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3039 00:43:13.656980 DQ12 =114, DQ13 =118, DQ14 =122, DQ15 =120
3040 00:43:13.657045
3041 00:43:13.657101
3042 00:43:13.666829 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3043 00:43:13.670223 CH0 RK1: MR19=403, MR18=11F2
3044 00:43:13.673616 CH0_RK1: MR19=0x403, MR18=0x11F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3045 00:43:13.676876 [RxdqsGatingPostProcess] freq 1200
3046 00:43:13.683567 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3047 00:43:13.686930 best DQS0 dly(2T, 0.5T) = (0, 11)
3048 00:43:13.690251 best DQS1 dly(2T, 0.5T) = (0, 12)
3049 00:43:13.693387 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3050 00:43:13.696822 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3051 00:43:13.700246 best DQS0 dly(2T, 0.5T) = (0, 11)
3052 00:43:13.703548 best DQS1 dly(2T, 0.5T) = (0, 11)
3053 00:43:13.703617 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3054 00:43:13.706739 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3055 00:43:13.710608 Pre-setting of DQS Precalculation
3056 00:43:13.716802 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3057 00:43:13.716877 ==
3058 00:43:13.720026 Dram Type= 6, Freq= 0, CH_1, rank 0
3059 00:43:13.723222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 00:43:13.723294 ==
3061 00:43:13.730146 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3062 00:43:13.736785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3063 00:43:13.743955 [CA 0] Center 37 (7~68) winsize 62
3064 00:43:13.747301 [CA 1] Center 37 (7~68) winsize 62
3065 00:43:13.750620 [CA 2] Center 35 (5~65) winsize 61
3066 00:43:13.754090 [CA 3] Center 34 (4~64) winsize 61
3067 00:43:13.757304 [CA 4] Center 34 (5~64) winsize 60
3068 00:43:13.760623 [CA 5] Center 33 (3~63) winsize 61
3069 00:43:13.760693
3070 00:43:13.764381 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3071 00:43:13.764453
3072 00:43:13.767419 [CATrainingPosCal] consider 1 rank data
3073 00:43:13.770660 u2DelayCellTimex100 = 270/100 ps
3074 00:43:13.773721 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3075 00:43:13.777207 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3076 00:43:13.783764 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3077 00:43:13.787229 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3078 00:43:13.790676 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3079 00:43:13.794022 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3080 00:43:13.794088
3081 00:43:13.797031 CA PerBit enable=1, Macro0, CA PI delay=33
3082 00:43:13.797127
3083 00:43:13.800408 [CBTSetCACLKResult] CA Dly = 33
3084 00:43:13.800505 CS Dly: 8 (0~39)
3085 00:43:13.803752 ==
3086 00:43:13.803831 Dram Type= 6, Freq= 0, CH_1, rank 1
3087 00:43:13.810375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 00:43:13.810445 ==
3089 00:43:13.813605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3090 00:43:13.820344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3091 00:43:13.829439 [CA 0] Center 37 (7~68) winsize 62
3092 00:43:13.832790 [CA 1] Center 38 (8~68) winsize 61
3093 00:43:13.836702 [CA 2] Center 35 (5~66) winsize 62
3094 00:43:13.839208 [CA 3] Center 34 (4~65) winsize 62
3095 00:43:13.842823 [CA 4] Center 34 (4~65) winsize 62
3096 00:43:13.846129 [CA 5] Center 34 (4~64) winsize 61
3097 00:43:13.846203
3098 00:43:13.849490 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3099 00:43:13.849581
3100 00:43:13.852741 [CATrainingPosCal] consider 2 rank data
3101 00:43:13.856491 u2DelayCellTimex100 = 270/100 ps
3102 00:43:13.859311 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3103 00:43:13.866078 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3104 00:43:13.869276 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3105 00:43:13.872325 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3106 00:43:13.875763 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3107 00:43:13.879026 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3108 00:43:13.879099
3109 00:43:13.882381 CA PerBit enable=1, Macro0, CA PI delay=33
3110 00:43:13.882454
3111 00:43:13.886344 [CBTSetCACLKResult] CA Dly = 33
3112 00:43:13.886416 CS Dly: 8 (0~40)
3113 00:43:13.889221
3114 00:43:13.892254 ----->DramcWriteLeveling(PI) begin...
3115 00:43:13.892325 ==
3116 00:43:13.895922 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 00:43:13.898959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 00:43:13.899030 ==
3119 00:43:13.902365 Write leveling (Byte 0): 25 => 25
3120 00:43:13.905606 Write leveling (Byte 1): 27 => 27
3121 00:43:13.908968 DramcWriteLeveling(PI) end<-----
3122 00:43:13.909045
3123 00:43:13.909105 ==
3124 00:43:13.912917 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 00:43:13.916273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 00:43:13.916343 ==
3127 00:43:13.919513 [Gating] SW mode calibration
3128 00:43:13.925887 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3129 00:43:13.932621 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3130 00:43:13.935782 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3131 00:43:13.939063 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 00:43:13.945622 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 00:43:13.948913 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 00:43:13.952407 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 00:43:13.955712 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 00:43:13.962521 0 15 24 | B1->B0 | 3333 2b2b | 0 1 | (0 0) (1 0)
3137 00:43:13.965636 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3138 00:43:13.968950 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 00:43:13.975499 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 00:43:13.979111 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 00:43:13.982571 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 00:43:13.989272 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 00:43:13.992584 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 00:43:13.995638 1 0 24 | B1->B0 | 3939 4444 | 0 0 | (1 1) (0 0)
3145 00:43:14.002728 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 00:43:14.005403 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 00:43:14.009331 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 00:43:14.015979 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 00:43:14.018839 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 00:43:14.022033 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 00:43:14.028758 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 00:43:14.032098 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3153 00:43:14.035419 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3154 00:43:14.042591 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 00:43:14.045225 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 00:43:14.048644 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 00:43:14.055372 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 00:43:14.059228 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 00:43:14.062044 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 00:43:14.068603 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 00:43:14.072428 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 00:43:14.075499 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 00:43:14.082219 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 00:43:14.085134 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 00:43:14.089005 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 00:43:14.092144 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 00:43:14.098623 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 00:43:14.101836 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3169 00:43:14.105378 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3170 00:43:14.112365 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 00:43:14.115080 Total UI for P1: 0, mck2ui 16
3172 00:43:14.119030 best dqsien dly found for B0: ( 1, 3, 26)
3173 00:43:14.122381 Total UI for P1: 0, mck2ui 16
3174 00:43:14.125467 best dqsien dly found for B1: ( 1, 3, 26)
3175 00:43:14.128625 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3176 00:43:14.131834 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3177 00:43:14.131931
3178 00:43:14.135108 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3179 00:43:14.138419 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3180 00:43:14.141951 [Gating] SW calibration Done
3181 00:43:14.142050 ==
3182 00:43:14.145165 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 00:43:14.148273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 00:43:14.148375 ==
3185 00:43:14.151598 RX Vref Scan: 0
3186 00:43:14.151695
3187 00:43:14.151778 RX Vref 0 -> 0, step: 1
3188 00:43:14.154963
3189 00:43:14.155052 RX Delay -40 -> 252, step: 8
3190 00:43:14.161679 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3191 00:43:14.165209 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3192 00:43:14.168556 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3193 00:43:14.171807 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3194 00:43:14.175165 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3195 00:43:14.181488 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3196 00:43:14.185071 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3197 00:43:14.188210 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3198 00:43:14.191589 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3199 00:43:14.194967 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3200 00:43:14.201584 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3201 00:43:14.204598 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3202 00:43:14.207790 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3203 00:43:14.211399 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3204 00:43:14.214712 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3205 00:43:14.221267 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3206 00:43:14.221342 ==
3207 00:43:14.224634 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 00:43:14.227805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 00:43:14.227879 ==
3210 00:43:14.227945 DQS Delay:
3211 00:43:14.231587 DQS0 = 0, DQS1 = 0
3212 00:43:14.231662 DQM Delay:
3213 00:43:14.234778 DQM0 = 119, DQM1 = 116
3214 00:43:14.234850 DQ Delay:
3215 00:43:14.238163 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3216 00:43:14.241325 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3217 00:43:14.244518 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3218 00:43:14.248099 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3219 00:43:14.250942
3220 00:43:14.251011
3221 00:43:14.251069 ==
3222 00:43:14.254529 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 00:43:14.257858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 00:43:14.257928 ==
3225 00:43:14.257985
3226 00:43:14.258039
3227 00:43:14.261209 TX Vref Scan disable
3228 00:43:14.261279 == TX Byte 0 ==
3229 00:43:14.267852 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3230 00:43:14.271114 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3231 00:43:14.271190 == TX Byte 1 ==
3232 00:43:14.277913 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3233 00:43:14.281192 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3234 00:43:14.281261 ==
3235 00:43:14.284382 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 00:43:14.287664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 00:43:14.287739 ==
3238 00:43:14.300474 TX Vref=22, minBit 1, minWin=25, winSum=414
3239 00:43:14.303598 TX Vref=24, minBit 2, minWin=25, winSum=418
3240 00:43:14.306920 TX Vref=26, minBit 9, minWin=25, winSum=424
3241 00:43:14.310270 TX Vref=28, minBit 1, minWin=26, winSum=425
3242 00:43:14.312999 TX Vref=30, minBit 2, minWin=26, winSum=432
3243 00:43:14.320252 TX Vref=32, minBit 10, minWin=25, winSum=429
3244 00:43:14.323689 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 30
3245 00:43:14.323758
3246 00:43:14.326803 Final TX Range 1 Vref 30
3247 00:43:14.326871
3248 00:43:14.326933 ==
3249 00:43:14.329868 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 00:43:14.333386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 00:43:14.333470 ==
3252 00:43:14.333526
3253 00:43:14.336669
3254 00:43:14.336732 TX Vref Scan disable
3255 00:43:14.339857 == TX Byte 0 ==
3256 00:43:14.343380 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3257 00:43:14.346532 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3258 00:43:14.350333 == TX Byte 1 ==
3259 00:43:14.353293 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3260 00:43:14.356490 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3261 00:43:14.356561
3262 00:43:14.359857 [DATLAT]
3263 00:43:14.359955 Freq=1200, CH1 RK0
3264 00:43:14.360054
3265 00:43:14.363114 DATLAT Default: 0xd
3266 00:43:14.363203 0, 0xFFFF, sum = 0
3267 00:43:14.366854 1, 0xFFFF, sum = 0
3268 00:43:14.366946 2, 0xFFFF, sum = 0
3269 00:43:14.369735 3, 0xFFFF, sum = 0
3270 00:43:14.369832 4, 0xFFFF, sum = 0
3271 00:43:14.373559 5, 0xFFFF, sum = 0
3272 00:43:14.373661 6, 0xFFFF, sum = 0
3273 00:43:14.376640 7, 0xFFFF, sum = 0
3274 00:43:14.376719 8, 0xFFFF, sum = 0
3275 00:43:14.379995 9, 0xFFFF, sum = 0
3276 00:43:14.383342 10, 0xFFFF, sum = 0
3277 00:43:14.383443 11, 0xFFFF, sum = 0
3278 00:43:14.386651 12, 0x0, sum = 1
3279 00:43:14.386758 13, 0x0, sum = 2
3280 00:43:14.386860 14, 0x0, sum = 3
3281 00:43:14.389756 15, 0x0, sum = 4
3282 00:43:14.389838 best_step = 13
3283 00:43:14.389921
3284 00:43:14.393086 ==
3285 00:43:14.393150 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 00:43:14.399616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 00:43:14.399696 ==
3288 00:43:14.399763 RX Vref Scan: 1
3289 00:43:14.399820
3290 00:43:14.403261 Set Vref Range= 32 -> 127
3291 00:43:14.403339
3292 00:43:14.406407 RX Vref 32 -> 127, step: 1
3293 00:43:14.406475
3294 00:43:14.409600 RX Delay -5 -> 252, step: 4
3295 00:43:14.409699
3296 00:43:14.413015 Set Vref, RX VrefLevel [Byte0]: 32
3297 00:43:14.416441 [Byte1]: 32
3298 00:43:14.416518
3299 00:43:14.419793 Set Vref, RX VrefLevel [Byte0]: 33
3300 00:43:14.423074 [Byte1]: 33
3301 00:43:14.423140
3302 00:43:14.426313 Set Vref, RX VrefLevel [Byte0]: 34
3303 00:43:14.429650 [Byte1]: 34
3304 00:43:14.433533
3305 00:43:14.433610 Set Vref, RX VrefLevel [Byte0]: 35
3306 00:43:14.436969 [Byte1]: 35
3307 00:43:14.441630
3308 00:43:14.441707 Set Vref, RX VrefLevel [Byte0]: 36
3309 00:43:14.444993 [Byte1]: 36
3310 00:43:14.449586
3311 00:43:14.449657 Set Vref, RX VrefLevel [Byte0]: 37
3312 00:43:14.452606 [Byte1]: 37
3313 00:43:14.457394
3314 00:43:14.457499 Set Vref, RX VrefLevel [Byte0]: 38
3315 00:43:14.460551 [Byte1]: 38
3316 00:43:14.465360
3317 00:43:14.465459 Set Vref, RX VrefLevel [Byte0]: 39
3318 00:43:14.468293 [Byte1]: 39
3319 00:43:14.473205
3320 00:43:14.473274 Set Vref, RX VrefLevel [Byte0]: 40
3321 00:43:14.476537 [Byte1]: 40
3322 00:43:14.480737
3323 00:43:14.480807 Set Vref, RX VrefLevel [Byte0]: 41
3324 00:43:14.484412 [Byte1]: 41
3325 00:43:14.488942
3326 00:43:14.489016 Set Vref, RX VrefLevel [Byte0]: 42
3327 00:43:14.491703 [Byte1]: 42
3328 00:43:14.496396
3329 00:43:14.496466 Set Vref, RX VrefLevel [Byte0]: 43
3330 00:43:14.499822 [Byte1]: 43
3331 00:43:14.504357
3332 00:43:14.504426 Set Vref, RX VrefLevel [Byte0]: 44
3333 00:43:14.507519 [Byte1]: 44
3334 00:43:14.512478
3335 00:43:14.512576 Set Vref, RX VrefLevel [Byte0]: 45
3336 00:43:14.515571 [Byte1]: 45
3337 00:43:14.520073
3338 00:43:14.520140 Set Vref, RX VrefLevel [Byte0]: 46
3339 00:43:14.523383 [Byte1]: 46
3340 00:43:14.527976
3341 00:43:14.528044 Set Vref, RX VrefLevel [Byte0]: 47
3342 00:43:14.531301 [Byte1]: 47
3343 00:43:14.535914
3344 00:43:14.535987 Set Vref, RX VrefLevel [Byte0]: 48
3345 00:43:14.539250 [Byte1]: 48
3346 00:43:14.543940
3347 00:43:14.544015 Set Vref, RX VrefLevel [Byte0]: 49
3348 00:43:14.547303 [Byte1]: 49
3349 00:43:14.551249
3350 00:43:14.551318 Set Vref, RX VrefLevel [Byte0]: 50
3351 00:43:14.554610 [Byte1]: 50
3352 00:43:14.559259
3353 00:43:14.559334 Set Vref, RX VrefLevel [Byte0]: 51
3354 00:43:14.562654 [Byte1]: 51
3355 00:43:14.567261
3356 00:43:14.567330 Set Vref, RX VrefLevel [Byte0]: 52
3357 00:43:14.570397 [Byte1]: 52
3358 00:43:14.574941
3359 00:43:14.575013 Set Vref, RX VrefLevel [Byte0]: 53
3360 00:43:14.578539 [Byte1]: 53
3361 00:43:14.582647
3362 00:43:14.582751 Set Vref, RX VrefLevel [Byte0]: 54
3363 00:43:14.585992 [Byte1]: 54
3364 00:43:14.590759
3365 00:43:14.590850 Set Vref, RX VrefLevel [Byte0]: 55
3366 00:43:14.593911 [Byte1]: 55
3367 00:43:14.598781
3368 00:43:14.598879 Set Vref, RX VrefLevel [Byte0]: 56
3369 00:43:14.602316 [Byte1]: 56
3370 00:43:14.606667
3371 00:43:14.606741 Set Vref, RX VrefLevel [Byte0]: 57
3372 00:43:14.609859 [Byte1]: 57
3373 00:43:14.614634
3374 00:43:14.614701 Set Vref, RX VrefLevel [Byte0]: 58
3375 00:43:14.617777 [Byte1]: 58
3376 00:43:14.622026
3377 00:43:14.622097 Set Vref, RX VrefLevel [Byte0]: 59
3378 00:43:14.625624 [Byte1]: 59
3379 00:43:14.630013
3380 00:43:14.630089 Set Vref, RX VrefLevel [Byte0]: 60
3381 00:43:14.633417 [Byte1]: 60
3382 00:43:14.638107
3383 00:43:14.638176 Set Vref, RX VrefLevel [Byte0]: 61
3384 00:43:14.641504 [Byte1]: 61
3385 00:43:14.645990
3386 00:43:14.646087 Set Vref, RX VrefLevel [Byte0]: 62
3387 00:43:14.649431 [Byte1]: 62
3388 00:43:14.653396
3389 00:43:14.653493 Set Vref, RX VrefLevel [Byte0]: 63
3390 00:43:14.656635 [Byte1]: 63
3391 00:43:14.661462
3392 00:43:14.661559 Set Vref, RX VrefLevel [Byte0]: 64
3393 00:43:14.664804 [Byte1]: 64
3394 00:43:14.669450
3395 00:43:14.669544 Set Vref, RX VrefLevel [Byte0]: 65
3396 00:43:14.672782 [Byte1]: 65
3397 00:43:14.677361
3398 00:43:14.677452 Set Vref, RX VrefLevel [Byte0]: 66
3399 00:43:14.680498 [Byte1]: 66
3400 00:43:14.685326
3401 00:43:14.685432 Set Vref, RX VrefLevel [Byte0]: 67
3402 00:43:14.688555 [Byte1]: 67
3403 00:43:14.692951
3404 00:43:14.693041 Final RX Vref Byte 0 = 53 to rank0
3405 00:43:14.695929 Final RX Vref Byte 1 = 45 to rank0
3406 00:43:14.699410 Final RX Vref Byte 0 = 53 to rank1
3407 00:43:14.702892 Final RX Vref Byte 1 = 45 to rank1==
3408 00:43:14.705954 Dram Type= 6, Freq= 0, CH_1, rank 0
3409 00:43:14.712819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3410 00:43:14.712900 ==
3411 00:43:14.712960 DQS Delay:
3412 00:43:14.713015 DQS0 = 0, DQS1 = 0
3413 00:43:14.716086 DQM Delay:
3414 00:43:14.716167 DQM0 = 120, DQM1 = 115
3415 00:43:14.719408 DQ Delay:
3416 00:43:14.722503 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3417 00:43:14.726322 DQ4 =118, DQ5 =130, DQ6 =128, DQ7 =120
3418 00:43:14.729313 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108
3419 00:43:14.732801 DQ12 =122, DQ13 =120, DQ14 =124, DQ15 =124
3420 00:43:14.732881
3421 00:43:14.732959
3422 00:43:14.742915 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3423 00:43:14.742996 CH1 RK0: MR19=404, MR18=316
3424 00:43:14.749143 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3425 00:43:14.749217
3426 00:43:14.752569 ----->DramcWriteLeveling(PI) begin...
3427 00:43:14.752643 ==
3428 00:43:14.755697 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 00:43:14.759630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 00:43:14.762260 ==
3431 00:43:14.762327 Write leveling (Byte 0): 25 => 25
3432 00:43:14.765640 Write leveling (Byte 1): 28 => 28
3433 00:43:14.769048 DramcWriteLeveling(PI) end<-----
3434 00:43:14.769118
3435 00:43:14.769181 ==
3436 00:43:14.772343 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 00:43:14.778981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 00:43:14.779049 ==
3439 00:43:14.782730 [Gating] SW mode calibration
3440 00:43:14.789288 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3441 00:43:14.792520 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3442 00:43:14.799255 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 00:43:14.802639 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 00:43:14.805854 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 00:43:14.812405 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 00:43:14.815699 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 00:43:14.819379 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3448 00:43:14.822094 0 15 24 | B1->B0 | 2929 3333 | 0 0 | (0 1) (0 1)
3449 00:43:14.828880 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3450 00:43:14.832124 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 00:43:14.835335 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 00:43:14.842045 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 00:43:14.845440 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 00:43:14.848663 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 00:43:14.855537 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3456 00:43:14.858893 1 0 24 | B1->B0 | 4343 2828 | 0 0 | (0 0) (0 0)
3457 00:43:14.862131 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 00:43:14.868674 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 00:43:14.871773 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 00:43:14.875761 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 00:43:14.882051 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 00:43:14.885387 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 00:43:14.888695 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3464 00:43:14.895307 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3465 00:43:14.898675 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3466 00:43:14.902008 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 00:43:14.908774 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 00:43:14.912076 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 00:43:14.914954 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 00:43:14.921954 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 00:43:14.925386 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 00:43:14.928292 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 00:43:14.935536 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 00:43:14.938594 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 00:43:14.941923 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 00:43:14.948551 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 00:43:14.952012 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 00:43:14.955407 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 00:43:14.958711 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3480 00:43:14.965361 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3481 00:43:14.968631 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3482 00:43:14.971992 Total UI for P1: 0, mck2ui 16
3483 00:43:14.975461 best dqsien dly found for B1: ( 1, 3, 22)
3484 00:43:14.978509 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 00:43:14.982007 Total UI for P1: 0, mck2ui 16
3486 00:43:14.985179 best dqsien dly found for B0: ( 1, 3, 28)
3487 00:43:14.988330 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3488 00:43:14.991655 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3489 00:43:14.991722
3490 00:43:14.998399 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3491 00:43:15.001821 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3492 00:43:15.005151 [Gating] SW calibration Done
3493 00:43:15.005226 ==
3494 00:43:15.008353 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 00:43:15.012089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 00:43:15.012168 ==
3497 00:43:15.012228 RX Vref Scan: 0
3498 00:43:15.012284
3499 00:43:15.015354 RX Vref 0 -> 0, step: 1
3500 00:43:15.015428
3501 00:43:15.018726 RX Delay -40 -> 252, step: 8
3502 00:43:15.021987 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3503 00:43:15.025342 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3504 00:43:15.032212 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3505 00:43:15.035285 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3506 00:43:15.038934 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3507 00:43:15.042280 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3508 00:43:15.044879 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3509 00:43:15.048852 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3510 00:43:15.055296 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3511 00:43:15.058449 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3512 00:43:15.062066 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3513 00:43:15.065467 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3514 00:43:15.071451 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3515 00:43:15.074876 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3516 00:43:15.078343 iDelay=200, Bit 14, Center 119 (56 ~ 183) 128
3517 00:43:15.081634 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3518 00:43:15.081711 ==
3519 00:43:15.084915 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 00:43:15.088465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 00:43:15.091681 ==
3522 00:43:15.091758 DQS Delay:
3523 00:43:15.091818 DQS0 = 0, DQS1 = 0
3524 00:43:15.095058 DQM Delay:
3525 00:43:15.095128 DQM0 = 120, DQM1 = 117
3526 00:43:15.098395 DQ Delay:
3527 00:43:15.101806 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3528 00:43:15.105052 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3529 00:43:15.108419 DQ8 =107, DQ9 =103, DQ10 =119, DQ11 =115
3530 00:43:15.111641 DQ12 =127, DQ13 =123, DQ14 =119, DQ15 =127
3531 00:43:15.111739
3532 00:43:15.111824
3533 00:43:15.111903 ==
3534 00:43:15.114892 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 00:43:15.118456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 00:43:15.118525 ==
3537 00:43:15.121471
3538 00:43:15.121543
3539 00:43:15.121608 TX Vref Scan disable
3540 00:43:15.124728 == TX Byte 0 ==
3541 00:43:15.128472 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3542 00:43:15.131342 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3543 00:43:15.134651 == TX Byte 1 ==
3544 00:43:15.137993 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3545 00:43:15.141629 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3546 00:43:15.141706 ==
3547 00:43:15.144710 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 00:43:15.151559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 00:43:15.151639 ==
3550 00:43:15.162503 TX Vref=22, minBit 1, minWin=26, winSum=424
3551 00:43:15.166010 TX Vref=24, minBit 10, minWin=25, winSum=426
3552 00:43:15.169761 TX Vref=26, minBit 1, minWin=26, winSum=427
3553 00:43:15.172640 TX Vref=28, minBit 10, minWin=25, winSum=428
3554 00:43:15.176104 TX Vref=30, minBit 10, minWin=26, winSum=434
3555 00:43:15.179471 TX Vref=32, minBit 9, minWin=26, winSum=434
3556 00:43:15.186301 [TxChooseVref] Worse bit 10, Min win 26, Win sum 434, Final Vref 30
3557 00:43:15.186422
3558 00:43:15.189694 Final TX Range 1 Vref 30
3559 00:43:15.189786
3560 00:43:15.189850 ==
3561 00:43:15.192721 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 00:43:15.195850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 00:43:15.195938 ==
3564 00:43:15.195995
3565 00:43:15.196053
3566 00:43:15.198908 TX Vref Scan disable
3567 00:43:15.202307 == TX Byte 0 ==
3568 00:43:15.205604 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3569 00:43:15.208944 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3570 00:43:15.212328 == TX Byte 1 ==
3571 00:43:15.215650 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3572 00:43:15.218866 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3573 00:43:15.218941
3574 00:43:15.222285 [DATLAT]
3575 00:43:15.222352 Freq=1200, CH1 RK1
3576 00:43:15.222415
3577 00:43:15.225752 DATLAT Default: 0xd
3578 00:43:15.225817 0, 0xFFFF, sum = 0
3579 00:43:15.228980 1, 0xFFFF, sum = 0
3580 00:43:15.229046 2, 0xFFFF, sum = 0
3581 00:43:15.232353 3, 0xFFFF, sum = 0
3582 00:43:15.232449 4, 0xFFFF, sum = 0
3583 00:43:15.235674 5, 0xFFFF, sum = 0
3584 00:43:15.235740 6, 0xFFFF, sum = 0
3585 00:43:15.239056 7, 0xFFFF, sum = 0
3586 00:43:15.239124 8, 0xFFFF, sum = 0
3587 00:43:15.242226 9, 0xFFFF, sum = 0
3588 00:43:15.245932 10, 0xFFFF, sum = 0
3589 00:43:15.246005 11, 0xFFFF, sum = 0
3590 00:43:15.249283 12, 0x0, sum = 1
3591 00:43:15.249359 13, 0x0, sum = 2
3592 00:43:15.249417 14, 0x0, sum = 3
3593 00:43:15.252125 15, 0x0, sum = 4
3594 00:43:15.252193 best_step = 13
3595 00:43:15.252245
3596 00:43:15.252296 ==
3597 00:43:15.255573 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 00:43:15.262465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 00:43:15.262538 ==
3600 00:43:15.262617 RX Vref Scan: 0
3601 00:43:15.262673
3602 00:43:15.265565 RX Vref 0 -> 0, step: 1
3603 00:43:15.265633
3604 00:43:15.268946 RX Delay -5 -> 252, step: 4
3605 00:43:15.272163 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3606 00:43:15.275574 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3607 00:43:15.281828 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3608 00:43:15.285392 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3609 00:43:15.288718 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3610 00:43:15.292263 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3611 00:43:15.295206 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3612 00:43:15.302081 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3613 00:43:15.305706 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3614 00:43:15.308593 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3615 00:43:15.311965 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3616 00:43:15.315380 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3617 00:43:15.322094 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3618 00:43:15.325468 iDelay=195, Bit 13, Center 122 (63 ~ 182) 120
3619 00:43:15.328748 iDelay=195, Bit 14, Center 120 (63 ~ 178) 116
3620 00:43:15.332302 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3621 00:43:15.332411 ==
3622 00:43:15.335574 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 00:43:15.342133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 00:43:15.342217 ==
3625 00:43:15.342278 DQS Delay:
3626 00:43:15.345508 DQS0 = 0, DQS1 = 0
3627 00:43:15.345583 DQM Delay:
3628 00:43:15.345639 DQM0 = 120, DQM1 = 115
3629 00:43:15.348913 DQ Delay:
3630 00:43:15.352333 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3631 00:43:15.355059 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3632 00:43:15.359000 DQ8 =104, DQ9 =104, DQ10 =116, DQ11 =110
3633 00:43:15.362068 DQ12 =126, DQ13 =122, DQ14 =120, DQ15 =124
3634 00:43:15.362139
3635 00:43:15.362195
3636 00:43:15.372179 [DQSOSCAuto] RK1, (LSB)MR18= 0x16f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 401 ps
3637 00:43:15.372260 CH1 RK1: MR19=403, MR18=16F2
3638 00:43:15.378769 CH1_RK1: MR19=0x403, MR18=0x16F2, DQSOSC=401, MR23=63, INC=40, DEC=27
3639 00:43:15.382179 [RxdqsGatingPostProcess] freq 1200
3640 00:43:15.388973 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3641 00:43:15.391748 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 00:43:15.395519 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 00:43:15.398743 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 00:43:15.402142 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 00:43:15.405176 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 00:43:15.405275 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 00:43:15.408666 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 00:43:15.412051 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 00:43:15.415148 Pre-setting of DQS Precalculation
3650 00:43:15.421843 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3651 00:43:15.428316 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3652 00:43:15.435435 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3653 00:43:15.435546
3654 00:43:15.435646
3655 00:43:15.438364 [Calibration Summary] 2400 Mbps
3656 00:43:15.441990 CH 0, Rank 0
3657 00:43:15.442080 SW Impedance : PASS
3658 00:43:15.445082 DUTY Scan : NO K
3659 00:43:15.445156 ZQ Calibration : PASS
3660 00:43:15.448441 Jitter Meter : NO K
3661 00:43:15.451763 CBT Training : PASS
3662 00:43:15.451847 Write leveling : PASS
3663 00:43:15.455170 RX DQS gating : PASS
3664 00:43:15.458417 RX DQ/DQS(RDDQC) : PASS
3665 00:43:15.458520 TX DQ/DQS : PASS
3666 00:43:15.461857 RX DATLAT : PASS
3667 00:43:15.465324 RX DQ/DQS(Engine): PASS
3668 00:43:15.465420 TX OE : NO K
3669 00:43:15.468639 All Pass.
3670 00:43:15.468714
3671 00:43:15.468774 CH 0, Rank 1
3672 00:43:15.472028 SW Impedance : PASS
3673 00:43:15.472101 DUTY Scan : NO K
3674 00:43:15.475372 ZQ Calibration : PASS
3675 00:43:15.478758 Jitter Meter : NO K
3676 00:43:15.478831 CBT Training : PASS
3677 00:43:15.481406 Write leveling : PASS
3678 00:43:15.484741 RX DQS gating : PASS
3679 00:43:15.484823 RX DQ/DQS(RDDQC) : PASS
3680 00:43:15.488075 TX DQ/DQS : PASS
3681 00:43:15.488157 RX DATLAT : PASS
3682 00:43:15.491440 RX DQ/DQS(Engine): PASS
3683 00:43:15.494722 TX OE : NO K
3684 00:43:15.494801 All Pass.
3685 00:43:15.494861
3686 00:43:15.494917 CH 1, Rank 0
3687 00:43:15.498114 SW Impedance : PASS
3688 00:43:15.501391 DUTY Scan : NO K
3689 00:43:15.501486 ZQ Calibration : PASS
3690 00:43:15.504712 Jitter Meter : NO K
3691 00:43:15.507879 CBT Training : PASS
3692 00:43:15.507957 Write leveling : PASS
3693 00:43:15.511772 RX DQS gating : PASS
3694 00:43:15.514836 RX DQ/DQS(RDDQC) : PASS
3695 00:43:15.514923 TX DQ/DQS : PASS
3696 00:43:15.517875 RX DATLAT : PASS
3697 00:43:15.521598 RX DQ/DQS(Engine): PASS
3698 00:43:15.521698 TX OE : NO K
3699 00:43:15.524978 All Pass.
3700 00:43:15.525074
3701 00:43:15.525164 CH 1, Rank 1
3702 00:43:15.528398 SW Impedance : PASS
3703 00:43:15.528489 DUTY Scan : NO K
3704 00:43:15.531214 ZQ Calibration : PASS
3705 00:43:15.534697 Jitter Meter : NO K
3706 00:43:15.534789 CBT Training : PASS
3707 00:43:15.538032 Write leveling : PASS
3708 00:43:15.541564 RX DQS gating : PASS
3709 00:43:15.541632 RX DQ/DQS(RDDQC) : PASS
3710 00:43:15.544735 TX DQ/DQS : PASS
3711 00:43:15.544800 RX DATLAT : PASS
3712 00:43:15.548252 RX DQ/DQS(Engine): PASS
3713 00:43:15.551147 TX OE : NO K
3714 00:43:15.551218 All Pass.
3715 00:43:15.551274
3716 00:43:15.554465 DramC Write-DBI off
3717 00:43:15.554533 PER_BANK_REFRESH: Hybrid Mode
3718 00:43:15.557829 TX_TRACKING: ON
3719 00:43:15.568049 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3720 00:43:15.571120 [FAST_K] Save calibration result to emmc
3721 00:43:15.574276 dramc_set_vcore_voltage set vcore to 650000
3722 00:43:15.574354 Read voltage for 600, 5
3723 00:43:15.577985 Vio18 = 0
3724 00:43:15.578068 Vcore = 650000
3725 00:43:15.578131 Vdram = 0
3726 00:43:15.581402 Vddq = 0
3727 00:43:15.581503 Vmddr = 0
3728 00:43:15.584706 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3729 00:43:15.591386 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3730 00:43:15.594765 MEM_TYPE=3, freq_sel=19
3731 00:43:15.598133 sv_algorithm_assistance_LP4_1600
3732 00:43:15.601360 ============ PULL DRAM RESETB DOWN ============
3733 00:43:15.604815 ========== PULL DRAM RESETB DOWN end =========
3734 00:43:15.610860 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3735 00:43:15.614250 ===================================
3736 00:43:15.614335 LPDDR4 DRAM CONFIGURATION
3737 00:43:15.618042 ===================================
3738 00:43:15.621218 EX_ROW_EN[0] = 0x0
3739 00:43:15.621319 EX_ROW_EN[1] = 0x0
3740 00:43:15.624237 LP4Y_EN = 0x0
3741 00:43:15.627873 WORK_FSP = 0x0
3742 00:43:15.627943 WL = 0x2
3743 00:43:15.630998 RL = 0x2
3744 00:43:15.631069 BL = 0x2
3745 00:43:15.634357 RPST = 0x0
3746 00:43:15.634430 RD_PRE = 0x0
3747 00:43:15.637798 WR_PRE = 0x1
3748 00:43:15.637867 WR_PST = 0x0
3749 00:43:15.640989 DBI_WR = 0x0
3750 00:43:15.641089 DBI_RD = 0x0
3751 00:43:15.644169 OTF = 0x1
3752 00:43:15.647968 ===================================
3753 00:43:15.651296 ===================================
3754 00:43:15.651367 ANA top config
3755 00:43:15.654529 ===================================
3756 00:43:15.657782 DLL_ASYNC_EN = 0
3757 00:43:15.661061 ALL_SLAVE_EN = 1
3758 00:43:15.661155 NEW_RANK_MODE = 1
3759 00:43:15.664324 DLL_IDLE_MODE = 1
3760 00:43:15.667645 LP45_APHY_COMB_EN = 1
3761 00:43:15.670682 TX_ODT_DIS = 1
3762 00:43:15.670789 NEW_8X_MODE = 1
3763 00:43:15.674486 ===================================
3764 00:43:15.678020 ===================================
3765 00:43:15.680915 data_rate = 1200
3766 00:43:15.684366 CKR = 1
3767 00:43:15.687555 DQ_P2S_RATIO = 8
3768 00:43:15.690997 ===================================
3769 00:43:15.694037 CA_P2S_RATIO = 8
3770 00:43:15.697837 DQ_CA_OPEN = 0
3771 00:43:15.697905 DQ_SEMI_OPEN = 0
3772 00:43:15.701135 CA_SEMI_OPEN = 0
3773 00:43:15.704360 CA_FULL_RATE = 0
3774 00:43:15.707714 DQ_CKDIV4_EN = 1
3775 00:43:15.711037 CA_CKDIV4_EN = 1
3776 00:43:15.714456 CA_PREDIV_EN = 0
3777 00:43:15.714531 PH8_DLY = 0
3778 00:43:15.717786 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3779 00:43:15.721129 DQ_AAMCK_DIV = 4
3780 00:43:15.724449 CA_AAMCK_DIV = 4
3781 00:43:15.727717 CA_ADMCK_DIV = 4
3782 00:43:15.730384 DQ_TRACK_CA_EN = 0
3783 00:43:15.734044 CA_PICK = 600
3784 00:43:15.734138 CA_MCKIO = 600
3785 00:43:15.736915 MCKIO_SEMI = 0
3786 00:43:15.740445 PLL_FREQ = 2288
3787 00:43:15.743698 DQ_UI_PI_RATIO = 32
3788 00:43:15.746979 CA_UI_PI_RATIO = 0
3789 00:43:15.750175 ===================================
3790 00:43:15.753761 ===================================
3791 00:43:15.757097 memory_type:LPDDR4
3792 00:43:15.757201 GP_NUM : 10
3793 00:43:15.760403 SRAM_EN : 1
3794 00:43:15.760495 MD32_EN : 0
3795 00:43:15.763706 ===================================
3796 00:43:15.767017 [ANA_INIT] >>>>>>>>>>>>>>
3797 00:43:15.770274 <<<<<< [CONFIGURE PHASE]: ANA_TX
3798 00:43:15.773626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3799 00:43:15.776969 ===================================
3800 00:43:15.779792 data_rate = 1200,PCW = 0X5800
3801 00:43:15.783685 ===================================
3802 00:43:15.786952 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3803 00:43:15.793442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 00:43:15.796487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 00:43:15.803149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3806 00:43:15.806711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3807 00:43:15.810237 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3808 00:43:15.810310 [ANA_INIT] flow start
3809 00:43:15.813362 [ANA_INIT] PLL >>>>>>>>
3810 00:43:15.816507 [ANA_INIT] PLL <<<<<<<<
3811 00:43:15.816583 [ANA_INIT] MIDPI >>>>>>>>
3812 00:43:15.820142 [ANA_INIT] MIDPI <<<<<<<<
3813 00:43:15.823122 [ANA_INIT] DLL >>>>>>>>
3814 00:43:15.823197 [ANA_INIT] flow end
3815 00:43:15.830373 ============ LP4 DIFF to SE enter ============
3816 00:43:15.833551 ============ LP4 DIFF to SE exit ============
3817 00:43:15.836870 [ANA_INIT] <<<<<<<<<<<<<
3818 00:43:15.840260 [Flow] Enable top DCM control >>>>>
3819 00:43:15.843442 [Flow] Enable top DCM control <<<<<
3820 00:43:15.843535 Enable DLL master slave shuffle
3821 00:43:15.849977 ==============================================================
3822 00:43:15.853174 Gating Mode config
3823 00:43:15.856878 ==============================================================
3824 00:43:15.859918 Config description:
3825 00:43:15.869713 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3826 00:43:15.876409 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3827 00:43:15.879606 SELPH_MODE 0: By rank 1: By Phase
3828 00:43:15.886428 ==============================================================
3829 00:43:15.889766 GAT_TRACK_EN = 1
3830 00:43:15.893126 RX_GATING_MODE = 2
3831 00:43:15.896475 RX_GATING_TRACK_MODE = 2
3832 00:43:15.896579 SELPH_MODE = 1
3833 00:43:15.899896 PICG_EARLY_EN = 1
3834 00:43:15.903021 VALID_LAT_VALUE = 1
3835 00:43:15.909807 ==============================================================
3836 00:43:15.912951 Enter into Gating configuration >>>>
3837 00:43:15.916231 Exit from Gating configuration <<<<
3838 00:43:15.919628 Enter into DVFS_PRE_config >>>>>
3839 00:43:15.929530 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3840 00:43:15.932743 Exit from DVFS_PRE_config <<<<<
3841 00:43:15.936003 Enter into PICG configuration >>>>
3842 00:43:15.939559 Exit from PICG configuration <<<<
3843 00:43:15.942564 [RX_INPUT] configuration >>>>>
3844 00:43:15.946131 [RX_INPUT] configuration <<<<<
3845 00:43:15.949736 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3846 00:43:15.956010 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3847 00:43:15.963115 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 00:43:15.969477 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 00:43:15.976408 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 00:43:15.979150 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 00:43:15.986302 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3852 00:43:15.989751 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3853 00:43:15.992477 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3854 00:43:15.995791 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3855 00:43:15.999142 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3856 00:43:16.005975 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3857 00:43:16.009375 ===================================
3858 00:43:16.012483 LPDDR4 DRAM CONFIGURATION
3859 00:43:16.015746 ===================================
3860 00:43:16.015819 EX_ROW_EN[0] = 0x0
3861 00:43:16.019334 EX_ROW_EN[1] = 0x0
3862 00:43:16.019401 LP4Y_EN = 0x0
3863 00:43:16.022747 WORK_FSP = 0x0
3864 00:43:16.022842 WL = 0x2
3865 00:43:16.025781 RL = 0x2
3866 00:43:16.025856 BL = 0x2
3867 00:43:16.029120 RPST = 0x0
3868 00:43:16.029185 RD_PRE = 0x0
3869 00:43:16.032521 WR_PRE = 0x1
3870 00:43:16.032587 WR_PST = 0x0
3871 00:43:16.035932 DBI_WR = 0x0
3872 00:43:16.035997 DBI_RD = 0x0
3873 00:43:16.039326 OTF = 0x1
3874 00:43:16.042740 ===================================
3875 00:43:16.046030 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3876 00:43:16.049281 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3877 00:43:16.056009 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 00:43:16.059160 ===================================
3879 00:43:16.059229 LPDDR4 DRAM CONFIGURATION
3880 00:43:16.062609 ===================================
3881 00:43:16.065643 EX_ROW_EN[0] = 0x10
3882 00:43:16.069393 EX_ROW_EN[1] = 0x0
3883 00:43:16.069486 LP4Y_EN = 0x0
3884 00:43:16.072295 WORK_FSP = 0x0
3885 00:43:16.072366 WL = 0x2
3886 00:43:16.076216 RL = 0x2
3887 00:43:16.076286 BL = 0x2
3888 00:43:16.078970 RPST = 0x0
3889 00:43:16.079039 RD_PRE = 0x0
3890 00:43:16.082360 WR_PRE = 0x1
3891 00:43:16.082432 WR_PST = 0x0
3892 00:43:16.085608 DBI_WR = 0x0
3893 00:43:16.085683 DBI_RD = 0x0
3894 00:43:16.089229 OTF = 0x1
3895 00:43:16.092843 ===================================
3896 00:43:16.098820 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3897 00:43:16.102815 nWR fixed to 30
3898 00:43:16.102883 [ModeRegInit_LP4] CH0 RK0
3899 00:43:16.106169 [ModeRegInit_LP4] CH0 RK1
3900 00:43:16.108892 [ModeRegInit_LP4] CH1 RK0
3901 00:43:16.112310 [ModeRegInit_LP4] CH1 RK1
3902 00:43:16.112374 match AC timing 17
3903 00:43:16.119106 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3904 00:43:16.122473 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3905 00:43:16.125629 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3906 00:43:16.129263 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3907 00:43:16.135719 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3908 00:43:16.135789 ==
3909 00:43:16.139059 Dram Type= 6, Freq= 0, CH_0, rank 0
3910 00:43:16.142469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3911 00:43:16.142546 ==
3912 00:43:16.149001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3913 00:43:16.155681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3914 00:43:16.158931 [CA 0] Center 35 (5~66) winsize 62
3915 00:43:16.162336 [CA 1] Center 35 (5~66) winsize 62
3916 00:43:16.165689 [CA 2] Center 33 (3~64) winsize 62
3917 00:43:16.169005 [CA 3] Center 33 (2~64) winsize 63
3918 00:43:16.172405 [CA 4] Center 32 (2~63) winsize 62
3919 00:43:16.175679 [CA 5] Center 32 (2~63) winsize 62
3920 00:43:16.175747
3921 00:43:16.178789 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3922 00:43:16.178906
3923 00:43:16.182264 [CATrainingPosCal] consider 1 rank data
3924 00:43:16.185630 u2DelayCellTimex100 = 270/100 ps
3925 00:43:16.188817 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3926 00:43:16.192118 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3927 00:43:16.195476 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3928 00:43:16.199096 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3929 00:43:16.202103 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3930 00:43:16.205272 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3931 00:43:16.205384
3932 00:43:16.209131 CA PerBit enable=1, Macro0, CA PI delay=32
3933 00:43:16.212244
3934 00:43:16.212339 [CBTSetCACLKResult] CA Dly = 32
3935 00:43:16.215297 CS Dly: 4 (0~35)
3936 00:43:16.215408 ==
3937 00:43:16.218969 Dram Type= 6, Freq= 0, CH_0, rank 1
3938 00:43:16.222039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 00:43:16.222148 ==
3940 00:43:16.228955 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3941 00:43:16.235725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3942 00:43:16.238997 [CA 0] Center 35 (5~66) winsize 62
3943 00:43:16.242118 [CA 1] Center 35 (5~66) winsize 62
3944 00:43:16.245343 [CA 2] Center 34 (3~65) winsize 63
3945 00:43:16.248874 [CA 3] Center 33 (3~64) winsize 62
3946 00:43:16.252239 [CA 4] Center 32 (2~63) winsize 62
3947 00:43:16.255504 [CA 5] Center 32 (2~63) winsize 62
3948 00:43:16.255585
3949 00:43:16.258784 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3950 00:43:16.258853
3951 00:43:16.262176 [CATrainingPosCal] consider 2 rank data
3952 00:43:16.265432 u2DelayCellTimex100 = 270/100 ps
3953 00:43:16.268907 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3954 00:43:16.272281 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3955 00:43:16.275646 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3956 00:43:16.278971 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3957 00:43:16.282248 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3958 00:43:16.285606 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3959 00:43:16.285685
3960 00:43:16.292343 CA PerBit enable=1, Macro0, CA PI delay=32
3961 00:43:16.292414
3962 00:43:16.292471 [CBTSetCACLKResult] CA Dly = 32
3963 00:43:16.295811 CS Dly: 4 (0~36)
3964 00:43:16.295880
3965 00:43:16.299057 ----->DramcWriteLeveling(PI) begin...
3966 00:43:16.299123 ==
3967 00:43:16.302017 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 00:43:16.305508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 00:43:16.305603 ==
3970 00:43:16.309137 Write leveling (Byte 0): 33 => 33
3971 00:43:16.312045 Write leveling (Byte 1): 30 => 30
3972 00:43:16.315115 DramcWriteLeveling(PI) end<-----
3973 00:43:16.315232
3974 00:43:16.315324 ==
3975 00:43:16.318539 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 00:43:16.322214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 00:43:16.325212 ==
3978 00:43:16.325323 [Gating] SW mode calibration
3979 00:43:16.335100 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3980 00:43:16.338204 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3981 00:43:16.341745 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 00:43:16.348312 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 00:43:16.352124 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 00:43:16.355413 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
3985 00:43:16.361633 0 9 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
3986 00:43:16.364927 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 00:43:16.368318 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 00:43:16.375447 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 00:43:16.378809 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 00:43:16.381561 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 00:43:16.388284 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 00:43:16.391545 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
3993 00:43:16.394850 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
3994 00:43:16.402043 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 00:43:16.405490 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 00:43:16.408864 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 00:43:16.411889 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 00:43:16.418615 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 00:43:16.421931 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 00:43:16.425231 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 00:43:16.432138 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4002 00:43:16.435365 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 00:43:16.438570 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 00:43:16.444901 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 00:43:16.448564 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 00:43:16.451587 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 00:43:16.458732 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 00:43:16.461593 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 00:43:16.465160 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:43:16.471904 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:43:16.474913 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:43:16.478549 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 00:43:16.485432 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 00:43:16.488484 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 00:43:16.491799 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 00:43:16.498462 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 00:43:16.501822 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 00:43:16.505171 Total UI for P1: 0, mck2ui 16
4019 00:43:16.508417 best dqsien dly found for B0: ( 0, 13, 14)
4020 00:43:16.511767 Total UI for P1: 0, mck2ui 16
4021 00:43:16.515076 best dqsien dly found for B1: ( 0, 13, 14)
4022 00:43:16.518519 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4023 00:43:16.522163 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4024 00:43:16.522240
4025 00:43:16.524805 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4026 00:43:16.528553 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4027 00:43:16.531804 [Gating] SW calibration Done
4028 00:43:16.531881 ==
4029 00:43:16.535089 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 00:43:16.538430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 00:43:16.538506 ==
4032 00:43:16.541504 RX Vref Scan: 0
4033 00:43:16.541583
4034 00:43:16.545223 RX Vref 0 -> 0, step: 1
4035 00:43:16.545294
4036 00:43:16.545386 RX Delay -230 -> 252, step: 16
4037 00:43:16.551617 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4038 00:43:16.555057 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4039 00:43:16.558281 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4040 00:43:16.561536 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4041 00:43:16.568019 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4042 00:43:16.571681 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4043 00:43:16.574572 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4044 00:43:16.578127 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4045 00:43:16.581413 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4046 00:43:16.588233 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4047 00:43:16.591876 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4048 00:43:16.594726 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4049 00:43:16.598083 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4050 00:43:16.605117 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4051 00:43:16.608380 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4052 00:43:16.611760 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4053 00:43:16.611838 ==
4054 00:43:16.615159 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 00:43:16.618586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 00:43:16.618669 ==
4057 00:43:16.621941 DQS Delay:
4058 00:43:16.622020 DQS0 = 0, DQS1 = 0
4059 00:43:16.625152 DQM Delay:
4060 00:43:16.625229 DQM0 = 53, DQM1 = 46
4061 00:43:16.625290 DQ Delay:
4062 00:43:16.628557 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4063 00:43:16.631561 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4064 00:43:16.634779 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4065 00:43:16.638083 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4066 00:43:16.638160
4067 00:43:16.638220
4068 00:43:16.641389 ==
4069 00:43:16.644723 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 00:43:16.648082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 00:43:16.648177 ==
4072 00:43:16.648262
4073 00:43:16.648352
4074 00:43:16.651400 TX Vref Scan disable
4075 00:43:16.651467 == TX Byte 0 ==
4076 00:43:16.657835 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4077 00:43:16.661519 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4078 00:43:16.661612 == TX Byte 1 ==
4079 00:43:16.667947 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4080 00:43:16.671091 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4081 00:43:16.671168 ==
4082 00:43:16.674791 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 00:43:16.678289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 00:43:16.678367 ==
4085 00:43:16.678441
4086 00:43:16.678512
4087 00:43:16.681618 TX Vref Scan disable
4088 00:43:16.684946 == TX Byte 0 ==
4089 00:43:16.687967 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4090 00:43:16.691365 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4091 00:43:16.694274 == TX Byte 1 ==
4092 00:43:16.698054 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4093 00:43:16.701258 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4094 00:43:16.701363
4095 00:43:16.704337 [DATLAT]
4096 00:43:16.704409 Freq=600, CH0 RK0
4097 00:43:16.704482
4098 00:43:16.707860 DATLAT Default: 0x9
4099 00:43:16.707951 0, 0xFFFF, sum = 0
4100 00:43:16.711340 1, 0xFFFF, sum = 0
4101 00:43:16.711409 2, 0xFFFF, sum = 0
4102 00:43:16.714397 3, 0xFFFF, sum = 0
4103 00:43:16.714470 4, 0xFFFF, sum = 0
4104 00:43:16.717793 5, 0xFFFF, sum = 0
4105 00:43:16.717862 6, 0xFFFF, sum = 0
4106 00:43:16.721136 7, 0xFFFF, sum = 0
4107 00:43:16.721204 8, 0x0, sum = 1
4108 00:43:16.724407 9, 0x0, sum = 2
4109 00:43:16.724475 10, 0x0, sum = 3
4110 00:43:16.727789 11, 0x0, sum = 4
4111 00:43:16.727859 best_step = 9
4112 00:43:16.727949
4113 00:43:16.728040 ==
4114 00:43:16.731110 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 00:43:16.737818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 00:43:16.737894 ==
4117 00:43:16.737969 RX Vref Scan: 1
4118 00:43:16.738040
4119 00:43:16.741115 RX Vref 0 -> 0, step: 1
4120 00:43:16.741222
4121 00:43:16.744235 RX Delay -163 -> 252, step: 8
4122 00:43:16.744326
4123 00:43:16.747825 Set Vref, RX VrefLevel [Byte0]: 53
4124 00:43:16.751008 [Byte1]: 50
4125 00:43:16.751102
4126 00:43:16.754366 Final RX Vref Byte 0 = 53 to rank0
4127 00:43:16.757715 Final RX Vref Byte 1 = 50 to rank0
4128 00:43:16.761008 Final RX Vref Byte 0 = 53 to rank1
4129 00:43:16.764397 Final RX Vref Byte 1 = 50 to rank1==
4130 00:43:16.767547 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 00:43:16.770708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 00:43:16.770782 ==
4133 00:43:16.770839 DQS Delay:
4134 00:43:16.774352 DQS0 = 0, DQS1 = 0
4135 00:43:16.774423 DQM Delay:
4136 00:43:16.777358 DQM0 = 52, DQM1 = 46
4137 00:43:16.777459 DQ Delay:
4138 00:43:16.781067 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4139 00:43:16.784144 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4140 00:43:16.787606 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4141 00:43:16.790964 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4142 00:43:16.791031
4143 00:43:16.791087
4144 00:43:16.800859 [DQSOSCAuto] RK0, (LSB)MR18= 0x7366, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4145 00:43:16.800963 CH0 RK0: MR19=808, MR18=7366
4146 00:43:16.807673 CH0_RK0: MR19=0x808, MR18=0x7366, DQSOSC=388, MR23=63, INC=174, DEC=116
4147 00:43:16.807774
4148 00:43:16.810967 ----->DramcWriteLeveling(PI) begin...
4149 00:43:16.811050 ==
4150 00:43:16.814235 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 00:43:16.820850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 00:43:16.820922 ==
4153 00:43:16.824218 Write leveling (Byte 0): 35 => 35
4154 00:43:16.827524 Write leveling (Byte 1): 31 => 31
4155 00:43:16.827623 DramcWriteLeveling(PI) end<-----
4156 00:43:16.827707
4157 00:43:16.830813 ==
4158 00:43:16.834270 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 00:43:16.837486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 00:43:16.837580 ==
4161 00:43:16.840997 [Gating] SW mode calibration
4162 00:43:16.847740 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4163 00:43:16.850504 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4164 00:43:16.857759 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 00:43:16.860733 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 00:43:16.864184 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 00:43:16.870649 0 9 12 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 0)
4168 00:43:16.873816 0 9 16 | B1->B0 | 2929 2424 | 1 0 | (1 0) (0 0)
4169 00:43:16.877197 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 00:43:16.883958 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 00:43:16.887895 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 00:43:16.890885 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 00:43:16.897515 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 00:43:16.900707 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 00:43:16.904332 0 10 12 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (0 0)
4176 00:43:16.910817 0 10 16 | B1->B0 | 3a3a 3e3e | 1 0 | (0 0) (0 0)
4177 00:43:16.913997 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 00:43:16.917002 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 00:43:16.920438 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 00:43:16.927250 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 00:43:16.930817 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 00:43:16.933646 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 00:43:16.940792 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4184 00:43:16.944072 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4185 00:43:16.947404 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 00:43:16.954250 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 00:43:16.957002 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 00:43:16.960320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 00:43:16.967093 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 00:43:16.970589 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 00:43:16.973917 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 00:43:16.980409 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 00:43:16.983712 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 00:43:16.987094 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 00:43:16.993846 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 00:43:16.997267 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 00:43:17.000471 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 00:43:17.006858 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 00:43:17.010180 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4200 00:43:17.013840 Total UI for P1: 0, mck2ui 16
4201 00:43:17.016869 best dqsien dly found for B0: ( 0, 13, 10)
4202 00:43:17.020192 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 00:43:17.023396 Total UI for P1: 0, mck2ui 16
4204 00:43:17.026793 best dqsien dly found for B1: ( 0, 13, 12)
4205 00:43:17.030259 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4206 00:43:17.033237 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4207 00:43:17.033309
4208 00:43:17.040440 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4209 00:43:17.043276 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4210 00:43:17.043350 [Gating] SW calibration Done
4211 00:43:17.046885 ==
4212 00:43:17.049938 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 00:43:17.053215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 00:43:17.053290 ==
4215 00:43:17.053364 RX Vref Scan: 0
4216 00:43:17.053454
4217 00:43:17.056912 RX Vref 0 -> 0, step: 1
4218 00:43:17.056988
4219 00:43:17.060135 RX Delay -230 -> 252, step: 16
4220 00:43:17.063555 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4221 00:43:17.066887 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4222 00:43:17.073535 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4223 00:43:17.076795 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4224 00:43:17.079717 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4225 00:43:17.083253 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4226 00:43:17.089741 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4227 00:43:17.093048 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4228 00:43:17.096476 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4229 00:43:17.099656 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4230 00:43:17.103027 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4231 00:43:17.109790 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4232 00:43:17.112947 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4233 00:43:17.116062 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4234 00:43:17.119985 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4235 00:43:17.125958 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4236 00:43:17.126044 ==
4237 00:43:17.129770 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 00:43:17.132942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 00:43:17.133011 ==
4240 00:43:17.133069 DQS Delay:
4241 00:43:17.135960 DQS0 = 0, DQS1 = 0
4242 00:43:17.136048 DQM Delay:
4243 00:43:17.139789 DQM0 = 51, DQM1 = 42
4244 00:43:17.139878 DQ Delay:
4245 00:43:17.143215 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4246 00:43:17.146455 DQ4 =57, DQ5 =41, DQ6 =49, DQ7 =65
4247 00:43:17.149756 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4248 00:43:17.153062 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4249 00:43:17.153153
4250 00:43:17.153246
4251 00:43:17.153328 ==
4252 00:43:17.156406 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 00:43:17.159511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 00:43:17.159581 ==
4255 00:43:17.162439
4256 00:43:17.162503
4257 00:43:17.162557 TX Vref Scan disable
4258 00:43:17.165903 == TX Byte 0 ==
4259 00:43:17.169625 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4260 00:43:17.172775 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4261 00:43:17.175807 == TX Byte 1 ==
4262 00:43:17.179341 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4263 00:43:17.182471 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4264 00:43:17.182542 ==
4265 00:43:17.185923 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 00:43:17.192744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 00:43:17.192822 ==
4268 00:43:17.192880
4269 00:43:17.192933
4270 00:43:17.192984 TX Vref Scan disable
4271 00:43:17.197358 == TX Byte 0 ==
4272 00:43:17.200721 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4273 00:43:17.207820 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4274 00:43:17.207892 == TX Byte 1 ==
4275 00:43:17.210581 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4276 00:43:17.213944 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4277 00:43:17.217336
4278 00:43:17.217402 [DATLAT]
4279 00:43:17.217457 Freq=600, CH0 RK1
4280 00:43:17.217515
4281 00:43:17.220636 DATLAT Default: 0x9
4282 00:43:17.220714 0, 0xFFFF, sum = 0
4283 00:43:17.223955 1, 0xFFFF, sum = 0
4284 00:43:17.224029 2, 0xFFFF, sum = 0
4285 00:43:17.227305 3, 0xFFFF, sum = 0
4286 00:43:17.230639 4, 0xFFFF, sum = 0
4287 00:43:17.230708 5, 0xFFFF, sum = 0
4288 00:43:17.234028 6, 0xFFFF, sum = 0
4289 00:43:17.234099 7, 0xFFFF, sum = 0
4290 00:43:17.237335 8, 0x0, sum = 1
4291 00:43:17.237406 9, 0x0, sum = 2
4292 00:43:17.237462 10, 0x0, sum = 3
4293 00:43:17.240787 11, 0x0, sum = 4
4294 00:43:17.240857 best_step = 9
4295 00:43:17.240911
4296 00:43:17.240962 ==
4297 00:43:17.243977 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 00:43:17.250459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 00:43:17.250534 ==
4300 00:43:17.250591 RX Vref Scan: 0
4301 00:43:17.250644
4302 00:43:17.253864 RX Vref 0 -> 0, step: 1
4303 00:43:17.253928
4304 00:43:17.257129 RX Delay -163 -> 252, step: 8
4305 00:43:17.260752 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4306 00:43:17.266951 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4307 00:43:17.270480 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4308 00:43:17.273647 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4309 00:43:17.276943 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4310 00:43:17.280597 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4311 00:43:17.284144 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4312 00:43:17.290692 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4313 00:43:17.293692 iDelay=197, Bit 8, Center 40 (-99 ~ 180) 280
4314 00:43:17.297352 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4315 00:43:17.300744 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4316 00:43:17.303856 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4317 00:43:17.310569 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4318 00:43:17.313615 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4319 00:43:17.317382 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4320 00:43:17.320669 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4321 00:43:17.320750 ==
4322 00:43:17.323918 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 00:43:17.330396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 00:43:17.330469 ==
4325 00:43:17.330533 DQS Delay:
4326 00:43:17.334200 DQS0 = 0, DQS1 = 0
4327 00:43:17.334267 DQM Delay:
4328 00:43:17.334323 DQM0 = 53, DQM1 = 47
4329 00:43:17.337638 DQ Delay:
4330 00:43:17.340260 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4331 00:43:17.343610 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4332 00:43:17.347015 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4333 00:43:17.350385 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4334 00:43:17.350454
4335 00:43:17.350510
4336 00:43:17.357652 [DQSOSCAuto] RK1, (LSB)MR18= 0x6727, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4337 00:43:17.360796 CH0 RK1: MR19=808, MR18=6727
4338 00:43:17.367335 CH0_RK1: MR19=0x808, MR18=0x6727, DQSOSC=390, MR23=63, INC=172, DEC=114
4339 00:43:17.370544 [RxdqsGatingPostProcess] freq 600
4340 00:43:17.373905 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4341 00:43:17.377224 Pre-setting of DQS Precalculation
4342 00:43:17.384032 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4343 00:43:17.384134 ==
4344 00:43:17.386865 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 00:43:17.390278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 00:43:17.390379 ==
4347 00:43:17.396975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4348 00:43:17.403589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4349 00:43:17.407187 [CA 0] Center 36 (5~67) winsize 63
4350 00:43:17.410507 [CA 1] Center 36 (5~67) winsize 63
4351 00:43:17.413828 [CA 2] Center 34 (4~65) winsize 62
4352 00:43:17.417242 [CA 3] Center 34 (4~65) winsize 62
4353 00:43:17.420204 [CA 4] Center 34 (4~65) winsize 62
4354 00:43:17.420316 [CA 5] Center 33 (3~64) winsize 62
4355 00:43:17.423462
4356 00:43:17.426782 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4357 00:43:17.426880
4358 00:43:17.430535 [CATrainingPosCal] consider 1 rank data
4359 00:43:17.433472 u2DelayCellTimex100 = 270/100 ps
4360 00:43:17.436861 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4361 00:43:17.440119 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4362 00:43:17.443465 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4363 00:43:17.446852 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4364 00:43:17.450324 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4365 00:43:17.453654 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4366 00:43:17.453765
4367 00:43:17.457054 CA PerBit enable=1, Macro0, CA PI delay=33
4368 00:43:17.457147
4369 00:43:17.460333 [CBTSetCACLKResult] CA Dly = 33
4370 00:43:17.463726 CS Dly: 7 (0~38)
4371 00:43:17.463796 ==
4372 00:43:17.467080 Dram Type= 6, Freq= 0, CH_1, rank 1
4373 00:43:17.470472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 00:43:17.470546 ==
4375 00:43:17.476903 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 00:43:17.483479 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4377 00:43:17.486894 [CA 0] Center 36 (6~67) winsize 62
4378 00:43:17.490282 [CA 1] Center 36 (6~67) winsize 62
4379 00:43:17.493660 [CA 2] Center 35 (4~66) winsize 63
4380 00:43:17.497049 [CA 3] Center 35 (4~66) winsize 63
4381 00:43:17.500325 [CA 4] Center 35 (4~66) winsize 63
4382 00:43:17.503667 [CA 5] Center 34 (4~65) winsize 62
4383 00:43:17.503738
4384 00:43:17.506909 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4385 00:43:17.506982
4386 00:43:17.510326 [CATrainingPosCal] consider 2 rank data
4387 00:43:17.513404 u2DelayCellTimex100 = 270/100 ps
4388 00:43:17.516671 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4389 00:43:17.520318 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4390 00:43:17.523413 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4391 00:43:17.526717 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 00:43:17.530397 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4393 00:43:17.533566 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4394 00:43:17.533664
4395 00:43:17.540264 CA PerBit enable=1, Macro0, CA PI delay=34
4396 00:43:17.540351
4397 00:43:17.540466 [CBTSetCACLKResult] CA Dly = 34
4398 00:43:17.543316 CS Dly: 6 (0~37)
4399 00:43:17.543395
4400 00:43:17.546883 ----->DramcWriteLeveling(PI) begin...
4401 00:43:17.546971 ==
4402 00:43:17.550010 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 00:43:17.553386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 00:43:17.553496 ==
4405 00:43:17.556633 Write leveling (Byte 0): 29 => 29
4406 00:43:17.560331 Write leveling (Byte 1): 29 => 29
4407 00:43:17.563812 DramcWriteLeveling(PI) end<-----
4408 00:43:17.563883
4409 00:43:17.563941 ==
4410 00:43:17.566427 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 00:43:17.569899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 00:43:17.573824 ==
4413 00:43:17.573902 [Gating] SW mode calibration
4414 00:43:17.579805 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4415 00:43:17.586457 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4416 00:43:17.589767 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 00:43:17.596666 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 00:43:17.600155 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4419 00:43:17.603019 0 9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)
4420 00:43:17.609883 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4421 00:43:17.613617 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 00:43:17.616900 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 00:43:17.623372 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 00:43:17.626537 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 00:43:17.629641 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 00:43:17.633527 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 00:43:17.639821 0 10 12 | B1->B0 | 3636 3c3c | 0 0 | (0 0) (0 0)
4428 00:43:17.643151 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 00:43:17.646534 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 00:43:17.653493 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 00:43:17.656697 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 00:43:17.659737 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 00:43:17.666819 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 00:43:17.669502 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 00:43:17.673252 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4436 00:43:17.679616 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 00:43:17.683059 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 00:43:17.686370 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 00:43:17.693027 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 00:43:17.696353 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 00:43:17.699759 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 00:43:17.706327 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 00:43:17.710025 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 00:43:17.713021 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 00:43:17.719798 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 00:43:17.723307 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:43:17.726387 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 00:43:17.733009 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 00:43:17.736607 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 00:43:17.740151 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4451 00:43:17.742986 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4452 00:43:17.750021 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 00:43:17.752742 Total UI for P1: 0, mck2ui 16
4454 00:43:17.756124 best dqsien dly found for B0: ( 0, 13, 10)
4455 00:43:17.759869 Total UI for P1: 0, mck2ui 16
4456 00:43:17.763108 best dqsien dly found for B1: ( 0, 13, 12)
4457 00:43:17.766386 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4458 00:43:17.769775 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4459 00:43:17.769846
4460 00:43:17.772995 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4461 00:43:17.776037 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4462 00:43:17.779578 [Gating] SW calibration Done
4463 00:43:17.779670 ==
4464 00:43:17.783001 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 00:43:17.786991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 00:43:17.787060 ==
4467 00:43:17.789825 RX Vref Scan: 0
4468 00:43:17.789916
4469 00:43:17.793124 RX Vref 0 -> 0, step: 1
4470 00:43:17.793218
4471 00:43:17.793299 RX Delay -230 -> 252, step: 16
4472 00:43:17.799845 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4473 00:43:17.803160 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4474 00:43:17.806567 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4475 00:43:17.809298 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4476 00:43:17.816376 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4477 00:43:17.819411 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4478 00:43:17.823202 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4479 00:43:17.825931 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4480 00:43:17.829791 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4481 00:43:17.836053 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4482 00:43:17.839477 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4483 00:43:17.842585 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4484 00:43:17.846413 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4485 00:43:17.852403 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4486 00:43:17.855934 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4487 00:43:17.859360 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4488 00:43:17.859436 ==
4489 00:43:17.862468 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 00:43:17.866324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 00:43:17.869453 ==
4492 00:43:17.869562 DQS Delay:
4493 00:43:17.869686 DQS0 = 0, DQS1 = 0
4494 00:43:17.872812 DQM Delay:
4495 00:43:17.872884 DQM0 = 50, DQM1 = 46
4496 00:43:17.876144 DQ Delay:
4497 00:43:17.876210 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4498 00:43:17.879520 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4499 00:43:17.882685 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4500 00:43:17.885902 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4501 00:43:17.885991
4502 00:43:17.889714
4503 00:43:17.889814 ==
4504 00:43:17.892855 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 00:43:17.896301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 00:43:17.896396 ==
4507 00:43:17.896479
4508 00:43:17.896556
4509 00:43:17.899036 TX Vref Scan disable
4510 00:43:17.899154 == TX Byte 0 ==
4511 00:43:17.905778 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4512 00:43:17.909670 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4513 00:43:17.909745 == TX Byte 1 ==
4514 00:43:17.912963 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4515 00:43:17.919528 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4516 00:43:17.919631 ==
4517 00:43:17.922989 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 00:43:17.926111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 00:43:17.926183 ==
4520 00:43:17.926241
4521 00:43:17.926295
4522 00:43:17.929308 TX Vref Scan disable
4523 00:43:17.932659 == TX Byte 0 ==
4524 00:43:17.935855 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4525 00:43:17.939814 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4526 00:43:17.942966 == TX Byte 1 ==
4527 00:43:17.946122 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4528 00:43:17.949363 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4529 00:43:17.949454
4530 00:43:17.952595 [DATLAT]
4531 00:43:17.952661 Freq=600, CH1 RK0
4532 00:43:17.952716
4533 00:43:17.955585 DATLAT Default: 0x9
4534 00:43:17.955645 0, 0xFFFF, sum = 0
4535 00:43:17.959014 1, 0xFFFF, sum = 0
4536 00:43:17.959081 2, 0xFFFF, sum = 0
4537 00:43:17.962226 3, 0xFFFF, sum = 0
4538 00:43:17.962294 4, 0xFFFF, sum = 0
4539 00:43:17.965887 5, 0xFFFF, sum = 0
4540 00:43:17.965953 6, 0xFFFF, sum = 0
4541 00:43:17.969435 7, 0xFFFF, sum = 0
4542 00:43:17.969527 8, 0x0, sum = 1
4543 00:43:17.972348 9, 0x0, sum = 2
4544 00:43:17.972442 10, 0x0, sum = 3
4545 00:43:17.975741 11, 0x0, sum = 4
4546 00:43:17.975829 best_step = 9
4547 00:43:17.975914
4548 00:43:17.975994 ==
4549 00:43:17.979326 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 00:43:17.982330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 00:43:17.985674 ==
4552 00:43:17.985736 RX Vref Scan: 1
4553 00:43:17.985791
4554 00:43:17.989072 RX Vref 0 -> 0, step: 1
4555 00:43:17.989160
4556 00:43:17.992239 RX Delay -163 -> 252, step: 8
4557 00:43:17.992327
4558 00:43:17.995420 Set Vref, RX VrefLevel [Byte0]: 53
4559 00:43:17.998829 [Byte1]: 45
4560 00:43:17.998901
4561 00:43:18.002300 Final RX Vref Byte 0 = 53 to rank0
4562 00:43:18.005375 Final RX Vref Byte 1 = 45 to rank0
4563 00:43:18.009147 Final RX Vref Byte 0 = 53 to rank1
4564 00:43:18.012263 Final RX Vref Byte 1 = 45 to rank1==
4565 00:43:18.015662 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 00:43:18.019031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 00:43:18.019097 ==
4568 00:43:18.022239 DQS Delay:
4569 00:43:18.022303 DQS0 = 0, DQS1 = 0
4570 00:43:18.022362 DQM Delay:
4571 00:43:18.025704 DQM0 = 49, DQM1 = 45
4572 00:43:18.025766 DQ Delay:
4573 00:43:18.028965 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4574 00:43:18.032069 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4575 00:43:18.035430 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4576 00:43:18.038646 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4577 00:43:18.038721
4578 00:43:18.038779
4579 00:43:18.048420 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4580 00:43:18.048514 CH1 RK0: MR19=808, MR18=4C72
4581 00:43:18.055382 CH1_RK0: MR19=0x808, MR18=0x4C72, DQSOSC=388, MR23=63, INC=174, DEC=116
4582 00:43:18.055459
4583 00:43:18.058585 ----->DramcWriteLeveling(PI) begin...
4584 00:43:18.058661 ==
4585 00:43:18.062517 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 00:43:18.068473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 00:43:18.068549 ==
4588 00:43:18.072272 Write leveling (Byte 0): 30 => 30
4589 00:43:18.075494 Write leveling (Byte 1): 30 => 30
4590 00:43:18.075586 DramcWriteLeveling(PI) end<-----
4591 00:43:18.078660
4592 00:43:18.078735 ==
4593 00:43:18.081806 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 00:43:18.085554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 00:43:18.085633 ==
4596 00:43:18.088489 [Gating] SW mode calibration
4597 00:43:18.095300 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4598 00:43:18.098417 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4599 00:43:18.104963 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4600 00:43:18.108304 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 00:43:18.111650 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 00:43:18.118145 0 9 12 | B1->B0 | 2d2d 2e2e | 0 1 | (0 0) (1 0)
4603 00:43:18.121640 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 00:43:18.125138 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 00:43:18.131496 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 00:43:18.134623 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 00:43:18.138605 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 00:43:18.144943 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 00:43:18.148175 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 00:43:18.151513 0 10 12 | B1->B0 | 3838 3c3c | 0 0 | (0 0) (0 0)
4611 00:43:18.158476 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 00:43:18.161673 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 00:43:18.164813 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 00:43:18.171379 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 00:43:18.174706 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 00:43:18.178518 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 00:43:18.185024 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 00:43:18.188376 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4619 00:43:18.191673 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 00:43:18.197907 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 00:43:18.201419 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 00:43:18.204708 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 00:43:18.211049 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 00:43:18.214328 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 00:43:18.217811 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 00:43:18.221109 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 00:43:18.227689 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 00:43:18.230849 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 00:43:18.234493 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 00:43:18.241354 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 00:43:18.244303 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 00:43:18.247948 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 00:43:18.254328 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4634 00:43:18.257511 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 00:43:18.260741 Total UI for P1: 0, mck2ui 16
4636 00:43:18.264746 best dqsien dly found for B0: ( 0, 13, 8)
4637 00:43:18.267462 Total UI for P1: 0, mck2ui 16
4638 00:43:18.270767 best dqsien dly found for B1: ( 0, 13, 8)
4639 00:43:18.274434 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4640 00:43:18.277352 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4641 00:43:18.277444
4642 00:43:18.280743 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4643 00:43:18.284493 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4644 00:43:18.287697 [Gating] SW calibration Done
4645 00:43:18.287791 ==
4646 00:43:18.290836 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 00:43:18.294342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 00:43:18.297762 ==
4649 00:43:18.297849 RX Vref Scan: 0
4650 00:43:18.297941
4651 00:43:18.301088 RX Vref 0 -> 0, step: 1
4652 00:43:18.301155
4653 00:43:18.304412 RX Delay -230 -> 252, step: 16
4654 00:43:18.307683 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4655 00:43:18.310783 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4656 00:43:18.314372 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4657 00:43:18.320963 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4658 00:43:18.324495 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4659 00:43:18.327165 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4660 00:43:18.331092 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4661 00:43:18.333843 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4662 00:43:18.340991 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4663 00:43:18.344196 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4664 00:43:18.347238 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4665 00:43:18.350873 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4666 00:43:18.357509 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4667 00:43:18.360935 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4668 00:43:18.363781 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4669 00:43:18.367374 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4670 00:43:18.367446 ==
4671 00:43:18.370491 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 00:43:18.377622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 00:43:18.377698 ==
4674 00:43:18.377769 DQS Delay:
4675 00:43:18.380903 DQS0 = 0, DQS1 = 0
4676 00:43:18.380969 DQM Delay:
4677 00:43:18.381042 DQM0 = 50, DQM1 = 46
4678 00:43:18.384121 DQ Delay:
4679 00:43:18.387260 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4680 00:43:18.390488 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4681 00:43:18.394312 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4682 00:43:18.397666 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4683 00:43:18.397744
4684 00:43:18.397798
4685 00:43:18.397849 ==
4686 00:43:18.400301 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 00:43:18.404297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 00:43:18.404359 ==
4689 00:43:18.404416
4690 00:43:18.404469
4691 00:43:18.407676 TX Vref Scan disable
4692 00:43:18.407741 == TX Byte 0 ==
4693 00:43:18.414349 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4694 00:43:18.417060 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4695 00:43:18.417126 == TX Byte 1 ==
4696 00:43:18.423732 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4697 00:43:18.427372 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4698 00:43:18.427442 ==
4699 00:43:18.430904 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 00:43:18.433721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 00:43:18.433788 ==
4702 00:43:18.433851
4703 00:43:18.433911
4704 00:43:18.437483 TX Vref Scan disable
4705 00:43:18.440827 == TX Byte 0 ==
4706 00:43:18.443582 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4707 00:43:18.447014 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4708 00:43:18.450395 == TX Byte 1 ==
4709 00:43:18.453739 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4710 00:43:18.457576 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4711 00:43:18.457651
4712 00:43:18.460906 [DATLAT]
4713 00:43:18.460968 Freq=600, CH1 RK1
4714 00:43:18.461028
4715 00:43:18.463994 DATLAT Default: 0x9
4716 00:43:18.464063 0, 0xFFFF, sum = 0
4717 00:43:18.467520 1, 0xFFFF, sum = 0
4718 00:43:18.467590 2, 0xFFFF, sum = 0
4719 00:43:18.470763 3, 0xFFFF, sum = 0
4720 00:43:18.470832 4, 0xFFFF, sum = 0
4721 00:43:18.474038 5, 0xFFFF, sum = 0
4722 00:43:18.474110 6, 0xFFFF, sum = 0
4723 00:43:18.477203 7, 0xFFFF, sum = 0
4724 00:43:18.477299 8, 0x0, sum = 1
4725 00:43:18.480655 9, 0x0, sum = 2
4726 00:43:18.480733 10, 0x0, sum = 3
4727 00:43:18.484110 11, 0x0, sum = 4
4728 00:43:18.484179 best_step = 9
4729 00:43:18.484235
4730 00:43:18.484287 ==
4731 00:43:18.487518 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 00:43:18.493920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 00:43:18.493997 ==
4734 00:43:18.494055 RX Vref Scan: 0
4735 00:43:18.494116
4736 00:43:18.496944 RX Vref 0 -> 0, step: 1
4737 00:43:18.497014
4738 00:43:18.500531 RX Delay -163 -> 252, step: 8
4739 00:43:18.504063 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4740 00:43:18.507066 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4741 00:43:18.513998 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4742 00:43:18.517302 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4743 00:43:18.520606 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4744 00:43:18.523951 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4745 00:43:18.527427 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4746 00:43:18.534020 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4747 00:43:18.536783 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4748 00:43:18.540227 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4749 00:43:18.544092 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4750 00:43:18.550427 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4751 00:43:18.553879 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4752 00:43:18.557090 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4753 00:43:18.560498 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4754 00:43:18.563717 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4755 00:43:18.567023 ==
4756 00:43:18.570181 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 00:43:18.573263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 00:43:18.573354 ==
4759 00:43:18.573437 DQS Delay:
4760 00:43:18.576995 DQS0 = 0, DQS1 = 0
4761 00:43:18.577088 DQM Delay:
4762 00:43:18.580245 DQM0 = 49, DQM1 = 45
4763 00:43:18.580315 DQ Delay:
4764 00:43:18.583604 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4765 00:43:18.586957 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4766 00:43:18.590283 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4767 00:43:18.593276 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4768 00:43:18.593378
4769 00:43:18.593465
4770 00:43:18.599952 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4771 00:43:18.603332 CH1 RK1: MR19=808, MR18=6C21
4772 00:43:18.609709 CH1_RK1: MR19=0x808, MR18=0x6C21, DQSOSC=389, MR23=63, INC=173, DEC=115
4773 00:43:18.613203 [RxdqsGatingPostProcess] freq 600
4774 00:43:18.619705 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4775 00:43:18.619786 Pre-setting of DQS Precalculation
4776 00:43:18.626710 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4777 00:43:18.633522 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4778 00:43:18.640354 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4779 00:43:18.640433
4780 00:43:18.640492
4781 00:43:18.643753 [Calibration Summary] 1200 Mbps
4782 00:43:18.646492 CH 0, Rank 0
4783 00:43:18.646570 SW Impedance : PASS
4784 00:43:18.649929 DUTY Scan : NO K
4785 00:43:18.650006 ZQ Calibration : PASS
4786 00:43:18.653392 Jitter Meter : NO K
4787 00:43:18.656683 CBT Training : PASS
4788 00:43:18.656761 Write leveling : PASS
4789 00:43:18.659988 RX DQS gating : PASS
4790 00:43:18.663197 RX DQ/DQS(RDDQC) : PASS
4791 00:43:18.663274 TX DQ/DQS : PASS
4792 00:43:18.666917 RX DATLAT : PASS
4793 00:43:18.669656 RX DQ/DQS(Engine): PASS
4794 00:43:18.669734 TX OE : NO K
4795 00:43:18.672981 All Pass.
4796 00:43:18.673058
4797 00:43:18.673119 CH 0, Rank 1
4798 00:43:18.676714 SW Impedance : PASS
4799 00:43:18.676792 DUTY Scan : NO K
4800 00:43:18.679660 ZQ Calibration : PASS
4801 00:43:18.682926 Jitter Meter : NO K
4802 00:43:18.683004 CBT Training : PASS
4803 00:43:18.686570 Write leveling : PASS
4804 00:43:18.689658 RX DQS gating : PASS
4805 00:43:18.689736 RX DQ/DQS(RDDQC) : PASS
4806 00:43:18.693472 TX DQ/DQS : PASS
4807 00:43:18.696156 RX DATLAT : PASS
4808 00:43:18.696234 RX DQ/DQS(Engine): PASS
4809 00:43:18.699455 TX OE : NO K
4810 00:43:18.699533 All Pass.
4811 00:43:18.699607
4812 00:43:18.703270 CH 1, Rank 0
4813 00:43:18.703348 SW Impedance : PASS
4814 00:43:18.706392 DUTY Scan : NO K
4815 00:43:18.706470 ZQ Calibration : PASS
4816 00:43:18.709529 Jitter Meter : NO K
4817 00:43:18.712834 CBT Training : PASS
4818 00:43:18.712910 Write leveling : PASS
4819 00:43:18.716117 RX DQS gating : PASS
4820 00:43:18.719488 RX DQ/DQS(RDDQC) : PASS
4821 00:43:18.719563 TX DQ/DQS : PASS
4822 00:43:18.722632 RX DATLAT : PASS
4823 00:43:18.725807 RX DQ/DQS(Engine): PASS
4824 00:43:18.725913 TX OE : NO K
4825 00:43:18.729453 All Pass.
4826 00:43:18.729529
4827 00:43:18.729621 CH 1, Rank 1
4828 00:43:18.732965 SW Impedance : PASS
4829 00:43:18.733041 DUTY Scan : NO K
4830 00:43:18.735892 ZQ Calibration : PASS
4831 00:43:18.739339 Jitter Meter : NO K
4832 00:43:18.739415 CBT Training : PASS
4833 00:43:18.742800 Write leveling : PASS
4834 00:43:18.746284 RX DQS gating : PASS
4835 00:43:18.746375 RX DQ/DQS(RDDQC) : PASS
4836 00:43:18.749207 TX DQ/DQS : PASS
4837 00:43:18.752563 RX DATLAT : PASS
4838 00:43:18.752638 RX DQ/DQS(Engine): PASS
4839 00:43:18.755921 TX OE : NO K
4840 00:43:18.756013 All Pass.
4841 00:43:18.756087
4842 00:43:18.759084 DramC Write-DBI off
4843 00:43:18.762621 PER_BANK_REFRESH: Hybrid Mode
4844 00:43:18.762714 TX_TRACKING: ON
4845 00:43:18.772682 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4846 00:43:18.776055 [FAST_K] Save calibration result to emmc
4847 00:43:18.779425 dramc_set_vcore_voltage set vcore to 662500
4848 00:43:18.782664 Read voltage for 933, 3
4849 00:43:18.782756 Vio18 = 0
4850 00:43:18.782830 Vcore = 662500
4851 00:43:18.782917 Vdram = 0
4852 00:43:18.785734 Vddq = 0
4853 00:43:18.785826 Vmddr = 0
4854 00:43:18.792595 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4855 00:43:18.795885 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4856 00:43:18.799072 MEM_TYPE=3, freq_sel=17
4857 00:43:18.802866 sv_algorithm_assistance_LP4_1600
4858 00:43:18.805663 ============ PULL DRAM RESETB DOWN ============
4859 00:43:18.808885 ========== PULL DRAM RESETB DOWN end =========
4860 00:43:18.816194 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4861 00:43:18.819012 ===================================
4862 00:43:18.819084 LPDDR4 DRAM CONFIGURATION
4863 00:43:18.822345 ===================================
4864 00:43:18.825687 EX_ROW_EN[0] = 0x0
4865 00:43:18.825776 EX_ROW_EN[1] = 0x0
4866 00:43:18.828971 LP4Y_EN = 0x0
4867 00:43:18.832335 WORK_FSP = 0x0
4868 00:43:18.832434 WL = 0x3
4869 00:43:18.836076 RL = 0x3
4870 00:43:18.836146 BL = 0x2
4871 00:43:18.839281 RPST = 0x0
4872 00:43:18.839347 RD_PRE = 0x0
4873 00:43:18.842472 WR_PRE = 0x1
4874 00:43:18.842559 WR_PST = 0x0
4875 00:43:18.845603 DBI_WR = 0x0
4876 00:43:18.845688 DBI_RD = 0x0
4877 00:43:18.849133 OTF = 0x1
4878 00:43:18.852221 ===================================
4879 00:43:18.855956 ===================================
4880 00:43:18.856031 ANA top config
4881 00:43:18.859065 ===================================
4882 00:43:18.862687 DLL_ASYNC_EN = 0
4883 00:43:18.865983 ALL_SLAVE_EN = 1
4884 00:43:18.866057 NEW_RANK_MODE = 1
4885 00:43:18.869272 DLL_IDLE_MODE = 1
4886 00:43:18.872623 LP45_APHY_COMB_EN = 1
4887 00:43:18.875908 TX_ODT_DIS = 1
4888 00:43:18.875977 NEW_8X_MODE = 1
4889 00:43:18.879236 ===================================
4890 00:43:18.882579 ===================================
4891 00:43:18.886026 data_rate = 1866
4892 00:43:18.889403 CKR = 1
4893 00:43:18.892896 DQ_P2S_RATIO = 8
4894 00:43:18.895488 ===================================
4895 00:43:18.898856 CA_P2S_RATIO = 8
4896 00:43:18.902243 DQ_CA_OPEN = 0
4897 00:43:18.905713 DQ_SEMI_OPEN = 0
4898 00:43:18.905780 CA_SEMI_OPEN = 0
4899 00:43:18.909129 CA_FULL_RATE = 0
4900 00:43:18.912358 DQ_CKDIV4_EN = 1
4901 00:43:18.915732 CA_CKDIV4_EN = 1
4902 00:43:18.918590 CA_PREDIV_EN = 0
4903 00:43:18.918666 PH8_DLY = 0
4904 00:43:18.921864 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4905 00:43:18.925724 DQ_AAMCK_DIV = 4
4906 00:43:18.929275 CA_AAMCK_DIV = 4
4907 00:43:18.931808 CA_ADMCK_DIV = 4
4908 00:43:18.935282 DQ_TRACK_CA_EN = 0
4909 00:43:18.938860 CA_PICK = 933
4910 00:43:18.938929 CA_MCKIO = 933
4911 00:43:18.942126 MCKIO_SEMI = 0
4912 00:43:18.945442 PLL_FREQ = 3732
4913 00:43:18.949056 DQ_UI_PI_RATIO = 32
4914 00:43:18.951991 CA_UI_PI_RATIO = 0
4915 00:43:18.955363 ===================================
4916 00:43:18.958950 ===================================
4917 00:43:18.961882 memory_type:LPDDR4
4918 00:43:18.961953 GP_NUM : 10
4919 00:43:18.965424 SRAM_EN : 1
4920 00:43:18.965512 MD32_EN : 0
4921 00:43:18.968436 ===================================
4922 00:43:18.972141 [ANA_INIT] >>>>>>>>>>>>>>
4923 00:43:18.975245 <<<<<< [CONFIGURE PHASE]: ANA_TX
4924 00:43:18.978798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4925 00:43:18.982140 ===================================
4926 00:43:18.985503 data_rate = 1866,PCW = 0X8f00
4927 00:43:18.988943 ===================================
4928 00:43:18.991773 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4929 00:43:18.995075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4930 00:43:19.001738 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4931 00:43:19.008471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4932 00:43:19.011780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4933 00:43:19.015119 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4934 00:43:19.015185 [ANA_INIT] flow start
4935 00:43:19.018362 [ANA_INIT] PLL >>>>>>>>
4936 00:43:19.021770 [ANA_INIT] PLL <<<<<<<<
4937 00:43:19.021835 [ANA_INIT] MIDPI >>>>>>>>
4938 00:43:19.025168 [ANA_INIT] MIDPI <<<<<<<<
4939 00:43:19.028451 [ANA_INIT] DLL >>>>>>>>
4940 00:43:19.028523 [ANA_INIT] flow end
4941 00:43:19.035253 ============ LP4 DIFF to SE enter ============
4942 00:43:19.038520 ============ LP4 DIFF to SE exit ============
4943 00:43:19.038592 [ANA_INIT] <<<<<<<<<<<<<
4944 00:43:19.041710 [Flow] Enable top DCM control >>>>>
4945 00:43:19.045239 [Flow] Enable top DCM control <<<<<
4946 00:43:19.048480 Enable DLL master slave shuffle
4947 00:43:19.054833 ==============================================================
4948 00:43:19.058278 Gating Mode config
4949 00:43:19.061756 ==============================================================
4950 00:43:19.064897 Config description:
4951 00:43:19.074898 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4952 00:43:19.081827 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4953 00:43:19.084746 SELPH_MODE 0: By rank 1: By Phase
4954 00:43:19.091677 ==============================================================
4955 00:43:19.095148 GAT_TRACK_EN = 1
4956 00:43:19.098424 RX_GATING_MODE = 2
4957 00:43:19.098521 RX_GATING_TRACK_MODE = 2
4958 00:43:19.101573 SELPH_MODE = 1
4959 00:43:19.104619 PICG_EARLY_EN = 1
4960 00:43:19.108068 VALID_LAT_VALUE = 1
4961 00:43:19.114654 ==============================================================
4962 00:43:19.117983 Enter into Gating configuration >>>>
4963 00:43:19.121340 Exit from Gating configuration <<<<
4964 00:43:19.124828 Enter into DVFS_PRE_config >>>>>
4965 00:43:19.134933 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4966 00:43:19.138357 Exit from DVFS_PRE_config <<<<<
4967 00:43:19.141793 Enter into PICG configuration >>>>
4968 00:43:19.144444 Exit from PICG configuration <<<<
4969 00:43:19.148246 [RX_INPUT] configuration >>>>>
4970 00:43:19.151397 [RX_INPUT] configuration <<<<<
4971 00:43:19.154450 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4972 00:43:19.161078 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4973 00:43:19.167739 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4974 00:43:19.174845 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4975 00:43:19.177958 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4976 00:43:19.184621 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4977 00:43:19.188028 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4978 00:43:19.194629 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4979 00:43:19.197796 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4980 00:43:19.201105 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4981 00:43:19.204393 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4982 00:43:19.210980 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4983 00:43:19.214580 ===================================
4984 00:43:19.214656 LPDDR4 DRAM CONFIGURATION
4985 00:43:19.217982 ===================================
4986 00:43:19.221001 EX_ROW_EN[0] = 0x0
4987 00:43:19.224154 EX_ROW_EN[1] = 0x0
4988 00:43:19.224229 LP4Y_EN = 0x0
4989 00:43:19.227794 WORK_FSP = 0x0
4990 00:43:19.227905 WL = 0x3
4991 00:43:19.231440 RL = 0x3
4992 00:43:19.231515 BL = 0x2
4993 00:43:19.234436 RPST = 0x0
4994 00:43:19.234558 RD_PRE = 0x0
4995 00:43:19.237796 WR_PRE = 0x1
4996 00:43:19.237869 WR_PST = 0x0
4997 00:43:19.241098 DBI_WR = 0x0
4998 00:43:19.241168 DBI_RD = 0x0
4999 00:43:19.244571 OTF = 0x1
5000 00:43:19.247861 ===================================
5001 00:43:19.251301 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5002 00:43:19.254405 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5003 00:43:19.260699 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5004 00:43:19.263992 ===================================
5005 00:43:19.264087 LPDDR4 DRAM CONFIGURATION
5006 00:43:19.267297 ===================================
5007 00:43:19.270765 EX_ROW_EN[0] = 0x10
5008 00:43:19.274106 EX_ROW_EN[1] = 0x0
5009 00:43:19.274177 LP4Y_EN = 0x0
5010 00:43:19.277487 WORK_FSP = 0x0
5011 00:43:19.277631 WL = 0x3
5012 00:43:19.280796 RL = 0x3
5013 00:43:19.280869 BL = 0x2
5014 00:43:19.283892 RPST = 0x0
5015 00:43:19.283985 RD_PRE = 0x0
5016 00:43:19.287541 WR_PRE = 0x1
5017 00:43:19.287635 WR_PST = 0x0
5018 00:43:19.290683 DBI_WR = 0x0
5019 00:43:19.290778 DBI_RD = 0x0
5020 00:43:19.294064 OTF = 0x1
5021 00:43:19.297417 ===================================
5022 00:43:19.304025 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5023 00:43:19.307319 nWR fixed to 30
5024 00:43:19.307420 [ModeRegInit_LP4] CH0 RK0
5025 00:43:19.310647 [ModeRegInit_LP4] CH0 RK1
5026 00:43:19.313944 [ModeRegInit_LP4] CH1 RK0
5027 00:43:19.317275 [ModeRegInit_LP4] CH1 RK1
5028 00:43:19.317368 match AC timing 9
5029 00:43:19.320730 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5030 00:43:19.324035 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5031 00:43:19.330592 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5032 00:43:19.333840 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5033 00:43:19.340887 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5034 00:43:19.340985 ==
5035 00:43:19.344100 Dram Type= 6, Freq= 0, CH_0, rank 0
5036 00:43:19.347674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5037 00:43:19.347770 ==
5038 00:43:19.354068 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5039 00:43:19.360582 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5040 00:43:19.364062 [CA 0] Center 37 (6~68) winsize 63
5041 00:43:19.367303 [CA 1] Center 37 (7~68) winsize 62
5042 00:43:19.370652 [CA 2] Center 34 (4~65) winsize 62
5043 00:43:19.373667 [CA 3] Center 34 (3~65) winsize 63
5044 00:43:19.377076 [CA 4] Center 33 (3~64) winsize 62
5045 00:43:19.377150 [CA 5] Center 32 (2~62) winsize 61
5046 00:43:19.377210
5047 00:43:19.384093 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5048 00:43:19.384166
5049 00:43:19.387514 [CATrainingPosCal] consider 1 rank data
5050 00:43:19.390661 u2DelayCellTimex100 = 270/100 ps
5051 00:43:19.394269 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5052 00:43:19.397084 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5053 00:43:19.400970 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5054 00:43:19.404154 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5055 00:43:19.407636 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5056 00:43:19.410337 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5057 00:43:19.410405
5058 00:43:19.413769 CA PerBit enable=1, Macro0, CA PI delay=32
5059 00:43:19.413835
5060 00:43:19.417007 [CBTSetCACLKResult] CA Dly = 32
5061 00:43:19.420374 CS Dly: 5 (0~36)
5062 00:43:19.420465 ==
5063 00:43:19.423636 Dram Type= 6, Freq= 0, CH_0, rank 1
5064 00:43:19.427452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5065 00:43:19.427515 ==
5066 00:43:19.433678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5067 00:43:19.440349 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5068 00:43:19.443779 [CA 0] Center 37 (6~68) winsize 63
5069 00:43:19.447163 [CA 1] Center 37 (7~68) winsize 62
5070 00:43:19.450404 [CA 2] Center 34 (4~65) winsize 62
5071 00:43:19.453508 [CA 3] Center 33 (3~64) winsize 62
5072 00:43:19.456758 [CA 4] Center 33 (3~63) winsize 61
5073 00:43:19.460646 [CA 5] Center 32 (2~62) winsize 61
5074 00:43:19.460751
5075 00:43:19.463862 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5076 00:43:19.463927
5077 00:43:19.467307 [CATrainingPosCal] consider 2 rank data
5078 00:43:19.470621 u2DelayCellTimex100 = 270/100 ps
5079 00:43:19.473749 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5080 00:43:19.476947 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5081 00:43:19.479957 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5082 00:43:19.483803 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5083 00:43:19.486813 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5084 00:43:19.490350 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5085 00:43:19.490418
5086 00:43:19.496713 CA PerBit enable=1, Macro0, CA PI delay=32
5087 00:43:19.496788
5088 00:43:19.496845 [CBTSetCACLKResult] CA Dly = 32
5089 00:43:19.499952 CS Dly: 5 (0~37)
5090 00:43:19.500031
5091 00:43:19.503536 ----->DramcWriteLeveling(PI) begin...
5092 00:43:19.503599 ==
5093 00:43:19.506809 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 00:43:19.509943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 00:43:19.510006 ==
5096 00:43:19.513311 Write leveling (Byte 0): 30 => 30
5097 00:43:19.516600 Write leveling (Byte 1): 29 => 29
5098 00:43:19.519773 DramcWriteLeveling(PI) end<-----
5099 00:43:19.519844
5100 00:43:19.519901 ==
5101 00:43:19.523101 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 00:43:19.526476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 00:43:19.530303 ==
5104 00:43:19.530387 [Gating] SW mode calibration
5105 00:43:19.539755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5106 00:43:19.543103 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5107 00:43:19.546494 0 14 0 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
5108 00:43:19.553100 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5109 00:43:19.556323 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 00:43:19.559988 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 00:43:19.566993 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 00:43:19.569646 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 00:43:19.572990 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5114 00:43:19.579736 0 14 28 | B1->B0 | 3333 2929 | 0 1 | (0 1) (1 0)
5115 00:43:19.582994 0 15 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
5116 00:43:19.586276 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 00:43:19.593083 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 00:43:19.596433 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 00:43:19.599796 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 00:43:19.606372 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 00:43:19.609718 0 15 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
5122 00:43:19.612993 0 15 28 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
5123 00:43:19.619316 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5124 00:43:19.622988 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 00:43:19.625954 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 00:43:19.632945 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 00:43:19.636246 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 00:43:19.639363 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 00:43:19.646220 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5130 00:43:19.649620 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5131 00:43:19.652656 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5132 00:43:19.655833 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 00:43:19.662894 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 00:43:19.666288 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 00:43:19.669498 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 00:43:19.676244 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 00:43:19.679543 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 00:43:19.682950 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 00:43:19.689399 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 00:43:19.692634 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 00:43:19.696049 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 00:43:19.702804 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 00:43:19.706089 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 00:43:19.709392 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 00:43:19.715871 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 00:43:19.719281 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5147 00:43:19.722692 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5148 00:43:19.725962 Total UI for P1: 0, mck2ui 16
5149 00:43:19.729719 best dqsien dly found for B0: ( 1, 2, 28)
5150 00:43:19.732920 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 00:43:19.736331 Total UI for P1: 0, mck2ui 16
5152 00:43:19.739608 best dqsien dly found for B1: ( 1, 3, 0)
5153 00:43:19.746392 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5154 00:43:19.749690 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5155 00:43:19.749757
5156 00:43:19.752860 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5157 00:43:19.756103 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5158 00:43:19.759337 [Gating] SW calibration Done
5159 00:43:19.759401 ==
5160 00:43:19.762637 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 00:43:19.766107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 00:43:19.766176 ==
5163 00:43:19.766231 RX Vref Scan: 0
5164 00:43:19.769347
5165 00:43:19.769411 RX Vref 0 -> 0, step: 1
5166 00:43:19.769464
5167 00:43:19.772361 RX Delay -80 -> 252, step: 8
5168 00:43:19.775799 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5169 00:43:19.779088 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5170 00:43:19.785883 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5171 00:43:19.789118 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5172 00:43:19.792729 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5173 00:43:19.795978 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5174 00:43:19.799193 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5175 00:43:19.802609 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5176 00:43:19.809527 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5177 00:43:19.812821 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5178 00:43:19.815980 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5179 00:43:19.819370 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5180 00:43:19.822691 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5181 00:43:19.826203 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5182 00:43:19.832771 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5183 00:43:19.835803 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5184 00:43:19.835871 ==
5185 00:43:19.839265 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 00:43:19.842584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 00:43:19.842651 ==
5188 00:43:19.842706 DQS Delay:
5189 00:43:19.846033 DQS0 = 0, DQS1 = 0
5190 00:43:19.846107 DQM Delay:
5191 00:43:19.849401 DQM0 = 103, DQM1 = 96
5192 00:43:19.849463 DQ Delay:
5193 00:43:19.852688 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5194 00:43:19.855892 DQ4 =103, DQ5 =91, DQ6 =115, DQ7 =115
5195 00:43:19.859089 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5196 00:43:19.862487 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5197 00:43:19.862584
5198 00:43:19.862643
5199 00:43:19.862709 ==
5200 00:43:19.865836 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 00:43:19.872559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 00:43:19.872635 ==
5203 00:43:19.872709
5204 00:43:19.872775
5205 00:43:19.872826 TX Vref Scan disable
5206 00:43:19.876570 == TX Byte 0 ==
5207 00:43:19.879958 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5208 00:43:19.883218 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5209 00:43:19.886378 == TX Byte 1 ==
5210 00:43:19.889627 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5211 00:43:19.895892 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5212 00:43:19.895991 ==
5213 00:43:19.899341 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 00:43:19.902777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 00:43:19.902876 ==
5216 00:43:19.902970
5217 00:43:19.903051
5218 00:43:19.905990 TX Vref Scan disable
5219 00:43:19.906103 == TX Byte 0 ==
5220 00:43:19.912651 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5221 00:43:19.915742 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5222 00:43:19.915819 == TX Byte 1 ==
5223 00:43:19.922818 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5224 00:43:19.925761 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5225 00:43:19.925838
5226 00:43:19.925898 [DATLAT]
5227 00:43:19.929202 Freq=933, CH0 RK0
5228 00:43:19.929279
5229 00:43:19.929339 DATLAT Default: 0xd
5230 00:43:19.932733 0, 0xFFFF, sum = 0
5231 00:43:19.932810 1, 0xFFFF, sum = 0
5232 00:43:19.935886 2, 0xFFFF, sum = 0
5233 00:43:19.935965 3, 0xFFFF, sum = 0
5234 00:43:19.939294 4, 0xFFFF, sum = 0
5235 00:43:19.942268 5, 0xFFFF, sum = 0
5236 00:43:19.942346 6, 0xFFFF, sum = 0
5237 00:43:19.945643 7, 0xFFFF, sum = 0
5238 00:43:19.945720 8, 0xFFFF, sum = 0
5239 00:43:19.949507 9, 0xFFFF, sum = 0
5240 00:43:19.949601 10, 0x0, sum = 1
5241 00:43:19.952276 11, 0x0, sum = 2
5242 00:43:19.952353 12, 0x0, sum = 3
5243 00:43:19.952414 13, 0x0, sum = 4
5244 00:43:19.955677 best_step = 11
5245 00:43:19.955754
5246 00:43:19.955812 ==
5247 00:43:19.959042 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 00:43:19.962344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 00:43:19.962420 ==
5250 00:43:19.966055 RX Vref Scan: 1
5251 00:43:19.966132
5252 00:43:19.966193 RX Vref 0 -> 0, step: 1
5253 00:43:19.969494
5254 00:43:19.969569 RX Delay -45 -> 252, step: 4
5255 00:43:19.969626
5256 00:43:19.972431 Set Vref, RX VrefLevel [Byte0]: 53
5257 00:43:19.975740 [Byte1]: 50
5258 00:43:19.980421
5259 00:43:19.980490 Final RX Vref Byte 0 = 53 to rank0
5260 00:43:19.983787 Final RX Vref Byte 1 = 50 to rank0
5261 00:43:19.987030 Final RX Vref Byte 0 = 53 to rank1
5262 00:43:19.990326 Final RX Vref Byte 1 = 50 to rank1==
5263 00:43:19.993490 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 00:43:20.000092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 00:43:20.000160 ==
5266 00:43:20.000216 DQS Delay:
5267 00:43:20.003441 DQS0 = 0, DQS1 = 0
5268 00:43:20.003505 DQM Delay:
5269 00:43:20.003560 DQM0 = 105, DQM1 = 96
5270 00:43:20.006590 DQ Delay:
5271 00:43:20.009878 DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =104
5272 00:43:20.013317 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5273 00:43:20.016711 DQ8 =86, DQ9 =86, DQ10 =98, DQ11 =90
5274 00:43:20.019876 DQ12 =100, DQ13 =100, DQ14 =106, DQ15 =102
5275 00:43:20.019954
5276 00:43:20.020055
5277 00:43:20.026282 [DQSOSCAuto] RK0, (LSB)MR18= 0x342c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5278 00:43:20.029653 CH0 RK0: MR19=505, MR18=342C
5279 00:43:20.036568 CH0_RK0: MR19=0x505, MR18=0x342C, DQSOSC=405, MR23=63, INC=66, DEC=44
5280 00:43:20.036644
5281 00:43:20.039549 ----->DramcWriteLeveling(PI) begin...
5282 00:43:20.039614 ==
5283 00:43:20.042761 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 00:43:20.046275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 00:43:20.049774 ==
5286 00:43:20.049849 Write leveling (Byte 0): 30 => 30
5287 00:43:20.052561 Write leveling (Byte 1): 27 => 27
5288 00:43:20.056039 DramcWriteLeveling(PI) end<-----
5289 00:43:20.056115
5290 00:43:20.056173 ==
5291 00:43:20.059296 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 00:43:20.066236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 00:43:20.066323 ==
5294 00:43:20.066383 [Gating] SW mode calibration
5295 00:43:20.076251 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5296 00:43:20.079334 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5297 00:43:20.086097 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5298 00:43:20.089480 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 00:43:20.092784 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 00:43:20.096145 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 00:43:20.102555 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 00:43:20.105970 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 00:43:20.109396 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5304 00:43:20.116027 0 14 28 | B1->B0 | 2828 2828 | 0 0 | (0 0) (1 0)
5305 00:43:20.119353 0 15 0 | B1->B0 | 2525 2828 | 0 1 | (0 0) (1 0)
5306 00:43:20.122751 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 00:43:20.129214 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 00:43:20.132611 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 00:43:20.135986 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 00:43:20.142690 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 00:43:20.146030 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5312 00:43:20.149286 0 15 28 | B1->B0 | 3a3a 3838 | 0 0 | (1 1) (0 0)
5313 00:43:20.156049 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5314 00:43:20.159378 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 00:43:20.162695 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 00:43:20.169353 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 00:43:20.172772 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 00:43:20.176134 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 00:43:20.182602 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 00:43:20.185694 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5321 00:43:20.189064 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 00:43:20.195817 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 00:43:20.199262 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 00:43:20.202256 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 00:43:20.208943 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 00:43:20.212266 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 00:43:20.215919 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 00:43:20.222317 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 00:43:20.226026 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 00:43:20.229319 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 00:43:20.232671 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 00:43:20.239367 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 00:43:20.242678 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 00:43:20.245425 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 00:43:20.252300 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5336 00:43:20.256191 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5337 00:43:20.258862 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 00:43:20.262657 Total UI for P1: 0, mck2ui 16
5339 00:43:20.265745 best dqsien dly found for B0: ( 1, 2, 26)
5340 00:43:20.269040 Total UI for P1: 0, mck2ui 16
5341 00:43:20.272318 best dqsien dly found for B1: ( 1, 2, 28)
5342 00:43:20.275718 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5343 00:43:20.279126 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5344 00:43:20.279203
5345 00:43:20.286144 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5346 00:43:20.289477 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5347 00:43:20.289581 [Gating] SW calibration Done
5348 00:43:20.292830 ==
5349 00:43:20.296107 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 00:43:20.298902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 00:43:20.298992 ==
5352 00:43:20.299083 RX Vref Scan: 0
5353 00:43:20.299166
5354 00:43:20.302764 RX Vref 0 -> 0, step: 1
5355 00:43:20.302840
5356 00:43:20.306149 RX Delay -80 -> 252, step: 8
5357 00:43:20.309386 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5358 00:43:20.312570 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5359 00:43:20.316085 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5360 00:43:20.322564 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5361 00:43:20.325770 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5362 00:43:20.328955 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5363 00:43:20.333149 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5364 00:43:20.335672 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5365 00:43:20.339109 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5366 00:43:20.346199 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5367 00:43:20.348849 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5368 00:43:20.352314 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5369 00:43:20.355712 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5370 00:43:20.358893 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5371 00:43:20.362072 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5372 00:43:20.368701 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5373 00:43:20.368803 ==
5374 00:43:20.372019 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 00:43:20.375871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 00:43:20.375971 ==
5377 00:43:20.376061 DQS Delay:
5378 00:43:20.379265 DQS0 = 0, DQS1 = 0
5379 00:43:20.379356 DQM Delay:
5380 00:43:20.381923 DQM0 = 104, DQM1 = 94
5381 00:43:20.382014 DQ Delay:
5382 00:43:20.385354 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5383 00:43:20.388760 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5384 00:43:20.392075 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5385 00:43:20.395459 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5386 00:43:20.395551
5387 00:43:20.395637
5388 00:43:20.395721 ==
5389 00:43:20.398839 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 00:43:20.405436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 00:43:20.405524 ==
5392 00:43:20.405625
5393 00:43:20.405680
5394 00:43:20.405735 TX Vref Scan disable
5395 00:43:20.408797 == TX Byte 0 ==
5396 00:43:20.412083 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5397 00:43:20.418649 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5398 00:43:20.418737 == TX Byte 1 ==
5399 00:43:20.421890 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5400 00:43:20.428602 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5401 00:43:20.428694 ==
5402 00:43:20.431982 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 00:43:20.435339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 00:43:20.435411 ==
5405 00:43:20.435497
5406 00:43:20.435576
5407 00:43:20.438616 TX Vref Scan disable
5408 00:43:20.438677 == TX Byte 0 ==
5409 00:43:20.445041 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5410 00:43:20.448347 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5411 00:43:20.448438 == TX Byte 1 ==
5412 00:43:20.455079 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5413 00:43:20.458584 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5414 00:43:20.458684
5415 00:43:20.458775 [DATLAT]
5416 00:43:20.461929 Freq=933, CH0 RK1
5417 00:43:20.462023
5418 00:43:20.462108 DATLAT Default: 0xb
5419 00:43:20.465432 0, 0xFFFF, sum = 0
5420 00:43:20.465538 1, 0xFFFF, sum = 0
5421 00:43:20.468577 2, 0xFFFF, sum = 0
5422 00:43:20.468672 3, 0xFFFF, sum = 0
5423 00:43:20.471733 4, 0xFFFF, sum = 0
5424 00:43:20.475289 5, 0xFFFF, sum = 0
5425 00:43:20.475393 6, 0xFFFF, sum = 0
5426 00:43:20.478297 7, 0xFFFF, sum = 0
5427 00:43:20.478400 8, 0xFFFF, sum = 0
5428 00:43:20.481983 9, 0xFFFF, sum = 0
5429 00:43:20.482085 10, 0x0, sum = 1
5430 00:43:20.485194 11, 0x0, sum = 2
5431 00:43:20.485299 12, 0x0, sum = 3
5432 00:43:20.485391 13, 0x0, sum = 4
5433 00:43:20.488603 best_step = 11
5434 00:43:20.488673
5435 00:43:20.488731 ==
5436 00:43:20.491807 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 00:43:20.494948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 00:43:20.495044 ==
5439 00:43:20.498314 RX Vref Scan: 0
5440 00:43:20.498413
5441 00:43:20.498504 RX Vref 0 -> 0, step: 1
5442 00:43:20.501398
5443 00:43:20.501500 RX Delay -45 -> 252, step: 4
5444 00:43:20.509103 iDelay=195, Bit 0, Center 102 (15 ~ 190) 176
5445 00:43:20.512530 iDelay=195, Bit 1, Center 108 (23 ~ 194) 172
5446 00:43:20.515957 iDelay=195, Bit 2, Center 102 (15 ~ 190) 176
5447 00:43:20.519367 iDelay=195, Bit 3, Center 102 (15 ~ 190) 176
5448 00:43:20.522770 iDelay=195, Bit 4, Center 106 (19 ~ 194) 176
5449 00:43:20.529012 iDelay=195, Bit 5, Center 98 (11 ~ 186) 176
5450 00:43:20.532357 iDelay=195, Bit 6, Center 112 (31 ~ 194) 164
5451 00:43:20.535855 iDelay=195, Bit 7, Center 110 (27 ~ 194) 168
5452 00:43:20.539123 iDelay=195, Bit 8, Center 86 (3 ~ 170) 168
5453 00:43:20.542645 iDelay=195, Bit 9, Center 82 (-1 ~ 166) 168
5454 00:43:20.546025 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5455 00:43:20.552774 iDelay=195, Bit 11, Center 88 (7 ~ 170) 164
5456 00:43:20.556144 iDelay=195, Bit 12, Center 100 (19 ~ 182) 164
5457 00:43:20.559419 iDelay=195, Bit 13, Center 100 (19 ~ 182) 164
5458 00:43:20.562976 iDelay=195, Bit 14, Center 104 (23 ~ 186) 164
5459 00:43:20.566384 iDelay=195, Bit 15, Center 102 (19 ~ 186) 168
5460 00:43:20.569410 ==
5461 00:43:20.572828 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 00:43:20.575610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 00:43:20.575706 ==
5464 00:43:20.575793 DQS Delay:
5465 00:43:20.578903 DQS0 = 0, DQS1 = 0
5466 00:43:20.578994 DQM Delay:
5467 00:43:20.582332 DQM0 = 105, DQM1 = 94
5468 00:43:20.582421 DQ Delay:
5469 00:43:20.585658 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5470 00:43:20.588984 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =110
5471 00:43:20.592338 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5472 00:43:20.596084 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5473 00:43:20.596176
5474 00:43:20.596259
5475 00:43:20.606016 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5476 00:43:20.606092 CH0 RK1: MR19=505, MR18=2B03
5477 00:43:20.612542 CH0_RK1: MR19=0x505, MR18=0x2B03, DQSOSC=408, MR23=63, INC=65, DEC=43
5478 00:43:20.615966 [RxdqsGatingPostProcess] freq 933
5479 00:43:20.622493 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5480 00:43:20.625543 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 00:43:20.629117 best DQS1 dly(2T, 0.5T) = (0, 11)
5482 00:43:20.632277 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 00:43:20.635756 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5484 00:43:20.638894 best DQS0 dly(2T, 0.5T) = (0, 10)
5485 00:43:20.638967 best DQS1 dly(2T, 0.5T) = (0, 10)
5486 00:43:20.642132 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5487 00:43:20.645538 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5488 00:43:20.648946 Pre-setting of DQS Precalculation
5489 00:43:20.655745 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5490 00:43:20.655827 ==
5491 00:43:20.659068 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 00:43:20.662387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 00:43:20.662463 ==
5494 00:43:20.668768 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5495 00:43:20.675896 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5496 00:43:20.678568 [CA 0] Center 36 (6~67) winsize 62
5497 00:43:20.681943 [CA 1] Center 36 (6~67) winsize 62
5498 00:43:20.685957 [CA 2] Center 34 (4~65) winsize 62
5499 00:43:20.688556 [CA 3] Center 34 (4~65) winsize 62
5500 00:43:20.691948 [CA 4] Center 34 (4~65) winsize 62
5501 00:43:20.695315 [CA 5] Center 33 (3~64) winsize 62
5502 00:43:20.695405
5503 00:43:20.698588 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5504 00:43:20.698653
5505 00:43:20.702286 [CATrainingPosCal] consider 1 rank data
5506 00:43:20.705503 u2DelayCellTimex100 = 270/100 ps
5507 00:43:20.708754 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5508 00:43:20.712127 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5509 00:43:20.715420 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5510 00:43:20.718805 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5511 00:43:20.722190 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5512 00:43:20.725357 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5513 00:43:20.725436
5514 00:43:20.728398 CA PerBit enable=1, Macro0, CA PI delay=33
5515 00:43:20.732145
5516 00:43:20.732223 [CBTSetCACLKResult] CA Dly = 33
5517 00:43:20.735694 CS Dly: 6 (0~37)
5518 00:43:20.735773 ==
5519 00:43:20.738365 Dram Type= 6, Freq= 0, CH_1, rank 1
5520 00:43:20.742175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 00:43:20.742254 ==
5522 00:43:20.748236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5523 00:43:20.755417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5524 00:43:20.758248 [CA 0] Center 37 (6~68) winsize 63
5525 00:43:20.762098 [CA 1] Center 37 (7~68) winsize 62
5526 00:43:20.764887 [CA 2] Center 35 (5~66) winsize 62
5527 00:43:20.768274 [CA 3] Center 34 (4~65) winsize 62
5528 00:43:20.771556 [CA 4] Center 34 (4~65) winsize 62
5529 00:43:20.775132 [CA 5] Center 34 (4~64) winsize 61
5530 00:43:20.775244
5531 00:43:20.778304 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5532 00:43:20.778389
5533 00:43:20.781592 [CATrainingPosCal] consider 2 rank data
5534 00:43:20.784715 u2DelayCellTimex100 = 270/100 ps
5535 00:43:20.788049 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5536 00:43:20.791386 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5537 00:43:20.794813 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5538 00:43:20.798338 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5539 00:43:20.801673 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5540 00:43:20.805026 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5541 00:43:20.805103
5542 00:43:20.811377 CA PerBit enable=1, Macro0, CA PI delay=34
5543 00:43:20.811455
5544 00:43:20.811514 [CBTSetCACLKResult] CA Dly = 34
5545 00:43:20.814828 CS Dly: 7 (0~40)
5546 00:43:20.814905
5547 00:43:20.818110 ----->DramcWriteLeveling(PI) begin...
5548 00:43:20.818189 ==
5549 00:43:20.821683 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 00:43:20.824930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 00:43:20.825013 ==
5552 00:43:20.828417 Write leveling (Byte 0): 26 => 26
5553 00:43:20.831710 Write leveling (Byte 1): 28 => 28
5554 00:43:20.834885 DramcWriteLeveling(PI) end<-----
5555 00:43:20.834962
5556 00:43:20.835025 ==
5557 00:43:20.838108 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 00:43:20.841912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 00:43:20.845328 ==
5560 00:43:20.845406 [Gating] SW mode calibration
5561 00:43:20.855062 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5562 00:43:20.858403 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5563 00:43:20.861430 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5564 00:43:20.867944 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 00:43:20.871264 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 00:43:20.875082 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 00:43:20.881367 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 00:43:20.884902 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5569 00:43:20.887963 0 14 24 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (1 0)
5570 00:43:20.894692 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
5571 00:43:20.898302 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 00:43:20.901412 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 00:43:20.908368 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 00:43:20.911433 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 00:43:20.914388 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 00:43:20.921487 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5577 00:43:20.924965 0 15 24 | B1->B0 | 2525 3736 | 0 1 | (0 0) (0 0)
5578 00:43:20.927806 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5579 00:43:20.934424 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 00:43:20.937927 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 00:43:20.941214 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 00:43:20.944426 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 00:43:20.951344 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 00:43:20.954800 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 00:43:20.957590 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5586 00:43:20.964794 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 00:43:20.967884 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 00:43:20.970963 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 00:43:20.977818 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 00:43:20.981361 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 00:43:20.984638 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 00:43:20.991358 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 00:43:20.994464 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 00:43:20.997991 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 00:43:21.004748 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 00:43:21.007871 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 00:43:21.010813 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 00:43:21.017505 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 00:43:21.020801 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 00:43:21.024298 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 00:43:21.030814 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5602 00:43:21.034401 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5603 00:43:21.037882 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 00:43:21.040686 Total UI for P1: 0, mck2ui 16
5605 00:43:21.044036 best dqsien dly found for B0: ( 1, 2, 26)
5606 00:43:21.047723 Total UI for P1: 0, mck2ui 16
5607 00:43:21.050962 best dqsien dly found for B1: ( 1, 2, 26)
5608 00:43:21.054272 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5609 00:43:21.057361 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5610 00:43:21.057466
5611 00:43:21.061397 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5612 00:43:21.067474 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5613 00:43:21.067546 [Gating] SW calibration Done
5614 00:43:21.067605 ==
5615 00:43:21.070817 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 00:43:21.077932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 00:43:21.078024 ==
5618 00:43:21.078084 RX Vref Scan: 0
5619 00:43:21.078147
5620 00:43:21.081383 RX Vref 0 -> 0, step: 1
5621 00:43:21.081448
5622 00:43:21.084671 RX Delay -80 -> 252, step: 8
5623 00:43:21.087793 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5624 00:43:21.091134 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5625 00:43:21.094748 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5626 00:43:21.097309 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5627 00:43:21.104095 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5628 00:43:21.107463 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5629 00:43:21.110911 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5630 00:43:21.113836 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5631 00:43:21.117086 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5632 00:43:21.120669 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5633 00:43:21.127415 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5634 00:43:21.130788 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5635 00:43:21.134203 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5636 00:43:21.137559 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5637 00:43:21.140882 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5638 00:43:21.147267 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5639 00:43:21.147337 ==
5640 00:43:21.150704 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 00:43:21.153760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 00:43:21.153851 ==
5643 00:43:21.153935 DQS Delay:
5644 00:43:21.157354 DQS0 = 0, DQS1 = 0
5645 00:43:21.157441 DQM Delay:
5646 00:43:21.160490 DQM0 = 102, DQM1 = 98
5647 00:43:21.160579 DQ Delay:
5648 00:43:21.163898 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5649 00:43:21.167101 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5650 00:43:21.170634 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5651 00:43:21.173773 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5652 00:43:21.173852
5653 00:43:21.173910
5654 00:43:21.173965 ==
5655 00:43:21.176995 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 00:43:21.183764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 00:43:21.183844 ==
5658 00:43:21.183903
5659 00:43:21.183957
5660 00:43:21.184009 TX Vref Scan disable
5661 00:43:21.187210 == TX Byte 0 ==
5662 00:43:21.190563 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5663 00:43:21.193683 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5664 00:43:21.197180 == TX Byte 1 ==
5665 00:43:21.200352 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5666 00:43:21.207076 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5667 00:43:21.207174 ==
5668 00:43:21.210556 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 00:43:21.214076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 00:43:21.214153 ==
5671 00:43:21.214213
5672 00:43:21.214268
5673 00:43:21.217381 TX Vref Scan disable
5674 00:43:21.217480 == TX Byte 0 ==
5675 00:43:21.224128 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5676 00:43:21.226904 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5677 00:43:21.226981 == TX Byte 1 ==
5678 00:43:21.233745 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5679 00:43:21.237174 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5680 00:43:21.237251
5681 00:43:21.237310 [DATLAT]
5682 00:43:21.240513 Freq=933, CH1 RK0
5683 00:43:21.240613
5684 00:43:21.240698 DATLAT Default: 0xd
5685 00:43:21.244015 0, 0xFFFF, sum = 0
5686 00:43:21.244085 1, 0xFFFF, sum = 0
5687 00:43:21.247374 2, 0xFFFF, sum = 0
5688 00:43:21.247439 3, 0xFFFF, sum = 0
5689 00:43:21.250839 4, 0xFFFF, sum = 0
5690 00:43:21.250905 5, 0xFFFF, sum = 0
5691 00:43:21.253745 6, 0xFFFF, sum = 0
5692 00:43:21.257005 7, 0xFFFF, sum = 0
5693 00:43:21.257070 8, 0xFFFF, sum = 0
5694 00:43:21.260245 9, 0xFFFF, sum = 0
5695 00:43:21.260307 10, 0x0, sum = 1
5696 00:43:21.260360 11, 0x0, sum = 2
5697 00:43:21.263635 12, 0x0, sum = 3
5698 00:43:21.263696 13, 0x0, sum = 4
5699 00:43:21.267141 best_step = 11
5700 00:43:21.267220
5701 00:43:21.267277 ==
5702 00:43:21.270581 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 00:43:21.273989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 00:43:21.274066 ==
5705 00:43:21.277267 RX Vref Scan: 1
5706 00:43:21.277343
5707 00:43:21.277402 RX Vref 0 -> 0, step: 1
5708 00:43:21.280563
5709 00:43:21.280639 RX Delay -45 -> 252, step: 4
5710 00:43:21.280698
5711 00:43:21.283786 Set Vref, RX VrefLevel [Byte0]: 53
5712 00:43:21.287045 [Byte1]: 45
5713 00:43:21.291416
5714 00:43:21.291492 Final RX Vref Byte 0 = 53 to rank0
5715 00:43:21.294661 Final RX Vref Byte 1 = 45 to rank0
5716 00:43:21.297841 Final RX Vref Byte 0 = 53 to rank1
5717 00:43:21.301101 Final RX Vref Byte 1 = 45 to rank1==
5718 00:43:21.304655 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 00:43:21.308021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 00:43:21.311136 ==
5721 00:43:21.311212 DQS Delay:
5722 00:43:21.311271 DQS0 = 0, DQS1 = 0
5723 00:43:21.314746 DQM Delay:
5724 00:43:21.314822 DQM0 = 102, DQM1 = 98
5725 00:43:21.318057 DQ Delay:
5726 00:43:21.321285 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5727 00:43:21.324761 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =100
5728 00:43:21.327980 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5729 00:43:21.331246 DQ12 =104, DQ13 =104, DQ14 =102, DQ15 =106
5730 00:43:21.331323
5731 00:43:21.331382
5732 00:43:21.337903 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5733 00:43:21.341425 CH1 RK0: MR19=505, MR18=1830
5734 00:43:21.347691 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5735 00:43:21.347770
5736 00:43:21.351681 ----->DramcWriteLeveling(PI) begin...
5737 00:43:21.351780 ==
5738 00:43:21.354483 Dram Type= 6, Freq= 0, CH_1, rank 1
5739 00:43:21.357943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 00:43:21.358033 ==
5741 00:43:21.361376 Write leveling (Byte 0): 27 => 27
5742 00:43:21.364520 Write leveling (Byte 1): 27 => 27
5743 00:43:21.367837 DramcWriteLeveling(PI) end<-----
5744 00:43:21.367915
5745 00:43:21.367974 ==
5746 00:43:21.371293 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 00:43:21.374709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 00:43:21.374786 ==
5749 00:43:21.377970 [Gating] SW mode calibration
5750 00:43:21.384546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5751 00:43:21.391368 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5752 00:43:21.394472 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 00:43:21.401402 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 00:43:21.404485 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 00:43:21.407727 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 00:43:21.414453 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 00:43:21.417929 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 00:43:21.421102 0 14 24 | B1->B0 | 2828 3131 | 0 1 | (0 0) (1 1)
5759 00:43:21.427931 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
5760 00:43:21.431111 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 00:43:21.434910 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 00:43:21.438191 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 00:43:21.444865 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 00:43:21.447988 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 00:43:21.451289 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5766 00:43:21.457706 0 15 24 | B1->B0 | 3636 2929 | 0 0 | (0 0) (0 0)
5767 00:43:21.461169 0 15 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (1 1)
5768 00:43:21.464321 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 00:43:21.471363 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 00:43:21.474750 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 00:43:21.477617 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 00:43:21.484133 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 00:43:21.487943 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 00:43:21.491044 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5775 00:43:21.497361 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5776 00:43:21.500841 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 00:43:21.504073 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 00:43:21.510767 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 00:43:21.514000 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 00:43:21.517327 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 00:43:21.523986 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 00:43:21.527303 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 00:43:21.531219 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 00:43:21.537220 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 00:43:21.540952 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 00:43:21.544318 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 00:43:21.551190 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 00:43:21.553964 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 00:43:21.557533 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 00:43:21.564260 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5791 00:43:21.567386 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5792 00:43:21.571070 Total UI for P1: 0, mck2ui 16
5793 00:43:21.574114 best dqsien dly found for B1: ( 1, 2, 24)
5794 00:43:21.577135 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 00:43:21.580972 Total UI for P1: 0, mck2ui 16
5796 00:43:21.583766 best dqsien dly found for B0: ( 1, 2, 26)
5797 00:43:21.586958 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5798 00:43:21.590935 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5799 00:43:21.591009
5800 00:43:21.594136 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5801 00:43:21.600468 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5802 00:43:21.600544 [Gating] SW calibration Done
5803 00:43:21.600604 ==
5804 00:43:21.603814 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 00:43:21.610816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 00:43:21.610896 ==
5807 00:43:21.610957 RX Vref Scan: 0
5808 00:43:21.611013
5809 00:43:21.613561 RX Vref 0 -> 0, step: 1
5810 00:43:21.613639
5811 00:43:21.616875 RX Delay -80 -> 252, step: 8
5812 00:43:21.620327 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5813 00:43:21.623604 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5814 00:43:21.626958 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5815 00:43:21.633693 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5816 00:43:21.637205 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5817 00:43:21.640497 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5818 00:43:21.643756 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5819 00:43:21.646896 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5820 00:43:21.650753 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5821 00:43:21.656847 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5822 00:43:21.660308 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5823 00:43:21.663793 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5824 00:43:21.667031 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5825 00:43:21.670344 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5826 00:43:21.677086 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5827 00:43:21.680390 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5828 00:43:21.680465 ==
5829 00:43:21.683872 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 00:43:21.687292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 00:43:21.687364 ==
5832 00:43:21.687430 DQS Delay:
5833 00:43:21.690681 DQS0 = 0, DQS1 = 0
5834 00:43:21.690750 DQM Delay:
5835 00:43:21.693646 DQM0 = 104, DQM1 = 97
5836 00:43:21.693731 DQ Delay:
5837 00:43:21.696749 DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =103
5838 00:43:21.700253 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5839 00:43:21.703479 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5840 00:43:21.706739 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5841 00:43:21.706806
5842 00:43:21.706872
5843 00:43:21.710090 ==
5844 00:43:21.710166 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 00:43:21.716988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 00:43:21.717063 ==
5847 00:43:21.717121
5848 00:43:21.717176
5849 00:43:21.719951 TX Vref Scan disable
5850 00:43:21.720019 == TX Byte 0 ==
5851 00:43:21.723542 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5852 00:43:21.730279 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5853 00:43:21.730359 == TX Byte 1 ==
5854 00:43:21.733496 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5855 00:43:21.740074 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5856 00:43:21.740159 ==
5857 00:43:21.743551 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 00:43:21.746990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 00:43:21.747096 ==
5860 00:43:21.747183
5861 00:43:21.747271
5862 00:43:21.750362 TX Vref Scan disable
5863 00:43:21.753611 == TX Byte 0 ==
5864 00:43:21.756734 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5865 00:43:21.760514 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5866 00:43:21.763259 == TX Byte 1 ==
5867 00:43:21.766754 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5868 00:43:21.770078 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5869 00:43:21.770153
5870 00:43:21.770230 [DATLAT]
5871 00:43:21.773377 Freq=933, CH1 RK1
5872 00:43:21.773470
5873 00:43:21.773579 DATLAT Default: 0xb
5874 00:43:21.776806 0, 0xFFFF, sum = 0
5875 00:43:21.780057 1, 0xFFFF, sum = 0
5876 00:43:21.780167 2, 0xFFFF, sum = 0
5877 00:43:21.783634 3, 0xFFFF, sum = 0
5878 00:43:21.783731 4, 0xFFFF, sum = 0
5879 00:43:21.786591 5, 0xFFFF, sum = 0
5880 00:43:21.786666 6, 0xFFFF, sum = 0
5881 00:43:21.790313 7, 0xFFFF, sum = 0
5882 00:43:21.790386 8, 0xFFFF, sum = 0
5883 00:43:21.793644 9, 0xFFFF, sum = 0
5884 00:43:21.793724 10, 0x0, sum = 1
5885 00:43:21.797015 11, 0x0, sum = 2
5886 00:43:21.797094 12, 0x0, sum = 3
5887 00:43:21.800471 13, 0x0, sum = 4
5888 00:43:21.800550 best_step = 11
5889 00:43:21.800610
5890 00:43:21.800666 ==
5891 00:43:21.803801 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 00:43:21.806619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 00:43:21.806698 ==
5894 00:43:21.809953 RX Vref Scan: 0
5895 00:43:21.810036
5896 00:43:21.813660 RX Vref 0 -> 0, step: 1
5897 00:43:21.813738
5898 00:43:21.813800 RX Delay -53 -> 252, step: 4
5899 00:43:21.821019 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5900 00:43:21.824628 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5901 00:43:21.827955 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5902 00:43:21.831080 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5903 00:43:21.834465 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5904 00:43:21.841244 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5905 00:43:21.844788 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5906 00:43:21.847815 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5907 00:43:21.851195 iDelay=203, Bit 8, Center 86 (-1 ~ 174) 176
5908 00:43:21.854593 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5909 00:43:21.861299 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5910 00:43:21.864338 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5911 00:43:21.868141 iDelay=203, Bit 12, Center 108 (23 ~ 194) 172
5912 00:43:21.871561 iDelay=203, Bit 13, Center 104 (23 ~ 186) 164
5913 00:43:21.874276 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5914 00:43:21.880987 iDelay=203, Bit 15, Center 106 (23 ~ 190) 168
5915 00:43:21.881076 ==
5916 00:43:21.884431 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 00:43:21.887993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 00:43:21.888075 ==
5919 00:43:21.888155 DQS Delay:
5920 00:43:21.891034 DQS0 = 0, DQS1 = 0
5921 00:43:21.891136 DQM Delay:
5922 00:43:21.894323 DQM0 = 105, DQM1 = 99
5923 00:43:21.894436 DQ Delay:
5924 00:43:21.898040 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5925 00:43:21.901100 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5926 00:43:21.904208 DQ8 =86, DQ9 =88, DQ10 =102, DQ11 =94
5927 00:43:21.907564 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =106
5928 00:43:21.907644
5929 00:43:21.907723
5930 00:43:21.917781 [DQSOSCAuto] RK1, (LSB)MR18= 0x3003, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
5931 00:43:21.917884 CH1 RK1: MR19=505, MR18=3003
5932 00:43:21.924531 CH1_RK1: MR19=0x505, MR18=0x3003, DQSOSC=406, MR23=63, INC=65, DEC=43
5933 00:43:21.927941 [RxdqsGatingPostProcess] freq 933
5934 00:43:21.934577 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5935 00:43:21.938056 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 00:43:21.941193 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 00:43:21.944342 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 00:43:21.947664 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 00:43:21.950747 best DQS0 dly(2T, 0.5T) = (0, 10)
5940 00:43:21.954262 best DQS1 dly(2T, 0.5T) = (0, 10)
5941 00:43:21.957398 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5942 00:43:21.957490 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5943 00:43:21.961192 Pre-setting of DQS Precalculation
5944 00:43:21.967720 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5945 00:43:21.974481 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5946 00:43:21.980781 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5947 00:43:21.980856
5948 00:43:21.980921
5949 00:43:21.984205 [Calibration Summary] 1866 Mbps
5950 00:43:21.987602 CH 0, Rank 0
5951 00:43:21.987696 SW Impedance : PASS
5952 00:43:21.991175 DUTY Scan : NO K
5953 00:43:21.991268 ZQ Calibration : PASS
5954 00:43:21.994477 Jitter Meter : NO K
5955 00:43:21.997260 CBT Training : PASS
5956 00:43:21.997350 Write leveling : PASS
5957 00:43:22.000605 RX DQS gating : PASS
5958 00:43:22.003975 RX DQ/DQS(RDDQC) : PASS
5959 00:43:22.004067 TX DQ/DQS : PASS
5960 00:43:22.007705 RX DATLAT : PASS
5961 00:43:22.010744 RX DQ/DQS(Engine): PASS
5962 00:43:22.010813 TX OE : NO K
5963 00:43:22.014279 All Pass.
5964 00:43:22.014371
5965 00:43:22.014459 CH 0, Rank 1
5966 00:43:22.017592 SW Impedance : PASS
5967 00:43:22.017663 DUTY Scan : NO K
5968 00:43:22.020946 ZQ Calibration : PASS
5969 00:43:22.024368 Jitter Meter : NO K
5970 00:43:22.024436 CBT Training : PASS
5971 00:43:22.027683 Write leveling : PASS
5972 00:43:22.030725 RX DQS gating : PASS
5973 00:43:22.030795 RX DQ/DQS(RDDQC) : PASS
5974 00:43:22.034417 TX DQ/DQS : PASS
5975 00:43:22.034485 RX DATLAT : PASS
5976 00:43:22.037616 RX DQ/DQS(Engine): PASS
5977 00:43:22.041147 TX OE : NO K
5978 00:43:22.041255 All Pass.
5979 00:43:22.041344
5980 00:43:22.041428 CH 1, Rank 0
5981 00:43:22.043863 SW Impedance : PASS
5982 00:43:22.047115 DUTY Scan : NO K
5983 00:43:22.047206 ZQ Calibration : PASS
5984 00:43:22.050540 Jitter Meter : NO K
5985 00:43:22.054347 CBT Training : PASS
5986 00:43:22.054445 Write leveling : PASS
5987 00:43:22.057747 RX DQS gating : PASS
5988 00:43:22.060995 RX DQ/DQS(RDDQC) : PASS
5989 00:43:22.061062 TX DQ/DQS : PASS
5990 00:43:22.064056 RX DATLAT : PASS
5991 00:43:22.067308 RX DQ/DQS(Engine): PASS
5992 00:43:22.067402 TX OE : NO K
5993 00:43:22.070739 All Pass.
5994 00:43:22.070809
5995 00:43:22.070867 CH 1, Rank 1
5996 00:43:22.074218 SW Impedance : PASS
5997 00:43:22.074285 DUTY Scan : NO K
5998 00:43:22.077185 ZQ Calibration : PASS
5999 00:43:22.080496 Jitter Meter : NO K
6000 00:43:22.080596 CBT Training : PASS
6001 00:43:22.083586 Write leveling : PASS
6002 00:43:22.087217 RX DQS gating : PASS
6003 00:43:22.087292 RX DQ/DQS(RDDQC) : PASS
6004 00:43:22.090750 TX DQ/DQS : PASS
6005 00:43:22.090816 RX DATLAT : PASS
6006 00:43:22.094098 RX DQ/DQS(Engine): PASS
6007 00:43:22.097202 TX OE : NO K
6008 00:43:22.097267 All Pass.
6009 00:43:22.097353
6010 00:43:22.100710 DramC Write-DBI off
6011 00:43:22.100788 PER_BANK_REFRESH: Hybrid Mode
6012 00:43:22.104057 TX_TRACKING: ON
6013 00:43:22.113976 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6014 00:43:22.117090 [FAST_K] Save calibration result to emmc
6015 00:43:22.120672 dramc_set_vcore_voltage set vcore to 650000
6016 00:43:22.120751 Read voltage for 400, 6
6017 00:43:22.123689 Vio18 = 0
6018 00:43:22.123759 Vcore = 650000
6019 00:43:22.123815 Vdram = 0
6020 00:43:22.126880 Vddq = 0
6021 00:43:22.126951 Vmddr = 0
6022 00:43:22.133722 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6023 00:43:22.136951 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6024 00:43:22.140179 MEM_TYPE=3, freq_sel=20
6025 00:43:22.143645 sv_algorithm_assistance_LP4_800
6026 00:43:22.146951 ============ PULL DRAM RESETB DOWN ============
6027 00:43:22.150330 ========== PULL DRAM RESETB DOWN end =========
6028 00:43:22.157052 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6029 00:43:22.160278 ===================================
6030 00:43:22.160390 LPDDR4 DRAM CONFIGURATION
6031 00:43:22.163770 ===================================
6032 00:43:22.167108 EX_ROW_EN[0] = 0x0
6033 00:43:22.167193 EX_ROW_EN[1] = 0x0
6034 00:43:22.170365 LP4Y_EN = 0x0
6035 00:43:22.173578 WORK_FSP = 0x0
6036 00:43:22.173701 WL = 0x2
6037 00:43:22.177139 RL = 0x2
6038 00:43:22.177217 BL = 0x2
6039 00:43:22.180402 RPST = 0x0
6040 00:43:22.180479 RD_PRE = 0x0
6041 00:43:22.183600 WR_PRE = 0x1
6042 00:43:22.183676 WR_PST = 0x0
6043 00:43:22.186769 DBI_WR = 0x0
6044 00:43:22.186883 DBI_RD = 0x0
6045 00:43:22.189817 OTF = 0x1
6046 00:43:22.193257 ===================================
6047 00:43:22.196606 ===================================
6048 00:43:22.196671 ANA top config
6049 00:43:22.199834 ===================================
6050 00:43:22.203530 DLL_ASYNC_EN = 0
6051 00:43:22.206956 ALL_SLAVE_EN = 1
6052 00:43:22.207050 NEW_RANK_MODE = 1
6053 00:43:22.209916 DLL_IDLE_MODE = 1
6054 00:43:22.213225 LP45_APHY_COMB_EN = 1
6055 00:43:22.216790 TX_ODT_DIS = 1
6056 00:43:22.220207 NEW_8X_MODE = 1
6057 00:43:22.223510 ===================================
6058 00:43:22.226681 ===================================
6059 00:43:22.226752 data_rate = 800
6060 00:43:22.229745 CKR = 1
6061 00:43:22.233275 DQ_P2S_RATIO = 4
6062 00:43:22.236840 ===================================
6063 00:43:22.240041 CA_P2S_RATIO = 4
6064 00:43:22.243419 DQ_CA_OPEN = 0
6065 00:43:22.246562 DQ_SEMI_OPEN = 1
6066 00:43:22.246628 CA_SEMI_OPEN = 1
6067 00:43:22.249867 CA_FULL_RATE = 0
6068 00:43:22.253292 DQ_CKDIV4_EN = 0
6069 00:43:22.256670 CA_CKDIV4_EN = 1
6070 00:43:22.259940 CA_PREDIV_EN = 0
6071 00:43:22.263325 PH8_DLY = 0
6072 00:43:22.263386 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6073 00:43:22.266496 DQ_AAMCK_DIV = 0
6074 00:43:22.270131 CA_AAMCK_DIV = 0
6075 00:43:22.273427 CA_ADMCK_DIV = 4
6076 00:43:22.276600 DQ_TRACK_CA_EN = 0
6077 00:43:22.279926 CA_PICK = 800
6078 00:43:22.280023 CA_MCKIO = 400
6079 00:43:22.283208 MCKIO_SEMI = 400
6080 00:43:22.286519 PLL_FREQ = 3016
6081 00:43:22.289786 DQ_UI_PI_RATIO = 32
6082 00:43:22.293058 CA_UI_PI_RATIO = 32
6083 00:43:22.296952 ===================================
6084 00:43:22.300323 ===================================
6085 00:43:22.302945 memory_type:LPDDR4
6086 00:43:22.303016 GP_NUM : 10
6087 00:43:22.306337 SRAM_EN : 1
6088 00:43:22.306427 MD32_EN : 0
6089 00:43:22.309590 ===================================
6090 00:43:22.313400 [ANA_INIT] >>>>>>>>>>>>>>
6091 00:43:22.316444 <<<<<< [CONFIGURE PHASE]: ANA_TX
6092 00:43:22.319744 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6093 00:43:22.323418 ===================================
6094 00:43:22.326435 data_rate = 800,PCW = 0X7400
6095 00:43:22.329946 ===================================
6096 00:43:22.333540 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6097 00:43:22.336727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 00:43:22.350043 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 00:43:22.353140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6100 00:43:22.356245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6101 00:43:22.359571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6102 00:43:22.362960 [ANA_INIT] flow start
6103 00:43:22.366341 [ANA_INIT] PLL >>>>>>>>
6104 00:43:22.366406 [ANA_INIT] PLL <<<<<<<<
6105 00:43:22.369800 [ANA_INIT] MIDPI >>>>>>>>
6106 00:43:22.373018 [ANA_INIT] MIDPI <<<<<<<<
6107 00:43:22.376242 [ANA_INIT] DLL >>>>>>>>
6108 00:43:22.376333 [ANA_INIT] flow end
6109 00:43:22.379329 ============ LP4 DIFF to SE enter ============
6110 00:43:22.385987 ============ LP4 DIFF to SE exit ============
6111 00:43:22.386086 [ANA_INIT] <<<<<<<<<<<<<
6112 00:43:22.389275 [Flow] Enable top DCM control >>>>>
6113 00:43:22.392604 [Flow] Enable top DCM control <<<<<
6114 00:43:22.395973 Enable DLL master slave shuffle
6115 00:43:22.403116 ==============================================================
6116 00:43:22.403195 Gating Mode config
6117 00:43:22.409862 ==============================================================
6118 00:43:22.412616 Config description:
6119 00:43:22.419817 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6120 00:43:22.426125 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6121 00:43:22.432937 SELPH_MODE 0: By rank 1: By Phase
6122 00:43:22.439312 ==============================================================
6123 00:43:22.439407 GAT_TRACK_EN = 0
6124 00:43:22.442857 RX_GATING_MODE = 2
6125 00:43:22.446340 RX_GATING_TRACK_MODE = 2
6126 00:43:22.449457 SELPH_MODE = 1
6127 00:43:22.452579 PICG_EARLY_EN = 1
6128 00:43:22.456231 VALID_LAT_VALUE = 1
6129 00:43:22.462652 ==============================================================
6130 00:43:22.465873 Enter into Gating configuration >>>>
6131 00:43:22.469259 Exit from Gating configuration <<<<
6132 00:43:22.472626 Enter into DVFS_PRE_config >>>>>
6133 00:43:22.482415 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6134 00:43:22.486277 Exit from DVFS_PRE_config <<<<<
6135 00:43:22.489260 Enter into PICG configuration >>>>
6136 00:43:22.492767 Exit from PICG configuration <<<<
6137 00:43:22.495740 [RX_INPUT] configuration >>>>>
6138 00:43:22.495834 [RX_INPUT] configuration <<<<<
6139 00:43:22.502463 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6140 00:43:22.509588 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6141 00:43:22.512812 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 00:43:22.519535 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 00:43:22.526032 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 00:43:22.532506 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 00:43:22.535859 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6146 00:43:22.539115 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6147 00:43:22.545880 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6148 00:43:22.549185 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6149 00:43:22.552330 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6150 00:43:22.559082 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6151 00:43:22.562298 ===================================
6152 00:43:22.562375 LPDDR4 DRAM CONFIGURATION
6153 00:43:22.565960 ===================================
6154 00:43:22.568925 EX_ROW_EN[0] = 0x0
6155 00:43:22.569001 EX_ROW_EN[1] = 0x0
6156 00:43:22.572479 LP4Y_EN = 0x0
6157 00:43:22.572555 WORK_FSP = 0x0
6158 00:43:22.575672 WL = 0x2
6159 00:43:22.575748 RL = 0x2
6160 00:43:22.578972 BL = 0x2
6161 00:43:22.582314 RPST = 0x0
6162 00:43:22.582390 RD_PRE = 0x0
6163 00:43:22.585674 WR_PRE = 0x1
6164 00:43:22.585750 WR_PST = 0x0
6165 00:43:22.589013 DBI_WR = 0x0
6166 00:43:22.589089 DBI_RD = 0x0
6167 00:43:22.592314 OTF = 0x1
6168 00:43:22.595673 ===================================
6169 00:43:22.598732 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6170 00:43:22.602524 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6171 00:43:22.605303 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 00:43:22.608834 ===================================
6173 00:43:22.612272 LPDDR4 DRAM CONFIGURATION
6174 00:43:22.615798 ===================================
6175 00:43:22.619324 EX_ROW_EN[0] = 0x10
6176 00:43:22.619416 EX_ROW_EN[1] = 0x0
6177 00:43:22.622102 LP4Y_EN = 0x0
6178 00:43:22.622194 WORK_FSP = 0x0
6179 00:43:22.625425 WL = 0x2
6180 00:43:22.625494 RL = 0x2
6181 00:43:22.628730 BL = 0x2
6182 00:43:22.628797 RPST = 0x0
6183 00:43:22.632051 RD_PRE = 0x0
6184 00:43:22.632146 WR_PRE = 0x1
6185 00:43:22.635334 WR_PST = 0x0
6186 00:43:22.638919 DBI_WR = 0x0
6187 00:43:22.639011 DBI_RD = 0x0
6188 00:43:22.641872 OTF = 0x1
6189 00:43:22.645714 ===================================
6190 00:43:22.649064 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6191 00:43:22.653830 nWR fixed to 30
6192 00:43:22.657248 [ModeRegInit_LP4] CH0 RK0
6193 00:43:22.657347 [ModeRegInit_LP4] CH0 RK1
6194 00:43:22.660502 [ModeRegInit_LP4] CH1 RK0
6195 00:43:22.663740 [ModeRegInit_LP4] CH1 RK1
6196 00:43:22.663833 match AC timing 19
6197 00:43:22.670730 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6198 00:43:22.673906 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6199 00:43:22.677203 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6200 00:43:22.683729 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6201 00:43:22.687239 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6202 00:43:22.687345 ==
6203 00:43:22.690755 Dram Type= 6, Freq= 0, CH_0, rank 0
6204 00:43:22.694071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6205 00:43:22.694165 ==
6206 00:43:22.700343 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6207 00:43:22.707159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6208 00:43:22.710396 [CA 0] Center 36 (8~64) winsize 57
6209 00:43:22.713694 [CA 1] Center 36 (8~64) winsize 57
6210 00:43:22.716871 [CA 2] Center 36 (8~64) winsize 57
6211 00:43:22.720174 [CA 3] Center 36 (8~64) winsize 57
6212 00:43:22.720248 [CA 4] Center 36 (8~64) winsize 57
6213 00:43:22.723508 [CA 5] Center 36 (8~64) winsize 57
6214 00:43:22.723600
6215 00:43:22.730412 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6216 00:43:22.730512
6217 00:43:22.733639 [CATrainingPosCal] consider 1 rank data
6218 00:43:22.737024 u2DelayCellTimex100 = 270/100 ps
6219 00:43:22.740292 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 00:43:22.743759 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 00:43:22.746976 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 00:43:22.750547 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 00:43:22.754015 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 00:43:22.757356 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 00:43:22.757473
6226 00:43:22.760074 CA PerBit enable=1, Macro0, CA PI delay=36
6227 00:43:22.760162
6228 00:43:22.763395 [CBTSetCACLKResult] CA Dly = 36
6229 00:43:22.766854 CS Dly: 1 (0~32)
6230 00:43:22.766940 ==
6231 00:43:22.770565 Dram Type= 6, Freq= 0, CH_0, rank 1
6232 00:43:22.773463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 00:43:22.773569 ==
6234 00:43:22.779980 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 00:43:22.783293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6236 00:43:22.786600 [CA 0] Center 36 (8~64) winsize 57
6237 00:43:22.790519 [CA 1] Center 36 (8~64) winsize 57
6238 00:43:22.793444 [CA 2] Center 36 (8~64) winsize 57
6239 00:43:22.796962 [CA 3] Center 36 (8~64) winsize 57
6240 00:43:22.799944 [CA 4] Center 36 (8~64) winsize 57
6241 00:43:22.803283 [CA 5] Center 36 (8~64) winsize 57
6242 00:43:22.803354
6243 00:43:22.806540 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6244 00:43:22.806633
6245 00:43:22.809958 [CATrainingPosCal] consider 2 rank data
6246 00:43:22.813254 u2DelayCellTimex100 = 270/100 ps
6247 00:43:22.816714 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 00:43:22.819845 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 00:43:22.826550 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 00:43:22.829885 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 00:43:22.833170 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 00:43:22.836506 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 00:43:22.836600
6254 00:43:22.840144 CA PerBit enable=1, Macro0, CA PI delay=36
6255 00:43:22.840229
6256 00:43:22.843063 [CBTSetCACLKResult] CA Dly = 36
6257 00:43:22.843164 CS Dly: 1 (0~32)
6258 00:43:22.843251
6259 00:43:22.846677 ----->DramcWriteLeveling(PI) begin...
6260 00:43:22.850034 ==
6261 00:43:22.850126 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 00:43:22.856459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 00:43:22.856537 ==
6264 00:43:22.860100 Write leveling (Byte 0): 40 => 8
6265 00:43:22.863411 Write leveling (Byte 1): 40 => 8
6266 00:43:22.863490 DramcWriteLeveling(PI) end<-----
6267 00:43:22.866810
6268 00:43:22.866888 ==
6269 00:43:22.869598 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 00:43:22.873054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 00:43:22.873132 ==
6272 00:43:22.876315 [Gating] SW mode calibration
6273 00:43:22.882868 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6274 00:43:22.886564 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6275 00:43:22.892833 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 00:43:22.896267 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 00:43:22.899751 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 00:43:22.906208 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 00:43:22.909852 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 00:43:22.913188 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 00:43:22.920132 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 00:43:22.922809 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 00:43:22.926205 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 00:43:22.929345 Total UI for P1: 0, mck2ui 16
6285 00:43:22.933126 best dqsien dly found for B0: ( 0, 14, 24)
6286 00:43:22.936440 Total UI for P1: 0, mck2ui 16
6287 00:43:22.939896 best dqsien dly found for B1: ( 0, 14, 24)
6288 00:43:22.943251 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6289 00:43:22.946675 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6290 00:43:22.946746
6291 00:43:22.952964 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 00:43:22.956638 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 00:43:22.956731 [Gating] SW calibration Done
6294 00:43:22.959809 ==
6295 00:43:22.959908 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 00:43:22.966227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 00:43:22.966330 ==
6298 00:43:22.966406 RX Vref Scan: 0
6299 00:43:22.966490
6300 00:43:22.969894 RX Vref 0 -> 0, step: 1
6301 00:43:22.969967
6302 00:43:22.973217 RX Delay -410 -> 252, step: 16
6303 00:43:22.976779 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6304 00:43:22.980064 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6305 00:43:22.986885 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6306 00:43:22.990037 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6307 00:43:22.993244 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6308 00:43:22.996246 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6309 00:43:23.003290 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6310 00:43:23.006682 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6311 00:43:23.010013 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6312 00:43:23.012965 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6313 00:43:23.019976 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6314 00:43:23.023167 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6315 00:43:23.026197 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6316 00:43:23.029799 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6317 00:43:23.036550 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6318 00:43:23.039956 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6319 00:43:23.040033 ==
6320 00:43:23.042983 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 00:43:23.046813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 00:43:23.046914 ==
6323 00:43:23.050215 DQS Delay:
6324 00:43:23.050289 DQS0 = 27, DQS1 = 35
6325 00:43:23.050347 DQM Delay:
6326 00:43:23.052944 DQM0 = 9, DQM1 = 11
6327 00:43:23.053011 DQ Delay:
6328 00:43:23.056350 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6329 00:43:23.059752 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6330 00:43:23.063538 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6331 00:43:23.066625 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6332 00:43:23.066695
6333 00:43:23.066765
6334 00:43:23.066846 ==
6335 00:43:23.069718 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 00:43:23.073307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 00:43:23.076218 ==
6338 00:43:23.076313
6339 00:43:23.076405
6340 00:43:23.076489 TX Vref Scan disable
6341 00:43:23.079924 == TX Byte 0 ==
6342 00:43:23.082798 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 00:43:23.086150 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 00:43:23.089685 == TX Byte 1 ==
6345 00:43:23.092965 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 00:43:23.096382 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 00:43:23.096477 ==
6348 00:43:23.099649 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 00:43:23.102690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 00:43:23.106312 ==
6351 00:43:23.106387
6352 00:43:23.106443
6353 00:43:23.106499 TX Vref Scan disable
6354 00:43:23.109886 == TX Byte 0 ==
6355 00:43:23.113075 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 00:43:23.116336 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 00:43:23.119709 == TX Byte 1 ==
6358 00:43:23.123120 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 00:43:23.126369 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 00:43:23.126464
6361 00:43:23.129519 [DATLAT]
6362 00:43:23.129644 Freq=400, CH0 RK0
6363 00:43:23.129733
6364 00:43:23.132768 DATLAT Default: 0xf
6365 00:43:23.132870 0, 0xFFFF, sum = 0
6366 00:43:23.135995 1, 0xFFFF, sum = 0
6367 00:43:23.136094 2, 0xFFFF, sum = 0
6368 00:43:23.139259 3, 0xFFFF, sum = 0
6369 00:43:23.139326 4, 0xFFFF, sum = 0
6370 00:43:23.143113 5, 0xFFFF, sum = 0
6371 00:43:23.143181 6, 0xFFFF, sum = 0
6372 00:43:23.146186 7, 0xFFFF, sum = 0
6373 00:43:23.146254 8, 0xFFFF, sum = 0
6374 00:43:23.149424 9, 0xFFFF, sum = 0
6375 00:43:23.149488 10, 0xFFFF, sum = 0
6376 00:43:23.152759 11, 0xFFFF, sum = 0
6377 00:43:23.152827 12, 0xFFFF, sum = 0
6378 00:43:23.156021 13, 0x0, sum = 1
6379 00:43:23.156114 14, 0x0, sum = 2
6380 00:43:23.159559 15, 0x0, sum = 3
6381 00:43:23.159659 16, 0x0, sum = 4
6382 00:43:23.162804 best_step = 14
6383 00:43:23.162870
6384 00:43:23.162923 ==
6385 00:43:23.166208 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 00:43:23.169670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 00:43:23.169741 ==
6388 00:43:23.172862 RX Vref Scan: 1
6389 00:43:23.172930
6390 00:43:23.172984 RX Vref 0 -> 0, step: 1
6391 00:43:23.173039
6392 00:43:23.176160 RX Delay -311 -> 252, step: 8
6393 00:43:23.176230
6394 00:43:23.179302 Set Vref, RX VrefLevel [Byte0]: 53
6395 00:43:23.182352 [Byte1]: 50
6396 00:43:23.187025
6397 00:43:23.187122 Final RX Vref Byte 0 = 53 to rank0
6398 00:43:23.190700 Final RX Vref Byte 1 = 50 to rank0
6399 00:43:23.194231 Final RX Vref Byte 0 = 53 to rank1
6400 00:43:23.197543 Final RX Vref Byte 1 = 50 to rank1==
6401 00:43:23.201086 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 00:43:23.203812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 00:43:23.207130 ==
6404 00:43:23.207209 DQS Delay:
6405 00:43:23.207273 DQS0 = 28, DQS1 = 36
6406 00:43:23.210387 DQM Delay:
6407 00:43:23.210452 DQM0 = 11, DQM1 = 12
6408 00:43:23.214106 DQ Delay:
6409 00:43:23.217025 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6410 00:43:23.217091 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6411 00:43:23.220707 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6412 00:43:23.223839 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6413 00:43:23.223911
6414 00:43:23.227027
6415 00:43:23.233758 [DQSOSCAuto] RK0, (LSB)MR18= 0xd3c0, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 383 ps
6416 00:43:23.237022 CH0 RK0: MR19=C0C, MR18=D3C0
6417 00:43:23.243785 CH0_RK0: MR19=0xC0C, MR18=0xD3C0, DQSOSC=383, MR23=63, INC=402, DEC=268
6418 00:43:23.243858 ==
6419 00:43:23.247031 Dram Type= 6, Freq= 0, CH_0, rank 1
6420 00:43:23.250575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 00:43:23.250667 ==
6422 00:43:23.253287 [Gating] SW mode calibration
6423 00:43:23.259945 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6424 00:43:23.267073 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6425 00:43:23.269931 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 00:43:23.273659 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 00:43:23.280354 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 00:43:23.283671 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 00:43:23.286961 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 00:43:23.293645 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 00:43:23.296509 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 00:43:23.300210 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 00:43:23.303248 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 00:43:23.306540 Total UI for P1: 0, mck2ui 16
6435 00:43:23.309770 best dqsien dly found for B0: ( 0, 14, 24)
6436 00:43:23.313229 Total UI for P1: 0, mck2ui 16
6437 00:43:23.316505 best dqsien dly found for B1: ( 0, 14, 24)
6438 00:43:23.323271 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6439 00:43:23.326369 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6440 00:43:23.326462
6441 00:43:23.329847 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 00:43:23.332913 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 00:43:23.336690 [Gating] SW calibration Done
6444 00:43:23.336793 ==
6445 00:43:23.339611 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 00:43:23.343323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 00:43:23.343421 ==
6448 00:43:23.346271 RX Vref Scan: 0
6449 00:43:23.346344
6450 00:43:23.346415 RX Vref 0 -> 0, step: 1
6451 00:43:23.346474
6452 00:43:23.349454 RX Delay -410 -> 252, step: 16
6453 00:43:23.352905 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6454 00:43:23.359683 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6455 00:43:23.363210 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6456 00:43:23.366485 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6457 00:43:23.369914 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6458 00:43:23.376073 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6459 00:43:23.379639 iDelay=230, Bit 6, Center -11 (-234 ~ 213) 448
6460 00:43:23.382735 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6461 00:43:23.386182 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6462 00:43:23.392856 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6463 00:43:23.396085 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6464 00:43:23.399427 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6465 00:43:23.402787 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6466 00:43:23.409323 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6467 00:43:23.413114 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6468 00:43:23.416488 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6469 00:43:23.416566 ==
6470 00:43:23.419601 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 00:43:23.426530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 00:43:23.426608 ==
6473 00:43:23.426669 DQS Delay:
6474 00:43:23.429940 DQS0 = 27, DQS1 = 35
6475 00:43:23.430018 DQM Delay:
6476 00:43:23.430077 DQM0 = 11, DQM1 = 12
6477 00:43:23.432684 DQ Delay:
6478 00:43:23.436600 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6479 00:43:23.436678 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6480 00:43:23.439353 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6481 00:43:23.442974 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6482 00:43:23.443051
6483 00:43:23.443111
6484 00:43:23.446216 ==
6485 00:43:23.449329 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 00:43:23.453043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 00:43:23.453121 ==
6488 00:43:23.453180
6489 00:43:23.453235
6490 00:43:23.456125 TX Vref Scan disable
6491 00:43:23.456203 == TX Byte 0 ==
6492 00:43:23.459722 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6493 00:43:23.466432 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6494 00:43:23.466511 == TX Byte 1 ==
6495 00:43:23.469354 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6496 00:43:23.472865 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6497 00:43:23.476249 ==
6498 00:43:23.479644 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 00:43:23.482991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 00:43:23.483061 ==
6501 00:43:23.483119
6502 00:43:23.483172
6503 00:43:23.486498 TX Vref Scan disable
6504 00:43:23.486569 == TX Byte 0 ==
6505 00:43:23.489845 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6506 00:43:23.496121 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6507 00:43:23.496207 == TX Byte 1 ==
6508 00:43:23.499323 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6509 00:43:23.502964 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6510 00:43:23.506375
6511 00:43:23.506456 [DATLAT]
6512 00:43:23.506520 Freq=400, CH0 RK1
6513 00:43:23.506576
6514 00:43:23.509501 DATLAT Default: 0xe
6515 00:43:23.509598 0, 0xFFFF, sum = 0
6516 00:43:23.512647 1, 0xFFFF, sum = 0
6517 00:43:23.512717 2, 0xFFFF, sum = 0
6518 00:43:23.516060 3, 0xFFFF, sum = 0
6519 00:43:23.516150 4, 0xFFFF, sum = 0
6520 00:43:23.519337 5, 0xFFFF, sum = 0
6521 00:43:23.522968 6, 0xFFFF, sum = 0
6522 00:43:23.523039 7, 0xFFFF, sum = 0
6523 00:43:23.526074 8, 0xFFFF, sum = 0
6524 00:43:23.526168 9, 0xFFFF, sum = 0
6525 00:43:23.529235 10, 0xFFFF, sum = 0
6526 00:43:23.529340 11, 0xFFFF, sum = 0
6527 00:43:23.532602 12, 0xFFFF, sum = 0
6528 00:43:23.532681 13, 0x0, sum = 1
6529 00:43:23.535897 14, 0x0, sum = 2
6530 00:43:23.535975 15, 0x0, sum = 3
6531 00:43:23.539325 16, 0x0, sum = 4
6532 00:43:23.539403 best_step = 14
6533 00:43:23.539462
6534 00:43:23.539517 ==
6535 00:43:23.542514 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 00:43:23.546000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 00:43:23.546077 ==
6538 00:43:23.549301 RX Vref Scan: 0
6539 00:43:23.549378
6540 00:43:23.552543 RX Vref 0 -> 0, step: 1
6541 00:43:23.552620
6542 00:43:23.552679 RX Delay -311 -> 252, step: 8
6543 00:43:23.561262 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6544 00:43:23.564989 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6545 00:43:23.568145 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6546 00:43:23.571620 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6547 00:43:23.578105 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6548 00:43:23.581394 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6549 00:43:23.584808 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6550 00:43:23.588121 iDelay=217, Bit 7, Center -4 (-223 ~ 216) 440
6551 00:43:23.594778 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6552 00:43:23.597992 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6553 00:43:23.601366 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6554 00:43:23.604672 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6555 00:43:23.611127 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6556 00:43:23.614354 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6557 00:43:23.618175 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6558 00:43:23.624776 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6559 00:43:23.624852 ==
6560 00:43:23.628072 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 00:43:23.631040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 00:43:23.631116 ==
6563 00:43:23.631176 DQS Delay:
6564 00:43:23.634183 DQS0 = 24, DQS1 = 32
6565 00:43:23.634259 DQM Delay:
6566 00:43:23.637670 DQM0 = 9, DQM1 = 9
6567 00:43:23.637747 DQ Delay:
6568 00:43:23.640807 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6569 00:43:23.644177 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =20
6570 00:43:23.647442 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6571 00:43:23.650654 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6572 00:43:23.650730
6573 00:43:23.650814
6574 00:43:23.657803 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6575 00:43:23.661017 CH0 RK1: MR19=C0C, MR18=BD5D
6576 00:43:23.667557 CH0_RK1: MR19=0xC0C, MR18=0xBD5D, DQSOSC=386, MR23=63, INC=396, DEC=264
6577 00:43:23.670820 [RxdqsGatingPostProcess] freq 400
6578 00:43:23.677124 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6579 00:43:23.677200 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 00:43:23.680882 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 00:43:23.683930 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 00:43:23.687700 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 00:43:23.690979 best DQS0 dly(2T, 0.5T) = (0, 10)
6584 00:43:23.694349 best DQS1 dly(2T, 0.5T) = (0, 10)
6585 00:43:23.697576 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6586 00:43:23.700802 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6587 00:43:23.704038 Pre-setting of DQS Precalculation
6588 00:43:23.707520 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6589 00:43:23.710809 ==
6590 00:43:23.710886 Dram Type= 6, Freq= 0, CH_1, rank 0
6591 00:43:23.717335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 00:43:23.717412 ==
6593 00:43:23.721026 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6594 00:43:23.727244 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6595 00:43:23.730968 [CA 0] Center 36 (8~64) winsize 57
6596 00:43:23.734390 [CA 1] Center 36 (8~64) winsize 57
6597 00:43:23.737540 [CA 2] Center 36 (8~64) winsize 57
6598 00:43:23.740669 [CA 3] Center 36 (8~64) winsize 57
6599 00:43:23.743765 [CA 4] Center 36 (8~64) winsize 57
6600 00:43:23.747331 [CA 5] Center 36 (8~64) winsize 57
6601 00:43:23.747408
6602 00:43:23.750371 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6603 00:43:23.750448
6604 00:43:23.753494 [CATrainingPosCal] consider 1 rank data
6605 00:43:23.757437 u2DelayCellTimex100 = 270/100 ps
6606 00:43:23.760725 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 00:43:23.763860 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 00:43:23.766972 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 00:43:23.770362 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 00:43:23.777153 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 00:43:23.780526 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 00:43:23.780601
6613 00:43:23.783749 CA PerBit enable=1, Macro0, CA PI delay=36
6614 00:43:23.783825
6615 00:43:23.786919 [CBTSetCACLKResult] CA Dly = 36
6616 00:43:23.786996 CS Dly: 1 (0~32)
6617 00:43:23.787054 ==
6618 00:43:23.791026 Dram Type= 6, Freq= 0, CH_1, rank 1
6619 00:43:23.796633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 00:43:23.796725 ==
6621 00:43:23.800354 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 00:43:23.806804 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6623 00:43:23.810199 [CA 0] Center 36 (8~64) winsize 57
6624 00:43:23.813368 [CA 1] Center 36 (8~64) winsize 57
6625 00:43:23.816708 [CA 2] Center 36 (8~64) winsize 57
6626 00:43:23.820082 [CA 3] Center 36 (8~64) winsize 57
6627 00:43:23.823314 [CA 4] Center 36 (8~64) winsize 57
6628 00:43:23.826481 [CA 5] Center 36 (8~64) winsize 57
6629 00:43:23.826557
6630 00:43:23.830034 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6631 00:43:23.830137
6632 00:43:23.833268 [CATrainingPosCal] consider 2 rank data
6633 00:43:23.836551 u2DelayCellTimex100 = 270/100 ps
6634 00:43:23.840327 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 00:43:23.843510 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 00:43:23.846767 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 00:43:23.849947 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 00:43:23.853684 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 00:43:23.856908 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 00:43:23.856993
6641 00:43:23.863587 CA PerBit enable=1, Macro0, CA PI delay=36
6642 00:43:23.863687
6643 00:43:23.863774 [CBTSetCACLKResult] CA Dly = 36
6644 00:43:23.866896 CS Dly: 1 (0~32)
6645 00:43:23.866992
6646 00:43:23.870020 ----->DramcWriteLeveling(PI) begin...
6647 00:43:23.870091 ==
6648 00:43:23.873292 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 00:43:23.876534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 00:43:23.876626 ==
6651 00:43:23.879892 Write leveling (Byte 0): 40 => 8
6652 00:43:23.883302 Write leveling (Byte 1): 40 => 8
6653 00:43:23.886309 DramcWriteLeveling(PI) end<-----
6654 00:43:23.886400
6655 00:43:23.886486 ==
6656 00:43:23.889667 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 00:43:23.893475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 00:43:23.896335 ==
6659 00:43:23.896409 [Gating] SW mode calibration
6660 00:43:23.903170 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6661 00:43:23.910079 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6662 00:43:23.913131 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 00:43:23.919812 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 00:43:23.923168 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 00:43:23.926391 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 00:43:23.932969 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 00:43:23.936354 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 00:43:23.939391 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 00:43:23.946328 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 00:43:23.949404 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 00:43:23.952619 Total UI for P1: 0, mck2ui 16
6672 00:43:23.956299 best dqsien dly found for B0: ( 0, 14, 24)
6673 00:43:23.959638 Total UI for P1: 0, mck2ui 16
6674 00:43:23.962953 best dqsien dly found for B1: ( 0, 14, 24)
6675 00:43:23.966294 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6676 00:43:23.969368 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6677 00:43:23.969461
6678 00:43:23.972453 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 00:43:23.976084 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 00:43:23.979237 [Gating] SW calibration Done
6681 00:43:23.979336 ==
6682 00:43:23.982574 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 00:43:23.985893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 00:43:23.989169 ==
6685 00:43:23.989259 RX Vref Scan: 0
6686 00:43:23.989351
6687 00:43:23.992994 RX Vref 0 -> 0, step: 1
6688 00:43:23.993082
6689 00:43:23.996311 RX Delay -410 -> 252, step: 16
6690 00:43:23.999556 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6691 00:43:24.002863 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6692 00:43:24.006144 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6693 00:43:24.012766 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6694 00:43:24.015912 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6695 00:43:24.019178 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6696 00:43:24.022679 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6697 00:43:24.029356 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6698 00:43:24.032709 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6699 00:43:24.036035 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6700 00:43:24.039141 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6701 00:43:24.045948 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6702 00:43:24.049236 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6703 00:43:24.052353 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6704 00:43:24.055964 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6705 00:43:24.062397 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6706 00:43:24.062469 ==
6707 00:43:24.066055 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 00:43:24.069291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 00:43:24.069384 ==
6710 00:43:24.069477 DQS Delay:
6711 00:43:24.072639 DQS0 = 35, DQS1 = 35
6712 00:43:24.072727 DQM Delay:
6713 00:43:24.075883 DQM0 = 18, DQM1 = 13
6714 00:43:24.075971 DQ Delay:
6715 00:43:24.079010 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6716 00:43:24.082819 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6717 00:43:24.085847 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6718 00:43:24.089043 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6719 00:43:24.089143
6720 00:43:24.089226
6721 00:43:24.089312 ==
6722 00:43:24.092293 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 00:43:24.095602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 00:43:24.095694 ==
6725 00:43:24.095778
6726 00:43:24.095857
6727 00:43:24.098911 TX Vref Scan disable
6728 00:43:24.102733 == TX Byte 0 ==
6729 00:43:24.105964 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 00:43:24.109364 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 00:43:24.112445 == TX Byte 1 ==
6732 00:43:24.115708 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 00:43:24.119085 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 00:43:24.119161 ==
6735 00:43:24.122494 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 00:43:24.125568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 00:43:24.125658 ==
6738 00:43:24.125716
6739 00:43:24.129427
6740 00:43:24.129503 TX Vref Scan disable
6741 00:43:24.132499 == TX Byte 0 ==
6742 00:43:24.135894 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 00:43:24.139332 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 00:43:24.142725 == TX Byte 1 ==
6745 00:43:24.145969 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 00:43:24.149214 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 00:43:24.149304
6748 00:43:24.149385 [DATLAT]
6749 00:43:24.152482 Freq=400, CH1 RK0
6750 00:43:24.152546
6751 00:43:24.152600 DATLAT Default: 0xf
6752 00:43:24.155792 0, 0xFFFF, sum = 0
6753 00:43:24.155852 1, 0xFFFF, sum = 0
6754 00:43:24.159750 2, 0xFFFF, sum = 0
6755 00:43:24.159837 3, 0xFFFF, sum = 0
6756 00:43:24.163129 4, 0xFFFF, sum = 0
6757 00:43:24.163217 5, 0xFFFF, sum = 0
6758 00:43:24.166150 6, 0xFFFF, sum = 0
6759 00:43:24.169257 7, 0xFFFF, sum = 0
6760 00:43:24.169357 8, 0xFFFF, sum = 0
6761 00:43:24.172804 9, 0xFFFF, sum = 0
6762 00:43:24.172869 10, 0xFFFF, sum = 0
6763 00:43:24.175737 11, 0xFFFF, sum = 0
6764 00:43:24.175873 12, 0xFFFF, sum = 0
6765 00:43:24.179257 13, 0x0, sum = 1
6766 00:43:24.179353 14, 0x0, sum = 2
6767 00:43:24.182411 15, 0x0, sum = 3
6768 00:43:24.182503 16, 0x0, sum = 4
6769 00:43:24.182588 best_step = 14
6770 00:43:24.185690
6771 00:43:24.185750 ==
6772 00:43:24.189623 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 00:43:24.192641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 00:43:24.192736 ==
6775 00:43:24.192819 RX Vref Scan: 1
6776 00:43:24.192909
6777 00:43:24.195818 RX Vref 0 -> 0, step: 1
6778 00:43:24.195909
6779 00:43:24.199368 RX Delay -311 -> 252, step: 8
6780 00:43:24.199456
6781 00:43:24.202353 Set Vref, RX VrefLevel [Byte0]: 53
6782 00:43:24.205700 [Byte1]: 45
6783 00:43:24.209509
6784 00:43:24.209608 Final RX Vref Byte 0 = 53 to rank0
6785 00:43:24.212853 Final RX Vref Byte 1 = 45 to rank0
6786 00:43:24.215985 Final RX Vref Byte 0 = 53 to rank1
6787 00:43:24.219854 Final RX Vref Byte 1 = 45 to rank1==
6788 00:43:24.222605 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 00:43:24.229250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 00:43:24.229342 ==
6791 00:43:24.229434 DQS Delay:
6792 00:43:24.232424 DQS0 = 32, DQS1 = 36
6793 00:43:24.232518 DQM Delay:
6794 00:43:24.232604 DQM0 = 13, DQM1 = 15
6795 00:43:24.236275 DQ Delay:
6796 00:43:24.239677 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6797 00:43:24.242943 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6798 00:43:24.243034 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6799 00:43:24.245694 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =24
6800 00:43:24.249018
6801 00:43:24.249104
6802 00:43:24.256248 [DQSOSCAuto] RK0, (LSB)MR18= 0x97cf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 390 ps
6803 00:43:24.259460 CH1 RK0: MR19=C0C, MR18=97CF
6804 00:43:24.265869 CH1_RK0: MR19=0xC0C, MR18=0x97CF, DQSOSC=384, MR23=63, INC=400, DEC=267
6805 00:43:24.265964 ==
6806 00:43:24.269255 Dram Type= 6, Freq= 0, CH_1, rank 1
6807 00:43:24.272600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 00:43:24.272696 ==
6809 00:43:24.276070 [Gating] SW mode calibration
6810 00:43:24.282258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6811 00:43:24.289095 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6812 00:43:24.292527 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 00:43:24.295497 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6814 00:43:24.302323 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 00:43:24.305928 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 00:43:24.308848 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 00:43:24.315867 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 00:43:24.318978 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 00:43:24.322211 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 00:43:24.325563 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 00:43:24.328931 Total UI for P1: 0, mck2ui 16
6822 00:43:24.332479 best dqsien dly found for B0: ( 0, 14, 24)
6823 00:43:24.335698 Total UI for P1: 0, mck2ui 16
6824 00:43:24.338866 best dqsien dly found for B1: ( 0, 14, 24)
6825 00:43:24.341997 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6826 00:43:24.349384 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6827 00:43:24.349460
6828 00:43:24.352053 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 00:43:24.355419 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 00:43:24.358797 [Gating] SW calibration Done
6831 00:43:24.358872 ==
6832 00:43:24.362191 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 00:43:24.365272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 00:43:24.365347 ==
6835 00:43:24.368530 RX Vref Scan: 0
6836 00:43:24.368627
6837 00:43:24.368722 RX Vref 0 -> 0, step: 1
6838 00:43:24.368805
6839 00:43:24.372142 RX Delay -410 -> 252, step: 16
6840 00:43:24.375451 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6841 00:43:24.382282 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6842 00:43:24.385731 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6843 00:43:24.388993 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6844 00:43:24.392219 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6845 00:43:24.398567 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6846 00:43:24.402229 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6847 00:43:24.405525 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6848 00:43:24.408443 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6849 00:43:24.415047 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6850 00:43:24.418500 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6851 00:43:24.421672 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6852 00:43:24.425129 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6853 00:43:24.432182 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6854 00:43:24.435296 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6855 00:43:24.438656 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6856 00:43:24.438749 ==
6857 00:43:24.441923 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 00:43:24.448962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 00:43:24.449057 ==
6860 00:43:24.449148 DQS Delay:
6861 00:43:24.449232 DQS0 = 35, DQS1 = 35
6862 00:43:24.452246 DQM Delay:
6863 00:43:24.452308 DQM0 = 19, DQM1 = 14
6864 00:43:24.454948 DQ Delay:
6865 00:43:24.458288 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6866 00:43:24.461681 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6867 00:43:24.461759 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6868 00:43:24.465039 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =32
6869 00:43:24.468397
6870 00:43:24.468484
6871 00:43:24.468564 ==
6872 00:43:24.471710 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 00:43:24.474902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 00:43:24.474991 ==
6875 00:43:24.475072
6876 00:43:24.475160
6877 00:43:24.478638 TX Vref Scan disable
6878 00:43:24.478727 == TX Byte 0 ==
6879 00:43:24.481959 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6880 00:43:24.488661 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6881 00:43:24.488757 == TX Byte 1 ==
6882 00:43:24.491303 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6883 00:43:24.497967 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6884 00:43:24.498062 ==
6885 00:43:24.501991 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 00:43:24.505342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 00:43:24.505429 ==
6888 00:43:24.505519
6889 00:43:24.505639
6890 00:43:24.508678 TX Vref Scan disable
6891 00:43:24.508754 == TX Byte 0 ==
6892 00:43:24.511718 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6893 00:43:24.518237 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6894 00:43:24.518336 == TX Byte 1 ==
6895 00:43:24.521796 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6896 00:43:24.528565 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6897 00:43:24.528642
6898 00:43:24.528701 [DATLAT]
6899 00:43:24.528755 Freq=400, CH1 RK1
6900 00:43:24.528837
6901 00:43:24.531704 DATLAT Default: 0xe
6902 00:43:24.534828 0, 0xFFFF, sum = 0
6903 00:43:24.534905 1, 0xFFFF, sum = 0
6904 00:43:24.538044 2, 0xFFFF, sum = 0
6905 00:43:24.538120 3, 0xFFFF, sum = 0
6906 00:43:24.541766 4, 0xFFFF, sum = 0
6907 00:43:24.541842 5, 0xFFFF, sum = 0
6908 00:43:24.544793 6, 0xFFFF, sum = 0
6909 00:43:24.544868 7, 0xFFFF, sum = 0
6910 00:43:24.548422 8, 0xFFFF, sum = 0
6911 00:43:24.548513 9, 0xFFFF, sum = 0
6912 00:43:24.551489 10, 0xFFFF, sum = 0
6913 00:43:24.551564 11, 0xFFFF, sum = 0
6914 00:43:24.554730 12, 0xFFFF, sum = 0
6915 00:43:24.554806 13, 0x0, sum = 1
6916 00:43:24.558335 14, 0x0, sum = 2
6917 00:43:24.558411 15, 0x0, sum = 3
6918 00:43:24.561757 16, 0x0, sum = 4
6919 00:43:24.561847 best_step = 14
6920 00:43:24.561905
6921 00:43:24.561958 ==
6922 00:43:24.564545 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 00:43:24.571316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 00:43:24.571392 ==
6925 00:43:24.571487 RX Vref Scan: 0
6926 00:43:24.571560
6927 00:43:24.574673 RX Vref 0 -> 0, step: 1
6928 00:43:24.574747
6929 00:43:24.578065 RX Delay -311 -> 252, step: 8
6930 00:43:24.584462 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6931 00:43:24.587721 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6932 00:43:24.591007 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6933 00:43:24.594813 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6934 00:43:24.600988 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6935 00:43:24.604904 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6936 00:43:24.608227 iDelay=217, Bit 6, Center -4 (-223 ~ 216) 440
6937 00:43:24.611540 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6938 00:43:24.614852 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6939 00:43:24.621485 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6940 00:43:24.624661 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6941 00:43:24.628129 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6942 00:43:24.631439 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6943 00:43:24.638201 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6944 00:43:24.641171 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6945 00:43:24.644240 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6946 00:43:24.644315 ==
6947 00:43:24.647803 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 00:43:24.654251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 00:43:24.654326 ==
6950 00:43:24.654389 DQS Delay:
6951 00:43:24.657875 DQS0 = 28, DQS1 = 32
6952 00:43:24.657950 DQM Delay:
6953 00:43:24.658008 DQM0 = 11, DQM1 = 11
6954 00:43:24.660887 DQ Delay:
6955 00:43:24.664513 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6956 00:43:24.664635 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6957 00:43:24.667999 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6958 00:43:24.671377 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6959 00:43:24.671452
6960 00:43:24.674588
6961 00:43:24.681403 [DQSOSCAuto] RK1, (LSB)MR18= 0xcb5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
6962 00:43:24.684619 CH1 RK1: MR19=C0C, MR18=CB5B
6963 00:43:24.691161 CH1_RK1: MR19=0xC0C, MR18=0xCB5B, DQSOSC=384, MR23=63, INC=400, DEC=267
6964 00:43:24.691237 [RxdqsGatingPostProcess] freq 400
6965 00:43:24.697821 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6966 00:43:24.701100 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 00:43:24.704370 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 00:43:24.708022 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 00:43:24.710968 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 00:43:24.714283 best DQS0 dly(2T, 0.5T) = (0, 10)
6971 00:43:24.717581 best DQS1 dly(2T, 0.5T) = (0, 10)
6972 00:43:24.720999 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6973 00:43:24.724301 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6974 00:43:24.727704 Pre-setting of DQS Precalculation
6975 00:43:24.731082 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6976 00:43:24.737736 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6977 00:43:24.744375 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6978 00:43:24.747792
6979 00:43:24.747886
6980 00:43:24.747970 [Calibration Summary] 800 Mbps
6981 00:43:24.751096 CH 0, Rank 0
6982 00:43:24.751171 SW Impedance : PASS
6983 00:43:24.754080 DUTY Scan : NO K
6984 00:43:24.757455 ZQ Calibration : PASS
6985 00:43:24.757530 Jitter Meter : NO K
6986 00:43:24.760845 CBT Training : PASS
6987 00:43:24.764494 Write leveling : PASS
6988 00:43:24.764604 RX DQS gating : PASS
6989 00:43:24.767542 RX DQ/DQS(RDDQC) : PASS
6990 00:43:24.771099 TX DQ/DQS : PASS
6991 00:43:24.771189 RX DATLAT : PASS
6992 00:43:24.773905 RX DQ/DQS(Engine): PASS
6993 00:43:24.777604 TX OE : NO K
6994 00:43:24.777695 All Pass.
6995 00:43:24.777753
6996 00:43:24.777810 CH 0, Rank 1
6997 00:43:24.780962 SW Impedance : PASS
6998 00:43:24.783958 DUTY Scan : NO K
6999 00:43:24.784032 ZQ Calibration : PASS
7000 00:43:24.787935 Jitter Meter : NO K
7001 00:43:24.790519 CBT Training : PASS
7002 00:43:24.790594 Write leveling : NO K
7003 00:43:24.794274 RX DQS gating : PASS
7004 00:43:24.794348 RX DQ/DQS(RDDQC) : PASS
7005 00:43:24.797662 TX DQ/DQS : PASS
7006 00:43:24.801018 RX DATLAT : PASS
7007 00:43:24.801092 RX DQ/DQS(Engine): PASS
7008 00:43:24.804374 TX OE : NO K
7009 00:43:24.804449 All Pass.
7010 00:43:24.804530
7011 00:43:24.807608 CH 1, Rank 0
7012 00:43:24.807682 SW Impedance : PASS
7013 00:43:24.810952 DUTY Scan : NO K
7014 00:43:24.814323 ZQ Calibration : PASS
7015 00:43:24.814398 Jitter Meter : NO K
7016 00:43:24.817379 CBT Training : PASS
7017 00:43:24.820942 Write leveling : PASS
7018 00:43:24.821033 RX DQS gating : PASS
7019 00:43:24.823753 RX DQ/DQS(RDDQC) : PASS
7020 00:43:24.827121 TX DQ/DQS : PASS
7021 00:43:24.827197 RX DATLAT : PASS
7022 00:43:24.830429 RX DQ/DQS(Engine): PASS
7023 00:43:24.833776 TX OE : NO K
7024 00:43:24.833851 All Pass.
7025 00:43:24.833908
7026 00:43:24.833970 CH 1, Rank 1
7027 00:43:24.837152 SW Impedance : PASS
7028 00:43:24.840520 DUTY Scan : NO K
7029 00:43:24.840594 ZQ Calibration : PASS
7030 00:43:24.843813 Jitter Meter : NO K
7031 00:43:24.847181 CBT Training : PASS
7032 00:43:24.847273 Write leveling : NO K
7033 00:43:24.850362 RX DQS gating : PASS
7034 00:43:24.850429 RX DQ/DQS(RDDQC) : PASS
7035 00:43:24.854123 TX DQ/DQS : PASS
7036 00:43:24.857282 RX DATLAT : PASS
7037 00:43:24.857370 RX DQ/DQS(Engine): PASS
7038 00:43:24.860513 TX OE : NO K
7039 00:43:24.860592 All Pass.
7040 00:43:24.860649
7041 00:43:24.863820 DramC Write-DBI off
7042 00:43:24.866845 PER_BANK_REFRESH: Hybrid Mode
7043 00:43:24.866991 TX_TRACKING: ON
7044 00:43:24.876901 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7045 00:43:24.880443 [FAST_K] Save calibration result to emmc
7046 00:43:24.883407 dramc_set_vcore_voltage set vcore to 725000
7047 00:43:24.886955 Read voltage for 1600, 0
7048 00:43:24.887039 Vio18 = 0
7049 00:43:24.890456 Vcore = 725000
7050 00:43:24.890525 Vdram = 0
7051 00:43:24.890580 Vddq = 0
7052 00:43:24.890632 Vmddr = 0
7053 00:43:24.897154 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7054 00:43:24.900580 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7055 00:43:24.903425 MEM_TYPE=3, freq_sel=13
7056 00:43:24.907130 sv_algorithm_assistance_LP4_3733
7057 00:43:24.910273 ============ PULL DRAM RESETB DOWN ============
7058 00:43:24.916929 ========== PULL DRAM RESETB DOWN end =========
7059 00:43:24.920263 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7060 00:43:24.923550 ===================================
7061 00:43:24.927074 LPDDR4 DRAM CONFIGURATION
7062 00:43:24.930524 ===================================
7063 00:43:24.930600 EX_ROW_EN[0] = 0x0
7064 00:43:24.933842 EX_ROW_EN[1] = 0x0
7065 00:43:24.933917 LP4Y_EN = 0x0
7066 00:43:24.937240 WORK_FSP = 0x1
7067 00:43:24.937315 WL = 0x5
7068 00:43:24.940570 RL = 0x5
7069 00:43:24.940645 BL = 0x2
7070 00:43:24.943295 RPST = 0x0
7071 00:43:24.943371 RD_PRE = 0x0
7072 00:43:24.946686 WR_PRE = 0x1
7073 00:43:24.946761 WR_PST = 0x1
7074 00:43:24.950012 DBI_WR = 0x0
7075 00:43:24.950089 DBI_RD = 0x0
7076 00:43:24.953413 OTF = 0x1
7077 00:43:24.956649 ===================================
7078 00:43:24.959869 ===================================
7079 00:43:24.959946 ANA top config
7080 00:43:24.963582 ===================================
7081 00:43:24.966852 DLL_ASYNC_EN = 0
7082 00:43:24.970160 ALL_SLAVE_EN = 0
7083 00:43:24.973708 NEW_RANK_MODE = 1
7084 00:43:24.976859 DLL_IDLE_MODE = 1
7085 00:43:24.976939 LP45_APHY_COMB_EN = 1
7086 00:43:24.980171 TX_ODT_DIS = 0
7087 00:43:24.983347 NEW_8X_MODE = 1
7088 00:43:24.986914 ===================================
7089 00:43:24.989936 ===================================
7090 00:43:24.993215 data_rate = 3200
7091 00:43:24.996978 CKR = 1
7092 00:43:24.997054 DQ_P2S_RATIO = 8
7093 00:43:24.999666 ===================================
7094 00:43:25.003242 CA_P2S_RATIO = 8
7095 00:43:25.006576 DQ_CA_OPEN = 0
7096 00:43:25.009845 DQ_SEMI_OPEN = 0
7097 00:43:25.012993 CA_SEMI_OPEN = 0
7098 00:43:25.016668 CA_FULL_RATE = 0
7099 00:43:25.016743 DQ_CKDIV4_EN = 0
7100 00:43:25.020068 CA_CKDIV4_EN = 0
7101 00:43:25.023428 CA_PREDIV_EN = 0
7102 00:43:25.026237 PH8_DLY = 12
7103 00:43:25.029844 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7104 00:43:25.033245 DQ_AAMCK_DIV = 4
7105 00:43:25.033343 CA_AAMCK_DIV = 4
7106 00:43:25.036737 CA_ADMCK_DIV = 4
7107 00:43:25.040049 DQ_TRACK_CA_EN = 0
7108 00:43:25.043359 CA_PICK = 1600
7109 00:43:25.046727 CA_MCKIO = 1600
7110 00:43:25.050147 MCKIO_SEMI = 0
7111 00:43:25.053387 PLL_FREQ = 3068
7112 00:43:25.053486 DQ_UI_PI_RATIO = 32
7113 00:43:25.056745 CA_UI_PI_RATIO = 0
7114 00:43:25.060106 ===================================
7115 00:43:25.063389 ===================================
7116 00:43:25.066728 memory_type:LPDDR4
7117 00:43:25.069693 GP_NUM : 10
7118 00:43:25.069772 SRAM_EN : 1
7119 00:43:25.073431 MD32_EN : 0
7120 00:43:25.076811 ===================================
7121 00:43:25.076902 [ANA_INIT] >>>>>>>>>>>>>>
7122 00:43:25.079945 <<<<<< [CONFIGURE PHASE]: ANA_TX
7123 00:43:25.083245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7124 00:43:25.086635 ===================================
7125 00:43:25.089862 data_rate = 3200,PCW = 0X7600
7126 00:43:25.092951 ===================================
7127 00:43:25.096134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7128 00:43:25.102727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 00:43:25.110088 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 00:43:25.112909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7131 00:43:25.116202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7132 00:43:25.119509 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7133 00:43:25.122886 [ANA_INIT] flow start
7134 00:43:25.122961 [ANA_INIT] PLL >>>>>>>>
7135 00:43:25.126136 [ANA_INIT] PLL <<<<<<<<
7136 00:43:25.129448 [ANA_INIT] MIDPI >>>>>>>>
7137 00:43:25.129568 [ANA_INIT] MIDPI <<<<<<<<
7138 00:43:25.132707 [ANA_INIT] DLL >>>>>>>>
7139 00:43:25.135927 [ANA_INIT] DLL <<<<<<<<
7140 00:43:25.136045 [ANA_INIT] flow end
7141 00:43:25.142982 ============ LP4 DIFF to SE enter ============
7142 00:43:25.145870 ============ LP4 DIFF to SE exit ============
7143 00:43:25.149659 [ANA_INIT] <<<<<<<<<<<<<
7144 00:43:25.153038 [Flow] Enable top DCM control >>>>>
7145 00:43:25.155932 [Flow] Enable top DCM control <<<<<
7146 00:43:25.156038 Enable DLL master slave shuffle
7147 00:43:25.162508 ==============================================================
7148 00:43:25.165849 Gating Mode config
7149 00:43:25.169312 ==============================================================
7150 00:43:25.172534 Config description:
7151 00:43:25.182856 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7152 00:43:25.189503 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7153 00:43:25.192355 SELPH_MODE 0: By rank 1: By Phase
7154 00:43:25.199495 ==============================================================
7155 00:43:25.202657 GAT_TRACK_EN = 1
7156 00:43:25.205859 RX_GATING_MODE = 2
7157 00:43:25.209029 RX_GATING_TRACK_MODE = 2
7158 00:43:25.209123 SELPH_MODE = 1
7159 00:43:25.212535 PICG_EARLY_EN = 1
7160 00:43:25.216105 VALID_LAT_VALUE = 1
7161 00:43:25.222648 ==============================================================
7162 00:43:25.226012 Enter into Gating configuration >>>>
7163 00:43:25.229255 Exit from Gating configuration <<<<
7164 00:43:25.232532 Enter into DVFS_PRE_config >>>>>
7165 00:43:25.242597 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7166 00:43:25.245827 Exit from DVFS_PRE_config <<<<<
7167 00:43:25.249133 Enter into PICG configuration >>>>
7168 00:43:25.252461 Exit from PICG configuration <<<<
7169 00:43:25.255573 [RX_INPUT] configuration >>>>>
7170 00:43:25.259057 [RX_INPUT] configuration <<<<<
7171 00:43:25.262510 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7172 00:43:25.269092 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7173 00:43:25.276160 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 00:43:25.282378 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 00:43:25.285544 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 00:43:25.292675 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 00:43:25.296052 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7178 00:43:25.302409 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7179 00:43:25.305696 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7180 00:43:25.308779 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7181 00:43:25.312478 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7182 00:43:25.319055 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7183 00:43:25.322652 ===================================
7184 00:43:25.322718 LPDDR4 DRAM CONFIGURATION
7185 00:43:25.325768 ===================================
7186 00:43:25.328656 EX_ROW_EN[0] = 0x0
7187 00:43:25.332344 EX_ROW_EN[1] = 0x0
7188 00:43:25.332435 LP4Y_EN = 0x0
7189 00:43:25.335579 WORK_FSP = 0x1
7190 00:43:25.335655 WL = 0x5
7191 00:43:25.338776 RL = 0x5
7192 00:43:25.338865 BL = 0x2
7193 00:43:25.342158 RPST = 0x0
7194 00:43:25.342246 RD_PRE = 0x0
7195 00:43:25.345499 WR_PRE = 0x1
7196 00:43:25.345624 WR_PST = 0x1
7197 00:43:25.348756 DBI_WR = 0x0
7198 00:43:25.348842 DBI_RD = 0x0
7199 00:43:25.351919 OTF = 0x1
7200 00:43:25.355302 ===================================
7201 00:43:25.358630 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7202 00:43:25.361913 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7203 00:43:25.368656 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 00:43:25.372553 ===================================
7205 00:43:25.372628 LPDDR4 DRAM CONFIGURATION
7206 00:43:25.375462 ===================================
7207 00:43:25.378854 EX_ROW_EN[0] = 0x10
7208 00:43:25.382512 EX_ROW_EN[1] = 0x0
7209 00:43:25.382587 LP4Y_EN = 0x0
7210 00:43:25.385461 WORK_FSP = 0x1
7211 00:43:25.385561 WL = 0x5
7212 00:43:25.389062 RL = 0x5
7213 00:43:25.389156 BL = 0x2
7214 00:43:25.392563 RPST = 0x0
7215 00:43:25.392651 RD_PRE = 0x0
7216 00:43:25.395291 WR_PRE = 0x1
7217 00:43:25.395357 WR_PST = 0x1
7218 00:43:25.398389 DBI_WR = 0x0
7219 00:43:25.398459 DBI_RD = 0x0
7220 00:43:25.402066 OTF = 0x1
7221 00:43:25.405368 ===================================
7222 00:43:25.412129 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7223 00:43:25.412208 ==
7224 00:43:25.415382 Dram Type= 6, Freq= 0, CH_0, rank 0
7225 00:43:25.418635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7226 00:43:25.418742 ==
7227 00:43:25.421937 [Duty_Offset_Calibration]
7228 00:43:25.422042 B0:2 B1:1 CA:1
7229 00:43:25.422100
7230 00:43:25.425282 [DutyScan_Calibration_Flow] k_type=0
7231 00:43:25.435936
7232 00:43:25.436010 ==CLK 0==
7233 00:43:25.438994 Final CLK duty delay cell = 0
7234 00:43:25.442700 [0] MAX Duty = 5156%(X100), DQS PI = 22
7235 00:43:25.445921 [0] MIN Duty = 4876%(X100), DQS PI = 48
7236 00:43:25.448683 [0] AVG Duty = 5016%(X100)
7237 00:43:25.448757
7238 00:43:25.452001 CH0 CLK Duty spec in!! Max-Min= 280%
7239 00:43:25.455890 [DutyScan_Calibration_Flow] ====Done====
7240 00:43:25.455964
7241 00:43:25.458606 [DutyScan_Calibration_Flow] k_type=1
7242 00:43:25.475383
7243 00:43:25.475459 ==DQS 0 ==
7244 00:43:25.478760 Final DQS duty delay cell = -4
7245 00:43:25.481883 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7246 00:43:25.484945 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7247 00:43:25.488449 [-4] AVG Duty = 4891%(X100)
7248 00:43:25.488527
7249 00:43:25.488586 ==DQS 1 ==
7250 00:43:25.491891 Final DQS duty delay cell = 0
7251 00:43:25.494922 [0] MAX Duty = 5187%(X100), DQS PI = 10
7252 00:43:25.498222 [0] MIN Duty = 5031%(X100), DQS PI = 52
7253 00:43:25.501519 [0] AVG Duty = 5109%(X100)
7254 00:43:25.501650
7255 00:43:25.504919 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7256 00:43:25.504982
7257 00:43:25.508643 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7258 00:43:25.511471 [DutyScan_Calibration_Flow] ====Done====
7259 00:43:25.511546
7260 00:43:25.514785 [DutyScan_Calibration_Flow] k_type=3
7261 00:43:25.532606
7262 00:43:25.532682 ==DQM 0 ==
7263 00:43:25.535733 Final DQM duty delay cell = 0
7264 00:43:25.538892 [0] MAX Duty = 5187%(X100), DQS PI = 26
7265 00:43:25.542607 [0] MIN Duty = 4907%(X100), DQS PI = 0
7266 00:43:25.542682 [0] AVG Duty = 5047%(X100)
7267 00:43:25.545823
7268 00:43:25.545890 ==DQM 1 ==
7269 00:43:25.549060 Final DQM duty delay cell = 0
7270 00:43:25.552759 [0] MAX Duty = 5187%(X100), DQS PI = 6
7271 00:43:25.555952 [0] MIN Duty = 5031%(X100), DQS PI = 48
7272 00:43:25.556022 [0] AVG Duty = 5109%(X100)
7273 00:43:25.559230
7274 00:43:25.562452 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7275 00:43:25.562521
7276 00:43:25.565835 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7277 00:43:25.569146 [DutyScan_Calibration_Flow] ====Done====
7278 00:43:25.569211
7279 00:43:25.571821 [DutyScan_Calibration_Flow] k_type=2
7280 00:43:25.589676
7281 00:43:25.589752 ==DQ 0 ==
7282 00:43:25.592929 Final DQ duty delay cell = 0
7283 00:43:25.596263 [0] MAX Duty = 5062%(X100), DQS PI = 26
7284 00:43:25.599458 [0] MIN Duty = 4907%(X100), DQS PI = 0
7285 00:43:25.599533 [0] AVG Duty = 4984%(X100)
7286 00:43:25.602530
7287 00:43:25.602604 ==DQ 1 ==
7288 00:43:25.606306 Final DQ duty delay cell = 0
7289 00:43:25.609690 [0] MAX Duty = 5125%(X100), DQS PI = 6
7290 00:43:25.613004 [0] MIN Duty = 4907%(X100), DQS PI = 34
7291 00:43:25.613097 [0] AVG Duty = 5016%(X100)
7292 00:43:25.613188
7293 00:43:25.616264 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7294 00:43:25.619467
7295 00:43:25.622756 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7296 00:43:25.626129 [DutyScan_Calibration_Flow] ====Done====
7297 00:43:25.626226 ==
7298 00:43:25.629257 Dram Type= 6, Freq= 0, CH_1, rank 0
7299 00:43:25.632500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 00:43:25.632593 ==
7301 00:43:25.636223 [Duty_Offset_Calibration]
7302 00:43:25.636320 B0:1 B1:0 CA:0
7303 00:43:25.636405
7304 00:43:25.639002 [DutyScan_Calibration_Flow] k_type=0
7305 00:43:25.648660
7306 00:43:25.648753 ==CLK 0==
7307 00:43:25.652161 Final CLK duty delay cell = -4
7308 00:43:25.655474 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7309 00:43:25.658807 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7310 00:43:25.662287 [-4] AVG Duty = 4906%(X100)
7311 00:43:25.662381
7312 00:43:25.665392 CH1 CLK Duty spec in!! Max-Min= 125%
7313 00:43:25.668502 [DutyScan_Calibration_Flow] ====Done====
7314 00:43:25.668599
7315 00:43:25.671956 [DutyScan_Calibration_Flow] k_type=1
7316 00:43:25.688574
7317 00:43:25.688651 ==DQS 0 ==
7318 00:43:25.691888 Final DQS duty delay cell = 0
7319 00:43:25.695477 [0] MAX Duty = 5093%(X100), DQS PI = 30
7320 00:43:25.698650 [0] MIN Duty = 4844%(X100), DQS PI = 2
7321 00:43:25.698745 [0] AVG Duty = 4968%(X100)
7322 00:43:25.702160
7323 00:43:25.702227 ==DQS 1 ==
7324 00:43:25.705255 Final DQS duty delay cell = 0
7325 00:43:25.708465 [0] MAX Duty = 5249%(X100), DQS PI = 16
7326 00:43:25.712179 [0] MIN Duty = 4969%(X100), DQS PI = 8
7327 00:43:25.715541 [0] AVG Duty = 5109%(X100)
7328 00:43:25.715606
7329 00:43:25.718909 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7330 00:43:25.718970
7331 00:43:25.722276 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7332 00:43:25.725298 [DutyScan_Calibration_Flow] ====Done====
7333 00:43:25.725359
7334 00:43:25.728688 [DutyScan_Calibration_Flow] k_type=3
7335 00:43:25.745953
7336 00:43:25.746019 ==DQM 0 ==
7337 00:43:25.748692 Final DQM duty delay cell = 0
7338 00:43:25.751999 [0] MAX Duty = 5187%(X100), DQS PI = 10
7339 00:43:25.755274 [0] MIN Duty = 4938%(X100), DQS PI = 48
7340 00:43:25.758999 [0] AVG Duty = 5062%(X100)
7341 00:43:25.759064
7342 00:43:25.759118 ==DQM 1 ==
7343 00:43:25.762161 Final DQM duty delay cell = 0
7344 00:43:25.765742 [0] MAX Duty = 5062%(X100), DQS PI = 18
7345 00:43:25.768738 [0] MIN Duty = 4876%(X100), DQS PI = 52
7346 00:43:25.772130 [0] AVG Duty = 4969%(X100)
7347 00:43:25.772207
7348 00:43:25.775326 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7349 00:43:25.775408
7350 00:43:25.778765 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7351 00:43:25.781928 [DutyScan_Calibration_Flow] ====Done====
7352 00:43:25.782012
7353 00:43:25.785441 [DutyScan_Calibration_Flow] k_type=2
7354 00:43:25.801805
7355 00:43:25.801894 ==DQ 0 ==
7356 00:43:25.804896 Final DQ duty delay cell = -4
7357 00:43:25.808366 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7358 00:43:25.811694 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7359 00:43:25.815291 [-4] AVG Duty = 4953%(X100)
7360 00:43:25.815383
7361 00:43:25.815467 ==DQ 1 ==
7362 00:43:25.818578 Final DQ duty delay cell = 0
7363 00:43:25.821693 [0] MAX Duty = 5125%(X100), DQS PI = 20
7364 00:43:25.824925 [0] MIN Duty = 4938%(X100), DQS PI = 8
7365 00:43:25.825010 [0] AVG Duty = 5031%(X100)
7366 00:43:25.828021
7367 00:43:25.832008 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7368 00:43:25.832095
7369 00:43:25.835368 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7370 00:43:25.838060 [DutyScan_Calibration_Flow] ====Done====
7371 00:43:25.841483 nWR fixed to 30
7372 00:43:25.841595 [ModeRegInit_LP4] CH0 RK0
7373 00:43:25.844944 [ModeRegInit_LP4] CH0 RK1
7374 00:43:25.848163 [ModeRegInit_LP4] CH1 RK0
7375 00:43:25.851390 [ModeRegInit_LP4] CH1 RK1
7376 00:43:25.851476 match AC timing 5
7377 00:43:25.858112 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7378 00:43:25.861444 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7379 00:43:25.864883 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7380 00:43:25.872096 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7381 00:43:25.875202 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7382 00:43:25.875311 [MiockJmeterHQA]
7383 00:43:25.875392
7384 00:43:25.878566 [DramcMiockJmeter] u1RxGatingPI = 0
7385 00:43:25.881569 0 : 4368, 4140
7386 00:43:25.881658 4 : 4254, 4029
7387 00:43:25.881745 8 : 4363, 4138
7388 00:43:25.885093 12 : 4258, 4026
7389 00:43:25.885183 16 : 4257, 4029
7390 00:43:25.888427 20 : 4367, 4140
7391 00:43:25.888522 24 : 4363, 4138
7392 00:43:25.891923 28 : 4253, 4026
7393 00:43:25.892016 32 : 4252, 4027
7394 00:43:25.894820 36 : 4250, 4027
7395 00:43:25.894922 40 : 4253, 4026
7396 00:43:25.895009 44 : 4252, 4030
7397 00:43:25.898166 48 : 4360, 4137
7398 00:43:25.898258 52 : 4250, 4027
7399 00:43:25.901990 56 : 4250, 4027
7400 00:43:25.902117 60 : 4252, 4029
7401 00:43:25.904715 64 : 4252, 4030
7402 00:43:25.904813 68 : 4250, 4027
7403 00:43:25.908311 72 : 4361, 4137
7404 00:43:25.908400 76 : 4361, 4138
7405 00:43:25.908484 80 : 4250, 4026
7406 00:43:25.911266 84 : 4252, 4027
7407 00:43:25.911362 88 : 4250, 108
7408 00:43:25.914976 92 : 4250, 0
7409 00:43:25.915075 96 : 4253, 0
7410 00:43:25.915164 100 : 4361, 0
7411 00:43:25.917863 104 : 4250, 0
7412 00:43:25.917977 108 : 4252, 0
7413 00:43:25.921416 112 : 4250, 0
7414 00:43:25.921510 116 : 4250, 0
7415 00:43:25.921618 120 : 4250, 0
7416 00:43:25.924861 124 : 4250, 0
7417 00:43:25.924957 128 : 4250, 0
7418 00:43:25.927983 132 : 4252, 0
7419 00:43:25.928075 136 : 4361, 0
7420 00:43:25.928160 140 : 4360, 0
7421 00:43:25.931774 144 : 4363, 0
7422 00:43:25.931881 148 : 4360, 0
7423 00:43:25.931966 152 : 4250, 0
7424 00:43:25.934873 156 : 4250, 0
7425 00:43:25.934964 160 : 4250, 0
7426 00:43:25.938140 164 : 4250, 0
7427 00:43:25.938234 168 : 4250, 0
7428 00:43:25.938332 172 : 4249, 0
7429 00:43:25.941249 176 : 4250, 0
7430 00:43:25.941365 180 : 4250, 0
7431 00:43:25.944563 184 : 4252, 0
7432 00:43:25.944658 188 : 4361, 0
7433 00:43:25.944744 192 : 4361, 0
7434 00:43:25.948017 196 : 4363, 0
7435 00:43:25.948175 200 : 4360, 0
7436 00:43:25.951748 204 : 4250, 986
7437 00:43:25.951847 208 : 4250, 4010
7438 00:43:25.951968 212 : 4361, 4138
7439 00:43:25.955028 216 : 4249, 4027
7440 00:43:25.955125 220 : 4250, 4026
7441 00:43:25.958457 224 : 4250, 4027
7442 00:43:25.958556 228 : 4252, 4030
7443 00:43:25.961689 232 : 4250, 4027
7444 00:43:25.961753 236 : 4250, 4026
7445 00:43:25.965156 240 : 4361, 4137
7446 00:43:25.965245 244 : 4250, 4027
7447 00:43:25.968429 248 : 4250, 4027
7448 00:43:25.968516 252 : 4361, 4137
7449 00:43:25.971766 256 : 4250, 4026
7450 00:43:25.971856 260 : 4250, 4027
7451 00:43:25.975057 264 : 4363, 4140
7452 00:43:25.975143 268 : 4250, 4026
7453 00:43:25.975224 272 : 4250, 4026
7454 00:43:25.978403 276 : 4253, 4029
7455 00:43:25.978488 280 : 4252, 4030
7456 00:43:25.981722 284 : 4250, 4026
7457 00:43:25.981788 288 : 4250, 4026
7458 00:43:25.985085 292 : 4361, 4137
7459 00:43:25.985172 296 : 4250, 4027
7460 00:43:25.988394 300 : 4250, 4027
7461 00:43:25.988478 304 : 4361, 4137
7462 00:43:25.991695 308 : 4250, 4006
7463 00:43:25.991784 312 : 4250, 2189
7464 00:43:25.994676 316 : 4361, 12
7465 00:43:25.994777
7466 00:43:25.994854 MIOCK jitter meter ch=0
7467 00:43:25.994930
7468 00:43:25.998290 1T = (316-88) = 228 dly cells
7469 00:43:26.004797 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7470 00:43:26.004872 ==
7471 00:43:26.007857 Dram Type= 6, Freq= 0, CH_0, rank 0
7472 00:43:26.011262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7473 00:43:26.011353 ==
7474 00:43:26.017693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7475 00:43:26.020950 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7476 00:43:26.024202 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7477 00:43:26.031367 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7478 00:43:26.040632 [CA 0] Center 42 (12~73) winsize 62
7479 00:43:26.043876 [CA 1] Center 42 (12~73) winsize 62
7480 00:43:26.047280 [CA 2] Center 37 (8~67) winsize 60
7481 00:43:26.050517 [CA 3] Center 37 (7~67) winsize 61
7482 00:43:26.054201 [CA 4] Center 36 (6~66) winsize 61
7483 00:43:26.057214 [CA 5] Center 35 (6~64) winsize 59
7484 00:43:26.057315
7485 00:43:26.060336 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7486 00:43:26.060437
7487 00:43:26.063738 [CATrainingPosCal] consider 1 rank data
7488 00:43:26.067562 u2DelayCellTimex100 = 285/100 ps
7489 00:43:26.070872 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7490 00:43:26.077308 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7491 00:43:26.080489 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7492 00:43:26.083721 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7493 00:43:26.087166 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7494 00:43:26.090470 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7495 00:43:26.090571
7496 00:43:26.093689 CA PerBit enable=1, Macro0, CA PI delay=35
7497 00:43:26.093754
7498 00:43:26.097092 [CBTSetCACLKResult] CA Dly = 35
7499 00:43:26.100352 CS Dly: 9 (0~40)
7500 00:43:26.103521 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7501 00:43:26.107052 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7502 00:43:26.107139 ==
7503 00:43:26.110006 Dram Type= 6, Freq= 0, CH_0, rank 1
7504 00:43:26.113260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7505 00:43:26.117004 ==
7506 00:43:26.120295 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7507 00:43:26.123750 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7508 00:43:26.130412 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7509 00:43:26.133931 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7510 00:43:26.143772 [CA 0] Center 42 (12~73) winsize 62
7511 00:43:26.146951 [CA 1] Center 42 (12~73) winsize 62
7512 00:43:26.150340 [CA 2] Center 38 (8~68) winsize 61
7513 00:43:26.153751 [CA 3] Center 38 (8~68) winsize 61
7514 00:43:26.157079 [CA 4] Center 36 (6~66) winsize 61
7515 00:43:26.160369 [CA 5] Center 35 (5~65) winsize 61
7516 00:43:26.160476
7517 00:43:26.163750 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7518 00:43:26.163837
7519 00:43:26.167048 [CATrainingPosCal] consider 2 rank data
7520 00:43:26.170476 u2DelayCellTimex100 = 285/100 ps
7521 00:43:26.176766 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7522 00:43:26.180430 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7523 00:43:26.183484 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7524 00:43:26.187098 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7525 00:43:26.190173 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7526 00:43:26.193353 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7527 00:43:26.193442
7528 00:43:26.196661 CA PerBit enable=1, Macro0, CA PI delay=35
7529 00:43:26.196748
7530 00:43:26.199849 [CBTSetCACLKResult] CA Dly = 35
7531 00:43:26.203779 CS Dly: 10 (0~42)
7532 00:43:26.207067 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7533 00:43:26.210354 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7534 00:43:26.210442
7535 00:43:26.213474 ----->DramcWriteLeveling(PI) begin...
7536 00:43:26.213581 ==
7537 00:43:26.217094 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 00:43:26.223706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 00:43:26.223796 ==
7540 00:43:26.226621 Write leveling (Byte 0): 36 => 36
7541 00:43:26.226712 Write leveling (Byte 1): 26 => 26
7542 00:43:26.230301 DramcWriteLeveling(PI) end<-----
7543 00:43:26.230365
7544 00:43:26.230504 ==
7545 00:43:26.233513 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 00:43:26.239843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 00:43:26.239934 ==
7548 00:43:26.243676 [Gating] SW mode calibration
7549 00:43:26.250127 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7550 00:43:26.253467 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7551 00:43:26.260207 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 00:43:26.263573 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 00:43:26.266284 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 00:43:26.272995 1 4 12 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
7555 00:43:26.276328 1 4 16 | B1->B0 | 2424 3535 | 0 1 | (0 0) (1 1)
7556 00:43:26.279598 1 4 20 | B1->B0 | 3333 3535 | 0 0 | (0 0) (0 0)
7557 00:43:26.286324 1 4 24 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7558 00:43:26.289660 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 00:43:26.292895 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7560 00:43:26.299514 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 00:43:26.303336 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7562 00:43:26.306322 1 5 12 | B1->B0 | 3434 2a29 | 1 1 | (1 1) (0 0)
7563 00:43:26.309725 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
7564 00:43:26.316477 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7565 00:43:26.319465 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7566 00:43:26.323467 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 00:43:26.329316 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 00:43:26.333066 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7569 00:43:26.335953 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7570 00:43:26.342679 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7571 00:43:26.346243 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7572 00:43:26.349665 1 6 20 | B1->B0 | 4444 4645 | 0 1 | (0 0) (0 0)
7573 00:43:26.355986 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7574 00:43:26.359508 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 00:43:26.363271 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 00:43:26.369267 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 00:43:26.372519 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7578 00:43:26.375969 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7579 00:43:26.382734 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7580 00:43:26.385894 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7581 00:43:26.389276 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 00:43:26.396105 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 00:43:26.399525 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 00:43:26.402895 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 00:43:26.408995 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 00:43:26.412856 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 00:43:26.416040 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 00:43:26.422450 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 00:43:26.425712 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 00:43:26.429071 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 00:43:26.435981 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 00:43:26.439038 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 00:43:26.442723 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 00:43:26.445943 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7595 00:43:26.452684 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7596 00:43:26.455919 Total UI for P1: 0, mck2ui 16
7597 00:43:26.459379 best dqsien dly found for B0: ( 1, 9, 10)
7598 00:43:26.462719 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7599 00:43:26.466057 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 00:43:26.469433 Total UI for P1: 0, mck2ui 16
7601 00:43:26.472747 best dqsien dly found for B1: ( 1, 9, 18)
7602 00:43:26.475653 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7603 00:43:26.478794 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7604 00:43:26.482670
7605 00:43:26.485628 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7606 00:43:26.488853 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7607 00:43:26.492237 [Gating] SW calibration Done
7608 00:43:26.492330 ==
7609 00:43:26.495662 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 00:43:26.499068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 00:43:26.499156 ==
7612 00:43:26.502378 RX Vref Scan: 0
7613 00:43:26.502442
7614 00:43:26.502497 RX Vref 0 -> 0, step: 1
7615 00:43:26.502549
7616 00:43:26.505754 RX Delay 0 -> 252, step: 8
7617 00:43:26.509088 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7618 00:43:26.512464 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7619 00:43:26.518941 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7620 00:43:26.522255 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7621 00:43:26.525527 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7622 00:43:26.528634 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7623 00:43:26.532058 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7624 00:43:26.538748 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7625 00:43:26.542136 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7626 00:43:26.545406 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7627 00:43:26.548684 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7628 00:43:26.551969 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7629 00:43:26.558491 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7630 00:43:26.561853 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7631 00:43:26.565302 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7632 00:43:26.568295 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7633 00:43:26.568386 ==
7634 00:43:26.571855 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 00:43:26.578411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 00:43:26.578503 ==
7637 00:43:26.578586 DQS Delay:
7638 00:43:26.581931 DQS0 = 0, DQS1 = 0
7639 00:43:26.582022 DQM Delay:
7640 00:43:26.582106 DQM0 = 136, DQM1 = 130
7641 00:43:26.585305 DQ Delay:
7642 00:43:26.588407 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7643 00:43:26.591840 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7644 00:43:26.595174 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7645 00:43:26.598394 DQ12 =131, DQ13 =139, DQ14 =139, DQ15 =135
7646 00:43:26.598483
7647 00:43:26.598564
7648 00:43:26.598681 ==
7649 00:43:26.601578 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 00:43:26.605051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 00:43:26.608739 ==
7652 00:43:26.608806
7653 00:43:26.608861
7654 00:43:26.608914 TX Vref Scan disable
7655 00:43:26.612071 == TX Byte 0 ==
7656 00:43:26.615472 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7657 00:43:26.618287 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7658 00:43:26.621660 == TX Byte 1 ==
7659 00:43:26.624916 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7660 00:43:26.628661 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7661 00:43:26.628747 ==
7662 00:43:26.631946 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 00:43:26.638605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 00:43:26.638676 ==
7665 00:43:26.650015
7666 00:43:26.653349 TX Vref early break, caculate TX vref
7667 00:43:26.656822 TX Vref=16, minBit 3, minWin=22, winSum=377
7668 00:43:26.660259 TX Vref=18, minBit 0, minWin=23, winSum=388
7669 00:43:26.663617 TX Vref=20, minBit 0, minWin=24, winSum=398
7670 00:43:26.666925 TX Vref=22, minBit 0, minWin=24, winSum=408
7671 00:43:26.669884 TX Vref=24, minBit 0, minWin=25, winSum=415
7672 00:43:26.676253 TX Vref=26, minBit 0, minWin=25, winSum=422
7673 00:43:26.679989 TX Vref=28, minBit 1, minWin=24, winSum=425
7674 00:43:26.682942 TX Vref=30, minBit 1, minWin=24, winSum=413
7675 00:43:26.686579 TX Vref=32, minBit 2, minWin=24, winSum=402
7676 00:43:26.693051 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
7677 00:43:26.693143
7678 00:43:26.696333 Final TX Range 0 Vref 26
7679 00:43:26.696428
7680 00:43:26.696510 ==
7681 00:43:26.700252 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 00:43:26.703353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 00:43:26.703447 ==
7684 00:43:26.703535
7685 00:43:26.703615
7686 00:43:26.706466 TX Vref Scan disable
7687 00:43:26.713348 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7688 00:43:26.713448 == TX Byte 0 ==
7689 00:43:26.716357 u2DelayCellOfst[0]=13 cells (4 PI)
7690 00:43:26.719828 u2DelayCellOfst[1]=17 cells (5 PI)
7691 00:43:26.723397 u2DelayCellOfst[2]=13 cells (4 PI)
7692 00:43:26.726604 u2DelayCellOfst[3]=10 cells (3 PI)
7693 00:43:26.729780 u2DelayCellOfst[4]=10 cells (3 PI)
7694 00:43:26.733212 u2DelayCellOfst[5]=0 cells (0 PI)
7695 00:43:26.733280 u2DelayCellOfst[6]=17 cells (5 PI)
7696 00:43:26.736546 u2DelayCellOfst[7]=17 cells (5 PI)
7697 00:43:26.742900 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7698 00:43:26.746246 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7699 00:43:26.746317 == TX Byte 1 ==
7700 00:43:26.749614 u2DelayCellOfst[8]=3 cells (1 PI)
7701 00:43:26.753052 u2DelayCellOfst[9]=0 cells (0 PI)
7702 00:43:26.756380 u2DelayCellOfst[10]=10 cells (3 PI)
7703 00:43:26.759734 u2DelayCellOfst[11]=6 cells (2 PI)
7704 00:43:26.763122 u2DelayCellOfst[12]=10 cells (3 PI)
7705 00:43:26.766555 u2DelayCellOfst[13]=13 cells (4 PI)
7706 00:43:26.769750 u2DelayCellOfst[14]=17 cells (5 PI)
7707 00:43:26.773039 u2DelayCellOfst[15]=10 cells (3 PI)
7708 00:43:26.776343 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7709 00:43:26.779593 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7710 00:43:26.782852 DramC Write-DBI on
7711 00:43:26.782952 ==
7712 00:43:26.786532 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 00:43:26.789666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 00:43:26.789778 ==
7715 00:43:26.789886
7716 00:43:26.789954
7717 00:43:26.792963 TX Vref Scan disable
7718 00:43:26.796281 == TX Byte 0 ==
7719 00:43:26.799448 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7720 00:43:26.803063 == TX Byte 1 ==
7721 00:43:26.806454 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7722 00:43:26.806542 DramC Write-DBI off
7723 00:43:26.806621
7724 00:43:26.809485 [DATLAT]
7725 00:43:26.809605 Freq=1600, CH0 RK0
7726 00:43:26.809664
7727 00:43:26.813139 DATLAT Default: 0xf
7728 00:43:26.813229 0, 0xFFFF, sum = 0
7729 00:43:26.816512 1, 0xFFFF, sum = 0
7730 00:43:26.816604 2, 0xFFFF, sum = 0
7731 00:43:26.819876 3, 0xFFFF, sum = 0
7732 00:43:26.819972 4, 0xFFFF, sum = 0
7733 00:43:26.822676 5, 0xFFFF, sum = 0
7734 00:43:26.822766 6, 0xFFFF, sum = 0
7735 00:43:26.826023 7, 0xFFFF, sum = 0
7736 00:43:26.826089 8, 0xFFFF, sum = 0
7737 00:43:26.829407 9, 0xFFFF, sum = 0
7738 00:43:26.832841 10, 0xFFFF, sum = 0
7739 00:43:26.832908 11, 0xFFFF, sum = 0
7740 00:43:26.836190 12, 0xFFFF, sum = 0
7741 00:43:26.836282 13, 0xFFFF, sum = 0
7742 00:43:26.839590 14, 0x0, sum = 1
7743 00:43:26.839660 15, 0x0, sum = 2
7744 00:43:26.842569 16, 0x0, sum = 3
7745 00:43:26.842636 17, 0x0, sum = 4
7746 00:43:26.842692 best_step = 15
7747 00:43:26.846413
7748 00:43:26.846486 ==
7749 00:43:26.849699 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 00:43:26.852785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 00:43:26.852854 ==
7752 00:43:26.852915 RX Vref Scan: 1
7753 00:43:26.852992
7754 00:43:26.856181 Set Vref Range= 24 -> 127
7755 00:43:26.856244
7756 00:43:26.859503 RX Vref 24 -> 127, step: 1
7757 00:43:26.859564
7758 00:43:26.862957 RX Delay 27 -> 252, step: 4
7759 00:43:26.863044
7760 00:43:26.866238 Set Vref, RX VrefLevel [Byte0]: 24
7761 00:43:26.869491 [Byte1]: 24
7762 00:43:26.869582
7763 00:43:26.872857 Set Vref, RX VrefLevel [Byte0]: 25
7764 00:43:26.876205 [Byte1]: 25
7765 00:43:26.876269
7766 00:43:26.879594 Set Vref, RX VrefLevel [Byte0]: 26
7767 00:43:26.882456 [Byte1]: 26
7768 00:43:26.885870
7769 00:43:26.885946 Set Vref, RX VrefLevel [Byte0]: 27
7770 00:43:26.889179 [Byte1]: 27
7771 00:43:26.893452
7772 00:43:26.893551 Set Vref, RX VrefLevel [Byte0]: 28
7773 00:43:26.897052 [Byte1]: 28
7774 00:43:26.900983
7775 00:43:26.901077 Set Vref, RX VrefLevel [Byte0]: 29
7776 00:43:26.904384 [Byte1]: 29
7777 00:43:26.908397
7778 00:43:26.908466 Set Vref, RX VrefLevel [Byte0]: 30
7779 00:43:26.911812 [Byte1]: 30
7780 00:43:26.916428
7781 00:43:26.916502 Set Vref, RX VrefLevel [Byte0]: 31
7782 00:43:26.919527 [Byte1]: 31
7783 00:43:26.923879
7784 00:43:26.923969 Set Vref, RX VrefLevel [Byte0]: 32
7785 00:43:26.927411 [Byte1]: 32
7786 00:43:26.931146
7787 00:43:26.931235 Set Vref, RX VrefLevel [Byte0]: 33
7788 00:43:26.934805 [Byte1]: 33
7789 00:43:26.938650
7790 00:43:26.938719 Set Vref, RX VrefLevel [Byte0]: 34
7791 00:43:26.942200 [Byte1]: 34
7792 00:43:26.946460
7793 00:43:26.946545 Set Vref, RX VrefLevel [Byte0]: 35
7794 00:43:26.949372 [Byte1]: 35
7795 00:43:26.953636
7796 00:43:26.953721 Set Vref, RX VrefLevel [Byte0]: 36
7797 00:43:26.957490 [Byte1]: 36
7798 00:43:26.961706
7799 00:43:26.961802 Set Vref, RX VrefLevel [Byte0]: 37
7800 00:43:26.964540 [Byte1]: 37
7801 00:43:26.969030
7802 00:43:26.969127 Set Vref, RX VrefLevel [Byte0]: 38
7803 00:43:26.972339 [Byte1]: 38
7804 00:43:26.976338
7805 00:43:26.976434 Set Vref, RX VrefLevel [Byte0]: 39
7806 00:43:26.979594 [Byte1]: 39
7807 00:43:26.984233
7808 00:43:26.984345 Set Vref, RX VrefLevel [Byte0]: 40
7809 00:43:26.987627 [Byte1]: 40
7810 00:43:26.991668
7811 00:43:26.991765 Set Vref, RX VrefLevel [Byte0]: 41
7812 00:43:26.994976 [Byte1]: 41
7813 00:43:26.999127
7814 00:43:26.999225 Set Vref, RX VrefLevel [Byte0]: 42
7815 00:43:27.002253 [Byte1]: 42
7816 00:43:27.006510
7817 00:43:27.006606 Set Vref, RX VrefLevel [Byte0]: 43
7818 00:43:27.009909 [Byte1]: 43
7819 00:43:27.014002
7820 00:43:27.014068 Set Vref, RX VrefLevel [Byte0]: 44
7821 00:43:27.017310 [Byte1]: 44
7822 00:43:27.021873
7823 00:43:27.021938 Set Vref, RX VrefLevel [Byte0]: 45
7824 00:43:27.025107 [Byte1]: 45
7825 00:43:27.028957
7826 00:43:27.029045 Set Vref, RX VrefLevel [Byte0]: 46
7827 00:43:27.032192 [Byte1]: 46
7828 00:43:27.036810
7829 00:43:27.036892 Set Vref, RX VrefLevel [Byte0]: 47
7830 00:43:27.040017 [Byte1]: 47
7831 00:43:27.044337
7832 00:43:27.044402 Set Vref, RX VrefLevel [Byte0]: 48
7833 00:43:27.047477 [Byte1]: 48
7834 00:43:27.051693
7835 00:43:27.051760 Set Vref, RX VrefLevel [Byte0]: 49
7836 00:43:27.055237 [Byte1]: 49
7837 00:43:27.059351
7838 00:43:27.059421 Set Vref, RX VrefLevel [Byte0]: 50
7839 00:43:27.062469 [Byte1]: 50
7840 00:43:27.067131
7841 00:43:27.067239 Set Vref, RX VrefLevel [Byte0]: 51
7842 00:43:27.070281 [Byte1]: 51
7843 00:43:27.074391
7844 00:43:27.074458 Set Vref, RX VrefLevel [Byte0]: 52
7845 00:43:27.077797 [Byte1]: 52
7846 00:43:27.081691
7847 00:43:27.081786 Set Vref, RX VrefLevel [Byte0]: 53
7848 00:43:27.085616 [Byte1]: 53
7849 00:43:27.089658
7850 00:43:27.089752 Set Vref, RX VrefLevel [Byte0]: 54
7851 00:43:27.093025 [Byte1]: 54
7852 00:43:27.097034
7853 00:43:27.097124 Set Vref, RX VrefLevel [Byte0]: 55
7854 00:43:27.100380 [Byte1]: 55
7855 00:43:27.104844
7856 00:43:27.104909 Set Vref, RX VrefLevel [Byte0]: 56
7857 00:43:27.108245 [Byte1]: 56
7858 00:43:27.112161
7859 00:43:27.112251 Set Vref, RX VrefLevel [Byte0]: 57
7860 00:43:27.115551 [Byte1]: 57
7861 00:43:27.119566
7862 00:43:27.119656 Set Vref, RX VrefLevel [Byte0]: 58
7863 00:43:27.122778 [Byte1]: 58
7864 00:43:27.127345
7865 00:43:27.127411 Set Vref, RX VrefLevel [Byte0]: 59
7866 00:43:27.130710 [Byte1]: 59
7867 00:43:27.134534
7868 00:43:27.134622 Set Vref, RX VrefLevel [Byte0]: 60
7869 00:43:27.137670 [Byte1]: 60
7870 00:43:27.142169
7871 00:43:27.142234 Set Vref, RX VrefLevel [Byte0]: 61
7872 00:43:27.145505 [Byte1]: 61
7873 00:43:27.149972
7874 00:43:27.150037 Set Vref, RX VrefLevel [Byte0]: 62
7875 00:43:27.153412 [Byte1]: 62
7876 00:43:27.157159
7877 00:43:27.157247 Set Vref, RX VrefLevel [Byte0]: 63
7878 00:43:27.160502 [Byte1]: 63
7879 00:43:27.164954
7880 00:43:27.165042 Set Vref, RX VrefLevel [Byte0]: 64
7881 00:43:27.168351 [Byte1]: 64
7882 00:43:27.172558
7883 00:43:27.172648 Set Vref, RX VrefLevel [Byte0]: 65
7884 00:43:27.175589 [Byte1]: 65
7885 00:43:27.179689
7886 00:43:27.179764 Set Vref, RX VrefLevel [Byte0]: 66
7887 00:43:27.183045 [Byte1]: 66
7888 00:43:27.187417
7889 00:43:27.187486 Set Vref, RX VrefLevel [Byte0]: 67
7890 00:43:27.190450 [Byte1]: 67
7891 00:43:27.195065
7892 00:43:27.195129 Set Vref, RX VrefLevel [Byte0]: 68
7893 00:43:27.198010 [Byte1]: 68
7894 00:43:27.202511
7895 00:43:27.202602 Set Vref, RX VrefLevel [Byte0]: 69
7896 00:43:27.205960 [Byte1]: 69
7897 00:43:27.210042
7898 00:43:27.210112 Set Vref, RX VrefLevel [Byte0]: 70
7899 00:43:27.213091 [Byte1]: 70
7900 00:43:27.217524
7901 00:43:27.217658 Set Vref, RX VrefLevel [Byte0]: 71
7902 00:43:27.220997 [Byte1]: 71
7903 00:43:27.224919
7904 00:43:27.225009 Set Vref, RX VrefLevel [Byte0]: 72
7905 00:43:27.228404 [Byte1]: 72
7906 00:43:27.232280
7907 00:43:27.232371 Set Vref, RX VrefLevel [Byte0]: 73
7908 00:43:27.235699 [Byte1]: 73
7909 00:43:27.240363
7910 00:43:27.240433 Set Vref, RX VrefLevel [Byte0]: 74
7911 00:43:27.243591 [Byte1]: 74
7912 00:43:27.247952
7913 00:43:27.248041 Final RX Vref Byte 0 = 56 to rank0
7914 00:43:27.251210 Final RX Vref Byte 1 = 61 to rank0
7915 00:43:27.254447 Final RX Vref Byte 0 = 56 to rank1
7916 00:43:27.257734 Final RX Vref Byte 1 = 61 to rank1==
7917 00:43:27.260906 Dram Type= 6, Freq= 0, CH_0, rank 0
7918 00:43:27.267679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7919 00:43:27.267748 ==
7920 00:43:27.267805 DQS Delay:
7921 00:43:27.267863 DQS0 = 0, DQS1 = 0
7922 00:43:27.271070 DQM Delay:
7923 00:43:27.271168 DQM0 = 133, DQM1 = 127
7924 00:43:27.274273 DQ Delay:
7925 00:43:27.277917 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7926 00:43:27.280921 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7927 00:43:27.284171 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7928 00:43:27.287625 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7929 00:43:27.287718
7930 00:43:27.287801
7931 00:43:27.287880
7932 00:43:27.290945 [DramC_TX_OE_Calibration] TA2
7933 00:43:27.294325 Original DQ_B0 (3 6) =30, OEN = 27
7934 00:43:27.297679 Original DQ_B1 (3 6) =30, OEN = 27
7935 00:43:27.300944 24, 0x0, End_B0=24 End_B1=24
7936 00:43:27.301016 25, 0x0, End_B0=25 End_B1=25
7937 00:43:27.304178 26, 0x0, End_B0=26 End_B1=26
7938 00:43:27.307309 27, 0x0, End_B0=27 End_B1=27
7939 00:43:27.310716 28, 0x0, End_B0=28 End_B1=28
7940 00:43:27.310812 29, 0x0, End_B0=29 End_B1=29
7941 00:43:27.314514 30, 0x0, End_B0=30 End_B1=30
7942 00:43:27.317681 31, 0x4545, End_B0=30 End_B1=30
7943 00:43:27.320642 Byte0 end_step=30 best_step=27
7944 00:43:27.324060 Byte1 end_step=30 best_step=27
7945 00:43:27.327456 Byte0 TX OE(2T, 0.5T) = (3, 3)
7946 00:43:27.327524 Byte1 TX OE(2T, 0.5T) = (3, 3)
7947 00:43:27.330947
7948 00:43:27.331031
7949 00:43:27.337723 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7950 00:43:27.340960 CH0 RK0: MR19=303, MR18=2622
7951 00:43:27.347447 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
7952 00:43:27.347515
7953 00:43:27.350591 ----->DramcWriteLeveling(PI) begin...
7954 00:43:27.350656 ==
7955 00:43:27.354262 Dram Type= 6, Freq= 0, CH_0, rank 1
7956 00:43:27.357560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 00:43:27.357650 ==
7958 00:43:27.360985 Write leveling (Byte 0): 35 => 35
7959 00:43:27.364159 Write leveling (Byte 1): 27 => 27
7960 00:43:27.367626 DramcWriteLeveling(PI) end<-----
7961 00:43:27.367687
7962 00:43:27.367740 ==
7963 00:43:27.370928 Dram Type= 6, Freq= 0, CH_0, rank 1
7964 00:43:27.374329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7965 00:43:27.374390 ==
7966 00:43:27.377624 [Gating] SW mode calibration
7967 00:43:27.384132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7968 00:43:27.390722 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7969 00:43:27.393712 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7970 00:43:27.397306 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 00:43:27.403771 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7972 00:43:27.407138 1 4 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7973 00:43:27.410362 1 4 16 | B1->B0 | 3030 3736 | 0 1 | (0 0) (0 0)
7974 00:43:27.417306 1 4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7975 00:43:27.420558 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7976 00:43:27.424017 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7977 00:43:27.430801 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7978 00:43:27.434157 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7979 00:43:27.437345 1 5 8 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7980 00:43:27.444077 1 5 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
7981 00:43:27.447296 1 5 16 | B1->B0 | 3131 2525 | 1 0 | (1 0) (0 0)
7982 00:43:27.450752 1 5 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7983 00:43:27.457562 1 5 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7984 00:43:27.460961 1 5 28 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7985 00:43:27.463790 1 6 0 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7986 00:43:27.470401 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 00:43:27.473786 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7988 00:43:27.477267 1 6 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7989 00:43:27.480587 1 6 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7990 00:43:27.487299 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 00:43:27.490541 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7992 00:43:27.493961 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7993 00:43:27.500568 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 00:43:27.503643 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 00:43:27.507098 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 00:43:27.513634 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 00:43:27.517099 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7998 00:43:27.520242 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 00:43:27.527310 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 00:43:27.530495 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 00:43:27.533253 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 00:43:27.540089 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 00:43:27.543351 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 00:43:27.546670 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 00:43:27.553404 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 00:43:27.556540 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 00:43:27.559898 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 00:43:27.566457 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 00:43:27.570003 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 00:43:27.573470 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 00:43:27.579874 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 00:43:27.583420 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8013 00:43:27.586448 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8014 00:43:27.593033 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 00:43:27.593132 Total UI for P1: 0, mck2ui 16
8016 00:43:27.599817 best dqsien dly found for B0: ( 1, 9, 14)
8017 00:43:27.599911 Total UI for P1: 0, mck2ui 16
8018 00:43:27.603025 best dqsien dly found for B1: ( 1, 9, 14)
8019 00:43:27.609723 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8020 00:43:27.613234 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8021 00:43:27.613328
8022 00:43:27.616400 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8023 00:43:27.619831 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8024 00:43:27.623076 [Gating] SW calibration Done
8025 00:43:27.623143 ==
8026 00:43:27.626238 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 00:43:27.630039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 00:43:27.630111 ==
8029 00:43:27.633364 RX Vref Scan: 0
8030 00:43:27.633453
8031 00:43:27.633534 RX Vref 0 -> 0, step: 1
8032 00:43:27.633651
8033 00:43:27.636602 RX Delay 0 -> 252, step: 8
8034 00:43:27.640009 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8035 00:43:27.646687 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8036 00:43:27.650006 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8037 00:43:27.653287 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8038 00:43:27.656633 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8039 00:43:27.659950 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8040 00:43:27.663173 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8041 00:43:27.670076 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8042 00:43:27.673326 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8043 00:43:27.676582 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8044 00:43:27.679793 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8045 00:43:27.682787 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8046 00:43:27.689681 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8047 00:43:27.693018 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8048 00:43:27.696312 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8049 00:43:27.699584 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8050 00:43:27.699675 ==
8051 00:43:27.702978 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 00:43:27.709931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 00:43:27.710005 ==
8054 00:43:27.710119 DQS Delay:
8055 00:43:27.712694 DQS0 = 0, DQS1 = 0
8056 00:43:27.712756 DQM Delay:
8057 00:43:27.716220 DQM0 = 137, DQM1 = 128
8058 00:43:27.716306 DQ Delay:
8059 00:43:27.719743 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8060 00:43:27.722960 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8061 00:43:27.726220 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8062 00:43:27.729811 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8063 00:43:27.729876
8064 00:43:27.729930
8065 00:43:27.729985 ==
8066 00:43:27.732825 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 00:43:27.739317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 00:43:27.739412 ==
8069 00:43:27.739497
8070 00:43:27.739577
8071 00:43:27.739657 TX Vref Scan disable
8072 00:43:27.742834 == TX Byte 0 ==
8073 00:43:27.746164 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8074 00:43:27.749325 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8075 00:43:27.752663 == TX Byte 1 ==
8076 00:43:27.756412 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8077 00:43:27.759824 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8078 00:43:27.763104 ==
8079 00:43:27.765846 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 00:43:27.769626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 00:43:27.769720 ==
8082 00:43:27.782437
8083 00:43:27.785823 TX Vref early break, caculate TX vref
8084 00:43:27.789472 TX Vref=16, minBit 1, minWin=23, winSum=385
8085 00:43:27.792500 TX Vref=18, minBit 1, minWin=23, winSum=399
8086 00:43:27.796340 TX Vref=20, minBit 1, minWin=23, winSum=404
8087 00:43:27.799549 TX Vref=22, minBit 0, minWin=25, winSum=414
8088 00:43:27.802999 TX Vref=24, minBit 1, minWin=24, winSum=421
8089 00:43:27.809637 TX Vref=26, minBit 1, minWin=25, winSum=424
8090 00:43:27.812966 TX Vref=28, minBit 0, minWin=25, winSum=422
8091 00:43:27.816420 TX Vref=30, minBit 0, minWin=25, winSum=418
8092 00:43:27.819720 TX Vref=32, minBit 0, minWin=25, winSum=412
8093 00:43:27.822875 TX Vref=34, minBit 4, minWin=23, winSum=400
8094 00:43:27.829347 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 26
8095 00:43:27.829441
8096 00:43:27.832744 Final TX Range 0 Vref 26
8097 00:43:27.832833
8098 00:43:27.832915 ==
8099 00:43:27.836004 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 00:43:27.839372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 00:43:27.839460 ==
8102 00:43:27.839541
8103 00:43:27.839619
8104 00:43:27.842626 TX Vref Scan disable
8105 00:43:27.846302 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8106 00:43:27.849234 == TX Byte 0 ==
8107 00:43:27.852649 u2DelayCellOfst[0]=13 cells (4 PI)
8108 00:43:27.855859 u2DelayCellOfst[1]=13 cells (4 PI)
8109 00:43:27.859206 u2DelayCellOfst[2]=10 cells (3 PI)
8110 00:43:27.862532 u2DelayCellOfst[3]=10 cells (3 PI)
8111 00:43:27.865856 u2DelayCellOfst[4]=6 cells (2 PI)
8112 00:43:27.869527 u2DelayCellOfst[5]=0 cells (0 PI)
8113 00:43:27.872622 u2DelayCellOfst[6]=13 cells (4 PI)
8114 00:43:27.872724 u2DelayCellOfst[7]=13 cells (4 PI)
8115 00:43:27.879772 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8116 00:43:27.882715 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8117 00:43:27.882806 == TX Byte 1 ==
8118 00:43:27.886189 u2DelayCellOfst[8]=0 cells (0 PI)
8119 00:43:27.889494 u2DelayCellOfst[9]=0 cells (0 PI)
8120 00:43:27.892935 u2DelayCellOfst[10]=3 cells (1 PI)
8121 00:43:27.896134 u2DelayCellOfst[11]=3 cells (1 PI)
8122 00:43:27.899168 u2DelayCellOfst[12]=6 cells (2 PI)
8123 00:43:27.902273 u2DelayCellOfst[13]=6 cells (2 PI)
8124 00:43:27.905955 u2DelayCellOfst[14]=10 cells (3 PI)
8125 00:43:27.909329 u2DelayCellOfst[15]=6 cells (2 PI)
8126 00:43:27.912539 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8127 00:43:27.915954 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8128 00:43:27.919343 DramC Write-DBI on
8129 00:43:27.919431 ==
8130 00:43:27.922652 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 00:43:27.925954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 00:43:27.926039 ==
8133 00:43:27.926120
8134 00:43:27.926198
8135 00:43:27.929414 TX Vref Scan disable
8136 00:43:27.932610 == TX Byte 0 ==
8137 00:43:27.935926 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8138 00:43:27.939319 == TX Byte 1 ==
8139 00:43:27.942826 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8140 00:43:27.942892 DramC Write-DBI off
8141 00:43:27.942947
8142 00:43:27.946056 [DATLAT]
8143 00:43:27.946146 Freq=1600, CH0 RK1
8144 00:43:27.946226
8145 00:43:27.949486 DATLAT Default: 0xf
8146 00:43:27.949590 0, 0xFFFF, sum = 0
8147 00:43:27.952755 1, 0xFFFF, sum = 0
8148 00:43:27.952816 2, 0xFFFF, sum = 0
8149 00:43:27.956010 3, 0xFFFF, sum = 0
8150 00:43:27.956073 4, 0xFFFF, sum = 0
8151 00:43:27.959408 5, 0xFFFF, sum = 0
8152 00:43:27.959476 6, 0xFFFF, sum = 0
8153 00:43:27.962494 7, 0xFFFF, sum = 0
8154 00:43:27.962580 8, 0xFFFF, sum = 0
8155 00:43:27.965724 9, 0xFFFF, sum = 0
8156 00:43:27.969019 10, 0xFFFF, sum = 0
8157 00:43:27.969120 11, 0xFFFF, sum = 0
8158 00:43:27.972157 12, 0xFFFF, sum = 0
8159 00:43:27.972238 13, 0xFFFF, sum = 0
8160 00:43:27.975930 14, 0x0, sum = 1
8161 00:43:27.976021 15, 0x0, sum = 2
8162 00:43:27.978580 16, 0x0, sum = 3
8163 00:43:27.978668 17, 0x0, sum = 4
8164 00:43:27.978749 best_step = 15
8165 00:43:27.981977
8166 00:43:27.982063 ==
8167 00:43:27.985318 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 00:43:27.988596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 00:43:27.988671 ==
8170 00:43:27.988723 RX Vref Scan: 0
8171 00:43:27.988773
8172 00:43:27.992410 RX Vref 0 -> 0, step: 1
8173 00:43:27.992509
8174 00:43:27.995549 RX Delay 19 -> 252, step: 4
8175 00:43:27.998581 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8176 00:43:28.001880 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8177 00:43:28.008937 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8178 00:43:28.011812 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8179 00:43:28.015612 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8180 00:43:28.018827 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8181 00:43:28.021949 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8182 00:43:28.028794 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8183 00:43:28.031959 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8184 00:43:28.035515 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8185 00:43:28.038578 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8186 00:43:28.041884 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8187 00:43:28.048667 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8188 00:43:28.052074 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8189 00:43:28.055262 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8190 00:43:28.058651 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8191 00:43:28.058740 ==
8192 00:43:28.061929 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 00:43:28.068420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 00:43:28.068543 ==
8195 00:43:28.068647 DQS Delay:
8196 00:43:28.071794 DQS0 = 0, DQS1 = 0
8197 00:43:28.071881 DQM Delay:
8198 00:43:28.071960 DQM0 = 134, DQM1 = 127
8199 00:43:28.075137 DQ Delay:
8200 00:43:28.078379 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8201 00:43:28.082028 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8202 00:43:28.084946 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8203 00:43:28.088760 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8204 00:43:28.088827
8205 00:43:28.088883
8206 00:43:28.088934
8207 00:43:28.092099 [DramC_TX_OE_Calibration] TA2
8208 00:43:28.094939 Original DQ_B0 (3 6) =30, OEN = 27
8209 00:43:28.098222 Original DQ_B1 (3 6) =30, OEN = 27
8210 00:43:28.101506 24, 0x0, End_B0=24 End_B1=24
8211 00:43:28.101596 25, 0x0, End_B0=25 End_B1=25
8212 00:43:28.104870 26, 0x0, End_B0=26 End_B1=26
8213 00:43:28.108088 27, 0x0, End_B0=27 End_B1=27
8214 00:43:28.111537 28, 0x0, End_B0=28 End_B1=28
8215 00:43:28.114903 29, 0x0, End_B0=29 End_B1=29
8216 00:43:28.114992 30, 0x0, End_B0=30 End_B1=30
8217 00:43:28.118109 31, 0x4141, End_B0=30 End_B1=30
8218 00:43:28.121446 Byte0 end_step=30 best_step=27
8219 00:43:28.124790 Byte1 end_step=30 best_step=27
8220 00:43:28.128133 Byte0 TX OE(2T, 0.5T) = (3, 3)
8221 00:43:28.131789 Byte1 TX OE(2T, 0.5T) = (3, 3)
8222 00:43:28.131876
8223 00:43:28.131955
8224 00:43:28.138275 [DQSOSCAuto] RK1, (LSB)MR18= 0x240c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
8225 00:43:28.141496 CH0 RK1: MR19=303, MR18=240C
8226 00:43:28.148250 CH0_RK1: MR19=0x303, MR18=0x240C, DQSOSC=391, MR23=63, INC=24, DEC=16
8227 00:43:28.151368 [RxdqsGatingPostProcess] freq 1600
8228 00:43:28.154851 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8229 00:43:28.157906 best DQS0 dly(2T, 0.5T) = (1, 1)
8230 00:43:28.161384 best DQS1 dly(2T, 0.5T) = (1, 1)
8231 00:43:28.164475 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8232 00:43:28.167836 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8233 00:43:28.171165 best DQS0 dly(2T, 0.5T) = (1, 1)
8234 00:43:28.174478 best DQS1 dly(2T, 0.5T) = (1, 1)
8235 00:43:28.178380 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8236 00:43:28.181272 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8237 00:43:28.184816 Pre-setting of DQS Precalculation
8238 00:43:28.188090 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8239 00:43:28.188166 ==
8240 00:43:28.191169 Dram Type= 6, Freq= 0, CH_1, rank 0
8241 00:43:28.195013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 00:43:28.198238 ==
8243 00:43:28.201527 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8244 00:43:28.204986 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8245 00:43:28.211666 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8246 00:43:28.215017 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8247 00:43:28.225006 [CA 0] Center 41 (12~71) winsize 60
8248 00:43:28.228547 [CA 1] Center 41 (12~71) winsize 60
8249 00:43:28.231939 [CA 2] Center 38 (9~68) winsize 60
8250 00:43:28.234620 [CA 3] Center 37 (9~66) winsize 58
8251 00:43:28.238032 [CA 4] Center 37 (8~67) winsize 60
8252 00:43:28.241295 [CA 5] Center 36 (7~66) winsize 60
8253 00:43:28.241368
8254 00:43:28.244812 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8255 00:43:28.244887
8256 00:43:28.248160 [CATrainingPosCal] consider 1 rank data
8257 00:43:28.251370 u2DelayCellTimex100 = 285/100 ps
8258 00:43:28.254641 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8259 00:43:28.261469 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8260 00:43:28.264802 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8261 00:43:28.268004 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8262 00:43:28.271735 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8263 00:43:28.274678 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8264 00:43:28.274776
8265 00:43:28.278568 CA PerBit enable=1, Macro0, CA PI delay=36
8266 00:43:28.278644
8267 00:43:28.281447 [CBTSetCACLKResult] CA Dly = 36
8268 00:43:28.281570 CS Dly: 10 (0~41)
8269 00:43:28.288188 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8270 00:43:28.291314 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8271 00:43:28.291389 ==
8272 00:43:28.294871 Dram Type= 6, Freq= 0, CH_1, rank 1
8273 00:43:28.297996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 00:43:28.298072 ==
8275 00:43:28.304824 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8276 00:43:28.307778 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8277 00:43:28.314551 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8278 00:43:28.317538 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8279 00:43:28.328089 [CA 0] Center 42 (13~72) winsize 60
8280 00:43:28.331433 [CA 1] Center 43 (14~72) winsize 59
8281 00:43:28.334917 [CA 2] Center 39 (10~69) winsize 60
8282 00:43:28.338342 [CA 3] Center 38 (9~68) winsize 60
8283 00:43:28.341782 [CA 4] Center 39 (9~69) winsize 61
8284 00:43:28.344489 [CA 5] Center 38 (9~68) winsize 60
8285 00:43:28.344564
8286 00:43:28.347917 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8287 00:43:28.347992
8288 00:43:28.351322 [CATrainingPosCal] consider 2 rank data
8289 00:43:28.354611 u2DelayCellTimex100 = 285/100 ps
8290 00:43:28.357906 CA0 delay=42 (13~71),Diff = 5 PI (17 cell)
8291 00:43:28.364659 CA1 delay=42 (14~71),Diff = 5 PI (17 cell)
8292 00:43:28.368089 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8293 00:43:28.371287 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8294 00:43:28.374419 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8295 00:43:28.378124 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8296 00:43:28.378199
8297 00:43:28.381409 CA PerBit enable=1, Macro0, CA PI delay=37
8298 00:43:28.381507
8299 00:43:28.384703 [CBTSetCACLKResult] CA Dly = 37
8300 00:43:28.387998 CS Dly: 11 (0~44)
8301 00:43:28.391480 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8302 00:43:28.394791 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8303 00:43:28.394866
8304 00:43:28.398145 ----->DramcWriteLeveling(PI) begin...
8305 00:43:28.398221 ==
8306 00:43:28.400868 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 00:43:28.408089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 00:43:28.408168 ==
8309 00:43:28.411278 Write leveling (Byte 0): 26 => 26
8310 00:43:28.414210 Write leveling (Byte 1): 28 => 28
8311 00:43:28.414284 DramcWriteLeveling(PI) end<-----
8312 00:43:28.414342
8313 00:43:28.417417 ==
8314 00:43:28.417521 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 00:43:28.424497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 00:43:28.424598 ==
8317 00:43:28.427599 [Gating] SW mode calibration
8318 00:43:28.434206 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8319 00:43:28.437887 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8320 00:43:28.444246 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 00:43:28.447500 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 00:43:28.451160 1 4 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
8323 00:43:28.457566 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8324 00:43:28.460848 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 00:43:28.464850 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 00:43:28.470849 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 00:43:28.474305 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 00:43:28.477675 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 00:43:28.484067 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 00:43:28.487786 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
8331 00:43:28.490881 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
8332 00:43:28.497497 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 00:43:28.501022 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 00:43:28.504410 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 00:43:28.507702 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 00:43:28.514105 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 00:43:28.517414 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 00:43:28.520427 1 6 8 | B1->B0 | 3333 4444 | 0 1 | (0 0) (0 0)
8339 00:43:28.527324 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8340 00:43:28.530318 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 00:43:28.533991 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 00:43:28.540584 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 00:43:28.543879 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 00:43:28.547374 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 00:43:28.554094 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 00:43:28.557421 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8347 00:43:28.560818 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8348 00:43:28.567234 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 00:43:28.570713 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 00:43:28.573707 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 00:43:28.580417 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 00:43:28.583744 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 00:43:28.587325 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 00:43:28.594067 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 00:43:28.597216 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 00:43:28.600499 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 00:43:28.607221 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 00:43:28.610223 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 00:43:28.613513 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 00:43:28.620968 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 00:43:28.623658 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 00:43:28.627590 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8363 00:43:28.630726 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8364 00:43:28.637502 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 00:43:28.640347 Total UI for P1: 0, mck2ui 16
8366 00:43:28.643769 best dqsien dly found for B0: ( 1, 9, 10)
8367 00:43:28.647428 Total UI for P1: 0, mck2ui 16
8368 00:43:28.650830 best dqsien dly found for B1: ( 1, 9, 10)
8369 00:43:28.654040 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8370 00:43:28.656709 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8371 00:43:28.656777
8372 00:43:28.660077 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8373 00:43:28.663452 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8374 00:43:28.666775 [Gating] SW calibration Done
8375 00:43:28.666866 ==
8376 00:43:28.670120 Dram Type= 6, Freq= 0, CH_1, rank 0
8377 00:43:28.673528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 00:43:28.673633 ==
8379 00:43:28.676951 RX Vref Scan: 0
8380 00:43:28.677015
8381 00:43:28.680316 RX Vref 0 -> 0, step: 1
8382 00:43:28.680404
8383 00:43:28.680493 RX Delay 0 -> 252, step: 8
8384 00:43:28.686830 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8385 00:43:28.689930 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8386 00:43:28.693615 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8387 00:43:28.696925 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8388 00:43:28.700281 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8389 00:43:28.706886 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8390 00:43:28.709993 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8391 00:43:28.713474 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8392 00:43:28.716730 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8393 00:43:28.720081 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8394 00:43:28.726567 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8395 00:43:28.729753 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8396 00:43:28.732866 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8397 00:43:28.736384 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8398 00:43:28.739814 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8399 00:43:28.746564 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8400 00:43:28.746635 ==
8401 00:43:28.749701 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 00:43:28.752728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 00:43:28.752834 ==
8404 00:43:28.752916 DQS Delay:
8405 00:43:28.756345 DQS0 = 0, DQS1 = 0
8406 00:43:28.756446 DQM Delay:
8407 00:43:28.759730 DQM0 = 136, DQM1 = 132
8408 00:43:28.759815 DQ Delay:
8409 00:43:28.762825 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8410 00:43:28.766437 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8411 00:43:28.769693 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
8412 00:43:28.772883 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =139
8413 00:43:28.772968
8414 00:43:28.776253
8415 00:43:28.776343 ==
8416 00:43:28.779619 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 00:43:28.783081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 00:43:28.783173 ==
8419 00:43:28.783256
8420 00:43:28.783313
8421 00:43:28.785690 TX Vref Scan disable
8422 00:43:28.785777 == TX Byte 0 ==
8423 00:43:28.792410 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8424 00:43:28.795683 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8425 00:43:28.795770 == TX Byte 1 ==
8426 00:43:28.802386 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8427 00:43:28.805760 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8428 00:43:28.805847 ==
8429 00:43:28.809006 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 00:43:28.812154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 00:43:28.812242 ==
8432 00:43:28.825784
8433 00:43:28.829124 TX Vref early break, caculate TX vref
8434 00:43:28.832371 TX Vref=16, minBit 1, minWin=22, winSum=380
8435 00:43:28.836116 TX Vref=18, minBit 1, minWin=23, winSum=387
8436 00:43:28.839010 TX Vref=20, minBit 0, minWin=24, winSum=398
8437 00:43:28.842496 TX Vref=22, minBit 0, minWin=24, winSum=408
8438 00:43:28.846206 TX Vref=24, minBit 0, minWin=24, winSum=414
8439 00:43:28.852448 TX Vref=26, minBit 1, minWin=25, winSum=424
8440 00:43:28.855606 TX Vref=28, minBit 6, minWin=25, winSum=431
8441 00:43:28.859271 TX Vref=30, minBit 0, minWin=25, winSum=421
8442 00:43:28.862435 TX Vref=32, minBit 2, minWin=24, winSum=410
8443 00:43:28.865453 TX Vref=34, minBit 0, minWin=24, winSum=404
8444 00:43:28.872450 [TxChooseVref] Worse bit 6, Min win 25, Win sum 431, Final Vref 28
8445 00:43:28.872520
8446 00:43:28.875723 Final TX Range 0 Vref 28
8447 00:43:28.875790
8448 00:43:28.875844 ==
8449 00:43:28.878702 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 00:43:28.882563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 00:43:28.882654 ==
8452 00:43:28.882734
8453 00:43:28.882815
8454 00:43:28.885693 TX Vref Scan disable
8455 00:43:28.892326 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8456 00:43:28.892422 == TX Byte 0 ==
8457 00:43:28.895601 u2DelayCellOfst[0]=13 cells (4 PI)
8458 00:43:28.899090 u2DelayCellOfst[1]=10 cells (3 PI)
8459 00:43:28.902431 u2DelayCellOfst[2]=0 cells (0 PI)
8460 00:43:28.905642 u2DelayCellOfst[3]=3 cells (1 PI)
8461 00:43:28.908797 u2DelayCellOfst[4]=6 cells (2 PI)
8462 00:43:28.912351 u2DelayCellOfst[5]=17 cells (5 PI)
8463 00:43:28.915569 u2DelayCellOfst[6]=17 cells (5 PI)
8464 00:43:28.915661 u2DelayCellOfst[7]=3 cells (1 PI)
8465 00:43:28.922246 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8466 00:43:28.925569 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8467 00:43:28.925668 == TX Byte 1 ==
8468 00:43:28.928425 u2DelayCellOfst[8]=0 cells (0 PI)
8469 00:43:28.932336 u2DelayCellOfst[9]=3 cells (1 PI)
8470 00:43:28.935749 u2DelayCellOfst[10]=13 cells (4 PI)
8471 00:43:28.938320 u2DelayCellOfst[11]=3 cells (1 PI)
8472 00:43:28.941652 u2DelayCellOfst[12]=13 cells (4 PI)
8473 00:43:28.945537 u2DelayCellOfst[13]=17 cells (5 PI)
8474 00:43:28.948611 u2DelayCellOfst[14]=17 cells (5 PI)
8475 00:43:28.951815 u2DelayCellOfst[15]=17 cells (5 PI)
8476 00:43:28.955170 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8477 00:43:28.961977 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8478 00:43:28.962070 DramC Write-DBI on
8479 00:43:28.962158 ==
8480 00:43:28.965117 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 00:43:28.968388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 00:43:28.968460 ==
8483 00:43:28.971692
8484 00:43:28.971783
8485 00:43:28.971865 TX Vref Scan disable
8486 00:43:28.975106 == TX Byte 0 ==
8487 00:43:28.978463 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8488 00:43:28.981730 == TX Byte 1 ==
8489 00:43:28.984760 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8490 00:43:28.988276 DramC Write-DBI off
8491 00:43:28.988369
8492 00:43:28.988452 [DATLAT]
8493 00:43:28.988532 Freq=1600, CH1 RK0
8494 00:43:28.988599
8495 00:43:28.991558 DATLAT Default: 0xf
8496 00:43:28.991647 0, 0xFFFF, sum = 0
8497 00:43:28.994893 1, 0xFFFF, sum = 0
8498 00:43:28.995006 2, 0xFFFF, sum = 0
8499 00:43:28.998065 3, 0xFFFF, sum = 0
8500 00:43:29.001652 4, 0xFFFF, sum = 0
8501 00:43:29.001746 5, 0xFFFF, sum = 0
8502 00:43:29.005056 6, 0xFFFF, sum = 0
8503 00:43:29.005149 7, 0xFFFF, sum = 0
8504 00:43:29.008235 8, 0xFFFF, sum = 0
8505 00:43:29.008328 9, 0xFFFF, sum = 0
8506 00:43:29.011500 10, 0xFFFF, sum = 0
8507 00:43:29.011594 11, 0xFFFF, sum = 0
8508 00:43:29.014659 12, 0xFFFF, sum = 0
8509 00:43:29.014751 13, 0xFFFF, sum = 0
8510 00:43:29.018064 14, 0x0, sum = 1
8511 00:43:29.018159 15, 0x0, sum = 2
8512 00:43:29.021467 16, 0x0, sum = 3
8513 00:43:29.021596 17, 0x0, sum = 4
8514 00:43:29.024878 best_step = 15
8515 00:43:29.024947
8516 00:43:29.025000 ==
8517 00:43:29.028102 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 00:43:29.031625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 00:43:29.031717 ==
8520 00:43:29.031798 RX Vref Scan: 1
8521 00:43:29.034844
8522 00:43:29.034937 Set Vref Range= 24 -> 127
8523 00:43:29.035022
8524 00:43:29.038331 RX Vref 24 -> 127, step: 1
8525 00:43:29.038399
8526 00:43:29.041736 RX Delay 27 -> 252, step: 4
8527 00:43:29.041803
8528 00:43:29.045065 Set Vref, RX VrefLevel [Byte0]: 24
8529 00:43:29.048561 [Byte1]: 24
8530 00:43:29.048628
8531 00:43:29.051689 Set Vref, RX VrefLevel [Byte0]: 25
8532 00:43:29.054759 [Byte1]: 25
8533 00:43:29.054870
8534 00:43:29.057877 Set Vref, RX VrefLevel [Byte0]: 26
8535 00:43:29.061299 [Byte1]: 26
8536 00:43:29.065091
8537 00:43:29.065185 Set Vref, RX VrefLevel [Byte0]: 27
8538 00:43:29.068467 [Byte1]: 27
8539 00:43:29.072829
8540 00:43:29.072910 Set Vref, RX VrefLevel [Byte0]: 28
8541 00:43:29.076414 [Byte1]: 28
8542 00:43:29.080320
8543 00:43:29.080414 Set Vref, RX VrefLevel [Byte0]: 29
8544 00:43:29.083683 [Byte1]: 29
8545 00:43:29.087566
8546 00:43:29.087664 Set Vref, RX VrefLevel [Byte0]: 30
8547 00:43:29.090930 [Byte1]: 30
8548 00:43:29.095954
8549 00:43:29.096044 Set Vref, RX VrefLevel [Byte0]: 31
8550 00:43:29.098809 [Byte1]: 31
8551 00:43:29.102883
8552 00:43:29.102976 Set Vref, RX VrefLevel [Byte0]: 32
8553 00:43:29.106238 [Byte1]: 32
8554 00:43:29.110302
8555 00:43:29.110390 Set Vref, RX VrefLevel [Byte0]: 33
8556 00:43:29.113690 [Byte1]: 33
8557 00:43:29.117627
8558 00:43:29.117691 Set Vref, RX VrefLevel [Byte0]: 34
8559 00:43:29.121381 [Byte1]: 34
8560 00:43:29.125753
8561 00:43:29.125840 Set Vref, RX VrefLevel [Byte0]: 35
8562 00:43:29.128894 [Byte1]: 35
8563 00:43:29.132575
8564 00:43:29.132666 Set Vref, RX VrefLevel [Byte0]: 36
8565 00:43:29.136229 [Byte1]: 36
8566 00:43:29.140588
8567 00:43:29.140677 Set Vref, RX VrefLevel [Byte0]: 37
8568 00:43:29.143538 [Byte1]: 37
8569 00:43:29.147720
8570 00:43:29.147810 Set Vref, RX VrefLevel [Byte0]: 38
8571 00:43:29.151210 [Byte1]: 38
8572 00:43:29.155341
8573 00:43:29.155430 Set Vref, RX VrefLevel [Byte0]: 39
8574 00:43:29.159127 [Byte1]: 39
8575 00:43:29.162945
8576 00:43:29.163037 Set Vref, RX VrefLevel [Byte0]: 40
8577 00:43:29.166468 [Byte1]: 40
8578 00:43:29.170291
8579 00:43:29.170397 Set Vref, RX VrefLevel [Byte0]: 41
8580 00:43:29.173708 [Byte1]: 41
8581 00:43:29.178376
8582 00:43:29.178463 Set Vref, RX VrefLevel [Byte0]: 42
8583 00:43:29.181427 [Byte1]: 42
8584 00:43:29.185352
8585 00:43:29.185444 Set Vref, RX VrefLevel [Byte0]: 43
8586 00:43:29.188860 [Byte1]: 43
8587 00:43:29.192839
8588 00:43:29.192929 Set Vref, RX VrefLevel [Byte0]: 44
8589 00:43:29.196236 [Byte1]: 44
8590 00:43:29.200689
8591 00:43:29.200782 Set Vref, RX VrefLevel [Byte0]: 45
8592 00:43:29.204035 [Byte1]: 45
8593 00:43:29.208116
8594 00:43:29.208206 Set Vref, RX VrefLevel [Byte0]: 46
8595 00:43:29.211357 [Byte1]: 46
8596 00:43:29.216106
8597 00:43:29.216203 Set Vref, RX VrefLevel [Byte0]: 47
8598 00:43:29.219309 [Byte1]: 47
8599 00:43:29.223404
8600 00:43:29.223500 Set Vref, RX VrefLevel [Byte0]: 48
8601 00:43:29.226718 [Byte1]: 48
8602 00:43:29.230706
8603 00:43:29.230799 Set Vref, RX VrefLevel [Byte0]: 49
8604 00:43:29.234021 [Byte1]: 49
8605 00:43:29.238514
8606 00:43:29.238606 Set Vref, RX VrefLevel [Byte0]: 50
8607 00:43:29.241678 [Byte1]: 50
8608 00:43:29.245760
8609 00:43:29.245869 Set Vref, RX VrefLevel [Byte0]: 51
8610 00:43:29.248987 [Byte1]: 51
8611 00:43:29.253303
8612 00:43:29.253396 Set Vref, RX VrefLevel [Byte0]: 52
8613 00:43:29.256877 [Byte1]: 52
8614 00:43:29.260823
8615 00:43:29.260915 Set Vref, RX VrefLevel [Byte0]: 53
8616 00:43:29.264567 [Byte1]: 53
8617 00:43:29.268664
8618 00:43:29.268732 Set Vref, RX VrefLevel [Byte0]: 54
8619 00:43:29.272058 [Byte1]: 54
8620 00:43:29.276064
8621 00:43:29.276156 Set Vref, RX VrefLevel [Byte0]: 55
8622 00:43:29.279413 [Byte1]: 55
8623 00:43:29.283495
8624 00:43:29.283587 Set Vref, RX VrefLevel [Byte0]: 56
8625 00:43:29.286952 [Byte1]: 56
8626 00:43:29.290870
8627 00:43:29.290964 Set Vref, RX VrefLevel [Byte0]: 57
8628 00:43:29.294188 [Byte1]: 57
8629 00:43:29.298705
8630 00:43:29.298797 Set Vref, RX VrefLevel [Byte0]: 58
8631 00:43:29.301948 [Byte1]: 58
8632 00:43:29.306192
8633 00:43:29.306286 Set Vref, RX VrefLevel [Byte0]: 59
8634 00:43:29.309623 [Byte1]: 59
8635 00:43:29.313540
8636 00:43:29.313648 Set Vref, RX VrefLevel [Byte0]: 60
8637 00:43:29.316881 [Byte1]: 60
8638 00:43:29.320903
8639 00:43:29.320973 Set Vref, RX VrefLevel [Byte0]: 61
8640 00:43:29.324203 [Byte1]: 61
8641 00:43:29.328940
8642 00:43:29.329006 Set Vref, RX VrefLevel [Byte0]: 62
8643 00:43:29.332283 [Byte1]: 62
8644 00:43:29.336390
8645 00:43:29.336479 Set Vref, RX VrefLevel [Byte0]: 63
8646 00:43:29.339824 [Byte1]: 63
8647 00:43:29.343695
8648 00:43:29.343786 Set Vref, RX VrefLevel [Byte0]: 64
8649 00:43:29.346956 [Byte1]: 64
8650 00:43:29.351517
8651 00:43:29.351608 Set Vref, RX VrefLevel [Byte0]: 65
8652 00:43:29.354810 [Byte1]: 65
8653 00:43:29.358751
8654 00:43:29.358840 Set Vref, RX VrefLevel [Byte0]: 66
8655 00:43:29.362410 [Byte1]: 66
8656 00:43:29.366559
8657 00:43:29.366630 Set Vref, RX VrefLevel [Byte0]: 67
8658 00:43:29.370033 [Byte1]: 67
8659 00:43:29.373924
8660 00:43:29.373994 Set Vref, RX VrefLevel [Byte0]: 68
8661 00:43:29.377284 [Byte1]: 68
8662 00:43:29.381130
8663 00:43:29.381222 Set Vref, RX VrefLevel [Byte0]: 69
8664 00:43:29.385047 [Byte1]: 69
8665 00:43:29.388836
8666 00:43:29.388905 Set Vref, RX VrefLevel [Byte0]: 70
8667 00:43:29.391996 [Byte1]: 70
8668 00:43:29.396648
8669 00:43:29.396726 Set Vref, RX VrefLevel [Byte0]: 71
8670 00:43:29.400040 [Byte1]: 71
8671 00:43:29.404104
8672 00:43:29.404197 Set Vref, RX VrefLevel [Byte0]: 72
8673 00:43:29.407376 [Byte1]: 72
8674 00:43:29.411406
8675 00:43:29.411488 Set Vref, RX VrefLevel [Byte0]: 73
8676 00:43:29.415101 [Byte1]: 73
8677 00:43:29.419004
8678 00:43:29.419094 Set Vref, RX VrefLevel [Byte0]: 74
8679 00:43:29.422438 [Byte1]: 74
8680 00:43:29.426650
8681 00:43:29.426743 Final RX Vref Byte 0 = 58 to rank0
8682 00:43:29.430033 Final RX Vref Byte 1 = 56 to rank0
8683 00:43:29.433367 Final RX Vref Byte 0 = 58 to rank1
8684 00:43:29.436437 Final RX Vref Byte 1 = 56 to rank1==
8685 00:43:29.439852 Dram Type= 6, Freq= 0, CH_1, rank 0
8686 00:43:29.446619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8687 00:43:29.446718 ==
8688 00:43:29.446796 DQS Delay:
8689 00:43:29.446852 DQS0 = 0, DQS1 = 0
8690 00:43:29.449746 DQM Delay:
8691 00:43:29.449812 DQM0 = 134, DQM1 = 131
8692 00:43:29.452884 DQ Delay:
8693 00:43:29.456260 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8694 00:43:29.459782 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8695 00:43:29.463089 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8696 00:43:29.466406 DQ12 =140, DQ13 =138, DQ14 =140, DQ15 =140
8697 00:43:29.466503
8698 00:43:29.466586
8699 00:43:29.466666
8700 00:43:29.470330 [DramC_TX_OE_Calibration] TA2
8701 00:43:29.473263 Original DQ_B0 (3 6) =30, OEN = 27
8702 00:43:29.476874 Original DQ_B1 (3 6) =30, OEN = 27
8703 00:43:29.479864 24, 0x0, End_B0=24 End_B1=24
8704 00:43:29.479933 25, 0x0, End_B0=25 End_B1=25
8705 00:43:29.483338 26, 0x0, End_B0=26 End_B1=26
8706 00:43:29.486546 27, 0x0, End_B0=27 End_B1=27
8707 00:43:29.489915 28, 0x0, End_B0=28 End_B1=28
8708 00:43:29.489988 29, 0x0, End_B0=29 End_B1=29
8709 00:43:29.493027 30, 0x0, End_B0=30 End_B1=30
8710 00:43:29.496953 31, 0x4141, End_B0=30 End_B1=30
8711 00:43:29.499991 Byte0 end_step=30 best_step=27
8712 00:43:29.503359 Byte1 end_step=30 best_step=27
8713 00:43:29.506602 Byte0 TX OE(2T, 0.5T) = (3, 3)
8714 00:43:29.506693 Byte1 TX OE(2T, 0.5T) = (3, 3)
8715 00:43:29.506774
8716 00:43:29.510027
8717 00:43:29.516829 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8718 00:43:29.520149 CH1 RK0: MR19=303, MR18=1623
8719 00:43:29.526841 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8720 00:43:29.526909
8721 00:43:29.530033 ----->DramcWriteLeveling(PI) begin...
8722 00:43:29.530102 ==
8723 00:43:29.533415 Dram Type= 6, Freq= 0, CH_1, rank 1
8724 00:43:29.536644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8725 00:43:29.536710 ==
8726 00:43:29.539850 Write leveling (Byte 0): 25 => 25
8727 00:43:29.543020 Write leveling (Byte 1): 29 => 29
8728 00:43:29.546552 DramcWriteLeveling(PI) end<-----
8729 00:43:29.546618
8730 00:43:29.546672 ==
8731 00:43:29.550031 Dram Type= 6, Freq= 0, CH_1, rank 1
8732 00:43:29.553369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8733 00:43:29.553458 ==
8734 00:43:29.556417 [Gating] SW mode calibration
8735 00:43:29.563124 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8736 00:43:29.569691 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8737 00:43:29.573304 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8738 00:43:29.576358 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8739 00:43:29.583188 1 4 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8740 00:43:29.586166 1 4 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8741 00:43:29.589726 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8742 00:43:29.596702 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8743 00:43:29.599965 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 00:43:29.603092 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 00:43:29.609802 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 00:43:29.613232 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8747 00:43:29.616604 1 5 8 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 1)
8748 00:43:29.622633 1 5 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
8749 00:43:29.625973 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 00:43:29.629324 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 00:43:29.636383 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 00:43:29.639755 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 00:43:29.643039 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 00:43:29.646370 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 00:43:29.652875 1 6 8 | B1->B0 | 3d3d 2424 | 1 0 | (0 0) (0 0)
8756 00:43:29.656200 1 6 12 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
8757 00:43:29.659593 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 00:43:29.666099 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 00:43:29.669311 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 00:43:29.672995 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 00:43:29.679453 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 00:43:29.682681 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8763 00:43:29.685874 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8764 00:43:29.692483 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8765 00:43:29.696335 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8766 00:43:29.699397 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 00:43:29.705998 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 00:43:29.709432 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 00:43:29.713032 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 00:43:29.719160 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 00:43:29.722668 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 00:43:29.726317 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 00:43:29.733148 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 00:43:29.736283 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 00:43:29.739478 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 00:43:29.746156 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 00:43:29.749631 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 00:43:29.752951 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8779 00:43:29.756269 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8780 00:43:29.762932 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8781 00:43:29.766340 Total UI for P1: 0, mck2ui 16
8782 00:43:29.769731 best dqsien dly found for B1: ( 1, 9, 6)
8783 00:43:29.773081 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 00:43:29.776358 Total UI for P1: 0, mck2ui 16
8785 00:43:29.779635 best dqsien dly found for B0: ( 1, 9, 12)
8786 00:43:29.782601 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8787 00:43:29.786163 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8788 00:43:29.786256
8789 00:43:29.789431 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8790 00:43:29.792967 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8791 00:43:29.796242 [Gating] SW calibration Done
8792 00:43:29.796332 ==
8793 00:43:29.799523 Dram Type= 6, Freq= 0, CH_1, rank 1
8794 00:43:29.806075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 00:43:29.806146 ==
8796 00:43:29.806206 RX Vref Scan: 0
8797 00:43:29.806261
8798 00:43:29.809404 RX Vref 0 -> 0, step: 1
8799 00:43:29.809496
8800 00:43:29.812720 RX Delay 0 -> 252, step: 8
8801 00:43:29.815914 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8802 00:43:29.819658 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8803 00:43:29.822464 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8804 00:43:29.825751 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8805 00:43:29.832824 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8806 00:43:29.836025 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8807 00:43:29.839493 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8808 00:43:29.842441 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8809 00:43:29.845580 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8810 00:43:29.852221 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8811 00:43:29.855760 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8812 00:43:29.858869 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8813 00:43:29.862394 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8814 00:43:29.865480 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8815 00:43:29.871937 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8816 00:43:29.875344 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8817 00:43:29.875438 ==
8818 00:43:29.878702 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 00:43:29.882150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 00:43:29.882219 ==
8821 00:43:29.885437 DQS Delay:
8822 00:43:29.885528 DQS0 = 0, DQS1 = 0
8823 00:43:29.885620 DQM Delay:
8824 00:43:29.888556 DQM0 = 136, DQM1 = 133
8825 00:43:29.888649 DQ Delay:
8826 00:43:29.892099 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8827 00:43:29.895118 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8828 00:43:29.901984 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8829 00:43:29.905348 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8830 00:43:29.905443
8831 00:43:29.905528
8832 00:43:29.905617 ==
8833 00:43:29.908761 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 00:43:29.911958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 00:43:29.912050 ==
8836 00:43:29.912133
8837 00:43:29.912216
8838 00:43:29.915253 TX Vref Scan disable
8839 00:43:29.915339 == TX Byte 0 ==
8840 00:43:29.921939 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8841 00:43:29.925292 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8842 00:43:29.928658 == TX Byte 1 ==
8843 00:43:29.931966 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8844 00:43:29.935385 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8845 00:43:29.935477 ==
8846 00:43:29.938688 Dram Type= 6, Freq= 0, CH_1, rank 1
8847 00:43:29.941939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8848 00:43:29.942032 ==
8849 00:43:29.956134
8850 00:43:29.959601 TX Vref early break, caculate TX vref
8851 00:43:29.963173 TX Vref=16, minBit 0, minWin=23, winSum=386
8852 00:43:29.965899 TX Vref=18, minBit 0, minWin=23, winSum=392
8853 00:43:29.969460 TX Vref=20, minBit 0, minWin=24, winSum=403
8854 00:43:29.972507 TX Vref=22, minBit 0, minWin=25, winSum=409
8855 00:43:29.975842 TX Vref=24, minBit 0, minWin=25, winSum=418
8856 00:43:29.982582 TX Vref=26, minBit 0, minWin=25, winSum=426
8857 00:43:29.985832 TX Vref=28, minBit 0, minWin=25, winSum=424
8858 00:43:29.989291 TX Vref=30, minBit 1, minWin=25, winSum=418
8859 00:43:29.992780 TX Vref=32, minBit 0, minWin=24, winSum=410
8860 00:43:29.995886 TX Vref=34, minBit 0, minWin=24, winSum=402
8861 00:43:30.002758 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 26
8862 00:43:30.002857
8863 00:43:30.006102 Final TX Range 0 Vref 26
8864 00:43:30.006198
8865 00:43:30.006283 ==
8866 00:43:30.009338 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 00:43:30.012442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 00:43:30.012538 ==
8869 00:43:30.012621
8870 00:43:30.012701
8871 00:43:30.015706 TX Vref Scan disable
8872 00:43:30.022895 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8873 00:43:30.022988 == TX Byte 0 ==
8874 00:43:30.026308 u2DelayCellOfst[0]=17 cells (5 PI)
8875 00:43:30.028969 u2DelayCellOfst[1]=10 cells (3 PI)
8876 00:43:30.032302 u2DelayCellOfst[2]=0 cells (0 PI)
8877 00:43:30.035723 u2DelayCellOfst[3]=6 cells (2 PI)
8878 00:43:30.039028 u2DelayCellOfst[4]=10 cells (3 PI)
8879 00:43:30.042345 u2DelayCellOfst[5]=17 cells (5 PI)
8880 00:43:30.045514 u2DelayCellOfst[6]=17 cells (5 PI)
8881 00:43:30.045632 u2DelayCellOfst[7]=6 cells (2 PI)
8882 00:43:30.052087 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8883 00:43:30.055434 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8884 00:43:30.055501 == TX Byte 1 ==
8885 00:43:30.059414 u2DelayCellOfst[8]=0 cells (0 PI)
8886 00:43:30.062203 u2DelayCellOfst[9]=3 cells (1 PI)
8887 00:43:30.065670 u2DelayCellOfst[10]=10 cells (3 PI)
8888 00:43:30.068826 u2DelayCellOfst[11]=3 cells (1 PI)
8889 00:43:30.072263 u2DelayCellOfst[12]=13 cells (4 PI)
8890 00:43:30.075361 u2DelayCellOfst[13]=17 cells (5 PI)
8891 00:43:30.078708 u2DelayCellOfst[14]=17 cells (5 PI)
8892 00:43:30.081975 u2DelayCellOfst[15]=17 cells (5 PI)
8893 00:43:30.085316 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8894 00:43:30.092195 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8895 00:43:30.092293 DramC Write-DBI on
8896 00:43:30.092378 ==
8897 00:43:30.095496 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 00:43:30.098759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 00:43:30.101757 ==
8900 00:43:30.101865
8901 00:43:30.101980
8902 00:43:30.102088 TX Vref Scan disable
8903 00:43:30.105467 == TX Byte 0 ==
8904 00:43:30.109156 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8905 00:43:30.112098 == TX Byte 1 ==
8906 00:43:30.115297 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8907 00:43:30.115414 DramC Write-DBI off
8908 00:43:30.118531
8909 00:43:30.118625 [DATLAT]
8910 00:43:30.118708 Freq=1600, CH1 RK1
8911 00:43:30.118792
8912 00:43:30.122157 DATLAT Default: 0xf
8913 00:43:30.122296 0, 0xFFFF, sum = 0
8914 00:43:30.125277 1, 0xFFFF, sum = 0
8915 00:43:30.125375 2, 0xFFFF, sum = 0
8916 00:43:30.128722 3, 0xFFFF, sum = 0
8917 00:43:30.131834 4, 0xFFFF, sum = 0
8918 00:43:30.131930 5, 0xFFFF, sum = 0
8919 00:43:30.135120 6, 0xFFFF, sum = 0
8920 00:43:30.135210 7, 0xFFFF, sum = 0
8921 00:43:30.138338 8, 0xFFFF, sum = 0
8922 00:43:30.138427 9, 0xFFFF, sum = 0
8923 00:43:30.141962 10, 0xFFFF, sum = 0
8924 00:43:30.142052 11, 0xFFFF, sum = 0
8925 00:43:30.145406 12, 0xFFFF, sum = 0
8926 00:43:30.145519 13, 0xFFFF, sum = 0
8927 00:43:30.148587 14, 0x0, sum = 1
8928 00:43:30.148676 15, 0x0, sum = 2
8929 00:43:30.151917 16, 0x0, sum = 3
8930 00:43:30.152023 17, 0x0, sum = 4
8931 00:43:30.155268 best_step = 15
8932 00:43:30.155344
8933 00:43:30.155398 ==
8934 00:43:30.158630 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 00:43:30.161442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 00:43:30.161525 ==
8937 00:43:30.165337 RX Vref Scan: 0
8938 00:43:30.165418
8939 00:43:30.165496 RX Vref 0 -> 0, step: 1
8940 00:43:30.165612
8941 00:43:30.168674 RX Delay 19 -> 252, step: 4
8942 00:43:30.172007 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8943 00:43:30.178630 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8944 00:43:30.181931 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8945 00:43:30.185368 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8946 00:43:30.188680 iDelay=195, Bit 4, Center 128 (79 ~ 178) 100
8947 00:43:30.191974 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8948 00:43:30.198274 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8949 00:43:30.202379 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
8950 00:43:30.204830 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8951 00:43:30.208790 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8952 00:43:30.212016 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8953 00:43:30.215320 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8954 00:43:30.221953 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8955 00:43:30.225315 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8956 00:43:30.228753 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8957 00:43:30.232084 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8958 00:43:30.232175 ==
8959 00:43:30.235363 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 00:43:30.242058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 00:43:30.242150 ==
8962 00:43:30.242234 DQS Delay:
8963 00:43:30.245052 DQS0 = 0, DQS1 = 0
8964 00:43:30.245141 DQM Delay:
8965 00:43:30.245223 DQM0 = 133, DQM1 = 130
8966 00:43:30.248581 DQ Delay:
8967 00:43:30.252101 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8968 00:43:30.255058 DQ4 =128, DQ5 =146, DQ6 =144, DQ7 =132
8969 00:43:30.258391 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8970 00:43:30.261955 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8971 00:43:30.262023
8972 00:43:30.262079
8973 00:43:30.262131
8974 00:43:30.265103 [DramC_TX_OE_Calibration] TA2
8975 00:43:30.268785 Original DQ_B0 (3 6) =30, OEN = 27
8976 00:43:30.271802 Original DQ_B1 (3 6) =30, OEN = 27
8977 00:43:30.275060 24, 0x0, End_B0=24 End_B1=24
8978 00:43:30.275137 25, 0x0, End_B0=25 End_B1=25
8979 00:43:30.278626 26, 0x0, End_B0=26 End_B1=26
8980 00:43:30.281853 27, 0x0, End_B0=27 End_B1=27
8981 00:43:30.284994 28, 0x0, End_B0=28 End_B1=28
8982 00:43:30.288263 29, 0x0, End_B0=29 End_B1=29
8983 00:43:30.288360 30, 0x0, End_B0=30 End_B1=30
8984 00:43:30.291667 31, 0x4141, End_B0=30 End_B1=30
8985 00:43:30.295057 Byte0 end_step=30 best_step=27
8986 00:43:30.298364 Byte1 end_step=30 best_step=27
8987 00:43:30.301511 Byte0 TX OE(2T, 0.5T) = (3, 3)
8988 00:43:30.304793 Byte1 TX OE(2T, 0.5T) = (3, 3)
8989 00:43:30.304873
8990 00:43:30.305009
8991 00:43:30.311833 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
8992 00:43:30.314777 CH1 RK1: MR19=303, MR18=2409
8993 00:43:30.321289 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
8994 00:43:30.324619 [RxdqsGatingPostProcess] freq 1600
8995 00:43:30.327937 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8996 00:43:30.331240 best DQS0 dly(2T, 0.5T) = (1, 1)
8997 00:43:30.334569 best DQS1 dly(2T, 0.5T) = (1, 1)
8998 00:43:30.337893 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8999 00:43:30.341314 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9000 00:43:30.345287 best DQS0 dly(2T, 0.5T) = (1, 1)
9001 00:43:30.348593 best DQS1 dly(2T, 0.5T) = (1, 1)
9002 00:43:30.351662 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9003 00:43:30.354872 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9004 00:43:30.358072 Pre-setting of DQS Precalculation
9005 00:43:30.361616 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9006 00:43:30.368268 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9007 00:43:30.374844 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9008 00:43:30.374920
9009 00:43:30.378265
9010 00:43:30.378335 [Calibration Summary] 3200 Mbps
9011 00:43:30.381590 CH 0, Rank 0
9012 00:43:30.381670 SW Impedance : PASS
9013 00:43:30.384772 DUTY Scan : NO K
9014 00:43:30.388194 ZQ Calibration : PASS
9015 00:43:30.388284 Jitter Meter : NO K
9016 00:43:30.391692 CBT Training : PASS
9017 00:43:30.394867 Write leveling : PASS
9018 00:43:30.394937 RX DQS gating : PASS
9019 00:43:30.398319 RX DQ/DQS(RDDQC) : PASS
9020 00:43:30.401683 TX DQ/DQS : PASS
9021 00:43:30.401785 RX DATLAT : PASS
9022 00:43:30.405024 RX DQ/DQS(Engine): PASS
9023 00:43:30.408344 TX OE : PASS
9024 00:43:30.408437 All Pass.
9025 00:43:30.408526
9026 00:43:30.408609 CH 0, Rank 1
9027 00:43:30.411331 SW Impedance : PASS
9028 00:43:30.414837 DUTY Scan : NO K
9029 00:43:30.414931 ZQ Calibration : PASS
9030 00:43:30.418378 Jitter Meter : NO K
9031 00:43:30.418471 CBT Training : PASS
9032 00:43:30.421503 Write leveling : PASS
9033 00:43:30.424885 RX DQS gating : PASS
9034 00:43:30.424979 RX DQ/DQS(RDDQC) : PASS
9035 00:43:30.428254 TX DQ/DQS : PASS
9036 00:43:30.431395 RX DATLAT : PASS
9037 00:43:30.431463 RX DQ/DQS(Engine): PASS
9038 00:43:30.434840 TX OE : PASS
9039 00:43:30.434934 All Pass.
9040 00:43:30.435018
9041 00:43:30.438052 CH 1, Rank 0
9042 00:43:30.438120 SW Impedance : PASS
9043 00:43:30.441443 DUTY Scan : NO K
9044 00:43:30.444630 ZQ Calibration : PASS
9045 00:43:30.444717 Jitter Meter : NO K
9046 00:43:30.447981 CBT Training : PASS
9047 00:43:30.451344 Write leveling : PASS
9048 00:43:30.451412 RX DQS gating : PASS
9049 00:43:30.454598 RX DQ/DQS(RDDQC) : PASS
9050 00:43:30.457694 TX DQ/DQS : PASS
9051 00:43:30.457759 RX DATLAT : PASS
9052 00:43:30.461559 RX DQ/DQS(Engine): PASS
9053 00:43:30.464805 TX OE : PASS
9054 00:43:30.464894 All Pass.
9055 00:43:30.464973
9056 00:43:30.465054 CH 1, Rank 1
9057 00:43:30.468157 SW Impedance : PASS
9058 00:43:30.471573 DUTY Scan : NO K
9059 00:43:30.471648 ZQ Calibration : PASS
9060 00:43:30.474854 Jitter Meter : NO K
9061 00:43:30.474928 CBT Training : PASS
9062 00:43:30.478108 Write leveling : PASS
9063 00:43:30.481402 RX DQS gating : PASS
9064 00:43:30.481496 RX DQ/DQS(RDDQC) : PASS
9065 00:43:30.484731 TX DQ/DQS : PASS
9066 00:43:30.487984 RX DATLAT : PASS
9067 00:43:30.488054 RX DQ/DQS(Engine): PASS
9068 00:43:30.491415 TX OE : PASS
9069 00:43:30.491510 All Pass.
9070 00:43:30.491592
9071 00:43:30.494798 DramC Write-DBI on
9072 00:43:30.498016 PER_BANK_REFRESH: Hybrid Mode
9073 00:43:30.498083 TX_TRACKING: ON
9074 00:43:30.507599 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9075 00:43:30.514191 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9076 00:43:30.521061 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9077 00:43:30.527838 [FAST_K] Save calibration result to emmc
9078 00:43:30.527911 sync common calibartion params.
9079 00:43:30.530938 sync cbt_mode0:1, 1:1
9080 00:43:30.534102 dram_init: ddr_geometry: 2
9081 00:43:30.534195 dram_init: ddr_geometry: 2
9082 00:43:30.537660 dram_init: ddr_geometry: 2
9083 00:43:30.541013 0:dram_rank_size:100000000
9084 00:43:30.544321 1:dram_rank_size:100000000
9085 00:43:30.547602 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9086 00:43:30.550746 DFS_SHUFFLE_HW_MODE: ON
9087 00:43:30.554282 dramc_set_vcore_voltage set vcore to 725000
9088 00:43:30.557714 Read voltage for 1600, 0
9089 00:43:30.557795 Vio18 = 0
9090 00:43:30.557867 Vcore = 725000
9091 00:43:30.560740 Vdram = 0
9092 00:43:30.560817 Vddq = 0
9093 00:43:30.560894 Vmddr = 0
9094 00:43:30.564003 switch to 3200 Mbps bootup
9095 00:43:30.567678 [DramcRunTimeConfig]
9096 00:43:30.567772 PHYPLL
9097 00:43:30.567857 DPM_CONTROL_AFTERK: ON
9098 00:43:30.571295 PER_BANK_REFRESH: ON
9099 00:43:30.574299 REFRESH_OVERHEAD_REDUCTION: ON
9100 00:43:30.574370 CMD_PICG_NEW_MODE: OFF
9101 00:43:30.577704 XRTWTW_NEW_MODE: ON
9102 00:43:30.581004 XRTRTR_NEW_MODE: ON
9103 00:43:30.581072 TX_TRACKING: ON
9104 00:43:30.584312 RDSEL_TRACKING: OFF
9105 00:43:30.584378 DQS Precalculation for DVFS: ON
9106 00:43:30.587685 RX_TRACKING: OFF
9107 00:43:30.587774 HW_GATING DBG: ON
9108 00:43:30.591017 ZQCS_ENABLE_LP4: ON
9109 00:43:30.591111 RX_PICG_NEW_MODE: ON
9110 00:43:30.594410 TX_PICG_NEW_MODE: ON
9111 00:43:30.597824 ENABLE_RX_DCM_DPHY: ON
9112 00:43:30.601033 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9113 00:43:30.601101 DUMMY_READ_FOR_TRACKING: OFF
9114 00:43:30.604488 !!! SPM_CONTROL_AFTERK: OFF
9115 00:43:30.607782 !!! SPM could not control APHY
9116 00:43:30.610506 IMPEDANCE_TRACKING: ON
9117 00:43:30.610569 TEMP_SENSOR: ON
9118 00:43:30.610643 HW_SAVE_FOR_SR: OFF
9119 00:43:30.614327 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9120 00:43:30.620861 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9121 00:43:30.620928 Read ODT Tracking: ON
9122 00:43:30.624145 Refresh Rate DeBounce: ON
9123 00:43:30.624212 DFS_NO_QUEUE_FLUSH: ON
9124 00:43:30.627326 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9125 00:43:30.630684 ENABLE_DFS_RUNTIME_MRW: OFF
9126 00:43:30.634042 DDR_RESERVE_NEW_MODE: ON
9127 00:43:30.634130 MR_CBT_SWITCH_FREQ: ON
9128 00:43:30.637435 =========================
9129 00:43:30.656663 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9130 00:43:30.660235 dram_init: ddr_geometry: 2
9131 00:43:30.678455 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9132 00:43:30.681663 dram_init: dram init end (result: 0)
9133 00:43:30.688235 DRAM-K: Full calibration passed in 24440 msecs
9134 00:43:30.691374 MRC: failed to locate region type 0.
9135 00:43:30.691472 DRAM rank0 size:0x100000000,
9136 00:43:30.695108 DRAM rank1 size=0x100000000
9137 00:43:30.704777 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9138 00:43:30.711851 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9139 00:43:30.718707 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9140 00:43:30.725268 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9141 00:43:30.727957 DRAM rank0 size:0x100000000,
9142 00:43:30.731795 DRAM rank1 size=0x100000000
9143 00:43:30.731864 CBMEM:
9144 00:43:30.735228 IMD: root @ 0xfffff000 254 entries.
9145 00:43:30.738532 IMD: root @ 0xffffec00 62 entries.
9146 00:43:30.741309 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9147 00:43:30.744629 WARNING: RO_VPD is uninitialized or empty.
9148 00:43:30.751251 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9149 00:43:30.758496 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9150 00:43:30.771533 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9151 00:43:30.782252 BS: romstage times (exec / console): total (unknown) / 23975 ms
9152 00:43:30.782332
9153 00:43:30.782393
9154 00:43:30.792632 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9155 00:43:30.795966 ARM64: Exception handlers installed.
9156 00:43:30.799222 ARM64: Testing exception
9157 00:43:30.802278 ARM64: Done test exception
9158 00:43:30.802347 Enumerating buses...
9159 00:43:30.805937 Show all devs... Before device enumeration.
9160 00:43:30.809258 Root Device: enabled 1
9161 00:43:30.812561 CPU_CLUSTER: 0: enabled 1
9162 00:43:30.812635 CPU: 00: enabled 1
9163 00:43:30.815571 Compare with tree...
9164 00:43:30.815659 Root Device: enabled 1
9165 00:43:30.818885 CPU_CLUSTER: 0: enabled 1
9166 00:43:30.822232 CPU: 00: enabled 1
9167 00:43:30.822300 Root Device scanning...
9168 00:43:30.825764 scan_static_bus for Root Device
9169 00:43:30.828818 CPU_CLUSTER: 0 enabled
9170 00:43:30.832633 scan_static_bus for Root Device done
9171 00:43:30.835832 scan_bus: bus Root Device finished in 8 msecs
9172 00:43:30.835920 done
9173 00:43:30.842102 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9174 00:43:30.845775 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9175 00:43:30.852465 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9176 00:43:30.855990 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9177 00:43:30.859341 Allocating resources...
9178 00:43:30.862739 Reading resources...
9179 00:43:30.866144 Root Device read_resources bus 0 link: 0
9180 00:43:30.866212 DRAM rank0 size:0x100000000,
9181 00:43:30.869199 DRAM rank1 size=0x100000000
9182 00:43:30.872555 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9183 00:43:30.875934 CPU: 00 missing read_resources
9184 00:43:30.879061 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9185 00:43:30.885503 Root Device read_resources bus 0 link: 0 done
9186 00:43:30.885641 Done reading resources.
9187 00:43:30.892024 Show resources in subtree (Root Device)...After reading.
9188 00:43:30.895883 Root Device child on link 0 CPU_CLUSTER: 0
9189 00:43:30.899091 CPU_CLUSTER: 0 child on link 0 CPU: 00
9190 00:43:30.908585 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9191 00:43:30.908687 CPU: 00
9192 00:43:30.912063 Root Device assign_resources, bus 0 link: 0
9193 00:43:30.915474 CPU_CLUSTER: 0 missing set_resources
9194 00:43:30.918937 Root Device assign_resources, bus 0 link: 0 done
9195 00:43:30.921980 Done setting resources.
9196 00:43:30.928619 Show resources in subtree (Root Device)...After assigning values.
9197 00:43:30.931882 Root Device child on link 0 CPU_CLUSTER: 0
9198 00:43:30.935124 CPU_CLUSTER: 0 child on link 0 CPU: 00
9199 00:43:30.945462 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9200 00:43:30.945561 CPU: 00
9201 00:43:30.948947 Done allocating resources.
9202 00:43:30.951753 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9203 00:43:30.955073 Enabling resources...
9204 00:43:30.955161 done.
9205 00:43:30.961830 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9206 00:43:30.961922 Initializing devices...
9207 00:43:30.965242 Root Device init
9208 00:43:30.965331 init hardware done!
9209 00:43:30.968301 0x00000018: ctrlr->caps
9210 00:43:30.971832 52.000 MHz: ctrlr->f_max
9211 00:43:30.971935 0.400 MHz: ctrlr->f_min
9212 00:43:30.975038 0x40ff8080: ctrlr->voltages
9213 00:43:30.975119 sclk: 390625
9214 00:43:30.978842 Bus Width = 1
9215 00:43:30.978911 sclk: 390625
9216 00:43:30.982159 Bus Width = 1
9217 00:43:30.982226 Early init status = 3
9218 00:43:30.988448 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9219 00:43:30.991688 in-header: 03 fc 00 00 01 00 00 00
9220 00:43:30.991782 in-data: 00
9221 00:43:30.998120 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9222 00:43:31.002650 in-header: 03 fd 00 00 00 00 00 00
9223 00:43:31.005931 in-data:
9224 00:43:31.009282 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9225 00:43:31.013252 in-header: 03 fc 00 00 01 00 00 00
9226 00:43:31.016591 in-data: 00
9227 00:43:31.019976 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9228 00:43:31.025322 in-header: 03 fd 00 00 00 00 00 00
9229 00:43:31.029145 in-data:
9230 00:43:31.032563 [SSUSB] Setting up USB HOST controller...
9231 00:43:31.035228 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9232 00:43:31.039050 [SSUSB] phy power-on done.
9233 00:43:31.042355 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9234 00:43:31.048883 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9235 00:43:31.052299 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9236 00:43:31.058791 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9237 00:43:31.065390 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9238 00:43:31.071787 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9239 00:43:31.078518 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9240 00:43:31.085414 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9241 00:43:31.088885 SPM: binary array size = 0x9dc
9242 00:43:31.092051 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9243 00:43:31.098599 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9244 00:43:31.105287 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9245 00:43:31.108698 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9246 00:43:31.115454 configure_display: Starting display init
9247 00:43:31.148691 anx7625_power_on_init: Init interface.
9248 00:43:31.151907 anx7625_disable_pd_protocol: Disabled PD feature.
9249 00:43:31.155286 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9250 00:43:31.183499 anx7625_start_dp_work: Secure OCM version=00
9251 00:43:31.186727 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9252 00:43:31.201304 sp_tx_get_edid_block: EDID Block = 1
9253 00:43:31.303913 Extracted contents:
9254 00:43:31.307337 header: 00 ff ff ff ff ff ff 00
9255 00:43:31.310649 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9256 00:43:31.314024 version: 01 04
9257 00:43:31.317279 basic params: 95 1f 11 78 0a
9258 00:43:31.320649 chroma info: 76 90 94 55 54 90 27 21 50 54
9259 00:43:31.323821 established: 00 00 00
9260 00:43:31.330905 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9261 00:43:31.334036 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9262 00:43:31.340780 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9263 00:43:31.346960 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9264 00:43:31.353698 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9265 00:43:31.357095 extensions: 00
9266 00:43:31.357161 checksum: fb
9267 00:43:31.357216
9268 00:43:31.360573 Manufacturer: IVO Model 57d Serial Number 0
9269 00:43:31.364140 Made week 0 of 2020
9270 00:43:31.364207 EDID version: 1.4
9271 00:43:31.367095 Digital display
9272 00:43:31.370652 6 bits per primary color channel
9273 00:43:31.370744 DisplayPort interface
9274 00:43:31.373591 Maximum image size: 31 cm x 17 cm
9275 00:43:31.376988 Gamma: 220%
9276 00:43:31.377095 Check DPMS levels
9277 00:43:31.380495 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9278 00:43:31.383961 First detailed timing is preferred timing
9279 00:43:31.386980 Established timings supported:
9280 00:43:31.390525 Standard timings supported:
9281 00:43:31.390609 Detailed timings
9282 00:43:31.396772 Hex of detail: 383680a07038204018303c0035ae10000019
9283 00:43:31.400713 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9284 00:43:31.406629 0780 0798 07c8 0820 hborder 0
9285 00:43:31.410624 0438 043b 0447 0458 vborder 0
9286 00:43:31.413395 -hsync -vsync
9287 00:43:31.413463 Did detailed timing
9288 00:43:31.416660 Hex of detail: 000000000000000000000000000000000000
9289 00:43:31.419999 Manufacturer-specified data, tag 0
9290 00:43:31.426477 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9291 00:43:31.426557 ASCII string: InfoVision
9292 00:43:31.433612 Hex of detail: 000000fe00523134304e574635205248200a
9293 00:43:31.436785 ASCII string: R140NWF5 RH
9294 00:43:31.436858 Checksum
9295 00:43:31.436932 Checksum: 0xfb (valid)
9296 00:43:31.443721 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9297 00:43:31.447057 DSI data_rate: 832800000 bps
9298 00:43:31.450357 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9299 00:43:31.457002 anx7625_parse_edid: pixelclock(138800).
9300 00:43:31.460270 hactive(1920), hsync(48), hfp(24), hbp(88)
9301 00:43:31.463504 vactive(1080), vsync(12), vfp(3), vbp(17)
9302 00:43:31.466619 anx7625_dsi_config: config dsi.
9303 00:43:31.473295 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9304 00:43:31.485745 anx7625_dsi_config: success to config DSI
9305 00:43:31.489070 anx7625_dp_start: MIPI phy setup OK.
9306 00:43:31.492543 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9307 00:43:31.496171 mtk_ddp_mode_set invalid vrefresh 60
9308 00:43:31.499100 main_disp_path_setup
9309 00:43:31.499188 ovl_layer_smi_id_en
9310 00:43:31.502431 ovl_layer_smi_id_en
9311 00:43:31.502524 ccorr_config
9312 00:43:31.502606 aal_config
9313 00:43:31.506180 gamma_config
9314 00:43:31.506267 postmask_config
9315 00:43:31.509214 dither_config
9316 00:43:31.512513 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9317 00:43:31.519110 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9318 00:43:31.522484 Root Device init finished in 554 msecs
9319 00:43:31.522579 CPU_CLUSTER: 0 init
9320 00:43:31.532629 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9321 00:43:31.535966 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9322 00:43:31.539310 APU_MBOX 0x190000b0 = 0x10001
9323 00:43:31.542479 APU_MBOX 0x190001b0 = 0x10001
9324 00:43:31.546207 APU_MBOX 0x190005b0 = 0x10001
9325 00:43:31.548991 APU_MBOX 0x190006b0 = 0x10001
9326 00:43:31.552346 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9327 00:43:31.564780 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9328 00:43:31.577610 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9329 00:43:31.584164 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9330 00:43:31.595752 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9331 00:43:31.604436 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9332 00:43:31.608437 CPU_CLUSTER: 0 init finished in 81 msecs
9333 00:43:31.611152 Devices initialized
9334 00:43:31.614632 Show all devs... After init.
9335 00:43:31.614705 Root Device: enabled 1
9336 00:43:31.617828 CPU_CLUSTER: 0: enabled 1
9337 00:43:31.621512 CPU: 00: enabled 1
9338 00:43:31.624302 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9339 00:43:31.628130 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9340 00:43:31.630915 ELOG: NV offset 0x57f000 size 0x1000
9341 00:43:31.637786 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9342 00:43:31.644532 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9343 00:43:31.647702 ELOG: Event(17) added with size 13 at 2024-06-16 00:43:31 UTC
9344 00:43:31.651399 out: cmd=0x121: 03 db 21 01 00 00 00 00
9345 00:43:31.654741 in-header: 03 bd 00 00 2c 00 00 00
9346 00:43:31.668376 in-data: 80 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9347 00:43:31.674983 ELOG: Event(A1) added with size 10 at 2024-06-16 00:43:31 UTC
9348 00:43:31.681440 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9349 00:43:31.688104 ELOG: Event(A0) added with size 9 at 2024-06-16 00:43:31 UTC
9350 00:43:31.692040 elog_add_boot_reason: Logged dev mode boot
9351 00:43:31.695230 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9352 00:43:31.698503 Finalize devices...
9353 00:43:31.698571 Devices finalized
9354 00:43:31.705159 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9355 00:43:31.708478 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9356 00:43:31.711909 in-header: 03 07 00 00 08 00 00 00
9357 00:43:31.715320 in-data: aa e4 47 04 13 02 00 00
9358 00:43:31.715386 Chrome EC: UHEPI supported
9359 00:43:31.721987 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9360 00:43:31.725456 in-header: 03 a9 00 00 08 00 00 00
9361 00:43:31.728671 in-data: 84 60 60 08 00 00 00 00
9362 00:43:31.735600 ELOG: Event(91) added with size 10 at 2024-06-16 00:43:31 UTC
9363 00:43:31.738759 Chrome EC: clear events_b mask to 0x0000000020004000
9364 00:43:31.745342 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9365 00:43:31.749740 in-header: 03 fd 00 00 00 00 00 00
9366 00:43:31.753310 in-data:
9367 00:43:31.756371 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9368 00:43:31.759806 Writing coreboot table at 0xffe64000
9369 00:43:31.763202 0. 000000000010a000-0000000000113fff: RAMSTAGE
9370 00:43:31.769648 1. 0000000040000000-00000000400fffff: RAM
9371 00:43:31.773051 2. 0000000040100000-000000004032afff: RAMSTAGE
9372 00:43:31.776408 3. 000000004032b000-00000000545fffff: RAM
9373 00:43:31.779572 4. 0000000054600000-000000005465ffff: BL31
9374 00:43:31.782688 5. 0000000054660000-00000000ffe63fff: RAM
9375 00:43:31.789337 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9376 00:43:31.792598 7. 0000000100000000-000000023fffffff: RAM
9377 00:43:31.795995 Passing 5 GPIOs to payload:
9378 00:43:31.799685 NAME | PORT | POLARITY | VALUE
9379 00:43:31.806022 EC in RW | 0x000000aa | low | undefined
9380 00:43:31.809297 EC interrupt | 0x00000005 | low | undefined
9381 00:43:31.812675 TPM interrupt | 0x000000ab | high | undefined
9382 00:43:31.819374 SD card detect | 0x00000011 | high | undefined
9383 00:43:31.822646 speaker enable | 0x00000093 | high | undefined
9384 00:43:31.826023 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9385 00:43:31.829268 in-header: 03 f9 00 00 02 00 00 00
9386 00:43:31.832632 in-data: 02 00
9387 00:43:31.835938 ADC[4]: Raw value=904357 ID=7
9388 00:43:31.836009 ADC[3]: Raw value=213441 ID=1
9389 00:43:31.839169 RAM Code: 0x71
9390 00:43:31.842539 ADC[6]: Raw value=75332 ID=0
9391 00:43:31.846126 ADC[5]: Raw value=212703 ID=1
9392 00:43:31.846233 SKU Code: 0x1
9393 00:43:31.852831 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8c83
9394 00:43:31.852923 coreboot table: 964 bytes.
9395 00:43:31.856025 IMD ROOT 0. 0xfffff000 0x00001000
9396 00:43:31.859182 IMD SMALL 1. 0xffffe000 0x00001000
9397 00:43:31.862458 RO MCACHE 2. 0xffffc000 0x00001104
9398 00:43:31.865630 CONSOLE 3. 0xfff7c000 0x00080000
9399 00:43:31.869301 FMAP 4. 0xfff7b000 0x00000452
9400 00:43:31.872470 TIME STAMP 5. 0xfff7a000 0x00000910
9401 00:43:31.875912 VBOOT WORK 6. 0xfff66000 0x00014000
9402 00:43:31.879114 RAMOOPS 7. 0xffe66000 0x00100000
9403 00:43:31.882363 COREBOOT 8. 0xffe64000 0x00002000
9404 00:43:31.885674 IMD small region:
9405 00:43:31.889435 IMD ROOT 0. 0xffffec00 0x00000400
9406 00:43:31.892566 VPD 1. 0xffffeb80 0x0000006c
9407 00:43:31.895863 MMC STATUS 2. 0xffffeb60 0x00000004
9408 00:43:31.899341 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9409 00:43:31.905644 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9410 00:43:31.946541 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9411 00:43:31.949846 Checking segment from ROM address 0x40100000
9412 00:43:31.953680 Checking segment from ROM address 0x4010001c
9413 00:43:31.960332 Loading segment from ROM address 0x40100000
9414 00:43:31.960404 code (compression=0)
9415 00:43:31.970171 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9416 00:43:31.976458 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9417 00:43:31.976553 it's not compressed!
9418 00:43:31.983455 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9419 00:43:31.989458 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9420 00:43:32.006886 Loading segment from ROM address 0x4010001c
9421 00:43:32.006984 Entry Point 0x80000000
9422 00:43:32.010837 Loaded segments
9423 00:43:32.013825 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9424 00:43:32.020315 Jumping to boot code at 0x80000000(0xffe64000)
9425 00:43:32.026980 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9426 00:43:32.033465 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9427 00:43:32.041690 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9428 00:43:32.044913 Checking segment from ROM address 0x40100000
9429 00:43:32.048191 Checking segment from ROM address 0x4010001c
9430 00:43:32.054643 Loading segment from ROM address 0x40100000
9431 00:43:32.054716 code (compression=1)
9432 00:43:32.061436 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9433 00:43:32.071157 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9434 00:43:32.071251 using LZMA
9435 00:43:32.080250 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9436 00:43:32.086699 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9437 00:43:32.089653 Loading segment from ROM address 0x4010001c
9438 00:43:32.089758 Entry Point 0x54601000
9439 00:43:32.093605 Loaded segments
9440 00:43:32.096244 NOTICE: MT8192 bl31_setup
9441 00:43:32.103676 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9442 00:43:32.106885 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9443 00:43:32.110015 WARNING: region 0:
9444 00:43:32.113354 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9445 00:43:32.113441 WARNING: region 1:
9446 00:43:32.119963 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9447 00:43:32.123650 WARNING: region 2:
9448 00:43:32.126657 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9449 00:43:32.130070 WARNING: region 3:
9450 00:43:32.133461 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9451 00:43:32.136770 WARNING: region 4:
9452 00:43:32.143404 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9453 00:43:32.143489 WARNING: region 5:
9454 00:43:32.147078 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 00:43:32.150636 WARNING: region 6:
9456 00:43:32.153871 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9457 00:43:32.153960 WARNING: region 7:
9458 00:43:32.160046 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 00:43:32.167246 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9460 00:43:32.170570 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9461 00:43:32.173699 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9462 00:43:32.179934 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9463 00:43:32.183645 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9464 00:43:32.187012 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9465 00:43:32.193512 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9466 00:43:32.196586 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9467 00:43:32.203418 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9468 00:43:32.206922 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9469 00:43:32.210217 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9470 00:43:32.216764 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9471 00:43:32.220052 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9472 00:43:32.223340 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9473 00:43:32.229724 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9474 00:43:32.233585 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9475 00:43:32.239862 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9476 00:43:32.243253 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9477 00:43:32.246641 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9478 00:43:32.253214 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9479 00:43:32.256429 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9480 00:43:32.259788 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9481 00:43:32.266365 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9482 00:43:32.270299 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9483 00:43:32.276589 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9484 00:43:32.280374 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9485 00:43:32.283288 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9486 00:43:32.289969 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9487 00:43:32.293072 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9488 00:43:32.299901 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9489 00:43:32.303076 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9490 00:43:32.306339 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9491 00:43:32.312751 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9492 00:43:32.316290 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9493 00:43:32.319945 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9494 00:43:32.323287 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9495 00:43:32.329319 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9496 00:43:32.333275 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9497 00:43:32.336484 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9498 00:43:32.339662 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9499 00:43:32.346172 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9500 00:43:32.349488 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9501 00:43:32.352815 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9502 00:43:32.356107 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9503 00:43:32.363167 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9504 00:43:32.366426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9505 00:43:32.369763 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9506 00:43:32.376349 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9507 00:43:32.379758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9508 00:43:32.383008 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9509 00:43:32.389686 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9510 00:43:32.393086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9511 00:43:32.399844 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9512 00:43:32.402411 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9513 00:43:32.409440 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9514 00:43:32.412370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9515 00:43:32.415860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9516 00:43:32.422447 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9517 00:43:32.425872 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9518 00:43:32.432907 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9519 00:43:32.435891 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9520 00:43:32.442550 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9521 00:43:32.445924 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9522 00:43:32.449354 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9523 00:43:32.456195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9524 00:43:32.459411 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9525 00:43:32.466394 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9526 00:43:32.469428 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9527 00:43:32.475961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9528 00:43:32.479390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9529 00:43:32.482660 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9530 00:43:32.489435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9531 00:43:32.492712 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9532 00:43:32.499541 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9533 00:43:32.502955 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9534 00:43:32.508922 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9535 00:43:32.512271 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9536 00:43:32.519227 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9537 00:43:32.522623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9538 00:43:32.525966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9539 00:43:32.532645 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9540 00:43:32.535896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9541 00:43:32.542290 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9542 00:43:32.545909 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9543 00:43:32.552551 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9544 00:43:32.555559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9545 00:43:32.559017 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9546 00:43:32.565810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9547 00:43:32.569159 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9548 00:43:32.575355 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9549 00:43:32.578950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9550 00:43:32.585537 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9551 00:43:32.589230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9552 00:43:32.592196 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9553 00:43:32.599283 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9554 00:43:32.602407 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9555 00:43:32.609362 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9556 00:43:32.612817 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9557 00:43:32.616338 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9558 00:43:32.618989 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9559 00:43:32.626259 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9560 00:43:32.628915 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9561 00:43:32.632373 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9562 00:43:32.639059 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9563 00:43:32.642233 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9564 00:43:32.649363 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9565 00:43:32.652665 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9566 00:43:32.655922 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9567 00:43:32.662445 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9568 00:43:32.665820 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9569 00:43:32.672236 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9570 00:43:32.675869 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9571 00:43:32.678862 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9572 00:43:32.685413 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9573 00:43:32.689289 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9574 00:43:32.695770 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9575 00:43:32.699022 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9576 00:43:32.702545 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9577 00:43:32.705537 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9578 00:43:32.712198 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9579 00:43:32.715560 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9580 00:43:32.718549 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9581 00:43:32.722131 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9582 00:43:32.728782 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9583 00:43:32.731927 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9584 00:43:32.738810 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9585 00:43:32.742136 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9586 00:43:32.745336 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9587 00:43:32.751806 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9588 00:43:32.755036 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9589 00:43:32.758961 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9590 00:43:32.765334 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9591 00:43:32.768708 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9592 00:43:32.775554 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9593 00:43:32.778883 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9594 00:43:32.781518 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9595 00:43:32.788194 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9596 00:43:32.791562 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9597 00:43:32.798831 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9598 00:43:32.801952 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9599 00:43:32.805289 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9600 00:43:32.812078 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9601 00:43:32.815340 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9602 00:43:32.818632 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9603 00:43:32.825337 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9604 00:43:32.828834 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9605 00:43:32.835169 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9606 00:43:32.838838 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9607 00:43:32.841968 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9608 00:43:32.848616 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9609 00:43:32.852129 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9610 00:43:32.858863 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9611 00:43:32.862052 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9612 00:43:32.865522 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9613 00:43:32.871948 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9614 00:43:32.875236 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9615 00:43:32.881968 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9616 00:43:32.885324 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9617 00:43:32.888591 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9618 00:43:32.895276 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9619 00:43:32.898274 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9620 00:43:32.901769 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9621 00:43:32.908583 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9622 00:43:32.911266 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9623 00:43:32.918701 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9624 00:43:32.921360 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9625 00:43:32.924767 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9626 00:43:32.931481 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9627 00:43:32.935098 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9628 00:43:32.941896 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9629 00:43:32.945135 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9630 00:43:32.948506 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9631 00:43:32.955015 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9632 00:43:32.958212 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9633 00:43:32.961922 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9634 00:43:32.968579 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9635 00:43:32.971841 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9636 00:43:32.978292 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9637 00:43:32.981469 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9638 00:43:32.985000 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9639 00:43:32.991778 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9640 00:43:32.995089 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9641 00:43:33.001581 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9642 00:43:33.004876 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9643 00:43:33.008106 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9644 00:43:33.014935 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9645 00:43:33.018273 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9646 00:43:33.021464 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9647 00:43:33.028271 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9648 00:43:33.031616 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9649 00:43:33.038273 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9650 00:43:33.041488 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9651 00:43:33.048504 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9652 00:43:33.051521 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9653 00:43:33.054845 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9654 00:43:33.061978 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9655 00:43:33.065143 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9656 00:43:33.071776 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9657 00:43:33.075215 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9658 00:43:33.077879 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9659 00:43:33.084827 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9660 00:43:33.087873 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9661 00:43:33.094679 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9662 00:43:33.097934 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9663 00:43:33.104889 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9664 00:43:33.108098 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9665 00:43:33.111191 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9666 00:43:33.117948 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9667 00:43:33.121477 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9668 00:43:33.128148 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9669 00:43:33.131467 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9670 00:43:33.134903 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9671 00:43:33.140980 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9672 00:43:33.144833 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9673 00:43:33.151422 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9674 00:43:33.154669 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9675 00:43:33.158352 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9676 00:43:33.164939 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9677 00:43:33.168044 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9678 00:43:33.174792 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9679 00:43:33.178129 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9680 00:43:33.184835 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9681 00:43:33.188132 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9682 00:43:33.191532 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9683 00:43:33.197872 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9684 00:43:33.201433 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9685 00:43:33.207991 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9686 00:43:33.211397 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9687 00:43:33.214652 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9688 00:43:33.221306 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9689 00:43:33.224534 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9690 00:43:33.228122 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9691 00:43:33.231142 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9692 00:43:33.238115 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9693 00:43:33.241304 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9694 00:43:33.244475 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9695 00:43:33.250986 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9696 00:43:33.254374 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9697 00:43:33.258376 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9698 00:43:33.264803 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9699 00:43:33.267846 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9700 00:43:33.271243 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9701 00:43:33.277830 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9702 00:43:33.280989 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9703 00:43:33.287966 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9704 00:43:33.291292 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9705 00:43:33.294577 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9706 00:43:33.301293 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9707 00:43:33.304493 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9708 00:43:33.307537 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9709 00:43:33.314247 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9710 00:43:33.317606 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9711 00:43:33.324369 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9712 00:43:33.327739 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9713 00:43:33.331052 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9714 00:43:33.337543 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9715 00:43:33.340821 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9716 00:43:33.344460 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9717 00:43:33.350972 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9718 00:43:33.354376 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9719 00:43:33.357922 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9720 00:43:33.364382 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9721 00:43:33.367462 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9722 00:43:33.370926 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9723 00:43:33.377330 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9724 00:43:33.380838 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9725 00:43:33.387639 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9726 00:43:33.390681 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9727 00:43:33.394327 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9728 00:43:33.397586 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9729 00:43:33.404373 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9730 00:43:33.407654 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9731 00:43:33.410405 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9732 00:43:33.414176 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9733 00:43:33.420903 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9734 00:43:33.424229 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9735 00:43:33.427495 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9736 00:43:33.430843 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9737 00:43:33.437522 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9738 00:43:33.440899 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9739 00:43:33.444343 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9740 00:43:33.447580 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9741 00:43:33.454301 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9742 00:43:33.457650 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9743 00:43:33.464401 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9744 00:43:33.467673 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9745 00:43:33.470893 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9746 00:43:33.477369 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9747 00:43:33.480499 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9748 00:43:33.487646 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9749 00:43:33.490492 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9750 00:43:33.493986 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9751 00:43:33.501020 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9752 00:43:33.504203 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9753 00:43:33.510679 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9754 00:43:33.513850 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9755 00:43:33.520938 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9756 00:43:33.523896 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9757 00:43:33.527446 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9758 00:43:33.533806 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9759 00:43:33.537104 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9760 00:43:33.544298 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9761 00:43:33.547023 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9762 00:43:33.550367 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9763 00:43:33.556977 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9764 00:43:33.560432 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9765 00:43:33.567272 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9766 00:43:33.570713 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9767 00:43:33.573421 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9768 00:43:33.580366 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9769 00:43:33.583617 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9770 00:43:33.590331 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9771 00:43:33.593581 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9772 00:43:33.596984 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9773 00:43:33.603436 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9774 00:43:33.607042 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9775 00:43:33.613367 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9776 00:43:33.617346 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9777 00:43:33.623430 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9778 00:43:33.626871 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9779 00:43:33.630441 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9780 00:43:33.637158 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9781 00:43:33.639969 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9782 00:43:33.643389 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9783 00:43:33.650282 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9784 00:43:33.653899 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9785 00:43:33.660054 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9786 00:43:33.663366 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9787 00:43:33.670035 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9788 00:43:33.673350 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9789 00:43:33.676732 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9790 00:43:33.683352 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9791 00:43:33.687350 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9792 00:43:33.693701 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9793 00:43:33.696940 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9794 00:43:33.700348 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9795 00:43:33.706968 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9796 00:43:33.710336 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9797 00:43:33.716715 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9798 00:43:33.720420 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9799 00:43:33.723698 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9800 00:43:33.730257 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9801 00:43:33.733486 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9802 00:43:33.739985 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9803 00:43:33.743230 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9804 00:43:33.746403 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9805 00:43:33.753695 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9806 00:43:33.756713 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9807 00:43:33.763745 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9808 00:43:33.766897 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9809 00:43:33.769811 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9810 00:43:33.776591 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9811 00:43:33.780035 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9812 00:43:33.786727 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9813 00:43:33.789919 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9814 00:43:33.793250 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9815 00:43:33.799993 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9816 00:43:33.803108 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9817 00:43:33.809709 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9818 00:43:33.813158 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9819 00:43:33.820131 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9820 00:43:33.823411 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9821 00:43:33.826698 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9822 00:43:33.833298 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9823 00:43:33.836629 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9824 00:43:33.843161 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9825 00:43:33.846644 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9826 00:43:33.853557 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9827 00:43:33.856294 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9828 00:43:33.859697 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9829 00:43:33.866917 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9830 00:43:33.869686 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9831 00:43:33.876769 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9832 00:43:33.880147 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9833 00:43:33.886347 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9834 00:43:33.889610 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9835 00:43:33.896688 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9836 00:43:33.899971 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9837 00:43:33.902993 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9838 00:43:33.909888 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9839 00:43:33.913193 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9840 00:43:33.919668 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9841 00:43:33.922913 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9842 00:43:33.930099 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9843 00:43:33.933421 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9844 00:43:33.936719 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9845 00:43:33.943349 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9846 00:43:33.946571 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9847 00:43:33.953447 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9848 00:43:33.956772 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9849 00:43:33.959858 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9850 00:43:33.966472 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9851 00:43:33.969766 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9852 00:43:33.976333 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9853 00:43:33.979863 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9854 00:43:33.986643 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9855 00:43:33.989978 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9856 00:43:33.996457 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9857 00:43:33.999752 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9858 00:43:34.003333 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9859 00:43:34.009722 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9860 00:43:34.013369 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9861 00:43:34.016878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9862 00:43:34.023230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9863 00:43:34.026540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9864 00:43:34.033119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9865 00:43:34.036598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9866 00:43:34.043399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9867 00:43:34.046362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9868 00:43:34.053492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9869 00:43:34.056624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9870 00:43:34.063259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9871 00:43:34.066339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9872 00:43:34.073395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9873 00:43:34.076700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9874 00:43:34.083296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9875 00:43:34.086747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9876 00:43:34.093314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9877 00:43:34.096459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9878 00:43:34.099821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9879 00:43:34.106685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9880 00:43:34.110167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9881 00:43:34.116809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9882 00:43:34.119938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9883 00:43:34.126431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9884 00:43:34.129855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9885 00:43:34.136540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9886 00:43:34.139879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9887 00:43:34.146487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9888 00:43:34.149558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9889 00:43:34.156407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9890 00:43:34.159661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9891 00:43:34.166457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9892 00:43:34.169901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9893 00:43:34.175914 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9894 00:43:34.175991 INFO: [APUAPC] vio 0
9895 00:43:34.183296 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9896 00:43:34.186566 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9897 00:43:34.189935 INFO: [APUAPC] D0_APC_0: 0x400510
9898 00:43:34.193357 INFO: [APUAPC] D0_APC_1: 0x0
9899 00:43:34.196642 INFO: [APUAPC] D0_APC_2: 0x1540
9900 00:43:34.199810 INFO: [APUAPC] D0_APC_3: 0x0
9901 00:43:34.203108 INFO: [APUAPC] D1_APC_0: 0xffffffff
9902 00:43:34.206429 INFO: [APUAPC] D1_APC_1: 0xffffffff
9903 00:43:34.209760 INFO: [APUAPC] D1_APC_2: 0x3fffff
9904 00:43:34.213070 INFO: [APUAPC] D1_APC_3: 0x0
9905 00:43:34.216403 INFO: [APUAPC] D2_APC_0: 0xffffffff
9906 00:43:34.219865 INFO: [APUAPC] D2_APC_1: 0xffffffff
9907 00:43:34.223207 INFO: [APUAPC] D2_APC_2: 0x3fffff
9908 00:43:34.226348 INFO: [APUAPC] D2_APC_3: 0x0
9909 00:43:34.229658 INFO: [APUAPC] D3_APC_0: 0xffffffff
9910 00:43:34.233414 INFO: [APUAPC] D3_APC_1: 0xffffffff
9911 00:43:34.236475 INFO: [APUAPC] D3_APC_2: 0x3fffff
9912 00:43:34.236576 INFO: [APUAPC] D3_APC_3: 0x0
9913 00:43:34.243493 INFO: [APUAPC] D4_APC_0: 0xffffffff
9914 00:43:34.246640 INFO: [APUAPC] D4_APC_1: 0xffffffff
9915 00:43:34.249719 INFO: [APUAPC] D4_APC_2: 0x3fffff
9916 00:43:34.249796 INFO: [APUAPC] D4_APC_3: 0x0
9917 00:43:34.253404 INFO: [APUAPC] D5_APC_0: 0xffffffff
9918 00:43:34.256475 INFO: [APUAPC] D5_APC_1: 0xffffffff
9919 00:43:34.259731 INFO: [APUAPC] D5_APC_2: 0x3fffff
9920 00:43:34.263511 INFO: [APUAPC] D5_APC_3: 0x0
9921 00:43:34.266505 INFO: [APUAPC] D6_APC_0: 0xffffffff
9922 00:43:34.269705 INFO: [APUAPC] D6_APC_1: 0xffffffff
9923 00:43:34.273388 INFO: [APUAPC] D6_APC_2: 0x3fffff
9924 00:43:34.276320 INFO: [APUAPC] D6_APC_3: 0x0
9925 00:43:34.279998 INFO: [APUAPC] D7_APC_0: 0xffffffff
9926 00:43:34.283215 INFO: [APUAPC] D7_APC_1: 0xffffffff
9927 00:43:34.286693 INFO: [APUAPC] D7_APC_2: 0x3fffff
9928 00:43:34.289649 INFO: [APUAPC] D7_APC_3: 0x0
9929 00:43:34.293023 INFO: [APUAPC] D8_APC_0: 0xffffffff
9930 00:43:34.296277 INFO: [APUAPC] D8_APC_1: 0xffffffff
9931 00:43:34.299748 INFO: [APUAPC] D8_APC_2: 0x3fffff
9932 00:43:34.302934 INFO: [APUAPC] D8_APC_3: 0x0
9933 00:43:34.306286 INFO: [APUAPC] D9_APC_0: 0xffffffff
9934 00:43:34.309430 INFO: [APUAPC] D9_APC_1: 0xffffffff
9935 00:43:34.312806 INFO: [APUAPC] D9_APC_2: 0x3fffff
9936 00:43:34.316246 INFO: [APUAPC] D9_APC_3: 0x0
9937 00:43:34.319650 INFO: [APUAPC] D10_APC_0: 0xffffffff
9938 00:43:34.323031 INFO: [APUAPC] D10_APC_1: 0xffffffff
9939 00:43:34.326454 INFO: [APUAPC] D10_APC_2: 0x3fffff
9940 00:43:34.329123 INFO: [APUAPC] D10_APC_3: 0x0
9941 00:43:34.333111 INFO: [APUAPC] D11_APC_0: 0xffffffff
9942 00:43:34.336356 INFO: [APUAPC] D11_APC_1: 0xffffffff
9943 00:43:34.339698 INFO: [APUAPC] D11_APC_2: 0x3fffff
9944 00:43:34.343020 INFO: [APUAPC] D11_APC_3: 0x0
9945 00:43:34.346119 INFO: [APUAPC] D12_APC_0: 0xffffffff
9946 00:43:34.349696 INFO: [APUAPC] D12_APC_1: 0xffffffff
9947 00:43:34.352434 INFO: [APUAPC] D12_APC_2: 0x3fffff
9948 00:43:34.356084 INFO: [APUAPC] D12_APC_3: 0x0
9949 00:43:34.359061 INFO: [APUAPC] D13_APC_0: 0xffffffff
9950 00:43:34.362796 INFO: [APUAPC] D13_APC_1: 0xffffffff
9951 00:43:34.365970 INFO: [APUAPC] D13_APC_2: 0x3fffff
9952 00:43:34.369278 INFO: [APUAPC] D13_APC_3: 0x0
9953 00:43:34.372819 INFO: [APUAPC] D14_APC_0: 0xffffffff
9954 00:43:34.376029 INFO: [APUAPC] D14_APC_1: 0xffffffff
9955 00:43:34.379269 INFO: [APUAPC] D14_APC_2: 0x3fffff
9956 00:43:34.382457 INFO: [APUAPC] D14_APC_3: 0x0
9957 00:43:34.385701 INFO: [APUAPC] D15_APC_0: 0xffffffff
9958 00:43:34.389278 INFO: [APUAPC] D15_APC_1: 0xffffffff
9959 00:43:34.392723 INFO: [APUAPC] D15_APC_2: 0x3fffff
9960 00:43:34.395997 INFO: [APUAPC] D15_APC_3: 0x0
9961 00:43:34.399031 INFO: [APUAPC] APC_CON: 0x4
9962 00:43:34.402812 INFO: [NOCDAPC] D0_APC_0: 0x0
9963 00:43:34.405732 INFO: [NOCDAPC] D0_APC_1: 0x0
9964 00:43:34.408859 INFO: [NOCDAPC] D1_APC_0: 0x0
9965 00:43:34.412732 INFO: [NOCDAPC] D1_APC_1: 0xfff
9966 00:43:34.412809 INFO: [NOCDAPC] D2_APC_0: 0x0
9967 00:43:34.415814 INFO: [NOCDAPC] D2_APC_1: 0xfff
9968 00:43:34.418982 INFO: [NOCDAPC] D3_APC_0: 0x0
9969 00:43:34.422443 INFO: [NOCDAPC] D3_APC_1: 0xfff
9970 00:43:34.425687 INFO: [NOCDAPC] D4_APC_0: 0x0
9971 00:43:34.429007 INFO: [NOCDAPC] D4_APC_1: 0xfff
9972 00:43:34.432351 INFO: [NOCDAPC] D5_APC_0: 0x0
9973 00:43:34.435670 INFO: [NOCDAPC] D5_APC_1: 0xfff
9974 00:43:34.438988 INFO: [NOCDAPC] D6_APC_0: 0x0
9975 00:43:34.442374 INFO: [NOCDAPC] D6_APC_1: 0xfff
9976 00:43:34.445706 INFO: [NOCDAPC] D7_APC_0: 0x0
9977 00:43:34.448499 INFO: [NOCDAPC] D7_APC_1: 0xfff
9978 00:43:34.448576 INFO: [NOCDAPC] D8_APC_0: 0x0
9979 00:43:34.451878 INFO: [NOCDAPC] D8_APC_1: 0xfff
9980 00:43:34.455129 INFO: [NOCDAPC] D9_APC_0: 0x0
9981 00:43:34.458811 INFO: [NOCDAPC] D9_APC_1: 0xfff
9982 00:43:34.462427 INFO: [NOCDAPC] D10_APC_0: 0x0
9983 00:43:34.465510 INFO: [NOCDAPC] D10_APC_1: 0xfff
9984 00:43:34.468941 INFO: [NOCDAPC] D11_APC_0: 0x0
9985 00:43:34.472248 INFO: [NOCDAPC] D11_APC_1: 0xfff
9986 00:43:34.475438 INFO: [NOCDAPC] D12_APC_0: 0x0
9987 00:43:34.478516 INFO: [NOCDAPC] D12_APC_1: 0xfff
9988 00:43:34.482018 INFO: [NOCDAPC] D13_APC_0: 0x0
9989 00:43:34.485080 INFO: [NOCDAPC] D13_APC_1: 0xfff
9990 00:43:34.488422 INFO: [NOCDAPC] D14_APC_0: 0x0
9991 00:43:34.488499 INFO: [NOCDAPC] D14_APC_1: 0xfff
9992 00:43:34.491704 INFO: [NOCDAPC] D15_APC_0: 0x0
9993 00:43:34.495196 INFO: [NOCDAPC] D15_APC_1: 0xfff
9994 00:43:34.498968 INFO: [NOCDAPC] APC_CON: 0x4
9995 00:43:34.501850 INFO: [APUAPC] set_apusys_apc done
9996 00:43:34.505502 INFO: [DEVAPC] devapc_init done
9997 00:43:34.508929 INFO: GICv3 without legacy support detected.
9998 00:43:34.515512 INFO: ARM GICv3 driver initialized in EL3
9999 00:43:34.518549 INFO: Maximum SPI INTID supported: 639
10000 00:43:34.522000 INFO: BL31: Initializing runtime services
10001 00:43:34.528358 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10002 00:43:34.532189 INFO: SPM: enable CPC mode
10003 00:43:34.534785 INFO: mcdi ready for mcusys-off-idle and system suspend
10004 00:43:34.538180 INFO: BL31: Preparing for EL3 exit to normal world
10005 00:43:34.544763 INFO: Entry point address = 0x80000000
10006 00:43:34.544840 INFO: SPSR = 0x8
10007 00:43:34.551499
10008 00:43:34.551575
10009 00:43:34.551633
10010 00:43:34.554900 Starting depthcharge on Spherion...
10011 00:43:34.554976
10012 00:43:34.555035 Wipe memory regions:
10013 00:43:34.555090
10014 00:43:34.555702 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10015 00:43:34.555795 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10016 00:43:34.555909 Setting prompt string to ['asurada:']
10017 00:43:34.555985 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10018 00:43:34.558219 [0x00000040000000, 0x00000054600000)
10019 00:43:34.680358
10020 00:43:34.680466 [0x00000054660000, 0x00000080000000)
10021 00:43:34.941023
10022 00:43:34.941146 [0x000000821a7280, 0x000000ffe64000)
10023 00:43:35.686291
10024 00:43:35.686457 [0x00000100000000, 0x00000240000000)
10025 00:43:37.576631
10026 00:43:37.579940 Initializing XHCI USB controller at 0x11200000.
10027 00:43:38.617784
10028 00:43:38.621096 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10029 00:43:38.621182
10030 00:43:38.621242
10031 00:43:38.621514 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10033 00:43:38.721903 asurada: tftpboot 192.168.201.1 14368394/tftp-deploy-qtxpfq2e/kernel/image.itb 14368394/tftp-deploy-qtxpfq2e/kernel/cmdline
10034 00:43:38.722074 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10035 00:43:38.722154 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10036 00:43:38.726270 tftpboot 192.168.201.1 14368394/tftp-deploy-qtxpfq2e/kernel/image.itp-deploy-qtxpfq2e/kernel/cmdline
10037 00:43:38.726348
10038 00:43:38.726408 Waiting for link
10039 00:43:38.884634
10040 00:43:38.884749 R8152: Initializing
10041 00:43:38.884809
10042 00:43:38.887883 Version 9 (ocp_data = 6010)
10043 00:43:38.887960
10044 00:43:38.890770 R8152: Done initializing
10045 00:43:38.890846
10046 00:43:38.890905 Adding net device
10047 00:43:40.766240
10048 00:43:40.766398 done.
10049 00:43:40.766474
10050 00:43:40.766574 MAC: 00:e0:4c:78:7a:aa
10051 00:43:40.766657
10052 00:43:40.769246 Sending DHCP discover... done.
10053 00:43:40.769323
10054 00:43:40.772329 Waiting for reply... done.
10055 00:43:40.772407
10056 00:43:40.775755 Sending DHCP request... done.
10057 00:43:40.775832
10058 00:43:40.775893 Waiting for reply... done.
10059 00:43:40.775948
10060 00:43:40.779436 My ip is 192.168.201.12
10061 00:43:40.779512
10062 00:43:40.782418 The DHCP server ip is 192.168.201.1
10063 00:43:40.782498
10064 00:43:40.785877 TFTP server IP predefined by user: 192.168.201.1
10065 00:43:40.785967
10066 00:43:40.792431 Bootfile predefined by user: 14368394/tftp-deploy-qtxpfq2e/kernel/image.itb
10067 00:43:40.792540
10068 00:43:40.795813 Sending tftp read request... done.
10069 00:43:40.795894
10070 00:43:40.799321 Waiting for the transfer...
10071 00:43:40.799412
10072 00:43:41.060006 00000000 ################################################################
10073 00:43:41.060126
10074 00:43:41.309934 00080000 ################################################################
10075 00:43:41.310050
10076 00:43:41.565860 00100000 ################################################################
10077 00:43:41.565971
10078 00:43:41.830529 00180000 ################################################################
10079 00:43:41.830673
10080 00:43:42.108342 00200000 ################################################################
10081 00:43:42.108479
10082 00:43:42.367058 00280000 ################################################################
10083 00:43:42.367176
10084 00:43:42.621389 00300000 ################################################################
10085 00:43:42.621525
10086 00:43:42.895377 00380000 ################################################################
10087 00:43:42.895493
10088 00:43:43.148925 00400000 ################################################################
10089 00:43:43.149033
10090 00:43:43.413457 00480000 ################################################################
10091 00:43:43.413597
10092 00:43:43.667993 00500000 ################################################################
10093 00:43:43.668105
10094 00:43:43.930270 00580000 ################################################################
10095 00:43:43.930421
10096 00:43:44.184160 00600000 ################################################################
10097 00:43:44.184282
10098 00:43:44.443740 00680000 ################################################################
10099 00:43:44.443881
10100 00:43:44.697649 00700000 ################################################################
10101 00:43:44.697784
10102 00:43:44.961238 00780000 ################################################################
10103 00:43:44.961375
10104 00:43:45.224898 00800000 ################################################################
10105 00:43:45.225014
10106 00:43:45.486388 00880000 ################################################################
10107 00:43:45.486514
10108 00:43:45.753970 00900000 ################################################################
10109 00:43:45.754119
10110 00:43:46.006174 00980000 ################################################################
10111 00:43:46.006291
10112 00:43:46.257349 00a00000 ################################################################
10113 00:43:46.257523
10114 00:43:46.513135 00a80000 ################################################################
10115 00:43:46.513252
10116 00:43:46.795190 00b00000 ################################################################
10117 00:43:46.795302
10118 00:43:47.068044 00b80000 ################################################################
10119 00:43:47.068157
10120 00:43:47.318590 00c00000 ################################################################
10121 00:43:47.318726
10122 00:43:47.568292 00c80000 ################################################################
10123 00:43:47.568404
10124 00:43:47.818759 00d00000 ################################################################
10125 00:43:47.818879
10126 00:43:48.067491 00d80000 ################################################################
10127 00:43:48.067603
10128 00:43:48.315658 00e00000 ################################################################
10129 00:43:48.315806
10130 00:43:48.566058 00e80000 ################################################################
10131 00:43:48.566171
10132 00:43:48.816094 00f00000 ################################################################
10133 00:43:48.816206
10134 00:43:49.064822 00f80000 ################################################################
10135 00:43:49.064937
10136 00:43:49.314398 01000000 ################################################################
10137 00:43:49.314512
10138 00:43:49.565772 01080000 ################################################################
10139 00:43:49.565885
10140 00:43:49.832751 01100000 ################################################################
10141 00:43:49.832860
10142 00:43:50.087183 01180000 ################################################################
10143 00:43:50.087359
10144 00:43:50.340866 01200000 ################################################################
10145 00:43:50.340978
10146 00:43:50.602002 01280000 ################################################################
10147 00:43:50.602120
10148 00:43:50.855395 01300000 ################################################################
10149 00:43:50.855512
10150 00:43:51.103485 01380000 ################################################################
10151 00:43:51.103625
10152 00:43:51.359219 01400000 ################################################################
10153 00:43:51.359342
10154 00:43:51.613338 01480000 ################################################################
10155 00:43:51.613451
10156 00:43:51.883251 01500000 ################################################################
10157 00:43:51.883366
10158 00:43:52.144499 01580000 ################################################################
10159 00:43:52.144657
10160 00:43:52.405212 01600000 ################################################################
10161 00:43:52.405349
10162 00:43:52.681399 01680000 ################################################################
10163 00:43:52.681516
10164 00:43:52.956573 01700000 ################################################################
10165 00:43:52.956692
10166 00:43:53.225532 01780000 ################################################################
10167 00:43:53.225690
10168 00:43:53.491747 01800000 ################################################################
10169 00:43:53.491860
10170 00:43:53.723998 01880000 ################################################################
10171 00:43:53.724211
10172 00:43:53.992156 01900000 ################################################################
10173 00:43:53.992274
10174 00:43:54.271892 01980000 ################################################################
10175 00:43:54.272034
10176 00:43:54.524294 01a00000 ################################################################
10177 00:43:54.524420
10178 00:43:54.792466 01a80000 ################################################################
10179 00:43:54.792580
10180 00:43:55.045940 01b00000 ################################################################
10181 00:43:55.046063
10182 00:43:55.299380 01b80000 ################################################################
10183 00:43:55.299525
10184 00:43:55.552346 01c00000 ################################################################
10185 00:43:55.552461
10186 00:43:55.801631 01c80000 ################################################################
10187 00:43:55.801744
10188 00:43:56.054751 01d00000 ################################################################
10189 00:43:56.054873
10190 00:43:56.304735 01d80000 ################################################################
10191 00:43:56.304847
10192 00:43:56.561630 01e00000 ################################################################
10193 00:43:56.561745
10194 00:43:56.822339 01e80000 ################################################################
10195 00:43:56.822453
10196 00:43:57.073125 01f00000 ################################################################
10197 00:43:57.073244
10198 00:43:57.333211 01f80000 ################################################################
10199 00:43:57.333384
10200 00:43:57.601864 02000000 ################################################################
10201 00:43:57.602031
10202 00:43:57.854176 02080000 ################################################################
10203 00:43:57.854312
10204 00:43:58.123382 02100000 ################################################################
10205 00:43:58.123514
10206 00:43:58.389089 02180000 ################################################################
10207 00:43:58.389240
10208 00:43:58.668961 02200000 ################################################################
10209 00:43:58.669087
10210 00:43:58.919871 02280000 ################################################################
10211 00:43:58.920016
10212 00:43:59.177202 02300000 ################################################################
10213 00:43:59.177326
10214 00:43:59.457937 02380000 ################################################################
10215 00:43:59.458058
10216 00:43:59.730610 02400000 ################################################################
10217 00:43:59.730733
10218 00:43:59.991335 02480000 ################################################################
10219 00:43:59.991455
10220 00:44:00.255210 02500000 ################################################################
10221 00:44:00.255333
10222 00:44:00.512225 02580000 ################################################################
10223 00:44:00.512342
10224 00:44:00.761283 02600000 ################################################################
10225 00:44:00.761405
10226 00:44:01.009274 02680000 ################################################################
10227 00:44:01.009392
10228 00:44:01.261108 02700000 ################################################################
10229 00:44:01.261225
10230 00:44:01.510882 02780000 ################################################################
10231 00:44:01.511029
10232 00:44:01.769268 02800000 ################################################################
10233 00:44:01.769385
10234 00:44:02.029871 02880000 ################################################################
10235 00:44:02.029983
10236 00:44:02.285645 02900000 ################################################################
10237 00:44:02.285761
10238 00:44:02.545886 02980000 ################################################################
10239 00:44:02.546002
10240 00:44:02.815961 02a00000 ################################################################
10241 00:44:02.816080
10242 00:44:03.074813 02a80000 ################################################################
10243 00:44:03.074931
10244 00:44:03.354483 02b00000 ################################################################
10245 00:44:03.354596
10246 00:44:03.645777 02b80000 ################################################################
10247 00:44:03.645900
10248 00:44:03.936090 02c00000 ################################################################
10249 00:44:03.936259
10250 00:44:04.234977 02c80000 ################################################################
10251 00:44:04.235097
10252 00:44:04.525556 02d00000 ################################################################
10253 00:44:04.525677
10254 00:44:04.817503 02d80000 ################################################################
10255 00:44:04.817632
10256 00:44:05.111923 02e00000 ################################################################
10257 00:44:05.112046
10258 00:44:05.410336 02e80000 ################################################################
10259 00:44:05.410451
10260 00:44:05.690823 02f00000 ################################################################
10261 00:44:05.690931
10262 00:44:05.972493 02f80000 ################################################################
10263 00:44:05.972601
10264 00:44:06.237686 03000000 ################################################################
10265 00:44:06.237794
10266 00:44:06.500914 03080000 ################################################################
10267 00:44:06.501024
10268 00:44:06.766773 03100000 ################################################################
10269 00:44:06.766888
10270 00:44:07.039009 03180000 ################################################################
10271 00:44:07.039121
10272 00:44:07.288233 03200000 ################################################################
10273 00:44:07.288343
10274 00:44:07.548359 03280000 ################################################################
10275 00:44:07.548482
10276 00:44:07.814370 03300000 ################################################################
10277 00:44:07.814496
10278 00:44:08.019793 03380000 ############################################### done.
10279 00:44:08.019914
10280 00:44:08.023060 The bootfile was 54386342 bytes long.
10281 00:44:08.023214
10282 00:44:08.026111 Sending tftp read request... done.
10283 00:44:08.026207
10284 00:44:08.026271 Waiting for the transfer...
10285 00:44:08.026331
10286 00:44:08.029695 00000000 # done.
10287 00:44:08.029787
10288 00:44:08.036362 Command line loaded dynamically from TFTP file: 14368394/tftp-deploy-qtxpfq2e/kernel/cmdline
10289 00:44:08.036459
10290 00:44:08.049704 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10291 00:44:08.049903
10292 00:44:08.052885 Loading FIT.
10293 00:44:08.053092
10294 00:44:08.056374 Image ramdisk-1 has 41210682 bytes.
10295 00:44:08.056556
10296 00:44:08.056671 Image fdt-1 has 47258 bytes.
10297 00:44:08.059730
10298 00:44:08.059891 Image kernel-1 has 13126376 bytes.
10299 00:44:08.060017
10300 00:44:08.069853 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10301 00:44:08.070154
10302 00:44:08.086244 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10303 00:44:08.086726
10304 00:44:08.092842 Choosing best match conf-1 for compat google,spherion-rev2.
10305 00:44:08.097726
10306 00:44:08.102303 Connected to device vid:did:rid of 1ae0:0028:00
10307 00:44:08.109931
10308 00:44:08.113103 tpm_get_response: command 0x17b, return code 0x0
10309 00:44:08.113494
10310 00:44:08.117011 ec_init: CrosEC protocol v3 supported (256, 248)
10311 00:44:08.120786
10312 00:44:08.123857 tpm_cleanup: add release locality here.
10313 00:44:08.124252
10314 00:44:08.124559 Shutting down all USB controllers.
10315 00:44:08.127411
10316 00:44:08.127798 Removing current net device
10317 00:44:08.128131
10318 00:44:08.133652 Exiting depthcharge with code 4 at timestamp: 62840000
10319 00:44:08.134046
10320 00:44:08.137511 LZMA decompressing kernel-1 to 0x821a6718
10321 00:44:08.137945
10322 00:44:08.140894 LZMA decompressing kernel-1 to 0x40000000
10323 00:44:09.757635
10324 00:44:09.758150 jumping to kernel
10325 00:44:09.760184 end: 2.2.4 bootloader-commands (duration 00:00:35) [common]
10326 00:44:09.760670 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10327 00:44:09.761035 Setting prompt string to ['Linux version [0-9]']
10328 00:44:09.761375 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10329 00:44:09.761755 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10330 00:44:09.840052
10331 00:44:09.843566 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10332 00:44:09.847028 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10333 00:44:09.847617 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10334 00:44:09.847995 Setting prompt string to []
10335 00:44:09.848405 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10336 00:44:09.848760 Using line separator: #'\n'#
10337 00:44:09.849061 No login prompt set.
10338 00:44:09.849381 Parsing kernel messages
10339 00:44:09.849707 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10340 00:44:09.850234 [login-action] Waiting for messages, (timeout 00:03:45)
10341 00:44:09.850576 Waiting using forced prompt support (timeout 00:01:52)
10342 00:44:09.865959 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232175-arm64-gcc-10-defconfig-arm64-chromebook-7lg8d) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024
10343 00:44:09.869410 [ 0.000000] random: crng init done
10344 00:44:09.876180 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10345 00:44:09.879630 [ 0.000000] efi: UEFI not found.
10346 00:44:09.886071 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10347 00:44:09.893257 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10348 00:44:09.903143 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10349 00:44:09.913200 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10350 00:44:09.919892 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10351 00:44:09.922528 [ 0.000000] printk: bootconsole [mtk8250] enabled
10352 00:44:09.931627 [ 0.000000] NUMA: No NUMA configuration found
10353 00:44:09.938094 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10354 00:44:09.944904 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10355 00:44:09.945743 [ 0.000000] Zone ranges:
10356 00:44:09.951248 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10357 00:44:09.955027 [ 0.000000] DMA32 empty
10358 00:44:09.961174 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10359 00:44:09.965066 [ 0.000000] Movable zone start for each node
10360 00:44:09.968037 [ 0.000000] Early memory node ranges
10361 00:44:09.974916 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10362 00:44:09.981394 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10363 00:44:09.987978 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10364 00:44:09.995070 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10365 00:44:10.001479 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10366 00:44:10.007828 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10367 00:44:10.064469 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10368 00:44:10.071444 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10369 00:44:10.077488 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10370 00:44:10.081147 [ 0.000000] psci: probing for conduit method from DT.
10371 00:44:10.087713 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10372 00:44:10.090879 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10373 00:44:10.097763 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10374 00:44:10.101094 [ 0.000000] psci: SMC Calling Convention v1.2
10375 00:44:10.107158 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10376 00:44:10.110968 [ 0.000000] Detected VIPT I-cache on CPU0
10377 00:44:10.117338 [ 0.000000] CPU features: detected: GIC system register CPU interface
10378 00:44:10.124517 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10379 00:44:10.130523 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10380 00:44:10.137765 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10381 00:44:10.144199 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10382 00:44:10.153703 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10383 00:44:10.157494 [ 0.000000] alternatives: applying boot alternatives
10384 00:44:10.164038 [ 0.000000] Fallback order for Node 0: 0
10385 00:44:10.170752 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10386 00:44:10.174262 [ 0.000000] Policy zone: Normal
10387 00:44:10.187095 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10388 00:44:10.196940 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10389 00:44:10.208818 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10390 00:44:10.218451 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10391 00:44:10.225588 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10392 00:44:10.228436 <6>[ 0.000000] software IO TLB: area num 8.
10393 00:44:10.285061 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10394 00:44:10.434484 <6>[ 0.000000] Memory: 7923816K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 428952K reserved, 32768K cma-reserved)
10395 00:44:10.441258 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10396 00:44:10.447481 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10397 00:44:10.451085 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10398 00:44:10.457456 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10399 00:44:10.464383 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10400 00:44:10.467777 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10401 00:44:10.477728 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10402 00:44:10.484007 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10403 00:44:10.490754 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10404 00:44:10.497414 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10405 00:44:10.500670 <6>[ 0.000000] GICv3: 608 SPIs implemented
10406 00:44:10.503982 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10407 00:44:10.510670 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10408 00:44:10.513880 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10409 00:44:10.520831 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10410 00:44:10.534298 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10411 00:44:10.543805 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10412 00:44:10.554020 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10413 00:44:10.561014 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10414 00:44:10.574400 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10415 00:44:10.580864 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10416 00:44:10.588008 <6>[ 0.009230] Console: colour dummy device 80x25
10417 00:44:10.597991 <6>[ 0.013989] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10418 00:44:10.604064 <6>[ 0.024430] pid_max: default: 32768 minimum: 301
10419 00:44:10.607779 <6>[ 0.029300] LSM: Security Framework initializing
10420 00:44:10.614172 <6>[ 0.034239] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10421 00:44:10.624133 <6>[ 0.042054] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10422 00:44:10.631005 <6>[ 0.051447] cblist_init_generic: Setting adjustable number of callback queues.
10423 00:44:10.637407 <6>[ 0.058889] cblist_init_generic: Setting shift to 3 and lim to 1.
10424 00:44:10.647389 <6>[ 0.065228] cblist_init_generic: Setting adjustable number of callback queues.
10425 00:44:10.651092 <6>[ 0.072654] cblist_init_generic: Setting shift to 3 and lim to 1.
10426 00:44:10.657619 <6>[ 0.079093] rcu: Hierarchical SRCU implementation.
10427 00:44:10.664328 <6>[ 0.084109] rcu: Max phase no-delay instances is 1000.
10428 00:44:10.671088 <6>[ 0.091135] EFI services will not be available.
10429 00:44:10.673953 <6>[ 0.096123] smp: Bringing up secondary CPUs ...
10430 00:44:10.682086 <6>[ 0.101201] Detected VIPT I-cache on CPU1
10431 00:44:10.688334 <6>[ 0.101273] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10432 00:44:10.695441 <6>[ 0.101304] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10433 00:44:10.698970 <6>[ 0.101626] Detected VIPT I-cache on CPU2
10434 00:44:10.705378 <6>[ 0.101672] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10435 00:44:10.711957 <6>[ 0.101687] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10436 00:44:10.718684 <6>[ 0.101938] Detected VIPT I-cache on CPU3
10437 00:44:10.725679 <6>[ 0.101985] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10438 00:44:10.731773 <6>[ 0.101998] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10439 00:44:10.735509 <6>[ 0.102303] CPU features: detected: Spectre-v4
10440 00:44:10.741795 <6>[ 0.102309] CPU features: detected: Spectre-BHB
10441 00:44:10.745339 <6>[ 0.102314] Detected PIPT I-cache on CPU4
10442 00:44:10.751955 <6>[ 0.102372] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10443 00:44:10.758682 <6>[ 0.102389] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10444 00:44:10.761824 <6>[ 0.102684] Detected PIPT I-cache on CPU5
10445 00:44:10.771922 <6>[ 0.102746] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10446 00:44:10.778469 <6>[ 0.102762] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10447 00:44:10.781717 <6>[ 0.103043] Detected PIPT I-cache on CPU6
10448 00:44:10.788050 <6>[ 0.103110] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10449 00:44:10.795079 <6>[ 0.103126] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10450 00:44:10.802114 <6>[ 0.103423] Detected PIPT I-cache on CPU7
10451 00:44:10.808632 <6>[ 0.103489] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10452 00:44:10.815138 <6>[ 0.103505] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10453 00:44:10.818435 <6>[ 0.103552] smp: Brought up 1 node, 8 CPUs
10454 00:44:10.825023 <6>[ 0.244997] SMP: Total of 8 processors activated.
10455 00:44:10.828437 <6>[ 0.249918] CPU features: detected: 32-bit EL0 Support
10456 00:44:10.838072 <6>[ 0.255281] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10457 00:44:10.845048 <6>[ 0.264136] CPU features: detected: Common not Private translations
10458 00:44:10.848425 <6>[ 0.270652] CPU features: detected: CRC32 instructions
10459 00:44:10.855034 <6>[ 0.276003] CPU features: detected: RCpc load-acquire (LDAPR)
10460 00:44:10.861438 <6>[ 0.281963] CPU features: detected: LSE atomic instructions
10461 00:44:10.868014 <6>[ 0.287780] CPU features: detected: Privileged Access Never
10462 00:44:10.871035 <6>[ 0.293560] CPU features: detected: RAS Extension Support
10463 00:44:10.881449 <6>[ 0.299168] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10464 00:44:10.884468 <6>[ 0.306432] CPU: All CPU(s) started at EL2
10465 00:44:10.891234 <6>[ 0.310775] alternatives: applying system-wide alternatives
10466 00:44:10.899826 <6>[ 0.321581] devtmpfs: initialized
10467 00:44:10.912229 <6>[ 0.330354] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10468 00:44:10.921853 <6>[ 0.340317] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10469 00:44:10.928594 <6>[ 0.348341] pinctrl core: initialized pinctrl subsystem
10470 00:44:10.931858 <6>[ 0.355015] DMI not present or invalid.
10471 00:44:10.938582 <6>[ 0.359428] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10472 00:44:10.948334 <6>[ 0.366282] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10473 00:44:10.954941 <6>[ 0.373871] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10474 00:44:10.964474 <6>[ 0.382093] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10475 00:44:10.968412 <6>[ 0.390335] audit: initializing netlink subsys (disabled)
10476 00:44:10.977692 <5>[ 0.396024] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10477 00:44:10.984657 <6>[ 0.396733] thermal_sys: Registered thermal governor 'step_wise'
10478 00:44:10.991328 <6>[ 0.403991] thermal_sys: Registered thermal governor 'power_allocator'
10479 00:44:10.994282 <6>[ 0.410243] cpuidle: using governor menu
10480 00:44:11.000709 <6>[ 0.421202] NET: Registered PF_QIPCRTR protocol family
10481 00:44:11.007235 <6>[ 0.426681] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10482 00:44:11.014488 <6>[ 0.433784] ASID allocator initialised with 32768 entries
10483 00:44:11.017456 <6>[ 0.440356] Serial: AMBA PL011 UART driver
10484 00:44:11.027261 <4>[ 0.449170] Trying to register duplicate clock ID: 134
10485 00:44:11.085879 <6>[ 0.510335] KASLR enabled
10486 00:44:11.099742 <6>[ 0.517940] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10487 00:44:11.106401 <6>[ 0.524955] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10488 00:44:11.112578 <6>[ 0.531445] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10489 00:44:11.119346 <6>[ 0.538450] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10490 00:44:11.126036 <6>[ 0.544939] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10491 00:44:11.132785 <6>[ 0.551943] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10492 00:44:11.139345 <6>[ 0.558430] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10493 00:44:11.146125 <6>[ 0.565434] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10494 00:44:11.149178 <6>[ 0.572894] ACPI: Interpreter disabled.
10495 00:44:11.157516 <6>[ 0.579341] iommu: Default domain type: Translated
10496 00:44:11.164388 <6>[ 0.584455] iommu: DMA domain TLB invalidation policy: strict mode
10497 00:44:11.167660 <5>[ 0.591116] SCSI subsystem initialized
10498 00:44:11.174267 <6>[ 0.595362] usbcore: registered new interface driver usbfs
10499 00:44:11.181055 <6>[ 0.601094] usbcore: registered new interface driver hub
10500 00:44:11.184238 <6>[ 0.606644] usbcore: registered new device driver usb
10501 00:44:11.191143 <6>[ 0.612759] pps_core: LinuxPPS API ver. 1 registered
10502 00:44:11.200933 <6>[ 0.617952] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10503 00:44:11.203989 <6>[ 0.627295] PTP clock support registered
10504 00:44:11.207647 <6>[ 0.631539] EDAC MC: Ver: 3.0.0
10505 00:44:11.215403 <6>[ 0.636729] FPGA manager framework
10506 00:44:11.218646 <6>[ 0.640405] Advanced Linux Sound Architecture Driver Initialized.
10507 00:44:11.221902 <6>[ 0.647177] vgaarb: loaded
10508 00:44:11.228566 <6>[ 0.650313] clocksource: Switched to clocksource arch_sys_counter
10509 00:44:11.235232 <5>[ 0.656753] VFS: Disk quotas dquot_6.6.0
10510 00:44:11.242388 <6>[ 0.660941] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10511 00:44:11.244934 <6>[ 0.668131] pnp: PnP ACPI: disabled
10512 00:44:11.253508 <6>[ 0.674801] NET: Registered PF_INET protocol family
10513 00:44:11.263001 <6>[ 0.680396] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10514 00:44:11.274072 <6>[ 0.692728] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10515 00:44:11.284323 <6>[ 0.701541] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10516 00:44:11.290881 <6>[ 0.709509] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10517 00:44:11.297397 <6>[ 0.718212] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10518 00:44:11.309366 <6>[ 0.727970] TCP: Hash tables configured (established 65536 bind 65536)
10519 00:44:11.316505 <6>[ 0.734838] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10520 00:44:11.322674 <6>[ 0.742041] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10521 00:44:11.329105 <6>[ 0.749750] NET: Registered PF_UNIX/PF_LOCAL protocol family
10522 00:44:11.335961 <6>[ 0.755898] RPC: Registered named UNIX socket transport module.
10523 00:44:11.339429 <6>[ 0.762052] RPC: Registered udp transport module.
10524 00:44:11.345603 <6>[ 0.766984] RPC: Registered tcp transport module.
10525 00:44:11.352262 <6>[ 0.771915] RPC: Registered tcp NFSv4.1 backchannel transport module.
10526 00:44:11.355575 <6>[ 0.778581] PCI: CLS 0 bytes, default 64
10527 00:44:11.358760 <6>[ 0.782924] Unpacking initramfs...
10528 00:44:11.384304 <6>[ 0.802428] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10529 00:44:11.394139 <6>[ 0.811080] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10530 00:44:11.397269 <6>[ 0.819911] kvm [1]: IPA Size Limit: 40 bits
10531 00:44:11.403865 <6>[ 0.824440] kvm [1]: GICv3: no GICV resource entry
10532 00:44:11.407673 <6>[ 0.829460] kvm [1]: disabling GICv2 emulation
10533 00:44:11.413667 <6>[ 0.834163] kvm [1]: GIC system register CPU interface enabled
10534 00:44:11.417266 <6>[ 0.840321] kvm [1]: vgic interrupt IRQ18
10535 00:44:11.423713 <6>[ 0.844674] kvm [1]: VHE mode initialized successfully
10536 00:44:11.430310 <5>[ 0.851095] Initialise system trusted keyrings
10537 00:44:11.436711 <6>[ 0.855894] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10538 00:44:11.444823 <6>[ 0.865908] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10539 00:44:11.451176 <5>[ 0.872301] NFS: Registering the id_resolver key type
10540 00:44:11.454588 <5>[ 0.877598] Key type id_resolver registered
10541 00:44:11.461117 <5>[ 0.882014] Key type id_legacy registered
10542 00:44:11.467205 <6>[ 0.886294] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10543 00:44:11.474791 <6>[ 0.893217] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10544 00:44:11.480965 <6>[ 0.900949] 9p: Installing v9fs 9p2000 file system support
10545 00:44:11.517711 <5>[ 0.939496] Key type asymmetric registered
10546 00:44:11.521631 <5>[ 0.943825] Asymmetric key parser 'x509' registered
10547 00:44:11.531078 <6>[ 0.948974] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10548 00:44:11.534293 <6>[ 0.956587] io scheduler mq-deadline registered
10549 00:44:11.537515 <6>[ 0.961365] io scheduler kyber registered
10550 00:44:11.556301 <6>[ 0.978364] EINJ: ACPI disabled.
10551 00:44:11.589740 <4>[ 1.004717] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10552 00:44:11.599272 <4>[ 1.015356] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10553 00:44:11.614912 <6>[ 1.036285] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10554 00:44:11.623091 <6>[ 1.044299] printk: console [ttyS0] disabled
10555 00:44:11.650528 <6>[ 1.068926] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10556 00:44:11.657413 <6>[ 1.078405] printk: console [ttyS0] enabled
10557 00:44:11.660524 <6>[ 1.078405] printk: console [ttyS0] enabled
10558 00:44:11.667375 <6>[ 1.087305] printk: bootconsole [mtk8250] disabled
10559 00:44:11.670568 <6>[ 1.087305] printk: bootconsole [mtk8250] disabled
10560 00:44:11.677248 <6>[ 1.098546] SuperH (H)SCI(F) driver initialized
10561 00:44:11.680369 <6>[ 1.103816] msm_serial: driver initialized
10562 00:44:11.694205 <6>[ 1.112818] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10563 00:44:11.704488 <6>[ 1.121364] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10564 00:44:11.711312 <6>[ 1.129907] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10565 00:44:11.721195 <6>[ 1.138536] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10566 00:44:11.727782 <6>[ 1.147242] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10567 00:44:11.737795 <6>[ 1.155957] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10568 00:44:11.747560 <6>[ 1.164500] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10569 00:44:11.754502 <6>[ 1.173303] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10570 00:44:11.764039 <6>[ 1.181851] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10571 00:44:11.775979 <6>[ 1.197262] loop: module loaded
10572 00:44:11.782384 <6>[ 1.203264] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10573 00:44:11.805409 <4>[ 1.226554] mtk-pmic-keys: Failed to locate of_node [id: -1]
10574 00:44:11.811849 <6>[ 1.233396] megasas: 07.719.03.00-rc1
10575 00:44:11.821712 <6>[ 1.243164] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10576 00:44:11.828282 <6>[ 1.249716] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10577 00:44:11.844975 <6>[ 1.266201] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10578 00:44:11.901988 <6>[ 1.316482] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10579 00:44:13.076640 <6>[ 2.498530] Freeing initrd memory: 40240K
10580 00:44:13.088013 <6>[ 2.510399] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10581 00:44:13.099129 <6>[ 2.521202] tun: Universal TUN/TAP device driver, 1.6
10582 00:44:13.102561 <6>[ 2.527261] thunder_xcv, ver 1.0
10583 00:44:13.105648 <6>[ 2.530766] thunder_bgx, ver 1.0
10584 00:44:13.108899 <6>[ 2.534254] nicpf, ver 1.0
10585 00:44:13.119752 <6>[ 2.538258] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10586 00:44:13.122969 <6>[ 2.545734] hns3: Copyright (c) 2017 Huawei Corporation.
10587 00:44:13.126316 <6>[ 2.551322] hclge is initializing
10588 00:44:13.133037 <6>[ 2.554897] e1000: Intel(R) PRO/1000 Network Driver
10589 00:44:13.140004 <6>[ 2.560026] e1000: Copyright (c) 1999-2006 Intel Corporation.
10590 00:44:13.143064 <6>[ 2.566039] e1000e: Intel(R) PRO/1000 Network Driver
10591 00:44:13.150066 <6>[ 2.571255] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10592 00:44:13.156161 <6>[ 2.577440] igb: Intel(R) Gigabit Ethernet Network Driver
10593 00:44:13.163320 <6>[ 2.583090] igb: Copyright (c) 2007-2014 Intel Corporation.
10594 00:44:13.169649 <6>[ 2.588925] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10595 00:44:13.176591 <6>[ 2.595442] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10596 00:44:13.179639 <6>[ 2.601902] sky2: driver version 1.30
10597 00:44:13.186079 <6>[ 2.606827] usbcore: registered new device driver r8152-cfgselector
10598 00:44:13.192598 <6>[ 2.613360] usbcore: registered new interface driver r8152
10599 00:44:13.196039 <6>[ 2.619174] VFIO - User Level meta-driver version: 0.3
10600 00:44:13.205945 <6>[ 2.627384] usbcore: registered new interface driver usb-storage
10601 00:44:13.211975 <6>[ 2.633825] usbcore: registered new device driver onboard-usb-hub
10602 00:44:13.221149 <6>[ 2.642963] mt6397-rtc mt6359-rtc: registered as rtc0
10603 00:44:13.231129 <6>[ 2.648429] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:44:13 UTC (1718498653)
10604 00:44:13.234314 <6>[ 2.657985] i2c_dev: i2c /dev entries driver
10605 00:44:13.248385 <4>[ 2.669961] cpu cpu0: supply cpu not found, using dummy regulator
10606 00:44:13.254594 <4>[ 2.676387] cpu cpu1: supply cpu not found, using dummy regulator
10607 00:44:13.261962 <4>[ 2.682789] cpu cpu2: supply cpu not found, using dummy regulator
10608 00:44:13.268030 <4>[ 2.689213] cpu cpu3: supply cpu not found, using dummy regulator
10609 00:44:13.274733 <4>[ 2.695610] cpu cpu4: supply cpu not found, using dummy regulator
10610 00:44:13.281453 <4>[ 2.702008] cpu cpu5: supply cpu not found, using dummy regulator
10611 00:44:13.288511 <4>[ 2.708403] cpu cpu6: supply cpu not found, using dummy regulator
10612 00:44:13.294805 <4>[ 2.714796] cpu cpu7: supply cpu not found, using dummy regulator
10613 00:44:13.313793 <6>[ 2.735456] cpu cpu0: EM: created perf domain
10614 00:44:13.316975 <6>[ 2.740399] cpu cpu4: EM: created perf domain
10615 00:44:13.324388 <6>[ 2.745983] sdhci: Secure Digital Host Controller Interface driver
10616 00:44:13.330887 <6>[ 2.752417] sdhci: Copyright(c) Pierre Ossman
10617 00:44:13.337382 <6>[ 2.757371] Synopsys Designware Multimedia Card Interface Driver
10618 00:44:13.343881 <6>[ 2.764011] sdhci-pltfm: SDHCI platform and OF driver helper
10619 00:44:13.347199 <6>[ 2.764143] mmc0: CQHCI version 5.10
10620 00:44:13.353781 <6>[ 2.773961] ledtrig-cpu: registered to indicate activity on CPUs
10621 00:44:13.360826 <6>[ 2.780988] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10622 00:44:13.367141 <6>[ 2.788051] usbcore: registered new interface driver usbhid
10623 00:44:13.370462 <6>[ 2.793873] usbhid: USB HID core driver
10624 00:44:13.377146 <6>[ 2.798077] spi_master spi0: will run message pump with realtime priority
10625 00:44:13.420332 <6>[ 2.834983] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10626 00:44:13.438317 <6>[ 2.849851] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10627 00:44:13.444974 <6>[ 2.864749] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15c14
10628 00:44:13.451604 <6>[ 2.864811] cros-ec-spi spi0.0: Chrome EC device registered
10629 00:44:13.454917 <6>[ 2.876791] mmc0: Command Queue Engine enabled
10630 00:44:13.461955 <6>[ 2.881523] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10631 00:44:13.468061 <6>[ 2.889218] mmcblk0: mmc0:0001 DA4128 116 GiB
10632 00:44:13.476755 <6>[ 2.898301] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10633 00:44:13.483699 <6>[ 2.905152] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10634 00:44:13.489861 <6>[ 2.911231] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10635 00:44:13.496357 <6>[ 2.917246] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10636 00:44:13.506321 <6>[ 2.922684] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10637 00:44:13.512900 <6>[ 2.934207] NET: Registered PF_PACKET protocol family
10638 00:44:13.516204 <6>[ 2.939602] 9pnet: Installing 9P2000 support
10639 00:44:13.522656 <5>[ 2.944166] Key type dns_resolver registered
10640 00:44:13.526842 <6>[ 2.949126] registered taskstats version 1
10641 00:44:13.532955 <5>[ 2.953511] Loading compiled-in X.509 certificates
10642 00:44:13.561913 <4>[ 2.977051] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 00:44:13.571669 <4>[ 2.988007] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 00:44:13.586679 <6>[ 3.008529] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10645 00:44:13.593721 <6>[ 3.015385] xhci-mtk 11200000.usb: xHCI Host Controller
10646 00:44:13.600000 <6>[ 3.020880] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10647 00:44:13.610321 <6>[ 3.028726] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10648 00:44:13.617183 <6>[ 3.038151] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10649 00:44:13.623533 <6>[ 3.044242] xhci-mtk 11200000.usb: xHCI Host Controller
10650 00:44:13.630421 <6>[ 3.049721] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10651 00:44:13.636576 <6>[ 3.057369] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10652 00:44:13.643804 <6>[ 3.065000] hub 1-0:1.0: USB hub found
10653 00:44:13.646761 <6>[ 3.069018] hub 1-0:1.0: 1 port detected
10654 00:44:13.653294 <6>[ 3.073295] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10655 00:44:13.660121 <6>[ 3.081814] hub 2-0:1.0: USB hub found
10656 00:44:13.663551 <6>[ 3.085822] hub 2-0:1.0: 1 port detected
10657 00:44:13.671022 <6>[ 3.092773] mtk-msdc 11f70000.mmc: Got CD GPIO
10658 00:44:13.684408 <6>[ 3.102450] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10659 00:44:13.694419 <6>[ 3.110829] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10660 00:44:13.700745 <6>[ 3.119169] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10661 00:44:13.710496 <6>[ 3.127509] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10662 00:44:13.717587 <6>[ 3.135847] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10663 00:44:13.727294 <6>[ 3.144189] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10664 00:44:13.734432 <6>[ 3.152535] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10665 00:44:13.743784 <6>[ 3.160873] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10666 00:44:13.750520 <6>[ 3.169212] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10667 00:44:13.759979 <6>[ 3.177558] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10668 00:44:13.766590 <6>[ 3.185896] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10669 00:44:13.776484 <6>[ 3.194240] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10670 00:44:13.783352 <6>[ 3.202578] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10671 00:44:13.793912 <6>[ 3.210916] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10672 00:44:13.800371 <6>[ 3.219253] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10673 00:44:13.806601 <6>[ 3.227956] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10674 00:44:13.813030 <6>[ 3.235103] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10675 00:44:13.820326 <6>[ 3.241902] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10676 00:44:13.830049 <6>[ 3.248675] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10677 00:44:13.836824 <6>[ 3.255655] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10678 00:44:13.843329 <6>[ 3.262517] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10679 00:44:13.853508 <6>[ 3.271648] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10680 00:44:13.863231 <6>[ 3.280774] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10681 00:44:13.873151 <6>[ 3.290066] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10682 00:44:13.883201 <6>[ 3.299534] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10683 00:44:13.889736 <6>[ 3.309002] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10684 00:44:13.899766 <6>[ 3.318122] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10685 00:44:13.909696 <6>[ 3.327587] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10686 00:44:13.919383 <6>[ 3.336709] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10687 00:44:13.929162 <6>[ 3.346004] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10688 00:44:13.939163 <6>[ 3.356164] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10689 00:44:13.950089 <6>[ 3.368283] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10690 00:44:14.071867 <6>[ 3.490655] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10691 00:44:14.227034 <6>[ 3.648676] hub 1-1:1.0: USB hub found
10692 00:44:14.230267 <6>[ 3.653201] hub 1-1:1.0: 4 ports detected
10693 00:44:14.242390 <6>[ 3.663816] hub 1-1:1.0: USB hub found
10694 00:44:14.245755 <6>[ 3.668104] hub 1-1:1.0: 4 ports detected
10695 00:44:14.352369 <6>[ 3.770955] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10696 00:44:14.378400 <6>[ 3.800480] hub 2-1:1.0: USB hub found
10697 00:44:14.381973 <6>[ 3.805000] hub 2-1:1.0: 3 ports detected
10698 00:44:14.392992 <6>[ 3.814790] hub 2-1:1.0: USB hub found
10699 00:44:14.396408 <6>[ 3.819148] hub 2-1:1.0: 3 ports detected
10700 00:44:14.567691 <6>[ 3.986571] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10701 00:44:14.699947 <6>[ 4.121782] hub 1-1.4:1.0: USB hub found
10702 00:44:14.702909 <6>[ 4.126361] hub 1-1.4:1.0: 2 ports detected
10703 00:44:14.714525 <6>[ 4.136524] hub 1-1.4:1.0: USB hub found
10704 00:44:14.718254 <6>[ 4.141035] hub 1-1.4:1.0: 2 ports detected
10705 00:44:14.784335 <6>[ 4.202723] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10706 00:44:14.892445 <6>[ 4.311286] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10707 00:44:14.928199 <4>[ 4.346655] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10708 00:44:14.938248 <4>[ 4.355747] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10709 00:44:14.982201 <6>[ 4.404236] r8152 2-1.3:1.0 eth0: v1.12.13
10710 00:44:15.015655 <6>[ 4.434389] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10711 00:44:15.203699 <6>[ 4.622495] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10712 00:44:16.687084 <6>[ 6.109572] r8152 2-1.3:1.0 eth0: carrier on
10713 00:44:19.115617 <5>[ 6.134427] Sending DHCP requests .., OK
10714 00:44:19.122340 <6>[ 8.542702] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10715 00:44:19.125660 <6>[ 8.551006] IP-Config: Complete:
10716 00:44:19.139265 <6>[ 8.554501] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10717 00:44:19.145632 <6>[ 8.565256] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10718 00:44:19.152216 <6>[ 8.573876] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10719 00:44:19.159204 <6>[ 8.573885] nameserver0=192.168.201.1
10720 00:44:19.162420 <6>[ 8.586044] clk: Disabling unused clocks
10721 00:44:19.165615 <6>[ 8.591581] ALSA device list:
10722 00:44:19.172148 <6>[ 8.594853] No soundcards found.
10723 00:44:19.179289 <6>[ 8.602175] Freeing unused kernel memory: 8512K
10724 00:44:19.183410 <6>[ 8.607130] Run /init as init process
10725 00:44:19.211542 <6>[ 8.634003] NET: Registered PF_INET6 protocol family
10726 00:44:19.218126 <6>[ 8.640754] Segment Routing with IPv6
10727 00:44:19.221214 <6>[ 8.644779] In-situ OAM (IOAM) with IPv6
10728 00:44:19.261310 <30>[ 8.657507] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10729 00:44:19.268313 <30>[ 8.690587] systemd[1]: Detected architecture arm64.
10730 00:44:19.268749
10731 00:44:19.274976 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10732 00:44:19.275441
10733 00:44:19.287943 <30>[ 8.710678] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10734 00:44:19.407512 <30>[ 8.827089] systemd[1]: Queued start job for default target graphical.target.
10735 00:44:19.436787 <30>[ 8.856241] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10736 00:44:19.443651 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10737 00:44:19.464397 <30>[ 8.883405] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10738 00:44:19.474110 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10739 00:44:19.492767 <30>[ 8.912124] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10740 00:44:19.503416 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10741 00:44:19.521157 <30>[ 8.940002] systemd[1]: Created slice user.slice - User and Session Slice.
10742 00:44:19.527768 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10743 00:44:19.551342 <30>[ 8.967270] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10744 00:44:19.560851 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10745 00:44:19.578748 <30>[ 8.994717] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10746 00:44:19.585517 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10747 00:44:19.613486 <30>[ 9.023139] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10748 00:44:19.623806 <30>[ 9.043079] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10749 00:44:19.630126 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10750 00:44:19.647627 <30>[ 9.066683] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10751 00:44:19.654015 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10752 00:44:19.671571 <30>[ 9.090706] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10753 00:44:19.681136 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10754 00:44:19.696216 <30>[ 9.118768] systemd[1]: Reached target paths.target - Path Units.
10755 00:44:19.706513 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10756 00:44:19.723856 <30>[ 9.143071] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10757 00:44:19.730112 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10758 00:44:19.744668 <30>[ 9.166625] systemd[1]: Reached target slices.target - Slice Units.
10759 00:44:19.754621 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10760 00:44:19.768904 <30>[ 9.191117] systemd[1]: Reached target swap.target - Swaps.
10761 00:44:19.774905 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10762 00:44:19.796104 <30>[ 9.215119] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10763 00:44:19.805846 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10764 00:44:19.823874 <30>[ 9.243014] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10765 00:44:19.833496 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10766 00:44:19.853514 <30>[ 9.272833] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10767 00:44:19.863112 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10768 00:44:19.880668 <30>[ 9.299409] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10769 00:44:19.890243 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10770 00:44:19.907679 <30>[ 9.327248] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10771 00:44:19.914374 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10772 00:44:19.931751 <30>[ 9.351306] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10773 00:44:19.942000 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10774 00:44:19.961306 <30>[ 9.380070] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10775 00:44:19.970601 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10776 00:44:19.988677 <30>[ 9.407719] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10777 00:44:19.998404 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10778 00:44:20.055582 <30>[ 9.474867] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10779 00:44:20.061986 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10780 00:44:20.081352 <30>[ 9.500474] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10781 00:44:20.088139 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10782 00:44:20.109473 <30>[ 9.528737] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10783 00:44:20.116565 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10784 00:44:20.141957 <30>[ 9.554852] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10785 00:44:20.167722 <30>[ 9.587009] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10786 00:44:20.177715 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10787 00:44:20.199715 <30>[ 9.619434] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10788 00:44:20.206669 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10789 00:44:20.232597 <30>[ 9.651888] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10790 00:44:20.242337 Startin<6>[ 9.661327] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10791 00:44:20.248928 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10792 00:44:20.292421 <30>[ 9.711445] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10793 00:44:20.298525 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10794 00:44:20.324725 <30>[ 9.744162] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10795 00:44:20.331684 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10796 00:44:20.356368 <30>[ 9.775981] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10797 00:44:20.363596 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10798 00:44:20.427872 <30>[ 9.847307] systemd[1]: Starting systemd-journald.service - Journal Service...
10799 00:44:20.434433 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10800 00:44:20.454793 <30>[ 9.874114] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10801 00:44:20.461319 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10802 00:44:20.486702 <30>[ 9.902744] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10803 00:44:20.493150 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10804 00:44:20.516487 <30>[ 9.935595] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10805 00:44:20.526128 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10806 00:44:20.546928 <30>[ 9.966069] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10807 00:44:20.556926 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10808 00:44:20.581201 <30>[ 10.000460] systemd[1]: Started systemd-journald.service - Journal Service.
10809 00:44:20.587459 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10810 00:44:20.609745 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10811 00:44:20.628377 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10812 00:44:20.648724 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10813 00:44:20.668867 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10814 00:44:20.689759 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10815 00:44:20.709587 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10816 00:44:20.730482 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10817 00:44:20.750803 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10818 00:44:20.777320 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10819 00:44:20.801419 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10820 00:44:20.821499 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10821 00:44:20.842041 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10822 00:44:20.856200 See 'systemctl status systemd-remount-fs.service' for details.
10823 00:44:20.876839 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10824 00:44:20.898204 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10825 00:44:20.955937 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10826 00:44:20.976514 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10827 00:44:20.995076 <46>[ 10.414513] systemd-journald[196]: Received client request to flush runtime journal.
10828 00:44:21.015673 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10829 00:44:21.035911 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10830 00:44:21.055413 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10831 00:44:21.078095 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10832 00:44:21.097388 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10833 00:44:21.116771 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10834 00:44:21.136894 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10835 00:44:21.156597 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10836 00:44:21.204026 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10837 00:44:21.235649 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10838 00:44:21.251917 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10839 00:44:21.267736 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10840 00:44:21.311789 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10841 00:44:21.336597 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10842 00:44:21.359759 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10843 00:44:21.408533 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10844 00:44:21.434655 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10845 00:44:21.457638 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10846 00:44:21.500437 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10847 00:44:21.532178 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10848 00:44:21.549277 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10849 00:44:21.651612 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10850 00:44:21.668950 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10851 00:44:21.688479 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10852 00:44:21.710363 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10853 00:44:21.728293 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10854 00:44:21.745450 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10855 00:44:21.763797 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10856 00:44:21.776755 <3>[ 11.195814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 00:44:21.783269 <3>[ 11.204045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 00:44:21.793137 <6>[ 11.205891] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10859 00:44:21.799836 <6>[ 11.209701] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10860 00:44:21.806708 <3>[ 11.212560] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10861 00:44:21.816536 <6>[ 11.215335] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10862 00:44:21.822758 <6>[ 11.215344] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10863 00:44:21.832802 <4>[ 11.215555] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10864 00:44:21.839513 <6>[ 11.216200] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10865 00:44:21.849711 <6>[ 11.216204] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10866 00:44:21.856213 <6>[ 11.216265] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10867 00:44:21.865423 <6>[ 11.216312] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10868 00:44:21.872142 <6>[ 11.216327] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10869 00:44:21.882293 <6>[ 11.225847] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10870 00:44:21.889129 <3>[ 11.236936] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 00:44:21.898540 <6>[ 11.243847] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10872 00:44:21.905600 <6>[ 11.243853] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10873 00:44:21.915586 <6>[ 11.243856] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10874 00:44:21.922531 <3>[ 11.251703] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10875 00:44:21.932470 <6>[ 11.262585] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10876 00:44:21.939289 <3>[ 11.268800] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10877 00:44:21.945998 <3>[ 11.268806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 00:44:21.956614 <3>[ 11.268810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10879 00:44:21.959916 <6>[ 11.270797] remoteproc remoteproc0: scp is available
10880 00:44:21.967438 <3>[ 11.273594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 00:44:21.974645 <6>[ 11.276842] mc: Linux media interface: v0.10
10882 00:44:21.981332 <3>[ 11.282882] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 00:44:21.987407 <6>[ 11.284600] remoteproc remoteproc0: powering up scp
10884 00:44:21.994062 <4>[ 11.291230] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10885 00:44:22.001294 <4>[ 11.292128] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10886 00:44:22.006969 <3>[ 11.293135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 00:44:22.017321 <3>[ 11.293142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10888 00:44:22.024172 <3>[ 11.308841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10889 00:44:22.034458 <6>[ 11.310656] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10890 00:44:22.038327 <6>[ 11.311002] videodev: Linux video capture interface: v2.00
10891 00:44:22.048928 <3>[ 11.318626] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10892 00:44:22.055162 <4>[ 11.321399] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10893 00:44:22.062686 <4>[ 11.321399] Fallback method does not support PEC.
10894 00:44:22.065795 <6>[ 11.325823] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10895 00:44:22.076315 <3>[ 11.333703] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10896 00:44:22.083276 <3>[ 11.338104] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 00:44:22.090266 <6>[ 11.347008] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10898 00:44:22.100410 <3>[ 11.351177] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10899 00:44:22.103168 <6>[ 11.358851] pci_bus 0000:00: root bus resource [bus 00-ff]
10900 00:44:22.113815 <3>[ 11.366679] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10901 00:44:22.120470 <3>[ 11.366830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10902 00:44:22.127270 <6>[ 11.375579] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10903 00:44:22.137261 <6>[ 11.402264] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10904 00:44:22.147531 <3>[ 11.405042] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 00:44:22.154761 <3>[ 11.405834] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10906 00:44:22.165052 <6>[ 11.408883] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10907 00:44:22.171182 <6>[ 11.408920] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10908 00:44:22.182180 <6>[ 11.414003] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10909 00:44:22.188605 <6>[ 11.414497] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10910 00:44:22.198570 <6>[ 11.421332] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10911 00:44:22.205915 <6>[ 11.468604] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10912 00:44:22.212562 <6>[ 11.468608] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10913 00:44:22.215624 <6>[ 11.470740] Bluetooth: Core ver 2.22
10914 00:44:22.222369 <6>[ 11.470809] NET: Registered PF_BLUETOOTH protocol family
10915 00:44:22.229006 <6>[ 11.470811] Bluetooth: HCI device and connection manager initialized
10916 00:44:22.232772 <6>[ 11.470824] Bluetooth: HCI socket layer initialized
10917 00:44:22.239442 <6>[ 11.470829] Bluetooth: L2CAP socket layer initialized
10918 00:44:22.243195 <6>[ 11.470835] Bluetooth: SCO socket layer initialized
10919 00:44:22.249231 <6>[ 11.475222] pci 0000:00:00.0: supports D1 D2
10920 00:44:22.256233 <3>[ 11.475887] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 00:44:22.266589 <6>[ 11.478046] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10922 00:44:22.273544 <3>[ 11.478082] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10923 00:44:22.280843 <6>[ 11.488806] remoteproc remoteproc0: remote processor scp is now up
10924 00:44:22.286949 <6>[ 11.489809] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10925 00:44:22.297631 <3>[ 11.490491] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 00:44:22.303758 <6>[ 11.490640] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10927 00:44:22.310587 <6>[ 11.494445] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10928 00:44:22.320120 <6>[ 11.496315] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10929 00:44:22.333533 <6>[ 11.498539] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10930 00:44:22.337025 <6>[ 11.498686] usbcore: registered new interface driver uvcvideo
10931 00:44:22.347152 <3>[ 11.511792] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 00:44:22.353477 <6>[ 11.518370] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10933 00:44:22.360151 <6>[ 11.533096] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10934 00:44:22.367303 <6>[ 11.533522] usbcore: registered new interface driver btusb
10935 00:44:22.376820 <4>[ 11.536105] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10936 00:44:22.383094 <3>[ 11.536120] Bluetooth: hci0: Failed to load firmware file (-2)
10937 00:44:22.386283 <3>[ 11.536125] Bluetooth: hci0: Failed to set up firmware (-2)
10938 00:44:22.400189 <4>[ 11.536133] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10939 00:44:22.406565 <6>[ 11.540171] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10940 00:44:22.413345 <3>[ 11.550039] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 00:44:22.423416 <6>[ 11.555391] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10942 00:44:22.429916 <5>[ 11.557176] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10943 00:44:22.436654 <5>[ 11.570611] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10944 00:44:22.443100 <6>[ 11.573457] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10945 00:44:22.452722 <5>[ 11.582479] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10946 00:44:22.462947 <3>[ 11.590125] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 00:44:22.465820 <6>[ 11.592244] pci 0000:01:00.0: supports D1 D2
10948 00:44:22.475957 <4>[ 11.598452] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10949 00:44:22.482355 <6>[ 11.608454] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10950 00:44:22.489119 <3>[ 11.610977] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 00:44:22.496095 <6>[ 11.617612] cfg80211: failed to load regulatory.db
10952 00:44:22.502665 <6>[ 11.628787] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10953 00:44:22.512915 <6>[ 11.930591] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10954 00:44:22.519036 <6>[ 11.938880] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10955 00:44:22.525323 <6>[ 11.946925] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10956 00:44:22.535206 <6>[ 11.954934] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10957 00:44:22.542307 <6>[ 11.962935] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10958 00:44:22.548600 <6>[ 11.970936] pci 0000:00:00.0: PCI bridge to [bus 01]
10959 00:44:22.554956 <6>[ 11.976153] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10960 00:44:22.565075 Startin<6>[ 11.984376] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10961 00:44:22.571556 g [0;1;39msyste<6>[ 11.992632] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10962 00:44:22.578291 md-networkd.…i<6>[ 12.000312] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10963 00:44:22.581326 ce[0m - Network Configuration...
10964 00:44:22.603027 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10965 00:44:22.647831 <6>[ 12.067429] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10966 00:44:22.654179 <6>[ 12.075023] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10967 00:44:22.665196 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10968 00:44:22.679199 <6>[ 12.102168] mt7921e 0000:01:00.0: ASIC revision: 79610010
10969 00:44:22.698556 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10970 00:44:22.721752 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10971 00:44:22.742697 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10972 00:44:22.789893 <6>[ 12.209295] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10973 00:44:22.793362 <6>[ 12.209295]
10974 00:44:22.799763 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10975 00:44:22.820934 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10976 00:44:22.838317 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10977 00:44:22.854764 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10978 00:44:22.874731 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10979 00:44:22.936638 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10980 00:44:22.961403 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10981 00:44:22.984438 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10982 00:44:23.006242 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10983 00:44:23.061055 <6>[ 12.480787] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10984 00:44:23.074265 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10985 00:44:23.100164 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10986 00:44:23.117719 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10987 00:44:23.133410 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10988 00:44:23.149449 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10989 00:44:23.211336 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10990 00:44:23.236489 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10991 00:44:23.258764 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10992 00:44:23.300189 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10993 00:44:23.357169
10994 00:44:23.360068 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10995 00:44:23.360497
10996 00:44:23.363598 debian-bookworm-arm64 login: root (automatic login)
10997 00:44:23.364105
10998 00:44:23.378994 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024 aarch64
10999 00:44:23.379486
11000 00:44:23.385339 The programs included with the Debian GNU/Linux system are free software;
11001 00:44:23.391881 the exact distribution terms for each program are described in the
11002 00:44:23.395051 individual files in /usr/share/doc/*/copyright.
11003 00:44:23.395481
11004 00:44:23.401767 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11005 00:44:23.405379 permitted by applicable law.
11006 00:44:23.406746 Matched prompt #10: / #
11008 00:44:23.407735 Setting prompt string to ['/ #']
11009 00:44:23.408174 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11011 00:44:23.409141 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11012 00:44:23.409624 start: 2.2.6 expect-shell-connection (timeout 00:03:31) [common]
11013 00:44:23.410013 Setting prompt string to ['/ #']
11014 00:44:23.410323 Forcing a shell prompt, looking for ['/ #']
11016 00:44:23.461108 / #
11017 00:44:23.461819 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11018 00:44:23.462207 Waiting using forced prompt support (timeout 00:02:30)
11019 00:44:23.468436
11020 00:44:23.469300 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11021 00:44:23.469865 start: 2.2.7 export-device-env (timeout 00:03:31) [common]
11022 00:44:23.470382 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11023 00:44:23.470913 end: 2.2 depthcharge-retry (duration 00:01:29) [common]
11024 00:44:23.471371 end: 2 depthcharge-action (duration 00:01:29) [common]
11025 00:44:23.471839 start: 3 lava-test-retry (timeout 00:08:10) [common]
11026 00:44:23.472294 start: 3.1 lava-test-shell (timeout 00:08:10) [common]
11027 00:44:23.472673 Using namespace: common
11029 00:44:23.573849 / # #
11030 00:44:23.574581 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11031 00:44:23.580436 #
11032 00:44:23.581222 Using /lava-14368394
11034 00:44:23.682288 / # export SHELL=/bin/sh
11035 00:44:23.688677 export SHELL=/bin/sh
11037 00:44:23.790418 / # . /lava-14368394/environment
11038 00:44:23.797426 . /lava-14368394/environment
11040 00:44:23.899172 / # /lava-14368394/bin/lava-test-runner /lava-14368394/0
11041 00:44:23.899817 Test shell timeout: 10s (minimum of the action and connection timeout)
11042 00:44:23.905704 /lava-14368394/bin/lava-test-runner /lava-14368394/0
11043 00:44:23.930548 <6>[ 13.353331] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11044 00:44:23.937115 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11045 00:44:23.940482 + cd /lava-14368394/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11046 00:44:23.944239 + cat uuid
11047 00:44:23.944754 + UUID=14368394_1.5.2.3.1
11048 00:44:23.947195 + set +x
11049 00:44:23.954053 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 14368394_1.5.2.3.1>
11050 00:44:23.954856 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 14368394_1.5.2.3.1
11051 00:44:23.955241 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (14368394_1.5.2.3.1)
11052 00:44:23.955658 Skipping test definition patterns.
11053 00:44:23.956689 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11054 00:44:23.960185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11055 00:44:23.960872 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11057 00:44:23.963245 device: /dev/video2
11058 00:44:23.973707 <4>[ 13.393004] use of bytesused == 0 is deprecated and will be removed in the future,
11059 00:44:23.976876 <4>[ 13.401010] use the actual size instead.
11060 00:44:23.998771 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11061 00:44:24.009689 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11062 00:44:24.016446
11063 00:44:24.029289 Compliance test for mtk-vcodec-enc device /dev/video2:
11064 00:44:24.035873
11065 00:44:24.045804 Driver Info:
11066 00:44:24.057273 Driver name : mtk-vcodec-enc
11067 00:44:24.071485 Card type : MT8192 video encoder
11068 00:44:24.082213 Bus info : platform:17020000.vcodec
11069 00:44:24.089850 Driver version : 6.1.92
11070 00:44:24.100773 Capabilities : 0x84204000
11071 00:44:24.112447 Video Memory-to-Memory Multiplanar
11072 00:44:24.128327 Streaming
11073 00:44:24.138722 Extended Pix Format
11074 00:44:24.155097 Device Capabilities
11075 00:44:24.166127 Device Caps : 0x04204000
11076 00:44:24.180144 Video Memory-to-Memory Multiplanar
11077 00:44:24.190724 Streaming
11078 00:44:24.202718 Extended Pix Format
11079 00:44:24.216976 Detected Stateful Encoder
11080 00:44:24.228196
11081 00:44:24.244110 Required ioctls:
11082 00:44:24.263552 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11083 00:44:24.264061 test VIDIOC_QUERYCAP: OK
11084 00:44:24.264659 Received signal: <TESTSET> START Required-ioctls
11085 00:44:24.265048 Starting test_set Required-ioctls
11086 00:44:24.291131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11087 00:44:24.291944 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11089 00:44:24.294434 test invalid ioctls: OK
11090 00:44:24.315547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11091 00:44:24.316058
11092 00:44:24.316642 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11094 00:44:24.327022 Allow for multiple opens:
11095 00:44:24.332971 <LAVA_SIGNAL_TESTSET STOP>
11096 00:44:24.333668 Received signal: <TESTSET> STOP
11097 00:44:24.334041 Closing test_set Required-ioctls
11098 00:44:24.343226 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11099 00:44:24.343987 Received signal: <TESTSET> START Allow-for-multiple-opens
11100 00:44:24.344348 Starting test_set Allow-for-multiple-opens
11101 00:44:24.346069 test second /dev/video2 open: OK
11102 00:44:24.367944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11103 00:44:24.368724 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11105 00:44:24.370515 test VIDIOC_QUERYCAP: OK
11106 00:44:24.393931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11107 00:44:24.394690 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11109 00:44:24.397052 test VIDIOC_G/S_PRIORITY: OK
11110 00:44:24.419161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11111 00:44:24.419907 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11113 00:44:24.422894 test for unlimited opens: OK
11114 00:44:24.444689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11115 00:44:24.445205
11116 00:44:24.445788 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11118 00:44:24.454442 Debug ioctls:
11119 00:44:24.463347 <LAVA_SIGNAL_TESTSET STOP>
11120 00:44:24.464114 Received signal: <TESTSET> STOP
11121 00:44:24.464480 Closing test_set Allow-for-multiple-opens
11122 00:44:24.474530 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11123 00:44:24.475289 Received signal: <TESTSET> START Debug-ioctls
11124 00:44:24.475645 Starting test_set Debug-ioctls
11125 00:44:24.477755 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11126 00:44:24.498858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11127 00:44:24.499597 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11129 00:44:24.505651 test VIDIOC_LOG_STATUS: OK (Not Supported)
11130 00:44:24.529315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11131 00:44:24.529844
11132 00:44:24.530417 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11134 00:44:24.540371 Input ioctls:
11135 00:44:24.547478 <LAVA_SIGNAL_TESTSET STOP>
11136 00:44:24.548239 Received signal: <TESTSET> STOP
11137 00:44:24.548602 Closing test_set Debug-ioctls
11138 00:44:24.556880 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11139 00:44:24.557648 Received signal: <TESTSET> START Input-ioctls
11140 00:44:24.558021 Starting test_set Input-ioctls
11141 00:44:24.559894 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11142 00:44:24.584223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11143 00:44:24.584966 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11145 00:44:24.587606 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11146 00:44:24.606207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11147 00:44:24.606956 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11149 00:44:24.612848 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11150 00:44:24.634554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11151 00:44:24.635233 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11153 00:44:24.641043 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11154 00:44:24.658672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11155 00:44:24.659551 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11157 00:44:24.662296 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11158 00:44:24.682840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11159 00:44:24.683519 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11161 00:44:24.685993 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11162 00:44:24.707271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11163 00:44:24.708067 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11165 00:44:24.710587 Inputs: 0 Audio Inputs: 0 Tuners: 0
11166 00:44:24.716970
11167 00:44:24.735525 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11168 00:44:24.757337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11169 00:44:24.758146 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11171 00:44:24.763473 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11172 00:44:24.781533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11173 00:44:24.782419 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11175 00:44:24.788010 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11176 00:44:24.806971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11177 00:44:24.807715 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11179 00:44:24.813518 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11180 00:44:24.832696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11181 00:44:24.833460 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11183 00:44:24.839128 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11184 00:44:24.857100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11185 00:44:24.857631
11186 00:44:24.858218 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11188 00:44:24.876204 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11189 00:44:24.902254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11190 00:44:24.903123 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11192 00:44:24.908941 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11193 00:44:24.931100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11194 00:44:24.931839 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11196 00:44:24.934412 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11197 00:44:24.953504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11198 00:44:24.954307 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11200 00:44:24.956462 test VIDIOC_G/S_EDID: OK (Not Supported)
11201 00:44:24.979034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11202 00:44:24.979537
11203 00:44:24.980111 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11205 00:44:24.989774 Control ioctls:
11206 00:44:24.995601 <LAVA_SIGNAL_TESTSET STOP>
11207 00:44:24.996352 Received signal: <TESTSET> STOP
11208 00:44:24.996713 Closing test_set Input-ioctls
11209 00:44:25.005741 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11210 00:44:25.006495 Received signal: <TESTSET> START Control-ioctls
11211 00:44:25.006859 Starting test_set Control-ioctls
11212 00:44:25.008388 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11213 00:44:25.032326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11214 00:44:25.032819 test VIDIOC_QUERYCTRL: OK
11215 00:44:25.033396 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11217 00:44:25.058348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11218 00:44:25.059101 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11220 00:44:25.061357 test VIDIOC_G/S_CTRL: OK
11221 00:44:25.083914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11222 00:44:25.084738 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11224 00:44:25.087480 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11225 00:44:25.108106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11226 00:44:25.108860 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11228 00:44:25.114424 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11229 00:44:25.122890 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11230 00:44:25.148123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11231 00:44:25.148878 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11233 00:44:25.151725 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11234 00:44:25.170416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11235 00:44:25.171158 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11237 00:44:25.173632 Standard Controls: 16 Private Controls: 0
11238 00:44:25.180221
11239 00:44:25.193973 Format ioctls:
11240 00:44:25.201315 <LAVA_SIGNAL_TESTSET STOP>
11241 00:44:25.202123 Received signal: <TESTSET> STOP
11242 00:44:25.202471 Closing test_set Control-ioctls
11243 00:44:25.211110 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11244 00:44:25.211863 Received signal: <TESTSET> START Format-ioctls
11245 00:44:25.212214 Starting test_set Format-ioctls
11246 00:44:25.214441 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11247 00:44:25.242274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11248 00:44:25.243011 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11250 00:44:25.245298 test VIDIOC_G/S_PARM: OK
11251 00:44:25.265417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11252 00:44:25.266227 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11254 00:44:25.268507 test VIDIOC_G_FBUF: OK (Not Supported)
11255 00:44:25.291941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11256 00:44:25.292692 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11258 00:44:25.294856 test VIDIOC_G_FMT: OK
11259 00:44:25.316923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11260 00:44:25.317668 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11262 00:44:25.319898 test VIDIOC_TRY_FMT: OK
11263 00:44:25.341327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11264 00:44:25.342128 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11266 00:44:25.347734 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11267 00:44:25.353536 test VIDIOC_S_FMT: FAIL
11268 00:44:25.382490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11269 00:44:25.383254 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11271 00:44:25.385472 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11272 00:44:25.412203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11273 00:44:25.412992 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11275 00:44:25.414742 test Cropping: OK
11276 00:44:25.434828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11277 00:44:25.435610 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11279 00:44:25.438020 test Composing: OK (Not Supported)
11280 00:44:25.460186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11281 00:44:25.461095 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11283 00:44:25.463174 test Scaling: OK (Not Supported)
11284 00:44:25.484072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11285 00:44:25.484586
11286 00:44:25.485173 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11288 00:44:25.500022 Codec ioctls:
11289 00:44:25.506851 <LAVA_SIGNAL_TESTSET STOP>
11290 00:44:25.507610 Received signal: <TESTSET> STOP
11291 00:44:25.507959 Closing test_set Format-ioctls
11292 00:44:25.516058 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11293 00:44:25.516817 Received signal: <TESTSET> START Codec-ioctls
11294 00:44:25.517171 Starting test_set Codec-ioctls
11295 00:44:25.519639 test VIDIOC_(TRY_)ENCODER_CMD: OK
11296 00:44:25.543377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11297 00:44:25.544117 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11299 00:44:25.550115 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11300 00:44:25.570257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11301 00:44:25.571016 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11303 00:44:25.577048 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11304 00:44:25.592726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11305 00:44:25.593237
11306 00:44:25.593861 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11308 00:44:25.601716 Buffer ioctls:
11309 00:44:25.608096 <LAVA_SIGNAL_TESTSET STOP>
11310 00:44:25.608891 Received signal: <TESTSET> STOP
11311 00:44:25.609245 Closing test_set Codec-ioctls
11312 00:44:25.617934 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11313 00:44:25.618703 Received signal: <TESTSET> START Buffer-ioctls
11314 00:44:25.619061 Starting test_set Buffer-ioctls
11315 00:44:25.620817 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11316 00:44:25.645451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11317 00:44:25.646228 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11319 00:44:25.648685 test CREATE_BUFS maximum buffers: OK
11320 00:44:25.668127 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11322 00:44:25.671729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11323 00:44:25.672249 test VIDIOC_EXPBUF: OK
11324 00:44:25.692597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11325 00:44:25.693386 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11327 00:44:25.695795 test Requests: OK (Not Supported)
11328 00:44:25.716329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11329 00:44:25.716824
11330 00:44:25.717662 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11332 00:44:25.726483 Test input 0:
11333 00:44:25.740708
11334 00:44:25.750822 Streaming ioctls:
11335 00:44:25.758029 <LAVA_SIGNAL_TESTSET STOP>
11336 00:44:25.758649 Received signal: <TESTSET> STOP
11337 00:44:25.758971 Closing test_set Buffer-ioctls
11338 00:44:25.767578 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11339 00:44:25.768205 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11340 00:44:25.768522 Starting test_set Streaming-ioctls_Test-input-0
11341 00:44:25.770722 test read/write: OK (Not Supported)
11342 00:44:25.793002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11343 00:44:25.793745 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11345 00:44:25.799662 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11346 00:44:25.810553 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11347 00:44:25.818498 test blocking wait: FAIL
11348 00:44:25.848376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11349 00:44:25.849135 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11351 00:44:25.854462 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11352 00:44:25.857909 test MMAP (select): FAIL
11353 00:44:25.886748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11354 00:44:25.887484 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11356 00:44:25.893662 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11357 00:44:25.898634 test MMAP (epoll): FAIL
11358 00:44:25.927009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11359 00:44:25.927853 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11361 00:44:25.933916 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11362 00:44:25.940959 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11363 00:44:25.948154 test USERPTR (select): FAIL
11364 00:44:25.979700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11365 00:44:25.980456 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11367 00:44:25.986149 test DMABUF: Cannot test, specify --expbuf-device
11368 00:44:25.991995
11369 00:44:26.013629 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11370 00:44:26.017364 <LAVA_TEST_RUNNER EXIT>
11371 00:44:26.018180 ok: lava_test_shell seems to have completed
11372 00:44:26.018576 Marking unfinished test run as failed
11374 00:44:26.023255 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls
Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11375 00:44:26.023978 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11376 00:44:26.024489 end: 3 lava-test-retry (duration 00:00:03) [common]
11377 00:44:26.025015 start: 4 finalize (timeout 00:08:07) [common]
11378 00:44:26.025540 start: 4.1 power-off (timeout 00:00:30) [common]
11379 00:44:26.026370 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11380 00:44:28.158192 >> Command sent successfully.
11381 00:44:28.172573 Returned 0 in 2 seconds
11382 00:44:28.273997 end: 4.1 power-off (duration 00:00:02) [common]
11384 00:44:28.275537 start: 4.2 read-feedback (timeout 00:08:05) [common]
11385 00:44:28.276815 Listened to connection for namespace 'common' for up to 1s
11386 00:44:29.277591 Finalising connection for namespace 'common'
11387 00:44:29.278287 Disconnecting from shell: Finalise
11388 00:44:29.278751 / #
11389 00:44:29.379751 end: 4.2 read-feedback (duration 00:00:01) [common]
11390 00:44:29.380449 end: 4 finalize (duration 00:00:03) [common]
11391 00:44:29.381179 Cleaning after the job
11392 00:44:29.381788 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/ramdisk
11393 00:44:29.403183 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/kernel
11394 00:44:29.433390 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/dtb
11395 00:44:29.433688 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368394/tftp-deploy-qtxpfq2e/modules
11396 00:44:29.440854 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368394
11397 00:44:29.501322 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368394
11398 00:44:29.501497 Job finished correctly