Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:44:26.473306 lava-dispatcher, installed at version: 2024.03
2 00:44:26.473532 start: 0 validate
3 00:44:26.473644 Start time: 2024-06-16 00:44:26.473639+00:00 (UTC)
4 00:44:26.473774 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:44:26.473907 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:44:26.728960 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:44:26.729691 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:44:26.985384 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:44:26.986196 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:44:27.240680 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:44:27.241538 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:44:27.504335 validate duration: 1.03
14 00:44:27.504573 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:44:27.504675 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:44:27.504760 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:44:27.504914 Not decompressing ramdisk as can be used compressed.
18 00:44:27.505008 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 00:44:27.505089 saving as /var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/ramdisk/rootfs.cpio.gz
20 00:44:27.505164 total size: 28105535 (26 MB)
21 00:44:27.506130 progress 0 % (0 MB)
22 00:44:27.513555 progress 5 % (1 MB)
23 00:44:27.521134 progress 10 % (2 MB)
24 00:44:27.528774 progress 15 % (4 MB)
25 00:44:27.536204 progress 20 % (5 MB)
26 00:44:27.543436 progress 25 % (6 MB)
27 00:44:27.550842 progress 30 % (8 MB)
28 00:44:27.557991 progress 35 % (9 MB)
29 00:44:27.565317 progress 40 % (10 MB)
30 00:44:27.572357 progress 45 % (12 MB)
31 00:44:27.579606 progress 50 % (13 MB)
32 00:44:27.586651 progress 55 % (14 MB)
33 00:44:27.593665 progress 60 % (16 MB)
34 00:44:27.600729 progress 65 % (17 MB)
35 00:44:27.607837 progress 70 % (18 MB)
36 00:44:27.614912 progress 75 % (20 MB)
37 00:44:27.621972 progress 80 % (21 MB)
38 00:44:27.629059 progress 85 % (22 MB)
39 00:44:27.636103 progress 90 % (24 MB)
40 00:44:27.643214 progress 95 % (25 MB)
41 00:44:27.650528 progress 100 % (26 MB)
42 00:44:27.650743 26 MB downloaded in 0.15 s (184.13 MB/s)
43 00:44:27.650902 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:44:27.651129 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:44:27.651210 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:44:27.651286 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:44:27.651437 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:44:27.651526 saving as /var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/kernel/Image
50 00:44:27.651608 total size: 54813184 (52 MB)
51 00:44:27.651691 No compression specified
52 00:44:27.653110 progress 0 % (0 MB)
53 00:44:27.667166 progress 5 % (2 MB)
54 00:44:27.681055 progress 10 % (5 MB)
55 00:44:27.694687 progress 15 % (7 MB)
56 00:44:27.708456 progress 20 % (10 MB)
57 00:44:27.722209 progress 25 % (13 MB)
58 00:44:27.735748 progress 30 % (15 MB)
59 00:44:27.749970 progress 35 % (18 MB)
60 00:44:27.764218 progress 40 % (20 MB)
61 00:44:27.777967 progress 45 % (23 MB)
62 00:44:27.791770 progress 50 % (26 MB)
63 00:44:27.805468 progress 55 % (28 MB)
64 00:44:27.819010 progress 60 % (31 MB)
65 00:44:27.832649 progress 65 % (34 MB)
66 00:44:27.846384 progress 70 % (36 MB)
67 00:44:27.860548 progress 75 % (39 MB)
68 00:44:27.874836 progress 80 % (41 MB)
69 00:44:27.888569 progress 85 % (44 MB)
70 00:44:27.902259 progress 90 % (47 MB)
71 00:44:27.915934 progress 95 % (49 MB)
72 00:44:27.929219 progress 100 % (52 MB)
73 00:44:27.929431 52 MB downloaded in 0.28 s (188.16 MB/s)
74 00:44:27.929580 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:44:27.929788 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:44:27.929871 start: 1.3 download-retry (timeout 00:10:00) [common]
78 00:44:27.929951 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 00:44:27.930076 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:44:27.930142 saving as /var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/dtb/mt8192-asurada-spherion-r0.dtb
81 00:44:27.930197 total size: 47258 (0 MB)
82 00:44:27.930289 No compression specified
83 00:44:27.931302 progress 69 % (0 MB)
84 00:44:27.931559 progress 100 % (0 MB)
85 00:44:27.931708 0 MB downloaded in 0.00 s (29.87 MB/s)
86 00:44:27.931820 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:44:27.932019 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:44:27.932100 start: 1.4 download-retry (timeout 00:10:00) [common]
90 00:44:27.932177 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 00:44:27.932279 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:44:27.932340 saving as /var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/modules/modules.tar
93 00:44:27.932392 total size: 8608736 (8 MB)
94 00:44:27.932445 Using unxz to decompress xz
95 00:44:27.933746 progress 0 % (0 MB)
96 00:44:27.952159 progress 5 % (0 MB)
97 00:44:27.978119 progress 10 % (0 MB)
98 00:44:28.005626 progress 15 % (1 MB)
99 00:44:28.028539 progress 20 % (1 MB)
100 00:44:28.051624 progress 25 % (2 MB)
101 00:44:28.074752 progress 30 % (2 MB)
102 00:44:28.098589 progress 35 % (2 MB)
103 00:44:28.124443 progress 40 % (3 MB)
104 00:44:28.146726 progress 45 % (3 MB)
105 00:44:28.170556 progress 50 % (4 MB)
106 00:44:28.194786 progress 55 % (4 MB)
107 00:44:28.218550 progress 60 % (4 MB)
108 00:44:28.242063 progress 65 % (5 MB)
109 00:44:28.266139 progress 70 % (5 MB)
110 00:44:28.291157 progress 75 % (6 MB)
111 00:44:28.316315 progress 80 % (6 MB)
112 00:44:28.340086 progress 85 % (7 MB)
113 00:44:28.364873 progress 90 % (7 MB)
114 00:44:28.389255 progress 95 % (7 MB)
115 00:44:28.413208 progress 100 % (8 MB)
116 00:44:28.418616 8 MB downloaded in 0.49 s (16.89 MB/s)
117 00:44:28.418769 end: 1.4.1 http-download (duration 00:00:00) [common]
119 00:44:28.418980 end: 1.4 download-retry (duration 00:00:00) [common]
120 00:44:28.419060 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:44:28.419137 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:44:28.419211 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:44:28.419282 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:44:28.419440 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c
125 00:44:28.419556 makedir: /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin
126 00:44:28.419645 makedir: /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/tests
127 00:44:28.419730 makedir: /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/results
128 00:44:28.419814 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-add-keys
129 00:44:28.419939 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-add-sources
130 00:44:28.420052 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-background-process-start
131 00:44:28.420165 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-background-process-stop
132 00:44:28.420286 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-common-functions
133 00:44:28.420398 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-echo-ipv4
134 00:44:28.420509 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-install-packages
135 00:44:28.420619 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-installed-packages
136 00:44:28.420728 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-os-build
137 00:44:28.420836 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-probe-channel
138 00:44:28.420946 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-probe-ip
139 00:44:28.421056 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-target-ip
140 00:44:28.421166 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-target-mac
141 00:44:28.421275 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-target-storage
142 00:44:28.421426 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-test-case
143 00:44:28.421614 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-test-event
144 00:44:28.421722 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-test-feedback
145 00:44:28.421831 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-test-raise
146 00:44:28.421940 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-test-reference
147 00:44:28.422049 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-test-runner
148 00:44:28.422157 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-test-set
149 00:44:28.422303 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-test-shell
150 00:44:28.422415 Updating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-install-packages (oe)
151 00:44:28.422549 Updating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/bin/lava-installed-packages (oe)
152 00:44:28.422657 Creating /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/environment
153 00:44:28.422740 LAVA metadata
154 00:44:28.422803 - LAVA_JOB_ID=14368417
155 00:44:28.422858 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:44:28.422946 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:44:28.423002 skipped lava-vland-overlay
158 00:44:28.423065 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:44:28.423134 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:44:28.423187 skipped lava-multinode-overlay
161 00:44:28.423252 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:44:28.423320 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:44:28.423380 Loading test definitions
164 00:44:28.423454 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:44:28.423512 Using /lava-14368417 at stage 0
166 00:44:28.423799 uuid=14368417_1.5.2.3.1 testdef=None
167 00:44:28.423879 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:44:28.423953 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:44:28.424379 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:44:28.424577 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:44:28.425119 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:44:28.425326 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:44:28.426770 runner path: /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/0/tests/0_v4l2-compliance-uvc test_uuid 14368417_1.5.2.3.1
176 00:44:28.426912 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:44:28.427103 Creating lava-test-runner.conf files
179 00:44:28.427159 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368417/lava-overlay-roo7sr6c/lava-14368417/0 for stage 0
180 00:44:28.427237 - 0_v4l2-compliance-uvc
181 00:44:28.427325 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:44:28.427401 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:44:28.433410 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:44:28.433510 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:44:28.433588 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:44:28.433663 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:44:28.433739 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:44:29.297985 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:44:29.298135 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 00:44:29.298274 extracting modules file /var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368417/extract-overlay-ramdisk-sywuhu7o/ramdisk
191 00:44:29.544999 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:44:29.545131 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 00:44:29.545212 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368417/compress-overlay-d5qpmuxz/overlay-1.5.2.4.tar.gz to ramdisk
194 00:44:29.545272 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368417/compress-overlay-d5qpmuxz/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368417/extract-overlay-ramdisk-sywuhu7o/ramdisk
195 00:44:29.552639 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:44:29.552762 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 00:44:29.552869 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:44:29.552985 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 00:44:29.553079 Building ramdisk /var/lib/lava/dispatcher/tmp/14368417/extract-overlay-ramdisk-sywuhu7o/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368417/extract-overlay-ramdisk-sywuhu7o/ramdisk
200 00:44:30.264524 >> 275951 blocks
201 00:44:34.445969 rename /var/lib/lava/dispatcher/tmp/14368417/extract-overlay-ramdisk-sywuhu7o/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/ramdisk/ramdisk.cpio.gz
202 00:44:34.446148 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 00:44:34.446269 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 00:44:34.446379 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 00:44:34.446480 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/kernel/Image']
206 00:44:47.641039 Returned 0 in 13 seconds
207 00:44:47.741927 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/kernel/image.itb
208 00:44:48.510838 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:44:48.510978 output: Created: Sun Jun 16 01:44:48 2024
210 00:44:48.511045 output: Image 0 (kernel-1)
211 00:44:48.511107 output: Description:
212 00:44:48.511166 output: Created: Sun Jun 16 01:44:48 2024
213 00:44:48.511225 output: Type: Kernel Image
214 00:44:48.511283 output: Compression: lzma compressed
215 00:44:48.511344 output: Data Size: 13126376 Bytes = 12818.73 KiB = 12.52 MiB
216 00:44:48.511400 output: Architecture: AArch64
217 00:44:48.511462 output: OS: Linux
218 00:44:48.511561 output: Load Address: 0x00000000
219 00:44:48.511616 output: Entry Point: 0x00000000
220 00:44:48.511668 output: Hash algo: crc32
221 00:44:48.511720 output: Hash value: c791a20a
222 00:44:48.511770 output: Image 1 (fdt-1)
223 00:44:48.511818 output: Description: mt8192-asurada-spherion-r0
224 00:44:48.511868 output: Created: Sun Jun 16 01:44:48 2024
225 00:44:48.511918 output: Type: Flat Device Tree
226 00:44:48.511965 output: Compression: uncompressed
227 00:44:48.512012 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:44:48.512060 output: Architecture: AArch64
229 00:44:48.512107 output: Hash algo: crc32
230 00:44:48.512153 output: Hash value: 0f8e4d2e
231 00:44:48.512201 output: Image 2 (ramdisk-1)
232 00:44:48.512249 output: Description: unavailable
233 00:44:48.512295 output: Created: Sun Jun 16 01:44:48 2024
234 00:44:48.512343 output: Type: RAMDisk Image
235 00:44:48.512390 output: Compression: uncompressed
236 00:44:48.512438 output: Data Size: 41215728 Bytes = 40249.73 KiB = 39.31 MiB
237 00:44:48.512485 output: Architecture: AArch64
238 00:44:48.512532 output: OS: Linux
239 00:44:48.512578 output: Load Address: unavailable
240 00:44:48.512625 output: Entry Point: unavailable
241 00:44:48.512673 output: Hash algo: crc32
242 00:44:48.512719 output: Hash value: d726b3c4
243 00:44:48.512765 output: Default Configuration: 'conf-1'
244 00:44:48.512812 output: Configuration 0 (conf-1)
245 00:44:48.512859 output: Description: mt8192-asurada-spherion-r0
246 00:44:48.512907 output: Kernel: kernel-1
247 00:44:48.512954 output: Init Ramdisk: ramdisk-1
248 00:44:48.513002 output: FDT: fdt-1
249 00:44:48.513050 output: Loadables: kernel-1
250 00:44:48.513096 output:
251 00:44:48.513225 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 00:44:48.513309 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 00:44:48.513399 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 00:44:48.513480 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 00:44:48.513547 No LXC device requested
256 00:44:48.513618 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:44:48.513698 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 00:44:48.513767 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:44:48.513828 Checking files for TFTP limit of 4294967296 bytes.
260 00:44:48.514277 end: 1 tftp-deploy (duration 00:00:21) [common]
261 00:44:48.514374 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:44:48.514452 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:44:48.514558 substitutions:
264 00:44:48.514617 - {DTB}: 14368417/tftp-deploy-fnw4d_c7/dtb/mt8192-asurada-spherion-r0.dtb
265 00:44:48.514676 - {INITRD}: 14368417/tftp-deploy-fnw4d_c7/ramdisk/ramdisk.cpio.gz
266 00:44:48.514728 - {KERNEL}: 14368417/tftp-deploy-fnw4d_c7/kernel/Image
267 00:44:48.514778 - {LAVA_MAC}: None
268 00:44:48.514827 - {PRESEED_CONFIG}: None
269 00:44:48.514877 - {PRESEED_LOCAL}: None
270 00:44:48.514925 - {RAMDISK}: 14368417/tftp-deploy-fnw4d_c7/ramdisk/ramdisk.cpio.gz
271 00:44:48.514980 - {ROOT_PART}: None
272 00:44:48.515029 - {ROOT}: None
273 00:44:48.515077 - {SERVER_IP}: 192.168.201.1
274 00:44:48.515125 - {TEE}: None
275 00:44:48.515173 Parsed boot commands:
276 00:44:48.515221 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:44:48.515366 Parsed boot commands: tftpboot 192.168.201.1 14368417/tftp-deploy-fnw4d_c7/kernel/image.itb 14368417/tftp-deploy-fnw4d_c7/kernel/cmdline
278 00:44:48.515447 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:44:48.515523 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:44:48.515599 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:44:48.515677 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:44:48.515736 Not connected, no need to disconnect.
283 00:44:48.515801 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:44:48.515870 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:44:48.515931 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 00:44:48.519213 Setting prompt string to ['lava-test: # ']
287 00:44:48.519607 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:44:48.519809 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:44:48.519899 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:44:48.519984 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:44:48.520143 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-4']
292 00:45:02.253046 Returned 0 in 13 seconds
293 00:45:02.354236 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 00:45:02.355616 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 00:45:02.356340 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 00:45:02.356918 Setting prompt string to 'Starting depthcharge on Spherion...'
298 00:45:02.357285 Changing prompt to 'Starting depthcharge on Spherion...'
299 00:45:02.357674 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 00:45:02.359680 [Enter `^Ec?' for help]
301 00:45:02.360131
302 00:45:02.360499
303 00:45:02.360838 F0: 102B 0000
304 00:45:02.361171
305 00:45:02.361570 F3: 1001 0000 [0200]
306 00:45:02.361927
307 00:45:02.362290 F3: 1001 0000
308 00:45:02.362672
309 00:45:02.362973 F7: 102D 0000
310 00:45:02.363263
311 00:45:02.363542 F1: 0000 0000
312 00:45:02.363826
313 00:45:02.364110 V0: 0000 0000 [0001]
314 00:45:02.364393
315 00:45:02.364673 00: 0007 8000
316 00:45:02.364951
317 00:45:02.365219 01: 0000 0000
318 00:45:02.365665
319 00:45:02.365969 BP: 0C00 0209 [0000]
320 00:45:02.366288
321 00:45:02.366686 G0: 1182 0000
322 00:45:02.366966
323 00:45:02.367241 EC: 0000 0021 [4000]
324 00:45:02.367529
325 00:45:02.367799 S7: 0000 0000 [0000]
326 00:45:02.368072
327 00:45:02.368342 CC: 0000 0000 [0001]
328 00:45:02.368613
329 00:45:02.368879 T0: 0000 0040 [010F]
330 00:45:02.369173
331 00:45:02.369592 Jump to BL
332 00:45:02.369877
333 00:45:02.370153
334 00:45:02.370472
335 00:45:02.370747 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 00:45:02.371038 ARM64: Exception handlers installed.
337 00:45:02.371320 ARM64: Testing exception
338 00:45:02.371695 ARM64: Done test exception
339 00:45:02.371981 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 00:45:02.372304 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 00:45:02.372672 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 00:45:02.372957 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 00:45:02.373237 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 00:45:02.373511 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 00:45:02.373784 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 00:45:02.374056 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 00:45:02.374373 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 00:45:02.374661 WDT: Last reset was cold boot
349 00:45:02.374908 SPI1(PAD0) initialized at 2873684 Hz
350 00:45:02.375157 SPI5(PAD0) initialized at 992727 Hz
351 00:45:02.375408 VBOOT: Loading verstage.
352 00:45:02.375763 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 00:45:02.376032 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 00:45:02.376285 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 00:45:02.376537 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 00:45:02.376883 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 00:45:02.377143 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 00:45:02.377397 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 00:45:02.377645
360 00:45:02.377888
361 00:45:02.378133 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 00:45:02.378425 ARM64: Exception handlers installed.
363 00:45:02.378678 ARM64: Testing exception
364 00:45:02.379052 ARM64: Done test exception
365 00:45:02.379315 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 00:45:02.379572 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 00:45:02.379821 Probing TPM: . done!
368 00:45:02.380065 TPM ready after 0 ms
369 00:45:02.380314 Connected to device vid:did:rid of 1ae0:0028:00
370 00:45:02.380564 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
371 00:45:02.380818 Initialized TPM device CR50 revision 0
372 00:45:02.381066 tlcl_send_startup: Startup return code is 0
373 00:45:02.381315 TPM: setup succeeded
374 00:45:02.381565 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 00:45:02.381815 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 00:45:02.382285 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 00:45:02.382563 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:45:02.382817 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 00:45:02.383072 in-header: 03 07 00 00 08 00 00 00
380 00:45:02.383321 in-data: aa e4 47 04 13 02 00 00
381 00:45:02.383571 Chrome EC: UHEPI supported
382 00:45:02.383817 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 00:45:02.384068 in-header: 03 a9 00 00 08 00 00 00
384 00:45:02.384391 in-data: 84 60 60 08 00 00 00 00
385 00:45:02.384736 Phase 1
386 00:45:02.384992 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 00:45:02.385247 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 00:45:02.385486 VB2:vb2_check_recovery() Recovery was requested manually
389 00:45:02.385747 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 00:45:02.385935 Recovery requested (1009000e)
391 00:45:02.386114 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 00:45:02.386336 tlcl_extend: response is 0
393 00:45:02.386520 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 00:45:02.386755 tlcl_extend: response is 0
395 00:45:02.386995 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 00:45:02.387188 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 00:45:02.387367 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 00:45:02.387542
399 00:45:02.387715
400 00:45:02.387892 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 00:45:02.388075 ARM64: Exception handlers installed.
402 00:45:02.388252 ARM64: Testing exception
403 00:45:02.388437 ARM64: Done test exception
404 00:45:02.388613 pmic_efuse_setting: Set efuses in 11 msecs
405 00:45:02.388869 pmwrap_interface_init: Select PMIF_VLD_RDY
406 00:45:02.389135 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 00:45:02.389326 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 00:45:02.389797 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 00:45:02.390014 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 00:45:02.390194 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 00:45:02.390421 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 00:45:02.390558 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 00:45:02.390693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 00:45:02.390826 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 00:45:02.390960 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 00:45:02.391092 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 00:45:02.391225 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 00:45:02.391357 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 00:45:02.391489 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 00:45:02.391622 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 00:45:02.391757 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 00:45:02.391890 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 00:45:02.392023 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 00:45:02.392157 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 00:45:02.392289 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 00:45:02.392420 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 00:45:02.392552 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 00:45:02.392685 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 00:45:02.392818 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 00:45:02.392950 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 00:45:02.393083 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 00:45:02.393216 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 00:45:02.393347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 00:45:02.393479 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 00:45:02.393612 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 00:45:02.393744 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 00:45:02.393877 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 00:45:02.394011 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 00:45:02.394142 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 00:45:02.394288 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 00:45:02.394421 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 00:45:02.394552 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 00:45:02.394685 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 00:45:02.394817 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 00:45:02.394950 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 00:45:02.395082 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 00:45:02.395214 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 00:45:02.395345 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 00:45:02.395479 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 00:45:02.395585 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 00:45:02.395689 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 00:45:02.395795 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 00:45:02.395901 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 00:45:02.396008 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 00:45:02.396113 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 00:45:02.396219 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 00:45:02.396326 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 00:45:02.396435 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 00:45:02.396543 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 00:45:02.396650 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 00:45:02.396758 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 00:45:02.396886 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 00:45:02.396997 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 00:45:02.397105 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:45:02.397212 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x4
466 00:45:02.397319 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 00:45:02.397425 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 00:45:02.397532 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 00:45:02.397640 [RTC]rtc_get_frequency_meter,154: input=15, output=764
470 00:45:02.397748 [RTC]rtc_get_frequency_meter,154: input=23, output=950
471 00:45:02.397855 [RTC]rtc_get_frequency_meter,154: input=19, output=858
472 00:45:02.397961 [RTC]rtc_get_frequency_meter,154: input=17, output=811
473 00:45:02.398068 [RTC]rtc_get_frequency_meter,154: input=16, output=787
474 00:45:02.398176 [RTC]rtc_get_frequency_meter,154: input=16, output=788
475 00:45:02.398300 [RTC]rtc_get_frequency_meter,154: input=17, output=811
476 00:45:02.398408 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 00:45:02.398515 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 00:45:02.398849 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 00:45:02.399055 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 00:45:02.399285 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 00:45:02.399513 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 00:45:02.399738 ADC[4]: Raw value=670063 ID=5
483 00:45:02.399910 ADC[3]: Raw value=212917 ID=1
484 00:45:02.400082 RAM Code: 0x51
485 00:45:02.400267 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 00:45:02.400447 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 00:45:02.400592 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
488 00:45:02.400735 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
489 00:45:02.400876 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 00:45:02.401018 in-header: 03 07 00 00 08 00 00 00
491 00:45:02.401159 in-data: aa e4 47 04 13 02 00 00
492 00:45:02.401300 Chrome EC: UHEPI supported
493 00:45:02.401442 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 00:45:02.401585 in-header: 03 a9 00 00 08 00 00 00
495 00:45:02.401725 in-data: 84 60 60 08 00 00 00 00
496 00:45:02.401871 MRC: failed to locate region type 0.
497 00:45:02.402015 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 00:45:02.402169 DRAM-K: Running full calibration
499 00:45:02.402297 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
500 00:45:02.402391 header.status = 0x0
501 00:45:02.402480 header.version = 0x6 (expected: 0x6)
502 00:45:02.402569 header.size = 0xd00 (expected: 0xd00)
503 00:45:02.402659 header.flags = 0x0
504 00:45:02.402749 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 00:45:02.402841 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 00:45:02.402931 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 00:45:02.403021 dram_init: ddr_geometry: 0
508 00:45:02.403110 [EMI] MDL number = 0
509 00:45:02.403198 [EMI] Get MDL freq = 0
510 00:45:02.403286 dram_init: ddr_type: 0
511 00:45:02.403378 is_discrete_lpddr4: 1
512 00:45:02.403467 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 00:45:02.403556
514 00:45:02.403645
515 00:45:02.403734 [Bian_co] ETT version 0.0.0.1
516 00:45:02.403824 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
517 00:45:02.403913
518 00:45:02.404001 dramc_set_vcore_voltage set vcore to 650000
519 00:45:02.404091 Read voltage for 800, 4
520 00:45:02.404178 Vio18 = 0
521 00:45:02.404265 Vcore = 650000
522 00:45:02.404354 Vdram = 0
523 00:45:02.404441 Vddq = 0
524 00:45:02.404529 Vmddr = 0
525 00:45:02.404617 dram_init: config_dvfs: 1
526 00:45:02.404705 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 00:45:02.404794 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 00:45:02.404883 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 00:45:02.404972 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 00:45:02.405061 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 00:45:02.405149 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 00:45:02.405237 MEM_TYPE=3, freq_sel=18
533 00:45:02.405325 sv_algorithm_assistance_LP4_1600
534 00:45:02.405419 ============ PULL DRAM RESETB DOWN ============
535 00:45:02.405521 ========== PULL DRAM RESETB DOWN end =========
536 00:45:02.405598 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 00:45:02.405676 ===================================
538 00:45:02.405752 LPDDR4 DRAM CONFIGURATION
539 00:45:02.405827 ===================================
540 00:45:02.405903 EX_ROW_EN[0] = 0x0
541 00:45:02.405978 EX_ROW_EN[1] = 0x0
542 00:45:02.406054 LP4Y_EN = 0x0
543 00:45:02.406131 WORK_FSP = 0x0
544 00:45:02.406206 WL = 0x2
545 00:45:02.406292 RL = 0x2
546 00:45:02.406368 BL = 0x2
547 00:45:02.406443 RPST = 0x0
548 00:45:02.406519 RD_PRE = 0x0
549 00:45:02.406593 WR_PRE = 0x1
550 00:45:02.406667 WR_PST = 0x0
551 00:45:02.406742 DBI_WR = 0x0
552 00:45:02.406818 DBI_RD = 0x0
553 00:45:02.406894 OTF = 0x1
554 00:45:02.406971 ===================================
555 00:45:02.407048 ===================================
556 00:45:02.407134 ANA top config
557 00:45:02.407210 ===================================
558 00:45:02.407288 DLL_ASYNC_EN = 0
559 00:45:02.407373 ALL_SLAVE_EN = 1
560 00:45:02.407450 NEW_RANK_MODE = 1
561 00:45:02.407527 DLL_IDLE_MODE = 1
562 00:45:02.407604 LP45_APHY_COMB_EN = 1
563 00:45:02.407679 TX_ODT_DIS = 1
564 00:45:02.407756 NEW_8X_MODE = 1
565 00:45:02.407831 ===================================
566 00:45:02.407907 ===================================
567 00:45:02.407983 data_rate = 1600
568 00:45:02.408058 CKR = 1
569 00:45:02.408133 DQ_P2S_RATIO = 8
570 00:45:02.408209 ===================================
571 00:45:02.408284 CA_P2S_RATIO = 8
572 00:45:02.408361 DQ_CA_OPEN = 0
573 00:45:02.408436 DQ_SEMI_OPEN = 0
574 00:45:02.408512 CA_SEMI_OPEN = 0
575 00:45:02.408587 CA_FULL_RATE = 0
576 00:45:02.408673 DQ_CKDIV4_EN = 1
577 00:45:02.408750 CA_CKDIV4_EN = 1
578 00:45:02.408826 CA_PREDIV_EN = 0
579 00:45:02.408901 PH8_DLY = 0
580 00:45:02.408977 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 00:45:02.409054 DQ_AAMCK_DIV = 4
582 00:45:02.409131 CA_AAMCK_DIV = 4
583 00:45:02.409207 CA_ADMCK_DIV = 4
584 00:45:02.409282 DQ_TRACK_CA_EN = 0
585 00:45:02.409358 CA_PICK = 800
586 00:45:02.409435 CA_MCKIO = 800
587 00:45:02.409511 MCKIO_SEMI = 0
588 00:45:02.409586 PLL_FREQ = 3068
589 00:45:02.409663 DQ_UI_PI_RATIO = 32
590 00:45:02.409738 CA_UI_PI_RATIO = 0
591 00:45:02.409814 ===================================
592 00:45:02.409890 ===================================
593 00:45:02.409966 memory_type:LPDDR4
594 00:45:02.410060 GP_NUM : 10
595 00:45:02.410137 SRAM_EN : 1
596 00:45:02.410222 MD32_EN : 0
597 00:45:02.410300 ===================================
598 00:45:02.410605 [ANA_INIT] >>>>>>>>>>>>>>
599 00:45:02.410732 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 00:45:02.410877 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 00:45:02.411012 ===================================
602 00:45:02.411148 data_rate = 1600,PCW = 0X7600
603 00:45:02.411275 ===================================
604 00:45:02.411384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 00:45:02.411493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 00:45:02.411601 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:45:02.411709 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 00:45:02.411816 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 00:45:02.411920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:45:02.411991 [ANA_INIT] flow start
611 00:45:02.412059 [ANA_INIT] PLL >>>>>>>>
612 00:45:02.412125 [ANA_INIT] PLL <<<<<<<<
613 00:45:02.412191 [ANA_INIT] MIDPI >>>>>>>>
614 00:45:02.412258 [ANA_INIT] MIDPI <<<<<<<<
615 00:45:02.412325 [ANA_INIT] DLL >>>>>>>>
616 00:45:02.412400 [ANA_INIT] flow end
617 00:45:02.412468 ============ LP4 DIFF to SE enter ============
618 00:45:02.412536 ============ LP4 DIFF to SE exit ============
619 00:45:02.412617 [ANA_INIT] <<<<<<<<<<<<<
620 00:45:02.412685 [Flow] Enable top DCM control >>>>>
621 00:45:02.412752 [Flow] Enable top DCM control <<<<<
622 00:45:02.412819 Enable DLL master slave shuffle
623 00:45:02.412887 ==============================================================
624 00:45:02.412955 Gating Mode config
625 00:45:02.413022 ==============================================================
626 00:45:02.413089 Config description:
627 00:45:02.413156 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 00:45:02.413224 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 00:45:02.413292 SELPH_MODE 0: By rank 1: By Phase
630 00:45:02.413358 ==============================================================
631 00:45:02.413426 GAT_TRACK_EN = 1
632 00:45:02.413494 RX_GATING_MODE = 2
633 00:45:02.413561 RX_GATING_TRACK_MODE = 2
634 00:45:02.413627 SELPH_MODE = 1
635 00:45:02.413694 PICG_EARLY_EN = 1
636 00:45:02.413760 VALID_LAT_VALUE = 1
637 00:45:02.413827 ==============================================================
638 00:45:02.413894 Enter into Gating configuration >>>>
639 00:45:02.413961 Exit from Gating configuration <<<<
640 00:45:02.414027 Enter into DVFS_PRE_config >>>>>
641 00:45:02.414095 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 00:45:02.414169 Exit from DVFS_PRE_config <<<<<
643 00:45:02.414249 Enter into PICG configuration >>>>
644 00:45:02.414318 Exit from PICG configuration <<<<
645 00:45:02.414386 [RX_INPUT] configuration >>>>>
646 00:45:02.414453 [RX_INPUT] configuration <<<<<
647 00:45:02.414519 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 00:45:02.414586 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 00:45:02.414654 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 00:45:02.414721 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 00:45:02.414789 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 00:45:02.414856 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 00:45:02.414923 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 00:45:02.414990 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 00:45:02.415056 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 00:45:02.415122 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 00:45:02.415189 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 00:45:02.415256 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 00:45:02.415334 ===================================
660 00:45:02.415403 LPDDR4 DRAM CONFIGURATION
661 00:45:02.415481 ===================================
662 00:45:02.415541 EX_ROW_EN[0] = 0x0
663 00:45:02.415600 EX_ROW_EN[1] = 0x0
664 00:45:02.415658 LP4Y_EN = 0x0
665 00:45:02.415717 WORK_FSP = 0x0
666 00:45:02.415776 WL = 0x2
667 00:45:02.415835 RL = 0x2
668 00:45:02.415894 BL = 0x2
669 00:45:02.415954 RPST = 0x0
670 00:45:02.416012 RD_PRE = 0x0
671 00:45:02.416070 WR_PRE = 0x1
672 00:45:02.416129 WR_PST = 0x0
673 00:45:02.416188 DBI_WR = 0x0
674 00:45:02.416247 DBI_RD = 0x0
675 00:45:02.416306 OTF = 0x1
676 00:45:02.416365 ===================================
677 00:45:02.416425 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 00:45:02.416485 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 00:45:02.416545 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 00:45:02.416605 ===================================
681 00:45:02.416664 LPDDR4 DRAM CONFIGURATION
682 00:45:02.416723 ===================================
683 00:45:02.416782 EX_ROW_EN[0] = 0x10
684 00:45:02.416841 EX_ROW_EN[1] = 0x0
685 00:45:02.416899 LP4Y_EN = 0x0
686 00:45:02.416959 WORK_FSP = 0x0
687 00:45:02.417019 WL = 0x2
688 00:45:02.417078 RL = 0x2
689 00:45:02.417137 BL = 0x2
690 00:45:02.417195 RPST = 0x0
691 00:45:02.417254 RD_PRE = 0x0
692 00:45:02.417313 WR_PRE = 0x1
693 00:45:02.417371 WR_PST = 0x0
694 00:45:02.417435 DBI_WR = 0x0
695 00:45:02.417496 DBI_RD = 0x0
696 00:45:02.417554 OTF = 0x1
697 00:45:02.417614 ===================================
698 00:45:02.417687 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 00:45:02.417749 nWR fixed to 40
700 00:45:02.417809 [ModeRegInit_LP4] CH0 RK0
701 00:45:02.417869 [ModeRegInit_LP4] CH0 RK1
702 00:45:02.417928 [ModeRegInit_LP4] CH1 RK0
703 00:45:02.417988 [ModeRegInit_LP4] CH1 RK1
704 00:45:02.418046 match AC timing 12
705 00:45:02.418104 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
706 00:45:02.418164 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 00:45:02.418438 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 00:45:02.418547 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 00:45:02.418659 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 00:45:02.418755 [EMI DOE] emi_dcm 0
711 00:45:02.418851 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 00:45:02.418945 ==
713 00:45:02.419040 Dram Type= 6, Freq= 0, CH_0, rank 0
714 00:45:02.419135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
715 00:45:02.419230 ==
716 00:45:02.419325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 00:45:02.419421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 00:45:02.419516 [CA 0] Center 37 (7~68) winsize 62
719 00:45:02.419611 [CA 1] Center 37 (7~68) winsize 62
720 00:45:02.419706 [CA 2] Center 35 (5~66) winsize 62
721 00:45:02.419800 [CA 3] Center 35 (5~66) winsize 62
722 00:45:02.419895 [CA 4] Center 34 (3~65) winsize 63
723 00:45:02.419989 [CA 5] Center 33 (3~64) winsize 62
724 00:45:02.420082
725 00:45:02.420176 [CmdBusTrainingLP45] Vref(ca) range 1: 32
726 00:45:02.420270
727 00:45:02.420364 [CATrainingPosCal] consider 1 rank data
728 00:45:02.420467 u2DelayCellTimex100 = 270/100 ps
729 00:45:02.420552 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 00:45:02.420637 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 00:45:02.420722 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 00:45:02.420807 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
733 00:45:02.420892 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
734 00:45:02.420977 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 00:45:02.421061
736 00:45:02.421146 CA PerBit enable=1, Macro0, CA PI delay=33
737 00:45:02.421230
738 00:45:02.421314 [CBTSetCACLKResult] CA Dly = 33
739 00:45:02.421398 CS Dly: 5 (0~36)
740 00:45:02.421482 ==
741 00:45:02.421567 Dram Type= 6, Freq= 0, CH_0, rank 1
742 00:45:02.421652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
743 00:45:02.421737 ==
744 00:45:02.421823 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 00:45:02.421909 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 00:45:02.421995 [CA 0] Center 37 (7~68) winsize 62
747 00:45:02.422080 [CA 1] Center 37 (6~68) winsize 63
748 00:45:02.422165 [CA 2] Center 35 (4~66) winsize 63
749 00:45:02.422259 [CA 3] Center 35 (4~66) winsize 63
750 00:45:02.422345 [CA 4] Center 33 (3~64) winsize 62
751 00:45:02.422430 [CA 5] Center 34 (3~65) winsize 63
752 00:45:02.422514
753 00:45:02.422599 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 00:45:02.422683
755 00:45:02.422768 [CATrainingPosCal] consider 2 rank data
756 00:45:02.422853 u2DelayCellTimex100 = 270/100 ps
757 00:45:02.422940 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 00:45:02.423026 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 00:45:02.423112 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 00:45:02.423197 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
761 00:45:02.423283 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 00:45:02.423368 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 00:45:02.423452
764 00:45:02.423537 CA PerBit enable=1, Macro0, CA PI delay=33
765 00:45:02.423622
766 00:45:02.423707 [CBTSetCACLKResult] CA Dly = 33
767 00:45:02.423792 CS Dly: 5 (0~37)
768 00:45:02.423876
769 00:45:02.423960 ----->DramcWriteLeveling(PI) begin...
770 00:45:02.424046 ==
771 00:45:02.424131 Dram Type= 6, Freq= 0, CH_0, rank 0
772 00:45:02.424217 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
773 00:45:02.424302 ==
774 00:45:02.424388 Write leveling (Byte 0): 30 => 30
775 00:45:02.424473 Write leveling (Byte 1): 27 => 27
776 00:45:02.424558 DramcWriteLeveling(PI) end<-----
777 00:45:02.424642
778 00:45:02.424726 ==
779 00:45:02.424811 Dram Type= 6, Freq= 0, CH_0, rank 0
780 00:45:02.424897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
781 00:45:02.424982 ==
782 00:45:02.425066 [Gating] SW mode calibration
783 00:45:02.425155 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 00:45:02.425242 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 00:45:02.425328 0 6 0 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 1)
786 00:45:02.425414 0 6 4 | B1->B0 | 2626 2424 | 0 1 | (0 0) (1 0)
787 00:45:02.425506 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 00:45:02.425584 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:45:02.425662 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:45:02.425740 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:45:02.425817 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:45:02.425895 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:45:02.425973 0 7 0 | B1->B0 | 2727 2a2a | 0 0 | (0 0) (0 0)
794 00:45:02.426051 0 7 4 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
795 00:45:02.426129 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
796 00:45:02.426206 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 00:45:02.426266 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 00:45:02.426316 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 00:45:02.426366 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 00:45:02.426415 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 00:45:02.426463 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
802 00:45:02.426512 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
803 00:45:02.426561 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 00:45:02.426609 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 00:45:02.426657 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 00:45:02.426706 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 00:45:02.426755 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 00:45:02.426804 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 00:45:02.426853 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 00:45:02.426902 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 00:45:02.426950 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 00:45:02.426999 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 00:45:02.427048 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 00:45:02.427296 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 00:45:02.427367 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 00:45:02.427467 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 00:45:02.427565 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
818 00:45:02.427663 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
819 00:45:02.427761 Total UI for P1: 0, mck2ui 16
820 00:45:02.427849 best dqsien dly found for B0: ( 0, 10, 2)
821 00:45:02.427928 Total UI for P1: 0, mck2ui 16
822 00:45:02.428006 best dqsien dly found for B1: ( 0, 10, 0)
823 00:45:02.428058 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
824 00:45:02.428107 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
825 00:45:02.428156
826 00:45:02.428204 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
827 00:45:02.428254 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
828 00:45:02.428303 [Gating] SW calibration Done
829 00:45:02.428351 ==
830 00:45:02.428400 Dram Type= 6, Freq= 0, CH_0, rank 0
831 00:45:02.428448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
832 00:45:02.428498 ==
833 00:45:02.428547 RX Vref Scan: 0
834 00:45:02.428596
835 00:45:02.428644 RX Vref 0 -> 0, step: 1
836 00:45:02.428692
837 00:45:02.428740 RX Delay -130 -> 252, step: 16
838 00:45:02.428789 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
839 00:45:02.428837 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
840 00:45:02.428885 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
841 00:45:02.428934 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
842 00:45:02.428983 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
843 00:45:02.429032 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
844 00:45:02.429081 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
845 00:45:02.429129 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
846 00:45:02.429178 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
847 00:45:02.429227 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
848 00:45:02.429275 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
849 00:45:02.429325 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
850 00:45:02.429373 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
851 00:45:02.429422 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
852 00:45:02.429471 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
853 00:45:02.429519 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
854 00:45:02.429567 ==
855 00:45:02.429616 Dram Type= 6, Freq= 0, CH_0, rank 0
856 00:45:02.429665 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
857 00:45:02.429714 ==
858 00:45:02.429762 DQS Delay:
859 00:45:02.429811 DQS0 = 0, DQS1 = 0
860 00:45:02.429866 DQM Delay:
861 00:45:02.429916 DQM0 = 83, DQM1 = 73
862 00:45:02.429965 DQ Delay:
863 00:45:02.430014 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
864 00:45:02.430062 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
865 00:45:02.430111 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
866 00:45:02.430160 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
867 00:45:02.430207
868 00:45:02.430265
869 00:45:02.430313 ==
870 00:45:02.430361 Dram Type= 6, Freq= 0, CH_0, rank 0
871 00:45:02.430424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
872 00:45:02.430472 ==
873 00:45:02.430519
874 00:45:02.430566
875 00:45:02.430613 TX Vref Scan disable
876 00:45:02.430661 == TX Byte 0 ==
877 00:45:02.430708 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
878 00:45:02.430756 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
879 00:45:02.430803 == TX Byte 1 ==
880 00:45:02.430851 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
881 00:45:02.430900 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
882 00:45:02.430947 ==
883 00:45:02.430995 Dram Type= 6, Freq= 0, CH_0, rank 0
884 00:45:02.431043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
885 00:45:02.431090 ==
886 00:45:02.431138 TX Vref=22, minBit 0, minWin=27, winSum=439
887 00:45:02.431186 TX Vref=24, minBit 4, minWin=27, winSum=447
888 00:45:02.431233 TX Vref=26, minBit 4, minWin=27, winSum=452
889 00:45:02.431281 TX Vref=28, minBit 0, minWin=28, winSum=451
890 00:45:02.431329 TX Vref=30, minBit 2, minWin=28, winSum=453
891 00:45:02.431377 TX Vref=32, minBit 0, minWin=28, winSum=450
892 00:45:02.431425 [TxChooseVref] Worse bit 2, Min win 28, Win sum 453, Final Vref 30
893 00:45:02.431473
894 00:45:02.431521 Final TX Range 1 Vref 30
895 00:45:02.431569
896 00:45:02.431616 ==
897 00:45:02.431664 Dram Type= 6, Freq= 0, CH_0, rank 0
898 00:45:02.431711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
899 00:45:02.431759 ==
900 00:45:02.431806
901 00:45:02.431852
902 00:45:02.431899 TX Vref Scan disable
903 00:45:02.431946 == TX Byte 0 ==
904 00:45:02.431993 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
905 00:45:02.432041 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
906 00:45:02.432088 == TX Byte 1 ==
907 00:45:02.432135 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
908 00:45:02.432183 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
909 00:45:02.432229
910 00:45:02.432276 [DATLAT]
911 00:45:02.432323 Freq=800, CH0 RK0
912 00:45:02.432371
913 00:45:02.432418 DATLAT Default: 0xa
914 00:45:02.432466 0, 0xFFFF, sum = 0
915 00:45:02.432514 1, 0xFFFF, sum = 0
916 00:45:02.432563 2, 0xFFFF, sum = 0
917 00:45:02.432611 3, 0xFFFF, sum = 0
918 00:45:02.432661 4, 0xFFFF, sum = 0
919 00:45:02.432709 5, 0xFFFF, sum = 0
920 00:45:02.432757 6, 0xFFFF, sum = 0
921 00:45:02.432805 7, 0xFFFF, sum = 0
922 00:45:02.432853 8, 0x0, sum = 1
923 00:45:02.432905 9, 0x0, sum = 2
924 00:45:02.432954 10, 0x0, sum = 3
925 00:45:02.433004 11, 0x0, sum = 4
926 00:45:02.433053 best_step = 9
927 00:45:02.433101
928 00:45:02.433148 ==
929 00:45:02.433195 Dram Type= 6, Freq= 0, CH_0, rank 0
930 00:45:02.433249 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
931 00:45:02.433298 ==
932 00:45:02.433345 RX Vref Scan: 1
933 00:45:02.433401
934 00:45:02.433450 Set Vref Range= 32 -> 127
935 00:45:02.433497
936 00:45:02.433544 RX Vref 32 -> 127, step: 1
937 00:45:02.433591
938 00:45:02.433638 RX Delay -111 -> 252, step: 8
939 00:45:02.433686
940 00:45:02.433733 Set Vref, RX VrefLevel [Byte0]: 32
941 00:45:02.433782 [Byte1]: 32
942 00:45:02.433829
943 00:45:02.433876 Set Vref, RX VrefLevel [Byte0]: 33
944 00:45:02.433922 [Byte1]: 33
945 00:45:02.433969
946 00:45:02.434016 Set Vref, RX VrefLevel [Byte0]: 34
947 00:45:02.434065 [Byte1]: 34
948 00:45:02.434112
949 00:45:02.434160 Set Vref, RX VrefLevel [Byte0]: 35
950 00:45:02.434208 [Byte1]: 35
951 00:45:02.434264
952 00:45:02.434312 Set Vref, RX VrefLevel [Byte0]: 36
953 00:45:02.434361 [Byte1]: 36
954 00:45:02.434408
955 00:45:02.434455 Set Vref, RX VrefLevel [Byte0]: 37
956 00:45:02.434503 [Byte1]: 37
957 00:45:02.434551
958 00:45:02.434598 Set Vref, RX VrefLevel [Byte0]: 38
959 00:45:02.434646 [Byte1]: 38
960 00:45:02.434693
961 00:45:02.434740 Set Vref, RX VrefLevel [Byte0]: 39
962 00:45:02.434787 [Byte1]: 39
963 00:45:02.434835
964 00:45:02.435074 Set Vref, RX VrefLevel [Byte0]: 40
965 00:45:02.435150 [Byte1]: 40
966 00:45:02.435246
967 00:45:02.435341 Set Vref, RX VrefLevel [Byte0]: 41
968 00:45:02.435438 [Byte1]: 41
969 00:45:02.435531
970 00:45:02.435614 Set Vref, RX VrefLevel [Byte0]: 42
971 00:45:02.435695 [Byte1]: 42
972 00:45:02.435746
973 00:45:02.435794 Set Vref, RX VrefLevel [Byte0]: 43
974 00:45:02.435842 [Byte1]: 43
975 00:45:02.435890
976 00:45:02.435937 Set Vref, RX VrefLevel [Byte0]: 44
977 00:45:02.435986 [Byte1]: 44
978 00:45:02.436034
979 00:45:02.436081 Set Vref, RX VrefLevel [Byte0]: 45
980 00:45:02.436129 [Byte1]: 45
981 00:45:02.436177
982 00:45:02.436225 Set Vref, RX VrefLevel [Byte0]: 46
983 00:45:02.436272 [Byte1]: 46
984 00:45:02.436326
985 00:45:02.436374 Set Vref, RX VrefLevel [Byte0]: 47
986 00:45:02.436423 [Byte1]: 47
987 00:45:02.436471
988 00:45:02.436518 Set Vref, RX VrefLevel [Byte0]: 48
989 00:45:02.436566 [Byte1]: 48
990 00:45:02.436613
991 00:45:02.436660 Set Vref, RX VrefLevel [Byte0]: 49
992 00:45:02.436707 [Byte1]: 49
993 00:45:02.436753
994 00:45:02.436800 Set Vref, RX VrefLevel [Byte0]: 50
995 00:45:02.436848 [Byte1]: 50
996 00:45:02.436895
997 00:45:02.436942 Set Vref, RX VrefLevel [Byte0]: 51
998 00:45:02.436990 [Byte1]: 51
999 00:45:02.437037
1000 00:45:02.437084 Set Vref, RX VrefLevel [Byte0]: 52
1001 00:45:02.437132 [Byte1]: 52
1002 00:45:02.437179
1003 00:45:02.437225 Set Vref, RX VrefLevel [Byte0]: 53
1004 00:45:02.437273 [Byte1]: 53
1005 00:45:02.437319
1006 00:45:02.437366 Set Vref, RX VrefLevel [Byte0]: 54
1007 00:45:02.437414 [Byte1]: 54
1008 00:45:02.437461
1009 00:45:02.437509 Set Vref, RX VrefLevel [Byte0]: 55
1010 00:45:02.437557 [Byte1]: 55
1011 00:45:02.437605
1012 00:45:02.437652 Set Vref, RX VrefLevel [Byte0]: 56
1013 00:45:02.437699 [Byte1]: 56
1014 00:45:02.437746
1015 00:45:02.437793 Set Vref, RX VrefLevel [Byte0]: 57
1016 00:45:02.437841 [Byte1]: 57
1017 00:45:02.437889
1018 00:45:02.437937 Set Vref, RX VrefLevel [Byte0]: 58
1019 00:45:02.437984 [Byte1]: 58
1020 00:45:02.438031
1021 00:45:02.438079 Set Vref, RX VrefLevel [Byte0]: 59
1022 00:45:02.438128 [Byte1]: 59
1023 00:45:02.438177
1024 00:45:02.438233 Set Vref, RX VrefLevel [Byte0]: 60
1025 00:45:02.438282 [Byte1]: 60
1026 00:45:02.438330
1027 00:45:02.438378 Set Vref, RX VrefLevel [Byte0]: 61
1028 00:45:02.438425 [Byte1]: 61
1029 00:45:02.438472
1030 00:45:02.438520 Set Vref, RX VrefLevel [Byte0]: 62
1031 00:45:02.438591 [Byte1]: 62
1032 00:45:02.438653
1033 00:45:02.438700 Set Vref, RX VrefLevel [Byte0]: 63
1034 00:45:02.438748 [Byte1]: 63
1035 00:45:02.438795
1036 00:45:02.438842 Set Vref, RX VrefLevel [Byte0]: 64
1037 00:45:02.438890 [Byte1]: 64
1038 00:45:02.438937
1039 00:45:02.438984 Set Vref, RX VrefLevel [Byte0]: 65
1040 00:45:02.439032 [Byte1]: 65
1041 00:45:02.439079
1042 00:45:02.439126 Set Vref, RX VrefLevel [Byte0]: 66
1043 00:45:02.439174 [Byte1]: 66
1044 00:45:02.439220
1045 00:45:02.439267 Set Vref, RX VrefLevel [Byte0]: 67
1046 00:45:02.439315 [Byte1]: 67
1047 00:45:02.439363
1048 00:45:02.439410 Set Vref, RX VrefLevel [Byte0]: 68
1049 00:45:02.439458 [Byte1]: 68
1050 00:45:02.439505
1051 00:45:02.439553 Set Vref, RX VrefLevel [Byte0]: 69
1052 00:45:02.439601 [Byte1]: 69
1053 00:45:02.439648
1054 00:45:02.439694 Set Vref, RX VrefLevel [Byte0]: 70
1055 00:45:02.439742 [Byte1]: 70
1056 00:45:02.439789
1057 00:45:02.439836 Set Vref, RX VrefLevel [Byte0]: 71
1058 00:45:02.439890 [Byte1]: 71
1059 00:45:02.439939
1060 00:45:02.439986 Set Vref, RX VrefLevel [Byte0]: 72
1061 00:45:02.440033 [Byte1]: 72
1062 00:45:02.440081
1063 00:45:02.440128 Set Vref, RX VrefLevel [Byte0]: 73
1064 00:45:02.440174 [Byte1]: 73
1065 00:45:02.440222
1066 00:45:02.440269 Set Vref, RX VrefLevel [Byte0]: 74
1067 00:45:02.440316 [Byte1]: 74
1068 00:45:02.440363
1069 00:45:02.440410 Set Vref, RX VrefLevel [Byte0]: 75
1070 00:45:02.440457 [Byte1]: 75
1071 00:45:02.440504
1072 00:45:02.440552 Set Vref, RX VrefLevel [Byte0]: 76
1073 00:45:02.440637 [Byte1]: 76
1074 00:45:02.440684
1075 00:45:02.440730 Final RX Vref Byte 0 = 48 to rank0
1076 00:45:02.440778 Final RX Vref Byte 1 = 49 to rank0
1077 00:45:02.440826 Final RX Vref Byte 0 = 48 to rank1
1078 00:45:02.440873 Final RX Vref Byte 1 = 49 to rank1==
1079 00:45:02.440921 Dram Type= 6, Freq= 0, CH_0, rank 0
1080 00:45:02.440968 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1081 00:45:02.441016 ==
1082 00:45:02.441064 DQS Delay:
1083 00:45:02.441110 DQS0 = 0, DQS1 = 0
1084 00:45:02.441156 DQM Delay:
1085 00:45:02.441204 DQM0 = 84, DQM1 = 73
1086 00:45:02.441251 DQ Delay:
1087 00:45:02.441299 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1088 00:45:02.441347 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1089 00:45:02.441394 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1090 00:45:02.441441 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1091 00:45:02.441489
1092 00:45:02.441535
1093 00:45:02.441584 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1094 00:45:02.441632 CH0 RK0: MR19=606, MR18=3F3F
1095 00:45:02.441680 CH0_RK0: MR19=0x606, MR18=0x3F3F, DQSOSC=393, MR23=63, INC=95, DEC=63
1096 00:45:02.441727
1097 00:45:02.441775 ----->DramcWriteLeveling(PI) begin...
1098 00:45:02.441824 ==
1099 00:45:02.441871 Dram Type= 6, Freq= 0, CH_0, rank 1
1100 00:45:02.441918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1101 00:45:02.441967 ==
1102 00:45:02.442015 Write leveling (Byte 0): 29 => 29
1103 00:45:02.442062 Write leveling (Byte 1): 30 => 30
1104 00:45:02.442109 DramcWriteLeveling(PI) end<-----
1105 00:45:02.442156
1106 00:45:02.442203 ==
1107 00:45:02.442280 Dram Type= 6, Freq= 0, CH_0, rank 1
1108 00:45:02.442342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1109 00:45:02.442390 ==
1110 00:45:02.442438 [Gating] SW mode calibration
1111 00:45:02.442486 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1112 00:45:02.442537 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1113 00:45:02.442584 0 6 0 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
1114 00:45:02.442632 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 00:45:02.442872 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 00:45:02.442970 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1117 00:45:02.443070 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1118 00:45:02.443146 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1119 00:45:02.443196 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1120 00:45:02.443245 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1121 00:45:02.443293 0 7 0 | B1->B0 | 2c2c 2e2e | 1 0 | (0 0) (0 0)
1122 00:45:02.443341 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1123 00:45:02.443389 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 00:45:02.443436 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1125 00:45:02.443483 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1126 00:45:02.443530 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1127 00:45:02.443578 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1128 00:45:02.443625 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1129 00:45:02.443673 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1130 00:45:02.443720 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 00:45:02.443767 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 00:45:02.443815 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 00:45:02.443862 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 00:45:02.443911 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 00:45:02.443958 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 00:45:02.444005 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 00:45:02.444052 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 00:45:02.444100 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 00:45:02.444147 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 00:45:02.444195 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 00:45:02.444242 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1142 00:45:02.444289 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1143 00:45:02.444336 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1144 00:45:02.444383 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1145 00:45:02.444431 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1146 00:45:02.444480 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1147 00:45:02.444531 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1148 00:45:02.444581 Total UI for P1: 0, mck2ui 16
1149 00:45:02.444630 best dqsien dly found for B0: ( 0, 10, 4)
1150 00:45:02.444678 Total UI for P1: 0, mck2ui 16
1151 00:45:02.444726 best dqsien dly found for B1: ( 0, 10, 4)
1152 00:45:02.444774 best DQS0 dly(MCK, UI, PI) = (0, 10, 4)
1153 00:45:02.444821 best DQS1 dly(MCK, UI, PI) = (0, 10, 4)
1154 00:45:02.444868
1155 00:45:02.444916 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 4)
1156 00:45:02.444964 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 4)
1157 00:45:02.445012 [Gating] SW calibration Done
1158 00:45:02.445060 ==
1159 00:45:02.445107 Dram Type= 6, Freq= 0, CH_0, rank 1
1160 00:45:02.445155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1161 00:45:02.445204 ==
1162 00:45:02.445250 RX Vref Scan: 0
1163 00:45:02.445297
1164 00:45:02.445344 RX Vref 0 -> 0, step: 1
1165 00:45:02.445391
1166 00:45:02.445438 RX Delay -130 -> 252, step: 16
1167 00:45:02.445486 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1168 00:45:02.445533 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1169 00:45:02.445581 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1170 00:45:02.445629 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1171 00:45:02.445676 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1172 00:45:02.445723 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1173 00:45:02.445770 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1174 00:45:02.445817 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1175 00:45:02.445864 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1176 00:45:02.445912 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1177 00:45:02.445960 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1178 00:45:02.446008 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1179 00:45:02.446055 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1180 00:45:02.446103 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1181 00:45:02.446149 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1182 00:45:02.446197 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1183 00:45:02.446274 ==
1184 00:45:02.446351 Dram Type= 6, Freq= 0, CH_0, rank 1
1185 00:45:02.446428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1186 00:45:02.446503 ==
1187 00:45:02.446625 DQS Delay:
1188 00:45:02.446700 DQS0 = 0, DQS1 = 0
1189 00:45:02.446775 DQM Delay:
1190 00:45:02.446860 DQM0 = 80, DQM1 = 70
1191 00:45:02.446913 DQ Delay:
1192 00:45:02.446961 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1193 00:45:02.447010 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1194 00:45:02.447058 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1195 00:45:02.447106 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1196 00:45:02.447153
1197 00:45:02.447200
1198 00:45:02.447248 ==
1199 00:45:02.447296 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 00:45:02.447344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1201 00:45:02.447392 ==
1202 00:45:02.447439
1203 00:45:02.447486
1204 00:45:02.447533 TX Vref Scan disable
1205 00:45:02.447581 == TX Byte 0 ==
1206 00:45:02.447627 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1207 00:45:02.447675 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1208 00:45:02.447723 == TX Byte 1 ==
1209 00:45:02.447770 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1210 00:45:02.447819 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1211 00:45:02.447866 ==
1212 00:45:02.447913 Dram Type= 6, Freq= 0, CH_0, rank 1
1213 00:45:02.447961 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1214 00:45:02.448008 ==
1215 00:45:02.448055 TX Vref=22, minBit 0, minWin=27, winSum=448
1216 00:45:02.448103 TX Vref=24, minBit 2, minWin=28, winSum=453
1217 00:45:02.448151 TX Vref=26, minBit 0, minWin=28, winSum=455
1218 00:45:02.448199 TX Vref=28, minBit 2, minWin=28, winSum=458
1219 00:45:02.448247 TX Vref=30, minBit 2, minWin=28, winSum=458
1220 00:45:02.448295 TX Vref=32, minBit 2, minWin=28, winSum=460
1221 00:45:02.448343 [TxChooseVref] Worse bit 2, Min win 28, Win sum 460, Final Vref 32
1222 00:45:02.448392
1223 00:45:02.448439 Final TX Range 1 Vref 32
1224 00:45:02.448486
1225 00:45:02.448533 ==
1226 00:45:02.448772 Dram Type= 6, Freq= 0, CH_0, rank 1
1227 00:45:02.448828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1228 00:45:02.448877 ==
1229 00:45:02.448925
1230 00:45:02.448974
1231 00:45:02.449021 TX Vref Scan disable
1232 00:45:02.449068 == TX Byte 0 ==
1233 00:45:02.449116 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1234 00:45:02.449164 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1235 00:45:02.449213 == TX Byte 1 ==
1236 00:45:02.449261 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1237 00:45:02.449309 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1238 00:45:02.449357
1239 00:45:02.449405 [DATLAT]
1240 00:45:02.449452 Freq=800, CH0 RK1
1241 00:45:02.449500
1242 00:45:02.449547 DATLAT Default: 0x9
1243 00:45:02.449594 0, 0xFFFF, sum = 0
1244 00:45:02.449642 1, 0xFFFF, sum = 0
1245 00:45:02.449690 2, 0xFFFF, sum = 0
1246 00:45:02.449739 3, 0xFFFF, sum = 0
1247 00:45:02.449787 4, 0xFFFF, sum = 0
1248 00:45:02.449835 5, 0xFFFF, sum = 0
1249 00:45:02.449883 6, 0xFFFF, sum = 0
1250 00:45:02.449931 7, 0xFFFF, sum = 0
1251 00:45:02.449979 8, 0x0, sum = 1
1252 00:45:02.450026 9, 0x0, sum = 2
1253 00:45:02.450075 10, 0x0, sum = 3
1254 00:45:02.450123 11, 0x0, sum = 4
1255 00:45:02.450171 best_step = 9
1256 00:45:02.450225
1257 00:45:02.450273 ==
1258 00:45:02.450321 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 00:45:02.450368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1260 00:45:02.450415 ==
1261 00:45:02.450464 RX Vref Scan: 0
1262 00:45:02.450511
1263 00:45:02.450559 RX Vref 0 -> 0, step: 1
1264 00:45:02.450605
1265 00:45:02.450652 RX Delay -95 -> 252, step: 8
1266 00:45:02.450700 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1267 00:45:02.450747 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1268 00:45:02.450795 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1269 00:45:02.450843 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1270 00:45:02.450891 iDelay=209, Bit 4, Center 88 (-31 ~ 208) 240
1271 00:45:02.450938 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1272 00:45:02.450986 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1273 00:45:02.451033 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1274 00:45:02.451081 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1275 00:45:02.451129 iDelay=209, Bit 9, Center 56 (-55 ~ 168) 224
1276 00:45:02.451176 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1277 00:45:02.451223 iDelay=209, Bit 11, Center 64 (-47 ~ 176) 224
1278 00:45:02.451270 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1279 00:45:02.451317 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1280 00:45:02.451365 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1281 00:45:02.451413 iDelay=209, Bit 15, Center 80 (-31 ~ 192) 224
1282 00:45:02.451460 ==
1283 00:45:02.451508 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 00:45:02.451556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1285 00:45:02.451604 ==
1286 00:45:02.451651 DQS Delay:
1287 00:45:02.451697 DQS0 = 0, DQS1 = 0
1288 00:45:02.451744 DQM Delay:
1289 00:45:02.451792 DQM0 = 85, DQM1 = 73
1290 00:45:02.451839 DQ Delay:
1291 00:45:02.451887 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1292 00:45:02.451934 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1293 00:45:02.451982 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1294 00:45:02.452029 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
1295 00:45:02.452077
1296 00:45:02.452122
1297 00:45:02.452169 [DQSOSCAuto] RK1, (LSB)MR18= 0x4848, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1298 00:45:02.452217 CH0 RK1: MR19=606, MR18=4848
1299 00:45:02.452264 CH0_RK1: MR19=0x606, MR18=0x4848, DQSOSC=391, MR23=63, INC=96, DEC=64
1300 00:45:02.452311 [RxdqsGatingPostProcess] freq 800
1301 00:45:02.452359 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1302 00:45:02.452406 Pre-setting of DQS Precalculation
1303 00:45:02.452454 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1304 00:45:02.452500 ==
1305 00:45:02.452559 Dram Type= 6, Freq= 0, CH_1, rank 0
1306 00:45:02.452607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1307 00:45:02.452655 ==
1308 00:45:02.452702 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1309 00:45:02.452750 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1310 00:45:02.452798 [CA 0] Center 36 (6~67) winsize 62
1311 00:45:02.452845 [CA 1] Center 36 (5~67) winsize 63
1312 00:45:02.452892 [CA 2] Center 34 (4~65) winsize 62
1313 00:45:02.452939 [CA 3] Center 34 (3~65) winsize 63
1314 00:45:02.452986 [CA 4] Center 33 (2~64) winsize 63
1315 00:45:02.453033 [CA 5] Center 33 (3~64) winsize 62
1316 00:45:02.453079
1317 00:45:02.453125 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1318 00:45:02.453172
1319 00:45:02.453220 [CATrainingPosCal] consider 1 rank data
1320 00:45:02.453267 u2DelayCellTimex100 = 270/100 ps
1321 00:45:02.453314 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1322 00:45:02.453362 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1323 00:45:02.453409 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1324 00:45:02.453456 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1325 00:45:02.453503 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1326 00:45:02.453550 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1327 00:45:02.453597
1328 00:45:02.453644 CA PerBit enable=1, Macro0, CA PI delay=33
1329 00:45:02.453691
1330 00:45:02.453738 [CBTSetCACLKResult] CA Dly = 33
1331 00:45:02.453786 CS Dly: 4 (0~35)
1332 00:45:02.453833 ==
1333 00:45:02.453881 Dram Type= 6, Freq= 0, CH_1, rank 1
1334 00:45:02.453928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1335 00:45:02.453975 ==
1336 00:45:02.454021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1337 00:45:02.454069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1338 00:45:02.454117 [CA 0] Center 36 (5~67) winsize 63
1339 00:45:02.454164 [CA 1] Center 36 (5~67) winsize 63
1340 00:45:02.454217 [CA 2] Center 34 (4~65) winsize 62
1341 00:45:02.454294 [CA 3] Center 34 (4~64) winsize 61
1342 00:45:02.454369 [CA 4] Center 33 (3~64) winsize 62
1343 00:45:02.454461 [CA 5] Center 33 (2~64) winsize 63
1344 00:45:02.454521
1345 00:45:02.454587 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1346 00:45:02.454635
1347 00:45:02.454683 [CATrainingPosCal] consider 2 rank data
1348 00:45:02.454731 u2DelayCellTimex100 = 270/100 ps
1349 00:45:02.454779 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1350 00:45:02.454827 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1351 00:45:02.454875 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1352 00:45:02.454922 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1353 00:45:02.454970 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1354 00:45:02.455017 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1355 00:45:02.455064
1356 00:45:02.455110 CA PerBit enable=1, Macro0, CA PI delay=33
1357 00:45:02.455157
1358 00:45:02.455204 [CBTSetCACLKResult] CA Dly = 33
1359 00:45:02.455251 CS Dly: 4 (0~36)
1360 00:45:02.455298
1361 00:45:02.455535 ----->DramcWriteLeveling(PI) begin...
1362 00:45:02.455605 ==
1363 00:45:02.455702 Dram Type= 6, Freq= 0, CH_1, rank 0
1364 00:45:02.455798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1365 00:45:02.455894 ==
1366 00:45:02.455989 Write leveling (Byte 0): 25 => 25
1367 00:45:02.456080 Write leveling (Byte 1): 25 => 25
1368 00:45:02.456163 DramcWriteLeveling(PI) end<-----
1369 00:45:02.456239
1370 00:45:02.456313 ==
1371 00:45:02.456388 Dram Type= 6, Freq= 0, CH_1, rank 0
1372 00:45:02.456464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1373 00:45:02.456540 ==
1374 00:45:02.456616 [Gating] SW mode calibration
1375 00:45:02.456693 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1376 00:45:02.456775 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1377 00:45:02.456853 0 6 0 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
1378 00:45:02.456930 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1379 00:45:02.457006 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1380 00:45:02.457082 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1381 00:45:02.457158 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1382 00:45:02.457234 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1383 00:45:02.457310 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1384 00:45:02.457385 0 6 28 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
1385 00:45:02.457461 0 7 0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
1386 00:45:02.457536 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1387 00:45:02.457613 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1388 00:45:02.457688 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1389 00:45:02.457764 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1390 00:45:02.457840 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1391 00:45:02.457915 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1392 00:45:02.457991 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1393 00:45:02.458066 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1394 00:45:02.458142 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 00:45:02.458222 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 00:45:02.458310 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 00:45:02.458358 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 00:45:02.458405 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 00:45:02.458452 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 00:45:02.458499 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 00:45:02.458546 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 00:45:02.458593 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 00:45:02.458641 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 00:45:02.458688 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 00:45:02.458735 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1406 00:45:02.458782 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1407 00:45:02.458829 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1408 00:45:02.458877 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1409 00:45:02.458924 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1410 00:45:02.458971 Total UI for P1: 0, mck2ui 16
1411 00:45:02.459018 best dqsien dly found for B0: ( 0, 9, 28)
1412 00:45:02.459066 Total UI for P1: 0, mck2ui 16
1413 00:45:02.459113 best dqsien dly found for B1: ( 0, 9, 30)
1414 00:45:02.459160 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1415 00:45:02.459207 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1416 00:45:02.459253
1417 00:45:02.459300 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1418 00:45:02.459347 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1419 00:45:02.459395 [Gating] SW calibration Done
1420 00:45:02.459441 ==
1421 00:45:02.459488 Dram Type= 6, Freq= 0, CH_1, rank 0
1422 00:45:02.459535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1423 00:45:02.459583 ==
1424 00:45:02.459629 RX Vref Scan: 0
1425 00:45:02.459675
1426 00:45:02.459721 RX Vref 0 -> 0, step: 1
1427 00:45:02.459772
1428 00:45:02.459820 RX Delay -130 -> 252, step: 16
1429 00:45:02.459869 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1430 00:45:02.459917 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1431 00:45:02.459964 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1432 00:45:02.460011 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1433 00:45:02.460058 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1434 00:45:02.460104 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1435 00:45:02.460151 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1436 00:45:02.460198 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1437 00:45:02.460246 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1438 00:45:02.460293 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1439 00:45:02.460339 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1440 00:45:02.460387 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1441 00:45:02.460434 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1442 00:45:02.460480 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1443 00:45:02.460532 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1444 00:45:02.460616 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1445 00:45:02.460664 ==
1446 00:45:02.460713 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 00:45:02.460760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1448 00:45:02.460807 ==
1449 00:45:02.460854 DQS Delay:
1450 00:45:02.460901 DQS0 = 0, DQS1 = 0
1451 00:45:02.460949 DQM Delay:
1452 00:45:02.460995 DQM0 = 81, DQM1 = 71
1453 00:45:02.461041 DQ Delay:
1454 00:45:02.461087 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1455 00:45:02.461134 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1456 00:45:02.461180 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1457 00:45:02.461228 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1458 00:45:02.461275
1459 00:45:02.461321
1460 00:45:02.461368 ==
1461 00:45:02.461415 Dram Type= 6, Freq= 0, CH_1, rank 0
1462 00:45:02.461461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1463 00:45:02.461508 ==
1464 00:45:02.461555
1465 00:45:02.461601
1466 00:45:02.461647 TX Vref Scan disable
1467 00:45:02.461694 == TX Byte 0 ==
1468 00:45:02.461741 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1469 00:45:02.461788 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1470 00:45:02.461836 == TX Byte 1 ==
1471 00:45:02.461883 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1472 00:45:02.462122 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1473 00:45:02.462222 ==
1474 00:45:02.462358 Dram Type= 6, Freq= 0, CH_1, rank 0
1475 00:45:02.462454 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1476 00:45:02.462572 ==
1477 00:45:02.462673 TX Vref=22, minBit 3, minWin=27, winSum=446
1478 00:45:02.462759 TX Vref=24, minBit 0, minWin=28, winSum=450
1479 00:45:02.462839 TX Vref=26, minBit 0, minWin=28, winSum=455
1480 00:45:02.462935 TX Vref=28, minBit 0, minWin=28, winSum=457
1481 00:45:02.463018 TX Vref=30, minBit 3, minWin=28, winSum=458
1482 00:45:02.463101 TX Vref=32, minBit 2, minWin=28, winSum=457
1483 00:45:02.463193 [TxChooseVref] Worse bit 3, Min win 28, Win sum 458, Final Vref 30
1484 00:45:02.463286
1485 00:45:02.463413 Final TX Range 1 Vref 30
1486 00:45:02.463508
1487 00:45:02.463586 ==
1488 00:45:02.463662 Dram Type= 6, Freq= 0, CH_1, rank 0
1489 00:45:02.463739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1490 00:45:02.463814 ==
1491 00:45:02.463889
1492 00:45:02.463963
1493 00:45:02.464037 TX Vref Scan disable
1494 00:45:02.464112 == TX Byte 0 ==
1495 00:45:02.464188 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1496 00:45:02.464264 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1497 00:45:02.464339 == TX Byte 1 ==
1498 00:45:02.464415 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1499 00:45:02.464491 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1500 00:45:02.464624
1501 00:45:02.464756 [DATLAT]
1502 00:45:02.464832 Freq=800, CH1 RK0
1503 00:45:02.464907
1504 00:45:02.464981 DATLAT Default: 0xa
1505 00:45:02.465056 0, 0xFFFF, sum = 0
1506 00:45:02.465134 1, 0xFFFF, sum = 0
1507 00:45:02.465211 2, 0xFFFF, sum = 0
1508 00:45:02.465288 3, 0xFFFF, sum = 0
1509 00:45:02.465365 4, 0xFFFF, sum = 0
1510 00:45:02.465442 5, 0xFFFF, sum = 0
1511 00:45:02.465521 6, 0xFFFF, sum = 0
1512 00:45:02.465574 7, 0xFFFF, sum = 0
1513 00:45:02.465624 8, 0x0, sum = 1
1514 00:45:02.465673 9, 0x0, sum = 2
1515 00:45:02.465722 10, 0x0, sum = 3
1516 00:45:02.465770 11, 0x0, sum = 4
1517 00:45:02.465818 best_step = 9
1518 00:45:02.465866
1519 00:45:02.465912 ==
1520 00:45:02.465958 Dram Type= 6, Freq= 0, CH_1, rank 0
1521 00:45:02.466007 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1522 00:45:02.466055 ==
1523 00:45:02.466103 RX Vref Scan: 1
1524 00:45:02.466150
1525 00:45:02.466196 Set Vref Range= 32 -> 127
1526 00:45:02.466254
1527 00:45:02.466302 RX Vref 32 -> 127, step: 1
1528 00:45:02.466349
1529 00:45:02.466395 RX Delay -111 -> 252, step: 8
1530 00:45:02.466441
1531 00:45:02.466488 Set Vref, RX VrefLevel [Byte0]: 32
1532 00:45:02.466536 [Byte1]: 32
1533 00:45:02.466583
1534 00:45:02.466629 Set Vref, RX VrefLevel [Byte0]: 33
1535 00:45:02.466676 [Byte1]: 33
1536 00:45:02.466723
1537 00:45:02.466769 Set Vref, RX VrefLevel [Byte0]: 34
1538 00:45:02.466816 [Byte1]: 34
1539 00:45:02.466862
1540 00:45:02.466908 Set Vref, RX VrefLevel [Byte0]: 35
1541 00:45:02.466955 [Byte1]: 35
1542 00:45:02.467001
1543 00:45:02.467047 Set Vref, RX VrefLevel [Byte0]: 36
1544 00:45:02.467095 [Byte1]: 36
1545 00:45:02.467142
1546 00:45:02.467189 Set Vref, RX VrefLevel [Byte0]: 37
1547 00:45:02.467236 [Byte1]: 37
1548 00:45:02.467282
1549 00:45:02.467329 Set Vref, RX VrefLevel [Byte0]: 38
1550 00:45:02.467376 [Byte1]: 38
1551 00:45:02.467423
1552 00:45:02.467469 Set Vref, RX VrefLevel [Byte0]: 39
1553 00:45:02.467516 [Byte1]: 39
1554 00:45:02.467564
1555 00:45:02.467611 Set Vref, RX VrefLevel [Byte0]: 40
1556 00:45:02.467658 [Byte1]: 40
1557 00:45:02.467704
1558 00:45:02.467751 Set Vref, RX VrefLevel [Byte0]: 41
1559 00:45:02.467798 [Byte1]: 41
1560 00:45:02.467845
1561 00:45:02.467891 Set Vref, RX VrefLevel [Byte0]: 42
1562 00:45:02.467938 [Byte1]: 42
1563 00:45:02.467985
1564 00:45:02.468032 Set Vref, RX VrefLevel [Byte0]: 43
1565 00:45:02.468080 [Byte1]: 43
1566 00:45:02.468127
1567 00:45:02.468174 Set Vref, RX VrefLevel [Byte0]: 44
1568 00:45:02.468222 [Byte1]: 44
1569 00:45:02.468269
1570 00:45:02.468315 Set Vref, RX VrefLevel [Byte0]: 45
1571 00:45:02.468362 [Byte1]: 45
1572 00:45:02.468408
1573 00:45:02.468455 Set Vref, RX VrefLevel [Byte0]: 46
1574 00:45:02.468503 [Byte1]: 46
1575 00:45:02.468573
1576 00:45:02.468655 Set Vref, RX VrefLevel [Byte0]: 47
1577 00:45:02.468707 [Byte1]: 47
1578 00:45:02.468755
1579 00:45:02.468802 Set Vref, RX VrefLevel [Byte0]: 48
1580 00:45:02.468849 [Byte1]: 48
1581 00:45:02.468897
1582 00:45:02.468944 Set Vref, RX VrefLevel [Byte0]: 49
1583 00:45:02.468992 [Byte1]: 49
1584 00:45:02.469039
1585 00:45:02.469086 Set Vref, RX VrefLevel [Byte0]: 50
1586 00:45:02.469133 [Byte1]: 50
1587 00:45:02.469179
1588 00:45:02.469226 Set Vref, RX VrefLevel [Byte0]: 51
1589 00:45:02.469273 [Byte1]: 51
1590 00:45:02.469323
1591 00:45:02.469376 Set Vref, RX VrefLevel [Byte0]: 52
1592 00:45:02.469424 [Byte1]: 52
1593 00:45:02.469471
1594 00:45:02.469518 Set Vref, RX VrefLevel [Byte0]: 53
1595 00:45:02.469565 [Byte1]: 53
1596 00:45:02.469612
1597 00:45:02.469695 Set Vref, RX VrefLevel [Byte0]: 54
1598 00:45:02.469747 [Byte1]: 54
1599 00:45:02.469795
1600 00:45:02.469842 Set Vref, RX VrefLevel [Byte0]: 55
1601 00:45:02.469890 [Byte1]: 55
1602 00:45:02.469938
1603 00:45:02.469985 Set Vref, RX VrefLevel [Byte0]: 56
1604 00:45:02.470032 [Byte1]: 56
1605 00:45:02.470080
1606 00:45:02.470126 Set Vref, RX VrefLevel [Byte0]: 57
1607 00:45:02.470174 [Byte1]: 57
1608 00:45:02.470227
1609 00:45:02.470315 Set Vref, RX VrefLevel [Byte0]: 58
1610 00:45:02.470362 [Byte1]: 58
1611 00:45:02.470410
1612 00:45:02.470457 Set Vref, RX VrefLevel [Byte0]: 59
1613 00:45:02.470504 [Byte1]: 59
1614 00:45:02.470551
1615 00:45:02.470597 Set Vref, RX VrefLevel [Byte0]: 60
1616 00:45:02.470646 [Byte1]: 60
1617 00:45:02.470693
1618 00:45:02.470741 Set Vref, RX VrefLevel [Byte0]: 61
1619 00:45:02.470789 [Byte1]: 61
1620 00:45:02.470835
1621 00:45:02.470882 Set Vref, RX VrefLevel [Byte0]: 62
1622 00:45:02.470929 [Byte1]: 62
1623 00:45:02.470976
1624 00:45:02.471021 Set Vref, RX VrefLevel [Byte0]: 63
1625 00:45:02.471069 [Byte1]: 63
1626 00:45:02.471116
1627 00:45:02.471163 Set Vref, RX VrefLevel [Byte0]: 64
1628 00:45:02.471210 [Byte1]: 64
1629 00:45:02.471257
1630 00:45:02.471303 Set Vref, RX VrefLevel [Byte0]: 65
1631 00:45:02.471351 [Byte1]: 65
1632 00:45:02.471398
1633 00:45:02.471444 Set Vref, RX VrefLevel [Byte0]: 66
1634 00:45:02.471491 [Byte1]: 66
1635 00:45:02.471538
1636 00:45:02.471584 Set Vref, RX VrefLevel [Byte0]: 67
1637 00:45:02.471631 [Byte1]: 67
1638 00:45:02.471679
1639 00:45:02.471915 Set Vref, RX VrefLevel [Byte0]: 68
1640 00:45:02.471969 [Byte1]: 68
1641 00:45:02.472017
1642 00:45:02.472065 Set Vref, RX VrefLevel [Byte0]: 69
1643 00:45:02.472112 [Byte1]: 69
1644 00:45:02.472160
1645 00:45:02.472208 Set Vref, RX VrefLevel [Byte0]: 70
1646 00:45:02.472256 [Byte1]: 70
1647 00:45:02.472304
1648 00:45:02.472351 Set Vref, RX VrefLevel [Byte0]: 71
1649 00:45:02.472399 [Byte1]: 71
1650 00:45:02.472447
1651 00:45:02.472494 Set Vref, RX VrefLevel [Byte0]: 72
1652 00:45:02.472540 [Byte1]: 72
1653 00:45:02.472586
1654 00:45:02.472632 Set Vref, RX VrefLevel [Byte0]: 73
1655 00:45:02.472679 [Byte1]: 73
1656 00:45:02.472726
1657 00:45:02.472774 Set Vref, RX VrefLevel [Byte0]: 74
1658 00:45:02.472822 [Byte1]: 74
1659 00:45:02.472869
1660 00:45:02.472915 Set Vref, RX VrefLevel [Byte0]: 75
1661 00:45:02.472962 [Byte1]: 75
1662 00:45:02.473009
1663 00:45:02.473055 Final RX Vref Byte 0 = 62 to rank0
1664 00:45:02.473102 Final RX Vref Byte 1 = 55 to rank0
1665 00:45:02.473149 Final RX Vref Byte 0 = 62 to rank1
1666 00:45:02.473196 Final RX Vref Byte 1 = 55 to rank1==
1667 00:45:02.473244 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 00:45:02.473292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1669 00:45:02.473340 ==
1670 00:45:02.473387 DQS Delay:
1671 00:45:02.473434 DQS0 = 0, DQS1 = 0
1672 00:45:02.473481 DQM Delay:
1673 00:45:02.473528 DQM0 = 79, DQM1 = 71
1674 00:45:02.473575 DQ Delay:
1675 00:45:02.473621 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1676 00:45:02.473668 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1677 00:45:02.473716 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1678 00:45:02.473763 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1679 00:45:02.473809
1680 00:45:02.473855
1681 00:45:02.473903 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1682 00:45:02.473951 CH1 RK0: MR19=606, MR18=5050
1683 00:45:02.473998 CH1_RK0: MR19=0x606, MR18=0x5050, DQSOSC=389, MR23=63, INC=97, DEC=65
1684 00:45:02.474045
1685 00:45:02.474092 ----->DramcWriteLeveling(PI) begin...
1686 00:45:02.474141 ==
1687 00:45:02.474188 Dram Type= 6, Freq= 0, CH_1, rank 1
1688 00:45:02.474272 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1689 00:45:02.474334 ==
1690 00:45:02.474382 Write leveling (Byte 0): 25 => 25
1691 00:45:02.474428 Write leveling (Byte 1): 26 => 26
1692 00:45:02.474474 DramcWriteLeveling(PI) end<-----
1693 00:45:02.474520
1694 00:45:02.474567 ==
1695 00:45:02.474614 Dram Type= 6, Freq= 0, CH_1, rank 1
1696 00:45:02.474661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1697 00:45:02.474708 ==
1698 00:45:02.474755 [Gating] SW mode calibration
1699 00:45:02.474803 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1700 00:45:02.474852 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1701 00:45:02.474899 0 6 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
1702 00:45:02.474979 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1703 00:45:02.475035 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1704 00:45:02.475083 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1705 00:45:02.475131 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1706 00:45:02.475178 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1707 00:45:02.475225 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1708 00:45:02.475272 0 6 28 | B1->B0 | 2525 3232 | 0 1 | (0 0) (0 0)
1709 00:45:02.475320 0 7 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1710 00:45:02.475367 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1711 00:45:02.475414 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1712 00:45:02.475461 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1713 00:45:02.475508 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1714 00:45:02.475555 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1715 00:45:02.475602 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1716 00:45:02.475649 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1717 00:45:02.475696 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1718 00:45:02.475743 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 00:45:02.475790 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 00:45:02.475837 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 00:45:02.475884 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 00:45:02.475931 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 00:45:02.475978 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 00:45:02.476024 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 00:45:02.476071 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 00:45:02.476118 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 00:45:02.476165 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 00:45:02.476213 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 00:45:02.476260 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 00:45:02.476307 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 00:45:02.476355 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1732 00:45:02.476403 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1733 00:45:02.476450 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1734 00:45:02.476497 Total UI for P1: 0, mck2ui 16
1735 00:45:02.476545 best dqsien dly found for B0: ( 0, 9, 26)
1736 00:45:02.476592 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1737 00:45:02.476639 Total UI for P1: 0, mck2ui 16
1738 00:45:02.476686 best dqsien dly found for B1: ( 0, 9, 30)
1739 00:45:02.476733 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1740 00:45:02.476780 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1741 00:45:02.476826
1742 00:45:02.476872 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1743 00:45:02.476920 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1744 00:45:02.476967 [Gating] SW calibration Done
1745 00:45:02.477014 ==
1746 00:45:02.477061 Dram Type= 6, Freq= 0, CH_1, rank 1
1747 00:45:02.477109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1748 00:45:02.477156 ==
1749 00:45:02.477203 RX Vref Scan: 0
1750 00:45:02.477250
1751 00:45:02.477296 RX Vref 0 -> 0, step: 1
1752 00:45:02.477342
1753 00:45:02.477389 RX Delay -130 -> 252, step: 16
1754 00:45:02.477436 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1755 00:45:02.477673 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1756 00:45:02.477729 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1757 00:45:02.477779 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1758 00:45:02.477827 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1759 00:45:02.477875 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1760 00:45:02.477922 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1761 00:45:02.477970 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1762 00:45:02.478017 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1763 00:45:02.478064 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1764 00:45:02.478111 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1765 00:45:02.478159 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1766 00:45:02.478206 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1767 00:45:02.478298 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1768 00:45:02.478345 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1769 00:45:02.478392 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1770 00:45:02.478441 ==
1771 00:45:02.478489 Dram Type= 6, Freq= 0, CH_1, rank 1
1772 00:45:02.478537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1773 00:45:02.478586 ==
1774 00:45:02.478633 DQS Delay:
1775 00:45:02.478679 DQS0 = 0, DQS1 = 0
1776 00:45:02.478727 DQM Delay:
1777 00:45:02.478773 DQM0 = 84, DQM1 = 73
1778 00:45:02.478819 DQ Delay:
1779 00:45:02.478866 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1780 00:45:02.478912 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1781 00:45:02.478960 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
1782 00:45:02.479007 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1783 00:45:02.479053
1784 00:45:02.479100
1785 00:45:02.479146 ==
1786 00:45:02.479193 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 00:45:02.479242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1788 00:45:02.479289 ==
1789 00:45:02.479335
1790 00:45:02.479381
1791 00:45:02.479427 TX Vref Scan disable
1792 00:45:02.479474 == TX Byte 0 ==
1793 00:45:02.479522 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1794 00:45:02.479569 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1795 00:45:02.479616 == TX Byte 1 ==
1796 00:45:02.479663 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1797 00:45:02.479710 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1798 00:45:02.479756 ==
1799 00:45:02.479803 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 00:45:02.479850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1801 00:45:02.479897 ==
1802 00:45:02.479944 TX Vref=22, minBit 0, minWin=28, winSum=450
1803 00:45:02.479992 TX Vref=24, minBit 0, minWin=28, winSum=454
1804 00:45:02.480039 TX Vref=26, minBit 1, minWin=28, winSum=456
1805 00:45:02.480086 TX Vref=28, minBit 8, minWin=27, winSum=456
1806 00:45:02.480134 TX Vref=30, minBit 0, minWin=28, winSum=458
1807 00:45:02.480182 TX Vref=32, minBit 0, minWin=28, winSum=455
1808 00:45:02.480229 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1809 00:45:02.480276
1810 00:45:02.480333 Final TX Range 1 Vref 30
1811 00:45:02.480409
1812 00:45:02.480459 ==
1813 00:45:02.480506 Dram Type= 6, Freq= 0, CH_1, rank 1
1814 00:45:02.480554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1815 00:45:02.480603 ==
1816 00:45:02.480650
1817 00:45:02.480697
1818 00:45:02.480744 TX Vref Scan disable
1819 00:45:02.480792 == TX Byte 0 ==
1820 00:45:02.480839 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1821 00:45:02.480886 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1822 00:45:02.480933 == TX Byte 1 ==
1823 00:45:02.480979 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1824 00:45:02.481025 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1825 00:45:02.481072
1826 00:45:02.481119 [DATLAT]
1827 00:45:02.481166 Freq=800, CH1 RK1
1828 00:45:02.481213
1829 00:45:02.481259 DATLAT Default: 0x9
1830 00:45:02.481305 0, 0xFFFF, sum = 0
1831 00:45:02.481354 1, 0xFFFF, sum = 0
1832 00:45:02.481401 2, 0xFFFF, sum = 0
1833 00:45:02.481449 3, 0xFFFF, sum = 0
1834 00:45:02.481496 4, 0xFFFF, sum = 0
1835 00:45:02.481544 5, 0xFFFF, sum = 0
1836 00:45:02.481591 6, 0xFFFF, sum = 0
1837 00:45:02.481639 7, 0xFFFF, sum = 0
1838 00:45:02.481687 8, 0x0, sum = 1
1839 00:45:02.481735 9, 0x0, sum = 2
1840 00:45:02.481782 10, 0x0, sum = 3
1841 00:45:02.481830 11, 0x0, sum = 4
1842 00:45:02.481877 best_step = 9
1843 00:45:02.481924
1844 00:45:02.481970 ==
1845 00:45:02.482017 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 00:45:02.482065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1847 00:45:02.482112 ==
1848 00:45:02.482158 RX Vref Scan: 0
1849 00:45:02.482205
1850 00:45:02.482260 RX Vref 0 -> 0, step: 1
1851 00:45:02.482307
1852 00:45:02.482353 RX Delay -111 -> 252, step: 8
1853 00:45:02.482401 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1854 00:45:02.482449 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1855 00:45:02.482497 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1856 00:45:02.482545 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1857 00:45:02.482594 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1858 00:45:02.482641 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1859 00:45:02.482688 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1860 00:45:02.482735 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1861 00:45:02.482782 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1862 00:45:02.482828 iDelay=217, Bit 9, Center 56 (-63 ~ 176) 240
1863 00:45:02.482876 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1864 00:45:02.482924 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1865 00:45:02.482972 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1866 00:45:02.483019 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1867 00:45:02.483066 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1868 00:45:02.483114 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1869 00:45:02.483160 ==
1870 00:45:02.483207 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 00:45:02.483255 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1872 00:45:02.483302 ==
1873 00:45:02.483349 DQS Delay:
1874 00:45:02.483395 DQS0 = 0, DQS1 = 0
1875 00:45:02.483442 DQM Delay:
1876 00:45:02.483488 DQM0 = 82, DQM1 = 72
1877 00:45:02.483535 DQ Delay:
1878 00:45:02.483582 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1879 00:45:02.483629 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1880 00:45:02.483675 DQ8 =56, DQ9 =56, DQ10 =72, DQ11 =64
1881 00:45:02.483722 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1882 00:45:02.483769
1883 00:45:02.483815
1884 00:45:02.483862 [DQSOSCAuto] RK1, (LSB)MR18= 0x4343, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1885 00:45:02.483910 CH1 RK1: MR19=606, MR18=4343
1886 00:45:02.483957 CH1_RK1: MR19=0x606, MR18=0x4343, DQSOSC=393, MR23=63, INC=95, DEC=63
1887 00:45:02.484004 [RxdqsGatingPostProcess] freq 800
1888 00:45:02.484052 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1889 00:45:02.484099 Pre-setting of DQS Precalculation
1890 00:45:02.484146 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1891 00:45:02.484385 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1892 00:45:02.484441 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1893 00:45:02.484491
1894 00:45:02.484540
1895 00:45:02.484587 [Calibration Summary] 1600 Mbps
1896 00:45:02.484634 CH 0, Rank 0
1897 00:45:02.484681 SW Impedance : PASS
1898 00:45:02.484729 DUTY Scan : NO K
1899 00:45:02.484777 ZQ Calibration : PASS
1900 00:45:02.484824 Jitter Meter : NO K
1901 00:45:02.484872 CBT Training : PASS
1902 00:45:02.484919 Write leveling : PASS
1903 00:45:02.484966 RX DQS gating : PASS
1904 00:45:02.485013 RX DQ/DQS(RDDQC) : PASS
1905 00:45:02.485060 TX DQ/DQS : PASS
1906 00:45:02.485107 RX DATLAT : PASS
1907 00:45:02.485153 RX DQ/DQS(Engine): PASS
1908 00:45:02.485200 TX OE : NO K
1909 00:45:02.485247 All Pass.
1910 00:45:02.485293
1911 00:45:02.485339 CH 0, Rank 1
1912 00:45:02.485386 SW Impedance : PASS
1913 00:45:02.485444 DUTY Scan : NO K
1914 00:45:02.485519 ZQ Calibration : PASS
1915 00:45:02.485568 Jitter Meter : NO K
1916 00:45:02.485615 CBT Training : PASS
1917 00:45:02.485663 Write leveling : PASS
1918 00:45:02.485710 RX DQS gating : PASS
1919 00:45:02.485757 RX DQ/DQS(RDDQC) : PASS
1920 00:45:02.485805 TX DQ/DQS : PASS
1921 00:45:02.485853 RX DATLAT : PASS
1922 00:45:02.485899 RX DQ/DQS(Engine): PASS
1923 00:45:02.485946 TX OE : NO K
1924 00:45:02.485993 All Pass.
1925 00:45:02.486040
1926 00:45:02.486086 CH 1, Rank 0
1927 00:45:02.486134 SW Impedance : PASS
1928 00:45:02.486181 DUTY Scan : NO K
1929 00:45:02.486237 ZQ Calibration : PASS
1930 00:45:02.486323 Jitter Meter : NO K
1931 00:45:02.486370 CBT Training : PASS
1932 00:45:02.486417 Write leveling : PASS
1933 00:45:02.486464 RX DQS gating : PASS
1934 00:45:02.486512 RX DQ/DQS(RDDQC) : PASS
1935 00:45:02.486558 TX DQ/DQS : PASS
1936 00:45:02.486605 RX DATLAT : PASS
1937 00:45:02.736595 RX DQ/DQS(Engine): PASS
1938 00:45:02.737089 TX OE : NO K
1939 00:45:02.737425 All Pass.
1940 00:45:02.737737
1941 00:45:02.738033 CH 1, Rank 1
1942 00:45:02.738364 SW Impedance : PASS
1943 00:45:02.738652 DUTY Scan : NO K
1944 00:45:02.738923 ZQ Calibration : PASS
1945 00:45:02.739192 Jitter Meter : NO K
1946 00:45:02.739463 CBT Training : PASS
1947 00:45:02.739736 Write leveling : PASS
1948 00:45:02.740008 RX DQS gating : PASS
1949 00:45:02.740279 RX DQ/DQS(RDDQC) : PASS
1950 00:45:02.740545 TX DQ/DQS : PASS
1951 00:45:02.740813 RX DATLAT : PASS
1952 00:45:02.741079 RX DQ/DQS(Engine): PASS
1953 00:45:02.741344 TX OE : NO K
1954 00:45:02.741611 All Pass.
1955 00:45:02.741928
1956 00:45:02.742201 DramC Write-DBI off
1957 00:45:02.742536 PER_BANK_REFRESH: Hybrid Mode
1958 00:45:02.742810 TX_TRACKING: ON
1959 00:45:02.743080 [GetDramInforAfterCalByMRR] Vendor 6.
1960 00:45:02.743347 [GetDramInforAfterCalByMRR] Revision 606.
1961 00:45:02.743620 [GetDramInforAfterCalByMRR] Revision 2 0.
1962 00:45:02.743887 MR0 0x3939
1963 00:45:02.744153 MR8 0x1111
1964 00:45:02.744418 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1965 00:45:02.744684
1966 00:45:02.744950 MR0 0x3939
1967 00:45:02.745213 MR8 0x1111
1968 00:45:02.745478 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1969 00:45:02.745744
1970 00:45:02.746008 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1971 00:45:02.746308 [FAST_K] Save calibration result to emmc
1972 00:45:02.746583 [FAST_K] Save calibration result to emmc
1973 00:45:02.746859 dram_init: config_dvfs: 1
1974 00:45:02.747163 dramc_set_vcore_voltage set vcore to 662500
1975 00:45:02.747435 Read voltage for 1200, 2
1976 00:45:02.747705 Vio18 = 0
1977 00:45:02.747979 Vcore = 662500
1978 00:45:02.748248 Vdram = 0
1979 00:45:02.748515 Vddq = 0
1980 00:45:02.748780 Vmddr = 0
1981 00:45:02.749047 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1982 00:45:02.749318 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1983 00:45:02.749589 MEM_TYPE=3, freq_sel=15
1984 00:45:02.749853 sv_algorithm_assistance_LP4_1600
1985 00:45:02.750119 ============ PULL DRAM RESETB DOWN ============
1986 00:45:02.750415 ========== PULL DRAM RESETB DOWN end =========
1987 00:45:02.750689 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1988 00:45:02.750957 ===================================
1989 00:45:02.751227 LPDDR4 DRAM CONFIGURATION
1990 00:45:02.751492 ===================================
1991 00:45:02.751762 EX_ROW_EN[0] = 0x0
1992 00:45:02.752032 EX_ROW_EN[1] = 0x0
1993 00:45:02.752340 LP4Y_EN = 0x0
1994 00:45:02.752614 WORK_FSP = 0x0
1995 00:45:02.752880 WL = 0x4
1996 00:45:02.753147 RL = 0x4
1997 00:45:02.753415 BL = 0x2
1998 00:45:02.753682 RPST = 0x0
1999 00:45:02.754009 RD_PRE = 0x0
2000 00:45:02.754324 WR_PRE = 0x1
2001 00:45:02.754600 WR_PST = 0x0
2002 00:45:02.754868 DBI_WR = 0x0
2003 00:45:02.755135 DBI_RD = 0x0
2004 00:45:02.755563 OTF = 0x1
2005 00:45:02.755953 ===================================
2006 00:45:02.756235 ===================================
2007 00:45:02.756505 ANA top config
2008 00:45:02.756771 ===================================
2009 00:45:02.757040 DLL_ASYNC_EN = 0
2010 00:45:02.757339 ALL_SLAVE_EN = 0
2011 00:45:02.757650 NEW_RANK_MODE = 1
2012 00:45:02.757930 DLL_IDLE_MODE = 1
2013 00:45:02.758200 LP45_APHY_COMB_EN = 1
2014 00:45:02.758519 TX_ODT_DIS = 1
2015 00:45:02.758793 NEW_8X_MODE = 1
2016 00:45:02.759064 ===================================
2017 00:45:02.759339 ===================================
2018 00:45:02.759605 data_rate = 2400
2019 00:45:02.759869 CKR = 1
2020 00:45:02.760134 DQ_P2S_RATIO = 8
2021 00:45:02.760421 ===================================
2022 00:45:02.760613 CA_P2S_RATIO = 8
2023 00:45:02.760802 DQ_CA_OPEN = 0
2024 00:45:02.760992 DQ_SEMI_OPEN = 0
2025 00:45:02.761181 CA_SEMI_OPEN = 0
2026 00:45:02.761369 CA_FULL_RATE = 0
2027 00:45:02.761554 DQ_CKDIV4_EN = 0
2028 00:45:02.761740 CA_CKDIV4_EN = 0
2029 00:45:02.761925 CA_PREDIV_EN = 0
2030 00:45:02.762112 PH8_DLY = 17
2031 00:45:02.762336 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2032 00:45:02.762635 DQ_AAMCK_DIV = 4
2033 00:45:02.762921 CA_AAMCK_DIV = 4
2034 00:45:02.763122 CA_ADMCK_DIV = 4
2035 00:45:02.763315 DQ_TRACK_CA_EN = 0
2036 00:45:02.763509 CA_PICK = 1200
2037 00:45:02.763703 CA_MCKIO = 1200
2038 00:45:02.763897 MCKIO_SEMI = 0
2039 00:45:02.764088 PLL_FREQ = 2366
2040 00:45:02.764279 DQ_UI_PI_RATIO = 32
2041 00:45:02.764471 CA_UI_PI_RATIO = 0
2042 00:45:02.764978 ===================================
2043 00:45:02.765198 ===================================
2044 00:45:02.765397 memory_type:LPDDR4
2045 00:45:02.765570 GP_NUM : 10
2046 00:45:02.765716 SRAM_EN : 1
2047 00:45:02.765859 MD32_EN : 0
2048 00:45:02.766000 ===================================
2049 00:45:02.766194 [ANA_INIT] >>>>>>>>>>>>>>
2050 00:45:02.766375 <<<<<< [CONFIGURE PHASE]: ANA_TX
2051 00:45:02.766522 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2052 00:45:02.766666 ===================================
2053 00:45:02.766810 data_rate = 2400,PCW = 0X5b00
2054 00:45:02.766952 ===================================
2055 00:45:02.767094 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2056 00:45:02.767235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2057 00:45:02.767376 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2058 00:45:02.767518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2059 00:45:02.767659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2060 00:45:02.767799 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2061 00:45:02.767942 [ANA_INIT] flow start
2062 00:45:02.768082 [ANA_INIT] PLL >>>>>>>>
2063 00:45:02.768221 [ANA_INIT] PLL <<<<<<<<
2064 00:45:02.768360 [ANA_INIT] MIDPI >>>>>>>>
2065 00:45:02.768498 [ANA_INIT] MIDPI <<<<<<<<
2066 00:45:02.768639 [ANA_INIT] DLL >>>>>>>>
2067 00:45:02.768778 [ANA_INIT] DLL <<<<<<<<
2068 00:45:02.768916 [ANA_INIT] flow end
2069 00:45:02.769055 ============ LP4 DIFF to SE enter ============
2070 00:45:02.769198 ============ LP4 DIFF to SE exit ============
2071 00:45:02.769339 [ANA_INIT] <<<<<<<<<<<<<
2072 00:45:02.769478 [Flow] Enable top DCM control >>>>>
2073 00:45:02.769619 [Flow] Enable top DCM control <<<<<
2074 00:45:02.769758 Enable DLL master slave shuffle
2075 00:45:02.769936 ==============================================================
2076 00:45:02.770083 Gating Mode config
2077 00:45:02.770242 ==============================================================
2078 00:45:02.770390 Config description:
2079 00:45:02.770525 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2080 00:45:02.770640 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2081 00:45:02.770754 SELPH_MODE 0: By rank 1: By Phase
2082 00:45:02.770866 ==============================================================
2083 00:45:02.770977 GAT_TRACK_EN = 1
2084 00:45:02.771089 RX_GATING_MODE = 2
2085 00:45:02.771199 RX_GATING_TRACK_MODE = 2
2086 00:45:02.771308 SELPH_MODE = 1
2087 00:45:02.771421 PICG_EARLY_EN = 1
2088 00:45:02.771531 VALID_LAT_VALUE = 1
2089 00:45:02.771642 ==============================================================
2090 00:45:02.771754 Enter into Gating configuration >>>>
2091 00:45:02.771866 Exit from Gating configuration <<<<
2092 00:45:02.771975 Enter into DVFS_PRE_config >>>>>
2093 00:45:02.772088 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2094 00:45:02.772202 Exit from DVFS_PRE_config <<<<<
2095 00:45:02.772313 Enter into PICG configuration >>>>
2096 00:45:02.772423 Exit from PICG configuration <<<<
2097 00:45:02.772535 [RX_INPUT] configuration >>>>>
2098 00:45:02.772645 [RX_INPUT] configuration <<<<<
2099 00:45:02.772755 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2100 00:45:02.772866 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2101 00:45:02.772981 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2102 00:45:02.773093 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2103 00:45:02.773203 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2104 00:45:02.773314 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2105 00:45:02.773424 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2106 00:45:02.773536 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2107 00:45:02.773647 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2108 00:45:02.773759 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2109 00:45:02.773870 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2110 00:45:02.773982 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2111 00:45:02.774091 ===================================
2112 00:45:02.774203 LPDDR4 DRAM CONFIGURATION
2113 00:45:02.774333 ===================================
2114 00:45:02.774445 EX_ROW_EN[0] = 0x0
2115 00:45:02.774558 EX_ROW_EN[1] = 0x0
2116 00:45:02.774668 LP4Y_EN = 0x0
2117 00:45:02.774778 WORK_FSP = 0x0
2118 00:45:02.774888 WL = 0x4
2119 00:45:02.774998 RL = 0x4
2120 00:45:02.775109 BL = 0x2
2121 00:45:02.775217 RPST = 0x0
2122 00:45:02.775327 RD_PRE = 0x0
2123 00:45:02.775441 WR_PRE = 0x1
2124 00:45:02.775532 WR_PST = 0x0
2125 00:45:02.775622 DBI_WR = 0x0
2126 00:45:02.775713 DBI_RD = 0x0
2127 00:45:02.775803 OTF = 0x1
2128 00:45:02.775895 ===================================
2129 00:45:02.775988 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2130 00:45:02.776081 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2131 00:45:02.776172 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2132 00:45:02.776263 ===================================
2133 00:45:02.776355 LPDDR4 DRAM CONFIGURATION
2134 00:45:02.776447 ===================================
2135 00:45:02.776538 EX_ROW_EN[0] = 0x10
2136 00:45:02.776630 EX_ROW_EN[1] = 0x0
2137 00:45:02.776721 LP4Y_EN = 0x0
2138 00:45:02.776811 WORK_FSP = 0x0
2139 00:45:02.776903 WL = 0x4
2140 00:45:02.776994 RL = 0x4
2141 00:45:02.777084 BL = 0x2
2142 00:45:02.777175 RPST = 0x0
2143 00:45:02.777266 RD_PRE = 0x0
2144 00:45:02.777358 WR_PRE = 0x1
2145 00:45:02.777449 WR_PST = 0x0
2146 00:45:02.777539 DBI_WR = 0x0
2147 00:45:02.777629 DBI_RD = 0x0
2148 00:45:02.777719 OTF = 0x1
2149 00:45:02.777811 ===================================
2150 00:45:02.778129 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2151 00:45:02.778249 ==
2152 00:45:02.778362 Dram Type= 6, Freq= 0, CH_0, rank 0
2153 00:45:02.778460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2154 00:45:02.778555 ==
2155 00:45:02.778647 [Duty_Offset_Calibration]
2156 00:45:02.778740 B0:0 B1:2 CA:1
2157 00:45:02.778833
2158 00:45:02.778923 [DutyScan_Calibration_Flow] k_type=0
2159 00:45:02.779014
2160 00:45:02.779105 ==CLK 0==
2161 00:45:02.779197 Final CLK duty delay cell = 0
2162 00:45:02.779291 [0] MAX Duty = 5093%(X100), DQS PI = 12
2163 00:45:02.779384 [0] MIN Duty = 4938%(X100), DQS PI = 54
2164 00:45:02.779477 [0] AVG Duty = 5015%(X100)
2165 00:45:02.779568
2166 00:45:02.779659 CH0 CLK Duty spec in!! Max-Min= 155%
2167 00:45:02.779751 [DutyScan_Calibration_Flow] ====Done====
2168 00:45:02.779842
2169 00:45:02.779931 [DutyScan_Calibration_Flow] k_type=1
2170 00:45:02.780022
2171 00:45:02.780113 ==DQS 0 ==
2172 00:45:02.780204 Final DQS duty delay cell = 0
2173 00:45:02.780298 [0] MAX Duty = 5093%(X100), DQS PI = 0
2174 00:45:02.780391 [0] MIN Duty = 5031%(X100), DQS PI = 6
2175 00:45:02.780485 [0] AVG Duty = 5062%(X100)
2176 00:45:02.780562
2177 00:45:02.780640 ==DQS 1 ==
2178 00:45:02.780718 Final DQS duty delay cell = 0
2179 00:45:02.780796 [0] MAX Duty = 5031%(X100), DQS PI = 52
2180 00:45:02.780874 [0] MIN Duty = 4875%(X100), DQS PI = 20
2181 00:45:02.780952 [0] AVG Duty = 4953%(X100)
2182 00:45:02.781031
2183 00:45:02.781109 CH0 DQS 0 Duty spec in!! Max-Min= 62%
2184 00:45:02.781188
2185 00:45:02.781266 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2186 00:45:02.781346 [DutyScan_Calibration_Flow] ====Done====
2187 00:45:02.781425
2188 00:45:02.781504 [DutyScan_Calibration_Flow] k_type=3
2189 00:45:02.781582
2190 00:45:02.781659 ==DQM 0 ==
2191 00:45:02.781739 Final DQM duty delay cell = 0
2192 00:45:02.781819 [0] MAX Duty = 5124%(X100), DQS PI = 20
2193 00:45:02.781899 [0] MIN Duty = 4969%(X100), DQS PI = 40
2194 00:45:02.781977 [0] AVG Duty = 5046%(X100)
2195 00:45:02.782055
2196 00:45:02.782133 ==DQM 1 ==
2197 00:45:02.782220 Final DQM duty delay cell = 4
2198 00:45:02.782306 [4] MAX Duty = 5187%(X100), DQS PI = 54
2199 00:45:02.782386 [4] MIN Duty = 5000%(X100), DQS PI = 16
2200 00:45:02.782466 [4] AVG Duty = 5093%(X100)
2201 00:45:02.782544
2202 00:45:02.782623 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2203 00:45:02.782702
2204 00:45:02.782780 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2205 00:45:02.782858 [DutyScan_Calibration_Flow] ====Done====
2206 00:45:02.782937
2207 00:45:02.783015 [DutyScan_Calibration_Flow] k_type=2
2208 00:45:02.783094
2209 00:45:02.783171 ==DQ 0 ==
2210 00:45:02.783249 Final DQ duty delay cell = -4
2211 00:45:02.783329 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2212 00:45:02.783409 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2213 00:45:02.783501 [-4] AVG Duty = 4937%(X100)
2214 00:45:02.783580
2215 00:45:02.783658 ==DQ 1 ==
2216 00:45:02.783737 Final DQ duty delay cell = -4
2217 00:45:02.783816 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2218 00:45:02.783894 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2219 00:45:02.783973 [-4] AVG Duty = 4969%(X100)
2220 00:45:02.784052
2221 00:45:02.784131 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2222 00:45:02.784210
2223 00:45:02.784289 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2224 00:45:02.784367 [DutyScan_Calibration_Flow] ====Done====
2225 00:45:02.784446 ==
2226 00:45:02.784524 Dram Type= 6, Freq= 0, CH_1, rank 0
2227 00:45:02.784604 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2228 00:45:02.784683 ==
2229 00:45:02.784761 [Duty_Offset_Calibration]
2230 00:45:02.784852 B0:0 B1:4 CA:-5
2231 00:45:02.784935
2232 00:45:02.785014 [DutyScan_Calibration_Flow] k_type=0
2233 00:45:02.785092
2234 00:45:02.785169 ==CLK 0==
2235 00:45:02.785247 Final CLK duty delay cell = 0
2236 00:45:02.785326 [0] MAX Duty = 5094%(X100), DQS PI = 24
2237 00:45:02.785418 [0] MIN Duty = 4875%(X100), DQS PI = 46
2238 00:45:02.785487 [0] AVG Duty = 4984%(X100)
2239 00:45:02.785553
2240 00:45:02.785620 CH1 CLK Duty spec in!! Max-Min= 219%
2241 00:45:02.785689 [DutyScan_Calibration_Flow] ====Done====
2242 00:45:02.785758
2243 00:45:02.785825 [DutyScan_Calibration_Flow] k_type=1
2244 00:45:02.785893
2245 00:45:02.785960 ==DQS 0 ==
2246 00:45:02.786028 Final DQS duty delay cell = 0
2247 00:45:02.786097 [0] MAX Duty = 5125%(X100), DQS PI = 16
2248 00:45:02.786165 [0] MIN Duty = 4875%(X100), DQS PI = 40
2249 00:45:02.786245 [0] AVG Duty = 5000%(X100)
2250 00:45:02.786316
2251 00:45:02.786384 ==DQS 1 ==
2252 00:45:02.786453 Final DQS duty delay cell = -4
2253 00:45:02.786523 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2254 00:45:02.786591 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2255 00:45:02.786661 [-4] AVG Duty = 4953%(X100)
2256 00:45:02.786730
2257 00:45:02.786798 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2258 00:45:02.786866
2259 00:45:02.786933 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2260 00:45:02.787002 [DutyScan_Calibration_Flow] ====Done====
2261 00:45:02.787070
2262 00:45:02.787139 [DutyScan_Calibration_Flow] k_type=3
2263 00:45:02.787206
2264 00:45:02.787274 ==DQM 0 ==
2265 00:45:02.787343 Final DQM duty delay cell = -4
2266 00:45:02.787412 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2267 00:45:02.787481 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2268 00:45:02.787549 [-4] AVG Duty = 4953%(X100)
2269 00:45:02.787618
2270 00:45:02.787685 ==DQM 1 ==
2271 00:45:02.787755 Final DQM duty delay cell = -4
2272 00:45:02.787824 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2273 00:45:02.787893 [-4] MIN Duty = 4875%(X100), DQS PI = 58
2274 00:45:02.787962 [-4] AVG Duty = 4968%(X100)
2275 00:45:02.788031
2276 00:45:02.788100 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2277 00:45:02.788169
2278 00:45:02.788236 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2279 00:45:02.788304 [DutyScan_Calibration_Flow] ====Done====
2280 00:45:02.788372
2281 00:45:02.788439 [DutyScan_Calibration_Flow] k_type=2
2282 00:45:02.788508
2283 00:45:02.788576 ==DQ 0 ==
2284 00:45:02.788644 Final DQ duty delay cell = 0
2285 00:45:02.788713 [0] MAX Duty = 5093%(X100), DQS PI = 0
2286 00:45:02.788782 [0] MIN Duty = 4969%(X100), DQS PI = 42
2287 00:45:02.788851 [0] AVG Duty = 5031%(X100)
2288 00:45:02.788918
2289 00:45:02.788986 ==DQ 1 ==
2290 00:45:02.789054 Final DQ duty delay cell = 0
2291 00:45:02.789123 [0] MAX Duty = 5031%(X100), DQS PI = 8
2292 00:45:02.789191 [0] MIN Duty = 4875%(X100), DQS PI = 0
2293 00:45:02.789260 [0] AVG Duty = 4953%(X100)
2294 00:45:02.789327
2295 00:45:02.789394 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2296 00:45:02.789462
2297 00:45:02.789530 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2298 00:45:02.789598 [DutyScan_Calibration_Flow] ====Done====
2299 00:45:02.789665 nWR fixed to 30
2300 00:45:02.789733 [ModeRegInit_LP4] CH0 RK0
2301 00:45:02.789801 [ModeRegInit_LP4] CH0 RK1
2302 00:45:02.789868 [ModeRegInit_LP4] CH1 RK0
2303 00:45:02.789935 [ModeRegInit_LP4] CH1 RK1
2304 00:45:02.790002 match AC timing 6
2305 00:45:02.790069 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2306 00:45:02.790137 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2307 00:45:02.790238 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2308 00:45:02.790312 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2309 00:45:02.790382 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2310 00:45:02.790657 ==
2311 00:45:02.790727 Dram Type= 6, Freq= 0, CH_0, rank 0
2312 00:45:02.790789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2313 00:45:02.790851 ==
2314 00:45:02.790912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2315 00:45:02.790972 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2316 00:45:02.791033 [CA 0] Center 39 (9~70) winsize 62
2317 00:45:02.791093 [CA 1] Center 39 (8~70) winsize 63
2318 00:45:02.791154 [CA 2] Center 36 (5~67) winsize 63
2319 00:45:02.791215 [CA 3] Center 35 (4~66) winsize 63
2320 00:45:02.791274 [CA 4] Center 34 (3~65) winsize 63
2321 00:45:02.791334 [CA 5] Center 33 (3~64) winsize 62
2322 00:45:02.791394
2323 00:45:02.791453 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2324 00:45:02.791512
2325 00:45:02.791571 [CATrainingPosCal] consider 1 rank data
2326 00:45:02.791631 u2DelayCellTimex100 = 270/100 ps
2327 00:45:02.791691 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2328 00:45:02.791751 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2329 00:45:02.791812 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2330 00:45:02.791871 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2331 00:45:02.791931 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2332 00:45:02.791990 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2333 00:45:02.792051
2334 00:45:02.792112 CA PerBit enable=1, Macro0, CA PI delay=33
2335 00:45:02.792171
2336 00:45:02.792251 [CBTSetCACLKResult] CA Dly = 33
2337 00:45:02.792360 CS Dly: 7 (0~38)
2338 00:45:02.792431 ==
2339 00:45:02.792493 Dram Type= 6, Freq= 0, CH_0, rank 1
2340 00:45:02.792554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2341 00:45:02.792615 ==
2342 00:45:02.792674 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2343 00:45:02.792736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2344 00:45:02.792797 [CA 0] Center 39 (8~70) winsize 63
2345 00:45:02.792857 [CA 1] Center 39 (8~70) winsize 63
2346 00:45:02.792917 [CA 2] Center 36 (5~67) winsize 63
2347 00:45:02.792977 [CA 3] Center 35 (4~66) winsize 63
2348 00:45:02.793037 [CA 4] Center 33 (3~64) winsize 62
2349 00:45:02.793097 [CA 5] Center 34 (3~65) winsize 63
2350 00:45:02.793157
2351 00:45:02.793217 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2352 00:45:02.793277
2353 00:45:02.793338 [CATrainingPosCal] consider 2 rank data
2354 00:45:02.793399 u2DelayCellTimex100 = 270/100 ps
2355 00:45:02.793458 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2356 00:45:02.793518 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2357 00:45:02.793578 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2358 00:45:02.793637 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2359 00:45:02.793705 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2360 00:45:02.793767 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2361 00:45:02.793828
2362 00:45:02.793888 CA PerBit enable=1, Macro0, CA PI delay=33
2363 00:45:02.793948
2364 00:45:02.794007 [CBTSetCACLKResult] CA Dly = 33
2365 00:45:02.794067 CS Dly: 7 (0~39)
2366 00:45:02.794127
2367 00:45:02.794187 ----->DramcWriteLeveling(PI) begin...
2368 00:45:02.794261 ==
2369 00:45:02.794321 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 00:45:02.794382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2371 00:45:02.794443 ==
2372 00:45:02.794504 Write leveling (Byte 0): 28 => 28
2373 00:45:02.794565 Write leveling (Byte 1): 26 => 26
2374 00:45:02.794626 DramcWriteLeveling(PI) end<-----
2375 00:45:02.794687
2376 00:45:02.794746 ==
2377 00:45:02.794806 Dram Type= 6, Freq= 0, CH_0, rank 0
2378 00:45:02.794889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2379 00:45:02.794953 ==
2380 00:45:02.795013 [Gating] SW mode calibration
2381 00:45:02.795075 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2382 00:45:02.795137 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2383 00:45:02.795197 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2384 00:45:02.795257 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2385 00:45:02.795317 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2386 00:45:02.795377 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2387 00:45:02.795448 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2388 00:45:02.795502 0 11 20 | B1->B0 | 2b2b 2727 | 0 0 | (0 1) (0 1)
2389 00:45:02.795556 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2390 00:45:02.795609 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2391 00:45:02.795664 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2392 00:45:02.795718 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2393 00:45:02.795772 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2394 00:45:02.795826 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2395 00:45:02.795880 0 12 16 | B1->B0 | 2424 2c2c | 0 1 | (0 0) (0 0)
2396 00:45:02.795934 0 12 20 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
2397 00:45:02.795988 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2398 00:45:02.796043 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2399 00:45:02.796097 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2400 00:45:02.796151 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2401 00:45:02.796204 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2402 00:45:02.796259 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2403 00:45:02.796314 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2404 00:45:02.796367 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2405 00:45:02.796421 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 00:45:02.796475 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 00:45:02.796529 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 00:45:02.796582 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 00:45:02.796638 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 00:45:02.796692 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 00:45:02.796745 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 00:45:02.796799 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 00:45:02.796852 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 00:45:02.796905 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 00:45:02.796959 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 00:45:02.797013 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 00:45:02.797260 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 00:45:02.797324 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 00:45:02.797380 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2420 00:45:02.797434 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2421 00:45:02.797488 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2422 00:45:02.797541 Total UI for P1: 0, mck2ui 16
2423 00:45:02.797597 best dqsien dly found for B0: ( 0, 15, 18)
2424 00:45:02.797651 Total UI for P1: 0, mck2ui 16
2425 00:45:02.797705 best dqsien dly found for B1: ( 0, 15, 20)
2426 00:45:02.797759 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2427 00:45:02.797814 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2428 00:45:02.797867
2429 00:45:02.797921 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2430 00:45:02.797974 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2431 00:45:02.798028 [Gating] SW calibration Done
2432 00:45:02.798082 ==
2433 00:45:02.798137 Dram Type= 6, Freq= 0, CH_0, rank 0
2434 00:45:02.798192 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2435 00:45:02.798255 ==
2436 00:45:02.798309 RX Vref Scan: 0
2437 00:45:02.798364
2438 00:45:02.798418 RX Vref 0 -> 0, step: 1
2439 00:45:02.798471
2440 00:45:02.798524 RX Delay -40 -> 252, step: 8
2441 00:45:02.798577 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2442 00:45:02.798631 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2443 00:45:02.798685 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2444 00:45:02.798739 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2445 00:45:02.798793 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2446 00:45:02.798847 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2447 00:45:02.798901 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2448 00:45:02.798955 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2449 00:45:02.799007 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2450 00:45:02.799069 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2451 00:45:02.799125 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2452 00:45:02.799180 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2453 00:45:02.799234 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2454 00:45:02.799288 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2455 00:45:02.799343 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2456 00:45:02.799396 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2457 00:45:02.799450 ==
2458 00:45:02.799503 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 00:45:02.799557 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2460 00:45:02.799612 ==
2461 00:45:02.799666 DQS Delay:
2462 00:45:02.799720 DQS0 = 0, DQS1 = 0
2463 00:45:02.799774 DQM Delay:
2464 00:45:02.799828 DQM0 = 115, DQM1 = 106
2465 00:45:02.799883 DQ Delay:
2466 00:45:02.799937 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2467 00:45:02.799992 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2468 00:45:02.800046 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2469 00:45:02.800100 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2470 00:45:02.800153
2471 00:45:02.800207
2472 00:45:02.800261 ==
2473 00:45:02.800314 Dram Type= 6, Freq= 0, CH_0, rank 0
2474 00:45:02.800368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2475 00:45:02.800436 ==
2476 00:45:02.800484
2477 00:45:02.800532
2478 00:45:02.800580 TX Vref Scan disable
2479 00:45:02.800630 == TX Byte 0 ==
2480 00:45:02.800679 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2481 00:45:02.800728 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2482 00:45:02.800778 == TX Byte 1 ==
2483 00:45:02.800826 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2484 00:45:02.800875 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2485 00:45:02.800924 ==
2486 00:45:02.800973 Dram Type= 6, Freq= 0, CH_0, rank 0
2487 00:45:02.801023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2488 00:45:02.801072 ==
2489 00:45:02.801121 TX Vref=22, minBit 8, minWin=25, winSum=421
2490 00:45:02.801171 TX Vref=24, minBit 8, minWin=24, winSum=420
2491 00:45:02.801220 TX Vref=26, minBit 10, minWin=25, winSum=431
2492 00:45:02.801269 TX Vref=28, minBit 10, minWin=25, winSum=435
2493 00:45:02.801319 TX Vref=30, minBit 8, minWin=26, winSum=433
2494 00:45:02.801368 TX Vref=32, minBit 10, minWin=26, winSum=436
2495 00:45:02.801417 [TxChooseVref] Worse bit 10, Min win 26, Win sum 436, Final Vref 32
2496 00:45:02.801465
2497 00:45:02.801513 Final TX Range 1 Vref 32
2498 00:45:02.801562
2499 00:45:02.801610 ==
2500 00:45:02.801659 Dram Type= 6, Freq= 0, CH_0, rank 0
2501 00:45:02.801708 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2502 00:45:02.801757 ==
2503 00:45:02.801805
2504 00:45:02.801852
2505 00:45:02.801900 TX Vref Scan disable
2506 00:45:02.801949 == TX Byte 0 ==
2507 00:45:02.801998 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2508 00:45:02.802047 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2509 00:45:02.802096 == TX Byte 1 ==
2510 00:45:02.802144 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2511 00:45:02.802194 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2512 00:45:02.802249
2513 00:45:02.802299 [DATLAT]
2514 00:45:02.802348 Freq=1200, CH0 RK0
2515 00:45:02.802398
2516 00:45:02.802446 DATLAT Default: 0xd
2517 00:45:02.802494 0, 0xFFFF, sum = 0
2518 00:45:02.802544 1, 0xFFFF, sum = 0
2519 00:45:02.802594 2, 0xFFFF, sum = 0
2520 00:45:02.802644 3, 0xFFFF, sum = 0
2521 00:45:02.802696 4, 0xFFFF, sum = 0
2522 00:45:02.802746 5, 0xFFFF, sum = 0
2523 00:45:02.802795 6, 0xFFFF, sum = 0
2524 00:45:02.802845 7, 0xFFFF, sum = 0
2525 00:45:02.802894 8, 0xFFFF, sum = 0
2526 00:45:02.802944 9, 0xFFFF, sum = 0
2527 00:45:02.802994 10, 0xFFFF, sum = 0
2528 00:45:02.803045 11, 0x0, sum = 1
2529 00:45:02.803095 12, 0x0, sum = 2
2530 00:45:02.803144 13, 0x0, sum = 3
2531 00:45:02.803194 14, 0x0, sum = 4
2532 00:45:02.803243 best_step = 12
2533 00:45:02.803291
2534 00:45:02.803339 ==
2535 00:45:02.803388 Dram Type= 6, Freq= 0, CH_0, rank 0
2536 00:45:02.803437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2537 00:45:02.803487 ==
2538 00:45:02.803536 RX Vref Scan: 1
2539 00:45:02.803585
2540 00:45:02.803633 Set Vref Range= 32 -> 127
2541 00:45:02.803683
2542 00:45:02.803731 RX Vref 32 -> 127, step: 1
2543 00:45:02.803780
2544 00:45:02.803828 RX Delay -21 -> 252, step: 4
2545 00:45:02.803876
2546 00:45:02.803925 Set Vref, RX VrefLevel [Byte0]: 32
2547 00:45:02.803974 [Byte1]: 32
2548 00:45:02.804023
2549 00:45:02.804072 Set Vref, RX VrefLevel [Byte0]: 33
2550 00:45:02.804121 [Byte1]: 33
2551 00:45:02.804170
2552 00:45:02.804217 Set Vref, RX VrefLevel [Byte0]: 34
2553 00:45:02.804266 [Byte1]: 34
2554 00:45:02.804320
2555 00:45:02.804370 Set Vref, RX VrefLevel [Byte0]: 35
2556 00:45:02.804419 [Byte1]: 35
2557 00:45:02.804469
2558 00:45:02.804518 Set Vref, RX VrefLevel [Byte0]: 36
2559 00:45:02.804567 [Byte1]: 36
2560 00:45:02.804616
2561 00:45:02.804665 Set Vref, RX VrefLevel [Byte0]: 37
2562 00:45:02.804714 [Byte1]: 37
2563 00:45:02.804764
2564 00:45:02.804812 Set Vref, RX VrefLevel [Byte0]: 38
2565 00:45:02.805060 [Byte1]: 38
2566 00:45:02.805116
2567 00:45:02.805166 Set Vref, RX VrefLevel [Byte0]: 39
2568 00:45:02.805216 [Byte1]: 39
2569 00:45:02.805266
2570 00:45:02.805315 Set Vref, RX VrefLevel [Byte0]: 40
2571 00:45:02.805365 [Byte1]: 40
2572 00:45:02.805426
2573 00:45:02.805474 Set Vref, RX VrefLevel [Byte0]: 41
2574 00:45:02.805521 [Byte1]: 41
2575 00:45:02.805568
2576 00:45:02.805615 Set Vref, RX VrefLevel [Byte0]: 42
2577 00:45:02.805662 [Byte1]: 42
2578 00:45:02.805708
2579 00:45:02.805754 Set Vref, RX VrefLevel [Byte0]: 43
2580 00:45:02.805801 [Byte1]: 43
2581 00:45:02.805848
2582 00:45:02.805894 Set Vref, RX VrefLevel [Byte0]: 44
2583 00:45:02.805940 [Byte1]: 44
2584 00:45:02.805986
2585 00:45:02.806033 Set Vref, RX VrefLevel [Byte0]: 45
2586 00:45:02.806079 [Byte1]: 45
2587 00:45:02.806125
2588 00:45:02.806171 Set Vref, RX VrefLevel [Byte0]: 46
2589 00:45:02.806226 [Byte1]: 46
2590 00:45:02.806275
2591 00:45:02.806322 Set Vref, RX VrefLevel [Byte0]: 47
2592 00:45:02.806369 [Byte1]: 47
2593 00:45:02.806416
2594 00:45:02.806462 Set Vref, RX VrefLevel [Byte0]: 48
2595 00:45:02.806508 [Byte1]: 48
2596 00:45:02.806554
2597 00:45:02.806601 Set Vref, RX VrefLevel [Byte0]: 49
2598 00:45:02.806648 [Byte1]: 49
2599 00:45:02.806694
2600 00:45:02.806740 Set Vref, RX VrefLevel [Byte0]: 50
2601 00:45:02.806786 [Byte1]: 50
2602 00:45:02.806833
2603 00:45:02.806878 Set Vref, RX VrefLevel [Byte0]: 51
2604 00:45:02.806925 [Byte1]: 51
2605 00:45:02.806972
2606 00:45:02.807018 Set Vref, RX VrefLevel [Byte0]: 52
2607 00:45:02.807065 [Byte1]: 52
2608 00:45:02.807113
2609 00:45:02.807159 Set Vref, RX VrefLevel [Byte0]: 53
2610 00:45:02.807206 [Byte1]: 53
2611 00:45:02.807252
2612 00:45:02.807299 Set Vref, RX VrefLevel [Byte0]: 54
2613 00:45:02.807345 [Byte1]: 54
2614 00:45:02.807392
2615 00:45:02.807438 Set Vref, RX VrefLevel [Byte0]: 55
2616 00:45:02.807484 [Byte1]: 55
2617 00:45:02.807530
2618 00:45:02.807577 Set Vref, RX VrefLevel [Byte0]: 56
2619 00:45:02.807624 [Byte1]: 56
2620 00:45:02.807670
2621 00:45:02.807716 Set Vref, RX VrefLevel [Byte0]: 57
2622 00:45:02.807763 [Byte1]: 57
2623 00:45:02.807809
2624 00:45:02.807854 Set Vref, RX VrefLevel [Byte0]: 58
2625 00:45:02.807901 [Byte1]: 58
2626 00:45:02.807947
2627 00:45:02.807993 Set Vref, RX VrefLevel [Byte0]: 59
2628 00:45:02.808040 [Byte1]: 59
2629 00:45:02.808086
2630 00:45:02.808132 Set Vref, RX VrefLevel [Byte0]: 60
2631 00:45:02.808178 [Byte1]: 60
2632 00:45:02.808225
2633 00:45:02.808271 Set Vref, RX VrefLevel [Byte0]: 61
2634 00:45:02.808318 [Byte1]: 61
2635 00:45:02.808364
2636 00:45:02.808410 Set Vref, RX VrefLevel [Byte0]: 62
2637 00:45:02.808456 [Byte1]: 62
2638 00:45:02.808503
2639 00:45:02.808549 Set Vref, RX VrefLevel [Byte0]: 63
2640 00:45:02.808596 [Byte1]: 63
2641 00:45:02.808643
2642 00:45:02.808689 Set Vref, RX VrefLevel [Byte0]: 64
2643 00:45:02.808735 [Byte1]: 64
2644 00:45:02.808782
2645 00:45:02.808828 Set Vref, RX VrefLevel [Byte0]: 65
2646 00:45:02.808874 [Byte1]: 65
2647 00:45:02.808921
2648 00:45:02.808967 Set Vref, RX VrefLevel [Byte0]: 66
2649 00:45:02.809014 [Byte1]: 66
2650 00:45:02.809060
2651 00:45:02.809107 Set Vref, RX VrefLevel [Byte0]: 67
2652 00:45:02.809153 [Byte1]: 67
2653 00:45:02.809199
2654 00:45:02.809245 Set Vref, RX VrefLevel [Byte0]: 68
2655 00:45:02.809291 [Byte1]: 68
2656 00:45:02.809338
2657 00:45:02.809385 Final RX Vref Byte 0 = 48 to rank0
2658 00:45:02.809433 Final RX Vref Byte 1 = 48 to rank0
2659 00:45:02.809480 Final RX Vref Byte 0 = 48 to rank1
2660 00:45:02.809527 Final RX Vref Byte 1 = 48 to rank1==
2661 00:45:02.809574 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 00:45:02.809621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2663 00:45:02.809678 ==
2664 00:45:02.809725 DQS Delay:
2665 00:45:02.809771 DQS0 = 0, DQS1 = 0
2666 00:45:02.809818 DQM Delay:
2667 00:45:02.809865 DQM0 = 114, DQM1 = 105
2668 00:45:02.809912 DQ Delay:
2669 00:45:02.809959 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =110
2670 00:45:02.810006 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2671 00:45:02.810052 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2672 00:45:02.810099 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2673 00:45:02.810145
2674 00:45:02.810190
2675 00:45:02.810281 [DQSOSCAuto] RK0, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2676 00:45:02.810345 CH0 RK0: MR19=404, MR18=707
2677 00:45:02.810393 CH0_RK0: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
2678 00:45:02.810440
2679 00:45:02.810487 ----->DramcWriteLeveling(PI) begin...
2680 00:45:02.810535 ==
2681 00:45:02.810582 Dram Type= 6, Freq= 0, CH_0, rank 1
2682 00:45:02.810635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2683 00:45:02.810687 ==
2684 00:45:02.810734 Write leveling (Byte 0): 28 => 28
2685 00:45:02.810780 Write leveling (Byte 1): 26 => 26
2686 00:45:02.810827 DramcWriteLeveling(PI) end<-----
2687 00:45:02.810873
2688 00:45:02.810919 ==
2689 00:45:02.810967 Dram Type= 6, Freq= 0, CH_0, rank 1
2690 00:45:02.811013 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2691 00:45:02.811060 ==
2692 00:45:02.811107 [Gating] SW mode calibration
2693 00:45:02.811153 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2694 00:45:02.811201 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2695 00:45:02.811248 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2696 00:45:02.811297 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2697 00:45:02.811344 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2698 00:45:02.811392 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2699 00:45:02.811438 0 11 16 | B1->B0 | 3434 3232 | 1 1 | (1 0) (0 0)
2700 00:45:02.811485 0 11 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
2701 00:45:02.811531 0 11 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2702 00:45:02.811577 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2703 00:45:02.811624 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2704 00:45:02.811671 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2705 00:45:02.811717 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2706 00:45:02.811764 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2707 00:45:02.811998 0 12 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2708 00:45:02.812056 0 12 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2709 00:45:02.812104 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2710 00:45:02.812152 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2711 00:45:02.812199 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2712 00:45:02.812247 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2713 00:45:02.812294 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2714 00:45:02.812341 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2715 00:45:02.812387 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2716 00:45:02.812434 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2717 00:45:02.812481 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 00:45:02.812528 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 00:45:02.812575 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 00:45:02.812622 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 00:45:02.812669 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 00:45:02.812715 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 00:45:02.812762 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 00:45:02.812808 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 00:45:02.812856 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 00:45:02.812902 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 00:45:02.812949 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2728 00:45:02.812996 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 00:45:02.813044 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2730 00:45:02.813091 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2731 00:45:02.813138 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2732 00:45:02.813185 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2733 00:45:02.813231 Total UI for P1: 0, mck2ui 16
2734 00:45:02.813278 best dqsien dly found for B0: ( 0, 15, 16)
2735 00:45:02.813325 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2736 00:45:02.813372 Total UI for P1: 0, mck2ui 16
2737 00:45:02.813419 best dqsien dly found for B1: ( 0, 15, 20)
2738 00:45:02.813466 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2739 00:45:02.813513 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2740 00:45:02.813560
2741 00:45:02.813606 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2742 00:45:02.813654 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2743 00:45:02.813701 [Gating] SW calibration Done
2744 00:45:02.813747 ==
2745 00:45:02.813794 Dram Type= 6, Freq= 0, CH_0, rank 1
2746 00:45:02.813841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2747 00:45:02.813888 ==
2748 00:45:02.813935 RX Vref Scan: 0
2749 00:45:02.813982
2750 00:45:02.814028 RX Vref 0 -> 0, step: 1
2751 00:45:02.814075
2752 00:45:02.814121 RX Delay -40 -> 252, step: 8
2753 00:45:02.814168 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2754 00:45:02.814220 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2755 00:45:02.814305 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2756 00:45:02.814351 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2757 00:45:02.814397 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2758 00:45:02.814443 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2759 00:45:02.814490 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2760 00:45:02.814536 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2761 00:45:02.814582 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2762 00:45:02.814629 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2763 00:45:02.814686 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2764 00:45:02.814734 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2765 00:45:02.814781 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2766 00:45:02.814828 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
2767 00:45:02.814876 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2768 00:45:02.814923 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2769 00:45:02.814969 ==
2770 00:45:02.815016 Dram Type= 6, Freq= 0, CH_0, rank 1
2771 00:45:02.815064 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2772 00:45:02.815110 ==
2773 00:45:02.815157 DQS Delay:
2774 00:45:02.815203 DQS0 = 0, DQS1 = 0
2775 00:45:02.815251 DQM Delay:
2776 00:45:02.815297 DQM0 = 114, DQM1 = 106
2777 00:45:02.815344 DQ Delay:
2778 00:45:02.815390 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2779 00:45:02.815437 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2780 00:45:02.815484 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2781 00:45:02.815531 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2782 00:45:02.815577
2783 00:45:02.815623
2784 00:45:02.815669 ==
2785 00:45:02.815716 Dram Type= 6, Freq= 0, CH_0, rank 1
2786 00:45:02.815763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2787 00:45:02.815810 ==
2788 00:45:02.815856
2789 00:45:02.815901
2790 00:45:02.815947 TX Vref Scan disable
2791 00:45:02.815993 == TX Byte 0 ==
2792 00:45:02.816040 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2793 00:45:02.816086 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2794 00:45:02.816132 == TX Byte 1 ==
2795 00:45:02.816179 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2796 00:45:02.816226 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2797 00:45:02.816272 ==
2798 00:45:02.816318 Dram Type= 6, Freq= 0, CH_0, rank 1
2799 00:45:02.816364 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2800 00:45:02.816411 ==
2801 00:45:02.816458 TX Vref=22, minBit 13, minWin=25, winSum=421
2802 00:45:02.816505 TX Vref=24, minBit 9, minWin=25, winSum=425
2803 00:45:02.816552 TX Vref=26, minBit 1, minWin=26, winSum=430
2804 00:45:02.816598 TX Vref=28, minBit 9, minWin=26, winSum=432
2805 00:45:02.816646 TX Vref=30, minBit 9, minWin=26, winSum=436
2806 00:45:02.816693 TX Vref=32, minBit 8, minWin=26, winSum=437
2807 00:45:02.816740 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 32
2808 00:45:02.816788
2809 00:45:02.816834 Final TX Range 1 Vref 32
2810 00:45:02.816881
2811 00:45:02.816927 ==
2812 00:45:02.816973 Dram Type= 6, Freq= 0, CH_0, rank 1
2813 00:45:02.817020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2814 00:45:02.817067 ==
2815 00:45:02.817114
2816 00:45:02.817161
2817 00:45:02.817207 TX Vref Scan disable
2818 00:45:02.817253 == TX Byte 0 ==
2819 00:45:02.817300 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2820 00:45:02.817347 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2821 00:45:02.817393 == TX Byte 1 ==
2822 00:45:02.817438 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2823 00:45:02.817669 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2824 00:45:02.817722
2825 00:45:02.817770 [DATLAT]
2826 00:45:02.817817 Freq=1200, CH0 RK1
2827 00:45:02.817865
2828 00:45:02.817912 DATLAT Default: 0xc
2829 00:45:02.817960 0, 0xFFFF, sum = 0
2830 00:45:02.818008 1, 0xFFFF, sum = 0
2831 00:45:02.818055 2, 0xFFFF, sum = 0
2832 00:45:02.818103 3, 0xFFFF, sum = 0
2833 00:45:02.818150 4, 0xFFFF, sum = 0
2834 00:45:02.818197 5, 0xFFFF, sum = 0
2835 00:45:02.818286 6, 0xFFFF, sum = 0
2836 00:45:02.818334 7, 0xFFFF, sum = 0
2837 00:45:02.818383 8, 0xFFFF, sum = 0
2838 00:45:02.818430 9, 0xFFFF, sum = 0
2839 00:45:02.818477 10, 0xFFFF, sum = 0
2840 00:45:02.818524 11, 0x0, sum = 1
2841 00:45:02.818571 12, 0x0, sum = 2
2842 00:45:02.818619 13, 0x0, sum = 3
2843 00:45:02.818667 14, 0x0, sum = 4
2844 00:45:02.818714 best_step = 12
2845 00:45:02.818760
2846 00:45:02.818806 ==
2847 00:45:02.818852 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 00:45:02.818899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2849 00:45:02.818946 ==
2850 00:45:02.818993 RX Vref Scan: 0
2851 00:45:02.819040
2852 00:45:02.819086 RX Vref 0 -> 0, step: 1
2853 00:45:02.819133
2854 00:45:02.819180 RX Delay -21 -> 252, step: 4
2855 00:45:02.819228 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2856 00:45:02.819274 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2857 00:45:02.819322 iDelay=195, Bit 2, Center 114 (43 ~ 186) 144
2858 00:45:02.819369 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2859 00:45:02.819416 iDelay=195, Bit 4, Center 116 (43 ~ 190) 148
2860 00:45:02.819463 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
2861 00:45:02.819510 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2862 00:45:02.819557 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2863 00:45:02.819604 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2864 00:45:02.819651 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2865 00:45:02.819698 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2866 00:45:02.819745 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2867 00:45:02.819792 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2868 00:45:02.819839 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2869 00:45:02.819892 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
2870 00:45:02.819941 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2871 00:45:02.819988 ==
2872 00:45:02.820035 Dram Type= 6, Freq= 0, CH_0, rank 1
2873 00:45:02.820083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2874 00:45:02.820130 ==
2875 00:45:02.820176 DQS Delay:
2876 00:45:02.820223 DQS0 = 0, DQS1 = 0
2877 00:45:02.820270 DQM Delay:
2878 00:45:02.820317 DQM0 = 114, DQM1 = 105
2879 00:45:02.820364 DQ Delay:
2880 00:45:02.820410 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2881 00:45:02.820458 DQ4 =116, DQ5 =106, DQ6 =124, DQ7 =122
2882 00:45:02.820506 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2883 00:45:02.820553 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2884 00:45:02.820599
2885 00:45:02.820646
2886 00:45:02.820692 [DQSOSCAuto] RK1, (LSB)MR18= 0x1010, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2887 00:45:02.820740 CH0 RK1: MR19=404, MR18=1010
2888 00:45:02.820788 CH0_RK1: MR19=0x404, MR18=0x1010, DQSOSC=403, MR23=63, INC=40, DEC=26
2889 00:45:02.820835 [RxdqsGatingPostProcess] freq 1200
2890 00:45:02.820882 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2891 00:45:02.820931 Pre-setting of DQS Precalculation
2892 00:45:02.820978 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2893 00:45:02.821024 ==
2894 00:45:02.821071 Dram Type= 6, Freq= 0, CH_1, rank 0
2895 00:45:02.821118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2896 00:45:02.821165 ==
2897 00:45:02.821212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2898 00:45:02.821259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2899 00:45:02.821307 [CA 0] Center 37 (7~68) winsize 62
2900 00:45:02.821354 [CA 1] Center 37 (7~68) winsize 62
2901 00:45:02.821401 [CA 2] Center 34 (4~65) winsize 62
2902 00:45:02.821447 [CA 3] Center 33 (3~64) winsize 62
2903 00:45:02.821494 [CA 4] Center 32 (2~63) winsize 62
2904 00:45:02.821540 [CA 5] Center 32 (2~63) winsize 62
2905 00:45:02.821587
2906 00:45:02.821633 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2907 00:45:02.821680
2908 00:45:02.821727 [CATrainingPosCal] consider 1 rank data
2909 00:45:02.821774 u2DelayCellTimex100 = 270/100 ps
2910 00:45:02.821821 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2911 00:45:02.821867 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2912 00:45:02.821914 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2913 00:45:02.821960 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2914 00:45:02.822007 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2915 00:45:02.822054 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2916 00:45:02.822101
2917 00:45:02.822147 CA PerBit enable=1, Macro0, CA PI delay=32
2918 00:45:02.822194
2919 00:45:02.822286 [CBTSetCACLKResult] CA Dly = 32
2920 00:45:02.822335 CS Dly: 6 (0~37)
2921 00:45:02.822381 ==
2922 00:45:02.822428 Dram Type= 6, Freq= 0, CH_1, rank 1
2923 00:45:02.822475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2924 00:45:02.822521 ==
2925 00:45:02.822568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2926 00:45:02.822615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2927 00:45:02.822662 [CA 0] Center 37 (7~68) winsize 62
2928 00:45:02.822709 [CA 1] Center 37 (7~68) winsize 62
2929 00:45:03.038510 [CA 2] Center 34 (3~65) winsize 63
2930 00:45:03.039234 [CA 3] Center 33 (3~64) winsize 62
2931 00:45:03.039793 [CA 4] Center 32 (2~63) winsize 62
2932 00:45:03.040322 [CA 5] Center 32 (1~63) winsize 63
2933 00:45:03.040838
2934 00:45:03.041344 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2935 00:45:03.041851
2936 00:45:03.042372 [CATrainingPosCal] consider 2 rank data
2937 00:45:03.042877 u2DelayCellTimex100 = 270/100 ps
2938 00:45:03.043374 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2939 00:45:03.043870 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2940 00:45:03.044361 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2941 00:45:03.044867 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2942 00:45:03.045372 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2943 00:45:03.045843 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2944 00:45:03.046333
2945 00:45:03.046787 CA PerBit enable=1, Macro0, CA PI delay=32
2946 00:45:03.047239
2947 00:45:03.047732 [CBTSetCACLKResult] CA Dly = 32
2948 00:45:03.048223 CS Dly: 6 (0~38)
2949 00:45:03.048704
2950 00:45:03.049144 ----->DramcWriteLeveling(PI) begin...
2951 00:45:03.049599 ==
2952 00:45:03.050046 Dram Type= 6, Freq= 0, CH_1, rank 0
2953 00:45:03.050520 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2954 00:45:03.050970 ==
2955 00:45:03.051413 Write leveling (Byte 0): 22 => 22
2956 00:45:03.051858 Write leveling (Byte 1): 23 => 23
2957 00:45:03.052720 DramcWriteLeveling(PI) end<-----
2958 00:45:03.053210
2959 00:45:03.053675 ==
2960 00:45:03.054133 Dram Type= 6, Freq= 0, CH_1, rank 0
2961 00:45:03.054625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2962 00:45:03.055084 ==
2963 00:45:03.055537 [Gating] SW mode calibration
2964 00:45:03.056003 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2965 00:45:03.056497 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2966 00:45:03.056965 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2967 00:45:03.057419 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2968 00:45:03.057872 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2969 00:45:03.058362 0 11 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2970 00:45:03.058819 0 11 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
2971 00:45:03.059269 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 00:45:03.059710 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2973 00:45:03.060152 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2974 00:45:03.060600 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2975 00:45:03.061046 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2976 00:45:03.061493 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2977 00:45:03.061939 0 12 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2978 00:45:03.062400 0 12 16 | B1->B0 | 3333 4343 | 0 0 | (0 0) (0 0)
2979 00:45:03.062853 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 00:45:03.063304 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 00:45:03.063761 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 00:45:03.064206 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 00:45:03.064651 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2984 00:45:03.065098 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2985 00:45:03.065527 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2986 00:45:03.065843 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2987 00:45:03.066156 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 00:45:03.066492 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 00:45:03.066811 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 00:45:03.067126 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 00:45:03.067443 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 00:45:03.067755 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 00:45:03.068069 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 00:45:03.068386 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 00:45:03.068697 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 00:45:03.069009 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 00:45:03.069319 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 00:45:03.069632 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 00:45:03.069945 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 00:45:03.070283 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 00:45:03.070570 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 00:45:03.070808 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3003 00:45:03.071048 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3004 00:45:03.071286 Total UI for P1: 0, mck2ui 16
3005 00:45:03.071528 best dqsien dly found for B0: ( 0, 15, 16)
3006 00:45:03.071772 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3007 00:45:03.072010 Total UI for P1: 0, mck2ui 16
3008 00:45:03.072250 best dqsien dly found for B1: ( 0, 15, 18)
3009 00:45:03.072487 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3010 00:45:03.072724 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3011 00:45:03.072961
3012 00:45:03.073194 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3013 00:45:03.073430 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3014 00:45:03.073665 [Gating] SW calibration Done
3015 00:45:03.073900 ==
3016 00:45:03.074135 Dram Type= 6, Freq= 0, CH_1, rank 0
3017 00:45:03.074386 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3018 00:45:03.074626 ==
3019 00:45:03.074864 RX Vref Scan: 0
3020 00:45:03.075101
3021 00:45:03.075334 RX Vref 0 -> 0, step: 1
3022 00:45:03.075553
3023 00:45:03.075742 RX Delay -40 -> 252, step: 8
3024 00:45:03.075935 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3025 00:45:03.076130 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3026 00:45:03.076325 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3027 00:45:03.076520 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3028 00:45:03.076710 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3029 00:45:03.076901 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3030 00:45:03.077091 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3031 00:45:03.077284 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3032 00:45:03.077433 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3033 00:45:03.077582 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3034 00:45:03.077728 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3035 00:45:03.077915 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3036 00:45:03.078061 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3037 00:45:03.078283 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3038 00:45:03.078563 iDelay=208, Bit 14, Center 111 (40 ~ 183) 144
3039 00:45:03.078779 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3040 00:45:03.078989 ==
3041 00:45:03.079167 Dram Type= 6, Freq= 0, CH_1, rank 0
3042 00:45:03.079340 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3043 00:45:03.079510 ==
3044 00:45:03.079679 DQS Delay:
3045 00:45:03.079846 DQS0 = 0, DQS1 = 0
3046 00:45:03.080014 DQM Delay:
3047 00:45:03.080181 DQM0 = 116, DQM1 = 106
3048 00:45:03.080354 DQ Delay:
3049 00:45:03.080521 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3050 00:45:03.080661 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3051 00:45:03.080801 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3052 00:45:03.080947 DQ12 =115, DQ13 =119, DQ14 =111, DQ15 =115
3053 00:45:03.081088
3054 00:45:03.081227
3055 00:45:03.081365 ==
3056 00:45:03.081506 Dram Type= 6, Freq= 0, CH_1, rank 0
3057 00:45:03.081647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3058 00:45:03.081787 ==
3059 00:45:03.081926
3060 00:45:03.082064
3061 00:45:03.082202 TX Vref Scan disable
3062 00:45:03.082314 == TX Byte 0 ==
3063 00:45:03.082406 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3064 00:45:03.082719 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3065 00:45:03.082826 == TX Byte 1 ==
3066 00:45:03.082917 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3067 00:45:03.083008 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3068 00:45:03.083104 ==
3069 00:45:03.083219 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 00:45:03.083314 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3071 00:45:03.083405 ==
3072 00:45:03.083495 TX Vref=22, minBit 8, minWin=25, winSum=416
3073 00:45:03.083586 TX Vref=24, minBit 8, minWin=25, winSum=418
3074 00:45:03.083689 TX Vref=26, minBit 11, minWin=25, winSum=421
3075 00:45:03.083782 TX Vref=28, minBit 8, minWin=26, winSum=431
3076 00:45:03.083884 TX Vref=30, minBit 8, minWin=26, winSum=432
3077 00:45:03.083976 TX Vref=32, minBit 8, minWin=26, winSum=432
3078 00:45:03.084067 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
3079 00:45:03.084157
3080 00:45:03.084246 Final TX Range 1 Vref 30
3081 00:45:03.084337
3082 00:45:03.084425 ==
3083 00:45:03.084514 Dram Type= 6, Freq= 0, CH_1, rank 0
3084 00:45:03.084603 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3085 00:45:03.084692 ==
3086 00:45:03.084780
3087 00:45:03.084868
3088 00:45:03.084994 TX Vref Scan disable
3089 00:45:03.085135 == TX Byte 0 ==
3090 00:45:03.085276 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3091 00:45:03.085414 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3092 00:45:03.085509 == TX Byte 1 ==
3093 00:45:03.085585 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3094 00:45:03.085661 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3095 00:45:03.085738
3096 00:45:03.085814 [DATLAT]
3097 00:45:03.085890 Freq=1200, CH1 RK0
3098 00:45:03.085966
3099 00:45:03.086041 DATLAT Default: 0xd
3100 00:45:03.086116 0, 0xFFFF, sum = 0
3101 00:45:03.086195 1, 0xFFFF, sum = 0
3102 00:45:03.086287 2, 0xFFFF, sum = 0
3103 00:45:03.086365 3, 0xFFFF, sum = 0
3104 00:45:03.086441 4, 0xFFFF, sum = 0
3105 00:45:03.086519 5, 0xFFFF, sum = 0
3106 00:45:03.086596 6, 0xFFFF, sum = 0
3107 00:45:03.086673 7, 0xFFFF, sum = 0
3108 00:45:03.086749 8, 0xFFFF, sum = 0
3109 00:45:03.086828 9, 0xFFFF, sum = 0
3110 00:45:03.086905 10, 0xFFFF, sum = 0
3111 00:45:03.086981 11, 0x0, sum = 1
3112 00:45:03.087058 12, 0x0, sum = 2
3113 00:45:03.087135 13, 0x0, sum = 3
3114 00:45:03.087212 14, 0x0, sum = 4
3115 00:45:03.087288 best_step = 12
3116 00:45:03.087364
3117 00:45:03.087455 ==
3118 00:45:03.087533 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 00:45:03.087610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3120 00:45:03.087687 ==
3121 00:45:03.087764 RX Vref Scan: 1
3122 00:45:03.087840
3123 00:45:03.087916 Set Vref Range= 32 -> 127
3124 00:45:03.087991
3125 00:45:03.088068 RX Vref 32 -> 127, step: 1
3126 00:45:03.088144
3127 00:45:03.088219 RX Delay -29 -> 252, step: 4
3128 00:45:03.088293
3129 00:45:03.088368 Set Vref, RX VrefLevel [Byte0]: 32
3130 00:45:03.088445 [Byte1]: 32
3131 00:45:03.088528
3132 00:45:03.088688 Set Vref, RX VrefLevel [Byte0]: 33
3133 00:45:03.088858 [Byte1]: 33
3134 00:45:03.088986
3135 00:45:03.089068 Set Vref, RX VrefLevel [Byte0]: 34
3136 00:45:03.089146 [Byte1]: 34
3137 00:45:03.089224
3138 00:45:03.089301 Set Vref, RX VrefLevel [Byte0]: 35
3139 00:45:03.089377 [Byte1]: 35
3140 00:45:03.089453
3141 00:45:03.089530 Set Vref, RX VrefLevel [Byte0]: 36
3142 00:45:03.089607 [Byte1]: 36
3143 00:45:03.089681
3144 00:45:03.089756 Set Vref, RX VrefLevel [Byte0]: 37
3145 00:45:03.089833 [Byte1]: 37
3146 00:45:03.089910
3147 00:45:03.089986 Set Vref, RX VrefLevel [Byte0]: 38
3148 00:45:03.090063 [Byte1]: 38
3149 00:45:03.090139
3150 00:45:03.090225 Set Vref, RX VrefLevel [Byte0]: 39
3151 00:45:03.090306 [Byte1]: 39
3152 00:45:03.090383
3153 00:45:03.090468 Set Vref, RX VrefLevel [Byte0]: 40
3154 00:45:03.090534 [Byte1]: 40
3155 00:45:03.090599
3156 00:45:03.090666 Set Vref, RX VrefLevel [Byte0]: 41
3157 00:45:03.090733 [Byte1]: 41
3158 00:45:03.090799
3159 00:45:03.090866 Set Vref, RX VrefLevel [Byte0]: 42
3160 00:45:03.090958 [Byte1]: 42
3161 00:45:03.091029
3162 00:45:03.091096 Set Vref, RX VrefLevel [Byte0]: 43
3163 00:45:03.091163 [Byte1]: 43
3164 00:45:03.091230
3165 00:45:03.091297 Set Vref, RX VrefLevel [Byte0]: 44
3166 00:45:03.091364 [Byte1]: 44
3167 00:45:03.091430
3168 00:45:03.091497 Set Vref, RX VrefLevel [Byte0]: 45
3169 00:45:03.091563 [Byte1]: 45
3170 00:45:03.091629
3171 00:45:03.091695 Set Vref, RX VrefLevel [Byte0]: 46
3172 00:45:03.091762 [Byte1]: 46
3173 00:45:03.091827
3174 00:45:03.091894 Set Vref, RX VrefLevel [Byte0]: 47
3175 00:45:03.091960 [Byte1]: 47
3176 00:45:03.092026
3177 00:45:03.092092 Set Vref, RX VrefLevel [Byte0]: 48
3178 00:45:03.092158 [Byte1]: 48
3179 00:45:03.092225
3180 00:45:03.092292 Set Vref, RX VrefLevel [Byte0]: 49
3181 00:45:03.092358 [Byte1]: 49
3182 00:45:03.092425
3183 00:45:03.092490 Set Vref, RX VrefLevel [Byte0]: 50
3184 00:45:03.092556 [Byte1]: 50
3185 00:45:03.092623
3186 00:45:03.092689 Set Vref, RX VrefLevel [Byte0]: 51
3187 00:45:03.092756 [Byte1]: 51
3188 00:45:03.092822
3189 00:45:03.092888 Set Vref, RX VrefLevel [Byte0]: 52
3190 00:45:03.092953 [Byte1]: 52
3191 00:45:03.093019
3192 00:45:03.093084 Set Vref, RX VrefLevel [Byte0]: 53
3193 00:45:03.093152 [Byte1]: 53
3194 00:45:03.093217
3195 00:45:03.093283 Set Vref, RX VrefLevel [Byte0]: 54
3196 00:45:03.093349 [Byte1]: 54
3197 00:45:03.093414
3198 00:45:03.093481 Set Vref, RX VrefLevel [Byte0]: 55
3199 00:45:03.093548 [Byte1]: 55
3200 00:45:03.093613
3201 00:45:03.093680 Set Vref, RX VrefLevel [Byte0]: 56
3202 00:45:03.093747 [Byte1]: 56
3203 00:45:03.093813
3204 00:45:03.093879 Set Vref, RX VrefLevel [Byte0]: 57
3205 00:45:03.093944 [Byte1]: 57
3206 00:45:03.094010
3207 00:45:03.094077 Set Vref, RX VrefLevel [Byte0]: 58
3208 00:45:03.094144 [Byte1]: 58
3209 00:45:03.094217
3210 00:45:03.094289 Set Vref, RX VrefLevel [Byte0]: 59
3211 00:45:03.094356 [Byte1]: 59
3212 00:45:03.094422
3213 00:45:03.094489 Set Vref, RX VrefLevel [Byte0]: 60
3214 00:45:03.094555 [Byte1]: 60
3215 00:45:03.094621
3216 00:45:03.094686 Set Vref, RX VrefLevel [Byte0]: 61
3217 00:45:03.094752 [Byte1]: 61
3218 00:45:03.094819
3219 00:45:03.094884 Set Vref, RX VrefLevel [Byte0]: 62
3220 00:45:03.094950 [Byte1]: 62
3221 00:45:03.095016
3222 00:45:03.095082 Set Vref, RX VrefLevel [Byte0]: 63
3223 00:45:03.095148 [Byte1]: 63
3224 00:45:03.095214
3225 00:45:03.095280 Set Vref, RX VrefLevel [Byte0]: 64
3226 00:45:03.095346 [Byte1]: 64
3227 00:45:03.095412
3228 00:45:03.095520 Final RX Vref Byte 0 = 54 to rank0
3229 00:45:03.095876 Final RX Vref Byte 1 = 50 to rank0
3230 00:45:03.095952 Final RX Vref Byte 0 = 54 to rank1
3231 00:45:03.096018 Final RX Vref Byte 1 = 50 to rank1==
3232 00:45:03.096082 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 00:45:03.096143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3234 00:45:03.096204 ==
3235 00:45:03.096266 DQS Delay:
3236 00:45:03.096326 DQS0 = 0, DQS1 = 0
3237 00:45:03.096387 DQM Delay:
3238 00:45:03.096446 DQM0 = 115, DQM1 = 105
3239 00:45:03.096507 DQ Delay:
3240 00:45:03.096566 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3241 00:45:03.096627 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3242 00:45:03.096687 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3243 00:45:03.096747 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =114
3244 00:45:03.096808
3245 00:45:03.096867
3246 00:45:03.096949 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x404, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
3247 00:45:03.097020 CH1 RK0: MR19=404, MR18=1E1E
3248 00:45:03.097104 CH1_RK0: MR19=0x404, MR18=0x1E1E, DQSOSC=398, MR23=63, INC=41, DEC=27
3249 00:45:03.097177
3250 00:45:03.097238 ----->DramcWriteLeveling(PI) begin...
3251 00:45:03.097300 ==
3252 00:45:03.097360 Dram Type= 6, Freq= 0, CH_1, rank 1
3253 00:45:03.097420 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3254 00:45:03.097487 ==
3255 00:45:03.097572 Write leveling (Byte 0): 21 => 21
3256 00:45:03.097669 Write leveling (Byte 1): 21 => 21
3257 00:45:03.097763 DramcWriteLeveling(PI) end<-----
3258 00:45:03.097856
3259 00:45:03.097948 ==
3260 00:45:03.098043 Dram Type= 6, Freq= 0, CH_1, rank 1
3261 00:45:03.098137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3262 00:45:03.098237 ==
3263 00:45:03.098302 [Gating] SW mode calibration
3264 00:45:03.098363 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3265 00:45:03.098425 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3266 00:45:03.098486 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3267 00:45:03.098547 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3268 00:45:03.098607 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3269 00:45:03.098666 0 11 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
3270 00:45:03.098726 0 11 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
3271 00:45:03.098786 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3272 00:45:03.098846 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3273 00:45:03.098906 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3274 00:45:03.098965 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3275 00:45:03.099025 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3276 00:45:03.099084 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3277 00:45:03.099145 0 12 12 | B1->B0 | 2525 3f3f | 0 0 | (0 0) (0 0)
3278 00:45:03.099205 0 12 16 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
3279 00:45:03.099264 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3280 00:45:03.099324 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3281 00:45:03.099383 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3282 00:45:03.099443 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3283 00:45:03.099502 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3284 00:45:03.099561 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3285 00:45:03.099624 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3286 00:45:03.099686 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3287 00:45:03.099756 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 00:45:03.099940 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 00:45:03.100059 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 00:45:03.100130 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 00:45:03.100196 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 00:45:03.100263 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 00:45:03.100324 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 00:45:03.100384 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 00:45:03.100451 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 00:45:03.100505 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 00:45:03.100557 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 00:45:03.100611 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 00:45:03.100664 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 00:45:03.100717 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 00:45:03.100770 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3302 00:45:03.100822 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3303 00:45:03.100875 Total UI for P1: 0, mck2ui 16
3304 00:45:03.100937 best dqsien dly found for B0: ( 0, 15, 12)
3305 00:45:03.100992 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3306 00:45:03.101046 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3307 00:45:03.101099 Total UI for P1: 0, mck2ui 16
3308 00:45:03.101153 best dqsien dly found for B1: ( 0, 15, 18)
3309 00:45:03.101206 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3310 00:45:03.101259 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3311 00:45:03.101312
3312 00:45:03.101364 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3313 00:45:03.101418 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3314 00:45:03.101470 [Gating] SW calibration Done
3315 00:45:03.101523 ==
3316 00:45:03.101576 Dram Type= 6, Freq= 0, CH_1, rank 1
3317 00:45:03.101629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3318 00:45:03.101683 ==
3319 00:45:03.101735 RX Vref Scan: 0
3320 00:45:03.101787
3321 00:45:03.101839 RX Vref 0 -> 0, step: 1
3322 00:45:03.101892
3323 00:45:03.101944 RX Delay -40 -> 252, step: 8
3324 00:45:03.101997 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3325 00:45:03.102051 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3326 00:45:03.102104 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3327 00:45:03.102157 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
3328 00:45:03.102221 iDelay=208, Bit 4, Center 119 (48 ~ 191) 144
3329 00:45:03.102278 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3330 00:45:03.102331 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3331 00:45:03.102386 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3332 00:45:03.102439 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3333 00:45:03.102493 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3334 00:45:03.102740 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3335 00:45:03.102801 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3336 00:45:03.102856 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3337 00:45:03.102909 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3338 00:45:03.102962 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3339 00:45:03.103015 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
3340 00:45:03.103068 ==
3341 00:45:03.103122 Dram Type= 6, Freq= 0, CH_1, rank 1
3342 00:45:03.103176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3343 00:45:03.103229 ==
3344 00:45:03.103282 DQS Delay:
3345 00:45:03.103334 DQS0 = 0, DQS1 = 0
3346 00:45:03.103387 DQM Delay:
3347 00:45:03.103441 DQM0 = 116, DQM1 = 106
3348 00:45:03.103493 DQ Delay:
3349 00:45:03.103546 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =119
3350 00:45:03.103599 DQ4 =119, DQ5 =127, DQ6 =123, DQ7 =115
3351 00:45:03.103653 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3352 00:45:03.103706 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3353 00:45:03.103759
3354 00:45:03.103811
3355 00:45:03.103864 ==
3356 00:45:03.103917 Dram Type= 6, Freq= 0, CH_1, rank 1
3357 00:45:03.103969 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3358 00:45:03.104044 ==
3359 00:45:03.104101
3360 00:45:03.104184
3361 00:45:03.104350 TX Vref Scan disable
3362 00:45:03.104450 == TX Byte 0 ==
3363 00:45:03.104522 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3364 00:45:03.104582 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3365 00:45:03.104664 == TX Byte 1 ==
3366 00:45:03.104755 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3367 00:45:03.104841 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3368 00:45:03.104932 ==
3369 00:45:03.105029 Dram Type= 6, Freq= 0, CH_1, rank 1
3370 00:45:03.105119 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3371 00:45:03.105206 ==
3372 00:45:03.105292 TX Vref=22, minBit 8, minWin=25, winSum=422
3373 00:45:03.105378 TX Vref=24, minBit 0, minWin=26, winSum=426
3374 00:45:03.105471 TX Vref=26, minBit 3, minWin=26, winSum=428
3375 00:45:03.105550 TX Vref=28, minBit 3, minWin=26, winSum=428
3376 00:45:03.105628 TX Vref=30, minBit 8, minWin=26, winSum=431
3377 00:45:03.105705 TX Vref=32, minBit 3, minWin=26, winSum=430
3378 00:45:03.105784 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 30
3379 00:45:03.105861
3380 00:45:03.105938 Final TX Range 1 Vref 30
3381 00:45:03.106015
3382 00:45:03.106091 ==
3383 00:45:03.106168 Dram Type= 6, Freq= 0, CH_1, rank 1
3384 00:45:03.106254 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3385 00:45:03.106332 ==
3386 00:45:03.106408
3387 00:45:03.106484
3388 00:45:03.106560 TX Vref Scan disable
3389 00:45:03.106637 == TX Byte 0 ==
3390 00:45:03.106714 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3391 00:45:03.106792 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3392 00:45:03.106869 == TX Byte 1 ==
3393 00:45:03.106946 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3394 00:45:03.107024 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3395 00:45:03.107100
3396 00:45:03.107176 [DATLAT]
3397 00:45:03.107252 Freq=1200, CH1 RK1
3398 00:45:03.107329
3399 00:45:03.107454 DATLAT Default: 0xc
3400 00:45:03.107591 0, 0xFFFF, sum = 0
3401 00:45:03.107682 1, 0xFFFF, sum = 0
3402 00:45:03.107737 2, 0xFFFF, sum = 0
3403 00:45:03.107787 3, 0xFFFF, sum = 0
3404 00:45:03.107837 4, 0xFFFF, sum = 0
3405 00:45:03.107887 5, 0xFFFF, sum = 0
3406 00:45:03.107936 6, 0xFFFF, sum = 0
3407 00:45:03.107985 7, 0xFFFF, sum = 0
3408 00:45:03.108034 8, 0xFFFF, sum = 0
3409 00:45:03.108083 9, 0xFFFF, sum = 0
3410 00:45:03.108132 10, 0xFFFF, sum = 0
3411 00:45:03.108181 11, 0x0, sum = 1
3412 00:45:03.108229 12, 0x0, sum = 2
3413 00:45:03.108278 13, 0x0, sum = 3
3414 00:45:03.108328 14, 0x0, sum = 4
3415 00:45:03.108378 best_step = 12
3416 00:45:03.108426
3417 00:45:03.108474 ==
3418 00:45:03.108522 Dram Type= 6, Freq= 0, CH_1, rank 1
3419 00:45:03.108571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3420 00:45:03.108619 ==
3421 00:45:03.108667 RX Vref Scan: 0
3422 00:45:03.108715
3423 00:45:03.108763 RX Vref 0 -> 0, step: 1
3424 00:45:03.108812
3425 00:45:03.108859 RX Delay -29 -> 252, step: 4
3426 00:45:03.108908 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3427 00:45:03.108956 iDelay=199, Bit 1, Center 108 (39 ~ 178) 140
3428 00:45:03.109004 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3429 00:45:03.109052 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3430 00:45:03.109100 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3431 00:45:03.109148 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3432 00:45:03.109197 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3433 00:45:03.109245 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3434 00:45:03.109293 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3435 00:45:03.109341 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3436 00:45:03.109389 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3437 00:45:03.109437 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3438 00:45:03.109485 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3439 00:45:03.109533 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3440 00:45:03.109581 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3441 00:45:03.109629 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3442 00:45:03.109677 ==
3443 00:45:03.109725 Dram Type= 6, Freq= 0, CH_1, rank 1
3444 00:45:03.109774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3445 00:45:03.109823 ==
3446 00:45:03.109872 DQS Delay:
3447 00:45:03.109919 DQS0 = 0, DQS1 = 0
3448 00:45:03.109967 DQM Delay:
3449 00:45:03.110015 DQM0 = 114, DQM1 = 104
3450 00:45:03.110063 DQ Delay:
3451 00:45:03.110112 DQ0 =116, DQ1 =108, DQ2 =108, DQ3 =112
3452 00:45:03.110161 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3453 00:45:03.110214 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3454 00:45:03.110266 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =112
3455 00:45:03.110315
3456 00:45:03.110364
3457 00:45:03.110412 [DQSOSCAuto] RK1, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3458 00:45:03.110473 CH1 RK1: MR19=404, MR18=909
3459 00:45:03.110522 CH1_RK1: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
3460 00:45:03.110570 [RxdqsGatingPostProcess] freq 1200
3461 00:45:03.110618 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3462 00:45:03.110665 Pre-setting of DQS Precalculation
3463 00:45:03.110713 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3464 00:45:03.110761 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3465 00:45:03.110809 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3466 00:45:03.110855
3467 00:45:03.110902
3468 00:45:03.110971 [Calibration Summary] 2400 Mbps
3469 00:45:03.111072 CH 0, Rank 0
3470 00:45:03.111151 SW Impedance : PASS
3471 00:45:03.111215 DUTY Scan : NO K
3472 00:45:03.111263 ZQ Calibration : PASS
3473 00:45:03.111502 Jitter Meter : NO K
3474 00:45:03.111559 CBT Training : PASS
3475 00:45:03.111607 Write leveling : PASS
3476 00:45:03.111655 RX DQS gating : PASS
3477 00:45:03.111702 RX DQ/DQS(RDDQC) : PASS
3478 00:45:03.111750 TX DQ/DQS : PASS
3479 00:45:03.111797 RX DATLAT : PASS
3480 00:45:03.111843 RX DQ/DQS(Engine): PASS
3481 00:45:03.111891 TX OE : NO K
3482 00:45:03.111938 All Pass.
3483 00:45:03.111987
3484 00:45:03.112034 CH 0, Rank 1
3485 00:45:03.112082 SW Impedance : PASS
3486 00:45:03.112130 DUTY Scan : NO K
3487 00:45:03.112177 ZQ Calibration : PASS
3488 00:45:03.112224 Jitter Meter : NO K
3489 00:45:03.112271 CBT Training : PASS
3490 00:45:03.112317 Write leveling : PASS
3491 00:45:03.112363 RX DQS gating : PASS
3492 00:45:03.112410 RX DQ/DQS(RDDQC) : PASS
3493 00:45:03.112457 TX DQ/DQS : PASS
3494 00:45:03.112505 RX DATLAT : PASS
3495 00:45:03.112553 RX DQ/DQS(Engine): PASS
3496 00:45:03.112600 TX OE : NO K
3497 00:45:03.112647 All Pass.
3498 00:45:03.112695
3499 00:45:03.112741 CH 1, Rank 0
3500 00:45:03.112788 SW Impedance : PASS
3501 00:45:03.112836 DUTY Scan : NO K
3502 00:45:03.112883 ZQ Calibration : PASS
3503 00:45:03.112930 Jitter Meter : NO K
3504 00:45:03.112977 CBT Training : PASS
3505 00:45:03.113024 Write leveling : PASS
3506 00:45:03.113071 RX DQS gating : PASS
3507 00:45:03.113118 RX DQ/DQS(RDDQC) : PASS
3508 00:45:03.113164 TX DQ/DQS : PASS
3509 00:45:03.113211 RX DATLAT : PASS
3510 00:45:03.113258 RX DQ/DQS(Engine): PASS
3511 00:45:03.113304 TX OE : NO K
3512 00:45:03.113351 All Pass.
3513 00:45:03.113398
3514 00:45:03.113444 CH 1, Rank 1
3515 00:45:03.113492 SW Impedance : PASS
3516 00:45:03.113539 DUTY Scan : NO K
3517 00:45:03.113586 ZQ Calibration : PASS
3518 00:45:03.113633 Jitter Meter : NO K
3519 00:45:03.113680 CBT Training : PASS
3520 00:45:03.113727 Write leveling : PASS
3521 00:45:03.113774 RX DQS gating : PASS
3522 00:45:03.113821 RX DQ/DQS(RDDQC) : PASS
3523 00:45:03.113867 TX DQ/DQS : PASS
3524 00:45:03.113915 RX DATLAT : PASS
3525 00:45:03.113961 RX DQ/DQS(Engine): PASS
3526 00:45:03.114008 TX OE : NO K
3527 00:45:03.114055 All Pass.
3528 00:45:03.114101
3529 00:45:03.114149 DramC Write-DBI off
3530 00:45:03.114196 PER_BANK_REFRESH: Hybrid Mode
3531 00:45:03.114280 TX_TRACKING: ON
3532 00:45:03.114341 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3533 00:45:03.114390 [FAST_K] Save calibration result to emmc
3534 00:45:03.114437 dramc_set_vcore_voltage set vcore to 650000
3535 00:45:03.114486 Read voltage for 600, 5
3536 00:45:03.114533 Vio18 = 0
3537 00:45:03.114581 Vcore = 650000
3538 00:45:03.114628 Vdram = 0
3539 00:45:03.114674 Vddq = 0
3540 00:45:03.114721 Vmddr = 0
3541 00:45:03.114767 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3542 00:45:03.114814 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3543 00:45:03.114861 MEM_TYPE=3, freq_sel=19
3544 00:45:03.114908 sv_algorithm_assistance_LP4_1600
3545 00:45:03.114955 ============ PULL DRAM RESETB DOWN ============
3546 00:45:03.115002 ========== PULL DRAM RESETB DOWN end =========
3547 00:45:03.115084 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3548 00:45:03.115194 ===================================
3549 00:45:03.115241 LPDDR4 DRAM CONFIGURATION
3550 00:45:03.115289 ===================================
3551 00:45:03.115346 EX_ROW_EN[0] = 0x0
3552 00:45:03.115401 EX_ROW_EN[1] = 0x0
3553 00:45:03.115507 LP4Y_EN = 0x0
3554 00:45:03.115678 WORK_FSP = 0x0
3555 00:45:03.115786 WL = 0x2
3556 00:45:03.115866 RL = 0x2
3557 00:45:03.115919 BL = 0x2
3558 00:45:03.115972 RPST = 0x0
3559 00:45:03.116056 RD_PRE = 0x0
3560 00:45:03.116134 WR_PRE = 0x1
3561 00:45:03.116209 WR_PST = 0x0
3562 00:45:03.116284 DBI_WR = 0x0
3563 00:45:03.116358 DBI_RD = 0x0
3564 00:45:03.116432 OTF = 0x1
3565 00:45:03.116508 ===================================
3566 00:45:03.116584 ===================================
3567 00:45:03.116660 ANA top config
3568 00:45:03.116735 ===================================
3569 00:45:03.116811 DLL_ASYNC_EN = 0
3570 00:45:03.116885 ALL_SLAVE_EN = 1
3571 00:45:03.116960 NEW_RANK_MODE = 1
3572 00:45:03.117057 DLL_IDLE_MODE = 1
3573 00:45:03.117147 LP45_APHY_COMB_EN = 1
3574 00:45:03.117222 TX_ODT_DIS = 1
3575 00:45:03.117298 NEW_8X_MODE = 1
3576 00:45:03.117374 ===================================
3577 00:45:03.117456 ===================================
3578 00:45:03.117537 data_rate = 1200
3579 00:45:03.117620 CKR = 1
3580 00:45:03.117758 DQ_P2S_RATIO = 8
3581 00:45:03.117860 ===================================
3582 00:45:03.117979 CA_P2S_RATIO = 8
3583 00:45:03.118061 DQ_CA_OPEN = 0
3584 00:45:03.118143 DQ_SEMI_OPEN = 0
3585 00:45:03.118248 CA_SEMI_OPEN = 0
3586 00:45:03.118338 CA_FULL_RATE = 0
3587 00:45:03.118413 DQ_CKDIV4_EN = 1
3588 00:45:03.118489 CA_CKDIV4_EN = 1
3589 00:45:03.118564 CA_PREDIV_EN = 0
3590 00:45:03.118639 PH8_DLY = 0
3591 00:45:03.118714 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3592 00:45:03.118789 DQ_AAMCK_DIV = 4
3593 00:45:03.118864 CA_AAMCK_DIV = 4
3594 00:45:03.118939 CA_ADMCK_DIV = 4
3595 00:45:03.119014 DQ_TRACK_CA_EN = 0
3596 00:45:03.119089 CA_PICK = 600
3597 00:45:03.119164 CA_MCKIO = 600
3598 00:45:03.119239 MCKIO_SEMI = 0
3599 00:45:03.119314 PLL_FREQ = 2288
3600 00:45:03.119389 DQ_UI_PI_RATIO = 32
3601 00:45:03.119464 CA_UI_PI_RATIO = 0
3602 00:45:03.119540 ===================================
3603 00:45:03.119615 ===================================
3604 00:45:03.119691 memory_type:LPDDR4
3605 00:45:03.119766 GP_NUM : 10
3606 00:45:03.119841 SRAM_EN : 1
3607 00:45:03.119916 MD32_EN : 0
3608 00:45:03.119991 ===================================
3609 00:45:03.120067 [ANA_INIT] >>>>>>>>>>>>>>
3610 00:45:03.120142 <<<<<< [CONFIGURE PHASE]: ANA_TX
3611 00:45:03.120218 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3612 00:45:03.120293 ===================================
3613 00:45:03.120370 data_rate = 1200,PCW = 0X5800
3614 00:45:03.120446 ===================================
3615 00:45:03.120522 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3616 00:45:03.120599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3617 00:45:03.120676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3618 00:45:03.120944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3619 00:45:03.121025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3620 00:45:03.121192 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3621 00:45:03.121299 [ANA_INIT] flow start
3622 00:45:03.121377 [ANA_INIT] PLL >>>>>>>>
3623 00:45:03.121453 [ANA_INIT] PLL <<<<<<<<
3624 00:45:03.121528 [ANA_INIT] MIDPI >>>>>>>>
3625 00:45:03.121603 [ANA_INIT] MIDPI <<<<<<<<
3626 00:45:03.121679 [ANA_INIT] DLL >>>>>>>>
3627 00:45:03.121754 [ANA_INIT] flow end
3628 00:45:03.121829 ============ LP4 DIFF to SE enter ============
3629 00:45:03.121911 ============ LP4 DIFF to SE exit ============
3630 00:45:03.122054 [ANA_INIT] <<<<<<<<<<<<<
3631 00:45:03.122129 [Flow] Enable top DCM control >>>>>
3632 00:45:03.122205 [Flow] Enable top DCM control <<<<<
3633 00:45:03.122294 Enable DLL master slave shuffle
3634 00:45:03.122344 ==============================================================
3635 00:45:03.122392 Gating Mode config
3636 00:45:03.122440 ==============================================================
3637 00:45:03.122488 Config description:
3638 00:45:03.122535 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3639 00:45:03.122584 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3640 00:45:03.122633 SELPH_MODE 0: By rank 1: By Phase
3641 00:45:03.122681 ==============================================================
3642 00:45:03.122728 GAT_TRACK_EN = 1
3643 00:45:03.122776 RX_GATING_MODE = 2
3644 00:45:03.122823 RX_GATING_TRACK_MODE = 2
3645 00:45:03.122870 SELPH_MODE = 1
3646 00:45:03.122917 PICG_EARLY_EN = 1
3647 00:45:03.122964 VALID_LAT_VALUE = 1
3648 00:45:03.123010 ==============================================================
3649 00:45:03.123058 Enter into Gating configuration >>>>
3650 00:45:03.123105 Exit from Gating configuration <<<<
3651 00:45:03.123153 Enter into DVFS_PRE_config >>>>>
3652 00:45:03.123200 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3653 00:45:03.123250 Exit from DVFS_PRE_config <<<<<
3654 00:45:03.123297 Enter into PICG configuration >>>>
3655 00:45:03.123345 Exit from PICG configuration <<<<
3656 00:45:03.123392 [RX_INPUT] configuration >>>>>
3657 00:45:03.123440 [RX_INPUT] configuration <<<<<
3658 00:45:03.123487 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3659 00:45:03.123535 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3660 00:45:03.123582 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3661 00:45:03.123630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3662 00:45:03.123678 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3663 00:45:03.123725 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3664 00:45:03.123772 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3665 00:45:03.123819 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3666 00:45:03.123866 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3667 00:45:03.123913 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3668 00:45:03.123960 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3669 00:45:03.124007 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3670 00:45:03.124055 ===================================
3671 00:45:03.124102 LPDDR4 DRAM CONFIGURATION
3672 00:45:03.124149 ===================================
3673 00:45:03.124196 EX_ROW_EN[0] = 0x0
3674 00:45:03.124243 EX_ROW_EN[1] = 0x0
3675 00:45:03.124289 LP4Y_EN = 0x0
3676 00:45:03.124336 WORK_FSP = 0x0
3677 00:45:03.124383 WL = 0x2
3678 00:45:03.124430 RL = 0x2
3679 00:45:03.124476 BL = 0x2
3680 00:45:03.124521 RPST = 0x0
3681 00:45:03.124568 RD_PRE = 0x0
3682 00:45:03.124614 WR_PRE = 0x1
3683 00:45:03.124661 WR_PST = 0x0
3684 00:45:03.124707 DBI_WR = 0x0
3685 00:45:03.124753 DBI_RD = 0x0
3686 00:45:03.124799 OTF = 0x1
3687 00:45:03.124846 ===================================
3688 00:45:03.124894 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3689 00:45:03.124942 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3690 00:45:03.124991 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3691 00:45:03.125039 ===================================
3692 00:45:03.125086 LPDDR4 DRAM CONFIGURATION
3693 00:45:03.125133 ===================================
3694 00:45:03.125180 EX_ROW_EN[0] = 0x10
3695 00:45:03.125226 EX_ROW_EN[1] = 0x0
3696 00:45:03.125273 LP4Y_EN = 0x0
3697 00:45:03.125320 WORK_FSP = 0x0
3698 00:45:03.125368 WL = 0x2
3699 00:45:03.125415 RL = 0x2
3700 00:45:03.125461 BL = 0x2
3701 00:45:03.125508 RPST = 0x0
3702 00:45:03.125554 RD_PRE = 0x0
3703 00:45:03.125601 WR_PRE = 0x1
3704 00:45:03.125647 WR_PST = 0x0
3705 00:45:03.125693 DBI_WR = 0x0
3706 00:45:03.125741 DBI_RD = 0x0
3707 00:45:03.125787 OTF = 0x1
3708 00:45:03.125834 ===================================
3709 00:45:03.125882 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3710 00:45:03.125929 nWR fixed to 30
3711 00:45:03.125977 [ModeRegInit_LP4] CH0 RK0
3712 00:45:03.126024 [ModeRegInit_LP4] CH0 RK1
3713 00:45:03.126071 [ModeRegInit_LP4] CH1 RK0
3714 00:45:03.126117 [ModeRegInit_LP4] CH1 RK1
3715 00:45:03.126162 match AC timing 16
3716 00:45:03.126213 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3717 00:45:03.126298 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3718 00:45:03.126346 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3719 00:45:03.126394 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3720 00:45:03.126441 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3721 00:45:03.126488 ==
3722 00:45:03.126535 Dram Type= 6, Freq= 0, CH_0, rank 0
3723 00:45:03.126582 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3724 00:45:03.126630 ==
3725 00:45:03.126677 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3726 00:45:03.126725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3727 00:45:03.126987 [CA 0] Center 35 (5~66) winsize 62
3728 00:45:03.127062 [CA 1] Center 35 (5~66) winsize 62
3729 00:45:03.127122 [CA 2] Center 34 (4~65) winsize 62
3730 00:45:03.127176 [CA 3] Center 34 (4~65) winsize 62
3731 00:45:03.127228 [CA 4] Center 33 (3~64) winsize 62
3732 00:45:03.127278 [CA 5] Center 33 (3~64) winsize 62
3733 00:45:03.127327
3734 00:45:03.127375 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3735 00:45:03.127423
3736 00:45:03.127471 [CATrainingPosCal] consider 1 rank data
3737 00:45:03.127519 u2DelayCellTimex100 = 270/100 ps
3738 00:45:03.127567 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3739 00:45:03.127615 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3740 00:45:03.127663 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3741 00:45:03.127710 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3742 00:45:03.127757 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3743 00:45:03.127805 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3744 00:45:03.127852
3745 00:45:03.127898 CA PerBit enable=1, Macro0, CA PI delay=33
3746 00:45:03.127946
3747 00:45:03.127993 [CBTSetCACLKResult] CA Dly = 33
3748 00:45:03.128040 CS Dly: 4 (0~35)
3749 00:45:03.128088 ==
3750 00:45:03.128135 Dram Type= 6, Freq= 0, CH_0, rank 1
3751 00:45:03.128183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3752 00:45:03.128230 ==
3753 00:45:03.128285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3754 00:45:03.128346 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3755 00:45:03.128395 [CA 0] Center 35 (5~66) winsize 62
3756 00:45:03.128443 [CA 1] Center 35 (5~66) winsize 62
3757 00:45:03.128491 [CA 2] Center 34 (4~65) winsize 62
3758 00:45:03.128538 [CA 3] Center 34 (4~65) winsize 62
3759 00:45:03.128585 [CA 4] Center 33 (3~64) winsize 62
3760 00:45:03.128632 [CA 5] Center 33 (3~64) winsize 62
3761 00:45:03.128679
3762 00:45:03.128726 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3763 00:45:03.128773
3764 00:45:03.128820 [CATrainingPosCal] consider 2 rank data
3765 00:45:03.128867 u2DelayCellTimex100 = 270/100 ps
3766 00:45:03.128915 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3767 00:45:03.128963 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3768 00:45:03.129010 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3769 00:45:03.129058 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3770 00:45:03.129105 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3771 00:45:03.129152 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3772 00:45:03.129197
3773 00:45:03.129244 CA PerBit enable=1, Macro0, CA PI delay=33
3774 00:45:03.129292
3775 00:45:03.129339 [CBTSetCACLKResult] CA Dly = 33
3776 00:45:03.129386 CS Dly: 5 (0~37)
3777 00:45:03.129433
3778 00:45:03.129480 ----->DramcWriteLeveling(PI) begin...
3779 00:45:03.129527 ==
3780 00:45:03.129574 Dram Type= 6, Freq= 0, CH_0, rank 0
3781 00:45:03.129623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3782 00:45:03.129670 ==
3783 00:45:03.129716 Write leveling (Byte 0): 30 => 30
3784 00:45:03.129763 Write leveling (Byte 1): 30 => 30
3785 00:45:03.129810 DramcWriteLeveling(PI) end<-----
3786 00:45:03.129857
3787 00:45:03.129904 ==
3788 00:45:03.129950 Dram Type= 6, Freq= 0, CH_0, rank 0
3789 00:45:03.130015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3790 00:45:03.130065 ==
3791 00:45:03.130111 [Gating] SW mode calibration
3792 00:45:03.130159 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3793 00:45:03.130207 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3794 00:45:03.130289 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3795 00:45:03.130351 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3796 00:45:03.130398 0 5 8 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)
3797 00:45:03.130446 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3798 00:45:03.130493 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3799 00:45:03.130540 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3800 00:45:03.130586 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3801 00:45:03.130633 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3802 00:45:03.130680 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3803 00:45:03.130727 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3804 00:45:03.130774 0 6 8 | B1->B0 | 2727 3030 | 0 0 | (0 0) (1 1)
3805 00:45:03.130821 0 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3806 00:45:03.130869 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3807 00:45:03.130916 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3808 00:45:03.130962 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3809 00:45:03.131009 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3810 00:45:03.131056 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3811 00:45:03.131103 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3812 00:45:03.131150 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3813 00:45:03.131197 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3814 00:45:03.131244 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 00:45:03.131291 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 00:45:03.131337 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 00:45:03.131384 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 00:45:03.131431 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 00:45:03.131478 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 00:45:03.131532 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 00:45:03.131591 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 00:45:03.131639 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 00:45:03.131686 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 00:45:03.131733 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 00:45:03.131780 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 00:45:03.131827 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 00:45:03.131874 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3828 00:45:03.131921 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3829 00:45:03.131968 Total UI for P1: 0, mck2ui 16
3830 00:45:03.132015 best dqsien dly found for B0: ( 0, 9, 4)
3831 00:45:03.132063 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3832 00:45:03.132110 Total UI for P1: 0, mck2ui 16
3833 00:45:03.132157 best dqsien dly found for B1: ( 0, 9, 8)
3834 00:45:03.132390 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
3835 00:45:03.132445 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3836 00:45:03.132495
3837 00:45:03.132543 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
3838 00:45:03.132591 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3839 00:45:03.132639 [Gating] SW calibration Done
3840 00:45:03.132687 ==
3841 00:45:03.132735 Dram Type= 6, Freq= 0, CH_0, rank 0
3842 00:45:03.132783 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3843 00:45:03.132831 ==
3844 00:45:03.132878 RX Vref Scan: 0
3845 00:45:03.132925
3846 00:45:03.132972 RX Vref 0 -> 0, step: 1
3847 00:45:03.133019
3848 00:45:03.133065 RX Delay -230 -> 252, step: 16
3849 00:45:03.133111 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3850 00:45:03.133159 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3851 00:45:03.133207 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3852 00:45:03.133253 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3853 00:45:03.133300 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3854 00:45:03.133347 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3855 00:45:03.133393 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3856 00:45:03.133440 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3857 00:45:03.133487 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3858 00:45:03.133534 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3859 00:45:03.133582 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3860 00:45:03.133629 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3861 00:45:03.133676 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3862 00:45:03.133723 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3863 00:45:03.133771 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3864 00:45:03.133818 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3865 00:45:03.133866 ==
3866 00:45:03.133913 Dram Type= 6, Freq= 0, CH_0, rank 0
3867 00:45:03.133960 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3868 00:45:03.134007 ==
3869 00:45:03.134054 DQS Delay:
3870 00:45:03.134100 DQS0 = 0, DQS1 = 0
3871 00:45:03.134146 DQM Delay:
3872 00:45:03.134192 DQM0 = 37, DQM1 = 33
3873 00:45:03.134274 DQ Delay:
3874 00:45:03.134335 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3875 00:45:03.134382 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
3876 00:45:03.134429 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3877 00:45:03.134476 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3878 00:45:03.134523
3879 00:45:03.134570
3880 00:45:03.134616 ==
3881 00:45:03.134663 Dram Type= 6, Freq= 0, CH_0, rank 0
3882 00:45:03.134711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3883 00:45:03.134758 ==
3884 00:45:03.134804
3885 00:45:03.134850
3886 00:45:03.134905 TX Vref Scan disable
3887 00:45:03.134962 == TX Byte 0 ==
3888 00:45:03.135010 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3889 00:45:03.135059 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3890 00:45:03.135105 == TX Byte 1 ==
3891 00:45:03.135152 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3892 00:45:03.135199 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3893 00:45:03.135246 ==
3894 00:45:03.135294 Dram Type= 6, Freq= 0, CH_0, rank 0
3895 00:45:03.135341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3896 00:45:03.135388 ==
3897 00:45:03.135435
3898 00:45:03.135481
3899 00:45:03.135526 TX Vref Scan disable
3900 00:45:03.135573 == TX Byte 0 ==
3901 00:45:03.135620 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3902 00:45:03.135667 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3903 00:45:03.135714 == TX Byte 1 ==
3904 00:45:03.135762 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3905 00:45:03.135808 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3906 00:45:03.135854
3907 00:45:03.135901 [DATLAT]
3908 00:45:03.135947 Freq=600, CH0 RK0
3909 00:45:03.135993
3910 00:45:03.136040 DATLAT Default: 0x9
3911 00:45:03.136087 0, 0xFFFF, sum = 0
3912 00:45:03.136135 1, 0xFFFF, sum = 0
3913 00:45:03.136184 2, 0xFFFF, sum = 0
3914 00:45:03.136232 3, 0xFFFF, sum = 0
3915 00:45:03.136281 4, 0xFFFF, sum = 0
3916 00:45:03.136329 5, 0xFFFF, sum = 0
3917 00:45:03.136376 6, 0xFFFF, sum = 0
3918 00:45:03.136424 7, 0x0, sum = 1
3919 00:45:03.136471 8, 0x0, sum = 2
3920 00:45:03.136519 9, 0x0, sum = 3
3921 00:45:03.136567 10, 0x0, sum = 4
3922 00:45:03.136615 best_step = 8
3923 00:45:03.136661
3924 00:45:03.136708 ==
3925 00:45:03.470960 Dram Type= 6, Freq= 0, CH_0, rank 0
3926 00:45:03.471463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3927 00:45:03.471797 ==
3928 00:45:03.472103 RX Vref Scan: 1
3929 00:45:03.472435
3930 00:45:03.472846 RX Vref 0 -> 0, step: 1
3931 00:45:03.473139
3932 00:45:03.473418 RX Delay -195 -> 252, step: 8
3933 00:45:03.473694
3934 00:45:03.473966 Set Vref, RX VrefLevel [Byte0]: 48
3935 00:45:03.474313 [Byte1]: 48
3936 00:45:03.474727
3937 00:45:03.475049 Final RX Vref Byte 0 = 48 to rank0
3938 00:45:03.475415 Final RX Vref Byte 1 = 48 to rank0
3939 00:45:03.475836 Final RX Vref Byte 0 = 48 to rank1
3940 00:45:03.476234 Final RX Vref Byte 1 = 48 to rank1==
3941 00:45:03.476535 Dram Type= 6, Freq= 0, CH_0, rank 0
3942 00:45:03.476812 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3943 00:45:03.477090 ==
3944 00:45:03.477360 DQS Delay:
3945 00:45:03.477629 DQS0 = 0, DQS1 = 0
3946 00:45:03.477898 DQM Delay:
3947 00:45:03.478163 DQM0 = 41, DQM1 = 29
3948 00:45:03.478477 DQ Delay:
3949 00:45:03.478758 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
3950 00:45:03.479103 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
3951 00:45:03.479406 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
3952 00:45:03.479678 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =40
3953 00:45:03.479946
3954 00:45:03.480214
3955 00:45:03.480482 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3956 00:45:03.480755 CH0 RK0: MR19=808, MR18=5454
3957 00:45:03.481027 CH0_RK0: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
3958 00:45:03.481299
3959 00:45:03.481578 ----->DramcWriteLeveling(PI) begin...
3960 00:45:03.481859 ==
3961 00:45:03.482127 Dram Type= 6, Freq= 0, CH_0, rank 1
3962 00:45:03.482433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3963 00:45:03.482842 ==
3964 00:45:03.483154 Write leveling (Byte 0): 33 => 33
3965 00:45:03.483432 Write leveling (Byte 1): 29 => 29
3966 00:45:03.483706 DramcWriteLeveling(PI) end<-----
3967 00:45:03.483978
3968 00:45:03.484248 ==
3969 00:45:03.484515 Dram Type= 6, Freq= 0, CH_0, rank 1
3970 00:45:03.484789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3971 00:45:03.485061 ==
3972 00:45:03.485332 [Gating] SW mode calibration
3973 00:45:03.485600 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3974 00:45:03.485917 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3975 00:45:03.486396 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 00:45:03.486687 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3977 00:45:03.487025 0 5 8 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 0)
3978 00:45:03.487315 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3979 00:45:03.488061 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 00:45:03.488378 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 00:45:03.488664 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 00:45:03.489023 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 00:45:03.489409 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 00:45:03.489695 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 00:45:03.489968 0 6 8 | B1->B0 | 3333 3232 | 0 0 | (1 1) (0 0)
3986 00:45:03.490274 0 6 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
3987 00:45:03.490554 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 00:45:03.490825 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 00:45:03.491096 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 00:45:03.491367 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 00:45:03.491637 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 00:45:03.491907 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 00:45:03.492175 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3994 00:45:03.492547 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 00:45:03.492838 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 00:45:03.493111 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 00:45:03.493382 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 00:45:03.493650 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 00:45:03.493921 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 00:45:03.494192 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 00:45:03.494503 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 00:45:03.494775 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 00:45:03.495041 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 00:45:03.495308 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 00:45:03.495578 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 00:45:03.495918 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 00:45:03.496221 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 00:45:03.496496 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 00:45:03.496770 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4010 00:45:03.497221 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 00:45:03.497578 Total UI for P1: 0, mck2ui 16
4012 00:45:03.497865 best dqsien dly found for B0: ( 0, 9, 8)
4013 00:45:03.498142 Total UI for P1: 0, mck2ui 16
4014 00:45:03.498473 best dqsien dly found for B1: ( 0, 9, 8)
4015 00:45:03.498752 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4016 00:45:03.499024 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4017 00:45:03.499400
4018 00:45:03.499678 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4019 00:45:03.499958 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4020 00:45:03.500231 [Gating] SW calibration Done
4021 00:45:03.500489 ==
4022 00:45:03.500679 Dram Type= 6, Freq= 0, CH_0, rank 1
4023 00:45:03.500891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4024 00:45:03.501090 ==
4025 00:45:03.501284 RX Vref Scan: 0
4026 00:45:03.501474
4027 00:45:03.501663 RX Vref 0 -> 0, step: 1
4028 00:45:03.501857
4029 00:45:03.502047 RX Delay -230 -> 252, step: 16
4030 00:45:03.502301 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4031 00:45:03.502522 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4032 00:45:03.502717 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4033 00:45:03.503044 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4034 00:45:03.503384 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4035 00:45:03.503662 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4036 00:45:03.503863 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4037 00:45:03.504080 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4038 00:45:03.504280 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4039 00:45:03.504473 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4040 00:45:03.504682 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4041 00:45:03.504883 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4042 00:45:03.505074 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4043 00:45:03.505299 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4044 00:45:03.505515 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4045 00:45:03.505671 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4046 00:45:03.505813 ==
4047 00:45:03.505973 Dram Type= 6, Freq= 0, CH_0, rank 1
4048 00:45:03.506126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4049 00:45:03.506292 ==
4050 00:45:03.506439 DQS Delay:
4051 00:45:03.506605 DQS0 = 0, DQS1 = 0
4052 00:45:03.506750 DQM Delay:
4053 00:45:03.506891 DQM0 = 43, DQM1 = 33
4054 00:45:03.507036 DQ Delay:
4055 00:45:03.507246 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4056 00:45:03.507393 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4057 00:45:03.507536 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4058 00:45:03.507677 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4059 00:45:03.507819
4060 00:45:03.507959
4061 00:45:03.508098 ==
4062 00:45:03.508239 Dram Type= 6, Freq= 0, CH_0, rank 1
4063 00:45:03.508382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4064 00:45:03.508527 ==
4065 00:45:03.508717
4066 00:45:03.508869
4067 00:45:03.509010 TX Vref Scan disable
4068 00:45:03.509152 == TX Byte 0 ==
4069 00:45:03.509294 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4070 00:45:03.509434 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4071 00:45:03.509575 == TX Byte 1 ==
4072 00:45:03.509714 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4073 00:45:03.509853 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4074 00:45:03.509995 ==
4075 00:45:03.510244 Dram Type= 6, Freq= 0, CH_0, rank 1
4076 00:45:03.510401 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4077 00:45:03.510535 ==
4078 00:45:03.510646
4079 00:45:03.510755
4080 00:45:03.510865 TX Vref Scan disable
4081 00:45:03.510978 == TX Byte 0 ==
4082 00:45:03.511090 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4083 00:45:03.511204 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4084 00:45:03.511317 == TX Byte 1 ==
4085 00:45:03.511429 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4086 00:45:03.511542 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4087 00:45:03.511653
4088 00:45:03.511762 [DATLAT]
4089 00:45:03.511873 Freq=600, CH0 RK1
4090 00:45:03.511984
4091 00:45:03.512136 DATLAT Default: 0x8
4092 00:45:03.512261 0, 0xFFFF, sum = 0
4093 00:45:03.512379 1, 0xFFFF, sum = 0
4094 00:45:03.512493 2, 0xFFFF, sum = 0
4095 00:45:03.512606 3, 0xFFFF, sum = 0
4096 00:45:03.512718 4, 0xFFFF, sum = 0
4097 00:45:03.512856 5, 0xFFFF, sum = 0
4098 00:45:03.512976 6, 0xFFFF, sum = 0
4099 00:45:03.513319 7, 0x0, sum = 1
4100 00:45:03.513447 8, 0x0, sum = 2
4101 00:45:03.513563 9, 0x0, sum = 3
4102 00:45:03.513679 10, 0x0, sum = 4
4103 00:45:03.513795 best_step = 8
4104 00:45:03.513906
4105 00:45:03.514016 ==
4106 00:45:03.514126 Dram Type= 6, Freq= 0, CH_0, rank 1
4107 00:45:03.514251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4108 00:45:03.514367 ==
4109 00:45:03.514480 RX Vref Scan: 0
4110 00:45:03.514592
4111 00:45:03.514702 RX Vref 0 -> 0, step: 1
4112 00:45:03.514814
4113 00:45:03.514925 RX Delay -195 -> 252, step: 8
4114 00:45:03.519581 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4115 00:45:03.522963 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4116 00:45:03.526162 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4117 00:45:03.529386 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4118 00:45:03.536272 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4119 00:45:03.539335 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4120 00:45:03.543047 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4121 00:45:03.546007 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4122 00:45:03.552429 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4123 00:45:03.555960 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4124 00:45:03.559147 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4125 00:45:03.562534 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4126 00:45:03.569037 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4127 00:45:03.572540 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4128 00:45:03.575830 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4129 00:45:03.579290 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4130 00:45:03.579569 ==
4131 00:45:03.582365 Dram Type= 6, Freq= 0, CH_0, rank 1
4132 00:45:03.589109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4133 00:45:03.589620 ==
4134 00:45:03.589971 DQS Delay:
4135 00:45:03.590317 DQS0 = 0, DQS1 = 0
4136 00:45:03.592446 DQM Delay:
4137 00:45:03.592883 DQM0 = 41, DQM1 = 31
4138 00:45:03.595763 DQ Delay:
4139 00:45:03.599573 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4140 00:45:03.602518 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4141 00:45:03.605750 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4142 00:45:03.609358 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4143 00:45:03.609809
4144 00:45:03.610142
4145 00:45:03.616090 [DQSOSCAuto] RK1, (LSB)MR18= 0x7474, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4146 00:45:03.619342 CH0 RK1: MR19=808, MR18=7474
4147 00:45:03.626011 CH0_RK1: MR19=0x808, MR18=0x7474, DQSOSC=388, MR23=63, INC=174, DEC=116
4148 00:45:03.629233 [RxdqsGatingPostProcess] freq 600
4149 00:45:03.632405 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4150 00:45:03.635709 Pre-setting of DQS Precalculation
4151 00:45:03.642145 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4152 00:45:03.642616 ==
4153 00:45:03.645564 Dram Type= 6, Freq= 0, CH_1, rank 0
4154 00:45:03.648774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4155 00:45:03.649218 ==
4156 00:45:03.655470 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4157 00:45:03.662020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4158 00:45:03.665789 [CA 0] Center 35 (5~66) winsize 62
4159 00:45:03.669028 [CA 1] Center 35 (4~66) winsize 63
4160 00:45:03.671935 [CA 2] Center 33 (3~64) winsize 62
4161 00:45:03.675110 [CA 3] Center 33 (3~64) winsize 62
4162 00:45:03.678874 [CA 4] Center 33 (2~64) winsize 63
4163 00:45:03.679388 [CA 5] Center 33 (2~64) winsize 63
4164 00:45:03.682161
4165 00:45:03.685266 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4166 00:45:03.685704
4167 00:45:03.688571 [CATrainingPosCal] consider 1 rank data
4168 00:45:03.692404 u2DelayCellTimex100 = 270/100 ps
4169 00:45:03.695114 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4170 00:45:03.698716 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4171 00:45:03.702020 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4172 00:45:03.705201 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4173 00:45:03.708237 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4174 00:45:03.711899 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4175 00:45:03.712461
4176 00:45:03.715196 CA PerBit enable=1, Macro0, CA PI delay=33
4177 00:45:03.718621
4178 00:45:03.719129 [CBTSetCACLKResult] CA Dly = 33
4179 00:45:03.721887 CS Dly: 4 (0~35)
4180 00:45:03.722498 ==
4181 00:45:03.725168 Dram Type= 6, Freq= 0, CH_1, rank 1
4182 00:45:03.728258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4183 00:45:03.728653 ==
4184 00:45:03.735019 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4185 00:45:03.741869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4186 00:45:03.745169 [CA 0] Center 35 (4~66) winsize 63
4187 00:45:03.748600 [CA 1] Center 34 (4~65) winsize 62
4188 00:45:03.751538 [CA 2] Center 33 (3~64) winsize 62
4189 00:45:03.755013 [CA 3] Center 33 (3~64) winsize 62
4190 00:45:03.758161 [CA 4] Center 32 (2~63) winsize 62
4191 00:45:03.761475 [CA 5] Center 32 (2~63) winsize 62
4192 00:45:03.762064
4193 00:45:03.765175 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4194 00:45:03.765608
4195 00:45:03.768149 [CATrainingPosCal] consider 2 rank data
4196 00:45:03.771439 u2DelayCellTimex100 = 270/100 ps
4197 00:45:03.774828 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4198 00:45:03.777997 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4199 00:45:03.781462 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4200 00:45:03.784794 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4201 00:45:03.788085 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4202 00:45:03.791501 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4203 00:45:03.791938
4204 00:45:03.798338 CA PerBit enable=1, Macro0, CA PI delay=32
4205 00:45:03.798826
4206 00:45:03.799144 [CBTSetCACLKResult] CA Dly = 32
4207 00:45:03.801509 CS Dly: 5 (0~37)
4208 00:45:03.801903
4209 00:45:03.804856 ----->DramcWriteLeveling(PI) begin...
4210 00:45:03.805329 ==
4211 00:45:03.808644 Dram Type= 6, Freq= 0, CH_1, rank 0
4212 00:45:03.811615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4213 00:45:03.812041 ==
4214 00:45:03.814893 Write leveling (Byte 0): 29 => 29
4215 00:45:03.817953 Write leveling (Byte 1): 26 => 26
4216 00:45:03.821502 DramcWriteLeveling(PI) end<-----
4217 00:45:03.822038
4218 00:45:03.822435 ==
4219 00:45:03.824568 Dram Type= 6, Freq= 0, CH_1, rank 0
4220 00:45:03.827888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4221 00:45:03.831283 ==
4222 00:45:03.831678 [Gating] SW mode calibration
4223 00:45:03.841050 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4224 00:45:03.844754 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4225 00:45:03.847941 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 00:45:03.854475 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4227 00:45:03.857510 0 5 8 | B1->B0 | 3030 2727 | 1 0 | (0 1) (0 0)
4228 00:45:03.860817 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 00:45:03.867472 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 00:45:03.870709 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 00:45:03.874266 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 00:45:03.881030 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 00:45:03.884215 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 00:45:03.887509 0 6 4 | B1->B0 | 2424 3131 | 0 1 | (0 0) (0 0)
4235 00:45:03.894010 0 6 8 | B1->B0 | 3434 4343 | 1 0 | (0 0) (0 0)
4236 00:45:03.897585 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 00:45:03.900786 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 00:45:03.907663 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 00:45:03.910605 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 00:45:03.913919 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 00:45:03.920768 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 00:45:03.923887 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4243 00:45:03.927198 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 00:45:03.933816 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 00:45:03.937350 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 00:45:03.940238 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 00:45:03.947078 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 00:45:03.950278 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 00:45:03.953537 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 00:45:03.960199 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 00:45:03.963547 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 00:45:03.966683 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 00:45:03.973660 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 00:45:03.976694 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 00:45:03.980119 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 00:45:03.986762 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 00:45:03.989989 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 00:45:03.993127 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4259 00:45:03.999816 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4260 00:45:04.000252 Total UI for P1: 0, mck2ui 16
4261 00:45:04.006611 best dqsien dly found for B0: ( 0, 9, 4)
4262 00:45:04.009912 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 00:45:04.013433 Total UI for P1: 0, mck2ui 16
4264 00:45:04.016538 best dqsien dly found for B1: ( 0, 9, 8)
4265 00:45:04.019766 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4266 00:45:04.022900 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4267 00:45:04.023508
4268 00:45:04.026171 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4269 00:45:04.029536 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4270 00:45:04.032896 [Gating] SW calibration Done
4271 00:45:04.033462 ==
4272 00:45:04.036336 Dram Type= 6, Freq= 0, CH_1, rank 0
4273 00:45:04.039588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4274 00:45:04.040022 ==
4275 00:45:04.043008 RX Vref Scan: 0
4276 00:45:04.043561
4277 00:45:04.046205 RX Vref 0 -> 0, step: 1
4278 00:45:04.046764
4279 00:45:04.049587 RX Delay -230 -> 252, step: 16
4280 00:45:04.052891 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4281 00:45:04.056044 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4282 00:45:04.059359 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4283 00:45:04.062453 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4284 00:45:04.069309 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4285 00:45:04.072509 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4286 00:45:04.075780 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4287 00:45:04.079228 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4288 00:45:04.085812 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4289 00:45:04.088949 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4290 00:45:04.092040 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4291 00:45:04.095874 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4292 00:45:04.102466 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4293 00:45:04.105394 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4294 00:45:04.108905 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4295 00:45:04.111977 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4296 00:45:04.112406 ==
4297 00:45:04.115371 Dram Type= 6, Freq= 0, CH_1, rank 0
4298 00:45:04.121858 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4299 00:45:04.122369 ==
4300 00:45:04.122717 DQS Delay:
4301 00:45:04.125288 DQS0 = 0, DQS1 = 0
4302 00:45:04.125716 DQM Delay:
4303 00:45:04.126046 DQM0 = 41, DQM1 = 33
4304 00:45:04.128721 DQ Delay:
4305 00:45:04.132114 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4306 00:45:04.135439 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =41
4307 00:45:04.138581 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4308 00:45:04.142407 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4309 00:45:04.142751
4310 00:45:04.143104
4311 00:45:04.143335 ==
4312 00:45:04.145229 Dram Type= 6, Freq= 0, CH_1, rank 0
4313 00:45:04.148569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4314 00:45:04.149174 ==
4315 00:45:04.149591
4316 00:45:04.149857
4317 00:45:04.151776 TX Vref Scan disable
4318 00:45:04.155292 == TX Byte 0 ==
4319 00:45:04.158343 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4320 00:45:04.161717 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4321 00:45:04.165078 == TX Byte 1 ==
4322 00:45:04.168726 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4323 00:45:04.172259 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4324 00:45:04.172823 ==
4325 00:45:04.175188 Dram Type= 6, Freq= 0, CH_1, rank 0
4326 00:45:04.178789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4327 00:45:04.181718 ==
4328 00:45:04.182145
4329 00:45:04.182512
4330 00:45:04.182833 TX Vref Scan disable
4331 00:45:04.185659 == TX Byte 0 ==
4332 00:45:04.189082 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4333 00:45:04.195461 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4334 00:45:04.195894 == TX Byte 1 ==
4335 00:45:04.198626 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4336 00:45:04.205681 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4337 00:45:04.206244
4338 00:45:04.206597 [DATLAT]
4339 00:45:04.206949 Freq=600, CH1 RK0
4340 00:45:04.207253
4341 00:45:04.208752 DATLAT Default: 0x9
4342 00:45:04.209183 0, 0xFFFF, sum = 0
4343 00:45:04.212177 1, 0xFFFF, sum = 0
4344 00:45:04.215242 2, 0xFFFF, sum = 0
4345 00:45:04.215680 3, 0xFFFF, sum = 0
4346 00:45:04.218503 4, 0xFFFF, sum = 0
4347 00:45:04.218943 5, 0xFFFF, sum = 0
4348 00:45:04.222106 6, 0xFFFF, sum = 0
4349 00:45:04.222704 7, 0x0, sum = 1
4350 00:45:04.223054 8, 0x0, sum = 2
4351 00:45:04.225409 9, 0x0, sum = 3
4352 00:45:04.225917 10, 0x0, sum = 4
4353 00:45:04.228565 best_step = 8
4354 00:45:04.228995
4355 00:45:04.229327 ==
4356 00:45:04.231987 Dram Type= 6, Freq= 0, CH_1, rank 0
4357 00:45:04.235334 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4358 00:45:04.235840 ==
4359 00:45:04.238759 RX Vref Scan: 1
4360 00:45:04.239192
4361 00:45:04.239524 RX Vref 0 -> 0, step: 1
4362 00:45:04.239836
4363 00:45:04.242369 RX Delay -195 -> 252, step: 8
4364 00:45:04.243035
4365 00:45:04.245090 Set Vref, RX VrefLevel [Byte0]: 54
4366 00:45:04.248509 [Byte1]: 50
4367 00:45:04.252397
4368 00:45:04.252826 Final RX Vref Byte 0 = 54 to rank0
4369 00:45:04.255721 Final RX Vref Byte 1 = 50 to rank0
4370 00:45:04.259338 Final RX Vref Byte 0 = 54 to rank1
4371 00:45:04.262328 Final RX Vref Byte 1 = 50 to rank1==
4372 00:45:04.265936 Dram Type= 6, Freq= 0, CH_1, rank 0
4373 00:45:04.272387 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4374 00:45:04.272887 ==
4375 00:45:04.273219 DQS Delay:
4376 00:45:04.275632 DQS0 = 0, DQS1 = 0
4377 00:45:04.276072 DQM Delay:
4378 00:45:04.276401 DQM0 = 37, DQM1 = 30
4379 00:45:04.278867 DQ Delay:
4380 00:45:04.282118 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4381 00:45:04.285463 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4382 00:45:04.289233 DQ8 =8, DQ9 =20, DQ10 =32, DQ11 =24
4383 00:45:04.292514 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4384 00:45:04.293024
4385 00:45:04.293360
4386 00:45:04.298840 [DQSOSCAuto] RK0, (LSB)MR18= 0x8080, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4387 00:45:04.302197 CH1 RK0: MR19=808, MR18=8080
4388 00:45:04.309135 CH1_RK0: MR19=0x808, MR18=0x8080, DQSOSC=386, MR23=63, INC=176, DEC=117
4389 00:45:04.309650
4390 00:45:04.312303 ----->DramcWriteLeveling(PI) begin...
4391 00:45:04.312743 ==
4392 00:45:04.315709 Dram Type= 6, Freq= 0, CH_1, rank 1
4393 00:45:04.318769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4394 00:45:04.319205 ==
4395 00:45:04.322125 Write leveling (Byte 0): 27 => 27
4396 00:45:04.325278 Write leveling (Byte 1): 27 => 27
4397 00:45:04.328765 DramcWriteLeveling(PI) end<-----
4398 00:45:04.329192
4399 00:45:04.329519 ==
4400 00:45:04.331961 Dram Type= 6, Freq= 0, CH_1, rank 1
4401 00:45:04.335571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4402 00:45:04.336076 ==
4403 00:45:04.338852 [Gating] SW mode calibration
4404 00:45:04.345544 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4405 00:45:04.351975 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4406 00:45:04.355563 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4407 00:45:04.362273 0 5 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
4408 00:45:04.365310 0 5 8 | B1->B0 | 2f2f 2424 | 1 0 | (0 0) (0 0)
4409 00:45:04.368666 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 00:45:04.375249 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 00:45:04.378205 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 00:45:04.381870 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 00:45:04.385184 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 00:45:04.391866 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 00:45:04.394951 0 6 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4416 00:45:04.398486 0 6 8 | B1->B0 | 3333 4141 | 0 0 | (0 0) (0 0)
4417 00:45:04.405076 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 00:45:04.408562 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 00:45:04.411405 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 00:45:04.418184 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 00:45:04.421408 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 00:45:04.424792 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 00:45:04.431380 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4424 00:45:04.435154 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 00:45:04.438058 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 00:45:04.444892 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 00:45:04.448315 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 00:45:04.451389 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 00:45:04.458163 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 00:45:04.461254 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 00:45:04.464592 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 00:45:04.471629 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 00:45:04.474498 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 00:45:04.478050 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 00:45:04.484516 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 00:45:04.487826 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 00:45:04.491189 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 00:45:04.497677 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 00:45:04.501307 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4440 00:45:04.504471 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 00:45:04.508106 Total UI for P1: 0, mck2ui 16
4442 00:45:04.511178 best dqsien dly found for B0: ( 0, 9, 4)
4443 00:45:04.514565 Total UI for P1: 0, mck2ui 16
4444 00:45:04.517874 best dqsien dly found for B1: ( 0, 9, 6)
4445 00:45:04.521123 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4446 00:45:04.524636 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4447 00:45:04.525030
4448 00:45:04.528008 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4449 00:45:04.534375 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4450 00:45:04.534774 [Gating] SW calibration Done
4451 00:45:04.535205 ==
4452 00:45:04.538260 Dram Type= 6, Freq= 0, CH_1, rank 1
4453 00:45:04.544645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4454 00:45:04.545123 ==
4455 00:45:04.545432 RX Vref Scan: 0
4456 00:45:04.545717
4457 00:45:04.547939 RX Vref 0 -> 0, step: 1
4458 00:45:04.548428
4459 00:45:04.550761 RX Delay -230 -> 252, step: 16
4460 00:45:04.554512 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4461 00:45:04.557517 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4462 00:45:04.560705 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4463 00:45:04.567489 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4464 00:45:04.571106 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4465 00:45:04.574328 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4466 00:45:04.577702 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4467 00:45:04.584704 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4468 00:45:04.587536 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4469 00:45:04.591053 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4470 00:45:04.594162 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4471 00:45:04.600978 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4472 00:45:04.604054 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4473 00:45:04.607525 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4474 00:45:04.610707 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4475 00:45:04.614135 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4476 00:45:04.617657 ==
4477 00:45:04.620992 Dram Type= 6, Freq= 0, CH_1, rank 1
4478 00:45:04.624318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4479 00:45:04.624760 ==
4480 00:45:04.625097 DQS Delay:
4481 00:45:04.627993 DQS0 = 0, DQS1 = 0
4482 00:45:04.628503 DQM Delay:
4483 00:45:04.630746 DQM0 = 41, DQM1 = 33
4484 00:45:04.631336 DQ Delay:
4485 00:45:04.634199 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4486 00:45:04.637310 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4487 00:45:04.640531 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4488 00:45:04.644126 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4489 00:45:04.644671
4490 00:45:04.645178
4491 00:45:04.645515 ==
4492 00:45:04.647133 Dram Type= 6, Freq= 0, CH_1, rank 1
4493 00:45:04.650807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4494 00:45:04.651365 ==
4495 00:45:04.651727
4496 00:45:04.652037
4497 00:45:04.653775 TX Vref Scan disable
4498 00:45:04.657006 == TX Byte 0 ==
4499 00:45:04.660546 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4500 00:45:04.663672 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4501 00:45:04.666974 == TX Byte 1 ==
4502 00:45:04.670256 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4503 00:45:04.673691 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4504 00:45:04.674130 ==
4505 00:45:04.676876 Dram Type= 6, Freq= 0, CH_1, rank 1
4506 00:45:04.683725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4507 00:45:04.684243 ==
4508 00:45:04.684578
4509 00:45:04.684889
4510 00:45:04.685188 TX Vref Scan disable
4511 00:45:04.687991 == TX Byte 0 ==
4512 00:45:04.691186 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4513 00:45:04.697990 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4514 00:45:04.698454 == TX Byte 1 ==
4515 00:45:04.701266 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4516 00:45:04.708032 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4517 00:45:04.708567
4518 00:45:04.708907 [DATLAT]
4519 00:45:04.709223 Freq=600, CH1 RK1
4520 00:45:04.709524
4521 00:45:04.710914 DATLAT Default: 0x8
4522 00:45:04.711349 0, 0xFFFF, sum = 0
4523 00:45:04.714354 1, 0xFFFF, sum = 0
4524 00:45:04.717870 2, 0xFFFF, sum = 0
4525 00:45:04.718541 3, 0xFFFF, sum = 0
4526 00:45:04.721131 4, 0xFFFF, sum = 0
4527 00:45:04.721650 5, 0xFFFF, sum = 0
4528 00:45:04.724165 6, 0xFFFF, sum = 0
4529 00:45:04.724605 7, 0x0, sum = 1
4530 00:45:04.724949 8, 0x0, sum = 2
4531 00:45:04.727718 9, 0x0, sum = 3
4532 00:45:04.728205 10, 0x0, sum = 4
4533 00:45:04.730772 best_step = 8
4534 00:45:04.731214
4535 00:45:04.731585 ==
4536 00:45:04.733941 Dram Type= 6, Freq= 0, CH_1, rank 1
4537 00:45:04.737844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4538 00:45:04.738395 ==
4539 00:45:04.740655 RX Vref Scan: 0
4540 00:45:04.741087
4541 00:45:04.741423 RX Vref 0 -> 0, step: 1
4542 00:45:04.741739
4543 00:45:04.744056 RX Delay -195 -> 252, step: 8
4544 00:45:04.751661 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4545 00:45:04.754704 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4546 00:45:04.758081 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4547 00:45:04.761707 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4548 00:45:04.768075 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4549 00:45:04.771125 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4550 00:45:04.774537 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4551 00:45:04.777901 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4552 00:45:04.784480 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4553 00:45:04.787879 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4554 00:45:04.791204 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4555 00:45:04.794675 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4556 00:45:04.797937 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4557 00:45:04.805181 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4558 00:45:04.807779 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4559 00:45:04.811158 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4560 00:45:04.811664 ==
4561 00:45:04.814338 Dram Type= 6, Freq= 0, CH_1, rank 1
4562 00:45:04.821116 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4563 00:45:04.821615 ==
4564 00:45:04.821951 DQS Delay:
4565 00:45:04.822451 DQS0 = 0, DQS1 = 0
4566 00:45:04.824212 DQM Delay:
4567 00:45:04.824647 DQM0 = 36, DQM1 = 28
4568 00:45:04.827476 DQ Delay:
4569 00:45:04.830793 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4570 00:45:04.834110 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4571 00:45:04.837694 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4572 00:45:04.840932 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4573 00:45:04.841541
4574 00:45:04.841885
4575 00:45:04.847525 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4576 00:45:04.850727 CH1 RK1: MR19=808, MR18=5E5E
4577 00:45:04.857192 CH1_RK1: MR19=0x808, MR18=0x5E5E, DQSOSC=392, MR23=63, INC=170, DEC=113
4578 00:45:04.860704 [RxdqsGatingPostProcess] freq 600
4579 00:45:04.864127 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4580 00:45:04.867160 Pre-setting of DQS Precalculation
4581 00:45:04.873768 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4582 00:45:04.880413 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4583 00:45:04.886973 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4584 00:45:04.887477
4585 00:45:04.887815
4586 00:45:04.890605 [Calibration Summary] 1200 Mbps
4587 00:45:04.891038 CH 0, Rank 0
4588 00:45:04.893829 SW Impedance : PASS
4589 00:45:04.896989 DUTY Scan : NO K
4590 00:45:04.897444 ZQ Calibration : PASS
4591 00:45:04.900191 Jitter Meter : NO K
4592 00:45:04.903393 CBT Training : PASS
4593 00:45:04.903830 Write leveling : PASS
4594 00:45:04.906908 RX DQS gating : PASS
4595 00:45:04.910094 RX DQ/DQS(RDDQC) : PASS
4596 00:45:04.910573 TX DQ/DQS : PASS
4597 00:45:04.913379 RX DATLAT : PASS
4598 00:45:04.916978 RX DQ/DQS(Engine): PASS
4599 00:45:04.917498 TX OE : NO K
4600 00:45:04.920037 All Pass.
4601 00:45:04.920467
4602 00:45:04.920797 CH 0, Rank 1
4603 00:45:04.923291 SW Impedance : PASS
4604 00:45:04.923724 DUTY Scan : NO K
4605 00:45:04.926687 ZQ Calibration : PASS
4606 00:45:04.929965 Jitter Meter : NO K
4607 00:45:04.930437 CBT Training : PASS
4608 00:45:04.933457 Write leveling : PASS
4609 00:45:04.936887 RX DQS gating : PASS
4610 00:45:04.937410 RX DQ/DQS(RDDQC) : PASS
4611 00:45:04.939893 TX DQ/DQS : PASS
4612 00:45:04.940326 RX DATLAT : PASS
4613 00:45:04.943225 RX DQ/DQS(Engine): PASS
4614 00:45:04.946758 TX OE : NO K
4615 00:45:04.947189 All Pass.
4616 00:45:04.947517
4617 00:45:04.947857 CH 1, Rank 0
4618 00:45:04.949888 SW Impedance : PASS
4619 00:45:04.953215 DUTY Scan : NO K
4620 00:45:04.953644 ZQ Calibration : PASS
4621 00:45:04.956602 Jitter Meter : NO K
4622 00:45:04.959779 CBT Training : PASS
4623 00:45:04.960213 Write leveling : PASS
4624 00:45:04.963259 RX DQS gating : PASS
4625 00:45:04.966583 RX DQ/DQS(RDDQC) : PASS
4626 00:45:04.967022 TX DQ/DQS : PASS
4627 00:45:04.969643 RX DATLAT : PASS
4628 00:45:04.973573 RX DQ/DQS(Engine): PASS
4629 00:45:04.974121 TX OE : NO K
4630 00:45:04.976348 All Pass.
4631 00:45:04.976775
4632 00:45:04.977119 CH 1, Rank 1
4633 00:45:04.979678 SW Impedance : PASS
4634 00:45:04.980108 DUTY Scan : NO K
4635 00:45:04.983019 ZQ Calibration : PASS
4636 00:45:04.986283 Jitter Meter : NO K
4637 00:45:04.986819 CBT Training : PASS
4638 00:45:04.989424 Write leveling : PASS
4639 00:45:04.992793 RX DQS gating : PASS
4640 00:45:04.993226 RX DQ/DQS(RDDQC) : PASS
4641 00:45:04.996266 TX DQ/DQS : PASS
4642 00:45:04.996699 RX DATLAT : PASS
4643 00:45:04.999651 RX DQ/DQS(Engine): PASS
4644 00:45:05.002780 TX OE : NO K
4645 00:45:05.003213 All Pass.
4646 00:45:05.003544
4647 00:45:05.006372 DramC Write-DBI off
4648 00:45:05.009466 PER_BANK_REFRESH: Hybrid Mode
4649 00:45:05.009900 TX_TRACKING: ON
4650 00:45:05.019324 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4651 00:45:05.022692 [FAST_K] Save calibration result to emmc
4652 00:45:05.026332 dramc_set_vcore_voltage set vcore to 662500
4653 00:45:05.026865 Read voltage for 933, 3
4654 00:45:05.029696 Vio18 = 0
4655 00:45:05.030246 Vcore = 662500
4656 00:45:05.030594 Vdram = 0
4657 00:45:05.032659 Vddq = 0
4658 00:45:05.033089 Vmddr = 0
4659 00:45:05.039723 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4660 00:45:05.042905 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4661 00:45:05.046146 MEM_TYPE=3, freq_sel=17
4662 00:45:05.049604 sv_algorithm_assistance_LP4_1600
4663 00:45:05.052968 ============ PULL DRAM RESETB DOWN ============
4664 00:45:05.056295 ========== PULL DRAM RESETB DOWN end =========
4665 00:45:05.063169 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4666 00:45:05.066011 ===================================
4667 00:45:05.066654 LPDDR4 DRAM CONFIGURATION
4668 00:45:05.069148 ===================================
4669 00:45:05.072524 EX_ROW_EN[0] = 0x0
4670 00:45:05.072957 EX_ROW_EN[1] = 0x0
4671 00:45:05.076006 LP4Y_EN = 0x0
4672 00:45:05.079219 WORK_FSP = 0x0
4673 00:45:05.079653 WL = 0x3
4674 00:45:05.082424 RL = 0x3
4675 00:45:05.082858 BL = 0x2
4676 00:45:05.085929 RPST = 0x0
4677 00:45:05.086400 RD_PRE = 0x0
4678 00:45:05.089350 WR_PRE = 0x1
4679 00:45:05.089871 WR_PST = 0x0
4680 00:45:05.092918 DBI_WR = 0x0
4681 00:45:05.093427 DBI_RD = 0x0
4682 00:45:05.095760 OTF = 0x1
4683 00:45:05.099283 ===================================
4684 00:45:05.102935 ===================================
4685 00:45:05.103449 ANA top config
4686 00:45:05.105791 ===================================
4687 00:45:05.109389 DLL_ASYNC_EN = 0
4688 00:45:05.112384 ALL_SLAVE_EN = 1
4689 00:45:05.112816 NEW_RANK_MODE = 1
4690 00:45:05.116168 DLL_IDLE_MODE = 1
4691 00:45:05.119346 LP45_APHY_COMB_EN = 1
4692 00:45:05.122683 TX_ODT_DIS = 1
4693 00:45:05.126058 NEW_8X_MODE = 1
4694 00:45:05.126605 ===================================
4695 00:45:05.129348 ===================================
4696 00:45:05.132250 data_rate = 1866
4697 00:45:05.135543 CKR = 1
4698 00:45:05.139202 DQ_P2S_RATIO = 8
4699 00:45:05.142574 ===================================
4700 00:45:05.145701 CA_P2S_RATIO = 8
4701 00:45:05.148913 DQ_CA_OPEN = 0
4702 00:45:05.152259 DQ_SEMI_OPEN = 0
4703 00:45:05.152690 CA_SEMI_OPEN = 0
4704 00:45:05.155558 CA_FULL_RATE = 0
4705 00:45:05.158719 DQ_CKDIV4_EN = 1
4706 00:45:05.162321 CA_CKDIV4_EN = 1
4707 00:45:05.165472 CA_PREDIV_EN = 0
4708 00:45:05.168805 PH8_DLY = 0
4709 00:45:05.169236 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4710 00:45:05.172498 DQ_AAMCK_DIV = 4
4711 00:45:05.175601 CA_AAMCK_DIV = 4
4712 00:45:05.178888 CA_ADMCK_DIV = 4
4713 00:45:05.182013 DQ_TRACK_CA_EN = 0
4714 00:45:05.185337 CA_PICK = 933
4715 00:45:05.185768 CA_MCKIO = 933
4716 00:45:05.189073 MCKIO_SEMI = 0
4717 00:45:05.192060 PLL_FREQ = 3732
4718 00:45:05.195626 DQ_UI_PI_RATIO = 32
4719 00:45:05.198759 CA_UI_PI_RATIO = 0
4720 00:45:05.202424 ===================================
4721 00:45:05.205279 ===================================
4722 00:45:05.208869 memory_type:LPDDR4
4723 00:45:05.209393 GP_NUM : 10
4724 00:45:05.212064 SRAM_EN : 1
4725 00:45:05.212570 MD32_EN : 0
4726 00:45:05.215359 ===================================
4727 00:45:05.218956 [ANA_INIT] >>>>>>>>>>>>>>
4728 00:45:05.222277 <<<<<< [CONFIGURE PHASE]: ANA_TX
4729 00:45:05.225489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4730 00:45:05.228594 ===================================
4731 00:45:05.231818 data_rate = 1866,PCW = 0X8f00
4732 00:45:05.235233 ===================================
4733 00:45:05.238705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4734 00:45:05.244895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4735 00:45:05.249121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4736 00:45:05.255134 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4737 00:45:05.258602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4738 00:45:05.261581 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4739 00:45:05.262019 [ANA_INIT] flow start
4740 00:45:05.264954 [ANA_INIT] PLL >>>>>>>>
4741 00:45:05.268215 [ANA_INIT] PLL <<<<<<<<
4742 00:45:05.268643 [ANA_INIT] MIDPI >>>>>>>>
4743 00:45:05.271345 [ANA_INIT] MIDPI <<<<<<<<
4744 00:45:05.274928 [ANA_INIT] DLL >>>>>>>>
4745 00:45:05.275360 [ANA_INIT] flow end
4746 00:45:05.281403 ============ LP4 DIFF to SE enter ============
4747 00:45:05.284670 ============ LP4 DIFF to SE exit ============
4748 00:45:05.287901 [ANA_INIT] <<<<<<<<<<<<<
4749 00:45:05.291271 [Flow] Enable top DCM control >>>>>
4750 00:45:05.294599 [Flow] Enable top DCM control <<<<<
4751 00:45:05.295033 Enable DLL master slave shuffle
4752 00:45:05.301185 ==============================================================
4753 00:45:05.304241 Gating Mode config
4754 00:45:05.308229 ==============================================================
4755 00:45:05.310965 Config description:
4756 00:45:05.320923 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4757 00:45:05.327598 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4758 00:45:05.331140 SELPH_MODE 0: By rank 1: By Phase
4759 00:45:05.337898 ==============================================================
4760 00:45:05.341155 GAT_TRACK_EN = 1
4761 00:45:05.344450 RX_GATING_MODE = 2
4762 00:45:05.347565 RX_GATING_TRACK_MODE = 2
4763 00:45:05.351119 SELPH_MODE = 1
4764 00:45:05.354261 PICG_EARLY_EN = 1
4765 00:45:05.354700 VALID_LAT_VALUE = 1
4766 00:45:05.361182 ==============================================================
4767 00:45:05.364502 Enter into Gating configuration >>>>
4768 00:45:05.367560 Exit from Gating configuration <<<<
4769 00:45:05.371050 Enter into DVFS_PRE_config >>>>>
4770 00:45:05.380784 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4771 00:45:05.383996 Exit from DVFS_PRE_config <<<<<
4772 00:45:05.387022 Enter into PICG configuration >>>>
4773 00:45:05.390666 Exit from PICG configuration <<<<
4774 00:45:05.393913 [RX_INPUT] configuration >>>>>
4775 00:45:05.397244 [RX_INPUT] configuration <<<<<
4776 00:45:05.403860 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4777 00:45:05.407600 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4778 00:45:05.413845 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4779 00:45:05.420163 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4780 00:45:05.426974 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4781 00:45:05.433460 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4782 00:45:05.436828 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4783 00:45:05.440236 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4784 00:45:05.443526 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4785 00:45:05.450259 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4786 00:45:05.453710 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4787 00:45:05.456941 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4788 00:45:05.460269 ===================================
4789 00:45:05.463615 LPDDR4 DRAM CONFIGURATION
4790 00:45:05.466751 ===================================
4791 00:45:05.467258 EX_ROW_EN[0] = 0x0
4792 00:45:05.469921 EX_ROW_EN[1] = 0x0
4793 00:45:05.473256 LP4Y_EN = 0x0
4794 00:45:05.473694 WORK_FSP = 0x0
4795 00:45:05.476549 WL = 0x3
4796 00:45:05.476981 RL = 0x3
4797 00:45:05.479804 BL = 0x2
4798 00:45:05.480402 RPST = 0x0
4799 00:45:05.483068 RD_PRE = 0x0
4800 00:45:05.483499 WR_PRE = 0x1
4801 00:45:05.486309 WR_PST = 0x0
4802 00:45:05.486741 DBI_WR = 0x0
4803 00:45:05.489859 DBI_RD = 0x0
4804 00:45:05.490452 OTF = 0x1
4805 00:45:05.493078 ===================================
4806 00:45:05.496687 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4807 00:45:05.503090 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4808 00:45:05.506502 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4809 00:45:05.509869 ===================================
4810 00:45:05.512964 LPDDR4 DRAM CONFIGURATION
4811 00:45:05.516047 ===================================
4812 00:45:05.516486 EX_ROW_EN[0] = 0x10
4813 00:45:05.519626 EX_ROW_EN[1] = 0x0
4814 00:45:05.522702 LP4Y_EN = 0x0
4815 00:45:05.523137 WORK_FSP = 0x0
4816 00:45:05.525971 WL = 0x3
4817 00:45:05.526437 RL = 0x3
4818 00:45:05.529353 BL = 0x2
4819 00:45:05.529918 RPST = 0x0
4820 00:45:05.532782 RD_PRE = 0x0
4821 00:45:05.533291 WR_PRE = 0x1
4822 00:45:05.535892 WR_PST = 0x0
4823 00:45:05.536332 DBI_WR = 0x0
4824 00:45:05.539225 DBI_RD = 0x0
4825 00:45:05.539657 OTF = 0x1
4826 00:45:05.542532 ===================================
4827 00:45:05.549059 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4828 00:45:05.553509 nWR fixed to 30
4829 00:45:05.557081 [ModeRegInit_LP4] CH0 RK0
4830 00:45:05.557532 [ModeRegInit_LP4] CH0 RK1
4831 00:45:05.560195 [ModeRegInit_LP4] CH1 RK0
4832 00:45:05.563329 [ModeRegInit_LP4] CH1 RK1
4833 00:45:05.563821 match AC timing 8
4834 00:45:05.570005 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4835 00:45:05.573373 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4836 00:45:05.576805 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4837 00:45:05.583489 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4838 00:45:05.586646 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4839 00:45:05.587201 ==
4840 00:45:05.590015 Dram Type= 6, Freq= 0, CH_0, rank 0
4841 00:45:05.593288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4842 00:45:05.593725 ==
4843 00:45:05.600114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4844 00:45:05.606774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4845 00:45:05.610115 [CA 0] Center 38 (8~69) winsize 62
4846 00:45:05.613091 [CA 1] Center 38 (8~69) winsize 62
4847 00:45:05.616626 [CA 2] Center 36 (5~67) winsize 63
4848 00:45:05.619920 [CA 3] Center 36 (6~67) winsize 62
4849 00:45:05.622951 [CA 4] Center 35 (5~65) winsize 61
4850 00:45:05.626281 [CA 5] Center 34 (4~65) winsize 62
4851 00:45:05.626679
4852 00:45:05.629864 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4853 00:45:05.630452
4854 00:45:05.633032 [CATrainingPosCal] consider 1 rank data
4855 00:45:05.636491 u2DelayCellTimex100 = 270/100 ps
4856 00:45:05.639884 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4857 00:45:05.643361 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4858 00:45:05.646262 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4859 00:45:05.649493 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4860 00:45:05.652692 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4861 00:45:05.659789 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4862 00:45:05.660221
4863 00:45:05.662665 CA PerBit enable=1, Macro0, CA PI delay=34
4864 00:45:05.663097
4865 00:45:05.666062 [CBTSetCACLKResult] CA Dly = 34
4866 00:45:05.666552 CS Dly: 6 (0~37)
4867 00:45:05.666853 ==
4868 00:45:05.669300 Dram Type= 6, Freq= 0, CH_0, rank 1
4869 00:45:05.672654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4870 00:45:05.675990 ==
4871 00:45:05.679252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4872 00:45:05.686062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4873 00:45:05.689354 [CA 0] Center 38 (8~69) winsize 62
4874 00:45:05.692663 [CA 1] Center 38 (8~69) winsize 62
4875 00:45:05.695883 [CA 2] Center 36 (6~67) winsize 62
4876 00:45:05.699369 [CA 3] Center 35 (5~66) winsize 62
4877 00:45:05.702396 [CA 4] Center 34 (4~65) winsize 62
4878 00:45:05.705790 [CA 5] Center 34 (4~65) winsize 62
4879 00:45:05.706185
4880 00:45:05.709320 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4881 00:45:05.709770
4882 00:45:05.712530 [CATrainingPosCal] consider 2 rank data
4883 00:45:05.715703 u2DelayCellTimex100 = 270/100 ps
4884 00:45:05.719611 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4885 00:45:05.722494 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4886 00:45:05.725947 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4887 00:45:05.732211 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4888 00:45:05.735770 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4889 00:45:05.739067 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4890 00:45:05.739583
4891 00:45:05.742130 CA PerBit enable=1, Macro0, CA PI delay=34
4892 00:45:05.742621
4893 00:45:05.745759 [CBTSetCACLKResult] CA Dly = 34
4894 00:45:05.746321 CS Dly: 7 (0~39)
4895 00:45:05.746670
4896 00:45:05.748829 ----->DramcWriteLeveling(PI) begin...
4897 00:45:05.752350 ==
4898 00:45:05.752786 Dram Type= 6, Freq= 0, CH_0, rank 0
4899 00:45:05.759128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4900 00:45:05.759673 ==
4901 00:45:05.762195 Write leveling (Byte 0): 29 => 29
4902 00:45:05.765738 Write leveling (Byte 1): 27 => 27
4903 00:45:05.769017 DramcWriteLeveling(PI) end<-----
4904 00:45:05.769556
4905 00:45:05.770069 ==
4906 00:45:05.772258 Dram Type= 6, Freq= 0, CH_0, rank 0
4907 00:45:05.775388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4908 00:45:05.775828 ==
4909 00:45:05.778750 [Gating] SW mode calibration
4910 00:45:05.785559 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4911 00:45:05.788617 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4912 00:45:05.795275 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4913 00:45:05.798598 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4914 00:45:05.801996 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4915 00:45:05.808550 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4916 00:45:05.811797 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4917 00:45:05.815030 0 10 20 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 0)
4918 00:45:05.821636 0 10 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4919 00:45:05.824976 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4920 00:45:05.828165 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4921 00:45:05.835115 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4922 00:45:05.838229 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4923 00:45:05.841987 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4924 00:45:05.848265 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4925 00:45:05.851904 0 11 20 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
4926 00:45:05.854894 0 11 24 | B1->B0 | 3838 4545 | 1 0 | (1 1) (0 0)
4927 00:45:05.861889 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4928 00:45:05.864869 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4929 00:45:05.868485 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4930 00:45:05.874931 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4931 00:45:05.878407 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4932 00:45:05.881705 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4933 00:45:05.888422 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4934 00:45:05.891591 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 00:45:05.894819 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 00:45:05.901500 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 00:45:05.904725 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 00:45:05.908157 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 00:45:05.914587 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 00:45:05.917763 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 00:45:05.921502 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 00:45:05.927899 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 00:45:05.931262 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 00:45:05.934389 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 00:45:05.941530 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 00:45:05.944875 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 00:45:05.947814 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 00:45:05.954492 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4949 00:45:05.958177 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4950 00:45:05.961068 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4951 00:45:05.964217 Total UI for P1: 0, mck2ui 16
4952 00:45:05.967788 best dqsien dly found for B0: ( 0, 14, 18)
4953 00:45:05.970983 Total UI for P1: 0, mck2ui 16
4954 00:45:05.974457 best dqsien dly found for B1: ( 0, 14, 20)
4955 00:45:05.977669 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
4956 00:45:05.981106 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4957 00:45:05.981621
4958 00:45:05.984520 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
4959 00:45:05.990701 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4960 00:45:05.991140 [Gating] SW calibration Done
4961 00:45:05.994037 ==
4962 00:45:05.994526 Dram Type= 6, Freq= 0, CH_0, rank 0
4963 00:45:06.000553 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4964 00:45:06.000991 ==
4965 00:45:06.001328 RX Vref Scan: 0
4966 00:45:06.001635
4967 00:45:06.004021 RX Vref 0 -> 0, step: 1
4968 00:45:06.004454
4969 00:45:06.007632 RX Delay -80 -> 252, step: 8
4970 00:45:06.010500 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4971 00:45:06.014283 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4972 00:45:06.017391 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4973 00:45:06.024057 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4974 00:45:06.027090 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4975 00:45:06.030706 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
4976 00:45:06.033940 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4977 00:45:06.037185 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4978 00:45:06.040783 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4979 00:45:06.047136 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4980 00:45:06.050317 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4981 00:45:06.053721 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4982 00:45:06.057001 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4983 00:45:06.060409 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4984 00:45:06.066871 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4985 00:45:06.070324 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4986 00:45:06.070764 ==
4987 00:45:06.073568 Dram Type= 6, Freq= 0, CH_0, rank 0
4988 00:45:06.077007 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4989 00:45:06.077477 ==
4990 00:45:06.077816 DQS Delay:
4991 00:45:06.080650 DQS0 = 0, DQS1 = 0
4992 00:45:06.081082 DQM Delay:
4993 00:45:06.083708 DQM0 = 95, DQM1 = 86
4994 00:45:06.084139 DQ Delay:
4995 00:45:06.087052 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
4996 00:45:06.090180 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
4997 00:45:06.093778 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
4998 00:45:06.097222 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
4999 00:45:06.097746
5000 00:45:06.098086
5001 00:45:06.098453 ==
5002 00:45:06.100362 Dram Type= 6, Freq= 0, CH_0, rank 0
5003 00:45:06.103629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5004 00:45:06.106846 ==
5005 00:45:06.107277
5006 00:45:06.107609
5007 00:45:06.107918 TX Vref Scan disable
5008 00:45:06.110417 == TX Byte 0 ==
5009 00:45:06.113812 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5010 00:45:06.117196 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5011 00:45:06.120152 == TX Byte 1 ==
5012 00:45:06.123743 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5013 00:45:06.126953 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5014 00:45:06.127391 ==
5015 00:45:06.130332 Dram Type= 6, Freq= 0, CH_0, rank 0
5016 00:45:06.137153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5017 00:45:06.137658 ==
5018 00:45:06.137997
5019 00:45:06.138357
5020 00:45:06.140387 TX Vref Scan disable
5021 00:45:06.140909 == TX Byte 0 ==
5022 00:45:06.147178 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5023 00:45:06.150389 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5024 00:45:06.150907 == TX Byte 1 ==
5025 00:45:06.157257 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5026 00:45:06.160237 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5027 00:45:06.160677
5028 00:45:06.161013 [DATLAT]
5029 00:45:06.163394 Freq=933, CH0 RK0
5030 00:45:06.163828
5031 00:45:06.164160 DATLAT Default: 0xd
5032 00:45:06.166558 0, 0xFFFF, sum = 0
5033 00:45:06.167002 1, 0xFFFF, sum = 0
5034 00:45:06.170245 2, 0xFFFF, sum = 0
5035 00:45:06.170884 3, 0xFFFF, sum = 0
5036 00:45:06.173198 4, 0xFFFF, sum = 0
5037 00:45:06.173822 5, 0xFFFF, sum = 0
5038 00:45:06.176594 6, 0xFFFF, sum = 0
5039 00:45:06.177038 7, 0xFFFF, sum = 0
5040 00:45:06.179763 8, 0xFFFF, sum = 0
5041 00:45:06.180209 9, 0xFFFF, sum = 0
5042 00:45:06.183194 10, 0x0, sum = 1
5043 00:45:06.183636 11, 0x0, sum = 2
5044 00:45:06.186401 12, 0x0, sum = 3
5045 00:45:06.186847 13, 0x0, sum = 4
5046 00:45:06.189796 best_step = 11
5047 00:45:06.190270
5048 00:45:06.190721 ==
5049 00:45:06.193348 Dram Type= 6, Freq= 0, CH_0, rank 0
5050 00:45:06.196420 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5051 00:45:06.196867 ==
5052 00:45:06.199865 RX Vref Scan: 1
5053 00:45:06.200307
5054 00:45:06.200739 RX Vref 0 -> 0, step: 1
5055 00:45:06.201155
5056 00:45:06.203210 RX Delay -69 -> 252, step: 4
5057 00:45:06.203642
5058 00:45:06.206503 Set Vref, RX VrefLevel [Byte0]: 48
5059 00:45:06.210200 [Byte1]: 48
5060 00:45:06.214192
5061 00:45:06.214734 Final RX Vref Byte 0 = 48 to rank0
5062 00:45:06.217553 Final RX Vref Byte 1 = 48 to rank0
5063 00:45:06.220653 Final RX Vref Byte 0 = 48 to rank1
5064 00:45:06.223847 Final RX Vref Byte 1 = 48 to rank1==
5065 00:45:06.227099 Dram Type= 6, Freq= 0, CH_0, rank 0
5066 00:45:06.233835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5067 00:45:06.234384 ==
5068 00:45:06.234730 DQS Delay:
5069 00:45:06.235040 DQS0 = 0, DQS1 = 0
5070 00:45:06.237399 DQM Delay:
5071 00:45:06.237924 DQM0 = 97, DQM1 = 87
5072 00:45:06.240405 DQ Delay:
5073 00:45:06.244000 DQ0 =92, DQ1 =100, DQ2 =96, DQ3 =92
5074 00:45:06.247136 DQ4 =102, DQ5 =88, DQ6 =106, DQ7 =104
5075 00:45:06.250351 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5076 00:45:06.254097 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =98
5077 00:45:06.254681
5078 00:45:06.255118
5079 00:45:06.260390 [DQSOSCAuto] RK0, (LSB)MR18= 0x2020, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5080 00:45:06.263610 CH0 RK0: MR19=505, MR18=2020
5081 00:45:06.270158 CH0_RK0: MR19=0x505, MR18=0x2020, DQSOSC=411, MR23=63, INC=64, DEC=42
5082 00:45:06.270653
5083 00:45:06.273574 ----->DramcWriteLeveling(PI) begin...
5084 00:45:06.274254 ==
5085 00:45:06.276897 Dram Type= 6, Freq= 0, CH_0, rank 1
5086 00:45:06.280372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5087 00:45:06.280826 ==
5088 00:45:06.283686 Write leveling (Byte 0): 30 => 30
5089 00:45:06.286778 Write leveling (Byte 1): 30 => 30
5090 00:45:06.290281 DramcWriteLeveling(PI) end<-----
5091 00:45:06.290719
5092 00:45:06.291056 ==
5093 00:45:06.293501 Dram Type= 6, Freq= 0, CH_0, rank 1
5094 00:45:06.296916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5095 00:45:06.297482 ==
5096 00:45:06.300357 [Gating] SW mode calibration
5097 00:45:06.306662 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5098 00:45:06.313489 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5099 00:45:06.317079 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 00:45:06.323404 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 00:45:06.326857 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 00:45:06.330140 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 00:45:06.337021 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 00:45:06.339952 0 10 20 | B1->B0 | 3333 3030 | 1 1 | (1 0) (1 0)
5105 00:45:06.343502 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5106 00:45:06.350090 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 00:45:06.353332 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 00:45:06.357073 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 00:45:06.363370 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 00:45:06.366687 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 00:45:06.370335 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5112 00:45:06.373431 0 11 20 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
5113 00:45:06.379890 0 11 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5114 00:45:06.383310 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 00:45:06.386603 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 00:45:06.393662 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 00:45:06.396315 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 00:45:06.399945 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 00:45:06.406610 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 00:45:06.410057 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5121 00:45:06.413492 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5122 00:45:06.419942 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 00:45:06.423077 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 00:45:06.426582 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 00:45:06.433052 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 00:45:06.436226 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 00:45:06.439483 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 00:45:06.446396 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 00:45:06.449589 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 00:45:06.453353 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 00:45:06.459406 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 00:45:06.462983 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 00:45:06.466171 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 00:45:06.473075 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 00:45:06.476089 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5136 00:45:06.479435 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5137 00:45:06.485976 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5138 00:45:06.486446 Total UI for P1: 0, mck2ui 16
5139 00:45:06.492632 best dqsien dly found for B0: ( 0, 14, 18)
5140 00:45:06.495999 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 00:45:06.499420 Total UI for P1: 0, mck2ui 16
5142 00:45:06.502729 best dqsien dly found for B1: ( 0, 14, 22)
5143 00:45:06.506064 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5144 00:45:06.509594 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5145 00:45:06.510102
5146 00:45:06.512601 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5147 00:45:06.516012 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5148 00:45:06.519219 [Gating] SW calibration Done
5149 00:45:06.519650 ==
5150 00:45:06.522662 Dram Type= 6, Freq= 0, CH_0, rank 1
5151 00:45:06.526359 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5152 00:45:06.526891 ==
5153 00:45:06.529467 RX Vref Scan: 0
5154 00:45:06.529896
5155 00:45:06.532644 RX Vref 0 -> 0, step: 1
5156 00:45:06.533070
5157 00:45:06.533402 RX Delay -80 -> 252, step: 8
5158 00:45:06.539386 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5159 00:45:06.542730 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5160 00:45:06.546431 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5161 00:45:06.549371 iDelay=200, Bit 3, Center 91 (0 ~ 183) 184
5162 00:45:06.552752 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5163 00:45:06.555823 iDelay=200, Bit 5, Center 91 (-8 ~ 191) 200
5164 00:45:06.562666 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5165 00:45:06.565647 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5166 00:45:06.568965 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5167 00:45:06.572581 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5168 00:45:06.575786 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5169 00:45:06.582370 iDelay=200, Bit 11, Center 75 (-16 ~ 167) 184
5170 00:45:06.585583 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5171 00:45:06.588939 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5172 00:45:06.592115 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5173 00:45:06.595718 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5174 00:45:06.596152 ==
5175 00:45:06.598893 Dram Type= 6, Freq= 0, CH_0, rank 1
5176 00:45:06.605511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5177 00:45:06.606070 ==
5178 00:45:06.606521 DQS Delay:
5179 00:45:06.609604 DQS0 = 0, DQS1 = 0
5180 00:45:06.610140 DQM Delay:
5181 00:45:06.610529 DQM0 = 96, DQM1 = 84
5182 00:45:06.612344 DQ Delay:
5183 00:45:06.615532 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5184 00:45:06.618862 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =103
5185 00:45:06.622078 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =75
5186 00:45:06.625790 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5187 00:45:06.626377
5188 00:45:06.626725
5189 00:45:06.627083 ==
5190 00:45:06.628718 Dram Type= 6, Freq= 0, CH_0, rank 1
5191 00:45:06.632000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5192 00:45:06.632551 ==
5193 00:45:06.632892
5194 00:45:06.633204
5195 00:45:06.635338 TX Vref Scan disable
5196 00:45:06.638589 == TX Byte 0 ==
5197 00:45:06.642251 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5198 00:45:06.645531 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5199 00:45:06.648542 == TX Byte 1 ==
5200 00:45:06.652206 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5201 00:45:06.655452 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5202 00:45:06.655893 ==
5203 00:45:06.658577 Dram Type= 6, Freq= 0, CH_0, rank 1
5204 00:45:06.662026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5205 00:45:06.662610 ==
5206 00:45:06.662988
5207 00:45:06.665666
5208 00:45:06.666194 TX Vref Scan disable
5209 00:45:06.668941 == TX Byte 0 ==
5210 00:45:06.672120 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5211 00:45:06.675117 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5212 00:45:06.678631 == TX Byte 1 ==
5213 00:45:06.681774 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5214 00:45:06.688595 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5215 00:45:06.689125
5216 00:45:06.689567 [DATLAT]
5217 00:45:06.689984 Freq=933, CH0 RK1
5218 00:45:06.690480
5219 00:45:06.691682 DATLAT Default: 0xb
5220 00:45:06.692133 0, 0xFFFF, sum = 0
5221 00:45:06.695264 1, 0xFFFF, sum = 0
5222 00:45:06.695785 2, 0xFFFF, sum = 0
5223 00:45:06.698340 3, 0xFFFF, sum = 0
5224 00:45:06.701954 4, 0xFFFF, sum = 0
5225 00:45:06.702540 5, 0xFFFF, sum = 0
5226 00:45:06.704974 6, 0xFFFF, sum = 0
5227 00:45:06.705419 7, 0xFFFF, sum = 0
5228 00:45:06.708540 8, 0xFFFF, sum = 0
5229 00:45:06.709069 9, 0xFFFF, sum = 0
5230 00:45:06.711529 10, 0x0, sum = 1
5231 00:45:06.711972 11, 0x0, sum = 2
5232 00:45:06.714807 12, 0x0, sum = 3
5233 00:45:06.715342 13, 0x0, sum = 4
5234 00:45:06.715692 best_step = 11
5235 00:45:06.716000
5236 00:45:06.718288 ==
5237 00:45:06.721616 Dram Type= 6, Freq= 0, CH_0, rank 1
5238 00:45:06.724729 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5239 00:45:06.725181 ==
5240 00:45:06.725697 RX Vref Scan: 0
5241 00:45:06.726033
5242 00:45:06.728213 RX Vref 0 -> 0, step: 1
5243 00:45:06.728644
5244 00:45:06.731491 RX Delay -69 -> 252, step: 4
5245 00:45:06.734771 iDelay=199, Bit 0, Center 92 (3 ~ 182) 180
5246 00:45:06.741366 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5247 00:45:06.744604 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5248 00:45:06.748052 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5249 00:45:06.751520 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5250 00:45:06.754480 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5251 00:45:06.761396 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5252 00:45:06.764745 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5253 00:45:06.767678 iDelay=199, Bit 8, Center 76 (-9 ~ 162) 172
5254 00:45:06.771444 iDelay=199, Bit 9, Center 74 (-13 ~ 162) 176
5255 00:45:06.774358 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5256 00:45:06.777516 iDelay=199, Bit 11, Center 76 (-9 ~ 162) 172
5257 00:45:06.784236 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5258 00:45:06.787652 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5259 00:45:06.790788 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5260 00:45:06.794394 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5261 00:45:06.794831 ==
5262 00:45:06.797677 Dram Type= 6, Freq= 0, CH_0, rank 1
5263 00:45:06.804190 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5264 00:45:06.804626 ==
5265 00:45:06.804963 DQS Delay:
5266 00:45:06.805270 DQS0 = 0, DQS1 = 0
5267 00:45:06.807833 DQM Delay:
5268 00:45:06.808348 DQM0 = 97, DQM1 = 86
5269 00:45:06.810771 DQ Delay:
5270 00:45:06.814071 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5271 00:45:06.817613 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =106
5272 00:45:06.820961 DQ8 =76, DQ9 =74, DQ10 =90, DQ11 =76
5273 00:45:06.823939 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =94
5274 00:45:06.824372
5275 00:45:06.824868
5276 00:45:06.830387 [DQSOSCAuto] RK1, (LSB)MR18= 0x3434, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5277 00:45:06.834170 CH0 RK1: MR19=505, MR18=3434
5278 00:45:06.840480 CH0_RK1: MR19=0x505, MR18=0x3434, DQSOSC=405, MR23=63, INC=66, DEC=44
5279 00:45:06.843969 [RxdqsGatingPostProcess] freq 933
5280 00:45:06.847201 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5281 00:45:06.850483 Pre-setting of DQS Precalculation
5282 00:45:06.857464 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5283 00:45:06.857972 ==
5284 00:45:06.860551 Dram Type= 6, Freq= 0, CH_1, rank 0
5285 00:45:06.863961 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5286 00:45:06.864410 ==
5287 00:45:06.870488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5288 00:45:06.877043 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5289 00:45:06.880422 [CA 0] Center 37 (6~68) winsize 63
5290 00:45:06.883737 [CA 1] Center 37 (6~68) winsize 63
5291 00:45:06.886886 [CA 2] Center 34 (4~65) winsize 62
5292 00:45:06.890131 [CA 3] Center 34 (3~65) winsize 63
5293 00:45:06.893980 [CA 4] Center 33 (3~64) winsize 62
5294 00:45:06.896788 [CA 5] Center 33 (3~64) winsize 62
5295 00:45:06.897219
5296 00:45:06.899900 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5297 00:45:06.900416
5298 00:45:06.903350 [CATrainingPosCal] consider 1 rank data
5299 00:45:06.906573 u2DelayCellTimex100 = 270/100 ps
5300 00:45:06.909874 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5301 00:45:06.913163 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5302 00:45:06.916484 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5303 00:45:06.919867 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5304 00:45:06.922988 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5305 00:45:06.926254 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5306 00:45:06.926461
5307 00:45:06.933108 CA PerBit enable=1, Macro0, CA PI delay=33
5308 00:45:06.933386
5309 00:45:06.933552 [CBTSetCACLKResult] CA Dly = 33
5310 00:45:06.936080 CS Dly: 5 (0~36)
5311 00:45:06.936288 ==
5312 00:45:06.939765 Dram Type= 6, Freq= 0, CH_1, rank 1
5313 00:45:06.942664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5314 00:45:06.942945 ==
5315 00:45:06.949299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5316 00:45:06.956525 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5317 00:45:06.959460 [CA 0] Center 37 (6~68) winsize 63
5318 00:45:06.962946 [CA 1] Center 37 (6~68) winsize 63
5319 00:45:06.966312 [CA 2] Center 34 (4~65) winsize 62
5320 00:45:06.969606 [CA 3] Center 34 (4~65) winsize 62
5321 00:45:06.972942 [CA 4] Center 33 (3~64) winsize 62
5322 00:45:06.976176 [CA 5] Center 33 (3~63) winsize 61
5323 00:45:06.976832
5324 00:45:06.979540 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5325 00:45:06.979972
5326 00:45:06.982665 [CATrainingPosCal] consider 2 rank data
5327 00:45:06.985998 u2DelayCellTimex100 = 270/100 ps
5328 00:45:06.989925 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5329 00:45:06.992732 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5330 00:45:06.996126 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5331 00:45:06.999414 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5332 00:45:07.002834 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5333 00:45:07.005997 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5334 00:45:07.009458
5335 00:45:07.012833 CA PerBit enable=1, Macro0, CA PI delay=33
5336 00:45:07.013363
5337 00:45:07.016158 [CBTSetCACLKResult] CA Dly = 33
5338 00:45:07.016672 CS Dly: 5 (0~37)
5339 00:45:07.017006
5340 00:45:07.019198 ----->DramcWriteLeveling(PI) begin...
5341 00:45:07.019637 ==
5342 00:45:07.022558 Dram Type= 6, Freq= 0, CH_1, rank 0
5343 00:45:07.025899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5344 00:45:07.029012 ==
5345 00:45:07.029440 Write leveling (Byte 0): 26 => 26
5346 00:45:07.032828 Write leveling (Byte 1): 26 => 26
5347 00:45:07.035576 DramcWriteLeveling(PI) end<-----
5348 00:45:07.036021
5349 00:45:07.036354 ==
5350 00:45:07.039424 Dram Type= 6, Freq= 0, CH_1, rank 0
5351 00:45:07.045762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5352 00:45:07.046295 ==
5353 00:45:07.049221 [Gating] SW mode calibration
5354 00:45:07.055666 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5355 00:45:07.058816 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5356 00:45:07.065767 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 00:45:07.069119 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 00:45:07.072206 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 00:45:07.078711 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 00:45:07.082062 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5361 00:45:07.085132 0 10 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
5362 00:45:07.092015 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
5363 00:45:07.095046 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 00:45:07.098561 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 00:45:07.104971 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 00:45:07.108915 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 00:45:07.112136 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 00:45:07.118190 0 11 16 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
5369 00:45:07.121936 0 11 20 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
5370 00:45:07.125118 0 11 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5371 00:45:07.131765 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 00:45:07.135006 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 00:45:07.138862 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 00:45:07.141877 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 00:45:07.148370 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 00:45:07.151586 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5377 00:45:07.155257 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5378 00:45:07.161330 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 00:45:07.164981 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 00:45:07.168122 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 00:45:07.174756 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 00:45:07.177769 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 00:45:07.181464 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 00:45:07.187947 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 00:45:07.190893 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 00:45:07.194155 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 00:45:07.200834 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 00:45:07.204178 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 00:45:07.207431 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 00:45:07.214411 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 00:45:07.217668 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 00:45:07.221327 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5393 00:45:07.227414 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5394 00:45:07.231069 Total UI for P1: 0, mck2ui 16
5395 00:45:07.234069 best dqsien dly found for B0: ( 0, 14, 16)
5396 00:45:07.237227 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 00:45:07.240384 Total UI for P1: 0, mck2ui 16
5398 00:45:07.243594 best dqsien dly found for B1: ( 0, 14, 20)
5399 00:45:07.247170 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5400 00:45:07.250681 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5401 00:45:07.251189
5402 00:45:07.254135 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5403 00:45:07.260522 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5404 00:45:07.261017 [Gating] SW calibration Done
5405 00:45:07.261363 ==
5406 00:45:07.263601 Dram Type= 6, Freq= 0, CH_1, rank 0
5407 00:45:07.270312 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5408 00:45:07.270822 ==
5409 00:45:07.271159 RX Vref Scan: 0
5410 00:45:07.271473
5411 00:45:07.273542 RX Vref 0 -> 0, step: 1
5412 00:45:07.273976
5413 00:45:07.276984 RX Delay -80 -> 252, step: 8
5414 00:45:07.280107 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5415 00:45:07.283437 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5416 00:45:07.286815 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5417 00:45:07.293143 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5418 00:45:07.296660 iDelay=208, Bit 4, Center 95 (-8 ~ 199) 208
5419 00:45:07.299909 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5420 00:45:07.303249 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5421 00:45:07.306503 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5422 00:45:07.310156 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5423 00:45:07.316590 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5424 00:45:07.319932 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5425 00:45:07.323158 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5426 00:45:07.326782 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5427 00:45:07.329896 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5428 00:45:07.336486 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5429 00:45:07.339766 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5430 00:45:07.340207 ==
5431 00:45:07.343265 Dram Type= 6, Freq= 0, CH_1, rank 0
5432 00:45:07.346660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5433 00:45:07.347185 ==
5434 00:45:07.347630 DQS Delay:
5435 00:45:07.349639 DQS0 = 0, DQS1 = 0
5436 00:45:07.350079 DQM Delay:
5437 00:45:07.353000 DQM0 = 95, DQM1 = 87
5438 00:45:07.353516 DQ Delay:
5439 00:45:07.356527 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5440 00:45:07.359729 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5441 00:45:07.362860 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5442 00:45:07.366324 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5443 00:45:07.366763
5444 00:45:07.367094
5445 00:45:07.367398 ==
5446 00:45:07.369467 Dram Type= 6, Freq= 0, CH_1, rank 0
5447 00:45:07.376079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5448 00:45:07.376516 ==
5449 00:45:07.376849
5450 00:45:07.377174
5451 00:45:07.377470 TX Vref Scan disable
5452 00:45:07.379477 == TX Byte 0 ==
5453 00:45:07.382566 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5454 00:45:07.389402 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5455 00:45:07.389916 == TX Byte 1 ==
5456 00:45:07.393582 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5457 00:45:07.399486 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5458 00:45:07.400007 ==
5459 00:45:07.402439 Dram Type= 6, Freq= 0, CH_1, rank 0
5460 00:45:07.405806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5461 00:45:07.406375 ==
5462 00:45:07.406721
5463 00:45:07.407031
5464 00:45:07.409198 TX Vref Scan disable
5465 00:45:07.412696 == TX Byte 0 ==
5466 00:45:07.415856 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5467 00:45:07.418921 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5468 00:45:07.422331 == TX Byte 1 ==
5469 00:45:07.425820 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5470 00:45:07.428777 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5471 00:45:07.429208
5472 00:45:07.429538 [DATLAT]
5473 00:45:07.432235 Freq=933, CH1 RK0
5474 00:45:07.432781
5475 00:45:07.435437 DATLAT Default: 0xd
5476 00:45:07.435867 0, 0xFFFF, sum = 0
5477 00:45:07.438617 1, 0xFFFF, sum = 0
5478 00:45:07.439056 2, 0xFFFF, sum = 0
5479 00:45:07.442101 3, 0xFFFF, sum = 0
5480 00:45:07.442681 4, 0xFFFF, sum = 0
5481 00:45:07.445638 5, 0xFFFF, sum = 0
5482 00:45:07.446151 6, 0xFFFF, sum = 0
5483 00:45:07.448542 7, 0xFFFF, sum = 0
5484 00:45:07.448978 8, 0xFFFF, sum = 0
5485 00:45:07.452051 9, 0xFFFF, sum = 0
5486 00:45:07.452486 10, 0x0, sum = 1
5487 00:45:07.455350 11, 0x0, sum = 2
5488 00:45:07.455789 12, 0x0, sum = 3
5489 00:45:07.459091 13, 0x0, sum = 4
5490 00:45:07.459604 best_step = 11
5491 00:45:07.459941
5492 00:45:07.460245 ==
5493 00:45:07.461998 Dram Type= 6, Freq= 0, CH_1, rank 0
5494 00:45:07.465280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5495 00:45:07.465714 ==
5496 00:45:07.468657 RX Vref Scan: 1
5497 00:45:07.469090
5498 00:45:07.472082 RX Vref 0 -> 0, step: 1
5499 00:45:07.472608
5500 00:45:07.473042 RX Delay -69 -> 252, step: 4
5501 00:45:07.475546
5502 00:45:07.475975 Set Vref, RX VrefLevel [Byte0]: 54
5503 00:45:07.478361 [Byte1]: 50
5504 00:45:07.483440
5505 00:45:07.483874 Final RX Vref Byte 0 = 54 to rank0
5506 00:45:07.486600 Final RX Vref Byte 1 = 50 to rank0
5507 00:45:07.490029 Final RX Vref Byte 0 = 54 to rank1
5508 00:45:07.493289 Final RX Vref Byte 1 = 50 to rank1==
5509 00:45:07.496729 Dram Type= 6, Freq= 0, CH_1, rank 0
5510 00:45:07.503628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5511 00:45:07.504103 ==
5512 00:45:07.504412 DQS Delay:
5513 00:45:07.504693 DQS0 = 0, DQS1 = 0
5514 00:45:07.506573 DQM Delay:
5515 00:45:07.506960 DQM0 = 93, DQM1 = 87
5516 00:45:07.510091 DQ Delay:
5517 00:45:07.513672 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =90
5518 00:45:07.516614 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5519 00:45:07.519989 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5520 00:45:07.523446 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5521 00:45:07.523914
5522 00:45:07.524220
5523 00:45:07.529905 [DQSOSCAuto] RK0, (LSB)MR18= 0x3737, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5524 00:45:07.533645 CH1 RK0: MR19=505, MR18=3737
5525 00:45:07.540155 CH1_RK0: MR19=0x505, MR18=0x3737, DQSOSC=404, MR23=63, INC=66, DEC=44
5526 00:45:07.540667
5527 00:45:07.543130 ----->DramcWriteLeveling(PI) begin...
5528 00:45:07.543612 ==
5529 00:45:07.546692 Dram Type= 6, Freq= 0, CH_1, rank 1
5530 00:45:07.549824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5531 00:45:07.550313 ==
5532 00:45:07.553083 Write leveling (Byte 0): 26 => 26
5533 00:45:07.556584 Write leveling (Byte 1): 26 => 26
5534 00:45:07.559651 DramcWriteLeveling(PI) end<-----
5535 00:45:07.560084
5536 00:45:07.560408 ==
5537 00:45:07.562816 Dram Type= 6, Freq= 0, CH_1, rank 1
5538 00:45:07.566561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5539 00:45:07.567113 ==
5540 00:45:07.569665 [Gating] SW mode calibration
5541 00:45:07.576434 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5542 00:45:07.582906 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5543 00:45:07.586315 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 00:45:07.593335 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5545 00:45:07.596344 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5546 00:45:07.600024 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 00:45:07.606093 0 10 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
5548 00:45:07.609814 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5549 00:45:07.613010 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 00:45:07.619684 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 00:45:07.622642 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 00:45:07.626040 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 00:45:07.629416 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 00:45:07.635906 0 11 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5555 00:45:07.639373 0 11 16 | B1->B0 | 2424 4141 | 0 0 | (0 0) (0 0)
5556 00:45:07.642849 0 11 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5557 00:45:07.649428 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 00:45:07.652646 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 00:45:07.656057 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 00:45:07.662529 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 00:45:07.666066 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 00:45:07.669176 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 00:45:07.675671 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5564 00:45:07.679116 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 00:45:07.682502 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 00:45:07.689039 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 00:45:07.692186 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 00:45:07.695779 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 00:45:07.702320 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 00:45:07.705994 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 00:45:07.708954 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 00:45:07.715532 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 00:45:07.718814 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 00:45:07.722555 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 00:45:07.729129 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 00:45:07.732283 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 00:45:07.735440 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 00:45:07.742195 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 00:45:07.745410 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5580 00:45:07.748747 Total UI for P1: 0, mck2ui 16
5581 00:45:07.752016 best dqsien dly found for B0: ( 0, 14, 14)
5582 00:45:07.755275 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5583 00:45:07.761736 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 00:45:07.762164 Total UI for P1: 0, mck2ui 16
5585 00:45:07.768593 best dqsien dly found for B1: ( 0, 14, 18)
5586 00:45:07.771813 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5587 00:45:07.775184 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5588 00:45:07.775611
5589 00:45:07.778555 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5590 00:45:07.782060 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5591 00:45:07.785491 [Gating] SW calibration Done
5592 00:45:07.785918 ==
5593 00:45:07.788613 Dram Type= 6, Freq= 0, CH_1, rank 1
5594 00:45:07.791916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5595 00:45:07.792312 ==
5596 00:45:07.795795 RX Vref Scan: 0
5597 00:45:07.796276
5598 00:45:07.796620 RX Vref 0 -> 0, step: 1
5599 00:45:07.796926
5600 00:45:07.798598 RX Delay -80 -> 252, step: 8
5601 00:45:07.802299 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5602 00:45:07.808774 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5603 00:45:07.812768 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5604 00:45:07.815177 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5605 00:45:07.818459 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5606 00:45:07.822149 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5607 00:45:07.825266 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5608 00:45:07.828960 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5609 00:45:07.835244 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5610 00:45:07.838870 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5611 00:45:07.842016 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5612 00:45:07.845314 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5613 00:45:07.848626 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5614 00:45:07.855226 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5615 00:45:07.858907 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5616 00:45:07.862236 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5617 00:45:07.862757 ==
5618 00:45:07.865361 Dram Type= 6, Freq= 0, CH_1, rank 1
5619 00:45:07.868815 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5620 00:45:07.869334 ==
5621 00:45:07.871636 DQS Delay:
5622 00:45:07.872065 DQS0 = 0, DQS1 = 0
5623 00:45:07.874927 DQM Delay:
5624 00:45:07.875354 DQM0 = 96, DQM1 = 87
5625 00:45:07.875690 DQ Delay:
5626 00:45:07.878058 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5627 00:45:07.881466 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5628 00:45:07.884695 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5629 00:45:07.888158 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5630 00:45:07.888595
5631 00:45:07.888928
5632 00:45:07.891558 ==
5633 00:45:07.894863 Dram Type= 6, Freq= 0, CH_1, rank 1
5634 00:45:07.898045 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5635 00:45:07.898628 ==
5636 00:45:07.899292
5637 00:45:07.899855
5638 00:45:07.901199 TX Vref Scan disable
5639 00:45:07.901630 == TX Byte 0 ==
5640 00:45:07.904649 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5641 00:45:07.911434 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5642 00:45:07.911907 == TX Byte 1 ==
5643 00:45:07.917822 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5644 00:45:07.921157 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5645 00:45:07.921821 ==
5646 00:45:07.924351 Dram Type= 6, Freq= 0, CH_1, rank 1
5647 00:45:07.927692 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5648 00:45:07.928228 ==
5649 00:45:07.928578
5650 00:45:07.928887
5651 00:45:07.931023 TX Vref Scan disable
5652 00:45:07.934696 == TX Byte 0 ==
5653 00:45:07.937754 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5654 00:45:07.940866 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5655 00:45:07.944379 == TX Byte 1 ==
5656 00:45:07.947784 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5657 00:45:07.950817 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5658 00:45:07.951522
5659 00:45:07.954166 [DATLAT]
5660 00:45:07.954852 Freq=933, CH1 RK1
5661 00:45:07.955468
5662 00:45:07.957744 DATLAT Default: 0xb
5663 00:45:07.958418 0, 0xFFFF, sum = 0
5664 00:45:07.960970 1, 0xFFFF, sum = 0
5665 00:45:07.961634 2, 0xFFFF, sum = 0
5666 00:45:07.964078 3, 0xFFFF, sum = 0
5667 00:45:07.964740 4, 0xFFFF, sum = 0
5668 00:45:07.967037 5, 0xFFFF, sum = 0
5669 00:45:07.967503 6, 0xFFFF, sum = 0
5670 00:45:07.970461 7, 0xFFFF, sum = 0
5671 00:45:07.970675 8, 0xFFFF, sum = 0
5672 00:45:07.974036 9, 0xFFFF, sum = 0
5673 00:45:07.974355 10, 0x0, sum = 1
5674 00:45:07.977329 11, 0x0, sum = 2
5675 00:45:07.977545 12, 0x0, sum = 3
5676 00:45:07.980524 13, 0x0, sum = 4
5677 00:45:07.980737 best_step = 11
5678 00:45:07.980899
5679 00:45:07.981116 ==
5680 00:45:07.983848 Dram Type= 6, Freq= 0, CH_1, rank 1
5681 00:45:07.990378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5682 00:45:07.990590 ==
5683 00:45:07.990753 RX Vref Scan: 0
5684 00:45:07.990905
5685 00:45:07.993710 RX Vref 0 -> 0, step: 1
5686 00:45:07.993975
5687 00:45:07.996775 RX Delay -69 -> 252, step: 4
5688 00:45:08.000213 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5689 00:45:08.003375 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5690 00:45:08.010065 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5691 00:45:08.013762 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5692 00:45:08.016787 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5693 00:45:08.019950 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5694 00:45:08.023830 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5695 00:45:08.029915 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5696 00:45:08.033260 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5697 00:45:08.037367 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5698 00:45:08.040209 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5699 00:45:08.043350 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5700 00:45:08.046753 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5701 00:45:08.053828 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5702 00:45:08.056613 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5703 00:45:08.060014 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5704 00:45:08.060447 ==
5705 00:45:08.063136 Dram Type= 6, Freq= 0, CH_1, rank 1
5706 00:45:08.066872 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5707 00:45:08.067310 ==
5708 00:45:08.069883 DQS Delay:
5709 00:45:08.070343 DQS0 = 0, DQS1 = 0
5710 00:45:08.073450 DQM Delay:
5711 00:45:08.073960 DQM0 = 96, DQM1 = 87
5712 00:45:08.074447 DQ Delay:
5713 00:45:08.076451 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5714 00:45:08.080036 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5715 00:45:08.083096 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =80
5716 00:45:08.086868 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =96
5717 00:45:08.087307
5718 00:45:08.087910
5719 00:45:08.096455 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b2b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5720 00:45:08.099740 CH1 RK1: MR19=505, MR18=2B2B
5721 00:45:08.106085 CH1_RK1: MR19=0x505, MR18=0x2B2B, DQSOSC=408, MR23=63, INC=65, DEC=43
5722 00:45:08.106512 [RxdqsGatingPostProcess] freq 933
5723 00:45:08.112760 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5724 00:45:08.116077 Pre-setting of DQS Precalculation
5725 00:45:08.122833 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5726 00:45:08.129462 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5727 00:45:08.136046 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5728 00:45:08.136445
5729 00:45:08.136820
5730 00:45:08.139725 [Calibration Summary] 1866 Mbps
5731 00:45:08.140117 CH 0, Rank 0
5732 00:45:08.142830 SW Impedance : PASS
5733 00:45:08.146159 DUTY Scan : NO K
5734 00:45:08.146605 ZQ Calibration : PASS
5735 00:45:08.149361 Jitter Meter : NO K
5736 00:45:08.149754 CBT Training : PASS
5737 00:45:08.153142 Write leveling : PASS
5738 00:45:08.156231 RX DQS gating : PASS
5739 00:45:08.156722 RX DQ/DQS(RDDQC) : PASS
5740 00:45:08.159429 TX DQ/DQS : PASS
5741 00:45:08.162473 RX DATLAT : PASS
5742 00:45:08.162903 RX DQ/DQS(Engine): PASS
5743 00:45:08.165873 TX OE : NO K
5744 00:45:08.166337 All Pass.
5745 00:45:08.166651
5746 00:45:08.169234 CH 0, Rank 1
5747 00:45:08.169625 SW Impedance : PASS
5748 00:45:08.173024 DUTY Scan : NO K
5749 00:45:08.175958 ZQ Calibration : PASS
5750 00:45:08.176450 Jitter Meter : NO K
5751 00:45:08.178934 CBT Training : PASS
5752 00:45:08.182312 Write leveling : PASS
5753 00:45:08.182936 RX DQS gating : PASS
5754 00:45:08.185747 RX DQ/DQS(RDDQC) : PASS
5755 00:45:08.188915 TX DQ/DQS : PASS
5756 00:45:08.189310 RX DATLAT : PASS
5757 00:45:08.192229 RX DQ/DQS(Engine): PASS
5758 00:45:08.195467 TX OE : NO K
5759 00:45:08.195867 All Pass.
5760 00:45:08.196183
5761 00:45:08.196464 CH 1, Rank 0
5762 00:45:08.198757 SW Impedance : PASS
5763 00:45:08.202294 DUTY Scan : NO K
5764 00:45:08.202771 ZQ Calibration : PASS
5765 00:45:08.205414 Jitter Meter : NO K
5766 00:45:08.209034 CBT Training : PASS
5767 00:45:08.209511 Write leveling : PASS
5768 00:45:08.212105 RX DQS gating : PASS
5769 00:45:08.215514 RX DQ/DQS(RDDQC) : PASS
5770 00:45:08.215909 TX DQ/DQS : PASS
5771 00:45:08.218744 RX DATLAT : PASS
5772 00:45:08.219130 RX DQ/DQS(Engine): PASS
5773 00:45:08.222040 TX OE : NO K
5774 00:45:08.222549 All Pass.
5775 00:45:08.222850
5776 00:45:08.225557 CH 1, Rank 1
5777 00:45:08.226180 SW Impedance : PASS
5778 00:45:08.228813 DUTY Scan : NO K
5779 00:45:08.232106 ZQ Calibration : PASS
5780 00:45:08.232493 Jitter Meter : NO K
5781 00:45:08.235111 CBT Training : PASS
5782 00:45:08.238517 Write leveling : PASS
5783 00:45:08.238949 RX DQS gating : PASS
5784 00:45:08.241926 RX DQ/DQS(RDDQC) : PASS
5785 00:45:08.245377 TX DQ/DQS : PASS
5786 00:45:08.245890 RX DATLAT : PASS
5787 00:45:08.248582 RX DQ/DQS(Engine): PASS
5788 00:45:08.252180 TX OE : NO K
5789 00:45:08.252736 All Pass.
5790 00:45:08.253076
5791 00:45:08.255073 DramC Write-DBI off
5792 00:45:08.255511 PER_BANK_REFRESH: Hybrid Mode
5793 00:45:08.258493 TX_TRACKING: ON
5794 00:45:08.265257 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5795 00:45:08.271805 [FAST_K] Save calibration result to emmc
5796 00:45:08.275012 dramc_set_vcore_voltage set vcore to 650000
5797 00:45:08.275458 Read voltage for 400, 6
5798 00:45:08.278292 Vio18 = 0
5799 00:45:08.278740 Vcore = 650000
5800 00:45:08.279077 Vdram = 0
5801 00:45:08.281689 Vddq = 0
5802 00:45:08.282134 Vmddr = 0
5803 00:45:08.285314 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5804 00:45:08.291455 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5805 00:45:08.295083 MEM_TYPE=3, freq_sel=20
5806 00:45:08.298257 sv_algorithm_assistance_LP4_800
5807 00:45:08.301486 ============ PULL DRAM RESETB DOWN ============
5808 00:45:08.304964 ========== PULL DRAM RESETB DOWN end =========
5809 00:45:08.308504 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5810 00:45:08.311473 ===================================
5811 00:45:08.314810 LPDDR4 DRAM CONFIGURATION
5812 00:45:08.318368 ===================================
5813 00:45:08.321696 EX_ROW_EN[0] = 0x0
5814 00:45:08.322162 EX_ROW_EN[1] = 0x0
5815 00:45:08.325187 LP4Y_EN = 0x0
5816 00:45:08.325716 WORK_FSP = 0x0
5817 00:45:08.328064 WL = 0x2
5818 00:45:08.328503 RL = 0x2
5819 00:45:08.331360 BL = 0x2
5820 00:45:08.331792 RPST = 0x0
5821 00:45:08.334693 RD_PRE = 0x0
5822 00:45:08.338292 WR_PRE = 0x1
5823 00:45:08.338700 WR_PST = 0x0
5824 00:45:08.341431 DBI_WR = 0x0
5825 00:45:08.341926 DBI_RD = 0x0
5826 00:45:08.345004 OTF = 0x1
5827 00:45:08.348372 ===================================
5828 00:45:08.351604 ===================================
5829 00:45:08.352094 ANA top config
5830 00:45:08.354756 ===================================
5831 00:45:08.358076 DLL_ASYNC_EN = 0
5832 00:45:08.358576 ALL_SLAVE_EN = 1
5833 00:45:08.361604 NEW_RANK_MODE = 1
5834 00:45:08.365199 DLL_IDLE_MODE = 1
5835 00:45:08.367877 LP45_APHY_COMB_EN = 1
5836 00:45:08.371671 TX_ODT_DIS = 1
5837 00:45:08.372166 NEW_8X_MODE = 1
5838 00:45:08.374805 ===================================
5839 00:45:08.377940 ===================================
5840 00:45:08.381296 data_rate = 800
5841 00:45:08.384782 CKR = 1
5842 00:45:08.388058 DQ_P2S_RATIO = 4
5843 00:45:08.391204 ===================================
5844 00:45:08.394469 CA_P2S_RATIO = 4
5845 00:45:08.397995 DQ_CA_OPEN = 0
5846 00:45:08.398427 DQ_SEMI_OPEN = 1
5847 00:45:08.401238 CA_SEMI_OPEN = 1
5848 00:45:08.404745 CA_FULL_RATE = 0
5849 00:45:08.408074 DQ_CKDIV4_EN = 0
5850 00:45:08.411066 CA_CKDIV4_EN = 1
5851 00:45:08.414523 CA_PREDIV_EN = 0
5852 00:45:08.414910 PH8_DLY = 0
5853 00:45:08.418282 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5854 00:45:08.421360 DQ_AAMCK_DIV = 0
5855 00:45:08.424657 CA_AAMCK_DIV = 0
5856 00:45:08.427885 CA_ADMCK_DIV = 4
5857 00:45:08.431042 DQ_TRACK_CA_EN = 0
5858 00:45:08.431534 CA_PICK = 800
5859 00:45:08.434613 CA_MCKIO = 400
5860 00:45:08.437649 MCKIO_SEMI = 400
5861 00:45:08.441232 PLL_FREQ = 3016
5862 00:45:08.444738 DQ_UI_PI_RATIO = 32
5863 00:45:08.447604 CA_UI_PI_RATIO = 32
5864 00:45:08.451050 ===================================
5865 00:45:08.454671 ===================================
5866 00:45:08.457428 memory_type:LPDDR4
5867 00:45:08.457856 GP_NUM : 10
5868 00:45:08.461166 SRAM_EN : 1
5869 00:45:08.461830 MD32_EN : 0
5870 00:45:08.464460 ===================================
5871 00:45:08.467753 [ANA_INIT] >>>>>>>>>>>>>>
5872 00:45:08.471184 <<<<<< [CONFIGURE PHASE]: ANA_TX
5873 00:45:08.474320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5874 00:45:08.477704 ===================================
5875 00:45:08.480831 data_rate = 800,PCW = 0X7400
5876 00:45:08.484032 ===================================
5877 00:45:08.487536 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5878 00:45:08.490822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5879 00:45:08.504000 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5880 00:45:08.507148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5881 00:45:08.510562 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5882 00:45:08.514031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5883 00:45:08.517133 [ANA_INIT] flow start
5884 00:45:08.520340 [ANA_INIT] PLL >>>>>>>>
5885 00:45:08.520776 [ANA_INIT] PLL <<<<<<<<
5886 00:45:08.523880 [ANA_INIT] MIDPI >>>>>>>>
5887 00:45:08.527467 [ANA_INIT] MIDPI <<<<<<<<
5888 00:45:08.530538 [ANA_INIT] DLL >>>>>>>>
5889 00:45:08.531067 [ANA_INIT] flow end
5890 00:45:08.533885 ============ LP4 DIFF to SE enter ============
5891 00:45:08.540106 ============ LP4 DIFF to SE exit ============
5892 00:45:08.540630 [ANA_INIT] <<<<<<<<<<<<<
5893 00:45:08.543637 [Flow] Enable top DCM control >>>>>
5894 00:45:08.546992 [Flow] Enable top DCM control <<<<<
5895 00:45:08.550635 Enable DLL master slave shuffle
5896 00:45:08.556928 ==============================================================
5897 00:45:08.557448 Gating Mode config
5898 00:45:08.563826 ==============================================================
5899 00:45:08.567081 Config description:
5900 00:45:08.576887 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5901 00:45:08.583618 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5902 00:45:08.586866 SELPH_MODE 0: By rank 1: By Phase
5903 00:45:08.593430 ==============================================================
5904 00:45:08.596565 GAT_TRACK_EN = 0
5905 00:45:08.597068 RX_GATING_MODE = 2
5906 00:45:08.600139 RX_GATING_TRACK_MODE = 2
5907 00:45:08.603529 SELPH_MODE = 1
5908 00:45:08.606757 PICG_EARLY_EN = 1
5909 00:45:08.610011 VALID_LAT_VALUE = 1
5910 00:45:08.616805 ==============================================================
5911 00:45:08.620026 Enter into Gating configuration >>>>
5912 00:45:08.623659 Exit from Gating configuration <<<<
5913 00:45:08.626754 Enter into DVFS_PRE_config >>>>>
5914 00:45:08.636512 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5915 00:45:08.639777 Exit from DVFS_PRE_config <<<<<
5916 00:45:08.642797 Enter into PICG configuration >>>>
5917 00:45:08.646209 Exit from PICG configuration <<<<
5918 00:45:08.649537 [RX_INPUT] configuration >>>>>
5919 00:45:08.652867 [RX_INPUT] configuration <<<<<
5920 00:45:08.656394 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5921 00:45:08.662584 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5922 00:45:08.669606 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5923 00:45:08.675997 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5924 00:45:08.679239 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5925 00:45:08.685783 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5926 00:45:08.689044 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5927 00:45:08.695673 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5928 00:45:08.699041 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5929 00:45:08.702530 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5930 00:45:08.706078 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5931 00:45:08.712549 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5932 00:45:08.715895 ===================================
5933 00:45:08.719243 LPDDR4 DRAM CONFIGURATION
5934 00:45:08.719758 ===================================
5935 00:45:08.722811 EX_ROW_EN[0] = 0x0
5936 00:45:08.725850 EX_ROW_EN[1] = 0x0
5937 00:45:08.726410 LP4Y_EN = 0x0
5938 00:45:08.729032 WORK_FSP = 0x0
5939 00:45:08.729464 WL = 0x2
5940 00:45:08.732374 RL = 0x2
5941 00:45:08.732813 BL = 0x2
5942 00:45:08.735569 RPST = 0x0
5943 00:45:08.736003 RD_PRE = 0x0
5944 00:45:08.739060 WR_PRE = 0x1
5945 00:45:08.739625 WR_PST = 0x0
5946 00:45:08.742429 DBI_WR = 0x0
5947 00:45:08.742864 DBI_RD = 0x0
5948 00:45:08.745714 OTF = 0x1
5949 00:45:08.749021 ===================================
5950 00:45:08.752398 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5951 00:45:08.755619 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5952 00:45:08.761877 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5953 00:45:08.765654 ===================================
5954 00:45:08.766169 LPDDR4 DRAM CONFIGURATION
5955 00:45:08.768586 ===================================
5956 00:45:08.772067 EX_ROW_EN[0] = 0x10
5957 00:45:08.775565 EX_ROW_EN[1] = 0x0
5958 00:45:08.776079 LP4Y_EN = 0x0
5959 00:45:08.778624 WORK_FSP = 0x0
5960 00:45:08.779058 WL = 0x2
5961 00:45:08.782169 RL = 0x2
5962 00:45:08.782677 BL = 0x2
5963 00:45:08.785133 RPST = 0x0
5964 00:45:08.785697 RD_PRE = 0x0
5965 00:45:08.788490 WR_PRE = 0x1
5966 00:45:08.788923 WR_PST = 0x0
5967 00:45:08.791849 DBI_WR = 0x0
5968 00:45:08.792278 DBI_RD = 0x0
5969 00:45:08.795152 OTF = 0x1
5970 00:45:08.798704 ===================================
5971 00:45:08.805236 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5972 00:45:08.808309 nWR fixed to 30
5973 00:45:08.811941 [ModeRegInit_LP4] CH0 RK0
5974 00:45:08.812426 [ModeRegInit_LP4] CH0 RK1
5975 00:45:08.815232 [ModeRegInit_LP4] CH1 RK0
5976 00:45:08.818403 [ModeRegInit_LP4] CH1 RK1
5977 00:45:08.818869 match AC timing 18
5978 00:45:08.825016 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5979 00:45:08.828505 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5980 00:45:08.831592 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5981 00:45:08.838345 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5982 00:45:08.842004 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5983 00:45:08.842573 ==
5984 00:45:08.844858 Dram Type= 6, Freq= 0, CH_0, rank 0
5985 00:45:08.848643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5986 00:45:08.849135 ==
5987 00:45:08.854879 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5988 00:45:08.861351 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5989 00:45:08.864554 [CA 0] Center 36 (8~64) winsize 57
5990 00:45:08.868503 [CA 1] Center 36 (8~64) winsize 57
5991 00:45:08.871489 [CA 2] Center 36 (8~64) winsize 57
5992 00:45:08.871969 [CA 3] Center 36 (8~64) winsize 57
5993 00:45:08.874846 [CA 4] Center 36 (8~64) winsize 57
5994 00:45:08.878480 [CA 5] Center 36 (8~64) winsize 57
5995 00:45:08.878993
5996 00:45:08.884640 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5997 00:45:08.885086
5998 00:45:08.887889 [CATrainingPosCal] consider 1 rank data
5999 00:45:08.891208 u2DelayCellTimex100 = 270/100 ps
6000 00:45:08.894368 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6001 00:45:08.897869 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6002 00:45:08.901099 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6003 00:45:08.904343 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6004 00:45:08.907697 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6005 00:45:08.911190 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6006 00:45:08.911582
6007 00:45:08.914390 CA PerBit enable=1, Macro0, CA PI delay=36
6008 00:45:08.914779
6009 00:45:08.917700 [CBTSetCACLKResult] CA Dly = 36
6010 00:45:08.921455 CS Dly: 1 (0~32)
6011 00:45:08.921940 ==
6012 00:45:08.924697 Dram Type= 6, Freq= 0, CH_0, rank 1
6013 00:45:08.927519 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6014 00:45:08.927957 ==
6015 00:45:08.934398 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6016 00:45:08.937581 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6017 00:45:08.941011 [CA 0] Center 36 (8~64) winsize 57
6018 00:45:08.944662 [CA 1] Center 36 (8~64) winsize 57
6019 00:45:08.947734 [CA 2] Center 36 (8~64) winsize 57
6020 00:45:08.951132 [CA 3] Center 36 (8~64) winsize 57
6021 00:45:08.954246 [CA 4] Center 36 (8~64) winsize 57
6022 00:45:08.957610 [CA 5] Center 36 (8~64) winsize 57
6023 00:45:08.958138
6024 00:45:08.960913 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6025 00:45:08.961428
6026 00:45:08.964248 [CATrainingPosCal] consider 2 rank data
6027 00:45:08.967661 u2DelayCellTimex100 = 270/100 ps
6028 00:45:08.970660 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6029 00:45:08.974016 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6030 00:45:08.980877 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6031 00:45:08.984039 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6032 00:45:08.987090 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6033 00:45:08.990686 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6034 00:45:08.991119
6035 00:45:08.993830 CA PerBit enable=1, Macro0, CA PI delay=36
6036 00:45:08.994310
6037 00:45:08.997179 [CBTSetCACLKResult] CA Dly = 36
6038 00:45:08.997610 CS Dly: 1 (0~32)
6039 00:45:08.997942
6040 00:45:09.000649 ----->DramcWriteLeveling(PI) begin...
6041 00:45:09.004005 ==
6042 00:45:09.004437 Dram Type= 6, Freq= 0, CH_0, rank 0
6043 00:45:09.010794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6044 00:45:09.011307 ==
6045 00:45:09.014095 Write leveling (Byte 0): 32 => 0
6046 00:45:09.017374 Write leveling (Byte 1): 32 => 0
6047 00:45:09.020646 DramcWriteLeveling(PI) end<-----
6048 00:45:09.021158
6049 00:45:09.021499 ==
6050 00:45:09.023739 Dram Type= 6, Freq= 0, CH_0, rank 0
6051 00:45:09.026936 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6052 00:45:09.027512 ==
6053 00:45:09.030294 [Gating] SW mode calibration
6054 00:45:09.036942 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6055 00:45:09.040351 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6056 00:45:09.047184 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6057 00:45:09.050684 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6058 00:45:09.053706 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6059 00:45:09.060643 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6060 00:45:09.063510 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6061 00:45:09.067199 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6062 00:45:09.073652 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6063 00:45:09.076998 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6064 00:45:09.080036 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6065 00:45:09.083440 Total UI for P1: 0, mck2ui 16
6066 00:45:09.086575 best dqsien dly found for B0: ( 0, 10, 16)
6067 00:45:09.090187 Total UI for P1: 0, mck2ui 16
6068 00:45:09.093349 best dqsien dly found for B1: ( 0, 10, 24)
6069 00:45:09.097189 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6070 00:45:09.103292 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6071 00:45:09.103735
6072 00:45:09.106480 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6073 00:45:09.109895 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6074 00:45:09.113354 [Gating] SW calibration Done
6075 00:45:09.113873 ==
6076 00:45:09.116319 Dram Type= 6, Freq= 0, CH_0, rank 0
6077 00:45:09.120135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6078 00:45:09.120679 ==
6079 00:45:09.122986 RX Vref Scan: 0
6080 00:45:09.123421
6081 00:45:09.123771 RX Vref 0 -> 0, step: 1
6082 00:45:09.124084
6083 00:45:09.126652 RX Delay -410 -> 252, step: 16
6084 00:45:09.129919 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6085 00:45:09.136527 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6086 00:45:09.139436 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6087 00:45:09.142901 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6088 00:45:09.149591 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6089 00:45:09.152948 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6090 00:45:09.155890 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6091 00:45:09.159325 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6092 00:45:09.166079 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6093 00:45:09.169457 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6094 00:45:09.172570 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6095 00:45:09.176450 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6096 00:45:09.182532 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6097 00:45:09.185881 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6098 00:45:09.189245 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6099 00:45:09.192454 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6100 00:45:09.192892 ==
6101 00:45:09.195804 Dram Type= 6, Freq= 0, CH_0, rank 0
6102 00:45:09.202512 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6103 00:45:09.202952 ==
6104 00:45:09.203287 DQS Delay:
6105 00:45:09.205623 DQS0 = 51, DQS1 = 59
6106 00:45:09.206055 DQM Delay:
6107 00:45:09.208800 DQM0 = 12, DQM1 = 12
6108 00:45:09.209208 DQ Delay:
6109 00:45:09.212163 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6110 00:45:09.215679 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6111 00:45:09.218917 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6112 00:45:09.222117 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6113 00:45:09.222547
6114 00:45:09.222851
6115 00:45:09.223127 ==
6116 00:45:09.225466 Dram Type= 6, Freq= 0, CH_0, rank 0
6117 00:45:09.228981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6118 00:45:09.229378 ==
6119 00:45:09.229726
6120 00:45:09.230108
6121 00:45:09.232069 TX Vref Scan disable
6122 00:45:09.232458 == TX Byte 0 ==
6123 00:45:09.238736 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6124 00:45:09.241960 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6125 00:45:09.242385 == TX Byte 1 ==
6126 00:45:09.248648 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6127 00:45:09.252094 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6128 00:45:09.252486 ==
6129 00:45:09.255225 Dram Type= 6, Freq= 0, CH_0, rank 0
6130 00:45:09.258736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6131 00:45:09.259216 ==
6132 00:45:09.259523
6133 00:45:09.259809
6134 00:45:09.261895 TX Vref Scan disable
6135 00:45:09.265249 == TX Byte 0 ==
6136 00:45:09.268387 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6137 00:45:09.271705 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6138 00:45:09.274852 == TX Byte 1 ==
6139 00:45:09.278089 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6140 00:45:09.281568 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6141 00:45:09.282013
6142 00:45:09.282379 [DATLAT]
6143 00:45:09.284958 Freq=400, CH0 RK0
6144 00:45:09.285350
6145 00:45:09.288039 DATLAT Default: 0xf
6146 00:45:09.288547 0, 0xFFFF, sum = 0
6147 00:45:09.291632 1, 0xFFFF, sum = 0
6148 00:45:09.292030 2, 0xFFFF, sum = 0
6149 00:45:09.294785 3, 0xFFFF, sum = 0
6150 00:45:09.295170 4, 0xFFFF, sum = 0
6151 00:45:09.298290 5, 0xFFFF, sum = 0
6152 00:45:09.298695 6, 0xFFFF, sum = 0
6153 00:45:09.301319 7, 0xFFFF, sum = 0
6154 00:45:09.301720 8, 0xFFFF, sum = 0
6155 00:45:09.304646 9, 0xFFFF, sum = 0
6156 00:45:09.305045 10, 0xFFFF, sum = 0
6157 00:45:09.307943 11, 0xFFFF, sum = 0
6158 00:45:09.308342 12, 0x0, sum = 1
6159 00:45:09.311618 13, 0x0, sum = 2
6160 00:45:09.312110 14, 0x0, sum = 3
6161 00:45:09.315069 15, 0x0, sum = 4
6162 00:45:09.315469 best_step = 13
6163 00:45:09.315771
6164 00:45:09.316052 ==
6165 00:45:09.317993 Dram Type= 6, Freq= 0, CH_0, rank 0
6166 00:45:09.324464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6167 00:45:09.324867 ==
6168 00:45:09.325170 RX Vref Scan: 1
6169 00:45:09.325451
6170 00:45:09.327919 RX Vref 0 -> 0, step: 1
6171 00:45:09.328313
6172 00:45:09.330895 RX Delay -359 -> 252, step: 8
6173 00:45:09.331465
6174 00:45:09.334394 Set Vref, RX VrefLevel [Byte0]: 48
6175 00:45:09.337639 [Byte1]: 48
6176 00:45:09.338032
6177 00:45:09.340867 Final RX Vref Byte 0 = 48 to rank0
6178 00:45:09.344288 Final RX Vref Byte 1 = 48 to rank0
6179 00:45:09.347689 Final RX Vref Byte 0 = 48 to rank1
6180 00:45:09.350999 Final RX Vref Byte 1 = 48 to rank1==
6181 00:45:09.354790 Dram Type= 6, Freq= 0, CH_0, rank 0
6182 00:45:09.357938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6183 00:45:09.361111 ==
6184 00:45:09.361575 DQS Delay:
6185 00:45:09.361878 DQS0 = 52, DQS1 = 68
6186 00:45:09.364094 DQM Delay:
6187 00:45:09.364547 DQM0 = 9, DQM1 = 17
6188 00:45:09.367773 DQ Delay:
6189 00:45:09.368248 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6190 00:45:09.370818 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6191 00:45:09.374432 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6192 00:45:09.377265 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6193 00:45:09.377658
6194 00:45:09.377957
6195 00:45:09.387402 [DQSOSCAuto] RK0, (LSB)MR18= 0xa6a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6196 00:45:09.390552 CH0 RK0: MR19=C0C, MR18=A6A6
6197 00:45:09.394077 CH0_RK0: MR19=0xC0C, MR18=0xA6A6, DQSOSC=389, MR23=63, INC=390, DEC=260
6198 00:45:09.397196 ==
6199 00:45:09.400818 Dram Type= 6, Freq= 0, CH_0, rank 1
6200 00:45:09.403845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6201 00:45:09.404284 ==
6202 00:45:09.407421 [Gating] SW mode calibration
6203 00:45:09.414082 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6204 00:45:09.417284 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6205 00:45:09.423996 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6206 00:45:09.427391 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6207 00:45:09.430754 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6208 00:45:09.437253 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6209 00:45:09.440441 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6210 00:45:09.443632 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6211 00:45:09.450313 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6212 00:45:09.453508 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6213 00:45:09.457151 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6214 00:45:09.460266 Total UI for P1: 0, mck2ui 16
6215 00:45:09.463213 best dqsien dly found for B0: ( 0, 10, 16)
6216 00:45:09.466698 Total UI for P1: 0, mck2ui 16
6217 00:45:09.470358 best dqsien dly found for B1: ( 0, 10, 16)
6218 00:45:09.473385 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6219 00:45:09.476792 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6220 00:45:09.477299
6221 00:45:09.483311 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6222 00:45:09.486656 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6223 00:45:09.490029 [Gating] SW calibration Done
6224 00:45:09.490511 ==
6225 00:45:09.493513 Dram Type= 6, Freq= 0, CH_0, rank 1
6226 00:45:09.496188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6227 00:45:09.496627 ==
6228 00:45:09.499636 RX Vref Scan: 0
6229 00:45:09.500069
6230 00:45:09.500400 RX Vref 0 -> 0, step: 1
6231 00:45:09.500715
6232 00:45:09.502979 RX Delay -410 -> 252, step: 16
6233 00:45:09.506239 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6234 00:45:09.512861 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6235 00:45:09.516280 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6236 00:45:09.519975 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6237 00:45:09.522910 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6238 00:45:09.529318 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528
6239 00:45:09.533108 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6240 00:45:09.536180 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6241 00:45:09.539263 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6242 00:45:09.546366 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6243 00:45:09.549240 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6244 00:45:09.552892 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6245 00:45:09.559416 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6246 00:45:09.562593 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6247 00:45:09.566041 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6248 00:45:09.569144 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6249 00:45:09.572308 ==
6250 00:45:09.572701 Dram Type= 6, Freq= 0, CH_0, rank 1
6251 00:45:09.578981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6252 00:45:09.579418 ==
6253 00:45:09.579816 DQS Delay:
6254 00:45:09.582382 DQS0 = 51, DQS1 = 59
6255 00:45:09.582816 DQM Delay:
6256 00:45:09.585598 DQM0 = 13, DQM1 = 14
6257 00:45:09.586074 DQ Delay:
6258 00:45:09.588903 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6259 00:45:09.592159 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6260 00:45:09.595577 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6261 00:45:09.598780 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6262 00:45:09.599210
6263 00:45:09.599538
6264 00:45:09.599858 ==
6265 00:45:09.602274 Dram Type= 6, Freq= 0, CH_0, rank 1
6266 00:45:09.605785 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6267 00:45:09.606320 ==
6268 00:45:09.606684
6269 00:45:09.606993
6270 00:45:09.608815 TX Vref Scan disable
6271 00:45:09.609202 == TX Byte 0 ==
6272 00:45:09.615466 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6273 00:45:09.618800 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6274 00:45:09.619189 == TX Byte 1 ==
6275 00:45:09.622309 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6276 00:45:09.628942 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6277 00:45:09.629455 ==
6278 00:45:09.631942 Dram Type= 6, Freq= 0, CH_0, rank 1
6279 00:45:09.635222 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6280 00:45:09.635736 ==
6281 00:45:09.636083
6282 00:45:09.636389
6283 00:45:09.639003 TX Vref Scan disable
6284 00:45:09.639536 == TX Byte 0 ==
6285 00:45:09.645427 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6286 00:45:09.648729 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6287 00:45:09.649257 == TX Byte 1 ==
6288 00:45:09.655113 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6289 00:45:09.658695 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6290 00:45:09.659218
6291 00:45:09.659657 [DATLAT]
6292 00:45:09.661899 Freq=400, CH0 RK1
6293 00:45:09.662460
6294 00:45:09.662803 DATLAT Default: 0xd
6295 00:45:09.664890 0, 0xFFFF, sum = 0
6296 00:45:09.665321 1, 0xFFFF, sum = 0
6297 00:45:09.668182 2, 0xFFFF, sum = 0
6298 00:45:09.668614 3, 0xFFFF, sum = 0
6299 00:45:09.671590 4, 0xFFFF, sum = 0
6300 00:45:09.672022 5, 0xFFFF, sum = 0
6301 00:45:09.674708 6, 0xFFFF, sum = 0
6302 00:45:09.675173 7, 0xFFFF, sum = 0
6303 00:45:09.678130 8, 0xFFFF, sum = 0
6304 00:45:09.678569 9, 0xFFFF, sum = 0
6305 00:45:09.681566 10, 0xFFFF, sum = 0
6306 00:45:09.684720 11, 0xFFFF, sum = 0
6307 00:45:09.685126 12, 0x0, sum = 1
6308 00:45:09.685443 13, 0x0, sum = 2
6309 00:45:09.688080 14, 0x0, sum = 3
6310 00:45:09.688469 15, 0x0, sum = 4
6311 00:45:09.691739 best_step = 13
6312 00:45:09.692123
6313 00:45:09.692417 ==
6314 00:45:09.694620 Dram Type= 6, Freq= 0, CH_0, rank 1
6315 00:45:09.698021 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6316 00:45:09.698493 ==
6317 00:45:09.701196 RX Vref Scan: 0
6318 00:45:09.701579
6319 00:45:09.701873 RX Vref 0 -> 0, step: 1
6320 00:45:09.704728
6321 00:45:09.705270 RX Delay -359 -> 252, step: 8
6322 00:45:09.713232 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6323 00:45:09.716503 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6324 00:45:09.719537 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6325 00:45:09.726310 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6326 00:45:09.729523 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6327 00:45:09.733049 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6328 00:45:09.736683 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6329 00:45:09.739817 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6330 00:45:09.746570 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6331 00:45:09.749736 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6332 00:45:09.753017 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6333 00:45:09.759477 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6334 00:45:09.762906 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6335 00:45:09.766258 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6336 00:45:09.769304 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6337 00:45:09.776157 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6338 00:45:09.776594 ==
6339 00:45:09.779686 Dram Type= 6, Freq= 0, CH_0, rank 1
6340 00:45:09.782728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6341 00:45:09.783196 ==
6342 00:45:09.783534 DQS Delay:
6343 00:45:09.786032 DQS0 = 52, DQS1 = 60
6344 00:45:09.786530 DQM Delay:
6345 00:45:09.789726 DQM0 = 10, DQM1 = 9
6346 00:45:09.790408 DQ Delay:
6347 00:45:09.793374 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6348 00:45:09.796007 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6349 00:45:09.799850 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6350 00:45:09.802816 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6351 00:45:09.803244
6352 00:45:09.803572
6353 00:45:09.809613 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1d1, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6354 00:45:09.813073 CH0 RK1: MR19=C0C, MR18=D1D1
6355 00:45:09.819583 CH0_RK1: MR19=0xC0C, MR18=0xD1D1, DQSOSC=384, MR23=63, INC=400, DEC=267
6356 00:45:09.822600 [RxdqsGatingPostProcess] freq 400
6357 00:45:09.829212 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6358 00:45:09.829706 Pre-setting of DQS Precalculation
6359 00:45:09.835968 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6360 00:45:09.836470 ==
6361 00:45:09.839127 Dram Type= 6, Freq= 0, CH_1, rank 0
6362 00:45:09.842583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6363 00:45:09.843025 ==
6364 00:45:09.849266 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6365 00:45:09.856257 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6366 00:45:09.859099 [CA 0] Center 36 (8~64) winsize 57
6367 00:45:09.862498 [CA 1] Center 36 (8~64) winsize 57
6368 00:45:09.865765 [CA 2] Center 36 (8~64) winsize 57
6369 00:45:09.869322 [CA 3] Center 36 (8~64) winsize 57
6370 00:45:09.869886 [CA 4] Center 36 (8~64) winsize 57
6371 00:45:09.872507 [CA 5] Center 36 (8~64) winsize 57
6372 00:45:09.872939
6373 00:45:09.878828 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6374 00:45:09.879330
6375 00:45:09.882142 [CATrainingPosCal] consider 1 rank data
6376 00:45:09.885533 u2DelayCellTimex100 = 270/100 ps
6377 00:45:09.889020 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6378 00:45:09.892287 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6379 00:45:09.895405 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6380 00:45:09.898851 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6381 00:45:09.901946 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6382 00:45:09.905347 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6383 00:45:09.905807
6384 00:45:09.909009 CA PerBit enable=1, Macro0, CA PI delay=36
6385 00:45:09.909535
6386 00:45:09.912192 [CBTSetCACLKResult] CA Dly = 36
6387 00:45:09.915674 CS Dly: 1 (0~32)
6388 00:45:09.916184 ==
6389 00:45:09.918687 Dram Type= 6, Freq= 0, CH_1, rank 1
6390 00:45:09.921804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6391 00:45:09.922271 ==
6392 00:45:09.928824 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6393 00:45:09.935033 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6394 00:45:09.938294 [CA 0] Center 36 (8~64) winsize 57
6395 00:45:09.938733 [CA 1] Center 36 (8~64) winsize 57
6396 00:45:09.941640 [CA 2] Center 36 (8~64) winsize 57
6397 00:45:09.945192 [CA 3] Center 36 (8~64) winsize 57
6398 00:45:09.948409 [CA 4] Center 36 (8~64) winsize 57
6399 00:45:09.951871 [CA 5] Center 36 (8~64) winsize 57
6400 00:45:09.952394
6401 00:45:09.955087 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6402 00:45:09.955601
6403 00:45:09.958290 [CATrainingPosCal] consider 2 rank data
6404 00:45:09.961705 u2DelayCellTimex100 = 270/100 ps
6405 00:45:09.965349 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6406 00:45:09.968566 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6407 00:45:09.975378 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6408 00:45:09.978205 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6409 00:45:09.981768 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6410 00:45:09.985187 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6411 00:45:09.985623
6412 00:45:09.988738 CA PerBit enable=1, Macro0, CA PI delay=36
6413 00:45:09.989177
6414 00:45:09.991518 [CBTSetCACLKResult] CA Dly = 36
6415 00:45:09.992191 CS Dly: 1 (0~32)
6416 00:45:09.992602
6417 00:45:09.994990 ----->DramcWriteLeveling(PI) begin...
6418 00:45:09.998447 ==
6419 00:45:10.001744 Dram Type= 6, Freq= 0, CH_1, rank 0
6420 00:45:10.005014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6421 00:45:10.005528 ==
6422 00:45:10.008082 Write leveling (Byte 0): 32 => 0
6423 00:45:10.011357 Write leveling (Byte 1): 32 => 0
6424 00:45:10.014777 DramcWriteLeveling(PI) end<-----
6425 00:45:10.015278
6426 00:45:10.015614 ==
6427 00:45:10.017890 Dram Type= 6, Freq= 0, CH_1, rank 0
6428 00:45:10.021145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6429 00:45:10.021567 ==
6430 00:45:10.024689 [Gating] SW mode calibration
6431 00:45:10.031341 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6432 00:45:10.038289 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6433 00:45:10.041285 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 00:45:10.044720 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 00:45:10.051044 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 00:45:10.054417 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 00:45:10.057712 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 00:45:10.064248 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 00:45:10.067873 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 00:45:10.071157 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6441 00:45:10.074727 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 00:45:10.077684 Total UI for P1: 0, mck2ui 16
6443 00:45:10.080959 best dqsien dly found for B0: ( 0, 10, 16)
6444 00:45:10.084211 Total UI for P1: 0, mck2ui 16
6445 00:45:10.087453 best dqsien dly found for B1: ( 0, 10, 16)
6446 00:45:10.090861 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6447 00:45:10.097512 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6448 00:45:10.097904
6449 00:45:10.100829 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6450 00:45:10.104134 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6451 00:45:10.107338 [Gating] SW calibration Done
6452 00:45:10.107731 ==
6453 00:45:10.110484 Dram Type= 6, Freq= 0, CH_1, rank 0
6454 00:45:10.113887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6455 00:45:10.114418 ==
6456 00:45:10.117343 RX Vref Scan: 0
6457 00:45:10.117734
6458 00:45:10.118036 RX Vref 0 -> 0, step: 1
6459 00:45:10.118366
6460 00:45:10.120501 RX Delay -410 -> 252, step: 16
6461 00:45:10.127303 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6462 00:45:10.130523 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6463 00:45:10.134031 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6464 00:45:10.136952 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6465 00:45:10.143850 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6466 00:45:10.146834 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6467 00:45:10.150197 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6468 00:45:10.153797 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6469 00:45:10.160662 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6470 00:45:10.163474 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6471 00:45:10.166975 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6472 00:45:10.170298 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6473 00:45:10.176763 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6474 00:45:10.180268 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6475 00:45:10.183484 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6476 00:45:10.186871 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6477 00:45:10.190175 ==
6478 00:45:10.193128 Dram Type= 6, Freq= 0, CH_1, rank 0
6479 00:45:10.196690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6480 00:45:10.197135 ==
6481 00:45:10.197470 DQS Delay:
6482 00:45:10.200297 DQS0 = 43, DQS1 = 59
6483 00:45:10.200816 DQM Delay:
6484 00:45:10.203188 DQM0 = 6, DQM1 = 15
6485 00:45:10.203757 DQ Delay:
6486 00:45:10.206503 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6487 00:45:10.210007 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6488 00:45:10.213446 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6489 00:45:10.216609 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6490 00:45:10.217155
6491 00:45:10.217499
6492 00:45:10.217809 ==
6493 00:45:10.219941 Dram Type= 6, Freq= 0, CH_1, rank 0
6494 00:45:10.223075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6495 00:45:10.223517 ==
6496 00:45:10.223852
6497 00:45:10.224165
6498 00:45:10.226423 TX Vref Scan disable
6499 00:45:10.226862 == TX Byte 0 ==
6500 00:45:10.233028 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6501 00:45:10.236259 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6502 00:45:10.236708 == TX Byte 1 ==
6503 00:45:10.243022 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6504 00:45:10.246322 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6505 00:45:10.246761 ==
6506 00:45:10.249555 Dram Type= 6, Freq= 0, CH_1, rank 0
6507 00:45:10.253164 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6508 00:45:10.253696 ==
6509 00:45:10.254036
6510 00:45:10.254421
6511 00:45:10.256169 TX Vref Scan disable
6512 00:45:10.259811 == TX Byte 0 ==
6513 00:45:10.262823 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6514 00:45:10.266260 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6515 00:45:10.269509 == TX Byte 1 ==
6516 00:45:10.272952 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6517 00:45:10.276184 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6518 00:45:10.276726
6519 00:45:10.277087 [DATLAT]
6520 00:45:10.279642 Freq=400, CH1 RK0
6521 00:45:10.280155
6522 00:45:10.280496 DATLAT Default: 0xf
6523 00:45:10.282908 0, 0xFFFF, sum = 0
6524 00:45:10.285891 1, 0xFFFF, sum = 0
6525 00:45:10.286366 2, 0xFFFF, sum = 0
6526 00:45:10.289217 3, 0xFFFF, sum = 0
6527 00:45:10.289660 4, 0xFFFF, sum = 0
6528 00:45:10.292414 5, 0xFFFF, sum = 0
6529 00:45:10.292858 6, 0xFFFF, sum = 0
6530 00:45:10.295691 7, 0xFFFF, sum = 0
6531 00:45:10.296170 8, 0xFFFF, sum = 0
6532 00:45:10.299159 9, 0xFFFF, sum = 0
6533 00:45:10.299603 10, 0xFFFF, sum = 0
6534 00:45:10.302361 11, 0xFFFF, sum = 0
6535 00:45:10.302808 12, 0x0, sum = 1
6536 00:45:10.305734 13, 0x0, sum = 2
6537 00:45:10.306284 14, 0x0, sum = 3
6538 00:45:10.309051 15, 0x0, sum = 4
6539 00:45:10.309495 best_step = 13
6540 00:45:10.309831
6541 00:45:10.310140 ==
6542 00:45:10.312378 Dram Type= 6, Freq= 0, CH_1, rank 0
6543 00:45:10.315801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6544 00:45:10.318828 ==
6545 00:45:10.319268 RX Vref Scan: 1
6546 00:45:10.319602
6547 00:45:10.322400 RX Vref 0 -> 0, step: 1
6548 00:45:10.322935
6549 00:45:10.325617 RX Delay -359 -> 252, step: 8
6550 00:45:10.326072
6551 00:45:10.328928 Set Vref, RX VrefLevel [Byte0]: 54
6552 00:45:10.332792 [Byte1]: 50
6553 00:45:10.333307
6554 00:45:10.335818 Final RX Vref Byte 0 = 54 to rank0
6555 00:45:10.339222 Final RX Vref Byte 1 = 50 to rank0
6556 00:45:10.342468 Final RX Vref Byte 0 = 54 to rank1
6557 00:45:10.345560 Final RX Vref Byte 1 = 50 to rank1==
6558 00:45:10.348994 Dram Type= 6, Freq= 0, CH_1, rank 0
6559 00:45:10.352365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6560 00:45:10.355304 ==
6561 00:45:10.355743 DQS Delay:
6562 00:45:10.356081 DQS0 = 48, DQS1 = 64
6563 00:45:10.359232 DQM Delay:
6564 00:45:10.359760 DQM0 = 9, DQM1 = 16
6565 00:45:10.362108 DQ Delay:
6566 00:45:10.362680 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =8
6567 00:45:10.365253 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6568 00:45:10.368418 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6569 00:45:10.371815 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6570 00:45:10.372252
6571 00:45:10.372585
6572 00:45:10.381725 [DQSOSCAuto] RK0, (LSB)MR18= 0xd4d4, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6573 00:45:10.385065 CH1 RK0: MR19=C0C, MR18=D4D4
6574 00:45:10.388585 CH1_RK0: MR19=0xC0C, MR18=0xD4D4, DQSOSC=383, MR23=63, INC=402, DEC=268
6575 00:45:10.391486 ==
6576 00:45:10.394955 Dram Type= 6, Freq= 0, CH_1, rank 1
6577 00:45:10.398467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6578 00:45:10.398943 ==
6579 00:45:10.401826 [Gating] SW mode calibration
6580 00:45:10.408530 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6581 00:45:10.411541 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6582 00:45:10.418296 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6583 00:45:10.421523 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6584 00:45:10.424939 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6585 00:45:10.431576 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6586 00:45:10.434748 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6587 00:45:10.438278 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6588 00:45:10.445116 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6589 00:45:10.448368 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6590 00:45:10.451757 Total UI for P1: 0, mck2ui 16
6591 00:45:10.454729 best dqsien dly found for B0: ( 0, 10, 8)
6592 00:45:10.457937 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6593 00:45:10.461134 Total UI for P1: 0, mck2ui 16
6594 00:45:10.464326 best dqsien dly found for B1: ( 0, 10, 16)
6595 00:45:10.467594 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6596 00:45:10.471121 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6597 00:45:10.471558
6598 00:45:10.477984 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6599 00:45:10.481088 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6600 00:45:10.484322 [Gating] SW calibration Done
6601 00:45:10.484809 ==
6602 00:45:10.487627 Dram Type= 6, Freq= 0, CH_1, rank 1
6603 00:45:10.491086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6604 00:45:10.491539 ==
6605 00:45:10.492083 RX Vref Scan: 0
6606 00:45:10.492414
6607 00:45:10.494359 RX Vref 0 -> 0, step: 1
6608 00:45:10.494902
6609 00:45:10.497776 RX Delay -410 -> 252, step: 16
6610 00:45:10.500948 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6611 00:45:10.507613 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6612 00:45:10.511009 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6613 00:45:10.514194 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6614 00:45:10.517547 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6615 00:45:10.524084 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6616 00:45:10.527519 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6617 00:45:10.531036 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6618 00:45:10.533928 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6619 00:45:10.540753 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6620 00:45:10.544546 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6621 00:45:10.547516 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6622 00:45:10.550728 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6623 00:45:10.557993 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6624 00:45:10.560574 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6625 00:45:10.564310 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6626 00:45:10.564821 ==
6627 00:45:10.567603 Dram Type= 6, Freq= 0, CH_1, rank 1
6628 00:45:10.571061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6629 00:45:10.573858 ==
6630 00:45:10.574322 DQS Delay:
6631 00:45:10.574696 DQS0 = 43, DQS1 = 59
6632 00:45:10.577428 DQM Delay:
6633 00:45:10.577937 DQM0 = 10, DQM1 = 17
6634 00:45:10.580824 DQ Delay:
6635 00:45:10.581329 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6636 00:45:10.584005 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6637 00:45:10.587189 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6638 00:45:10.590555 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6639 00:45:10.590983
6640 00:45:10.591311
6641 00:45:10.591613 ==
6642 00:45:10.593738 Dram Type= 6, Freq= 0, CH_1, rank 1
6643 00:45:10.600519 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6644 00:45:10.600953 ==
6645 00:45:10.601286
6646 00:45:10.601588
6647 00:45:10.601881 TX Vref Scan disable
6648 00:45:10.603954 == TX Byte 0 ==
6649 00:45:10.607313 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6650 00:45:10.610774 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6651 00:45:10.613938 == TX Byte 1 ==
6652 00:45:10.617329 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6653 00:45:10.620588 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6654 00:45:10.623926 ==
6655 00:45:10.624441 Dram Type= 6, Freq= 0, CH_1, rank 1
6656 00:45:10.630786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6657 00:45:10.631242 ==
6658 00:45:10.631578
6659 00:45:10.631884
6660 00:45:10.633697 TX Vref Scan disable
6661 00:45:10.634125 == TX Byte 0 ==
6662 00:45:10.636989 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6663 00:45:10.643930 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6664 00:45:10.644362 == TX Byte 1 ==
6665 00:45:10.647021 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6666 00:45:10.650409 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6667 00:45:10.653696
6668 00:45:10.654121 [DATLAT]
6669 00:45:10.654510 Freq=400, CH1 RK1
6670 00:45:10.654871
6671 00:45:10.657065 DATLAT Default: 0xd
6672 00:45:10.657591 0, 0xFFFF, sum = 0
6673 00:45:10.660324 1, 0xFFFF, sum = 0
6674 00:45:10.660844 2, 0xFFFF, sum = 0
6675 00:45:10.663339 3, 0xFFFF, sum = 0
6676 00:45:10.666717 4, 0xFFFF, sum = 0
6677 00:45:10.667153 5, 0xFFFF, sum = 0
6678 00:45:10.670425 6, 0xFFFF, sum = 0
6679 00:45:10.670947 7, 0xFFFF, sum = 0
6680 00:45:10.673352 8, 0xFFFF, sum = 0
6681 00:45:10.673790 9, 0xFFFF, sum = 0
6682 00:45:10.676700 10, 0xFFFF, sum = 0
6683 00:45:10.677136 11, 0xFFFF, sum = 0
6684 00:45:10.680324 12, 0x0, sum = 1
6685 00:45:10.680839 13, 0x0, sum = 2
6686 00:45:10.683516 14, 0x0, sum = 3
6687 00:45:10.683952 15, 0x0, sum = 4
6688 00:45:10.684353 best_step = 13
6689 00:45:10.687001
6690 00:45:10.687439 ==
6691 00:45:10.689893 Dram Type= 6, Freq= 0, CH_1, rank 1
6692 00:45:10.693250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6693 00:45:10.693685 ==
6694 00:45:10.694019 RX Vref Scan: 0
6695 00:45:10.694385
6696 00:45:10.696735 RX Vref 0 -> 0, step: 1
6697 00:45:10.697161
6698 00:45:10.699972 RX Delay -359 -> 252, step: 8
6699 00:45:10.707238 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6700 00:45:10.710368 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6701 00:45:10.713980 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6702 00:45:10.717154 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6703 00:45:10.723650 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6704 00:45:10.727053 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6705 00:45:10.730275 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6706 00:45:10.733946 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6707 00:45:10.740141 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6708 00:45:10.743638 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6709 00:45:10.746966 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6710 00:45:10.753788 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6711 00:45:10.756857 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6712 00:45:10.760219 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6713 00:45:10.763410 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6714 00:45:10.770098 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6715 00:45:10.770683 ==
6716 00:45:10.773273 Dram Type= 6, Freq= 0, CH_1, rank 1
6717 00:45:10.777015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6718 00:45:10.777590 ==
6719 00:45:10.778034 DQS Delay:
6720 00:45:10.779895 DQS0 = 48, DQS1 = 64
6721 00:45:10.780323 DQM Delay:
6722 00:45:10.783178 DQM0 = 9, DQM1 = 15
6723 00:45:10.783606 DQ Delay:
6724 00:45:10.786573 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6725 00:45:10.789879 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6726 00:45:10.793378 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6727 00:45:10.796561 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6728 00:45:10.797007
6729 00:45:10.797345
6730 00:45:10.803335 [DQSOSCAuto] RK1, (LSB)MR18= 0xb5b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6731 00:45:10.806601 CH1 RK1: MR19=C0C, MR18=B5B5
6732 00:45:10.813044 CH1_RK1: MR19=0xC0C, MR18=0xB5B5, DQSOSC=387, MR23=63, INC=394, DEC=262
6733 00:45:10.816415 [RxdqsGatingPostProcess] freq 400
6734 00:45:10.823366 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6735 00:45:10.823931 Pre-setting of DQS Precalculation
6736 00:45:10.829965 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6737 00:45:10.836270 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6738 00:45:10.842964 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6739 00:45:10.843465
6740 00:45:10.843799
6741 00:45:10.846324 [Calibration Summary] 800 Mbps
6742 00:45:10.849968 CH 0, Rank 0
6743 00:45:10.850607 SW Impedance : PASS
6744 00:45:10.852983 DUTY Scan : NO K
6745 00:45:10.856176 ZQ Calibration : PASS
6746 00:45:10.856709 Jitter Meter : NO K
6747 00:45:10.859676 CBT Training : PASS
6748 00:45:10.862619 Write leveling : PASS
6749 00:45:10.863051 RX DQS gating : PASS
6750 00:45:10.865900 RX DQ/DQS(RDDQC) : PASS
6751 00:45:10.869643 TX DQ/DQS : PASS
6752 00:45:10.870160 RX DATLAT : PASS
6753 00:45:10.872784 RX DQ/DQS(Engine): PASS
6754 00:45:10.873215 TX OE : NO K
6755 00:45:10.876033 All Pass.
6756 00:45:10.876495
6757 00:45:10.876833 CH 0, Rank 1
6758 00:45:10.879416 SW Impedance : PASS
6759 00:45:10.879938 DUTY Scan : NO K
6760 00:45:10.882589 ZQ Calibration : PASS
6761 00:45:10.885914 Jitter Meter : NO K
6762 00:45:10.886381 CBT Training : PASS
6763 00:45:10.889470 Write leveling : NO K
6764 00:45:10.892759 RX DQS gating : PASS
6765 00:45:10.893289 RX DQ/DQS(RDDQC) : PASS
6766 00:45:10.895910 TX DQ/DQS : PASS
6767 00:45:10.899137 RX DATLAT : PASS
6768 00:45:10.899585 RX DQ/DQS(Engine): PASS
6769 00:45:10.902686 TX OE : NO K
6770 00:45:10.903118 All Pass.
6771 00:45:10.903453
6772 00:45:10.905756 CH 1, Rank 0
6773 00:45:10.906187 SW Impedance : PASS
6774 00:45:10.909126 DUTY Scan : NO K
6775 00:45:10.912493 ZQ Calibration : PASS
6776 00:45:10.912962 Jitter Meter : NO K
6777 00:45:10.915773 CBT Training : PASS
6778 00:45:10.919081 Write leveling : PASS
6779 00:45:10.919503 RX DQS gating : PASS
6780 00:45:10.922286 RX DQ/DQS(RDDQC) : PASS
6781 00:45:10.922689 TX DQ/DQS : PASS
6782 00:45:10.925697 RX DATLAT : PASS
6783 00:45:10.929423 RX DQ/DQS(Engine): PASS
6784 00:45:10.929924 TX OE : NO K
6785 00:45:10.932342 All Pass.
6786 00:45:10.932797
6787 00:45:10.933233 CH 1, Rank 1
6788 00:45:10.935621 SW Impedance : PASS
6789 00:45:10.936059 DUTY Scan : NO K
6790 00:45:10.939146 ZQ Calibration : PASS
6791 00:45:10.942391 Jitter Meter : NO K
6792 00:45:10.942839 CBT Training : PASS
6793 00:45:10.945457 Write leveling : NO K
6794 00:45:10.949026 RX DQS gating : PASS
6795 00:45:10.949567 RX DQ/DQS(RDDQC) : PASS
6796 00:45:10.952396 TX DQ/DQS : PASS
6797 00:45:10.955624 RX DATLAT : PASS
6798 00:45:10.956158 RX DQ/DQS(Engine): PASS
6799 00:45:10.959107 TX OE : NO K
6800 00:45:10.959625 All Pass.
6801 00:45:10.960102
6802 00:45:10.962450 DramC Write-DBI off
6803 00:45:10.965785 PER_BANK_REFRESH: Hybrid Mode
6804 00:45:10.966351 TX_TRACKING: ON
6805 00:45:10.975609 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6806 00:45:10.979042 [FAST_K] Save calibration result to emmc
6807 00:45:10.982281 dramc_set_vcore_voltage set vcore to 725000
6808 00:45:10.985461 Read voltage for 1600, 0
6809 00:45:10.985904 Vio18 = 0
6810 00:45:10.986438 Vcore = 725000
6811 00:45:10.988714 Vdram = 0
6812 00:45:10.989151 Vddq = 0
6813 00:45:10.989589 Vmddr = 0
6814 00:45:10.995283 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6815 00:45:10.998676 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6816 00:45:11.002095 MEM_TYPE=3, freq_sel=13
6817 00:45:11.005356 sv_algorithm_assistance_LP4_3733
6818 00:45:11.008903 ============ PULL DRAM RESETB DOWN ============
6819 00:45:11.012129 ========== PULL DRAM RESETB DOWN end =========
6820 00:45:11.018612 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6821 00:45:11.022018 ===================================
6822 00:45:11.025291 LPDDR4 DRAM CONFIGURATION
6823 00:45:11.028506 ===================================
6824 00:45:11.028939 EX_ROW_EN[0] = 0x0
6825 00:45:11.031788 EX_ROW_EN[1] = 0x0
6826 00:45:11.032228 LP4Y_EN = 0x0
6827 00:45:11.035361 WORK_FSP = 0x1
6828 00:45:11.035793 WL = 0x5
6829 00:45:11.038516 RL = 0x5
6830 00:45:11.039009 BL = 0x2
6831 00:45:11.041812 RPST = 0x0
6832 00:45:11.042274 RD_PRE = 0x0
6833 00:45:11.045056 WR_PRE = 0x1
6834 00:45:11.045488 WR_PST = 0x1
6835 00:45:11.048775 DBI_WR = 0x0
6836 00:45:11.049301 DBI_RD = 0x0
6837 00:45:11.051666 OTF = 0x1
6838 00:45:11.055147 ===================================
6839 00:45:11.058593 ===================================
6840 00:45:11.059111 ANA top config
6841 00:45:11.061799 ===================================
6842 00:45:11.065254 DLL_ASYNC_EN = 0
6843 00:45:11.068846 ALL_SLAVE_EN = 0
6844 00:45:11.072056 NEW_RANK_MODE = 1
6845 00:45:11.072497 DLL_IDLE_MODE = 1
6846 00:45:11.075165 LP45_APHY_COMB_EN = 1
6847 00:45:11.078277 TX_ODT_DIS = 0
6848 00:45:11.081598 NEW_8X_MODE = 1
6849 00:45:11.085182 ===================================
6850 00:45:11.088192 ===================================
6851 00:45:11.091548 data_rate = 3200
6852 00:45:11.091979 CKR = 1
6853 00:45:11.094848 DQ_P2S_RATIO = 8
6854 00:45:11.098012 ===================================
6855 00:45:11.101376 CA_P2S_RATIO = 8
6856 00:45:11.104809 DQ_CA_OPEN = 0
6857 00:45:11.108100 DQ_SEMI_OPEN = 0
6858 00:45:11.111438 CA_SEMI_OPEN = 0
6859 00:45:11.111985 CA_FULL_RATE = 0
6860 00:45:11.114755 DQ_CKDIV4_EN = 0
6861 00:45:11.118080 CA_CKDIV4_EN = 0
6862 00:45:11.121419 CA_PREDIV_EN = 0
6863 00:45:11.124800 PH8_DLY = 12
6864 00:45:11.127953 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6865 00:45:11.128382 DQ_AAMCK_DIV = 4
6866 00:45:11.131176 CA_AAMCK_DIV = 4
6867 00:45:11.134857 CA_ADMCK_DIV = 4
6868 00:45:11.138347 DQ_TRACK_CA_EN = 0
6869 00:45:11.141285 CA_PICK = 1600
6870 00:45:11.144672 CA_MCKIO = 1600
6871 00:45:11.148037 MCKIO_SEMI = 0
6872 00:45:11.151810 PLL_FREQ = 3068
6873 00:45:11.152348 DQ_UI_PI_RATIO = 32
6874 00:45:11.154533 CA_UI_PI_RATIO = 0
6875 00:45:11.157777 ===================================
6876 00:45:11.161562 ===================================
6877 00:45:11.164563 memory_type:LPDDR4
6878 00:45:11.168346 GP_NUM : 10
6879 00:45:11.168868 SRAM_EN : 1
6880 00:45:11.171139 MD32_EN : 0
6881 00:45:11.174588 ===================================
6882 00:45:11.175022 [ANA_INIT] >>>>>>>>>>>>>>
6883 00:45:11.177632 <<<<<< [CONFIGURE PHASE]: ANA_TX
6884 00:45:11.181159 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6885 00:45:11.184230 ===================================
6886 00:45:11.187584 data_rate = 3200,PCW = 0X7600
6887 00:45:11.190948 ===================================
6888 00:45:11.194609 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6889 00:45:11.200965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6890 00:45:11.207596 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6891 00:45:11.210847 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6892 00:45:11.214032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6893 00:45:11.217624 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6894 00:45:11.221099 [ANA_INIT] flow start
6895 00:45:11.221638 [ANA_INIT] PLL >>>>>>>>
6896 00:45:11.224270 [ANA_INIT] PLL <<<<<<<<
6897 00:45:11.227347 [ANA_INIT] MIDPI >>>>>>>>
6898 00:45:11.227783 [ANA_INIT] MIDPI <<<<<<<<
6899 00:45:11.230796 [ANA_INIT] DLL >>>>>>>>
6900 00:45:11.234182 [ANA_INIT] DLL <<<<<<<<
6901 00:45:11.234784 [ANA_INIT] flow end
6902 00:45:11.240525 ============ LP4 DIFF to SE enter ============
6903 00:45:11.244037 ============ LP4 DIFF to SE exit ============
6904 00:45:11.247206 [ANA_INIT] <<<<<<<<<<<<<
6905 00:45:11.250772 [Flow] Enable top DCM control >>>>>
6906 00:45:11.253973 [Flow] Enable top DCM control <<<<<
6907 00:45:11.257076 Enable DLL master slave shuffle
6908 00:45:11.260636 ==============================================================
6909 00:45:11.263914 Gating Mode config
6910 00:45:11.266819 ==============================================================
6911 00:45:11.270285 Config description:
6912 00:45:11.280015 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6913 00:45:11.286694 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6914 00:45:11.290278 SELPH_MODE 0: By rank 1: By Phase
6915 00:45:11.296869 ==============================================================
6916 00:45:11.300183 GAT_TRACK_EN = 1
6917 00:45:11.303614 RX_GATING_MODE = 2
6918 00:45:11.306617 RX_GATING_TRACK_MODE = 2
6919 00:45:11.310157 SELPH_MODE = 1
6920 00:45:11.313198 PICG_EARLY_EN = 1
6921 00:45:11.313634 VALID_LAT_VALUE = 1
6922 00:45:11.319885 ==============================================================
6923 00:45:11.323558 Enter into Gating configuration >>>>
6924 00:45:11.326383 Exit from Gating configuration <<<<
6925 00:45:11.329911 Enter into DVFS_PRE_config >>>>>
6926 00:45:11.339705 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6927 00:45:11.343055 Exit from DVFS_PRE_config <<<<<
6928 00:45:11.346825 Enter into PICG configuration >>>>
6929 00:45:11.350045 Exit from PICG configuration <<<<
6930 00:45:11.353225 [RX_INPUT] configuration >>>>>
6931 00:45:11.356836 [RX_INPUT] configuration <<<<<
6932 00:45:11.362918 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6933 00:45:11.366666 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6934 00:45:11.373144 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6935 00:45:11.379370 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6936 00:45:11.385916 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6937 00:45:11.392734 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6938 00:45:11.396311 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6939 00:45:11.399475 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6940 00:45:11.402548 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6941 00:45:11.409380 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6942 00:45:11.412681 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6943 00:45:11.416026 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6944 00:45:11.419105 ===================================
6945 00:45:11.422637 LPDDR4 DRAM CONFIGURATION
6946 00:45:11.425876 ===================================
6947 00:45:11.426449 EX_ROW_EN[0] = 0x0
6948 00:45:11.429051 EX_ROW_EN[1] = 0x0
6949 00:45:11.432393 LP4Y_EN = 0x0
6950 00:45:11.432826 WORK_FSP = 0x1
6951 00:45:11.436071 WL = 0x5
6952 00:45:11.436605 RL = 0x5
6953 00:45:11.439352 BL = 0x2
6954 00:45:11.439842 RPST = 0x0
6955 00:45:11.442619 RD_PRE = 0x0
6956 00:45:11.443048 WR_PRE = 0x1
6957 00:45:11.445665 WR_PST = 0x1
6958 00:45:11.446097 DBI_WR = 0x0
6959 00:45:11.448802 DBI_RD = 0x0
6960 00:45:11.449235 OTF = 0x1
6961 00:45:11.452366 ===================================
6962 00:45:11.455857 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6963 00:45:11.462463 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6964 00:45:11.465427 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6965 00:45:11.468805 ===================================
6966 00:45:11.472225 LPDDR4 DRAM CONFIGURATION
6967 00:45:11.475527 ===================================
6968 00:45:11.475957 EX_ROW_EN[0] = 0x10
6969 00:45:11.478674 EX_ROW_EN[1] = 0x0
6970 00:45:11.481930 LP4Y_EN = 0x0
6971 00:45:11.482415 WORK_FSP = 0x1
6972 00:45:11.485378 WL = 0x5
6973 00:45:11.485800 RL = 0x5
6974 00:45:11.488709 BL = 0x2
6975 00:45:11.489105 RPST = 0x0
6976 00:45:11.492064 RD_PRE = 0x0
6977 00:45:11.492457 WR_PRE = 0x1
6978 00:45:11.495297 WR_PST = 0x1
6979 00:45:11.495694 DBI_WR = 0x0
6980 00:45:11.498703 DBI_RD = 0x0
6981 00:45:11.499103 OTF = 0x1
6982 00:45:11.501950 ===================================
6983 00:45:11.508887 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6984 00:45:11.509403 ==
6985 00:45:11.512081 Dram Type= 6, Freq= 0, CH_0, rank 0
6986 00:45:11.515162 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6987 00:45:11.515568 ==
6988 00:45:11.518837 [Duty_Offset_Calibration]
6989 00:45:11.521891 B0:0 B1:2 CA:1
6990 00:45:11.522315
6991 00:45:11.525303 [DutyScan_Calibration_Flow] k_type=0
6992 00:45:11.534124
6993 00:45:11.534674 ==CLK 0==
6994 00:45:11.537302 Final CLK duty delay cell = 0
6995 00:45:11.540419 [0] MAX Duty = 5156%(X100), DQS PI = 22
6996 00:45:11.544008 [0] MIN Duty = 4938%(X100), DQS PI = 50
6997 00:45:11.544497 [0] AVG Duty = 5047%(X100)
6998 00:45:11.547156
6999 00:45:11.550565 CH0 CLK Duty spec in!! Max-Min= 218%
7000 00:45:11.553729 [DutyScan_Calibration_Flow] ====Done====
7001 00:45:11.554170
7002 00:45:11.557324 [DutyScan_Calibration_Flow] k_type=1
7003 00:45:11.573836
7004 00:45:11.574429 ==DQS 0 ==
7005 00:45:11.577353 Final DQS duty delay cell = 0
7006 00:45:11.580969 [0] MAX Duty = 5125%(X100), DQS PI = 2
7007 00:45:11.583874 [0] MIN Duty = 5031%(X100), DQS PI = 8
7008 00:45:11.584311 [0] AVG Duty = 5078%(X100)
7009 00:45:11.584651
7010 00:45:11.587239 ==DQS 1 ==
7011 00:45:11.590694 Final DQS duty delay cell = 0
7012 00:45:11.594034 [0] MAX Duty = 5031%(X100), DQS PI = 46
7013 00:45:11.597330 [0] MIN Duty = 4876%(X100), DQS PI = 16
7014 00:45:11.597868 [0] AVG Duty = 4953%(X100)
7015 00:45:11.598255
7016 00:45:11.603943 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7017 00:45:11.604383
7018 00:45:11.607179 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7019 00:45:11.610483 [DutyScan_Calibration_Flow] ====Done====
7020 00:45:11.610920
7021 00:45:11.613712 [DutyScan_Calibration_Flow] k_type=3
7022 00:45:11.631024
7023 00:45:11.631489 ==DQM 0 ==
7024 00:45:11.634452 Final DQM duty delay cell = 0
7025 00:45:11.637567 [0] MAX Duty = 5187%(X100), DQS PI = 24
7026 00:45:11.640977 [0] MIN Duty = 4907%(X100), DQS PI = 42
7027 00:45:11.644683 [0] AVG Duty = 5047%(X100)
7028 00:45:11.645290
7029 00:45:11.645646 ==DQM 1 ==
7030 00:45:11.647692 Final DQM duty delay cell = 0
7031 00:45:11.650980 [0] MAX Duty = 5031%(X100), DQS PI = 50
7032 00:45:11.654069 [0] MIN Duty = 4782%(X100), DQS PI = 14
7033 00:45:11.657329 [0] AVG Duty = 4906%(X100)
7034 00:45:11.657781
7035 00:45:11.660950 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7036 00:45:11.661439
7037 00:45:11.664035 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7038 00:45:11.667492 [DutyScan_Calibration_Flow] ====Done====
7039 00:45:11.667900
7040 00:45:11.670748 [DutyScan_Calibration_Flow] k_type=2
7041 00:45:11.687224
7042 00:45:11.687733 ==DQ 0 ==
7043 00:45:11.690539 Final DQ duty delay cell = 0
7044 00:45:11.693992 [0] MAX Duty = 5218%(X100), DQS PI = 18
7045 00:45:11.697457 [0] MIN Duty = 4938%(X100), DQS PI = 54
7046 00:45:11.697987 [0] AVG Duty = 5078%(X100)
7047 00:45:11.700768
7048 00:45:11.701163 ==DQ 1 ==
7049 00:45:11.703817 Final DQ duty delay cell = -4
7050 00:45:11.707347 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7051 00:45:11.710488 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7052 00:45:11.713620 [-4] AVG Duty = 4953%(X100)
7053 00:45:11.714012
7054 00:45:11.717097 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7055 00:45:11.717492
7056 00:45:11.720310 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7057 00:45:11.723875 [DutyScan_Calibration_Flow] ====Done====
7058 00:45:11.724269 ==
7059 00:45:11.727236 Dram Type= 6, Freq= 0, CH_1, rank 0
7060 00:45:11.730582 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7061 00:45:11.730980 ==
7062 00:45:11.733944 [Duty_Offset_Calibration]
7063 00:45:11.734475 B0:0 B1:5 CA:-5
7064 00:45:11.734792
7065 00:45:11.737199 [DutyScan_Calibration_Flow] k_type=0
7066 00:45:11.748379
7067 00:45:11.748889 ==CLK 0==
7068 00:45:11.751359 Final CLK duty delay cell = 0
7069 00:45:11.754505 [0] MAX Duty = 5156%(X100), DQS PI = 18
7070 00:45:11.758122 [0] MIN Duty = 4906%(X100), DQS PI = 50
7071 00:45:11.761078 [0] AVG Duty = 5031%(X100)
7072 00:45:11.761595
7073 00:45:11.764612 CH1 CLK Duty spec in!! Max-Min= 250%
7074 00:45:11.767743 [DutyScan_Calibration_Flow] ====Done====
7075 00:45:11.768182
7076 00:45:11.770963 [DutyScan_Calibration_Flow] k_type=1
7077 00:45:11.786835
7078 00:45:11.787358 ==DQS 0 ==
7079 00:45:11.790291 Final DQS duty delay cell = 0
7080 00:45:11.793191 [0] MAX Duty = 5187%(X100), DQS PI = 20
7081 00:45:11.796867 [0] MIN Duty = 4876%(X100), DQS PI = 42
7082 00:45:11.799855 [0] AVG Duty = 5031%(X100)
7083 00:45:11.800305
7084 00:45:11.800641 ==DQS 1 ==
7085 00:45:11.803242 Final DQS duty delay cell = -4
7086 00:45:11.806703 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7087 00:45:11.809934 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7088 00:45:11.813429 [-4] AVG Duty = 4922%(X100)
7089 00:45:11.813931
7090 00:45:11.816819 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7091 00:45:11.817330
7092 00:45:11.820160 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7093 00:45:11.823198 [DutyScan_Calibration_Flow] ====Done====
7094 00:45:11.823635
7095 00:45:11.826430 [DutyScan_Calibration_Flow] k_type=3
7096 00:45:11.842563
7097 00:45:11.843069 ==DQM 0 ==
7098 00:45:11.845675 Final DQM duty delay cell = -4
7099 00:45:11.849324 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7100 00:45:11.852771 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7101 00:45:11.855861 [-4] AVG Duty = 4922%(X100)
7102 00:45:11.856369
7103 00:45:11.856705 ==DQM 1 ==
7104 00:45:11.859171 Final DQM duty delay cell = -4
7105 00:45:11.862741 [-4] MAX Duty = 5062%(X100), DQS PI = 14
7106 00:45:11.865867 [-4] MIN Duty = 4876%(X100), DQS PI = 40
7107 00:45:11.868999 [-4] AVG Duty = 4969%(X100)
7108 00:45:11.869518
7109 00:45:11.872254 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7110 00:45:11.872692
7111 00:45:11.875586 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7112 00:45:11.879188 [DutyScan_Calibration_Flow] ====Done====
7113 00:45:11.879629
7114 00:45:11.882383 [DutyScan_Calibration_Flow] k_type=2
7115 00:45:11.900080
7116 00:45:11.900766 ==DQ 0 ==
7117 00:45:11.903333 Final DQ duty delay cell = 0
7118 00:45:11.906744 [0] MAX Duty = 5062%(X100), DQS PI = 2
7119 00:45:11.910141 [0] MIN Duty = 4938%(X100), DQS PI = 46
7120 00:45:11.910620 [0] AVG Duty = 5000%(X100)
7121 00:45:11.913121
7122 00:45:11.913512 ==DQ 1 ==
7123 00:45:11.916674 Final DQ duty delay cell = 0
7124 00:45:11.920208 [0] MAX Duty = 5062%(X100), DQS PI = 6
7125 00:45:11.923016 [0] MIN Duty = 4875%(X100), DQS PI = 28
7126 00:45:11.923448 [0] AVG Duty = 4968%(X100)
7127 00:45:11.923793
7128 00:45:11.929905 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7129 00:45:11.930470
7130 00:45:11.933098 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7131 00:45:11.936669 [DutyScan_Calibration_Flow] ====Done====
7132 00:45:11.939604 nWR fixed to 30
7133 00:45:11.940151 [ModeRegInit_LP4] CH0 RK0
7134 00:45:11.943050 [ModeRegInit_LP4] CH0 RK1
7135 00:45:11.946442 [ModeRegInit_LP4] CH1 RK0
7136 00:45:11.949538 [ModeRegInit_LP4] CH1 RK1
7137 00:45:11.949929 match AC timing 4
7138 00:45:11.953293 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7139 00:45:11.959401 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7140 00:45:11.963281 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7141 00:45:11.969778 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7142 00:45:11.972959 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7143 00:45:11.973475 [MiockJmeterHQA]
7144 00:45:11.973815
7145 00:45:11.976027 [DramcMiockJmeter] u1RxGatingPI = 0
7146 00:45:11.979451 0 : 4252, 4027
7147 00:45:11.980015 4 : 4252, 4027
7148 00:45:11.983131 8 : 4252, 4027
7149 00:45:11.983652 12 : 4252, 4027
7150 00:45:11.984000 16 : 4364, 4137
7151 00:45:11.986093 20 : 4363, 4138
7152 00:45:11.986567 24 : 4253, 4027
7153 00:45:11.989165 28 : 4252, 4027
7154 00:45:11.989618 32 : 4253, 4027
7155 00:45:11.992565 36 : 4253, 4026
7156 00:45:11.993021 40 : 4252, 4027
7157 00:45:11.995794 44 : 4363, 4137
7158 00:45:11.996235 48 : 4252, 4027
7159 00:45:11.996574 52 : 4253, 4027
7160 00:45:11.999132 56 : 4253, 4027
7161 00:45:11.999568 60 : 4252, 4027
7162 00:45:12.002736 64 : 4250, 4027
7163 00:45:12.003176 68 : 4361, 4138
7164 00:45:12.005801 72 : 4360, 4138
7165 00:45:12.006375 76 : 4250, 4027
7166 00:45:12.009082 80 : 4250, 4026
7167 00:45:12.009521 84 : 4250, 4027
7168 00:45:12.009861 88 : 4250, 4027
7169 00:45:12.012378 92 : 4250, 4027
7170 00:45:12.012814 96 : 4361, 4137
7171 00:45:12.015909 100 : 4250, 2054
7172 00:45:12.016370 104 : 4250, 0
7173 00:45:12.019505 108 : 4254, 0
7174 00:45:12.019942 112 : 4361, 0
7175 00:45:12.020281 116 : 4361, 0
7176 00:45:12.022317 120 : 4250, 0
7177 00:45:12.022739 124 : 4250, 0
7178 00:45:12.023049 128 : 4363, 0
7179 00:45:12.025518 132 : 4250, 0
7180 00:45:12.025926 136 : 4250, 0
7181 00:45:12.028998 140 : 4250, 0
7182 00:45:12.029402 144 : 4253, 0
7183 00:45:12.029713 148 : 4250, 0
7184 00:45:12.032109 152 : 4250, 0
7185 00:45:12.032509 156 : 4250, 0
7186 00:45:12.035739 160 : 4361, 0
7187 00:45:12.036219 164 : 4250, 0
7188 00:45:12.036529 168 : 4250, 0
7189 00:45:12.038921 172 : 4250, 0
7190 00:45:12.039318 176 : 4250, 0
7191 00:45:12.042302 180 : 4364, 0
7192 00:45:12.042698 184 : 4250, 0
7193 00:45:12.043007 188 : 4250, 0
7194 00:45:12.045794 192 : 4250, 0
7195 00:45:12.046310 196 : 4250, 0
7196 00:45:12.046627 200 : 4250, 0
7197 00:45:12.049001 204 : 4250, 0
7198 00:45:12.049538 208 : 4250, 0
7199 00:45:12.052080 212 : 4361, 0
7200 00:45:12.052475 216 : 4250, 0
7201 00:45:12.055843 220 : 4250, 552
7202 00:45:12.056319 224 : 4250, 3957
7203 00:45:12.056630 228 : 4250, 4026
7204 00:45:12.058888 232 : 4253, 4029
7205 00:45:12.059373 236 : 4361, 4137
7206 00:45:12.062397 240 : 4361, 4137
7207 00:45:12.062876 244 : 4250, 4027
7208 00:45:12.065569 248 : 4250, 4027
7209 00:45:12.065967 252 : 4361, 4138
7210 00:45:12.068765 256 : 4250, 4027
7211 00:45:12.069163 260 : 4250, 4027
7212 00:45:12.072413 264 : 4250, 4027
7213 00:45:12.072888 268 : 4250, 4027
7214 00:45:12.075534 272 : 4249, 4027
7215 00:45:12.075934 276 : 4250, 4026
7216 00:45:12.078951 280 : 4361, 4138
7217 00:45:12.079493 284 : 4250, 4027
7218 00:45:12.079816 288 : 4251, 4027
7219 00:45:12.082038 292 : 4360, 4137
7220 00:45:12.082463 296 : 4250, 4027
7221 00:45:12.085563 300 : 4250, 4026
7222 00:45:12.086039 304 : 4360, 4138
7223 00:45:12.088720 308 : 4250, 4027
7224 00:45:12.089113 312 : 4250, 4027
7225 00:45:12.092360 316 : 4253, 4026
7226 00:45:12.092837 320 : 4250, 4027
7227 00:45:12.095204 324 : 4249, 4027
7228 00:45:12.095606 328 : 4250, 4027
7229 00:45:12.098496 332 : 4361, 4138
7230 00:45:12.098900 336 : 4250, 3843
7231 00:45:12.102144 340 : 4250, 1877
7232 00:45:12.102610
7233 00:45:12.103001 MIOCK jitter meter ch=0
7234 00:45:12.103435
7235 00:45:12.105395 1T = (340-100) = 240 dly cells
7236 00:45:12.111933 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7237 00:45:12.112330 ==
7238 00:45:12.115389 Dram Type= 6, Freq= 0, CH_0, rank 0
7239 00:45:12.118705 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7240 00:45:12.119141 ==
7241 00:45:12.125284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7242 00:45:12.128477 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7243 00:45:12.131679 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7244 00:45:12.138344 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7245 00:45:12.147289 [CA 0] Center 42 (12~73) winsize 62
7246 00:45:12.150682 [CA 1] Center 42 (12~73) winsize 62
7247 00:45:12.153947 [CA 2] Center 39 (9~69) winsize 61
7248 00:45:12.157288 [CA 3] Center 38 (9~68) winsize 60
7249 00:45:12.160850 [CA 4] Center 37 (7~67) winsize 61
7250 00:45:12.163835 [CA 5] Center 36 (6~66) winsize 61
7251 00:45:12.164271
7252 00:45:12.167400 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7253 00:45:12.167915
7254 00:45:12.170505 [CATrainingPosCal] consider 1 rank data
7255 00:45:12.173826 u2DelayCellTimex100 = 271/100 ps
7256 00:45:12.177203 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7257 00:45:12.183834 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7258 00:45:12.186977 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7259 00:45:12.190435 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7260 00:45:12.193624 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7261 00:45:12.196846 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7262 00:45:12.197240
7263 00:45:12.200235 CA PerBit enable=1, Macro0, CA PI delay=36
7264 00:45:12.200638
7265 00:45:12.203459 [CBTSetCACLKResult] CA Dly = 36
7266 00:45:12.207032 CS Dly: 10 (0~41)
7267 00:45:12.210291 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7268 00:45:12.213962 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7269 00:45:12.214489 ==
7270 00:45:12.216959 Dram Type= 6, Freq= 0, CH_0, rank 1
7271 00:45:12.220727 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7272 00:45:12.223760 ==
7273 00:45:12.227151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7274 00:45:12.230497 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7275 00:45:12.237165 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7276 00:45:12.240386 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7277 00:45:12.250130 [CA 0] Center 42 (12~73) winsize 62
7278 00:45:12.253490 [CA 1] Center 41 (11~72) winsize 62
7279 00:45:12.256789 [CA 2] Center 38 (8~68) winsize 61
7280 00:45:12.259931 [CA 3] Center 37 (7~67) winsize 61
7281 00:45:12.263142 [CA 4] Center 35 (5~65) winsize 61
7282 00:45:12.266879 [CA 5] Center 35 (5~66) winsize 62
7283 00:45:12.267424
7284 00:45:12.269787 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7285 00:45:12.270243
7286 00:45:12.273339 [CATrainingPosCal] consider 2 rank data
7287 00:45:12.276922 u2DelayCellTimex100 = 271/100 ps
7288 00:45:12.279670 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7289 00:45:12.286318 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7290 00:45:12.289577 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7291 00:45:12.293486 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7292 00:45:12.296308 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7293 00:45:12.299577 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7294 00:45:12.300010
7295 00:45:12.302946 CA PerBit enable=1, Macro0, CA PI delay=36
7296 00:45:12.303392
7297 00:45:12.306279 [CBTSetCACLKResult] CA Dly = 36
7298 00:45:12.309509 CS Dly: 11 (0~43)
7299 00:45:12.312904 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7300 00:45:12.316328 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7301 00:45:12.316789
7302 00:45:12.319588 ----->DramcWriteLeveling(PI) begin...
7303 00:45:12.320085 ==
7304 00:45:12.323025 Dram Type= 6, Freq= 0, CH_0, rank 0
7305 00:45:12.326194 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7306 00:45:12.329586 ==
7307 00:45:12.330018 Write leveling (Byte 0): 29 => 29
7308 00:45:12.333048 Write leveling (Byte 1): 25 => 25
7309 00:45:12.336180 DramcWriteLeveling(PI) end<-----
7310 00:45:12.336612
7311 00:45:12.336946 ==
7312 00:45:12.339566 Dram Type= 6, Freq= 0, CH_0, rank 0
7313 00:45:12.346330 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7314 00:45:12.346823 ==
7315 00:45:12.349431 [Gating] SW mode calibration
7316 00:45:12.356189 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7317 00:45:12.359462 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7318 00:45:12.366159 0 12 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7319 00:45:12.369127 0 12 4 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
7320 00:45:12.372504 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7321 00:45:12.378798 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7322 00:45:12.382561 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7323 00:45:12.385604 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7324 00:45:12.392311 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7325 00:45:12.395419 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7326 00:45:12.398887 0 13 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
7327 00:45:12.405398 0 13 4 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
7328 00:45:12.408731 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
7329 00:45:12.412308 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7330 00:45:12.418562 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7331 00:45:12.421981 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7332 00:45:12.425266 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7333 00:45:12.431735 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7334 00:45:12.435323 0 14 0 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7335 00:45:12.438328 0 14 4 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7336 00:45:12.445241 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7337 00:45:12.448380 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7338 00:45:12.451887 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7339 00:45:12.458495 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7340 00:45:12.461521 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7341 00:45:12.464949 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7342 00:45:12.471465 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7343 00:45:12.474926 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7344 00:45:12.478203 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 00:45:12.484660 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 00:45:12.487857 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 00:45:12.491271 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 00:45:12.497932 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 00:45:12.501114 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 00:45:12.504452 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 00:45:12.511371 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 00:45:12.514611 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 00:45:12.517569 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 00:45:12.524641 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 00:45:12.527679 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 00:45:12.531115 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 00:45:12.537922 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 00:45:12.541032 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7359 00:45:12.544182 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7360 00:45:12.547573 Total UI for P1: 0, mck2ui 16
7361 00:45:12.550847 best dqsien dly found for B0: ( 1, 1, 0)
7362 00:45:12.554783 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7363 00:45:12.560974 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7364 00:45:12.564483 Total UI for P1: 0, mck2ui 16
7365 00:45:12.567722 best dqsien dly found for B1: ( 1, 1, 6)
7366 00:45:12.570913 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7367 00:45:12.573990 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7368 00:45:12.574539
7369 00:45:12.577396 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7370 00:45:12.580672 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7371 00:45:12.583999 [Gating] SW calibration Done
7372 00:45:12.584452 ==
7373 00:45:12.587290 Dram Type= 6, Freq= 0, CH_0, rank 0
7374 00:45:12.590561 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7375 00:45:12.591012 ==
7376 00:45:12.594166 RX Vref Scan: 0
7377 00:45:12.594754
7378 00:45:12.595260 RX Vref 0 -> 0, step: 1
7379 00:45:12.595613
7380 00:45:12.597197 RX Delay 0 -> 252, step: 8
7381 00:45:12.600515 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7382 00:45:12.607192 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7383 00:45:12.610689 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7384 00:45:12.613779 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7385 00:45:12.617538 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7386 00:45:12.620566 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7387 00:45:12.627049 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7388 00:45:12.630361 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7389 00:45:12.633314 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7390 00:45:12.636837 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7391 00:45:12.643944 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7392 00:45:12.646596 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7393 00:45:12.650134 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7394 00:45:12.653658 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7395 00:45:12.656518 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7396 00:45:12.663348 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7397 00:45:12.663860 ==
7398 00:45:12.666468 Dram Type= 6, Freq= 0, CH_0, rank 0
7399 00:45:12.670007 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7400 00:45:12.670575 ==
7401 00:45:12.670920 DQS Delay:
7402 00:45:12.673090 DQS0 = 0, DQS1 = 0
7403 00:45:12.673523 DQM Delay:
7404 00:45:12.676353 DQM0 = 129, DQM1 = 124
7405 00:45:12.676785 DQ Delay:
7406 00:45:12.679563 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7407 00:45:12.682844 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7408 00:45:12.686246 DQ8 =115, DQ9 =107, DQ10 =119, DQ11 =115
7409 00:45:12.689545 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7410 00:45:12.692892
7411 00:45:12.693377
7412 00:45:12.693708 ==
7413 00:45:12.696460 Dram Type= 6, Freq= 0, CH_0, rank 0
7414 00:45:12.699714 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7415 00:45:12.700230 ==
7416 00:45:12.700580
7417 00:45:12.700884
7418 00:45:12.702824 TX Vref Scan disable
7419 00:45:12.703257 == TX Byte 0 ==
7420 00:45:12.709471 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7421 00:45:12.712749 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7422 00:45:12.713378 == TX Byte 1 ==
7423 00:45:12.719423 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7424 00:45:12.722567 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7425 00:45:12.723001 ==
7426 00:45:12.726258 Dram Type= 6, Freq= 0, CH_0, rank 0
7427 00:45:12.729373 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7428 00:45:12.729938 ==
7429 00:45:12.743149
7430 00:45:12.746360 TX Vref early break, caculate TX vref
7431 00:45:12.749685 TX Vref=16, minBit 8, minWin=22, winSum=369
7432 00:45:12.752960 TX Vref=18, minBit 8, minWin=22, winSum=376
7433 00:45:12.756378 TX Vref=20, minBit 8, minWin=23, winSum=388
7434 00:45:12.759579 TX Vref=22, minBit 10, minWin=23, winSum=398
7435 00:45:12.763013 TX Vref=24, minBit 8, minWin=23, winSum=405
7436 00:45:12.769565 TX Vref=26, minBit 10, minWin=24, winSum=415
7437 00:45:12.772828 TX Vref=28, minBit 4, minWin=25, winSum=416
7438 00:45:12.776129 TX Vref=30, minBit 8, minWin=24, winSum=410
7439 00:45:12.779408 TX Vref=32, minBit 8, minWin=24, winSum=400
7440 00:45:12.782717 TX Vref=34, minBit 3, minWin=24, winSum=394
7441 00:45:12.789251 [TxChooseVref] Worse bit 4, Min win 25, Win sum 416, Final Vref 28
7442 00:45:12.789788
7443 00:45:12.792588 Final TX Range 0 Vref 28
7444 00:45:12.792978
7445 00:45:12.793276 ==
7446 00:45:12.795740 Dram Type= 6, Freq= 0, CH_0, rank 0
7447 00:45:12.799187 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7448 00:45:12.799599 ==
7449 00:45:12.799901
7450 00:45:12.800173
7451 00:45:12.802418 TX Vref Scan disable
7452 00:45:12.809241 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7453 00:45:12.809709 == TX Byte 0 ==
7454 00:45:12.812624 u2DelayCellOfst[0]=10 cells (3 PI)
7455 00:45:12.815905 u2DelayCellOfst[1]=18 cells (5 PI)
7456 00:45:12.819055 u2DelayCellOfst[2]=14 cells (4 PI)
7457 00:45:12.822459 u2DelayCellOfst[3]=10 cells (3 PI)
7458 00:45:12.825702 u2DelayCellOfst[4]=7 cells (2 PI)
7459 00:45:12.829062 u2DelayCellOfst[5]=0 cells (0 PI)
7460 00:45:12.832386 u2DelayCellOfst[6]=18 cells (5 PI)
7461 00:45:12.835825 u2DelayCellOfst[7]=18 cells (5 PI)
7462 00:45:12.839278 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7463 00:45:12.842701 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7464 00:45:12.846184 == TX Byte 1 ==
7465 00:45:12.849165 u2DelayCellOfst[8]=0 cells (0 PI)
7466 00:45:12.849572 u2DelayCellOfst[9]=0 cells (0 PI)
7467 00:45:12.852350 u2DelayCellOfst[10]=10 cells (3 PI)
7468 00:45:12.855653 u2DelayCellOfst[11]=3 cells (1 PI)
7469 00:45:12.858809 u2DelayCellOfst[12]=18 cells (5 PI)
7470 00:45:12.862258 u2DelayCellOfst[13]=14 cells (4 PI)
7471 00:45:12.865913 u2DelayCellOfst[14]=18 cells (5 PI)
7472 00:45:12.868922 u2DelayCellOfst[15]=14 cells (4 PI)
7473 00:45:12.872141 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7474 00:45:12.878746 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7475 00:45:12.879191 DramC Write-DBI on
7476 00:45:12.879775 ==
7477 00:45:12.882107 Dram Type= 6, Freq= 0, CH_0, rank 0
7478 00:45:12.888612 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7479 00:45:12.889068 ==
7480 00:45:12.889414
7481 00:45:12.889730
7482 00:45:12.890286 TX Vref Scan disable
7483 00:45:12.892251 == TX Byte 0 ==
7484 00:45:12.896036 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7485 00:45:12.898981 == TX Byte 1 ==
7486 00:45:12.902353 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7487 00:45:12.905829 DramC Write-DBI off
7488 00:45:12.906527
7489 00:45:12.907004 [DATLAT]
7490 00:45:12.907328 Freq=1600, CH0 RK0
7491 00:45:12.907635
7492 00:45:12.909174 DATLAT Default: 0xf
7493 00:45:12.909594 0, 0xFFFF, sum = 0
7494 00:45:12.912433 1, 0xFFFF, sum = 0
7495 00:45:12.915716 2, 0xFFFF, sum = 0
7496 00:45:12.916110 3, 0xFFFF, sum = 0
7497 00:45:12.919283 4, 0xFFFF, sum = 0
7498 00:45:12.919720 5, 0xFFFF, sum = 0
7499 00:45:12.922303 6, 0xFFFF, sum = 0
7500 00:45:12.922720 7, 0xFFFF, sum = 0
7501 00:45:12.925696 8, 0xFFFF, sum = 0
7502 00:45:12.926132 9, 0xFFFF, sum = 0
7503 00:45:12.928888 10, 0xFFFF, sum = 0
7504 00:45:12.929280 11, 0xFFFF, sum = 0
7505 00:45:12.932100 12, 0xBFF, sum = 0
7506 00:45:12.932500 13, 0x0, sum = 1
7507 00:45:12.935644 14, 0x0, sum = 2
7508 00:45:12.936039 15, 0x0, sum = 3
7509 00:45:12.938773 16, 0x0, sum = 4
7510 00:45:12.939166 best_step = 14
7511 00:45:12.939464
7512 00:45:12.939737 ==
7513 00:45:12.942013 Dram Type= 6, Freq= 0, CH_0, rank 0
7514 00:45:12.945750 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7515 00:45:12.948780 ==
7516 00:45:12.949171 RX Vref Scan: 1
7517 00:45:12.949472
7518 00:45:12.952075 Set Vref Range= 24 -> 127
7519 00:45:12.952488
7520 00:45:12.955528 RX Vref 24 -> 127, step: 1
7521 00:45:12.956008
7522 00:45:12.956316 RX Delay 11 -> 252, step: 4
7523 00:45:12.956730
7524 00:45:12.958668 Set Vref, RX VrefLevel [Byte0]: 24
7525 00:45:12.961907 [Byte1]: 24
7526 00:45:12.966052
7527 00:45:12.966633 Set Vref, RX VrefLevel [Byte0]: 25
7528 00:45:12.969473 [Byte1]: 25
7529 00:45:12.973737
7530 00:45:12.974283 Set Vref, RX VrefLevel [Byte0]: 26
7531 00:45:12.977136 [Byte1]: 26
7532 00:45:12.981079
7533 00:45:12.981516 Set Vref, RX VrefLevel [Byte0]: 27
7534 00:45:12.984603 [Byte1]: 27
7535 00:45:12.988783
7536 00:45:12.989214 Set Vref, RX VrefLevel [Byte0]: 28
7537 00:45:12.991959 [Byte1]: 28
7538 00:45:12.996454
7539 00:45:12.996887 Set Vref, RX VrefLevel [Byte0]: 29
7540 00:45:12.999525 [Byte1]: 29
7541 00:45:13.003929
7542 00:45:13.004415 Set Vref, RX VrefLevel [Byte0]: 30
7543 00:45:13.007110 [Byte1]: 30
7544 00:45:13.011528
7545 00:45:13.012112 Set Vref, RX VrefLevel [Byte0]: 31
7546 00:45:13.014899 [Byte1]: 31
7547 00:45:13.019294
7548 00:45:13.019810 Set Vref, RX VrefLevel [Byte0]: 32
7549 00:45:13.022611 [Byte1]: 32
7550 00:45:13.026766
7551 00:45:13.027197 Set Vref, RX VrefLevel [Byte0]: 33
7552 00:45:13.033475 [Byte1]: 33
7553 00:45:13.033973
7554 00:45:13.036846 Set Vref, RX VrefLevel [Byte0]: 34
7555 00:45:13.040056 [Byte1]: 34
7556 00:45:13.040498
7557 00:45:13.043166 Set Vref, RX VrefLevel [Byte0]: 35
7558 00:45:13.046581 [Byte1]: 35
7559 00:45:13.047029
7560 00:45:13.050198 Set Vref, RX VrefLevel [Byte0]: 36
7561 00:45:13.053141 [Byte1]: 36
7562 00:45:13.057284
7563 00:45:13.057714 Set Vref, RX VrefLevel [Byte0]: 37
7564 00:45:13.060616 [Byte1]: 37
7565 00:45:13.064967
7566 00:45:13.065483 Set Vref, RX VrefLevel [Byte0]: 38
7567 00:45:13.068478 [Byte1]: 38
7568 00:45:13.072826
7569 00:45:13.073369 Set Vref, RX VrefLevel [Byte0]: 39
7570 00:45:13.075847 [Byte1]: 39
7571 00:45:13.080061
7572 00:45:13.080574 Set Vref, RX VrefLevel [Byte0]: 40
7573 00:45:13.083444 [Byte1]: 40
7574 00:45:13.087718
7575 00:45:13.088189 Set Vref, RX VrefLevel [Byte0]: 41
7576 00:45:13.090904 [Byte1]: 41
7577 00:45:13.095536
7578 00:45:13.096047 Set Vref, RX VrefLevel [Byte0]: 42
7579 00:45:13.098926 [Byte1]: 42
7580 00:45:13.103107
7581 00:45:13.103620 Set Vref, RX VrefLevel [Byte0]: 43
7582 00:45:13.106057 [Byte1]: 43
7583 00:45:13.110845
7584 00:45:13.111358 Set Vref, RX VrefLevel [Byte0]: 44
7585 00:45:13.114104 [Byte1]: 44
7586 00:45:13.118310
7587 00:45:13.118833 Set Vref, RX VrefLevel [Byte0]: 45
7588 00:45:13.121571 [Byte1]: 45
7589 00:45:13.125819
7590 00:45:13.126372 Set Vref, RX VrefLevel [Byte0]: 46
7591 00:45:13.128929 [Byte1]: 46
7592 00:45:13.133318
7593 00:45:13.133747 Set Vref, RX VrefLevel [Byte0]: 47
7594 00:45:13.136925 [Byte1]: 47
7595 00:45:13.141298
7596 00:45:13.141819 Set Vref, RX VrefLevel [Byte0]: 48
7597 00:45:13.144753 [Byte1]: 48
7598 00:45:13.148471
7599 00:45:13.148996 Set Vref, RX VrefLevel [Byte0]: 49
7600 00:45:13.151922 [Byte1]: 49
7601 00:45:13.156085
7602 00:45:13.156607 Set Vref, RX VrefLevel [Byte0]: 50
7603 00:45:13.159443 [Byte1]: 50
7604 00:45:13.164030
7605 00:45:13.164545 Set Vref, RX VrefLevel [Byte0]: 51
7606 00:45:13.167181 [Byte1]: 51
7607 00:45:13.171794
7608 00:45:13.172365 Set Vref, RX VrefLevel [Byte0]: 52
7609 00:45:13.175065 [Byte1]: 52
7610 00:45:13.179095
7611 00:45:13.179606 Set Vref, RX VrefLevel [Byte0]: 53
7612 00:45:13.182355 [Byte1]: 53
7613 00:45:13.186809
7614 00:45:13.187237 Set Vref, RX VrefLevel [Byte0]: 54
7615 00:45:13.189884 [Byte1]: 54
7616 00:45:13.194195
7617 00:45:13.194665 Set Vref, RX VrefLevel [Byte0]: 55
7618 00:45:13.198202 [Byte1]: 55
7619 00:45:13.202283
7620 00:45:13.202806 Set Vref, RX VrefLevel [Byte0]: 56
7621 00:45:13.205077 [Byte1]: 56
7622 00:45:13.209778
7623 00:45:13.210240 Set Vref, RX VrefLevel [Byte0]: 57
7624 00:45:13.212785 [Byte1]: 57
7625 00:45:13.217298
7626 00:45:13.217812 Set Vref, RX VrefLevel [Byte0]: 58
7627 00:45:13.220275 [Byte1]: 58
7628 00:45:13.224961
7629 00:45:13.225671 Set Vref, RX VrefLevel [Byte0]: 59
7630 00:45:13.231187 [Byte1]: 59
7631 00:45:13.231690
7632 00:45:13.234448 Set Vref, RX VrefLevel [Byte0]: 60
7633 00:45:13.237685 [Byte1]: 60
7634 00:45:13.238117
7635 00:45:13.241102 Set Vref, RX VrefLevel [Byte0]: 61
7636 00:45:13.244335 [Byte1]: 61
7637 00:45:13.244768
7638 00:45:13.247939 Set Vref, RX VrefLevel [Byte0]: 62
7639 00:45:13.251201 [Byte1]: 62
7640 00:45:13.255054
7641 00:45:13.255487 Set Vref, RX VrefLevel [Byte0]: 63
7642 00:45:13.259012 [Byte1]: 63
7643 00:45:13.262794
7644 00:45:13.263225 Set Vref, RX VrefLevel [Byte0]: 64
7645 00:45:13.266035 [Byte1]: 64
7646 00:45:13.270428
7647 00:45:13.270947 Set Vref, RX VrefLevel [Byte0]: 65
7648 00:45:13.273754 [Byte1]: 65
7649 00:45:13.278137
7650 00:45:13.278709 Set Vref, RX VrefLevel [Byte0]: 66
7651 00:45:13.281305 [Byte1]: 66
7652 00:45:13.285806
7653 00:45:13.286415 Set Vref, RX VrefLevel [Byte0]: 67
7654 00:45:13.288786 [Byte1]: 67
7655 00:45:13.293122
7656 00:45:13.293713 Set Vref, RX VrefLevel [Byte0]: 68
7657 00:45:13.296523 [Byte1]: 68
7658 00:45:13.300924
7659 00:45:13.301537 Set Vref, RX VrefLevel [Byte0]: 69
7660 00:45:13.304120 [Byte1]: 69
7661 00:45:13.308297
7662 00:45:13.308918 Set Vref, RX VrefLevel [Byte0]: 70
7663 00:45:13.311953 [Byte1]: 70
7664 00:45:13.315989
7665 00:45:13.316428 Set Vref, RX VrefLevel [Byte0]: 71
7666 00:45:13.319125 [Byte1]: 71
7667 00:45:13.323628
7668 00:45:13.324061 Final RX Vref Byte 0 = 53 to rank0
7669 00:45:13.326945 Final RX Vref Byte 1 = 56 to rank0
7670 00:45:13.330518 Final RX Vref Byte 0 = 53 to rank1
7671 00:45:13.333936 Final RX Vref Byte 1 = 56 to rank1==
7672 00:45:13.337154 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 00:45:13.343944 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7674 00:45:13.344499 ==
7675 00:45:13.344846 DQS Delay:
7676 00:45:13.345156 DQS0 = 0, DQS1 = 0
7677 00:45:13.346964 DQM Delay:
7678 00:45:13.347401 DQM0 = 127, DQM1 = 121
7679 00:45:13.350118 DQ Delay:
7680 00:45:13.353702 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =122
7681 00:45:13.356889 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7682 00:45:13.360429 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112
7683 00:45:13.363604 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7684 00:45:13.364122
7685 00:45:13.364461
7686 00:45:13.364768
7687 00:45:13.366834 [DramC_TX_OE_Calibration] TA2
7688 00:45:13.370384 Original DQ_B0 (3 6) =30, OEN = 27
7689 00:45:13.373713 Original DQ_B1 (3 6) =30, OEN = 27
7690 00:45:13.376653 24, 0x0, End_B0=24 End_B1=24
7691 00:45:13.377098 25, 0x0, End_B0=25 End_B1=25
7692 00:45:13.380237 26, 0x0, End_B0=26 End_B1=26
7693 00:45:13.383592 27, 0x0, End_B0=27 End_B1=27
7694 00:45:13.386801 28, 0x0, End_B0=28 End_B1=28
7695 00:45:13.390096 29, 0x0, End_B0=29 End_B1=29
7696 00:45:13.390578 30, 0x0, End_B0=30 End_B1=30
7697 00:45:13.393379 31, 0x4545, End_B0=30 End_B1=30
7698 00:45:13.396952 Byte0 end_step=30 best_step=27
7699 00:45:13.399924 Byte1 end_step=30 best_step=27
7700 00:45:13.403214 Byte0 TX OE(2T, 0.5T) = (3, 3)
7701 00:45:13.406539 Byte1 TX OE(2T, 0.5T) = (3, 3)
7702 00:45:13.406971
7703 00:45:13.407301
7704 00:45:13.413218 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7705 00:45:13.416576 CH0 RK0: MR19=303, MR18=1F1F
7706 00:45:13.423259 CH0_RK0: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
7707 00:45:13.423789
7708 00:45:13.426735 ----->DramcWriteLeveling(PI) begin...
7709 00:45:13.427179 ==
7710 00:45:13.429796 Dram Type= 6, Freq= 0, CH_0, rank 1
7711 00:45:13.432840 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7712 00:45:13.433277 ==
7713 00:45:13.436398 Write leveling (Byte 0): 28 => 28
7714 00:45:13.439829 Write leveling (Byte 1): 25 => 25
7715 00:45:13.443081 DramcWriteLeveling(PI) end<-----
7716 00:45:13.443707
7717 00:45:13.444062 ==
7718 00:45:13.446258 Dram Type= 6, Freq= 0, CH_0, rank 1
7719 00:45:13.449766 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7720 00:45:13.450355 ==
7721 00:45:13.453027 [Gating] SW mode calibration
7722 00:45:13.459786 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7723 00:45:13.466364 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7724 00:45:13.470123 0 12 0 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7725 00:45:13.476233 0 12 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7726 00:45:13.479743 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7727 00:45:13.482936 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7728 00:45:13.486257 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7729 00:45:13.492674 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7730 00:45:13.496089 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7731 00:45:13.499463 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7732 00:45:13.505997 0 13 0 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
7733 00:45:13.509198 0 13 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
7734 00:45:13.512784 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7735 00:45:13.519263 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7736 00:45:13.522507 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7737 00:45:13.526083 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7738 00:45:13.532640 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7739 00:45:13.535988 0 13 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7740 00:45:13.539118 0 14 0 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
7741 00:45:13.545991 0 14 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7742 00:45:13.549073 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7743 00:45:13.552464 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7744 00:45:13.559143 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7745 00:45:13.562192 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7746 00:45:13.565569 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7747 00:45:13.572144 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7748 00:45:13.575510 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7749 00:45:13.579002 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7750 00:45:13.585600 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7751 00:45:13.589009 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 00:45:13.591951 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 00:45:13.598683 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 00:45:13.601741 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 00:45:13.605274 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 00:45:13.611636 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 00:45:13.615292 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 00:45:13.618566 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 00:45:13.625363 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 00:45:13.628350 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 00:45:13.631791 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 00:45:13.638343 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7763 00:45:13.641935 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7764 00:45:13.645141 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7765 00:45:13.652096 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7766 00:45:13.652617 Total UI for P1: 0, mck2ui 16
7767 00:45:13.658757 best dqsien dly found for B0: ( 1, 0, 28)
7768 00:45:13.662084 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7769 00:45:13.665057 Total UI for P1: 0, mck2ui 16
7770 00:45:13.668804 best dqsien dly found for B1: ( 1, 1, 4)
7771 00:45:13.671896 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7772 00:45:13.675232 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7773 00:45:13.675746
7774 00:45:13.678584 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7775 00:45:13.681435 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7776 00:45:13.684754 [Gating] SW calibration Done
7777 00:45:13.685190 ==
7778 00:45:13.688458 Dram Type= 6, Freq= 0, CH_0, rank 1
7779 00:45:13.691609 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7780 00:45:13.692051 ==
7781 00:45:13.694859 RX Vref Scan: 0
7782 00:45:13.695294
7783 00:45:13.698565 RX Vref 0 -> 0, step: 1
7784 00:45:13.699082
7785 00:45:13.699423 RX Delay 0 -> 252, step: 8
7786 00:45:13.704761 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7787 00:45:13.708103 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7788 00:45:13.711526 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7789 00:45:13.714431 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7790 00:45:13.717946 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7791 00:45:13.725140 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7792 00:45:13.727790 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7793 00:45:13.731144 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7794 00:45:13.734754 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7795 00:45:13.738356 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7796 00:45:13.744706 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7797 00:45:13.747749 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7798 00:45:13.751034 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7799 00:45:13.754371 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7800 00:45:13.757958 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7801 00:45:13.764535 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7802 00:45:13.765035 ==
7803 00:45:13.768072 Dram Type= 6, Freq= 0, CH_0, rank 1
7804 00:45:13.771126 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7805 00:45:13.771649 ==
7806 00:45:13.771993 DQS Delay:
7807 00:45:13.774493 DQS0 = 0, DQS1 = 0
7808 00:45:13.774924 DQM Delay:
7809 00:45:13.777901 DQM0 = 131, DQM1 = 124
7810 00:45:13.778458 DQ Delay:
7811 00:45:13.781088 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7812 00:45:13.784302 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7813 00:45:13.787446 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7814 00:45:13.794242 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7815 00:45:13.794747
7816 00:45:13.795086
7817 00:45:13.795398 ==
7818 00:45:13.797560 Dram Type= 6, Freq= 0, CH_0, rank 1
7819 00:45:13.800770 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7820 00:45:13.801252 ==
7821 00:45:13.801608
7822 00:45:13.801915
7823 00:45:13.804090 TX Vref Scan disable
7824 00:45:13.804523 == TX Byte 0 ==
7825 00:45:13.810820 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7826 00:45:13.813952 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7827 00:45:13.814430 == TX Byte 1 ==
7828 00:45:13.820538 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7829 00:45:13.824184 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7830 00:45:13.824696 ==
7831 00:45:13.827288 Dram Type= 6, Freq= 0, CH_0, rank 1
7832 00:45:13.830531 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7833 00:45:13.830976 ==
7834 00:45:13.844531
7835 00:45:13.847418 TX Vref early break, caculate TX vref
7836 00:45:13.850780 TX Vref=16, minBit 8, minWin=22, winSum=376
7837 00:45:13.854056 TX Vref=18, minBit 8, minWin=22, winSum=378
7838 00:45:13.857564 TX Vref=20, minBit 8, minWin=23, winSum=389
7839 00:45:13.860899 TX Vref=22, minBit 1, minWin=24, winSum=400
7840 00:45:13.863940 TX Vref=24, minBit 9, minWin=24, winSum=407
7841 00:45:13.870512 TX Vref=26, minBit 1, minWin=25, winSum=414
7842 00:45:13.874253 TX Vref=28, minBit 4, minWin=25, winSum=417
7843 00:45:13.877238 TX Vref=30, minBit 0, minWin=25, winSum=413
7844 00:45:13.880610 TX Vref=32, minBit 8, minWin=23, winSum=407
7845 00:45:13.883870 TX Vref=34, minBit 8, minWin=22, winSum=394
7846 00:45:13.890647 [TxChooseVref] Worse bit 4, Min win 25, Win sum 417, Final Vref 28
7847 00:45:13.891083
7848 00:45:13.893722 Final TX Range 0 Vref 28
7849 00:45:13.894267
7850 00:45:13.894613 ==
7851 00:45:13.897059 Dram Type= 6, Freq= 0, CH_0, rank 1
7852 00:45:13.900691 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7853 00:45:13.901125 ==
7854 00:45:13.901459
7855 00:45:13.901768
7856 00:45:13.903988 TX Vref Scan disable
7857 00:45:13.910206 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7858 00:45:13.910690 == TX Byte 0 ==
7859 00:45:13.913533 u2DelayCellOfst[0]=14 cells (4 PI)
7860 00:45:13.917075 u2DelayCellOfst[1]=18 cells (5 PI)
7861 00:45:13.920235 u2DelayCellOfst[2]=14 cells (4 PI)
7862 00:45:13.923734 u2DelayCellOfst[3]=14 cells (4 PI)
7863 00:45:13.926760 u2DelayCellOfst[4]=7 cells (2 PI)
7864 00:45:13.930055 u2DelayCellOfst[5]=0 cells (0 PI)
7865 00:45:13.933301 u2DelayCellOfst[6]=18 cells (5 PI)
7866 00:45:13.936599 u2DelayCellOfst[7]=18 cells (5 PI)
7867 00:45:13.940177 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7868 00:45:13.943357 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7869 00:45:13.946564 == TX Byte 1 ==
7870 00:45:13.949730 u2DelayCellOfst[8]=3 cells (1 PI)
7871 00:45:13.953354 u2DelayCellOfst[9]=0 cells (0 PI)
7872 00:45:13.953800 u2DelayCellOfst[10]=10 cells (3 PI)
7873 00:45:13.956889 u2DelayCellOfst[11]=7 cells (2 PI)
7874 00:45:13.959918 u2DelayCellOfst[12]=18 cells (5 PI)
7875 00:45:13.963088 u2DelayCellOfst[13]=14 cells (4 PI)
7876 00:45:13.966408 u2DelayCellOfst[14]=21 cells (6 PI)
7877 00:45:13.969859 u2DelayCellOfst[15]=18 cells (5 PI)
7878 00:45:13.976281 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7879 00:45:13.979760 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7880 00:45:13.980191 DramC Write-DBI on
7881 00:45:13.980534 ==
7882 00:45:13.982943 Dram Type= 6, Freq= 0, CH_0, rank 1
7883 00:45:13.989412 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7884 00:45:13.989804 ==
7885 00:45:13.990266
7886 00:45:13.990571
7887 00:45:13.990843 TX Vref Scan disable
7888 00:45:13.993587 == TX Byte 0 ==
7889 00:45:13.997212 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7890 00:45:14.000603 == TX Byte 1 ==
7891 00:45:14.003611 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7892 00:45:14.006992 DramC Write-DBI off
7893 00:45:14.007423
7894 00:45:14.007757 [DATLAT]
7895 00:45:14.008257 Freq=1600, CH0 RK1
7896 00:45:14.008683
7897 00:45:14.010265 DATLAT Default: 0xe
7898 00:45:14.010713 0, 0xFFFF, sum = 0
7899 00:45:14.013593 1, 0xFFFF, sum = 0
7900 00:45:14.014002 2, 0xFFFF, sum = 0
7901 00:45:14.016854 3, 0xFFFF, sum = 0
7902 00:45:14.020208 4, 0xFFFF, sum = 0
7903 00:45:14.020658 5, 0xFFFF, sum = 0
7904 00:45:14.023810 6, 0xFFFF, sum = 0
7905 00:45:14.024309 7, 0xFFFF, sum = 0
7906 00:45:14.026911 8, 0xFFFF, sum = 0
7907 00:45:14.027320 9, 0xFFFF, sum = 0
7908 00:45:14.030607 10, 0xFFFF, sum = 0
7909 00:45:14.031184 11, 0xFFFF, sum = 0
7910 00:45:14.033274 12, 0x8FFF, sum = 0
7911 00:45:14.033685 13, 0x0, sum = 1
7912 00:45:14.036831 14, 0x0, sum = 2
7913 00:45:14.037239 15, 0x0, sum = 3
7914 00:45:14.040074 16, 0x0, sum = 4
7915 00:45:14.040484 best_step = 14
7916 00:45:14.040877
7917 00:45:14.041246 ==
7918 00:45:14.043387 Dram Type= 6, Freq= 0, CH_0, rank 1
7919 00:45:14.046588 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7920 00:45:14.049895 ==
7921 00:45:14.050393 RX Vref Scan: 0
7922 00:45:14.050708
7923 00:45:14.053558 RX Vref 0 -> 0, step: 1
7924 00:45:14.054026
7925 00:45:14.054520 RX Delay 11 -> 252, step: 4
7926 00:45:14.061077 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7927 00:45:14.064466 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7928 00:45:14.067541 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7929 00:45:14.070917 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7930 00:45:14.074164 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7931 00:45:14.080747 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7932 00:45:14.084118 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7933 00:45:14.087308 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7934 00:45:14.090523 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7935 00:45:14.094012 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7936 00:45:14.100651 iDelay=195, Bit 10, Center 120 (67 ~ 174) 108
7937 00:45:14.103849 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7938 00:45:14.107398 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7939 00:45:14.110484 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7940 00:45:14.117425 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7941 00:45:14.120627 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7942 00:45:14.121071 ==
7943 00:45:14.124338 Dram Type= 6, Freq= 0, CH_0, rank 1
7944 00:45:14.127228 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7945 00:45:14.127684 ==
7946 00:45:14.128124 DQS Delay:
7947 00:45:14.130640 DQS0 = 0, DQS1 = 0
7948 00:45:14.131222 DQM Delay:
7949 00:45:14.133806 DQM0 = 129, DQM1 = 120
7950 00:45:14.134352 DQ Delay:
7951 00:45:14.137138 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7952 00:45:14.140592 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7953 00:45:14.143894 DQ8 =108, DQ9 =106, DQ10 =120, DQ11 =112
7954 00:45:14.147186 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7955 00:45:14.150470
7956 00:45:14.150864
7957 00:45:14.151256
7958 00:45:14.151626 [DramC_TX_OE_Calibration] TA2
7959 00:45:14.153883 Original DQ_B0 (3 6) =30, OEN = 27
7960 00:45:14.157568 Original DQ_B1 (3 6) =30, OEN = 27
7961 00:45:14.160797 24, 0x0, End_B0=24 End_B1=24
7962 00:45:14.164075 25, 0x0, End_B0=25 End_B1=25
7963 00:45:14.167088 26, 0x0, End_B0=26 End_B1=26
7964 00:45:14.167556 27, 0x0, End_B0=27 End_B1=27
7965 00:45:14.170417 28, 0x0, End_B0=28 End_B1=28
7966 00:45:14.173935 29, 0x0, End_B0=29 End_B1=29
7967 00:45:14.176943 30, 0x0, End_B0=30 End_B1=30
7968 00:45:14.180242 31, 0x5151, End_B0=30 End_B1=30
7969 00:45:14.180842 Byte0 end_step=30 best_step=27
7970 00:45:14.183503 Byte1 end_step=30 best_step=27
7971 00:45:14.187374 Byte0 TX OE(2T, 0.5T) = (3, 3)
7972 00:45:14.190486 Byte1 TX OE(2T, 0.5T) = (3, 3)
7973 00:45:14.190879
7974 00:45:14.191179
7975 00:45:14.200418 [DQSOSCAuto] RK1, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
7976 00:45:14.200874 CH0 RK1: MR19=303, MR18=2626
7977 00:45:14.206877 CH0_RK1: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
7978 00:45:14.210385 [RxdqsGatingPostProcess] freq 1600
7979 00:45:14.217221 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7980 00:45:14.220304 Pre-setting of DQS Precalculation
7981 00:45:14.223949 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7982 00:45:14.224343 ==
7983 00:45:14.227059 Dram Type= 6, Freq= 0, CH_1, rank 0
7984 00:45:14.230192 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7985 00:45:14.233787 ==
7986 00:45:14.236938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7987 00:45:14.240344 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7988 00:45:14.246929 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7989 00:45:14.250124 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7990 00:45:14.259646 [CA 0] Center 41 (11~71) winsize 61
7991 00:45:14.262981 [CA 1] Center 40 (10~71) winsize 62
7992 00:45:14.266143 [CA 2] Center 36 (7~66) winsize 60
7993 00:45:14.269606 [CA 3] Center 36 (7~65) winsize 59
7994 00:45:14.273104 [CA 4] Center 34 (4~64) winsize 61
7995 00:45:14.275918 [CA 5] Center 34 (4~64) winsize 61
7996 00:45:14.276522
7997 00:45:14.279205 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7998 00:45:14.279598
7999 00:45:14.286080 [CATrainingPosCal] consider 1 rank data
8000 00:45:14.286555 u2DelayCellTimex100 = 271/100 ps
8001 00:45:14.292563 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8002 00:45:14.295987 CA1 delay=40 (10~71),Diff = 6 PI (21 cell)
8003 00:45:14.299079 CA2 delay=36 (7~66),Diff = 2 PI (7 cell)
8004 00:45:14.302415 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8005 00:45:14.305633 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8006 00:45:14.309154 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8007 00:45:14.309629
8008 00:45:14.312293 CA PerBit enable=1, Macro0, CA PI delay=34
8009 00:45:14.312729
8010 00:45:14.315852 [CBTSetCACLKResult] CA Dly = 34
8011 00:45:14.318937 CS Dly: 8 (0~39)
8012 00:45:14.322287 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8013 00:45:14.325478 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8014 00:45:14.325910 ==
8015 00:45:14.328907 Dram Type= 6, Freq= 0, CH_1, rank 1
8016 00:45:14.335570 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8017 00:45:14.336008 ==
8018 00:45:14.338764 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8019 00:45:14.342471 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8020 00:45:14.349301 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8021 00:45:14.355292 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8022 00:45:14.362295 [CA 0] Center 40 (10~70) winsize 61
8023 00:45:14.365510 [CA 1] Center 39 (9~70) winsize 62
8024 00:45:14.368565 [CA 2] Center 35 (6~65) winsize 60
8025 00:45:14.372010 [CA 3] Center 35 (6~65) winsize 60
8026 00:45:14.375140 [CA 4] Center 33 (3~63) winsize 61
8027 00:45:14.378645 [CA 5] Center 33 (3~63) winsize 61
8028 00:45:14.379157
8029 00:45:14.381946 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8030 00:45:14.382506
8031 00:45:14.385088 [CATrainingPosCal] consider 2 rank data
8032 00:45:14.388322 u2DelayCellTimex100 = 271/100 ps
8033 00:45:14.391786 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8034 00:45:14.398583 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8035 00:45:14.401680 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8036 00:45:14.405147 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8037 00:45:14.408326 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8038 00:45:14.411815 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8039 00:45:14.412332
8040 00:45:14.414903 CA PerBit enable=1, Macro0, CA PI delay=33
8041 00:45:14.415330
8042 00:45:14.418327 [CBTSetCACLKResult] CA Dly = 33
8043 00:45:14.421539 CS Dly: 9 (0~41)
8044 00:45:14.425000 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8045 00:45:14.428184 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8046 00:45:14.428619
8047 00:45:14.431917 ----->DramcWriteLeveling(PI) begin...
8048 00:45:14.432467 ==
8049 00:45:14.434854 Dram Type= 6, Freq= 0, CH_1, rank 0
8050 00:45:14.438180 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8051 00:45:14.441747 ==
8052 00:45:14.444782 Write leveling (Byte 0): 22 => 22
8053 00:45:14.445213 Write leveling (Byte 1): 22 => 22
8054 00:45:14.448497 DramcWriteLeveling(PI) end<-----
8055 00:45:14.449017
8056 00:45:14.449353 ==
8057 00:45:14.451520 Dram Type= 6, Freq= 0, CH_1, rank 0
8058 00:45:14.458411 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8059 00:45:14.458931 ==
8060 00:45:14.461604 [Gating] SW mode calibration
8061 00:45:14.468086 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8062 00:45:14.471317 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8063 00:45:14.477757 0 12 0 | B1->B0 | 2f2f 3434 | 0 1 | (1 1) (1 1)
8064 00:45:14.481320 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 00:45:14.484546 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 00:45:14.491456 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 00:45:14.494687 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 00:45:14.497858 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 00:45:14.504597 0 12 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
8070 00:45:14.507955 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8071 00:45:14.511136 0 13 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
8072 00:45:14.514379 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8073 00:45:14.521404 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 00:45:14.524911 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 00:45:14.527628 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 00:45:14.534283 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 00:45:14.537564 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 00:45:14.541204 0 13 28 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8079 00:45:14.547457 0 14 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8080 00:45:14.551022 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 00:45:14.554446 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 00:45:14.561026 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 00:45:14.564140 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 00:45:14.567708 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 00:45:14.574360 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 00:45:14.577220 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8087 00:45:14.580682 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8088 00:45:14.587433 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8089 00:45:14.590663 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 00:45:14.593697 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 00:45:14.600416 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 00:45:14.603807 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 00:45:14.607114 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 00:45:14.613941 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 00:45:14.617130 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 00:45:14.620349 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 00:45:14.627052 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 00:45:14.630338 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 00:45:14.633780 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 00:45:14.640274 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 00:45:14.643617 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8102 00:45:14.646849 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8103 00:45:14.650526 Total UI for P1: 0, mck2ui 16
8104 00:45:14.653729 best dqsien dly found for B0: ( 1, 0, 24)
8105 00:45:14.660697 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8106 00:45:14.663697 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8107 00:45:14.666903 Total UI for P1: 0, mck2ui 16
8108 00:45:14.670526 best dqsien dly found for B1: ( 1, 0, 30)
8109 00:45:14.673673 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8110 00:45:14.677077 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8111 00:45:14.677609
8112 00:45:14.680157 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8113 00:45:14.683761 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8114 00:45:14.686996 [Gating] SW calibration Done
8115 00:45:14.687426 ==
8116 00:45:14.690023 Dram Type= 6, Freq= 0, CH_1, rank 0
8117 00:45:14.693736 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8118 00:45:14.696683 ==
8119 00:45:14.697177 RX Vref Scan: 0
8120 00:45:14.697508
8121 00:45:14.700141 RX Vref 0 -> 0, step: 1
8122 00:45:14.700575
8123 00:45:14.700905 RX Delay 0 -> 252, step: 8
8124 00:45:14.706766 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8125 00:45:14.710110 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8126 00:45:14.713479 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8127 00:45:14.716482 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8128 00:45:14.720175 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8129 00:45:14.726708 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8130 00:45:14.730047 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8131 00:45:14.733409 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8132 00:45:14.736841 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8133 00:45:14.740239 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8134 00:45:14.746537 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8135 00:45:14.750324 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8136 00:45:14.753355 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8137 00:45:14.756676 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8138 00:45:14.763060 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8139 00:45:14.766315 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8140 00:45:14.766747 ==
8141 00:45:14.769693 Dram Type= 6, Freq= 0, CH_1, rank 0
8142 00:45:14.773082 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8143 00:45:14.773512 ==
8144 00:45:14.773895 DQS Delay:
8145 00:45:14.776468 DQS0 = 0, DQS1 = 0
8146 00:45:14.776893 DQM Delay:
8147 00:45:14.779682 DQM0 = 130, DQM1 = 126
8148 00:45:14.780107 DQ Delay:
8149 00:45:14.783178 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8150 00:45:14.786583 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8151 00:45:14.789641 DQ8 =107, DQ9 =119, DQ10 =127, DQ11 =115
8152 00:45:14.796305 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8153 00:45:14.796735
8154 00:45:14.797063
8155 00:45:14.797367 ==
8156 00:45:14.799665 Dram Type= 6, Freq= 0, CH_1, rank 0
8157 00:45:14.803340 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8158 00:45:14.803877 ==
8159 00:45:14.804219
8160 00:45:14.804540
8161 00:45:14.806264 TX Vref Scan disable
8162 00:45:14.806693 == TX Byte 0 ==
8163 00:45:14.813010 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8164 00:45:14.816066 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8165 00:45:14.816631 == TX Byte 1 ==
8166 00:45:14.822964 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8167 00:45:14.826129 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8168 00:45:14.826602 ==
8169 00:45:14.829674 Dram Type= 6, Freq= 0, CH_1, rank 0
8170 00:45:14.832914 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8171 00:45:14.833429 ==
8172 00:45:14.846966
8173 00:45:14.850382 TX Vref early break, caculate TX vref
8174 00:45:14.853646 TX Vref=16, minBit 0, minWin=21, winSum=366
8175 00:45:14.856945 TX Vref=18, minBit 0, minWin=23, winSum=379
8176 00:45:14.859969 TX Vref=20, minBit 3, minWin=22, winSum=384
8177 00:45:14.863269 TX Vref=22, minBit 1, minWin=23, winSum=393
8178 00:45:14.866798 TX Vref=24, minBit 0, minWin=24, winSum=403
8179 00:45:14.873403 TX Vref=26, minBit 0, minWin=24, winSum=408
8180 00:45:14.876938 TX Vref=28, minBit 3, minWin=24, winSum=408
8181 00:45:14.880028 TX Vref=30, minBit 3, minWin=24, winSum=404
8182 00:45:14.883324 TX Vref=32, minBit 3, minWin=23, winSum=397
8183 00:45:14.886575 TX Vref=34, minBit 3, minWin=22, winSum=387
8184 00:45:14.890014 TX Vref=36, minBit 1, minWin=22, winSum=379
8185 00:45:14.896304 [TxChooseVref] Worse bit 0, Min win 24, Win sum 408, Final Vref 26
8186 00:45:14.896782
8187 00:45:14.899553 Final TX Range 0 Vref 26
8188 00:45:14.899981
8189 00:45:14.900309 ==
8190 00:45:14.903092 Dram Type= 6, Freq= 0, CH_1, rank 0
8191 00:45:14.906169 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8192 00:45:14.906669 ==
8193 00:45:14.907007
8194 00:45:14.909483
8195 00:45:14.909868 TX Vref Scan disable
8196 00:45:14.916196 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8197 00:45:14.916719 == TX Byte 0 ==
8198 00:45:14.919433 u2DelayCellOfst[0]=18 cells (5 PI)
8199 00:45:14.922807 u2DelayCellOfst[1]=14 cells (4 PI)
8200 00:45:14.926600 u2DelayCellOfst[2]=0 cells (0 PI)
8201 00:45:14.929312 u2DelayCellOfst[3]=7 cells (2 PI)
8202 00:45:14.932876 u2DelayCellOfst[4]=10 cells (3 PI)
8203 00:45:14.936324 u2DelayCellOfst[5]=18 cells (5 PI)
8204 00:45:14.939599 u2DelayCellOfst[6]=18 cells (5 PI)
8205 00:45:14.942755 u2DelayCellOfst[7]=7 cells (2 PI)
8206 00:45:14.945907 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8207 00:45:14.949500 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8208 00:45:14.952559 == TX Byte 1 ==
8209 00:45:14.956115 u2DelayCellOfst[8]=0 cells (0 PI)
8210 00:45:14.959157 u2DelayCellOfst[9]=7 cells (2 PI)
8211 00:45:14.962837 u2DelayCellOfst[10]=10 cells (3 PI)
8212 00:45:14.963268 u2DelayCellOfst[11]=3 cells (1 PI)
8213 00:45:14.965916 u2DelayCellOfst[12]=18 cells (5 PI)
8214 00:45:14.969580 u2DelayCellOfst[13]=21 cells (6 PI)
8215 00:45:14.972520 u2DelayCellOfst[14]=21 cells (6 PI)
8216 00:45:14.975778 u2DelayCellOfst[15]=18 cells (5 PI)
8217 00:45:14.982489 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8218 00:45:14.985983 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8219 00:45:14.986576 DramC Write-DBI on
8220 00:45:14.989180 ==
8221 00:45:14.992187 Dram Type= 6, Freq= 0, CH_1, rank 0
8222 00:45:14.995536 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8223 00:45:14.995985 ==
8224 00:45:14.996318
8225 00:45:14.996624
8226 00:45:14.998958 TX Vref Scan disable
8227 00:45:14.999384 == TX Byte 0 ==
8228 00:45:15.006096 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8229 00:45:15.006659 == TX Byte 1 ==
8230 00:45:15.008824 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8231 00:45:15.012181 DramC Write-DBI off
8232 00:45:15.012608
8233 00:45:15.012944 [DATLAT]
8234 00:45:15.015662 Freq=1600, CH1 RK0
8235 00:45:15.016088
8236 00:45:15.016420 DATLAT Default: 0xf
8237 00:45:15.018743 0, 0xFFFF, sum = 0
8238 00:45:15.019180 1, 0xFFFF, sum = 0
8239 00:45:15.022002 2, 0xFFFF, sum = 0
8240 00:45:15.022493 3, 0xFFFF, sum = 0
8241 00:45:15.025137 4, 0xFFFF, sum = 0
8242 00:45:15.025583 5, 0xFFFF, sum = 0
8243 00:45:15.028753 6, 0xFFFF, sum = 0
8244 00:45:15.029281 7, 0xFFFF, sum = 0
8245 00:45:15.031877 8, 0xFFFF, sum = 0
8246 00:45:15.032325 9, 0xFFFF, sum = 0
8247 00:45:15.035569 10, 0xFFFF, sum = 0
8248 00:45:15.038443 11, 0xFFFF, sum = 0
8249 00:45:15.038886 12, 0x8FFF, sum = 0
8250 00:45:15.042074 13, 0x0, sum = 1
8251 00:45:15.042645 14, 0x0, sum = 2
8252 00:45:15.045165 15, 0x0, sum = 3
8253 00:45:15.045607 16, 0x0, sum = 4
8254 00:45:15.046018 best_step = 14
8255 00:45:15.046518
8256 00:45:15.048580 ==
8257 00:45:15.052011 Dram Type= 6, Freq= 0, CH_1, rank 0
8258 00:45:15.054985 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8259 00:45:15.055425 ==
8260 00:45:15.055760 RX Vref Scan: 1
8261 00:45:15.056077
8262 00:45:15.058542 Set Vref Range= 24 -> 127
8263 00:45:15.058976
8264 00:45:15.061525 RX Vref 24 -> 127, step: 1
8265 00:45:15.061960
8266 00:45:15.065143 RX Delay 3 -> 252, step: 4
8267 00:45:15.065669
8268 00:45:15.068370 Set Vref, RX VrefLevel [Byte0]: 24
8269 00:45:15.071369 [Byte1]: 24
8270 00:45:15.071816
8271 00:45:15.074654 Set Vref, RX VrefLevel [Byte0]: 25
8272 00:45:15.078480 [Byte1]: 25
8273 00:45:15.078993
8274 00:45:15.081476 Set Vref, RX VrefLevel [Byte0]: 26
8275 00:45:15.084708 [Byte1]: 26
8276 00:45:15.088722
8277 00:45:15.089232 Set Vref, RX VrefLevel [Byte0]: 27
8278 00:45:15.091688 [Byte1]: 27
8279 00:45:15.096280
8280 00:45:15.096794 Set Vref, RX VrefLevel [Byte0]: 28
8281 00:45:15.099307 [Byte1]: 28
8282 00:45:15.103711
8283 00:45:15.104231 Set Vref, RX VrefLevel [Byte0]: 29
8284 00:45:15.107232 [Byte1]: 29
8285 00:45:15.111417
8286 00:45:15.114692 Set Vref, RX VrefLevel [Byte0]: 30
8287 00:45:15.118026 [Byte1]: 30
8288 00:45:15.118509
8289 00:45:15.121363 Set Vref, RX VrefLevel [Byte0]: 31
8290 00:45:15.124531 [Byte1]: 31
8291 00:45:15.124967
8292 00:45:15.128119 Set Vref, RX VrefLevel [Byte0]: 32
8293 00:45:15.131190 [Byte1]: 32
8294 00:45:15.134190
8295 00:45:15.134666 Set Vref, RX VrefLevel [Byte0]: 33
8296 00:45:15.138724 [Byte1]: 33
8297 00:45:15.142004
8298 00:45:15.142482 Set Vref, RX VrefLevel [Byte0]: 34
8299 00:45:15.145267 [Byte1]: 34
8300 00:45:15.149576
8301 00:45:15.149962 Set Vref, RX VrefLevel [Byte0]: 35
8302 00:45:15.153072 [Byte1]: 35
8303 00:45:15.157477
8304 00:45:15.157755 Set Vref, RX VrefLevel [Byte0]: 36
8305 00:45:15.160440 [Byte1]: 36
8306 00:45:15.164875
8307 00:45:15.165226 Set Vref, RX VrefLevel [Byte0]: 37
8308 00:45:15.168309 [Byte1]: 37
8309 00:45:15.172777
8310 00:45:15.173136 Set Vref, RX VrefLevel [Byte0]: 38
8311 00:45:15.175974 [Byte1]: 38
8312 00:45:15.180371
8313 00:45:15.180726 Set Vref, RX VrefLevel [Byte0]: 39
8314 00:45:15.183530 [Byte1]: 39
8315 00:45:15.187648
8316 00:45:15.187956 Set Vref, RX VrefLevel [Byte0]: 40
8317 00:45:15.191142 [Byte1]: 40
8318 00:45:15.195476
8319 00:45:15.195753 Set Vref, RX VrefLevel [Byte0]: 41
8320 00:45:15.198826 [Byte1]: 41
8321 00:45:15.203365
8322 00:45:15.203796 Set Vref, RX VrefLevel [Byte0]: 42
8323 00:45:15.206620 [Byte1]: 42
8324 00:45:15.211112
8325 00:45:15.211628 Set Vref, RX VrefLevel [Byte0]: 43
8326 00:45:15.214315 [Byte1]: 43
8327 00:45:15.218677
8328 00:45:15.219106 Set Vref, RX VrefLevel [Byte0]: 44
8329 00:45:15.222276 [Byte1]: 44
8330 00:45:15.226526
8331 00:45:15.227042 Set Vref, RX VrefLevel [Byte0]: 45
8332 00:45:15.229778 [Byte1]: 45
8333 00:45:15.234005
8334 00:45:15.234485 Set Vref, RX VrefLevel [Byte0]: 46
8335 00:45:15.237459 [Byte1]: 46
8336 00:45:15.241761
8337 00:45:15.242324 Set Vref, RX VrefLevel [Byte0]: 47
8338 00:45:15.245059 [Byte1]: 47
8339 00:45:15.249477
8340 00:45:15.249986 Set Vref, RX VrefLevel [Byte0]: 48
8341 00:45:15.252660 [Byte1]: 48
8342 00:45:15.256924
8343 00:45:15.257356 Set Vref, RX VrefLevel [Byte0]: 49
8344 00:45:15.260508 [Byte1]: 49
8345 00:45:15.264699
8346 00:45:15.265208 Set Vref, RX VrefLevel [Byte0]: 50
8347 00:45:15.267706 [Byte1]: 50
8348 00:45:15.272434
8349 00:45:15.272968 Set Vref, RX VrefLevel [Byte0]: 51
8350 00:45:15.275635 [Byte1]: 51
8351 00:45:15.280000
8352 00:45:15.280510 Set Vref, RX VrefLevel [Byte0]: 52
8353 00:45:15.283006 [Byte1]: 52
8354 00:45:15.287695
8355 00:45:15.288208 Set Vref, RX VrefLevel [Byte0]: 53
8356 00:45:15.291196 [Byte1]: 53
8357 00:45:15.295316
8358 00:45:15.295833 Set Vref, RX VrefLevel [Byte0]: 54
8359 00:45:15.298441 [Byte1]: 54
8360 00:45:15.302872
8361 00:45:15.303381 Set Vref, RX VrefLevel [Byte0]: 55
8362 00:45:15.306178 [Byte1]: 55
8363 00:45:15.310531
8364 00:45:15.310965 Set Vref, RX VrefLevel [Byte0]: 56
8365 00:45:15.313851 [Byte1]: 56
8366 00:45:15.318267
8367 00:45:15.318793 Set Vref, RX VrefLevel [Byte0]: 57
8368 00:45:15.321528 [Byte1]: 57
8369 00:45:15.325706
8370 00:45:15.326401 Set Vref, RX VrefLevel [Byte0]: 58
8371 00:45:15.328882 [Byte1]: 58
8372 00:45:15.333444
8373 00:45:15.333879 Set Vref, RX VrefLevel [Byte0]: 59
8374 00:45:15.336838 [Byte1]: 59
8375 00:45:15.340903
8376 00:45:15.341439 Set Vref, RX VrefLevel [Byte0]: 60
8377 00:45:15.344763 [Byte1]: 60
8378 00:45:15.348775
8379 00:45:15.349201 Set Vref, RX VrefLevel [Byte0]: 61
8380 00:45:15.352233 [Byte1]: 61
8381 00:45:15.356346
8382 00:45:15.356785 Set Vref, RX VrefLevel [Byte0]: 62
8383 00:45:15.359544 [Byte1]: 62
8384 00:45:15.364187
8385 00:45:15.364621 Set Vref, RX VrefLevel [Byte0]: 63
8386 00:45:15.367435 [Byte1]: 63
8387 00:45:15.371797
8388 00:45:15.372254 Set Vref, RX VrefLevel [Byte0]: 64
8389 00:45:15.374853 [Byte1]: 64
8390 00:45:15.379366
8391 00:45:15.379887 Set Vref, RX VrefLevel [Byte0]: 65
8392 00:45:15.382785 [Byte1]: 65
8393 00:45:15.386912
8394 00:45:15.387343 Set Vref, RX VrefLevel [Byte0]: 66
8395 00:45:15.390340 [Byte1]: 66
8396 00:45:15.394588
8397 00:45:15.395033 Set Vref, RX VrefLevel [Byte0]: 67
8398 00:45:15.397733 [Byte1]: 67
8399 00:45:15.402266
8400 00:45:15.402703 Set Vref, RX VrefLevel [Byte0]: 68
8401 00:45:15.405342 [Byte1]: 68
8402 00:45:15.409801
8403 00:45:15.410263 Set Vref, RX VrefLevel [Byte0]: 69
8404 00:45:15.413514 [Byte1]: 69
8405 00:45:15.417628
8406 00:45:15.418040 Set Vref, RX VrefLevel [Byte0]: 70
8407 00:45:15.420798 [Byte1]: 70
8408 00:45:15.425532
8409 00:45:15.426052 Set Vref, RX VrefLevel [Byte0]: 71
8410 00:45:15.429128 [Byte1]: 71
8411 00:45:15.432968
8412 00:45:15.433402 Set Vref, RX VrefLevel [Byte0]: 72
8413 00:45:15.436215 [Byte1]: 72
8414 00:45:15.440692
8415 00:45:15.441207 Set Vref, RX VrefLevel [Byte0]: 73
8416 00:45:15.443760 [Byte1]: 73
8417 00:45:15.448232
8418 00:45:15.448746 Set Vref, RX VrefLevel [Byte0]: 74
8419 00:45:15.451718 [Byte1]: 74
8420 00:45:15.456082
8421 00:45:15.456613 Set Vref, RX VrefLevel [Byte0]: 75
8422 00:45:15.459173 [Byte1]: 75
8423 00:45:15.463672
8424 00:45:15.464183 Final RX Vref Byte 0 = 62 to rank0
8425 00:45:15.466839 Final RX Vref Byte 1 = 54 to rank0
8426 00:45:15.469906 Final RX Vref Byte 0 = 62 to rank1
8427 00:45:15.473363 Final RX Vref Byte 1 = 54 to rank1==
8428 00:45:15.476574 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 00:45:15.483253 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8430 00:45:15.483653 ==
8431 00:45:15.483972 DQS Delay:
8432 00:45:15.486651 DQS0 = 0, DQS1 = 0
8433 00:45:15.487043 DQM Delay:
8434 00:45:15.487348 DQM0 = 128, DQM1 = 123
8435 00:45:15.489904 DQ Delay:
8436 00:45:15.493075 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =126
8437 00:45:15.496312 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =126
8438 00:45:15.499835 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =114
8439 00:45:15.503001 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8440 00:45:15.503486
8441 00:45:15.503794
8442 00:45:15.504078
8443 00:45:15.506416 [DramC_TX_OE_Calibration] TA2
8444 00:45:15.509572 Original DQ_B0 (3 6) =30, OEN = 27
8445 00:45:15.512794 Original DQ_B1 (3 6) =30, OEN = 27
8446 00:45:15.516067 24, 0x0, End_B0=24 End_B1=24
8447 00:45:15.519367 25, 0x0, End_B0=25 End_B1=25
8448 00:45:15.519778 26, 0x0, End_B0=26 End_B1=26
8449 00:45:15.522768 27, 0x0, End_B0=27 End_B1=27
8450 00:45:15.526039 28, 0x0, End_B0=28 End_B1=28
8451 00:45:15.529655 29, 0x0, End_B0=29 End_B1=29
8452 00:45:15.530133 30, 0x0, End_B0=30 End_B1=30
8453 00:45:15.532993 31, 0x4545, End_B0=30 End_B1=30
8454 00:45:15.536027 Byte0 end_step=30 best_step=27
8455 00:45:15.539359 Byte1 end_step=30 best_step=27
8456 00:45:15.542796 Byte0 TX OE(2T, 0.5T) = (3, 3)
8457 00:45:15.546375 Byte1 TX OE(2T, 0.5T) = (3, 3)
8458 00:45:15.546893
8459 00:45:15.547227
8460 00:45:15.552707 [DQSOSCAuto] RK0, (LSB)MR18= 0x2828, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8461 00:45:15.556103 CH1 RK0: MR19=303, MR18=2828
8462 00:45:15.562884 CH1_RK0: MR19=0x303, MR18=0x2828, DQSOSC=389, MR23=63, INC=24, DEC=16
8463 00:45:15.563383
8464 00:45:15.566255 ----->DramcWriteLeveling(PI) begin...
8465 00:45:15.566920 ==
8466 00:45:15.569369 Dram Type= 6, Freq= 0, CH_1, rank 1
8467 00:45:15.572927 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8468 00:45:15.573356 ==
8469 00:45:15.576080 Write leveling (Byte 0): 22 => 22
8470 00:45:15.579622 Write leveling (Byte 1): 19 => 19
8471 00:45:15.582910 DramcWriteLeveling(PI) end<-----
8472 00:45:15.583341
8473 00:45:15.583672 ==
8474 00:45:15.586388 Dram Type= 6, Freq= 0, CH_1, rank 1
8475 00:45:15.589443 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8476 00:45:15.589873 ==
8477 00:45:15.592770 [Gating] SW mode calibration
8478 00:45:15.599521 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8479 00:45:15.606059 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8480 00:45:15.609220 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8481 00:45:15.615696 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8482 00:45:15.619189 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8483 00:45:15.622623 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8484 00:45:15.629249 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8485 00:45:15.632561 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8486 00:45:15.635822 0 12 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8487 00:45:15.642268 0 12 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8488 00:45:15.645857 0 13 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8489 00:45:15.649121 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8490 00:45:15.652265 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8491 00:45:15.658910 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8492 00:45:15.662334 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8493 00:45:15.665818 0 13 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8494 00:45:15.672186 0 13 24 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8495 00:45:15.675668 0 13 28 | B1->B0 | 2423 4646 | 1 0 | (0 0) (0 0)
8496 00:45:15.678727 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8497 00:45:15.685443 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8498 00:45:15.688690 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8499 00:45:15.691959 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8500 00:45:15.698467 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8501 00:45:15.701817 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8502 00:45:15.705143 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8503 00:45:15.711658 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8504 00:45:15.715010 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 00:45:15.718592 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 00:45:15.724861 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 00:45:15.728346 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 00:45:15.731580 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 00:45:15.738265 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 00:45:15.741465 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 00:45:15.744687 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 00:45:15.751371 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 00:45:15.754922 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 00:45:15.757907 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8515 00:45:15.764826 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8516 00:45:15.768143 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8517 00:45:15.771096 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8518 00:45:15.778020 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8519 00:45:15.781236 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8520 00:45:15.784732 Total UI for P1: 0, mck2ui 16
8521 00:45:15.787713 best dqsien dly found for B0: ( 1, 0, 24)
8522 00:45:15.790927 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8523 00:45:15.794289 Total UI for P1: 0, mck2ui 16
8524 00:45:15.797465 best dqsien dly found for B1: ( 1, 0, 28)
8525 00:45:15.800929 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8526 00:45:15.804103 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8527 00:45:15.807607
8528 00:45:15.811019 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8529 00:45:15.814143 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8530 00:45:15.817687 [Gating] SW calibration Done
8531 00:45:15.818256 ==
8532 00:45:15.820471 Dram Type= 6, Freq= 0, CH_1, rank 1
8533 00:45:15.823917 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8534 00:45:15.824517 ==
8535 00:45:15.824861 RX Vref Scan: 0
8536 00:45:15.827693
8537 00:45:15.828222 RX Vref 0 -> 0, step: 1
8538 00:45:15.828687
8539 00:45:15.830690 RX Delay 0 -> 252, step: 8
8540 00:45:15.833890 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8541 00:45:15.837297 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8542 00:45:15.843681 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8543 00:45:15.846936 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8544 00:45:15.850487 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8545 00:45:15.854318 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8546 00:45:15.857075 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8547 00:45:15.863815 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8548 00:45:15.866785 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8549 00:45:15.870378 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8550 00:45:15.873748 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8551 00:45:15.877005 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8552 00:45:15.883575 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8553 00:45:15.886919 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8554 00:45:15.890670 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8555 00:45:15.893439 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8556 00:45:15.893870 ==
8557 00:45:15.896884 Dram Type= 6, Freq= 0, CH_1, rank 1
8558 00:45:15.903282 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8559 00:45:15.903780 ==
8560 00:45:15.904113 DQS Delay:
8561 00:45:15.906764 DQS0 = 0, DQS1 = 0
8562 00:45:15.907192 DQM Delay:
8563 00:45:15.909739 DQM0 = 130, DQM1 = 124
8564 00:45:15.910165 DQ Delay:
8565 00:45:15.913003 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =127
8566 00:45:15.916832 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =127
8567 00:45:15.919988 DQ8 =107, DQ9 =111, DQ10 =127, DQ11 =115
8568 00:45:15.922950 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8569 00:45:15.923385
8570 00:45:15.923716
8571 00:45:15.924020 ==
8572 00:45:15.926308 Dram Type= 6, Freq= 0, CH_1, rank 1
8573 00:45:15.933309 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8574 00:45:15.933834 ==
8575 00:45:15.934177
8576 00:45:15.934532
8577 00:45:15.934831 TX Vref Scan disable
8578 00:45:15.936244 == TX Byte 0 ==
8579 00:45:15.939506 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8580 00:45:15.946763 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8581 00:45:15.947421 == TX Byte 1 ==
8582 00:45:15.949613 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8583 00:45:15.956250 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8584 00:45:15.956681 ==
8585 00:45:15.959516 Dram Type= 6, Freq= 0, CH_1, rank 1
8586 00:45:15.962662 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8587 00:45:15.963098 ==
8588 00:45:15.976415
8589 00:45:15.979534 TX Vref early break, caculate TX vref
8590 00:45:15.982914 TX Vref=16, minBit 0, minWin=22, winSum=383
8591 00:45:15.986454 TX Vref=18, minBit 6, minWin=22, winSum=391
8592 00:45:15.989670 TX Vref=20, minBit 7, minWin=23, winSum=399
8593 00:45:15.992638 TX Vref=22, minBit 0, minWin=25, winSum=409
8594 00:45:15.995907 TX Vref=24, minBit 3, minWin=24, winSum=411
8595 00:45:16.002811 TX Vref=26, minBit 0, minWin=25, winSum=422
8596 00:45:16.005807 TX Vref=28, minBit 2, minWin=24, winSum=421
8597 00:45:16.009269 TX Vref=30, minBit 0, minWin=25, winSum=422
8598 00:45:16.012350 TX Vref=32, minBit 0, minWin=24, winSum=413
8599 00:45:16.016212 TX Vref=34, minBit 0, minWin=23, winSum=404
8600 00:45:16.019060 TX Vref=36, minBit 0, minWin=23, winSum=393
8601 00:45:16.025914 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
8602 00:45:16.026396
8603 00:45:16.029226 Final TX Range 0 Vref 26
8604 00:45:16.029655
8605 00:45:16.029987 ==
8606 00:45:16.032402 Dram Type= 6, Freq= 0, CH_1, rank 1
8607 00:45:16.035532 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8608 00:45:16.035963 ==
8609 00:45:16.038961
8610 00:45:16.039388
8611 00:45:16.039717 TX Vref Scan disable
8612 00:45:16.045529 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8613 00:45:16.045962 == TX Byte 0 ==
8614 00:45:16.048739 u2DelayCellOfst[0]=18 cells (5 PI)
8615 00:45:16.052240 u2DelayCellOfst[1]=10 cells (3 PI)
8616 00:45:16.055444 u2DelayCellOfst[2]=0 cells (0 PI)
8617 00:45:16.058953 u2DelayCellOfst[3]=7 cells (2 PI)
8618 00:45:16.062177 u2DelayCellOfst[4]=10 cells (3 PI)
8619 00:45:16.065829 u2DelayCellOfst[5]=18 cells (5 PI)
8620 00:45:16.068621 u2DelayCellOfst[6]=18 cells (5 PI)
8621 00:45:16.072197 u2DelayCellOfst[7]=7 cells (2 PI)
8622 00:45:16.075738 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8623 00:45:16.079126 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8624 00:45:16.081969 == TX Byte 1 ==
8625 00:45:16.085412 u2DelayCellOfst[8]=0 cells (0 PI)
8626 00:45:16.088576 u2DelayCellOfst[9]=7 cells (2 PI)
8627 00:45:16.091754 u2DelayCellOfst[10]=7 cells (2 PI)
8628 00:45:16.095487 u2DelayCellOfst[11]=3 cells (1 PI)
8629 00:45:16.095996 u2DelayCellOfst[12]=14 cells (4 PI)
8630 00:45:16.098669 u2DelayCellOfst[13]=18 cells (5 PI)
8631 00:45:16.101729 u2DelayCellOfst[14]=14 cells (4 PI)
8632 00:45:16.104896 u2DelayCellOfst[15]=14 cells (4 PI)
8633 00:45:16.111561 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8634 00:45:16.115010 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8635 00:45:16.115439 DramC Write-DBI on
8636 00:45:16.118441 ==
8637 00:45:16.121476 Dram Type= 6, Freq= 0, CH_1, rank 1
8638 00:45:16.124806 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8639 00:45:16.125245 ==
8640 00:45:16.125655
8641 00:45:16.125968
8642 00:45:16.128470 TX Vref Scan disable
8643 00:45:16.128981 == TX Byte 0 ==
8644 00:45:16.134917 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8645 00:45:16.135370 == TX Byte 1 ==
8646 00:45:16.138080 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8647 00:45:16.141526 DramC Write-DBI off
8648 00:45:16.142018
8649 00:45:16.142422 [DATLAT]
8650 00:45:16.144873 Freq=1600, CH1 RK1
8651 00:45:16.145380
8652 00:45:16.145710 DATLAT Default: 0xe
8653 00:45:16.148235 0, 0xFFFF, sum = 0
8654 00:45:16.148826 1, 0xFFFF, sum = 0
8655 00:45:16.151319 2, 0xFFFF, sum = 0
8656 00:45:16.151756 3, 0xFFFF, sum = 0
8657 00:45:16.154596 4, 0xFFFF, sum = 0
8658 00:45:16.155090 5, 0xFFFF, sum = 0
8659 00:45:16.158107 6, 0xFFFF, sum = 0
8660 00:45:16.158667 7, 0xFFFF, sum = 0
8661 00:45:16.161551 8, 0xFFFF, sum = 0
8662 00:45:16.164750 9, 0xFFFF, sum = 0
8663 00:45:16.165267 10, 0xFFFF, sum = 0
8664 00:45:16.167793 11, 0xFFFF, sum = 0
8665 00:45:16.168310 12, 0xF5F, sum = 0
8666 00:45:16.170938 13, 0x0, sum = 1
8667 00:45:16.171377 14, 0x0, sum = 2
8668 00:45:16.174335 15, 0x0, sum = 3
8669 00:45:16.174845 16, 0x0, sum = 4
8670 00:45:16.175187 best_step = 14
8671 00:45:16.177743
8672 00:45:16.178310 ==
8673 00:45:16.181166 Dram Type= 6, Freq= 0, CH_1, rank 1
8674 00:45:16.184203 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8675 00:45:16.184640 ==
8676 00:45:16.184972 RX Vref Scan: 0
8677 00:45:16.185278
8678 00:45:16.187631 RX Vref 0 -> 0, step: 1
8679 00:45:16.188061
8680 00:45:16.190895 RX Delay 3 -> 252, step: 4
8681 00:45:16.194282 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8682 00:45:16.200694 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8683 00:45:16.204029 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8684 00:45:16.207320 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8685 00:45:16.210556 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8686 00:45:16.213791 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8687 00:45:16.220419 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8688 00:45:16.223872 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8689 00:45:16.227063 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8690 00:45:16.230397 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8691 00:45:16.234186 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8692 00:45:16.240545 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8693 00:45:16.243603 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8694 00:45:16.247117 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8695 00:45:16.250250 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8696 00:45:16.256970 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8697 00:45:16.257486 ==
8698 00:45:16.260444 Dram Type= 6, Freq= 0, CH_1, rank 1
8699 00:45:16.263667 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8700 00:45:16.264375 ==
8701 00:45:16.264725 DQS Delay:
8702 00:45:16.266890 DQS0 = 0, DQS1 = 0
8703 00:45:16.267322 DQM Delay:
8704 00:45:16.270019 DQM0 = 127, DQM1 = 122
8705 00:45:16.270490 DQ Delay:
8706 00:45:16.273422 DQ0 =128, DQ1 =122, DQ2 =118, DQ3 =122
8707 00:45:16.276649 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8708 00:45:16.279920 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =112
8709 00:45:16.283507 DQ12 =130, DQ13 =132, DQ14 =134, DQ15 =132
8710 00:45:16.283937
8711 00:45:16.284269
8712 00:45:16.284572
8713 00:45:16.286799 [DramC_TX_OE_Calibration] TA2
8714 00:45:16.290046 Original DQ_B0 (3 6) =30, OEN = 27
8715 00:45:16.293165 Original DQ_B1 (3 6) =30, OEN = 27
8716 00:45:16.296619 24, 0x0, End_B0=24 End_B1=24
8717 00:45:16.299868 25, 0x0, End_B0=25 End_B1=25
8718 00:45:16.303037 26, 0x0, End_B0=26 End_B1=26
8719 00:45:16.303474 27, 0x0, End_B0=27 End_B1=27
8720 00:45:16.306502 28, 0x0, End_B0=28 End_B1=28
8721 00:45:16.309746 29, 0x0, End_B0=29 End_B1=29
8722 00:45:16.313222 30, 0x0, End_B0=30 End_B1=30
8723 00:45:16.313746 31, 0x4545, End_B0=30 End_B1=30
8724 00:45:16.316371 Byte0 end_step=30 best_step=27
8725 00:45:16.320044 Byte1 end_step=30 best_step=27
8726 00:45:16.322923 Byte0 TX OE(2T, 0.5T) = (3, 3)
8727 00:45:16.326386 Byte1 TX OE(2T, 0.5T) = (3, 3)
8728 00:45:16.326819
8729 00:45:16.327260
8730 00:45:16.333048 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8731 00:45:16.336415 CH1 RK1: MR19=303, MR18=1D1D
8732 00:45:16.342905 CH1_RK1: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8733 00:45:16.346592 [RxdqsGatingPostProcess] freq 1600
8734 00:45:16.352844 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8735 00:45:16.356524 Pre-setting of DQS Precalculation
8736 00:45:16.359622 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8737 00:45:16.366559 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8738 00:45:16.372886 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8739 00:45:16.373603
8740 00:45:16.376213
8741 00:45:16.376720 [Calibration Summary] 3200 Mbps
8742 00:45:16.379382 CH 0, Rank 0
8743 00:45:16.379814 SW Impedance : PASS
8744 00:45:16.382745 DUTY Scan : NO K
8745 00:45:16.385848 ZQ Calibration : PASS
8746 00:45:16.386326 Jitter Meter : NO K
8747 00:45:16.389295 CBT Training : PASS
8748 00:45:16.392806 Write leveling : PASS
8749 00:45:16.393363 RX DQS gating : PASS
8750 00:45:16.395882 RX DQ/DQS(RDDQC) : PASS
8751 00:45:16.399113 TX DQ/DQS : PASS
8752 00:45:16.399555 RX DATLAT : PASS
8753 00:45:16.402771 RX DQ/DQS(Engine): PASS
8754 00:45:16.406015 TX OE : PASS
8755 00:45:16.406483 All Pass.
8756 00:45:16.406818
8757 00:45:16.407126 CH 0, Rank 1
8758 00:45:16.409110 SW Impedance : PASS
8759 00:45:16.412317 DUTY Scan : NO K
8760 00:45:16.412752 ZQ Calibration : PASS
8761 00:45:16.415568 Jitter Meter : NO K
8762 00:45:16.418890 CBT Training : PASS
8763 00:45:16.419321 Write leveling : PASS
8764 00:45:16.422703 RX DQS gating : PASS
8765 00:45:16.423251 RX DQ/DQS(RDDQC) : PASS
8766 00:45:16.425717 TX DQ/DQS : PASS
8767 00:45:16.429121 RX DATLAT : PASS
8768 00:45:16.429553 RX DQ/DQS(Engine): PASS
8769 00:45:16.432098 TX OE : PASS
8770 00:45:16.432532 All Pass.
8771 00:45:16.432867
8772 00:45:16.435797 CH 1, Rank 0
8773 00:45:16.436316 SW Impedance : PASS
8774 00:45:16.439352 DUTY Scan : NO K
8775 00:45:16.442111 ZQ Calibration : PASS
8776 00:45:16.442722 Jitter Meter : NO K
8777 00:45:16.445517 CBT Training : PASS
8778 00:45:16.448977 Write leveling : PASS
8779 00:45:16.449497 RX DQS gating : PASS
8780 00:45:16.452127 RX DQ/DQS(RDDQC) : PASS
8781 00:45:16.455463 TX DQ/DQS : PASS
8782 00:45:16.455932 RX DATLAT : PASS
8783 00:45:16.458790 RX DQ/DQS(Engine): PASS
8784 00:45:16.462379 TX OE : PASS
8785 00:45:16.462821 All Pass.
8786 00:45:16.463159
8787 00:45:16.463466 CH 1, Rank 1
8788 00:45:16.465654 SW Impedance : PASS
8789 00:45:16.468825 DUTY Scan : NO K
8790 00:45:16.469444 ZQ Calibration : PASS
8791 00:45:16.472066 Jitter Meter : NO K
8792 00:45:16.475391 CBT Training : PASS
8793 00:45:16.475908 Write leveling : PASS
8794 00:45:16.478619 RX DQS gating : PASS
8795 00:45:16.479053 RX DQ/DQS(RDDQC) : PASS
8796 00:45:16.482171 TX DQ/DQS : PASS
8797 00:45:16.485050 RX DATLAT : PASS
8798 00:45:16.485483 RX DQ/DQS(Engine): PASS
8799 00:45:16.488511 TX OE : PASS
8800 00:45:16.488944 All Pass.
8801 00:45:16.489276
8802 00:45:16.492135 DramC Write-DBI on
8803 00:45:16.495312 PER_BANK_REFRESH: Hybrid Mode
8804 00:45:16.495745 TX_TRACKING: ON
8805 00:45:16.505394 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8806 00:45:16.512202 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8807 00:45:16.518586 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8808 00:45:16.525106 [FAST_K] Save calibration result to emmc
8809 00:45:16.525716 sync common calibartion params.
8810 00:45:16.528491 sync cbt_mode0:0, 1:0
8811 00:45:16.531870 dram_init: ddr_geometry: 0
8812 00:45:16.532401 dram_init: ddr_geometry: 0
8813 00:45:16.534909 dram_init: ddr_geometry: 0
8814 00:45:16.538184 0:dram_rank_size:80000000
8815 00:45:16.541419 1:dram_rank_size:80000000
8816 00:45:16.545175 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8817 00:45:16.548225 DFS_SHUFFLE_HW_MODE: ON
8818 00:45:16.551593 dramc_set_vcore_voltage set vcore to 725000
8819 00:45:16.554982 Read voltage for 1600, 0
8820 00:45:16.555428 Vio18 = 0
8821 00:45:16.555871 Vcore = 725000
8822 00:45:16.558177 Vdram = 0
8823 00:45:16.558666 Vddq = 0
8824 00:45:16.559106 Vmddr = 0
8825 00:45:16.561425 switch to 3200 Mbps bootup
8826 00:45:16.564885 [DramcRunTimeConfig]
8827 00:45:16.565336 PHYPLL
8828 00:45:16.565776 DPM_CONTROL_AFTERK: ON
8829 00:45:16.568211 PER_BANK_REFRESH: ON
8830 00:45:16.571397 REFRESH_OVERHEAD_REDUCTION: ON
8831 00:45:16.571845 CMD_PICG_NEW_MODE: OFF
8832 00:45:16.574653 XRTWTW_NEW_MODE: ON
8833 00:45:16.578069 XRTRTR_NEW_MODE: ON
8834 00:45:16.578560 TX_TRACKING: ON
8835 00:45:16.581655 RDSEL_TRACKING: OFF
8836 00:45:16.582192 DQS Precalculation for DVFS: ON
8837 00:45:16.584639 RX_TRACKING: OFF
8838 00:45:16.585278 HW_GATING DBG: ON
8839 00:45:16.587947 ZQCS_ENABLE_LP4: ON
8840 00:45:16.588380 RX_PICG_NEW_MODE: ON
8841 00:45:16.591460 TX_PICG_NEW_MODE: ON
8842 00:45:16.595072 ENABLE_RX_DCM_DPHY: ON
8843 00:45:16.597918 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8844 00:45:16.598372 DUMMY_READ_FOR_TRACKING: OFF
8845 00:45:16.601403 !!! SPM_CONTROL_AFTERK: OFF
8846 00:45:16.604565 !!! SPM could not control APHY
8847 00:45:16.607906 IMPEDANCE_TRACKING: ON
8848 00:45:16.608356 TEMP_SENSOR: ON
8849 00:45:16.611197 HW_SAVE_FOR_SR: OFF
8850 00:45:16.611647 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8851 00:45:16.618086 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8852 00:45:16.618715 Read ODT Tracking: ON
8853 00:45:16.621395 Refresh Rate DeBounce: ON
8854 00:45:16.621841 DFS_NO_QUEUE_FLUSH: ON
8855 00:45:16.624550 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8856 00:45:16.628147 ENABLE_DFS_RUNTIME_MRW: OFF
8857 00:45:16.631084 DDR_RESERVE_NEW_MODE: ON
8858 00:45:16.634306 MR_CBT_SWITCH_FREQ: ON
8859 00:45:16.634758 =========================
8860 00:45:16.653751 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8861 00:45:16.657330 dram_init: ddr_geometry: 0
8862 00:45:16.675409 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8863 00:45:16.678389 dram_init: dram init end (result: 0)
8864 00:45:16.685134 DRAM-K: Full calibration passed in 23427 msecs
8865 00:45:16.688326 MRC: failed to locate region type 0.
8866 00:45:16.688779 DRAM rank0 size:0x80000000,
8867 00:45:16.691637 DRAM rank1 size=0x80000000
8868 00:45:16.701812 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8869 00:45:16.708198 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8870 00:45:16.715041 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8871 00:45:16.721614 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8872 00:45:16.724994 DRAM rank0 size:0x80000000,
8873 00:45:16.728234 DRAM rank1 size=0x80000000
8874 00:45:16.728751 CBMEM:
8875 00:45:16.731591 IMD: root @ 0xfffff000 254 entries.
8876 00:45:16.734746 IMD: root @ 0xffffec00 62 entries.
8877 00:45:16.737919 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8878 00:45:16.741379 WARNING: RO_VPD is uninitialized or empty.
8879 00:45:16.748011 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8880 00:45:16.754799 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8881 00:45:16.767571 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
8882 00:45:16.779082 BS: romstage times (exec / console): total (unknown) / 22964 ms
8883 00:45:16.779594
8884 00:45:16.779931
8885 00:45:16.788946 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8886 00:45:16.792697 ARM64: Exception handlers installed.
8887 00:45:16.795578 ARM64: Testing exception
8888 00:45:16.798895 ARM64: Done test exception
8889 00:45:16.799346 Enumerating buses...
8890 00:45:16.802303 Show all devs... Before device enumeration.
8891 00:45:16.805586 Root Device: enabled 1
8892 00:45:16.808644 CPU_CLUSTER: 0: enabled 1
8893 00:45:16.809083 CPU: 00: enabled 1
8894 00:45:16.812140 Compare with tree...
8895 00:45:16.812654 Root Device: enabled 1
8896 00:45:16.815272 CPU_CLUSTER: 0: enabled 1
8897 00:45:16.818597 CPU: 00: enabled 1
8898 00:45:16.819034 Root Device scanning...
8899 00:45:16.822288 scan_static_bus for Root Device
8900 00:45:16.825587 CPU_CLUSTER: 0 enabled
8901 00:45:16.828773 scan_static_bus for Root Device done
8902 00:45:16.832122 scan_bus: bus Root Device finished in 8 msecs
8903 00:45:16.832581 done
8904 00:45:16.838640 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8905 00:45:16.841890 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8906 00:45:16.848877 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8907 00:45:16.851750 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8908 00:45:16.855263 Allocating resources...
8909 00:45:16.858319 Reading resources...
8910 00:45:16.862142 Root Device read_resources bus 0 link: 0
8911 00:45:16.862707 DRAM rank0 size:0x80000000,
8912 00:45:16.865037 DRAM rank1 size=0x80000000
8913 00:45:16.868314 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8914 00:45:16.871802 CPU: 00 missing read_resources
8915 00:45:16.874924 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8916 00:45:16.881563 Root Device read_resources bus 0 link: 0 done
8917 00:45:16.882004 Done reading resources.
8918 00:45:16.888359 Show resources in subtree (Root Device)...After reading.
8919 00:45:16.891663 Root Device child on link 0 CPU_CLUSTER: 0
8920 00:45:16.894932 CPU_CLUSTER: 0 child on link 0 CPU: 00
8921 00:45:16.904837 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8922 00:45:16.905293 CPU: 00
8923 00:45:16.908004 Root Device assign_resources, bus 0 link: 0
8924 00:45:16.911457 CPU_CLUSTER: 0 missing set_resources
8925 00:45:16.917889 Root Device assign_resources, bus 0 link: 0 done
8926 00:45:16.918430 Done setting resources.
8927 00:45:16.924569 Show resources in subtree (Root Device)...After assigning values.
8928 00:45:16.927801 Root Device child on link 0 CPU_CLUSTER: 0
8929 00:45:16.931395 CPU_CLUSTER: 0 child on link 0 CPU: 00
8930 00:45:16.941391 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8931 00:45:16.942122 CPU: 00
8932 00:45:16.944609 Done allocating resources.
8933 00:45:16.947960 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8934 00:45:16.951027 Enabling resources...
8935 00:45:16.951462 done.
8936 00:45:16.957827 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8937 00:45:16.958310 Initializing devices...
8938 00:45:16.961424 Root Device init
8939 00:45:16.962024 init hardware done!
8940 00:45:16.964404 0x00000018: ctrlr->caps
8941 00:45:16.968196 52.000 MHz: ctrlr->f_max
8942 00:45:16.968840 0.400 MHz: ctrlr->f_min
8943 00:45:16.971160 0x40ff8080: ctrlr->voltages
8944 00:45:16.971619 sclk: 390625
8945 00:45:16.974357 Bus Width = 1
8946 00:45:16.974906 sclk: 390625
8947 00:45:16.977946 Bus Width = 1
8948 00:45:16.978528 Early init status = 3
8949 00:45:16.984893 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8950 00:45:16.987491 in-header: 03 fc 00 00 01 00 00 00
8951 00:45:16.987931 in-data: 00
8952 00:45:16.994161 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8953 00:45:16.997688 in-header: 03 fd 00 00 00 00 00 00
8954 00:45:17.000913 in-data:
8955 00:45:17.004015 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8956 00:45:17.007633 in-header: 03 fc 00 00 01 00 00 00
8957 00:45:17.011025 in-data: 00
8958 00:45:17.014001 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8959 00:45:17.018966 in-header: 03 fd 00 00 00 00 00 00
8960 00:45:17.022331 in-data:
8961 00:45:17.026246 [SSUSB] Setting up USB HOST controller...
8962 00:45:17.028962 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8963 00:45:17.032250 [SSUSB] phy power-on done.
8964 00:45:17.035902 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8965 00:45:17.042188 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8966 00:45:17.045544 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8967 00:45:17.052231 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8968 00:45:17.058513 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
8969 00:45:17.065142 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8970 00:45:17.071897 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8971 00:45:17.078669 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8972 00:45:17.081767 SPM: binary array size = 0x9dc
8973 00:45:17.085245 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8974 00:45:17.092232 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8975 00:45:17.098267 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8976 00:45:17.105054 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8977 00:45:17.108275 configure_display: Starting display init
8978 00:45:17.142155 anx7625_power_on_init: Init interface.
8979 00:45:17.145326 anx7625_disable_pd_protocol: Disabled PD feature.
8980 00:45:17.148901 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8981 00:45:17.176900 anx7625_start_dp_work: Secure OCM version=00
8982 00:45:17.179863 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8983 00:45:17.194789 sp_tx_get_edid_block: EDID Block = 1
8984 00:45:17.297397 Extracted contents:
8985 00:45:17.300707 header: 00 ff ff ff ff ff ff 00
8986 00:45:17.303920 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8987 00:45:17.307232 version: 01 04
8988 00:45:17.310594 basic params: 95 1f 11 78 0a
8989 00:45:17.313766 chroma info: 76 90 94 55 54 90 27 21 50 54
8990 00:45:17.317158 established: 00 00 00
8991 00:45:17.323857 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8992 00:45:17.327109 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8993 00:45:17.333741 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8994 00:45:17.340216 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8995 00:45:17.346776 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8996 00:45:17.350338 extensions: 00
8997 00:45:17.350890 checksum: fb
8998 00:45:17.351342
8999 00:45:17.353590 Manufacturer: IVO Model 57d Serial Number 0
9000 00:45:17.356870 Made week 0 of 2020
9001 00:45:17.357319 EDID version: 1.4
9002 00:45:17.360351 Digital display
9003 00:45:17.363296 6 bits per primary color channel
9004 00:45:17.363744 DisplayPort interface
9005 00:45:17.366820 Maximum image size: 31 cm x 17 cm
9006 00:45:17.370382 Gamma: 220%
9007 00:45:17.370902 Check DPMS levels
9008 00:45:17.373665 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9009 00:45:17.380326 First detailed timing is preferred timing
9010 00:45:17.380830 Established timings supported:
9011 00:45:17.383429 Standard timings supported:
9012 00:45:17.386568 Detailed timings
9013 00:45:17.390032 Hex of detail: 383680a07038204018303c0035ae10000019
9014 00:45:17.393381 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9015 00:45:17.399713 0780 0798 07c8 0820 hborder 0
9016 00:45:17.403012 0438 043b 0447 0458 vborder 0
9017 00:45:17.406324 -hsync -vsync
9018 00:45:17.406948 Did detailed timing
9019 00:45:17.413380 Hex of detail: 000000000000000000000000000000000000
9020 00:45:17.414107 Manufacturer-specified data, tag 0
9021 00:45:17.419759 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9022 00:45:17.423450 ASCII string: InfoVision
9023 00:45:17.426390 Hex of detail: 000000fe00523134304e574635205248200a
9024 00:45:17.429584 ASCII string: R140NWF5 RH
9025 00:45:17.430032 Checksum
9026 00:45:17.433207 Checksum: 0xfb (valid)
9027 00:45:17.436404 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9028 00:45:17.439804 DSI data_rate: 832800000 bps
9029 00:45:17.446400 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9030 00:45:17.449863 anx7625_parse_edid: pixelclock(138800).
9031 00:45:17.453185 hactive(1920), hsync(48), hfp(24), hbp(88)
9032 00:45:17.456357 vactive(1080), vsync(12), vfp(3), vbp(17)
9033 00:45:17.459683 anx7625_dsi_config: config dsi.
9034 00:45:17.466353 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9035 00:45:17.479395 anx7625_dsi_config: success to config DSI
9036 00:45:17.482659 anx7625_dp_start: MIPI phy setup OK.
9037 00:45:17.486121 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9038 00:45:17.489351 mtk_ddp_mode_set invalid vrefresh 60
9039 00:45:17.492517 main_disp_path_setup
9040 00:45:17.492947 ovl_layer_smi_id_en
9041 00:45:17.495949 ovl_layer_smi_id_en
9042 00:45:17.496478 ccorr_config
9043 00:45:17.496987 aal_config
9044 00:45:17.499103 gamma_config
9045 00:45:17.499539 postmask_config
9046 00:45:17.502415 dither_config
9047 00:45:17.505887 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9048 00:45:17.512708 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9049 00:45:17.516237 Root Device init finished in 551 msecs
9050 00:45:17.518861 CPU_CLUSTER: 0 init
9051 00:45:17.525938 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9052 00:45:17.529115 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9053 00:45:17.532627 APU_MBOX 0x190000b0 = 0x10001
9054 00:45:17.535592 APU_MBOX 0x190001b0 = 0x10001
9055 00:45:17.538917 APU_MBOX 0x190005b0 = 0x10001
9056 00:45:17.542452 APU_MBOX 0x190006b0 = 0x10001
9057 00:45:17.545445 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9058 00:45:17.558097 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9059 00:45:17.570781 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9060 00:45:17.577370 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9061 00:45:17.588958 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9062 00:45:17.598018 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9063 00:45:17.601529 CPU_CLUSTER: 0 init finished in 81 msecs
9064 00:45:17.604879 Devices initialized
9065 00:45:17.607862 Show all devs... After init.
9066 00:45:17.608302 Root Device: enabled 1
9067 00:45:17.611602 CPU_CLUSTER: 0: enabled 1
9068 00:45:17.614821 CPU: 00: enabled 1
9069 00:45:17.617919 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9070 00:45:17.621267 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9071 00:45:17.624675 ELOG: NV offset 0x57f000 size 0x1000
9072 00:45:17.631157 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9073 00:45:17.637708 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9074 00:45:17.641382 ELOG: Event(17) added with size 13 at 2024-06-16 00:45:17 UTC
9075 00:45:17.644403 out: cmd=0x121: 03 db 21 01 00 00 00 00
9076 00:45:17.648403 in-header: 03 17 00 00 2c 00 00 00
9077 00:45:17.661457 in-data: 2b 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9078 00:45:17.667975 ELOG: Event(A1) added with size 10 at 2024-06-16 00:45:17 UTC
9079 00:45:17.674868 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9080 00:45:17.681520 ELOG: Event(A0) added with size 9 at 2024-06-16 00:45:17 UTC
9081 00:45:17.684666 elog_add_boot_reason: Logged dev mode boot
9082 00:45:17.687814 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9083 00:45:17.691092 Finalize devices...
9084 00:45:17.691525 Devices finalized
9085 00:45:17.697751 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9086 00:45:17.701177 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9087 00:45:17.704373 in-header: 03 07 00 00 08 00 00 00
9088 00:45:17.707733 in-data: aa e4 47 04 13 02 00 00
9089 00:45:17.711117 Chrome EC: UHEPI supported
9090 00:45:17.717653 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9091 00:45:17.721075 in-header: 03 a9 00 00 08 00 00 00
9092 00:45:17.724458 in-data: 84 60 60 08 00 00 00 00
9093 00:45:17.727575 ELOG: Event(91) added with size 10 at 2024-06-16 00:45:17 UTC
9094 00:45:17.734378 Chrome EC: clear events_b mask to 0x0000000020004000
9095 00:45:17.741126 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9096 00:45:17.744847 in-header: 03 fd 00 00 00 00 00 00
9097 00:45:17.745312 in-data:
9098 00:45:17.751215 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9099 00:45:17.754715 Writing coreboot table at 0xffe64000
9100 00:45:17.757926 0. 000000000010a000-0000000000113fff: RAMSTAGE
9101 00:45:17.761295 1. 0000000040000000-00000000400fffff: RAM
9102 00:45:17.765267 2. 0000000040100000-000000004032afff: RAMSTAGE
9103 00:45:17.771413 3. 000000004032b000-00000000545fffff: RAM
9104 00:45:17.774726 4. 0000000054600000-000000005465ffff: BL31
9105 00:45:17.778003 5. 0000000054660000-00000000ffe63fff: RAM
9106 00:45:17.781285 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9107 00:45:17.788039 7. 0000000100000000-000000013fffffff: RAM
9108 00:45:17.788473 Passing 5 GPIOs to payload:
9109 00:45:17.794654 NAME | PORT | POLARITY | VALUE
9110 00:45:17.798024 EC in RW | 0x000000aa | low | undefined
9111 00:45:17.801562 EC interrupt | 0x00000005 | low | undefined
9112 00:45:17.807982 TPM interrupt | 0x000000ab | high | undefined
9113 00:45:17.811483 SD card detect | 0x00000011 | high | undefined
9114 00:45:17.818165 speaker enable | 0x00000093 | high | undefined
9115 00:45:17.821153 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9116 00:45:17.824647 in-header: 03 f8 00 00 02 00 00 00
9117 00:45:17.825043 in-data: 03 00
9118 00:45:17.828084 ADC[4]: Raw value=669327 ID=5
9119 00:45:17.831017 ADC[3]: Raw value=212917 ID=1
9120 00:45:17.831448 RAM Code: 0x51
9121 00:45:17.834405 ADC[6]: Raw value=74778 ID=0
9122 00:45:17.837891 ADC[5]: Raw value=211444 ID=1
9123 00:45:17.838357 SKU Code: 0x1
9124 00:45:17.844311 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8e1f
9125 00:45:17.847635 coreboot table: 964 bytes.
9126 00:45:17.851179 IMD ROOT 0. 0xfffff000 0x00001000
9127 00:45:17.854366 IMD SMALL 1. 0xffffe000 0x00001000
9128 00:45:17.857631 RO MCACHE 2. 0xffffc000 0x00001104
9129 00:45:17.860889 CONSOLE 3. 0xfff7c000 0x00080000
9130 00:45:17.864184 FMAP 4. 0xfff7b000 0x00000452
9131 00:45:17.867946 TIME STAMP 5. 0xfff7a000 0x00000910
9132 00:45:17.870911 VBOOT WORK 6. 0xfff66000 0x00014000
9133 00:45:17.874432 RAMOOPS 7. 0xffe66000 0x00100000
9134 00:45:17.877749 COREBOOT 8. 0xffe64000 0x00002000
9135 00:45:17.878286 IMD small region:
9136 00:45:17.880930 IMD ROOT 0. 0xffffec00 0x00000400
9137 00:45:17.884283 VPD 1. 0xffffeb80 0x0000006c
9138 00:45:17.887598 MMC STATUS 2. 0xffffeb60 0x00000004
9139 00:45:17.894434 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9140 00:45:17.900941 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9141 00:45:17.939811 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9142 00:45:17.943442 Checking segment from ROM address 0x40100000
9143 00:45:17.946648 Checking segment from ROM address 0x4010001c
9144 00:45:17.953171 Loading segment from ROM address 0x40100000
9145 00:45:17.953671 code (compression=0)
9146 00:45:17.963089 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9147 00:45:17.970343 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9148 00:45:17.970854 it's not compressed!
9149 00:45:17.976539 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9150 00:45:17.983007 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9151 00:45:18.000310 Loading segment from ROM address 0x4010001c
9152 00:45:18.000808 Entry Point 0x80000000
9153 00:45:18.003856 Loaded segments
9154 00:45:18.006956 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9155 00:45:18.013800 Jumping to boot code at 0x80000000(0xffe64000)
9156 00:45:18.020283 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9157 00:45:18.027027 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9158 00:45:18.035146 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9159 00:45:18.038045 Checking segment from ROM address 0x40100000
9160 00:45:18.041657 Checking segment from ROM address 0x4010001c
9161 00:45:18.048896 Loading segment from ROM address 0x40100000
9162 00:45:18.049472 code (compression=1)
9163 00:45:18.054964 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9164 00:45:18.064683 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9165 00:45:18.065126 using LZMA
9166 00:45:18.073067 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9167 00:45:18.079953 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9168 00:45:18.083174 Loading segment from ROM address 0x4010001c
9169 00:45:18.083616 Entry Point 0x54601000
9170 00:45:18.086360 Loaded segments
9171 00:45:18.089856 NOTICE: MT8192 bl31_setup
9172 00:45:18.096667 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9173 00:45:18.099934 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9174 00:45:18.103295 WARNING: region 0:
9175 00:45:18.106781 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9176 00:45:18.107233 WARNING: region 1:
9177 00:45:18.113606 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9178 00:45:18.116544 WARNING: region 2:
9179 00:45:18.120049 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9180 00:45:18.123404 WARNING: region 3:
9181 00:45:18.126905 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9182 00:45:18.130122 WARNING: region 4:
9183 00:45:18.136922 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9184 00:45:18.137445 WARNING: region 5:
9185 00:45:18.140168 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9186 00:45:18.143664 WARNING: region 6:
9187 00:45:18.146560 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9188 00:45:18.150087 WARNING: region 7:
9189 00:45:18.153351 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9190 00:45:18.159681 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9191 00:45:18.163147 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9192 00:45:18.166529 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9193 00:45:18.173129 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9194 00:45:18.176553 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9195 00:45:18.179780 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9196 00:45:18.186576 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9197 00:45:18.189807 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9198 00:45:18.196248 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9199 00:45:18.199559 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9200 00:45:18.202926 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9201 00:45:18.209381 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9202 00:45:18.212867 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9203 00:45:18.219295 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9204 00:45:18.222804 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9205 00:45:18.226045 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9206 00:45:18.232416 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9207 00:45:18.236087 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9208 00:45:18.239181 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9209 00:45:18.245963 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9210 00:45:18.249490 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9211 00:45:18.256048 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9212 00:45:18.259443 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9213 00:45:18.262811 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9214 00:45:18.269730 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9215 00:45:18.272565 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9216 00:45:18.279615 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9217 00:45:18.282753 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9218 00:45:18.286070 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9219 00:45:18.292530 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9220 00:45:18.296163 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9221 00:45:18.302556 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9222 00:45:18.305742 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9223 00:45:18.309271 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9224 00:45:18.312581 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9225 00:45:18.318874 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9226 00:45:18.322088 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9227 00:45:18.325546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9228 00:45:18.328736 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9229 00:45:18.335529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9230 00:45:18.338783 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9231 00:45:18.342032 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9232 00:45:18.345312 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9233 00:45:18.352411 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9234 00:45:18.355212 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9235 00:45:18.358603 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9236 00:45:18.361880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9237 00:45:18.368800 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9238 00:45:18.372278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9239 00:45:18.378878 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9240 00:45:18.381875 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9241 00:45:18.385191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9242 00:45:18.391655 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9243 00:45:18.395252 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9244 00:45:18.401724 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9245 00:45:18.405387 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9246 00:45:18.412051 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9247 00:45:18.414973 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9248 00:45:18.418659 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9249 00:45:18.425334 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9250 00:45:18.428697 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9251 00:45:18.434921 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9252 00:45:18.438572 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9253 00:45:18.444788 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9254 00:45:18.448344 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9255 00:45:18.454979 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9256 00:45:18.458518 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9257 00:45:18.461919 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9258 00:45:18.468594 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9259 00:45:18.471959 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9260 00:45:18.478148 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9261 00:45:18.481871 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9262 00:45:18.488214 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9263 00:45:18.491299 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9264 00:45:18.494812 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9265 00:45:18.501403 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9266 00:45:18.504766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9267 00:45:18.511177 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9268 00:45:18.514854 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9269 00:45:18.521350 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9270 00:45:18.524988 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9271 00:45:18.531356 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9272 00:45:18.534395 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9273 00:45:18.537723 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9274 00:45:18.544370 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9275 00:45:18.547798 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9276 00:45:18.554601 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9277 00:45:18.558088 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9278 00:45:18.564750 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9279 00:45:18.568107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9280 00:45:18.571278 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9281 00:45:18.577889 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9282 00:45:18.581041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9283 00:45:18.587666 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9284 00:45:18.591111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9285 00:45:18.597548 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9286 00:45:18.600915 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9287 00:45:18.604322 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9288 00:45:18.607675 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9289 00:45:18.614136 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9290 00:45:18.617580 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9291 00:45:18.621008 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9292 00:45:18.627543 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9293 00:45:18.630860 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9294 00:45:18.637463 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9295 00:45:18.640685 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9296 00:45:18.643940 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9297 00:45:18.650827 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9298 00:45:18.653953 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9299 00:45:18.660986 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9300 00:45:18.664041 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9301 00:45:18.667605 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9302 00:45:18.674200 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9303 00:45:18.677512 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9304 00:45:18.684154 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9305 00:45:18.687483 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9306 00:45:18.690731 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9307 00:45:18.697554 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9308 00:45:18.700544 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9309 00:45:18.703902 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9310 00:45:18.707178 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9311 00:45:18.713700 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9312 00:45:18.716982 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9313 00:45:18.720597 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9314 00:45:18.727210 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9315 00:45:18.730636 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9316 00:45:18.733799 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9317 00:45:18.740744 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9318 00:45:18.743648 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9319 00:45:18.750282 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9320 00:45:18.753743 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9321 00:45:18.757025 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9322 00:45:18.763485 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9323 00:45:18.767162 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9324 00:45:18.770251 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9325 00:45:18.777183 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9326 00:45:18.780384 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9327 00:45:18.787423 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9328 00:45:18.790183 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9329 00:45:18.793599 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9330 00:45:18.800058 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9331 00:45:18.803481 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9332 00:45:18.810165 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9333 00:45:18.813340 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9334 00:45:18.817172 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9335 00:45:18.823799 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9336 00:45:18.827032 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9337 00:45:18.833452 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9338 00:45:18.836809 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9339 00:45:18.839836 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9340 00:45:18.846660 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9341 00:45:18.849977 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9342 00:45:18.853109 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9343 00:45:18.859880 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9344 00:45:18.863310 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9345 00:45:18.870144 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9346 00:45:18.873455 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9347 00:45:18.876850 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9348 00:45:18.883268 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9349 00:45:18.886409 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9350 00:45:18.892915 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9351 00:45:18.896448 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9352 00:45:18.899725 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9353 00:45:18.906536 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9354 00:45:18.909658 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9355 00:45:18.916293 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9356 00:45:18.919637 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9357 00:45:18.923154 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9358 00:45:18.929646 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9359 00:45:18.932994 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9360 00:45:18.939640 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9361 00:45:18.942866 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9362 00:45:18.946317 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9363 00:45:18.952995 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9364 00:45:18.956377 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9365 00:45:18.959607 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9366 00:45:18.966237 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9367 00:45:18.969404 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9368 00:45:18.976053 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9369 00:45:18.979513 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9370 00:45:18.982750 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9371 00:45:18.989140 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9372 00:45:18.992710 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9373 00:45:18.999324 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9374 00:45:19.002706 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9375 00:45:19.005987 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9376 00:45:19.012615 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9377 00:45:19.015815 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9378 00:45:19.022460 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9379 00:45:19.025687 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9380 00:45:19.029360 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9381 00:45:19.035887 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9382 00:45:19.039205 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9383 00:45:19.045800 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9384 00:45:19.049132 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9385 00:45:19.052461 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9386 00:45:19.059115 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9387 00:45:19.062480 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9388 00:45:19.069035 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9389 00:45:19.072681 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9390 00:45:19.078908 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9391 00:45:19.082272 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9392 00:45:19.085597 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9393 00:45:19.092426 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9394 00:45:19.095660 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9395 00:45:19.102584 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9396 00:45:19.105555 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9397 00:45:19.109032 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9398 00:45:19.115555 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9399 00:45:19.118876 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9400 00:45:19.125574 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9401 00:45:19.128960 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9402 00:45:19.135599 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9403 00:45:19.138980 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9404 00:45:19.142161 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9405 00:45:19.148866 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9406 00:45:19.152213 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9407 00:45:19.159015 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9408 00:45:19.162434 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9409 00:45:19.165901 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9410 00:45:19.172620 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9411 00:45:19.175619 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9412 00:45:19.182429 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9413 00:45:19.185785 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9414 00:45:19.189277 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9415 00:45:19.195673 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9416 00:45:19.198957 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9417 00:45:19.205707 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9418 00:45:19.208674 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9419 00:45:19.211991 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9420 00:45:19.218739 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9421 00:45:19.222164 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9422 00:45:19.225589 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9423 00:45:19.228589 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9424 00:45:19.235495 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9425 00:45:19.238568 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9426 00:45:19.241979 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9427 00:45:19.248356 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9428 00:45:19.251819 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9429 00:45:19.255060 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9430 00:45:19.262044 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9431 00:45:19.265198 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9432 00:45:19.271812 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9433 00:45:19.275134 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9434 00:45:19.278485 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9435 00:45:19.285290 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9436 00:45:19.288783 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9437 00:45:19.292016 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9438 00:45:19.299130 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9439 00:45:19.301806 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9440 00:45:19.305144 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9441 00:45:19.311669 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9442 00:45:19.315261 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9443 00:45:19.321720 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9444 00:45:19.325216 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9445 00:45:19.328407 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9446 00:45:19.335176 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9447 00:45:19.338457 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9448 00:45:19.341615 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9449 00:45:19.348243 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9450 00:45:19.351744 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9451 00:45:19.358536 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9452 00:45:19.361506 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9453 00:45:19.365628 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9454 00:45:19.372090 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9455 00:45:19.375073 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9456 00:45:19.378203 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9457 00:45:19.384779 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9458 00:45:19.388519 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9459 00:45:19.391468 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9460 00:45:19.394824 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9461 00:45:19.401444 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9462 00:45:19.404857 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9463 00:45:19.408181 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9464 00:45:19.411374 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9465 00:45:19.418356 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9466 00:45:19.421475 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9467 00:45:19.424845 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9468 00:45:19.428219 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9469 00:45:19.435076 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9470 00:45:19.438268 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9471 00:45:19.441210 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9472 00:45:19.447926 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9473 00:45:19.451383 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9474 00:45:19.454413 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9475 00:45:19.461249 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9476 00:45:19.464352 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9477 00:45:19.471634 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9478 00:45:19.474513 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9479 00:45:19.478185 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9480 00:45:19.484567 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9481 00:45:19.488030 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9482 00:45:19.494383 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9483 00:45:19.497916 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9484 00:45:19.504425 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9485 00:45:19.508137 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9486 00:45:19.511249 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9487 00:45:19.517713 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9488 00:45:19.521158 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9489 00:45:19.527950 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9490 00:45:19.531111 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9491 00:45:19.534515 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9492 00:45:19.540965 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9493 00:45:19.544410 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9494 00:45:19.551011 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9495 00:45:19.554321 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9496 00:45:19.557965 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9497 00:45:19.564432 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9498 00:45:19.568044 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9499 00:45:19.574416 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9500 00:45:19.577726 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9501 00:45:19.581379 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9502 00:45:19.587660 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9503 00:45:19.590936 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9504 00:45:19.597544 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9505 00:45:19.600858 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9506 00:45:19.604209 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9507 00:45:19.610783 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9508 00:45:19.614202 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9509 00:45:19.620760 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9510 00:45:19.624302 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9511 00:45:19.627540 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9512 00:45:19.634104 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9513 00:45:19.637651 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9514 00:45:19.644090 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9515 00:45:19.647594 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9516 00:45:19.653941 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9517 00:45:19.657572 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9518 00:45:19.661051 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9519 00:45:19.667269 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9520 00:45:19.670572 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9521 00:45:19.677219 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9522 00:45:19.680745 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9523 00:45:19.684223 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9524 00:45:19.691115 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9525 00:45:19.693777 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9526 00:45:19.700532 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9527 00:45:19.703760 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9528 00:45:19.707075 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9529 00:45:19.713924 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9530 00:45:19.717456 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9531 00:45:19.724172 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9532 00:45:19.727314 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9533 00:45:19.730554 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9534 00:45:19.737200 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9535 00:45:19.740618 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9536 00:45:19.747275 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9537 00:45:19.750516 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9538 00:45:19.753829 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9539 00:45:19.760361 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9540 00:45:19.763508 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9541 00:45:19.770388 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9542 00:45:19.773832 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9543 00:45:19.777137 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9544 00:45:19.783539 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9545 00:45:19.786933 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9546 00:45:19.793466 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9547 00:45:19.796881 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9548 00:45:19.803800 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9549 00:45:19.806888 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9550 00:45:19.813482 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9551 00:45:19.816723 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9552 00:45:19.820153 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9553 00:45:19.827114 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9554 00:45:19.830342 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9555 00:45:19.836927 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9556 00:45:19.839934 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9557 00:45:19.846510 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9558 00:45:19.850207 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9559 00:45:19.853476 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9560 00:45:19.860108 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9561 00:45:19.863521 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9562 00:45:19.869690 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9563 00:45:19.873411 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9564 00:45:19.879578 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9565 00:45:19.883067 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9566 00:45:19.889817 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9567 00:45:19.892909 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9568 00:45:19.896203 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9569 00:45:19.902868 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9570 00:45:19.906304 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9571 00:45:19.912802 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9572 00:45:19.916335 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9573 00:45:19.922719 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9574 00:45:19.926141 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9575 00:45:19.929502 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9576 00:45:19.936221 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9577 00:45:19.939225 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9578 00:45:19.946468 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9579 00:45:19.949182 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9580 00:45:19.955983 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9581 00:45:19.959071 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9582 00:45:19.965867 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9583 00:45:19.969441 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9584 00:45:19.972535 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9585 00:45:19.979157 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9586 00:45:19.982163 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9587 00:45:19.989241 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9588 00:45:19.992280 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9589 00:45:19.998866 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9590 00:45:20.002019 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9591 00:45:20.005246 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9592 00:45:20.012089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9593 00:45:20.015511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9594 00:45:20.021961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9595 00:45:20.025777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9596 00:45:20.032271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9597 00:45:20.035485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9598 00:45:20.041844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9599 00:45:20.045021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9600 00:45:20.051759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9601 00:45:20.054990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9602 00:45:20.061716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9603 00:45:20.065223 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9604 00:45:20.071405 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9605 00:45:20.075042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9606 00:45:20.081477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9607 00:45:20.085441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9608 00:45:20.091736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9609 00:45:20.094695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9610 00:45:20.098046 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9611 00:45:20.104668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9612 00:45:20.107975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9613 00:45:20.114556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9614 00:45:20.117895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9615 00:45:20.124956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9616 00:45:20.128603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9617 00:45:20.134576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9618 00:45:20.141104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9619 00:45:20.144367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9620 00:45:20.151059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9621 00:45:20.154794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9622 00:45:20.158128 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9623 00:45:20.164397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9624 00:45:20.167770 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9625 00:45:20.171365 INFO: [APUAPC] vio 0
9626 00:45:20.174325 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9627 00:45:20.181390 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9628 00:45:20.184284 INFO: [APUAPC] D0_APC_0: 0x400510
9629 00:45:20.187635 INFO: [APUAPC] D0_APC_1: 0x0
9630 00:45:20.190811 INFO: [APUAPC] D0_APC_2: 0x1540
9631 00:45:20.191257 INFO: [APUAPC] D0_APC_3: 0x0
9632 00:45:20.194169 INFO: [APUAPC] D1_APC_0: 0xffffffff
9633 00:45:20.197565 INFO: [APUAPC] D1_APC_1: 0xffffffff
9634 00:45:20.200892 INFO: [APUAPC] D1_APC_2: 0x3fffff
9635 00:45:20.204164 INFO: [APUAPC] D1_APC_3: 0x0
9636 00:45:20.207538 INFO: [APUAPC] D2_APC_0: 0xffffffff
9637 00:45:20.210882 INFO: [APUAPC] D2_APC_1: 0xffffffff
9638 00:45:20.214121 INFO: [APUAPC] D2_APC_2: 0x3fffff
9639 00:45:20.217403 INFO: [APUAPC] D2_APC_3: 0x0
9640 00:45:20.220993 INFO: [APUAPC] D3_APC_0: 0xffffffff
9641 00:45:20.224205 INFO: [APUAPC] D3_APC_1: 0xffffffff
9642 00:45:20.227698 INFO: [APUAPC] D3_APC_2: 0x3fffff
9643 00:45:20.230618 INFO: [APUAPC] D3_APC_3: 0x0
9644 00:45:20.233994 INFO: [APUAPC] D4_APC_0: 0xffffffff
9645 00:45:20.237676 INFO: [APUAPC] D4_APC_1: 0xffffffff
9646 00:45:20.240858 INFO: [APUAPC] D4_APC_2: 0x3fffff
9647 00:45:20.243975 INFO: [APUAPC] D4_APC_3: 0x0
9648 00:45:20.247095 INFO: [APUAPC] D5_APC_0: 0xffffffff
9649 00:45:20.250515 INFO: [APUAPC] D5_APC_1: 0xffffffff
9650 00:45:20.253870 INFO: [APUAPC] D5_APC_2: 0x3fffff
9651 00:45:20.257216 INFO: [APUAPC] D5_APC_3: 0x0
9652 00:45:20.260622 INFO: [APUAPC] D6_APC_0: 0xffffffff
9653 00:45:20.263773 INFO: [APUAPC] D6_APC_1: 0xffffffff
9654 00:45:20.267413 INFO: [APUAPC] D6_APC_2: 0x3fffff
9655 00:45:20.270586 INFO: [APUAPC] D6_APC_3: 0x0
9656 00:45:20.273594 INFO: [APUAPC] D7_APC_0: 0xffffffff
9657 00:45:20.276946 INFO: [APUAPC] D7_APC_1: 0xffffffff
9658 00:45:20.280017 INFO: [APUAPC] D7_APC_2: 0x3fffff
9659 00:45:20.283724 INFO: [APUAPC] D7_APC_3: 0x0
9660 00:45:20.286932 INFO: [APUAPC] D8_APC_0: 0xffffffff
9661 00:45:20.290091 INFO: [APUAPC] D8_APC_1: 0xffffffff
9662 00:45:20.293404 INFO: [APUAPC] D8_APC_2: 0x3fffff
9663 00:45:20.296886 INFO: [APUAPC] D8_APC_3: 0x0
9664 00:45:20.300032 INFO: [APUAPC] D9_APC_0: 0xffffffff
9665 00:45:20.303238 INFO: [APUAPC] D9_APC_1: 0xffffffff
9666 00:45:20.306675 INFO: [APUAPC] D9_APC_2: 0x3fffff
9667 00:45:20.310003 INFO: [APUAPC] D9_APC_3: 0x0
9668 00:45:20.313723 INFO: [APUAPC] D10_APC_0: 0xffffffff
9669 00:45:20.317191 INFO: [APUAPC] D10_APC_1: 0xffffffff
9670 00:45:20.319873 INFO: [APUAPC] D10_APC_2: 0x3fffff
9671 00:45:20.323081 INFO: [APUAPC] D10_APC_3: 0x0
9672 00:45:20.326326 INFO: [APUAPC] D11_APC_0: 0xffffffff
9673 00:45:20.329900 INFO: [APUAPC] D11_APC_1: 0xffffffff
9674 00:45:20.332927 INFO: [APUAPC] D11_APC_2: 0x3fffff
9675 00:45:20.336625 INFO: [APUAPC] D11_APC_3: 0x0
9676 00:45:20.340280 INFO: [APUAPC] D12_APC_0: 0xffffffff
9677 00:45:20.343130 INFO: [APUAPC] D12_APC_1: 0xffffffff
9678 00:45:20.346463 INFO: [APUAPC] D12_APC_2: 0x3fffff
9679 00:45:20.349862 INFO: [APUAPC] D12_APC_3: 0x0
9680 00:45:20.353022 INFO: [APUAPC] D13_APC_0: 0xffffffff
9681 00:45:20.356368 INFO: [APUAPC] D13_APC_1: 0xffffffff
9682 00:45:20.359715 INFO: [APUAPC] D13_APC_2: 0x3fffff
9683 00:45:20.363019 INFO: [APUAPC] D13_APC_3: 0x0
9684 00:45:20.366254 INFO: [APUAPC] D14_APC_0: 0xffffffff
9685 00:45:20.369524 INFO: [APUAPC] D14_APC_1: 0xffffffff
9686 00:45:20.372991 INFO: [APUAPC] D14_APC_2: 0x3fffff
9687 00:45:20.376235 INFO: [APUAPC] D14_APC_3: 0x0
9688 00:45:20.379759 INFO: [APUAPC] D15_APC_0: 0xffffffff
9689 00:45:20.383411 INFO: [APUAPC] D15_APC_1: 0xffffffff
9690 00:45:20.386512 INFO: [APUAPC] D15_APC_2: 0x3fffff
9691 00:45:20.390061 INFO: [APUAPC] D15_APC_3: 0x0
9692 00:45:20.393277 INFO: [APUAPC] APC_CON: 0x4
9693 00:45:20.396189 INFO: [NOCDAPC] D0_APC_0: 0x0
9694 00:45:20.399753 INFO: [NOCDAPC] D0_APC_1: 0x0
9695 00:45:20.400427 INFO: [NOCDAPC] D1_APC_0: 0x0
9696 00:45:20.402931 INFO: [NOCDAPC] D1_APC_1: 0xfff
9697 00:45:20.406365 INFO: [NOCDAPC] D2_APC_0: 0x0
9698 00:45:20.409479 INFO: [NOCDAPC] D2_APC_1: 0xfff
9699 00:45:20.412856 INFO: [NOCDAPC] D3_APC_0: 0x0
9700 00:45:20.416583 INFO: [NOCDAPC] D3_APC_1: 0xfff
9701 00:45:20.419509 INFO: [NOCDAPC] D4_APC_0: 0x0
9702 00:45:20.422890 INFO: [NOCDAPC] D4_APC_1: 0xfff
9703 00:45:20.426427 INFO: [NOCDAPC] D5_APC_0: 0x0
9704 00:45:20.429642 INFO: [NOCDAPC] D5_APC_1: 0xfff
9705 00:45:20.432946 INFO: [NOCDAPC] D6_APC_0: 0x0
9706 00:45:20.433460 INFO: [NOCDAPC] D6_APC_1: 0xfff
9707 00:45:20.436069 INFO: [NOCDAPC] D7_APC_0: 0x0
9708 00:45:20.439590 INFO: [NOCDAPC] D7_APC_1: 0xfff
9709 00:45:20.442946 INFO: [NOCDAPC] D8_APC_0: 0x0
9710 00:45:20.446144 INFO: [NOCDAPC] D8_APC_1: 0xfff
9711 00:45:20.449506 INFO: [NOCDAPC] D9_APC_0: 0x0
9712 00:45:20.452828 INFO: [NOCDAPC] D9_APC_1: 0xfff
9713 00:45:20.456385 INFO: [NOCDAPC] D10_APC_0: 0x0
9714 00:45:20.459570 INFO: [NOCDAPC] D10_APC_1: 0xfff
9715 00:45:20.462791 INFO: [NOCDAPC] D11_APC_0: 0x0
9716 00:45:20.466038 INFO: [NOCDAPC] D11_APC_1: 0xfff
9717 00:45:20.469573 INFO: [NOCDAPC] D12_APC_0: 0x0
9718 00:45:20.472605 INFO: [NOCDAPC] D12_APC_1: 0xfff
9719 00:45:20.472995 INFO: [NOCDAPC] D13_APC_0: 0x0
9720 00:45:20.475971 INFO: [NOCDAPC] D13_APC_1: 0xfff
9721 00:45:20.479374 INFO: [NOCDAPC] D14_APC_0: 0x0
9722 00:45:20.482938 INFO: [NOCDAPC] D14_APC_1: 0xfff
9723 00:45:20.486384 INFO: [NOCDAPC] D15_APC_0: 0x0
9724 00:45:20.489178 INFO: [NOCDAPC] D15_APC_1: 0xfff
9725 00:45:20.492582 INFO: [NOCDAPC] APC_CON: 0x4
9726 00:45:20.495841 INFO: [APUAPC] set_apusys_apc done
9727 00:45:20.499231 INFO: [DEVAPC] devapc_init done
9728 00:45:20.502694 INFO: GICv3 without legacy support detected.
9729 00:45:20.506148 INFO: ARM GICv3 driver initialized in EL3
9730 00:45:20.512641 INFO: Maximum SPI INTID supported: 639
9731 00:45:20.515737 INFO: BL31: Initializing runtime services
9732 00:45:20.519307 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9733 00:45:20.522452 INFO: SPM: enable CPC mode
9734 00:45:20.529076 INFO: mcdi ready for mcusys-off-idle and system suspend
9735 00:45:20.532383 INFO: BL31: Preparing for EL3 exit to normal world
9736 00:45:20.535581 INFO: Entry point address = 0x80000000
9737 00:45:20.539209 INFO: SPSR = 0x8
9738 00:45:20.544613
9739 00:45:20.545008
9740 00:45:20.545312
9741 00:45:20.548037 Starting depthcharge on Spherion...
9742 00:45:20.548505
9743 00:45:20.548809 Wipe memory regions:
9744 00:45:20.549086
9745 00:45:20.551161 end: 2.2.3 depthcharge-start (duration 00:00:18) [common]
9746 00:45:20.551608 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
9747 00:45:20.551984 Setting prompt string to ['asurada:']
9748 00:45:20.552341 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:28)
9749 00:45:20.552932 [0x00000040000000, 0x00000054600000)
9750 00:45:20.673617
9751 00:45:20.674132 [0x00000054660000, 0x00000080000000)
9752 00:45:20.934254
9753 00:45:20.934763 [0x000000821a7280, 0x000000ffe64000)
9754 00:45:21.679190
9755 00:45:21.679980 [0x00000100000000, 0x00000140000000)
9756 00:45:22.060515
9757 00:45:22.063434 Initializing XHCI USB controller at 0x11200000.
9758 00:45:23.101669
9759 00:45:23.104493 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9760 00:45:23.104984
9761 00:45:23.105316
9762 00:45:23.106088 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9764 00:45:23.207537 asurada: tftpboot 192.168.201.1 14368417/tftp-deploy-fnw4d_c7/kernel/image.itb 14368417/tftp-deploy-fnw4d_c7/kernel/cmdline
9765 00:45:23.208300 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9766 00:45:23.208806 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:25)
9767 00:45:23.212924 tftpboot 192.168.201.1 14368417/tftp-deploy-fnw4d_c7/kernel/image.ittp-deploy-fnw4d_c7/kernel/cmdline
9768 00:45:23.213367
9769 00:45:23.213702 Waiting for link
9770 00:45:23.371223
9771 00:45:23.371731 R8152: Initializing
9772 00:45:23.372065
9773 00:45:23.374140 Version 9 (ocp_data = 6010)
9774 00:45:23.374612
9775 00:45:23.377580 R8152: Done initializing
9776 00:45:23.378007
9777 00:45:23.378390 Adding net device
9778 00:45:25.389347
9779 00:45:25.389856 done.
9780 00:45:25.390185
9781 00:45:25.390542 MAC: 00:e0:4c:68:03:bd
9782 00:45:25.390840
9783 00:45:25.392450 Sending DHCP discover... done.
9784 00:45:25.392879
9785 00:45:35.773234 Waiting for reply... R8152: Bulk read error 0xffffffbf
9786 00:45:35.773388
9787 00:45:35.776456 Receive failed.
9788 00:45:35.776543
9789 00:45:35.776601 done.
9790 00:45:35.776654
9791 00:45:35.779765 Sending DHCP request... done.
9792 00:45:35.779847
9793 00:45:35.783039 Waiting for reply... done.
9794 00:45:35.783115
9795 00:45:35.783173 My ip is 192.168.201.16
9796 00:45:35.783226
9797 00:45:35.786488 The DHCP server ip is 192.168.201.1
9798 00:45:35.786565
9799 00:45:35.792959 TFTP server IP predefined by user: 192.168.201.1
9800 00:45:35.793092
9801 00:45:35.799656 Bootfile predefined by user: 14368417/tftp-deploy-fnw4d_c7/kernel/image.itb
9802 00:45:35.799768
9803 00:45:35.802876 Sending tftp read request... done.
9804 00:45:35.802958
9805 00:45:35.806571 Waiting for the transfer...
9806 00:45:35.806650
9807 00:45:36.074217 00000000 ################################################################
9808 00:45:36.074363
9809 00:45:36.350918 00080000 ################################################################
9810 00:45:36.351051
9811 00:45:36.629604 00100000 ################################################################
9812 00:45:36.629737
9813 00:45:36.900666 00180000 ################################################################
9814 00:45:36.900802
9815 00:45:37.157741 00200000 ################################################################
9816 00:45:37.157877
9817 00:45:37.419940 00280000 ################################################################
9818 00:45:37.420074
9819 00:45:37.683974 00300000 ################################################################
9820 00:45:37.684108
9821 00:45:37.981238 00380000 ################################################################
9822 00:45:37.981373
9823 00:45:38.276536 00400000 ################################################################
9824 00:45:38.276668
9825 00:45:38.571552 00480000 ################################################################
9826 00:45:38.571682
9827 00:45:38.846443 00500000 ################################################################
9828 00:45:38.846596
9829 00:45:39.139134 00580000 ################################################################
9830 00:45:39.139267
9831 00:45:39.410507 00600000 ################################################################
9832 00:45:39.410641
9833 00:45:39.685990 00680000 ################################################################
9834 00:45:39.686152
9835 00:45:39.980119 00700000 ################################################################
9836 00:45:39.980253
9837 00:45:40.242879 00780000 ################################################################
9838 00:45:40.243014
9839 00:45:40.507068 00800000 ################################################################
9840 00:45:40.507198
9841 00:45:40.784070 00880000 ################################################################
9842 00:45:40.784202
9843 00:45:41.043830 00900000 ################################################################
9844 00:45:41.043968
9845 00:45:41.306792 00980000 ################################################################
9846 00:45:41.306926
9847 00:45:41.572338 00a00000 ################################################################
9848 00:45:41.572514
9849 00:45:41.856683 00a80000 ################################################################
9850 00:45:41.856902
9851 00:45:42.122354 00b00000 ################################################################
9852 00:45:42.122486
9853 00:45:42.382638 00b80000 ################################################################
9854 00:45:42.382773
9855 00:45:42.664276 00c00000 ################################################################
9856 00:45:42.664409
9857 00:45:42.957531 00c80000 ################################################################
9858 00:45:42.957665
9859 00:45:43.250573 00d00000 ################################################################
9860 00:45:43.250729
9861 00:45:43.544140 00d80000 ################################################################
9862 00:45:43.544272
9863 00:45:43.833413 00e00000 ################################################################
9864 00:45:43.833548
9865 00:45:44.104522 00e80000 ################################################################
9866 00:45:44.104655
9867 00:45:44.388175 00f00000 ################################################################
9868 00:45:44.388328
9869 00:45:44.663473 00f80000 ################################################################
9870 00:45:44.663607
9871 00:45:44.933503 01000000 ################################################################
9872 00:45:44.933642
9873 00:45:45.230031 01080000 ################################################################
9874 00:45:45.230186
9875 00:45:45.504575 01100000 ################################################################
9876 00:45:45.504705
9877 00:45:45.780539 01180000 ################################################################
9878 00:45:45.780669
9879 00:45:46.077644 01200000 ################################################################
9880 00:45:46.077777
9881 00:45:46.373150 01280000 ################################################################
9882 00:45:46.373279
9883 00:45:46.668404 01300000 ################################################################
9884 00:45:46.668534
9885 00:45:46.924094 01380000 ################################################################
9886 00:45:46.924226
9887 00:45:47.202604 01400000 ################################################################
9888 00:45:47.202733
9889 00:45:47.484937 01480000 ################################################################
9890 00:45:47.485068
9891 00:45:47.766751 01500000 ################################################################
9892 00:45:47.766894
9893 00:45:48.033639 01580000 ################################################################
9894 00:45:48.033765
9895 00:45:48.310539 01600000 ################################################################
9896 00:45:48.310688
9897 00:45:48.602654 01680000 ################################################################
9898 00:45:48.602785
9899 00:45:48.898375 01700000 ################################################################
9900 00:45:48.898503
9901 00:45:49.201321 01780000 ################################################################
9902 00:45:49.201447
9903 00:45:49.518730 01800000 ################################################################
9904 00:45:49.518856
9905 00:45:49.813664 01880000 ################################################################
9906 00:45:49.813790
9907 00:45:50.115426 01900000 ################################################################
9908 00:45:50.115550
9909 00:45:50.407331 01980000 ################################################################
9910 00:45:50.407453
9911 00:45:50.681705 01a00000 ################################################################
9912 00:45:50.681828
9913 00:45:50.944531 01a80000 ################################################################
9914 00:45:50.944654
9915 00:45:51.227785 01b00000 ################################################################
9916 00:45:51.227913
9917 00:45:51.513682 01b80000 ################################################################
9918 00:45:51.513809
9919 00:45:51.796685 01c00000 ################################################################
9920 00:45:51.796812
9921 00:45:52.051908 01c80000 ################################################################
9922 00:45:52.052057
9923 00:45:52.320030 01d00000 ################################################################
9924 00:45:52.320155
9925 00:45:52.584762 01d80000 ################################################################
9926 00:45:52.584888
9927 00:45:52.837096 01e00000 ################################################################
9928 00:45:52.837238
9929 00:45:53.111011 01e80000 ################################################################
9930 00:45:53.111139
9931 00:45:53.393263 01f00000 ################################################################
9932 00:45:53.393410
9933 00:45:53.682152 01f80000 ################################################################
9934 00:45:53.682290
9935 00:45:53.949579 02000000 ################################################################
9936 00:45:53.949706
9937 00:45:54.208741 02080000 ################################################################
9938 00:45:54.208884
9939 00:45:54.470048 02100000 ################################################################
9940 00:45:54.470173
9941 00:45:54.745562 02180000 ################################################################
9942 00:45:54.745694
9943 00:45:55.012730 02200000 ################################################################
9944 00:45:55.012855
9945 00:45:55.282721 02280000 ################################################################
9946 00:45:55.282848
9947 00:45:55.548585 02300000 ################################################################
9948 00:45:55.548715
9949 00:45:55.851296 02380000 ################################################################
9950 00:45:55.851417
9951 00:45:56.142516 02400000 ################################################################
9952 00:45:56.142644
9953 00:45:56.427713 02480000 ################################################################
9954 00:45:56.427860
9955 00:45:56.698418 02500000 ################################################################
9956 00:45:56.698543
9957 00:45:56.957647 02580000 ################################################################
9958 00:45:56.957793
9959 00:45:57.227111 02600000 ################################################################
9960 00:45:57.227232
9961 00:45:57.525142 02680000 ################################################################
9962 00:45:57.525277
9963 00:45:57.804687 02700000 ################################################################
9964 00:45:57.804836
9965 00:45:58.068993 02780000 ################################################################
9966 00:45:58.069118
9967 00:45:58.328688 02800000 ################################################################
9968 00:45:58.328812
9969 00:45:58.587899 02880000 ################################################################
9970 00:45:58.588026
9971 00:45:58.865537 02900000 ################################################################
9972 00:45:58.865660
9973 00:45:59.135559 02980000 ################################################################
9974 00:45:59.135684
9975 00:45:59.422329 02a00000 ################################################################
9976 00:45:59.422454
9977 00:45:59.706202 02a80000 ################################################################
9978 00:45:59.706331
9979 00:45:59.967939 02b00000 ################################################################
9980 00:45:59.968083
9981 00:46:00.233854 02b80000 ################################################################
9982 00:46:00.233977
9983 00:46:00.492572 02c00000 ################################################################
9984 00:46:00.492699
9985 00:46:00.746054 02c80000 ################################################################
9986 00:46:00.746198
9987 00:46:01.009058 02d00000 ################################################################
9988 00:46:01.009216
9989 00:46:01.266806 02d80000 ################################################################
9990 00:46:01.266929
9991 00:46:01.520510 02e00000 ################################################################
9992 00:46:01.520634
9993 00:46:01.778191 02e80000 ################################################################
9994 00:46:01.778366
9995 00:46:02.050776 02f00000 ################################################################
9996 00:46:02.050900
9997 00:46:02.431419 02f80000 ################################################################
9998 00:46:02.431894
9999 00:46:02.824371 03000000 ################################################################
10000 00:46:02.824957
10001 00:46:03.228806 03080000 ################################################################
10002 00:46:03.229287
10003 00:46:03.594650 03100000 ################################################################
10004 00:46:03.594778
10005 00:46:03.870328 03180000 ################################################################
10006 00:46:03.870460
10007 00:46:04.166939 03200000 ################################################################
10008 00:46:04.167062
10009 00:46:04.467251 03280000 ################################################################
10010 00:46:04.467376
10011 00:46:04.751804 03300000 ################################################################
10012 00:46:04.751919
10013 00:46:04.967444 03380000 ################################################ done.
10014 00:46:04.970842
10015 00:46:04.970928 The bootfile was 54391386 bytes long.
10016 00:46:04.974116
10017 00:46:04.974230 Sending tftp read request... done.
10018 00:46:04.974297
10019 00:46:04.977259 Waiting for the transfer...
10020 00:46:04.977374
10021 00:46:04.980737 00000000 # done.
10022 00:46:04.980833
10023 00:46:04.987612 Command line loaded dynamically from TFTP file: 14368417/tftp-deploy-fnw4d_c7/kernel/cmdline
10024 00:46:04.987716
10025 00:46:05.000691 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10026 00:46:05.000900
10027 00:46:05.004168 Loading FIT.
10028 00:46:05.004378
10029 00:46:05.007367 Image ramdisk-1 has 41215728 bytes.
10030 00:46:05.007595
10031 00:46:05.007727 Image fdt-1 has 47258 bytes.
10032 00:46:05.007846
10033 00:46:05.010504 Image kernel-1 has 13126376 bytes.
10034 00:46:05.010740
10035 00:46:05.020740 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10036 00:46:05.021095
10037 00:46:05.037636 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10038 00:46:05.038097
10039 00:46:05.044006 Choosing best match conf-1 for compat google,spherion-rev3.
10040 00:46:05.047764
10041 00:46:05.052458 Connected to device vid:did:rid of 1ae0:0028:00
10042 00:46:05.060303
10043 00:46:05.063535 tpm_get_response: command 0x17b, return code 0x0
10044 00:46:05.063895
10045 00:46:05.066708 ec_init: CrosEC protocol v3 supported (256, 248)
10046 00:46:05.070694
10047 00:46:05.073886 tpm_cleanup: add release locality here.
10048 00:46:05.074423
10049 00:46:05.074900 Shutting down all USB controllers.
10050 00:46:05.077322
10051 00:46:05.077852 Removing current net device
10052 00:46:05.078285
10053 00:46:05.084133 Exiting depthcharge with code 4 at timestamp: 72776228
10054 00:46:05.084495
10055 00:46:05.087477 LZMA decompressing kernel-1 to 0x821a6718
10056 00:46:05.087833
10057 00:46:05.090755 LZMA decompressing kernel-1 to 0x40000000
10058 00:46:06.706832
10059 00:46:06.707333 jumping to kernel
10060 00:46:06.709748 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10061 00:46:06.710312 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10062 00:46:06.710694 Setting prompt string to ['Linux version [0-9]']
10063 00:46:06.711042 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10064 00:46:06.711390 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10065 00:46:06.758321
10066 00:46:06.761490 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10067 00:46:06.764795 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10068 00:46:06.765314 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10069 00:46:06.765687 Setting prompt string to []
10070 00:46:06.766088 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10071 00:46:06.766604 Using line separator: #'\n'#
10072 00:46:06.766930 No login prompt set.
10073 00:46:06.767253 Parsing kernel messages
10074 00:46:06.767543 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10075 00:46:06.768063 [login-action] Waiting for messages, (timeout 00:03:42)
10076 00:46:06.768475 Waiting using forced prompt support (timeout 00:01:51)
10077 00:46:06.784851 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232175-arm64-gcc-10-defconfig-arm64-chromebook-7lg8d) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024
10078 00:46:06.787170 [ 0.000000] random: crng init done
10079 00:46:06.793890 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10080 00:46:06.797191 [ 0.000000] efi: UEFI not found.
10081 00:46:06.804188 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10082 00:46:06.810628 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10083 00:46:06.820868 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10084 00:46:06.830978 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10085 00:46:06.837533 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10086 00:46:06.843829 [ 0.000000] printk: bootconsole [mtk8250] enabled
10087 00:46:06.850620 [ 0.000000] NUMA: No NUMA configuration found
10088 00:46:06.857254 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10089 00:46:06.861085 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10090 00:46:06.863664 [ 0.000000] Zone ranges:
10091 00:46:06.870123 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10092 00:46:06.873568 [ 0.000000] DMA32 empty
10093 00:46:06.880015 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10094 00:46:06.883405 [ 0.000000] Movable zone start for each node
10095 00:46:06.886724 [ 0.000000] Early memory node ranges
10096 00:46:06.893595 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10097 00:46:06.900081 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10098 00:46:06.906525 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10099 00:46:06.913056 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10100 00:46:06.919860 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10101 00:46:06.926198 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10102 00:46:06.956942 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10103 00:46:06.963643 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10104 00:46:06.969679 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10105 00:46:06.973112 [ 0.000000] psci: probing for conduit method from DT.
10106 00:46:06.979921 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10107 00:46:06.983248 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10108 00:46:06.990068 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10109 00:46:06.992868 [ 0.000000] psci: SMC Calling Convention v1.2
10110 00:46:06.999613 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10111 00:46:07.002888 [ 0.000000] Detected VIPT I-cache on CPU0
10112 00:46:07.009543 [ 0.000000] CPU features: detected: GIC system register CPU interface
10113 00:46:07.016322 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10114 00:46:07.022460 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10115 00:46:07.029604 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10116 00:46:07.035881 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10117 00:46:07.045896 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10118 00:46:07.049509 [ 0.000000] alternatives: applying boot alternatives
10119 00:46:07.055648 [ 0.000000] Fallback order for Node 0: 0
10120 00:46:07.062536 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10121 00:46:07.065773 [ 0.000000] Policy zone: Normal
10122 00:46:07.079085 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10123 00:46:07.088451 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10124 00:46:07.098786 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10125 00:46:07.109301 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10126 00:46:07.115628 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10127 00:46:07.118343 <6>[ 0.000000] software IO TLB: area num 8.
10128 00:46:07.174007 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10129 00:46:07.254893 <6>[ 0.000000] Memory: 3809396K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 349068K reserved, 32768K cma-reserved)
10130 00:46:07.261359 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10131 00:46:07.268113 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10132 00:46:07.271432 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10133 00:46:07.278447 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10134 00:46:07.284800 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10135 00:46:07.287684 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10136 00:46:07.297754 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10137 00:46:07.304749 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10138 00:46:07.311123 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10139 00:46:07.317967 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10140 00:46:07.321237 <6>[ 0.000000] GICv3: 608 SPIs implemented
10141 00:46:07.324485 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10142 00:46:07.331232 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10143 00:46:07.334632 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10144 00:46:07.340967 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10145 00:46:07.354192 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10146 00:46:07.367200 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10147 00:46:07.373741 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10148 00:46:07.381783 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10149 00:46:07.394971 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10150 00:46:07.401978 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10151 00:46:07.408613 <6>[ 0.009175] Console: colour dummy device 80x25
10152 00:46:07.418484 <6>[ 0.013931] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10153 00:46:07.424525 <6>[ 0.024372] pid_max: default: 32768 minimum: 301
10154 00:46:07.428138 <6>[ 0.029242] LSM: Security Framework initializing
10155 00:46:07.435294 <6>[ 0.034157] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10156 00:46:07.444704 <6>[ 0.041811] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10157 00:46:07.451178 <6>[ 0.051051] cblist_init_generic: Setting adjustable number of callback queues.
10158 00:46:07.457600 <6>[ 0.058493] cblist_init_generic: Setting shift to 3 and lim to 1.
10159 00:46:07.468325 <6>[ 0.064833] cblist_init_generic: Setting adjustable number of callback queues.
10160 00:46:07.470922 <6>[ 0.072306] cblist_init_generic: Setting shift to 3 and lim to 1.
10161 00:46:07.477802 <6>[ 0.078710] rcu: Hierarchical SRCU implementation.
10162 00:46:07.484028 <6>[ 0.083724] rcu: Max phase no-delay instances is 1000.
10163 00:46:07.490751 <6>[ 0.090751] EFI services will not be available.
10164 00:46:07.493929 <6>[ 0.095706] smp: Bringing up secondary CPUs ...
10165 00:46:07.502208 <6>[ 0.100755] Detected VIPT I-cache on CPU1
10166 00:46:07.508764 <6>[ 0.100823] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10167 00:46:07.515499 <6>[ 0.100854] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10168 00:46:07.518706 <6>[ 0.101192] Detected VIPT I-cache on CPU2
10169 00:46:07.525324 <6>[ 0.101243] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10170 00:46:07.534921 <6>[ 0.101261] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10171 00:46:07.538769 <6>[ 0.101525] Detected VIPT I-cache on CPU3
10172 00:46:07.545196 <6>[ 0.101573] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10173 00:46:07.551542 <6>[ 0.101587] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10174 00:46:07.555042 <6>[ 0.101890] CPU features: detected: Spectre-v4
10175 00:46:07.561703 <6>[ 0.101896] CPU features: detected: Spectre-BHB
10176 00:46:07.565113 <6>[ 0.101901] Detected PIPT I-cache on CPU4
10177 00:46:07.571527 <6>[ 0.101962] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10178 00:46:07.577892 <6>[ 0.101979] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10179 00:46:07.584415 <6>[ 0.102272] Detected PIPT I-cache on CPU5
10180 00:46:07.591095 <6>[ 0.102334] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10181 00:46:07.597841 <6>[ 0.102351] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10182 00:46:07.601394 <6>[ 0.102633] Detected PIPT I-cache on CPU6
10183 00:46:07.608180 <6>[ 0.102695] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10184 00:46:07.614545 <6>[ 0.102712] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10185 00:46:07.620936 <6>[ 0.103010] Detected PIPT I-cache on CPU7
10186 00:46:07.627809 <6>[ 0.103075] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10187 00:46:07.634458 <6>[ 0.103091] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10188 00:46:07.637699 <6>[ 0.103137] smp: Brought up 1 node, 8 CPUs
10189 00:46:07.644079 <6>[ 0.244374] SMP: Total of 8 processors activated.
10190 00:46:07.647478 <6>[ 0.249294] CPU features: detected: 32-bit EL0 Support
10191 00:46:07.657708 <6>[ 0.254691] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10192 00:46:07.664236 <6>[ 0.263491] CPU features: detected: Common not Private translations
10193 00:46:07.670930 <6>[ 0.269967] CPU features: detected: CRC32 instructions
10194 00:46:07.673856 <6>[ 0.275319] CPU features: detected: RCpc load-acquire (LDAPR)
10195 00:46:07.680695 <6>[ 0.281279] CPU features: detected: LSE atomic instructions
10196 00:46:07.687280 <6>[ 0.287060] CPU features: detected: Privileged Access Never
10197 00:46:07.693721 <6>[ 0.292840] CPU features: detected: RAS Extension Support
10198 00:46:07.700343 <6>[ 0.298449] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10199 00:46:07.703795 <6>[ 0.305669] CPU: All CPU(s) started at EL2
10200 00:46:07.710160 <6>[ 0.309985] alternatives: applying system-wide alternatives
10201 00:46:07.718557 <6>[ 0.319936] devtmpfs: initialized
10202 00:46:07.733849 <6>[ 0.328126] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10203 00:46:07.739945 <6>[ 0.338086] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10204 00:46:07.746978 <6>[ 0.346353] pinctrl core: initialized pinctrl subsystem
10205 00:46:07.750172 <6>[ 0.353051] DMI not present or invalid.
10206 00:46:07.756926 <6>[ 0.357454] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10207 00:46:07.766652 <6>[ 0.364314] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10208 00:46:07.773395 <6>[ 0.371762] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10209 00:46:07.783452 <6>[ 0.379857] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10210 00:46:07.786682 <6>[ 0.388012] audit: initializing netlink subsys (disabled)
10211 00:46:07.796504 <5>[ 0.393707] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10212 00:46:07.803230 <6>[ 0.394412] thermal_sys: Registered thermal governor 'step_wise'
10213 00:46:07.809537 <6>[ 0.401674] thermal_sys: Registered thermal governor 'power_allocator'
10214 00:46:07.813086 <6>[ 0.407929] cpuidle: using governor menu
10215 00:46:07.819804 <6>[ 0.418888] NET: Registered PF_QIPCRTR protocol family
10216 00:46:07.826362 <6>[ 0.424361] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10217 00:46:07.829348 <6>[ 0.431458] ASID allocator initialised with 32768 entries
10218 00:46:07.836675 <6>[ 0.438023] Serial: AMBA PL011 UART driver
10219 00:46:07.845767 <4>[ 0.446830] Trying to register duplicate clock ID: 134
10220 00:46:07.903831 <6>[ 0.508373] KASLR enabled
10221 00:46:07.918169 <6>[ 0.516106] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10222 00:46:07.925279 <6>[ 0.523118] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10223 00:46:07.931614 <6>[ 0.529610] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10224 00:46:07.938072 <6>[ 0.536613] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10225 00:46:07.944852 <6>[ 0.543102] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10226 00:46:07.951551 <6>[ 0.550106] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10227 00:46:07.957910 <6>[ 0.556593] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10228 00:46:07.964657 <6>[ 0.563599] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10229 00:46:07.967959 <6>[ 0.571109] ACPI: Interpreter disabled.
10230 00:46:07.976380 <6>[ 0.577520] iommu: Default domain type: Translated
10231 00:46:07.983378 <6>[ 0.582631] iommu: DMA domain TLB invalidation policy: strict mode
10232 00:46:07.986508 <5>[ 0.589289] SCSI subsystem initialized
10233 00:46:07.993015 <6>[ 0.593452] usbcore: registered new interface driver usbfs
10234 00:46:07.999659 <6>[ 0.599184] usbcore: registered new interface driver hub
10235 00:46:08.003015 <6>[ 0.604737] usbcore: registered new device driver usb
10236 00:46:08.009868 <6>[ 0.610832] pps_core: LinuxPPS API ver. 1 registered
10237 00:46:08.019819 <6>[ 0.616025] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10238 00:46:08.023052 <6>[ 0.625370] PTP clock support registered
10239 00:46:08.026361 <6>[ 0.629615] EDAC MC: Ver: 3.0.0
10240 00:46:08.034167 <6>[ 0.634754] FPGA manager framework
10241 00:46:08.036890 <6>[ 0.638437] Advanced Linux Sound Architecture Driver Initialized.
10242 00:46:08.040685 <6>[ 0.645209] vgaarb: loaded
10243 00:46:08.047487 <6>[ 0.648351] clocksource: Switched to clocksource arch_sys_counter
10244 00:46:08.054423 <5>[ 0.654796] VFS: Disk quotas dquot_6.6.0
10245 00:46:08.060605 <6>[ 0.658979] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10246 00:46:08.063736 <6>[ 0.666171] pnp: PnP ACPI: disabled
10247 00:46:08.071850 <6>[ 0.672899] NET: Registered PF_INET protocol family
10248 00:46:08.078313 <6>[ 0.678277] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10249 00:46:08.090426 <6>[ 0.688303] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10250 00:46:08.100709 <6>[ 0.697094] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10251 00:46:08.107572 <6>[ 0.705061] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10252 00:46:08.113428 <6>[ 0.713463] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10253 00:46:08.124688 <6>[ 0.722121] TCP: Hash tables configured (established 32768 bind 32768)
10254 00:46:08.130906 <6>[ 0.728976] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10255 00:46:08.137668 <6>[ 0.735998] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10256 00:46:08.144042 <6>[ 0.743518] NET: Registered PF_UNIX/PF_LOCAL protocol family
10257 00:46:08.150775 <6>[ 0.749643] RPC: Registered named UNIX socket transport module.
10258 00:46:08.153896 <6>[ 0.755797] RPC: Registered udp transport module.
10259 00:46:08.160440 <6>[ 0.760729] RPC: Registered tcp transport module.
10260 00:46:08.167176 <6>[ 0.765659] RPC: Registered tcp NFSv4.1 backchannel transport module.
10261 00:46:08.170609 <6>[ 0.772324] PCI: CLS 0 bytes, default 64
10262 00:46:08.173726 <6>[ 0.776617] Unpacking initramfs...
10263 00:46:08.202396 <6>[ 0.800409] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10264 00:46:08.212817 <6>[ 0.809097] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10265 00:46:08.215974 <6>[ 0.817904] kvm [1]: IPA Size Limit: 40 bits
10266 00:46:08.222481 <6>[ 0.822430] kvm [1]: GICv3: no GICV resource entry
10267 00:46:08.226119 <6>[ 0.827452] kvm [1]: disabling GICv2 emulation
10268 00:46:08.232490 <6>[ 0.832142] kvm [1]: GIC system register CPU interface enabled
10269 00:46:08.235705 <6>[ 0.838297] kvm [1]: vgic interrupt IRQ18
10270 00:46:08.242338 <6>[ 0.842653] kvm [1]: VHE mode initialized successfully
10271 00:46:08.249062 <5>[ 0.849092] Initialise system trusted keyrings
10272 00:46:08.255462 <6>[ 0.853874] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10273 00:46:08.262736 <6>[ 0.863897] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10274 00:46:08.269382 <5>[ 0.870260] NFS: Registering the id_resolver key type
10275 00:46:08.272512 <5>[ 0.875556] Key type id_resolver registered
10276 00:46:08.279073 <5>[ 0.879973] Key type id_legacy registered
10277 00:46:08.285624 <6>[ 0.884262] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10278 00:46:08.292218 <6>[ 0.891183] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10279 00:46:08.299168 <6>[ 0.898885] 9p: Installing v9fs 9p2000 file system support
10280 00:46:08.336014 <5>[ 0.937095] Key type asymmetric registered
10281 00:46:08.339246 <5>[ 0.941424] Asymmetric key parser 'x509' registered
10282 00:46:08.349404 <6>[ 0.946568] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10283 00:46:08.352645 <6>[ 0.954183] io scheduler mq-deadline registered
10284 00:46:08.355900 <6>[ 0.958944] io scheduler kyber registered
10285 00:46:08.374573 <6>[ 0.975686] EINJ: ACPI disabled.
10286 00:46:08.406971 <4>[ 1.001417] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10287 00:46:08.416753 <4>[ 1.012030] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10288 00:46:08.431639 <6>[ 1.032734] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10289 00:46:08.439477 <6>[ 1.040674] printk: console [ttyS0] disabled
10290 00:46:08.467486 <6>[ 1.065300] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10291 00:46:08.474179 <6>[ 1.074770] printk: console [ttyS0] enabled
10292 00:46:08.477258 <6>[ 1.074770] printk: console [ttyS0] enabled
10293 00:46:08.483999 <6>[ 1.083664] printk: bootconsole [mtk8250] disabled
10294 00:46:08.487208 <6>[ 1.083664] printk: bootconsole [mtk8250] disabled
10295 00:46:08.493816 <6>[ 1.094679] SuperH (H)SCI(F) driver initialized
10296 00:46:08.497427 <6>[ 1.099966] msm_serial: driver initialized
10297 00:46:08.510844 <6>[ 1.108811] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10298 00:46:08.521143 <6>[ 1.117352] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10299 00:46:08.528138 <6>[ 1.125894] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10300 00:46:08.537361 <6>[ 1.134521] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10301 00:46:08.544099 <6>[ 1.143227] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10302 00:46:08.554023 <6>[ 1.151940] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10303 00:46:08.564241 <6>[ 1.160479] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10304 00:46:08.570651 <6>[ 1.169272] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10305 00:46:08.580230 <6>[ 1.177820] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10306 00:46:08.592048 <6>[ 1.193436] loop: module loaded
10307 00:46:08.598746 <6>[ 1.199286] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10308 00:46:08.620987 <4>[ 1.221995] mtk-pmic-keys: Failed to locate of_node [id: -1]
10309 00:46:08.627813 <6>[ 1.228815] megasas: 07.719.03.00-rc1
10310 00:46:08.637257 <6>[ 1.238443] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10311 00:46:08.646925 <6>[ 1.247753] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10312 00:46:08.662311 <6>[ 1.263560] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10313 00:46:08.717742 <6>[ 1.312552] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10314 00:46:09.916764 <6>[ 2.518137] Freeing initrd memory: 40244K
10315 00:46:09.928712 <6>[ 2.529661] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10316 00:46:09.939118 <6>[ 2.540655] tun: Universal TUN/TAP device driver, 1.6
10317 00:46:09.942407 <6>[ 2.546708] thunder_xcv, ver 1.0
10318 00:46:09.946120 <6>[ 2.550214] thunder_bgx, ver 1.0
10319 00:46:09.949159 <6>[ 2.553708] nicpf, ver 1.0
10320 00:46:09.959509 <6>[ 2.557711] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10321 00:46:09.963159 <6>[ 2.565187] hns3: Copyright (c) 2017 Huawei Corporation.
10322 00:46:09.969326 <6>[ 2.570775] hclge is initializing
10323 00:46:09.972825 <6>[ 2.574354] e1000: Intel(R) PRO/1000 Network Driver
10324 00:46:09.979633 <6>[ 2.579484] e1000: Copyright (c) 1999-2006 Intel Corporation.
10325 00:46:09.982894 <6>[ 2.585497] e1000e: Intel(R) PRO/1000 Network Driver
10326 00:46:09.989356 <6>[ 2.590712] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10327 00:46:09.996140 <6>[ 2.596900] igb: Intel(R) Gigabit Ethernet Network Driver
10328 00:46:10.002542 <6>[ 2.602550] igb: Copyright (c) 2007-2014 Intel Corporation.
10329 00:46:10.009674 <6>[ 2.608386] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10330 00:46:10.015819 <6>[ 2.614904] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10331 00:46:10.019177 <6>[ 2.621361] sky2: driver version 1.30
10332 00:46:10.025722 <6>[ 2.626288] usbcore: registered new device driver r8152-cfgselector
10333 00:46:10.032401 <6>[ 2.632823] usbcore: registered new interface driver r8152
10334 00:46:10.038895 <6>[ 2.638639] VFIO - User Level meta-driver version: 0.3
10335 00:46:10.045446 <6>[ 2.646857] usbcore: registered new interface driver usb-storage
10336 00:46:10.052298 <6>[ 2.653294] usbcore: registered new device driver onboard-usb-hub
10337 00:46:10.060962 <6>[ 2.662426] mt6397-rtc mt6359-rtc: registered as rtc0
10338 00:46:10.070815 <6>[ 2.667889] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:46:09 UTC (1718498769)
10339 00:46:10.074050 <6>[ 2.677449] i2c_dev: i2c /dev entries driver
10340 00:46:10.087919 <4>[ 2.689422] cpu cpu0: supply cpu not found, using dummy regulator
10341 00:46:10.095018 <4>[ 2.695847] cpu cpu1: supply cpu not found, using dummy regulator
10342 00:46:10.101440 <4>[ 2.702253] cpu cpu2: supply cpu not found, using dummy regulator
10343 00:46:10.108270 <4>[ 2.708677] cpu cpu3: supply cpu not found, using dummy regulator
10344 00:46:10.114497 <4>[ 2.715077] cpu cpu4: supply cpu not found, using dummy regulator
10345 00:46:10.121652 <4>[ 2.721471] cpu cpu5: supply cpu not found, using dummy regulator
10346 00:46:10.127763 <4>[ 2.727865] cpu cpu6: supply cpu not found, using dummy regulator
10347 00:46:10.134319 <4>[ 2.734265] cpu cpu7: supply cpu not found, using dummy regulator
10348 00:46:10.154493 <6>[ 2.755912] cpu cpu0: EM: created perf domain
10349 00:46:10.157998 <6>[ 2.760816] cpu cpu4: EM: created perf domain
10350 00:46:10.165426 <6>[ 2.766338] sdhci: Secure Digital Host Controller Interface driver
10351 00:46:10.171282 <6>[ 2.772771] sdhci: Copyright(c) Pierre Ossman
10352 00:46:10.178501 <6>[ 2.777683] Synopsys Designware Multimedia Card Interface Driver
10353 00:46:10.185393 <6>[ 2.784279] sdhci-pltfm: SDHCI platform and OF driver helper
10354 00:46:10.188048 <6>[ 2.784455] mmc0: CQHCI version 5.10
10355 00:46:10.194910 <6>[ 2.794332] ledtrig-cpu: registered to indicate activity on CPUs
10356 00:46:10.201554 <6>[ 2.801374] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10357 00:46:10.208337 <6>[ 2.808405] usbcore: registered new interface driver usbhid
10358 00:46:10.211092 <6>[ 2.814225] usbhid: USB HID core driver
10359 00:46:10.218112 <6>[ 2.818408] spi_master spi0: will run message pump with realtime priority
10360 00:46:10.261006 <6>[ 2.855642] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10361 00:46:10.279848 <6>[ 2.870806] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10362 00:46:10.282943 <6>[ 2.884901] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16814
10363 00:46:10.289865 <6>[ 2.891109] cros-ec-spi spi0.0: Chrome EC device registered
10364 00:46:10.296367 <6>[ 2.897181] mmc0: Command Queue Engine enabled
10365 00:46:10.303116 <6>[ 2.901952] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10366 00:46:10.306740 <6>[ 2.909566] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10367 00:46:10.317284 <6>[ 2.918202] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10368 00:46:10.324062 <6>[ 2.924988] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10369 00:46:10.330359 <6>[ 2.931018] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10370 00:46:10.337366 <6>[ 2.937482] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10371 00:46:10.346705 <6>[ 2.942460] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10372 00:46:10.353531 <6>[ 2.954549] NET: Registered PF_PACKET protocol family
10373 00:46:10.357015 <6>[ 2.959938] 9pnet: Installing 9P2000 support
10374 00:46:10.363270 <5>[ 2.964484] Key type dns_resolver registered
10375 00:46:10.366843 <6>[ 2.969443] registered taskstats version 1
10376 00:46:10.372972 <5>[ 2.973824] Loading compiled-in X.509 certificates
10377 00:46:10.402092 <4>[ 2.996591] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10378 00:46:10.411960 <4>[ 3.007319] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10379 00:46:10.423753 <6>[ 3.025058] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10380 00:46:10.430684 <6>[ 3.031858] xhci-mtk 11200000.usb: xHCI Host Controller
10381 00:46:10.437263 <6>[ 3.037357] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10382 00:46:10.447329 <6>[ 3.045207] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10383 00:46:10.454080 <6>[ 3.054637] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10384 00:46:10.461248 <6>[ 3.060730] xhci-mtk 11200000.usb: xHCI Host Controller
10385 00:46:10.467013 <6>[ 3.066210] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10386 00:46:10.473690 <6>[ 3.073861] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10387 00:46:10.480331 <6>[ 3.081545] hub 1-0:1.0: USB hub found
10388 00:46:10.483716 <6>[ 3.085566] hub 1-0:1.0: 1 port detected
10389 00:46:10.490316 <6>[ 3.089850] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10390 00:46:10.497207 <6>[ 3.098430] hub 2-0:1.0: USB hub found
10391 00:46:10.500073 <6>[ 3.102445] hub 2-0:1.0: 1 port detected
10392 00:46:10.508546 <6>[ 3.110027] mtk-msdc 11f70000.mmc: Got CD GPIO
10393 00:46:10.521659 <6>[ 3.119844] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10394 00:46:10.531711 <6>[ 3.128223] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10395 00:46:10.538126 <6>[ 3.136563] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10396 00:46:10.548292 <6>[ 3.144905] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10397 00:46:10.554665 <6>[ 3.153243] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10398 00:46:10.564708 <6>[ 3.161582] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10399 00:46:10.571463 <6>[ 3.169920] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10400 00:46:10.581094 <6>[ 3.178258] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10401 00:46:10.588274 <6>[ 3.186595] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10402 00:46:10.597720 <6>[ 3.194941] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10403 00:46:10.604277 <6>[ 3.203281] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10404 00:46:10.614464 <6>[ 3.211622] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10405 00:46:10.620965 <6>[ 3.219959] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10406 00:46:10.631034 <6>[ 3.228297] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10407 00:46:10.637316 <6>[ 3.236635] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10408 00:46:10.644278 <6>[ 3.245394] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10409 00:46:10.651105 <6>[ 3.252617] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10410 00:46:10.658157 <6>[ 3.259454] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10411 00:46:10.667922 <6>[ 3.266228] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10412 00:46:10.674764 <6>[ 3.273211] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10413 00:46:10.681209 <6>[ 3.280084] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10414 00:46:10.690961 <6>[ 3.289221] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10415 00:46:10.701457 <6>[ 3.298348] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10416 00:46:10.711064 <6>[ 3.307642] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10417 00:46:10.721213 <6>[ 3.317108] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10418 00:46:10.730810 <6>[ 3.326575] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10419 00:46:10.737560 <6>[ 3.335694] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10420 00:46:10.747234 <6>[ 3.345159] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10421 00:46:10.757490 <6>[ 3.354278] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10422 00:46:10.766906 <6>[ 3.363572] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10423 00:46:10.776836 <6>[ 3.373731] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10424 00:46:10.786835 <6>[ 3.385262] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10425 00:46:10.914505 <6>[ 3.512626] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10426 00:46:11.069123 <6>[ 3.670666] hub 1-1:1.0: USB hub found
10427 00:46:11.072601 <6>[ 3.675180] hub 1-1:1.0: 4 ports detected
10428 00:46:11.084602 <6>[ 3.685661] hub 1-1:1.0: USB hub found
10429 00:46:11.087302 <6>[ 3.690170] hub 1-1:1.0: 4 ports detected
10430 00:46:11.194361 <6>[ 3.792914] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10431 00:46:11.221539 <6>[ 3.822765] hub 2-1:1.0: USB hub found
10432 00:46:11.225229 <6>[ 3.827260] hub 2-1:1.0: 3 ports detected
10433 00:46:11.235391 <6>[ 3.836757] hub 2-1:1.0: USB hub found
10434 00:46:11.238715 <6>[ 3.841148] hub 2-1:1.0: 3 ports detected
10435 00:46:11.406523 <6>[ 4.004665] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10436 00:46:11.538432 <6>[ 4.140464] hub 1-1.4:1.0: USB hub found
10437 00:46:11.542084 <6>[ 4.145129] hub 1-1.4:1.0: 2 ports detected
10438 00:46:11.554430 <6>[ 4.156222] hub 1-1.4:1.0: USB hub found
10439 00:46:11.558473 <6>[ 4.160748] hub 1-1.4:1.0: 2 ports detected
10440 00:46:11.618355 <6>[ 4.216783] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10441 00:46:11.727073 <6>[ 4.325301] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10442 00:46:11.762774 <4>[ 4.360814] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10443 00:46:11.772598 <4>[ 4.369934] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10444 00:46:11.812571 <6>[ 4.414147] r8152 2-1.3:1.0 eth0: v1.12.13
10445 00:46:11.854114 <6>[ 4.452623] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10446 00:46:12.050349 <6>[ 4.648685] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10447 00:46:13.395241 <6>[ 5.997146] r8152 2-1.3:1.0 eth0: carrier on
10448 00:46:15.510422 <5>[ 6.024427] Sending DHCP requests .., OK
10449 00:46:15.517059 <6>[ 8.116808] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10450 00:46:15.520180 <6>[ 8.125101] IP-Config: Complete:
10451 00:46:15.533538 <6>[ 8.128598] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10452 00:46:15.540553 <6>[ 8.139303] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10453 00:46:15.547024 <6>[ 8.147920] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10454 00:46:15.553576 <6>[ 8.147929] nameserver0=192.168.201.1
10455 00:46:15.556690 <6>[ 8.160067] clk: Disabling unused clocks
10456 00:46:15.560372 <6>[ 8.165793] ALSA device list:
10457 00:46:15.566702 <6>[ 8.169036] No soundcards found.
10458 00:46:15.574942 <6>[ 8.176448] Freeing unused kernel memory: 8512K
10459 00:46:15.577892 <6>[ 8.181376] Run /init as init process
10460 00:46:15.608156 <6>[ 8.210076] NET: Registered PF_INET6 protocol family
10461 00:46:15.615479 <6>[ 8.216302] Segment Routing with IPv6
10462 00:46:15.617718 <6>[ 8.220276] In-situ OAM (IOAM) with IPv6
10463 00:46:15.657425 <30>[ 8.233025] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10464 00:46:15.663979 <30>[ 8.266077] systemd[1]: Detected architecture arm64.
10465 00:46:15.664454
10466 00:46:15.670295 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10467 00:46:15.670772
10468 00:46:15.686702 <30>[ 8.288708] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10469 00:46:15.809985 <30>[ 8.408655] systemd[1]: Queued start job for default target graphical.target.
10470 00:46:15.867568 <30>[ 8.466185] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10471 00:46:15.874002 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10472 00:46:15.894864 <30>[ 8.493344] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10473 00:46:15.904671 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10474 00:46:15.922488 <30>[ 8.521253] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10475 00:46:15.932333 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10476 00:46:15.951329 <30>[ 8.550191] systemd[1]: Created slice user.slice - User and Session Slice.
10477 00:46:15.957956 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10478 00:46:15.981778 <30>[ 8.577310] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10479 00:46:15.991607 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10480 00:46:16.009411 <30>[ 8.604846] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10481 00:46:16.016042 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10482 00:46:16.044005 <30>[ 8.633040] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10483 00:46:16.053917 <30>[ 8.652929] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10484 00:46:16.060824 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10485 00:46:16.078323 <30>[ 8.677046] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10486 00:46:16.088134 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10487 00:46:16.106175 <30>[ 8.705128] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10488 00:46:16.116330 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10489 00:46:16.131106 <30>[ 8.733181] systemd[1]: Reached target paths.target - Path Units.
10490 00:46:16.141233 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10491 00:46:16.158054 <30>[ 8.757074] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10492 00:46:16.164724 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10493 00:46:16.178762 <30>[ 8.780642] systemd[1]: Reached target slices.target - Slice Units.
10494 00:46:16.188539 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10495 00:46:16.203262 <30>[ 8.805154] systemd[1]: Reached target swap.target - Swaps.
10496 00:46:16.209750 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10497 00:46:16.230352 <30>[ 8.829165] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10498 00:46:16.240251 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10499 00:46:16.258974 <30>[ 8.857612] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10500 00:46:16.268499 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10501 00:46:16.287751 <30>[ 8.886711] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10502 00:46:16.297650 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10503 00:46:16.314701 <30>[ 8.913314] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10504 00:46:16.324367 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10505 00:46:16.342396 <30>[ 8.941296] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10506 00:46:16.349205 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10507 00:46:16.366438 <30>[ 8.965435] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10508 00:46:16.376619 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10509 00:46:16.395180 <30>[ 8.994039] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10510 00:46:16.404945 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10511 00:46:16.423066 <30>[ 9.021741] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10512 00:46:16.432974 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10513 00:46:16.486673 <30>[ 9.084892] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10514 00:46:16.492694 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10515 00:46:16.512087 <30>[ 9.110713] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10516 00:46:16.519201 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10517 00:46:16.540866 <30>[ 9.139254] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10518 00:46:16.546965 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10519 00:46:16.572803 <30>[ 9.164945] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10520 00:46:16.585072 <30>[ 9.183794] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10521 00:46:16.594675 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10522 00:46:16.654820 <30>[ 9.253289] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10523 00:46:16.660822 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10524 00:46:16.687557 <30>[ 9.286162] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10525 00:46:16.697133 Startin<6>[ 9.295486] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10526 00:46:16.703765 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10527 00:46:16.726830 <30>[ 9.325732] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10528 00:46:16.733344 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10529 00:46:16.798404 <30>[ 9.397373] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10530 00:46:16.808366 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10531 00:46:16.831064 <30>[ 9.429966] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10532 00:46:16.837731 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10533 00:46:16.898456 <30>[ 9.497194] systemd[1]: Starting systemd-journald.service - Journal Service...
10534 00:46:16.904799 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10535 00:46:16.925249 <30>[ 9.524078] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10536 00:46:16.931634 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10537 00:46:16.962513 <30>[ 9.558040] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10538 00:46:16.968741 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10539 00:46:16.994559 <30>[ 9.593612] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10540 00:46:17.004345 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10541 00:46:17.031072 <30>[ 9.629908] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10542 00:46:17.040921 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10543 00:46:17.068665 <30>[ 9.667603] systemd[1]: Started systemd-journald.service - Journal Service.
10544 00:46:17.075669 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10545 00:46:17.097724 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10546 00:46:17.114772 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10547 00:46:17.139133 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10548 00:46:17.159448 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10549 00:46:17.180159 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10550 00:46:17.200071 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10551 00:46:17.225144 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10552 00:46:17.249505 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10553 00:46:17.272813 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10554 00:46:17.291064 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10555 00:46:17.311476 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10556 00:46:17.332533 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10557 00:46:17.339130 See 'systemctl status systemd-remount-fs.service' for details.
10558 00:46:17.348683 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10559 00:46:17.368782 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10560 00:46:17.410207 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10561 00:46:17.429998 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10562 00:46:17.449846 Startin<46>[ 10.049500] systemd-journald[185]: Received client request to flush runtime journal.
10563 00:46:17.456466 g [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10564 00:46:17.479472 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10565 00:46:17.506923 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10566 00:46:17.529619 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10567 00:46:17.547464 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10568 00:46:17.566941 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10569 00:46:17.587179 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10570 00:46:17.607163 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10571 00:46:17.658420 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10572 00:46:17.692888 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10573 00:46:17.710081 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10574 00:46:17.726048 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10575 00:46:17.774348 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10576 00:46:17.798678 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10577 00:46:17.821292 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10578 00:46:17.863281 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10579 00:46:17.888933 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10580 00:46:17.909351 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10581 00:46:17.958283 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10582 00:46:17.984459 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10583 00:46:18.014301 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10584 00:46:18.104642 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10585 00:46:18.123448 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10586 00:46:18.142425 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10587 00:46:18.163638 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10588 00:46:18.183499 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10589 00:46:18.202968 [[0;32m OK [0m] Listening on [0;1;39mdbus.s<6>[ 10.801159] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10590 00:46:18.209496 <6>[ 10.804899] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10591 00:46:18.215914 <6>[ 10.813585] remoteproc remoteproc0: scp is available
10592 00:46:18.226076 ocket[…- D-Bu<6>[ 10.819484] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10593 00:46:18.232564 s System Message<6>[ 10.823535] remoteproc remoteproc0: powering up scp
10594 00:46:18.233050 Bus Socket.
10595 00:46:18.239034 <6>[ 10.823792] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10596 00:46:18.249047 <6>[ 10.823804] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10597 00:46:18.259374 <4>[ 10.824024] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10598 00:46:18.265866 <6>[ 10.827971] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10599 00:46:18.272089 <6>[ 10.827980] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10600 00:46:18.282367 <6>[ 10.828313] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10601 00:46:18.288602 <6>[ 10.828338] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10602 00:46:18.298789 <6>[ 10.828796] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10603 00:46:18.305234 <6>[ 10.828806] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10604 00:46:18.314974 <6>[ 10.833073] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10605 00:46:18.325278 <6>[ 10.838658] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10606 00:46:18.328491 <6>[ 10.838727] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10607 00:46:18.338376 <6>[ 10.847981] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10608 00:46:18.345129 <3>[ 10.879613] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10609 00:46:18.354692 <4>[ 10.890619] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10610 00:46:18.361334 <3>[ 10.896682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10611 00:46:18.367896 <4>[ 10.907698] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10612 00:46:18.377930 <3>[ 10.913602] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10613 00:46:18.384364 <6>[ 10.958750] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10614 00:46:18.391014 <3>[ 10.960840] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10615 00:46:18.398027 <6>[ 10.963327] mc: Linux media interface: v0.10
10616 00:46:18.404437 <4>[ 10.981576] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10617 00:46:18.410919 <4>[ 10.981576] Fallback method does not support PEC.
10618 00:46:18.417554 <6>[ 10.981639] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10619 00:46:18.427597 <6>[ 10.984196] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10620 00:46:18.434321 <3>[ 10.984520] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10621 00:46:18.440655 <3>[ 10.984535] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10622 00:46:18.450549 <3>[ 10.984544] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10623 00:46:18.457399 <3>[ 10.984548] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10624 00:46:18.467055 <3>[ 10.984649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10625 00:46:18.473888 <3>[ 10.987660] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10626 00:46:18.483743 <3>[ 10.987670] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10627 00:46:18.490589 <3>[ 10.987673] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10628 00:46:18.499970 <3>[ 10.991294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10629 00:46:18.506924 <3>[ 10.991313] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10630 00:46:18.513273 <3>[ 10.991318] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10631 00:46:18.523774 <3>[ 10.991322] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10632 00:46:18.529970 <3>[ 10.991326] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10633 00:46:18.539989 <3>[ 10.991537] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10634 00:46:18.546304 <6>[ 11.001708] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10635 00:46:18.553137 <6>[ 11.004350] remoteproc remoteproc0: remote processor scp is now up
10636 00:46:18.559641 <6>[ 11.018174] pci_bus 0000:00: root bus resource [bus 00-ff]
10637 00:46:18.566588 <6>[ 11.019245] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10638 00:46:18.576169 <6>[ 11.021246] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10639 00:46:18.582607 <6>[ 11.051224] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10640 00:46:18.592605 <6>[ 11.057854] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10641 00:46:18.602823 <6>[ 11.057868] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10642 00:46:18.609916 <6>[ 11.058256] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10643 00:46:18.617121 <6>[ 11.082463] videodev: Linux video capture interface: v2.00
10644 00:46:18.627019 <6>[ 11.090088] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10645 00:46:18.630382 <6>[ 11.106772] Bluetooth: Core ver 2.22
10646 00:46:18.637129 <6>[ 11.114376] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10647 00:46:18.641020 <6>[ 11.122503] NET: Registered PF_BLUETOOTH protocol family
10648 00:46:18.647614 <6>[ 11.130509] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10649 00:46:18.654371 <6>[ 11.138555] Bluetooth: HCI device and connection manager initialized
10650 00:46:18.661138 <6>[ 11.138574] Bluetooth: HCI socket layer initialized
10651 00:46:18.665037 <6>[ 11.146711] pci 0000:00:00.0: supports D1 D2
10652 00:46:18.672074 <6>[ 11.153500] Bluetooth: L2CAP socket layer initialized
10653 00:46:18.678709 <6>[ 11.156149] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10654 00:46:18.691856 <6>[ 11.157361] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10655 00:46:18.695571 <6>[ 11.157550] usbcore: registered new interface driver uvcvideo
10656 00:46:18.702418 <6>[ 11.159956] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10657 00:46:18.712108 <6>[ 11.161632] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10658 00:46:18.715750 <6>[ 11.165816] Bluetooth: SCO socket layer initialized
10659 00:46:18.722866 <6>[ 11.199783] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10660 00:46:18.729762 <6>[ 11.209141] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10661 00:46:18.740025 <3>[ 11.220076] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10662 00:46:18.746628 <3>[ 11.221640] power_supply sbs-5-000b: driver failed to report `health' property: -6
10663 00:46:18.753338 <6>[ 11.223756] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10664 00:46:18.759869 <6>[ 11.237965] usbcore: registered new interface driver btusb
10665 00:46:18.769640 <4>[ 11.238812] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10666 00:46:18.777061 <3>[ 11.238826] Bluetooth: hci0: Failed to load firmware file (-2)
10667 00:46:18.780191 <3>[ 11.238831] Bluetooth: hci0: Failed to set up firmware (-2)
10668 00:46:18.790523 <4>[ 11.238837] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10669 00:46:18.800264 <6>[ 11.243724] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10670 00:46:18.807655 <3>[ 11.249176] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10671 00:46:18.817541 <3>[ 11.250101] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
10672 00:46:18.824370 <6>[ 11.256753] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10673 00:46:18.828105 <6>[ 11.256865] pci 0000:01:00.0: supports D1 D2
10674 00:46:18.838237 <3>[ 11.265954] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10675 00:46:18.845360 <6>[ 11.268483] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10676 00:46:18.852177 <6>[ 11.280526] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10677 00:46:18.858767 <3>[ 11.284621] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10678 00:46:18.869105 <3>[ 11.303147] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10679 00:46:18.875890 <6>[ 11.303792] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10680 00:46:18.885832 <3>[ 11.328592] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10681 00:46:18.891972 <6>[ 11.330518] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10682 00:46:18.902267 <3>[ 11.354549] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10683 00:46:18.908773 <6>[ 11.360827] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10684 00:46:18.918680 <6>[ 11.360839] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10685 00:46:18.925207 <3>[ 11.385425] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10686 00:46:18.935124 <6>[ 11.388977] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10687 00:46:18.938721 <6>[ 11.542234] pci 0000:00:00.0: PCI bridge to [bus 01]
10688 00:46:18.948414 <6>[ 11.542240] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10689 00:46:18.954840 <6>[ 11.542396] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10690 00:46:18.961721 [[0;32m OK [<6>[ 11.562489] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10691 00:46:18.968174 0m] Reached targ<6>[ 11.570230] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10692 00:46:18.974508 et [0;1;39msockets.target[0m - Socket Units.
10693 00:46:18.988558 <5>[ 11.587560] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10694 00:46:19.013553 Starting [0;1;39msystemd-networkd.…ice[0m - Network<5>[ 11.614573] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10695 00:46:19.023615 Configuration..<5>[ 11.622245] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10696 00:46:19.024011 .
10697 00:46:19.033659 <4>[ 11.631781] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10698 00:46:19.036747 <6>[ 11.640948] cfg80211: failed to load regulatory.db
10699 00:46:19.046802 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10700 00:46:19.066296 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10701 00:46:19.086984 <6>[ 11.686252] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10702 00:46:19.093837 <6>[ 11.693800] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10703 00:46:19.103998 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10704 00:46:19.117795 <6>[ 11.720671] mt7921e 0000:01:00.0: ASIC revision: 79610010
10705 00:46:19.128526 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10706 00:46:19.158853 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10707 00:46:19.219781 [[0;32m OK [0m] Started [0;1;39msystemd-log<6>[ 11.819868] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10708 00:46:19.223248 <6>[ 11.819868]
10709 00:46:19.226305 ind.service[0m - User Login Management.
10710 00:46:19.253577 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10711 00:46:19.270167 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10712 00:46:19.286992 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10713 00:46:19.306489 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10714 00:46:19.367475 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10715 00:46:19.392434 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10716 00:46:19.415303 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10717 00:46:19.436423 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10718 00:46:19.493249 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Ge<6>[ 12.090834] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10719 00:46:19.493732 tty on tty1.
10720 00:46:19.513866 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10721 00:46:19.530187 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10722 00:46:19.550065 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10723 00:46:19.570457 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10724 00:46:19.627537 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10725 00:46:19.652466 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10726 00:46:19.671540 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10727 00:46:19.704886 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10728 00:46:19.750886
10729 00:46:19.753616 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10730 00:46:19.754043
10731 00:46:19.757775 debian-bookworm-arm64 login: root (automatic login)
10732 00:46:19.758337
10733 00:46:19.768790 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024 aarch64
10734 00:46:19.769222
10735 00:46:19.776064 The programs included with the Debian GNU/Linux system are free software;
10736 00:46:19.781676 the exact distribution terms for each program are described in the
10737 00:46:19.785103 individual files in /usr/share/doc/*/copyright.
10738 00:46:19.785534
10739 00:46:19.791770 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10740 00:46:19.794775 permitted by applicable law.
10741 00:46:19.796162 Matched prompt #10: / #
10743 00:46:19.797205 Setting prompt string to ['/ #']
10744 00:46:19.797687 end: 2.2.5.1 login-action (duration 00:00:13) [common]
10746 00:46:19.798724 end: 2.2.5 auto-login-action (duration 00:00:13) [common]
10747 00:46:19.799184 start: 2.2.6 expect-shell-connection (timeout 00:03:29) [common]
10748 00:46:19.799569 Setting prompt string to ['/ #']
10749 00:46:19.799890 Forcing a shell prompt, looking for ['/ #']
10751 00:46:19.850628 / #
10752 00:46:19.851301 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10753 00:46:19.851690 Waiting using forced prompt support (timeout 00:02:30)
10754 00:46:19.856346
10755 00:46:19.857126 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10756 00:46:19.857635 start: 2.2.7 export-device-env (timeout 00:03:29) [common]
10757 00:46:19.858093 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10758 00:46:19.858582 end: 2.2 depthcharge-retry (duration 00:01:31) [common]
10759 00:46:19.859054 end: 2 depthcharge-action (duration 00:01:31) [common]
10760 00:46:19.859561 start: 3 lava-test-retry (timeout 00:08:08) [common]
10761 00:46:19.860011 start: 3.1 lava-test-shell (timeout 00:08:08) [common]
10762 00:46:19.860377 Using namespace: common
10764 00:46:19.961643 / # #
10765 00:46:19.962294 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10766 00:46:19.967608 #
10767 00:46:19.968377 Using /lava-14368417
10769 00:46:20.069479 / # export SHELL=/bin/sh
10770 00:46:20.076101 export SHELL=/bin/sh
10772 00:46:20.177766 / # . /lava-14368417/environment
10773 00:46:20.184486 . /lava-14368417/environment
10775 00:46:20.286165 / # /lava-14368417/bin/lava-test-runner /lava-14368417/0
10776 00:46:20.286839 Test shell timeout: 10s (minimum of the action and connection timeout)
10777 00:46:20.292633 /lava-14368417/bin/lava-test-runner /lava-14368417/0
10778 00:46:20.313960 + export TESTRUN_ID=0_v4l2-compliance-uvc
10779 00:46:20.316936 + cd /lava-14368417/0/tests/0_v4l2-compliance-uvc
10780 00:46:20.317371 + cat uuid
10781 00:46:20.320148 + UUID=14368417_1.5.2.3.1
10782 00:46:20.320629 + set +x
10783 00:46:20.326928 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14368417_1.5.2.3.1>
10784 00:46:20.327734 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14368417_1.5.2.3.1
10785 00:46:20.328116 Starting test lava.0_v4l2-compliance-uvc (14368417_1.5.2.3.1)
10786 00:46:20.328518 Skipping test definition patterns.
10787 00:46:20.329944 + /usr/bin/v4l2-parser.sh -d uvcvideo
10788 00:46:20.336778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10789 00:46:20.337297 device: /dev/video0
10790 00:46:20.337948 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10792 00:46:20.350180 <6>[ 12.952744] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10793 00:46:26.831573 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
10794 00:46:26.843043 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
10795 00:46:26.851177
10796 00:46:26.869260 Compliance test for uvcvideo device /dev/video0:
10797 00:46:26.876714
10798 00:46:26.890521 Driver Info:
10799 00:46:26.903901 Driver name : uvcvideo
10800 00:46:26.918673 Card type : HD User Facing: HD User Facing
10801 00:46:26.929521 Bus info : usb-11200000.usb-1.4.1
10802 00:46:26.938792 Driver version : 6.1.92
10803 00:46:26.948676 Capabilities : 0x84a00001
10804 00:46:26.961847 Metadata Capture
10805 00:46:26.973459 Streaming
10806 00:46:26.987186 Extended Pix Format
10807 00:46:26.998543 Device Capabilities
10808 00:46:27.009337 Device Caps : 0x04200001
10809 00:46:27.026222 Streaming
10810 00:46:27.035453 Extended Pix Format
10811 00:46:27.048715 Media Driver Info:
10812 00:46:27.058991 Driver name : uvcvideo
10813 00:46:27.077698 Model : HD User Facing: HD User Facing
10814 00:46:27.084430 Serial : 200901010001
10815 00:46:27.097929 Bus info : usb-11200000.usb-1.4.1
10816 00:46:27.109631 Media version : 6.1.92
10817 00:46:27.125780 Hardware revision: 0x00009758 (38744)
10818 00:46:27.136734 Driver version : 6.1.92
10819 00:46:27.147086 Interface Info:
10820 00:46:27.161916 <LAVA_SIGNAL_TESTSET START Interface-Info>
10821 00:46:27.161992 ID : 0x03000002
10822 00:46:27.162229 Received signal: <TESTSET> START Interface-Info
10823 00:46:27.162329 Starting test_set Interface-Info
10824 00:46:27.172120 Type : V4L Video
10825 00:46:27.184255 Entity Info:
10826 00:46:27.193343 <LAVA_SIGNAL_TESTSET STOP>
10827 00:46:27.193584 Received signal: <TESTSET> STOP
10828 00:46:27.193647 Closing test_set Interface-Info
10829 00:46:27.203161 <LAVA_SIGNAL_TESTSET START Entity-Info>
10830 00:46:27.203403 Received signal: <TESTSET> START Entity-Info
10831 00:46:27.203466 Starting test_set Entity-Info
10832 00:46:27.206008 ID : 0x00000001 (1)
10833 00:46:27.218342 Name : HD User Facing: HD User Facing
10834 00:46:27.226618 Function : V4L2 I/O
10835 00:46:27.236143 Flags : default
10836 00:46:27.246955 Pad 0x01000007 : 0: Sink
10837 00:46:27.267886 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
10838 00:46:27.267963
10839 00:46:27.282794 Required ioctls:
10840 00:46:27.290431 <LAVA_SIGNAL_TESTSET STOP>
10841 00:46:27.290674 Received signal: <TESTSET> STOP
10842 00:46:27.290735 Closing test_set Entity-Info
10843 00:46:27.300619 <LAVA_SIGNAL_TESTSET START Required-ioctls>
10844 00:46:27.300862 Received signal: <TESTSET> START Required-ioctls
10845 00:46:27.300926 Starting test_set Required-ioctls
10846 00:46:27.303734 test MC information (see 'Media Driver Info' above): OK
10847 00:46:27.328158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
10848 00:46:27.328403 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
10850 00:46:27.331239 test VIDIOC_QUERYCAP: OK
10851 00:46:27.347883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10852 00:46:27.348157 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10854 00:46:27.351303 test invalid ioctls: OK
10855 00:46:27.370984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
10856 00:46:27.371060
10857 00:46:27.371284 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
10859 00:46:27.383083 Allow for multiple opens:
10860 00:46:27.390481 <LAVA_SIGNAL_TESTSET STOP>
10861 00:46:27.390715 Received signal: <TESTSET> STOP
10862 00:46:27.390776 Closing test_set Required-ioctls
10863 00:46:27.400137 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
10864 00:46:27.400378 Received signal: <TESTSET> START Allow-for-multiple-opens
10865 00:46:27.400448 Starting test_set Allow-for-multiple-opens
10866 00:46:27.403943 test second /dev/video0 open: OK
10867 00:46:27.422982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
10868 00:46:27.423223 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
10870 00:46:27.426108 test VIDIOC_QUERYCAP: OK
10871 00:46:27.450520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10872 00:46:27.450762 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10874 00:46:27.453889 test VIDIOC_G/S_PRIORITY: OK
10875 00:46:27.473988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
10876 00:46:27.474304 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
10878 00:46:27.477055 test for unlimited opens: OK
10879 00:46:27.498459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
10880 00:46:27.498534
10881 00:46:27.498763 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
10883 00:46:27.509522 Debug ioctls:
10884 00:46:27.515902 <LAVA_SIGNAL_TESTSET STOP>
10885 00:46:27.516168 Received signal: <TESTSET> STOP
10886 00:46:27.516267 Closing test_set Allow-for-multiple-opens
10887 00:46:27.524830 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
10888 00:46:27.525066 Received signal: <TESTSET> START Debug-ioctls
10889 00:46:27.525134 Starting test_set Debug-ioctls
10890 00:46:27.527941 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
10891 00:46:27.550489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
10892 00:46:27.550737 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
10894 00:46:27.557008 test VIDIOC_LOG_STATUS: OK (Not Supported)
10895 00:46:27.574417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
10896 00:46:27.574513
10897 00:46:27.574765 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
10899 00:46:27.584103 Input ioctls:
10900 00:46:27.591844 <LAVA_SIGNAL_TESTSET STOP>
10901 00:46:27.592076 Received signal: <TESTSET> STOP
10902 00:46:27.592135 Closing test_set Debug-ioctls
10903 00:46:27.601856 <LAVA_SIGNAL_TESTSET START Input-ioctls>
10904 00:46:27.602092 Received signal: <TESTSET> START Input-ioctls
10905 00:46:27.602149 Starting test_set Input-ioctls
10906 00:46:27.605119 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
10907 00:46:27.628422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
10908 00:46:27.628684 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
10910 00:46:27.631885 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
10911 00:46:27.654285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
10912 00:46:27.654526 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
10914 00:46:27.660507 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
10915 00:46:27.682126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
10916 00:46:27.682397 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
10918 00:46:27.688752 test VIDIOC_ENUMAUDIO: OK (Not Supported)
10919 00:46:27.706762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
10920 00:46:27.706998 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
10922 00:46:27.709841 test VIDIOC_G/S/ENUMINPUT: OK
10923 00:46:27.731179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
10924 00:46:27.731416 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
10926 00:46:27.734386 test VIDIOC_G/S_AUDIO: OK (Not Supported)
10927 00:46:27.756598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
10928 00:46:27.756838 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
10930 00:46:27.760061 Inputs: 1 Audio Inputs: 0 Tuners: 0
10931 00:46:27.767003
10932 00:46:27.782461 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
10933 00:46:27.802640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
10934 00:46:27.802878 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
10936 00:46:27.809153 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
10937 00:46:27.830852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
10938 00:46:27.831091 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
10940 00:46:27.834420 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
10941 00:46:27.855244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
10942 00:46:27.855507 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
10944 00:46:27.861861 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
10945 00:46:27.882888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
10946 00:46:27.883126 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
10948 00:46:27.889161 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
10949 00:46:27.906875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
10950 00:46:27.907118 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
10952 00:46:27.911889
10953 00:46:27.930735 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
10954 00:46:27.950896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
10955 00:46:27.951135 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
10957 00:46:27.957161 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
10958 00:46:27.983427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
10959 00:46:27.983663 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
10961 00:46:27.986699 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
10962 00:46:28.004941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
10963 00:46:28.005185 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
10965 00:46:28.008373 test VIDIOC_G/S_EDID: OK (Not Supported)
10966 00:46:28.029080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
10967 00:46:28.029153
10968 00:46:28.029374 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
10970 00:46:28.042835 Control ioctls (Input 0):
10971 00:46:28.050133 <LAVA_SIGNAL_TESTSET STOP>
10972 00:46:28.050403 Received signal: <TESTSET> STOP
10973 00:46:28.050488 Closing test_set Input-ioctls
10974 00:46:28.059042 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
10975 00:46:28.059282 Received signal: <TESTSET> START Control-ioctls-Input-0
10976 00:46:28.059342 Starting test_set Control-ioctls-Input-0
10977 00:46:28.062530 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
10978 00:46:28.091228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
10979 00:46:28.091298 test VIDIOC_QUERYCTRL: OK
10980 00:46:28.091525 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
10982 00:46:28.112079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
10983 00:46:28.112321 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
10985 00:46:28.114894 test VIDIOC_G/S_CTRL: OK
10986 00:46:28.138255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
10987 00:46:28.138496 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
10989 00:46:28.141621 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
10990 00:46:28.162891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
10991 00:46:28.163133 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
10993 00:46:28.168955 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
10994 00:46:28.189465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
10995 00:46:28.189705 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
10997 00:46:28.193074 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
10998 00:46:28.213873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
10999 00:46:28.214109 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11001 00:46:28.217484 Standard Controls: 16 Private Controls: 0
11002 00:46:28.226241
11003 00:46:28.239226 Format ioctls (Input 0):
11004 00:46:28.248626 <LAVA_SIGNAL_TESTSET STOP>
11005 00:46:28.248864 Received signal: <TESTSET> STOP
11006 00:46:28.248926 Closing test_set Control-ioctls-Input-0
11007 00:46:28.257741 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11008 00:46:28.257979 Received signal: <TESTSET> START Format-ioctls-Input-0
11009 00:46:28.258042 Starting test_set Format-ioctls-Input-0
11010 00:46:28.261194 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11011 00:46:28.289367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11012 00:46:28.289616 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11014 00:46:28.292537 test VIDIOC_G/S_PARM: OK
11015 00:46:28.309119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11016 00:46:28.309360 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11018 00:46:28.312219 test VIDIOC_G_FBUF: OK (Not Supported)
11019 00:46:28.333710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11020 00:46:28.333950 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11022 00:46:28.337292 test VIDIOC_G_FMT: OK
11023 00:46:28.355251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11024 00:46:28.355493 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11026 00:46:28.358366 test VIDIOC_TRY_FMT: OK
11027 00:46:28.380946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11028 00:46:28.381188 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11030 00:46:28.387405 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11031 00:46:28.390862 test VIDIOC_S_FMT: OK
11032 00:46:28.415529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11033 00:46:28.415770 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11035 00:46:28.418642 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11036 00:46:28.439125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11037 00:46:28.439367 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11039 00:46:28.442402 test Cropping: OK (Not Supported)
11040 00:46:28.466190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11041 00:46:28.466501 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11043 00:46:28.469076 test Composing: OK (Not Supported)
11044 00:46:28.487667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11045 00:46:28.487908 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11047 00:46:28.491214 test Scaling: OK (Not Supported)
11048 00:46:28.512828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11049 00:46:28.512903
11050 00:46:28.513126 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11052 00:46:28.526268 Codec ioctls (Input 0):
11053 00:46:28.533801 <LAVA_SIGNAL_TESTSET STOP>
11054 00:46:28.534041 Received signal: <TESTSET> STOP
11055 00:46:28.534102 Closing test_set Format-ioctls-Input-0
11056 00:46:28.543570 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11057 00:46:28.543811 Received signal: <TESTSET> START Codec-ioctls-Input-0
11058 00:46:28.543872 Starting test_set Codec-ioctls-Input-0
11059 00:46:28.546742 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11060 00:46:28.571544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11061 00:46:28.571789 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11063 00:46:28.578069 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11064 00:46:28.595753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11065 00:46:28.595995 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11067 00:46:28.602309 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11068 00:46:28.620671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11069 00:46:28.620747
11070 00:46:28.620971 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11072 00:46:28.631162 Buffer ioctls (Input 0):
11073 00:46:28.637968 <LAVA_SIGNAL_TESTSET STOP>
11074 00:46:28.638284 Received signal: <TESTSET> STOP
11075 00:46:28.638413 Closing test_set Codec-ioctls-Input-0
11076 00:46:28.650142 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11077 00:46:28.650408 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11078 00:46:28.650471 Starting test_set Buffer-ioctls-Input-0
11079 00:46:28.653160 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11080 00:46:28.677964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11081 00:46:28.678206 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11083 00:46:28.680871 test CREATE_BUFS maximum buffers: OK
11084 00:46:28.702839 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11086 00:46:28.705685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11087 00:46:28.705765 test VIDIOC_EXPBUF: OK
11088 00:46:28.725197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11089 00:46:28.725439 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11091 00:46:28.728589 test Requests: OK (Not Supported)
11092 00:46:28.750130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11093 00:46:28.750207
11094 00:46:28.750469 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11096 00:46:28.762272 Test input 0:
11097 00:46:28.770849
11098 00:46:28.782034 Streaming ioctls:
11099 00:46:28.789129 <LAVA_SIGNAL_TESTSET STOP>
11100 00:46:28.789369 Received signal: <TESTSET> STOP
11101 00:46:28.789430 Closing test_set Buffer-ioctls-Input-0
11102 00:46:28.797425 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11103 00:46:28.797667 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11104 00:46:28.797728 Starting test_set Streaming-ioctls_Test-input-0
11105 00:46:28.801026 test read/write: OK (Not Supported)
11106 00:46:28.825830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11107 00:46:28.826072 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11109 00:46:28.829525 test blocking wait: OK
11110 00:46:28.848773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11111 00:46:28.849015 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11113 00:46:28.855568 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11114 00:46:28.858717 test MMAP (no poll): FAIL
11115 00:46:28.881208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11116 00:46:28.881449 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11118 00:46:28.887682 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11119 00:46:28.894960 test MMAP (select): FAIL
11120 00:46:28.919826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11121 00:46:28.920068 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11123 00:46:28.926051 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11124 00:46:28.928985 test MMAP (epoll): FAIL
11125 00:46:28.952031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11126 00:46:28.952109
11127 00:46:28.952333 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11129 00:46:28.965359
11130 00:46:29.128248
11131 00:46:29.136561 test USERPTR (no poll): OK
11132 00:46:29.158985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11133 00:46:29.159063
11134 00:46:29.159288 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11136 00:46:29.173783
11137 00:46:29.353518
11138 00:46:29.366024 test USERPTR (select): OK
11139 00:46:29.390281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11140 00:46:29.390525 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11142 00:46:29.397022 test DMABUF: Cannot test, specify --expbuf-device
11143 00:46:29.401361
11144 00:46:29.423879 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11145 00:46:29.426661 <LAVA_TEST_RUNNER EXIT>
11146 00:46:29.426901 ok: lava_test_shell seems to have completed
11147 00:46:29.426968 Marking unfinished test run as failed
11149 00:46:29.427815 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11150 00:46:29.427942 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11151 00:46:29.428021 end: 3 lava-test-retry (duration 00:00:10) [common]
11152 00:46:29.428102 start: 4 finalize (timeout 00:07:58) [common]
11153 00:46:29.428186 start: 4.1 power-off (timeout 00:00:30) [common]
11154 00:46:29.428323 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
11155 00:46:29.643656 >> Command sent successfully.
11156 00:46:29.658436 Returned 0 in 0 seconds
11157 00:46:29.759845 end: 4.1 power-off (duration 00:00:00) [common]
11159 00:46:29.761147 start: 4.2 read-feedback (timeout 00:07:58) [common]
11160 00:46:29.762188 Listened to connection for namespace 'common' for up to 1s
11161 00:46:30.762431 Finalising connection for namespace 'common'
11162 00:46:30.763048 Disconnecting from shell: Finalise
11163 00:46:30.763457 / #
11164 00:46:30.864435 end: 4.2 read-feedback (duration 00:00:01) [common]
11165 00:46:30.865092 end: 4 finalize (duration 00:00:01) [common]
11166 00:46:30.865770 Cleaning after the job
11167 00:46:30.866376 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/ramdisk
11168 00:46:30.889730 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/kernel
11169 00:46:30.920140 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/dtb
11170 00:46:30.920410 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368417/tftp-deploy-fnw4d_c7/modules
11171 00:46:30.927953 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368417
11172 00:46:30.989636 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368417
11173 00:46:30.989796 Job finished correctly