Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 22
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 09:23:46.545269 lava-dispatcher, installed at version: 2024.03
2 09:23:46.545520 start: 0 validate
3 09:23:46.545703 Start time: 2024-06-18 09:23:46.545680+00:00 (UTC)
4 09:23:46.545833 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:23:46.545979 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 09:23:46.806356 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:23:46.806555 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:23:47.071301 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:23:47.071508 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:24:33.639691 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:24:33.640589 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:24:34.153670 validate duration: 47.61
14 09:24:34.155142 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:24:34.155813 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:24:34.156392 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:24:34.157103 Not decompressing ramdisk as can be used compressed.
18 09:24:34.157774 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 09:24:34.158332 saving as /var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/ramdisk/rootfs.cpio.gz
20 09:24:34.158778 total size: 8181887 (7 MB)
21 09:24:46.316962 progress 0 % (0 MB)
22 09:24:46.319866 progress 5 % (0 MB)
23 09:24:46.322642 progress 10 % (0 MB)
24 09:24:46.325684 progress 15 % (1 MB)
25 09:24:46.328763 progress 20 % (1 MB)
26 09:24:46.332052 progress 25 % (1 MB)
27 09:24:46.335079 progress 30 % (2 MB)
28 09:24:46.338427 progress 35 % (2 MB)
29 09:24:46.341428 progress 40 % (3 MB)
30 09:24:46.344681 progress 45 % (3 MB)
31 09:24:46.347718 progress 50 % (3 MB)
32 09:24:46.350848 progress 55 % (4 MB)
33 09:24:46.353468 progress 60 % (4 MB)
34 09:24:46.356199 progress 65 % (5 MB)
35 09:24:46.358548 progress 70 % (5 MB)
36 09:24:46.360985 progress 75 % (5 MB)
37 09:24:46.363133 progress 80 % (6 MB)
38 09:24:46.365414 progress 85 % (6 MB)
39 09:24:46.367457 progress 90 % (7 MB)
40 09:24:46.369600 progress 95 % (7 MB)
41 09:24:46.371640 progress 100 % (7 MB)
42 09:24:46.371833 7 MB downloaded in 12.21 s (0.64 MB/s)
43 09:24:46.371983 end: 1.1.1 http-download (duration 00:00:12) [common]
45 09:24:46.372218 end: 1.1 download-retry (duration 00:00:12) [common]
46 09:24:46.372303 start: 1.2 download-retry (timeout 00:09:48) [common]
47 09:24:46.372386 start: 1.2.1 http-download (timeout 00:09:48) [common]
48 09:24:46.372521 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:24:46.372589 saving as /var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/kernel/Image
50 09:24:46.372648 total size: 54813184 (52 MB)
51 09:24:46.372707 No compression specified
52 09:24:46.637153 progress 0 % (0 MB)
53 09:24:46.651677 progress 5 % (2 MB)
54 09:24:46.665757 progress 10 % (5 MB)
55 09:24:46.679530 progress 15 % (7 MB)
56 09:24:46.693920 progress 20 % (10 MB)
57 09:24:46.708178 progress 25 % (13 MB)
58 09:24:46.721987 progress 30 % (15 MB)
59 09:24:46.736378 progress 35 % (18 MB)
60 09:24:46.750621 progress 40 % (20 MB)
61 09:24:46.764337 progress 45 % (23 MB)
62 09:24:46.778885 progress 50 % (26 MB)
63 09:24:46.793488 progress 55 % (28 MB)
64 09:24:46.808070 progress 60 % (31 MB)
65 09:24:46.822269 progress 65 % (34 MB)
66 09:24:46.836143 progress 70 % (36 MB)
67 09:24:46.850245 progress 75 % (39 MB)
68 09:24:46.864191 progress 80 % (41 MB)
69 09:24:46.878735 progress 85 % (44 MB)
70 09:24:46.893882 progress 90 % (47 MB)
71 09:24:46.907972 progress 95 % (49 MB)
72 09:24:46.922491 progress 100 % (52 MB)
73 09:24:46.922749 52 MB downloaded in 0.55 s (95.03 MB/s)
74 09:24:46.922911 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:24:46.923140 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:24:46.923227 start: 1.3 download-retry (timeout 00:09:47) [common]
78 09:24:46.923310 start: 1.3.1 http-download (timeout 00:09:47) [common]
79 09:24:46.923442 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:24:46.923510 saving as /var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/dtb/mt8192-asurada-spherion-r0.dtb
81 09:24:46.923569 total size: 47258 (0 MB)
82 09:24:46.923628 No compression specified
83 09:24:47.176444 progress 69 % (0 MB)
84 09:24:47.176797 progress 100 % (0 MB)
85 09:24:47.176984 0 MB downloaded in 0.25 s (0.18 MB/s)
86 09:24:47.177167 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:24:47.177520 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:24:47.177635 start: 1.4 download-retry (timeout 00:09:47) [common]
90 09:24:47.177747 start: 1.4.1 http-download (timeout 00:09:47) [common]
91 09:24:47.177923 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:24:47.178021 saving as /var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/modules/modules.tar
93 09:24:47.178110 total size: 8619356 (8 MB)
94 09:24:47.178233 Using unxz to decompress xz
95 09:24:47.182246 progress 0 % (0 MB)
96 09:24:47.201827 progress 5 % (0 MB)
97 09:24:47.226346 progress 10 % (0 MB)
98 09:24:47.251485 progress 15 % (1 MB)
99 09:24:47.276059 progress 20 % (1 MB)
100 09:24:47.301334 progress 25 % (2 MB)
101 09:24:47.327064 progress 30 % (2 MB)
102 09:24:47.353060 progress 35 % (2 MB)
103 09:24:47.377806 progress 40 % (3 MB)
104 09:24:47.402596 progress 45 % (3 MB)
105 09:24:47.426785 progress 50 % (4 MB)
106 09:24:47.451730 progress 55 % (4 MB)
107 09:24:47.476238 progress 60 % (4 MB)
108 09:24:47.500361 progress 65 % (5 MB)
109 09:24:47.528633 progress 70 % (5 MB)
110 09:24:47.554182 progress 75 % (6 MB)
111 09:24:47.577864 progress 80 % (6 MB)
112 09:24:47.601500 progress 85 % (7 MB)
113 09:24:47.625493 progress 90 % (7 MB)
114 09:24:47.653766 progress 95 % (7 MB)
115 09:24:47.684223 progress 100 % (8 MB)
116 09:24:47.688872 8 MB downloaded in 0.51 s (16.09 MB/s)
117 09:24:47.689107 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:24:47.689368 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:24:47.689463 start: 1.5 prepare-tftp-overlay (timeout 00:09:46) [common]
121 09:24:47.689556 start: 1.5.1 extract-nfsrootfs (timeout 00:09:46) [common]
122 09:24:47.689638 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:24:47.689722 start: 1.5.2 lava-overlay (timeout 00:09:46) [common]
124 09:24:47.689954 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7
125 09:24:47.690086 makedir: /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin
126 09:24:47.690237 makedir: /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/tests
127 09:24:47.690335 makedir: /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/results
128 09:24:47.690449 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-add-keys
129 09:24:47.690595 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-add-sources
130 09:24:47.690727 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-background-process-start
131 09:24:47.690856 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-background-process-stop
132 09:24:47.690982 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-common-functions
133 09:24:47.691105 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-echo-ipv4
134 09:24:47.691228 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-install-packages
135 09:24:47.691377 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-installed-packages
136 09:24:47.691501 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-os-build
137 09:24:47.691628 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-probe-channel
138 09:24:47.691752 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-probe-ip
139 09:24:47.691874 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-target-ip
140 09:24:47.691995 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-target-mac
141 09:24:47.692117 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-target-storage
142 09:24:47.692244 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-test-case
143 09:24:47.692368 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-test-event
144 09:24:47.692489 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-test-feedback
145 09:24:47.692612 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-test-raise
146 09:24:47.692733 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-test-reference
147 09:24:47.692856 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-test-runner
148 09:24:47.692978 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-test-set
149 09:24:47.693102 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-test-shell
150 09:24:47.693228 Updating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-install-packages (oe)
151 09:24:47.693377 Updating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/bin/lava-installed-packages (oe)
152 09:24:47.693496 Creating /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/environment
153 09:24:47.693603 LAVA metadata
154 09:24:47.693675 - LAVA_JOB_ID=14407593
155 09:24:47.693738 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:24:47.693840 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:46) [common]
157 09:24:47.693907 skipped lava-vland-overlay
158 09:24:47.693981 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:24:47.694061 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
160 09:24:47.694124 skipped lava-multinode-overlay
161 09:24:47.694229 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:24:47.694335 start: 1.5.2.3 test-definition (timeout 00:09:46) [common]
163 09:24:47.694409 Loading test definitions
164 09:24:47.694538 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:46) [common]
165 09:24:47.694615 Using /lava-14407593 at stage 0
166 09:24:47.694928 uuid=14407593_1.5.2.3.1 testdef=None
167 09:24:47.695018 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:24:47.695103 start: 1.5.2.3.2 test-overlay (timeout 00:09:46) [common]
169 09:24:47.695631 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:24:47.695851 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:46) [common]
172 09:24:47.696484 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:24:47.696712 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
175 09:24:47.697327 runner path: /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/0/tests/0_dmesg test_uuid 14407593_1.5.2.3.1
176 09:24:47.697482 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:24:47.697687 Creating lava-test-runner.conf files
179 09:24:47.697750 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407593/lava-overlay-qve15vr7/lava-14407593/0 for stage 0
180 09:24:47.697838 - 0_dmesg
181 09:24:47.697934 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 09:24:47.698022 start: 1.5.2.4 compress-overlay (timeout 00:09:46) [common]
183 09:24:47.705946 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 09:24:47.706083 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:46) [common]
185 09:24:47.706208 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 09:24:47.706312 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 09:24:47.706398 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:46) [common]
188 09:24:47.944481 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 09:24:47.944867 start: 1.5.4 extract-modules (timeout 00:09:46) [common]
190 09:24:47.944974 extracting modules file /var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407593/extract-overlay-ramdisk-9ny78ana/ramdisk
191 09:24:48.175806 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 09:24:48.175999 start: 1.5.5 apply-overlay-tftp (timeout 00:09:46) [common]
193 09:24:48.176124 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407593/compress-overlay-47r3j1bj/overlay-1.5.2.4.tar.gz to ramdisk
194 09:24:48.176221 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407593/compress-overlay-47r3j1bj/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407593/extract-overlay-ramdisk-9ny78ana/ramdisk
195 09:24:48.183737 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 09:24:48.183872 start: 1.5.6 configure-preseed-file (timeout 00:09:46) [common]
197 09:24:48.183968 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 09:24:48.184061 start: 1.5.7 compress-ramdisk (timeout 00:09:46) [common]
199 09:24:48.184145 Building ramdisk /var/lib/lava/dispatcher/tmp/14407593/extract-overlay-ramdisk-9ny78ana/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407593/extract-overlay-ramdisk-9ny78ana/ramdisk
200 09:24:48.693105 >> 145247 blocks
201 09:24:51.117067 rename /var/lib/lava/dispatcher/tmp/14407593/extract-overlay-ramdisk-9ny78ana/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/ramdisk/ramdisk.cpio.gz
202 09:24:51.117513 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 09:24:51.117642 start: 1.5.8 prepare-kernel (timeout 00:09:43) [common]
204 09:24:51.117744 start: 1.5.8.1 prepare-fit (timeout 00:09:43) [common]
205 09:24:51.117855 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/kernel/Image']
206 09:25:05.113228 Returned 0 in 13 seconds
207 09:25:05.213819 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/kernel/image.itb
208 09:25:05.596483 output: FIT description: Kernel Image image with one or more FDT blobs
209 09:25:05.596855 output: Created: Tue Jun 18 10:25:05 2024
210 09:25:05.596928 output: Image 0 (kernel-1)
211 09:25:05.596991 output: Description:
212 09:25:05.597050 output: Created: Tue Jun 18 10:25:05 2024
213 09:25:05.597111 output: Type: Kernel Image
214 09:25:05.597172 output: Compression: lzma compressed
215 09:25:05.597233 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
216 09:25:05.597295 output: Architecture: AArch64
217 09:25:05.597356 output: OS: Linux
218 09:25:05.597414 output: Load Address: 0x00000000
219 09:25:05.597473 output: Entry Point: 0x00000000
220 09:25:05.597528 output: Hash algo: crc32
221 09:25:05.597584 output: Hash value: 4137a6e7
222 09:25:05.597642 output: Image 1 (fdt-1)
223 09:25:05.597698 output: Description: mt8192-asurada-spherion-r0
224 09:25:05.597753 output: Created: Tue Jun 18 10:25:05 2024
225 09:25:05.597806 output: Type: Flat Device Tree
226 09:25:05.597859 output: Compression: uncompressed
227 09:25:05.597912 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 09:25:05.597965 output: Architecture: AArch64
229 09:25:05.598017 output: Hash algo: crc32
230 09:25:05.598069 output: Hash value: 0f8e4d2e
231 09:25:05.598122 output: Image 2 (ramdisk-1)
232 09:25:05.598200 output: Description: unavailable
233 09:25:05.598267 output: Created: Tue Jun 18 10:25:05 2024
234 09:25:05.598320 output: Type: RAMDisk Image
235 09:25:05.598373 output: Compression: Unknown Compression
236 09:25:05.598425 output: Data Size: 21382913 Bytes = 20881.75 KiB = 20.39 MiB
237 09:25:05.598478 output: Architecture: AArch64
238 09:25:05.598531 output: OS: Linux
239 09:25:05.598583 output: Load Address: unavailable
240 09:25:05.598696 output: Entry Point: unavailable
241 09:25:05.598753 output: Hash algo: crc32
242 09:25:05.598805 output: Hash value: b1744025
243 09:25:05.598858 output: Default Configuration: 'conf-1'
244 09:25:05.598911 output: Configuration 0 (conf-1)
245 09:25:05.598963 output: Description: mt8192-asurada-spherion-r0
246 09:25:05.599015 output: Kernel: kernel-1
247 09:25:05.599068 output: Init Ramdisk: ramdisk-1
248 09:25:05.599121 output: FDT: fdt-1
249 09:25:05.599173 output: Loadables: kernel-1
250 09:25:05.599225 output:
251 09:25:05.599422 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 09:25:05.599521 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 09:25:05.599627 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 09:25:05.599725 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:29) [common]
255 09:25:05.599805 No LXC device requested
256 09:25:05.599884 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 09:25:05.599971 start: 1.7 deploy-device-env (timeout 00:09:29) [common]
258 09:25:05.600047 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 09:25:05.600115 Checking files for TFTP limit of 4294967296 bytes.
260 09:25:05.600614 end: 1 tftp-deploy (duration 00:00:31) [common]
261 09:25:05.600723 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 09:25:05.600815 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 09:25:05.600940 substitutions:
264 09:25:05.601010 - {DTB}: 14407593/tftp-deploy-qhfq9a8z/dtb/mt8192-asurada-spherion-r0.dtb
265 09:25:05.601076 - {INITRD}: 14407593/tftp-deploy-qhfq9a8z/ramdisk/ramdisk.cpio.gz
266 09:25:05.601136 - {KERNEL}: 14407593/tftp-deploy-qhfq9a8z/kernel/Image
267 09:25:05.601193 - {LAVA_MAC}: None
268 09:25:05.601260 - {PRESEED_CONFIG}: None
269 09:25:05.601316 - {PRESEED_LOCAL}: None
270 09:25:05.601370 - {RAMDISK}: 14407593/tftp-deploy-qhfq9a8z/ramdisk/ramdisk.cpio.gz
271 09:25:05.601425 - {ROOT_PART}: None
272 09:25:05.601479 - {ROOT}: None
273 09:25:05.601533 - {SERVER_IP}: 192.168.201.1
274 09:25:05.601587 - {TEE}: None
275 09:25:05.601640 Parsed boot commands:
276 09:25:05.601695 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 09:25:05.601871 Parsed boot commands: tftpboot 192.168.201.1 14407593/tftp-deploy-qhfq9a8z/kernel/image.itb 14407593/tftp-deploy-qhfq9a8z/kernel/cmdline
278 09:25:05.601961 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 09:25:05.602045 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 09:25:05.602136 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 09:25:05.602266 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 09:25:05.602337 Not connected, no need to disconnect.
283 09:25:05.602410 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 09:25:05.602487 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 09:25:05.602553 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 09:25:05.606420 Setting prompt string to ['lava-test: # ']
287 09:25:05.606878 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 09:25:05.606982 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 09:25:05.607084 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 09:25:05.607222 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 09:25:05.607470 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
292 09:25:19.645300 Returned 0 in 14 seconds
293 09:25:19.746318 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 09:25:19.746778 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 09:25:19.746920 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 09:25:19.747052 Setting prompt string to 'Starting depthcharge on Spherion...'
298 09:25:19.747157 Changing prompt to 'Starting depthcharge on Spherion...'
299 09:25:19.747262 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 09:25:19.747836 [Enter `^Ec?' for help]
301 09:25:19.747955
302 09:25:19.748054
303 09:25:19.748147 F0: 102B 0000
304 09:25:19.748242
305 09:25:19.748331 F3: 1001 0000 [0200]
306 09:25:19.748424
307 09:25:19.748518 F3: 1001 0000
308 09:25:19.748615
309 09:25:19.748709 F7: 102D 0000
310 09:25:19.748798
311 09:25:19.748888 F1: 0000 0000
312 09:25:19.748977
313 09:25:19.749066 V0: 0000 0000 [0001]
314 09:25:19.749155
315 09:25:19.749243 00: 0007 8000
316 09:25:19.749337
317 09:25:19.749425 01: 0000 0000
318 09:25:19.749517
319 09:25:19.749605 BP: 0C00 0209 [0000]
320 09:25:19.749694
321 09:25:19.749781 G0: 1182 0000
322 09:25:19.749869
323 09:25:19.749957 EC: 0000 0021 [4000]
324 09:25:19.750047
325 09:25:19.750134 S7: 0000 0000 [0000]
326 09:25:19.750235
327 09:25:19.750325 CC: 0000 0000 [0001]
328 09:25:19.750414
329 09:25:19.750501 T0: 0000 0040 [010F]
330 09:25:19.750590
331 09:25:19.750676 Jump to BL
332 09:25:19.750764
333 09:25:19.750851
334 09:25:19.750939
335 09:25:19.751026 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 09:25:19.751120 ARM64: Exception handlers installed.
337 09:25:19.751209 ARM64: Testing exception
338 09:25:19.751298 ARM64: Done test exception
339 09:25:19.751386 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 09:25:19.751478 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 09:25:19.751569 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 09:25:19.751659 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 09:25:19.751749 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 09:25:19.751838 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 09:25:19.751928 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 09:25:19.752018 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 09:25:19.752107 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 09:25:19.752198 WDT: Last reset was cold boot
349 09:25:19.752287 SPI1(PAD0) initialized at 2873684 Hz
350 09:25:19.752376 SPI5(PAD0) initialized at 992727 Hz
351 09:25:19.752463 VBOOT: Loading verstage.
352 09:25:19.752550 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 09:25:19.752639 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 09:25:19.752729 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 09:25:19.752817 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 09:25:19.752907 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 09:25:19.752997 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 09:25:19.753087 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 09:25:19.753175
360 09:25:19.753263
361 09:25:19.753351 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 09:25:19.753441 ARM64: Exception handlers installed.
363 09:25:19.753530 ARM64: Testing exception
364 09:25:19.753619 ARM64: Done test exception
365 09:25:19.753707 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 09:25:19.753796 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 09:25:19.753884 Probing TPM: . done!
368 09:25:19.753972 TPM ready after 0 ms
369 09:25:19.754059 Connected to device vid:did:rid of 1ae0:0028:00
370 09:25:19.754147 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
371 09:25:19.754244 Initialized TPM device CR50 revision 0
372 09:25:19.754333 tlcl_send_startup: Startup return code is 0
373 09:25:19.754423 TPM: setup succeeded
374 09:25:19.754511 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 09:25:19.754599 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 09:25:19.754687 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 09:25:19.754776 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 09:25:19.754864 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 09:25:19.754953 in-header: 03 07 00 00 08 00 00 00
380 09:25:19.755039 in-data: aa e4 47 04 13 02 00 00
381 09:25:19.755127 Chrome EC: UHEPI supported
382 09:25:19.755216 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 09:25:19.755306 in-header: 03 a9 00 00 08 00 00 00
384 09:25:19.755395 in-data: 84 60 60 08 00 00 00 00
385 09:25:19.755482 Phase 1
386 09:25:19.755571 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 09:25:19.755662 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 09:25:19.755757 VB2:vb2_check_recovery() Recovery was requested manually
389 09:25:19.755848 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 09:25:19.755937 Recovery requested (1009000e)
391 09:25:19.756025 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 09:25:19.756114 tlcl_extend: response is 0
393 09:25:19.756202 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 09:25:19.756292 tlcl_extend: response is 0
395 09:25:19.756381 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 09:25:19.756470 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 09:25:19.756560 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 09:25:19.756649
399 09:25:19.756736
400 09:25:19.756824 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 09:25:19.756914 ARM64: Exception handlers installed.
402 09:25:19.757003 ARM64: Testing exception
403 09:25:19.757091 ARM64: Done test exception
404 09:25:19.757179 pmic_efuse_setting: Set efuses in 11 msecs
405 09:25:19.757266 pmwrap_interface_init: Select PMIF_VLD_RDY
406 09:25:19.757354 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 09:25:19.757659 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 09:25:19.757762 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 09:25:19.757855 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 09:25:19.757946 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 09:25:19.758036 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 09:25:19.758127 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 09:25:19.758231 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 09:25:19.758321 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 09:25:19.758410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 09:25:19.758498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 09:25:19.758589 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 09:25:19.758679 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 09:25:19.758768 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 09:25:19.758859 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 09:25:19.758948 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 09:25:19.759038 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 09:25:19.759127 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 09:25:19.759216 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 09:25:19.759306 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 09:25:19.759394 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 09:25:19.759483 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 09:25:19.759571 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 09:25:19.759660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 09:25:19.759748 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 09:25:19.759836 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 09:25:19.759925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 09:25:19.760014 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 09:25:19.760102 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 09:25:19.760190 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 09:25:19.760279 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 09:25:19.760371 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 09:25:19.760459 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 09:25:19.760547 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 09:25:19.760635 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 09:25:19.760724 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 09:25:19.760811 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 09:25:19.760900 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 09:25:19.760988 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 09:25:19.761076 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 09:25:19.761164 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 09:25:19.761253 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 09:25:19.761341 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 09:25:19.761428 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 09:25:19.761516 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 09:25:19.761604 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 09:25:19.761691 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 09:25:19.761781 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 09:25:19.761868 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 09:25:19.761956 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 09:25:19.762044 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 09:25:19.762132 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 09:25:19.762228 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 09:25:19.762317 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 09:25:19.762406 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 09:25:19.762495 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 09:25:19.762584 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 09:25:19.762674 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 09:25:19.762761 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 09:25:19.762849 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x32
466 09:25:19.762939 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 09:25:19.763028 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
468 09:25:19.763116 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 09:25:19.763203 [RTC]rtc_get_frequency_meter,154: input=15, output=836
470 09:25:19.763291 [RTC]rtc_get_frequency_meter,154: input=7, output=709
471 09:25:19.763378 [RTC]rtc_get_frequency_meter,154: input=11, output=772
472 09:25:19.763467 [RTC]rtc_get_frequency_meter,154: input=13, output=804
473 09:25:19.763555 [RTC]rtc_get_frequency_meter,154: input=12, output=788
474 09:25:19.763642 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 09:25:19.763730 [RTC]rtc_get_frequency_meter,154: input=13, output=804
476 09:25:19.763818 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
477 09:25:19.764121 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
478 09:25:19.764223 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 09:25:19.764314 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 09:25:19.764406 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 09:25:19.764495 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 09:25:19.764584 ADC[4]: Raw value=903031 ID=7
483 09:25:19.764672 ADC[3]: Raw value=214021 ID=1
484 09:25:19.764761 RAM Code: 0x71
485 09:25:19.764850 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 09:25:19.764939 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 09:25:19.765027 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 09:25:19.765117 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 09:25:19.765205 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 09:25:19.765294 in-header: 03 07 00 00 08 00 00 00
491 09:25:19.765382 in-data: aa e4 47 04 13 02 00 00
492 09:25:19.765470 Chrome EC: UHEPI supported
493 09:25:19.765557 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 09:25:19.765646 in-header: 03 a9 00 00 08 00 00 00
495 09:25:19.765734 in-data: 84 60 60 08 00 00 00 00
496 09:25:19.765822 MRC: failed to locate region type 0.
497 09:25:19.765912 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 09:25:19.766001 DRAM-K: Running full calibration
499 09:25:19.766089 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 09:25:19.766194 header.status = 0x0
501 09:25:19.766286 header.version = 0x6 (expected: 0x6)
502 09:25:19.766375 header.size = 0xd00 (expected: 0xd00)
503 09:25:19.766464 header.flags = 0x0
504 09:25:19.766551 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 09:25:19.766640 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 09:25:19.766729 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 09:25:19.766818 dram_init: ddr_geometry: 2
508 09:25:19.766906 [EMI] MDL number = 2
509 09:25:19.766993 [EMI] Get MDL freq = 0
510 09:25:19.767079 dram_init: ddr_type: 0
511 09:25:19.767166 is_discrete_lpddr4: 1
512 09:25:19.767253 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 09:25:19.767340
514 09:25:19.767426
515 09:25:19.767516 [Bian_co] ETT version 0.0.0.1
516 09:25:19.767607 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 09:25:19.767695
518 09:25:19.767782 dramc_set_vcore_voltage set vcore to 650000
519 09:25:19.767869 Read voltage for 800, 4
520 09:25:19.767957 Vio18 = 0
521 09:25:19.768044 Vcore = 650000
522 09:25:19.768131 Vdram = 0
523 09:25:19.768217 Vddq = 0
524 09:25:19.768306 Vmddr = 0
525 09:25:19.768393 dram_init: config_dvfs: 1
526 09:25:19.768482 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 09:25:19.768571 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 09:25:19.768659 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
529 09:25:19.768747 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
530 09:25:19.768836 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
531 09:25:19.768925 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
532 09:25:19.769012 MEM_TYPE=3, freq_sel=18
533 09:25:19.769100 sv_algorithm_assistance_LP4_1600
534 09:25:19.769189 ============ PULL DRAM RESETB DOWN ============
535 09:25:19.769279 ========== PULL DRAM RESETB DOWN end =========
536 09:25:19.769367 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 09:25:19.769454 ===================================
538 09:25:19.769542 LPDDR4 DRAM CONFIGURATION
539 09:25:19.769628 ===================================
540 09:25:19.769716 EX_ROW_EN[0] = 0x0
541 09:25:19.769804 EX_ROW_EN[1] = 0x0
542 09:25:19.769893 LP4Y_EN = 0x0
543 09:25:19.769980 WORK_FSP = 0x0
544 09:25:19.770068 WL = 0x2
545 09:25:19.770157 RL = 0x2
546 09:25:19.770252 BL = 0x2
547 09:25:19.770340 RPST = 0x0
548 09:25:19.770427 RD_PRE = 0x0
549 09:25:19.770513 WR_PRE = 0x1
550 09:25:19.770601 WR_PST = 0x0
551 09:25:19.770687 DBI_WR = 0x0
552 09:25:19.770775 DBI_RD = 0x0
553 09:25:19.770863 OTF = 0x1
554 09:25:19.770951 ===================================
555 09:25:19.771039 ===================================
556 09:25:19.771128 ANA top config
557 09:25:19.771215 ===================================
558 09:25:19.771304 DLL_ASYNC_EN = 0
559 09:25:19.771392 ALL_SLAVE_EN = 1
560 09:25:19.771480 NEW_RANK_MODE = 1
561 09:25:19.771570 DLL_IDLE_MODE = 1
562 09:25:19.771658 LP45_APHY_COMB_EN = 1
563 09:25:19.771747 TX_ODT_DIS = 1
564 09:25:19.771835 NEW_8X_MODE = 1
565 09:25:19.771924 ===================================
566 09:25:19.772013 ===================================
567 09:25:19.772104 data_rate = 1600
568 09:25:19.772193 CKR = 1
569 09:25:19.772279 DQ_P2S_RATIO = 8
570 09:25:19.772368 ===================================
571 09:25:19.772457 CA_P2S_RATIO = 8
572 09:25:19.772546 DQ_CA_OPEN = 0
573 09:25:19.772632 DQ_SEMI_OPEN = 0
574 09:25:19.772719 CA_SEMI_OPEN = 0
575 09:25:19.772808 CA_FULL_RATE = 0
576 09:25:19.772896 DQ_CKDIV4_EN = 1
577 09:25:19.772984 CA_CKDIV4_EN = 1
578 09:25:19.773072 CA_PREDIV_EN = 0
579 09:25:19.773160 PH8_DLY = 0
580 09:25:19.773248 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 09:25:19.773336 DQ_AAMCK_DIV = 4
582 09:25:19.773424 CA_AAMCK_DIV = 4
583 09:25:19.773513 CA_ADMCK_DIV = 4
584 09:25:19.773600 DQ_TRACK_CA_EN = 0
585 09:25:19.773687 CA_PICK = 800
586 09:25:19.773775 CA_MCKIO = 800
587 09:25:19.773863 MCKIO_SEMI = 0
588 09:25:19.773951 PLL_FREQ = 3068
589 09:25:19.774039 DQ_UI_PI_RATIO = 32
590 09:25:19.774127 CA_UI_PI_RATIO = 0
591 09:25:19.774222 ===================================
592 09:25:19.774312 ===================================
593 09:25:19.774400 memory_type:LPDDR4
594 09:25:19.774486 GP_NUM : 10
595 09:25:19.774573 SRAM_EN : 1
596 09:25:19.774661 MD32_EN : 0
597 09:25:19.774983 ===================================
598 09:25:19.775085 [ANA_INIT] >>>>>>>>>>>>>>
599 09:25:19.775179 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 09:25:19.775274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 09:25:19.775365 ===================================
602 09:25:19.775455 data_rate = 1600,PCW = 0X7600
603 09:25:19.775545 ===================================
604 09:25:19.775637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 09:25:19.775726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 09:25:19.775815 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 09:25:19.775906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 09:25:19.775995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 09:25:19.776083 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 09:25:19.776169 [ANA_INIT] flow start
611 09:25:19.776257 [ANA_INIT] PLL >>>>>>>>
612 09:25:19.776347 [ANA_INIT] PLL <<<<<<<<
613 09:25:19.776434 [ANA_INIT] MIDPI >>>>>>>>
614 09:25:19.776522 [ANA_INIT] MIDPI <<<<<<<<
615 09:25:19.776608 [ANA_INIT] DLL >>>>>>>>
616 09:25:19.776695 [ANA_INIT] flow end
617 09:25:19.776782 ============ LP4 DIFF to SE enter ============
618 09:25:19.776870 ============ LP4 DIFF to SE exit ============
619 09:25:19.776958 [ANA_INIT] <<<<<<<<<<<<<
620 09:25:19.777044 [Flow] Enable top DCM control >>>>>
621 09:25:19.777130 [Flow] Enable top DCM control <<<<<
622 09:25:19.777218 Enable DLL master slave shuffle
623 09:25:19.777307 ==============================================================
624 09:25:19.777396 Gating Mode config
625 09:25:19.777486 ==============================================================
626 09:25:19.777574 Config description:
627 09:25:19.777662 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 09:25:19.777753 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 09:25:19.777842 SELPH_MODE 0: By rank 1: By Phase
630 09:25:19.777931 ==============================================================
631 09:25:19.778021 GAT_TRACK_EN = 1
632 09:25:19.778110 RX_GATING_MODE = 2
633 09:25:19.778210 RX_GATING_TRACK_MODE = 2
634 09:25:19.778300 SELPH_MODE = 1
635 09:25:19.778390 PICG_EARLY_EN = 1
636 09:25:19.778479 VALID_LAT_VALUE = 1
637 09:25:19.778568 ==============================================================
638 09:25:19.778657 Enter into Gating configuration >>>>
639 09:25:19.778746 Exit from Gating configuration <<<<
640 09:25:19.778834 Enter into DVFS_PRE_config >>>>>
641 09:25:19.778923 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 09:25:19.779016 Exit from DVFS_PRE_config <<<<<
643 09:25:19.779104 Enter into PICG configuration >>>>
644 09:25:19.779192 Exit from PICG configuration <<<<
645 09:25:19.779280 [RX_INPUT] configuration >>>>>
646 09:25:19.779367 [RX_INPUT] configuration <<<<<
647 09:25:19.779456 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 09:25:19.779544 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 09:25:19.779632 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 09:25:19.779722 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 09:25:19.779810 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 09:25:19.779899 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 09:25:19.779987 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 09:25:19.780083 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 09:25:19.780172 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 09:25:19.780261 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 09:25:19.780350 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 09:25:19.780439 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 09:25:19.780528 ===================================
660 09:25:19.780617 LPDDR4 DRAM CONFIGURATION
661 09:25:19.780703 ===================================
662 09:25:19.780790 EX_ROW_EN[0] = 0x0
663 09:25:19.780878 EX_ROW_EN[1] = 0x0
664 09:25:19.780965 LP4Y_EN = 0x0
665 09:25:19.781052 WORK_FSP = 0x0
666 09:25:19.781139 WL = 0x2
667 09:25:19.781226 RL = 0x2
668 09:25:19.781315 BL = 0x2
669 09:25:19.781403 RPST = 0x0
670 09:25:19.781490 RD_PRE = 0x0
671 09:25:19.781578 WR_PRE = 0x1
672 09:25:19.781665 WR_PST = 0x0
673 09:25:19.781752 DBI_WR = 0x0
674 09:25:19.781840 DBI_RD = 0x0
675 09:25:19.781927 OTF = 0x1
676 09:25:19.782015 ===================================
677 09:25:19.782105 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 09:25:19.782205 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 09:25:19.782294 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 09:25:19.782382 ===================================
681 09:25:19.782471 LPDDR4 DRAM CONFIGURATION
682 09:25:19.782559 ===================================
683 09:25:19.782647 EX_ROW_EN[0] = 0x10
684 09:25:19.782734 EX_ROW_EN[1] = 0x0
685 09:25:19.782822 LP4Y_EN = 0x0
686 09:25:19.782910 WORK_FSP = 0x0
687 09:25:19.782997 WL = 0x2
688 09:25:19.783084 RL = 0x2
689 09:25:19.783170 BL = 0x2
690 09:25:19.783257 RPST = 0x0
691 09:25:19.783342 RD_PRE = 0x0
692 09:25:19.783428 WR_PRE = 0x1
693 09:25:19.783515 WR_PST = 0x0
694 09:25:19.783601 DBI_WR = 0x0
695 09:25:19.783689 DBI_RD = 0x0
696 09:25:19.783776 OTF = 0x1
697 09:25:19.783864 ===================================
698 09:25:19.783953 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 09:25:19.784042 nWR fixed to 40
700 09:25:19.784131 [ModeRegInit_LP4] CH0 RK0
701 09:25:19.784219 [ModeRegInit_LP4] CH0 RK1
702 09:25:19.784307 [ModeRegInit_LP4] CH1 RK0
703 09:25:19.784394 [ModeRegInit_LP4] CH1 RK1
704 09:25:19.784482 match AC timing 13
705 09:25:19.784570 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 09:25:19.784882 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 09:25:19.784985 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 09:25:19.785078 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 09:25:19.785172 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 09:25:19.785263 [EMI DOE] emi_dcm 0
711 09:25:19.785350 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 09:25:19.785440 ==
713 09:25:19.785531 Dram Type= 6, Freq= 0, CH_0, rank 0
714 09:25:19.785622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 09:25:19.785713 ==
716 09:25:19.785803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 09:25:19.785892 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 09:25:19.785980 [CA 0] Center 37 (7~68) winsize 62
719 09:25:19.786071 [CA 1] Center 37 (6~68) winsize 63
720 09:25:19.786171 [CA 2] Center 34 (4~65) winsize 62
721 09:25:19.786261 [CA 3] Center 34 (4~65) winsize 62
722 09:25:19.786349 [CA 4] Center 33 (3~64) winsize 62
723 09:25:19.786437 [CA 5] Center 33 (3~64) winsize 62
724 09:25:19.786525
725 09:25:19.786612 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 09:25:19.786698
727 09:25:19.786785 [CATrainingPosCal] consider 1 rank data
728 09:25:19.786872 u2DelayCellTimex100 = 270/100 ps
729 09:25:19.786959 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 09:25:19.787049 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 09:25:19.787137 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 09:25:19.787226 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 09:25:19.787314 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 09:25:19.787405 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 09:25:19.787493
736 09:25:19.787580 CA PerBit enable=1, Macro0, CA PI delay=33
737 09:25:19.787669
738 09:25:19.787757 [CBTSetCACLKResult] CA Dly = 33
739 09:25:19.787845 CS Dly: 7 (0~38)
740 09:25:19.787934 ==
741 09:25:19.788022 Dram Type= 6, Freq= 0, CH_0, rank 1
742 09:25:19.788110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 09:25:19.788199 ==
744 09:25:19.788286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 09:25:19.788376 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 09:25:19.788466 [CA 0] Center 37 (6~68) winsize 63
747 09:25:19.788554 [CA 1] Center 37 (7~68) winsize 62
748 09:25:19.788642 [CA 2] Center 34 (4~65) winsize 62
749 09:25:19.788729 [CA 3] Center 34 (4~65) winsize 62
750 09:25:19.788817 [CA 4] Center 33 (3~64) winsize 62
751 09:25:19.788906 [CA 5] Center 33 (3~64) winsize 62
752 09:25:19.788993
753 09:25:19.789081 [CmdBusTrainingLP45] Vref(ca) range 1: 32
754 09:25:19.789169
755 09:25:19.789259 [CATrainingPosCal] consider 2 rank data
756 09:25:19.789347 u2DelayCellTimex100 = 270/100 ps
757 09:25:19.789437 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 09:25:19.789524 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 09:25:19.789614 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 09:25:19.789703 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 09:25:19.789792 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 09:25:19.789881 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 09:25:19.789972
764 09:25:19.790060 CA PerBit enable=1, Macro0, CA PI delay=33
765 09:25:19.790149
766 09:25:19.790262 [CBTSetCACLKResult] CA Dly = 33
767 09:25:19.790353 CS Dly: 7 (0~38)
768 09:25:19.790442
769 09:25:19.790530 ----->DramcWriteLeveling(PI) begin...
770 09:25:19.790620 ==
771 09:25:19.790711 Dram Type= 6, Freq= 0, CH_0, rank 0
772 09:25:19.790799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 09:25:19.790890 ==
774 09:25:19.790978 Write leveling (Byte 0): 32 => 32
775 09:25:19.791066 Write leveling (Byte 1): 31 => 31
776 09:25:19.791157 DramcWriteLeveling(PI) end<-----
777 09:25:19.791246
778 09:25:19.791337 ==
779 09:25:19.791424 Dram Type= 6, Freq= 0, CH_0, rank 0
780 09:25:19.791511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 09:25:19.791599 ==
782 09:25:19.791687 [Gating] SW mode calibration
783 09:25:19.791775 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 09:25:19.791863 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 09:25:19.791951 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 09:25:19.792040 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 09:25:19.792128 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 09:25:19.792216 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 09:25:19.792303 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 09:25:19.792391 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 09:25:19.792478 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 09:25:19.792565 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 09:25:19.792653 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 09:25:19.792741 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 09:25:19.792830 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 09:25:19.792919 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 09:25:19.793008 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 09:25:19.793097 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 09:25:19.793186 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 09:25:19.793274 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 09:25:19.793362 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 09:25:19.793450 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 09:25:19.793538 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
804 09:25:19.793626 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 09:25:19.793716 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 09:25:19.793804 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 09:25:19.793893 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 09:25:19.793981 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 09:25:19.794069 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 09:25:19.794165 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 09:25:19.794255 0 9 8 | B1->B0 | 2322 2b2b | 1 1 | (0 0) (1 1)
812 09:25:19.794343 0 9 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
813 09:25:19.794432 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 09:25:19.794759 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 09:25:19.794859 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 09:25:19.794951 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 09:25:19.795041 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 09:25:19.795131 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
819 09:25:19.795220 0 10 8 | B1->B0 | 3333 2626 | 0 0 | (0 1) (0 0)
820 09:25:19.795308 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
821 09:25:19.795397 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 09:25:19.795486 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 09:25:19.795573 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 09:25:19.795662 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 09:25:19.795752 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 09:25:19.795841 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
827 09:25:19.795931 0 11 8 | B1->B0 | 2626 3c3c | 0 1 | (0 0) (0 0)
828 09:25:19.796019 0 11 12 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
829 09:25:19.796106 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 09:25:19.796194 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 09:25:19.796282 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 09:25:19.796370 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 09:25:19.796457 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 09:25:19.796544 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 09:25:19.796631 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
836 09:25:19.796719 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 09:25:19.796806 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 09:25:19.796892 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 09:25:19.796979 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 09:25:19.797066 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 09:25:19.797154 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 09:25:19.797241 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 09:25:19.797328 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:25:19.797417 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 09:25:19.797504 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 09:25:19.797592 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 09:25:19.797681 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 09:25:19.797770 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 09:25:19.797859 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 09:25:19.797947 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 09:25:19.798035 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 09:25:19.798123 Total UI for P1: 0, mck2ui 16
853 09:25:19.798230 best dqsien dly found for B0: ( 0, 14, 4)
854 09:25:19.798321 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
855 09:25:19.798409 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 09:25:19.798497 Total UI for P1: 0, mck2ui 16
857 09:25:19.798585 best dqsien dly found for B1: ( 0, 14, 10)
858 09:25:19.798672 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 09:25:19.798760 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 09:25:19.798848
861 09:25:19.798935 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 09:25:19.799024 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 09:25:19.799113 [Gating] SW calibration Done
864 09:25:19.799201 ==
865 09:25:19.799289 Dram Type= 6, Freq= 0, CH_0, rank 0
866 09:25:19.799376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 09:25:19.799466 ==
868 09:25:19.799554 RX Vref Scan: 0
869 09:25:19.799641
870 09:25:19.799728 RX Vref 0 -> 0, step: 1
871 09:25:19.799815
872 09:25:19.799902 RX Delay -130 -> 252, step: 16
873 09:25:19.799991 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 09:25:19.800080 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 09:25:19.800168 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 09:25:19.800256 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 09:25:19.800343 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 09:25:19.800431 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 09:25:19.800519 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 09:25:19.800608 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 09:25:19.800696 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
882 09:25:19.800787 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
883 09:25:19.800875 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 09:25:19.800965 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
885 09:25:19.801054 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
886 09:25:19.801145 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
887 09:25:19.801234 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 09:25:19.801325 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
889 09:25:19.801413 ==
890 09:25:19.801502 Dram Type= 6, Freq= 0, CH_0, rank 0
891 09:25:19.801591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 09:25:19.801679 ==
893 09:25:19.801768 DQS Delay:
894 09:25:19.801855 DQS0 = 0, DQS1 = 0
895 09:25:19.801942 DQM Delay:
896 09:25:19.802029 DQM0 = 87, DQM1 = 70
897 09:25:19.802115 DQ Delay:
898 09:25:19.802210 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 09:25:19.802300 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
900 09:25:19.802388 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
901 09:25:19.802477 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
902 09:25:19.802564
903 09:25:19.802653
904 09:25:19.802740 ==
905 09:25:19.802828 Dram Type= 6, Freq= 0, CH_0, rank 0
906 09:25:19.802917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 09:25:19.803005 ==
908 09:25:19.803093
909 09:25:19.803180
910 09:25:19.803267 TX Vref Scan disable
911 09:25:19.803353 == TX Byte 0 ==
912 09:25:19.803440 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 09:25:19.803529 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 09:25:19.803618 == TX Byte 1 ==
915 09:25:19.803705 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
916 09:25:19.803795 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
917 09:25:19.803883 ==
918 09:25:19.803973 Dram Type= 6, Freq= 0, CH_0, rank 0
919 09:25:19.804062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 09:25:19.804153 ==
921 09:25:19.804462 TX Vref=22, minBit 5, minWin=27, winSum=444
922 09:25:19.804564 TX Vref=24, minBit 13, minWin=27, winSum=448
923 09:25:19.804657 TX Vref=26, minBit 4, minWin=27, winSum=448
924 09:25:19.804749 TX Vref=28, minBit 10, minWin=27, winSum=451
925 09:25:19.804840 TX Vref=30, minBit 9, minWin=27, winSum=449
926 09:25:19.804929 TX Vref=32, minBit 5, minWin=27, winSum=444
927 09:25:19.805018 [TxChooseVref] Worse bit 10, Min win 27, Win sum 451, Final Vref 28
928 09:25:19.805107
929 09:25:19.805194 Final TX Range 1 Vref 28
930 09:25:19.805282
931 09:25:19.805369 ==
932 09:25:19.805457 Dram Type= 6, Freq= 0, CH_0, rank 0
933 09:25:19.805545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 09:25:19.805634 ==
935 09:25:19.805723
936 09:25:19.805808
937 09:25:19.805894 TX Vref Scan disable
938 09:25:19.805982 == TX Byte 0 ==
939 09:25:19.806068 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 09:25:19.806156 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 09:25:19.806256 == TX Byte 1 ==
942 09:25:19.806344 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
943 09:25:19.806437 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
944 09:25:19.806524
945 09:25:19.806613 [DATLAT]
946 09:25:19.806700 Freq=800, CH0 RK0
947 09:25:19.806790
948 09:25:19.806877 DATLAT Default: 0xa
949 09:25:19.806962 0, 0xFFFF, sum = 0
950 09:25:19.807052 1, 0xFFFF, sum = 0
951 09:25:19.807141 2, 0xFFFF, sum = 0
952 09:25:19.807229 3, 0xFFFF, sum = 0
953 09:25:19.807317 4, 0xFFFF, sum = 0
954 09:25:19.807405 5, 0xFFFF, sum = 0
955 09:25:19.807493 6, 0xFFFF, sum = 0
956 09:25:19.807582 7, 0xFFFF, sum = 0
957 09:25:19.807671 8, 0xFFFF, sum = 0
958 09:25:19.807760 9, 0x0, sum = 1
959 09:25:19.807850 10, 0x0, sum = 2
960 09:25:19.807940 11, 0x0, sum = 3
961 09:25:19.808028 12, 0x0, sum = 4
962 09:25:19.808116 best_step = 10
963 09:25:19.808203
964 09:25:19.808289 ==
965 09:25:19.808374 Dram Type= 6, Freq= 0, CH_0, rank 0
966 09:25:19.808461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 09:25:19.808549 ==
968 09:25:19.808636 RX Vref Scan: 1
969 09:25:19.808722
970 09:25:19.808809 Set Vref Range= 32 -> 127
971 09:25:19.808895
972 09:25:19.808981 RX Vref 32 -> 127, step: 1
973 09:25:19.809067
974 09:25:19.809152 RX Delay -111 -> 252, step: 8
975 09:25:19.809239
976 09:25:19.809327 Set Vref, RX VrefLevel [Byte0]: 32
977 09:25:19.809414 [Byte1]: 32
978 09:25:19.809501
979 09:25:19.809588 Set Vref, RX VrefLevel [Byte0]: 33
980 09:25:19.809676 [Byte1]: 33
981 09:25:19.809762
982 09:25:19.809850 Set Vref, RX VrefLevel [Byte0]: 34
983 09:25:19.809937 [Byte1]: 34
984 09:25:19.810023
985 09:25:19.810111 Set Vref, RX VrefLevel [Byte0]: 35
986 09:25:19.810235 [Byte1]: 35
987 09:25:19.810348
988 09:25:19.810444 Set Vref, RX VrefLevel [Byte0]: 36
989 09:25:19.810510 [Byte1]: 36
990 09:25:19.810570
991 09:25:19.810652 Set Vref, RX VrefLevel [Byte0]: 37
992 09:25:19.810742 [Byte1]: 37
993 09:25:19.810832
994 09:25:19.810917 Set Vref, RX VrefLevel [Byte0]: 38
995 09:25:19.811005 [Byte1]: 38
996 09:25:19.811093
997 09:25:19.811178 Set Vref, RX VrefLevel [Byte0]: 39
998 09:25:19.811267 [Byte1]: 39
999 09:25:19.811348
1000 09:25:19.811404 Set Vref, RX VrefLevel [Byte0]: 40
1001 09:25:19.811464 [Byte1]: 40
1002 09:25:19.811520
1003 09:25:19.811573 Set Vref, RX VrefLevel [Byte0]: 41
1004 09:25:19.811635 [Byte1]: 41
1005 09:25:19.811720
1006 09:25:19.811803 Set Vref, RX VrefLevel [Byte0]: 42
1007 09:25:19.811890 [Byte1]: 42
1008 09:25:19.811977
1009 09:25:19.812069 Set Vref, RX VrefLevel [Byte0]: 43
1010 09:25:19.812154 [Byte1]: 43
1011 09:25:19.812240
1012 09:25:19.812332 Set Vref, RX VrefLevel [Byte0]: 44
1013 09:25:19.812422 [Byte1]: 44
1014 09:25:19.812516
1015 09:25:19.812600 Set Vref, RX VrefLevel [Byte0]: 45
1016 09:25:19.812682 [Byte1]: 45
1017 09:25:19.812740
1018 09:25:19.812797 Set Vref, RX VrefLevel [Byte0]: 46
1019 09:25:19.812857 [Byte1]: 46
1020 09:25:19.812941
1021 09:25:19.813025 Set Vref, RX VrefLevel [Byte0]: 47
1022 09:25:19.813112 [Byte1]: 47
1023 09:25:19.813195
1024 09:25:19.813284 Set Vref, RX VrefLevel [Byte0]: 48
1025 09:25:19.813375 [Byte1]: 48
1026 09:25:19.813465
1027 09:25:19.813554 Set Vref, RX VrefLevel [Byte0]: 49
1028 09:25:19.813643 [Byte1]: 49
1029 09:25:19.813728
1030 09:25:19.813821 Set Vref, RX VrefLevel [Byte0]: 50
1031 09:25:19.813909 [Byte1]: 50
1032 09:25:19.813992
1033 09:25:19.814077 Set Vref, RX VrefLevel [Byte0]: 51
1034 09:25:19.814172 [Byte1]: 51
1035 09:25:19.814257
1036 09:25:19.814343 Set Vref, RX VrefLevel [Byte0]: 52
1037 09:25:19.814426 [Byte1]: 52
1038 09:25:19.814511
1039 09:25:19.814597 Set Vref, RX VrefLevel [Byte0]: 53
1040 09:25:19.814684 [Byte1]: 53
1041 09:25:19.814739
1042 09:25:19.814792 Set Vref, RX VrefLevel [Byte0]: 54
1043 09:25:19.814852 [Byte1]: 54
1044 09:25:19.814906
1045 09:25:19.814959 Set Vref, RX VrefLevel [Byte0]: 55
1046 09:25:19.815012 [Byte1]: 55
1047 09:25:19.815094
1048 09:25:19.815180 Set Vref, RX VrefLevel [Byte0]: 56
1049 09:25:19.815263 [Byte1]: 56
1050 09:25:19.815350
1051 09:25:19.815432 Set Vref, RX VrefLevel [Byte0]: 57
1052 09:25:19.815518 [Byte1]: 57
1053 09:25:19.815600
1054 09:25:19.815687 Set Vref, RX VrefLevel [Byte0]: 58
1055 09:25:19.815748 [Byte1]: 58
1056 09:25:19.815801
1057 09:25:19.815854 Set Vref, RX VrefLevel [Byte0]: 59
1058 09:25:19.815925 [Byte1]: 59
1059 09:25:19.815980
1060 09:25:19.816031 Set Vref, RX VrefLevel [Byte0]: 60
1061 09:25:19.816091 [Byte1]: 60
1062 09:25:19.816174
1063 09:25:19.816256 Set Vref, RX VrefLevel [Byte0]: 61
1064 09:25:19.816345 [Byte1]: 61
1065 09:25:19.816427
1066 09:25:19.816509 Set Vref, RX VrefLevel [Byte0]: 62
1067 09:25:19.816595 [Byte1]: 62
1068 09:25:19.816691
1069 09:25:19.816779 Set Vref, RX VrefLevel [Byte0]: 63
1070 09:25:19.816862 [Byte1]: 63
1071 09:25:19.816940
1072 09:25:19.817005 Set Vref, RX VrefLevel [Byte0]: 64
1073 09:25:19.817059 [Byte1]: 64
1074 09:25:19.817120
1075 09:25:19.817174 Set Vref, RX VrefLevel [Byte0]: 65
1076 09:25:19.817227 [Byte1]: 65
1077 09:25:19.817279
1078 09:25:19.817365 Set Vref, RX VrefLevel [Byte0]: 66
1079 09:25:19.817448 [Byte1]: 66
1080 09:25:19.817533
1081 09:25:19.817615 Set Vref, RX VrefLevel [Byte0]: 67
1082 09:25:19.817701 [Byte1]: 67
1083 09:25:19.817795
1084 09:25:19.817879 Set Vref, RX VrefLevel [Byte0]: 68
1085 09:25:19.817964 [Byte1]: 68
1086 09:25:19.818047
1087 09:25:19.818130 Set Vref, RX VrefLevel [Byte0]: 69
1088 09:25:19.818423 [Byte1]: 69
1089 09:25:19.818514
1090 09:25:19.818599 Set Vref, RX VrefLevel [Byte0]: 70
1091 09:25:19.818706 [Byte1]: 70
1092 09:25:19.818805
1093 09:25:19.818896 Set Vref, RX VrefLevel [Byte0]: 71
1094 09:25:19.818984 [Byte1]: 71
1095 09:25:19.819066
1096 09:25:19.819154 Set Vref, RX VrefLevel [Byte0]: 72
1097 09:25:19.819238 [Byte1]: 72
1098 09:25:19.819320
1099 09:25:19.819412 Set Vref, RX VrefLevel [Byte0]: 73
1100 09:25:19.819469 [Byte1]: 73
1101 09:25:19.819522
1102 09:25:19.819607 Set Vref, RX VrefLevel [Byte0]: 74
1103 09:25:19.819689 [Byte1]: 74
1104 09:25:19.819777
1105 09:25:19.819859 Set Vref, RX VrefLevel [Byte0]: 75
1106 09:25:19.819948 [Byte1]: 75
1107 09:25:19.820030
1108 09:25:19.820118 Set Vref, RX VrefLevel [Byte0]: 76
1109 09:25:19.820216 [Byte1]: 76
1110 09:25:19.820303
1111 09:25:19.820390 Set Vref, RX VrefLevel [Byte0]: 77
1112 09:25:19.820473 [Byte1]: 77
1113 09:25:19.820554
1114 09:25:19.820652 Set Vref, RX VrefLevel [Byte0]: 78
1115 09:25:19.820738 [Byte1]: 78
1116 09:25:19.820807
1117 09:25:19.820890 Set Vref, RX VrefLevel [Byte0]: 79
1118 09:25:19.820975 [Byte1]: 79
1119 09:25:19.821058
1120 09:25:19.821140 Set Vref, RX VrefLevel [Byte0]: 80
1121 09:25:19.821237 [Byte1]: 80
1122 09:25:19.821327
1123 09:25:19.821416 Set Vref, RX VrefLevel [Byte0]: 81
1124 09:25:19.821503 [Byte1]: 81
1125 09:25:19.821592
1126 09:25:19.821674 Set Vref, RX VrefLevel [Byte0]: 82
1127 09:25:19.821762 [Byte1]: 82
1128 09:25:19.821849
1129 09:25:19.821936 Set Vref, RX VrefLevel [Byte0]: 83
1130 09:25:19.822021 [Byte1]: 83
1131 09:25:19.822102
1132 09:25:19.822216 Final RX Vref Byte 0 = 62 to rank0
1133 09:25:19.822306 Final RX Vref Byte 1 = 57 to rank0
1134 09:25:19.822397 Final RX Vref Byte 0 = 62 to rank1
1135 09:25:19.822481 Final RX Vref Byte 1 = 57 to rank1==
1136 09:25:19.822565 Dram Type= 6, Freq= 0, CH_0, rank 0
1137 09:25:19.822664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 09:25:19.822757 ==
1139 09:25:19.822841 DQS Delay:
1140 09:25:19.822930 DQS0 = 0, DQS1 = 0
1141 09:25:19.823022 DQM Delay:
1142 09:25:19.823105 DQM0 = 87, DQM1 = 75
1143 09:25:19.823190 DQ Delay:
1144 09:25:19.823273 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1145 09:25:19.823359 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1146 09:25:19.823450 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1147 09:25:19.823537 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1148 09:25:19.823637
1149 09:25:19.823719
1150 09:25:19.823803 [DQSOSCAuto] RK0, (LSB)MR18= 0x4829, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
1151 09:25:19.823891 CH0 RK0: MR19=606, MR18=4829
1152 09:25:19.823982 CH0_RK0: MR19=0x606, MR18=0x4829, DQSOSC=391, MR23=63, INC=96, DEC=64
1153 09:25:19.824069
1154 09:25:19.824152 ----->DramcWriteLeveling(PI) begin...
1155 09:25:19.824243 ==
1156 09:25:19.824327 Dram Type= 6, Freq= 0, CH_0, rank 1
1157 09:25:19.824413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 09:25:19.824496 ==
1159 09:25:19.824586 Write leveling (Byte 0): 33 => 33
1160 09:25:19.824685 Write leveling (Byte 1): 34 => 34
1161 09:25:19.824777 DramcWriteLeveling(PI) end<-----
1162 09:25:19.824866
1163 09:25:19.824952 ==
1164 09:25:19.825038 Dram Type= 6, Freq= 0, CH_0, rank 1
1165 09:25:19.825122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1166 09:25:19.825206 ==
1167 09:25:19.825295 [Gating] SW mode calibration
1168 09:25:19.825351 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1169 09:25:19.825413 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1170 09:25:19.825499 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1171 09:25:19.825582 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1172 09:25:19.825670 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1173 09:25:19.825752 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 09:25:19.825844 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 09:25:19.825933 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 09:25:19.826016 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 09:25:19.826105 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 09:25:19.826197 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 09:25:19.826285 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 09:25:19.826369 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 09:25:19.826460 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 09:25:19.826522 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 09:25:19.826576 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 09:25:19.826642 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 09:25:19.826735 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 09:25:19.826820 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 09:25:19.826906 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1188 09:25:19.827007 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1189 09:25:19.827097 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 09:25:19.827181 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 09:25:19.827268 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 09:25:19.827355 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 09:25:19.827442 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 09:25:19.827526 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 09:25:19.827582 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 09:25:19.827635 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1197 09:25:19.827697 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 09:25:19.827781 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 09:25:19.827868 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 09:25:19.827953 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 09:25:19.828040 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1202 09:25:19.828107 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1203 09:25:19.828161 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1204 09:25:19.828214 0 10 8 | B1->B0 | 3030 2a2a | 0 0 | (0 1) (0 1)
1205 09:25:19.828510 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1206 09:25:19.828625 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 09:25:19.828743 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 09:25:19.828852 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 09:25:19.828959 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 09:25:19.829052 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 09:25:19.829143 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1212 09:25:19.829228 0 11 8 | B1->B0 | 2f2f 4343 | 0 0 | (0 0) (0 0)
1213 09:25:19.829314 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 09:25:19.829398 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 09:25:19.829483 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 09:25:19.829575 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 09:25:19.829660 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 09:25:19.829747 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 09:25:19.829831 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 09:25:19.829920 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1221 09:25:19.830009 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 09:25:19.830093 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 09:25:19.830201 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 09:25:19.830287 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 09:25:19.830374 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 09:25:19.830457 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 09:25:19.830540 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 09:25:19.830597 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 09:25:19.830655 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 09:25:19.830729 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 09:25:19.830784 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 09:25:19.830837 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 09:25:19.830890 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 09:25:19.830952 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 09:25:19.831005 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 09:25:19.831058 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1237 09:25:19.831120 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1238 09:25:19.831208 Total UI for P1: 0, mck2ui 16
1239 09:25:19.831295 best dqsien dly found for B0: ( 0, 14, 8)
1240 09:25:19.831382 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 09:25:19.831466 Total UI for P1: 0, mck2ui 16
1242 09:25:19.831556 best dqsien dly found for B1: ( 0, 14, 10)
1243 09:25:19.831637 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1244 09:25:19.831692 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1245 09:25:19.831757
1246 09:25:19.831841 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1247 09:25:19.831925 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1248 09:25:19.832009 [Gating] SW calibration Done
1249 09:25:19.832091 ==
1250 09:25:19.832181 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 09:25:19.832263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1252 09:25:19.832328 ==
1253 09:25:19.832411 RX Vref Scan: 0
1254 09:25:19.832493
1255 09:25:19.832579 RX Vref 0 -> 0, step: 1
1256 09:25:19.832681
1257 09:25:19.832783 RX Delay -130 -> 252, step: 16
1258 09:25:19.832861 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1259 09:25:19.832916 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1260 09:25:19.832996 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1261 09:25:19.833080 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1262 09:25:19.833172 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1263 09:25:19.833270 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1264 09:25:19.833359 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1265 09:25:19.833445 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1266 09:25:19.833537 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1267 09:25:19.833632 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1268 09:25:19.833728 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1269 09:25:19.833815 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1270 09:25:19.833898 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1271 09:25:19.834000 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1272 09:25:19.834092 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1273 09:25:19.834213 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1274 09:25:19.834299 ==
1275 09:25:19.834388 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 09:25:19.834472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 09:25:19.834561 ==
1278 09:25:19.834652 DQS Delay:
1279 09:25:19.834751 DQS0 = 0, DQS1 = 0
1280 09:25:19.834835 DQM Delay:
1281 09:25:19.834916 DQM0 = 82, DQM1 = 75
1282 09:25:19.835006 DQ Delay:
1283 09:25:19.835093 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1284 09:25:19.835155 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1285 09:25:19.835209 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1286 09:25:19.835262 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1287 09:25:19.835317
1288 09:25:19.835402
1289 09:25:19.835484 ==
1290 09:25:19.835567 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 09:25:19.835653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 09:25:19.835740 ==
1293 09:25:19.835829
1294 09:25:19.835911
1295 09:25:19.835999 TX Vref Scan disable
1296 09:25:19.836086 == TX Byte 0 ==
1297 09:25:19.836173 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1298 09:25:19.836257 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1299 09:25:19.836339 == TX Byte 1 ==
1300 09:25:19.836425 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1301 09:25:19.836509 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1302 09:25:19.836599 ==
1303 09:25:19.836655 Dram Type= 6, Freq= 0, CH_0, rank 1
1304 09:25:19.836751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1305 09:25:19.836834 ==
1306 09:25:19.836917 TX Vref=22, minBit 5, minWin=27, winSum=447
1307 09:25:19.837003 TX Vref=24, minBit 8, minWin=27, winSum=449
1308 09:25:19.837094 TX Vref=26, minBit 0, minWin=28, winSum=451
1309 09:25:19.837181 TX Vref=28, minBit 1, minWin=28, winSum=451
1310 09:25:19.837268 TX Vref=30, minBit 10, minWin=27, winSum=450
1311 09:25:19.837351 TX Vref=32, minBit 10, minWin=27, winSum=448
1312 09:25:19.837443 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 26
1313 09:25:19.837529
1314 09:25:19.837618 Final TX Range 1 Vref 26
1315 09:25:19.837702
1316 09:25:19.838003 ==
1317 09:25:19.838111 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 09:25:19.838233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 09:25:19.838340 ==
1320 09:25:19.838449
1321 09:25:19.838542
1322 09:25:19.838636 TX Vref Scan disable
1323 09:25:19.838693 == TX Byte 0 ==
1324 09:25:19.838747 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1325 09:25:19.838800 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1326 09:25:19.838885 == TX Byte 1 ==
1327 09:25:19.838967 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1328 09:25:19.839036 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1329 09:25:19.839089
1330 09:25:19.839140 [DATLAT]
1331 09:25:19.839194 Freq=800, CH0 RK1
1332 09:25:19.839271
1333 09:25:19.839324 DATLAT Default: 0xa
1334 09:25:19.839376 0, 0xFFFF, sum = 0
1335 09:25:19.839437 1, 0xFFFF, sum = 0
1336 09:25:19.839492 2, 0xFFFF, sum = 0
1337 09:25:19.839545 3, 0xFFFF, sum = 0
1338 09:25:19.839606 4, 0xFFFF, sum = 0
1339 09:25:19.839670 5, 0xFFFF, sum = 0
1340 09:25:19.839724 6, 0xFFFF, sum = 0
1341 09:25:19.839778 7, 0xFFFF, sum = 0
1342 09:25:19.839834 8, 0xFFFF, sum = 0
1343 09:25:19.839889 9, 0x0, sum = 1
1344 09:25:19.839942 10, 0x0, sum = 2
1345 09:25:19.839994 11, 0x0, sum = 3
1346 09:25:19.840054 12, 0x0, sum = 4
1347 09:25:19.840107 best_step = 10
1348 09:25:19.840171
1349 09:25:19.840235 ==
1350 09:25:19.840288 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 09:25:19.840340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 09:25:19.840411 ==
1353 09:25:19.840486 RX Vref Scan: 0
1354 09:25:19.840541
1355 09:25:19.840593 RX Vref 0 -> 0, step: 1
1356 09:25:19.840679
1357 09:25:19.840760 RX Delay -95 -> 252, step: 8
1358 09:25:19.840845 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1359 09:25:19.840935 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1360 09:25:19.841017 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1361 09:25:19.841109 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1362 09:25:19.841197 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1363 09:25:19.841285 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1364 09:25:19.841368 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1365 09:25:19.841450 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1366 09:25:19.841545 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1367 09:25:19.841628 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1368 09:25:19.841716 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1369 09:25:19.841798 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1370 09:25:19.841895 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1371 09:25:19.841979 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1372 09:25:19.842068 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1373 09:25:19.842152 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1374 09:25:19.842218 ==
1375 09:25:19.842316 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 09:25:19.842400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 09:25:19.842484 ==
1378 09:25:19.842572 DQS Delay:
1379 09:25:19.842654 DQS0 = 0, DQS1 = 0
1380 09:25:19.842749 DQM Delay:
1381 09:25:19.842831 DQM0 = 85, DQM1 = 76
1382 09:25:19.842918 DQ Delay:
1383 09:25:19.843001 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =84
1384 09:25:19.843091 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1385 09:25:19.843177 DQ8 =68, DQ9 =60, DQ10 =80, DQ11 =68
1386 09:25:19.843263 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1387 09:25:19.843333
1388 09:25:19.843415
1389 09:25:19.843512 [DQSOSCAuto] RK1, (LSB)MR18= 0x4006, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1390 09:25:19.843596 CH0 RK1: MR19=606, MR18=4006
1391 09:25:19.843694 CH0_RK1: MR19=0x606, MR18=0x4006, DQSOSC=393, MR23=63, INC=95, DEC=63
1392 09:25:19.843779 [RxdqsGatingPostProcess] freq 800
1393 09:25:19.843862 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1394 09:25:19.843952 Pre-setting of DQS Precalculation
1395 09:25:19.844035 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1396 09:25:19.844127 ==
1397 09:25:19.844218 Dram Type= 6, Freq= 0, CH_1, rank 0
1398 09:25:19.844316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 09:25:19.844413 ==
1400 09:25:19.844514 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1401 09:25:19.844601 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1402 09:25:19.844689 [CA 0] Center 36 (6~67) winsize 62
1403 09:25:19.844773 [CA 1] Center 36 (6~67) winsize 62
1404 09:25:19.844862 [CA 2] Center 34 (4~65) winsize 62
1405 09:25:19.844959 [CA 3] Center 34 (3~65) winsize 63
1406 09:25:19.845054 [CA 4] Center 34 (4~65) winsize 62
1407 09:25:19.845136 [CA 5] Center 34 (3~65) winsize 63
1408 09:25:19.845211
1409 09:25:19.845265 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1410 09:25:19.845317
1411 09:25:19.845406 [CATrainingPosCal] consider 1 rank data
1412 09:25:19.845490 u2DelayCellTimex100 = 270/100 ps
1413 09:25:19.845585 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1414 09:25:19.845670 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1415 09:25:19.845765 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1416 09:25:19.845851 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1417 09:25:19.845938 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1418 09:25:19.846021 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1419 09:25:19.846104
1420 09:25:19.846197 CA PerBit enable=1, Macro0, CA PI delay=34
1421 09:25:19.846252
1422 09:25:19.846311 [CBTSetCACLKResult] CA Dly = 34
1423 09:25:19.846375 CS Dly: 5 (0~36)
1424 09:25:19.846440 ==
1425 09:25:19.846502 Dram Type= 6, Freq= 0, CH_1, rank 1
1426 09:25:19.846554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 09:25:19.846649 ==
1428 09:25:19.846732 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1429 09:25:19.846824 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1430 09:25:19.846921 [CA 0] Center 36 (6~67) winsize 62
1431 09:25:19.847017 [CA 1] Center 36 (6~67) winsize 62
1432 09:25:19.847100 [CA 2] Center 34 (4~65) winsize 62
1433 09:25:19.847189 [CA 3] Center 34 (3~65) winsize 63
1434 09:25:19.847271 [CA 4] Center 34 (4~65) winsize 62
1435 09:25:19.847354 [CA 5] Center 34 (3~65) winsize 63
1436 09:25:19.847435
1437 09:25:19.847517 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1438 09:25:19.847614
1439 09:25:19.847696 [CATrainingPosCal] consider 2 rank data
1440 09:25:19.847790 u2DelayCellTimex100 = 270/100 ps
1441 09:25:19.847873 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1442 09:25:19.847963 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1443 09:25:19.848057 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1444 09:25:19.848140 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1445 09:25:19.848228 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1446 09:25:19.848310 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1447 09:25:19.848402
1448 09:25:19.848487 CA PerBit enable=1, Macro0, CA PI delay=34
1449 09:25:19.848575
1450 09:25:19.848873 [CBTSetCACLKResult] CA Dly = 34
1451 09:25:19.848981 CS Dly: 6 (0~38)
1452 09:25:19.849081
1453 09:25:19.849173 ----->DramcWriteLeveling(PI) begin...
1454 09:25:19.849242 ==
1455 09:25:19.849346 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 09:25:19.849438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 09:25:19.849494 ==
1458 09:25:19.849547 Write leveling (Byte 0): 26 => 26
1459 09:25:19.849607 Write leveling (Byte 1): 29 => 29
1460 09:25:19.849660 DramcWriteLeveling(PI) end<-----
1461 09:25:19.849712
1462 09:25:19.849764 ==
1463 09:25:19.849861 Dram Type= 6, Freq= 0, CH_1, rank 0
1464 09:25:19.849945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 09:25:19.850033 ==
1466 09:25:19.850116 [Gating] SW mode calibration
1467 09:25:19.850205 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1468 09:25:19.850261 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1469 09:25:19.850314 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1470 09:25:19.850373 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1471 09:25:19.850429 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 09:25:19.850482 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 09:25:19.850534 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 09:25:19.850586 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 09:25:19.850645 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 09:25:19.850699 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 09:25:19.850751 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 09:25:19.850808 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 09:25:19.850861 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 09:25:19.850913 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 09:25:19.850965 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 09:25:19.851024 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 09:25:19.851077 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 09:25:19.851128 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 09:25:19.851185 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1486 09:25:19.851240 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1487 09:25:19.851292 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 09:25:19.851344 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 09:25:19.851428 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 09:25:19.851484 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 09:25:19.851537 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 09:25:19.851615 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 09:25:19.851670 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 09:25:19.851722 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 09:25:19.851783 0 9 8 | B1->B0 | 2e2e 2d2d | 0 1 | (0 0) (1 1)
1496 09:25:19.851846 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 09:25:19.851901 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 09:25:19.851953 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 09:25:19.852005 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1500 09:25:19.852085 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1501 09:25:19.852145 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1502 09:25:19.852216 0 10 4 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 0)
1503 09:25:19.852277 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (1 1) (0 0)
1504 09:25:19.852330 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 09:25:19.852383 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 09:25:19.852460 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 09:25:19.852515 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 09:25:19.852567 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 09:25:19.852632 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 09:25:19.852687 0 11 4 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (0 0)
1511 09:25:19.852739 0 11 8 | B1->B0 | 3737 4343 | 0 1 | (0 0) (0 0)
1512 09:25:19.852800 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 09:25:19.852891 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 09:25:19.852974 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 09:25:19.853064 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 09:25:19.853146 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 09:25:19.853230 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1518 09:25:19.853286 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1519 09:25:19.853338 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 09:25:19.853391 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 09:25:19.853469 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 09:25:19.853526 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 09:25:19.853579 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 09:25:19.853644 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 09:25:19.853727 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 09:25:19.853810 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 09:25:19.853899 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 09:25:19.853981 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 09:25:19.854077 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 09:25:19.854179 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 09:25:19.854274 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 09:25:19.854330 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 09:25:19.854383 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 09:25:19.854444 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1535 09:25:19.854497 Total UI for P1: 0, mck2ui 16
1536 09:25:19.854551 best dqsien dly found for B0: ( 0, 14, 2)
1537 09:25:19.854613 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1538 09:25:19.854693 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 09:25:19.854960 Total UI for P1: 0, mck2ui 16
1540 09:25:19.855023 best dqsien dly found for B1: ( 0, 14, 8)
1541 09:25:19.855112 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1542 09:25:19.855196 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1543 09:25:19.855292
1544 09:25:19.855376 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1545 09:25:19.855467 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1546 09:25:19.855550 [Gating] SW calibration Done
1547 09:25:19.855644 ==
1548 09:25:19.855732 Dram Type= 6, Freq= 0, CH_1, rank 0
1549 09:25:19.855822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1550 09:25:19.855910 ==
1551 09:25:19.855991 RX Vref Scan: 0
1552 09:25:19.856087
1553 09:25:19.856184 RX Vref 0 -> 0, step: 1
1554 09:25:19.856277
1555 09:25:19.856370 RX Delay -130 -> 252, step: 16
1556 09:25:19.856465 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1557 09:25:19.856548 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1558 09:25:19.856638 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1559 09:25:19.856721 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1560 09:25:19.856817 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1561 09:25:19.856901 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1562 09:25:19.856992 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1563 09:25:19.857076 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1564 09:25:19.857170 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1565 09:25:19.857255 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1566 09:25:19.857341 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1567 09:25:19.857420 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1568 09:25:19.857475 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1569 09:25:19.857526 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1570 09:25:19.857585 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1571 09:25:19.857669 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1572 09:25:19.857751 ==
1573 09:25:19.857846 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 09:25:19.857928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 09:25:19.858016 ==
1576 09:25:19.858098 DQS Delay:
1577 09:25:19.858191 DQS0 = 0, DQS1 = 0
1578 09:25:19.858251 DQM Delay:
1579 09:25:19.858311 DQM0 = 89, DQM1 = 79
1580 09:25:19.858402 DQ Delay:
1581 09:25:19.858458 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1582 09:25:19.858510 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1583 09:25:19.858576 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1584 09:25:19.858629 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1585 09:25:19.858680
1586 09:25:19.858739
1587 09:25:19.858809 ==
1588 09:25:19.858894 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 09:25:19.858976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 09:25:19.859071 ==
1591 09:25:19.859153
1592 09:25:19.859241
1593 09:25:19.859323 TX Vref Scan disable
1594 09:25:19.859414 == TX Byte 0 ==
1595 09:25:19.859499 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1596 09:25:19.859587 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1597 09:25:19.859671 == TX Byte 1 ==
1598 09:25:19.859753 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1599 09:25:19.859861 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1600 09:25:19.859943 ==
1601 09:25:19.860042 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 09:25:19.860127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 09:25:19.860209 ==
1604 09:25:19.860298 TX Vref=22, minBit 10, minWin=26, winSum=440
1605 09:25:19.860381 TX Vref=24, minBit 8, minWin=27, winSum=446
1606 09:25:19.860476 TX Vref=26, minBit 8, minWin=27, winSum=449
1607 09:25:19.860560 TX Vref=28, minBit 8, minWin=27, winSum=451
1608 09:25:19.860656 TX Vref=30, minBit 9, minWin=27, winSum=451
1609 09:25:19.860740 TX Vref=32, minBit 9, minWin=27, winSum=447
1610 09:25:19.860828 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 28
1611 09:25:19.860911
1612 09:25:19.860998 Final TX Range 1 Vref 28
1613 09:25:19.861089
1614 09:25:19.861171 ==
1615 09:25:19.861233 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 09:25:19.861286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 09:25:19.861338 ==
1618 09:25:19.861413
1619 09:25:19.861472
1620 09:25:19.861524 TX Vref Scan disable
1621 09:25:19.861576 == TX Byte 0 ==
1622 09:25:19.861628 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1623 09:25:19.861718 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1624 09:25:19.861800 == TX Byte 1 ==
1625 09:25:19.861895 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1626 09:25:19.861979 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1627 09:25:19.862068
1628 09:25:19.862149 [DATLAT]
1629 09:25:19.862240 Freq=800, CH1 RK0
1630 09:25:19.862297
1631 09:25:19.862349 DATLAT Default: 0xa
1632 09:25:19.862405 0, 0xFFFF, sum = 0
1633 09:25:19.862470 1, 0xFFFF, sum = 0
1634 09:25:19.862524 2, 0xFFFF, sum = 0
1635 09:25:19.862577 3, 0xFFFF, sum = 0
1636 09:25:19.862674 4, 0xFFFF, sum = 0
1637 09:25:19.862758 5, 0xFFFF, sum = 0
1638 09:25:19.862848 6, 0xFFFF, sum = 0
1639 09:25:19.862945 7, 0xFFFF, sum = 0
1640 09:25:19.863040 8, 0xFFFF, sum = 0
1641 09:25:19.863131 9, 0x0, sum = 1
1642 09:25:19.863215 10, 0x0, sum = 2
1643 09:25:19.863312 11, 0x0, sum = 3
1644 09:25:19.863398 12, 0x0, sum = 4
1645 09:25:19.863488 best_step = 10
1646 09:25:19.863570
1647 09:25:19.863655 ==
1648 09:25:19.863747 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 09:25:19.863832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 09:25:19.863918 ==
1651 09:25:19.863999 RX Vref Scan: 1
1652 09:25:19.864094
1653 09:25:19.864182 Set Vref Range= 32 -> 127
1654 09:25:19.864264
1655 09:25:19.864352 RX Vref 32 -> 127, step: 1
1656 09:25:19.864434
1657 09:25:19.864523 RX Delay -95 -> 252, step: 8
1658 09:25:19.864609
1659 09:25:19.864699 Set Vref, RX VrefLevel [Byte0]: 32
1660 09:25:19.864786 [Byte1]: 32
1661 09:25:19.864867
1662 09:25:19.864954 Set Vref, RX VrefLevel [Byte0]: 33
1663 09:25:19.865036 [Byte1]: 33
1664 09:25:19.865132
1665 09:25:19.865215 Set Vref, RX VrefLevel [Byte0]: 34
1666 09:25:19.865297 [Byte1]: 34
1667 09:25:19.865352
1668 09:25:19.865403 Set Vref, RX VrefLevel [Byte0]: 35
1669 09:25:19.865462 [Byte1]: 35
1670 09:25:19.865535
1671 09:25:19.865617 Set Vref, RX VrefLevel [Byte0]: 36
1672 09:25:19.865700 [Byte1]: 36
1673 09:25:19.865795
1674 09:25:19.865877 Set Vref, RX VrefLevel [Byte0]: 37
1675 09:25:19.865975 [Byte1]: 37
1676 09:25:19.866058
1677 09:25:19.866152 Set Vref, RX VrefLevel [Byte0]: 38
1678 09:25:19.866222 [Byte1]: 38
1679 09:25:19.866277
1680 09:25:19.866357 Set Vref, RX VrefLevel [Byte0]: 39
1681 09:25:19.866411 [Byte1]: 39
1682 09:25:19.866463
1683 09:25:19.866564 Set Vref, RX VrefLevel [Byte0]: 40
1684 09:25:19.866648 [Byte1]: 40
1685 09:25:19.866740
1686 09:25:19.866822 Set Vref, RX VrefLevel [Byte0]: 41
1687 09:25:19.866912 [Byte1]: 41
1688 09:25:19.867000
1689 09:25:19.867097 Set Vref, RX VrefLevel [Byte0]: 42
1690 09:25:19.867182 [Byte1]: 42
1691 09:25:19.867274
1692 09:25:19.867359 Set Vref, RX VrefLevel [Byte0]: 43
1693 09:25:19.867666 [Byte1]: 43
1694 09:25:19.867755
1695 09:25:19.867845 Set Vref, RX VrefLevel [Byte0]: 44
1696 09:25:19.867929 [Byte1]: 44
1697 09:25:19.868015
1698 09:25:19.868109 Set Vref, RX VrefLevel [Byte0]: 45
1699 09:25:19.868194 [Byte1]: 45
1700 09:25:19.868279
1701 09:25:19.868360 Set Vref, RX VrefLevel [Byte0]: 46
1702 09:25:19.868456 [Byte1]: 46
1703 09:25:19.868543
1704 09:25:19.868626 Set Vref, RX VrefLevel [Byte0]: 47
1705 09:25:19.868714 [Byte1]: 47
1706 09:25:19.868796
1707 09:25:19.868885 Set Vref, RX VrefLevel [Byte0]: 48
1708 09:25:19.868973 [Byte1]: 48
1709 09:25:19.869058
1710 09:25:19.869150 Set Vref, RX VrefLevel [Byte0]: 49
1711 09:25:19.869233 [Byte1]: 49
1712 09:25:19.869297
1713 09:25:19.869349 Set Vref, RX VrefLevel [Byte0]: 50
1714 09:25:19.869401 [Byte1]: 50
1715 09:25:19.869467
1716 09:25:19.869562 Set Vref, RX VrefLevel [Byte0]: 51
1717 09:25:19.869658 [Byte1]: 51
1718 09:25:19.869747
1719 09:25:19.869830 Set Vref, RX VrefLevel [Byte0]: 52
1720 09:25:19.869920 [Byte1]: 52
1721 09:25:19.870005
1722 09:25:19.870088 Set Vref, RX VrefLevel [Byte0]: 53
1723 09:25:19.870202 [Byte1]: 53
1724 09:25:19.870259
1725 09:25:19.870326 Set Vref, RX VrefLevel [Byte0]: 54
1726 09:25:19.870379 [Byte1]: 54
1727 09:25:19.870431
1728 09:25:19.870503 Set Vref, RX VrefLevel [Byte0]: 55
1729 09:25:19.870563 [Byte1]: 55
1730 09:25:19.870617
1731 09:25:19.870681 Set Vref, RX VrefLevel [Byte0]: 56
1732 09:25:19.870736 [Byte1]: 56
1733 09:25:19.870788
1734 09:25:19.870839 Set Vref, RX VrefLevel [Byte0]: 57
1735 09:25:19.870933 [Byte1]: 57
1736 09:25:19.871015
1737 09:25:19.871099 Set Vref, RX VrefLevel [Byte0]: 58
1738 09:25:19.871186 [Byte1]: 58
1739 09:25:19.871267
1740 09:25:19.871363 Set Vref, RX VrefLevel [Byte0]: 59
1741 09:25:19.871445 [Byte1]: 59
1742 09:25:19.871532
1743 09:25:19.871614 Set Vref, RX VrefLevel [Byte0]: 60
1744 09:25:19.871708 [Byte1]: 60
1745 09:25:19.871791
1746 09:25:19.871877 Set Vref, RX VrefLevel [Byte0]: 61
1747 09:25:19.871964 [Byte1]: 61
1748 09:25:19.872045
1749 09:25:19.872139 Set Vref, RX VrefLevel [Byte0]: 62
1750 09:25:19.872222 [Byte1]: 62
1751 09:25:19.872310
1752 09:25:19.872403 Set Vref, RX VrefLevel [Byte0]: 63
1753 09:25:19.872486 [Byte1]: 63
1754 09:25:19.872573
1755 09:25:19.872654 Set Vref, RX VrefLevel [Byte0]: 64
1756 09:25:19.872748 [Byte1]: 64
1757 09:25:19.872832
1758 09:25:19.872918 Set Vref, RX VrefLevel [Byte0]: 65
1759 09:25:19.873006 [Byte1]: 65
1760 09:25:19.873088
1761 09:25:19.873181 Set Vref, RX VrefLevel [Byte0]: 66
1762 09:25:19.873277 [Byte1]: 66
1763 09:25:19.873344
1764 09:25:19.873397 Set Vref, RX VrefLevel [Byte0]: 67
1765 09:25:19.873449 [Byte1]: 67
1766 09:25:19.873529
1767 09:25:19.873612 Set Vref, RX VrefLevel [Byte0]: 68
1768 09:25:19.873700 [Byte1]: 68
1769 09:25:19.873793
1770 09:25:19.873877 Set Vref, RX VrefLevel [Byte0]: 69
1771 09:25:19.873961 [Byte1]: 69
1772 09:25:19.874046
1773 09:25:19.874128 Set Vref, RX VrefLevel [Byte0]: 70
1774 09:25:19.874217 [Byte1]: 70
1775 09:25:19.874271
1776 09:25:19.874322 Set Vref, RX VrefLevel [Byte0]: 71
1777 09:25:19.874386 [Byte1]: 71
1778 09:25:19.874438
1779 09:25:19.874490 Set Vref, RX VrefLevel [Byte0]: 72
1780 09:25:19.874553 [Byte1]: 72
1781 09:25:19.874620
1782 09:25:19.874673 Set Vref, RX VrefLevel [Byte0]: 73
1783 09:25:19.874732 [Byte1]: 73
1784 09:25:19.874786
1785 09:25:19.874837 Set Vref, RX VrefLevel [Byte0]: 74
1786 09:25:19.874889 [Byte1]: 74
1787 09:25:19.874968
1788 09:25:19.875058 Set Vref, RX VrefLevel [Byte0]: 75
1789 09:25:19.875140 [Byte1]: 75
1790 09:25:19.875235
1791 09:25:19.875318 Set Vref, RX VrefLevel [Byte0]: 76
1792 09:25:19.875408 [Byte1]: 76
1793 09:25:19.875490
1794 09:25:19.875577 Set Vref, RX VrefLevel [Byte0]: 77
1795 09:25:19.875665 [Byte1]: 77
1796 09:25:19.875747
1797 09:25:19.875835 Final RX Vref Byte 0 = 55 to rank0
1798 09:25:19.875918 Final RX Vref Byte 1 = 66 to rank0
1799 09:25:19.876014 Final RX Vref Byte 0 = 55 to rank1
1800 09:25:19.876097 Final RX Vref Byte 1 = 66 to rank1==
1801 09:25:19.876187 Dram Type= 6, Freq= 0, CH_1, rank 0
1802 09:25:19.876282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 09:25:19.876376 ==
1804 09:25:19.876464 DQS Delay:
1805 09:25:19.876548 DQS0 = 0, DQS1 = 0
1806 09:25:19.876637 DQM Delay:
1807 09:25:19.876719 DQM0 = 86, DQM1 = 78
1808 09:25:19.876812 DQ Delay:
1809 09:25:19.876896 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1810 09:25:19.876983 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1811 09:25:19.877066 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1812 09:25:19.877148 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1813 09:25:19.877229
1814 09:25:19.877284
1815 09:25:19.877340 [DQSOSCAuto] RK0, (LSB)MR18= 0x3520, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1816 09:25:19.877421 CH1 RK0: MR19=606, MR18=3520
1817 09:25:19.877475 CH1_RK0: MR19=0x606, MR18=0x3520, DQSOSC=396, MR23=63, INC=94, DEC=62
1818 09:25:19.877529
1819 09:25:19.877610 ----->DramcWriteLeveling(PI) begin...
1820 09:25:19.877694 ==
1821 09:25:19.877784 Dram Type= 6, Freq= 0, CH_1, rank 1
1822 09:25:19.877879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1823 09:25:19.877961 ==
1824 09:25:19.878051 Write leveling (Byte 0): 29 => 29
1825 09:25:19.878133 Write leveling (Byte 1): 29 => 29
1826 09:25:19.878235 DramcWriteLeveling(PI) end<-----
1827 09:25:19.878293
1828 09:25:19.878344 ==
1829 09:25:19.878407 Dram Type= 6, Freq= 0, CH_1, rank 1
1830 09:25:19.878461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 09:25:19.878518 ==
1832 09:25:19.878602 [Gating] SW mode calibration
1833 09:25:19.878688 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1834 09:25:19.878776 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1835 09:25:19.878865 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1836 09:25:19.878950 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1837 09:25:19.879043 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 09:25:19.879126 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 09:25:19.879217 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 09:25:19.879300 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 09:25:19.879607 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 09:25:19.879697 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 09:25:19.879796 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 09:25:19.879880 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 09:25:19.879969 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 09:25:19.880053 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 09:25:19.880150 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 09:25:19.880234 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 09:25:19.880325 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 09:25:19.880411 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 09:25:19.880500 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1852 09:25:19.880594 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1853 09:25:19.880676 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1854 09:25:19.880765 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 09:25:19.880854 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 09:25:19.880940 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 09:25:19.881024 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 09:25:19.881106 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 09:25:19.881201 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 09:25:19.881284 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 09:25:19.881370 0 9 8 | B1->B0 | 3030 2828 | 0 1 | (0 0) (0 0)
1862 09:25:19.881425 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 09:25:19.881477 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1864 09:25:19.881542 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1865 09:25:19.881625 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 09:25:19.881715 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 09:25:19.881804 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 09:25:19.881888 0 10 4 | B1->B0 | 3131 3434 | 0 1 | (0 1) (1 1)
1869 09:25:19.881969 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 0)
1870 09:25:19.882059 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 09:25:19.882142 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 09:25:19.882239 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 09:25:19.882294 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 09:25:19.882346 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 09:25:19.882415 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 09:25:19.882470 0 11 4 | B1->B0 | 2a2a 2525 | 0 0 | (0 0) (0 0)
1877 09:25:19.882526 0 11 8 | B1->B0 | 3d3d 3535 | 1 0 | (0 0) (1 1)
1878 09:25:19.882628 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 09:25:19.882721 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 09:25:19.882815 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 09:25:19.882898 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 09:25:19.882996 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 09:25:19.883080 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 09:25:19.883170 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1885 09:25:19.883267 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1886 09:25:19.883351 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 09:25:19.883439 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 09:25:19.883522 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 09:25:19.883612 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 09:25:19.883707 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 09:25:19.883795 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 09:25:19.883879 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 09:25:19.883961 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 09:25:19.884056 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 09:25:19.884139 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 09:25:19.884229 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 09:25:19.884311 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 09:25:19.884407 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 09:25:19.884491 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 09:25:19.884581 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1901 09:25:19.884676 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 09:25:19.884770 Total UI for P1: 0, mck2ui 16
1903 09:25:19.884870 best dqsien dly found for B0: ( 0, 14, 6)
1904 09:25:19.884954 Total UI for P1: 0, mck2ui 16
1905 09:25:19.885043 best dqsien dly found for B1: ( 0, 14, 4)
1906 09:25:19.885125 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1907 09:25:19.885217 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1908 09:25:19.885274
1909 09:25:19.885326 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1910 09:25:19.885384 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1911 09:25:19.885454 [Gating] SW calibration Done
1912 09:25:19.885507 ==
1913 09:25:19.885560 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 09:25:19.885646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 09:25:19.885729 ==
1916 09:25:19.885826 RX Vref Scan: 0
1917 09:25:19.885908
1918 09:25:19.885997 RX Vref 0 -> 0, step: 1
1919 09:25:19.886090
1920 09:25:19.886210 RX Delay -130 -> 252, step: 16
1921 09:25:20.036389 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1922 09:25:20.036563 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1923 09:25:20.036662 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1924 09:25:20.036755 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1925 09:25:20.036843 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1926 09:25:20.036910 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1927 09:25:20.036966 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1928 09:25:20.037022 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1929 09:25:20.037098 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1930 09:25:20.037182 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1931 09:25:20.037482 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1932 09:25:20.037578 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1933 09:25:20.037673 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1934 09:25:20.037781 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1935 09:25:20.037888 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1936 09:25:20.037986 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1937 09:25:20.038072 ==
1938 09:25:20.038173 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 09:25:20.038263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 09:25:20.038350 ==
1941 09:25:20.038432 DQS Delay:
1942 09:25:20.038502 DQS0 = 0, DQS1 = 0
1943 09:25:20.038557 DQM Delay:
1944 09:25:20.038610 DQM0 = 86, DQM1 = 78
1945 09:25:20.038670 DQ Delay:
1946 09:25:20.038754 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1947 09:25:20.038838 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1948 09:25:20.038921 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1949 09:25:20.039005 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1950 09:25:20.039086
1951 09:25:20.039171
1952 09:25:20.039252 ==
1953 09:25:20.039342 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 09:25:20.039426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 09:25:20.039514 ==
1956 09:25:20.039597
1957 09:25:20.039678
1958 09:25:20.039746 TX Vref Scan disable
1959 09:25:20.039800 == TX Byte 0 ==
1960 09:25:20.039852 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1961 09:25:20.039919 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1962 09:25:20.040001 == TX Byte 1 ==
1963 09:25:20.040087 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1964 09:25:20.040172 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1965 09:25:20.040254 ==
1966 09:25:20.040338 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 09:25:20.040422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 09:25:20.040503 ==
1969 09:25:20.040590 TX Vref=22, minBit 8, minWin=27, winSum=449
1970 09:25:20.040660 TX Vref=24, minBit 8, minWin=27, winSum=449
1971 09:25:20.040715 TX Vref=26, minBit 8, minWin=27, winSum=450
1972 09:25:20.040775 TX Vref=28, minBit 8, minWin=27, winSum=451
1973 09:25:20.040828 TX Vref=30, minBit 8, minWin=27, winSum=453
1974 09:25:20.040885 TX Vref=32, minBit 8, minWin=27, winSum=452
1975 09:25:20.040959 [TxChooseVref] Worse bit 8, Min win 27, Win sum 453, Final Vref 30
1976 09:25:20.041013
1977 09:25:20.041065 Final TX Range 1 Vref 30
1978 09:25:20.041126
1979 09:25:20.041179 ==
1980 09:25:20.041231 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 09:25:20.041283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 09:25:20.041363 ==
1983 09:25:20.041466
1984 09:25:20.041555
1985 09:25:20.041638 TX Vref Scan disable
1986 09:25:20.041719 == TX Byte 0 ==
1987 09:25:20.041805 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1988 09:25:20.041887 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1989 09:25:20.041973 == TX Byte 1 ==
1990 09:25:20.042055 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1991 09:25:20.042139 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1992 09:25:20.042232
1993 09:25:20.042314 [DATLAT]
1994 09:25:20.042401 Freq=800, CH1 RK1
1995 09:25:20.042483
1996 09:25:20.042568 DATLAT Default: 0xa
1997 09:25:20.042651 0, 0xFFFF, sum = 0
1998 09:25:20.042739 1, 0xFFFF, sum = 0
1999 09:25:20.042825 2, 0xFFFF, sum = 0
2000 09:25:20.042909 3, 0xFFFF, sum = 0
2001 09:25:20.042996 4, 0xFFFF, sum = 0
2002 09:25:20.043081 5, 0xFFFF, sum = 0
2003 09:25:20.043167 6, 0xFFFF, sum = 0
2004 09:25:20.043252 7, 0xFFFF, sum = 0
2005 09:25:20.043336 8, 0xFFFF, sum = 0
2006 09:25:20.043423 9, 0x0, sum = 1
2007 09:25:20.043507 10, 0x0, sum = 2
2008 09:25:20.043595 11, 0x0, sum = 3
2009 09:25:20.043679 12, 0x0, sum = 4
2010 09:25:20.043762 best_step = 10
2011 09:25:20.043817
2012 09:25:20.043870 ==
2013 09:25:20.043927 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 09:25:20.044013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 09:25:20.044095 ==
2016 09:25:20.044183 RX Vref Scan: 0
2017 09:25:20.044266
2018 09:25:20.044368 RX Vref 0 -> 0, step: 1
2019 09:25:20.044452
2020 09:25:20.044539 RX Delay -95 -> 252, step: 8
2021 09:25:20.044624 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2022 09:25:20.044866 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2023 09:25:20.044968 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2024 09:25:20.045062 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2025 09:25:20.045147 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2026 09:25:20.045241 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2027 09:25:20.045332 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2028 09:25:20.045422 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2029 09:25:20.045480 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2030 09:25:20.045533 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2031 09:25:20.045586 iDelay=217, Bit 10, Center 80 (-31 ~ 192) 224
2032 09:25:20.045646 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2033 09:25:20.045706 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2034 09:25:20.045759 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2035 09:25:20.045812 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
2036 09:25:20.045874 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2037 09:25:20.045930 ==
2038 09:25:20.045984 Dram Type= 6, Freq= 0, CH_1, rank 1
2039 09:25:20.046036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2040 09:25:20.046095 ==
2041 09:25:20.046148 DQS Delay:
2042 09:25:20.046216 DQS0 = 0, DQS1 = 0
2043 09:25:20.046276 DQM Delay:
2044 09:25:20.046330 DQM0 = 87, DQM1 = 79
2045 09:25:20.046382 DQ Delay:
2046 09:25:20.046434 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2047 09:25:20.046495 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2048 09:25:20.046548 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2049 09:25:20.046600 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
2050 09:25:20.046662
2051 09:25:20.046716
2052 09:25:20.046768 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2053 09:25:20.046822 CH1 RK1: MR19=606, MR18=1B13
2054 09:25:20.046886 CH1_RK1: MR19=0x606, MR18=0x1B13, DQSOSC=403, MR23=63, INC=90, DEC=60
2055 09:25:20.046961 [RxdqsGatingPostProcess] freq 800
2056 09:25:20.047017 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2057 09:25:20.047079 Pre-setting of DQS Precalculation
2058 09:25:20.047134 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2059 09:25:20.047187 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2060 09:25:20.047241 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2061 09:25:20.047300
2062 09:25:20.047353
2063 09:25:20.047405 [Calibration Summary] 1600 Mbps
2064 09:25:20.047457 CH 0, Rank 0
2065 09:25:20.047516 SW Impedance : PASS
2066 09:25:20.047569 DUTY Scan : NO K
2067 09:25:20.047621 ZQ Calibration : PASS
2068 09:25:20.047679 Jitter Meter : NO K
2069 09:25:20.047732 CBT Training : PASS
2070 09:25:20.047794 Write leveling : PASS
2071 09:25:20.048075 RX DQS gating : PASS
2072 09:25:20.048136 RX DQ/DQS(RDDQC) : PASS
2073 09:25:20.048190 TX DQ/DQS : PASS
2074 09:25:20.048250 RX DATLAT : PASS
2075 09:25:20.048304 RX DQ/DQS(Engine): PASS
2076 09:25:20.048356 TX OE : NO K
2077 09:25:20.048409 All Pass.
2078 09:25:20.048470
2079 09:25:20.048529 CH 0, Rank 1
2080 09:25:20.048583 SW Impedance : PASS
2081 09:25:20.048635 DUTY Scan : NO K
2082 09:25:20.048687 ZQ Calibration : PASS
2083 09:25:20.048751 Jitter Meter : NO K
2084 09:25:20.048807 CBT Training : PASS
2085 09:25:20.048897 Write leveling : PASS
2086 09:25:20.048992 RX DQS gating : PASS
2087 09:25:20.049075 RX DQ/DQS(RDDQC) : PASS
2088 09:25:20.049165 TX DQ/DQS : PASS
2089 09:25:20.049248 RX DATLAT : PASS
2090 09:25:20.049345 RX DQ/DQS(Engine): PASS
2091 09:25:20.049427 TX OE : NO K
2092 09:25:20.049517 All Pass.
2093 09:25:20.049599
2094 09:25:20.049688 CH 1, Rank 0
2095 09:25:20.049772 SW Impedance : PASS
2096 09:25:20.049854 DUTY Scan : NO K
2097 09:25:20.049941 ZQ Calibration : PASS
2098 09:25:20.050024 Jitter Meter : NO K
2099 09:25:20.050108 CBT Training : PASS
2100 09:25:20.050198 Write leveling : PASS
2101 09:25:20.050252 RX DQS gating : PASS
2102 09:25:20.050315 RX DQ/DQS(RDDQC) : PASS
2103 09:25:20.050369 TX DQ/DQS : PASS
2104 09:25:20.050422 RX DATLAT : PASS
2105 09:25:20.050474 RX DQ/DQS(Engine): PASS
2106 09:25:20.050538 TX OE : NO K
2107 09:25:20.050591 All Pass.
2108 09:25:20.050643
2109 09:25:20.050702 CH 1, Rank 1
2110 09:25:20.050756 SW Impedance : PASS
2111 09:25:20.050808 DUTY Scan : NO K
2112 09:25:20.050860 ZQ Calibration : PASS
2113 09:25:20.050926 Jitter Meter : NO K
2114 09:25:20.050981 CBT Training : PASS
2115 09:25:20.051039 Write leveling : PASS
2116 09:25:20.051093 RX DQS gating : PASS
2117 09:25:20.051146 RX DQ/DQS(RDDQC) : PASS
2118 09:25:20.051205 TX DQ/DQS : PASS
2119 09:25:20.051258 RX DATLAT : PASS
2120 09:25:20.051310 RX DQ/DQS(Engine): PASS
2121 09:25:20.051368 TX OE : NO K
2122 09:25:20.051421 All Pass.
2123 09:25:20.051473
2124 09:25:20.051524 DramC Write-DBI off
2125 09:25:20.051584 PER_BANK_REFRESH: Hybrid Mode
2126 09:25:20.051637 TX_TRACKING: ON
2127 09:25:20.051689 [GetDramInforAfterCalByMRR] Vendor 6.
2128 09:25:20.051748 [GetDramInforAfterCalByMRR] Revision 606.
2129 09:25:20.051801 [GetDramInforAfterCalByMRR] Revision 2 0.
2130 09:25:20.051854 MR0 0x3b3b
2131 09:25:20.051905 MR8 0x5151
2132 09:25:20.051969 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2133 09:25:20.052022
2134 09:25:20.052074 MR0 0x3b3b
2135 09:25:20.052134 MR8 0x5151
2136 09:25:20.052187 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2137 09:25:20.052239
2138 09:25:20.052291 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2139 09:25:20.052351 [FAST_K] Save calibration result to emmc
2140 09:25:20.052415 [FAST_K] Save calibration result to emmc
2141 09:25:20.052468 dram_init: config_dvfs: 1
2142 09:25:20.052520 dramc_set_vcore_voltage set vcore to 662500
2143 09:25:20.052578 Read voltage for 1200, 2
2144 09:25:20.052631 Vio18 = 0
2145 09:25:20.052683 Vcore = 662500
2146 09:25:20.052735 Vdram = 0
2147 09:25:20.052795 Vddq = 0
2148 09:25:20.052848 Vmddr = 0
2149 09:25:20.052908 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2150 09:25:20.052999 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2151 09:25:20.053089 MEM_TYPE=3, freq_sel=15
2152 09:25:20.053186 sv_algorithm_assistance_LP4_1600
2153 09:25:20.053270 ============ PULL DRAM RESETB DOWN ============
2154 09:25:20.053363 ========== PULL DRAM RESETB DOWN end =========
2155 09:25:20.053448 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2156 09:25:20.053544 ===================================
2157 09:25:20.053629 LPDDR4 DRAM CONFIGURATION
2158 09:25:20.053718 ===================================
2159 09:25:20.053804 EX_ROW_EN[0] = 0x0
2160 09:25:20.053886 EX_ROW_EN[1] = 0x0
2161 09:25:20.053974 LP4Y_EN = 0x0
2162 09:25:20.054057 WORK_FSP = 0x0
2163 09:25:20.054139 WL = 0x4
2164 09:25:20.054239 RL = 0x4
2165 09:25:20.054322 BL = 0x2
2166 09:25:20.054415 RPST = 0x0
2167 09:25:20.054479 RD_PRE = 0x0
2168 09:25:20.054532 WR_PRE = 0x1
2169 09:25:20.054593 WR_PST = 0x0
2170 09:25:20.054645 DBI_WR = 0x0
2171 09:25:20.054698 DBI_RD = 0x0
2172 09:25:20.054759 OTF = 0x1
2173 09:25:20.054813 ===================================
2174 09:25:20.054866 ===================================
2175 09:25:20.054925 ANA top config
2176 09:25:20.054989 ===================================
2177 09:25:20.055042 DLL_ASYNC_EN = 0
2178 09:25:20.055094 ALL_SLAVE_EN = 0
2179 09:25:20.055155 NEW_RANK_MODE = 1
2180 09:25:20.055215 DLL_IDLE_MODE = 1
2181 09:25:20.055268 LP45_APHY_COMB_EN = 1
2182 09:25:20.055320 TX_ODT_DIS = 1
2183 09:25:20.055372 NEW_8X_MODE = 1
2184 09:25:20.055437 ===================================
2185 09:25:20.055489 ===================================
2186 09:25:20.055541 data_rate = 2400
2187 09:25:20.055600 CKR = 1
2188 09:25:20.055654 DQ_P2S_RATIO = 8
2189 09:25:20.055707 ===================================
2190 09:25:20.055758 CA_P2S_RATIO = 8
2191 09:25:20.055818 DQ_CA_OPEN = 0
2192 09:25:20.055871 DQ_SEMI_OPEN = 0
2193 09:25:20.055922 CA_SEMI_OPEN = 0
2194 09:25:20.055986 CA_FULL_RATE = 0
2195 09:25:20.056040 DQ_CKDIV4_EN = 0
2196 09:25:20.056092 CA_CKDIV4_EN = 0
2197 09:25:20.056144 CA_PREDIV_EN = 0
2198 09:25:20.056203 PH8_DLY = 17
2199 09:25:20.056256 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2200 09:25:20.056307 DQ_AAMCK_DIV = 4
2201 09:25:20.056366 CA_AAMCK_DIV = 4
2202 09:25:20.056421 CA_ADMCK_DIV = 4
2203 09:25:20.056473 DQ_TRACK_CA_EN = 0
2204 09:25:20.056524 CA_PICK = 1200
2205 09:25:20.056577 CA_MCKIO = 1200
2206 09:25:20.056636 MCKIO_SEMI = 0
2207 09:25:20.056688 PLL_FREQ = 2366
2208 09:25:20.056740 DQ_UI_PI_RATIO = 32
2209 09:25:20.056792 CA_UI_PI_RATIO = 0
2210 09:25:20.056850 ===================================
2211 09:25:20.056911 ===================================
2212 09:25:20.056973 memory_type:LPDDR4
2213 09:25:20.057038 GP_NUM : 10
2214 09:25:20.057091 SRAM_EN : 1
2215 09:25:20.057143 MD32_EN : 0
2216 09:25:20.057203 ===================================
2217 09:25:20.057256 [ANA_INIT] >>>>>>>>>>>>>>
2218 09:25:20.057308 <<<<<< [CONFIGURE PHASE]: ANA_TX
2219 09:25:20.057361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2220 09:25:20.057427 ===================================
2221 09:25:20.057699 data_rate = 2400,PCW = 0X5b00
2222 09:25:20.057766 ===================================
2223 09:25:20.057832 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2224 09:25:20.057888 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2225 09:25:20.057942 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2226 09:25:20.057995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2227 09:25:20.058055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2228 09:25:20.058108 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2229 09:25:20.058172 [ANA_INIT] flow start
2230 09:25:20.058268 [ANA_INIT] PLL >>>>>>>>
2231 09:25:20.058359 [ANA_INIT] PLL <<<<<<<<
2232 09:25:20.058455 [ANA_INIT] MIDPI >>>>>>>>
2233 09:25:20.058544 [ANA_INIT] MIDPI <<<<<<<<
2234 09:25:20.058647 [ANA_INIT] DLL >>>>>>>>
2235 09:25:20.058734 [ANA_INIT] DLL <<<<<<<<
2236 09:25:20.058843 [ANA_INIT] flow end
2237 09:25:20.058939 ============ LP4 DIFF to SE enter ============
2238 09:25:20.059054 ============ LP4 DIFF to SE exit ============
2239 09:25:20.059151 [ANA_INIT] <<<<<<<<<<<<<
2240 09:25:20.059256 [Flow] Enable top DCM control >>>>>
2241 09:25:20.059351 [Flow] Enable top DCM control <<<<<
2242 09:25:20.059455 Enable DLL master slave shuffle
2243 09:25:20.059550 ==============================================================
2244 09:25:20.059653 Gating Mode config
2245 09:25:20.059748 ==============================================================
2246 09:25:20.059852 Config description:
2247 09:25:20.059947 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2248 09:25:20.060051 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2249 09:25:20.060147 SELPH_MODE 0: By rank 1: By Phase
2250 09:25:20.060259 ==============================================================
2251 09:25:20.060353 GAT_TRACK_EN = 1
2252 09:25:20.060455 RX_GATING_MODE = 2
2253 09:25:20.060550 RX_GATING_TRACK_MODE = 2
2254 09:25:20.060654 SELPH_MODE = 1
2255 09:25:20.060751 PICG_EARLY_EN = 1
2256 09:25:20.060854 VALID_LAT_VALUE = 1
2257 09:25:20.060948 ==============================================================
2258 09:25:20.061051 Enter into Gating configuration >>>>
2259 09:25:20.061145 Exit from Gating configuration <<<<
2260 09:25:20.061245 Enter into DVFS_PRE_config >>>>>
2261 09:25:20.061338 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2262 09:25:20.061445 Exit from DVFS_PRE_config <<<<<
2263 09:25:20.061537 Enter into PICG configuration >>>>
2264 09:25:20.061634 Exit from PICG configuration <<<<
2265 09:25:20.061723 [RX_INPUT] configuration >>>>>
2266 09:25:20.061824 [RX_INPUT] configuration <<<<<
2267 09:25:20.061921 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2268 09:25:20.062016 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2269 09:25:20.062117 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2270 09:25:20.062220 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2271 09:25:20.062321 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2272 09:25:20.062416 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2273 09:25:20.062517 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2274 09:25:20.062611 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2275 09:25:20.062713 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2276 09:25:20.062809 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2277 09:25:20.062913 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2278 09:25:20.063008 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 09:25:20.063110 ===================================
2280 09:25:20.063199 LPDDR4 DRAM CONFIGURATION
2281 09:25:20.063303 ===================================
2282 09:25:20.063391 EX_ROW_EN[0] = 0x0
2283 09:25:20.063450 EX_ROW_EN[1] = 0x0
2284 09:25:20.063513 LP4Y_EN = 0x0
2285 09:25:20.063568 WORK_FSP = 0x0
2286 09:25:20.063622 WL = 0x4
2287 09:25:20.063674 RL = 0x4
2288 09:25:20.063735 BL = 0x2
2289 09:25:20.063788 RPST = 0x0
2290 09:25:20.063840 RD_PRE = 0x0
2291 09:25:20.063895 WR_PRE = 0x1
2292 09:25:20.063946 WR_PST = 0x0
2293 09:25:20.063998 DBI_WR = 0x0
2294 09:25:20.064049 DBI_RD = 0x0
2295 09:25:20.064118 OTF = 0x1
2296 09:25:20.064172 ===================================
2297 09:25:20.064224 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2298 09:25:20.064288 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2299 09:25:20.064342 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2300 09:25:20.064394 ===================================
2301 09:25:20.064446 LPDDR4 DRAM CONFIGURATION
2302 09:25:20.064519 ===================================
2303 09:25:20.064581 EX_ROW_EN[0] = 0x10
2304 09:25:20.064642 EX_ROW_EN[1] = 0x0
2305 09:25:20.064696 LP4Y_EN = 0x0
2306 09:25:20.064750 WORK_FSP = 0x0
2307 09:25:20.064801 WL = 0x4
2308 09:25:20.064853 RL = 0x4
2309 09:25:20.064912 BL = 0x2
2310 09:25:20.064965 RPST = 0x0
2311 09:25:20.065017 RD_PRE = 0x0
2312 09:25:20.065068 WR_PRE = 0x1
2313 09:25:20.065127 WR_PST = 0x0
2314 09:25:20.065178 DBI_WR = 0x0
2315 09:25:20.065230 DBI_RD = 0x0
2316 09:25:20.065281 OTF = 0x1
2317 09:25:20.065346 ===================================
2318 09:25:20.065398 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2319 09:25:20.065450 ==
2320 09:25:20.065509 Dram Type= 6, Freq= 0, CH_0, rank 0
2321 09:25:20.065561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2322 09:25:20.065613 ==
2323 09:25:20.065664 [Duty_Offset_Calibration]
2324 09:25:20.065730 B0:1 B1:-1 CA:0
2325 09:25:20.065782
2326 09:25:20.065833 [DutyScan_Calibration_Flow] k_type=0
2327 09:25:20.065891
2328 09:25:20.065944 ==CLK 0==
2329 09:25:20.065996 Final CLK duty delay cell = 0
2330 09:25:20.066048 [0] MAX Duty = 5094%(X100), DQS PI = 16
2331 09:25:20.066118 [0] MIN Duty = 4875%(X100), DQS PI = 8
2332 09:25:20.066184 [0] AVG Duty = 4984%(X100)
2333 09:25:20.066243
2334 09:25:20.066513 CH0 CLK Duty spec in!! Max-Min= 219%
2335 09:25:20.066586 [DutyScan_Calibration_Flow] ====Done====
2336 09:25:20.066675
2337 09:25:20.066755 [DutyScan_Calibration_Flow] k_type=1
2338 09:25:20.066810
2339 09:25:20.066862 ==DQS 0 ==
2340 09:25:20.066929 Final DQS duty delay cell = -4
2341 09:25:20.066983 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2342 09:25:20.067035 [-4] MIN Duty = 4875%(X100), DQS PI = 46
2343 09:25:20.067093 [-4] AVG Duty = 4968%(X100)
2344 09:25:20.067147
2345 09:25:20.067198 ==DQS 1 ==
2346 09:25:20.067251 Final DQS duty delay cell = 0
2347 09:25:20.067310 [0] MAX Duty = 5124%(X100), DQS PI = 4
2348 09:25:20.067375 [0] MIN Duty = 5000%(X100), DQS PI = 22
2349 09:25:20.067437 [0] AVG Duty = 5062%(X100)
2350 09:25:20.067490
2351 09:25:20.067548 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2352 09:25:20.067601
2353 09:25:20.067652 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2354 09:25:20.067703 [DutyScan_Calibration_Flow] ====Done====
2355 09:25:20.067761
2356 09:25:20.067813 [DutyScan_Calibration_Flow] k_type=3
2357 09:25:20.067865
2358 09:25:20.067922 ==DQM 0 ==
2359 09:25:20.067975 Final DQM duty delay cell = 0
2360 09:25:20.068027 [0] MAX Duty = 5062%(X100), DQS PI = 20
2361 09:25:20.068079 [0] MIN Duty = 4875%(X100), DQS PI = 6
2362 09:25:20.068138 [0] AVG Duty = 4968%(X100)
2363 09:25:20.068189
2364 09:25:20.068240 ==DQM 1 ==
2365 09:25:20.068290 Final DQM duty delay cell = 4
2366 09:25:20.068353 [4] MAX Duty = 5187%(X100), DQS PI = 32
2367 09:25:20.068405 [4] MIN Duty = 4969%(X100), DQS PI = 26
2368 09:25:20.068456 [4] AVG Duty = 5078%(X100)
2369 09:25:20.068522
2370 09:25:20.068574 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2371 09:25:20.068626
2372 09:25:20.068677 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2373 09:25:20.068735 [DutyScan_Calibration_Flow] ====Done====
2374 09:25:20.068798
2375 09:25:20.068849 [DutyScan_Calibration_Flow] k_type=2
2376 09:25:20.068900
2377 09:25:20.068956 ==DQ 0 ==
2378 09:25:20.069009 Final DQ duty delay cell = -4
2379 09:25:20.069062 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2380 09:25:20.069114 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2381 09:25:20.069176 [-4] AVG Duty = 4969%(X100)
2382 09:25:20.069228
2383 09:25:20.069279 ==DQ 1 ==
2384 09:25:20.069338 Final DQ duty delay cell = -4
2385 09:25:20.069391 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2386 09:25:20.069443 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2387 09:25:20.069494 [-4] AVG Duty = 4922%(X100)
2388 09:25:20.069552
2389 09:25:20.069603 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2390 09:25:20.069655
2391 09:25:20.069705 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2392 09:25:20.069767 [DutyScan_Calibration_Flow] ====Done====
2393 09:25:20.069819 ==
2394 09:25:20.069870 Dram Type= 6, Freq= 0, CH_1, rank 0
2395 09:25:20.069937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2396 09:25:20.069991 ==
2397 09:25:20.070041 [Duty_Offset_Calibration]
2398 09:25:20.070099 B0:-1 B1:1 CA:2
2399 09:25:20.070152
2400 09:25:20.070221 [DutyScan_Calibration_Flow] k_type=0
2401 09:25:20.070273
2402 09:25:20.070324 ==CLK 0==
2403 09:25:20.070384 Final CLK duty delay cell = 0
2404 09:25:20.070436 [0] MAX Duty = 5156%(X100), DQS PI = 22
2405 09:25:20.070487 [0] MIN Duty = 5000%(X100), DQS PI = 0
2406 09:25:20.070544 [0] AVG Duty = 5078%(X100)
2407 09:25:20.070597
2408 09:25:20.070648 CH1 CLK Duty spec in!! Max-Min= 156%
2409 09:25:20.070700 [DutyScan_Calibration_Flow] ====Done====
2410 09:25:20.070758
2411 09:25:20.070810 [DutyScan_Calibration_Flow] k_type=1
2412 09:25:20.070862
2413 09:25:20.070914 ==DQS 0 ==
2414 09:25:20.070981 Final DQS duty delay cell = 0
2415 09:25:20.071035 [0] MAX Duty = 5125%(X100), DQS PI = 48
2416 09:25:20.071087 [0] MIN Duty = 4875%(X100), DQS PI = 6
2417 09:25:20.071158 [0] AVG Duty = 5000%(X100)
2418 09:25:20.071212
2419 09:25:20.071263 ==DQS 1 ==
2420 09:25:20.071321 Final DQS duty delay cell = 0
2421 09:25:20.071374 [0] MAX Duty = 5094%(X100), DQS PI = 12
2422 09:25:20.071427 [0] MIN Duty = 4969%(X100), DQS PI = 54
2423 09:25:20.071479 [0] AVG Duty = 5031%(X100)
2424 09:25:20.071538
2425 09:25:20.071596 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2426 09:25:20.071648
2427 09:25:20.071699 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2428 09:25:20.071750 [DutyScan_Calibration_Flow] ====Done====
2429 09:25:20.071814
2430 09:25:20.071865 [DutyScan_Calibration_Flow] k_type=3
2431 09:25:20.071917
2432 09:25:20.071975 ==DQM 0 ==
2433 09:25:20.072028 Final DQM duty delay cell = -4
2434 09:25:20.072080 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2435 09:25:20.072131 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2436 09:25:20.072191 [-4] AVG Duty = 4937%(X100)
2437 09:25:20.072243
2438 09:25:20.072293 ==DQM 1 ==
2439 09:25:20.072358 Final DQM duty delay cell = 0
2440 09:25:20.072411 [0] MAX Duty = 5156%(X100), DQS PI = 4
2441 09:25:20.072463 [0] MIN Duty = 4969%(X100), DQS PI = 28
2442 09:25:20.072514 [0] AVG Duty = 5062%(X100)
2443 09:25:20.072579
2444 09:25:20.072631 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2445 09:25:20.072683
2446 09:25:20.072741 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2447 09:25:20.072808 [DutyScan_Calibration_Flow] ====Done====
2448 09:25:20.072861
2449 09:25:20.072912 [DutyScan_Calibration_Flow] k_type=2
2450 09:25:20.072963
2451 09:25:20.073031 ==DQ 0 ==
2452 09:25:20.073083 Final DQ duty delay cell = 0
2453 09:25:20.073135 [0] MAX Duty = 5156%(X100), DQS PI = 28
2454 09:25:20.073201 [0] MIN Duty = 4876%(X100), DQS PI = 8
2455 09:25:20.073253 [0] AVG Duty = 5016%(X100)
2456 09:25:20.073305
2457 09:25:20.073362 ==DQ 1 ==
2458 09:25:20.073416 Final DQ duty delay cell = 0
2459 09:25:20.073468 [0] MAX Duty = 5124%(X100), DQS PI = 10
2460 09:25:20.073519 [0] MIN Duty = 4938%(X100), DQS PI = 62
2461 09:25:20.073572 [0] AVG Duty = 5031%(X100)
2462 09:25:20.073624
2463 09:25:20.073675 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2464 09:25:20.073728
2465 09:25:20.073803 CH1 DQ 1 Duty spec in!! Max-Min= 186%
2466 09:25:20.073856 [DutyScan_Calibration_Flow] ====Done====
2467 09:25:20.073908 nWR fixed to 30
2468 09:25:20.073969 [ModeRegInit_LP4] CH0 RK0
2469 09:25:20.074022 [ModeRegInit_LP4] CH0 RK1
2470 09:25:20.074107 [ModeRegInit_LP4] CH1 RK0
2471 09:25:20.074207 [ModeRegInit_LP4] CH1 RK1
2472 09:25:20.074261 match AC timing 7
2473 09:25:20.074321 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2474 09:25:20.074375 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2475 09:25:20.074427 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2476 09:25:20.074480 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2477 09:25:20.074540 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2478 09:25:20.074592 ==
2479 09:25:20.074644 Dram Type= 6, Freq= 0, CH_0, rank 0
2480 09:25:20.074702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2481 09:25:20.074755 ==
2482 09:25:20.074807 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2483 09:25:20.074858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2484 09:25:20.074918 [CA 0] Center 39 (9~70) winsize 62
2485 09:25:20.074971 [CA 1] Center 39 (9~69) winsize 61
2486 09:25:20.075023 [CA 2] Center 35 (5~66) winsize 62
2487 09:25:20.075080 [CA 3] Center 35 (5~66) winsize 62
2488 09:25:20.075341 [CA 4] Center 33 (4~63) winsize 60
2489 09:25:20.075400 [CA 5] Center 33 (3~63) winsize 61
2490 09:25:20.075453
2491 09:25:20.075514 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2492 09:25:20.075567
2493 09:25:20.075618 [CATrainingPosCal] consider 1 rank data
2494 09:25:20.075693 u2DelayCellTimex100 = 270/100 ps
2495 09:25:20.075759 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2496 09:25:20.075812 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2497 09:25:20.075864 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2498 09:25:20.075917 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2499 09:25:20.075968 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2500 09:25:20.076028 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2501 09:25:20.076080
2502 09:25:20.076131 CA PerBit enable=1, Macro0, CA PI delay=33
2503 09:25:20.076191
2504 09:25:20.076244 [CBTSetCACLKResult] CA Dly = 33
2505 09:25:20.076296 CS Dly: 8 (0~39)
2506 09:25:20.076347 ==
2507 09:25:20.076406 Dram Type= 6, Freq= 0, CH_0, rank 1
2508 09:25:20.076458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 09:25:20.076510 ==
2510 09:25:20.076577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2511 09:25:20.076631 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2512 09:25:20.076683 [CA 0] Center 39 (9~70) winsize 62
2513 09:25:20.076735 [CA 1] Center 39 (9~70) winsize 62
2514 09:25:20.076794 [CA 2] Center 35 (5~66) winsize 62
2515 09:25:20.076846 [CA 3] Center 34 (4~65) winsize 62
2516 09:25:20.076897 [CA 4] Center 33 (3~64) winsize 62
2517 09:25:20.076956 [CA 5] Center 33 (3~63) winsize 61
2518 09:25:20.077010
2519 09:25:20.077061 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2520 09:25:20.077112
2521 09:25:20.077162 [CATrainingPosCal] consider 2 rank data
2522 09:25:20.077221 u2DelayCellTimex100 = 270/100 ps
2523 09:25:20.077273 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2524 09:25:20.077325 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2525 09:25:20.077376 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2526 09:25:20.077435 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2527 09:25:20.077487 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2528 09:25:20.077538 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2529 09:25:20.077596
2530 09:25:20.077648 CA PerBit enable=1, Macro0, CA PI delay=33
2531 09:25:20.077710
2532 09:25:20.077762 [CBTSetCACLKResult] CA Dly = 33
2533 09:25:20.077821 CS Dly: 8 (0~40)
2534 09:25:20.077873
2535 09:25:20.077924 ----->DramcWriteLeveling(PI) begin...
2536 09:25:20.077989 ==
2537 09:25:20.078043 Dram Type= 6, Freq= 0, CH_0, rank 0
2538 09:25:20.078095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2539 09:25:20.078147 ==
2540 09:25:20.078220 Write leveling (Byte 0): 33 => 33
2541 09:25:20.078272 Write leveling (Byte 1): 28 => 28
2542 09:25:20.078324 DramcWriteLeveling(PI) end<-----
2543 09:25:20.078384
2544 09:25:20.078436 ==
2545 09:25:20.078500 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 09:25:20.078553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 09:25:20.078604 ==
2548 09:25:20.078662 [Gating] SW mode calibration
2549 09:25:20.078715 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2550 09:25:20.078767 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2551 09:25:20.078820 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2552 09:25:20.078880 0 15 4 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
2553 09:25:20.078932 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2554 09:25:20.078984 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2555 09:25:20.079037 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2556 09:25:20.079089 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2557 09:25:20.079141 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2558 09:25:20.079192 0 15 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
2559 09:25:20.079256 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2560 09:25:20.079308 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 09:25:20.079360 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 09:25:20.079425 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2563 09:25:20.079478 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2564 09:25:20.079529 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 09:25:20.079581 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 09:25:20.079639 1 0 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2567 09:25:20.079702 1 1 0 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2568 09:25:20.079754 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2569 09:25:20.079806 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 09:25:20.079858 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 09:25:20.079916 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 09:25:20.079968 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 09:25:20.080019 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 09:25:20.080077 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2575 09:25:20.080130 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2576 09:25:20.080182 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 09:25:20.080234 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 09:25:20.080293 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 09:25:20.080345 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 09:25:20.080396 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 09:25:20.080454 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 09:25:20.080507 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 09:25:20.080559 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 09:25:20.080611 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 09:25:20.080664 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 09:25:20.080715 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 09:25:20.080767 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 09:25:20.080818 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 09:25:20.080893 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 09:25:20.080946 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2591 09:25:20.080998 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2592 09:25:20.081058 Total UI for P1: 0, mck2ui 16
2593 09:25:20.081326 best dqsien dly found for B0: ( 1, 3, 28)
2594 09:25:20.081386 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 09:25:20.081439 Total UI for P1: 0, mck2ui 16
2596 09:25:20.081494 best dqsien dly found for B1: ( 1, 4, 0)
2597 09:25:20.081546 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2598 09:25:20.081598 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2599 09:25:20.081650
2600 09:25:20.081709 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2601 09:25:20.081762 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2602 09:25:20.081814 [Gating] SW calibration Done
2603 09:25:20.081865 ==
2604 09:25:20.081930 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 09:25:20.081982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 09:25:20.082034 ==
2607 09:25:20.082093 RX Vref Scan: 0
2608 09:25:20.082146
2609 09:25:20.082221 RX Vref 0 -> 0, step: 1
2610 09:25:20.082282
2611 09:25:20.082335 RX Delay -40 -> 252, step: 8
2612 09:25:20.082389 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2613 09:25:20.082440 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2614 09:25:20.082492 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2615 09:25:20.082552 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2616 09:25:20.082605 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2617 09:25:20.082656 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2618 09:25:20.082708 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2619 09:25:20.082765 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2620 09:25:20.082817 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2621 09:25:20.082868 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2622 09:25:20.082929 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2623 09:25:20.082983 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2624 09:25:20.083045 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2625 09:25:20.083099 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2626 09:25:20.083160 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2627 09:25:20.083212 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2628 09:25:20.083264 ==
2629 09:25:20.083323 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 09:25:20.083375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 09:25:20.083428 ==
2632 09:25:20.083480 DQS Delay:
2633 09:25:20.083544 DQS0 = 0, DQS1 = 0
2634 09:25:20.083603 DQM Delay:
2635 09:25:20.083655 DQM0 = 119, DQM1 = 107
2636 09:25:20.083715 DQ Delay:
2637 09:25:20.083768 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2638 09:25:20.083819 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2639 09:25:20.083876 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2640 09:25:20.083930 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2641 09:25:20.083984
2642 09:25:20.084035
2643 09:25:20.084086 ==
2644 09:25:20.084136 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 09:25:20.084196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 09:25:20.084249 ==
2647 09:25:20.084307
2648 09:25:20.084366
2649 09:25:20.084419 TX Vref Scan disable
2650 09:25:20.084470 == TX Byte 0 ==
2651 09:25:20.084522 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2652 09:25:20.084581 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2653 09:25:20.084633 == TX Byte 1 ==
2654 09:25:20.084685 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2655 09:25:20.084748 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2656 09:25:20.084802 ==
2657 09:25:20.084853 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 09:25:20.084905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 09:25:20.084970 ==
2660 09:25:20.085022 TX Vref=22, minBit 1, minWin=25, winSum=409
2661 09:25:20.085074 TX Vref=24, minBit 1, minWin=25, winSum=418
2662 09:25:20.085132 TX Vref=26, minBit 1, minWin=26, winSum=426
2663 09:25:20.085185 TX Vref=28, minBit 5, minWin=26, winSum=434
2664 09:25:20.085238 TX Vref=30, minBit 4, minWin=26, winSum=429
2665 09:25:20.085290 TX Vref=32, minBit 4, minWin=26, winSum=431
2666 09:25:20.085350 [TxChooseVref] Worse bit 5, Min win 26, Win sum 434, Final Vref 28
2667 09:25:20.085408
2668 09:25:20.085460 Final TX Range 1 Vref 28
2669 09:25:20.085513
2670 09:25:20.085564 ==
2671 09:25:20.085627 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 09:25:20.085679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 09:25:20.085732 ==
2674 09:25:20.085789
2675 09:25:20.085842
2676 09:25:20.085893 TX Vref Scan disable
2677 09:25:20.085945 == TX Byte 0 ==
2678 09:25:20.086004 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2679 09:25:20.086056 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2680 09:25:20.086107 == TX Byte 1 ==
2681 09:25:20.086177 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2682 09:25:20.086233 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2683 09:25:20.086284
2684 09:25:20.086335 [DATLAT]
2685 09:25:20.086394 Freq=1200, CH0 RK0
2686 09:25:20.086447
2687 09:25:20.086498 DATLAT Default: 0xd
2688 09:25:20.086555 0, 0xFFFF, sum = 0
2689 09:25:20.086622 1, 0xFFFF, sum = 0
2690 09:25:20.086679 2, 0xFFFF, sum = 0
2691 09:25:20.086732 3, 0xFFFF, sum = 0
2692 09:25:20.086793 4, 0xFFFF, sum = 0
2693 09:25:20.086856 5, 0xFFFF, sum = 0
2694 09:25:20.086909 6, 0xFFFF, sum = 0
2695 09:25:20.086961 7, 0xFFFF, sum = 0
2696 09:25:20.087024 8, 0xFFFF, sum = 0
2697 09:25:20.087080 9, 0xFFFF, sum = 0
2698 09:25:20.087133 10, 0xFFFF, sum = 0
2699 09:25:20.087191 11, 0xFFFF, sum = 0
2700 09:25:20.087246 12, 0x0, sum = 1
2701 09:25:20.087298 13, 0x0, sum = 2
2702 09:25:20.087361 14, 0x0, sum = 3
2703 09:25:20.087422 15, 0x0, sum = 4
2704 09:25:20.087474 best_step = 13
2705 09:25:20.087526
2706 09:25:20.087579 ==
2707 09:25:20.087630 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 09:25:20.087681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 09:25:20.087734 ==
2710 09:25:20.087798 RX Vref Scan: 1
2711 09:25:20.087851
2712 09:25:20.087902 Set Vref Range= 32 -> 127
2713 09:25:20.087960
2714 09:25:20.088012 RX Vref 32 -> 127, step: 1
2715 09:25:20.088063
2716 09:25:20.088114 RX Delay -21 -> 252, step: 4
2717 09:25:20.088171
2718 09:25:20.088233 Set Vref, RX VrefLevel [Byte0]: 32
2719 09:25:20.088286 [Byte1]: 32
2720 09:25:20.088338
2721 09:25:20.088388 Set Vref, RX VrefLevel [Byte0]: 33
2722 09:25:20.088447 [Byte1]: 33
2723 09:25:20.088499
2724 09:25:20.088550 Set Vref, RX VrefLevel [Byte0]: 34
2725 09:25:20.088607 [Byte1]: 34
2726 09:25:20.088661
2727 09:25:20.088711 Set Vref, RX VrefLevel [Byte0]: 35
2728 09:25:20.088766 [Byte1]: 35
2729 09:25:20.088843
2730 09:25:20.088896 Set Vref, RX VrefLevel [Byte0]: 36
2731 09:25:20.088948 [Byte1]: 36
2732 09:25:20.089009
2733 09:25:20.089062 Set Vref, RX VrefLevel [Byte0]: 37
2734 09:25:20.089113 [Byte1]: 37
2735 09:25:20.089164
2736 09:25:20.089217 Set Vref, RX VrefLevel [Byte0]: 38
2737 09:25:20.089276 [Byte1]: 38
2738 09:25:20.089328
2739 09:25:20.089379 Set Vref, RX VrefLevel [Byte0]: 39
2740 09:25:20.089430 [Byte1]: 39
2741 09:25:20.089490
2742 09:25:20.089542 Set Vref, RX VrefLevel [Byte0]: 40
2743 09:25:20.089593 [Byte1]: 40
2744 09:25:20.089650
2745 09:25:20.089703 Set Vref, RX VrefLevel [Byte0]: 41
2746 09:25:20.089971 [Byte1]: 41
2747 09:25:20.090086
2748 09:25:20.090221 Set Vref, RX VrefLevel [Byte0]: 42
2749 09:25:20.090321 [Byte1]: 42
2750 09:25:20.090413
2751 09:25:20.090496 Set Vref, RX VrefLevel [Byte0]: 43
2752 09:25:20.090579 [Byte1]: 43
2753 09:25:20.090670
2754 09:25:20.090752 Set Vref, RX VrefLevel [Byte0]: 44
2755 09:25:20.090834 [Byte1]: 44
2756 09:25:20.090919
2757 09:25:20.090974 Set Vref, RX VrefLevel [Byte0]: 45
2758 09:25:20.091026 [Byte1]: 45
2759 09:25:20.091086
2760 09:25:20.091137 Set Vref, RX VrefLevel [Byte0]: 46
2761 09:25:20.091188 [Byte1]: 46
2762 09:25:20.091247
2763 09:25:20.091299 Set Vref, RX VrefLevel [Byte0]: 47
2764 09:25:20.091351 [Byte1]: 47
2765 09:25:20.091402
2766 09:25:20.091466 Set Vref, RX VrefLevel [Byte0]: 48
2767 09:25:20.091518 [Byte1]: 48
2768 09:25:20.091570
2769 09:25:20.091627 Set Vref, RX VrefLevel [Byte0]: 49
2770 09:25:20.091680 [Byte1]: 49
2771 09:25:20.091732
2772 09:25:20.091784 Set Vref, RX VrefLevel [Byte0]: 50
2773 09:25:20.091843 [Byte1]: 50
2774 09:25:20.091896
2775 09:25:20.091948 Set Vref, RX VrefLevel [Byte0]: 51
2776 09:25:20.091999 [Byte1]: 51
2777 09:25:20.092051
2778 09:25:20.092109 Set Vref, RX VrefLevel [Byte0]: 52
2779 09:25:20.092160 [Byte1]: 52
2780 09:25:20.092211
2781 09:25:20.092268 Set Vref, RX VrefLevel [Byte0]: 53
2782 09:25:20.092321 [Byte1]: 53
2783 09:25:20.092373
2784 09:25:20.092424 Set Vref, RX VrefLevel [Byte0]: 54
2785 09:25:20.092483 [Byte1]: 54
2786 09:25:20.092535
2787 09:25:20.092585 Set Vref, RX VrefLevel [Byte0]: 55
2788 09:25:20.092636 [Byte1]: 55
2789 09:25:20.092696
2790 09:25:20.092747 Set Vref, RX VrefLevel [Byte0]: 56
2791 09:25:20.092799 [Byte1]: 56
2792 09:25:20.092859
2793 09:25:20.092911 Set Vref, RX VrefLevel [Byte0]: 57
2794 09:25:20.092962 [Byte1]: 57
2795 09:25:20.093013
2796 09:25:20.093066 Set Vref, RX VrefLevel [Byte0]: 58
2797 09:25:20.093117 [Byte1]: 58
2798 09:25:20.093168
2799 09:25:20.093228 Set Vref, RX VrefLevel [Byte0]: 59
2800 09:25:20.093283 [Byte1]: 59
2801 09:25:20.093340
2802 09:25:20.093394 Set Vref, RX VrefLevel [Byte0]: 60
2803 09:25:20.093445 [Byte1]: 60
2804 09:25:20.093496
2805 09:25:20.093547 Set Vref, RX VrefLevel [Byte0]: 61
2806 09:25:20.093606 [Byte1]: 61
2807 09:25:20.093659
2808 09:25:20.093710 Set Vref, RX VrefLevel [Byte0]: 62
2809 09:25:20.093761 [Byte1]: 62
2810 09:25:20.093820
2811 09:25:20.093882 Set Vref, RX VrefLevel [Byte0]: 63
2812 09:25:20.093935 [Byte1]: 63
2813 09:25:20.093994
2814 09:25:20.094045 Set Vref, RX VrefLevel [Byte0]: 64
2815 09:25:20.094097 [Byte1]: 64
2816 09:25:20.094149
2817 09:25:20.094243 Set Vref, RX VrefLevel [Byte0]: 65
2818 09:25:20.094296 [Byte1]: 65
2819 09:25:20.094347
2820 09:25:20.094406 Set Vref, RX VrefLevel [Byte0]: 66
2821 09:25:20.094459 [Byte1]: 66
2822 09:25:20.094510
2823 09:25:20.094568 Set Vref, RX VrefLevel [Byte0]: 67
2824 09:25:20.094622 [Byte1]: 67
2825 09:25:20.094678
2826 09:25:20.094731 Set Vref, RX VrefLevel [Byte0]: 68
2827 09:25:20.094783 [Byte1]: 68
2828 09:25:20.094843
2829 09:25:20.094926 Set Vref, RX VrefLevel [Byte0]: 69
2830 09:25:20.095008 [Byte1]: 69
2831 09:25:20.095078
2832 09:25:20.095131 Set Vref, RX VrefLevel [Byte0]: 70
2833 09:25:20.095183 [Byte1]: 70
2834 09:25:20.095242
2835 09:25:20.095295 Set Vref, RX VrefLevel [Byte0]: 71
2836 09:25:20.095347 [Byte1]: 71
2837 09:25:20.095402
2838 09:25:20.095456 Set Vref, RX VrefLevel [Byte0]: 72
2839 09:25:20.095508 [Byte1]: 72
2840 09:25:20.095559
2841 09:25:20.095621 Set Vref, RX VrefLevel [Byte0]: 73
2842 09:25:20.095704 [Byte1]: 73
2843 09:25:20.095787
2844 09:25:20.095873 Set Vref, RX VrefLevel [Byte0]: 74
2845 09:25:20.095955 [Byte1]: 74
2846 09:25:20.096039
2847 09:25:20.096126 Set Vref, RX VrefLevel [Byte0]: 75
2848 09:25:20.096207 [Byte1]: 75
2849 09:25:20.096291
2850 09:25:20.096373 Set Vref, RX VrefLevel [Byte0]: 76
2851 09:25:20.096461 [Byte1]: 76
2852 09:25:20.096554
2853 09:25:20.096645 Set Vref, RX VrefLevel [Byte0]: 77
2854 09:25:20.096731 [Byte1]: 77
2855 09:25:20.096813
2856 09:25:20.096898 Final RX Vref Byte 0 = 61 to rank0
2857 09:25:20.096984 Final RX Vref Byte 1 = 49 to rank0
2858 09:25:20.097066 Final RX Vref Byte 0 = 61 to rank1
2859 09:25:20.097166 Final RX Vref Byte 1 = 49 to rank1==
2860 09:25:20.097250 Dram Type= 6, Freq= 0, CH_0, rank 0
2861 09:25:20.097336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 09:25:20.097419 ==
2863 09:25:20.097506 DQS Delay:
2864 09:25:20.097592 DQS0 = 0, DQS1 = 0
2865 09:25:20.097673 DQM Delay:
2866 09:25:20.097760 DQM0 = 118, DQM1 = 107
2867 09:25:20.097849 DQ Delay:
2868 09:25:20.097932 DQ0 =116, DQ1 =120, DQ2 =114, DQ3 =116
2869 09:25:20.098016 DQ4 =120, DQ5 =110, DQ6 =124, DQ7 =126
2870 09:25:20.098103 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =100
2871 09:25:20.098196 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
2872 09:25:20.098282
2873 09:25:20.098364
2874 09:25:20.098449 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 402 ps
2875 09:25:20.098534 CH0 RK0: MR19=403, MR18=14FF
2876 09:25:20.098616 CH0_RK0: MR19=0x403, MR18=0x14FF, DQSOSC=402, MR23=63, INC=40, DEC=27
2877 09:25:20.098702
2878 09:25:20.098787 ----->DramcWriteLeveling(PI) begin...
2879 09:25:20.098871 ==
2880 09:25:20.098960 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 09:25:20.099043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 09:25:20.099128 ==
2883 09:25:20.099210 Write leveling (Byte 0): 32 => 32
2884 09:25:20.099292 Write leveling (Byte 1): 30 => 30
2885 09:25:20.099356 DramcWriteLeveling(PI) end<-----
2886 09:25:20.099409
2887 09:25:20.099460 ==
2888 09:25:20.099535 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 09:25:20.099622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 09:25:20.099711 ==
2891 09:25:20.099794 [Gating] SW mode calibration
2892 09:25:20.099879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2893 09:25:20.099966 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2894 09:25:20.100052 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2895 09:25:20.100135 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2896 09:25:20.100440 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 09:25:20.100506 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 09:25:20.100574 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 09:25:20.100631 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 09:25:20.100689 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2901 09:25:20.100742 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2902 09:25:20.100795 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
2903 09:25:20.100853 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 09:25:20.100907 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 09:25:20.100960 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 09:25:20.101012 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 09:25:20.101069 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 09:25:20.101121 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 09:25:20.101173 1 0 28 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
2910 09:25:20.101234 1 1 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2911 09:25:20.101289 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 09:25:20.101342 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 09:25:20.101393 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 09:25:20.101451 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 09:25:20.101503 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 09:25:20.101555 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2917 09:25:20.101626 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2918 09:25:20.101710 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2919 09:25:20.101792 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 09:25:20.101877 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 09:25:20.101960 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 09:25:20.102042 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 09:25:20.102128 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 09:25:20.102208 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 09:25:20.102267 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 09:25:20.102321 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 09:25:20.102373 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 09:25:20.102425 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 09:25:20.102487 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 09:25:20.102539 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 09:25:20.102591 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 09:25:20.102649 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 09:25:20.102704 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2934 09:25:20.102756 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2935 09:25:20.102807 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 09:25:20.102871 Total UI for P1: 0, mck2ui 16
2937 09:25:20.102927 best dqsien dly found for B0: ( 1, 3, 30)
2938 09:25:20.102979 Total UI for P1: 0, mck2ui 16
2939 09:25:20.329002 best dqsien dly found for B1: ( 1, 3, 30)
2940 09:25:20.329175 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2941 09:25:20.329258 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2942 09:25:20.329320
2943 09:25:20.329386 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2944 09:25:20.329461 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2945 09:25:20.329521 [Gating] SW calibration Done
2946 09:25:20.329576 ==
2947 09:25:20.329631 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 09:25:20.329685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 09:25:20.329772 ==
2950 09:25:20.329855 RX Vref Scan: 0
2951 09:25:20.329941
2952 09:25:20.330023 RX Vref 0 -> 0, step: 1
2953 09:25:20.330109
2954 09:25:20.330204 RX Delay -40 -> 252, step: 8
2955 09:25:20.330267 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2956 09:25:20.330324 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2957 09:25:20.330377 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2958 09:25:20.330431 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2959 09:25:20.330514 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2960 09:25:20.330597 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2961 09:25:20.330683 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2962 09:25:20.330767 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2963 09:25:20.330849 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2964 09:25:20.330935 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2965 09:25:20.331018 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2966 09:25:20.331103 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2967 09:25:20.331184 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2968 09:25:20.331239 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2969 09:25:20.331296 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2970 09:25:20.331350 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2971 09:25:20.331412 ==
2972 09:25:20.331475 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 09:25:20.331560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 09:25:20.331642 ==
2975 09:25:20.331733 DQS Delay:
2976 09:25:20.331826 DQS0 = 0, DQS1 = 0
2977 09:25:20.331911 DQM Delay:
2978 09:25:20.331993 DQM0 = 116, DQM1 = 108
2979 09:25:20.332077 DQ Delay:
2980 09:25:20.332163 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2981 09:25:20.332245 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2982 09:25:20.332331 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2983 09:25:20.332414 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2984 09:25:20.332497
2985 09:25:20.332580
2986 09:25:20.332660 ==
2987 09:25:20.332746 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 09:25:20.332828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 09:25:20.332913 ==
2990 09:25:20.332995
2991 09:25:20.333079
2992 09:25:20.333165 TX Vref Scan disable
2993 09:25:20.333253 == TX Byte 0 ==
2994 09:25:20.333319 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2995 09:25:20.333377 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2996 09:25:20.333430 == TX Byte 1 ==
2997 09:25:20.333482 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2998 09:25:20.333534 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2999 09:25:20.333618 ==
3000 09:25:20.333700 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 09:25:20.333786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 09:25:20.333867 ==
3003 09:25:20.334185 TX Vref=22, minBit 1, minWin=26, winSum=421
3004 09:25:20.334263 TX Vref=24, minBit 1, minWin=26, winSum=426
3005 09:25:20.334327 TX Vref=26, minBit 4, minWin=26, winSum=432
3006 09:25:20.334383 TX Vref=28, minBit 13, minWin=26, winSum=434
3007 09:25:20.334436 TX Vref=30, minBit 1, minWin=27, winSum=439
3008 09:25:20.334496 TX Vref=32, minBit 10, minWin=26, winSum=433
3009 09:25:20.334581 [TxChooseVref] Worse bit 1, Min win 27, Win sum 439, Final Vref 30
3010 09:25:20.334664
3011 09:25:20.334763 Final TX Range 1 Vref 30
3012 09:25:20.334846
3013 09:25:20.334926 ==
3014 09:25:20.335014 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 09:25:20.335096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 09:25:20.335182 ==
3017 09:25:20.335263
3018 09:25:20.335350
3019 09:25:20.335432 TX Vref Scan disable
3020 09:25:20.335513 == TX Byte 0 ==
3021 09:25:20.335599 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3022 09:25:20.335681 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3023 09:25:20.335768 == TX Byte 1 ==
3024 09:25:20.335850 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3025 09:25:20.335937 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3026 09:25:20.336019
3027 09:25:20.336103 [DATLAT]
3028 09:25:20.336187 Freq=1200, CH0 RK1
3029 09:25:20.336269
3030 09:25:20.336350 DATLAT Default: 0xd
3031 09:25:20.336435 0, 0xFFFF, sum = 0
3032 09:25:20.336528 1, 0xFFFF, sum = 0
3033 09:25:20.336618 2, 0xFFFF, sum = 0
3034 09:25:20.336707 3, 0xFFFF, sum = 0
3035 09:25:20.336798 4, 0xFFFF, sum = 0
3036 09:25:20.336890 5, 0xFFFF, sum = 0
3037 09:25:20.336982 6, 0xFFFF, sum = 0
3038 09:25:20.337066 7, 0xFFFF, sum = 0
3039 09:25:20.337155 8, 0xFFFF, sum = 0
3040 09:25:20.337240 9, 0xFFFF, sum = 0
3041 09:25:20.337334 10, 0xFFFF, sum = 0
3042 09:25:20.337391 11, 0xFFFF, sum = 0
3043 09:25:20.337444 12, 0x0, sum = 1
3044 09:25:20.337498 13, 0x0, sum = 2
3045 09:25:20.337586 14, 0x0, sum = 3
3046 09:25:20.337670 15, 0x0, sum = 4
3047 09:25:20.337754 best_step = 13
3048 09:25:20.337839
3049 09:25:20.337920 ==
3050 09:25:20.338008 Dram Type= 6, Freq= 0, CH_0, rank 1
3051 09:25:20.338098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3052 09:25:20.338197 ==
3053 09:25:20.338286 RX Vref Scan: 0
3054 09:25:20.338379
3055 09:25:20.338435 RX Vref 0 -> 0, step: 1
3056 09:25:20.338488
3057 09:25:20.338543 RX Delay -21 -> 252, step: 4
3058 09:25:20.338628 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3059 09:25:20.338711 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3060 09:25:20.338801 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3061 09:25:20.338884 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3062 09:25:20.338967 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3063 09:25:20.339054 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3064 09:25:20.339136 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3065 09:25:20.339224 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3066 09:25:20.339331 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3067 09:25:20.339419 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3068 09:25:20.339502 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3069 09:25:20.339589 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3070 09:25:20.339677 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3071 09:25:20.339764 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3072 09:25:20.339849 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3073 09:25:20.339919 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3074 09:25:20.339984 ==
3075 09:25:20.340038 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 09:25:20.340090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 09:25:20.340149 ==
3078 09:25:20.340235 DQS Delay:
3079 09:25:20.340318 DQS0 = 0, DQS1 = 0
3080 09:25:20.340401 DQM Delay:
3081 09:25:20.340486 DQM0 = 115, DQM1 = 107
3082 09:25:20.340567 DQ Delay:
3083 09:25:20.340653 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =112
3084 09:25:20.340735 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3085 09:25:20.340820 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3086 09:25:20.340905 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3087 09:25:20.340991
3088 09:25:20.341084
3089 09:25:20.341170 [DQSOSCAuto] RK1, (LSB)MR18= 0x10eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps
3090 09:25:20.341260 CH0 RK1: MR19=403, MR18=10EB
3091 09:25:20.341349 CH0_RK1: MR19=0x403, MR18=0x10EB, DQSOSC=403, MR23=63, INC=40, DEC=26
3092 09:25:20.341443 [RxdqsGatingPostProcess] freq 1200
3093 09:25:20.341533 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3094 09:25:20.341599 best DQS0 dly(2T, 0.5T) = (0, 11)
3095 09:25:20.341656 best DQS1 dly(2T, 0.5T) = (0, 12)
3096 09:25:20.341709 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3097 09:25:20.341762 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3098 09:25:20.341829 best DQS0 dly(2T, 0.5T) = (0, 11)
3099 09:25:20.341911 best DQS1 dly(2T, 0.5T) = (0, 11)
3100 09:25:20.341997 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3101 09:25:20.342080 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3102 09:25:20.342169 Pre-setting of DQS Precalculation
3103 09:25:20.342257 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3104 09:25:20.342339 ==
3105 09:25:20.342425 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 09:25:20.342507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 09:25:20.342598 ==
3108 09:25:20.342681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3109 09:25:20.342767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3110 09:25:20.342851 [CA 0] Center 37 (7~68) winsize 62
3111 09:25:20.342935 [CA 1] Center 37 (7~68) winsize 62
3112 09:25:20.343020 [CA 2] Center 34 (4~64) winsize 61
3113 09:25:20.343103 [CA 3] Center 33 (3~64) winsize 62
3114 09:25:20.343184 [CA 4] Center 34 (5~64) winsize 60
3115 09:25:20.343274 [CA 5] Center 33 (3~64) winsize 62
3116 09:25:20.343372
3117 09:25:20.343465 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3118 09:25:20.343559
3119 09:25:20.343647 [CATrainingPosCal] consider 1 rank data
3120 09:25:20.343730 u2DelayCellTimex100 = 270/100 ps
3121 09:25:20.343818 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3122 09:25:20.343903 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3123 09:25:20.343986 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3124 09:25:20.344071 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3125 09:25:20.344154 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3126 09:25:20.344242 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3127 09:25:20.344309
3128 09:25:20.344362 CA PerBit enable=1, Macro0, CA PI delay=33
3129 09:25:20.344414
3130 09:25:20.344473 [CBTSetCACLKResult] CA Dly = 33
3131 09:25:20.344528 CS Dly: 6 (0~37)
3132 09:25:20.344580 ==
3133 09:25:20.344633 Dram Type= 6, Freq= 0, CH_1, rank 1
3134 09:25:20.344718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 09:25:20.344811 ==
3136 09:25:20.344898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3137 09:25:20.345206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3138 09:25:20.345320 [CA 0] Center 37 (7~67) winsize 61
3139 09:25:20.345399 [CA 1] Center 38 (8~68) winsize 61
3140 09:25:20.345464 [CA 2] Center 34 (4~65) winsize 62
3141 09:25:20.345519 [CA 3] Center 33 (3~64) winsize 62
3142 09:25:20.345573 [CA 4] Center 34 (3~65) winsize 63
3143 09:25:20.345636 [CA 5] Center 33 (3~64) winsize 62
3144 09:25:20.345724
3145 09:25:20.345808 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3146 09:25:20.345892
3147 09:25:20.345975 [CATrainingPosCal] consider 2 rank data
3148 09:25:20.346057 u2DelayCellTimex100 = 270/100 ps
3149 09:25:20.346143 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3150 09:25:20.346216 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3151 09:25:20.346278 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 09:25:20.346332 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3153 09:25:20.346385 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3154 09:25:20.346436 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3155 09:25:20.346494
3156 09:25:20.346547 CA PerBit enable=1, Macro0, CA PI delay=33
3157 09:25:20.346599
3158 09:25:20.346669 [CBTSetCACLKResult] CA Dly = 33
3159 09:25:20.346751 CS Dly: 7 (0~40)
3160 09:25:20.346834
3161 09:25:20.346919 ----->DramcWriteLeveling(PI) begin...
3162 09:25:20.347002 ==
3163 09:25:20.347090 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 09:25:20.347173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 09:25:20.347261 ==
3166 09:25:20.347360 Write leveling (Byte 0): 24 => 24
3167 09:25:20.347443 Write leveling (Byte 1): 27 => 27
3168 09:25:20.347529 DramcWriteLeveling(PI) end<-----
3169 09:25:20.347610
3170 09:25:20.347696 ==
3171 09:25:20.347779 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 09:25:20.347865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 09:25:20.347948 ==
3174 09:25:20.348040 [Gating] SW mode calibration
3175 09:25:20.348129 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3176 09:25:20.348213 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3177 09:25:20.348300 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3178 09:25:20.348384 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 09:25:20.348470 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 09:25:20.348556 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 09:25:20.348639 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 09:25:20.348727 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 09:25:20.348810 0 15 24 | B1->B0 | 3333 2b2b | 1 0 | (1 1) (0 1)
3184 09:25:20.348901 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3185 09:25:20.348987 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 09:25:20.349077 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 09:25:20.349162 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 09:25:20.349251 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 09:25:20.349324 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 09:25:20.349378 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 09:25:20.349431 1 0 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
3192 09:25:20.349516 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3193 09:25:20.349600 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 09:25:20.349688 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 09:25:20.349775 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 09:25:20.349863 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 09:25:20.349951 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 09:25:20.350046 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3199 09:25:20.350133 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3200 09:25:20.350229 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3201 09:25:20.350284 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 09:25:20.350367 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 09:25:20.350461 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 09:25:20.350556 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 09:25:20.350645 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 09:25:20.350737 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 09:25:20.350820 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 09:25:20.350915 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 09:25:20.351009 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 09:25:20.351097 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 09:25:20.351194 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 09:25:20.351287 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 09:25:20.351379 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 09:25:20.351462 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 09:25:20.351548 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3216 09:25:20.351636 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3217 09:25:20.351720 Total UI for P1: 0, mck2ui 16
3218 09:25:20.351814 best dqsien dly found for B0: ( 1, 3, 24)
3219 09:25:20.351902 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 09:25:20.351986 Total UI for P1: 0, mck2ui 16
3221 09:25:20.352069 best dqsien dly found for B1: ( 1, 3, 26)
3222 09:25:20.352157 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3223 09:25:20.352247 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3224 09:25:20.352336
3225 09:25:20.352418 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3226 09:25:20.352512 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3227 09:25:20.352596 [Gating] SW calibration Done
3228 09:25:20.352691 ==
3229 09:25:20.352779 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 09:25:20.352868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 09:25:20.352956 ==
3232 09:25:20.353049 RX Vref Scan: 0
3233 09:25:20.353140
3234 09:25:20.353223 RX Vref 0 -> 0, step: 1
3235 09:25:20.353312
3236 09:25:20.353382 RX Delay -40 -> 252, step: 8
3237 09:25:20.353467 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3238 09:25:20.353565 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3239 09:25:20.353654 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3240 09:25:20.353749 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3241 09:25:20.353840 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3242 09:25:20.354155 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3243 09:25:20.354261 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3244 09:25:20.354364 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3245 09:25:20.354451 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3246 09:25:20.354546 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3247 09:25:20.354632 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3248 09:25:20.354726 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3249 09:25:20.354813 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3250 09:25:20.354896 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3251 09:25:20.354982 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3252 09:25:20.355065 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3253 09:25:20.355152 ==
3254 09:25:20.355243 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 09:25:20.355339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 09:25:20.355426 ==
3257 09:25:20.355515 DQS Delay:
3258 09:25:20.355601 DQS0 = 0, DQS1 = 0
3259 09:25:20.355693 DQM Delay:
3260 09:25:20.355780 DQM0 = 117, DQM1 = 110
3261 09:25:20.355870 DQ Delay:
3262 09:25:20.355959 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3263 09:25:20.356047 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3264 09:25:20.356130 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3265 09:25:20.356225 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3266 09:25:20.356309
3267 09:25:20.356403
3268 09:25:20.356485 ==
3269 09:25:20.356583 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 09:25:20.356670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3271 09:25:20.356761 ==
3272 09:25:20.356848
3273 09:25:20.356929
3274 09:25:20.357014 TX Vref Scan disable
3275 09:25:20.357097 == TX Byte 0 ==
3276 09:25:20.357190 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3277 09:25:20.357290 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3278 09:25:20.357385 == TX Byte 1 ==
3279 09:25:20.357442 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3280 09:25:20.357496 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3281 09:25:20.357550 ==
3282 09:25:20.357636 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 09:25:20.357719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 09:25:20.357807 ==
3285 09:25:20.357901 TX Vref=22, minBit 10, minWin=24, winSum=415
3286 09:25:20.357988 TX Vref=24, minBit 11, minWin=25, winSum=422
3287 09:25:20.358074 TX Vref=26, minBit 2, minWin=26, winSum=429
3288 09:25:20.358174 TX Vref=28, minBit 9, minWin=25, winSum=430
3289 09:25:20.358259 TX Vref=30, minBit 9, minWin=25, winSum=428
3290 09:25:20.358345 TX Vref=32, minBit 9, minWin=25, winSum=424
3291 09:25:20.358429 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 26
3292 09:25:20.358515
3293 09:25:20.358597 Final TX Range 1 Vref 26
3294 09:25:20.358682
3295 09:25:20.358764 ==
3296 09:25:20.358851 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 09:25:20.358940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 09:25:20.359027 ==
3299 09:25:20.359115
3300 09:25:20.359196
3301 09:25:20.359291 TX Vref Scan disable
3302 09:25:20.359385 == TX Byte 0 ==
3303 09:25:20.359469 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3304 09:25:20.359559 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3305 09:25:20.359642 == TX Byte 1 ==
3306 09:25:20.359735 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3307 09:25:20.359822 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3308 09:25:20.359907
3309 09:25:20.359989 [DATLAT]
3310 09:25:20.360070 Freq=1200, CH1 RK0
3311 09:25:20.360155
3312 09:25:20.360236 DATLAT Default: 0xd
3313 09:25:20.360322 0, 0xFFFF, sum = 0
3314 09:25:20.360415 1, 0xFFFF, sum = 0
3315 09:25:20.360505 2, 0xFFFF, sum = 0
3316 09:25:20.360589 3, 0xFFFF, sum = 0
3317 09:25:20.360681 4, 0xFFFF, sum = 0
3318 09:25:20.360768 5, 0xFFFF, sum = 0
3319 09:25:20.360866 6, 0xFFFF, sum = 0
3320 09:25:20.360954 7, 0xFFFF, sum = 0
3321 09:25:20.361037 8, 0xFFFF, sum = 0
3322 09:25:20.361125 9, 0xFFFF, sum = 0
3323 09:25:20.361208 10, 0xFFFF, sum = 0
3324 09:25:20.361302 11, 0xFFFF, sum = 0
3325 09:25:20.361357 12, 0x0, sum = 1
3326 09:25:20.361411 13, 0x0, sum = 2
3327 09:25:20.361469 14, 0x0, sum = 3
3328 09:25:20.361555 15, 0x0, sum = 4
3329 09:25:20.361637 best_step = 13
3330 09:25:20.361724
3331 09:25:20.361813 ==
3332 09:25:20.361900 Dram Type= 6, Freq= 0, CH_1, rank 0
3333 09:25:20.361988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3334 09:25:20.362074 ==
3335 09:25:20.362177 RX Vref Scan: 1
3336 09:25:20.362235
3337 09:25:20.362297 Set Vref Range= 32 -> 127
3338 09:25:20.362384
3339 09:25:20.362468 RX Vref 32 -> 127, step: 1
3340 09:25:20.362553
3341 09:25:20.362635 RX Delay -21 -> 252, step: 4
3342 09:25:20.362716
3343 09:25:20.362800 Set Vref, RX VrefLevel [Byte0]: 32
3344 09:25:20.362881 [Byte1]: 32
3345 09:25:20.362980
3346 09:25:20.363063 Set Vref, RX VrefLevel [Byte0]: 33
3347 09:25:20.363151 [Byte1]: 33
3348 09:25:20.363239
3349 09:25:20.363347 Set Vref, RX VrefLevel [Byte0]: 34
3350 09:25:20.363442 [Byte1]: 34
3351 09:25:20.363525
3352 09:25:20.363614 Set Vref, RX VrefLevel [Byte0]: 35
3353 09:25:20.363697 [Byte1]: 35
3354 09:25:20.363799
3355 09:25:20.363882 Set Vref, RX VrefLevel [Byte0]: 36
3356 09:25:20.363971 [Byte1]: 36
3357 09:25:20.364064
3358 09:25:20.364157 Set Vref, RX VrefLevel [Byte0]: 37
3359 09:25:20.364241 [Byte1]: 37
3360 09:25:20.364324
3361 09:25:20.364413 Set Vref, RX VrefLevel [Byte0]: 38
3362 09:25:20.364495 [Byte1]: 38
3363 09:25:20.364589
3364 09:25:20.364671 Set Vref, RX VrefLevel [Byte0]: 39
3365 09:25:20.364762 [Byte1]: 39
3366 09:25:20.364853
3367 09:25:20.364935 Set Vref, RX VrefLevel [Byte0]: 40
3368 09:25:20.365023 [Byte1]: 40
3369 09:25:20.365104
3370 09:25:20.365195 Set Vref, RX VrefLevel [Byte0]: 41
3371 09:25:20.365256 [Byte1]: 41
3372 09:25:20.365337
3373 09:25:20.365423 Set Vref, RX VrefLevel [Byte0]: 42
3374 09:25:20.365505 [Byte1]: 42
3375 09:25:20.365602
3376 09:25:20.365685 Set Vref, RX VrefLevel [Byte0]: 43
3377 09:25:20.365773 [Byte1]: 43
3378 09:25:20.365855
3379 09:25:20.365949 Set Vref, RX VrefLevel [Byte0]: 44
3380 09:25:20.366035 [Byte1]: 44
3381 09:25:20.366123
3382 09:25:20.366205 Set Vref, RX VrefLevel [Byte0]: 45
3383 09:25:20.366260 [Byte1]: 45
3384 09:25:20.366333
3385 09:25:20.366404 Set Vref, RX VrefLevel [Byte0]: 46
3386 09:25:20.366458 [Byte1]: 46
3387 09:25:20.366510
3388 09:25:20.366571 Set Vref, RX VrefLevel [Byte0]: 47
3389 09:25:20.366661 [Byte1]: 47
3390 09:25:20.366744
3391 09:25:20.366834 Set Vref, RX VrefLevel [Byte0]: 48
3392 09:25:20.366917 [Byte1]: 48
3393 09:25:20.367012
3394 09:25:20.367094 Set Vref, RX VrefLevel [Byte0]: 49
3395 09:25:20.367189 [Byte1]: 49
3396 09:25:20.367278
3397 09:25:20.367402 Set Vref, RX VrefLevel [Byte0]: 50
3398 09:25:20.367486 [Byte1]: 50
3399 09:25:20.367581
3400 09:25:20.367665 Set Vref, RX VrefLevel [Byte0]: 51
3401 09:25:20.367984 [Byte1]: 51
3402 09:25:20.368073
3403 09:25:20.368164 Set Vref, RX VrefLevel [Byte0]: 52
3404 09:25:20.368247 [Byte1]: 52
3405 09:25:20.368340
3406 09:25:20.368423 Set Vref, RX VrefLevel [Byte0]: 53
3407 09:25:20.368512 [Byte1]: 53
3408 09:25:20.368594
3409 09:25:20.368681 Set Vref, RX VrefLevel [Byte0]: 54
3410 09:25:20.368764 [Byte1]: 54
3411 09:25:20.368855
3412 09:25:20.368940 Set Vref, RX VrefLevel [Byte0]: 55
3413 09:25:20.369028 [Byte1]: 55
3414 09:25:20.369117
3415 09:25:20.369203 Set Vref, RX VrefLevel [Byte0]: 56
3416 09:25:20.369284 [Byte1]: 56
3417 09:25:20.369345
3418 09:25:20.369403 Set Vref, RX VrefLevel [Byte0]: 57
3419 09:25:20.369488 [Byte1]: 57
3420 09:25:20.369573
3421 09:25:20.369660 Set Vref, RX VrefLevel [Byte0]: 58
3422 09:25:20.369746 [Byte1]: 58
3423 09:25:20.369828
3424 09:25:20.369916 Set Vref, RX VrefLevel [Byte0]: 59
3425 09:25:20.370001 [Byte1]: 59
3426 09:25:20.370084
3427 09:25:20.370184 Set Vref, RX VrefLevel [Byte0]: 60
3428 09:25:20.370275 [Byte1]: 60
3429 09:25:20.370360
3430 09:25:20.370442 Set Vref, RX VrefLevel [Byte0]: 61
3431 09:25:20.370525 [Byte1]: 61
3432 09:25:20.370610
3433 09:25:20.370692 Set Vref, RX VrefLevel [Byte0]: 62
3434 09:25:20.370777 [Byte1]: 62
3435 09:25:20.370858
3436 09:25:20.370943 Set Vref, RX VrefLevel [Byte0]: 63
3437 09:25:20.371036 [Byte1]: 63
3438 09:25:20.371122
3439 09:25:20.371204 Set Vref, RX VrefLevel [Byte0]: 64
3440 09:25:20.371299 [Byte1]: 64
3441 09:25:20.371381
3442 09:25:20.371462 Set Vref, RX VrefLevel [Byte0]: 65
3443 09:25:20.371549 [Byte1]: 65
3444 09:25:20.371630
3445 09:25:20.371711 Set Vref, RX VrefLevel [Byte0]: 66
3446 09:25:20.371797 [Byte1]: 66
3447 09:25:20.371878
3448 09:25:20.371962 Final RX Vref Byte 0 = 46 to rank0
3449 09:25:20.372045 Final RX Vref Byte 1 = 53 to rank0
3450 09:25:20.372129 Final RX Vref Byte 0 = 46 to rank1
3451 09:25:20.372215 Final RX Vref Byte 1 = 53 to rank1==
3452 09:25:20.372297 Dram Type= 6, Freq= 0, CH_1, rank 0
3453 09:25:20.372383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 09:25:20.372465 ==
3455 09:25:20.372550 DQS Delay:
3456 09:25:20.372632 DQS0 = 0, DQS1 = 0
3457 09:25:20.372718 DQM Delay:
3458 09:25:20.372801 DQM0 = 116, DQM1 = 110
3459 09:25:20.372882 DQ Delay:
3460 09:25:20.372967 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112
3461 09:25:20.373049 DQ4 =112, DQ5 =128, DQ6 =124, DQ7 =114
3462 09:25:20.373136 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =100
3463 09:25:20.373213 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3464 09:25:20.373271
3465 09:25:20.373375
3466 09:25:20.373469 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3467 09:25:20.373558 CH1 RK0: MR19=403, MR18=3F6
3468 09:25:20.373650 CH1_RK0: MR19=0x403, MR18=0x3F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3469 09:25:20.373737
3470 09:25:20.373828 ----->DramcWriteLeveling(PI) begin...
3471 09:25:20.373931 ==
3472 09:25:20.374022 Dram Type= 6, Freq= 0, CH_1, rank 1
3473 09:25:20.374106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 09:25:20.374211 ==
3475 09:25:20.374296 Write leveling (Byte 0): 23 => 23
3476 09:25:20.374383 Write leveling (Byte 1): 28 => 28
3477 09:25:20.374466 DramcWriteLeveling(PI) end<-----
3478 09:25:20.374554
3479 09:25:20.374636 ==
3480 09:25:20.374729 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 09:25:20.374827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 09:25:20.374913 ==
3483 09:25:20.374999 [Gating] SW mode calibration
3484 09:25:20.375096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3485 09:25:20.375185 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3486 09:25:20.375275 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3487 09:25:20.375358 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 09:25:20.375455 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 09:25:20.375538 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 09:25:20.375627 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 09:25:20.375723 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 09:25:20.375806 0 15 24 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 0)
3493 09:25:20.375896 0 15 28 | B1->B0 | 2323 2929 | 0 1 | (1 0) (1 0)
3494 09:25:20.375979 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 09:25:20.376073 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 09:25:20.376158 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 09:25:20.376246 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 09:25:20.376330 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 09:25:20.376416 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3500 09:25:20.376507 1 0 24 | B1->B0 | 4343 3131 | 0 1 | (0 0) (0 0)
3501 09:25:20.376590 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3502 09:25:20.376682 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 09:25:20.376766 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 09:25:20.376862 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 09:25:20.376945 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 09:25:20.377035 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 09:25:20.377128 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 09:25:20.377211 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 09:25:20.377289 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3510 09:25:20.377343 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 09:25:20.377395 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 09:25:20.377477 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 09:25:20.377573 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 09:25:20.377662 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 09:25:20.377744 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 09:25:20.377832 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 09:25:20.377916 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 09:25:20.377998 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 09:25:20.378095 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 09:25:20.378400 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 09:25:20.378473 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 09:25:20.378560 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 09:25:20.378644 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 09:25:20.378740 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3525 09:25:20.378824 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3526 09:25:20.378914 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 09:25:20.378997 Total UI for P1: 0, mck2ui 16
3528 09:25:20.379093 best dqsien dly found for B0: ( 1, 3, 26)
3529 09:25:20.379177 Total UI for P1: 0, mck2ui 16
3530 09:25:20.379271 best dqsien dly found for B1: ( 1, 3, 26)
3531 09:25:20.379366 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3532 09:25:20.379462 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3533 09:25:20.379545
3534 09:25:20.379634 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3535 09:25:20.379718 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3536 09:25:20.379799 [Gating] SW calibration Done
3537 09:25:20.379896 ==
3538 09:25:20.379981 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 09:25:20.380065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 09:25:20.380158 ==
3541 09:25:20.380240 RX Vref Scan: 0
3542 09:25:20.380327
3543 09:25:20.380408 RX Vref 0 -> 0, step: 1
3544 09:25:20.380496
3545 09:25:20.380578 RX Delay -40 -> 252, step: 8
3546 09:25:20.380675 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3547 09:25:20.380762 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3548 09:25:20.380849 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3549 09:25:20.380933 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3550 09:25:20.381034 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3551 09:25:20.381124 iDelay=200, Bit 5, Center 123 (56 ~ 191) 136
3552 09:25:20.381207 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3553 09:25:20.381303 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3554 09:25:20.381370 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3555 09:25:20.381423 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3556 09:25:20.381475 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3557 09:25:20.381561 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3558 09:25:20.381644 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3559 09:25:20.381735 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3560 09:25:20.381818 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3561 09:25:20.381910 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3562 09:25:20.381994 ==
3563 09:25:20.382081 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 09:25:20.382176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 09:25:20.382234 ==
3566 09:25:20.382316 DQS Delay:
3567 09:25:20.382372 DQS0 = 0, DQS1 = 0
3568 09:25:20.382425 DQM Delay:
3569 09:25:20.382486 DQM0 = 116, DQM1 = 110
3570 09:25:20.382582 DQ Delay:
3571 09:25:20.382671 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3572 09:25:20.382753 DQ4 =115, DQ5 =123, DQ6 =127, DQ7 =115
3573 09:25:20.382841 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3574 09:25:20.382924 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3575 09:25:20.383012
3576 09:25:20.383098
3577 09:25:20.383179 ==
3578 09:25:20.383274 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 09:25:20.383368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 09:25:20.383464 ==
3581 09:25:20.383546
3582 09:25:20.383634
3583 09:25:20.383716 TX Vref Scan disable
3584 09:25:20.383811 == TX Byte 0 ==
3585 09:25:20.383895 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3586 09:25:20.383982 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3587 09:25:20.384077 == TX Byte 1 ==
3588 09:25:20.384172 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3589 09:25:20.384262 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3590 09:25:20.384344 ==
3591 09:25:20.384431 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 09:25:20.384515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 09:25:20.384598 ==
3594 09:25:20.384692 TX Vref=22, minBit 8, minWin=25, winSum=424
3595 09:25:20.384775 TX Vref=24, minBit 3, minWin=26, winSum=427
3596 09:25:20.384871 TX Vref=26, minBit 8, minWin=25, winSum=434
3597 09:25:20.384954 TX Vref=28, minBit 8, minWin=26, winSum=435
3598 09:25:20.385047 TX Vref=30, minBit 8, minWin=26, winSum=437
3599 09:25:20.385131 TX Vref=32, minBit 9, minWin=25, winSum=432
3600 09:25:20.385222 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 30
3601 09:25:20.385294
3602 09:25:20.385348 Final TX Range 1 Vref 30
3603 09:25:20.385417
3604 09:25:20.385498 ==
3605 09:25:20.385579 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 09:25:20.385676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 09:25:20.385760 ==
3608 09:25:20.385847
3609 09:25:20.385934
3610 09:25:20.386016 TX Vref Scan disable
3611 09:25:20.386104 == TX Byte 0 ==
3612 09:25:20.386188 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3613 09:25:20.386274 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3614 09:25:20.386329 == TX Byte 1 ==
3615 09:25:20.386381 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3616 09:25:20.386447 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3617 09:25:20.386500
3618 09:25:20.386551 [DATLAT]
3619 09:25:20.386618 Freq=1200, CH1 RK1
3620 09:25:20.386709
3621 09:25:20.386790 DATLAT Default: 0xd
3622 09:25:20.386879 0, 0xFFFF, sum = 0
3623 09:25:20.386963 1, 0xFFFF, sum = 0
3624 09:25:20.387057 2, 0xFFFF, sum = 0
3625 09:25:20.387144 3, 0xFFFF, sum = 0
3626 09:25:20.387257 4, 0xFFFF, sum = 0
3627 09:25:20.387353 5, 0xFFFF, sum = 0
3628 09:25:20.387445 6, 0xFFFF, sum = 0
3629 09:25:20.387530 7, 0xFFFF, sum = 0
3630 09:25:20.387623 8, 0xFFFF, sum = 0
3631 09:25:20.387714 9, 0xFFFF, sum = 0
3632 09:25:20.387801 10, 0xFFFF, sum = 0
3633 09:25:20.387887 11, 0xFFFF, sum = 0
3634 09:25:20.387970 12, 0x0, sum = 1
3635 09:25:20.388068 13, 0x0, sum = 2
3636 09:25:20.388153 14, 0x0, sum = 3
3637 09:25:20.388240 15, 0x0, sum = 4
3638 09:25:20.388332 best_step = 13
3639 09:25:20.388419
3640 09:25:20.388514 ==
3641 09:25:20.388598 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 09:25:20.388686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 09:25:20.388768 ==
3644 09:25:20.388859 RX Vref Scan: 0
3645 09:25:20.388946
3646 09:25:20.389028 RX Vref 0 -> 0, step: 1
3647 09:25:20.389114
3648 09:25:20.389195 RX Delay -21 -> 252, step: 4
3649 09:25:20.389281 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3650 09:25:20.389347 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3651 09:25:20.389412 iDelay=199, Bit 2, Center 104 (39 ~ 170) 132
3652 09:25:20.389471 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3653 09:25:20.389549 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3654 09:25:20.389634 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3655 09:25:20.389723 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3656 09:25:20.389806 iDelay=199, Bit 7, Center 114 (51 ~ 178) 128
3657 09:25:20.389890 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3658 09:25:20.390213 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3659 09:25:20.390287 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3660 09:25:20.390360 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3661 09:25:20.390425 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3662 09:25:20.390497 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3663 09:25:20.390552 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3664 09:25:20.390605 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3665 09:25:20.390657 ==
3666 09:25:20.390757 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 09:25:20.390852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 09:25:20.390942 ==
3669 09:25:20.391030 DQS Delay:
3670 09:25:20.391114 DQS0 = 0, DQS1 = 0
3671 09:25:20.391200 DQM Delay:
3672 09:25:20.391281 DQM0 = 116, DQM1 = 110
3673 09:25:20.391374 DQ Delay:
3674 09:25:20.391456 DQ0 =120, DQ1 =110, DQ2 =104, DQ3 =114
3675 09:25:20.391547 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =114
3676 09:25:20.391630 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3677 09:25:20.391725 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =118
3678 09:25:20.391821
3679 09:25:20.391912
3680 09:25:20.392001 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4ef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3681 09:25:20.392090 CH1 RK1: MR19=303, MR18=F4EF
3682 09:25:20.392183 CH1_RK1: MR19=0x303, MR18=0xF4EF, DQSOSC=415, MR23=63, INC=38, DEC=25
3683 09:25:20.392278 [RxdqsGatingPostProcess] freq 1200
3684 09:25:20.392367 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3685 09:25:20.392451 best DQS0 dly(2T, 0.5T) = (0, 11)
3686 09:25:20.392537 best DQS1 dly(2T, 0.5T) = (0, 11)
3687 09:25:20.392620 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3688 09:25:20.392702 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3689 09:25:20.392789 best DQS0 dly(2T, 0.5T) = (0, 11)
3690 09:25:20.392870 best DQS1 dly(2T, 0.5T) = (0, 11)
3691 09:25:20.392956 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3692 09:25:20.393039 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3693 09:25:20.393127 Pre-setting of DQS Precalculation
3694 09:25:20.393217 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3695 09:25:20.393297 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3696 09:25:20.393354 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3697 09:25:20.393407
3698 09:25:20.393460
3699 09:25:20.393547 [Calibration Summary] 2400 Mbps
3700 09:25:20.393629 CH 0, Rank 0
3701 09:25:20.393721 SW Impedance : PASS
3702 09:25:20.393806 DUTY Scan : NO K
3703 09:25:20.393888 ZQ Calibration : PASS
3704 09:25:20.393974 Jitter Meter : NO K
3705 09:25:20.394057 CBT Training : PASS
3706 09:25:20.394142 Write leveling : PASS
3707 09:25:20.394225 RX DQS gating : PASS
3708 09:25:20.394278 RX DQ/DQS(RDDQC) : PASS
3709 09:25:20.394338 TX DQ/DQS : PASS
3710 09:25:20.394392 RX DATLAT : PASS
3711 09:25:20.394443 RX DQ/DQS(Engine): PASS
3712 09:25:20.394500 TX OE : NO K
3713 09:25:20.394556 All Pass.
3714 09:25:20.394608
3715 09:25:20.394659 CH 0, Rank 1
3716 09:25:20.394734 SW Impedance : PASS
3717 09:25:20.394818 DUTY Scan : NO K
3718 09:25:20.394909 ZQ Calibration : PASS
3719 09:25:20.395007 Jitter Meter : NO K
3720 09:25:20.395105 CBT Training : PASS
3721 09:25:20.395197 Write leveling : PASS
3722 09:25:20.395280 RX DQS gating : PASS
3723 09:25:20.395367 RX DQ/DQS(RDDQC) : PASS
3724 09:25:20.395449 TX DQ/DQS : PASS
3725 09:25:20.395535 RX DATLAT : PASS
3726 09:25:20.395618 RX DQ/DQS(Engine): PASS
3727 09:25:20.395699 TX OE : NO K
3728 09:25:20.395784 All Pass.
3729 09:25:20.395865
3730 09:25:20.395952 CH 1, Rank 0
3731 09:25:20.396034 SW Impedance : PASS
3732 09:25:20.396118 DUTY Scan : NO K
3733 09:25:20.396200 ZQ Calibration : PASS
3734 09:25:20.396281 Jitter Meter : NO K
3735 09:25:20.396372 CBT Training : PASS
3736 09:25:20.396455 Write leveling : PASS
3737 09:25:20.396537 RX DQS gating : PASS
3738 09:25:20.396621 RX DQ/DQS(RDDQC) : PASS
3739 09:25:20.396703 TX DQ/DQS : PASS
3740 09:25:20.396788 RX DATLAT : PASS
3741 09:25:20.396869 RX DQ/DQS(Engine): PASS
3742 09:25:20.396953 TX OE : NO K
3743 09:25:20.397037 All Pass.
3744 09:25:20.397118
3745 09:25:20.397203 CH 1, Rank 1
3746 09:25:20.397297 SW Impedance : PASS
3747 09:25:20.397370 DUTY Scan : NO K
3748 09:25:20.397423 ZQ Calibration : PASS
3749 09:25:20.397475 Jitter Meter : NO K
3750 09:25:20.397537 CBT Training : PASS
3751 09:25:20.397621 Write leveling : PASS
3752 09:25:20.397702 RX DQS gating : PASS
3753 09:25:20.397786 RX DQ/DQS(RDDQC) : PASS
3754 09:25:20.397869 TX DQ/DQS : PASS
3755 09:25:20.397951 RX DATLAT : PASS
3756 09:25:20.398036 RX DQ/DQS(Engine): PASS
3757 09:25:20.398117 TX OE : NO K
3758 09:25:20.398221 All Pass.
3759 09:25:20.398304
3760 09:25:20.398388 DramC Write-DBI off
3761 09:25:20.398470 PER_BANK_REFRESH: Hybrid Mode
3762 09:25:20.398557 TX_TRACKING: ON
3763 09:25:20.398644 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3764 09:25:20.398727 [FAST_K] Save calibration result to emmc
3765 09:25:20.398813 dramc_set_vcore_voltage set vcore to 650000
3766 09:25:20.398894 Read voltage for 600, 5
3767 09:25:20.398979 Vio18 = 0
3768 09:25:20.399063 Vcore = 650000
3769 09:25:20.399149 Vdram = 0
3770 09:25:20.399241 Vddq = 0
3771 09:25:20.399322 Vmddr = 0
3772 09:25:20.399405 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3773 09:25:20.399490 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3774 09:25:20.399572 MEM_TYPE=3, freq_sel=19
3775 09:25:20.399632 sv_algorithm_assistance_LP4_1600
3776 09:25:20.399685 ============ PULL DRAM RESETB DOWN ============
3777 09:25:20.399738 ========== PULL DRAM RESETB DOWN end =========
3778 09:25:20.399797 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3779 09:25:20.399851 ===================================
3780 09:25:20.399904 LPDDR4 DRAM CONFIGURATION
3781 09:25:20.399955 ===================================
3782 09:25:20.400034 EX_ROW_EN[0] = 0x0
3783 09:25:20.400121 EX_ROW_EN[1] = 0x0
3784 09:25:20.400212 LP4Y_EN = 0x0
3785 09:25:20.400297 WORK_FSP = 0x0
3786 09:25:20.400379 WL = 0x2
3787 09:25:20.400467 RL = 0x2
3788 09:25:20.400563 BL = 0x2
3789 09:25:20.400655 RPST = 0x0
3790 09:25:20.400746 RD_PRE = 0x0
3791 09:25:20.400831 WR_PRE = 0x1
3792 09:25:20.400913 WR_PST = 0x0
3793 09:25:20.400997 DBI_WR = 0x0
3794 09:25:20.401079 DBI_RD = 0x0
3795 09:25:20.401173 OTF = 0x1
3796 09:25:20.401271 ===================================
3797 09:25:20.401327 ===================================
3798 09:25:20.401380 ANA top config
3799 09:25:20.401468 ===================================
3800 09:25:20.401550 DLL_ASYNC_EN = 0
3801 09:25:20.401877 ALL_SLAVE_EN = 1
3802 09:25:20.401975 NEW_RANK_MODE = 1
3803 09:25:20.402065 DLL_IDLE_MODE = 1
3804 09:25:20.402150 LP45_APHY_COMB_EN = 1
3805 09:25:20.402224 TX_ODT_DIS = 1
3806 09:25:20.402284 NEW_8X_MODE = 1
3807 09:25:20.402338 ===================================
3808 09:25:20.402391 ===================================
3809 09:25:20.402448 data_rate = 1200
3810 09:25:20.402501 CKR = 1
3811 09:25:20.402553 DQ_P2S_RATIO = 8
3812 09:25:20.402605 ===================================
3813 09:25:20.402675 CA_P2S_RATIO = 8
3814 09:25:20.402729 DQ_CA_OPEN = 0
3815 09:25:20.402780 DQ_SEMI_OPEN = 0
3816 09:25:20.402837 CA_SEMI_OPEN = 0
3817 09:25:20.402911 CA_FULL_RATE = 0
3818 09:25:20.402995 DQ_CKDIV4_EN = 1
3819 09:25:20.403091 CA_CKDIV4_EN = 1
3820 09:25:20.403186 CA_PREDIV_EN = 0
3821 09:25:20.403282 PH8_DLY = 0
3822 09:25:20.403371 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3823 09:25:20.403457 DQ_AAMCK_DIV = 4
3824 09:25:20.403540 CA_AAMCK_DIV = 4
3825 09:25:20.403623 CA_ADMCK_DIV = 4
3826 09:25:20.403708 DQ_TRACK_CA_EN = 0
3827 09:25:20.403800 CA_PICK = 600
3828 09:25:20.403888 CA_MCKIO = 600
3829 09:25:20.403970 MCKIO_SEMI = 0
3830 09:25:20.404055 PLL_FREQ = 2288
3831 09:25:20.404138 DQ_UI_PI_RATIO = 32
3832 09:25:20.404221 CA_UI_PI_RATIO = 0
3833 09:25:20.404306 ===================================
3834 09:25:20.404389 ===================================
3835 09:25:20.404470 memory_type:LPDDR4
3836 09:25:20.404556 GP_NUM : 10
3837 09:25:20.404637 SRAM_EN : 1
3838 09:25:20.404722 MD32_EN : 0
3839 09:25:20.404804 ===================================
3840 09:25:20.404889 [ANA_INIT] >>>>>>>>>>>>>>
3841 09:25:20.404972 <<<<<< [CONFIGURE PHASE]: ANA_TX
3842 09:25:20.405055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3843 09:25:20.405140 ===================================
3844 09:25:20.405222 data_rate = 1200,PCW = 0X5800
3845 09:25:20.405295 ===================================
3846 09:25:20.405349 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3847 09:25:20.405401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3848 09:25:20.405458 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3849 09:25:20.405512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3850 09:25:20.405564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3851 09:25:20.405616 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3852 09:25:20.405693 [ANA_INIT] flow start
3853 09:25:20.405778 [ANA_INIT] PLL >>>>>>>>
3854 09:25:20.405859 [ANA_INIT] PLL <<<<<<<<
3855 09:25:20.405944 [ANA_INIT] MIDPI >>>>>>>>
3856 09:25:20.406026 [ANA_INIT] MIDPI <<<<<<<<
3857 09:25:20.406114 [ANA_INIT] DLL >>>>>>>>
3858 09:25:20.406193 [ANA_INIT] flow end
3859 09:25:20.406247 ============ LP4 DIFF to SE enter ============
3860 09:25:20.406306 ============ LP4 DIFF to SE exit ============
3861 09:25:20.406383 [ANA_INIT] <<<<<<<<<<<<<
3862 09:25:20.407474 [Flow] Enable top DCM control >>>>>
3863 09:25:20.410559 [Flow] Enable top DCM control <<<<<
3864 09:25:20.414023 Enable DLL master slave shuffle
3865 09:25:20.420823 ==============================================================
3866 09:25:20.420970 Gating Mode config
3867 09:25:20.426915 ==============================================================
3868 09:25:20.427055 Config description:
3869 09:25:20.437356 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3870 09:25:20.443602 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3871 09:25:20.450247 SELPH_MODE 0: By rank 1: By Phase
3872 09:25:20.453812 ==============================================================
3873 09:25:20.457288 GAT_TRACK_EN = 1
3874 09:25:20.460167 RX_GATING_MODE = 2
3875 09:25:20.463472 RX_GATING_TRACK_MODE = 2
3876 09:25:20.466841 SELPH_MODE = 1
3877 09:25:20.470318 PICG_EARLY_EN = 1
3878 09:25:20.473598 VALID_LAT_VALUE = 1
3879 09:25:20.479566 ==============================================================
3880 09:25:20.482858 Enter into Gating configuration >>>>
3881 09:25:20.486500 Exit from Gating configuration <<<<
3882 09:25:20.489834 Enter into DVFS_PRE_config >>>>>
3883 09:25:20.499392 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3884 09:25:20.503025 Exit from DVFS_PRE_config <<<<<
3885 09:25:20.505927 Enter into PICG configuration >>>>
3886 09:25:20.509554 Exit from PICG configuration <<<<
3887 09:25:20.512603 [RX_INPUT] configuration >>>>>
3888 09:25:20.516103 [RX_INPUT] configuration <<<<<
3889 09:25:20.519153 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3890 09:25:20.525704 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3891 09:25:20.532228 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3892 09:25:20.535816 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3893 09:25:20.542215 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3894 09:25:20.548895 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3895 09:25:20.552515 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3896 09:25:20.559078 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3897 09:25:20.562056 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3898 09:25:20.565245 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3899 09:25:20.568635 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3900 09:25:20.575546 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3901 09:25:20.578681 ===================================
3902 09:25:20.582191 LPDDR4 DRAM CONFIGURATION
3903 09:25:20.585149 ===================================
3904 09:25:20.585256 EX_ROW_EN[0] = 0x0
3905 09:25:20.588305 EX_ROW_EN[1] = 0x0
3906 09:25:20.588403 LP4Y_EN = 0x0
3907 09:25:20.591422 WORK_FSP = 0x0
3908 09:25:20.591528 WL = 0x2
3909 09:25:20.594732 RL = 0x2
3910 09:25:20.594829 BL = 0x2
3911 09:25:20.598066 RPST = 0x0
3912 09:25:20.598159 RD_PRE = 0x0
3913 09:25:20.601937 WR_PRE = 0x1
3914 09:25:20.602059 WR_PST = 0x0
3915 09:25:20.605164 DBI_WR = 0x0
3916 09:25:20.605278 DBI_RD = 0x0
3917 09:25:20.608046 OTF = 0x1
3918 09:25:20.611695 ===================================
3919 09:25:20.614982 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3920 09:25:20.617957 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3921 09:25:20.624685 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3922 09:25:20.628267 ===================================
3923 09:25:20.631241 LPDDR4 DRAM CONFIGURATION
3924 09:25:20.634388 ===================================
3925 09:25:20.634522 EX_ROW_EN[0] = 0x10
3926 09:25:20.637943 EX_ROW_EN[1] = 0x0
3927 09:25:20.638059 LP4Y_EN = 0x0
3928 09:25:20.640929 WORK_FSP = 0x0
3929 09:25:20.641039 WL = 0x2
3930 09:25:20.644413 RL = 0x2
3931 09:25:20.644531 BL = 0x2
3932 09:25:20.648015 RPST = 0x0
3933 09:25:20.648150 RD_PRE = 0x0
3934 09:25:20.651068 WR_PRE = 0x1
3935 09:25:20.651165 WR_PST = 0x0
3936 09:25:20.654649 DBI_WR = 0x0
3937 09:25:20.654799 DBI_RD = 0x0
3938 09:25:20.657915 OTF = 0x1
3939 09:25:20.660935 ===================================
3940 09:25:20.668061 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3941 09:25:20.671323 nWR fixed to 30
3942 09:25:20.674378 [ModeRegInit_LP4] CH0 RK0
3943 09:25:20.674505 [ModeRegInit_LP4] CH0 RK1
3944 09:25:20.677679 [ModeRegInit_LP4] CH1 RK0
3945 09:25:20.680821 [ModeRegInit_LP4] CH1 RK1
3946 09:25:20.680964 match AC timing 17
3947 09:25:20.687405 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3948 09:25:20.690834 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3949 09:25:20.694152 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3950 09:25:20.700965 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3951 09:25:20.703899 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3952 09:25:20.704007 ==
3953 09:25:20.707316 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 09:25:20.710173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 09:25:20.710285 ==
3956 09:25:20.717136 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3957 09:25:20.724002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3958 09:25:20.727061 [CA 0] Center 36 (6~66) winsize 61
3959 09:25:20.730059 [CA 1] Center 36 (6~66) winsize 61
3960 09:25:20.733552 [CA 2] Center 34 (4~65) winsize 62
3961 09:25:20.737141 [CA 3] Center 34 (3~65) winsize 63
3962 09:25:20.740168 [CA 4] Center 33 (3~64) winsize 62
3963 09:25:20.743806 [CA 5] Center 33 (3~64) winsize 62
3964 09:25:20.743951
3965 09:25:20.746800 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3966 09:25:20.746902
3967 09:25:20.750155 [CATrainingPosCal] consider 1 rank data
3968 09:25:20.753441 u2DelayCellTimex100 = 270/100 ps
3969 09:25:20.756972 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3970 09:25:20.760007 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3971 09:25:20.763664 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3972 09:25:20.769929 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3973 09:25:20.772957 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3974 09:25:20.776452 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3975 09:25:20.776572
3976 09:25:20.779891 CA PerBit enable=1, Macro0, CA PI delay=33
3977 09:25:20.779988
3978 09:25:20.782983 [CBTSetCACLKResult] CA Dly = 33
3979 09:25:20.783077 CS Dly: 5 (0~36)
3980 09:25:20.783149 ==
3981 09:25:20.786500 Dram Type= 6, Freq= 0, CH_0, rank 1
3982 09:25:20.792896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 09:25:20.793032 ==
3984 09:25:20.796210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3985 09:25:20.802954 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3986 09:25:20.806413 [CA 0] Center 36 (6~66) winsize 61
3987 09:25:20.809888 [CA 1] Center 36 (6~66) winsize 61
3988 09:25:20.812703 [CA 2] Center 33 (3~64) winsize 62
3989 09:25:20.816201 [CA 3] Center 33 (3~64) winsize 62
3990 09:25:20.819991 [CA 4] Center 33 (2~64) winsize 63
3991 09:25:20.822798 [CA 5] Center 33 (2~64) winsize 63
3992 09:25:20.822893
3993 09:25:20.826253 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3994 09:25:20.826350
3995 09:25:20.829624 [CATrainingPosCal] consider 2 rank data
3996 09:25:20.832905 u2DelayCellTimex100 = 270/100 ps
3997 09:25:20.836270 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3998 09:25:20.842974 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3999 09:25:20.845904 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4000 09:25:20.849616 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 09:25:20.852571 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4002 09:25:20.856123 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4003 09:25:20.856283
4004 09:25:20.859091 CA PerBit enable=1, Macro0, CA PI delay=33
4005 09:25:20.859212
4006 09:25:20.862758 [CBTSetCACLKResult] CA Dly = 33
4007 09:25:20.865861 CS Dly: 6 (0~38)
4008 09:25:20.865993
4009 09:25:20.869378 ----->DramcWriteLeveling(PI) begin...
4010 09:25:20.869505 ==
4011 09:25:20.872450 Dram Type= 6, Freq= 0, CH_0, rank 0
4012 09:25:20.875657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 09:25:20.875796 ==
4014 09:25:20.879368 Write leveling (Byte 0): 33 => 33
4015 09:25:20.882208 Write leveling (Byte 1): 30 => 30
4016 09:25:20.885328 DramcWriteLeveling(PI) end<-----
4017 09:25:20.885459
4018 09:25:20.885556 ==
4019 09:25:20.888768 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 09:25:20.892270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 09:25:20.892408 ==
4022 09:25:20.895766 [Gating] SW mode calibration
4023 09:25:20.902445 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4024 09:25:20.908867 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4025 09:25:20.911981 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 09:25:20.915394 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4027 09:25:20.921611 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4028 09:25:20.925255 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4029 09:25:20.928763 0 9 16 | B1->B0 | 3030 2929 | 0 0 | (0 0) (1 1)
4030 09:25:20.935175 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 09:25:20.938808 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 09:25:20.941216 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 09:25:20.948197 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 09:25:20.951957 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 09:25:20.954954 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 09:25:20.961903 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4037 09:25:20.964905 0 10 16 | B1->B0 | 3535 4040 | 0 0 | (0 0) (0 0)
4038 09:25:20.968039 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 09:25:20.974682 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 09:25:20.978236 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 09:25:20.981233 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 09:25:20.988249 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 09:25:20.991304 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 09:25:20.994392 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 09:25:21.001220 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 09:25:21.004852 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 09:25:21.007689 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 09:25:21.014316 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 09:25:21.017952 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 09:25:21.020950 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 09:25:21.027540 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 09:25:21.031188 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 09:25:21.034307 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 09:25:21.040979 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 09:25:21.043845 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 09:25:21.046991 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 09:25:21.053706 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 09:25:21.057114 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 09:25:21.060628 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 09:25:21.067213 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4061 09:25:21.070753 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4062 09:25:21.073617 Total UI for P1: 0, mck2ui 16
4063 09:25:21.076732 best dqsien dly found for B0: ( 0, 13, 12)
4064 09:25:21.080320 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 09:25:21.083373 Total UI for P1: 0, mck2ui 16
4066 09:25:21.086921 best dqsien dly found for B1: ( 0, 13, 14)
4067 09:25:21.090134 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4068 09:25:21.093616 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4069 09:25:21.093758
4070 09:25:21.099868 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4071 09:25:21.103395 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4072 09:25:21.106802 [Gating] SW calibration Done
4073 09:25:21.106926 ==
4074 09:25:21.110369 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 09:25:21.113519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 09:25:21.113630 ==
4077 09:25:21.113697 RX Vref Scan: 0
4078 09:25:21.113789
4079 09:25:21.116428 RX Vref 0 -> 0, step: 1
4080 09:25:21.116544
4081 09:25:21.119942 RX Delay -230 -> 252, step: 16
4082 09:25:21.123338 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4083 09:25:21.129651 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4084 09:25:21.133193 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4085 09:25:21.136155 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4086 09:25:21.139855 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4087 09:25:21.142896 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4088 09:25:21.149656 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4089 09:25:21.152725 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4090 09:25:21.156123 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4091 09:25:21.159652 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4092 09:25:21.166118 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4093 09:25:21.169628 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4094 09:25:21.172586 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4095 09:25:21.176364 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4096 09:25:21.182757 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4097 09:25:21.186050 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4098 09:25:21.186201 ==
4099 09:25:21.189458 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 09:25:21.192428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 09:25:21.192535 ==
4102 09:25:21.196002 DQS Delay:
4103 09:25:21.196112 DQS0 = 0, DQS1 = 0
4104 09:25:21.196178 DQM Delay:
4105 09:25:21.198945 DQM0 = 41, DQM1 = 29
4106 09:25:21.199090 DQ Delay:
4107 09:25:21.202381 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4108 09:25:21.205796 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4109 09:25:21.209166 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4110 09:25:21.212152 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4111 09:25:21.212297
4112 09:25:21.212395
4113 09:25:21.212490 ==
4114 09:25:21.215753 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 09:25:21.222227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 09:25:21.222406 ==
4117 09:25:21.222504
4118 09:25:21.222592
4119 09:25:21.222679 TX Vref Scan disable
4120 09:25:21.226107 == TX Byte 0 ==
4121 09:25:21.229042 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4122 09:25:21.235988 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4123 09:25:21.236168 == TX Byte 1 ==
4124 09:25:21.238899 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4125 09:25:21.245587 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4126 09:25:21.245765 ==
4127 09:25:21.248955 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 09:25:21.252277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 09:25:21.252417 ==
4130 09:25:21.252511
4131 09:25:21.252598
4132 09:25:21.255469 TX Vref Scan disable
4133 09:25:21.259152 == TX Byte 0 ==
4134 09:25:21.262478 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4135 09:25:21.265241 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4136 09:25:21.268448 == TX Byte 1 ==
4137 09:25:21.272381 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4138 09:25:21.275548 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4139 09:25:21.275687
4140 09:25:21.278965 [DATLAT]
4141 09:25:21.279090 Freq=600, CH0 RK0
4142 09:25:21.279185
4143 09:25:21.282047 DATLAT Default: 0x9
4144 09:25:21.282167 0, 0xFFFF, sum = 0
4145 09:25:21.285183 1, 0xFFFF, sum = 0
4146 09:25:21.285303 2, 0xFFFF, sum = 0
4147 09:25:21.288879 3, 0xFFFF, sum = 0
4148 09:25:21.289021 4, 0xFFFF, sum = 0
4149 09:25:21.291798 5, 0xFFFF, sum = 0
4150 09:25:21.291927 6, 0xFFFF, sum = 0
4151 09:25:21.295489 7, 0xFFFF, sum = 0
4152 09:25:21.295624 8, 0x0, sum = 1
4153 09:25:21.298418 9, 0x0, sum = 2
4154 09:25:21.298535 10, 0x0, sum = 3
4155 09:25:21.301918 11, 0x0, sum = 4
4156 09:25:21.302041 best_step = 9
4157 09:25:21.302134
4158 09:25:21.302261 ==
4159 09:25:21.305185 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 09:25:21.308208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 09:25:21.311632 ==
4162 09:25:21.311780 RX Vref Scan: 1
4163 09:25:21.311878
4164 09:25:21.314826 RX Vref 0 -> 0, step: 1
4165 09:25:21.314955
4166 09:25:21.318136 RX Delay -195 -> 252, step: 8
4167 09:25:21.318301
4168 09:25:21.321545 Set Vref, RX VrefLevel [Byte0]: 61
4169 09:25:21.324583 [Byte1]: 49
4170 09:25:21.324719
4171 09:25:21.327672 Final RX Vref Byte 0 = 61 to rank0
4172 09:25:21.330933 Final RX Vref Byte 1 = 49 to rank0
4173 09:25:21.334608 Final RX Vref Byte 0 = 61 to rank1
4174 09:25:21.337969 Final RX Vref Byte 1 = 49 to rank1==
4175 09:25:21.340972 Dram Type= 6, Freq= 0, CH_0, rank 0
4176 09:25:21.344606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 09:25:21.344747 ==
4178 09:25:21.347572 DQS Delay:
4179 09:25:21.347712 DQS0 = 0, DQS1 = 0
4180 09:25:21.347807 DQM Delay:
4181 09:25:21.351072 DQM0 = 43, DQM1 = 32
4182 09:25:21.351194 DQ Delay:
4183 09:25:21.354082 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4184 09:25:21.357759 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4185 09:25:21.361026 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4186 09:25:21.364158 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4187 09:25:21.364298
4188 09:25:21.364395
4189 09:25:21.374061 [DQSOSCAuto] RK0, (LSB)MR18= 0x6940, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4190 09:25:21.377377 CH0 RK0: MR19=808, MR18=6940
4191 09:25:21.380510 CH0_RK0: MR19=0x808, MR18=0x6940, DQSOSC=390, MR23=63, INC=172, DEC=114
4192 09:25:21.383973
4193 09:25:21.387232 ----->DramcWriteLeveling(PI) begin...
4194 09:25:21.387385 ==
4195 09:25:21.390348 Dram Type= 6, Freq= 0, CH_0, rank 1
4196 09:25:21.393835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 09:25:21.393972 ==
4198 09:25:21.396822 Write leveling (Byte 0): 33 => 33
4199 09:25:21.400451 Write leveling (Byte 1): 31 => 31
4200 09:25:21.403533 DramcWriteLeveling(PI) end<-----
4201 09:25:21.403682
4202 09:25:21.403780 ==
4203 09:25:21.407109 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 09:25:21.410064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 09:25:21.410226 ==
4206 09:25:21.413616 [Gating] SW mode calibration
4207 09:25:21.420085 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4208 09:25:21.426632 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4209 09:25:21.430133 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4210 09:25:21.433579 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4211 09:25:21.439562 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4212 09:25:21.443119 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
4213 09:25:21.446345 0 9 16 | B1->B0 | 2b2b 2a2a | 1 1 | (1 0) (1 0)
4214 09:25:21.452851 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 09:25:21.456560 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 09:25:21.459468 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 09:25:21.466054 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 09:25:21.469724 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 09:25:21.472575 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 09:25:21.479389 0 10 12 | B1->B0 | 2828 2929 | 0 0 | (0 0) (0 0)
4221 09:25:21.482675 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4222 09:25:21.485981 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 09:25:21.492768 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 09:25:21.495700 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 09:25:21.499255 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 09:25:21.505802 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 09:25:21.509264 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 09:25:21.512503 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4229 09:25:21.518929 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4230 09:25:21.521977 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 09:25:21.525695 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 09:25:21.531974 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 09:25:21.535411 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 09:25:21.538756 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 09:25:21.545297 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 09:25:21.548744 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 09:25:21.551673 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 09:25:21.558392 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 09:25:21.562045 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 09:25:21.565106 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 09:25:21.571543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 09:25:21.575218 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 09:25:21.577971 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 09:25:21.584861 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4245 09:25:21.587991 Total UI for P1: 0, mck2ui 16
4246 09:25:21.591816 best dqsien dly found for B1: ( 0, 13, 10)
4247 09:25:21.594502 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4248 09:25:21.598069 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 09:25:21.601357 Total UI for P1: 0, mck2ui 16
4250 09:25:21.604968 best dqsien dly found for B0: ( 0, 13, 14)
4251 09:25:21.608188 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4252 09:25:21.611344 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4253 09:25:21.614637
4254 09:25:21.617681 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4255 09:25:21.621240 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4256 09:25:21.624244 [Gating] SW calibration Done
4257 09:25:21.624380 ==
4258 09:25:21.627943 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 09:25:21.631115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 09:25:21.631243 ==
4261 09:25:21.631339 RX Vref Scan: 0
4262 09:25:21.634495
4263 09:25:21.634611 RX Vref 0 -> 0, step: 1
4264 09:25:21.634704
4265 09:25:21.637987 RX Delay -230 -> 252, step: 16
4266 09:25:21.640811 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4267 09:25:21.647983 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4268 09:25:21.650924 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4269 09:25:21.654058 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4270 09:25:21.657565 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4271 09:25:21.660988 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4272 09:25:21.667795 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4273 09:25:21.671437 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4274 09:25:21.674561 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4275 09:25:21.677436 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4276 09:25:21.684240 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4277 09:25:21.687336 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4278 09:25:21.690864 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4279 09:25:21.694207 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4280 09:25:21.700305 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4281 09:25:21.703801 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4282 09:25:21.703952 ==
4283 09:25:21.707370 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 09:25:21.710919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 09:25:21.711064 ==
4286 09:25:21.713985 DQS Delay:
4287 09:25:21.714085 DQS0 = 0, DQS1 = 0
4288 09:25:21.714150 DQM Delay:
4289 09:25:21.716969 DQM0 = 44, DQM1 = 35
4290 09:25:21.717060 DQ Delay:
4291 09:25:21.720320 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4292 09:25:21.723762 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4293 09:25:21.726760 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4294 09:25:21.730290 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4295 09:25:21.730450
4296 09:25:21.730547
4297 09:25:21.730635 ==
4298 09:25:21.733927 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 09:25:21.740404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 09:25:21.740585 ==
4301 09:25:21.740683
4302 09:25:21.740772
4303 09:25:21.740859 TX Vref Scan disable
4304 09:25:21.743896 == TX Byte 0 ==
4305 09:25:21.747563 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4306 09:25:21.753815 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4307 09:25:21.753996 == TX Byte 1 ==
4308 09:25:21.757442 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4309 09:25:21.763896 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4310 09:25:21.764077 ==
4311 09:25:21.767042 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 09:25:21.770578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 09:25:21.770729 ==
4314 09:25:21.770823
4315 09:25:21.770912
4316 09:25:21.773477 TX Vref Scan disable
4317 09:25:21.777405 == TX Byte 0 ==
4318 09:25:21.780276 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4319 09:25:21.783303 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4320 09:25:21.786940 == TX Byte 1 ==
4321 09:25:21.790473 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4322 09:25:21.793656 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4323 09:25:21.793785
4324 09:25:21.793878 [DATLAT]
4325 09:25:21.796575 Freq=600, CH0 RK1
4326 09:25:21.796686
4327 09:25:21.800146 DATLAT Default: 0x9
4328 09:25:21.800271 0, 0xFFFF, sum = 0
4329 09:25:21.803469 1, 0xFFFF, sum = 0
4330 09:25:21.803588 2, 0xFFFF, sum = 0
4331 09:25:21.806555 3, 0xFFFF, sum = 0
4332 09:25:21.806676 4, 0xFFFF, sum = 0
4333 09:25:21.809946 5, 0xFFFF, sum = 0
4334 09:25:21.810076 6, 0xFFFF, sum = 0
4335 09:25:21.813327 7, 0xFFFF, sum = 0
4336 09:25:21.813461 8, 0x0, sum = 1
4337 09:25:21.816440 9, 0x0, sum = 2
4338 09:25:21.816566 10, 0x0, sum = 3
4339 09:25:21.819999 11, 0x0, sum = 4
4340 09:25:21.820132 best_step = 9
4341 09:25:21.820227
4342 09:25:21.820315 ==
4343 09:25:21.823845 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 09:25:21.826334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 09:25:21.826450 ==
4346 09:25:21.829756 RX Vref Scan: 0
4347 09:25:21.829868
4348 09:25:21.833102 RX Vref 0 -> 0, step: 1
4349 09:25:21.833222
4350 09:25:21.833313 RX Delay -195 -> 252, step: 8
4351 09:25:21.841064 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4352 09:25:21.844093 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4353 09:25:21.847520 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4354 09:25:21.850955 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4355 09:25:21.857386 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4356 09:25:21.860759 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4357 09:25:21.863860 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4358 09:25:21.867388 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4359 09:25:21.873874 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4360 09:25:21.877549 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4361 09:25:21.880672 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4362 09:25:21.884021 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4363 09:25:21.890448 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4364 09:25:21.894017 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4365 09:25:21.897062 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4366 09:25:21.900444 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4367 09:25:21.900581 ==
4368 09:25:21.903460 Dram Type= 6, Freq= 0, CH_0, rank 1
4369 09:25:21.909933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 09:25:21.910105 ==
4371 09:25:21.910247 DQS Delay:
4372 09:25:21.913313 DQS0 = 0, DQS1 = 0
4373 09:25:21.913438 DQM Delay:
4374 09:25:21.913530 DQM0 = 41, DQM1 = 37
4375 09:25:21.916513 DQ Delay:
4376 09:25:21.920021 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4377 09:25:21.923518 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4378 09:25:21.926869 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4379 09:25:21.930120 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4380 09:25:21.930265
4381 09:25:21.930331
4382 09:25:21.936635 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f13, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4383 09:25:21.939719 CH0 RK1: MR19=808, MR18=5F13
4384 09:25:21.947020 CH0_RK1: MR19=0x808, MR18=0x5F13, DQSOSC=391, MR23=63, INC=171, DEC=114
4385 09:25:21.949723 [RxdqsGatingPostProcess] freq 600
4386 09:25:21.956548 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4387 09:25:21.956734 Pre-setting of DQS Precalculation
4388 09:25:21.963184 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4389 09:25:21.963361 ==
4390 09:25:21.966019 Dram Type= 6, Freq= 0, CH_1, rank 0
4391 09:25:21.969690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 09:25:21.969830 ==
4393 09:25:21.976187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 09:25:21.982708 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4395 09:25:21.986147 [CA 0] Center 35 (5~66) winsize 62
4396 09:25:21.989578 [CA 1] Center 35 (5~66) winsize 62
4397 09:25:21.993055 [CA 2] Center 34 (4~65) winsize 62
4398 09:25:21.995987 [CA 3] Center 33 (3~64) winsize 62
4399 09:25:21.999607 [CA 4] Center 34 (4~65) winsize 62
4400 09:25:22.002606 [CA 5] Center 33 (3~64) winsize 62
4401 09:25:22.002739
4402 09:25:22.005733 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4403 09:25:22.005857
4404 09:25:22.009292 [CATrainingPosCal] consider 1 rank data
4405 09:25:22.012261 u2DelayCellTimex100 = 270/100 ps
4406 09:25:22.015344 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4407 09:25:22.018793 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4408 09:25:22.022492 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 09:25:22.025558 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4410 09:25:22.028745 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4411 09:25:22.035381 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 09:25:22.035560
4413 09:25:22.039151 CA PerBit enable=1, Macro0, CA PI delay=33
4414 09:25:22.039289
4415 09:25:22.042018 [CBTSetCACLKResult] CA Dly = 33
4416 09:25:22.042149 CS Dly: 3 (0~34)
4417 09:25:22.042267 ==
4418 09:25:22.045339 Dram Type= 6, Freq= 0, CH_1, rank 1
4419 09:25:22.048523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 09:25:22.051894 ==
4421 09:25:22.055075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4422 09:25:22.062072 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4423 09:25:22.065046 [CA 0] Center 35 (5~66) winsize 62
4424 09:25:22.068276 [CA 1] Center 36 (6~66) winsize 61
4425 09:25:22.071960 [CA 2] Center 34 (4~65) winsize 62
4426 09:25:22.075003 [CA 3] Center 34 (3~65) winsize 63
4427 09:25:22.078509 [CA 4] Center 34 (3~65) winsize 63
4428 09:25:22.081769 [CA 5] Center 34 (4~65) winsize 62
4429 09:25:22.081882
4430 09:25:22.084890 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4431 09:25:22.084984
4432 09:25:22.088469 [CATrainingPosCal] consider 2 rank data
4433 09:25:22.091465 u2DelayCellTimex100 = 270/100 ps
4434 09:25:22.095370 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4435 09:25:22.097934 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4436 09:25:22.101471 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4437 09:25:22.108142 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4438 09:25:22.111302 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4439 09:25:22.114854 CA5 delay=34 (4~64),Diff = 1 PI (9 cell)
4440 09:25:22.114980
4441 09:25:22.117889 CA PerBit enable=1, Macro0, CA PI delay=33
4442 09:25:22.117984
4443 09:25:22.121456 [CBTSetCACLKResult] CA Dly = 33
4444 09:25:22.121559 CS Dly: 4 (0~36)
4445 09:25:22.121626
4446 09:25:22.124456 ----->DramcWriteLeveling(PI) begin...
4447 09:25:22.128003 ==
4448 09:25:22.131062 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 09:25:22.134326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 09:25:22.134447 ==
4451 09:25:22.137553 Write leveling (Byte 0): 29 => 29
4452 09:25:22.141253 Write leveling (Byte 1): 29 => 29
4453 09:25:22.144356 DramcWriteLeveling(PI) end<-----
4454 09:25:22.144472
4455 09:25:22.144535 ==
4456 09:25:22.148045 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 09:25:22.151633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 09:25:22.151754 ==
4459 09:25:22.154478 [Gating] SW mode calibration
4460 09:25:22.161158 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4461 09:25:22.167640 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4462 09:25:22.170656 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 09:25:22.174225 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4464 09:25:22.180780 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4465 09:25:22.183805 0 9 12 | B1->B0 | 3333 3030 | 1 0 | (0 0) (1 0)
4466 09:25:22.187346 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4467 09:25:22.193680 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 09:25:22.197227 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 09:25:22.200635 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 09:25:22.206928 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 09:25:22.210614 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 09:25:22.213590 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 09:25:22.220335 0 10 12 | B1->B0 | 2d2d 3939 | 1 0 | (0 0) (0 0)
4474 09:25:22.223294 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 09:25:22.226892 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 09:25:22.233398 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 09:25:22.237053 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 09:25:22.239821 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 09:25:22.246643 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 09:25:22.250344 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 09:25:22.253237 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4482 09:25:22.259475 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 09:25:22.263032 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 09:25:22.266433 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 09:25:22.272852 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 09:25:22.276233 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 09:25:22.279488 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 09:25:22.286458 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 09:25:22.289294 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 09:25:22.292985 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 09:25:22.299630 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 09:25:22.302500 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 09:25:22.305870 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 09:25:22.312541 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 09:25:22.316042 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 09:25:22.319200 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 09:25:22.325652 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4498 09:25:22.328666 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 09:25:22.332308 Total UI for P1: 0, mck2ui 16
4500 09:25:22.335350 best dqsien dly found for B0: ( 0, 13, 12)
4501 09:25:22.338891 Total UI for P1: 0, mck2ui 16
4502 09:25:22.341970 best dqsien dly found for B1: ( 0, 13, 14)
4503 09:25:22.345514 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4504 09:25:22.348732 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4505 09:25:22.348865
4506 09:25:22.351920 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4507 09:25:22.355127 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4508 09:25:22.358451 [Gating] SW calibration Done
4509 09:25:22.358577 ==
4510 09:25:22.361429 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 09:25:22.368354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 09:25:22.368501 ==
4513 09:25:22.368568 RX Vref Scan: 0
4514 09:25:22.368626
4515 09:25:22.371753 RX Vref 0 -> 0, step: 1
4516 09:25:22.371842
4517 09:25:22.374668 RX Delay -230 -> 252, step: 16
4518 09:25:22.378552 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4519 09:25:22.381254 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4520 09:25:22.384797 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4521 09:25:22.391596 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4522 09:25:22.394514 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4523 09:25:22.397735 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4524 09:25:22.400740 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4525 09:25:22.407939 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4526 09:25:22.410687 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4527 09:25:22.414014 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4528 09:25:22.417398 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4529 09:25:22.424116 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4530 09:25:22.427064 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4531 09:25:22.430138 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4532 09:25:22.433705 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4533 09:25:22.440201 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4534 09:25:22.440379 ==
4535 09:25:22.443819 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 09:25:22.446843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 09:25:22.446982 ==
4538 09:25:22.447079 DQS Delay:
4539 09:25:22.449900 DQS0 = 0, DQS1 = 0
4540 09:25:22.450027 DQM Delay:
4541 09:25:22.453497 DQM0 = 47, DQM1 = 39
4542 09:25:22.453619 DQ Delay:
4543 09:25:22.456483 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4544 09:25:22.460085 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4545 09:25:22.463356 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25
4546 09:25:22.466912 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4547 09:25:22.467070
4548 09:25:22.467166
4549 09:25:22.467255 ==
4550 09:25:22.470349 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 09:25:22.473122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 09:25:22.476383 ==
4553 09:25:22.476519
4554 09:25:22.476613
4555 09:25:22.476700 TX Vref Scan disable
4556 09:25:22.479636 == TX Byte 0 ==
4557 09:25:22.483239 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4558 09:25:22.489800 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4559 09:25:22.489981 == TX Byte 1 ==
4560 09:25:22.493336 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4561 09:25:22.500126 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4562 09:25:22.500309 ==
4563 09:25:22.503090 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 09:25:22.506337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 09:25:22.506464 ==
4566 09:25:22.506561
4567 09:25:22.506649
4568 09:25:22.509686 TX Vref Scan disable
4569 09:25:22.513072 == TX Byte 0 ==
4570 09:25:22.516019 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4571 09:25:22.519458 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4572 09:25:22.522753 == TX Byte 1 ==
4573 09:25:22.526100 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4574 09:25:22.529645 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4575 09:25:22.529794
4576 09:25:22.529889 [DATLAT]
4577 09:25:22.532690 Freq=600, CH1 RK0
4578 09:25:22.532804
4579 09:25:22.536082 DATLAT Default: 0x9
4580 09:25:22.536202 0, 0xFFFF, sum = 0
4581 09:25:22.539030 1, 0xFFFF, sum = 0
4582 09:25:22.539153 2, 0xFFFF, sum = 0
4583 09:25:22.542644 3, 0xFFFF, sum = 0
4584 09:25:22.542794 4, 0xFFFF, sum = 0
4585 09:25:22.545747 5, 0xFFFF, sum = 0
4586 09:25:22.545863 6, 0xFFFF, sum = 0
4587 09:25:22.548728 7, 0xFFFF, sum = 0
4588 09:25:22.548844 8, 0x0, sum = 1
4589 09:25:22.552441 9, 0x0, sum = 2
4590 09:25:22.552561 10, 0x0, sum = 3
4591 09:25:22.555471 11, 0x0, sum = 4
4592 09:25:22.555566 best_step = 9
4593 09:25:22.555630
4594 09:25:22.555687 ==
4595 09:25:22.558973 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 09:25:22.561920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 09:25:22.562042 ==
4598 09:25:22.565576 RX Vref Scan: 1
4599 09:25:22.565674
4600 09:25:22.569007 RX Vref 0 -> 0, step: 1
4601 09:25:22.569138
4602 09:25:22.569233 RX Delay -179 -> 252, step: 8
4603 09:25:22.572089
4604 09:25:22.572213 Set Vref, RX VrefLevel [Byte0]: 46
4605 09:25:22.575478 [Byte1]: 53
4606 09:25:22.580172
4607 09:25:22.580306 Final RX Vref Byte 0 = 46 to rank0
4608 09:25:22.583458 Final RX Vref Byte 1 = 53 to rank0
4609 09:25:22.586832 Final RX Vref Byte 0 = 46 to rank1
4610 09:25:22.590661 Final RX Vref Byte 1 = 53 to rank1==
4611 09:25:22.593271 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 09:25:22.599974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 09:25:22.600144 ==
4614 09:25:22.600218 DQS Delay:
4615 09:25:22.600278 DQS0 = 0, DQS1 = 0
4616 09:25:22.603688 DQM Delay:
4617 09:25:22.603793 DQM0 = 47, DQM1 = 36
4618 09:25:22.606937 DQ Delay:
4619 09:25:22.610349 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =44
4620 09:25:22.613364 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =40
4621 09:25:22.616569 DQ8 =28, DQ9 =28, DQ10 =36, DQ11 =28
4622 09:25:22.620458 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4623 09:25:22.620584
4624 09:25:22.620649
4625 09:25:22.626634 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e32, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4626 09:25:22.629825 CH1 RK0: MR19=808, MR18=4E32
4627 09:25:22.636573 CH1_RK0: MR19=0x808, MR18=0x4E32, DQSOSC=395, MR23=63, INC=168, DEC=112
4628 09:25:22.636700
4629 09:25:22.640136 ----->DramcWriteLeveling(PI) begin...
4630 09:25:22.640222 ==
4631 09:25:22.643220 Dram Type= 6, Freq= 0, CH_1, rank 1
4632 09:25:22.646821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 09:25:22.646918 ==
4634 09:25:22.649715 Write leveling (Byte 0): 27 => 27
4635 09:25:22.653484 Write leveling (Byte 1): 30 => 30
4636 09:25:22.656429 DramcWriteLeveling(PI) end<-----
4637 09:25:22.656546
4638 09:25:22.656634 ==
4639 09:25:22.659482 Dram Type= 6, Freq= 0, CH_1, rank 1
4640 09:25:22.662872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 09:25:22.662992 ==
4642 09:25:22.666096 [Gating] SW mode calibration
4643 09:25:22.673035 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4644 09:25:22.679409 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4645 09:25:22.682715 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 09:25:22.689261 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4647 09:25:22.692508 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4648 09:25:22.695940 0 9 12 | B1->B0 | 3030 3232 | 1 1 | (0 0) (1 0)
4649 09:25:22.702342 0 9 16 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
4650 09:25:22.705962 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 09:25:22.708984 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 09:25:22.715601 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 09:25:22.719261 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 09:25:22.722349 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 09:25:22.728814 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 09:25:22.731792 0 10 12 | B1->B0 | 3636 2a2a | 0 0 | (1 1) (0 0)
4657 09:25:22.735741 0 10 16 | B1->B0 | 4141 4040 | 0 0 | (0 0) (0 0)
4658 09:25:22.741965 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 09:25:22.745197 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 09:25:22.748653 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 09:25:22.755285 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 09:25:22.758418 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 09:25:22.761633 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 09:25:22.768265 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4665 09:25:22.771858 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4666 09:25:22.774962 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 09:25:22.781239 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 09:25:22.784866 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 09:25:22.787992 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 09:25:22.794499 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 09:25:22.797823 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 09:25:22.801303 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 09:25:22.807643 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 09:25:22.811262 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 09:25:22.814280 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 09:25:22.820922 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 09:25:22.824642 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 09:25:22.827628 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 09:25:22.834244 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 09:25:22.837940 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4681 09:25:22.840824 Total UI for P1: 0, mck2ui 16
4682 09:25:22.844152 best dqsien dly found for B1: ( 0, 13, 10)
4683 09:25:22.847456 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 09:25:22.850674 Total UI for P1: 0, mck2ui 16
4685 09:25:22.853848 best dqsien dly found for B0: ( 0, 13, 12)
4686 09:25:22.857387 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4687 09:25:22.860519 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4688 09:25:22.863720
4689 09:25:22.867027 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4690 09:25:22.870796 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4691 09:25:22.873640 [Gating] SW calibration Done
4692 09:25:22.873739 ==
4693 09:25:22.877262 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 09:25:22.880248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 09:25:22.880345 ==
4696 09:25:22.880422 RX Vref Scan: 0
4697 09:25:22.883851
4698 09:25:22.883957 RX Vref 0 -> 0, step: 1
4699 09:25:22.884023
4700 09:25:22.886831 RX Delay -230 -> 252, step: 16
4701 09:25:22.890249 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4702 09:25:22.896984 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4703 09:25:22.900160 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4704 09:25:22.903713 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4705 09:25:22.906372 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4706 09:25:22.913382 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4707 09:25:22.916500 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4708 09:25:22.919564 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4709 09:25:22.923083 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4710 09:25:22.926626 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4711 09:25:22.932667 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4712 09:25:22.936341 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4713 09:25:22.939989 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4714 09:25:22.942865 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4715 09:25:22.949269 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4716 09:25:22.952445 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4717 09:25:22.952599 ==
4718 09:25:22.955766 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 09:25:22.959603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 09:25:22.959740 ==
4721 09:25:22.962318 DQS Delay:
4722 09:25:22.962431 DQS0 = 0, DQS1 = 0
4723 09:25:22.965867 DQM Delay:
4724 09:25:22.965980 DQM0 = 45, DQM1 = 39
4725 09:25:22.966076 DQ Delay:
4726 09:25:22.969004 DQ0 =57, DQ1 =41, DQ2 =25, DQ3 =41
4727 09:25:22.972632 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4728 09:25:22.975763 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =33
4729 09:25:22.979332 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4730 09:25:22.979459
4731 09:25:22.979552
4732 09:25:22.982244 ==
4733 09:25:22.982355 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 09:25:22.988805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 09:25:22.988954 ==
4736 09:25:22.989051
4737 09:25:22.989140
4738 09:25:22.992232 TX Vref Scan disable
4739 09:25:22.992347 == TX Byte 0 ==
4740 09:25:22.998866 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4741 09:25:23.001854 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4742 09:25:23.001980 == TX Byte 1 ==
4743 09:25:23.008510 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4744 09:25:23.012054 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4745 09:25:23.012184 ==
4746 09:25:23.015581 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 09:25:23.018672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 09:25:23.018799 ==
4749 09:25:23.018895
4750 09:25:23.018984
4751 09:25:23.022038 TX Vref Scan disable
4752 09:25:23.025248 == TX Byte 0 ==
4753 09:25:23.028676 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4754 09:25:23.031768 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4755 09:25:23.035215 == TX Byte 1 ==
4756 09:25:23.038174 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4757 09:25:23.041758 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4758 09:25:23.044834
4759 09:25:23.044941 [DATLAT]
4760 09:25:23.045007 Freq=600, CH1 RK1
4761 09:25:23.045068
4762 09:25:23.047864 DATLAT Default: 0x9
4763 09:25:23.047953 0, 0xFFFF, sum = 0
4764 09:25:23.051511 1, 0xFFFF, sum = 0
4765 09:25:23.051639 2, 0xFFFF, sum = 0
4766 09:25:23.054797 3, 0xFFFF, sum = 0
4767 09:25:23.058077 4, 0xFFFF, sum = 0
4768 09:25:23.058211 5, 0xFFFF, sum = 0
4769 09:25:23.061361 6, 0xFFFF, sum = 0
4770 09:25:23.061475 7, 0xFFFF, sum = 0
4771 09:25:23.064922 8, 0x0, sum = 1
4772 09:25:23.065050 9, 0x0, sum = 2
4773 09:25:23.065144 10, 0x0, sum = 3
4774 09:25:23.067788 11, 0x0, sum = 4
4775 09:25:23.067901 best_step = 9
4776 09:25:23.067994
4777 09:25:23.068084 ==
4778 09:25:23.071545 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 09:25:23.078291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 09:25:23.078450 ==
4781 09:25:23.078546 RX Vref Scan: 0
4782 09:25:23.078638
4783 09:25:23.081254 RX Vref 0 -> 0, step: 1
4784 09:25:23.081360
4785 09:25:23.084373 RX Delay -195 -> 252, step: 8
4786 09:25:23.088131 iDelay=213, Bit 0, Center 52 (-91 ~ 196) 288
4787 09:25:23.094467 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4788 09:25:23.098065 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4789 09:25:23.101007 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4790 09:25:23.104526 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4791 09:25:23.110784 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4792 09:25:23.114315 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4793 09:25:23.117502 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4794 09:25:23.120833 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4795 09:25:23.124543 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4796 09:25:23.130455 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4797 09:25:23.134111 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4798 09:25:23.137140 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4799 09:25:23.140357 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4800 09:25:23.146944 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4801 09:25:23.150455 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4802 09:25:23.150611 ==
4803 09:25:23.153502 Dram Type= 6, Freq= 0, CH_1, rank 1
4804 09:25:23.157315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4805 09:25:23.157421 ==
4806 09:25:23.160053 DQS Delay:
4807 09:25:23.160142 DQS0 = 0, DQS1 = 0
4808 09:25:23.163706 DQM Delay:
4809 09:25:23.163799 DQM0 = 45, DQM1 = 37
4810 09:25:23.163874 DQ Delay:
4811 09:25:23.166851 DQ0 =52, DQ1 =40, DQ2 =32, DQ3 =40
4812 09:25:23.169939 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =40
4813 09:25:23.173878 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4814 09:25:23.176739 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4815 09:25:23.176831
4816 09:25:23.176900
4817 09:25:23.186470 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4818 09:25:23.190011 CH1 RK1: MR19=808, MR18=2C21
4819 09:25:23.196384 CH1_RK1: MR19=0x808, MR18=0x2C21, DQSOSC=401, MR23=63, INC=163, DEC=108
4820 09:25:23.199826 [RxdqsGatingPostProcess] freq 600
4821 09:25:23.202919 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4822 09:25:23.206424 Pre-setting of DQS Precalculation
4823 09:25:23.212919 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4824 09:25:23.219923 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4825 09:25:23.226369 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4826 09:25:23.226530
4827 09:25:23.226629
4828 09:25:23.229198 [Calibration Summary] 1200 Mbps
4829 09:25:23.229286 CH 0, Rank 0
4830 09:25:23.233028 SW Impedance : PASS
4831 09:25:23.235799 DUTY Scan : NO K
4832 09:25:23.235916 ZQ Calibration : PASS
4833 09:25:23.239219 Jitter Meter : NO K
4834 09:25:23.242497 CBT Training : PASS
4835 09:25:23.242626 Write leveling : PASS
4836 09:25:23.246051 RX DQS gating : PASS
4837 09:25:23.246186 RX DQ/DQS(RDDQC) : PASS
4838 09:25:23.249163 TX DQ/DQS : PASS
4839 09:25:23.252290 RX DATLAT : PASS
4840 09:25:23.252435 RX DQ/DQS(Engine): PASS
4841 09:25:23.256055 TX OE : NO K
4842 09:25:23.256196 All Pass.
4843 09:25:23.256291
4844 09:25:23.259066 CH 0, Rank 1
4845 09:25:23.259177 SW Impedance : PASS
4846 09:25:23.262525 DUTY Scan : NO K
4847 09:25:23.265673 ZQ Calibration : PASS
4848 09:25:23.265802 Jitter Meter : NO K
4849 09:25:23.268790 CBT Training : PASS
4850 09:25:23.272394 Write leveling : PASS
4851 09:25:23.272531 RX DQS gating : PASS
4852 09:25:23.275345 RX DQ/DQS(RDDQC) : PASS
4853 09:25:23.278813 TX DQ/DQS : PASS
4854 09:25:23.278931 RX DATLAT : PASS
4855 09:25:23.282181 RX DQ/DQS(Engine): PASS
4856 09:25:23.285807 TX OE : NO K
4857 09:25:23.285927 All Pass.
4858 09:25:23.286017
4859 09:25:23.286102 CH 1, Rank 0
4860 09:25:23.288807 SW Impedance : PASS
4861 09:25:23.292166 DUTY Scan : NO K
4862 09:25:23.292279 ZQ Calibration : PASS
4863 09:25:23.295747 Jitter Meter : NO K
4864 09:25:23.298509 CBT Training : PASS
4865 09:25:23.298613 Write leveling : PASS
4866 09:25:23.301830 RX DQS gating : PASS
4867 09:25:23.305361 RX DQ/DQS(RDDQC) : PASS
4868 09:25:23.305472 TX DQ/DQS : PASS
4869 09:25:23.308488 RX DATLAT : PASS
4870 09:25:23.308596 RX DQ/DQS(Engine): PASS
4871 09:25:23.312210 TX OE : NO K
4872 09:25:23.312322 All Pass.
4873 09:25:23.312416
4874 09:25:23.315295 CH 1, Rank 1
4875 09:25:23.318815 SW Impedance : PASS
4876 09:25:23.318925 DUTY Scan : NO K
4877 09:25:23.321792 ZQ Calibration : PASS
4878 09:25:23.321902 Jitter Meter : NO K
4879 09:25:23.325126 CBT Training : PASS
4880 09:25:23.328605 Write leveling : PASS
4881 09:25:23.328717 RX DQS gating : PASS
4882 09:25:23.331684 RX DQ/DQS(RDDQC) : PASS
4883 09:25:23.334909 TX DQ/DQS : PASS
4884 09:25:23.335017 RX DATLAT : PASS
4885 09:25:23.338557 RX DQ/DQS(Engine): PASS
4886 09:25:23.341851 TX OE : NO K
4887 09:25:23.341969 All Pass.
4888 09:25:23.342063
4889 09:25:23.345003 DramC Write-DBI off
4890 09:25:23.345112 PER_BANK_REFRESH: Hybrid Mode
4891 09:25:23.348212 TX_TRACKING: ON
4892 09:25:23.354705 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4893 09:25:23.361453 [FAST_K] Save calibration result to emmc
4894 09:25:23.364796 dramc_set_vcore_voltage set vcore to 662500
4895 09:25:23.364928 Read voltage for 933, 3
4896 09:25:23.368288 Vio18 = 0
4897 09:25:23.368407 Vcore = 662500
4898 09:25:23.368505 Vdram = 0
4899 09:25:23.371405 Vddq = 0
4900 09:25:23.371514 Vmddr = 0
4901 09:25:23.375018 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4902 09:25:23.381012 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4903 09:25:23.384706 MEM_TYPE=3, freq_sel=17
4904 09:25:23.388159 sv_algorithm_assistance_LP4_1600
4905 09:25:23.390883 ============ PULL DRAM RESETB DOWN ============
4906 09:25:23.394667 ========== PULL DRAM RESETB DOWN end =========
4907 09:25:23.400874 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4908 09:25:23.404278 ===================================
4909 09:25:23.404362 LPDDR4 DRAM CONFIGURATION
4910 09:25:23.407378 ===================================
4911 09:25:23.410744 EX_ROW_EN[0] = 0x0
4912 09:25:23.414289 EX_ROW_EN[1] = 0x0
4913 09:25:23.414384 LP4Y_EN = 0x0
4914 09:25:23.417274 WORK_FSP = 0x0
4915 09:25:23.417371 WL = 0x3
4916 09:25:23.420594 RL = 0x3
4917 09:25:23.420683 BL = 0x2
4918 09:25:23.424120 RPST = 0x0
4919 09:25:23.424209 RD_PRE = 0x0
4920 09:25:23.427186 WR_PRE = 0x1
4921 09:25:23.427271 WR_PST = 0x0
4922 09:25:23.430859 DBI_WR = 0x0
4923 09:25:23.430951 DBI_RD = 0x0
4924 09:25:23.433984 OTF = 0x1
4925 09:25:23.436861 ===================================
4926 09:25:23.439987 ===================================
4927 09:25:23.440079 ANA top config
4928 09:25:23.443526 ===================================
4929 09:25:23.447153 DLL_ASYNC_EN = 0
4930 09:25:23.449983 ALL_SLAVE_EN = 1
4931 09:25:23.453373 NEW_RANK_MODE = 1
4932 09:25:23.456301 DLL_IDLE_MODE = 1
4933 09:25:23.456397 LP45_APHY_COMB_EN = 1
4934 09:25:23.460187 TX_ODT_DIS = 1
4935 09:25:23.463016 NEW_8X_MODE = 1
4936 09:25:23.466266 ===================================
4937 09:25:23.469515 ===================================
4938 09:25:23.473709 data_rate = 1866
4939 09:25:23.476535 CKR = 1
4940 09:25:23.476659 DQ_P2S_RATIO = 8
4941 09:25:23.479525 ===================================
4942 09:25:23.483122 CA_P2S_RATIO = 8
4943 09:25:23.486086 DQ_CA_OPEN = 0
4944 09:25:23.490006 DQ_SEMI_OPEN = 0
4945 09:25:23.492709 CA_SEMI_OPEN = 0
4946 09:25:23.496184 CA_FULL_RATE = 0
4947 09:25:23.496302 DQ_CKDIV4_EN = 1
4948 09:25:23.499054 CA_CKDIV4_EN = 1
4949 09:25:23.502441 CA_PREDIV_EN = 0
4950 09:25:23.506026 PH8_DLY = 0
4951 09:25:23.509094 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4952 09:25:23.512828 DQ_AAMCK_DIV = 4
4953 09:25:23.512952 CA_AAMCK_DIV = 4
4954 09:25:23.515494 CA_ADMCK_DIV = 4
4955 09:25:23.518787 DQ_TRACK_CA_EN = 0
4956 09:25:23.522272 CA_PICK = 933
4957 09:25:23.525737 CA_MCKIO = 933
4958 09:25:23.528721 MCKIO_SEMI = 0
4959 09:25:23.532266 PLL_FREQ = 3732
4960 09:25:23.535195 DQ_UI_PI_RATIO = 32
4961 09:25:23.535319 CA_UI_PI_RATIO = 0
4962 09:25:23.538820 ===================================
4963 09:25:23.541842 ===================================
4964 09:25:23.545412 memory_type:LPDDR4
4965 09:25:23.548446 GP_NUM : 10
4966 09:25:23.548568 SRAM_EN : 1
4967 09:25:23.551954 MD32_EN : 0
4968 09:25:23.554767 ===================================
4969 09:25:23.558570 [ANA_INIT] >>>>>>>>>>>>>>
4970 09:25:23.561977 <<<<<< [CONFIGURE PHASE]: ANA_TX
4971 09:25:23.564867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4972 09:25:23.567937 ===================================
4973 09:25:23.571526 data_rate = 1866,PCW = 0X8f00
4974 09:25:23.574899 ===================================
4975 09:25:23.578131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4976 09:25:23.581440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4977 09:25:23.588283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4978 09:25:23.591646 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4979 09:25:23.594750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4980 09:25:23.598284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4981 09:25:23.601135 [ANA_INIT] flow start
4982 09:25:23.604569 [ANA_INIT] PLL >>>>>>>>
4983 09:25:23.604710 [ANA_INIT] PLL <<<<<<<<
4984 09:25:23.608222 [ANA_INIT] MIDPI >>>>>>>>
4985 09:25:23.611053 [ANA_INIT] MIDPI <<<<<<<<
4986 09:25:23.611163 [ANA_INIT] DLL >>>>>>>>
4987 09:25:23.614425 [ANA_INIT] flow end
4988 09:25:23.617739 ============ LP4 DIFF to SE enter ============
4989 09:25:23.624741 ============ LP4 DIFF to SE exit ============
4990 09:25:23.624881 [ANA_INIT] <<<<<<<<<<<<<
4991 09:25:23.627960 [Flow] Enable top DCM control >>>>>
4992 09:25:23.631164 [Flow] Enable top DCM control <<<<<
4993 09:25:23.634141 Enable DLL master slave shuffle
4994 09:25:23.641048 ==============================================================
4995 09:25:23.641190 Gating Mode config
4996 09:25:23.647397 ==============================================================
4997 09:25:23.650957 Config description:
4998 09:25:23.660317 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4999 09:25:23.667230 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5000 09:25:23.670899 SELPH_MODE 0: By rank 1: By Phase
5001 09:25:23.676871 ==============================================================
5002 09:25:23.680398 GAT_TRACK_EN = 1
5003 09:25:23.683878 RX_GATING_MODE = 2
5004 09:25:23.683966 RX_GATING_TRACK_MODE = 2
5005 09:25:23.686793 SELPH_MODE = 1
5006 09:25:23.689967 PICG_EARLY_EN = 1
5007 09:25:23.693868 VALID_LAT_VALUE = 1
5008 09:25:23.700191 ==============================================================
5009 09:25:23.703901 Enter into Gating configuration >>>>
5010 09:25:23.707002 Exit from Gating configuration <<<<
5011 09:25:23.709907 Enter into DVFS_PRE_config >>>>>
5012 09:25:23.719967 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5013 09:25:23.722972 Exit from DVFS_PRE_config <<<<<
5014 09:25:23.726248 Enter into PICG configuration >>>>
5015 09:25:23.729818 Exit from PICG configuration <<<<
5016 09:25:23.733067 [RX_INPUT] configuration >>>>>
5017 09:25:23.736607 [RX_INPUT] configuration <<<<<
5018 09:25:23.739913 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5019 09:25:23.746696 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5020 09:25:23.753023 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5021 09:25:23.759571 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5022 09:25:23.766174 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5023 09:25:23.769530 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5024 09:25:23.776055 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5025 09:25:23.779036 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5026 09:25:23.782577 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5027 09:25:23.785512 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5028 09:25:23.792017 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5029 09:25:23.795338 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5030 09:25:23.799112 ===================================
5031 09:25:23.802293 LPDDR4 DRAM CONFIGURATION
5032 09:25:23.805638 ===================================
5033 09:25:23.805728 EX_ROW_EN[0] = 0x0
5034 09:25:23.808632 EX_ROW_EN[1] = 0x0
5035 09:25:23.808719 LP4Y_EN = 0x0
5036 09:25:23.812247 WORK_FSP = 0x0
5037 09:25:23.815193 WL = 0x3
5038 09:25:23.815308 RL = 0x3
5039 09:25:23.818376 BL = 0x2
5040 09:25:23.818461 RPST = 0x0
5041 09:25:23.821875 RD_PRE = 0x0
5042 09:25:23.821965 WR_PRE = 0x1
5043 09:25:23.825410 WR_PST = 0x0
5044 09:25:23.825524 DBI_WR = 0x0
5045 09:25:23.828382 DBI_RD = 0x0
5046 09:25:23.828469 OTF = 0x1
5047 09:25:23.832010 ===================================
5048 09:25:23.834987 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5049 09:25:23.841680 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5050 09:25:23.845219 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5051 09:25:23.848054 ===================================
5052 09:25:23.851510 LPDDR4 DRAM CONFIGURATION
5053 09:25:23.855122 ===================================
5054 09:25:23.855248 EX_ROW_EN[0] = 0x10
5055 09:25:23.858093 EX_ROW_EN[1] = 0x0
5056 09:25:23.858214 LP4Y_EN = 0x0
5057 09:25:23.861814 WORK_FSP = 0x0
5058 09:25:23.864879 WL = 0x3
5059 09:25:23.864989 RL = 0x3
5060 09:25:23.868086 BL = 0x2
5061 09:25:23.868201 RPST = 0x0
5062 09:25:23.871591 RD_PRE = 0x0
5063 09:25:23.871717 WR_PRE = 0x1
5064 09:25:23.874387 WR_PST = 0x0
5065 09:25:23.874499 DBI_WR = 0x0
5066 09:25:23.877924 DBI_RD = 0x0
5067 09:25:23.878032 OTF = 0x1
5068 09:25:23.881040 ===================================
5069 09:25:23.887735 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5070 09:25:23.891963 nWR fixed to 30
5071 09:25:23.895537 [ModeRegInit_LP4] CH0 RK0
5072 09:25:23.895655 [ModeRegInit_LP4] CH0 RK1
5073 09:25:23.898611 [ModeRegInit_LP4] CH1 RK0
5074 09:25:23.902119 [ModeRegInit_LP4] CH1 RK1
5075 09:25:23.902239 match AC timing 9
5076 09:25:23.908590 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5077 09:25:23.911584 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5078 09:25:23.914665 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5079 09:25:23.921859 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5080 09:25:23.924835 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5081 09:25:23.924956 ==
5082 09:25:23.928200 Dram Type= 6, Freq= 0, CH_0, rank 0
5083 09:25:23.931420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 09:25:23.934909 ==
5085 09:25:23.937923 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5086 09:25:23.944622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5087 09:25:23.947819 [CA 0] Center 37 (7~68) winsize 62
5088 09:25:23.951451 [CA 1] Center 37 (7~68) winsize 62
5089 09:25:23.954195 [CA 2] Center 34 (4~65) winsize 62
5090 09:25:23.957479 [CA 3] Center 34 (4~65) winsize 62
5091 09:25:23.960805 [CA 4] Center 33 (3~64) winsize 62
5092 09:25:23.964046 [CA 5] Center 33 (3~63) winsize 61
5093 09:25:23.964177
5094 09:25:23.967332 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5095 09:25:23.967447
5096 09:25:23.971189 [CATrainingPosCal] consider 1 rank data
5097 09:25:23.974251 u2DelayCellTimex100 = 270/100 ps
5098 09:25:23.977274 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5099 09:25:23.980706 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5100 09:25:23.983963 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5101 09:25:23.990365 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5102 09:25:23.994188 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5103 09:25:23.997045 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5104 09:25:23.997156
5105 09:25:24.000752 CA PerBit enable=1, Macro0, CA PI delay=33
5106 09:25:24.000874
5107 09:25:24.003633 [CBTSetCACLKResult] CA Dly = 33
5108 09:25:24.003744 CS Dly: 7 (0~38)
5109 09:25:24.003839 ==
5110 09:25:24.007134 Dram Type= 6, Freq= 0, CH_0, rank 1
5111 09:25:24.014057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 09:25:24.014217 ==
5113 09:25:24.016713 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5114 09:25:24.023318 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5115 09:25:24.026894 [CA 0] Center 37 (7~68) winsize 62
5116 09:25:24.030425 [CA 1] Center 37 (7~68) winsize 62
5117 09:25:24.033748 [CA 2] Center 34 (4~65) winsize 62
5118 09:25:24.036747 [CA 3] Center 34 (4~65) winsize 62
5119 09:25:24.040465 [CA 4] Center 33 (3~64) winsize 62
5120 09:25:24.043388 [CA 5] Center 33 (3~63) winsize 61
5121 09:25:24.043488
5122 09:25:24.047268 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5123 09:25:24.047391
5124 09:25:24.050045 [CATrainingPosCal] consider 2 rank data
5125 09:25:24.053618 u2DelayCellTimex100 = 270/100 ps
5126 09:25:24.056559 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5127 09:25:24.063289 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5128 09:25:24.066531 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5129 09:25:24.069881 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5130 09:25:24.073183 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5131 09:25:24.076525 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5132 09:25:24.076655
5133 09:25:24.079617 CA PerBit enable=1, Macro0, CA PI delay=33
5134 09:25:24.079735
5135 09:25:24.083071 [CBTSetCACLKResult] CA Dly = 33
5136 09:25:24.086394 CS Dly: 7 (0~39)
5137 09:25:24.086513
5138 09:25:24.089601 ----->DramcWriteLeveling(PI) begin...
5139 09:25:24.089720 ==
5140 09:25:24.093129 Dram Type= 6, Freq= 0, CH_0, rank 0
5141 09:25:24.096078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5142 09:25:24.096213 ==
5143 09:25:24.099505 Write leveling (Byte 0): 33 => 33
5144 09:25:24.103319 Write leveling (Byte 1): 31 => 31
5145 09:25:24.105988 DramcWriteLeveling(PI) end<-----
5146 09:25:24.106109
5147 09:25:24.106212 ==
5148 09:25:24.109713 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 09:25:24.112870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 09:25:24.112996 ==
5151 09:25:24.115964 [Gating] SW mode calibration
5152 09:25:24.122576 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5153 09:25:24.129097 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5154 09:25:24.132698 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5155 09:25:24.136268 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5156 09:25:24.142300 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 09:25:24.145960 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 09:25:24.148971 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 09:25:24.155881 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 09:25:24.158877 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5161 09:25:24.162580 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5162 09:25:24.169147 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5163 09:25:24.172288 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 09:25:24.175857 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 09:25:24.182249 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 09:25:24.185367 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 09:25:24.188632 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 09:25:24.195571 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 09:25:24.198915 0 15 28 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5170 09:25:24.201940 1 0 0 | B1->B0 | 3232 4646 | 0 0 | (1 1) (0 0)
5171 09:25:24.208554 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 09:25:24.211734 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 09:25:24.215268 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 09:25:24.221858 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 09:25:24.224932 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 09:25:24.228315 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 09:25:24.234809 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5178 09:25:24.238558 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5179 09:25:24.241624 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 09:25:24.248026 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 09:25:24.251894 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 09:25:24.254940 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 09:25:24.261671 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 09:25:24.264625 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 09:25:24.268224 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 09:25:24.274219 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 09:25:24.278003 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 09:25:24.280904 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 09:25:24.287496 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 09:25:24.291437 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 09:25:24.294023 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 09:25:24.300694 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 09:25:24.304352 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5194 09:25:24.307620 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5195 09:25:24.311110 Total UI for P1: 0, mck2ui 16
5196 09:25:24.314232 best dqsien dly found for B0: ( 1, 2, 28)
5197 09:25:24.320580 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 09:25:24.320722 Total UI for P1: 0, mck2ui 16
5199 09:25:24.327431 best dqsien dly found for B1: ( 1, 3, 0)
5200 09:25:24.330433 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5201 09:25:24.334082 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5202 09:25:24.334210
5203 09:25:24.336911 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5204 09:25:24.340430 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5205 09:25:24.343761 [Gating] SW calibration Done
5206 09:25:24.343878 ==
5207 09:25:24.346743 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 09:25:24.350250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 09:25:24.350367 ==
5210 09:25:24.353870 RX Vref Scan: 0
5211 09:25:24.353998
5212 09:25:24.354095 RX Vref 0 -> 0, step: 1
5213 09:25:24.356877
5214 09:25:24.356991 RX Delay -80 -> 252, step: 8
5215 09:25:24.363396 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5216 09:25:24.366884 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5217 09:25:24.369900 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5218 09:25:24.373464 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5219 09:25:24.376514 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5220 09:25:24.380316 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5221 09:25:24.386359 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5222 09:25:24.389897 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5223 09:25:24.393560 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5224 09:25:24.396570 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5225 09:25:24.399517 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5226 09:25:24.406201 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5227 09:25:24.409354 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5228 09:25:24.413136 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5229 09:25:24.415968 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5230 09:25:24.419895 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5231 09:25:24.422601 ==
5232 09:25:24.422720 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 09:25:24.429022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 09:25:24.429156 ==
5235 09:25:24.429255 DQS Delay:
5236 09:25:24.432310 DQS0 = 0, DQS1 = 0
5237 09:25:24.432419 DQM Delay:
5238 09:25:24.435996 DQM0 = 96, DQM1 = 86
5239 09:25:24.436138 DQ Delay:
5240 09:25:24.439159 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5241 09:25:24.442257 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5242 09:25:24.445466 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5243 09:25:24.448922 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5244 09:25:24.449039
5245 09:25:24.449133
5246 09:25:24.449216 ==
5247 09:25:24.452171 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 09:25:24.455476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 09:25:24.455612 ==
5250 09:25:24.455709
5251 09:25:24.455798
5252 09:25:24.459118 TX Vref Scan disable
5253 09:25:24.462078 == TX Byte 0 ==
5254 09:25:24.465523 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5255 09:25:24.468917 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5256 09:25:24.471868 == TX Byte 1 ==
5257 09:25:24.475583 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5258 09:25:24.478671 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5259 09:25:24.478794 ==
5260 09:25:24.482242 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 09:25:24.488961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 09:25:24.489100 ==
5263 09:25:24.489197
5264 09:25:24.489288
5265 09:25:24.489378 TX Vref Scan disable
5266 09:25:24.492462 == TX Byte 0 ==
5267 09:25:24.496113 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5268 09:25:24.502722 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5269 09:25:24.502854 == TX Byte 1 ==
5270 09:25:24.505958 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5271 09:25:24.512384 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5272 09:25:24.512523
5273 09:25:24.512621 [DATLAT]
5274 09:25:24.512714 Freq=933, CH0 RK0
5275 09:25:24.512804
5276 09:25:24.516262 DATLAT Default: 0xd
5277 09:25:24.516372 0, 0xFFFF, sum = 0
5278 09:25:24.519197 1, 0xFFFF, sum = 0
5279 09:25:24.522243 2, 0xFFFF, sum = 0
5280 09:25:24.522358 3, 0xFFFF, sum = 0
5281 09:25:24.525691 4, 0xFFFF, sum = 0
5282 09:25:24.525806 5, 0xFFFF, sum = 0
5283 09:25:24.528929 6, 0xFFFF, sum = 0
5284 09:25:24.529045 7, 0xFFFF, sum = 0
5285 09:25:24.532477 8, 0xFFFF, sum = 0
5286 09:25:24.532590 9, 0xFFFF, sum = 0
5287 09:25:24.535837 10, 0x0, sum = 1
5288 09:25:24.535952 11, 0x0, sum = 2
5289 09:25:24.538955 12, 0x0, sum = 3
5290 09:25:24.539067 13, 0x0, sum = 4
5291 09:25:24.539162 best_step = 11
5292 09:25:24.542352
5293 09:25:24.542463 ==
5294 09:25:24.545904 Dram Type= 6, Freq= 0, CH_0, rank 0
5295 09:25:24.548893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 09:25:24.549020 ==
5297 09:25:24.549114 RX Vref Scan: 1
5298 09:25:24.549204
5299 09:25:24.552428 RX Vref 0 -> 0, step: 1
5300 09:25:24.552555
5301 09:25:24.556036 RX Delay -61 -> 252, step: 4
5302 09:25:24.556155
5303 09:25:24.558968 Set Vref, RX VrefLevel [Byte0]: 61
5304 09:25:24.561867 [Byte1]: 49
5305 09:25:24.561980
5306 09:25:24.565555 Final RX Vref Byte 0 = 61 to rank0
5307 09:25:24.568528 Final RX Vref Byte 1 = 49 to rank0
5308 09:25:24.571865 Final RX Vref Byte 0 = 61 to rank1
5309 09:25:24.575117 Final RX Vref Byte 1 = 49 to rank1==
5310 09:25:24.578133 Dram Type= 6, Freq= 0, CH_0, rank 0
5311 09:25:24.585021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 09:25:24.585162 ==
5313 09:25:24.585259 DQS Delay:
5314 09:25:24.588363 DQS0 = 0, DQS1 = 0
5315 09:25:24.588470 DQM Delay:
5316 09:25:24.588562 DQM0 = 96, DQM1 = 84
5317 09:25:24.592005 DQ Delay:
5318 09:25:24.595010 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5319 09:25:24.598498 DQ4 =96, DQ5 =88, DQ6 =108, DQ7 =106
5320 09:25:24.601445 DQ8 =76, DQ9 =74, DQ10 =84, DQ11 =80
5321 09:25:24.604880 DQ12 =90, DQ13 =88, DQ14 =94, DQ15 =92
5322 09:25:24.604971
5323 09:25:24.605037
5324 09:25:24.611544 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5325 09:25:24.614530 CH0 RK0: MR19=505, MR18=2D14
5326 09:25:24.621328 CH0_RK0: MR19=0x505, MR18=0x2D14, DQSOSC=407, MR23=63, INC=65, DEC=43
5327 09:25:24.621463
5328 09:25:24.624580 ----->DramcWriteLeveling(PI) begin...
5329 09:25:24.624700 ==
5330 09:25:24.627744 Dram Type= 6, Freq= 0, CH_0, rank 1
5331 09:25:24.631126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5332 09:25:24.631239 ==
5333 09:25:24.634392 Write leveling (Byte 0): 30 => 30
5334 09:25:24.637503 Write leveling (Byte 1): 28 => 28
5335 09:25:24.640860 DramcWriteLeveling(PI) end<-----
5336 09:25:24.640979
5337 09:25:24.641072 ==
5338 09:25:24.644300 Dram Type= 6, Freq= 0, CH_0, rank 1
5339 09:25:24.650754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5340 09:25:24.650896 ==
5341 09:25:24.650992 [Gating] SW mode calibration
5342 09:25:24.660573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5343 09:25:24.664185 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5344 09:25:24.670579 0 14 0 | B1->B0 | 2e2e 2f2f | 1 0 | (1 1) (0 0)
5345 09:25:24.673500 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5346 09:25:24.676865 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 09:25:24.683742 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 09:25:24.687174 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 09:25:24.690267 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 09:25:24.693837 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 09:25:24.699972 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 0)
5352 09:25:24.703682 0 15 0 | B1->B0 | 2c2c 2525 | 1 0 | (1 0) (1 1)
5353 09:25:24.707053 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 09:25:24.713102 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 09:25:24.716678 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 09:25:24.719844 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 09:25:24.726963 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 09:25:24.729952 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 09:25:24.732941 0 15 28 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
5360 09:25:24.739537 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5361 09:25:24.743019 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 09:25:24.746498 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 09:25:24.752818 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 09:25:24.756573 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 09:25:24.759649 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 09:25:24.766112 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 09:25:24.769735 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5368 09:25:24.772743 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5369 09:25:24.779269 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 09:25:24.782886 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 09:25:24.786407 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 09:25:24.792541 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 09:25:24.796053 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 09:25:24.798995 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 09:25:24.805978 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 09:25:24.808953 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 09:25:24.812567 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 09:25:24.819013 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 09:25:24.821982 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 09:25:24.825662 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 09:25:24.832219 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 09:25:24.835177 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 09:25:24.841652 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5384 09:25:24.845369 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5385 09:25:24.848403 Total UI for P1: 0, mck2ui 16
5386 09:25:24.851950 best dqsien dly found for B0: ( 1, 2, 28)
5387 09:25:24.855405 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 09:25:24.858743 Total UI for P1: 0, mck2ui 16
5389 09:25:24.861951 best dqsien dly found for B1: ( 1, 3, 0)
5390 09:25:24.864629 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5391 09:25:24.868213 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5392 09:25:24.868329
5393 09:25:24.871527 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5394 09:25:24.877995 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5395 09:25:24.878136 [Gating] SW calibration Done
5396 09:25:24.878251 ==
5397 09:25:24.881374 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 09:25:24.888214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 09:25:24.888334 ==
5400 09:25:24.888424 RX Vref Scan: 0
5401 09:25:24.888506
5402 09:25:24.891251 RX Vref 0 -> 0, step: 1
5403 09:25:24.891356
5404 09:25:24.894826 RX Delay -80 -> 252, step: 8
5405 09:25:24.897974 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5406 09:25:24.901257 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5407 09:25:24.904159 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5408 09:25:24.911026 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5409 09:25:24.914497 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5410 09:25:24.917507 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5411 09:25:24.921113 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5412 09:25:24.924117 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5413 09:25:24.928032 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5414 09:25:24.934465 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5415 09:25:24.937444 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5416 09:25:24.941227 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5417 09:25:24.944168 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5418 09:25:24.947962 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5419 09:25:24.953847 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5420 09:25:24.957520 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5421 09:25:24.957657 ==
5422 09:25:24.960386 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 09:25:24.963879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 09:25:24.964000 ==
5425 09:25:24.964091 DQS Delay:
5426 09:25:24.967002 DQS0 = 0, DQS1 = 0
5427 09:25:24.967109 DQM Delay:
5428 09:25:24.970318 DQM0 = 97, DQM1 = 87
5429 09:25:24.970430 DQ Delay:
5430 09:25:24.973953 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5431 09:25:24.976987 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5432 09:25:24.980189 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5433 09:25:24.984034 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5434 09:25:24.984156
5435 09:25:24.984246
5436 09:25:24.984330 ==
5437 09:25:24.987229 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 09:25:24.993184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 09:25:24.993314 ==
5440 09:25:24.993408
5441 09:25:24.993494
5442 09:25:24.993576 TX Vref Scan disable
5443 09:25:24.997183 == TX Byte 0 ==
5444 09:25:25.000599 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5445 09:25:25.007205 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5446 09:25:25.007348 == TX Byte 1 ==
5447 09:25:25.010118 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5448 09:25:25.016984 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5449 09:25:25.017118 ==
5450 09:25:25.020155 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 09:25:25.023042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 09:25:25.023154 ==
5453 09:25:25.023243
5454 09:25:25.023326
5455 09:25:25.026558 TX Vref Scan disable
5456 09:25:25.029754 == TX Byte 0 ==
5457 09:25:25.033088 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5458 09:25:25.036749 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5459 09:25:25.039662 == TX Byte 1 ==
5460 09:25:25.043238 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5461 09:25:25.046124 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5462 09:25:25.046262
5463 09:25:25.046353 [DATLAT]
5464 09:25:25.049890 Freq=933, CH0 RK1
5465 09:25:25.050004
5466 09:25:25.052712 DATLAT Default: 0xb
5467 09:25:25.052817 0, 0xFFFF, sum = 0
5468 09:25:25.056368 1, 0xFFFF, sum = 0
5469 09:25:25.056486 2, 0xFFFF, sum = 0
5470 09:25:25.059273 3, 0xFFFF, sum = 0
5471 09:25:25.059380 4, 0xFFFF, sum = 0
5472 09:25:25.062794 5, 0xFFFF, sum = 0
5473 09:25:25.062907 6, 0xFFFF, sum = 0
5474 09:25:25.066252 7, 0xFFFF, sum = 0
5475 09:25:25.066360 8, 0xFFFF, sum = 0
5476 09:25:25.069861 9, 0xFFFF, sum = 0
5477 09:25:25.069970 10, 0x0, sum = 1
5478 09:25:25.073094 11, 0x0, sum = 2
5479 09:25:25.073199 12, 0x0, sum = 3
5480 09:25:25.076343 13, 0x0, sum = 4
5481 09:25:25.076468 best_step = 11
5482 09:25:25.076557
5483 09:25:25.076642 ==
5484 09:25:25.079333 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 09:25:25.082832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 09:25:25.086148 ==
5487 09:25:25.086274 RX Vref Scan: 0
5488 09:25:25.086369
5489 09:25:25.089404 RX Vref 0 -> 0, step: 1
5490 09:25:25.089516
5491 09:25:25.092799 RX Delay -61 -> 252, step: 4
5492 09:25:25.096199 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5493 09:25:25.098995 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5494 09:25:25.106223 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5495 09:25:25.109217 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5496 09:25:25.112120 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5497 09:25:25.115637 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5498 09:25:25.118641 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5499 09:25:25.122232 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5500 09:25:25.128563 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5501 09:25:25.132341 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5502 09:25:25.135180 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5503 09:25:25.138575 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5504 09:25:25.141967 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5505 09:25:25.148483 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5506 09:25:25.151560 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5507 09:25:25.155324 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5508 09:25:25.155467 ==
5509 09:25:25.158339 Dram Type= 6, Freq= 0, CH_0, rank 1
5510 09:25:25.161621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 09:25:25.161741 ==
5512 09:25:25.165253 DQS Delay:
5513 09:25:25.165366 DQS0 = 0, DQS1 = 0
5514 09:25:25.168178 DQM Delay:
5515 09:25:25.168290 DQM0 = 95, DQM1 = 85
5516 09:25:25.168386 DQ Delay:
5517 09:25:25.171776 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5518 09:25:25.175113 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5519 09:25:25.178033 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5520 09:25:25.181564 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5521 09:25:25.181686
5522 09:25:25.185087
5523 09:25:25.191701 [DQSOSCAuto] RK1, (LSB)MR18= 0x25f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5524 09:25:25.194997 CH0 RK1: MR19=504, MR18=25F6
5525 09:25:25.201482 CH0_RK1: MR19=0x504, MR18=0x25F6, DQSOSC=410, MR23=63, INC=64, DEC=42
5526 09:25:25.204721 [RxdqsGatingPostProcess] freq 933
5527 09:25:25.208241 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5528 09:25:25.211337 best DQS0 dly(2T, 0.5T) = (0, 10)
5529 09:25:25.214367 best DQS1 dly(2T, 0.5T) = (0, 11)
5530 09:25:25.217631 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5531 09:25:25.221128 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5532 09:25:25.224262 best DQS0 dly(2T, 0.5T) = (0, 10)
5533 09:25:25.227930 best DQS1 dly(2T, 0.5T) = (0, 11)
5534 09:25:25.230904 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5535 09:25:25.234474 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5536 09:25:25.237372 Pre-setting of DQS Precalculation
5537 09:25:25.241057 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5538 09:25:25.241175 ==
5539 09:25:25.244226 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 09:25:25.250679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 09:25:25.250817 ==
5542 09:25:25.253751 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5543 09:25:25.260961 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5544 09:25:25.263671 [CA 0] Center 36 (6~67) winsize 62
5545 09:25:25.267219 [CA 1] Center 37 (6~68) winsize 63
5546 09:25:25.270283 [CA 2] Center 34 (4~65) winsize 62
5547 09:25:25.273612 [CA 3] Center 33 (3~64) winsize 62
5548 09:25:25.277271 [CA 4] Center 34 (4~64) winsize 61
5549 09:25:25.280629 [CA 5] Center 33 (3~64) winsize 62
5550 09:25:25.280751
5551 09:25:25.283517 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5552 09:25:25.283630
5553 09:25:25.287257 [CATrainingPosCal] consider 1 rank data
5554 09:25:25.290185 u2DelayCellTimex100 = 270/100 ps
5555 09:25:25.293667 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5556 09:25:25.300040 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5557 09:25:25.303508 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5558 09:25:25.306968 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5559 09:25:25.310377 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5560 09:25:25.313503 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5561 09:25:25.313617
5562 09:25:25.316764 CA PerBit enable=1, Macro0, CA PI delay=33
5563 09:25:25.316879
5564 09:25:25.320330 [CBTSetCACLKResult] CA Dly = 33
5565 09:25:25.323395 CS Dly: 6 (0~37)
5566 09:25:25.323514 ==
5567 09:25:25.326965 Dram Type= 6, Freq= 0, CH_1, rank 1
5568 09:25:25.329984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 09:25:25.330096 ==
5570 09:25:25.336553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5571 09:25:25.339578 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5572 09:25:25.343805 [CA 0] Center 36 (6~67) winsize 62
5573 09:25:25.347277 [CA 1] Center 37 (7~67) winsize 61
5574 09:25:25.350553 [CA 2] Center 34 (4~65) winsize 62
5575 09:25:25.353558 [CA 3] Center 33 (3~64) winsize 62
5576 09:25:25.357007 [CA 4] Center 34 (3~65) winsize 63
5577 09:25:25.360206 [CA 5] Center 33 (3~64) winsize 62
5578 09:25:25.360324
5579 09:25:25.363299 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5580 09:25:25.363411
5581 09:25:25.366946 [CATrainingPosCal] consider 2 rank data
5582 09:25:25.370202 u2DelayCellTimex100 = 270/100 ps
5583 09:25:25.373206 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5584 09:25:25.380463 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5585 09:25:25.383413 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5586 09:25:25.386890 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5587 09:25:25.390345 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5588 09:25:25.393290 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5589 09:25:25.393402
5590 09:25:25.396910 CA PerBit enable=1, Macro0, CA PI delay=33
5591 09:25:25.397024
5592 09:25:25.399797 [CBTSetCACLKResult] CA Dly = 33
5593 09:25:25.403251 CS Dly: 7 (0~39)
5594 09:25:25.403369
5595 09:25:25.406349 ----->DramcWriteLeveling(PI) begin...
5596 09:25:25.406468 ==
5597 09:25:25.409924 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 09:25:25.412840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 09:25:25.412956 ==
5600 09:25:25.416570 Write leveling (Byte 0): 23 => 23
5601 09:25:25.419718 Write leveling (Byte 1): 30 => 30
5602 09:25:25.423177 DramcWriteLeveling(PI) end<-----
5603 09:25:25.423302
5604 09:25:25.423402 ==
5605 09:25:25.426170 Dram Type= 6, Freq= 0, CH_1, rank 0
5606 09:25:25.429602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5607 09:25:25.429729 ==
5608 09:25:25.432773 [Gating] SW mode calibration
5609 09:25:25.439443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5610 09:25:25.445700 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5611 09:25:25.449328 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5612 09:25:25.452354 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 09:25:25.459163 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 09:25:25.462589 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 09:25:25.465600 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 09:25:25.472398 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 09:25:25.475803 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 1)
5618 09:25:25.478889 0 14 28 | B1->B0 | 2f2f 2828 | 1 0 | (1 0) (0 0)
5619 09:25:25.485699 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 09:25:25.488596 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 09:25:25.492098 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 09:25:25.498514 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 09:25:25.502157 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 09:25:25.508388 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 09:25:25.512084 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
5626 09:25:25.515021 0 15 28 | B1->B0 | 3636 3b3a | 0 1 | (0 0) (0 0)
5627 09:25:25.518841 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 09:25:25.524802 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 09:25:25.528242 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 09:25:25.534872 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 09:25:25.538266 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 09:25:25.541633 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 09:25:25.548078 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 09:25:25.551718 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 09:25:25.554552 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 09:25:25.561227 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 09:25:25.564185 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 09:25:25.567910 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 09:25:25.574253 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 09:25:25.577751 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 09:25:25.581071 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 09:25:25.587218 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 09:25:25.590601 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 09:25:25.594043 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 09:25:25.600493 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 09:25:25.603729 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 09:25:25.607337 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 09:25:25.613659 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5649 09:25:25.617307 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5650 09:25:25.620866 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 09:25:25.624107 Total UI for P1: 0, mck2ui 16
5652 09:25:25.627153 best dqsien dly found for B0: ( 1, 2, 22)
5653 09:25:25.630644 Total UI for P1: 0, mck2ui 16
5654 09:25:25.633579 best dqsien dly found for B1: ( 1, 2, 24)
5655 09:25:25.637215 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5656 09:25:25.640479 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5657 09:25:25.640607
5658 09:25:25.643478 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5659 09:25:25.650208 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5660 09:25:25.650358 [Gating] SW calibration Done
5661 09:25:25.650458 ==
5662 09:25:25.653761 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 09:25:25.660340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 09:25:25.660505 ==
5665 09:25:25.660606 RX Vref Scan: 0
5666 09:25:25.660699
5667 09:25:25.663721 RX Vref 0 -> 0, step: 1
5668 09:25:25.663833
5669 09:25:25.666729 RX Delay -80 -> 252, step: 8
5670 09:25:25.669860 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5671 09:25:25.673462 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5672 09:25:25.676956 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5673 09:25:25.679838 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5674 09:25:25.686444 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5675 09:25:25.689619 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5676 09:25:25.692820 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5677 09:25:25.696591 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5678 09:25:25.699765 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5679 09:25:25.706439 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5680 09:25:25.709587 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5681 09:25:25.712762 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5682 09:25:25.716144 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5683 09:25:25.719723 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5684 09:25:25.726268 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5685 09:25:25.729641 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5686 09:25:25.729766 ==
5687 09:25:25.732607 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 09:25:25.736062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 09:25:25.736182 ==
5690 09:25:25.736278 DQS Delay:
5691 09:25:25.738977 DQS0 = 0, DQS1 = 0
5692 09:25:25.739088 DQM Delay:
5693 09:25:25.742857 DQM0 = 100, DQM1 = 90
5694 09:25:25.742975 DQ Delay:
5695 09:25:25.745640 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =95
5696 09:25:25.748822 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5697 09:25:25.752275 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5698 09:25:25.755613 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5699 09:25:25.755741
5700 09:25:25.755840
5701 09:25:25.755933 ==
5702 09:25:25.758799 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 09:25:25.765261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 09:25:25.765398 ==
5705 09:25:25.765498
5706 09:25:25.765591
5707 09:25:25.765681 TX Vref Scan disable
5708 09:25:25.769476 == TX Byte 0 ==
5709 09:25:25.772811 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5710 09:25:25.779454 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5711 09:25:25.779629 == TX Byte 1 ==
5712 09:25:25.782824 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5713 09:25:25.789294 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5714 09:25:25.789467 ==
5715 09:25:25.792370 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 09:25:25.795924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 09:25:25.796057 ==
5718 09:25:25.796157
5719 09:25:25.796250
5720 09:25:25.798709 TX Vref Scan disable
5721 09:25:25.802176 == TX Byte 0 ==
5722 09:25:25.805688 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5723 09:25:25.809077 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5724 09:25:25.812147 == TX Byte 1 ==
5725 09:25:25.815653 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5726 09:25:25.819204 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5727 09:25:25.819333
5728 09:25:25.819431 [DATLAT]
5729 09:25:25.822033 Freq=933, CH1 RK0
5730 09:25:25.822144
5731 09:25:25.822251 DATLAT Default: 0xd
5732 09:25:25.825103 0, 0xFFFF, sum = 0
5733 09:25:25.828635 1, 0xFFFF, sum = 0
5734 09:25:25.828758 2, 0xFFFF, sum = 0
5735 09:25:25.832230 3, 0xFFFF, sum = 0
5736 09:25:25.832347 4, 0xFFFF, sum = 0
5737 09:25:25.835291 5, 0xFFFF, sum = 0
5738 09:25:25.835403 6, 0xFFFF, sum = 0
5739 09:25:25.838618 7, 0xFFFF, sum = 0
5740 09:25:25.838735 8, 0xFFFF, sum = 0
5741 09:25:25.841643 9, 0xFFFF, sum = 0
5742 09:25:25.841758 10, 0x0, sum = 1
5743 09:25:25.845203 11, 0x0, sum = 2
5744 09:25:25.845325 12, 0x0, sum = 3
5745 09:25:25.848238 13, 0x0, sum = 4
5746 09:25:25.848357 best_step = 11
5747 09:25:25.848453
5748 09:25:25.848547 ==
5749 09:25:25.851946 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 09:25:25.855010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 09:25:25.855155 ==
5752 09:25:25.858489 RX Vref Scan: 1
5753 09:25:25.858599
5754 09:25:25.861538 RX Vref 0 -> 0, step: 1
5755 09:25:25.861652
5756 09:25:25.861752 RX Delay -69 -> 252, step: 4
5757 09:25:25.864942
5758 09:25:25.865056 Set Vref, RX VrefLevel [Byte0]: 46
5759 09:25:25.868420 [Byte1]: 53
5760 09:25:25.873401
5761 09:25:25.873557 Final RX Vref Byte 0 = 46 to rank0
5762 09:25:25.876777 Final RX Vref Byte 1 = 53 to rank0
5763 09:25:25.879669 Final RX Vref Byte 0 = 46 to rank1
5764 09:25:25.883230 Final RX Vref Byte 1 = 53 to rank1==
5765 09:25:25.886482 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 09:25:25.892973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 09:25:25.893149 ==
5768 09:25:25.893254 DQS Delay:
5769 09:25:25.896024 DQS0 = 0, DQS1 = 0
5770 09:25:25.896139 DQM Delay:
5771 09:25:25.896235 DQM0 = 101, DQM1 = 93
5772 09:25:25.899617 DQ Delay:
5773 09:25:25.903213 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5774 09:25:25.906077 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =98
5775 09:25:25.909750 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
5776 09:25:25.913364 DQ12 =102, DQ13 =98, DQ14 =102, DQ15 =104
5777 09:25:25.913494
5778 09:25:25.913591
5779 09:25:25.919873 [DQSOSCAuto] RK0, (LSB)MR18= 0x200f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 411 ps
5780 09:25:25.922943 CH1 RK0: MR19=505, MR18=200F
5781 09:25:25.929918 CH1_RK0: MR19=0x505, MR18=0x200F, DQSOSC=411, MR23=63, INC=64, DEC=42
5782 09:25:25.930088
5783 09:25:25.932817 ----->DramcWriteLeveling(PI) begin...
5784 09:25:25.932948 ==
5785 09:25:25.936384 Dram Type= 6, Freq= 0, CH_1, rank 1
5786 09:25:25.939300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 09:25:25.939415 ==
5788 09:25:25.942767 Write leveling (Byte 0): 28 => 28
5789 09:25:25.945916 Write leveling (Byte 1): 32 => 32
5790 09:25:25.949356 DramcWriteLeveling(PI) end<-----
5791 09:25:25.949486
5792 09:25:25.949589 ==
5793 09:25:25.952761 Dram Type= 6, Freq= 0, CH_1, rank 1
5794 09:25:25.959379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 09:25:25.959542 ==
5796 09:25:25.959641 [Gating] SW mode calibration
5797 09:25:25.969118 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5798 09:25:25.972502 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5799 09:25:25.978620 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 09:25:25.982052 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 09:25:25.985547 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 09:25:25.991987 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 09:25:25.995682 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 09:25:25.998695 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 09:25:26.005294 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5806 09:25:26.008874 0 14 28 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 1)
5807 09:25:26.011767 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5808 09:25:26.018213 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 09:25:26.021786 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 09:25:26.025227 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 09:25:26.031805 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 09:25:26.034782 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 09:25:26.038018 0 15 24 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
5814 09:25:26.044915 0 15 28 | B1->B0 | 3e3e 3636 | 0 0 | (0 0) (0 0)
5815 09:25:26.047932 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5816 09:25:26.051442 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 09:25:26.058140 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 09:25:26.061702 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 09:25:26.065088 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 09:25:26.071542 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5821 09:25:26.074603 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 09:25:26.077826 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5823 09:25:26.084454 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 09:25:26.087806 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 09:25:26.091142 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 09:25:26.097383 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 09:25:26.101020 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 09:25:26.104089 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 09:25:26.110604 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 09:25:26.114187 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 09:25:26.117265 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 09:25:26.123845 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 09:25:26.127304 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 09:25:26.130264 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 09:25:26.137108 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 09:25:26.140568 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5837 09:25:26.143834 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 09:25:26.150053 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5839 09:25:26.153177 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5840 09:25:26.156653 Total UI for P1: 0, mck2ui 16
5841 09:25:26.160294 best dqsien dly found for B1: ( 1, 2, 28)
5842 09:25:26.163707 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 09:25:26.166558 Total UI for P1: 0, mck2ui 16
5844 09:25:26.169938 best dqsien dly found for B0: ( 1, 2, 30)
5845 09:25:26.173053 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5846 09:25:26.176261 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5847 09:25:26.176383
5848 09:25:26.183221 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5849 09:25:26.186008 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5850 09:25:26.186130 [Gating] SW calibration Done
5851 09:25:26.189586 ==
5852 09:25:26.192699 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 09:25:26.195979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 09:25:26.196100 ==
5855 09:25:26.196193 RX Vref Scan: 0
5856 09:25:26.196286
5857 09:25:26.199252 RX Vref 0 -> 0, step: 1
5858 09:25:26.199363
5859 09:25:26.203397 RX Delay -80 -> 252, step: 8
5860 09:25:26.206355 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5861 09:25:26.209355 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5862 09:25:26.215848 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5863 09:25:26.218979 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5864 09:25:26.222555 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5865 09:25:26.225473 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5866 09:25:26.229213 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5867 09:25:26.232579 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5868 09:25:26.238983 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5869 09:25:26.242510 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5870 09:25:26.245272 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5871 09:25:26.248776 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5872 09:25:26.252073 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5873 09:25:26.258430 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5874 09:25:26.262010 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5875 09:25:26.265516 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5876 09:25:26.265609 ==
5877 09:25:26.268573 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 09:25:26.272131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 09:25:26.272228 ==
5880 09:25:26.275005 DQS Delay:
5881 09:25:26.275094 DQS0 = 0, DQS1 = 0
5882 09:25:26.275159 DQM Delay:
5883 09:25:26.278358 DQM0 = 100, DQM1 = 91
5884 09:25:26.278446 DQ Delay:
5885 09:25:26.282051 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5886 09:25:26.284774 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5887 09:25:26.288063 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5888 09:25:26.291637 DQ12 =103, DQ13 =99, DQ14 =95, DQ15 =99
5889 09:25:26.291739
5890 09:25:26.295237
5891 09:25:26.295368 ==
5892 09:25:26.298181 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 09:25:26.301678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 09:25:26.301808 ==
5895 09:25:26.301907
5896 09:25:26.301998
5897 09:25:26.304992 TX Vref Scan disable
5898 09:25:26.305119 == TX Byte 0 ==
5899 09:25:26.311208 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5900 09:25:26.314989 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5901 09:25:26.315134 == TX Byte 1 ==
5902 09:25:26.321318 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5903 09:25:26.324412 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5904 09:25:26.324550 ==
5905 09:25:26.328000 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 09:25:26.331015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 09:25:26.331137 ==
5908 09:25:26.331234
5909 09:25:26.331326
5910 09:25:26.334553 TX Vref Scan disable
5911 09:25:26.337494 == TX Byte 0 ==
5912 09:25:26.341005 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5913 09:25:26.344466 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5914 09:25:26.347499 == TX Byte 1 ==
5915 09:25:26.350986 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5916 09:25:26.354417 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5917 09:25:26.354532
5918 09:25:26.357975 [DATLAT]
5919 09:25:26.358096 Freq=933, CH1 RK1
5920 09:25:26.358204
5921 09:25:26.361131 DATLAT Default: 0xb
5922 09:25:26.361240 0, 0xFFFF, sum = 0
5923 09:25:26.364228 1, 0xFFFF, sum = 0
5924 09:25:26.364342 2, 0xFFFF, sum = 0
5925 09:25:26.367245 3, 0xFFFF, sum = 0
5926 09:25:26.367360 4, 0xFFFF, sum = 0
5927 09:25:26.370793 5, 0xFFFF, sum = 0
5928 09:25:26.370915 6, 0xFFFF, sum = 0
5929 09:25:26.373741 7, 0xFFFF, sum = 0
5930 09:25:26.377322 8, 0xFFFF, sum = 0
5931 09:25:26.377441 9, 0xFFFF, sum = 0
5932 09:25:26.380404 10, 0x0, sum = 1
5933 09:25:26.380520 11, 0x0, sum = 2
5934 09:25:26.380618 12, 0x0, sum = 3
5935 09:25:26.383953 13, 0x0, sum = 4
5936 09:25:26.384072 best_step = 11
5937 09:25:26.384168
5938 09:25:26.384259 ==
5939 09:25:26.387302 Dram Type= 6, Freq= 0, CH_1, rank 1
5940 09:25:26.394060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5941 09:25:26.394211 ==
5942 09:25:26.394317 RX Vref Scan: 0
5943 09:25:26.394419
5944 09:25:26.397082 RX Vref 0 -> 0, step: 1
5945 09:25:26.397200
5946 09:25:26.400487 RX Delay -61 -> 252, step: 4
5947 09:25:26.403565 iDelay=203, Bit 0, Center 106 (19 ~ 194) 176
5948 09:25:26.410116 iDelay=203, Bit 1, Center 94 (7 ~ 182) 176
5949 09:25:26.413658 iDelay=203, Bit 2, Center 90 (3 ~ 178) 176
5950 09:25:26.416963 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5951 09:25:26.419783 iDelay=203, Bit 4, Center 100 (11 ~ 190) 180
5952 09:25:26.423759 iDelay=203, Bit 5, Center 110 (23 ~ 198) 176
5953 09:25:26.429835 iDelay=203, Bit 6, Center 112 (23 ~ 202) 180
5954 09:25:26.433356 iDelay=203, Bit 7, Center 96 (7 ~ 186) 180
5955 09:25:26.436493 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5956 09:25:26.439892 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5957 09:25:26.443426 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5958 09:25:26.446364 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
5959 09:25:26.453119 iDelay=203, Bit 12, Center 102 (11 ~ 194) 184
5960 09:25:26.456763 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5961 09:25:26.459505 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5962 09:25:26.463021 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5963 09:25:26.463122 ==
5964 09:25:26.466073 Dram Type= 6, Freq= 0, CH_1, rank 1
5965 09:25:26.472978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5966 09:25:26.473095 ==
5967 09:25:26.473162 DQS Delay:
5968 09:25:26.476239 DQS0 = 0, DQS1 = 0
5969 09:25:26.476325 DQM Delay:
5970 09:25:26.476391 DQM0 = 101, DQM1 = 92
5971 09:25:26.479496 DQ Delay:
5972 09:25:26.483108 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =100
5973 09:25:26.486142 DQ4 =100, DQ5 =110, DQ6 =112, DQ7 =96
5974 09:25:26.489192 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =84
5975 09:25:26.492773 DQ12 =102, DQ13 =98, DQ14 =96, DQ15 =102
5976 09:25:26.492891
5977 09:25:26.492988
5978 09:25:26.499251 [DQSOSCAuto] RK1, (LSB)MR18= 0x901, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5979 09:25:26.502872 CH1 RK1: MR19=505, MR18=901
5980 09:25:26.509054 CH1_RK1: MR19=0x505, MR18=0x901, DQSOSC=419, MR23=63, INC=61, DEC=41
5981 09:25:26.512411 [RxdqsGatingPostProcess] freq 933
5982 09:25:26.519076 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5983 09:25:26.522090 best DQS0 dly(2T, 0.5T) = (0, 10)
5984 09:25:26.522229 best DQS1 dly(2T, 0.5T) = (0, 10)
5985 09:25:26.525605 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5986 09:25:26.528696 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5987 09:25:26.532170 best DQS0 dly(2T, 0.5T) = (0, 10)
5988 09:25:26.535226 best DQS1 dly(2T, 0.5T) = (0, 10)
5989 09:25:26.538779 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5990 09:25:26.541854 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5991 09:25:26.545500 Pre-setting of DQS Precalculation
5992 09:25:26.551414 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5993 09:25:26.558057 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5994 09:25:26.565044 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5995 09:25:26.565215
5996 09:25:26.565322
5997 09:25:26.568056 [Calibration Summary] 1866 Mbps
5998 09:25:26.568166 CH 0, Rank 0
5999 09:25:26.571241 SW Impedance : PASS
6000 09:25:26.574953 DUTY Scan : NO K
6001 09:25:26.575051 ZQ Calibration : PASS
6002 09:25:26.577870 Jitter Meter : NO K
6003 09:25:26.581585 CBT Training : PASS
6004 09:25:26.581703 Write leveling : PASS
6005 09:25:26.584499 RX DQS gating : PASS
6006 09:25:26.588074 RX DQ/DQS(RDDQC) : PASS
6007 09:25:26.588188 TX DQ/DQS : PASS
6008 09:25:26.591601 RX DATLAT : PASS
6009 09:25:26.594639 RX DQ/DQS(Engine): PASS
6010 09:25:26.594755 TX OE : NO K
6011 09:25:26.597546 All Pass.
6012 09:25:26.597635
6013 09:25:26.597702 CH 0, Rank 1
6014 09:25:26.601108 SW Impedance : PASS
6015 09:25:26.601196 DUTY Scan : NO K
6016 09:25:26.604206 ZQ Calibration : PASS
6017 09:25:26.607644 Jitter Meter : NO K
6018 09:25:26.607739 CBT Training : PASS
6019 09:25:26.611076 Write leveling : PASS
6020 09:25:26.614109 RX DQS gating : PASS
6021 09:25:26.614207 RX DQ/DQS(RDDQC) : PASS
6022 09:25:26.617301 TX DQ/DQS : PASS
6023 09:25:26.620464 RX DATLAT : PASS
6024 09:25:26.620553 RX DQ/DQS(Engine): PASS
6025 09:25:26.624152 TX OE : NO K
6026 09:25:26.624268 All Pass.
6027 09:25:26.624361
6028 09:25:26.627155 CH 1, Rank 0
6029 09:25:26.627242 SW Impedance : PASS
6030 09:25:26.630631 DUTY Scan : NO K
6031 09:25:26.634221 ZQ Calibration : PASS
6032 09:25:26.634303 Jitter Meter : NO K
6033 09:25:26.637340 CBT Training : PASS
6034 09:25:26.640327 Write leveling : PASS
6035 09:25:26.640414 RX DQS gating : PASS
6036 09:25:26.643990 RX DQ/DQS(RDDQC) : PASS
6037 09:25:26.644071 TX DQ/DQS : PASS
6038 09:25:26.646932 RX DATLAT : PASS
6039 09:25:26.650312 RX DQ/DQS(Engine): PASS
6040 09:25:26.650402 TX OE : NO K
6041 09:25:26.653849 All Pass.
6042 09:25:26.653943
6043 09:25:26.654032 CH 1, Rank 1
6044 09:25:26.656847 SW Impedance : PASS
6045 09:25:26.656958 DUTY Scan : NO K
6046 09:25:26.660371 ZQ Calibration : PASS
6047 09:25:26.663587 Jitter Meter : NO K
6048 09:25:26.663712 CBT Training : PASS
6049 09:25:26.666912 Write leveling : PASS
6050 09:25:26.670459 RX DQS gating : PASS
6051 09:25:26.670580 RX DQ/DQS(RDDQC) : PASS
6052 09:25:26.673205 TX DQ/DQS : PASS
6053 09:25:26.676792 RX DATLAT : PASS
6054 09:25:26.676907 RX DQ/DQS(Engine): PASS
6055 09:25:26.680330 TX OE : NO K
6056 09:25:26.680444 All Pass.
6057 09:25:26.680538
6058 09:25:26.683161 DramC Write-DBI off
6059 09:25:26.686664 PER_BANK_REFRESH: Hybrid Mode
6060 09:25:26.686786 TX_TRACKING: ON
6061 09:25:26.696394 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6062 09:25:26.699884 [FAST_K] Save calibration result to emmc
6063 09:25:26.702916 dramc_set_vcore_voltage set vcore to 650000
6064 09:25:26.706532 Read voltage for 400, 6
6065 09:25:26.706656 Vio18 = 0
6066 09:25:26.706752 Vcore = 650000
6067 09:25:26.709479 Vdram = 0
6068 09:25:26.709592 Vddq = 0
6069 09:25:26.709686 Vmddr = 0
6070 09:25:26.716065 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6071 09:25:26.719532 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6072 09:25:26.722729 MEM_TYPE=3, freq_sel=20
6073 09:25:26.726211 sv_algorithm_assistance_LP4_800
6074 09:25:26.729317 ============ PULL DRAM RESETB DOWN ============
6075 09:25:26.736161 ========== PULL DRAM RESETB DOWN end =========
6076 09:25:26.739085 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6077 09:25:26.742386 ===================================
6078 09:25:26.745630 LPDDR4 DRAM CONFIGURATION
6079 09:25:26.748924 ===================================
6080 09:25:26.749052 EX_ROW_EN[0] = 0x0
6081 09:25:26.752327 EX_ROW_EN[1] = 0x0
6082 09:25:26.752446 LP4Y_EN = 0x0
6083 09:25:26.756233 WORK_FSP = 0x0
6084 09:25:26.756364 WL = 0x2
6085 09:25:26.759178 RL = 0x2
6086 09:25:26.759287 BL = 0x2
6087 09:25:26.762804 RPST = 0x0
6088 09:25:26.762893 RD_PRE = 0x0
6089 09:25:26.765677 WR_PRE = 0x1
6090 09:25:26.769241 WR_PST = 0x0
6091 09:25:26.769328 DBI_WR = 0x0
6092 09:25:26.772657 DBI_RD = 0x0
6093 09:25:26.772747 OTF = 0x1
6094 09:25:26.775868 ===================================
6095 09:25:26.778577 ===================================
6096 09:25:26.782313 ANA top config
6097 09:25:26.785261 ===================================
6098 09:25:26.785387 DLL_ASYNC_EN = 0
6099 09:25:26.788368 ALL_SLAVE_EN = 1
6100 09:25:26.791875 NEW_RANK_MODE = 1
6101 09:25:26.795443 DLL_IDLE_MODE = 1
6102 09:25:26.795544 LP45_APHY_COMB_EN = 1
6103 09:25:26.798458 TX_ODT_DIS = 1
6104 09:25:26.802100 NEW_8X_MODE = 1
6105 09:25:26.805035 ===================================
6106 09:25:26.808751 ===================================
6107 09:25:26.812025 data_rate = 800
6108 09:25:26.815144 CKR = 1
6109 09:25:26.818583 DQ_P2S_RATIO = 4
6110 09:25:26.821642 ===================================
6111 09:25:26.821759 CA_P2S_RATIO = 4
6112 09:25:26.825208 DQ_CA_OPEN = 0
6113 09:25:26.828278 DQ_SEMI_OPEN = 1
6114 09:25:26.831593 CA_SEMI_OPEN = 1
6115 09:25:26.834947 CA_FULL_RATE = 0
6116 09:25:26.838069 DQ_CKDIV4_EN = 0
6117 09:25:26.838204 CA_CKDIV4_EN = 1
6118 09:25:26.841301 CA_PREDIV_EN = 0
6119 09:25:26.845045 PH8_DLY = 0
6120 09:25:26.847846 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6121 09:25:26.851187 DQ_AAMCK_DIV = 0
6122 09:25:26.854455 CA_AAMCK_DIV = 0
6123 09:25:26.854546 CA_ADMCK_DIV = 4
6124 09:25:26.858102 DQ_TRACK_CA_EN = 0
6125 09:25:26.861048 CA_PICK = 800
6126 09:25:26.864645 CA_MCKIO = 400
6127 09:25:26.867697 MCKIO_SEMI = 400
6128 09:25:26.871382 PLL_FREQ = 3016
6129 09:25:26.874415 DQ_UI_PI_RATIO = 32
6130 09:25:26.877916 CA_UI_PI_RATIO = 32
6131 09:25:26.881113 ===================================
6132 09:25:26.884606 ===================================
6133 09:25:26.884728 memory_type:LPDDR4
6134 09:25:26.887892 GP_NUM : 10
6135 09:25:26.891547 SRAM_EN : 1
6136 09:25:26.891669 MD32_EN : 0
6137 09:25:26.894249 ===================================
6138 09:25:26.897866 [ANA_INIT] >>>>>>>>>>>>>>
6139 09:25:26.900886 <<<<<< [CONFIGURE PHASE]: ANA_TX
6140 09:25:26.904435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6141 09:25:26.907709 ===================================
6142 09:25:26.911006 data_rate = 800,PCW = 0X7400
6143 09:25:26.914267 ===================================
6144 09:25:26.917411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6145 09:25:26.921032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6146 09:25:26.934027 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6147 09:25:26.937082 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6148 09:25:26.940687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6149 09:25:26.943603 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6150 09:25:26.947028 [ANA_INIT] flow start
6151 09:25:26.950239 [ANA_INIT] PLL >>>>>>>>
6152 09:25:26.950357 [ANA_INIT] PLL <<<<<<<<
6153 09:25:26.953429 [ANA_INIT] MIDPI >>>>>>>>
6154 09:25:26.956658 [ANA_INIT] MIDPI <<<<<<<<
6155 09:25:26.956773 [ANA_INIT] DLL >>>>>>>>
6156 09:25:26.960038 [ANA_INIT] flow end
6157 09:25:26.963241 ============ LP4 DIFF to SE enter ============
6158 09:25:26.966487 ============ LP4 DIFF to SE exit ============
6159 09:25:26.970080 [ANA_INIT] <<<<<<<<<<<<<
6160 09:25:26.973559 [Flow] Enable top DCM control >>>>>
6161 09:25:26.976447 [Flow] Enable top DCM control <<<<<
6162 09:25:26.979708 Enable DLL master slave shuffle
6163 09:25:26.986264 ==============================================================
6164 09:25:26.986401 Gating Mode config
6165 09:25:26.992809 ==============================================================
6166 09:25:26.996226 Config description:
6167 09:25:27.003188 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6168 09:25:27.009701 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6169 09:25:27.016244 SELPH_MODE 0: By rank 1: By Phase
6170 09:25:27.022928 ==============================================================
6171 09:25:27.026267 GAT_TRACK_EN = 0
6172 09:25:27.026396 RX_GATING_MODE = 2
6173 09:25:27.029109 RX_GATING_TRACK_MODE = 2
6174 09:25:27.032583 SELPH_MODE = 1
6175 09:25:27.035679 PICG_EARLY_EN = 1
6176 09:25:27.039342 VALID_LAT_VALUE = 1
6177 09:25:27.045998 ==============================================================
6178 09:25:27.048795 Enter into Gating configuration >>>>
6179 09:25:27.052545 Exit from Gating configuration <<<<
6180 09:25:27.055449 Enter into DVFS_PRE_config >>>>>
6181 09:25:27.065606 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6182 09:25:27.068998 Exit from DVFS_PRE_config <<<<<
6183 09:25:27.072182 Enter into PICG configuration >>>>
6184 09:25:27.075325 Exit from PICG configuration <<<<
6185 09:25:27.079004 [RX_INPUT] configuration >>>>>
6186 09:25:27.081985 [RX_INPUT] configuration <<<<<
6187 09:25:27.085661 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6188 09:25:27.091755 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6189 09:25:27.098562 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6190 09:25:27.104843 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6191 09:25:27.108297 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6192 09:25:27.114980 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6193 09:25:27.121637 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6194 09:25:27.124761 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6195 09:25:27.128368 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6196 09:25:27.131436 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6197 09:25:27.137841 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6198 09:25:27.141398 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6199 09:25:27.144435 ===================================
6200 09:25:27.148045 LPDDR4 DRAM CONFIGURATION
6201 09:25:27.151444 ===================================
6202 09:25:27.151567 EX_ROW_EN[0] = 0x0
6203 09:25:27.154643 EX_ROW_EN[1] = 0x0
6204 09:25:27.154752 LP4Y_EN = 0x0
6205 09:25:27.157572 WORK_FSP = 0x0
6206 09:25:27.157689 WL = 0x2
6207 09:25:27.161289 RL = 0x2
6208 09:25:27.161375 BL = 0x2
6209 09:25:27.164592 RPST = 0x0
6210 09:25:27.164696 RD_PRE = 0x0
6211 09:25:27.167849 WR_PRE = 0x1
6212 09:25:27.171049 WR_PST = 0x0
6213 09:25:27.171161 DBI_WR = 0x0
6214 09:25:27.174407 DBI_RD = 0x0
6215 09:25:27.174500 OTF = 0x1
6216 09:25:27.177385 ===================================
6217 09:25:27.180801 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6218 09:25:27.187481 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6219 09:25:27.191095 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6220 09:25:27.194000 ===================================
6221 09:25:27.198011 LPDDR4 DRAM CONFIGURATION
6222 09:25:27.200932 ===================================
6223 09:25:27.201045 EX_ROW_EN[0] = 0x10
6224 09:25:27.204225 EX_ROW_EN[1] = 0x0
6225 09:25:27.204339 LP4Y_EN = 0x0
6226 09:25:27.207480 WORK_FSP = 0x0
6227 09:25:27.207586 WL = 0x2
6228 09:25:27.210897 RL = 0x2
6229 09:25:27.210998 BL = 0x2
6230 09:25:27.213790 RPST = 0x0
6231 09:25:27.213903 RD_PRE = 0x0
6232 09:25:27.217339 WR_PRE = 0x1
6233 09:25:27.220375 WR_PST = 0x0
6234 09:25:27.220491 DBI_WR = 0x0
6235 09:25:27.224144 DBI_RD = 0x0
6236 09:25:27.224261 OTF = 0x1
6237 09:25:27.227092 ===================================
6238 09:25:27.233778 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6239 09:25:27.237407 nWR fixed to 30
6240 09:25:27.240821 [ModeRegInit_LP4] CH0 RK0
6241 09:25:27.240934 [ModeRegInit_LP4] CH0 RK1
6242 09:25:27.243834 [ModeRegInit_LP4] CH1 RK0
6243 09:25:27.247338 [ModeRegInit_LP4] CH1 RK1
6244 09:25:27.247453 match AC timing 19
6245 09:25:27.254209 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6246 09:25:27.257150 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6247 09:25:27.260562 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6248 09:25:27.267445 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6249 09:25:27.270652 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6250 09:25:27.270768 ==
6251 09:25:27.273580 Dram Type= 6, Freq= 0, CH_0, rank 0
6252 09:25:27.277029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 09:25:27.277147 ==
6254 09:25:27.283745 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6255 09:25:27.289968 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6256 09:25:27.293097 [CA 0] Center 36 (8~64) winsize 57
6257 09:25:27.296438 [CA 1] Center 36 (8~64) winsize 57
6258 09:25:27.300031 [CA 2] Center 36 (8~64) winsize 57
6259 09:25:27.303550 [CA 3] Center 36 (8~64) winsize 57
6260 09:25:27.306642 [CA 4] Center 36 (8~64) winsize 57
6261 09:25:27.309626 [CA 5] Center 36 (8~64) winsize 57
6262 09:25:27.309736
6263 09:25:27.313044 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6264 09:25:27.313153
6265 09:25:27.316394 [CATrainingPosCal] consider 1 rank data
6266 09:25:27.319594 u2DelayCellTimex100 = 270/100 ps
6267 09:25:27.323034 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 09:25:27.326613 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 09:25:27.329573 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 09:25:27.332576 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 09:25:27.336054 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 09:25:27.339725 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 09:25:27.339841
6274 09:25:27.346158 CA PerBit enable=1, Macro0, CA PI delay=36
6275 09:25:27.346284
6276 09:25:27.346382 [CBTSetCACLKResult] CA Dly = 36
6277 09:25:27.349589 CS Dly: 1 (0~32)
6278 09:25:27.349698 ==
6279 09:25:27.352704 Dram Type= 6, Freq= 0, CH_0, rank 1
6280 09:25:27.356039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 09:25:27.356151 ==
6282 09:25:27.362850 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6283 09:25:27.368852 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6284 09:25:27.372563 [CA 0] Center 36 (8~64) winsize 57
6285 09:25:27.375447 [CA 1] Center 36 (8~64) winsize 57
6286 09:25:27.379010 [CA 2] Center 36 (8~64) winsize 57
6287 09:25:27.381901 [CA 3] Center 36 (8~64) winsize 57
6288 09:25:27.385310 [CA 4] Center 36 (8~64) winsize 57
6289 09:25:27.388681 [CA 5] Center 36 (8~64) winsize 57
6290 09:25:27.388771
6291 09:25:27.392011 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6292 09:25:27.392099
6293 09:25:27.395524 [CATrainingPosCal] consider 2 rank data
6294 09:25:27.398716 u2DelayCellTimex100 = 270/100 ps
6295 09:25:27.401909 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 09:25:27.405030 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 09:25:27.408701 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 09:25:27.411658 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 09:25:27.415330 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 09:25:27.418292 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 09:25:27.418380
6302 09:25:27.424947 CA PerBit enable=1, Macro0, CA PI delay=36
6303 09:25:27.425069
6304 09:25:27.425163 [CBTSetCACLKResult] CA Dly = 36
6305 09:25:27.428180 CS Dly: 1 (0~32)
6306 09:25:27.428264
6307 09:25:27.431645 ----->DramcWriteLeveling(PI) begin...
6308 09:25:27.431732 ==
6309 09:25:27.434675 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 09:25:27.438181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 09:25:27.438267 ==
6312 09:25:27.441277 Write leveling (Byte 0): 40 => 8
6313 09:25:27.444793 Write leveling (Byte 1): 32 => 0
6314 09:25:27.447879 DramcWriteLeveling(PI) end<-----
6315 09:25:27.447992
6316 09:25:27.448085 ==
6317 09:25:27.451483 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 09:25:27.454508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 09:25:27.458152 ==
6320 09:25:27.458279 [Gating] SW mode calibration
6321 09:25:27.468142 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6322 09:25:27.471131 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6323 09:25:27.474154 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6324 09:25:27.481153 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6325 09:25:27.484306 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6326 09:25:27.487248 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 09:25:27.494360 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 09:25:27.497124 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 09:25:27.500447 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6330 09:25:27.507229 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 09:25:27.510615 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6332 09:25:27.513834 Total UI for P1: 0, mck2ui 16
6333 09:25:27.517094 best dqsien dly found for B0: ( 0, 14, 24)
6334 09:25:27.520274 Total UI for P1: 0, mck2ui 16
6335 09:25:27.523894 best dqsien dly found for B1: ( 0, 14, 24)
6336 09:25:27.526974 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6337 09:25:27.530448 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6338 09:25:27.530558
6339 09:25:27.533834 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6340 09:25:27.540558 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6341 09:25:27.540733 [Gating] SW calibration Done
6342 09:25:27.540831 ==
6343 09:25:27.543599 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 09:25:27.550324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 09:25:27.550454 ==
6346 09:25:27.550550 RX Vref Scan: 0
6347 09:25:27.550641
6348 09:25:27.553673 RX Vref 0 -> 0, step: 1
6349 09:25:27.553784
6350 09:25:27.556522 RX Delay -410 -> 252, step: 16
6351 09:25:27.560245 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6352 09:25:27.563739 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6353 09:25:27.570116 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6354 09:25:27.573173 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6355 09:25:27.576266 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6356 09:25:27.580364 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6357 09:25:27.586614 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6358 09:25:27.589837 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6359 09:25:27.592790 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6360 09:25:27.596180 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6361 09:25:27.602622 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6362 09:25:27.606096 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6363 09:25:27.609558 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6364 09:25:27.616022 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6365 09:25:27.619578 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6366 09:25:27.622249 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6367 09:25:27.622368 ==
6368 09:25:27.625705 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 09:25:27.628839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 09:25:27.632510 ==
6371 09:25:27.632635 DQS Delay:
6372 09:25:27.632731 DQS0 = 43, DQS1 = 59
6373 09:25:27.635603 DQM Delay:
6374 09:25:27.635716 DQM0 = 10, DQM1 = 11
6375 09:25:27.639376 DQ Delay:
6376 09:25:27.639487 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6377 09:25:27.642832 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6378 09:25:27.645790 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6379 09:25:27.648965 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6380 09:25:27.649081
6381 09:25:27.649176
6382 09:25:27.652595 ==
6383 09:25:27.655504 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 09:25:27.659078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 09:25:27.659211 ==
6386 09:25:27.659309
6387 09:25:27.659400
6388 09:25:27.662186 TX Vref Scan disable
6389 09:25:27.662297 == TX Byte 0 ==
6390 09:25:27.665741 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6391 09:25:27.671815 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6392 09:25:27.671935 == TX Byte 1 ==
6393 09:25:27.675461 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6394 09:25:27.681884 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6395 09:25:27.682000 ==
6396 09:25:27.684959 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 09:25:27.688572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 09:25:27.688692 ==
6399 09:25:27.688787
6400 09:25:27.688877
6401 09:25:27.691819 TX Vref Scan disable
6402 09:25:27.691927 == TX Byte 0 ==
6403 09:25:27.698227 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6404 09:25:27.701948 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6405 09:25:27.702063 == TX Byte 1 ==
6406 09:25:27.708587 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6407 09:25:27.711549 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6408 09:25:27.711666
6409 09:25:27.711760 [DATLAT]
6410 09:25:27.715192 Freq=400, CH0 RK0
6411 09:25:27.715300
6412 09:25:27.715395 DATLAT Default: 0xf
6413 09:25:27.718272 0, 0xFFFF, sum = 0
6414 09:25:27.718384 1, 0xFFFF, sum = 0
6415 09:25:27.721311 2, 0xFFFF, sum = 0
6416 09:25:27.721419 3, 0xFFFF, sum = 0
6417 09:25:27.724853 4, 0xFFFF, sum = 0
6418 09:25:27.724968 5, 0xFFFF, sum = 0
6419 09:25:27.727868 6, 0xFFFF, sum = 0
6420 09:25:27.727981 7, 0xFFFF, sum = 0
6421 09:25:27.731242 8, 0xFFFF, sum = 0
6422 09:25:27.731354 9, 0xFFFF, sum = 0
6423 09:25:27.734456 10, 0xFFFF, sum = 0
6424 09:25:27.737912 11, 0xFFFF, sum = 0
6425 09:25:27.738027 12, 0xFFFF, sum = 0
6426 09:25:27.741479 13, 0x0, sum = 1
6427 09:25:27.741590 14, 0x0, sum = 2
6428 09:25:27.744499 15, 0x0, sum = 3
6429 09:25:27.744610 16, 0x0, sum = 4
6430 09:25:27.744707 best_step = 14
6431 09:25:27.744797
6432 09:25:27.747986 ==
6433 09:25:27.751343 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 09:25:27.755070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 09:25:27.755184 ==
6436 09:25:27.755279 RX Vref Scan: 1
6437 09:25:27.755371
6438 09:25:27.757815 RX Vref 0 -> 0, step: 1
6439 09:25:27.757920
6440 09:25:27.761010 RX Delay -359 -> 252, step: 8
6441 09:25:27.761129
6442 09:25:27.764475 Set Vref, RX VrefLevel [Byte0]: 61
6443 09:25:27.767596 [Byte1]: 49
6444 09:25:27.771733
6445 09:25:27.771845 Final RX Vref Byte 0 = 61 to rank0
6446 09:25:27.774730 Final RX Vref Byte 1 = 49 to rank0
6447 09:25:27.778344 Final RX Vref Byte 0 = 61 to rank1
6448 09:25:27.781374 Final RX Vref Byte 1 = 49 to rank1==
6449 09:25:27.784323 Dram Type= 6, Freq= 0, CH_0, rank 0
6450 09:25:27.791179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 09:25:27.791302 ==
6452 09:25:27.791401 DQS Delay:
6453 09:25:27.794370 DQS0 = 48, DQS1 = 60
6454 09:25:27.794481 DQM Delay:
6455 09:25:27.794575 DQM0 = 11, DQM1 = 11
6456 09:25:27.798211 DQ Delay:
6457 09:25:27.800803 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6458 09:25:27.804291 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6459 09:25:27.807809 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6460 09:25:27.810831 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6461 09:25:27.810943
6462 09:25:27.811038
6463 09:25:27.817437 [DQSOSCAuto] RK0, (LSB)MR18= 0xc285, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6464 09:25:27.820703 CH0 RK0: MR19=C0C, MR18=C285
6465 09:25:27.827328 CH0_RK0: MR19=0xC0C, MR18=0xC285, DQSOSC=385, MR23=63, INC=398, DEC=265
6466 09:25:27.827465 ==
6467 09:25:27.830393 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 09:25:27.833998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 09:25:27.834120 ==
6470 09:25:27.836963 [Gating] SW mode calibration
6471 09:25:27.843669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6472 09:25:27.850512 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6473 09:25:27.853294 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6474 09:25:27.856983 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6475 09:25:27.863401 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6476 09:25:27.866723 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 09:25:27.869865 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 09:25:27.876961 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 09:25:27.879949 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 09:25:27.883139 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 09:25:27.889911 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6482 09:25:27.892853 Total UI for P1: 0, mck2ui 16
6483 09:25:27.896553 best dqsien dly found for B0: ( 0, 14, 24)
6484 09:25:27.899460 Total UI for P1: 0, mck2ui 16
6485 09:25:27.902906 best dqsien dly found for B1: ( 0, 14, 24)
6486 09:25:27.906271 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6487 09:25:27.909517 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6488 09:25:27.909635
6489 09:25:27.912809 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6490 09:25:27.916157 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6491 09:25:27.919666 [Gating] SW calibration Done
6492 09:25:27.919784 ==
6493 09:25:27.922799 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 09:25:27.926261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 09:25:27.926374 ==
6496 09:25:27.929292 RX Vref Scan: 0
6497 09:25:27.929400
6498 09:25:27.932709 RX Vref 0 -> 0, step: 1
6499 09:25:27.932817
6500 09:25:27.932911 RX Delay -410 -> 252, step: 16
6501 09:25:27.939622 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6502 09:25:27.943161 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6503 09:25:27.946349 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6504 09:25:27.952925 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6505 09:25:27.956666 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6506 09:25:27.959527 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6507 09:25:27.963308 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6508 09:25:27.969191 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6509 09:25:27.972864 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6510 09:25:27.975743 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6511 09:25:27.979107 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6512 09:25:27.985690 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6513 09:25:27.989265 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6514 09:25:27.992558 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6515 09:25:27.995967 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6516 09:25:28.002032 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6517 09:25:28.002158 ==
6518 09:25:28.005714 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 09:25:28.008907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 09:25:28.008989 ==
6521 09:25:28.009064 DQS Delay:
6522 09:25:28.012329 DQS0 = 43, DQS1 = 59
6523 09:25:28.012414 DQM Delay:
6524 09:25:28.015754 DQM0 = 9, DQM1 = 16
6525 09:25:28.015827 DQ Delay:
6526 09:25:28.018566 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6527 09:25:28.022240 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6528 09:25:28.025706 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6529 09:25:28.028551 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6530 09:25:28.028642
6531 09:25:28.028707
6532 09:25:28.028768 ==
6533 09:25:28.032086 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 09:25:28.035157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 09:25:28.035247 ==
6536 09:25:28.035313
6537 09:25:28.038706
6538 09:25:28.038791 TX Vref Scan disable
6539 09:25:28.042217 == TX Byte 0 ==
6540 09:25:28.044947 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6541 09:25:28.048499 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6542 09:25:28.051653 == TX Byte 1 ==
6543 09:25:28.055048 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6544 09:25:28.058173 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6545 09:25:28.058263 ==
6546 09:25:28.061743 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 09:25:28.064992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 09:25:28.065081 ==
6549 09:25:28.068439
6550 09:25:28.068523
6551 09:25:28.068589 TX Vref Scan disable
6552 09:25:28.071447 == TX Byte 0 ==
6553 09:25:28.075014 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6554 09:25:28.078431 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6555 09:25:28.081420 == TX Byte 1 ==
6556 09:25:28.084635 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6557 09:25:28.088301 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6558 09:25:28.088387
6559 09:25:28.088453 [DATLAT]
6560 09:25:28.091733 Freq=400, CH0 RK1
6561 09:25:28.091819
6562 09:25:28.094744 DATLAT Default: 0xe
6563 09:25:28.094858 0, 0xFFFF, sum = 0
6564 09:25:28.098248 1, 0xFFFF, sum = 0
6565 09:25:28.098360 2, 0xFFFF, sum = 0
6566 09:25:28.101199 3, 0xFFFF, sum = 0
6567 09:25:28.101311 4, 0xFFFF, sum = 0
6568 09:25:28.104826 5, 0xFFFF, sum = 0
6569 09:25:28.104945 6, 0xFFFF, sum = 0
6570 09:25:28.107849 7, 0xFFFF, sum = 0
6571 09:25:28.107959 8, 0xFFFF, sum = 0
6572 09:25:28.111661 9, 0xFFFF, sum = 0
6573 09:25:28.111771 10, 0xFFFF, sum = 0
6574 09:25:28.114323 11, 0xFFFF, sum = 0
6575 09:25:28.114435 12, 0xFFFF, sum = 0
6576 09:25:28.117926 13, 0x0, sum = 1
6577 09:25:28.118036 14, 0x0, sum = 2
6578 09:25:28.120834 15, 0x0, sum = 3
6579 09:25:28.120945 16, 0x0, sum = 4
6580 09:25:28.124363 best_step = 14
6581 09:25:28.124473
6582 09:25:28.124568 ==
6583 09:25:28.127342 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 09:25:28.130638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 09:25:28.130752 ==
6586 09:25:28.134297 RX Vref Scan: 0
6587 09:25:28.134408
6588 09:25:28.134503 RX Vref 0 -> 0, step: 1
6589 09:25:28.134595
6590 09:25:28.137573 RX Delay -359 -> 252, step: 8
6591 09:25:28.145579 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6592 09:25:28.148868 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6593 09:25:28.152361 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6594 09:25:28.158609 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6595 09:25:28.162088 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6596 09:25:28.165495 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6597 09:25:28.168991 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6598 09:25:28.175840 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6599 09:25:28.178510 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6600 09:25:28.182133 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6601 09:25:28.185170 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6602 09:25:28.191705 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6603 09:25:28.195222 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6604 09:25:28.198423 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6605 09:25:28.201610 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6606 09:25:28.208215 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6607 09:25:28.208371 ==
6608 09:25:28.211929 Dram Type= 6, Freq= 0, CH_0, rank 1
6609 09:25:28.214790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 09:25:28.214900 ==
6611 09:25:28.217886 DQS Delay:
6612 09:25:28.217992 DQS0 = 44, DQS1 = 60
6613 09:25:28.218084 DQM Delay:
6614 09:25:28.221476 DQM0 = 7, DQM1 = 14
6615 09:25:28.221582 DQ Delay:
6616 09:25:28.224416 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6617 09:25:28.228002 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6618 09:25:28.230905 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6619 09:25:28.233977 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6620 09:25:28.234090
6621 09:25:28.234207
6622 09:25:28.244266 [DQSOSCAuto] RK1, (LSB)MR18= 0xb846, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6623 09:25:28.244433 CH0 RK1: MR19=C0C, MR18=B846
6624 09:25:28.250619 CH0_RK1: MR19=0xC0C, MR18=0xB846, DQSOSC=386, MR23=63, INC=396, DEC=264
6625 09:25:28.253719 [RxdqsGatingPostProcess] freq 400
6626 09:25:28.260585 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6627 09:25:28.263700 best DQS0 dly(2T, 0.5T) = (0, 10)
6628 09:25:28.267179 best DQS1 dly(2T, 0.5T) = (0, 10)
6629 09:25:28.270403 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6630 09:25:28.273750 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6631 09:25:28.277343 best DQS0 dly(2T, 0.5T) = (0, 10)
6632 09:25:28.280672 best DQS1 dly(2T, 0.5T) = (0, 10)
6633 09:25:28.283990 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6634 09:25:28.287256 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6635 09:25:28.287371 Pre-setting of DQS Precalculation
6636 09:25:28.293919 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6637 09:25:28.294044 ==
6638 09:25:28.296818 Dram Type= 6, Freq= 0, CH_1, rank 0
6639 09:25:28.300369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 09:25:28.300487 ==
6641 09:25:28.306512 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6642 09:25:28.313583 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6643 09:25:28.316409 [CA 0] Center 36 (8~64) winsize 57
6644 09:25:28.320074 [CA 1] Center 36 (8~64) winsize 57
6645 09:25:28.323011 [CA 2] Center 36 (8~64) winsize 57
6646 09:25:28.326774 [CA 3] Center 36 (8~64) winsize 57
6647 09:25:28.329980 [CA 4] Center 36 (8~64) winsize 57
6648 09:25:28.330106 [CA 5] Center 36 (8~64) winsize 57
6649 09:25:28.333373
6650 09:25:28.336514 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6651 09:25:28.336609
6652 09:25:28.339383 [CATrainingPosCal] consider 1 rank data
6653 09:25:28.343061 u2DelayCellTimex100 = 270/100 ps
6654 09:25:28.346480 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 09:25:28.349841 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 09:25:28.353076 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 09:25:28.356308 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 09:25:28.359459 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 09:25:28.362517 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 09:25:28.362615
6661 09:25:28.366179 CA PerBit enable=1, Macro0, CA PI delay=36
6662 09:25:28.366267
6663 09:25:28.369093 [CBTSetCACLKResult] CA Dly = 36
6664 09:25:28.372513 CS Dly: 1 (0~32)
6665 09:25:28.372611 ==
6666 09:25:28.375751 Dram Type= 6, Freq= 0, CH_1, rank 1
6667 09:25:28.379628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 09:25:28.379721 ==
6669 09:25:28.385663 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6670 09:25:28.392313 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6671 09:25:28.395883 [CA 0] Center 36 (8~64) winsize 57
6672 09:25:28.398831 [CA 1] Center 36 (8~64) winsize 57
6673 09:25:28.402312 [CA 2] Center 36 (8~64) winsize 57
6674 09:25:28.402434 [CA 3] Center 36 (8~64) winsize 57
6675 09:25:28.405354 [CA 4] Center 36 (8~64) winsize 57
6676 09:25:28.408912 [CA 5] Center 36 (8~64) winsize 57
6677 09:25:28.409029
6678 09:25:28.415375 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6679 09:25:28.415503
6680 09:25:28.418627 [CATrainingPosCal] consider 2 rank data
6681 09:25:28.422112 u2DelayCellTimex100 = 270/100 ps
6682 09:25:28.425415 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 09:25:28.428990 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 09:25:28.431957 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 09:25:28.434960 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 09:25:28.438600 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 09:25:28.441520 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 09:25:28.441628
6689 09:25:28.445132 CA PerBit enable=1, Macro0, CA PI delay=36
6690 09:25:28.445246
6691 09:25:28.448107 [CBTSetCACLKResult] CA Dly = 36
6692 09:25:28.451548 CS Dly: 1 (0~32)
6693 09:25:28.451650
6694 09:25:28.454974 ----->DramcWriteLeveling(PI) begin...
6695 09:25:28.455091 ==
6696 09:25:28.458072 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 09:25:28.461564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 09:25:28.461689 ==
6699 09:25:28.464864 Write leveling (Byte 0): 40 => 8
6700 09:25:28.467754 Write leveling (Byte 1): 40 => 8
6701 09:25:28.471422 DramcWriteLeveling(PI) end<-----
6702 09:25:28.471539
6703 09:25:28.471634 ==
6704 09:25:28.474605 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 09:25:28.477645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 09:25:28.477749 ==
6707 09:25:28.480981 [Gating] SW mode calibration
6708 09:25:28.488216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6709 09:25:28.494648 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6710 09:25:28.497881 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6711 09:25:28.504536 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6712 09:25:28.507591 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6713 09:25:28.510600 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 09:25:28.517054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 09:25:28.520442 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 09:25:28.523855 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6717 09:25:28.531250 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 09:25:28.534023 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6719 09:25:28.537052 Total UI for P1: 0, mck2ui 16
6720 09:25:28.540762 best dqsien dly found for B0: ( 0, 14, 24)
6721 09:25:28.543709 Total UI for P1: 0, mck2ui 16
6722 09:25:28.546812 best dqsien dly found for B1: ( 0, 14, 24)
6723 09:25:28.550402 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6724 09:25:28.554097 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6725 09:25:28.554243
6726 09:25:28.556879 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6727 09:25:28.560523 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6728 09:25:28.563338 [Gating] SW calibration Done
6729 09:25:28.563459 ==
6730 09:25:28.566877 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 09:25:28.573164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 09:25:28.573283 ==
6733 09:25:28.573376 RX Vref Scan: 0
6734 09:25:28.573475
6735 09:25:28.576595 RX Vref 0 -> 0, step: 1
6736 09:25:28.576696
6737 09:25:28.579897 RX Delay -410 -> 252, step: 16
6738 09:25:28.583204 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6739 09:25:28.586614 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6740 09:25:28.593456 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6741 09:25:28.596316 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6742 09:25:28.600073 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6743 09:25:28.603035 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6744 09:25:28.609715 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6745 09:25:28.613360 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6746 09:25:28.616243 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6747 09:25:28.619871 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6748 09:25:28.626543 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6749 09:25:28.629425 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6750 09:25:28.632732 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6751 09:25:28.635968 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6752 09:25:28.642488 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6753 09:25:28.645981 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6754 09:25:28.646100 ==
6755 09:25:28.649601 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 09:25:28.652580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 09:25:28.652686 ==
6758 09:25:28.656216 DQS Delay:
6759 09:25:28.656320 DQS0 = 43, DQS1 = 51
6760 09:25:28.659124 DQM Delay:
6761 09:25:28.659224 DQM0 = 12, DQM1 = 14
6762 09:25:28.659317 DQ Delay:
6763 09:25:28.662476 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6764 09:25:28.665830 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6765 09:25:28.669238 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6766 09:25:28.672481 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6767 09:25:28.672590
6768 09:25:28.672681
6769 09:25:28.672770 ==
6770 09:25:28.676041 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 09:25:28.682301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 09:25:28.682428 ==
6773 09:25:28.682522
6774 09:25:28.682603
6775 09:25:28.682691 TX Vref Scan disable
6776 09:25:28.685729 == TX Byte 0 ==
6777 09:25:28.688759 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6778 09:25:28.692483 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6779 09:25:28.695485 == TX Byte 1 ==
6780 09:25:28.699101 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6781 09:25:28.702489 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6782 09:25:28.702634 ==
6783 09:25:28.705529 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 09:25:28.712083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 09:25:28.712226 ==
6786 09:25:28.712321
6787 09:25:28.712412
6788 09:25:28.712500 TX Vref Scan disable
6789 09:25:28.715551 == TX Byte 0 ==
6790 09:25:28.718797 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6791 09:25:28.721843 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6792 09:25:28.725330 == TX Byte 1 ==
6793 09:25:28.728462 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 09:25:28.732286 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 09:25:28.732403
6796 09:25:28.735108 [DATLAT]
6797 09:25:28.735209 Freq=400, CH1 RK0
6798 09:25:28.735294
6799 09:25:28.738593 DATLAT Default: 0xf
6800 09:25:28.738696 0, 0xFFFF, sum = 0
6801 09:25:28.742027 1, 0xFFFF, sum = 0
6802 09:25:28.742138 2, 0xFFFF, sum = 0
6803 09:25:28.745171 3, 0xFFFF, sum = 0
6804 09:25:28.745275 4, 0xFFFF, sum = 0
6805 09:25:28.748258 5, 0xFFFF, sum = 0
6806 09:25:28.751804 6, 0xFFFF, sum = 0
6807 09:25:28.751915 7, 0xFFFF, sum = 0
6808 09:25:28.754768 8, 0xFFFF, sum = 0
6809 09:25:28.754873 9, 0xFFFF, sum = 0
6810 09:25:28.758409 10, 0xFFFF, sum = 0
6811 09:25:28.758511 11, 0xFFFF, sum = 0
6812 09:25:28.761481 12, 0xFFFF, sum = 0
6813 09:25:28.761596 13, 0x0, sum = 1
6814 09:25:28.764920 14, 0x0, sum = 2
6815 09:25:28.765059 15, 0x0, sum = 3
6816 09:25:28.768596 16, 0x0, sum = 4
6817 09:25:28.768701 best_step = 14
6818 09:25:28.768794
6819 09:25:28.768880 ==
6820 09:25:28.771609 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 09:25:28.774504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 09:25:28.777789 ==
6823 09:25:28.777905 RX Vref Scan: 1
6824 09:25:28.778007
6825 09:25:28.781038 RX Vref 0 -> 0, step: 1
6826 09:25:28.781138
6827 09:25:28.784675 RX Delay -343 -> 252, step: 8
6828 09:25:28.784775
6829 09:25:28.788039 Set Vref, RX VrefLevel [Byte0]: 46
6830 09:25:28.791242 [Byte1]: 53
6831 09:25:28.791345
6832 09:25:28.794603 Final RX Vref Byte 0 = 46 to rank0
6833 09:25:28.797567 Final RX Vref Byte 1 = 53 to rank0
6834 09:25:28.800915 Final RX Vref Byte 0 = 46 to rank1
6835 09:25:28.804507 Final RX Vref Byte 1 = 53 to rank1==
6836 09:25:28.807608 Dram Type= 6, Freq= 0, CH_1, rank 0
6837 09:25:28.811036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 09:25:28.811150 ==
6839 09:25:28.814070 DQS Delay:
6840 09:25:28.814194 DQS0 = 44, DQS1 = 56
6841 09:25:28.817691 DQM Delay:
6842 09:25:28.817792 DQM0 = 8, DQM1 = 12
6843 09:25:28.821131 DQ Delay:
6844 09:25:28.821235 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6845 09:25:28.824396 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6846 09:25:28.827704 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6847 09:25:28.830641 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =20
6848 09:25:28.830751
6849 09:25:28.830841
6850 09:25:28.840707 [DQSOSCAuto] RK0, (LSB)MR18= 0x986e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6851 09:25:28.843810 CH1 RK0: MR19=C0C, MR18=986E
6852 09:25:28.847240 CH1_RK0: MR19=0xC0C, MR18=0x986E, DQSOSC=390, MR23=63, INC=388, DEC=258
6853 09:25:28.850804 ==
6854 09:25:28.853690 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 09:25:28.857071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 09:25:28.857184 ==
6857 09:25:28.860930 [Gating] SW mode calibration
6858 09:25:28.867366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6859 09:25:28.870157 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6860 09:25:28.876756 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6861 09:25:28.880363 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6862 09:25:28.883414 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6863 09:25:28.890304 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 09:25:28.893158 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 09:25:28.896691 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 09:25:28.903556 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6867 09:25:28.906865 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 09:25:28.909895 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6869 09:25:28.913338 Total UI for P1: 0, mck2ui 16
6870 09:25:28.916773 best dqsien dly found for B0: ( 0, 14, 24)
6871 09:25:28.919772 Total UI for P1: 0, mck2ui 16
6872 09:25:28.923271 best dqsien dly found for B1: ( 0, 14, 24)
6873 09:25:28.926616 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6874 09:25:28.932706 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6875 09:25:28.932834
6876 09:25:28.935944 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6877 09:25:28.939570 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6878 09:25:28.942657 [Gating] SW calibration Done
6879 09:25:28.942762 ==
6880 09:25:28.946253 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 09:25:28.949782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 09:25:28.949886 ==
6883 09:25:28.952712 RX Vref Scan: 0
6884 09:25:28.952811
6885 09:25:28.952929 RX Vref 0 -> 0, step: 1
6886 09:25:28.953015
6887 09:25:28.955748 RX Delay -410 -> 252, step: 16
6888 09:25:28.959210 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6889 09:25:28.965897 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6890 09:25:28.969609 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6891 09:25:28.972510 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6892 09:25:28.975883 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6893 09:25:28.982540 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6894 09:25:28.985582 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6895 09:25:28.988592 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6896 09:25:28.995205 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6897 09:25:28.998713 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6898 09:25:29.002208 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6899 09:25:29.005217 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6900 09:25:29.012217 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6901 09:25:29.015266 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6902 09:25:29.018225 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6903 09:25:29.025229 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6904 09:25:29.025361 ==
6905 09:25:29.028167 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 09:25:29.031986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 09:25:29.032096 ==
6908 09:25:29.032190 DQS Delay:
6909 09:25:29.035032 DQS0 = 51, DQS1 = 51
6910 09:25:29.035132 DQM Delay:
6911 09:25:29.038836 DQM0 = 19, DQM1 = 14
6912 09:25:29.038915 DQ Delay:
6913 09:25:29.041685 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6914 09:25:29.044984 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6915 09:25:29.048107 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6916 09:25:29.051427 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6917 09:25:29.051530
6918 09:25:29.051622
6919 09:25:29.051709 ==
6920 09:25:29.054531 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 09:25:29.058149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 09:25:29.058260 ==
6923 09:25:29.058353
6924 09:25:29.058440
6925 09:25:29.061086 TX Vref Scan disable
6926 09:25:29.061192 == TX Byte 0 ==
6927 09:25:29.068074 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6928 09:25:29.071368 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6929 09:25:29.071473 == TX Byte 1 ==
6930 09:25:29.077751 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6931 09:25:29.081331 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6932 09:25:29.081434 ==
6933 09:25:29.084299 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 09:25:29.087863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 09:25:29.087961 ==
6936 09:25:29.088052
6937 09:25:29.088140
6938 09:25:29.091445 TX Vref Scan disable
6939 09:25:29.094499 == TX Byte 0 ==
6940 09:25:29.097563 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6941 09:25:29.101143 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6942 09:25:29.104238 == TX Byte 1 ==
6943 09:25:29.107616 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6944 09:25:29.110763 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6945 09:25:29.110868
6946 09:25:29.110961 [DATLAT]
6947 09:25:29.114029 Freq=400, CH1 RK1
6948 09:25:29.114129
6949 09:25:29.114220 DATLAT Default: 0xe
6950 09:25:29.117469 0, 0xFFFF, sum = 0
6951 09:25:29.117577 1, 0xFFFF, sum = 0
6952 09:25:29.121008 2, 0xFFFF, sum = 0
6953 09:25:29.124008 3, 0xFFFF, sum = 0
6954 09:25:29.124120 4, 0xFFFF, sum = 0
6955 09:25:29.127629 5, 0xFFFF, sum = 0
6956 09:25:29.127710 6, 0xFFFF, sum = 0
6957 09:25:29.130788 7, 0xFFFF, sum = 0
6958 09:25:29.130894 8, 0xFFFF, sum = 0
6959 09:25:29.133870 9, 0xFFFF, sum = 0
6960 09:25:29.133973 10, 0xFFFF, sum = 0
6961 09:25:29.137459 11, 0xFFFF, sum = 0
6962 09:25:29.137565 12, 0xFFFF, sum = 0
6963 09:25:29.140781 13, 0x0, sum = 1
6964 09:25:29.140886 14, 0x0, sum = 2
6965 09:25:29.143940 15, 0x0, sum = 3
6966 09:25:29.144052 16, 0x0, sum = 4
6967 09:25:29.147274 best_step = 14
6968 09:25:29.147377
6969 09:25:29.147468 ==
6970 09:25:29.150507 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 09:25:29.154071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 09:25:29.154197 ==
6973 09:25:29.157267 RX Vref Scan: 0
6974 09:25:29.157360
6975 09:25:29.157423 RX Vref 0 -> 0, step: 1
6976 09:25:29.157481
6977 09:25:29.160374 RX Delay -343 -> 252, step: 8
6978 09:25:29.167998 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6979 09:25:29.171011 iDelay=217, Bit 1, Center -40 (-279 ~ 200) 480
6980 09:25:29.174410 iDelay=217, Bit 2, Center -48 (-287 ~ 192) 480
6981 09:25:29.181064 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6982 09:25:29.184503 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6983 09:25:29.188118 iDelay=217, Bit 5, Center -24 (-263 ~ 216) 480
6984 09:25:29.191132 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6985 09:25:29.197992 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6986 09:25:29.200767 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6987 09:25:29.204352 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6988 09:25:29.207445 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6989 09:25:29.213951 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6990 09:25:29.217304 iDelay=217, Bit 12, Center -36 (-287 ~ 216) 504
6991 09:25:29.220936 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6992 09:25:29.226881 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6993 09:25:29.230037 iDelay=217, Bit 15, Center -36 (-287 ~ 216) 504
6994 09:25:29.230128 ==
6995 09:25:29.233517 Dram Type= 6, Freq= 0, CH_1, rank 1
6996 09:25:29.237017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6997 09:25:29.237104 ==
6998 09:25:29.240018 DQS Delay:
6999 09:25:29.240104 DQS0 = 48, DQS1 = 56
7000 09:25:29.240171 DQM Delay:
7001 09:25:29.243440 DQM0 = 12, DQM1 = 10
7002 09:25:29.243525 DQ Delay:
7003 09:25:29.246632 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7004 09:25:29.250018 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
7005 09:25:29.253499 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7006 09:25:29.256471 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7007 09:25:29.256558
7008 09:25:29.256624
7009 09:25:29.266594 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e5f, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
7010 09:25:29.266719 CH1 RK1: MR19=C0C, MR18=6E5F
7011 09:25:29.272896 CH1_RK1: MR19=0xC0C, MR18=0x6E5F, DQSOSC=395, MR23=63, INC=378, DEC=252
7012 09:25:29.276002 [RxdqsGatingPostProcess] freq 400
7013 09:25:29.282950 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7014 09:25:29.286193 best DQS0 dly(2T, 0.5T) = (0, 10)
7015 09:25:29.289763 best DQS1 dly(2T, 0.5T) = (0, 10)
7016 09:25:29.292309 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7017 09:25:29.295828 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7018 09:25:29.299439 best DQS0 dly(2T, 0.5T) = (0, 10)
7019 09:25:29.303007 best DQS1 dly(2T, 0.5T) = (0, 10)
7020 09:25:29.305992 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7021 09:25:29.309048 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7022 09:25:29.312651 Pre-setting of DQS Precalculation
7023 09:25:29.316057 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7024 09:25:29.322736 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7025 09:25:29.329231 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7026 09:25:29.329332
7027 09:25:29.332033
7028 09:25:29.332148 [Calibration Summary] 800 Mbps
7029 09:25:29.335563 CH 0, Rank 0
7030 09:25:29.335674 SW Impedance : PASS
7031 09:25:29.338565 DUTY Scan : NO K
7032 09:25:29.342212 ZQ Calibration : PASS
7033 09:25:29.342313 Jitter Meter : NO K
7034 09:25:29.345250 CBT Training : PASS
7035 09:25:29.348801 Write leveling : PASS
7036 09:25:29.348904 RX DQS gating : PASS
7037 09:25:29.352136 RX DQ/DQS(RDDQC) : PASS
7038 09:25:29.355333 TX DQ/DQS : PASS
7039 09:25:29.355439 RX DATLAT : PASS
7040 09:25:29.358938 RX DQ/DQS(Engine): PASS
7041 09:25:29.362108 TX OE : NO K
7042 09:25:29.362229 All Pass.
7043 09:25:29.362324
7044 09:25:29.362414 CH 0, Rank 1
7045 09:25:29.365498 SW Impedance : PASS
7046 09:25:29.368352 DUTY Scan : NO K
7047 09:25:29.368452 ZQ Calibration : PASS
7048 09:25:29.371752 Jitter Meter : NO K
7049 09:25:29.375072 CBT Training : PASS
7050 09:25:29.375182 Write leveling : NO K
7051 09:25:29.378565 RX DQS gating : PASS
7052 09:25:29.381806 RX DQ/DQS(RDDQC) : PASS
7053 09:25:29.381908 TX DQ/DQS : PASS
7054 09:25:29.385110 RX DATLAT : PASS
7055 09:25:29.385208 RX DQ/DQS(Engine): PASS
7056 09:25:29.387915 TX OE : NO K
7057 09:25:29.388018 All Pass.
7058 09:25:29.388107
7059 09:25:29.391378 CH 1, Rank 0
7060 09:25:29.394559 SW Impedance : PASS
7061 09:25:29.394634 DUTY Scan : NO K
7062 09:25:29.398180 ZQ Calibration : PASS
7063 09:25:29.398270 Jitter Meter : NO K
7064 09:25:29.401148 CBT Training : PASS
7065 09:25:29.404770 Write leveling : PASS
7066 09:25:29.404869 RX DQS gating : PASS
7067 09:25:29.407872 RX DQ/DQS(RDDQC) : PASS
7068 09:25:29.411693 TX DQ/DQS : PASS
7069 09:25:29.411790 RX DATLAT : PASS
7070 09:25:29.414459 RX DQ/DQS(Engine): PASS
7071 09:25:29.417545 TX OE : NO K
7072 09:25:29.417646 All Pass.
7073 09:25:29.417736
7074 09:25:29.417822 CH 1, Rank 1
7075 09:25:29.421183 SW Impedance : PASS
7076 09:25:29.424150 DUTY Scan : NO K
7077 09:25:29.424267 ZQ Calibration : PASS
7078 09:25:29.427592 Jitter Meter : NO K
7079 09:25:29.431128 CBT Training : PASS
7080 09:25:29.431240 Write leveling : NO K
7081 09:25:29.434294 RX DQS gating : PASS
7082 09:25:29.437767 RX DQ/DQS(RDDQC) : PASS
7083 09:25:29.437872 TX DQ/DQS : PASS
7084 09:25:29.441178 RX DATLAT : PASS
7085 09:25:29.444323 RX DQ/DQS(Engine): PASS
7086 09:25:29.444429 TX OE : NO K
7087 09:25:29.447934 All Pass.
7088 09:25:29.448035
7089 09:25:29.448123 DramC Write-DBI off
7090 09:25:29.450930 PER_BANK_REFRESH: Hybrid Mode
7091 09:25:29.451000 TX_TRACKING: ON
7092 09:25:29.460787 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7093 09:25:29.464191 [FAST_K] Save calibration result to emmc
7094 09:25:29.467345 dramc_set_vcore_voltage set vcore to 725000
7095 09:25:29.470906 Read voltage for 1600, 0
7096 09:25:29.471009 Vio18 = 0
7097 09:25:29.474365 Vcore = 725000
7098 09:25:29.474470 Vdram = 0
7099 09:25:29.474562 Vddq = 0
7100 09:25:29.477211 Vmddr = 0
7101 09:25:29.480638 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7102 09:25:29.487399 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7103 09:25:29.487510 MEM_TYPE=3, freq_sel=13
7104 09:25:29.490723 sv_algorithm_assistance_LP4_3733
7105 09:25:29.497026 ============ PULL DRAM RESETB DOWN ============
7106 09:25:29.500376 ========== PULL DRAM RESETB DOWN end =========
7107 09:25:29.503899 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7108 09:25:29.506950 ===================================
7109 09:25:29.510086 LPDDR4 DRAM CONFIGURATION
7110 09:25:29.513193 ===================================
7111 09:25:29.516844 EX_ROW_EN[0] = 0x0
7112 09:25:29.516962 EX_ROW_EN[1] = 0x0
7113 09:25:29.519924 LP4Y_EN = 0x0
7114 09:25:29.520008 WORK_FSP = 0x1
7115 09:25:29.523340 WL = 0x5
7116 09:25:29.523422 RL = 0x5
7117 09:25:29.526633 BL = 0x2
7118 09:25:29.526717 RPST = 0x0
7119 09:25:29.529941 RD_PRE = 0x0
7120 09:25:29.530050 WR_PRE = 0x1
7121 09:25:29.533063 WR_PST = 0x1
7122 09:25:29.533172 DBI_WR = 0x0
7123 09:25:29.536792 DBI_RD = 0x0
7124 09:25:29.536899 OTF = 0x1
7125 09:25:29.539799 ===================================
7126 09:25:29.543385 ===================================
7127 09:25:29.546475 ANA top config
7128 09:25:29.550120 ===================================
7129 09:25:29.552996 DLL_ASYNC_EN = 0
7130 09:25:29.553208 ALL_SLAVE_EN = 0
7131 09:25:29.556470 NEW_RANK_MODE = 1
7132 09:25:29.560011 DLL_IDLE_MODE = 1
7133 09:25:29.563020 LP45_APHY_COMB_EN = 1
7134 09:25:29.566331 TX_ODT_DIS = 0
7135 09:25:29.566458 NEW_8X_MODE = 1
7136 09:25:29.569777 ===================================
7137 09:25:29.572813 ===================================
7138 09:25:29.576434 data_rate = 3200
7139 09:25:29.579377 CKR = 1
7140 09:25:29.582958 DQ_P2S_RATIO = 8
7141 09:25:29.585790 ===================================
7142 09:25:29.589451 CA_P2S_RATIO = 8
7143 09:25:29.592662 DQ_CA_OPEN = 0
7144 09:25:29.592856 DQ_SEMI_OPEN = 0
7145 09:25:29.596037 CA_SEMI_OPEN = 0
7146 09:25:29.599576 CA_FULL_RATE = 0
7147 09:25:29.602419 DQ_CKDIV4_EN = 0
7148 09:25:29.605901 CA_CKDIV4_EN = 0
7149 09:25:29.608898 CA_PREDIV_EN = 0
7150 09:25:29.609062 PH8_DLY = 12
7151 09:25:29.612248 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7152 09:25:29.615521 DQ_AAMCK_DIV = 4
7153 09:25:29.619244 CA_AAMCK_DIV = 4
7154 09:25:29.622135 CA_ADMCK_DIV = 4
7155 09:25:29.625515 DQ_TRACK_CA_EN = 0
7156 09:25:29.628618 CA_PICK = 1600
7157 09:25:29.628777 CA_MCKIO = 1600
7158 09:25:29.632117 MCKIO_SEMI = 0
7159 09:25:29.635638 PLL_FREQ = 3068
7160 09:25:29.639142 DQ_UI_PI_RATIO = 32
7161 09:25:29.642080 CA_UI_PI_RATIO = 0
7162 09:25:29.645729 ===================================
7163 09:25:29.648598 ===================================
7164 09:25:29.652187 memory_type:LPDDR4
7165 09:25:29.652341 GP_NUM : 10
7166 09:25:29.655190 SRAM_EN : 1
7167 09:25:29.655342 MD32_EN : 0
7168 09:25:29.658679 ===================================
7169 09:25:29.662375 [ANA_INIT] >>>>>>>>>>>>>>
7170 09:25:29.665290 <<<<<< [CONFIGURE PHASE]: ANA_TX
7171 09:25:29.668896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7172 09:25:29.671725 ===================================
7173 09:25:29.675332 data_rate = 3200,PCW = 0X7600
7174 09:25:29.678755 ===================================
7175 09:25:29.681907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7176 09:25:29.688801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7177 09:25:29.691601 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7178 09:25:29.698579 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7179 09:25:29.702044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7180 09:25:29.705256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7181 09:25:29.705415 [ANA_INIT] flow start
7182 09:25:29.708474 [ANA_INIT] PLL >>>>>>>>
7183 09:25:29.711249 [ANA_INIT] PLL <<<<<<<<
7184 09:25:29.711402 [ANA_INIT] MIDPI >>>>>>>>
7185 09:25:29.714902 [ANA_INIT] MIDPI <<<<<<<<
7186 09:25:29.718373 [ANA_INIT] DLL >>>>>>>>
7187 09:25:29.718529 [ANA_INIT] DLL <<<<<<<<
7188 09:25:29.721221 [ANA_INIT] flow end
7189 09:25:29.724799 ============ LP4 DIFF to SE enter ============
7190 09:25:29.731538 ============ LP4 DIFF to SE exit ============
7191 09:25:29.731707 [ANA_INIT] <<<<<<<<<<<<<
7192 09:25:29.734916 [Flow] Enable top DCM control >>>>>
7193 09:25:29.737899 [Flow] Enable top DCM control <<<<<
7194 09:25:29.741376 Enable DLL master slave shuffle
7195 09:25:29.747934 ==============================================================
7196 09:25:29.748101 Gating Mode config
7197 09:25:29.754412 ==============================================================
7198 09:25:29.757950 Config description:
7199 09:25:29.767401 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7200 09:25:29.773899 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7201 09:25:29.777699 SELPH_MODE 0: By rank 1: By Phase
7202 09:25:29.783941 ==============================================================
7203 09:25:29.787592 GAT_TRACK_EN = 1
7204 09:25:29.790667 RX_GATING_MODE = 2
7205 09:25:29.790825 RX_GATING_TRACK_MODE = 2
7206 09:25:29.793582 SELPH_MODE = 1
7207 09:25:29.797416 PICG_EARLY_EN = 1
7208 09:25:29.800236 VALID_LAT_VALUE = 1
7209 09:25:29.807017 ==============================================================
7210 09:25:29.810447 Enter into Gating configuration >>>>
7211 09:25:29.813215 Exit from Gating configuration <<<<
7212 09:25:29.816892 Enter into DVFS_PRE_config >>>>>
7213 09:25:29.826650 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7214 09:25:29.829723 Exit from DVFS_PRE_config <<<<<
7215 09:25:29.833170 Enter into PICG configuration >>>>
7216 09:25:29.836775 Exit from PICG configuration <<<<
7217 09:25:29.839765 [RX_INPUT] configuration >>>>>
7218 09:25:29.843293 [RX_INPUT] configuration <<<<<
7219 09:25:29.846383 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7220 09:25:29.852907 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7221 09:25:29.859489 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7222 09:25:29.866531 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7223 09:25:29.873025 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7224 09:25:29.879574 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7225 09:25:29.882880 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7226 09:25:29.885992 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7227 09:25:29.889591 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7228 09:25:29.892454 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7229 09:25:29.899053 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7230 09:25:29.902673 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7231 09:25:29.905638 ===================================
7232 09:25:29.909071 LPDDR4 DRAM CONFIGURATION
7233 09:25:29.912457 ===================================
7234 09:25:29.912563 EX_ROW_EN[0] = 0x0
7235 09:25:29.915426 EX_ROW_EN[1] = 0x0
7236 09:25:29.918972 LP4Y_EN = 0x0
7237 09:25:29.919058 WORK_FSP = 0x1
7238 09:25:29.922467 WL = 0x5
7239 09:25:29.922559 RL = 0x5
7240 09:25:29.925202 BL = 0x2
7241 09:25:29.925344 RPST = 0x0
7242 09:25:29.928872 RD_PRE = 0x0
7243 09:25:29.929074 WR_PRE = 0x1
7244 09:25:29.931990 WR_PST = 0x1
7245 09:25:29.932126 DBI_WR = 0x0
7246 09:25:29.935764 DBI_RD = 0x0
7247 09:25:29.935916 OTF = 0x1
7248 09:25:29.938671 ===================================
7249 09:25:29.941619 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7250 09:25:29.948556 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7251 09:25:29.952072 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7252 09:25:29.954908 ===================================
7253 09:25:29.957983 LPDDR4 DRAM CONFIGURATION
7254 09:25:29.961291 ===================================
7255 09:25:29.961458 EX_ROW_EN[0] = 0x10
7256 09:25:29.964907 EX_ROW_EN[1] = 0x0
7257 09:25:29.967988 LP4Y_EN = 0x0
7258 09:25:29.968090 WORK_FSP = 0x1
7259 09:25:29.971143 WL = 0x5
7260 09:25:29.971241 RL = 0x5
7261 09:25:29.974777 BL = 0x2
7262 09:25:29.974877 RPST = 0x0
7263 09:25:29.977884 RD_PRE = 0x0
7264 09:25:29.977992 WR_PRE = 0x1
7265 09:25:29.980954 WR_PST = 0x1
7266 09:25:29.981057 DBI_WR = 0x0
7267 09:25:29.984499 DBI_RD = 0x0
7268 09:25:29.984618 OTF = 0x1
7269 09:25:29.988040 ===================================
7270 09:25:29.994148 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7271 09:25:29.994278 ==
7272 09:25:29.997959 Dram Type= 6, Freq= 0, CH_0, rank 0
7273 09:25:30.004512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7274 09:25:30.004689 ==
7275 09:25:30.004785 [Duty_Offset_Calibration]
7276 09:25:30.007690 B0:1 B1:-1 CA:0
7277 09:25:30.007776
7278 09:25:30.010628 [DutyScan_Calibration_Flow] k_type=0
7279 09:25:30.020634
7280 09:25:30.020755 ==CLK 0==
7281 09:25:30.023622 Final CLK duty delay cell = 0
7282 09:25:30.027195 [0] MAX Duty = 5124%(X100), DQS PI = 22
7283 09:25:30.030043 [0] MIN Duty = 4907%(X100), DQS PI = 6
7284 09:25:30.030153 [0] AVG Duty = 5015%(X100)
7285 09:25:30.033518
7286 09:25:30.037053 CH0 CLK Duty spec in!! Max-Min= 217%
7287 09:25:30.040241 [DutyScan_Calibration_Flow] ====Done====
7288 09:25:30.040348
7289 09:25:30.043194 [DutyScan_Calibration_Flow] k_type=1
7290 09:25:30.059585
7291 09:25:30.059750 ==DQS 0 ==
7292 09:25:30.062457 Final DQS duty delay cell = -4
7293 09:25:30.065976 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7294 09:25:30.069277 [-4] MIN Duty = 4844%(X100), DQS PI = 10
7295 09:25:30.072588 [-4] AVG Duty = 4906%(X100)
7296 09:25:30.072709
7297 09:25:30.072804 ==DQS 1 ==
7298 09:25:30.075530 Final DQS duty delay cell = 0
7299 09:25:30.078797 [0] MAX Duty = 5156%(X100), DQS PI = 2
7300 09:25:30.082381 [0] MIN Duty = 5000%(X100), DQS PI = 20
7301 09:25:30.085377 [0] AVG Duty = 5078%(X100)
7302 09:25:30.085490
7303 09:25:30.088873 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7304 09:25:30.088978
7305 09:25:30.092349 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7306 09:25:30.095467 [DutyScan_Calibration_Flow] ====Done====
7307 09:25:30.095587
7308 09:25:30.098590 [DutyScan_Calibration_Flow] k_type=3
7309 09:25:30.117200
7310 09:25:30.117468 ==DQM 0 ==
7311 09:25:30.120032 Final DQM duty delay cell = 0
7312 09:25:30.123269 [0] MAX Duty = 5124%(X100), DQS PI = 22
7313 09:25:30.126860 [0] MIN Duty = 4907%(X100), DQS PI = 10
7314 09:25:30.129878 [0] AVG Duty = 5015%(X100)
7315 09:25:30.130032
7316 09:25:30.130118 ==DQM 1 ==
7317 09:25:30.133259 Final DQM duty delay cell = 0
7318 09:25:30.136801 [0] MAX Duty = 5000%(X100), DQS PI = 4
7319 09:25:30.139975 [0] MIN Duty = 4782%(X100), DQS PI = 20
7320 09:25:30.142961 [0] AVG Duty = 4891%(X100)
7321 09:25:30.143134
7322 09:25:30.146852 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7323 09:25:30.147096
7324 09:25:30.149884 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7325 09:25:30.153288 [DutyScan_Calibration_Flow] ====Done====
7326 09:25:30.153430
7327 09:25:30.156371 [DutyScan_Calibration_Flow] k_type=2
7328 09:25:30.172942
7329 09:25:30.173157 ==DQ 0 ==
7330 09:25:30.176373 Final DQ duty delay cell = -4
7331 09:25:30.179690 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7332 09:25:30.183252 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7333 09:25:30.186595 [-4] AVG Duty = 4953%(X100)
7334 09:25:30.186752
7335 09:25:30.186892 ==DQ 1 ==
7336 09:25:30.189773 Final DQ duty delay cell = 0
7337 09:25:30.193322 [0] MAX Duty = 5125%(X100), DQS PI = 2
7338 09:25:30.196150 [0] MIN Duty = 4969%(X100), DQS PI = 38
7339 09:25:30.199273 [0] AVG Duty = 5047%(X100)
7340 09:25:30.199434
7341 09:25:30.203240 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7342 09:25:30.203398
7343 09:25:30.206125 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7344 09:25:30.209314 [DutyScan_Calibration_Flow] ====Done====
7345 09:25:30.209472 ==
7346 09:25:30.212951 Dram Type= 6, Freq= 0, CH_1, rank 0
7347 09:25:30.216055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7348 09:25:30.216214 ==
7349 09:25:30.219124 [Duty_Offset_Calibration]
7350 09:25:30.219281 B0:-1 B1:1 CA:2
7351 09:25:30.219425
7352 09:25:30.222743 [DutyScan_Calibration_Flow] k_type=0
7353 09:25:30.233730
7354 09:25:30.233923 ==CLK 0==
7355 09:25:30.236707 Final CLK duty delay cell = 0
7356 09:25:30.240222 [0] MAX Duty = 5187%(X100), DQS PI = 22
7357 09:25:30.243447 [0] MIN Duty = 5000%(X100), DQS PI = 0
7358 09:25:30.243606 [0] AVG Duty = 5093%(X100)
7359 09:25:30.247251
7360 09:25:30.250155 CH1 CLK Duty spec in!! Max-Min= 187%
7361 09:25:30.253235 [DutyScan_Calibration_Flow] ====Done====
7362 09:25:30.253367
7363 09:25:30.257025 [DutyScan_Calibration_Flow] k_type=1
7364 09:25:30.273277
7365 09:25:30.273500 ==DQS 0 ==
7366 09:25:30.276816 Final DQS duty delay cell = 0
7367 09:25:30.279893 [0] MAX Duty = 5124%(X100), DQS PI = 18
7368 09:25:30.283297 [0] MIN Duty = 4907%(X100), DQS PI = 10
7369 09:25:30.286402 [0] AVG Duty = 5015%(X100)
7370 09:25:30.286536
7371 09:25:30.286620 ==DQS 1 ==
7372 09:25:30.289805 Final DQS duty delay cell = 0
7373 09:25:30.293323 [0] MAX Duty = 5093%(X100), DQS PI = 26
7374 09:25:30.296383 [0] MIN Duty = 4969%(X100), DQS PI = 54
7375 09:25:30.299890 [0] AVG Duty = 5031%(X100)
7376 09:25:30.300094
7377 09:25:30.302932 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7378 09:25:30.303030
7379 09:25:30.306535 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7380 09:25:30.309610 [DutyScan_Calibration_Flow] ====Done====
7381 09:25:30.309752
7382 09:25:30.312645 [DutyScan_Calibration_Flow] k_type=3
7383 09:25:30.330348
7384 09:25:30.330470 ==DQM 0 ==
7385 09:25:30.333625 Final DQM duty delay cell = 0
7386 09:25:30.336674 [0] MAX Duty = 5218%(X100), DQS PI = 18
7387 09:25:30.340267 [0] MIN Duty = 5031%(X100), DQS PI = 6
7388 09:25:30.343300 [0] AVG Duty = 5124%(X100)
7389 09:25:30.343428
7390 09:25:30.343496 ==DQM 1 ==
7391 09:25:30.346903 Final DQM duty delay cell = 0
7392 09:25:30.350159 [0] MAX Duty = 5156%(X100), DQS PI = 0
7393 09:25:30.353692 [0] MIN Duty = 4938%(X100), DQS PI = 34
7394 09:25:30.356644 [0] AVG Duty = 5047%(X100)
7395 09:25:30.356731
7396 09:25:30.360318 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7397 09:25:30.360411
7398 09:25:30.363153 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7399 09:25:30.366720 [DutyScan_Calibration_Flow] ====Done====
7400 09:25:30.366824
7401 09:25:30.369676 [DutyScan_Calibration_Flow] k_type=2
7402 09:25:30.387155
7403 09:25:30.387308 ==DQ 0 ==
7404 09:25:30.390641 Final DQ duty delay cell = 0
7405 09:25:30.393883 [0] MAX Duty = 5187%(X100), DQS PI = 32
7406 09:25:30.396770 [0] MIN Duty = 4906%(X100), DQS PI = 8
7407 09:25:30.396879 [0] AVG Duty = 5046%(X100)
7408 09:25:30.400178
7409 09:25:30.400279 ==DQ 1 ==
7410 09:25:30.403698 Final DQ duty delay cell = 0
7411 09:25:30.406965 [0] MAX Duty = 5156%(X100), DQS PI = 8
7412 09:25:30.410171 [0] MIN Duty = 4969%(X100), DQS PI = 32
7413 09:25:30.410289 [0] AVG Duty = 5062%(X100)
7414 09:25:30.410384
7415 09:25:30.413333 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7416 09:25:30.416980
7417 09:25:30.420182 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7418 09:25:30.423815 [DutyScan_Calibration_Flow] ====Done====
7419 09:25:30.426805 nWR fixed to 30
7420 09:25:30.426917 [ModeRegInit_LP4] CH0 RK0
7421 09:25:30.430153 [ModeRegInit_LP4] CH0 RK1
7422 09:25:30.433332 [ModeRegInit_LP4] CH1 RK0
7423 09:25:30.436355 [ModeRegInit_LP4] CH1 RK1
7424 09:25:30.436469 match AC timing 5
7425 09:25:30.443379 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7426 09:25:30.446210 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7427 09:25:30.449861 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7428 09:25:30.456338 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7429 09:25:30.459777 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7430 09:25:30.459880 [MiockJmeterHQA]
7431 09:25:30.459955
7432 09:25:30.463227 [DramcMiockJmeter] u1RxGatingPI = 0
7433 09:25:30.466007 0 : 4257, 4032
7434 09:25:30.466139 4 : 4255, 4029
7435 09:25:30.469728 8 : 4364, 4137
7436 09:25:30.469845 12 : 4257, 4029
7437 09:25:30.469953 16 : 4365, 4140
7438 09:25:30.472630 20 : 4252, 4027
7439 09:25:30.472746 24 : 4360, 4137
7440 09:25:30.476260 28 : 4252, 4027
7441 09:25:30.476361 32 : 4363, 4137
7442 09:25:30.479352 36 : 4253, 4027
7443 09:25:30.479465 40 : 4252, 4027
7444 09:25:30.483025 44 : 4254, 4029
7445 09:25:30.483159 48 : 4252, 4026
7446 09:25:30.486070 52 : 4252, 4027
7447 09:25:30.486235 56 : 4253, 4026
7448 09:25:30.486304 60 : 4253, 4027
7449 09:25:30.489285 64 : 4252, 4027
7450 09:25:30.489390 68 : 4366, 4140
7451 09:25:30.492923 72 : 4252, 4027
7452 09:25:30.493066 76 : 4255, 4030
7453 09:25:30.495990 80 : 4250, 4027
7454 09:25:30.496089 84 : 4363, 4137
7455 09:25:30.496166 88 : 4253, 4027
7456 09:25:30.499112 92 : 4250, 214
7457 09:25:30.499246 96 : 4360, 0
7458 09:25:30.502838 100 : 4252, 0
7459 09:25:30.503026 104 : 4250, 0
7460 09:25:30.503136 108 : 4361, 0
7461 09:25:30.505862 112 : 4363, 0
7462 09:25:30.506025 116 : 4250, 0
7463 09:25:30.508812 120 : 4250, 0
7464 09:25:30.508935 124 : 4255, 0
7465 09:25:30.509033 128 : 4249, 0
7466 09:25:30.512418 132 : 4363, 0
7467 09:25:30.512559 136 : 4255, 0
7468 09:25:30.515853 140 : 4250, 0
7469 09:25:30.515980 144 : 4250, 0
7470 09:25:30.516076 148 : 4363, 0
7471 09:25:30.519344 152 : 4250, 0
7472 09:25:30.519429 156 : 4360, 0
7473 09:25:30.522271 160 : 4361, 0
7474 09:25:30.522354 164 : 4248, 0
7475 09:25:30.522428 168 : 4250, 0
7476 09:25:30.525351 172 : 4250, 0
7477 09:25:30.525470 176 : 4250, 0
7478 09:25:30.528510 180 : 4360, 0
7479 09:25:30.528619 184 : 4250, 0
7480 09:25:30.528715 188 : 4250, 0
7481 09:25:30.532197 192 : 4250, 0
7482 09:25:30.532270 196 : 4250, 0
7483 09:25:30.532332 200 : 4250, 0
7484 09:25:30.535193 204 : 4250, 0
7485 09:25:30.535282 208 : 4250, 0
7486 09:25:30.539077 212 : 4366, 0
7487 09:25:30.539173 216 : 4360, 0
7488 09:25:30.539249 220 : 4361, 0
7489 09:25:30.542059 224 : 4250, 231
7490 09:25:30.542176 228 : 4360, 3529
7491 09:25:30.545492 232 : 4250, 4026
7492 09:25:30.545670 236 : 4252, 4029
7493 09:25:30.548430 240 : 4250, 4027
7494 09:25:30.548576 244 : 4253, 4027
7495 09:25:30.552103 248 : 4250, 4026
7496 09:25:30.552220 252 : 4253, 4029
7497 09:25:30.555223 256 : 4250, 4027
7498 09:25:30.555332 260 : 4360, 4138
7499 09:25:30.558307 264 : 4249, 4027
7500 09:25:30.558417 268 : 4250, 4026
7501 09:25:30.561866 272 : 4249, 4027
7502 09:25:30.561979 276 : 4250, 4027
7503 09:25:30.562064 280 : 4360, 4137
7504 09:25:30.565459 284 : 4250, 4027
7505 09:25:30.565572 288 : 4361, 4137
7506 09:25:30.568254 292 : 4250, 4027
7507 09:25:30.568423 296 : 4249, 4027
7508 09:25:30.571968 300 : 4250, 4026
7509 09:25:30.572120 304 : 4250, 4026
7510 09:25:30.574988 308 : 4252, 4027
7511 09:25:30.575128 312 : 4360, 4138
7512 09:25:30.578488 316 : 4250, 4027
7513 09:25:30.578627 320 : 4250, 4026
7514 09:25:30.581801 324 : 4255, 4029
7515 09:25:30.581930 328 : 4250, 4027
7516 09:25:30.584874 332 : 4360, 4137
7517 09:25:30.584968 336 : 4250, 3840
7518 09:25:30.585036 340 : 4363, 2087
7519 09:25:30.588614
7520 09:25:30.588698 MIOCK jitter meter ch=0
7521 09:25:30.588764
7522 09:25:30.591661 1T = (340-92) = 248 dly cells
7523 09:25:30.598311 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7524 09:25:30.598432 ==
7525 09:25:30.601498 Dram Type= 6, Freq= 0, CH_0, rank 0
7526 09:25:30.604555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 09:25:30.604646 ==
7528 09:25:30.611264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 09:25:30.614515 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 09:25:30.617628 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 09:25:30.624399 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 09:25:30.634415 [CA 0] Center 43 (13~74) winsize 62
7533 09:25:30.637454 [CA 1] Center 42 (12~73) winsize 62
7534 09:25:30.640481 [CA 2] Center 38 (9~68) winsize 60
7535 09:25:30.644153 [CA 3] Center 38 (8~68) winsize 61
7536 09:25:30.647438 [CA 4] Center 36 (7~66) winsize 60
7537 09:25:30.650817 [CA 5] Center 35 (6~65) winsize 60
7538 09:25:30.650921
7539 09:25:30.653632 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7540 09:25:30.653717
7541 09:25:30.657165 [CATrainingPosCal] consider 1 rank data
7542 09:25:30.660799 u2DelayCellTimex100 = 262/100 ps
7543 09:25:30.666821 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7544 09:25:30.670518 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7545 09:25:30.674237 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7546 09:25:30.677064 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7547 09:25:30.680033 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7548 09:25:30.683490 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7549 09:25:30.683585
7550 09:25:30.686948 CA PerBit enable=1, Macro0, CA PI delay=35
7551 09:25:30.687056
7552 09:25:30.689978 [CBTSetCACLKResult] CA Dly = 35
7553 09:25:30.693617 CS Dly: 12 (0~43)
7554 09:25:30.696762 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 09:25:30.700386 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 09:25:30.700477 ==
7557 09:25:30.703348 Dram Type= 6, Freq= 0, CH_0, rank 1
7558 09:25:30.710183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 09:25:30.710294 ==
7560 09:25:30.713248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7561 09:25:30.720073 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7562 09:25:30.723233 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7563 09:25:30.729499 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7564 09:25:30.737962 [CA 0] Center 43 (13~74) winsize 62
7565 09:25:30.740723 [CA 1] Center 44 (14~74) winsize 61
7566 09:25:30.743984 [CA 2] Center 38 (9~68) winsize 60
7567 09:25:30.747549 [CA 3] Center 38 (9~68) winsize 60
7568 09:25:30.750560 [CA 4] Center 36 (7~66) winsize 60
7569 09:25:30.754244 [CA 5] Center 36 (6~66) winsize 61
7570 09:25:30.754327
7571 09:25:30.757272 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7572 09:25:30.757355
7573 09:25:30.763561 [CATrainingPosCal] consider 2 rank data
7574 09:25:30.763645 u2DelayCellTimex100 = 262/100 ps
7575 09:25:30.770705 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7576 09:25:30.773679 CA1 delay=43 (14~73),Diff = 8 PI (29 cell)
7577 09:25:30.777509 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7578 09:25:30.780427 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7579 09:25:30.783511 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7580 09:25:30.786899 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7581 09:25:30.786981
7582 09:25:30.790320 CA PerBit enable=1, Macro0, CA PI delay=35
7583 09:25:30.790403
7584 09:25:30.793851 [CBTSetCACLKResult] CA Dly = 35
7585 09:25:30.796842 CS Dly: 12 (0~44)
7586 09:25:30.799949 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7587 09:25:30.803521 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7588 09:25:30.803602
7589 09:25:30.806514 ----->DramcWriteLeveling(PI) begin...
7590 09:25:30.810300 ==
7591 09:25:30.810382 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 09:25:30.816377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 09:25:30.816458 ==
7594 09:25:30.820075 Write leveling (Byte 0): 34 => 34
7595 09:25:30.823146 Write leveling (Byte 1): 28 => 28
7596 09:25:30.826287 DramcWriteLeveling(PI) end<-----
7597 09:25:30.826400
7598 09:25:30.826493 ==
7599 09:25:30.830046 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 09:25:30.833291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 09:25:30.833372 ==
7602 09:25:30.836401 [Gating] SW mode calibration
7603 09:25:30.843275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7604 09:25:30.849956 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7605 09:25:30.852826 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 09:25:30.856099 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 09:25:30.862975 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 09:25:30.865947 1 4 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7609 09:25:30.869286 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7610 09:25:30.875791 1 4 20 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7611 09:25:30.879500 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 09:25:30.882510 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 09:25:30.889211 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 09:25:30.892563 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7615 09:25:30.895937 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7616 09:25:30.902660 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7617 09:25:30.905815 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7618 09:25:30.908722 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
7619 09:25:30.915922 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7620 09:25:30.919058 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 09:25:30.922087 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 09:25:30.928950 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 09:25:30.932089 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 09:25:30.935210 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7625 09:25:30.941963 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7626 09:25:30.945044 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7627 09:25:30.948763 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7628 09:25:30.954998 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 09:25:30.958716 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 09:25:30.961605 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 09:25:30.968415 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 09:25:30.971712 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7633 09:25:30.975012 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7634 09:25:30.981687 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7635 09:25:30.984901 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 09:25:30.988242 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 09:25:30.994771 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 09:25:30.997832 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 09:25:31.001326 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 09:25:31.007576 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 09:25:31.011277 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 09:25:31.014129 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 09:25:31.020751 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 09:25:31.024439 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 09:25:31.027513 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 09:25:31.034405 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 09:25:31.037482 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 09:25:31.041169 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7649 09:25:31.044314 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7650 09:25:31.047403 Total UI for P1: 0, mck2ui 16
7651 09:25:31.051049 best dqsien dly found for B0: ( 1, 9, 12)
7652 09:25:31.057042 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7653 09:25:31.060798 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 09:25:31.063858 Total UI for P1: 0, mck2ui 16
7655 09:25:31.067114 best dqsien dly found for B1: ( 1, 9, 18)
7656 09:25:31.070727 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7657 09:25:31.073704 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7658 09:25:31.073790
7659 09:25:31.077091 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7660 09:25:31.083927 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7661 09:25:31.084044 [Gating] SW calibration Done
7662 09:25:31.086858 ==
7663 09:25:31.090229 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 09:25:31.093753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 09:25:31.093842 ==
7666 09:25:31.093911 RX Vref Scan: 0
7667 09:25:31.093996
7668 09:25:31.096817 RX Vref 0 -> 0, step: 1
7669 09:25:31.096925
7670 09:25:31.100187 RX Delay 0 -> 252, step: 8
7671 09:25:31.103739 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7672 09:25:31.106558 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7673 09:25:31.110026 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7674 09:25:31.116955 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7675 09:25:31.119988 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7676 09:25:31.123071 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7677 09:25:31.126255 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7678 09:25:31.130077 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7679 09:25:31.136230 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7680 09:25:31.139960 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7681 09:25:31.142978 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7682 09:25:31.146080 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7683 09:25:31.152856 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7684 09:25:31.156046 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7685 09:25:31.159798 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7686 09:25:31.162766 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7687 09:25:31.162840 ==
7688 09:25:31.165953 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 09:25:31.172741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 09:25:31.172831 ==
7691 09:25:31.172896 DQS Delay:
7692 09:25:31.175727 DQS0 = 0, DQS1 = 0
7693 09:25:31.175816 DQM Delay:
7694 09:25:31.175880 DQM0 = 135, DQM1 = 125
7695 09:25:31.179468 DQ Delay:
7696 09:25:31.182547 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7697 09:25:31.185533 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =147
7698 09:25:31.189003 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7699 09:25:31.192369 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7700 09:25:31.192445
7701 09:25:31.192508
7702 09:25:31.192566 ==
7703 09:25:31.195833 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 09:25:31.198854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 09:25:31.202403 ==
7706 09:25:31.202480
7707 09:25:31.202538
7708 09:25:31.202609 TX Vref Scan disable
7709 09:25:31.205858 == TX Byte 0 ==
7710 09:25:31.209062 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7711 09:25:31.212244 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7712 09:25:31.215424 == TX Byte 1 ==
7713 09:25:31.218817 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7714 09:25:31.225452 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7715 09:25:31.225591 ==
7716 09:25:31.228805 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 09:25:31.232062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 09:25:31.232186 ==
7719 09:25:31.244433
7720 09:25:31.248129 TX Vref early break, caculate TX vref
7721 09:25:31.251175 TX Vref=16, minBit 4, minWin=22, winSum=375
7722 09:25:31.254857 TX Vref=18, minBit 1, minWin=23, winSum=381
7723 09:25:31.258105 TX Vref=20, minBit 1, minWin=23, winSum=393
7724 09:25:31.261101 TX Vref=22, minBit 4, minWin=24, winSum=403
7725 09:25:31.264141 TX Vref=24, minBit 1, minWin=25, winSum=414
7726 09:25:31.270986 TX Vref=26, minBit 4, minWin=25, winSum=423
7727 09:25:31.274120 TX Vref=28, minBit 4, minWin=25, winSum=422
7728 09:25:31.277221 TX Vref=30, minBit 4, minWin=24, winSum=410
7729 09:25:31.280923 TX Vref=32, minBit 7, minWin=23, winSum=401
7730 09:25:31.283882 TX Vref=34, minBit 4, minWin=23, winSum=391
7731 09:25:31.290386 [TxChooseVref] Worse bit 4, Min win 25, Win sum 423, Final Vref 26
7732 09:25:31.290466
7733 09:25:31.294070 Final TX Range 0 Vref 26
7734 09:25:31.294221
7735 09:25:31.294286 ==
7736 09:25:31.297432 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 09:25:31.300215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 09:25:31.300289 ==
7739 09:25:31.300360
7740 09:25:31.300420
7741 09:25:31.303546 TX Vref Scan disable
7742 09:25:31.310341 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7743 09:25:31.310439 == TX Byte 0 ==
7744 09:25:31.314008 u2DelayCellOfst[0]=14 cells (4 PI)
7745 09:25:31.316987 u2DelayCellOfst[1]=18 cells (5 PI)
7746 09:25:31.319970 u2DelayCellOfst[2]=11 cells (3 PI)
7747 09:25:31.323558 u2DelayCellOfst[3]=14 cells (4 PI)
7748 09:25:31.326594 u2DelayCellOfst[4]=11 cells (3 PI)
7749 09:25:31.329996 u2DelayCellOfst[5]=0 cells (0 PI)
7750 09:25:31.333130 u2DelayCellOfst[6]=22 cells (6 PI)
7751 09:25:31.336770 u2DelayCellOfst[7]=22 cells (6 PI)
7752 09:25:31.339755 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7753 09:25:31.343491 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7754 09:25:31.346619 == TX Byte 1 ==
7755 09:25:31.350143 u2DelayCellOfst[8]=0 cells (0 PI)
7756 09:25:31.353165 u2DelayCellOfst[9]=0 cells (0 PI)
7757 09:25:31.356931 u2DelayCellOfst[10]=7 cells (2 PI)
7758 09:25:31.359939 u2DelayCellOfst[11]=3 cells (1 PI)
7759 09:25:31.363048 u2DelayCellOfst[12]=11 cells (3 PI)
7760 09:25:31.363121 u2DelayCellOfst[13]=11 cells (3 PI)
7761 09:25:31.366624 u2DelayCellOfst[14]=14 cells (4 PI)
7762 09:25:31.369758 u2DelayCellOfst[15]=11 cells (3 PI)
7763 09:25:31.376639 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7764 09:25:31.379862 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7765 09:25:31.382949 DramC Write-DBI on
7766 09:25:31.383061 ==
7767 09:25:31.386134 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 09:25:31.389049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 09:25:31.389158 ==
7770 09:25:31.389251
7771 09:25:31.389344
7772 09:25:31.392725 TX Vref Scan disable
7773 09:25:31.392837 == TX Byte 0 ==
7774 09:25:31.398890 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7775 09:25:31.398993 == TX Byte 1 ==
7776 09:25:31.402603 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7777 09:25:31.405540 DramC Write-DBI off
7778 09:25:31.405612
7779 09:25:31.405673 [DATLAT]
7780 09:25:31.409140 Freq=1600, CH0 RK0
7781 09:25:31.409213
7782 09:25:31.409273 DATLAT Default: 0xf
7783 09:25:31.412623 0, 0xFFFF, sum = 0
7784 09:25:31.415786 1, 0xFFFF, sum = 0
7785 09:25:31.415866 2, 0xFFFF, sum = 0
7786 09:25:31.418872 3, 0xFFFF, sum = 0
7787 09:25:31.418975 4, 0xFFFF, sum = 0
7788 09:25:31.422352 5, 0xFFFF, sum = 0
7789 09:25:31.422440 6, 0xFFFF, sum = 0
7790 09:25:31.425390 7, 0xFFFF, sum = 0
7791 09:25:31.425477 8, 0xFFFF, sum = 0
7792 09:25:31.429066 9, 0xFFFF, sum = 0
7793 09:25:31.429144 10, 0xFFFF, sum = 0
7794 09:25:31.432337 11, 0xFFFF, sum = 0
7795 09:25:31.432440 12, 0xFFFF, sum = 0
7796 09:25:31.435702 13, 0xFFFF, sum = 0
7797 09:25:31.435784 14, 0x0, sum = 1
7798 09:25:31.438573 15, 0x0, sum = 2
7799 09:25:31.438654 16, 0x0, sum = 3
7800 09:25:31.442144 17, 0x0, sum = 4
7801 09:25:31.442273 best_step = 15
7802 09:25:31.442338
7803 09:25:31.442397 ==
7804 09:25:31.445120 Dram Type= 6, Freq= 0, CH_0, rank 0
7805 09:25:31.452030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7806 09:25:31.452140 ==
7807 09:25:31.452278 RX Vref Scan: 1
7808 09:25:31.452376
7809 09:25:31.455400 Set Vref Range= 24 -> 127
7810 09:25:31.455471
7811 09:25:31.458366 RX Vref 24 -> 127, step: 1
7812 09:25:31.458473
7813 09:25:31.458538 RX Delay 11 -> 252, step: 4
7814 09:25:31.462084
7815 09:25:31.462264 Set Vref, RX VrefLevel [Byte0]: 24
7816 09:25:31.465156 [Byte1]: 24
7817 09:25:31.469575
7818 09:25:31.469723 Set Vref, RX VrefLevel [Byte0]: 25
7819 09:25:31.472570 [Byte1]: 25
7820 09:25:31.476890
7821 09:25:31.477003 Set Vref, RX VrefLevel [Byte0]: 26
7822 09:25:31.479959 [Byte1]: 26
7823 09:25:31.484919
7824 09:25:31.485035 Set Vref, RX VrefLevel [Byte0]: 27
7825 09:25:31.488016 [Byte1]: 27
7826 09:25:31.492375
7827 09:25:31.492481 Set Vref, RX VrefLevel [Byte0]: 28
7828 09:25:31.495308 [Byte1]: 28
7829 09:25:31.499800
7830 09:25:31.502907 Set Vref, RX VrefLevel [Byte0]: 29
7831 09:25:31.506509 [Byte1]: 29
7832 09:25:31.506588
7833 09:25:31.509652 Set Vref, RX VrefLevel [Byte0]: 30
7834 09:25:31.512753 [Byte1]: 30
7835 09:25:31.512876
7836 09:25:31.516289 Set Vref, RX VrefLevel [Byte0]: 31
7837 09:25:31.519164 [Byte1]: 31
7838 09:25:31.522475
7839 09:25:31.522551 Set Vref, RX VrefLevel [Byte0]: 32
7840 09:25:31.526118 [Byte1]: 32
7841 09:25:31.530395
7842 09:25:31.530493 Set Vref, RX VrefLevel [Byte0]: 33
7843 09:25:31.533293 [Byte1]: 33
7844 09:25:31.537584
7845 09:25:31.537688 Set Vref, RX VrefLevel [Byte0]: 34
7846 09:25:31.541089 [Byte1]: 34
7847 09:25:31.545360
7848 09:25:31.545445 Set Vref, RX VrefLevel [Byte0]: 35
7849 09:25:31.548896 [Byte1]: 35
7850 09:25:31.553148
7851 09:25:31.553252 Set Vref, RX VrefLevel [Byte0]: 36
7852 09:25:31.556300 [Byte1]: 36
7853 09:25:31.560547
7854 09:25:31.560652 Set Vref, RX VrefLevel [Byte0]: 37
7855 09:25:31.564010 [Byte1]: 37
7856 09:25:31.568385
7857 09:25:31.568491 Set Vref, RX VrefLevel [Byte0]: 38
7858 09:25:31.571647 [Byte1]: 38
7859 09:25:31.575788
7860 09:25:31.575869 Set Vref, RX VrefLevel [Byte0]: 39
7861 09:25:31.579562 [Byte1]: 39
7862 09:25:31.583331
7863 09:25:31.583444 Set Vref, RX VrefLevel [Byte0]: 40
7864 09:25:31.586907 [Byte1]: 40
7865 09:25:31.591043
7866 09:25:31.591174 Set Vref, RX VrefLevel [Byte0]: 41
7867 09:25:31.594776 [Byte1]: 41
7868 09:25:31.599191
7869 09:25:31.599313 Set Vref, RX VrefLevel [Byte0]: 42
7870 09:25:31.602133 [Byte1]: 42
7871 09:25:31.606786
7872 09:25:31.606950 Set Vref, RX VrefLevel [Byte0]: 43
7873 09:25:31.609480 [Byte1]: 43
7874 09:25:31.614179
7875 09:25:31.614293 Set Vref, RX VrefLevel [Byte0]: 44
7876 09:25:31.617486 [Byte1]: 44
7877 09:25:31.621609
7878 09:25:31.621702 Set Vref, RX VrefLevel [Byte0]: 45
7879 09:25:31.624627 [Byte1]: 45
7880 09:25:31.629373
7881 09:25:31.629459 Set Vref, RX VrefLevel [Byte0]: 46
7882 09:25:31.632196 [Byte1]: 46
7883 09:25:31.636510
7884 09:25:31.636625 Set Vref, RX VrefLevel [Byte0]: 47
7885 09:25:31.639904 [Byte1]: 47
7886 09:25:31.644231
7887 09:25:31.644341 Set Vref, RX VrefLevel [Byte0]: 48
7888 09:25:31.647949 [Byte1]: 48
7889 09:25:31.652054
7890 09:25:31.652148 Set Vref, RX VrefLevel [Byte0]: 49
7891 09:25:31.655654 [Byte1]: 49
7892 09:25:31.659449
7893 09:25:31.659526 Set Vref, RX VrefLevel [Byte0]: 50
7894 09:25:31.663217 [Byte1]: 50
7895 09:25:31.667392
7896 09:25:31.667471 Set Vref, RX VrefLevel [Byte0]: 51
7897 09:25:31.670505 [Byte1]: 51
7898 09:25:31.674713
7899 09:25:31.674831 Set Vref, RX VrefLevel [Byte0]: 52
7900 09:25:31.678072 [Byte1]: 52
7901 09:25:31.682583
7902 09:25:31.682673 Set Vref, RX VrefLevel [Byte0]: 53
7903 09:25:31.685926 [Byte1]: 53
7904 09:25:31.690303
7905 09:25:31.690384 Set Vref, RX VrefLevel [Byte0]: 54
7906 09:25:31.693347 [Byte1]: 54
7907 09:25:31.697593
7908 09:25:31.700728 Set Vref, RX VrefLevel [Byte0]: 55
7909 09:25:31.704379 [Byte1]: 55
7910 09:25:31.704463
7911 09:25:31.707494 Set Vref, RX VrefLevel [Byte0]: 56
7912 09:25:31.710535 [Byte1]: 56
7913 09:25:31.710617
7914 09:25:31.714312 Set Vref, RX VrefLevel [Byte0]: 57
7915 09:25:31.717418 [Byte1]: 57
7916 09:25:31.720635
7917 09:25:31.720717 Set Vref, RX VrefLevel [Byte0]: 58
7918 09:25:31.723576 [Byte1]: 58
7919 09:25:31.727939
7920 09:25:31.728022 Set Vref, RX VrefLevel [Byte0]: 59
7921 09:25:31.731449 [Byte1]: 59
7922 09:25:31.735551
7923 09:25:31.735647 Set Vref, RX VrefLevel [Byte0]: 60
7924 09:25:31.739127 [Byte1]: 60
7925 09:25:31.743298
7926 09:25:31.743404 Set Vref, RX VrefLevel [Byte0]: 61
7927 09:25:31.746444 [Byte1]: 61
7928 09:25:31.750841
7929 09:25:31.750995 Set Vref, RX VrefLevel [Byte0]: 62
7930 09:25:31.754180 [Byte1]: 62
7931 09:25:31.758881
7932 09:25:31.758986 Set Vref, RX VrefLevel [Byte0]: 63
7933 09:25:31.761928 [Byte1]: 63
7934 09:25:31.766200
7935 09:25:31.766290 Set Vref, RX VrefLevel [Byte0]: 64
7936 09:25:31.769394 [Byte1]: 64
7937 09:25:31.773573
7938 09:25:31.773656 Set Vref, RX VrefLevel [Byte0]: 65
7939 09:25:31.777324 [Byte1]: 65
7940 09:25:31.781512
7941 09:25:31.781623 Set Vref, RX VrefLevel [Byte0]: 66
7942 09:25:31.785193 [Byte1]: 66
7943 09:25:31.789296
7944 09:25:31.789381 Set Vref, RX VrefLevel [Byte0]: 67
7945 09:25:31.792683 [Byte1]: 67
7946 09:25:31.796732
7947 09:25:31.796842 Set Vref, RX VrefLevel [Byte0]: 68
7948 09:25:31.800189 [Byte1]: 68
7949 09:25:31.804513
7950 09:25:31.804588 Set Vref, RX VrefLevel [Byte0]: 69
7951 09:25:31.807510 [Byte1]: 69
7952 09:25:31.811861
7953 09:25:31.811939 Set Vref, RX VrefLevel [Byte0]: 70
7954 09:25:31.815020 [Byte1]: 70
7955 09:25:31.819448
7956 09:25:31.819530 Set Vref, RX VrefLevel [Byte0]: 71
7957 09:25:31.822971 [Byte1]: 71
7958 09:25:31.827393
7959 09:25:31.827503 Set Vref, RX VrefLevel [Byte0]: 72
7960 09:25:31.830507 [Byte1]: 72
7961 09:25:31.834824
7962 09:25:31.834976 Set Vref, RX VrefLevel [Byte0]: 73
7963 09:25:31.838424 [Byte1]: 73
7964 09:25:31.842174
7965 09:25:31.842278 Set Vref, RX VrefLevel [Byte0]: 74
7966 09:25:31.845881 [Byte1]: 74
7967 09:25:31.849818
7968 09:25:31.849904 Set Vref, RX VrefLevel [Byte0]: 75
7969 09:25:31.853165 [Byte1]: 75
7970 09:25:31.857436
7971 09:25:31.857519 Set Vref, RX VrefLevel [Byte0]: 76
7972 09:25:31.860849 [Byte1]: 76
7973 09:25:31.865441
7974 09:25:31.865627 Set Vref, RX VrefLevel [Byte0]: 77
7975 09:25:31.868214 [Byte1]: 77
7976 09:25:31.873090
7977 09:25:31.873266 Set Vref, RX VrefLevel [Byte0]: 78
7978 09:25:31.876144 [Byte1]: 78
7979 09:25:31.880448
7980 09:25:31.880601 Final RX Vref Byte 0 = 66 to rank0
7981 09:25:31.883563 Final RX Vref Byte 1 = 58 to rank0
7982 09:25:31.887373 Final RX Vref Byte 0 = 66 to rank1
7983 09:25:31.890375 Final RX Vref Byte 1 = 58 to rank1==
7984 09:25:31.893371 Dram Type= 6, Freq= 0, CH_0, rank 0
7985 09:25:31.899909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7986 09:25:31.900026 ==
7987 09:25:31.900095 DQS Delay:
7988 09:25:31.903348 DQS0 = 0, DQS1 = 0
7989 09:25:31.903435 DQM Delay:
7990 09:25:31.903499 DQM0 = 133, DQM1 = 122
7991 09:25:31.906662 DQ Delay:
7992 09:25:31.910252 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
7993 09:25:31.913512 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
7994 09:25:31.916942 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =118
7995 09:25:31.920006 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
7996 09:25:31.920091
7997 09:25:31.920155
7998 09:25:31.920214
7999 09:25:31.923274 [DramC_TX_OE_Calibration] TA2
8000 09:25:31.926953 Original DQ_B0 (3 6) =30, OEN = 27
8001 09:25:31.929839 Original DQ_B1 (3 6) =30, OEN = 27
8002 09:25:31.933555 24, 0x0, End_B0=24 End_B1=24
8003 09:25:31.933662 25, 0x0, End_B0=25 End_B1=25
8004 09:25:31.936649 26, 0x0, End_B0=26 End_B1=26
8005 09:25:31.939717 27, 0x0, End_B0=27 End_B1=27
8006 09:25:31.943396 28, 0x0, End_B0=28 End_B1=28
8007 09:25:31.946498 29, 0x0, End_B0=29 End_B1=29
8008 09:25:31.946652 30, 0x0, End_B0=30 End_B1=30
8009 09:25:31.949528 31, 0x4141, End_B0=30 End_B1=30
8010 09:25:31.953408 Byte0 end_step=30 best_step=27
8011 09:25:31.956444 Byte1 end_step=30 best_step=27
8012 09:25:31.959461 Byte0 TX OE(2T, 0.5T) = (3, 3)
8013 09:25:31.962971 Byte1 TX OE(2T, 0.5T) = (3, 3)
8014 09:25:31.963092
8015 09:25:31.963186
8016 09:25:31.969875 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8017 09:25:31.973219 CH0 RK0: MR19=303, MR18=2112
8018 09:25:31.979549 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8019 09:25:31.979668
8020 09:25:31.983076 ----->DramcWriteLeveling(PI) begin...
8021 09:25:31.983191 ==
8022 09:25:31.986238 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 09:25:31.989310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 09:25:31.989421 ==
8025 09:25:31.993033 Write leveling (Byte 0): 36 => 36
8026 09:25:31.996075 Write leveling (Byte 1): 28 => 28
8027 09:25:31.999581 DramcWriteLeveling(PI) end<-----
8028 09:25:31.999710
8029 09:25:31.999815 ==
8030 09:25:32.003105 Dram Type= 6, Freq= 0, CH_0, rank 1
8031 09:25:32.006307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8032 09:25:32.006390 ==
8033 09:25:32.009270 [Gating] SW mode calibration
8034 09:25:32.015960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8035 09:25:32.022673 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8036 09:25:32.025732 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 09:25:32.032557 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 09:25:32.036214 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 09:25:32.039300 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8040 09:25:32.045420 1 4 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8041 09:25:32.048950 1 4 20 | B1->B0 | 2d2d 3434 | 0 1 | (1 1) (1 1)
8042 09:25:32.052557 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 09:25:32.058829 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 09:25:32.061995 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 09:25:32.065556 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 09:25:32.071992 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8047 09:25:32.075661 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8048 09:25:32.078613 1 5 16 | B1->B0 | 3434 2828 | 1 1 | (1 0) (1 0)
8049 09:25:32.085056 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8050 09:25:32.088513 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 09:25:32.091574 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 09:25:32.098367 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 09:25:32.101963 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 09:25:32.105068 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 09:25:32.111811 1 6 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8056 09:25:32.114917 1 6 16 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
8057 09:25:32.117981 1 6 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8058 09:25:32.125059 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 09:25:32.128139 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 09:25:32.131509 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 09:25:32.138024 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 09:25:32.141165 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8063 09:25:32.144956 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8064 09:25:32.151136 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8065 09:25:32.154520 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 09:25:32.157638 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 09:25:32.164409 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 09:25:32.168061 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 09:25:32.171195 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 09:25:32.177760 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 09:25:32.181440 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 09:25:32.184228 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 09:25:32.191116 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 09:25:32.194110 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 09:25:32.197511 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 09:25:32.204199 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 09:25:32.207216 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 09:25:32.210844 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 09:25:32.217604 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8080 09:25:32.220759 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8081 09:25:32.223998 Total UI for P1: 0, mck2ui 16
8082 09:25:32.227501 best dqsien dly found for B0: ( 1, 9, 12)
8083 09:25:32.230596 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8084 09:25:32.236867 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 09:25:32.237256 Total UI for P1: 0, mck2ui 16
8086 09:25:32.244074 best dqsien dly found for B1: ( 1, 9, 18)
8087 09:25:32.247061 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8088 09:25:32.250855 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8089 09:25:32.251352
8090 09:25:32.253992 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8091 09:25:32.256986 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8092 09:25:32.260554 [Gating] SW calibration Done
8093 09:25:32.260938 ==
8094 09:25:32.263524 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 09:25:32.267344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 09:25:32.267730 ==
8097 09:25:32.270305 RX Vref Scan: 0
8098 09:25:32.270691
8099 09:25:32.270991 RX Vref 0 -> 0, step: 1
8100 09:25:32.271278
8101 09:25:32.273479 RX Delay 0 -> 252, step: 8
8102 09:25:32.277122 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8103 09:25:32.283784 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8104 09:25:32.286846 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8105 09:25:32.290451 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8106 09:25:32.293591 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8107 09:25:32.296631 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8108 09:25:32.303192 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8109 09:25:32.306725 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8110 09:25:32.309737 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8111 09:25:32.313052 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8112 09:25:32.316507 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8113 09:25:32.323238 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8114 09:25:32.326315 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8115 09:25:32.329315 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8116 09:25:32.333162 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8117 09:25:32.339351 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8118 09:25:32.339441 ==
8119 09:25:32.342636 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 09:25:32.346025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 09:25:32.346151 ==
8122 09:25:32.346241 DQS Delay:
8123 09:25:32.349453 DQS0 = 0, DQS1 = 0
8124 09:25:32.349555 DQM Delay:
8125 09:25:32.352734 DQM0 = 132, DQM1 = 129
8126 09:25:32.352840 DQ Delay:
8127 09:25:32.355911 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8128 09:25:32.359348 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8129 09:25:32.362195 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8130 09:25:32.365733 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8131 09:25:32.365872
8132 09:25:32.369312
8133 09:25:32.369469 ==
8134 09:25:32.372336 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 09:25:32.376118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 09:25:32.376308 ==
8137 09:25:32.376451
8138 09:25:32.376583
8139 09:25:32.379382 TX Vref Scan disable
8140 09:25:32.379593 == TX Byte 0 ==
8141 09:25:32.386085 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8142 09:25:32.389200 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8143 09:25:32.389533 == TX Byte 1 ==
8144 09:25:32.395940 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8145 09:25:32.399035 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8146 09:25:32.399452 ==
8147 09:25:32.402208 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 09:25:32.405330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 09:25:32.405766 ==
8150 09:25:32.418587
8151 09:25:32.422154 TX Vref early break, caculate TX vref
8152 09:25:32.425139 TX Vref=16, minBit 3, minWin=22, winSum=379
8153 09:25:32.428272 TX Vref=18, minBit 0, minWin=23, winSum=390
8154 09:25:32.431866 TX Vref=20, minBit 0, minWin=23, winSum=394
8155 09:25:32.435195 TX Vref=22, minBit 0, minWin=23, winSum=400
8156 09:25:32.438761 TX Vref=24, minBit 6, minWin=24, winSum=411
8157 09:25:32.444855 TX Vref=26, minBit 0, minWin=25, winSum=417
8158 09:25:32.448589 TX Vref=28, minBit 1, minWin=24, winSum=415
8159 09:25:32.451725 TX Vref=30, minBit 0, minWin=24, winSum=406
8160 09:25:32.454707 TX Vref=32, minBit 7, minWin=23, winSum=395
8161 09:25:32.462000 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 26
8162 09:25:32.462598
8163 09:25:32.464929 Final TX Range 0 Vref 26
8164 09:25:32.465387
8165 09:25:32.465717 ==
8166 09:25:32.468575 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 09:25:32.471883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 09:25:32.472299 ==
8169 09:25:32.472622
8170 09:25:32.472924
8171 09:25:32.474838 TX Vref Scan disable
8172 09:25:32.488275 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8173 09:25:32.488718 == TX Byte 0 ==
8174 09:25:32.489047 u2DelayCellOfst[0]=11 cells (3 PI)
8175 09:25:32.489353 u2DelayCellOfst[1]=14 cells (4 PI)
8176 09:25:32.491370 u2DelayCellOfst[2]=11 cells (3 PI)
8177 09:25:32.494956 u2DelayCellOfst[3]=14 cells (4 PI)
8178 09:25:32.497898 u2DelayCellOfst[4]=7 cells (2 PI)
8179 09:25:32.501389 u2DelayCellOfst[5]=0 cells (0 PI)
8180 09:25:32.504482 u2DelayCellOfst[6]=14 cells (4 PI)
8181 09:25:32.508478 u2DelayCellOfst[7]=14 cells (4 PI)
8182 09:25:32.511141 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8183 09:25:32.514622 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8184 09:25:32.517724 == TX Byte 1 ==
8185 09:25:32.518138 u2DelayCellOfst[8]=0 cells (0 PI)
8186 09:25:32.521191 u2DelayCellOfst[9]=3 cells (1 PI)
8187 09:25:32.524625 u2DelayCellOfst[10]=7 cells (2 PI)
8188 09:25:32.527901 u2DelayCellOfst[11]=3 cells (1 PI)
8189 09:25:32.530870 u2DelayCellOfst[12]=14 cells (4 PI)
8190 09:25:32.534400 u2DelayCellOfst[13]=11 cells (3 PI)
8191 09:25:32.537367 u2DelayCellOfst[14]=18 cells (5 PI)
8192 09:25:32.540560 u2DelayCellOfst[15]=11 cells (3 PI)
8193 09:25:32.544419 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8194 09:25:32.550637 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8195 09:25:32.551175 DramC Write-DBI on
8196 09:25:32.551717 ==
8197 09:25:32.554479 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 09:25:32.560577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 09:25:32.561225 ==
8200 09:25:32.561649
8201 09:25:32.562123
8202 09:25:32.562688 TX Vref Scan disable
8203 09:25:32.564239 == TX Byte 0 ==
8204 09:25:32.567941 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8205 09:25:32.571120 == TX Byte 1 ==
8206 09:25:32.574030 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8207 09:25:32.577682 DramC Write-DBI off
8208 09:25:32.578288
8209 09:25:32.578739 [DATLAT]
8210 09:25:32.579179 Freq=1600, CH0 RK1
8211 09:25:32.579631
8212 09:25:32.580585 DATLAT Default: 0xf
8213 09:25:32.584037 0, 0xFFFF, sum = 0
8214 09:25:32.584537 1, 0xFFFF, sum = 0
8215 09:25:32.587524 2, 0xFFFF, sum = 0
8216 09:25:32.588042 3, 0xFFFF, sum = 0
8217 09:25:32.590724 4, 0xFFFF, sum = 0
8218 09:25:32.591168 5, 0xFFFF, sum = 0
8219 09:25:32.593804 6, 0xFFFF, sum = 0
8220 09:25:32.594279 7, 0xFFFF, sum = 0
8221 09:25:32.597599 8, 0xFFFF, sum = 0
8222 09:25:32.598021 9, 0xFFFF, sum = 0
8223 09:25:32.600586 10, 0xFFFF, sum = 0
8224 09:25:32.601006 11, 0xFFFF, sum = 0
8225 09:25:32.603998 12, 0xFFFF, sum = 0
8226 09:25:32.604080 13, 0xFFFF, sum = 0
8227 09:25:32.607118 14, 0x0, sum = 1
8228 09:25:32.607200 15, 0x0, sum = 2
8229 09:25:32.609895 16, 0x0, sum = 3
8230 09:25:32.609976 17, 0x0, sum = 4
8231 09:25:32.613637 best_step = 15
8232 09:25:32.613718
8233 09:25:32.613780 ==
8234 09:25:32.616668 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 09:25:32.619656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 09:25:32.619737 ==
8237 09:25:32.623366 RX Vref Scan: 0
8238 09:25:32.623447
8239 09:25:32.623511 RX Vref 0 -> 0, step: 1
8240 09:25:32.623571
8241 09:25:32.626466 RX Delay 11 -> 252, step: 4
8242 09:25:32.633023 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8243 09:25:32.636462 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8244 09:25:32.639780 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8245 09:25:32.642680 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8246 09:25:32.646409 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8247 09:25:32.652610 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8248 09:25:32.656369 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8249 09:25:32.659348 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8250 09:25:32.662483 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8251 09:25:32.666124 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8252 09:25:32.672897 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8253 09:25:32.675863 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8254 09:25:32.679484 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8255 09:25:32.682651 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8256 09:25:32.689457 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8257 09:25:32.692634 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8258 09:25:32.692715 ==
8259 09:25:32.696147 Dram Type= 6, Freq= 0, CH_0, rank 1
8260 09:25:32.699130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 09:25:32.699212 ==
8262 09:25:32.702620 DQS Delay:
8263 09:25:32.702700 DQS0 = 0, DQS1 = 0
8264 09:25:32.702763 DQM Delay:
8265 09:25:32.705427 DQM0 = 130, DQM1 = 125
8266 09:25:32.705507 DQ Delay:
8267 09:25:32.708758 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8268 09:25:32.712302 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8269 09:25:32.718807 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8270 09:25:32.722319 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8271 09:25:32.722411
8272 09:25:32.722475
8273 09:25:32.722541
8274 09:25:32.725222 [DramC_TX_OE_Calibration] TA2
8275 09:25:32.728359 Original DQ_B0 (3 6) =30, OEN = 27
8276 09:25:32.732077 Original DQ_B1 (3 6) =30, OEN = 27
8277 09:25:32.732189 24, 0x0, End_B0=24 End_B1=24
8278 09:25:32.735227 25, 0x0, End_B0=25 End_B1=25
8279 09:25:32.738842 26, 0x0, End_B0=26 End_B1=26
8280 09:25:32.741985 27, 0x0, End_B0=27 End_B1=27
8281 09:25:32.742095 28, 0x0, End_B0=28 End_B1=28
8282 09:25:32.745302 29, 0x0, End_B0=29 End_B1=29
8283 09:25:32.748253 30, 0x0, End_B0=30 End_B1=30
8284 09:25:32.751630 31, 0x5151, End_B0=30 End_B1=30
8285 09:25:32.755068 Byte0 end_step=30 best_step=27
8286 09:25:32.758499 Byte1 end_step=30 best_step=27
8287 09:25:32.758575 Byte0 TX OE(2T, 0.5T) = (3, 3)
8288 09:25:32.761416 Byte1 TX OE(2T, 0.5T) = (3, 3)
8289 09:25:32.761484
8290 09:25:32.761542
8291 09:25:32.771285 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e02, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8292 09:25:32.774948 CH0 RK1: MR19=303, MR18=1E02
8293 09:25:32.781641 CH0_RK1: MR19=0x303, MR18=0x1E02, DQSOSC=394, MR23=63, INC=23, DEC=15
8294 09:25:32.781753 [RxdqsGatingPostProcess] freq 1600
8295 09:25:32.787843 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8296 09:25:32.791420 best DQS0 dly(2T, 0.5T) = (1, 1)
8297 09:25:32.794494 best DQS1 dly(2T, 0.5T) = (1, 1)
8298 09:25:32.798226 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8299 09:25:32.801436 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8300 09:25:32.804459 best DQS0 dly(2T, 0.5T) = (1, 1)
8301 09:25:32.808073 best DQS1 dly(2T, 0.5T) = (1, 1)
8302 09:25:32.811235 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8303 09:25:32.814135 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8304 09:25:32.814251 Pre-setting of DQS Precalculation
8305 09:25:32.821125 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8306 09:25:32.821206 ==
8307 09:25:32.824260 Dram Type= 6, Freq= 0, CH_1, rank 0
8308 09:25:32.827436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 09:25:32.827518 ==
8310 09:25:32.834099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8311 09:25:32.837100 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8312 09:25:32.843903 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8313 09:25:32.847078 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8314 09:25:32.857129 [CA 0] Center 41 (12~71) winsize 60
8315 09:25:32.860636 [CA 1] Center 42 (12~72) winsize 61
8316 09:25:32.863647 [CA 2] Center 37 (8~66) winsize 59
8317 09:25:32.867269 [CA 3] Center 35 (6~65) winsize 60
8318 09:25:32.870444 [CA 4] Center 37 (8~66) winsize 59
8319 09:25:32.874132 [CA 5] Center 36 (7~66) winsize 60
8320 09:25:32.874249
8321 09:25:32.877177 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8322 09:25:32.877331
8323 09:25:32.880378 [CATrainingPosCal] consider 1 rank data
8324 09:25:32.883925 u2DelayCellTimex100 = 262/100 ps
8325 09:25:32.890092 CA0 delay=41 (12~71),Diff = 6 PI (22 cell)
8326 09:25:32.893726 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8327 09:25:32.896988 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8328 09:25:32.900494 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8329 09:25:32.903585 CA4 delay=37 (8~66),Diff = 2 PI (7 cell)
8330 09:25:32.906731 CA5 delay=36 (7~66),Diff = 1 PI (3 cell)
8331 09:25:32.906854
8332 09:25:32.909819 CA PerBit enable=1, Macro0, CA PI delay=35
8333 09:25:32.909928
8334 09:25:32.913620 [CBTSetCACLKResult] CA Dly = 35
8335 09:25:32.916924 CS Dly: 10 (0~41)
8336 09:25:32.919910 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8337 09:25:32.923006 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8338 09:25:32.923117 ==
8339 09:25:32.926713 Dram Type= 6, Freq= 0, CH_1, rank 1
8340 09:25:32.932754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 09:25:32.932861 ==
8342 09:25:32.936273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8343 09:25:32.942808 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8344 09:25:32.945884 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8345 09:25:32.952617 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8346 09:25:32.960968 [CA 0] Center 42 (12~72) winsize 61
8347 09:25:32.963782 [CA 1] Center 42 (13~72) winsize 60
8348 09:25:32.966817 [CA 2] Center 37 (8~67) winsize 60
8349 09:25:32.970401 [CA 3] Center 37 (8~66) winsize 59
8350 09:25:32.973839 [CA 4] Center 37 (8~67) winsize 60
8351 09:25:32.976935 [CA 5] Center 37 (7~67) winsize 61
8352 09:25:32.977017
8353 09:25:32.980075 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8354 09:25:32.980154
8355 09:25:32.986979 [CATrainingPosCal] consider 2 rank data
8356 09:25:32.987061 u2DelayCellTimex100 = 262/100 ps
8357 09:25:32.993188 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8358 09:25:32.996817 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8359 09:25:32.999955 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8360 09:25:33.003338 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8361 09:25:33.006520 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8362 09:25:33.009492 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8363 09:25:33.009573
8364 09:25:33.013189 CA PerBit enable=1, Macro0, CA PI delay=36
8365 09:25:33.013270
8366 09:25:33.016368 [CBTSetCACLKResult] CA Dly = 36
8367 09:25:33.019485 CS Dly: 11 (0~43)
8368 09:25:33.022654 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8369 09:25:33.026364 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8370 09:25:33.026444
8371 09:25:33.029415 ----->DramcWriteLeveling(PI) begin...
8372 09:25:33.029496 ==
8373 09:25:33.033183 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 09:25:33.039231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 09:25:33.039314 ==
8376 09:25:33.042440 Write leveling (Byte 0): 24 => 24
8377 09:25:33.046297 Write leveling (Byte 1): 27 => 27
8378 09:25:33.049199 DramcWriteLeveling(PI) end<-----
8379 09:25:33.049280
8380 09:25:33.049344 ==
8381 09:25:33.052271 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 09:25:33.055840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 09:25:33.055922 ==
8384 09:25:33.058862 [Gating] SW mode calibration
8385 09:25:33.065970 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8386 09:25:33.072185 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8387 09:25:33.075808 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 09:25:33.078622 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 09:25:33.085313 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8390 09:25:33.088888 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
8391 09:25:33.091800 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 09:25:33.098478 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 09:25:33.102253 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 09:25:33.105241 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 09:25:33.111721 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 09:25:33.114857 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 09:25:33.118581 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8398 09:25:33.124812 1 5 12 | B1->B0 | 3333 2828 | 1 0 | (1 0) (0 1)
8399 09:25:33.128416 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 09:25:33.131575 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 09:25:33.138275 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 09:25:33.141394 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 09:25:33.144516 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 09:25:33.151389 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 09:25:33.155048 1 6 8 | B1->B0 | 2323 2525 | 1 0 | (0 0) (0 0)
8406 09:25:33.158083 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8407 09:25:33.164831 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 09:25:33.167862 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 09:25:33.171538 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 09:25:33.174606 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 09:25:33.181356 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 09:25:33.184314 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 09:25:33.188021 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8414 09:25:33.194697 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8415 09:25:33.197703 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8416 09:25:33.201256 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 09:25:33.207642 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 09:25:33.210930 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 09:25:33.214358 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 09:25:33.221128 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 09:25:33.224140 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 09:25:33.227893 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 09:25:33.233993 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 09:25:33.237633 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 09:25:33.240634 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 09:25:33.247601 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 09:25:33.250804 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 09:25:33.253894 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 09:25:33.260752 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8430 09:25:33.263604 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8431 09:25:33.267230 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8432 09:25:33.270366 Total UI for P1: 0, mck2ui 16
8433 09:25:33.273477 best dqsien dly found for B0: ( 1, 9, 10)
8434 09:25:33.280151 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 09:25:33.283400 Total UI for P1: 0, mck2ui 16
8436 09:25:33.286920 best dqsien dly found for B1: ( 1, 9, 12)
8437 09:25:33.289982 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8438 09:25:33.293037 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8439 09:25:33.293112
8440 09:25:33.296533 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8441 09:25:33.300130 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8442 09:25:33.303524 [Gating] SW calibration Done
8443 09:25:33.303602 ==
8444 09:25:33.306323 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 09:25:33.309785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 09:25:33.309861 ==
8447 09:25:33.312870 RX Vref Scan: 0
8448 09:25:33.312949
8449 09:25:33.316530 RX Vref 0 -> 0, step: 1
8450 09:25:33.316604
8451 09:25:33.316683 RX Delay 0 -> 252, step: 8
8452 09:25:33.323068 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8453 09:25:33.326344 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8454 09:25:33.329728 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8455 09:25:33.333091 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8456 09:25:33.336346 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8457 09:25:33.342654 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8458 09:25:33.346090 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8459 09:25:33.349364 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8460 09:25:33.353059 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8461 09:25:33.356096 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8462 09:25:33.362297 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8463 09:25:33.365907 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8464 09:25:33.368936 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8465 09:25:33.372702 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8466 09:25:33.379009 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8467 09:25:33.382710 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8468 09:25:33.382790 ==
8469 09:25:33.385796 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 09:25:33.388877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 09:25:33.388953 ==
8472 09:25:33.392424 DQS Delay:
8473 09:25:33.392497 DQS0 = 0, DQS1 = 0
8474 09:25:33.392574 DQM Delay:
8475 09:25:33.395436 DQM0 = 136, DQM1 = 129
8476 09:25:33.395512 DQ Delay:
8477 09:25:33.399153 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =131
8478 09:25:33.402053 DQ4 =135, DQ5 =151, DQ6 =143, DQ7 =135
8479 09:25:33.409071 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
8480 09:25:33.412223 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8481 09:25:33.412304
8482 09:25:33.412385
8483 09:25:33.412460 ==
8484 09:25:33.415836 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 09:25:33.418661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 09:25:33.418742 ==
8487 09:25:33.418823
8488 09:25:33.418901
8489 09:25:33.422110 TX Vref Scan disable
8490 09:25:33.422239 == TX Byte 0 ==
8491 09:25:33.428417 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8492 09:25:33.431816 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8493 09:25:33.435486 == TX Byte 1 ==
8494 09:25:33.438986 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8495 09:25:33.441806 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8496 09:25:33.441890 ==
8497 09:25:33.445106 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 09:25:33.448467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 09:25:33.452017 ==
8500 09:25:33.462843
8501 09:25:33.465954 TX Vref early break, caculate TX vref
8502 09:25:33.469043 TX Vref=16, minBit 0, minWin=22, winSum=378
8503 09:25:33.472659 TX Vref=18, minBit 0, minWin=23, winSum=389
8504 09:25:33.475777 TX Vref=20, minBit 0, minWin=24, winSum=398
8505 09:25:33.478970 TX Vref=22, minBit 0, minWin=24, winSum=407
8506 09:25:33.482503 TX Vref=24, minBit 0, minWin=25, winSum=420
8507 09:25:33.488855 TX Vref=26, minBit 0, minWin=25, winSum=424
8508 09:25:33.492521 TX Vref=28, minBit 0, minWin=24, winSum=419
8509 09:25:33.495558 TX Vref=30, minBit 5, minWin=25, winSum=415
8510 09:25:33.499153 TX Vref=32, minBit 5, minWin=23, winSum=402
8511 09:25:33.502241 TX Vref=34, minBit 5, minWin=23, winSum=396
8512 09:25:33.508521 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
8513 09:25:33.508602
8514 09:25:33.511970 Final TX Range 0 Vref 26
8515 09:25:33.512046
8516 09:25:33.512130 ==
8517 09:25:33.515486 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 09:25:33.518594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 09:25:33.518676 ==
8520 09:25:33.518761
8521 09:25:33.518838
8522 09:25:33.522106 TX Vref Scan disable
8523 09:25:33.528471 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8524 09:25:33.528555 == TX Byte 0 ==
8525 09:25:33.531995 u2DelayCellOfst[0]=18 cells (5 PI)
8526 09:25:33.534922 u2DelayCellOfst[1]=11 cells (3 PI)
8527 09:25:33.538320 u2DelayCellOfst[2]=0 cells (0 PI)
8528 09:25:33.541813 u2DelayCellOfst[3]=3 cells (1 PI)
8529 09:25:33.544897 u2DelayCellOfst[4]=7 cells (2 PI)
8530 09:25:33.548018 u2DelayCellOfst[5]=22 cells (6 PI)
8531 09:25:33.551320 u2DelayCellOfst[6]=18 cells (5 PI)
8532 09:25:33.554907 u2DelayCellOfst[7]=3 cells (1 PI)
8533 09:25:33.558272 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8534 09:25:33.561411 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8535 09:25:33.564903 == TX Byte 1 ==
8536 09:25:33.568014 u2DelayCellOfst[8]=0 cells (0 PI)
8537 09:25:33.571095 u2DelayCellOfst[9]=3 cells (1 PI)
8538 09:25:33.571202 u2DelayCellOfst[10]=11 cells (3 PI)
8539 09:25:33.574675 u2DelayCellOfst[11]=7 cells (2 PI)
8540 09:25:33.577724 u2DelayCellOfst[12]=14 cells (4 PI)
8541 09:25:33.581424 u2DelayCellOfst[13]=18 cells (5 PI)
8542 09:25:33.584553 u2DelayCellOfst[14]=18 cells (5 PI)
8543 09:25:33.587626 u2DelayCellOfst[15]=18 cells (5 PI)
8544 09:25:33.594425 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8545 09:25:33.597546 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8546 09:25:33.597619 DramC Write-DBI on
8547 09:25:33.597700 ==
8548 09:25:33.601072 Dram Type= 6, Freq= 0, CH_1, rank 0
8549 09:25:33.607377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8550 09:25:33.607457 ==
8551 09:25:33.607538
8552 09:25:33.607617
8553 09:25:33.610962 TX Vref Scan disable
8554 09:25:33.611036 == TX Byte 0 ==
8555 09:25:33.617458 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8556 09:25:33.617560 == TX Byte 1 ==
8557 09:25:33.620953 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8558 09:25:33.624014 DramC Write-DBI off
8559 09:25:33.624093
8560 09:25:33.624170 [DATLAT]
8561 09:25:33.627108 Freq=1600, CH1 RK0
8562 09:25:33.627184
8563 09:25:33.627270 DATLAT Default: 0xf
8564 09:25:33.630685 0, 0xFFFF, sum = 0
8565 09:25:33.630765 1, 0xFFFF, sum = 0
8566 09:25:33.634153 2, 0xFFFF, sum = 0
8567 09:25:33.634270 3, 0xFFFF, sum = 0
8568 09:25:33.637108 4, 0xFFFF, sum = 0
8569 09:25:33.637189 5, 0xFFFF, sum = 0
8570 09:25:33.640801 6, 0xFFFF, sum = 0
8571 09:25:33.640876 7, 0xFFFF, sum = 0
8572 09:25:33.643588 8, 0xFFFF, sum = 0
8573 09:25:33.643667 9, 0xFFFF, sum = 0
8574 09:25:33.647221 10, 0xFFFF, sum = 0
8575 09:25:33.650306 11, 0xFFFF, sum = 0
8576 09:25:33.650395 12, 0xFFFF, sum = 0
8577 09:25:33.654063 13, 0xFFFF, sum = 0
8578 09:25:33.654136 14, 0x0, sum = 1
8579 09:25:33.656846 15, 0x0, sum = 2
8580 09:25:33.656918 16, 0x0, sum = 3
8581 09:25:33.660535 17, 0x0, sum = 4
8582 09:25:33.660613 best_step = 15
8583 09:25:33.660693
8584 09:25:33.660767 ==
8585 09:25:33.663531 Dram Type= 6, Freq= 0, CH_1, rank 0
8586 09:25:33.667080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8587 09:25:33.667150 ==
8588 09:25:33.670125 RX Vref Scan: 1
8589 09:25:33.670240
8590 09:25:33.673524 Set Vref Range= 24 -> 127
8591 09:25:33.673599
8592 09:25:33.673678 RX Vref 24 -> 127, step: 1
8593 09:25:33.677011
8594 09:25:33.677083 RX Delay 11 -> 252, step: 4
8595 09:25:33.677163
8596 09:25:33.680073 Set Vref, RX VrefLevel [Byte0]: 24
8597 09:25:33.683191 [Byte1]: 24
8598 09:25:33.686976
8599 09:25:33.687057 Set Vref, RX VrefLevel [Byte0]: 25
8600 09:25:33.690046 [Byte1]: 25
8601 09:25:33.694328
8602 09:25:33.694404 Set Vref, RX VrefLevel [Byte0]: 26
8603 09:25:33.698076 [Byte1]: 26
8604 09:25:33.702324
8605 09:25:33.702396 Set Vref, RX VrefLevel [Byte0]: 27
8606 09:25:33.705292 [Byte1]: 27
8607 09:25:33.709994
8608 09:25:33.710069 Set Vref, RX VrefLevel [Byte0]: 28
8609 09:25:33.713076 [Byte1]: 28
8610 09:25:33.717496
8611 09:25:33.717594 Set Vref, RX VrefLevel [Byte0]: 29
8612 09:25:33.720572 [Byte1]: 29
8613 09:25:33.725259
8614 09:25:33.725333 Set Vref, RX VrefLevel [Byte0]: 30
8615 09:25:33.728225 [Byte1]: 30
8616 09:25:33.732908
8617 09:25:33.732986 Set Vref, RX VrefLevel [Byte0]: 31
8618 09:25:33.736030 [Byte1]: 31
8619 09:25:33.740228
8620 09:25:33.740306 Set Vref, RX VrefLevel [Byte0]: 32
8621 09:25:33.743658 [Byte1]: 32
8622 09:25:33.748028
8623 09:25:33.748109 Set Vref, RX VrefLevel [Byte0]: 33
8624 09:25:33.751147 [Byte1]: 33
8625 09:25:33.755450
8626 09:25:33.755544 Set Vref, RX VrefLevel [Byte0]: 34
8627 09:25:33.759190 [Byte1]: 34
8628 09:25:33.763123
8629 09:25:33.763199 Set Vref, RX VrefLevel [Byte0]: 35
8630 09:25:33.766729 [Byte1]: 35
8631 09:25:33.771019
8632 09:25:33.771144 Set Vref, RX VrefLevel [Byte0]: 36
8633 09:25:33.774022 [Byte1]: 36
8634 09:25:33.778103
8635 09:25:33.778212 Set Vref, RX VrefLevel [Byte0]: 37
8636 09:25:33.781536 [Byte1]: 37
8637 09:25:33.786103
8638 09:25:33.786221 Set Vref, RX VrefLevel [Byte0]: 38
8639 09:25:33.789312 [Byte1]: 38
8640 09:25:33.793596
8641 09:25:33.793716 Set Vref, RX VrefLevel [Byte0]: 39
8642 09:25:33.796557 [Byte1]: 39
8643 09:25:33.800888
8644 09:25:33.800958 Set Vref, RX VrefLevel [Byte0]: 40
8645 09:25:33.804588 [Byte1]: 40
8646 09:25:33.809066
8647 09:25:33.809135 Set Vref, RX VrefLevel [Byte0]: 41
8648 09:25:33.811980 [Byte1]: 41
8649 09:25:33.816732
8650 09:25:33.816808 Set Vref, RX VrefLevel [Byte0]: 42
8651 09:25:33.819908 [Byte1]: 42
8652 09:25:33.824131
8653 09:25:33.824213 Set Vref, RX VrefLevel [Byte0]: 43
8654 09:25:33.827243 [Byte1]: 43
8655 09:25:33.831405
8656 09:25:33.831518 Set Vref, RX VrefLevel [Byte0]: 44
8657 09:25:33.835104 [Byte1]: 44
8658 09:25:33.839350
8659 09:25:33.839433 Set Vref, RX VrefLevel [Byte0]: 45
8660 09:25:33.842323 [Byte1]: 45
8661 09:25:33.847008
8662 09:25:33.847080 Set Vref, RX VrefLevel [Byte0]: 46
8663 09:25:33.849828 [Byte1]: 46
8664 09:25:33.854358
8665 09:25:33.854462 Set Vref, RX VrefLevel [Byte0]: 47
8666 09:25:33.857931 [Byte1]: 47
8667 09:25:33.862207
8668 09:25:33.862297 Set Vref, RX VrefLevel [Byte0]: 48
8669 09:25:33.865263 [Byte1]: 48
8670 09:25:33.869497
8671 09:25:33.869596 Set Vref, RX VrefLevel [Byte0]: 49
8672 09:25:33.872969 [Byte1]: 49
8673 09:25:33.877011
8674 09:25:33.877114 Set Vref, RX VrefLevel [Byte0]: 50
8675 09:25:33.880706 [Byte1]: 50
8676 09:25:33.885015
8677 09:25:33.885087 Set Vref, RX VrefLevel [Byte0]: 51
8678 09:25:33.887976 [Byte1]: 51
8679 09:25:33.892781
8680 09:25:33.892887 Set Vref, RX VrefLevel [Byte0]: 52
8681 09:25:33.895727 [Byte1]: 52
8682 09:25:33.900258
8683 09:25:33.900328 Set Vref, RX VrefLevel [Byte0]: 53
8684 09:25:33.903401 [Byte1]: 53
8685 09:25:33.907793
8686 09:25:33.907861 Set Vref, RX VrefLevel [Byte0]: 54
8687 09:25:33.910969 [Byte1]: 54
8688 09:25:33.915781
8689 09:25:33.915854 Set Vref, RX VrefLevel [Byte0]: 55
8690 09:25:33.918632 [Byte1]: 55
8691 09:25:33.922952
8692 09:25:33.923034 Set Vref, RX VrefLevel [Byte0]: 56
8693 09:25:33.926010 [Byte1]: 56
8694 09:25:33.930420
8695 09:25:33.930492 Set Vref, RX VrefLevel [Byte0]: 57
8696 09:25:33.934086 [Byte1]: 57
8697 09:25:33.938441
8698 09:25:33.938525 Set Vref, RX VrefLevel [Byte0]: 58
8699 09:25:33.941374 [Byte1]: 58
8700 09:25:33.945714
8701 09:25:33.945797 Set Vref, RX VrefLevel [Byte0]: 59
8702 09:25:33.948893 [Byte1]: 59
8703 09:25:33.953598
8704 09:25:33.953695 Set Vref, RX VrefLevel [Byte0]: 60
8705 09:25:33.956404 [Byte1]: 60
8706 09:25:33.960886
8707 09:25:33.960961 Set Vref, RX VrefLevel [Byte0]: 61
8708 09:25:33.964322 [Byte1]: 61
8709 09:25:33.968433
8710 09:25:33.968510 Set Vref, RX VrefLevel [Byte0]: 62
8711 09:25:33.972187 [Byte1]: 62
8712 09:25:33.976626
8713 09:25:33.976733 Set Vref, RX VrefLevel [Byte0]: 63
8714 09:25:33.979267 [Byte1]: 63
8715 09:25:33.984070
8716 09:25:33.984141 Set Vref, RX VrefLevel [Byte0]: 64
8717 09:25:33.986953 [Byte1]: 64
8718 09:25:33.991284
8719 09:25:33.991365 Set Vref, RX VrefLevel [Byte0]: 65
8720 09:25:33.994571 [Byte1]: 65
8721 09:25:33.998817
8722 09:25:33.998891 Set Vref, RX VrefLevel [Byte0]: 66
8723 09:25:34.002442 [Byte1]: 66
8724 09:25:34.006688
8725 09:25:34.006771 Set Vref, RX VrefLevel [Byte0]: 67
8726 09:25:34.009812 [Byte1]: 67
8727 09:25:34.014098
8728 09:25:34.014216 Set Vref, RX VrefLevel [Byte0]: 68
8729 09:25:34.017841 [Byte1]: 68
8730 09:25:34.021959
8731 09:25:34.022069 Set Vref, RX VrefLevel [Byte0]: 69
8732 09:25:34.025093 [Byte1]: 69
8733 09:25:34.029289
8734 09:25:34.029364 Set Vref, RX VrefLevel [Byte0]: 70
8735 09:25:34.033028 [Byte1]: 70
8736 09:25:34.037351
8737 09:25:34.037440 Set Vref, RX VrefLevel [Byte0]: 71
8738 09:25:34.040302 [Byte1]: 71
8739 09:25:34.045054
8740 09:25:34.045162 Set Vref, RX VrefLevel [Byte0]: 72
8741 09:25:34.048032 [Byte1]: 72
8742 09:25:34.052350
8743 09:25:34.052425 Set Vref, RX VrefLevel [Byte0]: 73
8744 09:25:34.055616 [Byte1]: 73
8745 09:25:34.059870
8746 09:25:34.059944 Final RX Vref Byte 0 = 53 to rank0
8747 09:25:34.063465 Final RX Vref Byte 1 = 61 to rank0
8748 09:25:34.066279 Final RX Vref Byte 0 = 53 to rank1
8749 09:25:34.069556 Final RX Vref Byte 1 = 61 to rank1==
8750 09:25:34.072911 Dram Type= 6, Freq= 0, CH_1, rank 0
8751 09:25:34.079607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8752 09:25:34.079690 ==
8753 09:25:34.079764 DQS Delay:
8754 09:25:34.082848 DQS0 = 0, DQS1 = 0
8755 09:25:34.082921 DQM Delay:
8756 09:25:34.082982 DQM0 = 133, DQM1 = 127
8757 09:25:34.086412 DQ Delay:
8758 09:25:34.089421 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8759 09:25:34.093059 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8760 09:25:34.096412 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8761 09:25:34.099196 DQ12 =136, DQ13 =134, DQ14 =136, DQ15 =136
8762 09:25:34.099291
8763 09:25:34.099356
8764 09:25:34.099418
8765 09:25:34.102448 [DramC_TX_OE_Calibration] TA2
8766 09:25:34.105911 Original DQ_B0 (3 6) =30, OEN = 27
8767 09:25:34.109043 Original DQ_B1 (3 6) =30, OEN = 27
8768 09:25:34.112923 24, 0x0, End_B0=24 End_B1=24
8769 09:25:34.115958 25, 0x0, End_B0=25 End_B1=25
8770 09:25:34.116034 26, 0x0, End_B0=26 End_B1=26
8771 09:25:34.119655 27, 0x0, End_B0=27 End_B1=27
8772 09:25:34.122653 28, 0x0, End_B0=28 End_B1=28
8773 09:25:34.125779 29, 0x0, End_B0=29 End_B1=29
8774 09:25:34.125880 30, 0x0, End_B0=30 End_B1=30
8775 09:25:34.129100 31, 0x4141, End_B0=30 End_B1=30
8776 09:25:34.132215 Byte0 end_step=30 best_step=27
8777 09:25:34.135953 Byte1 end_step=30 best_step=27
8778 09:25:34.139176 Byte0 TX OE(2T, 0.5T) = (3, 3)
8779 09:25:34.142099 Byte1 TX OE(2T, 0.5T) = (3, 3)
8780 09:25:34.142192
8781 09:25:34.142269
8782 09:25:34.148914 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c11, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
8783 09:25:34.152372 CH1 RK0: MR19=303, MR18=1C11
8784 09:25:34.158728 CH1_RK0: MR19=0x303, MR18=0x1C11, DQSOSC=395, MR23=63, INC=23, DEC=15
8785 09:25:34.158804
8786 09:25:34.162403 ----->DramcWriteLeveling(PI) begin...
8787 09:25:34.162475 ==
8788 09:25:34.165502 Dram Type= 6, Freq= 0, CH_1, rank 1
8789 09:25:34.168562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8790 09:25:34.168639 ==
8791 09:25:34.172125 Write leveling (Byte 0): 24 => 24
8792 09:25:34.175157 Write leveling (Byte 1): 27 => 27
8793 09:25:34.178808 DramcWriteLeveling(PI) end<-----
8794 09:25:34.178884
8795 09:25:34.178958 ==
8796 09:25:34.182087 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 09:25:34.188545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 09:25:34.188624 ==
8799 09:25:34.188686 [Gating] SW mode calibration
8800 09:25:34.197975 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8801 09:25:34.201693 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8802 09:25:34.208254 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 09:25:34.211793 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 09:25:34.214576 1 4 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8805 09:25:34.221370 1 4 12 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8806 09:25:34.224441 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 09:25:34.228117 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 09:25:34.234742 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 09:25:34.237819 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 09:25:34.240849 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 09:25:34.247490 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 09:25:34.251117 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8813 09:25:34.254081 1 5 12 | B1->B0 | 2828 3434 | 1 1 | (1 0) (1 0)
8814 09:25:34.260770 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8815 09:25:34.263924 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 09:25:34.267710 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 09:25:34.270742 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 09:25:34.277399 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 09:25:34.280619 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 09:25:34.284539 1 6 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8821 09:25:34.291035 1 6 12 | B1->B0 | 4646 2929 | 0 0 | (0 0) (1 1)
8822 09:25:34.294405 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 09:25:34.297947 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 09:25:34.304142 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 09:25:34.307564 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 09:25:34.310885 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 09:25:34.317277 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 09:25:34.320714 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8829 09:25:34.323864 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8830 09:25:34.330389 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 09:25:34.334118 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 09:25:34.337127 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 09:25:34.343812 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 09:25:34.347512 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 09:25:34.350540 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 09:25:34.356635 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 09:25:34.360233 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 09:25:34.363300 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 09:25:34.370064 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 09:25:34.373755 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 09:25:34.376893 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 09:25:34.383398 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 09:25:34.386603 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 09:25:34.390274 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8845 09:25:34.396358 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8846 09:25:34.399918 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8847 09:25:34.403274 Total UI for P1: 0, mck2ui 16
8848 09:25:34.406549 best dqsien dly found for B1: ( 1, 9, 10)
8849 09:25:34.409947 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 09:25:34.413228 Total UI for P1: 0, mck2ui 16
8851 09:25:34.416227 best dqsien dly found for B0: ( 1, 9, 12)
8852 09:25:34.419899 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8853 09:25:34.422853 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8854 09:25:34.426361
8855 09:25:34.429766 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8856 09:25:34.432838 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8857 09:25:34.436161 [Gating] SW calibration Done
8858 09:25:34.436548 ==
8859 09:25:34.439802 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 09:25:34.442946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 09:25:34.443458 ==
8862 09:25:34.446288 RX Vref Scan: 0
8863 09:25:34.446705
8864 09:25:34.447035 RX Vref 0 -> 0, step: 1
8865 09:25:34.447362
8866 09:25:34.449492 RX Delay 0 -> 252, step: 8
8867 09:25:34.452913 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8868 09:25:34.456076 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8869 09:25:34.462773 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8870 09:25:34.465842 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8871 09:25:34.469476 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8872 09:25:34.472524 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8873 09:25:34.475608 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8874 09:25:34.482549 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8875 09:25:34.486056 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8876 09:25:34.489122 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8877 09:25:34.492195 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8878 09:25:34.499089 iDelay=208, Bit 11, Center 119 (56 ~ 183) 128
8879 09:25:34.502222 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8880 09:25:34.505759 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8881 09:25:34.508686 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8882 09:25:34.511962 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8883 09:25:34.515638 ==
8884 09:25:34.516069 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 09:25:34.522215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 09:25:34.522724 ==
8887 09:25:34.523198 DQS Delay:
8888 09:25:34.525255 DQS0 = 0, DQS1 = 0
8889 09:25:34.525720 DQM Delay:
8890 09:25:34.528934 DQM0 = 136, DQM1 = 129
8891 09:25:34.529343 DQ Delay:
8892 09:25:34.532029 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8893 09:25:34.535447 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8894 09:25:34.538400 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8895 09:25:34.542214 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8896 09:25:34.542635
8897 09:25:34.542953
8898 09:25:34.543264 ==
8899 09:25:34.544976 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 09:25:34.551554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 09:25:34.551997 ==
8902 09:25:34.552325
8903 09:25:34.552626
8904 09:25:34.555105 TX Vref Scan disable
8905 09:25:34.555580 == TX Byte 0 ==
8906 09:25:34.558019 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8907 09:25:34.564610 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8908 09:25:34.565023 == TX Byte 1 ==
8909 09:25:34.568013 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8910 09:25:34.574713 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8911 09:25:34.575131 ==
8912 09:25:34.577906 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 09:25:34.580974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 09:25:34.581463 ==
8915 09:25:34.595674
8916 09:25:34.598798 TX Vref early break, caculate TX vref
8917 09:25:34.601874 TX Vref=16, minBit 0, minWin=23, winSum=386
8918 09:25:34.605522 TX Vref=18, minBit 0, minWin=24, winSum=397
8919 09:25:34.608694 TX Vref=20, minBit 6, minWin=24, winSum=404
8920 09:25:34.611731 TX Vref=22, minBit 0, minWin=25, winSum=409
8921 09:25:34.615333 TX Vref=24, minBit 0, minWin=25, winSum=415
8922 09:25:34.621977 TX Vref=26, minBit 5, minWin=25, winSum=422
8923 09:25:34.624792 TX Vref=28, minBit 0, minWin=25, winSum=422
8924 09:25:34.628403 TX Vref=30, minBit 1, minWin=25, winSum=417
8925 09:25:34.631556 TX Vref=32, minBit 0, minWin=24, winSum=409
8926 09:25:34.634598 TX Vref=34, minBit 0, minWin=23, winSum=400
8927 09:25:34.641253 TX Vref=36, minBit 1, minWin=23, winSum=389
8928 09:25:34.644807 [TxChooseVref] Worse bit 5, Min win 25, Win sum 422, Final Vref 26
8929 09:25:34.645387
8930 09:25:34.647943 Final TX Range 0 Vref 26
8931 09:25:34.648531
8932 09:25:34.649083 ==
8933 09:25:34.651497 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 09:25:34.654261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 09:25:34.657862 ==
8936 09:25:34.658332
8937 09:25:34.658770
8938 09:25:34.659177 TX Vref Scan disable
8939 09:25:34.664488 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8940 09:25:34.664919 == TX Byte 0 ==
8941 09:25:34.667873 u2DelayCellOfst[0]=18 cells (5 PI)
8942 09:25:34.671316 u2DelayCellOfst[1]=11 cells (3 PI)
8943 09:25:34.674413 u2DelayCellOfst[2]=0 cells (0 PI)
8944 09:25:34.677882 u2DelayCellOfst[3]=3 cells (1 PI)
8945 09:25:34.681641 u2DelayCellOfst[4]=11 cells (3 PI)
8946 09:25:34.684745 u2DelayCellOfst[5]=22 cells (6 PI)
8947 09:25:34.687860 u2DelayCellOfst[6]=18 cells (5 PI)
8948 09:25:34.690998 u2DelayCellOfst[7]=3 cells (1 PI)
8949 09:25:34.694576 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8950 09:25:34.697707 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8951 09:25:34.700839 == TX Byte 1 ==
8952 09:25:34.704381 u2DelayCellOfst[8]=0 cells (0 PI)
8953 09:25:34.707424 u2DelayCellOfst[9]=3 cells (1 PI)
8954 09:25:34.711183 u2DelayCellOfst[10]=11 cells (3 PI)
8955 09:25:34.714344 u2DelayCellOfst[11]=7 cells (2 PI)
8956 09:25:34.717528 u2DelayCellOfst[12]=14 cells (4 PI)
8957 09:25:34.720576 u2DelayCellOfst[13]=18 cells (5 PI)
8958 09:25:34.724456 u2DelayCellOfst[14]=18 cells (5 PI)
8959 09:25:34.724971 u2DelayCellOfst[15]=18 cells (5 PI)
8960 09:25:34.730784 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8961 09:25:34.733511 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8962 09:25:34.737021 DramC Write-DBI on
8963 09:25:34.737435 ==
8964 09:25:34.740734 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 09:25:34.743959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 09:25:34.744374 ==
8967 09:25:34.744697
8968 09:25:34.744996
8969 09:25:34.746823 TX Vref Scan disable
8970 09:25:34.747234 == TX Byte 0 ==
8971 09:25:34.753441 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8972 09:25:34.753860 == TX Byte 1 ==
8973 09:25:34.757216 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8974 09:25:34.760134 DramC Write-DBI off
8975 09:25:34.760715
8976 09:25:34.761071 [DATLAT]
8977 09:25:34.763507 Freq=1600, CH1 RK1
8978 09:25:34.763920
8979 09:25:34.764246 DATLAT Default: 0xf
8980 09:25:34.767065 0, 0xFFFF, sum = 0
8981 09:25:34.767488 1, 0xFFFF, sum = 0
8982 09:25:34.770272 2, 0xFFFF, sum = 0
8983 09:25:34.773220 3, 0xFFFF, sum = 0
8984 09:25:34.773917 4, 0xFFFF, sum = 0
8985 09:25:34.776911 5, 0xFFFF, sum = 0
8986 09:25:34.777440 6, 0xFFFF, sum = 0
8987 09:25:34.780360 7, 0xFFFF, sum = 0
8988 09:25:34.780922 8, 0xFFFF, sum = 0
8989 09:25:34.783097 9, 0xFFFF, sum = 0
8990 09:25:34.783535 10, 0xFFFF, sum = 0
8991 09:25:34.786696 11, 0xFFFF, sum = 0
8992 09:25:34.787118 12, 0xFFFF, sum = 0
8993 09:25:34.790222 13, 0xFFFF, sum = 0
8994 09:25:34.790641 14, 0x0, sum = 1
8995 09:25:34.793334 15, 0x0, sum = 2
8996 09:25:34.793755 16, 0x0, sum = 3
8997 09:25:34.796401 17, 0x0, sum = 4
8998 09:25:34.796823 best_step = 15
8999 09:25:34.797151
9000 09:25:34.797456 ==
9001 09:25:34.799936 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 09:25:34.806797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 09:25:34.807223 ==
9004 09:25:34.807582 RX Vref Scan: 0
9005 09:25:34.807892
9006 09:25:34.809755 RX Vref 0 -> 0, step: 1
9007 09:25:34.810203
9008 09:25:34.812869 RX Delay 11 -> 252, step: 4
9009 09:25:34.816603 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9010 09:25:34.819704 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9011 09:25:34.822848 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9012 09:25:34.829802 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9013 09:25:34.832862 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9014 09:25:34.836434 iDelay=203, Bit 5, Center 146 (95 ~ 198) 104
9015 09:25:34.839211 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9016 09:25:34.845590 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9017 09:25:34.848957 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9018 09:25:34.852870 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9019 09:25:34.855865 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9020 09:25:34.859529 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9021 09:25:34.865491 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9022 09:25:34.869033 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9023 09:25:34.872466 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9024 09:25:34.875789 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9025 09:25:34.876248 ==
9026 09:25:34.878913 Dram Type= 6, Freq= 0, CH_1, rank 1
9027 09:25:34.885440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9028 09:25:34.885859 ==
9029 09:25:34.886227 DQS Delay:
9030 09:25:34.888544 DQS0 = 0, DQS1 = 0
9031 09:25:34.888957 DQM Delay:
9032 09:25:34.891970 DQM0 = 134, DQM1 = 126
9033 09:25:34.892408 DQ Delay:
9034 09:25:34.895069 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9035 09:25:34.898638 DQ4 =132, DQ5 =146, DQ6 =146, DQ7 =130
9036 09:25:34.901563 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9037 09:25:34.905139 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9038 09:25:34.905675
9039 09:25:34.906047
9040 09:25:34.906485
9041 09:25:34.908205 [DramC_TX_OE_Calibration] TA2
9042 09:25:34.911796 Original DQ_B0 (3 6) =30, OEN = 27
9043 09:25:34.914970 Original DQ_B1 (3 6) =30, OEN = 27
9044 09:25:34.918667 24, 0x0, End_B0=24 End_B1=24
9045 09:25:34.921882 25, 0x0, End_B0=25 End_B1=25
9046 09:25:34.922357 26, 0x0, End_B0=26 End_B1=26
9047 09:25:34.924915 27, 0x0, End_B0=27 End_B1=27
9048 09:25:34.928615 28, 0x0, End_B0=28 End_B1=28
9049 09:25:34.931850 29, 0x0, End_B0=29 End_B1=29
9050 09:25:34.932432 30, 0x0, End_B0=30 End_B1=30
9051 09:25:34.934896 31, 0x4545, End_B0=30 End_B1=30
9052 09:25:34.938124 Byte0 end_step=30 best_step=27
9053 09:25:34.941952 Byte1 end_step=30 best_step=27
9054 09:25:34.944914 Byte0 TX OE(2T, 0.5T) = (3, 3)
9055 09:25:34.948043 Byte1 TX OE(2T, 0.5T) = (3, 3)
9056 09:25:34.948599
9057 09:25:34.949091
9058 09:25:34.954884 [DQSOSCAuto] RK1, (LSB)MR18= 0xb08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 404 ps
9059 09:25:34.958143 CH1 RK1: MR19=303, MR18=B08
9060 09:25:34.964537 CH1_RK1: MR19=0x303, MR18=0xB08, DQSOSC=404, MR23=63, INC=22, DEC=15
9061 09:25:34.968215 [RxdqsGatingPostProcess] freq 1600
9062 09:25:34.971230 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9063 09:25:34.974193 best DQS0 dly(2T, 0.5T) = (1, 1)
9064 09:25:34.977648 best DQS1 dly(2T, 0.5T) = (1, 1)
9065 09:25:34.981185 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9066 09:25:34.984207 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9067 09:25:34.987596 best DQS0 dly(2T, 0.5T) = (1, 1)
9068 09:25:34.991212 best DQS1 dly(2T, 0.5T) = (1, 1)
9069 09:25:34.994216 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9070 09:25:34.997329 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9071 09:25:35.000871 Pre-setting of DQS Precalculation
9072 09:25:35.004307 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9073 09:25:35.013863 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9074 09:25:35.020530 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9075 09:25:35.020977
9076 09:25:35.021305
9077 09:25:35.023599 [Calibration Summary] 3200 Mbps
9078 09:25:35.024177 CH 0, Rank 0
9079 09:25:35.027420 SW Impedance : PASS
9080 09:25:35.027947 DUTY Scan : NO K
9081 09:25:35.030666 ZQ Calibration : PASS
9082 09:25:35.033616 Jitter Meter : NO K
9083 09:25:35.034227 CBT Training : PASS
9084 09:25:35.037389 Write leveling : PASS
9085 09:25:35.040481 RX DQS gating : PASS
9086 09:25:35.040982 RX DQ/DQS(RDDQC) : PASS
9087 09:25:35.043589 TX DQ/DQS : PASS
9088 09:25:35.046664 RX DATLAT : PASS
9089 09:25:35.047180 RX DQ/DQS(Engine): PASS
9090 09:25:35.050343 TX OE : PASS
9091 09:25:35.050964 All Pass.
9092 09:25:35.051468
9093 09:25:35.053664 CH 0, Rank 1
9094 09:25:35.054299 SW Impedance : PASS
9095 09:25:35.056840 DUTY Scan : NO K
9096 09:25:35.059889 ZQ Calibration : PASS
9097 09:25:35.060497 Jitter Meter : NO K
9098 09:25:35.063716 CBT Training : PASS
9099 09:25:35.066633 Write leveling : PASS
9100 09:25:35.067223 RX DQS gating : PASS
9101 09:25:35.070060 RX DQ/DQS(RDDQC) : PASS
9102 09:25:35.073420 TX DQ/DQS : PASS
9103 09:25:35.073993 RX DATLAT : PASS
9104 09:25:35.076415 RX DQ/DQS(Engine): PASS
9105 09:25:35.076952 TX OE : PASS
9106 09:25:35.079951 All Pass.
9107 09:25:35.080478
9108 09:25:35.080975 CH 1, Rank 0
9109 09:25:35.082930 SW Impedance : PASS
9110 09:25:35.086589 DUTY Scan : NO K
9111 09:25:35.087040 ZQ Calibration : PASS
9112 09:25:35.089935 Jitter Meter : NO K
9113 09:25:35.090632 CBT Training : PASS
9114 09:25:35.093379 Write leveling : PASS
9115 09:25:35.095958 RX DQS gating : PASS
9116 09:25:35.096375 RX DQ/DQS(RDDQC) : PASS
9117 09:25:35.099403 TX DQ/DQS : PASS
9118 09:25:35.102927 RX DATLAT : PASS
9119 09:25:35.103342 RX DQ/DQS(Engine): PASS
9120 09:25:35.105968 TX OE : PASS
9121 09:25:35.106480 All Pass.
9122 09:25:35.106815
9123 09:25:35.109317 CH 1, Rank 1
9124 09:25:35.109728 SW Impedance : PASS
9125 09:25:35.112707 DUTY Scan : NO K
9126 09:25:35.116321 ZQ Calibration : PASS
9127 09:25:35.116871 Jitter Meter : NO K
9128 09:25:35.119360 CBT Training : PASS
9129 09:25:35.122425 Write leveling : PASS
9130 09:25:35.122995 RX DQS gating : PASS
9131 09:25:35.126120 RX DQ/DQS(RDDQC) : PASS
9132 09:25:35.129075 TX DQ/DQS : PASS
9133 09:25:35.129628 RX DATLAT : PASS
9134 09:25:35.132234 RX DQ/DQS(Engine): PASS
9135 09:25:35.136044 TX OE : PASS
9136 09:25:35.136606 All Pass.
9137 09:25:35.137089
9138 09:25:35.137559 DramC Write-DBI on
9139 09:25:35.139194 PER_BANK_REFRESH: Hybrid Mode
9140 09:25:35.142346 TX_TRACKING: ON
9141 09:25:35.149052 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9142 09:25:35.159067 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9143 09:25:35.165678 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9144 09:25:35.168493 [FAST_K] Save calibration result to emmc
9145 09:25:35.172227 sync common calibartion params.
9146 09:25:35.175369 sync cbt_mode0:1, 1:1
9147 09:25:35.175925 dram_init: ddr_geometry: 2
9148 09:25:35.178545 dram_init: ddr_geometry: 2
9149 09:25:35.182238 dram_init: ddr_geometry: 2
9150 09:25:35.185113 0:dram_rank_size:100000000
9151 09:25:35.185697 1:dram_rank_size:100000000
9152 09:25:35.191887 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9153 09:25:35.195149 DFS_SHUFFLE_HW_MODE: ON
9154 09:25:35.198616 dramc_set_vcore_voltage set vcore to 725000
9155 09:25:35.201671 Read voltage for 1600, 0
9156 09:25:35.202297 Vio18 = 0
9157 09:25:35.202762 Vcore = 725000
9158 09:25:35.203215 Vdram = 0
9159 09:25:35.204774 Vddq = 0
9160 09:25:35.205276 Vmddr = 0
9161 09:25:35.208229 switch to 3200 Mbps bootup
9162 09:25:35.208798 [DramcRunTimeConfig]
9163 09:25:35.211422 PHYPLL
9164 09:25:35.211965 DPM_CONTROL_AFTERK: ON
9165 09:25:35.214746 PER_BANK_REFRESH: ON
9166 09:25:35.218249 REFRESH_OVERHEAD_REDUCTION: ON
9167 09:25:35.218756 CMD_PICG_NEW_MODE: OFF
9168 09:25:35.221384 XRTWTW_NEW_MODE: ON
9169 09:25:35.221916 XRTRTR_NEW_MODE: ON
9170 09:25:35.224635 TX_TRACKING: ON
9171 09:25:35.225154 RDSEL_TRACKING: OFF
9172 09:25:35.227850 DQS Precalculation for DVFS: ON
9173 09:25:35.231109 RX_TRACKING: OFF
9174 09:25:35.231214 HW_GATING DBG: ON
9175 09:25:35.234184 ZQCS_ENABLE_LP4: ON
9176 09:25:35.234303 RX_PICG_NEW_MODE: ON
9177 09:25:35.237792 TX_PICG_NEW_MODE: ON
9178 09:25:35.237902 ENABLE_RX_DCM_DPHY: ON
9179 09:25:35.240988 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9180 09:25:35.244079 DUMMY_READ_FOR_TRACKING: OFF
9181 09:25:35.247201 !!! SPM_CONTROL_AFTERK: OFF
9182 09:25:35.250977 !!! SPM could not control APHY
9183 09:25:35.251064 IMPEDANCE_TRACKING: ON
9184 09:25:35.254055 TEMP_SENSOR: ON
9185 09:25:35.254156 HW_SAVE_FOR_SR: OFF
9186 09:25:35.257044 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9187 09:25:35.260849 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9188 09:25:35.263894 Read ODT Tracking: ON
9189 09:25:35.267165 Refresh Rate DeBounce: ON
9190 09:25:35.267266 DFS_NO_QUEUE_FLUSH: ON
9191 09:25:35.270587 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9192 09:25:35.273600 ENABLE_DFS_RUNTIME_MRW: OFF
9193 09:25:35.277335 DDR_RESERVE_NEW_MODE: ON
9194 09:25:35.277441 MR_CBT_SWITCH_FREQ: ON
9195 09:25:35.280349 =========================
9196 09:25:35.299466 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9197 09:25:35.302965 dram_init: ddr_geometry: 2
9198 09:25:35.320998 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9199 09:25:35.324478 dram_init: dram init end (result: 0)
9200 09:25:35.331208 DRAM-K: Full calibration passed in 24643 msecs
9201 09:25:35.334490 MRC: failed to locate region type 0.
9202 09:25:35.334595 DRAM rank0 size:0x100000000,
9203 09:25:35.337381 DRAM rank1 size=0x100000000
9204 09:25:35.347827 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9205 09:25:35.354142 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9206 09:25:35.360848 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9207 09:25:35.370480 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9208 09:25:35.370583 DRAM rank0 size:0x100000000,
9209 09:25:35.374131 DRAM rank1 size=0x100000000
9210 09:25:35.374264 CBMEM:
9211 09:25:35.377243 IMD: root @ 0xfffff000 254 entries.
9212 09:25:35.380292 IMD: root @ 0xffffec00 62 entries.
9213 09:25:35.383954 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9214 09:25:35.390118 WARNING: RO_VPD is uninitialized or empty.
9215 09:25:35.393380 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9216 09:25:35.401082 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9217 09:25:35.413785 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9218 09:25:35.425212 BS: romstage times (exec / console): total (unknown) / 24135 ms
9219 09:25:35.425319
9220 09:25:35.425409
9221 09:25:35.435278 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9222 09:25:35.438758 ARM64: Exception handlers installed.
9223 09:25:35.442085 ARM64: Testing exception
9224 09:25:35.444880 ARM64: Done test exception
9225 09:25:35.444978 Enumerating buses...
9226 09:25:35.448279 Show all devs... Before device enumeration.
9227 09:25:35.451941 Root Device: enabled 1
9228 09:25:35.455002 CPU_CLUSTER: 0: enabled 1
9229 09:25:35.455099 CPU: 00: enabled 1
9230 09:25:35.458067 Compare with tree...
9231 09:25:35.458195 Root Device: enabled 1
9232 09:25:35.461777 CPU_CLUSTER: 0: enabled 1
9233 09:25:35.464808 CPU: 00: enabled 1
9234 09:25:35.464899 Root Device scanning...
9235 09:25:35.467924 scan_static_bus for Root Device
9236 09:25:35.471675 CPU_CLUSTER: 0 enabled
9237 09:25:35.474799 scan_static_bus for Root Device done
9238 09:25:35.477905 scan_bus: bus Root Device finished in 8 msecs
9239 09:25:35.478003 done
9240 09:25:35.484607 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9241 09:25:35.488165 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9242 09:25:35.494371 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9243 09:25:35.501208 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9244 09:25:35.501306 Allocating resources...
9245 09:25:35.504219 Reading resources...
9246 09:25:35.507780 Root Device read_resources bus 0 link: 0
9247 09:25:35.510638 DRAM rank0 size:0x100000000,
9248 09:25:35.510741 DRAM rank1 size=0x100000000
9249 09:25:35.517608 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9250 09:25:35.517711 CPU: 00 missing read_resources
9251 09:25:35.523723 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9252 09:25:35.527397 Root Device read_resources bus 0 link: 0 done
9253 09:25:35.530388 Done reading resources.
9254 09:25:35.533859 Show resources in subtree (Root Device)...After reading.
9255 09:25:35.536977 Root Device child on link 0 CPU_CLUSTER: 0
9256 09:25:35.540500 CPU_CLUSTER: 0 child on link 0 CPU: 00
9257 09:25:35.550265 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9258 09:25:35.550372 CPU: 00
9259 09:25:35.557032 Root Device assign_resources, bus 0 link: 0
9260 09:25:35.560015 CPU_CLUSTER: 0 missing set_resources
9261 09:25:35.563679 Root Device assign_resources, bus 0 link: 0 done
9262 09:25:35.566812 Done setting resources.
9263 09:25:35.569922 Show resources in subtree (Root Device)...After assigning values.
9264 09:25:35.573618 Root Device child on link 0 CPU_CLUSTER: 0
9265 09:25:35.579932 CPU_CLUSTER: 0 child on link 0 CPU: 00
9266 09:25:35.586545 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9267 09:25:35.590265 CPU: 00
9268 09:25:35.590361 Done allocating resources.
9269 09:25:35.596436 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9270 09:25:35.596533 Enabling resources...
9271 09:25:35.599470 done.
9272 09:25:35.603272 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9273 09:25:35.606395 Initializing devices...
9274 09:25:35.606469 Root Device init
9275 09:25:35.609848 init hardware done!
9276 09:25:35.609959 0x00000018: ctrlr->caps
9277 09:25:35.612955 52.000 MHz: ctrlr->f_max
9278 09:25:35.616606 0.400 MHz: ctrlr->f_min
9279 09:25:35.619446 0x40ff8080: ctrlr->voltages
9280 09:25:35.619555 sclk: 390625
9281 09:25:35.619642 Bus Width = 1
9282 09:25:35.622767 sclk: 390625
9283 09:25:35.622871 Bus Width = 1
9284 09:25:35.626294 Early init status = 3
9285 09:25:35.629369 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9286 09:25:35.633168 in-header: 03 fc 00 00 01 00 00 00
9287 09:25:35.636237 in-data: 00
9288 09:25:35.639315 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9289 09:25:35.644461 in-header: 03 fd 00 00 00 00 00 00
9290 09:25:35.647296 in-data:
9291 09:25:35.650553 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9292 09:25:35.657777 in-header: 03 fc 00 00 01 00 00 00
9293 09:25:35.657908 in-data: 00
9294 09:25:35.661231 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9295 09:25:35.666764 in-header: 03 fd 00 00 00 00 00 00
9296 09:25:35.670369 in-data:
9297 09:25:35.673808 [SSUSB] Setting up USB HOST controller...
9298 09:25:35.677007 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9299 09:25:35.680133 [SSUSB] phy power-on done.
9300 09:25:35.683258 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9301 09:25:35.689857 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9302 09:25:35.693532 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9303 09:25:35.700236 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9304 09:25:35.706525 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9305 09:25:35.713075 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9306 09:25:35.719901 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9307 09:25:35.726531 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9308 09:25:35.730042 SPM: binary array size = 0x9dc
9309 09:25:35.732882 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9310 09:25:35.739935 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9311 09:25:35.746143 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9312 09:25:35.752748 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9313 09:25:35.755936 configure_display: Starting display init
9314 09:25:35.790439 anx7625_power_on_init: Init interface.
9315 09:25:35.793574 anx7625_disable_pd_protocol: Disabled PD feature.
9316 09:25:35.799631 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9317 09:25:35.824786 anx7625_start_dp_work: Secure OCM version=00
9318 09:25:35.827881 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9319 09:25:35.842880 sp_tx_get_edid_block: EDID Block = 1
9320 09:25:35.945635 Extracted contents:
9321 09:25:35.948553 header: 00 ff ff ff ff ff ff 00
9322 09:25:35.952026 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9323 09:25:35.955410 version: 01 04
9324 09:25:35.958833 basic params: 95 1f 11 78 0a
9325 09:25:35.961815 chroma info: 76 90 94 55 54 90 27 21 50 54
9326 09:25:35.965438 established: 00 00 00
9327 09:25:35.971604 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9328 09:25:35.975136 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9329 09:25:35.981325 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9330 09:25:35.987848 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9331 09:25:35.994918 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9332 09:25:35.997857 extensions: 00
9333 09:25:35.997953 checksum: fb
9334 09:25:35.998063
9335 09:25:36.001529 Manufacturer: IVO Model 57d Serial Number 0
9336 09:25:36.004478 Made week 0 of 2020
9337 09:25:36.007735 EDID version: 1.4
9338 09:25:36.007830 Digital display
9339 09:25:36.011354 6 bits per primary color channel
9340 09:25:36.011450 DisplayPort interface
9341 09:25:36.014363 Maximum image size: 31 cm x 17 cm
9342 09:25:36.018079 Gamma: 220%
9343 09:25:36.018211 Check DPMS levels
9344 09:25:36.021187 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9345 09:25:36.027834 First detailed timing is preferred timing
9346 09:25:36.027939 Established timings supported:
9347 09:25:36.031575 Standard timings supported:
9348 09:25:36.034622 Detailed timings
9349 09:25:36.037741 Hex of detail: 383680a07038204018303c0035ae10000019
9350 09:25:36.044477 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9351 09:25:36.047608 0780 0798 07c8 0820 hborder 0
9352 09:25:36.051321 0438 043b 0447 0458 vborder 0
9353 09:25:36.054383 -hsync -vsync
9354 09:25:36.054481 Did detailed timing
9355 09:25:36.060850 Hex of detail: 000000000000000000000000000000000000
9356 09:25:36.064437 Manufacturer-specified data, tag 0
9357 09:25:36.067252 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9358 09:25:36.070709 ASCII string: InfoVision
9359 09:25:36.073844 Hex of detail: 000000fe00523134304e574635205248200a
9360 09:25:36.077561 ASCII string: R140NWF5 RH
9361 09:25:36.077665 Checksum
9362 09:25:36.080621 Checksum: 0xfb (valid)
9363 09:25:36.083825 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9364 09:25:36.087433 DSI data_rate: 832800000 bps
9365 09:25:36.093480 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9366 09:25:36.097255 anx7625_parse_edid: pixelclock(138800).
9367 09:25:36.099990 hactive(1920), hsync(48), hfp(24), hbp(88)
9368 09:25:36.103259 vactive(1080), vsync(12), vfp(3), vbp(17)
9369 09:25:36.106913 anx7625_dsi_config: config dsi.
9370 09:25:36.113209 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9371 09:25:36.127093 anx7625_dsi_config: success to config DSI
9372 09:25:36.130671 anx7625_dp_start: MIPI phy setup OK.
9373 09:25:36.133701 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9374 09:25:36.137400 mtk_ddp_mode_set invalid vrefresh 60
9375 09:25:36.140446 main_disp_path_setup
9376 09:25:36.140542 ovl_layer_smi_id_en
9377 09:25:36.143547 ovl_layer_smi_id_en
9378 09:25:36.143612 ccorr_config
9379 09:25:36.143672 aal_config
9380 09:25:36.147249 gamma_config
9381 09:25:36.147318 postmask_config
9382 09:25:36.150317 dither_config
9383 09:25:36.153475 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9384 09:25:36.160250 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9385 09:25:36.163419 Root Device init finished in 553 msecs
9386 09:25:36.167088 CPU_CLUSTER: 0 init
9387 09:25:36.173045 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9388 09:25:36.179729 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9389 09:25:36.179834 APU_MBOX 0x190000b0 = 0x10001
9390 09:25:36.183403 APU_MBOX 0x190001b0 = 0x10001
9391 09:25:36.186467 APU_MBOX 0x190005b0 = 0x10001
9392 09:25:36.189567 APU_MBOX 0x190006b0 = 0x10001
9393 09:25:36.196370 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9394 09:25:36.206431 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9395 09:25:36.218830 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9396 09:25:36.225202 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9397 09:25:36.236835 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9398 09:25:36.245993 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9399 09:25:36.249643 CPU_CLUSTER: 0 init finished in 81 msecs
9400 09:25:36.252851 Devices initialized
9401 09:25:36.255930 Show all devs... After init.
9402 09:25:36.256026 Root Device: enabled 1
9403 09:25:36.259081 CPU_CLUSTER: 0: enabled 1
9404 09:25:36.262681 CPU: 00: enabled 1
9405 09:25:36.265717 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9406 09:25:36.268769 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9407 09:25:36.272484 ELOG: NV offset 0x57f000 size 0x1000
9408 09:25:36.279022 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9409 09:25:36.285985 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9410 09:25:36.289051 ELOG: Event(17) added with size 13 at 2024-06-18 09:25:35 UTC
9411 09:25:36.295766 out: cmd=0x121: 03 db 21 01 00 00 00 00
9412 09:25:36.298805 in-header: 03 29 00 00 2c 00 00 00
9413 09:25:36.312146 in-data: 13 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9414 09:25:36.315229 ELOG: Event(A1) added with size 10 at 2024-06-18 09:25:35 UTC
9415 09:25:36.324947 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9416 09:25:36.328777 ELOG: Event(A0) added with size 9 at 2024-06-18 09:25:35 UTC
9417 09:25:36.331953 elog_add_boot_reason: Logged dev mode boot
9418 09:25:36.338466 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9419 09:25:36.338571 Finalize devices...
9420 09:25:36.341722 Devices finalized
9421 09:25:36.344892 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9422 09:25:36.351818 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9423 09:25:36.354943 in-header: 03 07 00 00 08 00 00 00
9424 09:25:36.358074 in-data: aa e4 47 04 13 02 00 00
9425 09:25:36.358190 Chrome EC: UHEPI supported
9426 09:25:36.364861 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9427 09:25:36.367932 in-header: 03 a9 00 00 08 00 00 00
9428 09:25:36.371826 in-data: 84 60 60 08 00 00 00 00
9429 09:25:36.377757 ELOG: Event(91) added with size 10 at 2024-06-18 09:25:35 UTC
9430 09:25:36.381465 Chrome EC: clear events_b mask to 0x0000000020004000
9431 09:25:36.387738 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9432 09:25:36.391792 in-header: 03 fd 00 00 00 00 00 00
9433 09:25:36.395395 in-data:
9434 09:25:36.398478 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9435 09:25:36.401613 Writing coreboot table at 0xffe64000
9436 09:25:36.408423 0. 000000000010a000-0000000000113fff: RAMSTAGE
9437 09:25:36.411943 1. 0000000040000000-00000000400fffff: RAM
9438 09:25:36.414692 2. 0000000040100000-000000004032afff: RAMSTAGE
9439 09:25:36.418373 3. 000000004032b000-00000000545fffff: RAM
9440 09:25:36.421338 4. 0000000054600000-000000005465ffff: BL31
9441 09:25:36.428192 5. 0000000054660000-00000000ffe63fff: RAM
9442 09:25:36.431294 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9443 09:25:36.434874 7. 0000000100000000-000000023fffffff: RAM
9444 09:25:36.437749 Passing 5 GPIOs to payload:
9445 09:25:36.441748 NAME | PORT | POLARITY | VALUE
9446 09:25:36.448171 EC in RW | 0x000000aa | low | undefined
9447 09:25:36.451276 EC interrupt | 0x00000005 | low | undefined
9448 09:25:36.458014 TPM interrupt | 0x000000ab | high | undefined
9449 09:25:36.461235 SD card detect | 0x00000011 | high | undefined
9450 09:25:36.464781 speaker enable | 0x00000093 | high | undefined
9451 09:25:36.467735 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9452 09:25:36.472827 in-header: 03 f9 00 00 02 00 00 00
9453 09:25:36.475917 in-data: 02 00
9454 09:25:36.478778 ADC[4]: Raw value=903400 ID=7
9455 09:25:36.482543 ADC[3]: Raw value=213652 ID=1
9456 09:25:36.482642 RAM Code: 0x71
9457 09:25:36.485574 ADC[6]: Raw value=75036 ID=0
9458 09:25:36.489300 ADC[5]: Raw value=213282 ID=1
9459 09:25:36.489398 SKU Code: 0x1
9460 09:25:36.495341 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum aa70
9461 09:25:36.495443 coreboot table: 964 bytes.
9462 09:25:36.498994 IMD ROOT 0. 0xfffff000 0x00001000
9463 09:25:36.502172 IMD SMALL 1. 0xffffe000 0x00001000
9464 09:25:36.505174 RO MCACHE 2. 0xffffc000 0x00001104
9465 09:25:36.508877 CONSOLE 3. 0xfff7c000 0x00080000
9466 09:25:36.512001 FMAP 4. 0xfff7b000 0x00000452
9467 09:25:36.515632 TIME STAMP 5. 0xfff7a000 0x00000910
9468 09:25:36.518514 VBOOT WORK 6. 0xfff66000 0x00014000
9469 09:25:36.521907 RAMOOPS 7. 0xffe66000 0x00100000
9470 09:25:36.525275 COREBOOT 8. 0xffe64000 0x00002000
9471 09:25:36.528622 IMD small region:
9472 09:25:36.531590 IMD ROOT 0. 0xffffec00 0x00000400
9473 09:25:36.534744 VPD 1. 0xffffeb80 0x0000006c
9474 09:25:36.538463 MMC STATUS 2. 0xffffeb60 0x00000004
9475 09:25:36.544504 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9476 09:25:36.551346 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9477 09:25:36.589805 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9478 09:25:36.593461 Checking segment from ROM address 0x40100000
9479 09:25:36.596482 Checking segment from ROM address 0x4010001c
9480 09:25:36.603438 Loading segment from ROM address 0x40100000
9481 09:25:36.603539 code (compression=0)
9482 09:25:36.613252 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9483 09:25:36.619539 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9484 09:25:36.619643 it's not compressed!
9485 09:25:36.626244 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9486 09:25:36.632568 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9487 09:25:36.650754 Loading segment from ROM address 0x4010001c
9488 09:25:36.650863 Entry Point 0x80000000
9489 09:25:36.653790 Loaded segments
9490 09:25:36.657133 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9491 09:25:36.663505 Jumping to boot code at 0x80000000(0xffe64000)
9492 09:25:36.670329 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9493 09:25:36.676926 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9494 09:25:36.684923 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9495 09:25:36.688205 Checking segment from ROM address 0x40100000
9496 09:25:36.691179 Checking segment from ROM address 0x4010001c
9497 09:25:36.698024 Loading segment from ROM address 0x40100000
9498 09:25:36.698107 code (compression=1)
9499 09:25:36.704323 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9500 09:25:36.714643 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9501 09:25:36.714721 using LZMA
9502 09:25:36.722968 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9503 09:25:36.729764 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9504 09:25:36.732757 Loading segment from ROM address 0x4010001c
9505 09:25:36.736209 Entry Point 0x54601000
9506 09:25:36.736309 Loaded segments
9507 09:25:36.739542 NOTICE: MT8192 bl31_setup
9508 09:25:36.746994 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9509 09:25:36.750091 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9510 09:25:36.753181 WARNING: region 0:
9511 09:25:36.756910 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 09:25:36.757027 WARNING: region 1:
9513 09:25:36.763067 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9514 09:25:36.766826 WARNING: region 2:
9515 09:25:36.769826 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9516 09:25:36.772992 WARNING: region 3:
9517 09:25:36.779555 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9518 09:25:36.779648 WARNING: region 4:
9519 09:25:36.786400 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9520 09:25:36.786511 WARNING: region 5:
9521 09:25:36.789855 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9522 09:25:36.792851 WARNING: region 6:
9523 09:25:36.796475 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9524 09:25:36.799416 WARNING: region 7:
9525 09:25:36.803094 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9526 09:25:36.809399 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9527 09:25:36.812636 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9528 09:25:36.819518 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9529 09:25:36.822532 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9530 09:25:36.826026 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9531 09:25:36.832484 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9532 09:25:36.836067 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9533 09:25:36.839124 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9534 09:25:36.845769 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9535 09:25:36.849235 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9536 09:25:36.855497 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9537 09:25:36.859223 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9538 09:25:36.862406 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9539 09:25:36.869036 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9540 09:25:36.871982 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9541 09:25:36.875373 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9542 09:25:36.882141 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9543 09:25:36.885331 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9544 09:25:36.892267 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9545 09:25:36.895225 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9546 09:25:36.898798 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9547 09:25:36.905419 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9548 09:25:36.908379 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9549 09:25:36.915265 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9550 09:25:36.918373 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9551 09:25:36.921466 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9552 09:25:36.928302 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9553 09:25:36.931840 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9554 09:25:36.938616 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9555 09:25:36.941706 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9556 09:25:36.948043 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9557 09:25:36.951652 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9558 09:25:36.954578 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9559 09:25:36.958000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9560 09:25:36.964689 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9561 09:25:36.967822 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9562 09:25:36.971540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9563 09:25:36.974574 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9564 09:25:36.981146 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9565 09:25:36.984833 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9566 09:25:36.988043 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9567 09:25:36.991515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9568 09:25:36.997524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9569 09:25:37.001030 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9570 09:25:37.004273 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9571 09:25:37.011101 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9572 09:25:37.014342 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9573 09:25:37.017461 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9574 09:25:37.024345 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9575 09:25:37.027429 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9576 09:25:37.030554 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9577 09:25:37.037484 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9578 09:25:37.041094 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9579 09:25:37.047494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9580 09:25:37.050543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9581 09:25:37.057444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9582 09:25:37.060485 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9583 09:25:37.063821 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9584 09:25:37.070388 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9585 09:25:37.073549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9586 09:25:37.080259 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9587 09:25:37.083368 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9588 09:25:37.090115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9589 09:25:37.093312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9590 09:25:37.100078 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9591 09:25:37.103137 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9592 09:25:37.110001 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9593 09:25:37.113345 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9594 09:25:37.116656 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9595 09:25:37.122989 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9596 09:25:37.126384 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9597 09:25:37.132844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9598 09:25:37.136083 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9599 09:25:37.142779 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9600 09:25:37.146586 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9601 09:25:37.153200 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9602 09:25:37.155973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9603 09:25:37.159707 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9604 09:25:37.165878 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9605 09:25:37.169444 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9606 09:25:37.175667 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9607 09:25:37.179437 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9608 09:25:37.185638 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9609 09:25:37.189177 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9610 09:25:37.195736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9611 09:25:37.198832 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9612 09:25:37.202476 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9613 09:25:37.208706 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9614 09:25:37.212245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9615 09:25:37.218626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9616 09:25:37.222377 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9617 09:25:37.228926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9618 09:25:37.232317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9619 09:25:37.238823 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9620 09:25:37.242065 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9621 09:25:37.245234 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9622 09:25:37.252018 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9623 09:25:37.255072 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9624 09:25:37.258585 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9625 09:25:37.262230 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9626 09:25:37.268193 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9627 09:25:37.271965 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9628 09:25:37.278573 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9629 09:25:37.281517 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9630 09:25:37.285105 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9631 09:25:37.291330 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9632 09:25:37.294943 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9633 09:25:37.301662 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9634 09:25:37.304686 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9635 09:25:37.311531 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9636 09:25:37.314667 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9637 09:25:37.317773 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9638 09:25:37.324407 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9639 09:25:37.327548 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9640 09:25:37.334393 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9641 09:25:37.337465 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9642 09:25:37.341231 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9643 09:25:37.344053 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9644 09:25:37.351086 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9645 09:25:37.354264 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9646 09:25:37.357185 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9647 09:25:37.364139 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9648 09:25:37.367605 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9649 09:25:37.370534 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9650 09:25:37.374077 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9651 09:25:37.380960 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9652 09:25:37.383896 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9653 09:25:37.390974 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9654 09:25:37.393944 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9655 09:25:37.400828 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9656 09:25:37.403773 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9657 09:25:37.407050 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9658 09:25:37.413476 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9659 09:25:37.417267 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9660 09:25:37.423316 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9661 09:25:37.426869 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9662 09:25:37.429995 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9663 09:25:37.436754 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9664 09:25:37.439941 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9665 09:25:37.443102 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9666 09:25:37.449899 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9667 09:25:37.453012 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9668 09:25:37.459770 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9669 09:25:37.463050 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9670 09:25:37.469831 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9671 09:25:37.473036 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9672 09:25:37.475984 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9673 09:25:37.482863 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9674 09:25:37.485925 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9675 09:25:37.492756 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9676 09:25:37.495778 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9677 09:25:37.499032 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9678 09:25:37.505801 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9679 09:25:37.508881 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9680 09:25:37.515332 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9681 09:25:37.518753 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9682 09:25:37.522306 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9683 09:25:37.528712 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9684 09:25:37.532355 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9685 09:25:37.538600 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9686 09:25:37.541718 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9687 09:25:37.545499 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9688 09:25:37.552185 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9689 09:25:37.555332 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9690 09:25:37.562075 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9691 09:25:37.565066 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9692 09:25:37.568471 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9693 09:25:37.575230 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9694 09:25:37.578500 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9695 09:25:37.584696 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9696 09:25:37.588042 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9697 09:25:37.591476 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9698 09:25:37.598476 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9699 09:25:37.601478 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9700 09:25:37.607807 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9701 09:25:37.611039 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9702 09:25:37.614728 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9703 09:25:37.621408 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9704 09:25:37.624403 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9705 09:25:37.631391 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9706 09:25:37.634706 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9707 09:25:37.637884 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9708 09:25:37.645132 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9709 09:25:37.647976 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9710 09:25:37.651135 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9711 09:25:37.657958 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9712 09:25:37.661045 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9713 09:25:37.667904 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9714 09:25:37.670818 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9715 09:25:37.677442 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9716 09:25:37.681055 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9717 09:25:37.684620 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9718 09:25:37.691008 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9719 09:25:37.694403 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9720 09:25:37.700679 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9721 09:25:37.703835 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9722 09:25:37.707501 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9723 09:25:37.714015 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9724 09:25:37.717370 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9725 09:25:37.723982 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9726 09:25:37.727100 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9727 09:25:37.733895 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9728 09:25:37.736935 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9729 09:25:37.740539 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9730 09:25:37.747018 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9731 09:25:37.750021 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9732 09:25:37.756853 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9733 09:25:37.760005 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9734 09:25:37.766767 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9735 09:25:37.769881 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9736 09:25:37.773556 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9737 09:25:37.779781 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9738 09:25:37.783225 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9739 09:25:37.789844 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9740 09:25:37.792900 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9741 09:25:37.799629 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9742 09:25:37.802935 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9743 09:25:37.806051 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9744 09:25:37.813204 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9745 09:25:37.816270 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9746 09:25:37.822610 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9747 09:25:37.826080 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9748 09:25:37.832762 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9749 09:25:37.835862 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9750 09:25:37.838984 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9751 09:25:37.845820 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9752 09:25:37.849030 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9753 09:25:37.855730 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9754 09:25:37.859161 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9755 09:25:37.862403 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9756 09:25:37.868546 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9757 09:25:37.872338 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9758 09:25:37.875482 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9759 09:25:37.878571 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9760 09:25:37.885572 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9761 09:25:37.888744 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9762 09:25:37.891785 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9763 09:25:37.898451 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9764 09:25:37.901783 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9765 09:25:37.908121 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9766 09:25:37.911653 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9767 09:25:37.914988 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9768 09:25:37.921895 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9769 09:25:37.925242 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9770 09:25:37.928184 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9771 09:25:37.934774 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9772 09:25:37.937919 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9773 09:25:37.944213 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9774 09:25:37.947978 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9775 09:25:37.951137 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9776 09:25:37.957790 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9777 09:25:37.960898 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9778 09:25:37.967483 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9779 09:25:37.970942 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9780 09:25:37.974315 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9781 09:25:37.981054 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9782 09:25:37.984165 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9783 09:25:37.987116 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9784 09:25:37.993951 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9785 09:25:37.997108 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9786 09:25:38.003536 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9787 09:25:38.006737 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9788 09:25:38.009923 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9789 09:25:38.016897 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9790 09:25:38.019939 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9791 09:25:38.023351 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9792 09:25:38.029604 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9793 09:25:38.032863 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9794 09:25:38.039423 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9795 09:25:38.042942 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9796 09:25:38.046401 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9797 09:25:38.049571 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9798 09:25:38.052754 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9799 09:25:38.059490 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9800 09:25:38.062565 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9801 09:25:38.066153 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9802 09:25:38.069199 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9803 09:25:38.076123 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9804 09:25:38.079215 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9805 09:25:38.082690 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9806 09:25:38.089250 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9807 09:25:38.092769 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9808 09:25:38.095652 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9809 09:25:38.102499 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9810 09:25:38.105833 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9811 09:25:38.112138 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9812 09:25:38.115910 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9813 09:25:38.118964 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9814 09:25:38.125740 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9815 09:25:38.128798 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9816 09:25:38.135413 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9817 09:25:38.138926 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9818 09:25:38.141786 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9819 09:25:38.149220 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9820 09:25:38.151894 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9821 09:25:38.158467 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9822 09:25:38.162221 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9823 09:25:38.165269 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9824 09:25:38.172010 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9825 09:25:38.175268 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9826 09:25:38.181851 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9827 09:25:38.185487 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9828 09:25:38.191649 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9829 09:25:38.195132 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9830 09:25:38.201433 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9831 09:25:38.204833 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9832 09:25:38.208310 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9833 09:25:38.214900 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9834 09:25:38.217984 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9835 09:25:38.224755 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9836 09:25:38.227869 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9837 09:25:38.230862 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9838 09:25:38.237723 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9839 09:25:38.240806 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9840 09:25:38.247698 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9841 09:25:38.251152 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9842 09:25:38.254209 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9843 09:25:38.260794 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9844 09:25:38.264258 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9845 09:25:38.271092 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9846 09:25:38.274111 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9847 09:25:38.277338 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9848 09:25:38.284064 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9849 09:25:38.287295 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9850 09:25:38.294012 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9851 09:25:38.297097 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9852 09:25:38.303791 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9853 09:25:38.306779 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9854 09:25:38.313442 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9855 09:25:38.317062 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9856 09:25:38.320248 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9857 09:25:38.326700 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9858 09:25:38.330342 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9859 09:25:38.336436 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9860 09:25:38.340247 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9861 09:25:38.343428 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9862 09:25:38.350205 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9863 09:25:38.353106 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9864 09:25:38.359593 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9865 09:25:38.362995 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9866 09:25:38.366482 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9867 09:25:38.372767 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9868 09:25:38.376287 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9869 09:25:38.383202 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9870 09:25:38.386137 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9871 09:25:38.392929 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9872 09:25:38.395982 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9873 09:25:38.399083 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9874 09:25:38.406052 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9875 09:25:38.409170 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9876 09:25:38.415378 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9877 09:25:38.418836 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9878 09:25:38.425707 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9879 09:25:38.429041 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9880 09:25:38.432370 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9881 09:25:38.439209 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9882 09:25:38.442399 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9883 09:25:38.449367 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9884 09:25:38.452432 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9885 09:25:38.459032 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9886 09:25:38.462040 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9887 09:25:38.465693 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9888 09:25:38.472151 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9889 09:25:38.475592 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9890 09:25:38.482228 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9891 09:25:38.485336 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9892 09:25:38.491847 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9893 09:25:38.494966 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9894 09:25:38.501759 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9895 09:25:38.504853 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9896 09:25:38.508630 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9897 09:25:38.514888 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9898 09:25:38.518020 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9899 09:25:38.524723 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9900 09:25:38.528167 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9901 09:25:38.534699 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9902 09:25:38.538128 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9903 09:25:38.541520 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9904 09:25:38.547941 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9905 09:25:38.550986 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9906 09:25:38.557740 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9907 09:25:38.560880 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9908 09:25:38.567572 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9909 09:25:38.571346 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9910 09:25:38.577467 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9911 09:25:38.580899 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9912 09:25:38.584434 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9913 09:25:38.590949 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9914 09:25:38.594472 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9915 09:25:38.600948 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9916 09:25:38.604274 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9917 09:25:38.611471 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9918 09:25:38.614404 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9919 09:25:38.621292 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9920 09:25:38.624351 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9921 09:25:38.627932 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9922 09:25:38.634301 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9923 09:25:38.637454 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9924 09:25:38.644095 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9925 09:25:38.647594 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9926 09:25:38.654157 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9927 09:25:38.656924 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9928 09:25:38.660813 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9929 09:25:38.666730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9930 09:25:38.670454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9931 09:25:38.677224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9932 09:25:38.680160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9933 09:25:38.686786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9934 09:25:38.690298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9935 09:25:38.696418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9936 09:25:38.700129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9937 09:25:38.706628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9938 09:25:38.710122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9939 09:25:38.716814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9940 09:25:38.719834 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9941 09:25:38.726607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9942 09:25:38.729626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9943 09:25:38.736553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9944 09:25:38.739395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9945 09:25:38.746438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9946 09:25:38.749399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9947 09:25:38.756204 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9948 09:25:38.759307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9949 09:25:38.765794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9950 09:25:38.769457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9951 09:25:38.775711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9952 09:25:38.779037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9953 09:25:38.785698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9954 09:25:38.789441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9955 09:25:38.795946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9956 09:25:38.798926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9957 09:25:38.805832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9958 09:25:38.808888 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9959 09:25:38.815656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9960 09:25:38.819078 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9961 09:25:38.822197 INFO: [APUAPC] vio 0
9962 09:25:38.825778 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9963 09:25:38.831833 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9964 09:25:38.835762 INFO: [APUAPC] D0_APC_0: 0x400510
9965 09:25:38.838646 INFO: [APUAPC] D0_APC_1: 0x0
9966 09:25:38.839098 INFO: [APUAPC] D0_APC_2: 0x1540
9967 09:25:38.842206 INFO: [APUAPC] D0_APC_3: 0x0
9968 09:25:38.845610 INFO: [APUAPC] D1_APC_0: 0xffffffff
9969 09:25:38.848466 INFO: [APUAPC] D1_APC_1: 0xffffffff
9970 09:25:38.851912 INFO: [APUAPC] D1_APC_2: 0x3fffff
9971 09:25:38.855037 INFO: [APUAPC] D1_APC_3: 0x0
9972 09:25:38.858198 INFO: [APUAPC] D2_APC_0: 0xffffffff
9973 09:25:38.861756 INFO: [APUAPC] D2_APC_1: 0xffffffff
9974 09:25:38.864942 INFO: [APUAPC] D2_APC_2: 0x3fffff
9975 09:25:38.868680 INFO: [APUAPC] D2_APC_3: 0x0
9976 09:25:38.871359 INFO: [APUAPC] D3_APC_0: 0xffffffff
9977 09:25:38.874705 INFO: [APUAPC] D3_APC_1: 0xffffffff
9978 09:25:38.878210 INFO: [APUAPC] D3_APC_2: 0x3fffff
9979 09:25:38.881326 INFO: [APUAPC] D3_APC_3: 0x0
9980 09:25:38.885067 INFO: [APUAPC] D4_APC_0: 0xffffffff
9981 09:25:38.888071 INFO: [APUAPC] D4_APC_1: 0xffffffff
9982 09:25:38.892022 INFO: [APUAPC] D4_APC_2: 0x3fffff
9983 09:25:38.894723 INFO: [APUAPC] D4_APC_3: 0x0
9984 09:25:38.897689 INFO: [APUAPC] D5_APC_0: 0xffffffff
9985 09:25:38.901576 INFO: [APUAPC] D5_APC_1: 0xffffffff
9986 09:25:38.904431 INFO: [APUAPC] D5_APC_2: 0x3fffff
9987 09:25:38.908035 INFO: [APUAPC] D5_APC_3: 0x0
9988 09:25:38.911196 INFO: [APUAPC] D6_APC_0: 0xffffffff
9989 09:25:38.914292 INFO: [APUAPC] D6_APC_1: 0xffffffff
9990 09:25:38.917613 INFO: [APUAPC] D6_APC_2: 0x3fffff
9991 09:25:38.921147 INFO: [APUAPC] D6_APC_3: 0x0
9992 09:25:38.924034 INFO: [APUAPC] D7_APC_0: 0xffffffff
9993 09:25:38.927359 INFO: [APUAPC] D7_APC_1: 0xffffffff
9994 09:25:38.930992 INFO: [APUAPC] D7_APC_2: 0x3fffff
9995 09:25:38.934475 INFO: [APUAPC] D7_APC_3: 0x0
9996 09:25:38.937283 INFO: [APUAPC] D8_APC_0: 0xffffffff
9997 09:25:38.940970 INFO: [APUAPC] D8_APC_1: 0xffffffff
9998 09:25:38.944210 INFO: [APUAPC] D8_APC_2: 0x3fffff
9999 09:25:38.947276 INFO: [APUAPC] D8_APC_3: 0x0
10000 09:25:38.950773 INFO: [APUAPC] D9_APC_0: 0xffffffff
10001 09:25:38.953655 INFO: [APUAPC] D9_APC_1: 0xffffffff
10002 09:25:38.956858 INFO: [APUAPC] D9_APC_2: 0x3fffff
10003 09:25:38.960674 INFO: [APUAPC] D9_APC_3: 0x0
10004 09:25:38.963923 INFO: [APUAPC] D10_APC_0: 0xffffffff
10005 09:25:38.966978 INFO: [APUAPC] D10_APC_1: 0xffffffff
10006 09:25:38.970638 INFO: [APUAPC] D10_APC_2: 0x3fffff
10007 09:25:38.973647 INFO: [APUAPC] D10_APC_3: 0x0
10008 09:25:38.977538 INFO: [APUAPC] D11_APC_0: 0xffffffff
10009 09:25:38.980372 INFO: [APUAPC] D11_APC_1: 0xffffffff
10010 09:25:38.983565 INFO: [APUAPC] D11_APC_2: 0x3fffff
10011 09:25:38.986933 INFO: [APUAPC] D11_APC_3: 0x0
10012 09:25:38.990608 INFO: [APUAPC] D12_APC_0: 0xffffffff
10013 09:25:38.993576 INFO: [APUAPC] D12_APC_1: 0xffffffff
10014 09:25:38.997439 INFO: [APUAPC] D12_APC_2: 0x3fffff
10015 09:25:38.999780 INFO: [APUAPC] D12_APC_3: 0x0
10016 09:25:39.003183 INFO: [APUAPC] D13_APC_0: 0xffffffff
10017 09:25:39.006908 INFO: [APUAPC] D13_APC_1: 0xffffffff
10018 09:25:39.010086 INFO: [APUAPC] D13_APC_2: 0x3fffff
10019 09:25:39.012977 INFO: [APUAPC] D13_APC_3: 0x0
10020 09:25:39.016537 INFO: [APUAPC] D14_APC_0: 0xffffffff
10021 09:25:39.019599 INFO: [APUAPC] D14_APC_1: 0xffffffff
10022 09:25:39.023465 INFO: [APUAPC] D14_APC_2: 0x3fffff
10023 09:25:39.026359 INFO: [APUAPC] D14_APC_3: 0x0
10024 09:25:39.029734 INFO: [APUAPC] D15_APC_0: 0xffffffff
10025 09:25:39.033098 INFO: [APUAPC] D15_APC_1: 0xffffffff
10026 09:25:39.036358 INFO: [APUAPC] D15_APC_2: 0x3fffff
10027 09:25:39.039676 INFO: [APUAPC] D15_APC_3: 0x0
10028 09:25:39.042883 INFO: [APUAPC] APC_CON: 0x4
10029 09:25:39.046521 INFO: [NOCDAPC] D0_APC_0: 0x0
10030 09:25:39.049839 INFO: [NOCDAPC] D0_APC_1: 0x0
10031 09:25:39.052698 INFO: [NOCDAPC] D1_APC_0: 0x0
10032 09:25:39.056386 INFO: [NOCDAPC] D1_APC_1: 0xfff
10033 09:25:39.059819 INFO: [NOCDAPC] D2_APC_0: 0x0
10034 09:25:39.060239 INFO: [NOCDAPC] D2_APC_1: 0xfff
10035 09:25:39.062531 INFO: [NOCDAPC] D3_APC_0: 0x0
10036 09:25:39.065912 INFO: [NOCDAPC] D3_APC_1: 0xfff
10037 09:25:39.069331 INFO: [NOCDAPC] D4_APC_0: 0x0
10038 09:25:39.073039 INFO: [NOCDAPC] D4_APC_1: 0xfff
10039 09:25:39.075906 INFO: [NOCDAPC] D5_APC_0: 0x0
10040 09:25:39.079086 INFO: [NOCDAPC] D5_APC_1: 0xfff
10041 09:25:39.082669 INFO: [NOCDAPC] D6_APC_0: 0x0
10042 09:25:39.085830 INFO: [NOCDAPC] D6_APC_1: 0xfff
10043 09:25:39.089064 INFO: [NOCDAPC] D7_APC_0: 0x0
10044 09:25:39.092278 INFO: [NOCDAPC] D7_APC_1: 0xfff
10045 09:25:39.095776 INFO: [NOCDAPC] D8_APC_0: 0x0
10046 09:25:39.096198 INFO: [NOCDAPC] D8_APC_1: 0xfff
10047 09:25:39.098693 INFO: [NOCDAPC] D9_APC_0: 0x0
10048 09:25:39.102150 INFO: [NOCDAPC] D9_APC_1: 0xfff
10049 09:25:39.105321 INFO: [NOCDAPC] D10_APC_0: 0x0
10050 09:25:39.109071 INFO: [NOCDAPC] D10_APC_1: 0xfff
10051 09:25:39.112320 INFO: [NOCDAPC] D11_APC_0: 0x0
10052 09:25:39.115452 INFO: [NOCDAPC] D11_APC_1: 0xfff
10053 09:25:39.118691 INFO: [NOCDAPC] D12_APC_0: 0x0
10054 09:25:39.122000 INFO: [NOCDAPC] D12_APC_1: 0xfff
10055 09:25:39.125206 INFO: [NOCDAPC] D13_APC_0: 0x0
10056 09:25:39.128298 INFO: [NOCDAPC] D13_APC_1: 0xfff
10057 09:25:39.132190 INFO: [NOCDAPC] D14_APC_0: 0x0
10058 09:25:39.135296 INFO: [NOCDAPC] D14_APC_1: 0xfff
10059 09:25:39.138504 INFO: [NOCDAPC] D15_APC_0: 0x0
10060 09:25:39.142064 INFO: [NOCDAPC] D15_APC_1: 0xfff
10061 09:25:39.142703 INFO: [NOCDAPC] APC_CON: 0x4
10062 09:25:39.145546 INFO: [APUAPC] set_apusys_apc done
10063 09:25:39.148458 INFO: [DEVAPC] devapc_init done
10064 09:25:39.155226 INFO: GICv3 without legacy support detected.
10065 09:25:39.158211 INFO: ARM GICv3 driver initialized in EL3
10066 09:25:39.161876 INFO: Maximum SPI INTID supported: 639
10067 09:25:39.164861 INFO: BL31: Initializing runtime services
10068 09:25:39.171305 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10069 09:25:39.174397 INFO: SPM: enable CPC mode
10070 09:25:39.178084 INFO: mcdi ready for mcusys-off-idle and system suspend
10071 09:25:39.184691 INFO: BL31: Preparing for EL3 exit to normal world
10072 09:25:39.187874 INFO: Entry point address = 0x80000000
10073 09:25:39.188004 INFO: SPSR = 0x8
10074 09:25:39.194732
10075 09:25:39.194868
10076 09:25:39.194945
10077 09:25:39.198320 Starting depthcharge on Spherion...
10078 09:25:39.198443
10079 09:25:39.198546 Wipe memory regions:
10080 09:25:39.198645
10081 09:25:39.199310 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10082 09:25:39.199414 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10083 09:25:39.199509 Setting prompt string to ['asurada:']
10084 09:25:39.199589 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10085 09:25:39.201417 [0x00000040000000, 0x00000054600000)
10086 09:25:39.324269
10087 09:25:39.324560 [0x00000054660000, 0x00000080000000)
10088 09:25:39.584819
10089 09:25:39.585436 [0x000000821a7280, 0x000000ffe64000)
10090 09:25:40.329790
10091 09:25:40.330325 [0x00000100000000, 0x00000240000000)
10092 09:25:42.220065
10093 09:25:42.223141 Initializing XHCI USB controller at 0x11200000.
10094 09:25:43.261863
10095 09:25:43.265021 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10096 09:25:43.265104
10097 09:25:43.265167
10098 09:25:43.265444 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10100 09:25:43.366013 asurada: tftpboot 192.168.201.1 14407593/tftp-deploy-qhfq9a8z/kernel/image.itb 14407593/tftp-deploy-qhfq9a8z/kernel/cmdline
10101 09:25:43.366638 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10102 09:25:43.367041 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10103 09:25:43.371413 tftpboot 192.168.201.1 14407593/tftp-deploy-qhfq9a8z/kernel/image.ittp-deploy-qhfq9a8z/kernel/cmdline
10104 09:25:43.371845
10105 09:25:43.372171 Waiting for link
10106 09:25:43.529843
10107 09:25:43.530560 R8152: Initializing
10108 09:25:43.530912
10109 09:25:43.532757 Version 6 (ocp_data = 5c30)
10110 09:25:43.533169
10111 09:25:43.536555 R8152: Done initializing
10112 09:25:43.536980
10113 09:25:43.537307 Adding net device
10114 09:25:45.567148
10115 09:25:45.567648 done.
10116 09:25:45.567987
10117 09:25:45.568294 MAC: 00:e0:4c:68:02:81
10118 09:25:45.568783
10119 09:25:45.570496 Sending DHCP discover... done.
10120 09:25:45.570911
10121 09:25:45.573794 Waiting for reply... done.
10122 09:25:45.574246
10123 09:25:45.576959 Sending DHCP request... done.
10124 09:25:45.577478
10125 09:25:45.581825 Waiting for reply... done.
10126 09:25:45.582289
10127 09:25:45.582627 My ip is 192.168.201.14
10128 09:25:45.582937
10129 09:25:45.585613 The DHCP server ip is 192.168.201.1
10130 09:25:45.586032
10131 09:25:45.591788 TFTP server IP predefined by user: 192.168.201.1
10132 09:25:45.592211
10133 09:25:45.598447 Bootfile predefined by user: 14407593/tftp-deploy-qhfq9a8z/kernel/image.itb
10134 09:25:45.598862
10135 09:25:45.601593 Sending tftp read request... done.
10136 09:25:45.602010
10137 09:25:45.608442 Waiting for the transfer...
10138 09:25:45.608863
10139 09:25:46.244957 00000000 ################################################################
10140 09:25:46.245480
10141 09:25:46.887900 00080000 ################################################################
10142 09:25:46.888466
10143 09:25:47.535479 00100000 ################################################################
10144 09:25:47.536013
10145 09:25:48.138606 00180000 ################################################################
10146 09:25:48.138758
10147 09:25:48.664430 00200000 ################################################################
10148 09:25:48.664638
10149 09:25:49.188175 00280000 ################################################################
10150 09:25:49.188320
10151 09:25:49.701459 00300000 ################################################################
10152 09:25:49.701599
10153 09:25:50.220916 00380000 ################################################################
10154 09:25:50.221061
10155 09:25:50.734413 00400000 ################################################################
10156 09:25:50.734598
10157 09:25:51.248642 00480000 ################################################################
10158 09:25:51.248788
10159 09:25:51.760788 00500000 ################################################################
10160 09:25:51.760943
10161 09:25:52.281577 00580000 ################################################################
10162 09:25:52.281751
10163 09:25:52.796462 00600000 ################################################################
10164 09:25:52.796670
10165 09:25:53.317825 00680000 ################################################################
10166 09:25:53.317998
10167 09:25:53.849064 00700000 ################################################################
10168 09:25:53.849214
10169 09:25:54.377704 00780000 ################################################################
10170 09:25:54.377848
10171 09:25:54.904880 00800000 ################################################################
10172 09:25:54.905026
10173 09:25:55.433788 00880000 ################################################################
10174 09:25:55.433947
10175 09:25:55.957592 00900000 ################################################################
10176 09:25:55.957745
10177 09:25:56.478219 00980000 ################################################################
10178 09:25:56.478366
10179 09:25:57.004940 00a00000 ################################################################
10180 09:25:57.005110
10181 09:25:57.524968 00a80000 ################################################################
10182 09:25:57.525137
10183 09:25:58.046480 00b00000 ################################################################
10184 09:25:58.046656
10185 09:25:58.567607 00b80000 ################################################################
10186 09:25:58.567778
10187 09:25:59.091683 00c00000 ################################################################
10188 09:25:59.091861
10189 09:25:59.627054 00c80000 ################################################################
10190 09:25:59.627225
10191 09:26:00.149716 00d00000 ################################################################
10192 09:26:00.149890
10193 09:26:00.667980 00d80000 ################################################################
10194 09:26:00.668149
10195 09:26:01.192721 00e00000 ################################################################
10196 09:26:01.192894
10197 09:26:01.714319 00e80000 ################################################################
10198 09:26:01.714485
10199 09:26:02.233368 00f00000 ################################################################
10200 09:26:02.233540
10201 09:26:02.751900 00f80000 ################################################################
10202 09:26:02.752079
10203 09:26:03.269360 01000000 ################################################################
10204 09:26:03.269531
10205 09:26:03.791992 01080000 ################################################################
10206 09:26:03.792168
10207 09:26:04.329721 01100000 ################################################################
10208 09:26:04.329897
10209 09:26:04.859980 01180000 ################################################################
10210 09:26:04.860151
10211 09:26:05.390650 01200000 ################################################################
10212 09:26:05.390792
10213 09:26:05.934414 01280000 ################################################################
10214 09:26:05.934559
10215 09:26:06.480856 01300000 ################################################################
10216 09:26:06.481033
10217 09:26:07.029756 01380000 ################################################################
10218 09:26:07.029921
10219 09:26:07.559580 01400000 ################################################################
10220 09:26:07.559755
10221 09:26:08.087507 01480000 ################################################################
10222 09:26:08.087684
10223 09:26:08.611377 01500000 ################################################################
10224 09:26:08.611555
10225 09:26:09.140018 01580000 ################################################################
10226 09:26:09.140193
10227 09:26:09.666767 01600000 ################################################################
10228 09:26:09.666926
10229 09:26:10.194361 01680000 ################################################################
10230 09:26:10.194497
10231 09:26:10.740317 01700000 ################################################################
10232 09:26:10.740449
10233 09:26:11.281957 01780000 ################################################################
10234 09:26:11.282133
10235 09:26:11.822759 01800000 ################################################################
10236 09:26:11.822906
10237 09:26:12.350348 01880000 ################################################################
10238 09:26:12.350498
10239 09:26:12.881731 01900000 ################################################################
10240 09:26:12.881868
10241 09:26:13.410005 01980000 ################################################################
10242 09:26:13.410182
10243 09:26:13.936122 01a00000 ################################################################
10244 09:26:13.936286
10245 09:26:14.466283 01a80000 ################################################################
10246 09:26:14.466444
10247 09:26:14.993896 01b00000 ################################################################
10248 09:26:14.994053
10249 09:26:15.539992 01b80000 ################################################################
10250 09:26:15.540123
10251 09:26:16.119677 01c00000 ################################################################
10252 09:26:16.120177
10253 09:26:16.725735 01c80000 ################################################################
10254 09:26:16.725878
10255 09:26:17.266638 01d00000 ################################################################
10256 09:26:17.266782
10257 09:26:17.809378 01d80000 ################################################################
10258 09:26:17.809513
10259 09:26:18.340947 01e00000 ################################################################
10260 09:26:18.341109
10261 09:26:18.868175 01e80000 ################################################################
10262 09:26:18.868311
10263 09:26:19.404681 01f00000 ################################################################
10264 09:26:19.404838
10265 09:26:19.935274 01f80000 ################################################################
10266 09:26:19.935410
10267 09:26:20.469242 02000000 ################################################################
10268 09:26:20.469409
10269 09:26:20.956810 02080000 ########################################################### done.
10270 09:26:20.956946
10271 09:26:20.960552 The bootfile was 34558934 bytes long.
10272 09:26:20.960639
10273 09:26:20.963833 Sending tftp read request... done.
10274 09:26:20.963962
10275 09:26:20.964030 Waiting for the transfer...
10276 09:26:20.964092
10277 09:26:20.966725 00000000 # done.
10278 09:26:20.966809
10279 09:26:20.973444 Command line loaded dynamically from TFTP file: 14407593/tftp-deploy-qhfq9a8z/kernel/cmdline
10280 09:26:20.973527
10281 09:26:20.986708 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10282 09:26:20.986795
10283 09:26:20.990053 Loading FIT.
10284 09:26:20.990134
10285 09:26:20.993371 Image ramdisk-1 has 21382913 bytes.
10286 09:26:20.993452
10287 09:26:20.996683 Image fdt-1 has 47258 bytes.
10288 09:26:20.996764
10289 09:26:20.996829 Image kernel-1 has 13126726 bytes.
10290 09:26:21.000052
10291 09:26:21.006850 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10292 09:26:21.006933
10293 09:26:21.026320 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10294 09:26:21.026407
10295 09:26:21.030007 Choosing best match conf-1 for compat google,spherion-rev2.
10296 09:26:21.034414
10297 09:26:21.038072 Connected to device vid:did:rid of 1ae0:0028:00
10298 09:26:21.045380
10299 09:26:21.049004 tpm_get_response: command 0x17b, return code 0x0
10300 09:26:21.049086
10301 09:26:21.052062 ec_init: CrosEC protocol v3 supported (256, 248)
10302 09:26:21.056603
10303 09:26:21.059446 tpm_cleanup: add release locality here.
10304 09:26:21.059527
10305 09:26:21.059592 Shutting down all USB controllers.
10306 09:26:21.062841
10307 09:26:21.062922 Removing current net device
10308 09:26:21.062987
10309 09:26:21.069489 Exiting depthcharge with code 4 at timestamp: 71334795
10310 09:26:21.069571
10311 09:26:21.072726 LZMA decompressing kernel-1 to 0x821a6718
10312 09:26:21.072808
10313 09:26:21.075656 LZMA decompressing kernel-1 to 0x40000000
10314 09:26:22.693981
10315 09:26:22.694156 jumping to kernel
10316 09:26:22.694787 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10317 09:26:22.694919 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10318 09:26:22.695025 Setting prompt string to ['Linux version [0-9]']
10319 09:26:22.695122 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10320 09:26:22.695227 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10321 09:26:22.775832
10322 09:26:22.779484 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10323 09:26:22.782772 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10324 09:26:22.782896 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10325 09:26:22.782975 Setting prompt string to []
10326 09:26:22.783056 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10327 09:26:22.783152 Using line separator: #'\n'#
10328 09:26:22.783238 No login prompt set.
10329 09:26:22.783328 Parsing kernel messages
10330 09:26:22.783411 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10331 09:26:22.783582 [login-action] Waiting for messages, (timeout 00:03:43)
10332 09:26:22.783676 Waiting using forced prompt support (timeout 00:01:51)
10333 09:26:22.802314 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
10334 09:26:22.805319 [ 0.000000] random: crng init done
10335 09:26:22.811953 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10336 09:26:22.815270 [ 0.000000] efi: UEFI not found.
10337 09:26:22.821754 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10338 09:26:22.832228 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10339 09:26:22.838416 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10340 09:26:22.848351 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10341 09:26:22.855177 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10342 09:26:22.861932 [ 0.000000] printk: bootconsole [mtk8250] enabled
10343 09:26:22.868081 [ 0.000000] NUMA: No NUMA configuration found
10344 09:26:22.875203 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10345 09:26:22.878202 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10346 09:26:22.881345 [ 0.000000] Zone ranges:
10347 09:26:22.888114 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10348 09:26:22.891250 [ 0.000000] DMA32 empty
10349 09:26:22.898043 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10350 09:26:22.901149 [ 0.000000] Movable zone start for each node
10351 09:26:22.904817 [ 0.000000] Early memory node ranges
10352 09:26:22.910863 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10353 09:26:22.917973 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10354 09:26:22.924087 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10355 09:26:22.930914 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10356 09:26:22.937682 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10357 09:26:22.944091 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10358 09:26:23.000312 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10359 09:26:23.007175 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10360 09:26:23.013679 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10361 09:26:23.017270 [ 0.000000] psci: probing for conduit method from DT.
10362 09:26:23.023622 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10363 09:26:23.027357 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10364 09:26:23.033707 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10365 09:26:23.036607 [ 0.000000] psci: SMC Calling Convention v1.2
10366 09:26:23.043266 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10367 09:26:23.046443 [ 0.000000] Detected VIPT I-cache on CPU0
10368 09:26:23.052973 [ 0.000000] CPU features: detected: GIC system register CPU interface
10369 09:26:23.059951 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10370 09:26:23.066411 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10371 09:26:23.073174 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10372 09:26:23.082993 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10373 09:26:23.089663 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10374 09:26:23.092757 [ 0.000000] alternatives: applying boot alternatives
10375 09:26:23.099745 [ 0.000000] Fallback order for Node 0: 0
10376 09:26:23.105818 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10377 09:26:23.109487 [ 0.000000] Policy zone: Normal
10378 09:26:23.122720 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10379 09:26:23.132564 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10380 09:26:23.145243 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10381 09:26:23.155217 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10382 09:26:23.161218 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10383 09:26:23.164605 <6>[ 0.000000] software IO TLB: area num 8.
10384 09:26:23.221354 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10385 09:26:23.371325 <6>[ 0.000000] Memory: 7943180K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 409588K reserved, 32768K cma-reserved)
10386 09:26:23.377383 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10387 09:26:23.384133 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10388 09:26:23.387723 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10389 09:26:23.393914 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10390 09:26:23.401098 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10391 09:26:23.403999 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10392 09:26:23.413963 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10393 09:26:23.420698 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10394 09:26:23.427299 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10395 09:26:23.433444 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10396 09:26:23.437134 <6>[ 0.000000] GICv3: 608 SPIs implemented
10397 09:26:23.440631 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10398 09:26:23.446803 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10399 09:26:23.450624 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10400 09:26:23.456617 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10401 09:26:23.470044 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10402 09:26:23.483401 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10403 09:26:23.489913 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10404 09:26:23.497608 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10405 09:26:23.511159 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10406 09:26:23.517820 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10407 09:26:23.524001 <6>[ 0.009177] Console: colour dummy device 80x25
10408 09:26:23.534233 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10409 09:26:23.541128 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10410 09:26:23.544005 <6>[ 0.029250] LSM: Security Framework initializing
10411 09:26:23.550704 <6>[ 0.034190] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10412 09:26:23.560530 <6>[ 0.042049] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10413 09:26:23.570186 <6>[ 0.051420] cblist_init_generic: Setting adjustable number of callback queues.
10414 09:26:23.573879 <6>[ 0.058863] cblist_init_generic: Setting shift to 3 and lim to 1.
10415 09:26:23.583531 <6>[ 0.065201] cblist_init_generic: Setting adjustable number of callback queues.
10416 09:26:23.590413 <6>[ 0.072675] cblist_init_generic: Setting shift to 3 and lim to 1.
10417 09:26:23.593371 <6>[ 0.079115] rcu: Hierarchical SRCU implementation.
10418 09:26:23.600177 <6>[ 0.084130] rcu: Max phase no-delay instances is 1000.
10419 09:26:23.606826 <6>[ 0.091151] EFI services will not be available.
10420 09:26:23.609804 <6>[ 0.096110] smp: Bringing up secondary CPUs ...
10421 09:26:23.618373 <6>[ 0.101188] Detected VIPT I-cache on CPU1
10422 09:26:23.625282 <6>[ 0.101261] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10423 09:26:23.631528 <6>[ 0.101293] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10424 09:26:23.635130 <6>[ 0.101630] Detected VIPT I-cache on CPU2
10425 09:26:23.644877 <6>[ 0.101684] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10426 09:26:23.651541 <6>[ 0.101701] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10427 09:26:23.654613 <6>[ 0.101960] Detected VIPT I-cache on CPU3
10428 09:26:23.661452 <6>[ 0.102009] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10429 09:26:23.668108 <6>[ 0.102023] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10430 09:26:23.674157 <6>[ 0.102324] CPU features: detected: Spectre-v4
10431 09:26:23.677944 <6>[ 0.102330] CPU features: detected: Spectre-BHB
10432 09:26:23.681098 <6>[ 0.102335] Detected PIPT I-cache on CPU4
10433 09:26:23.687774 <6>[ 0.102394] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10434 09:26:23.694412 <6>[ 0.102410] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10435 09:26:23.700817 <6>[ 0.102705] Detected PIPT I-cache on CPU5
10436 09:26:23.707549 <6>[ 0.102768] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10437 09:26:23.714090 <6>[ 0.102784] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10438 09:26:23.717277 <6>[ 0.103065] Detected PIPT I-cache on CPU6
10439 09:26:23.726843 <6>[ 0.103133] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10440 09:26:23.733568 <6>[ 0.103148] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10441 09:26:23.737288 <6>[ 0.103447] Detected PIPT I-cache on CPU7
10442 09:26:23.743779 <6>[ 0.103512] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10443 09:26:23.750304 <6>[ 0.103528] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10444 09:26:23.753422 <6>[ 0.103575] smp: Brought up 1 node, 8 CPUs
10445 09:26:23.760183 <6>[ 0.244881] SMP: Total of 8 processors activated.
10446 09:26:23.766474 <6>[ 0.249802] CPU features: detected: 32-bit EL0 Support
10447 09:26:23.773192 <6>[ 0.255166] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10448 09:26:23.780029 <6>[ 0.264021] CPU features: detected: Common not Private translations
10449 09:26:23.786195 <6>[ 0.270537] CPU features: detected: CRC32 instructions
10450 09:26:23.793172 <6>[ 0.275921] CPU features: detected: RCpc load-acquire (LDAPR)
10451 09:26:23.796425 <6>[ 0.281882] CPU features: detected: LSE atomic instructions
10452 09:26:23.802724 <6>[ 0.287663] CPU features: detected: Privileged Access Never
10453 09:26:23.809673 <6>[ 0.293478] CPU features: detected: RAS Extension Support
10454 09:26:23.816306 <6>[ 0.299087] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10455 09:26:23.819249 <6>[ 0.306306] CPU: All CPU(s) started at EL2
10456 09:26:23.826040 <6>[ 0.310623] alternatives: applying system-wide alternatives
10457 09:26:23.836415 <6>[ 0.321409] devtmpfs: initialized
10458 09:26:23.851738 <6>[ 0.330227] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10459 09:26:23.858506 <6>[ 0.340187] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10460 09:26:23.865022 <6>[ 0.348207] pinctrl core: initialized pinctrl subsystem
10461 09:26:23.868151 <6>[ 0.354888] DMI not present or invalid.
10462 09:26:23.874731 <6>[ 0.359300] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10463 09:26:23.884604 <6>[ 0.366162] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10464 09:26:23.891732 <6>[ 0.373753] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10465 09:26:23.901068 <6>[ 0.381975] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10466 09:26:23.904204 <6>[ 0.390219] audit: initializing netlink subsys (disabled)
10467 09:26:23.914596 <5>[ 0.395912] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10468 09:26:23.920851 <6>[ 0.396627] thermal_sys: Registered thermal governor 'step_wise'
10469 09:26:23.927666 <6>[ 0.403879] thermal_sys: Registered thermal governor 'power_allocator'
10470 09:26:23.930841 <6>[ 0.410134] cpuidle: using governor menu
10471 09:26:23.937636 <6>[ 0.421095] NET: Registered PF_QIPCRTR protocol family
10472 09:26:23.943789 <6>[ 0.426572] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10473 09:26:23.950628 <6>[ 0.433674] ASID allocator initialised with 32768 entries
10474 09:26:23.953654 <6>[ 0.440248] Serial: AMBA PL011 UART driver
10475 09:26:23.963618 <4>[ 0.449080] Trying to register duplicate clock ID: 134
10476 09:26:24.022013 <6>[ 0.510407] KASLR enabled
10477 09:26:24.036528 <6>[ 0.518057] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10478 09:26:24.042626 <6>[ 0.525070] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10479 09:26:24.049353 <6>[ 0.531557] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10480 09:26:24.056131 <6>[ 0.538565] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10481 09:26:24.062834 <6>[ 0.545053] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10482 09:26:24.069603 <6>[ 0.552057] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10483 09:26:24.075964 <6>[ 0.558545] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10484 09:26:24.082171 <6>[ 0.565549] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10485 09:26:24.085822 <6>[ 0.573009] ACPI: Interpreter disabled.
10486 09:26:24.094343 <6>[ 0.579451] iommu: Default domain type: Translated
10487 09:26:24.101208 <6>[ 0.584565] iommu: DMA domain TLB invalidation policy: strict mode
10488 09:26:24.104314 <5>[ 0.591228] SCSI subsystem initialized
10489 09:26:24.110934 <6>[ 0.595475] usbcore: registered new interface driver usbfs
10490 09:26:24.117789 <6>[ 0.601207] usbcore: registered new interface driver hub
10491 09:26:24.120759 <6>[ 0.606759] usbcore: registered new device driver usb
10492 09:26:24.127834 <6>[ 0.612874] pps_core: LinuxPPS API ver. 1 registered
10493 09:26:24.137534 <6>[ 0.618066] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10494 09:26:24.141080 <6>[ 0.627409] PTP clock support registered
10495 09:26:24.144397 <6>[ 0.631653] EDAC MC: Ver: 3.0.0
10496 09:26:24.151996 <6>[ 0.636818] FPGA manager framework
10497 09:26:24.158097 <6>[ 0.640495] Advanced Linux Sound Architecture Driver Initialized.
10498 09:26:24.161257 <6>[ 0.647270] vgaarb: loaded
10499 09:26:24.167807 <6>[ 0.650416] clocksource: Switched to clocksource arch_sys_counter
10500 09:26:24.171507 <5>[ 0.656862] VFS: Disk quotas dquot_6.6.0
10501 09:26:24.177688 <6>[ 0.661050] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10502 09:26:24.181325 <6>[ 0.668241] pnp: PnP ACPI: disabled
10503 09:26:24.189875 <6>[ 0.674956] NET: Registered PF_INET protocol family
10504 09:26:24.199598 <6>[ 0.680548] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10505 09:26:24.210958 <6>[ 0.692875] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10506 09:26:24.220963 <6>[ 0.701689] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10507 09:26:24.227327 <6>[ 0.709657] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10508 09:26:24.237208 <6>[ 0.718357] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10509 09:26:24.243968 <6>[ 0.728109] TCP: Hash tables configured (established 65536 bind 65536)
10510 09:26:24.250640 <6>[ 0.734979] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10511 09:26:24.260398 <6>[ 0.742178] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10512 09:26:24.267298 <6>[ 0.749885] NET: Registered PF_UNIX/PF_LOCAL protocol family
10513 09:26:24.273398 <6>[ 0.756029] RPC: Registered named UNIX socket transport module.
10514 09:26:24.277132 <6>[ 0.762182] RPC: Registered udp transport module.
10515 09:26:24.283333 <6>[ 0.767114] RPC: Registered tcp transport module.
10516 09:26:24.289976 <6>[ 0.772047] RPC: Registered tcp NFSv4.1 backchannel transport module.
10517 09:26:24.293554 <6>[ 0.778715] PCI: CLS 0 bytes, default 64
10518 09:26:24.296428 <6>[ 0.783045] Unpacking initramfs...
10519 09:26:24.312897 <6>[ 0.794931] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10520 09:26:24.323267 <6>[ 0.803568] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10521 09:26:24.326341 <6>[ 0.812393] kvm [1]: IPA Size Limit: 40 bits
10522 09:26:24.333097 <6>[ 0.816925] kvm [1]: GICv3: no GICV resource entry
10523 09:26:24.336037 <6>[ 0.821949] kvm [1]: disabling GICv2 emulation
10524 09:26:24.342891 <6>[ 0.826634] kvm [1]: GIC system register CPU interface enabled
10525 09:26:24.349520 <6>[ 0.834459] kvm [1]: vgic interrupt IRQ18
10526 09:26:24.352636 <6>[ 0.838843] kvm [1]: VHE mode initialized successfully
10527 09:26:24.359946 <5>[ 0.845286] Initialise system trusted keyrings
10528 09:26:24.366543 <6>[ 0.850085] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10529 09:26:24.375130 <6>[ 0.860208] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10530 09:26:24.381895 <5>[ 0.866645] NFS: Registering the id_resolver key type
10531 09:26:24.385011 <5>[ 0.871949] Key type id_resolver registered
10532 09:26:24.391857 <5>[ 0.876365] Key type id_legacy registered
10533 09:26:24.398293 <6>[ 0.880644] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10534 09:26:24.404884 <6>[ 0.887565] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10535 09:26:24.411779 <6>[ 0.895276] 9p: Installing v9fs 9p2000 file system support
10536 09:26:24.448974 <5>[ 0.934142] Key type asymmetric registered
10537 09:26:24.452616 <5>[ 0.938472] Asymmetric key parser 'x509' registered
10538 09:26:24.462377 <6>[ 0.943608] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10539 09:26:24.465296 <6>[ 0.951225] io scheduler mq-deadline registered
10540 09:26:24.468728 <6>[ 0.955988] io scheduler kyber registered
10541 09:26:24.487648 <6>[ 0.973075] EINJ: ACPI disabled.
10542 09:26:24.520605 <4>[ 0.999281] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10543 09:26:24.530887 <4>[ 1.009891] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10544 09:26:24.545677 <6>[ 1.030772] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10545 09:26:24.553792 <6>[ 1.038712] printk: console [ttyS0] disabled
10546 09:26:24.581387 <6>[ 1.063335] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10547 09:26:24.588169 <6>[ 1.072806] printk: console [ttyS0] enabled
10548 09:26:24.591439 <6>[ 1.072806] printk: console [ttyS0] enabled
10549 09:26:24.598100 <6>[ 1.081703] printk: bootconsole [mtk8250] disabled
10550 09:26:24.601249 <6>[ 1.081703] printk: bootconsole [mtk8250] disabled
10551 09:26:24.608145 <6>[ 1.092705] SuperH (H)SCI(F) driver initialized
10552 09:26:24.611080 <6>[ 1.097977] msm_serial: driver initialized
10553 09:26:24.624937 <6>[ 1.106842] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10554 09:26:24.634812 <6>[ 1.115385] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10555 09:26:24.641668 <6>[ 1.123926] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10556 09:26:24.651621 <6>[ 1.132554] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10557 09:26:24.661556 <6>[ 1.141260] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10558 09:26:24.668111 <6>[ 1.149978] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10559 09:26:24.677906 <6>[ 1.158519] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10560 09:26:24.684395 <6>[ 1.167312] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10561 09:26:24.694219 <6>[ 1.175854] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10562 09:26:24.706424 <6>[ 1.191310] loop: module loaded
10563 09:26:24.712608 <6>[ 1.197190] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10564 09:26:24.735570 <4>[ 1.220498] mtk-pmic-keys: Failed to locate of_node [id: -1]
10565 09:26:24.742156 <6>[ 1.227278] megasas: 07.719.03.00-rc1
10566 09:26:24.751794 <6>[ 1.236930] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10567 09:26:24.761165 <6>[ 1.245806] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10568 09:26:24.777402 <6>[ 1.261992] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10569 09:26:24.836632 <6>[ 1.315087] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10570 09:26:25.196292 <6>[ 1.681192] Freeing initrd memory: 20876K
10571 09:26:25.211938 <6>[ 1.697093] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10572 09:26:25.223328 <6>[ 1.708256] tun: Universal TUN/TAP device driver, 1.6
10573 09:26:25.226374 <6>[ 1.714327] thunder_xcv, ver 1.0
10574 09:26:25.229833 <6>[ 1.717831] thunder_bgx, ver 1.0
10575 09:26:25.232905 <6>[ 1.721328] nicpf, ver 1.0
10576 09:26:25.243319 <6>[ 1.725356] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10577 09:26:25.246771 <6>[ 1.732832] hns3: Copyright (c) 2017 Huawei Corporation.
10578 09:26:25.253343 <6>[ 1.738424] hclge is initializing
10579 09:26:25.256669 <6>[ 1.742003] e1000: Intel(R) PRO/1000 Network Driver
10580 09:26:25.263435 <6>[ 1.747133] e1000: Copyright (c) 1999-2006 Intel Corporation.
10581 09:26:25.266913 <6>[ 1.753150] e1000e: Intel(R) PRO/1000 Network Driver
10582 09:26:25.273325 <6>[ 1.758366] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10583 09:26:25.279973 <6>[ 1.764552] igb: Intel(R) Gigabit Ethernet Network Driver
10584 09:26:25.286604 <6>[ 1.770202] igb: Copyright (c) 2007-2014 Intel Corporation.
10585 09:26:25.293140 <6>[ 1.776038] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10586 09:26:25.299993 <6>[ 1.782556] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10587 09:26:25.303067 <6>[ 1.789020] sky2: driver version 1.30
10588 09:26:25.309945 <6>[ 1.793936] usbcore: registered new device driver r8152-cfgselector
10589 09:26:25.316582 <6>[ 1.800470] usbcore: registered new interface driver r8152
10590 09:26:25.323069 <6>[ 1.806288] VFIO - User Level meta-driver version: 0.3
10591 09:26:25.329585 <6>[ 1.814539] usbcore: registered new interface driver usb-storage
10592 09:26:25.336133 <6>[ 1.820985] usbcore: registered new device driver onboard-usb-hub
10593 09:26:25.345335 <6>[ 1.830149] mt6397-rtc mt6359-rtc: registered as rtc0
10594 09:26:25.354992 <6>[ 1.835616] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-18T09:26:24 UTC (1718702784)
10595 09:26:25.358537 <6>[ 1.845181] i2c_dev: i2c /dev entries driver
10596 09:26:25.372188 <4>[ 1.857221] cpu cpu0: supply cpu not found, using dummy regulator
10597 09:26:25.378776 <4>[ 1.863646] cpu cpu1: supply cpu not found, using dummy regulator
10598 09:26:25.385354 <4>[ 1.870069] cpu cpu2: supply cpu not found, using dummy regulator
10599 09:26:25.392127 <4>[ 1.876471] cpu cpu3: supply cpu not found, using dummy regulator
10600 09:26:25.398784 <4>[ 1.882867] cpu cpu4: supply cpu not found, using dummy regulator
10601 09:26:25.404940 <4>[ 1.889266] cpu cpu5: supply cpu not found, using dummy regulator
10602 09:26:25.411870 <4>[ 1.895665] cpu cpu6: supply cpu not found, using dummy regulator
10603 09:26:25.418125 <4>[ 1.902073] cpu cpu7: supply cpu not found, using dummy regulator
10604 09:26:25.437431 <6>[ 1.922714] cpu cpu0: EM: created perf domain
10605 09:26:25.440875 <6>[ 1.927620] cpu cpu4: EM: created perf domain
10606 09:26:25.448130 <6>[ 1.933235] sdhci: Secure Digital Host Controller Interface driver
10607 09:26:25.454969 <6>[ 1.939666] sdhci: Copyright(c) Pierre Ossman
10608 09:26:25.461240 <6>[ 1.944623] Synopsys Designware Multimedia Card Interface Driver
10609 09:26:25.467989 <6>[ 1.951263] sdhci-pltfm: SDHCI platform and OF driver helper
10610 09:26:25.471237 <6>[ 1.951333] mmc0: CQHCI version 5.10
10611 09:26:25.477907 <6>[ 1.961233] ledtrig-cpu: registered to indicate activity on CPUs
10612 09:26:25.484387 <6>[ 1.968128] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10613 09:26:25.491347 <6>[ 1.975171] usbcore: registered new interface driver usbhid
10614 09:26:25.494348 <6>[ 1.980993] usbhid: USB HID core driver
10615 09:26:25.500983 <6>[ 1.985190] spi_master spi0: will run message pump with realtime priority
10616 09:26:25.549965 <6>[ 2.028558] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10617 09:26:25.569979 <6>[ 2.044610] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10618 09:26:25.573077 <6>[ 2.056770] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16414
10619 09:26:25.580418 <6>[ 2.060176] cros-ec-spi spi0.0: Chrome EC device registered
10620 09:26:25.583331 <6>[ 2.069993] mmc0: Command Queue Engine enabled
10621 09:26:25.589887 <6>[ 2.074754] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10622 09:26:25.596547 <6>[ 2.081970] mmcblk0: mmc0:0001 DA4128 116 GiB
10623 09:26:25.606733 <6>[ 2.085416] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10624 09:26:25.613203 <6>[ 2.090320] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10625 09:26:25.616905 <6>[ 2.097257] NET: Registered PF_PACKET protocol family
10626 09:26:25.623107 <6>[ 2.103156] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10627 09:26:25.626803 <6>[ 2.107289] 9pnet: Installing 9P2000 support
10628 09:26:25.633173 <6>[ 2.113048] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10629 09:26:25.636228 <5>[ 2.116982] Key type dns_resolver registered
10630 09:26:25.643301 <6>[ 2.122814] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10631 09:26:25.646328 <6>[ 2.127230] registered taskstats version 1
10632 09:26:25.652866 <5>[ 2.137579] Loading compiled-in X.509 certificates
10633 09:26:25.680596 <4>[ 2.159324] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10634 09:26:25.690662 <4>[ 2.170029] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10635 09:26:25.704461 <6>[ 2.189857] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10636 09:26:25.711647 <6>[ 2.196667] xhci-mtk 11200000.usb: xHCI Host Controller
10637 09:26:25.718114 <6>[ 2.202172] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10638 09:26:25.728088 <6>[ 2.210027] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10639 09:26:25.734739 <6>[ 2.219456] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10640 09:26:25.741604 <6>[ 2.225544] xhci-mtk 11200000.usb: xHCI Host Controller
10641 09:26:25.747871 <6>[ 2.231124] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10642 09:26:25.754265 <6>[ 2.238794] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10643 09:26:25.761317 <6>[ 2.246729] hub 1-0:1.0: USB hub found
10644 09:26:25.764682 <6>[ 2.250778] hub 1-0:1.0: 1 port detected
10645 09:26:25.774852 <6>[ 2.255083] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10646 09:26:25.778380 <6>[ 2.263862] hub 2-0:1.0: USB hub found
10647 09:26:25.781416 <6>[ 2.267887] hub 2-0:1.0: 1 port detected
10648 09:26:25.790592 <6>[ 2.275977] mtk-msdc 11f70000.mmc: Got CD GPIO
10649 09:26:25.809669 <6>[ 2.291238] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10650 09:26:25.819212 <6>[ 2.299616] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10651 09:26:25.826070 <6>[ 2.307957] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10652 09:26:25.835942 <6>[ 2.316296] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10653 09:26:25.842672 <6>[ 2.324638] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10654 09:26:25.852611 <6>[ 2.332975] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10655 09:26:25.858848 <6>[ 2.341314] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10656 09:26:25.868655 <6>[ 2.349652] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10657 09:26:25.875316 <6>[ 2.357990] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10658 09:26:25.885404 <6>[ 2.366327] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10659 09:26:25.892072 <6>[ 2.374675] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10660 09:26:25.902115 <6>[ 2.383013] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10661 09:26:25.908531 <6>[ 2.391351] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10662 09:26:25.918403 <6>[ 2.399689] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10663 09:26:25.925078 <6>[ 2.408027] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10664 09:26:25.931688 <6>[ 2.416733] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10665 09:26:25.938493 <6>[ 2.423891] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10666 09:26:25.945320 <6>[ 2.430695] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10667 09:26:25.955641 <6>[ 2.437459] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10668 09:26:25.961718 <6>[ 2.444386] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10669 09:26:25.968698 <6>[ 2.451243] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10670 09:26:25.978174 <6>[ 2.460374] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10671 09:26:25.988068 <6>[ 2.469496] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10672 09:26:25.998350 <6>[ 2.478789] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10673 09:26:26.008028 <6>[ 2.488257] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10674 09:26:26.018157 <6>[ 2.497724] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10675 09:26:26.024317 <6>[ 2.506857] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10676 09:26:26.034297 <6>[ 2.516323] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10677 09:26:26.044838 <6>[ 2.525450] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10678 09:26:26.054411 <6>[ 2.534744] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10679 09:26:26.063954 <6>[ 2.544905] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10680 09:26:26.075245 <6>[ 2.556964] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10681 09:26:26.172749 <6>[ 2.655003] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10682 09:26:26.200690 <6>[ 2.685681] hub 2-1:1.0: USB hub found
10683 09:26:26.203806 <6>[ 2.690124] hub 2-1:1.0: 3 ports detected
10684 09:26:26.213105 <6>[ 2.698206] hub 2-1:1.0: USB hub found
10685 09:26:26.216241 <6>[ 2.702638] hub 2-1:1.0: 3 ports detected
10686 09:26:26.324804 <6>[ 2.806694] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10687 09:26:26.480009 <6>[ 2.964842] hub 1-1:1.0: USB hub found
10688 09:26:26.482985 <6>[ 2.969335] hub 1-1:1.0: 4 ports detected
10689 09:26:26.495355 <6>[ 2.980742] hub 1-1:1.0: USB hub found
10690 09:26:26.498965 <6>[ 2.985191] hub 1-1:1.0: 4 ports detected
10691 09:26:26.556705 <6>[ 3.038799] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10692 09:26:26.665226 <6>[ 3.147109] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10693 09:26:26.697802 <4>[ 3.179471] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10694 09:26:26.707314 <4>[ 3.188621] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10695 09:26:26.742037 <6>[ 3.227235] r8152 2-1.3:1.0 eth0: v1.12.13
10696 09:26:26.820604 <6>[ 3.302667] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10697 09:26:26.953113 <6>[ 3.438341] hub 1-1.4:1.0: USB hub found
10698 09:26:26.956432 <6>[ 3.443010] hub 1-1.4:1.0: 2 ports detected
10699 09:26:26.968550 <6>[ 3.453761] hub 1-1.4:1.0: USB hub found
10700 09:26:26.971778 <6>[ 3.458263] hub 1-1.4:1.0: 2 ports detected
10701 09:26:27.268795 <6>[ 3.750765] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10702 09:26:27.464401 <6>[ 3.946632] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10703 09:26:28.482836 <6>[ 4.968695] r8152 2-1.3:1.0 eth0: carrier on
10704 09:26:30.716959 <5>[ 4.994526] Sending DHCP requests .., OK
10705 09:26:30.723116 <6>[ 7.206864] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10706 09:26:30.726846 <6>[ 7.215167] IP-Config: Complete:
10707 09:26:30.739804 <6>[ 7.218663] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10708 09:26:30.746532 <6>[ 7.229371] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10709 09:26:30.753337 <6>[ 7.237987] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10710 09:26:30.759475 <6>[ 7.237997] nameserver0=192.168.201.1
10711 09:26:30.762885 <6>[ 7.250171] clk: Disabling unused clocks
10712 09:26:30.766703 <6>[ 7.255728] ALSA device list:
10713 09:26:30.773109 <6>[ 7.259002] No soundcards found.
10714 09:26:30.780358 <6>[ 7.266249] Freeing unused kernel memory: 8512K
10715 09:26:30.783952 <6>[ 7.271193] Run /init as init process
10716 09:26:30.808453 Starting syslogd: OK
10717 09:26:30.815868 Starting klogd: OK
10718 09:26:30.822968 Running sysctl: OK
10719 09:26:30.832696 Populating /dev using udev: <30>[ 7.317368] udevd[189]: starting version 3.2.9
10720 09:26:30.839518 <27>[ 7.325277] udevd[189]: specified user 'tss' unknown
10721 09:26:30.846363 <27>[ 7.330660] udevd[189]: specified group 'tss' unknown
10722 09:26:30.849505 <30>[ 7.337146] udevd[190]: starting eudev-3.2.9
10723 09:26:30.871392 <27>[ 7.357386] udevd[190]: specified user 'tss' unknown
10724 09:26:30.878086 <27>[ 7.362774] udevd[190]: specified group 'tss' unknown
10725 09:26:30.966976 <6>[ 7.449169] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10726 09:26:30.979324 <6>[ 7.461895] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10727 09:26:30.985818 <6>[ 7.469969] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10728 09:26:30.996902 <4>[ 7.479292] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10729 09:26:31.007288 <6>[ 7.489507] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10730 09:26:31.013356 <6>[ 7.490503] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10731 09:26:31.023237 <6>[ 7.497746] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10732 09:26:31.029820 <6>[ 7.507012] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10733 09:26:31.036639 <6>[ 7.517255] remoteproc remoteproc0: scp is available
10734 09:26:31.043644 <6>[ 7.517798] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10735 09:26:31.049803 <6>[ 7.517812] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10736 09:26:31.059886 <6>[ 7.517815] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10737 09:26:31.066444 <6>[ 7.517818] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10738 09:26:31.076298 <4>[ 7.526544] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10739 09:26:31.079870 <6>[ 7.533978] remoteproc remoteproc0: powering up scp
10740 09:26:31.089600 <4>[ 7.542476] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10741 09:26:31.096433 <6>[ 7.545375] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10742 09:26:31.106414 <6>[ 7.545400] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10743 09:26:31.112669 <6>[ 7.545405] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10744 09:26:31.122896 <6>[ 7.549864] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10745 09:26:31.129299 <3>[ 7.549943] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 09:26:31.138953 <3>[ 7.549964] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 09:26:31.145645 <3>[ 7.549971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 09:26:31.155517 <3>[ 7.550074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 09:26:31.162514 <3>[ 7.550078] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 09:26:31.171937 <3>[ 7.550080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 09:26:31.178852 <3>[ 7.550086] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 09:26:31.185100 <3>[ 7.550089] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 09:26:31.195223 <3>[ 7.550125] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 09:26:31.201529 <3>[ 7.550159] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 09:26:31.212349 <3>[ 7.550162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 09:26:31.218968 <3>[ 7.550164] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 09:26:31.229009 <3>[ 7.550183] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 09:26:31.235346 <3>[ 7.550186] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 09:26:31.242083 <3>[ 7.550189] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 09:26:31.251835 <3>[ 7.550192] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 09:26:31.258900 <3>[ 7.550194] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 09:26:31.268863 <3>[ 7.550214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 09:26:31.271889 <6>[ 7.571096] mc: Linux media interface: v0.10
10764 09:26:31.279095 <6>[ 7.571755] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10765 09:26:31.285302 <6>[ 7.667893] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10766 09:26:31.294993 <6>[ 7.680210] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10767 09:26:31.305139 <4>[ 7.684595] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10768 09:26:31.308232 <4>[ 7.684595] Fallback method does not support PEC.
10769 09:26:31.314912 <6>[ 7.685910] pci_bus 0000:00: root bus resource [bus 00-ff]
10770 09:26:31.321426 <6>[ 7.685914] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10771 09:26:31.331554 <6>[ 7.685918] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10772 09:26:31.341585 <6>[ 7.690330] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10773 09:26:31.351141 <6>[ 7.694138] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10774 09:26:31.354754 <6>[ 7.702106] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10775 09:26:31.364799 <3>[ 7.703749] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10776 09:26:31.370974 <6>[ 7.734904] videodev: Linux video capture interface: v2.00
10777 09:26:31.377750 <6>[ 7.742860] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10778 09:26:31.387386 <3>[ 7.759390] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10779 09:26:31.391076 <6>[ 7.763364] pci 0000:00:00.0: supports D1 D2
10780 09:26:31.394224 <6>[ 7.764176] Bluetooth: Core ver 2.22
10781 09:26:31.400761 <6>[ 7.764382] NET: Registered PF_BLUETOOTH protocol family
10782 09:26:31.407235 <6>[ 7.764398] Bluetooth: HCI device and connection manager initialized
10783 09:26:31.414060 <6>[ 7.764451] Bluetooth: HCI socket layer initialized
10784 09:26:31.417239 <6>[ 7.764460] Bluetooth: L2CAP socket layer initialized
10785 09:26:31.423864 <6>[ 7.764499] Bluetooth: SCO socket layer initialized
10786 09:26:31.430489 <6>[ 7.799615] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10787 09:26:31.437062 <6>[ 7.805242] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10788 09:26:31.443814 <6>[ 7.807175] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10789 09:26:31.453658 <6>[ 7.812620] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10790 09:26:31.460230 <6>[ 7.822413] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10791 09:26:31.467045 <6>[ 7.831892] remoteproc remoteproc0: remote processor scp is now up
10792 09:26:31.473218 <6>[ 7.840719] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10793 09:26:31.480025 <6>[ 7.840738] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10794 09:26:31.490043 <6>[ 7.840845] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10795 09:26:31.493131 <6>[ 7.841652] usbcore: registered new interface driver btusb
10796 09:26:31.502967 <4>[ 7.847686] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10797 09:26:31.513032 <6>[ 7.848751] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10798 09:26:31.526379 <6>[ 7.848870] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10799 09:26:31.532540 <6>[ 7.849041] usbcore: registered new interface driver uvcvideo
10800 09:26:31.539683 <6>[ 7.851841] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10801 09:26:31.546078 <6>[ 7.855772] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10802 09:26:31.552817 <6>[ 7.855902] pci 0000:01:00.0: supports D1 D2
10803 09:26:31.558954 <6>[ 7.857070] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10804 09:26:31.565711 <3>[ 7.861562] Bluetooth: hci0: Failed to load firmware file (-2)
10805 09:26:31.572643 <6>[ 7.869009] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10806 09:26:31.578879 <6>[ 7.882543] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10807 09:26:31.582068 <3>[ 7.886148] Bluetooth: hci0: Failed to set up firmware (-2)
10808 09:26:31.592030 <6>[ 7.891732] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10809 09:26:31.601961 <4>[ 7.898380] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10810 09:26:31.608468 <6>[ 7.903439] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10811 09:26:31.618471 <6>[ 7.903450] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10812 09:26:31.625091 <6>[ 7.903462] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10813 09:26:31.634873 <6>[ 7.903476] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10814 09:26:31.638655 <6>[ 7.903491] pci 0000:00:00.0: PCI bridge to [bus 01]
10815 09:26:31.648379 <6>[ 7.903498] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10816 09:26:31.654749 <6>[ 7.903803] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10817 09:26:31.661562 <6>[ 8.145016] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10818 09:26:31.667633 <6>[ 8.151841] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10819 09:26:31.686821 <5>[ 8.169319] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10820 09:26:31.725106 <5>[ 8.207450] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10821 09:26:31.731185 <5>[ 8.215480] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10822 09:26:31.741476 <4>[ 8.223986] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10823 09:26:31.748108 <6>[ 8.232915] cfg80211: failed to load regulatory.db
10824 09:26:31.803288 <6>[ 8.285916] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10825 09:26:31.809990 <6>[ 8.293549] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10826 09:26:31.834315 <6>[ 8.320428] mt7921e 0000:01:00.0: ASIC revision: 79610010
10827 09:26:31.938031 <6>[ 8.420831] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10828 09:26:31.941777 <6>[ 8.420831]
10829 09:26:31.941869 done
10830 09:26:31.951657 Saving random seed: OK
10831 09:26:31.961550 Starting network: ip: RTNETLINK answers: File exists
10832 09:26:31.964544 FAIL
10833 09:26:31.998302 Starting dropbear sshd: <6>[ 8.484428] NET: Registered PF_INET6 protocol family
10834 09:26:32.005085 <6>[ 8.490709] Segment Routing with IPv6
10835 09:26:32.008071 <6>[ 8.494758] In-situ OAM (IOAM) with IPv6
10836 09:26:32.011697 OK
10837 09:26:32.021048 /bin/sh: can't access tty; job control turned off
10838 09:26:32.021391 Matched prompt #10: / #
10840 09:26:32.021611 Setting prompt string to ['/ #']
10841 09:26:32.021711 end: 2.2.5.1 login-action (duration 00:00:09) [common]
10843 09:26:32.021913 end: 2.2.5 auto-login-action (duration 00:00:09) [common]
10844 09:26:32.021999 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10845 09:26:32.022089 Setting prompt string to ['/ #']
10846 09:26:32.022196 Forcing a shell prompt, looking for ['/ #']
10848 09:26:32.072411 / #
10849 09:26:32.072583 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10850 09:26:32.072768 Waiting using forced prompt support (timeout 00:02:30)
10851 09:26:32.077840
10852 09:26:32.078149 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10853 09:26:32.078371 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10854 09:26:32.078503 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10855 09:26:32.078623 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10856 09:26:32.078737 end: 2 depthcharge-action (duration 00:01:26) [common]
10857 09:26:32.078856 start: 3 lava-test-retry (timeout 00:01:00) [common]
10858 09:26:32.078970 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10859 09:26:32.079075 Using namespace: common
10861 09:26:32.179468 / # #
10862 09:26:32.179687 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10863 09:26:32.184362 #
10864 09:26:32.184661 Using /lava-14407593
10866 09:26:32.285002 / # export SHELL=/bin/sh
10867 09:26:32.285213 <6>[ 8.687879] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10868 09:26:32.289900 export SHELL=/bin/sh
10870 09:26:32.390507 / # . /lava-14407593/environment
10871 09:26:32.395492 . /lava-14407593/environment
10873 09:26:32.496083 / # /lava-14407593/bin/lava-test-runner /lava-14407593/0
10874 09:26:32.496230 Test shell timeout: 10s (minimum of the action and connection timeout)
10875 09:26:32.501088 /lava-14407593/bin/lava-test-runner /lava-14407593/0
10876 09:26:32.518631 + export 'TESTRUN_ID=0_dmesg'
10877 09:26:32.525527 + c<8>[ 9.009721] <LAVA_SIGNAL_STARTRUN 0_dmesg 14407593_1.5.2.3.1>
10878 09:26:32.525822 Received signal: <STARTRUN> 0_dmesg 14407593_1.5.2.3.1
10879 09:26:32.525925 Starting test lava.0_dmesg (14407593_1.5.2.3.1)
10880 09:26:32.526039 Skipping test definition patterns.
10881 09:26:32.528581 d /lava-14407593/0/tests/0_dmesg
10882 09:26:32.528663 + cat uuid
10883 09:26:32.531704 + UUID=14407593_1.5.2.3.1
10884 09:26:32.531786 + set +x
10885 09:26:32.538602 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10886 09:26:32.544872 <8>[ 9.028239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10887 09:26:32.545126 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10889 09:26:32.567334 <8>[ 9.049855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10890 09:26:32.567590 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10892 09:26:32.587302 <8>[ 9.069777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10893 09:26:32.587583 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10895 09:26:32.590466 + set +x
10896 09:26:32.593731 <8>[ 9.079437] <LAVA_SIGNAL_ENDRUN 0_dmesg 14407593_1.5.2.3.1>
10897 09:26:32.594051 Received signal: <ENDRUN> 0_dmesg 14407593_1.5.2.3.1
10898 09:26:32.594201 Ending use of test pattern.
10899 09:26:32.594297 Ending test lava.0_dmesg (14407593_1.5.2.3.1), duration 0.07
10901 09:26:32.598095 <LAVA_TEST_RUNNER EXIT>
10902 09:26:32.598415 ok: lava_test_shell seems to have completed
10903 09:26:32.598524 alert: pass
crit: pass
emerg: pass
10904 09:26:32.598614 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10905 09:26:32.598699 end: 3 lava-test-retry (duration 00:00:01) [common]
10906 09:26:32.598785 start: 4 finalize (timeout 00:08:02) [common]
10907 09:26:32.598877 start: 4.1 power-off (timeout 00:00:30) [common]
10908 09:26:32.599029 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
10909 09:26:32.797460 >> Command sent successfully.
10910 09:26:32.799765 Returned 0 in 0 seconds
10911 09:26:32.900311 end: 4.1 power-off (duration 00:00:00) [common]
10913 09:26:32.900747 start: 4.2 read-feedback (timeout 00:08:01) [common]
10914 09:26:32.901048 Listened to connection for namespace 'common' for up to 1s
10915 09:26:33.901975 Finalising connection for namespace 'common'
10916 09:26:33.902197 Disconnecting from shell: Finalise
10917 09:26:33.902340 / #
10918 09:26:34.002694 end: 4.2 read-feedback (duration 00:00:01) [common]
10919 09:26:34.002883 end: 4 finalize (duration 00:00:01) [common]
10920 09:26:34.003028 Cleaning after the job
10921 09:26:34.003159 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/ramdisk
10922 09:26:34.005588 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/kernel
10923 09:26:34.013067 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/dtb
10924 09:26:34.013273 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407593/tftp-deploy-qhfq9a8z/modules
10925 09:26:34.018921 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407593
10926 09:26:34.064269 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407593
10927 09:26:34.064453 Job finished correctly