Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 09:30:46.564635 lava-dispatcher, installed at version: 2024.03
2 09:30:46.564824 start: 0 validate
3 09:30:46.564967 Start time: 2024-06-18 09:30:46.564960+00:00 (UTC)
4 09:30:46.565089 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:30:46.565226 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 09:30:46.835949 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:30:46.836633 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:30:47.090587 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:30:47.090807 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:30:47.342322 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:30:47.342939 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:30:47.603461 validate duration: 1.04
14 09:30:47.604892 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:30:47.605533 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:30:47.606091 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:30:47.606804 Not decompressing ramdisk as can be used compressed.
18 09:30:47.607284 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 09:30:47.607648 saving as /var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/ramdisk/rootfs.cpio.gz
20 09:30:47.608046 total size: 47897469 (45 MB)
21 09:30:47.613741 progress 0 % (0 MB)
22 09:30:47.650857 progress 5 % (2 MB)
23 09:30:47.663462 progress 10 % (4 MB)
24 09:30:47.675757 progress 15 % (6 MB)
25 09:30:47.688276 progress 20 % (9 MB)
26 09:30:47.700409 progress 25 % (11 MB)
27 09:30:47.712755 progress 30 % (13 MB)
28 09:30:47.724966 progress 35 % (16 MB)
29 09:30:47.737072 progress 40 % (18 MB)
30 09:30:47.749287 progress 45 % (20 MB)
31 09:30:47.761687 progress 50 % (22 MB)
32 09:30:47.773945 progress 55 % (25 MB)
33 09:30:47.786461 progress 60 % (27 MB)
34 09:30:47.799661 progress 65 % (29 MB)
35 09:30:47.812448 progress 70 % (32 MB)
36 09:30:47.825291 progress 75 % (34 MB)
37 09:30:47.838392 progress 80 % (36 MB)
38 09:30:47.851486 progress 85 % (38 MB)
39 09:30:47.864503 progress 90 % (41 MB)
40 09:30:47.877751 progress 95 % (43 MB)
41 09:30:47.889862 progress 100 % (45 MB)
42 09:30:47.890086 45 MB downloaded in 0.28 s (161.94 MB/s)
43 09:30:47.890279 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:30:47.890518 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:30:47.890603 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:30:47.890686 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:30:47.890818 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:30:47.890892 saving as /var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/kernel/Image
50 09:30:47.890952 total size: 54813184 (52 MB)
51 09:30:47.891012 No compression specified
52 09:30:47.892113 progress 0 % (0 MB)
53 09:30:47.906933 progress 5 % (2 MB)
54 09:30:47.922319 progress 10 % (5 MB)
55 09:30:47.936536 progress 15 % (7 MB)
56 09:30:47.950509 progress 20 % (10 MB)
57 09:30:47.964901 progress 25 % (13 MB)
58 09:30:47.978819 progress 30 % (15 MB)
59 09:30:47.992755 progress 35 % (18 MB)
60 09:30:48.006690 progress 40 % (20 MB)
61 09:30:48.020590 progress 45 % (23 MB)
62 09:30:48.034675 progress 50 % (26 MB)
63 09:30:48.049152 progress 55 % (28 MB)
64 09:30:48.063152 progress 60 % (31 MB)
65 09:30:48.077695 progress 65 % (34 MB)
66 09:30:48.091746 progress 70 % (36 MB)
67 09:30:48.105949 progress 75 % (39 MB)
68 09:30:48.119962 progress 80 % (41 MB)
69 09:30:48.133787 progress 85 % (44 MB)
70 09:30:48.147809 progress 90 % (47 MB)
71 09:30:48.161943 progress 95 % (49 MB)
72 09:30:48.175744 progress 100 % (52 MB)
73 09:30:48.175989 52 MB downloaded in 0.29 s (183.40 MB/s)
74 09:30:48.176139 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:30:48.176376 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:30:48.176462 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:30:48.176545 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:30:48.176682 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:30:48.176756 saving as /var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/dtb/mt8192-asurada-spherion-r0.dtb
81 09:30:48.176817 total size: 47258 (0 MB)
82 09:30:48.176878 No compression specified
83 09:30:48.178008 progress 69 % (0 MB)
84 09:30:48.178317 progress 100 % (0 MB)
85 09:30:48.178473 0 MB downloaded in 0.00 s (27.26 MB/s)
86 09:30:48.178594 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:30:48.178813 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:30:48.178898 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:30:48.178980 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:30:48.179092 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:30:48.179162 saving as /var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/modules/modules.tar
93 09:30:48.179225 total size: 8619356 (8 MB)
94 09:30:48.179318 Using unxz to decompress xz
95 09:30:48.183441 progress 0 % (0 MB)
96 09:30:48.203027 progress 5 % (0 MB)
97 09:30:48.227735 progress 10 % (0 MB)
98 09:30:48.253409 progress 15 % (1 MB)
99 09:30:48.280161 progress 20 % (1 MB)
100 09:30:48.306136 progress 25 % (2 MB)
101 09:30:48.332253 progress 30 % (2 MB)
102 09:30:48.358778 progress 35 % (2 MB)
103 09:30:48.386324 progress 40 % (3 MB)
104 09:30:48.413168 progress 45 % (3 MB)
105 09:30:48.437949 progress 50 % (4 MB)
106 09:30:48.465195 progress 55 % (4 MB)
107 09:30:48.491243 progress 60 % (4 MB)
108 09:30:48.517001 progress 65 % (5 MB)
109 09:30:48.548915 progress 70 % (5 MB)
110 09:30:48.576327 progress 75 % (6 MB)
111 09:30:48.604620 progress 80 % (6 MB)
112 09:30:48.633047 progress 85 % (7 MB)
113 09:30:48.657851 progress 90 % (7 MB)
114 09:30:48.686920 progress 95 % (7 MB)
115 09:30:48.718011 progress 100 % (8 MB)
116 09:30:48.722699 8 MB downloaded in 0.54 s (15.13 MB/s)
117 09:30:48.722946 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:30:48.723219 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:30:48.723316 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 09:30:48.723409 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 09:30:48.723493 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:30:48.723581 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 09:30:48.723822 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis
125 09:30:48.723958 makedir: /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin
126 09:30:48.724066 makedir: /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/tests
127 09:30:48.724166 makedir: /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/results
128 09:30:48.724286 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-add-keys
129 09:30:48.724434 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-add-sources
130 09:30:48.724575 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-background-process-start
131 09:30:48.724713 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-background-process-stop
132 09:30:48.724841 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-common-functions
133 09:30:48.724968 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-echo-ipv4
134 09:30:48.725096 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-install-packages
135 09:30:48.725222 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-installed-packages
136 09:30:48.725348 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-os-build
137 09:30:48.725477 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-probe-channel
138 09:30:48.725605 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-probe-ip
139 09:30:48.725731 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-target-ip
140 09:30:48.725856 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-target-mac
141 09:30:48.725981 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-target-storage
142 09:30:48.726112 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-test-case
143 09:30:48.726244 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-test-event
144 09:30:48.726369 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-test-feedback
145 09:30:48.726494 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-test-raise
146 09:30:48.726618 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-test-reference
147 09:30:48.726746 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-test-runner
148 09:30:48.726878 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-test-set
149 09:30:48.727014 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-test-shell
150 09:30:48.727146 Updating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-install-packages (oe)
151 09:30:48.727307 Updating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/bin/lava-installed-packages (oe)
152 09:30:48.727430 Creating /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/environment
153 09:30:48.727533 LAVA metadata
154 09:30:48.727608 - LAVA_JOB_ID=14407680
155 09:30:48.727674 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:30:48.727777 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 09:30:48.727846 skipped lava-vland-overlay
158 09:30:48.727922 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:30:48.728007 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 09:30:48.728086 skipped lava-multinode-overlay
161 09:30:48.728162 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:30:48.728248 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 09:30:48.728323 Loading test definitions
164 09:30:48.728416 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 09:30:48.728491 Using /lava-14407680 at stage 0
166 09:30:48.728798 uuid=14407680_1.5.2.3.1 testdef=None
167 09:30:48.728889 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:30:48.728976 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 09:30:48.729572 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:30:48.729801 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 09:30:48.730445 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:30:48.730680 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 09:30:48.731298 runner path: /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/0/tests/0_igt-gpu-panfrost test_uuid 14407680_1.5.2.3.1
176 09:30:48.731476 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:30:48.731707 Creating lava-test-runner.conf files
179 09:30:48.731795 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407680/lava-overlay-g7szeuis/lava-14407680/0 for stage 0
180 09:30:48.731913 - 0_igt-gpu-panfrost
181 09:30:48.732029 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 09:30:48.732128 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 09:30:48.740616 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 09:30:48.740741 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 09:30:48.740846 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 09:30:48.740951 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 09:30:48.741054 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 09:30:50.496052 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 09:30:50.496431 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 09:30:50.496567 extracting modules file /var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407680/extract-overlay-ramdisk-t7anwmo7/ramdisk
191 09:30:50.718895 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 09:30:50.719068 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 09:30:50.719166 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407680/compress-overlay-a_lmnhmt/overlay-1.5.2.4.tar.gz to ramdisk
194 09:30:50.719237 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407680/compress-overlay-a_lmnhmt/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407680/extract-overlay-ramdisk-t7anwmo7/ramdisk
195 09:30:50.725760 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 09:30:50.725874 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 09:30:50.725966 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 09:30:50.726056 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 09:30:50.726133 Building ramdisk /var/lib/lava/dispatcher/tmp/14407680/extract-overlay-ramdisk-t7anwmo7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407680/extract-overlay-ramdisk-t7anwmo7/ramdisk
200 09:30:51.938829 >> 466049 blocks
201 09:30:58.203976 rename /var/lib/lava/dispatcher/tmp/14407680/extract-overlay-ramdisk-t7anwmo7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/ramdisk/ramdisk.cpio.gz
202 09:30:58.204434 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 09:30:58.204564 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 09:30:58.204661 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 09:30:58.204766 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/kernel/Image']
206 09:31:11.510676 Returned 0 in 13 seconds
207 09:31:11.611665 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/kernel/image.itb
208 09:31:12.482663 output: FIT description: Kernel Image image with one or more FDT blobs
209 09:31:12.483039 output: Created: Tue Jun 18 10:31:12 2024
210 09:31:12.483114 output: Image 0 (kernel-1)
211 09:31:12.483179 output: Description:
212 09:31:12.483240 output: Created: Tue Jun 18 10:31:12 2024
213 09:31:12.483301 output: Type: Kernel Image
214 09:31:12.483365 output: Compression: lzma compressed
215 09:31:12.483425 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
216 09:31:12.483485 output: Architecture: AArch64
217 09:31:12.483544 output: OS: Linux
218 09:31:12.483605 output: Load Address: 0x00000000
219 09:31:12.483663 output: Entry Point: 0x00000000
220 09:31:12.483723 output: Hash algo: crc32
221 09:31:12.483781 output: Hash value: 4137a6e7
222 09:31:12.483835 output: Image 1 (fdt-1)
223 09:31:12.483890 output: Description: mt8192-asurada-spherion-r0
224 09:31:12.483946 output: Created: Tue Jun 18 10:31:12 2024
225 09:31:12.484001 output: Type: Flat Device Tree
226 09:31:12.484054 output: Compression: uncompressed
227 09:31:12.484108 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 09:31:12.484161 output: Architecture: AArch64
229 09:31:12.484214 output: Hash algo: crc32
230 09:31:12.484268 output: Hash value: 0f8e4d2e
231 09:31:12.484322 output: Image 2 (ramdisk-1)
232 09:31:12.484374 output: Description: unavailable
233 09:31:12.484427 output: Created: Tue Jun 18 10:31:12 2024
234 09:31:12.484481 output: Type: RAMDisk Image
235 09:31:12.484535 output: Compression: Unknown Compression
236 09:31:12.484588 output: Data Size: 61004844 Bytes = 59575.04 KiB = 58.18 MiB
237 09:31:12.484642 output: Architecture: AArch64
238 09:31:12.484695 output: OS: Linux
239 09:31:12.484748 output: Load Address: unavailable
240 09:31:12.484802 output: Entry Point: unavailable
241 09:31:12.484855 output: Hash algo: crc32
242 09:31:12.484908 output: Hash value: e996b999
243 09:31:12.484960 output: Default Configuration: 'conf-1'
244 09:31:12.485014 output: Configuration 0 (conf-1)
245 09:31:12.485067 output: Description: mt8192-asurada-spherion-r0
246 09:31:12.485120 output: Kernel: kernel-1
247 09:31:12.485174 output: Init Ramdisk: ramdisk-1
248 09:31:12.485227 output: FDT: fdt-1
249 09:31:12.485280 output: Loadables: kernel-1
250 09:31:12.485333 output:
251 09:31:12.485555 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 09:31:12.485655 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 09:31:12.485764 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 09:31:12.485860 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 09:31:12.485937 No LXC device requested
256 09:31:12.486017 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 09:31:12.486101 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 09:31:12.486203 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 09:31:12.486286 Checking files for TFTP limit of 4294967296 bytes.
260 09:31:12.486802 end: 1 tftp-deploy (duration 00:00:25) [common]
261 09:31:12.486907 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 09:31:12.486998 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 09:31:12.487123 substitutions:
264 09:31:12.487189 - {DTB}: 14407680/tftp-deploy-7ld5grgi/dtb/mt8192-asurada-spherion-r0.dtb
265 09:31:12.487255 - {INITRD}: 14407680/tftp-deploy-7ld5grgi/ramdisk/ramdisk.cpio.gz
266 09:31:12.487315 - {KERNEL}: 14407680/tftp-deploy-7ld5grgi/kernel/Image
267 09:31:12.487373 - {LAVA_MAC}: None
268 09:31:12.487430 - {PRESEED_CONFIG}: None
269 09:31:12.487486 - {PRESEED_LOCAL}: None
270 09:31:12.487541 - {RAMDISK}: 14407680/tftp-deploy-7ld5grgi/ramdisk/ramdisk.cpio.gz
271 09:31:12.487596 - {ROOT_PART}: None
272 09:31:12.487650 - {ROOT}: None
273 09:31:12.487705 - {SERVER_IP}: 192.168.201.1
274 09:31:12.487758 - {TEE}: None
275 09:31:12.487812 Parsed boot commands:
276 09:31:12.487866 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 09:31:12.488062 Parsed boot commands: tftpboot 192.168.201.1 14407680/tftp-deploy-7ld5grgi/kernel/image.itb 14407680/tftp-deploy-7ld5grgi/kernel/cmdline
278 09:31:12.488151 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 09:31:12.488241 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 09:31:12.488333 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 09:31:12.488420 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 09:31:12.488488 Not connected, no need to disconnect.
283 09:31:12.488560 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 09:31:12.488640 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 09:31:12.488708 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 09:31:12.492687 Setting prompt string to ['lava-test: # ']
287 09:31:12.493113 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 09:31:12.493225 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 09:31:12.493326 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 09:31:12.493446 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 09:31:12.493638 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
292 09:31:26.339796 Returned 0 in 13 seconds
293 09:31:26.440858 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 09:31:26.441187 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 09:31:26.441285 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 09:31:26.441371 Setting prompt string to 'Starting depthcharge on Spherion...'
298 09:31:26.441439 Changing prompt to 'Starting depthcharge on Spherion...'
299 09:31:26.441507 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 09:31:26.441914 [Enter `^Ec?' for help]
301 09:31:26.441996
302 09:31:26.442061
303 09:31:26.442123 F0: 102B 0000
304 09:31:26.442210
305 09:31:26.442283 F3: 1001 0000 [0200]
306 09:31:26.442343
307 09:31:26.442400 F3: 1001 0000
308 09:31:26.442459
309 09:31:26.442516 F7: 102D 0000
310 09:31:26.442571
311 09:31:26.442625 F1: 0000 0000
312 09:31:26.442679
313 09:31:26.442732 V0: 0000 0000 [0001]
314 09:31:26.442786
315 09:31:26.442840 00: 0007 8000
316 09:31:26.442898
317 09:31:26.442951 01: 0000 0000
318 09:31:26.443006
319 09:31:26.443060 BP: 0C00 0209 [0000]
320 09:31:26.443113
321 09:31:26.443166 G0: 1182 0000
322 09:31:26.443219
323 09:31:26.443273 EC: 0000 0021 [4000]
324 09:31:26.443326
325 09:31:26.443379 S7: 0000 0000 [0000]
326 09:31:26.443433
327 09:31:26.443486 CC: 0000 0000 [0001]
328 09:31:26.443539
329 09:31:26.443592 T0: 0000 0040 [010F]
330 09:31:26.443646
331 09:31:26.443699 Jump to BL
332 09:31:26.443753
333 09:31:26.443806
334 09:31:26.443859
335 09:31:26.443912 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 09:31:26.443969 ARM64: Exception handlers installed.
337 09:31:26.444022 ARM64: Testing exception
338 09:31:26.444076 ARM64: Done test exception
339 09:31:26.444129 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 09:31:26.444184 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 09:31:26.444239 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 09:31:26.444294 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 09:31:26.444349 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 09:31:26.444404 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 09:31:26.444457 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 09:31:26.444512 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 09:31:26.444566 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 09:31:26.444620 WDT: Last reset was cold boot
349 09:31:26.444673 SPI1(PAD0) initialized at 2873684 Hz
350 09:31:26.444727 SPI5(PAD0) initialized at 992727 Hz
351 09:31:26.444781 VBOOT: Loading verstage.
352 09:31:26.444835 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 09:31:26.444889 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 09:31:26.444943 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 09:31:26.444997 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 09:31:26.445051 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 09:31:26.445106 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 09:31:26.445160 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 09:31:26.445213
360 09:31:26.445266
361 09:31:26.445320 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 09:31:26.445374 ARM64: Exception handlers installed.
363 09:31:26.445428 ARM64: Testing exception
364 09:31:26.445481 ARM64: Done test exception
365 09:31:26.445535 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 09:31:26.445589 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 09:31:26.445642 Probing TPM: . done!
368 09:31:26.445696 TPM ready after 0 ms
369 09:31:26.445749 Connected to device vid:did:rid of 1ae0:0028:00
370 09:31:26.445803 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
371 09:31:26.445858 Initialized TPM device CR50 revision 0
372 09:31:26.445912 tlcl_send_startup: Startup return code is 0
373 09:31:26.445966 TPM: setup succeeded
374 09:31:26.446019 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 09:31:26.446073 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 09:31:26.446127 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 09:31:26.446206 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 09:31:26.446275 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 09:31:26.446330 in-header: 03 07 00 00 08 00 00 00
380 09:31:26.446418 in-data: aa e4 47 04 13 02 00 00
381 09:31:26.446487 Chrome EC: UHEPI supported
382 09:31:26.446542 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 09:31:26.446598 in-header: 03 a9 00 00 08 00 00 00
384 09:31:26.446653 in-data: 84 60 60 08 00 00 00 00
385 09:31:26.446706 Phase 1
386 09:31:26.446761 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 09:31:26.446816 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 09:31:26.446870 VB2:vb2_check_recovery() Recovery was requested manually
389 09:31:26.446924 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 09:31:26.446978 Recovery requested (1009000e)
391 09:31:26.447032 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 09:31:26.447087 tlcl_extend: response is 0
393 09:31:26.447141 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 09:31:26.447195 tlcl_extend: response is 0
395 09:31:26.447250 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 09:31:26.447304 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 09:31:26.447359 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 09:31:26.447413
399 09:31:26.447466
400 09:31:26.447520 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 09:31:26.447576 ARM64: Exception handlers installed.
402 09:31:26.447630 ARM64: Testing exception
403 09:31:26.447683 ARM64: Done test exception
404 09:31:26.447736 pmic_efuse_setting: Set efuses in 11 msecs
405 09:31:26.447790 pmwrap_interface_init: Select PMIF_VLD_RDY
406 09:31:26.447845 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 09:31:26.447899 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 09:31:26.448150 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 09:31:26.448243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 09:31:26.448298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 09:31:26.448352 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 09:31:26.448407 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 09:31:26.448461 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 09:31:26.448515 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 09:31:26.448569 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 09:31:26.448624 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 09:31:26.448710 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 09:31:26.448763 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 09:31:26.448817 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 09:31:26.448871 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 09:31:26.448925 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 09:31:26.448979 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 09:31:26.449032 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 09:31:26.449085 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 09:31:26.449139 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 09:31:26.449193 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 09:31:26.449246 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 09:31:26.449300 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 09:31:26.449354 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 09:31:26.449407 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 09:31:26.449461 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 09:31:26.449514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 09:31:26.449568 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 09:31:26.449622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 09:31:26.449676 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 09:31:26.449730 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 09:31:26.449784 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 09:31:26.449838 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 09:31:26.449892 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 09:31:26.449946 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 09:31:26.449999 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 09:31:26.450053 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 09:31:26.450106 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 09:31:26.450169 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 09:31:26.450261 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 09:31:26.450315 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 09:31:26.450369 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 09:31:26.450422 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 09:31:26.450475 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 09:31:26.450529 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 09:31:26.450582 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 09:31:26.450636 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 09:31:26.450689 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 09:31:26.450743 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 09:31:26.450796 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 09:31:26.450850 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 09:31:26.450904 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 09:31:26.450959 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 09:31:26.451013 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 09:31:26.451067 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 09:31:26.451122 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 09:31:26.451176 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 09:31:26.451230 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 09:31:26.451284 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 09:31:26.451337 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x32
466 09:31:26.451391 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 09:31:26.451445 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
468 09:31:26.451499 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 09:31:26.451553 [RTC]rtc_get_frequency_meter,154: input=15, output=835
470 09:31:26.451607 [RTC]rtc_get_frequency_meter,154: input=7, output=708
471 09:31:26.451660 [RTC]rtc_get_frequency_meter,154: input=11, output=772
472 09:31:26.451714 [RTC]rtc_get_frequency_meter,154: input=13, output=803
473 09:31:26.451767 [RTC]rtc_get_frequency_meter,154: input=12, output=788
474 09:31:26.451820 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 09:31:26.451873 [RTC]rtc_get_frequency_meter,154: input=13, output=803
476 09:31:26.451927 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
477 09:31:26.451988 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
478 09:31:26.452332 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 09:31:26.452414 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 09:31:26.452471 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 09:31:26.452526 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 09:31:26.452581 ADC[4]: Raw value=903400 ID=7
483 09:31:26.452636 ADC[3]: Raw value=212912 ID=1
484 09:31:26.452690 RAM Code: 0x71
485 09:31:26.452744 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 09:31:26.452799 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 09:31:26.452853 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 09:31:26.452908 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 09:31:26.452965 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 09:31:26.453020 in-header: 03 07 00 00 08 00 00 00
491 09:31:26.453101 in-data: aa e4 47 04 13 02 00 00
492 09:31:26.453172 Chrome EC: UHEPI supported
493 09:31:26.453225 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 09:31:26.453280 in-header: 03 a9 00 00 08 00 00 00
495 09:31:26.453334 in-data: 84 60 60 08 00 00 00 00
496 09:31:26.453388 MRC: failed to locate region type 0.
497 09:31:26.453442 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 09:31:26.453496 DRAM-K: Running full calibration
499 09:31:26.453550 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 09:31:26.453604 header.status = 0x0
501 09:31:26.453658 header.version = 0x6 (expected: 0x6)
502 09:31:26.453712 header.size = 0xd00 (expected: 0xd00)
503 09:31:26.453766 header.flags = 0x0
504 09:31:26.453820 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 09:31:26.453873 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 09:31:26.453928 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 09:31:26.453981 dram_init: ddr_geometry: 2
508 09:31:26.454035 [EMI] MDL number = 2
509 09:31:26.454088 [EMI] Get MDL freq = 0
510 09:31:26.454141 dram_init: ddr_type: 0
511 09:31:26.454264 is_discrete_lpddr4: 1
512 09:31:26.454352 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 09:31:26.454410
514 09:31:26.454464
515 09:31:26.454518 [Bian_co] ETT version 0.0.0.1
516 09:31:26.454611 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 09:31:26.454677
518 09:31:26.454766 dramc_set_vcore_voltage set vcore to 650000
519 09:31:26.454827 Read voltage for 800, 4
520 09:31:26.454882 Vio18 = 0
521 09:31:26.454937 Vcore = 650000
522 09:31:26.454991 Vdram = 0
523 09:31:26.455048 Vddq = 0
524 09:31:26.455102 Vmddr = 0
525 09:31:26.455155 dram_init: config_dvfs: 1
526 09:31:26.455210 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 09:31:26.455265 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 09:31:26.455319 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
529 09:31:26.455373 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
530 09:31:26.455428 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
531 09:31:26.455481 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
532 09:31:26.455535 MEM_TYPE=3, freq_sel=18
533 09:31:26.455588 sv_algorithm_assistance_LP4_1600
534 09:31:26.455642 ============ PULL DRAM RESETB DOWN ============
535 09:31:26.455700 ========== PULL DRAM RESETB DOWN end =========
536 09:31:26.455754 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 09:31:26.455808 ===================================
538 09:31:26.455862 LPDDR4 DRAM CONFIGURATION
539 09:31:26.455915 ===================================
540 09:31:26.455969 EX_ROW_EN[0] = 0x0
541 09:31:26.456022 EX_ROW_EN[1] = 0x0
542 09:31:26.456076 LP4Y_EN = 0x0
543 09:31:26.456129 WORK_FSP = 0x0
544 09:31:26.456202 WL = 0x2
545 09:31:26.456294 RL = 0x2
546 09:31:26.456352 BL = 0x2
547 09:31:26.456406 RPST = 0x0
548 09:31:26.456461 RD_PRE = 0x0
549 09:31:26.456514 WR_PRE = 0x1
550 09:31:26.456568 WR_PST = 0x0
551 09:31:26.456621 DBI_WR = 0x0
552 09:31:26.456675 DBI_RD = 0x0
553 09:31:26.456728 OTF = 0x1
554 09:31:26.456782 ===================================
555 09:31:26.456837 ===================================
556 09:31:26.456891 ANA top config
557 09:31:26.456944 ===================================
558 09:31:26.456998 DLL_ASYNC_EN = 0
559 09:31:26.457052 ALL_SLAVE_EN = 1
560 09:31:26.457105 NEW_RANK_MODE = 1
561 09:31:26.457160 DLL_IDLE_MODE = 1
562 09:31:26.457214 LP45_APHY_COMB_EN = 1
563 09:31:26.457267 TX_ODT_DIS = 1
564 09:31:26.457321 NEW_8X_MODE = 1
565 09:31:26.457375 ===================================
566 09:31:26.457429 ===================================
567 09:31:26.457483 data_rate = 1600
568 09:31:26.457537 CKR = 1
569 09:31:26.457590 DQ_P2S_RATIO = 8
570 09:31:26.457643 ===================================
571 09:31:26.457698 CA_P2S_RATIO = 8
572 09:31:26.457751 DQ_CA_OPEN = 0
573 09:31:26.457804 DQ_SEMI_OPEN = 0
574 09:31:26.457858 CA_SEMI_OPEN = 0
575 09:31:26.457911 CA_FULL_RATE = 0
576 09:31:26.457964 DQ_CKDIV4_EN = 1
577 09:31:26.458018 CA_CKDIV4_EN = 1
578 09:31:26.458097 CA_PREDIV_EN = 0
579 09:31:26.458183 PH8_DLY = 0
580 09:31:26.458293 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 09:31:26.458401 DQ_AAMCK_DIV = 4
582 09:31:26.458457 CA_AAMCK_DIV = 4
583 09:31:26.458512 CA_ADMCK_DIV = 4
584 09:31:26.458566 DQ_TRACK_CA_EN = 0
585 09:31:26.458620 CA_PICK = 800
586 09:31:26.458674 CA_MCKIO = 800
587 09:31:26.458728 MCKIO_SEMI = 0
588 09:31:26.458782 PLL_FREQ = 3068
589 09:31:26.458836 DQ_UI_PI_RATIO = 32
590 09:31:26.458890 CA_UI_PI_RATIO = 0
591 09:31:26.458943 ===================================
592 09:31:26.459023 ===================================
593 09:31:26.459092 memory_type:LPDDR4
594 09:31:26.459146 GP_NUM : 10
595 09:31:26.459200 SRAM_EN : 1
596 09:31:26.459254 MD32_EN : 0
597 09:31:26.459514 ===================================
598 09:31:26.459574 [ANA_INIT] >>>>>>>>>>>>>>
599 09:31:26.459629 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 09:31:26.459689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 09:31:26.459744 ===================================
602 09:31:26.459798 data_rate = 1600,PCW = 0X7600
603 09:31:26.459851 ===================================
604 09:31:26.459905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 09:31:26.459959 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 09:31:26.460014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 09:31:26.460067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 09:31:26.460121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 09:31:26.460175 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 09:31:26.460228 [ANA_INIT] flow start
611 09:31:26.460282 [ANA_INIT] PLL >>>>>>>>
612 09:31:26.460335 [ANA_INIT] PLL <<<<<<<<
613 09:31:26.460389 [ANA_INIT] MIDPI >>>>>>>>
614 09:31:26.460442 [ANA_INIT] MIDPI <<<<<<<<
615 09:31:26.460495 [ANA_INIT] DLL >>>>>>>>
616 09:31:26.460549 [ANA_INIT] flow end
617 09:31:26.460602 ============ LP4 DIFF to SE enter ============
618 09:31:26.460657 ============ LP4 DIFF to SE exit ============
619 09:31:26.460711 [ANA_INIT] <<<<<<<<<<<<<
620 09:31:26.460764 [Flow] Enable top DCM control >>>>>
621 09:31:26.460818 [Flow] Enable top DCM control <<<<<
622 09:31:26.460871 Enable DLL master slave shuffle
623 09:31:26.460924 ==============================================================
624 09:31:26.460978 Gating Mode config
625 09:31:26.461032 ==============================================================
626 09:31:26.461085 Config description:
627 09:31:26.461139 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 09:31:26.461194 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 09:31:26.461249 SELPH_MODE 0: By rank 1: By Phase
630 09:31:26.461302 ==============================================================
631 09:31:26.461356 GAT_TRACK_EN = 1
632 09:31:26.461410 RX_GATING_MODE = 2
633 09:31:26.461463 RX_GATING_TRACK_MODE = 2
634 09:31:26.461516 SELPH_MODE = 1
635 09:31:26.461569 PICG_EARLY_EN = 1
636 09:31:26.461638 VALID_LAT_VALUE = 1
637 09:31:26.461694 ==============================================================
638 09:31:26.461749 Enter into Gating configuration >>>>
639 09:31:26.461820 Exit from Gating configuration <<<<
640 09:31:26.461889 Enter into DVFS_PRE_config >>>>>
641 09:31:26.461943 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 09:31:26.462001 Exit from DVFS_PRE_config <<<<<
643 09:31:26.462054 Enter into PICG configuration >>>>
644 09:31:26.462107 Exit from PICG configuration <<<<
645 09:31:26.462188 [RX_INPUT] configuration >>>>>
646 09:31:26.462261 [RX_INPUT] configuration <<<<<
647 09:31:26.462315 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 09:31:26.462369 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 09:31:26.462424 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 09:31:26.462478 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 09:31:26.462532 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 09:31:26.462586 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 09:31:26.462657 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 09:31:26.462715 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 09:31:26.462769 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 09:31:26.462823 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 09:31:26.462877 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 09:31:26.462931 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 09:31:26.462985 ===================================
660 09:31:26.463039 LPDDR4 DRAM CONFIGURATION
661 09:31:26.463093 ===================================
662 09:31:26.463146 EX_ROW_EN[0] = 0x0
663 09:31:26.463200 EX_ROW_EN[1] = 0x0
664 09:31:26.463253 LP4Y_EN = 0x0
665 09:31:26.463306 WORK_FSP = 0x0
666 09:31:26.463359 WL = 0x2
667 09:31:26.463412 RL = 0x2
668 09:31:26.463465 BL = 0x2
669 09:31:26.463519 RPST = 0x0
670 09:31:26.463572 RD_PRE = 0x0
671 09:31:26.463626 WR_PRE = 0x1
672 09:31:26.463679 WR_PST = 0x0
673 09:31:26.463732 DBI_WR = 0x0
674 09:31:26.463785 DBI_RD = 0x0
675 09:31:26.463838 OTF = 0x1
676 09:31:26.463891 ===================================
677 09:31:26.463945 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 09:31:26.463999 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 09:31:26.464054 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 09:31:26.464107 ===================================
681 09:31:26.464161 LPDDR4 DRAM CONFIGURATION
682 09:31:26.464215 ===================================
683 09:31:26.464268 EX_ROW_EN[0] = 0x10
684 09:31:26.464322 EX_ROW_EN[1] = 0x0
685 09:31:26.464375 LP4Y_EN = 0x0
686 09:31:26.464429 WORK_FSP = 0x0
687 09:31:26.464482 WL = 0x2
688 09:31:26.464535 RL = 0x2
689 09:31:26.464588 BL = 0x2
690 09:31:26.464641 RPST = 0x0
691 09:31:26.464694 RD_PRE = 0x0
692 09:31:26.464747 WR_PRE = 0x1
693 09:31:26.464800 WR_PST = 0x0
694 09:31:26.464853 DBI_WR = 0x0
695 09:31:26.464906 DBI_RD = 0x0
696 09:31:26.464959 OTF = 0x1
697 09:31:26.465012 ===================================
698 09:31:26.465065 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 09:31:26.465118 nWR fixed to 40
700 09:31:26.465173 [ModeRegInit_LP4] CH0 RK0
701 09:31:26.465226 [ModeRegInit_LP4] CH0 RK1
702 09:31:26.465279 [ModeRegInit_LP4] CH1 RK0
703 09:31:26.465332 [ModeRegInit_LP4] CH1 RK1
704 09:31:26.465385 match AC timing 13
705 09:31:26.465439 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 09:31:26.465691 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 09:31:26.465750 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 09:31:26.465805 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 09:31:26.465859 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 09:31:26.465913 [EMI DOE] emi_dcm 0
711 09:31:26.465967 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 09:31:26.466022 ==
713 09:31:26.466076 Dram Type= 6, Freq= 0, CH_0, rank 0
714 09:31:26.466129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 09:31:26.466229 ==
716 09:31:26.466284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 09:31:26.466339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 09:31:26.466393 [CA 0] Center 37 (7~68) winsize 62
719 09:31:26.466447 [CA 1] Center 37 (7~68) winsize 62
720 09:31:26.466501 [CA 2] Center 34 (4~65) winsize 62
721 09:31:26.466555 [CA 3] Center 34 (4~65) winsize 62
722 09:31:26.466608 [CA 4] Center 33 (3~64) winsize 62
723 09:31:26.466661 [CA 5] Center 33 (3~64) winsize 62
724 09:31:26.466714
725 09:31:26.466766 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 09:31:26.466820
727 09:31:26.466873 [CATrainingPosCal] consider 1 rank data
728 09:31:26.466927 u2DelayCellTimex100 = 270/100 ps
729 09:31:26.466981 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 09:31:26.467034 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 09:31:26.467089 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 09:31:26.467142 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 09:31:26.467195 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 09:31:26.467249 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 09:31:26.467302
736 09:31:26.467355 CA PerBit enable=1, Macro0, CA PI delay=33
737 09:31:26.467409
738 09:31:26.467462 [CBTSetCACLKResult] CA Dly = 33
739 09:31:26.467516 CS Dly: 7 (0~38)
740 09:31:26.467569 ==
741 09:31:26.467622 Dram Type= 6, Freq= 0, CH_0, rank 1
742 09:31:26.467675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 09:31:26.467729 ==
744 09:31:26.467783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 09:31:26.467836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 09:31:26.467890 [CA 0] Center 37 (7~68) winsize 62
747 09:31:26.467943 [CA 1] Center 37 (7~68) winsize 62
748 09:31:26.467997 [CA 2] Center 34 (4~65) winsize 62
749 09:31:26.468050 [CA 3] Center 34 (4~65) winsize 62
750 09:31:26.468103 [CA 4] Center 33 (3~64) winsize 62
751 09:31:26.468157 [CA 5] Center 33 (3~64) winsize 62
752 09:31:26.468210
753 09:31:26.468263 [CmdBusTrainingLP45] Vref(ca) range 1: 32
754 09:31:26.468316
755 09:31:26.468369 [CATrainingPosCal] consider 2 rank data
756 09:31:26.468422 u2DelayCellTimex100 = 270/100 ps
757 09:31:26.468476 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 09:31:26.468529 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 09:31:26.468583 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 09:31:26.468637 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 09:31:26.468690 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 09:31:26.468744 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 09:31:26.468798
764 09:31:26.468852 CA PerBit enable=1, Macro0, CA PI delay=33
765 09:31:26.468905
766 09:31:26.468958 [CBTSetCACLKResult] CA Dly = 33
767 09:31:26.469011 CS Dly: 7 (0~38)
768 09:31:26.469065
769 09:31:26.469117 ----->DramcWriteLeveling(PI) begin...
770 09:31:26.469174 ==
771 09:31:26.469228 Dram Type= 6, Freq= 0, CH_0, rank 0
772 09:31:26.469282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 09:31:26.469336 ==
774 09:31:26.469389 Write leveling (Byte 0): 33 => 33
775 09:31:26.469443 Write leveling (Byte 1): 33 => 33
776 09:31:26.469496 DramcWriteLeveling(PI) end<-----
777 09:31:26.469549
778 09:31:26.469602 ==
779 09:31:26.469655 Dram Type= 6, Freq= 0, CH_0, rank 0
780 09:31:26.469708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 09:31:26.469762 ==
782 09:31:26.469815 [Gating] SW mode calibration
783 09:31:26.469869 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 09:31:26.469922 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 09:31:26.469976 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 09:31:26.470030 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 09:31:26.470084 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 09:31:26.470138 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 09:31:26.470241 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 09:31:26.470295 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 09:31:26.470350 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 09:31:26.470404 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 09:31:26.470457 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 09:31:26.470511 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 09:31:26.470565 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 09:31:26.470618 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 09:31:26.470672 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 09:31:26.470726 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 09:31:26.470779 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 09:31:26.470832 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 09:31:26.470886 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 09:31:26.470939 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 09:31:26.470993 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
804 09:31:26.471046 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 09:31:26.471100 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 09:31:26.471154 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 09:31:26.471207 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 09:31:26.471261 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 09:31:26.471314 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 09:31:26.471368 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 09:31:26.471422 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
812 09:31:26.471476 0 9 12 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
813 09:31:26.471529 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 09:31:26.471777 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 09:31:26.471836 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 09:31:26.471891 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 09:31:26.471945 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 09:31:26.471999 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
819 09:31:26.472054 0 10 8 | B1->B0 | 3434 2626 | 0 0 | (0 0) (1 0)
820 09:31:26.472107 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
821 09:31:26.472161 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 09:31:26.472215 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 09:31:26.472269 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 09:31:26.472343 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 09:31:26.472411 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 09:31:26.472490 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
827 09:31:26.472581 0 11 8 | B1->B0 | 2626 3b3b | 0 0 | (0 0) (0 0)
828 09:31:26.472672 0 11 12 | B1->B0 | 3c3b 4646 | 1 0 | (0 0) (0 0)
829 09:31:26.472731 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 09:31:26.472786 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 09:31:26.472841 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 09:31:26.472896 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 09:31:26.472950 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 09:31:26.473004 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 09:31:26.473058 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
836 09:31:26.473113 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 09:31:26.473167 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 09:31:26.473221 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 09:31:26.473274 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 09:31:26.473328 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 09:31:26.473383 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 09:31:26.473437 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 09:31:26.473490 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:31:26.473543 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 09:31:26.473597 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 09:31:26.473651 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 09:31:26.473705 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 09:31:26.473759 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 09:31:26.473813 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 09:31:26.473867 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 09:31:26.473920 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 09:31:26.473974 Total UI for P1: 0, mck2ui 16
853 09:31:26.474028 best dqsien dly found for B0: ( 0, 14, 6)
854 09:31:26.474082 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 09:31:26.474136 Total UI for P1: 0, mck2ui 16
856 09:31:26.474240 best dqsien dly found for B1: ( 0, 14, 8)
857 09:31:26.474295 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
858 09:31:26.474349 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 09:31:26.474402
860 09:31:26.474456 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
861 09:31:26.474510 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 09:31:26.474564 [Gating] SW calibration Done
863 09:31:26.474618 ==
864 09:31:26.474672 Dram Type= 6, Freq= 0, CH_0, rank 0
865 09:31:26.474728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 09:31:26.474782 ==
867 09:31:26.474837 RX Vref Scan: 0
868 09:31:26.474890
869 09:31:26.474944 RX Vref 0 -> 0, step: 1
870 09:31:26.474998
871 09:31:26.475052 RX Delay -130 -> 252, step: 16
872 09:31:26.475106 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 09:31:26.475160 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 09:31:26.475214 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 09:31:26.475268 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 09:31:26.475322 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
877 09:31:26.475376 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
878 09:31:26.475430 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
879 09:31:26.475484 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
880 09:31:26.475538 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
881 09:31:26.475592 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
882 09:31:26.475646 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 09:31:26.475700 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
884 09:31:26.475754 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
885 09:31:26.475846 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
886 09:31:26.475903 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 09:31:26.475991 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
888 09:31:26.476051 ==
889 09:31:26.476106 Dram Type= 6, Freq= 0, CH_0, rank 0
890 09:31:26.476161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 09:31:26.476216 ==
892 09:31:26.476270 DQS Delay:
893 09:31:26.476324 DQS0 = 0, DQS1 = 0
894 09:31:26.476379 DQM Delay:
895 09:31:26.476433 DQM0 = 85, DQM1 = 70
896 09:31:26.476487 DQ Delay:
897 09:31:26.476541 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 09:31:26.476595 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
899 09:31:26.476649 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
900 09:31:26.476703 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
901 09:31:26.476757
902 09:31:26.476811
903 09:31:26.476864 ==
904 09:31:26.476918 Dram Type= 6, Freq= 0, CH_0, rank 0
905 09:31:26.476971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 09:31:26.477025 ==
907 09:31:26.477079
908 09:31:26.477133
909 09:31:26.477185 TX Vref Scan disable
910 09:31:26.477240 == TX Byte 0 ==
911 09:31:26.477293 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
912 09:31:26.477348 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
913 09:31:26.477402 == TX Byte 1 ==
914 09:31:26.477455 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
915 09:31:26.477509 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
916 09:31:26.477563 ==
917 09:31:26.477617 Dram Type= 6, Freq= 0, CH_0, rank 0
918 09:31:26.477671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 09:31:26.477725 ==
920 09:31:26.477779 TX Vref=22, minBit 4, minWin=27, winSum=442
921 09:31:26.477834 TX Vref=24, minBit 3, minWin=27, winSum=445
922 09:31:26.478093 TX Vref=26, minBit 10, minWin=27, winSum=449
923 09:31:26.478154 TX Vref=28, minBit 8, minWin=27, winSum=451
924 09:31:26.478260 TX Vref=30, minBit 0, minWin=28, winSum=451
925 09:31:26.478315 TX Vref=32, minBit 10, minWin=27, winSum=449
926 09:31:26.478370 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
927 09:31:26.478457
928 09:31:26.478577 Final TX Range 1 Vref 30
929 09:31:26.478726
930 09:31:26.478836 ==
931 09:31:26.478905 Dram Type= 6, Freq= 0, CH_0, rank 0
932 09:31:26.478962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 09:31:26.479018 ==
934 09:31:26.479072
935 09:31:26.479126
936 09:31:26.479179 TX Vref Scan disable
937 09:31:26.479234 == TX Byte 0 ==
938 09:31:26.479288 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
939 09:31:26.479342 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
940 09:31:26.479396 == TX Byte 1 ==
941 09:31:26.479450 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
942 09:31:26.479504 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
943 09:31:26.479561
944 09:31:26.479615 [DATLAT]
945 09:31:26.479669 Freq=800, CH0 RK0
946 09:31:26.479723
947 09:31:26.479777 DATLAT Default: 0xa
948 09:31:26.479831 0, 0xFFFF, sum = 0
949 09:31:26.479886 1, 0xFFFF, sum = 0
950 09:31:26.479941 2, 0xFFFF, sum = 0
951 09:31:26.479995 3, 0xFFFF, sum = 0
952 09:31:26.480049 4, 0xFFFF, sum = 0
953 09:31:26.480104 5, 0xFFFF, sum = 0
954 09:31:26.480193 6, 0xFFFF, sum = 0
955 09:31:26.480247 7, 0xFFFF, sum = 0
956 09:31:26.480301 8, 0xFFFF, sum = 0
957 09:31:26.480356 9, 0x0, sum = 1
958 09:31:26.480410 10, 0x0, sum = 2
959 09:31:26.480464 11, 0x0, sum = 3
960 09:31:26.480518 12, 0x0, sum = 4
961 09:31:26.480572 best_step = 10
962 09:31:26.480626
963 09:31:26.480679 ==
964 09:31:26.480733 Dram Type= 6, Freq= 0, CH_0, rank 0
965 09:31:26.480787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 09:31:26.480842 ==
967 09:31:26.480896 RX Vref Scan: 1
968 09:31:26.480950
969 09:31:26.481014 Set Vref Range= 32 -> 127
970 09:31:26.481070
971 09:31:26.481124 RX Vref 32 -> 127, step: 1
972 09:31:26.481178
973 09:31:26.481232 RX Delay -111 -> 252, step: 8
974 09:31:26.481286
975 09:31:26.481339 Set Vref, RX VrefLevel [Byte0]: 32
976 09:31:26.481393 [Byte1]: 32
977 09:31:26.481447
978 09:31:26.481501 Set Vref, RX VrefLevel [Byte0]: 33
979 09:31:26.481554 [Byte1]: 33
980 09:31:26.481608
981 09:31:26.481662 Set Vref, RX VrefLevel [Byte0]: 34
982 09:31:26.481716 [Byte1]: 34
983 09:31:26.481769
984 09:31:26.481822 Set Vref, RX VrefLevel [Byte0]: 35
985 09:31:26.481876 [Byte1]: 35
986 09:31:26.481929
987 09:31:26.481983 Set Vref, RX VrefLevel [Byte0]: 36
988 09:31:26.482037 [Byte1]: 36
989 09:31:26.482090
990 09:31:26.482144 Set Vref, RX VrefLevel [Byte0]: 37
991 09:31:26.482241 [Byte1]: 37
992 09:31:26.482295
993 09:31:26.482348 Set Vref, RX VrefLevel [Byte0]: 38
994 09:31:26.482402 [Byte1]: 38
995 09:31:26.482454
996 09:31:26.482507 Set Vref, RX VrefLevel [Byte0]: 39
997 09:31:26.482560 [Byte1]: 39
998 09:31:26.482614
999 09:31:26.482667 Set Vref, RX VrefLevel [Byte0]: 40
1000 09:31:26.482720 [Byte1]: 40
1001 09:31:26.482773
1002 09:31:26.482826 Set Vref, RX VrefLevel [Byte0]: 41
1003 09:31:26.482879 [Byte1]: 41
1004 09:31:26.482932
1005 09:31:26.482985 Set Vref, RX VrefLevel [Byte0]: 42
1006 09:31:26.483039 [Byte1]: 42
1007 09:31:26.483091
1008 09:31:26.483144 Set Vref, RX VrefLevel [Byte0]: 43
1009 09:31:26.483198 [Byte1]: 43
1010 09:31:26.483251
1011 09:31:26.483304 Set Vref, RX VrefLevel [Byte0]: 44
1012 09:31:26.483357 [Byte1]: 44
1013 09:31:26.483426
1014 09:31:26.483481 Set Vref, RX VrefLevel [Byte0]: 45
1015 09:31:26.483534 [Byte1]: 45
1016 09:31:26.483588
1017 09:31:26.483642 Set Vref, RX VrefLevel [Byte0]: 46
1018 09:31:26.483696 [Byte1]: 46
1019 09:31:26.483750
1020 09:31:26.483803 Set Vref, RX VrefLevel [Byte0]: 47
1021 09:31:26.483856 [Byte1]: 47
1022 09:31:26.483910
1023 09:31:26.483966 Set Vref, RX VrefLevel [Byte0]: 48
1024 09:31:26.484019 [Byte1]: 48
1025 09:31:26.484080
1026 09:31:26.484136 Set Vref, RX VrefLevel [Byte0]: 49
1027 09:31:26.484191 [Byte1]: 49
1028 09:31:26.484245
1029 09:31:26.484298 Set Vref, RX VrefLevel [Byte0]: 50
1030 09:31:26.484353 [Byte1]: 50
1031 09:31:26.484407
1032 09:31:26.484460 Set Vref, RX VrefLevel [Byte0]: 51
1033 09:31:26.484513 [Byte1]: 51
1034 09:31:26.484566
1035 09:31:26.484619 Set Vref, RX VrefLevel [Byte0]: 52
1036 09:31:26.484673 [Byte1]: 52
1037 09:31:26.484725
1038 09:31:26.484778 Set Vref, RX VrefLevel [Byte0]: 53
1039 09:31:26.484831 [Byte1]: 53
1040 09:31:26.484883
1041 09:31:26.484936 Set Vref, RX VrefLevel [Byte0]: 54
1042 09:31:26.484989 [Byte1]: 54
1043 09:31:26.485042
1044 09:31:26.485095 Set Vref, RX VrefLevel [Byte0]: 55
1045 09:31:26.485148 [Byte1]: 55
1046 09:31:26.485201
1047 09:31:26.485253 Set Vref, RX VrefLevel [Byte0]: 56
1048 09:31:26.485306 [Byte1]: 56
1049 09:31:26.485358
1050 09:31:26.485411 Set Vref, RX VrefLevel [Byte0]: 57
1051 09:31:26.485464 [Byte1]: 57
1052 09:31:26.485517
1053 09:31:26.485569 Set Vref, RX VrefLevel [Byte0]: 58
1054 09:31:26.485622 [Byte1]: 58
1055 09:31:26.485675
1056 09:31:26.485727 Set Vref, RX VrefLevel [Byte0]: 59
1057 09:31:26.485781 [Byte1]: 59
1058 09:31:26.485833
1059 09:31:26.485886 Set Vref, RX VrefLevel [Byte0]: 60
1060 09:31:26.485938 [Byte1]: 60
1061 09:31:26.485991
1062 09:31:26.486043 Set Vref, RX VrefLevel [Byte0]: 61
1063 09:31:26.486095 [Byte1]: 61
1064 09:31:26.486148
1065 09:31:26.486242 Set Vref, RX VrefLevel [Byte0]: 62
1066 09:31:26.486295 [Byte1]: 62
1067 09:31:26.486348
1068 09:31:26.486401 Set Vref, RX VrefLevel [Byte0]: 63
1069 09:31:26.486453 [Byte1]: 63
1070 09:31:26.486505
1071 09:31:26.486557 Set Vref, RX VrefLevel [Byte0]: 64
1072 09:31:26.486610 [Byte1]: 64
1073 09:31:26.486662
1074 09:31:26.486715 Set Vref, RX VrefLevel [Byte0]: 65
1075 09:31:26.486767 [Byte1]: 65
1076 09:31:26.486821
1077 09:31:26.486873 Set Vref, RX VrefLevel [Byte0]: 66
1078 09:31:26.486925 [Byte1]: 66
1079 09:31:26.486978
1080 09:31:26.487030 Set Vref, RX VrefLevel [Byte0]: 67
1081 09:31:26.487083 [Byte1]: 67
1082 09:31:26.487136
1083 09:31:26.487188 Set Vref, RX VrefLevel [Byte0]: 68
1084 09:31:26.487241 [Byte1]: 68
1085 09:31:26.487294
1086 09:31:26.487346 Set Vref, RX VrefLevel [Byte0]: 69
1087 09:31:26.487399 [Byte1]: 69
1088 09:31:26.487451
1089 09:31:26.487503 Set Vref, RX VrefLevel [Byte0]: 70
1090 09:31:26.487766 [Byte1]: 70
1091 09:31:26.487830
1092 09:31:26.487884 Set Vref, RX VrefLevel [Byte0]: 71
1093 09:31:26.487938 [Byte1]: 71
1094 09:31:26.487991
1095 09:31:26.488045 Set Vref, RX VrefLevel [Byte0]: 72
1096 09:31:26.488118 [Byte1]: 72
1097 09:31:26.488186
1098 09:31:26.488238 Set Vref, RX VrefLevel [Byte0]: 73
1099 09:31:26.488291 [Byte1]: 73
1100 09:31:26.488343
1101 09:31:26.488395 Set Vref, RX VrefLevel [Byte0]: 74
1102 09:31:26.488449 [Byte1]: 74
1103 09:31:26.488502
1104 09:31:26.488555 Set Vref, RX VrefLevel [Byte0]: 75
1105 09:31:26.488608 [Byte1]: 75
1106 09:31:26.488661
1107 09:31:26.488713 Set Vref, RX VrefLevel [Byte0]: 76
1108 09:31:26.488766 [Byte1]: 76
1109 09:31:26.488819
1110 09:31:26.488871 Set Vref, RX VrefLevel [Byte0]: 77
1111 09:31:26.488924 [Byte1]: 77
1112 09:31:26.488977
1113 09:31:26.489029 Set Vref, RX VrefLevel [Byte0]: 78
1114 09:31:26.489081 [Byte1]: 78
1115 09:31:26.489134
1116 09:31:26.489186 Set Vref, RX VrefLevel [Byte0]: 79
1117 09:31:26.489238 [Byte1]: 79
1118 09:31:26.489290
1119 09:31:26.489343 Final RX Vref Byte 0 = 65 to rank0
1120 09:31:26.489396 Final RX Vref Byte 1 = 59 to rank0
1121 09:31:26.489450 Final RX Vref Byte 0 = 65 to rank1
1122 09:31:26.489503 Final RX Vref Byte 1 = 59 to rank1==
1123 09:31:26.489556 Dram Type= 6, Freq= 0, CH_0, rank 0
1124 09:31:26.489609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1125 09:31:26.489662 ==
1126 09:31:26.489715 DQS Delay:
1127 09:31:26.489768 DQS0 = 0, DQS1 = 0
1128 09:31:26.489820 DQM Delay:
1129 09:31:26.489873 DQM0 = 87, DQM1 = 75
1130 09:31:26.489925 DQ Delay:
1131 09:31:26.489977 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1132 09:31:26.490030 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1133 09:31:26.490083 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1134 09:31:26.490135 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1135 09:31:26.490220
1136 09:31:26.490287
1137 09:31:26.490339 [DQSOSCAuto] RK0, (LSB)MR18= 0x4324, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1138 09:31:26.490394 CH0 RK0: MR19=606, MR18=4324
1139 09:31:26.490447 CH0_RK0: MR19=0x606, MR18=0x4324, DQSOSC=393, MR23=63, INC=95, DEC=63
1140 09:31:26.490500
1141 09:31:26.490553 ----->DramcWriteLeveling(PI) begin...
1142 09:31:26.490608 ==
1143 09:31:26.490661 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 09:31:26.490714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 09:31:26.490768 ==
1146 09:31:26.490820 Write leveling (Byte 0): 32 => 32
1147 09:31:26.490873 Write leveling (Byte 1): 29 => 29
1148 09:31:26.490926 DramcWriteLeveling(PI) end<-----
1149 09:31:26.490978
1150 09:31:26.491030 ==
1151 09:31:26.491083 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 09:31:26.491136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1153 09:31:26.491189 ==
1154 09:31:26.491241 [Gating] SW mode calibration
1155 09:31:26.491294 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1156 09:31:26.491348 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1157 09:31:26.491401 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1158 09:31:26.491454 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 09:31:26.491506 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 09:31:26.491559 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 09:31:26.491612 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 09:31:26.491665 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 09:31:26.491717 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 09:31:26.491770 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 09:31:26.491823 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 09:31:26.491875 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 09:31:26.491928 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 09:31:26.491980 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 09:31:26.492033 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 09:31:26.492086 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 09:31:26.492139 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 09:31:26.492191 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 09:31:26.492244 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 09:31:26.492296 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1175 09:31:26.492349 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1176 09:31:26.492402 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 09:31:26.492454 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 09:31:26.492507 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 09:31:26.492560 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 09:31:26.492646 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 09:31:26.492698 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 09:31:26.492761 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 09:31:26.492850 0 9 8 | B1->B0 | 2323 3030 | 1 1 | (1 1) (1 1)
1184 09:31:26.492939 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
1185 09:31:26.493019 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 09:31:26.493075 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 09:31:26.493129 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 09:31:26.493183 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 09:31:26.493237 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 09:31:26.493290 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1191 09:31:26.493344 0 10 8 | B1->B0 | 2f2f 2828 | 1 1 | (1 1) (1 0)
1192 09:31:26.493397 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1193 09:31:26.493451 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 09:31:26.493504 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 09:31:26.493557 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 09:31:26.493610 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 09:31:26.493663 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 09:31:26.493716 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1199 09:31:26.493768 0 11 8 | B1->B0 | 2d2d 3d3d | 0 0 | (1 1) (1 1)
1200 09:31:26.494029 0 11 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
1201 09:31:26.494089 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 09:31:26.494143 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 09:31:26.494244 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 09:31:26.494298 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 09:31:26.494352 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 09:31:26.494405 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 09:31:26.494458 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1208 09:31:26.494511 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 09:31:26.494564 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 09:31:26.494616 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 09:31:26.494669 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 09:31:26.494723 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 09:31:26.494776 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 09:31:26.494828 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 09:31:26.494881 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 09:31:26.494934 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 09:31:26.494987 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 09:31:26.495040 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 09:31:26.495093 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 09:31:26.495146 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 09:31:26.495198 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 09:31:26.495251 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1223 09:31:26.495304 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1224 09:31:26.495356 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1225 09:31:26.495410 Total UI for P1: 0, mck2ui 16
1226 09:31:26.495464 best dqsien dly found for B0: ( 0, 14, 6)
1227 09:31:26.495517 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 09:31:26.495570 Total UI for P1: 0, mck2ui 16
1229 09:31:26.495623 best dqsien dly found for B1: ( 0, 14, 10)
1230 09:31:26.495699 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1231 09:31:26.495794 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1232 09:31:26.495895
1233 09:31:26.495956 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1234 09:31:26.496012 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1235 09:31:26.496067 [Gating] SW calibration Done
1236 09:31:26.496121 ==
1237 09:31:26.496175 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 09:31:26.496228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 09:31:26.496282 ==
1240 09:31:26.496335 RX Vref Scan: 0
1241 09:31:26.496389
1242 09:31:26.496442 RX Vref 0 -> 0, step: 1
1243 09:31:26.496496
1244 09:31:26.496549 RX Delay -130 -> 252, step: 16
1245 09:31:26.496602 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1246 09:31:26.496655 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1247 09:31:26.496708 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1248 09:31:26.496761 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1249 09:31:26.496814 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1250 09:31:26.496867 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1251 09:31:26.496920 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1252 09:31:26.496973 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1253 09:31:26.497025 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1254 09:31:26.497078 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1255 09:31:26.497131 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1256 09:31:26.497184 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1257 09:31:26.497236 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1258 09:31:26.497289 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1259 09:31:26.497342 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1260 09:31:26.497394 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1261 09:31:26.497447 ==
1262 09:31:26.497500 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 09:31:26.497554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 09:31:26.497608 ==
1265 09:31:26.497661 DQS Delay:
1266 09:31:26.497713 DQS0 = 0, DQS1 = 0
1267 09:31:26.497766 DQM Delay:
1268 09:31:26.497819 DQM0 = 82, DQM1 = 76
1269 09:31:26.497872 DQ Delay:
1270 09:31:26.497924 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1271 09:31:26.497977 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1272 09:31:26.498031 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1273 09:31:26.498084 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =77
1274 09:31:26.498137
1275 09:31:26.498236
1276 09:31:26.498290 ==
1277 09:31:26.498343 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 09:31:26.498396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 09:31:26.498448 ==
1280 09:31:26.498501
1281 09:31:26.498554
1282 09:31:26.498606 TX Vref Scan disable
1283 09:31:26.498659 == TX Byte 0 ==
1284 09:31:26.498712 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1285 09:31:26.498766 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1286 09:31:26.498819 == TX Byte 1 ==
1287 09:31:26.498871 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1288 09:31:26.498924 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1289 09:31:26.498976 ==
1290 09:31:26.499029 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 09:31:26.499082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 09:31:26.499135 ==
1293 09:31:26.499188 TX Vref=22, minBit 3, minWin=27, winSum=445
1294 09:31:26.499241 TX Vref=24, minBit 8, minWin=27, winSum=446
1295 09:31:26.499295 TX Vref=26, minBit 9, minWin=27, winSum=448
1296 09:31:26.499347 TX Vref=28, minBit 9, minWin=27, winSum=448
1297 09:31:26.499399 TX Vref=30, minBit 8, minWin=27, winSum=447
1298 09:31:26.499452 TX Vref=32, minBit 9, minWin=27, winSum=449
1299 09:31:26.499504 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 32
1300 09:31:26.499557
1301 09:31:26.499609 Final TX Range 1 Vref 32
1302 09:31:26.499662
1303 09:31:26.499713 ==
1304 09:31:26.499765 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 09:31:26.499817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 09:31:26.499870 ==
1307 09:31:26.499922
1308 09:31:26.499973
1309 09:31:26.500025 TX Vref Scan disable
1310 09:31:26.500077 == TX Byte 0 ==
1311 09:31:26.500129 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1312 09:31:26.500182 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1313 09:31:26.500234 == TX Byte 1 ==
1314 09:31:26.500286 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1315 09:31:26.500339 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1316 09:31:26.500391
1317 09:31:26.500442 [DATLAT]
1318 09:31:26.500493 Freq=800, CH0 RK1
1319 09:31:26.500546
1320 09:31:26.500800 DATLAT Default: 0xa
1321 09:31:26.500859 0, 0xFFFF, sum = 0
1322 09:31:26.500914 1, 0xFFFF, sum = 0
1323 09:31:26.500968 2, 0xFFFF, sum = 0
1324 09:31:26.501021 3, 0xFFFF, sum = 0
1325 09:31:26.501075 4, 0xFFFF, sum = 0
1326 09:31:26.501128 5, 0xFFFF, sum = 0
1327 09:31:26.501181 6, 0xFFFF, sum = 0
1328 09:31:26.501233 7, 0xFFFF, sum = 0
1329 09:31:26.501286 8, 0xFFFF, sum = 0
1330 09:31:26.501339 9, 0x0, sum = 1
1331 09:31:26.501392 10, 0x0, sum = 2
1332 09:31:26.501445 11, 0x0, sum = 3
1333 09:31:26.501497 12, 0x0, sum = 4
1334 09:31:26.501550 best_step = 10
1335 09:31:26.501601
1336 09:31:26.501653 ==
1337 09:31:26.501706 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 09:31:26.501759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 09:31:26.501812 ==
1340 09:31:26.501864 RX Vref Scan: 0
1341 09:31:26.501916
1342 09:31:26.501968 RX Vref 0 -> 0, step: 1
1343 09:31:26.502019
1344 09:31:26.502071 RX Delay -95 -> 252, step: 8
1345 09:31:26.502123 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1346 09:31:26.502186 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1347 09:31:26.502240 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1348 09:31:26.502292 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1349 09:31:26.502344 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1350 09:31:26.502396 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1351 09:31:26.502449 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1352 09:31:26.502501 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1353 09:31:26.502552 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1354 09:31:26.502605 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1355 09:31:26.502657 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1356 09:31:26.502709 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1357 09:31:26.502761 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1358 09:31:26.502813 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1359 09:31:26.502865 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1360 09:31:26.502917 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1361 09:31:26.502969 ==
1362 09:31:26.503021 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 09:31:26.503074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 09:31:26.503127 ==
1365 09:31:26.503179 DQS Delay:
1366 09:31:26.503231 DQS0 = 0, DQS1 = 0
1367 09:31:26.503283 DQM Delay:
1368 09:31:26.503335 DQM0 = 85, DQM1 = 76
1369 09:31:26.503387 DQ Delay:
1370 09:31:26.503439 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =84
1371 09:31:26.503492 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1372 09:31:26.503544 DQ8 =68, DQ9 =60, DQ10 =80, DQ11 =68
1373 09:31:26.503596 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1374 09:31:26.503649
1375 09:31:26.503700
1376 09:31:26.503752 [DQSOSCAuto] RK1, (LSB)MR18= 0x4008, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1377 09:31:26.503807 CH0 RK1: MR19=606, MR18=4008
1378 09:31:26.503860 CH0_RK1: MR19=0x606, MR18=0x4008, DQSOSC=393, MR23=63, INC=95, DEC=63
1379 09:31:26.503953 [RxdqsGatingPostProcess] freq 800
1380 09:31:26.504042 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 09:31:26.504135 Pre-setting of DQS Precalculation
1382 09:31:26.504195 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 09:31:26.504249 ==
1384 09:31:26.504302 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 09:31:26.504355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 09:31:26.504409 ==
1387 09:31:26.504462 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 09:31:26.504515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 09:31:26.504568 [CA 0] Center 36 (6~67) winsize 62
1390 09:31:26.504620 [CA 1] Center 36 (6~67) winsize 62
1391 09:31:26.504673 [CA 2] Center 34 (4~65) winsize 62
1392 09:31:26.504724 [CA 3] Center 34 (3~65) winsize 63
1393 09:31:26.504777 [CA 4] Center 34 (4~65) winsize 62
1394 09:31:26.504829 [CA 5] Center 33 (3~64) winsize 62
1395 09:31:26.504882
1396 09:31:26.504934 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1397 09:31:26.504987
1398 09:31:26.505039 [CATrainingPosCal] consider 1 rank data
1399 09:31:26.505091 u2DelayCellTimex100 = 270/100 ps
1400 09:31:26.505144 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1401 09:31:26.505196 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1402 09:31:26.505249 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1403 09:31:26.505301 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1404 09:31:26.505353 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1405 09:31:26.505405 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1406 09:31:26.505461
1407 09:31:26.505512 CA PerBit enable=1, Macro0, CA PI delay=33
1408 09:31:26.505565
1409 09:31:26.505615 [CBTSetCACLKResult] CA Dly = 33
1410 09:31:26.505668 CS Dly: 5 (0~36)
1411 09:31:26.505720 ==
1412 09:31:26.505773 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 09:31:26.505825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 09:31:26.505877 ==
1415 09:31:26.505931 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 09:31:26.505984 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 09:31:26.506036 [CA 0] Center 36 (6~67) winsize 62
1418 09:31:26.506088 [CA 1] Center 37 (6~68) winsize 63
1419 09:31:26.506140 [CA 2] Center 34 (4~65) winsize 62
1420 09:31:26.506225 [CA 3] Center 34 (3~65) winsize 63
1421 09:31:26.506292 [CA 4] Center 34 (4~65) winsize 62
1422 09:31:26.506344 [CA 5] Center 34 (4~65) winsize 62
1423 09:31:26.506395
1424 09:31:26.506447 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1425 09:31:26.506499
1426 09:31:26.506550 [CATrainingPosCal] consider 2 rank data
1427 09:31:26.506603 u2DelayCellTimex100 = 270/100 ps
1428 09:31:26.506655 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1429 09:31:26.506708 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1430 09:31:26.506760 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1431 09:31:26.506811 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1432 09:31:26.506864 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1433 09:31:26.506915 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1434 09:31:26.506967
1435 09:31:26.507018 CA PerBit enable=1, Macro0, CA PI delay=34
1436 09:31:26.507070
1437 09:31:26.507122 [CBTSetCACLKResult] CA Dly = 34
1438 09:31:26.507174 CS Dly: 6 (0~38)
1439 09:31:26.507226
1440 09:31:26.507278 ----->DramcWriteLeveling(PI) begin...
1441 09:31:26.507331 ==
1442 09:31:26.507384 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 09:31:26.507436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 09:31:26.507489 ==
1445 09:31:26.507541 Write leveling (Byte 0): 29 => 29
1446 09:31:26.507593 Write leveling (Byte 1): 29 => 29
1447 09:31:26.507645 DramcWriteLeveling(PI) end<-----
1448 09:31:26.507697
1449 09:31:26.507749 ==
1450 09:31:26.507801 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 09:31:26.507853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 09:31:26.507905 ==
1453 09:31:26.508161 [Gating] SW mode calibration
1454 09:31:26.508224 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 09:31:26.508280 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 09:31:26.508334 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1457 09:31:26.508387 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1458 09:31:26.508440 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 09:31:26.508493 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 09:31:26.508545 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 09:31:26.508598 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 09:31:26.508650 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 09:31:26.508703 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 09:31:26.508755 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 09:31:26.508808 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 09:31:26.508860 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 09:31:26.508913 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 09:31:26.508966 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 09:31:26.509019 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 09:31:26.509071 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 09:31:26.509124 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 09:31:26.509176 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1473 09:31:26.509228 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1474 09:31:26.509280 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1475 09:31:26.509333 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 09:31:26.509384 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 09:31:26.509437 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 09:31:26.509489 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 09:31:26.509542 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 09:31:26.509593 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 09:31:26.509649 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1482 09:31:26.509702 0 9 8 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 0)
1483 09:31:26.509754 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 09:31:26.509806 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 09:31:26.509858 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 09:31:26.509910 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 09:31:26.509962 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 09:31:26.510015 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 09:31:26.510068 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1490 09:31:26.510120 0 10 8 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
1491 09:31:26.510207 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 09:31:26.510276 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 09:31:26.510328 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 09:31:26.510381 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 09:31:26.510433 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 09:31:26.510486 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 09:31:26.510538 0 11 4 | B1->B0 | 2d2d 2525 | 0 0 | (0 0) (0 0)
1498 09:31:26.510590 0 11 8 | B1->B0 | 3e3d 3e3e | 1 1 | (1 1) (1 1)
1499 09:31:26.510642 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 09:31:26.510694 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 09:31:26.510746 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 09:31:26.510799 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 09:31:26.510851 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 09:31:26.510903 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 09:31:26.510955 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1506 09:31:26.511020 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1507 09:31:26.511074 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 09:31:26.511126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 09:31:26.511178 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 09:31:26.511231 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 09:31:26.511283 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 09:31:26.511336 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 09:31:26.511388 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 09:31:26.511439 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 09:31:26.511492 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 09:31:26.511544 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 09:31:26.511596 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 09:31:26.511649 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 09:31:26.511701 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 09:31:26.511753 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 09:31:26.511806 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 09:31:26.511858 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 09:31:26.511911 Total UI for P1: 0, mck2ui 16
1524 09:31:26.511964 best dqsien dly found for B0: ( 0, 14, 6)
1525 09:31:26.512016 Total UI for P1: 0, mck2ui 16
1526 09:31:26.512069 best dqsien dly found for B1: ( 0, 14, 6)
1527 09:31:26.512121 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1528 09:31:26.512174 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1529 09:31:26.512227
1530 09:31:26.512278 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1531 09:31:26.512331 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1532 09:31:26.512383 [Gating] SW calibration Done
1533 09:31:26.512436 ==
1534 09:31:26.512488 Dram Type= 6, Freq= 0, CH_1, rank 0
1535 09:31:26.512541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1536 09:31:26.512594 ==
1537 09:31:26.512646 RX Vref Scan: 0
1538 09:31:26.512697
1539 09:31:26.512749 RX Vref 0 -> 0, step: 1
1540 09:31:26.512801
1541 09:31:26.512852 RX Delay -130 -> 252, step: 16
1542 09:31:26.513100 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1543 09:31:26.513159 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1544 09:31:26.513212 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1545 09:31:26.513265 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1546 09:31:26.513317 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1547 09:31:26.513369 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1548 09:31:26.513421 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1549 09:31:26.513473 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1550 09:31:26.513525 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1551 09:31:26.513577 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1552 09:31:26.513630 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1553 09:31:26.513682 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1554 09:31:26.513734 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1555 09:31:26.513785 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1556 09:31:26.513837 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1557 09:31:26.513889 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1558 09:31:26.513941 ==
1559 09:31:26.513994 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 09:31:26.514046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 09:31:26.514099 ==
1562 09:31:26.514152 DQS Delay:
1563 09:31:26.514254 DQS0 = 0, DQS1 = 0
1564 09:31:26.514307 DQM Delay:
1565 09:31:26.514359 DQM0 = 86, DQM1 = 79
1566 09:31:26.514411 DQ Delay:
1567 09:31:26.514463 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1568 09:31:26.514515 DQ4 =77, DQ5 =101, DQ6 =101, DQ7 =85
1569 09:31:26.514567 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1570 09:31:26.514620 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1571 09:31:26.514672
1572 09:31:26.514723
1573 09:31:26.514774 ==
1574 09:31:26.514826 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 09:31:26.514878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 09:31:26.514930 ==
1577 09:31:26.514982
1578 09:31:26.515034
1579 09:31:26.515085 TX Vref Scan disable
1580 09:31:26.515136 == TX Byte 0 ==
1581 09:31:26.515188 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1582 09:31:26.515241 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1583 09:31:26.515293 == TX Byte 1 ==
1584 09:31:26.515345 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1585 09:31:26.515397 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1586 09:31:26.515449 ==
1587 09:31:26.515501 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 09:31:26.515553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 09:31:26.515605 ==
1590 09:31:26.515656 TX Vref=22, minBit 10, minWin=26, winSum=440
1591 09:31:26.515709 TX Vref=24, minBit 8, minWin=27, winSum=448
1592 09:31:26.515762 TX Vref=26, minBit 8, minWin=27, winSum=448
1593 09:31:26.515814 TX Vref=28, minBit 9, minWin=27, winSum=451
1594 09:31:26.515867 TX Vref=30, minBit 9, minWin=27, winSum=448
1595 09:31:26.515919 TX Vref=32, minBit 9, minWin=27, winSum=445
1596 09:31:26.515971 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 28
1597 09:31:26.516024
1598 09:31:26.516075 Final TX Range 1 Vref 28
1599 09:31:26.516127
1600 09:31:26.516178 ==
1601 09:31:26.516231 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 09:31:26.516283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 09:31:26.516335 ==
1604 09:31:26.516387
1605 09:31:26.516438
1606 09:31:26.516489 TX Vref Scan disable
1607 09:31:26.516541 == TX Byte 0 ==
1608 09:31:26.516592 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1609 09:31:26.516645 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1610 09:31:26.516697 == TX Byte 1 ==
1611 09:31:26.516749 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1612 09:31:26.516801 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1613 09:31:26.516853
1614 09:31:26.516921 [DATLAT]
1615 09:31:26.516974 Freq=800, CH1 RK0
1616 09:31:26.517027
1617 09:31:26.517079 DATLAT Default: 0xa
1618 09:31:26.517131 0, 0xFFFF, sum = 0
1619 09:31:26.517184 1, 0xFFFF, sum = 0
1620 09:31:26.517238 2, 0xFFFF, sum = 0
1621 09:31:26.517291 3, 0xFFFF, sum = 0
1622 09:31:26.517345 4, 0xFFFF, sum = 0
1623 09:31:26.517397 5, 0xFFFF, sum = 0
1624 09:31:26.517450 6, 0xFFFF, sum = 0
1625 09:31:26.517502 7, 0xFFFF, sum = 0
1626 09:31:26.517555 8, 0xFFFF, sum = 0
1627 09:31:26.517607 9, 0x0, sum = 1
1628 09:31:26.517690 10, 0x0, sum = 2
1629 09:31:26.517783 11, 0x0, sum = 3
1630 09:31:26.517863 12, 0x0, sum = 4
1631 09:31:26.517920 best_step = 10
1632 09:31:26.517974
1633 09:31:26.518026 ==
1634 09:31:26.518079 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 09:31:26.518133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 09:31:26.518222 ==
1637 09:31:26.518290 RX Vref Scan: 1
1638 09:31:26.518343
1639 09:31:26.518394 Set Vref Range= 32 -> 127
1640 09:31:26.518446
1641 09:31:26.518499 RX Vref 32 -> 127, step: 1
1642 09:31:26.518551
1643 09:31:26.518603 RX Delay -95 -> 252, step: 8
1644 09:31:26.518656
1645 09:31:26.518708 Set Vref, RX VrefLevel [Byte0]: 32
1646 09:31:26.518762 [Byte1]: 32
1647 09:31:26.518815
1648 09:31:26.518867 Set Vref, RX VrefLevel [Byte0]: 33
1649 09:31:26.518920 [Byte1]: 33
1650 09:31:26.518971
1651 09:31:26.519024 Set Vref, RX VrefLevel [Byte0]: 34
1652 09:31:26.519076 [Byte1]: 34
1653 09:31:26.519128
1654 09:31:26.519180 Set Vref, RX VrefLevel [Byte0]: 35
1655 09:31:26.519232 [Byte1]: 35
1656 09:31:26.519284
1657 09:31:26.519336 Set Vref, RX VrefLevel [Byte0]: 36
1658 09:31:26.519389 [Byte1]: 36
1659 09:31:26.519441
1660 09:31:26.519493 Set Vref, RX VrefLevel [Byte0]: 37
1661 09:31:26.519545 [Byte1]: 37
1662 09:31:26.519597
1663 09:31:26.519649 Set Vref, RX VrefLevel [Byte0]: 38
1664 09:31:26.519701 [Byte1]: 38
1665 09:31:26.519753
1666 09:31:26.519805 Set Vref, RX VrefLevel [Byte0]: 39
1667 09:31:26.519857 [Byte1]: 39
1668 09:31:26.519908
1669 09:31:26.519960 Set Vref, RX VrefLevel [Byte0]: 40
1670 09:31:26.520012 [Byte1]: 40
1671 09:31:26.520064
1672 09:31:26.520116 Set Vref, RX VrefLevel [Byte0]: 41
1673 09:31:26.520168 [Byte1]: 41
1674 09:31:26.520219
1675 09:31:26.520271 Set Vref, RX VrefLevel [Byte0]: 42
1676 09:31:26.520323 [Byte1]: 42
1677 09:31:26.520375
1678 09:31:26.520427 Set Vref, RX VrefLevel [Byte0]: 43
1679 09:31:26.520479 [Byte1]: 43
1680 09:31:26.520531
1681 09:31:26.520582 Set Vref, RX VrefLevel [Byte0]: 44
1682 09:31:26.520634 [Byte1]: 44
1683 09:31:26.520685
1684 09:31:26.520737 Set Vref, RX VrefLevel [Byte0]: 45
1685 09:31:26.520789 [Byte1]: 45
1686 09:31:26.520841
1687 09:31:26.520893 Set Vref, RX VrefLevel [Byte0]: 46
1688 09:31:26.520946 [Byte1]: 46
1689 09:31:26.520998
1690 09:31:26.521049 Set Vref, RX VrefLevel [Byte0]: 47
1691 09:31:26.521101 [Byte1]: 47
1692 09:31:26.521153
1693 09:31:26.521204 Set Vref, RX VrefLevel [Byte0]: 48
1694 09:31:26.521256 [Byte1]: 48
1695 09:31:26.521308
1696 09:31:26.521359 Set Vref, RX VrefLevel [Byte0]: 49
1697 09:31:26.521617 [Byte1]: 49
1698 09:31:26.521675
1699 09:31:26.521728 Set Vref, RX VrefLevel [Byte0]: 50
1700 09:31:26.521780 [Byte1]: 50
1701 09:31:26.521833
1702 09:31:26.521885 Set Vref, RX VrefLevel [Byte0]: 51
1703 09:31:26.521938 [Byte1]: 51
1704 09:31:26.521989
1705 09:31:26.522041 Set Vref, RX VrefLevel [Byte0]: 52
1706 09:31:26.522093 [Byte1]: 52
1707 09:31:26.522145
1708 09:31:26.522237 Set Vref, RX VrefLevel [Byte0]: 53
1709 09:31:26.522290 [Byte1]: 53
1710 09:31:26.522342
1711 09:31:26.522394 Set Vref, RX VrefLevel [Byte0]: 54
1712 09:31:26.522446 [Byte1]: 54
1713 09:31:26.522498
1714 09:31:26.522550 Set Vref, RX VrefLevel [Byte0]: 55
1715 09:31:26.522602 [Byte1]: 55
1716 09:31:26.522654
1717 09:31:26.522706 Set Vref, RX VrefLevel [Byte0]: 56
1718 09:31:26.522758 [Byte1]: 56
1719 09:31:26.522810
1720 09:31:26.522862 Set Vref, RX VrefLevel [Byte0]: 57
1721 09:31:26.522914 [Byte1]: 57
1722 09:31:26.522967
1723 09:31:26.523019 Set Vref, RX VrefLevel [Byte0]: 58
1724 09:31:26.523071 [Byte1]: 58
1725 09:31:26.523123
1726 09:31:26.523174 Set Vref, RX VrefLevel [Byte0]: 59
1727 09:31:26.523227 [Byte1]: 59
1728 09:31:26.523278
1729 09:31:26.523330 Set Vref, RX VrefLevel [Byte0]: 60
1730 09:31:26.523382 [Byte1]: 60
1731 09:31:26.523435
1732 09:31:26.523486 Set Vref, RX VrefLevel [Byte0]: 61
1733 09:31:26.523538 [Byte1]: 61
1734 09:31:26.523590
1735 09:31:26.523642 Set Vref, RX VrefLevel [Byte0]: 62
1736 09:31:26.523695 [Byte1]: 62
1737 09:31:26.523746
1738 09:31:26.523798 Set Vref, RX VrefLevel [Byte0]: 63
1739 09:31:26.523849 [Byte1]: 63
1740 09:31:26.523901
1741 09:31:26.523953 Set Vref, RX VrefLevel [Byte0]: 64
1742 09:31:26.524005 [Byte1]: 64
1743 09:31:26.524057
1744 09:31:26.524109 Set Vref, RX VrefLevel [Byte0]: 65
1745 09:31:26.524161 [Byte1]: 65
1746 09:31:26.524213
1747 09:31:26.524264 Set Vref, RX VrefLevel [Byte0]: 66
1748 09:31:26.524316 [Byte1]: 66
1749 09:31:26.524368
1750 09:31:26.524419 Set Vref, RX VrefLevel [Byte0]: 67
1751 09:31:26.524470 [Byte1]: 67
1752 09:31:26.524522
1753 09:31:26.524573 Set Vref, RX VrefLevel [Byte0]: 68
1754 09:31:26.524625 [Byte1]: 68
1755 09:31:26.524677
1756 09:31:26.524729 Set Vref, RX VrefLevel [Byte0]: 69
1757 09:31:26.524781 [Byte1]: 69
1758 09:31:26.524832
1759 09:31:26.524884 Set Vref, RX VrefLevel [Byte0]: 70
1760 09:31:26.524936 [Byte1]: 70
1761 09:31:26.524988
1762 09:31:26.525039 Set Vref, RX VrefLevel [Byte0]: 71
1763 09:31:26.525091 [Byte1]: 71
1764 09:31:26.525144
1765 09:31:26.525195 Set Vref, RX VrefLevel [Byte0]: 72
1766 09:31:26.525248 [Byte1]: 72
1767 09:31:26.525300
1768 09:31:26.525351 Set Vref, RX VrefLevel [Byte0]: 73
1769 09:31:26.525403 [Byte1]: 73
1770 09:31:26.525456
1771 09:31:26.525507 Set Vref, RX VrefLevel [Byte0]: 74
1772 09:31:26.525560 [Byte1]: 74
1773 09:31:26.525612
1774 09:31:26.525663 Set Vref, RX VrefLevel [Byte0]: 75
1775 09:31:26.525715 [Byte1]: 75
1776 09:31:26.525769
1777 09:31:26.525833 Set Vref, RX VrefLevel [Byte0]: 76
1778 09:31:26.525886 [Byte1]: 76
1779 09:31:26.525938
1780 09:31:26.525990 Set Vref, RX VrefLevel [Byte0]: 77
1781 09:31:26.526043 [Byte1]: 77
1782 09:31:26.526095
1783 09:31:26.526146 Set Vref, RX VrefLevel [Byte0]: 78
1784 09:31:26.526204 [Byte1]: 78
1785 09:31:26.526256
1786 09:31:26.526308 Final RX Vref Byte 0 = 55 to rank0
1787 09:31:26.526360 Final RX Vref Byte 1 = 66 to rank0
1788 09:31:26.526413 Final RX Vref Byte 0 = 55 to rank1
1789 09:31:26.526465 Final RX Vref Byte 1 = 66 to rank1==
1790 09:31:26.526518 Dram Type= 6, Freq= 0, CH_1, rank 0
1791 09:31:26.526570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 09:31:26.526623 ==
1793 09:31:26.526676 DQS Delay:
1794 09:31:26.526728 DQS0 = 0, DQS1 = 0
1795 09:31:26.526780 DQM Delay:
1796 09:31:26.526832 DQM0 = 86, DQM1 = 78
1797 09:31:26.526883 DQ Delay:
1798 09:31:26.526935 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1799 09:31:26.526987 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1800 09:31:26.527040 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1801 09:31:26.527092 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1802 09:31:26.527144
1803 09:31:26.527196
1804 09:31:26.527248 [DQSOSCAuto] RK0, (LSB)MR18= 0x301d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1805 09:31:26.527301 CH1 RK0: MR19=606, MR18=301D
1806 09:31:26.527353 CH1_RK0: MR19=0x606, MR18=0x301D, DQSOSC=397, MR23=63, INC=93, DEC=62
1807 09:31:26.527405
1808 09:31:26.527460 ----->DramcWriteLeveling(PI) begin...
1809 09:31:26.527513 ==
1810 09:31:26.527565 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 09:31:26.527617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 09:31:26.527670 ==
1813 09:31:26.527722 Write leveling (Byte 0): 29 => 29
1814 09:31:26.527775 Write leveling (Byte 1): 28 => 28
1815 09:31:26.527826 DramcWriteLeveling(PI) end<-----
1816 09:31:26.527878
1817 09:31:26.527929 ==
1818 09:31:26.527981 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 09:31:26.528033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 09:31:26.528086 ==
1821 09:31:26.528138 [Gating] SW mode calibration
1822 09:31:26.528189 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1823 09:31:26.528242 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1824 09:31:26.528294 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1825 09:31:26.528347 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1826 09:31:26.528399 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 09:31:26.528452 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 09:31:26.528504 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 09:31:26.528556 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 09:31:26.528607 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 09:31:26.528660 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 09:31:26.528712 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 09:31:26.528765 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 09:31:26.528817 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 09:31:26.528869 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 09:31:26.528921 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 09:31:26.529179 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 09:31:26.529243 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 09:31:26.529297 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 09:31:26.529350 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 09:31:26.529403 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1842 09:31:26.529455 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1843 09:31:26.529508 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 09:31:26.529560 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 09:31:26.529612 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 09:31:26.529665 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 09:31:26.529717 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 09:31:26.529770 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 09:31:26.529823 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 09:31:26.529875 0 9 8 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (0 0)
1851 09:31:26.529928 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 09:31:26.529980 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 09:31:26.530032 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 09:31:26.530084 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 09:31:26.530137 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 09:31:26.530224 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1857 09:31:26.530291 0 10 4 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 0)
1858 09:31:26.530343 0 10 8 | B1->B0 | 2424 2c2c | 0 1 | (0 0) (1 0)
1859 09:31:26.530395 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 09:31:26.530447 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 09:31:26.530500 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 09:31:26.530553 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 09:31:26.530604 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 09:31:26.530656 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 09:31:26.530709 0 11 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1866 09:31:26.530760 0 11 8 | B1->B0 | 3b3b 3939 | 0 1 | (0 0) (0 0)
1867 09:31:26.530884 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 09:31:26.530966 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 09:31:26.531019 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 09:31:26.531070 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 09:31:26.531123 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 09:31:26.531175 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 09:31:26.531227 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1874 09:31:26.531279 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1875 09:31:26.531331 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 09:31:26.531383 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 09:31:26.531435 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 09:31:26.531487 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 09:31:26.531539 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 09:31:26.531591 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 09:31:26.531644 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 09:31:26.531697 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 09:31:26.531749 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 09:31:26.531803 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 09:31:26.531856 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 09:31:26.531908 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 09:31:26.531960 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 09:31:26.532012 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 09:31:26.532064 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1890 09:31:26.532116 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1891 09:31:26.532168 Total UI for P1: 0, mck2ui 16
1892 09:31:26.532221 best dqsien dly found for B1: ( 0, 14, 4)
1893 09:31:26.532274 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 09:31:26.532326 Total UI for P1: 0, mck2ui 16
1895 09:31:26.532378 best dqsien dly found for B0: ( 0, 14, 6)
1896 09:31:26.532431 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1897 09:31:26.532483 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1898 09:31:26.532535
1899 09:31:26.532587 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1900 09:31:26.532639 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1901 09:31:26.532691 [Gating] SW calibration Done
1902 09:31:26.532744 ==
1903 09:31:26.532796 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 09:31:26.532848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 09:31:26.532901 ==
1906 09:31:26.532952 RX Vref Scan: 0
1907 09:31:26.533004
1908 09:31:26.533055 RX Vref 0 -> 0, step: 1
1909 09:31:26.533107
1910 09:31:26.533159 RX Delay -130 -> 252, step: 16
1911 09:31:26.533211 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1912 09:31:26.533264 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1913 09:31:26.533316 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1914 09:31:26.533368 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1915 09:31:26.533420 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1916 09:31:26.533472 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1917 09:31:26.533524 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1918 09:31:26.828658 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1919 09:31:26.829145 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1920 09:31:26.829477 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1921 09:31:26.829787 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1922 09:31:26.830089 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1923 09:31:26.830441 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1924 09:31:26.830773 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1925 09:31:26.831113 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1926 09:31:26.831400 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1927 09:31:26.831679 ==
1928 09:31:26.831960 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 09:31:26.832630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 09:31:26.832943 ==
1931 09:31:26.833226 DQS Delay:
1932 09:31:26.833499 DQS0 = 0, DQS1 = 0
1933 09:31:26.833894 DQM Delay:
1934 09:31:26.834217 DQM0 = 86, DQM1 = 77
1935 09:31:26.834505 DQ Delay:
1936 09:31:26.834888 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1937 09:31:26.835258 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1938 09:31:26.835543 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1939 09:31:26.835818 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1940 09:31:26.836093
1941 09:31:26.836368
1942 09:31:26.836643 ==
1943 09:31:26.836915 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 09:31:26.837192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 09:31:26.837580 ==
1946 09:31:26.837860
1947 09:31:26.838129
1948 09:31:26.838443 TX Vref Scan disable
1949 09:31:26.838717 == TX Byte 0 ==
1950 09:31:26.838988 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1951 09:31:26.839265 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1952 09:31:26.839540 == TX Byte 1 ==
1953 09:31:26.839824 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1954 09:31:26.840117 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1955 09:31:26.840479 ==
1956 09:31:26.840762 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 09:31:26.841040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 09:31:26.841315 ==
1959 09:31:26.841587 TX Vref=22, minBit 9, minWin=26, winSum=445
1960 09:31:26.841865 TX Vref=24, minBit 8, minWin=27, winSum=445
1961 09:31:26.842142 TX Vref=26, minBit 8, minWin=27, winSum=448
1962 09:31:26.842452 TX Vref=28, minBit 8, minWin=27, winSum=449
1963 09:31:26.842728 TX Vref=30, minBit 0, minWin=28, winSum=450
1964 09:31:26.842999 TX Vref=32, minBit 8, minWin=27, winSum=451
1965 09:31:26.843272 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 30
1966 09:31:26.843546
1967 09:31:26.843827 Final TX Range 1 Vref 30
1968 09:31:26.844195
1969 09:31:26.844472 ==
1970 09:31:26.844744 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 09:31:26.845017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 09:31:26.845294 ==
1973 09:31:26.845565
1974 09:31:26.845833
1975 09:31:26.846101 TX Vref Scan disable
1976 09:31:26.846430 == TX Byte 0 ==
1977 09:31:26.846706 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1978 09:31:26.846984 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1979 09:31:26.847370 == TX Byte 1 ==
1980 09:31:26.847577 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1981 09:31:26.847777 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1982 09:31:26.847974
1983 09:31:26.848171 [DATLAT]
1984 09:31:26.848365 Freq=800, CH1 RK1
1985 09:31:26.848563
1986 09:31:26.848757 DATLAT Default: 0xa
1987 09:31:26.848951 0, 0xFFFF, sum = 0
1988 09:31:26.849151 1, 0xFFFF, sum = 0
1989 09:31:26.849348 2, 0xFFFF, sum = 0
1990 09:31:26.849545 3, 0xFFFF, sum = 0
1991 09:31:26.849745 4, 0xFFFF, sum = 0
1992 09:31:26.849943 5, 0xFFFF, sum = 0
1993 09:31:26.850274 6, 0xFFFF, sum = 0
1994 09:31:26.850485 7, 0xFFFF, sum = 0
1995 09:31:26.850685 8, 0xFFFF, sum = 0
1996 09:31:26.850884 9, 0x0, sum = 1
1997 09:31:26.851082 10, 0x0, sum = 2
1998 09:31:26.851279 11, 0x0, sum = 3
1999 09:31:26.851479 12, 0x0, sum = 4
2000 09:31:26.851676 best_step = 10
2001 09:31:26.851872
2002 09:31:26.852069 ==
2003 09:31:26.852265 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 09:31:26.852444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 09:31:26.852592 ==
2006 09:31:26.852738 RX Vref Scan: 0
2007 09:31:26.852884
2008 09:31:26.853030 RX Vref 0 -> 0, step: 1
2009 09:31:26.853176
2010 09:31:26.853321 RX Delay -111 -> 252, step: 8
2011 09:31:26.853483 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2012 09:31:26.853666 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2013 09:31:26.853816 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2014 09:31:26.853964 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2015 09:31:26.854111 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2016 09:31:26.854275 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2017 09:31:26.854423 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2018 09:31:26.854571 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2019 09:31:26.854720 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2020 09:31:26.854864 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2021 09:31:26.855010 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2022 09:31:26.855157 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2023 09:31:26.855304 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2024 09:31:26.855449 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2025 09:31:26.855658 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2026 09:31:26.855894 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2027 09:31:26.856048 ==
2028 09:31:26.856199 Dram Type= 6, Freq= 0, CH_1, rank 1
2029 09:31:26.856346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2030 09:31:26.856495 ==
2031 09:31:26.856641 DQS Delay:
2032 09:31:26.856787 DQS0 = 0, DQS1 = 0
2033 09:31:26.856994 DQM Delay:
2034 09:31:26.857147 DQM0 = 87, DQM1 = 79
2035 09:31:26.857306 DQ Delay:
2036 09:31:26.857427 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2037 09:31:26.857547 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2038 09:31:26.857666 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =72
2039 09:31:26.857785 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2040 09:31:26.858014
2041 09:31:26.858213
2042 09:31:26.858340 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2043 09:31:26.858465 CH1 RK1: MR19=606, MR18=1A11
2044 09:31:26.858586 CH1_RK1: MR19=0x606, MR18=0x1A11, DQSOSC=403, MR23=63, INC=90, DEC=60
2045 09:31:26.858707 [RxdqsGatingPostProcess] freq 800
2046 09:31:26.858826 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2047 09:31:26.858947 Pre-setting of DQS Precalculation
2048 09:31:26.859066 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2049 09:31:26.859186 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2050 09:31:26.859307 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2051 09:31:26.859428
2052 09:31:26.859547
2053 09:31:26.859664 [Calibration Summary] 1600 Mbps
2054 09:31:26.859784 CH 0, Rank 0
2055 09:31:26.859901 SW Impedance : PASS
2056 09:31:26.860019 DUTY Scan : NO K
2057 09:31:26.860138 ZQ Calibration : PASS
2058 09:31:26.860290 Jitter Meter : NO K
2059 09:31:26.860418 CBT Training : PASS
2060 09:31:26.860536 Write leveling : PASS
2061 09:31:26.860655 RX DQS gating : PASS
2062 09:31:26.860772 RX DQ/DQS(RDDQC) : PASS
2063 09:31:26.860890 TX DQ/DQS : PASS
2064 09:31:26.861010 RX DATLAT : PASS
2065 09:31:26.861128 RX DQ/DQS(Engine): PASS
2066 09:31:26.861245 TX OE : NO K
2067 09:31:26.861364 All Pass.
2068 09:31:26.861481
2069 09:31:26.861597 CH 0, Rank 1
2070 09:31:26.861714 SW Impedance : PASS
2071 09:31:26.861832 DUTY Scan : NO K
2072 09:31:26.861950 ZQ Calibration : PASS
2073 09:31:26.862067 Jitter Meter : NO K
2074 09:31:26.862207 CBT Training : PASS
2075 09:31:26.862405 Write leveling : PASS
2076 09:31:26.862747 RX DQS gating : PASS
2077 09:31:26.862857 RX DQ/DQS(RDDQC) : PASS
2078 09:31:26.862958 TX DQ/DQS : PASS
2079 09:31:26.863058 RX DATLAT : PASS
2080 09:31:26.863157 RX DQ/DQS(Engine): PASS
2081 09:31:26.863309 TX OE : NO K
2082 09:31:26.863470 All Pass.
2083 09:31:26.863590
2084 09:31:26.863690 CH 1, Rank 0
2085 09:31:26.863790 SW Impedance : PASS
2086 09:31:26.863889 DUTY Scan : NO K
2087 09:31:26.863988 ZQ Calibration : PASS
2088 09:31:26.864086 Jitter Meter : NO K
2089 09:31:26.864185 CBT Training : PASS
2090 09:31:26.864284 Write leveling : PASS
2091 09:31:26.864383 RX DQS gating : PASS
2092 09:31:26.864482 RX DQ/DQS(RDDQC) : PASS
2093 09:31:26.864582 TX DQ/DQS : PASS
2094 09:31:26.864681 RX DATLAT : PASS
2095 09:31:26.864778 RX DQ/DQS(Engine): PASS
2096 09:31:26.864876 TX OE : NO K
2097 09:31:26.864975 All Pass.
2098 09:31:26.865073
2099 09:31:26.865170 CH 1, Rank 1
2100 09:31:26.865269 SW Impedance : PASS
2101 09:31:26.865366 DUTY Scan : NO K
2102 09:31:26.865464 ZQ Calibration : PASS
2103 09:31:26.865562 Jitter Meter : NO K
2104 09:31:26.865660 CBT Training : PASS
2105 09:31:26.865758 Write leveling : PASS
2106 09:31:26.865857 RX DQS gating : PASS
2107 09:31:26.865954 RX DQ/DQS(RDDQC) : PASS
2108 09:31:26.866051 TX DQ/DQS : PASS
2109 09:31:26.866150 RX DATLAT : PASS
2110 09:31:26.866264 RX DQ/DQS(Engine): PASS
2111 09:31:26.866363 TX OE : NO K
2112 09:31:26.866462 All Pass.
2113 09:31:26.866560
2114 09:31:26.866658 DramC Write-DBI off
2115 09:31:26.866756 PER_BANK_REFRESH: Hybrid Mode
2116 09:31:26.866853 TX_TRACKING: ON
2117 09:31:26.866990 [GetDramInforAfterCalByMRR] Vendor 6.
2118 09:31:26.867094 [GetDramInforAfterCalByMRR] Revision 606.
2119 09:31:26.867193 [GetDramInforAfterCalByMRR] Revision 2 0.
2120 09:31:26.867291 MR0 0x3b3b
2121 09:31:26.867392 MR8 0x5151
2122 09:31:26.867477 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 09:31:26.867561
2124 09:31:26.867644 MR0 0x3b3b
2125 09:31:26.867727 MR8 0x5151
2126 09:31:26.867811 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2127 09:31:26.867895
2128 09:31:26.867979 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2129 09:31:26.868065 [FAST_K] Save calibration result to emmc
2130 09:31:26.868150 [FAST_K] Save calibration result to emmc
2131 09:31:26.868235 dram_init: config_dvfs: 1
2132 09:31:26.868319 dramc_set_vcore_voltage set vcore to 662500
2133 09:31:26.868404 Read voltage for 1200, 2
2134 09:31:26.868489 Vio18 = 0
2135 09:31:26.868572 Vcore = 662500
2136 09:31:26.868657 Vdram = 0
2137 09:31:26.868741 Vddq = 0
2138 09:31:26.868824 Vmddr = 0
2139 09:31:26.868907 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2140 09:31:26.868991 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2141 09:31:26.869076 MEM_TYPE=3, freq_sel=15
2142 09:31:26.869160 sv_algorithm_assistance_LP4_1600
2143 09:31:26.869245 ============ PULL DRAM RESETB DOWN ============
2144 09:31:26.869331 ========== PULL DRAM RESETB DOWN end =========
2145 09:31:26.869417 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2146 09:31:26.869501 ===================================
2147 09:31:26.869586 LPDDR4 DRAM CONFIGURATION
2148 09:31:26.869670 ===================================
2149 09:31:26.869755 EX_ROW_EN[0] = 0x0
2150 09:31:26.869838 EX_ROW_EN[1] = 0x0
2151 09:31:26.869922 LP4Y_EN = 0x0
2152 09:31:26.870007 WORK_FSP = 0x0
2153 09:31:26.870090 WL = 0x4
2154 09:31:26.870185 RL = 0x4
2155 09:31:26.870281 BL = 0x2
2156 09:31:26.870386 RPST = 0x0
2157 09:31:26.870472 RD_PRE = 0x0
2158 09:31:26.870556 WR_PRE = 0x1
2159 09:31:26.870640 WR_PST = 0x0
2160 09:31:26.870725 DBI_WR = 0x0
2161 09:31:26.870809 DBI_RD = 0x0
2162 09:31:26.870894 OTF = 0x1
2163 09:31:26.870979 ===================================
2164 09:31:26.871065 ===================================
2165 09:31:26.871150 ANA top config
2166 09:31:26.871235 ===================================
2167 09:31:26.871320 DLL_ASYNC_EN = 0
2168 09:31:26.871405 ALL_SLAVE_EN = 0
2169 09:31:26.871489 NEW_RANK_MODE = 1
2170 09:31:26.871575 DLL_IDLE_MODE = 1
2171 09:31:26.871659 LP45_APHY_COMB_EN = 1
2172 09:31:26.871743 TX_ODT_DIS = 1
2173 09:31:26.871828 NEW_8X_MODE = 1
2174 09:31:26.871914 ===================================
2175 09:31:26.871998 ===================================
2176 09:31:26.872084 data_rate = 2400
2177 09:31:26.872169 CKR = 1
2178 09:31:26.872254 DQ_P2S_RATIO = 8
2179 09:31:26.872345 ===================================
2180 09:31:26.872420 CA_P2S_RATIO = 8
2181 09:31:26.872494 DQ_CA_OPEN = 0
2182 09:31:26.872569 DQ_SEMI_OPEN = 0
2183 09:31:26.872642 CA_SEMI_OPEN = 0
2184 09:31:26.872716 CA_FULL_RATE = 0
2185 09:31:26.872790 DQ_CKDIV4_EN = 0
2186 09:31:26.872864 CA_CKDIV4_EN = 0
2187 09:31:26.872937 CA_PREDIV_EN = 0
2188 09:31:26.873011 PH8_DLY = 17
2189 09:31:26.873085 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2190 09:31:26.873159 DQ_AAMCK_DIV = 4
2191 09:31:26.873263 CA_AAMCK_DIV = 4
2192 09:31:26.873341 CA_ADMCK_DIV = 4
2193 09:31:26.873415 DQ_TRACK_CA_EN = 0
2194 09:31:26.873490 CA_PICK = 1200
2195 09:31:26.873564 CA_MCKIO = 1200
2196 09:31:26.873639 MCKIO_SEMI = 0
2197 09:31:26.873713 PLL_FREQ = 2366
2198 09:31:26.873787 DQ_UI_PI_RATIO = 32
2199 09:31:26.873862 CA_UI_PI_RATIO = 0
2200 09:31:26.873936 ===================================
2201 09:31:26.874011 ===================================
2202 09:31:26.874085 memory_type:LPDDR4
2203 09:31:26.874166 GP_NUM : 10
2204 09:31:26.874246 SRAM_EN : 1
2205 09:31:26.874320 MD32_EN : 0
2206 09:31:26.874395 ===================================
2207 09:31:26.874470 [ANA_INIT] >>>>>>>>>>>>>>
2208 09:31:26.874545 <<<<<< [CONFIGURE PHASE]: ANA_TX
2209 09:31:26.874620 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2210 09:31:26.874695 ===================================
2211 09:31:26.874770 data_rate = 2400,PCW = 0X5b00
2212 09:31:26.874844 ===================================
2213 09:31:26.874918 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2214 09:31:26.874993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2215 09:31:26.875068 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2216 09:31:26.875143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2217 09:31:26.875218 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2218 09:31:26.875501 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2219 09:31:26.875585 [ANA_INIT] flow start
2220 09:31:26.875661 [ANA_INIT] PLL >>>>>>>>
2221 09:31:26.875736 [ANA_INIT] PLL <<<<<<<<
2222 09:31:26.875811 [ANA_INIT] MIDPI >>>>>>>>
2223 09:31:26.875885 [ANA_INIT] MIDPI <<<<<<<<
2224 09:31:26.875958 [ANA_INIT] DLL >>>>>>>>
2225 09:31:26.876033 [ANA_INIT] DLL <<<<<<<<
2226 09:31:26.876106 [ANA_INIT] flow end
2227 09:31:26.876180 ============ LP4 DIFF to SE enter ============
2228 09:31:26.876255 ============ LP4 DIFF to SE exit ============
2229 09:31:26.876329 [ANA_INIT] <<<<<<<<<<<<<
2230 09:31:26.876403 [Flow] Enable top DCM control >>>>>
2231 09:31:26.876478 [Flow] Enable top DCM control <<<<<
2232 09:31:26.876552 Enable DLL master slave shuffle
2233 09:31:26.876627 ==============================================================
2234 09:31:26.876732 Gating Mode config
2235 09:31:26.876810 ==============================================================
2236 09:31:26.876886 Config description:
2237 09:31:26.876960 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2238 09:31:26.877036 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2239 09:31:26.877112 SELPH_MODE 0: By rank 1: By Phase
2240 09:31:26.877187 ==============================================================
2241 09:31:26.877262 GAT_TRACK_EN = 1
2242 09:31:26.877348 RX_GATING_MODE = 2
2243 09:31:26.877414 RX_GATING_TRACK_MODE = 2
2244 09:31:26.877481 SELPH_MODE = 1
2245 09:31:26.877547 PICG_EARLY_EN = 1
2246 09:31:26.877613 VALID_LAT_VALUE = 1
2247 09:31:26.877679 ==============================================================
2248 09:31:26.877746 Enter into Gating configuration >>>>
2249 09:31:26.877812 Exit from Gating configuration <<<<
2250 09:31:26.877879 Enter into DVFS_PRE_config >>>>>
2251 09:31:26.877946 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2252 09:31:26.878014 Exit from DVFS_PRE_config <<<<<
2253 09:31:26.878080 Enter into PICG configuration >>>>
2254 09:31:26.878146 Exit from PICG configuration <<<<
2255 09:31:26.878224 [RX_INPUT] configuration >>>>>
2256 09:31:26.878292 [RX_INPUT] configuration <<<<<
2257 09:31:26.878358 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2258 09:31:26.878426 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2259 09:31:26.878492 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 09:31:26.878592 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 09:31:26.878680 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2262 09:31:26.878749 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2263 09:31:26.878817 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2264 09:31:26.878884 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2265 09:31:26.878951 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2266 09:31:26.879017 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2267 09:31:26.879083 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2268 09:31:26.879150 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2269 09:31:26.879216 ===================================
2270 09:31:26.879284 LPDDR4 DRAM CONFIGURATION
2271 09:31:26.879349 ===================================
2272 09:31:26.879416 EX_ROW_EN[0] = 0x0
2273 09:31:26.879482 EX_ROW_EN[1] = 0x0
2274 09:31:26.879548 LP4Y_EN = 0x0
2275 09:31:26.879614 WORK_FSP = 0x0
2276 09:31:26.879679 WL = 0x4
2277 09:31:26.879745 RL = 0x4
2278 09:31:26.879811 BL = 0x2
2279 09:31:26.879876 RPST = 0x0
2280 09:31:26.879969 RD_PRE = 0x0
2281 09:31:26.880038 WR_PRE = 0x1
2282 09:31:26.880105 WR_PST = 0x0
2283 09:31:26.880171 DBI_WR = 0x0
2284 09:31:26.880237 DBI_RD = 0x0
2285 09:31:26.880302 OTF = 0x1
2286 09:31:26.880369 ===================================
2287 09:31:26.880436 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2288 09:31:26.880503 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2289 09:31:26.880569 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2290 09:31:26.880636 ===================================
2291 09:31:26.880703 LPDDR4 DRAM CONFIGURATION
2292 09:31:26.880769 ===================================
2293 09:31:26.880835 EX_ROW_EN[0] = 0x10
2294 09:31:26.880901 EX_ROW_EN[1] = 0x0
2295 09:31:26.880967 LP4Y_EN = 0x0
2296 09:31:26.881032 WORK_FSP = 0x0
2297 09:31:26.881097 WL = 0x4
2298 09:31:26.881162 RL = 0x4
2299 09:31:26.881227 BL = 0x2
2300 09:31:26.881292 RPST = 0x0
2301 09:31:26.881357 RD_PRE = 0x0
2302 09:31:26.881422 WR_PRE = 0x1
2303 09:31:26.881488 WR_PST = 0x0
2304 09:31:26.881553 DBI_WR = 0x0
2305 09:31:26.881618 DBI_RD = 0x0
2306 09:31:26.881682 OTF = 0x1
2307 09:31:26.881763 ===================================
2308 09:31:26.881832 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2309 09:31:26.881898 ==
2310 09:31:26.881963 Dram Type= 6, Freq= 0, CH_0, rank 0
2311 09:31:26.882030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2312 09:31:26.882096 ==
2313 09:31:26.882169 [Duty_Offset_Calibration]
2314 09:31:26.882238 B0:1 B1:-1 CA:0
2315 09:31:26.882304
2316 09:31:26.882378 [DutyScan_Calibration_Flow] k_type=0
2317 09:31:26.882438
2318 09:31:26.882496 ==CLK 0==
2319 09:31:26.882555 Final CLK duty delay cell = 0
2320 09:31:26.882615 [0] MAX Duty = 5094%(X100), DQS PI = 16
2321 09:31:26.882675 [0] MIN Duty = 4875%(X100), DQS PI = 8
2322 09:31:26.882735 [0] AVG Duty = 4984%(X100)
2323 09:31:26.882794
2324 09:31:26.882854 CH0 CLK Duty spec in!! Max-Min= 219%
2325 09:31:26.882913 [DutyScan_Calibration_Flow] ====Done====
2326 09:31:26.882972
2327 09:31:26.883029 [DutyScan_Calibration_Flow] k_type=1
2328 09:31:26.883088
2329 09:31:26.883146 ==DQS 0 ==
2330 09:31:26.883222 Final DQS duty delay cell = -4
2331 09:31:26.883287 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2332 09:31:26.883347 [-4] MIN Duty = 4875%(X100), DQS PI = 44
2333 09:31:26.883406 [-4] AVG Duty = 4968%(X100)
2334 09:31:26.883465
2335 09:31:26.883524 ==DQS 1 ==
2336 09:31:26.883583 Final DQS duty delay cell = 0
2337 09:31:26.883844 [0] MAX Duty = 5124%(X100), DQS PI = 6
2338 09:31:26.883913 [0] MIN Duty = 5000%(X100), DQS PI = 20
2339 09:31:26.883973 [0] AVG Duty = 5062%(X100)
2340 09:31:26.884034
2341 09:31:26.884104 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2342 09:31:26.884167
2343 09:31:26.884227 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2344 09:31:26.884287 [DutyScan_Calibration_Flow] ====Done====
2345 09:31:26.884347
2346 09:31:26.884405 [DutyScan_Calibration_Flow] k_type=3
2347 09:31:26.884464
2348 09:31:26.884523 ==DQM 0 ==
2349 09:31:26.884583 Final DQM duty delay cell = 0
2350 09:31:26.884643 [0] MAX Duty = 5062%(X100), DQS PI = 20
2351 09:31:26.884703 [0] MIN Duty = 4907%(X100), DQS PI = 6
2352 09:31:26.884763 [0] AVG Duty = 4984%(X100)
2353 09:31:26.884823
2354 09:31:26.884881 ==DQM 1 ==
2355 09:31:26.884941 Final DQM duty delay cell = 4
2356 09:31:26.884999 [4] MAX Duty = 5187%(X100), DQS PI = 14
2357 09:31:26.885059 [4] MIN Duty = 5000%(X100), DQS PI = 22
2358 09:31:26.885118 [4] AVG Duty = 5093%(X100)
2359 09:31:26.885177
2360 09:31:26.885236 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2361 09:31:26.885295
2362 09:31:26.885353 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2363 09:31:26.885412 [DutyScan_Calibration_Flow] ====Done====
2364 09:31:26.885471
2365 09:31:26.885530 [DutyScan_Calibration_Flow] k_type=2
2366 09:31:26.885589
2367 09:31:26.885647 ==DQ 0 ==
2368 09:31:26.885706 Final DQ duty delay cell = -4
2369 09:31:26.885765 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2370 09:31:26.885824 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2371 09:31:26.885883 [-4] AVG Duty = 4953%(X100)
2372 09:31:26.885942
2373 09:31:26.885999 ==DQ 1 ==
2374 09:31:26.886058 Final DQ duty delay cell = -4
2375 09:31:26.886117 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2376 09:31:26.886187 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2377 09:31:26.886248 [-4] AVG Duty = 4922%(X100)
2378 09:31:26.886306
2379 09:31:26.886393 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2380 09:31:26.886456
2381 09:31:26.886515 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2382 09:31:26.886575 [DutyScan_Calibration_Flow] ====Done====
2383 09:31:26.886634 ==
2384 09:31:26.886693 Dram Type= 6, Freq= 0, CH_1, rank 0
2385 09:31:26.886752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2386 09:31:26.886812 ==
2387 09:31:26.886871 [Duty_Offset_Calibration]
2388 09:31:26.886929 B0:-1 B1:1 CA:1
2389 09:31:26.886989
2390 09:31:26.887047 [DutyScan_Calibration_Flow] k_type=0
2391 09:31:26.887105
2392 09:31:26.887164 ==CLK 0==
2393 09:31:26.887223 Final CLK duty delay cell = 0
2394 09:31:26.887282 [0] MAX Duty = 5156%(X100), DQS PI = 22
2395 09:31:26.887353 [0] MIN Duty = 4969%(X100), DQS PI = 62
2396 09:31:26.887407 [0] AVG Duty = 5062%(X100)
2397 09:31:26.887461
2398 09:31:26.887514 CH1 CLK Duty spec in!! Max-Min= 187%
2399 09:31:26.887568 [DutyScan_Calibration_Flow] ====Done====
2400 09:31:26.887622
2401 09:31:26.887675 [DutyScan_Calibration_Flow] k_type=1
2402 09:31:26.887728
2403 09:31:26.887781 ==DQS 0 ==
2404 09:31:26.887834 Final DQS duty delay cell = 0
2405 09:31:26.887888 [0] MAX Duty = 5125%(X100), DQS PI = 48
2406 09:31:26.887942 [0] MIN Duty = 4875%(X100), DQS PI = 6
2407 09:31:26.887996 [0] AVG Duty = 5000%(X100)
2408 09:31:26.888049
2409 09:31:26.888102 ==DQS 1 ==
2410 09:31:26.888155 Final DQS duty delay cell = 0
2411 09:31:26.888209 [0] MAX Duty = 5062%(X100), DQS PI = 12
2412 09:31:26.888262 [0] MIN Duty = 4969%(X100), DQS PI = 56
2413 09:31:26.888316 [0] AVG Duty = 5015%(X100)
2414 09:31:26.888369
2415 09:31:26.888423 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2416 09:31:26.888476
2417 09:31:26.888529 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2418 09:31:26.888582 [DutyScan_Calibration_Flow] ====Done====
2419 09:31:26.888636
2420 09:31:26.888688 [DutyScan_Calibration_Flow] k_type=3
2421 09:31:26.888742
2422 09:31:26.888795 ==DQM 0 ==
2423 09:31:26.888849 Final DQM duty delay cell = -4
2424 09:31:26.888903 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2425 09:31:26.888956 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2426 09:31:26.889010 [-4] AVG Duty = 4937%(X100)
2427 09:31:26.889063
2428 09:31:26.889117 ==DQM 1 ==
2429 09:31:26.889181 Final DQM duty delay cell = 0
2430 09:31:26.889266 [0] MAX Duty = 5156%(X100), DQS PI = 6
2431 09:31:26.889323 [0] MIN Duty = 4969%(X100), DQS PI = 28
2432 09:31:26.889377 [0] AVG Duty = 5062%(X100)
2433 09:31:26.889432
2434 09:31:26.889485 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2435 09:31:26.889539
2436 09:31:26.889592 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2437 09:31:26.889646 [DutyScan_Calibration_Flow] ====Done====
2438 09:31:26.889700
2439 09:31:26.889753 [DutyScan_Calibration_Flow] k_type=2
2440 09:31:26.889807
2441 09:31:26.889877 ==DQ 0 ==
2442 09:31:26.889935 Final DQ duty delay cell = 0
2443 09:31:26.889990 [0] MAX Duty = 5156%(X100), DQS PI = 28
2444 09:31:26.890044 [0] MIN Duty = 4907%(X100), DQS PI = 6
2445 09:31:26.890098 [0] AVG Duty = 5031%(X100)
2446 09:31:26.890152
2447 09:31:26.890216 ==DQ 1 ==
2448 09:31:26.890270 Final DQ duty delay cell = 0
2449 09:31:26.890324 [0] MAX Duty = 5124%(X100), DQS PI = 10
2450 09:31:26.890378 [0] MIN Duty = 4938%(X100), DQS PI = 62
2451 09:31:26.890432 [0] AVG Duty = 5031%(X100)
2452 09:31:26.890487
2453 09:31:26.890540 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2454 09:31:26.890593
2455 09:31:26.890647 CH1 DQ 1 Duty spec in!! Max-Min= 186%
2456 09:31:26.890700 [DutyScan_Calibration_Flow] ====Done====
2457 09:31:26.890755 nWR fixed to 30
2458 09:31:26.890809 [ModeRegInit_LP4] CH0 RK0
2459 09:31:26.890863 [ModeRegInit_LP4] CH0 RK1
2460 09:31:26.890916 [ModeRegInit_LP4] CH1 RK0
2461 09:31:26.890973 [ModeRegInit_LP4] CH1 RK1
2462 09:31:26.891026 match AC timing 7
2463 09:31:26.891080 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2464 09:31:26.891135 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2465 09:31:26.891235 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2466 09:31:26.891332 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2467 09:31:26.891391 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2468 09:31:26.891446 ==
2469 09:31:26.891501 Dram Type= 6, Freq= 0, CH_0, rank 0
2470 09:31:26.891556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2471 09:31:26.891610 ==
2472 09:31:26.891664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2473 09:31:26.891719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2474 09:31:26.891773 [CA 0] Center 39 (9~70) winsize 62
2475 09:31:26.891827 [CA 1] Center 39 (9~70) winsize 62
2476 09:31:26.891881 [CA 2] Center 35 (5~66) winsize 62
2477 09:31:26.891935 [CA 3] Center 35 (5~66) winsize 62
2478 09:31:26.891989 [CA 4] Center 33 (4~63) winsize 60
2479 09:31:26.892043 [CA 5] Center 33 (3~63) winsize 61
2480 09:31:26.892096
2481 09:31:26.892150 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2482 09:31:26.892205
2483 09:31:26.892262 [CATrainingPosCal] consider 1 rank data
2484 09:31:26.892353 u2DelayCellTimex100 = 270/100 ps
2485 09:31:26.892424 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2486 09:31:26.892477 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2487 09:31:26.892725 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 09:31:26.892803 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2489 09:31:26.892859 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2490 09:31:26.892912 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2491 09:31:26.892966
2492 09:31:26.893019 CA PerBit enable=1, Macro0, CA PI delay=33
2493 09:31:26.893073
2494 09:31:26.893125 [CBTSetCACLKResult] CA Dly = 33
2495 09:31:26.893178 CS Dly: 8 (0~39)
2496 09:31:26.893231 ==
2497 09:31:26.893284 Dram Type= 6, Freq= 0, CH_0, rank 1
2498 09:31:26.893337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 09:31:26.893390 ==
2500 09:31:26.893442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2501 09:31:26.893496 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2502 09:31:26.893551 [CA 0] Center 39 (9~70) winsize 62
2503 09:31:26.893604 [CA 1] Center 39 (9~70) winsize 62
2504 09:31:26.893656 [CA 2] Center 35 (5~66) winsize 62
2505 09:31:26.893709 [CA 3] Center 35 (5~65) winsize 61
2506 09:31:26.893761 [CA 4] Center 33 (3~64) winsize 62
2507 09:31:26.893813 [CA 5] Center 33 (3~63) winsize 61
2508 09:31:26.893865
2509 09:31:26.893917 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2510 09:31:26.893970
2511 09:31:26.894022 [CATrainingPosCal] consider 2 rank data
2512 09:31:26.894075 u2DelayCellTimex100 = 270/100 ps
2513 09:31:26.894129 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2514 09:31:26.894248 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2515 09:31:26.894304 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2516 09:31:26.894358 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2517 09:31:26.894411 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2518 09:31:26.894463 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2519 09:31:26.894516
2520 09:31:26.894568 CA PerBit enable=1, Macro0, CA PI delay=33
2521 09:31:26.894621
2522 09:31:26.894674 [CBTSetCACLKResult] CA Dly = 33
2523 09:31:26.894727 CS Dly: 9 (0~41)
2524 09:31:26.894778
2525 09:31:26.894830 ----->DramcWriteLeveling(PI) begin...
2526 09:31:26.894884 ==
2527 09:31:26.894936 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 09:31:26.894989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 09:31:26.895042 ==
2530 09:31:26.895094 Write leveling (Byte 0): 34 => 34
2531 09:31:26.895147 Write leveling (Byte 1): 29 => 29
2532 09:31:26.895200 DramcWriteLeveling(PI) end<-----
2533 09:31:26.895253
2534 09:31:26.895305 ==
2535 09:31:26.895357 Dram Type= 6, Freq= 0, CH_0, rank 0
2536 09:31:26.895411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2537 09:31:26.895464 ==
2538 09:31:26.895516 [Gating] SW mode calibration
2539 09:31:26.895568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2540 09:31:26.895622 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2541 09:31:26.895674 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2542 09:31:26.895730 0 15 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2543 09:31:26.895783 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 09:31:26.895836 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 09:31:26.895889 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 09:31:26.895942 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 09:31:26.895995 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2548 09:31:26.896047 0 15 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
2549 09:31:26.896100 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (1 0) (0 0)
2550 09:31:26.896152 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 09:31:26.896227 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 09:31:26.896282 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 09:31:26.896335 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 09:31:26.896388 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 09:31:26.896441 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 09:31:26.896494 1 0 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
2557 09:31:26.896546 1 1 0 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
2558 09:31:26.896599 1 1 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2559 09:31:26.896652 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 09:31:26.896704 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 09:31:26.896757 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 09:31:26.896809 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 09:31:26.896862 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 09:31:26.896914 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2565 09:31:26.896967 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2566 09:31:26.897019 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2567 09:31:26.897071 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 09:31:26.897123 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 09:31:26.897176 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 09:31:26.897228 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 09:31:26.897281 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 09:31:26.897334 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 09:31:26.897387 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 09:31:26.897439 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 09:31:26.897492 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 09:31:26.897545 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 09:31:26.897598 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 09:31:26.897650 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 09:31:26.897702 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 09:31:26.897755 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2581 09:31:26.897808 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2582 09:31:26.897860 Total UI for P1: 0, mck2ui 16
2583 09:31:26.897913 best dqsien dly found for B0: ( 1, 3, 28)
2584 09:31:26.897966 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2585 09:31:26.898019 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 09:31:26.898071 Total UI for P1: 0, mck2ui 16
2587 09:31:26.898124 best dqsien dly found for B1: ( 1, 4, 2)
2588 09:31:26.898206 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2589 09:31:26.898275 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2590 09:31:26.898327
2591 09:31:26.898574 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2592 09:31:26.898635 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2593 09:31:26.898689 [Gating] SW calibration Done
2594 09:31:26.898742 ==
2595 09:31:26.898795 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 09:31:26.898849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2597 09:31:26.898903 ==
2598 09:31:26.898955 RX Vref Scan: 0
2599 09:31:26.899008
2600 09:31:26.899059 RX Vref 0 -> 0, step: 1
2601 09:31:26.899112
2602 09:31:26.899164 RX Delay -40 -> 252, step: 8
2603 09:31:26.899216 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2604 09:31:26.899269 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2605 09:31:26.899322 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2606 09:31:26.899375 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2607 09:31:26.899427 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2608 09:31:26.899480 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2609 09:31:26.899532 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2610 09:31:26.899584 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2611 09:31:26.899659 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2612 09:31:26.899716 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2613 09:31:26.899769 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2614 09:31:26.899822 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2615 09:31:26.899875 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2616 09:31:26.899928 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2617 09:31:26.899981 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2618 09:31:26.900034 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2619 09:31:26.900086 ==
2620 09:31:26.900138 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 09:31:26.900192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 09:31:26.900245 ==
2623 09:31:26.900297 DQS Delay:
2624 09:31:26.900350 DQS0 = 0, DQS1 = 0
2625 09:31:26.900405 DQM Delay:
2626 09:31:26.900458 DQM0 = 119, DQM1 = 106
2627 09:31:26.900511 DQ Delay:
2628 09:31:26.900563 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2629 09:31:26.900615 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2630 09:31:26.900667 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2631 09:31:26.900720 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2632 09:31:26.900772
2633 09:31:26.900824
2634 09:31:26.900876 ==
2635 09:31:26.900928 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 09:31:26.900980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 09:31:26.901033 ==
2638 09:31:26.901086
2639 09:31:26.901138
2640 09:31:26.901189 TX Vref Scan disable
2641 09:31:26.901242 == TX Byte 0 ==
2642 09:31:26.901294 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2643 09:31:26.901347 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2644 09:31:26.901400 == TX Byte 1 ==
2645 09:31:26.901452 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2646 09:31:26.901504 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2647 09:31:26.901557 ==
2648 09:31:26.901609 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 09:31:26.901661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 09:31:26.901714 ==
2651 09:31:26.901767 TX Vref=22, minBit 1, minWin=25, winSum=415
2652 09:31:26.901820 TX Vref=24, minBit 5, minWin=25, winSum=418
2653 09:31:26.901874 TX Vref=26, minBit 1, minWin=26, winSum=427
2654 09:31:26.901927 TX Vref=28, minBit 13, minWin=26, winSum=434
2655 09:31:26.901980 TX Vref=30, minBit 13, minWin=26, winSum=435
2656 09:31:26.902033 TX Vref=32, minBit 4, minWin=26, winSum=432
2657 09:31:26.902085 [TxChooseVref] Worse bit 13, Min win 26, Win sum 435, Final Vref 30
2658 09:31:26.902138
2659 09:31:26.902201 Final TX Range 1 Vref 30
2660 09:31:26.902254
2661 09:31:26.902306 ==
2662 09:31:26.902359 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 09:31:26.902411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 09:31:26.902465 ==
2665 09:31:26.902517
2666 09:31:26.902569
2667 09:31:26.902621 TX Vref Scan disable
2668 09:31:26.902674 == TX Byte 0 ==
2669 09:31:26.902725 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2670 09:31:26.902778 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2671 09:31:26.902852 == TX Byte 1 ==
2672 09:31:26.902906 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2673 09:31:26.902959 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2674 09:31:26.903011
2675 09:31:26.903063 [DATLAT]
2676 09:31:26.903116 Freq=1200, CH0 RK0
2677 09:31:26.903168
2678 09:31:26.903221 DATLAT Default: 0xd
2679 09:31:26.903273 0, 0xFFFF, sum = 0
2680 09:31:26.903327 1, 0xFFFF, sum = 0
2681 09:31:26.903381 2, 0xFFFF, sum = 0
2682 09:31:26.903434 3, 0xFFFF, sum = 0
2683 09:31:26.903487 4, 0xFFFF, sum = 0
2684 09:31:26.903541 5, 0xFFFF, sum = 0
2685 09:31:26.903594 6, 0xFFFF, sum = 0
2686 09:31:26.903647 7, 0xFFFF, sum = 0
2687 09:31:26.903699 8, 0xFFFF, sum = 0
2688 09:31:26.903752 9, 0xFFFF, sum = 0
2689 09:31:26.903806 10, 0xFFFF, sum = 0
2690 09:31:26.903859 11, 0xFFFF, sum = 0
2691 09:31:26.903912 12, 0x0, sum = 1
2692 09:31:26.903966 13, 0x0, sum = 2
2693 09:31:26.904019 14, 0x0, sum = 3
2694 09:31:26.904072 15, 0x0, sum = 4
2695 09:31:26.904125 best_step = 13
2696 09:31:26.904179
2697 09:31:26.904231 ==
2698 09:31:26.904283 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 09:31:26.904336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 09:31:26.904389 ==
2701 09:31:26.904442 RX Vref Scan: 1
2702 09:31:26.904495
2703 09:31:26.904547 Set Vref Range= 32 -> 127
2704 09:31:26.904600
2705 09:31:26.904652 RX Vref 32 -> 127, step: 1
2706 09:31:26.904705
2707 09:31:26.904757 RX Delay -21 -> 252, step: 4
2708 09:31:26.904809
2709 09:31:26.904861 Set Vref, RX VrefLevel [Byte0]: 32
2710 09:31:26.904913 [Byte1]: 32
2711 09:31:26.904966
2712 09:31:26.905018 Set Vref, RX VrefLevel [Byte0]: 33
2713 09:31:26.905070 [Byte1]: 33
2714 09:31:26.905123
2715 09:31:26.905174 Set Vref, RX VrefLevel [Byte0]: 34
2716 09:31:26.905227 [Byte1]: 34
2717 09:31:26.905279
2718 09:31:26.905330 Set Vref, RX VrefLevel [Byte0]: 35
2719 09:31:26.905383 [Byte1]: 35
2720 09:31:26.905435
2721 09:31:26.905487 Set Vref, RX VrefLevel [Byte0]: 36
2722 09:31:26.905539 [Byte1]: 36
2723 09:31:26.905592
2724 09:31:26.905644 Set Vref, RX VrefLevel [Byte0]: 37
2725 09:31:26.905696 [Byte1]: 37
2726 09:31:26.905748
2727 09:31:26.905800 Set Vref, RX VrefLevel [Byte0]: 38
2728 09:31:26.905852 [Byte1]: 38
2729 09:31:26.905904
2730 09:31:26.905956 Set Vref, RX VrefLevel [Byte0]: 39
2731 09:31:26.906008 [Byte1]: 39
2732 09:31:26.906071
2733 09:31:26.906158 Set Vref, RX VrefLevel [Byte0]: 40
2734 09:31:26.906222 [Byte1]: 40
2735 09:31:26.906275
2736 09:31:26.906328 Set Vref, RX VrefLevel [Byte0]: 41
2737 09:31:26.906381 [Byte1]: 41
2738 09:31:26.906441
2739 09:31:26.906493 Set Vref, RX VrefLevel [Byte0]: 42
2740 09:31:26.906547 [Byte1]: 42
2741 09:31:26.906600
2742 09:31:26.906653 Set Vref, RX VrefLevel [Byte0]: 43
2743 09:31:26.906705 [Byte1]: 43
2744 09:31:26.906758
2745 09:31:26.906810 Set Vref, RX VrefLevel [Byte0]: 44
2746 09:31:26.907055 [Byte1]: 44
2747 09:31:26.907114
2748 09:31:26.907167 Set Vref, RX VrefLevel [Byte0]: 45
2749 09:31:26.907219 [Byte1]: 45
2750 09:31:26.907271
2751 09:31:26.907323 Set Vref, RX VrefLevel [Byte0]: 46
2752 09:31:26.907376 [Byte1]: 46
2753 09:31:26.907427
2754 09:31:26.907479 Set Vref, RX VrefLevel [Byte0]: 47
2755 09:31:26.907532 [Byte1]: 47
2756 09:31:26.907584
2757 09:31:26.907636 Set Vref, RX VrefLevel [Byte0]: 48
2758 09:31:26.907688 [Byte1]: 48
2759 09:31:26.907740
2760 09:31:26.907792 Set Vref, RX VrefLevel [Byte0]: 49
2761 09:31:26.907844 [Byte1]: 49
2762 09:31:26.907896
2763 09:31:26.907948 Set Vref, RX VrefLevel [Byte0]: 50
2764 09:31:26.908001 [Byte1]: 50
2765 09:31:26.908054
2766 09:31:26.908106 Set Vref, RX VrefLevel [Byte0]: 51
2767 09:31:26.908157 [Byte1]: 51
2768 09:31:26.908210
2769 09:31:26.908261 Set Vref, RX VrefLevel [Byte0]: 52
2770 09:31:26.908314 [Byte1]: 52
2771 09:31:26.908366
2772 09:31:26.908418 Set Vref, RX VrefLevel [Byte0]: 53
2773 09:31:26.908471 [Byte1]: 53
2774 09:31:26.908523
2775 09:31:26.908574 Set Vref, RX VrefLevel [Byte0]: 54
2776 09:31:26.908626 [Byte1]: 54
2777 09:31:26.908678
2778 09:31:26.908730 Set Vref, RX VrefLevel [Byte0]: 55
2779 09:31:26.908783 [Byte1]: 55
2780 09:31:26.908834
2781 09:31:26.908886 Set Vref, RX VrefLevel [Byte0]: 56
2782 09:31:26.908939 [Byte1]: 56
2783 09:31:26.908992
2784 09:31:26.909044 Set Vref, RX VrefLevel [Byte0]: 57
2785 09:31:26.909096 [Byte1]: 57
2786 09:31:26.909148
2787 09:31:26.909201 Set Vref, RX VrefLevel [Byte0]: 58
2788 09:31:26.909252 [Byte1]: 58
2789 09:31:26.909304
2790 09:31:26.909366 Set Vref, RX VrefLevel [Byte0]: 59
2791 09:31:26.909428 [Byte1]: 59
2792 09:31:26.909481
2793 09:31:26.909533 Set Vref, RX VrefLevel [Byte0]: 60
2794 09:31:26.909586 [Byte1]: 60
2795 09:31:26.909639
2796 09:31:26.909691 Set Vref, RX VrefLevel [Byte0]: 61
2797 09:31:26.909743 [Byte1]: 61
2798 09:31:26.909796
2799 09:31:26.909848 Set Vref, RX VrefLevel [Byte0]: 62
2800 09:31:26.909900 [Byte1]: 62
2801 09:31:26.909952
2802 09:31:26.910004 Set Vref, RX VrefLevel [Byte0]: 63
2803 09:31:26.910056 [Byte1]: 63
2804 09:31:26.910109
2805 09:31:26.910171 Set Vref, RX VrefLevel [Byte0]: 64
2806 09:31:26.910265 [Byte1]: 64
2807 09:31:26.910317
2808 09:31:26.910370 Set Vref, RX VrefLevel [Byte0]: 65
2809 09:31:26.910422 [Byte1]: 65
2810 09:31:26.910474
2811 09:31:26.910527 Set Vref, RX VrefLevel [Byte0]: 66
2812 09:31:26.910580 [Byte1]: 66
2813 09:31:26.910632
2814 09:31:26.910684 Set Vref, RX VrefLevel [Byte0]: 67
2815 09:31:26.910737 [Byte1]: 67
2816 09:31:26.910790
2817 09:31:26.910842 Set Vref, RX VrefLevel [Byte0]: 68
2818 09:31:26.910894 [Byte1]: 68
2819 09:31:26.910947
2820 09:31:26.910999 Set Vref, RX VrefLevel [Byte0]: 69
2821 09:31:26.911052 [Byte1]: 69
2822 09:31:26.911105
2823 09:31:26.911157 Set Vref, RX VrefLevel [Byte0]: 70
2824 09:31:26.911210 [Byte1]: 70
2825 09:31:26.911262
2826 09:31:26.911315 Set Vref, RX VrefLevel [Byte0]: 71
2827 09:31:26.911367 [Byte1]: 71
2828 09:31:26.911419
2829 09:31:26.911472 Set Vref, RX VrefLevel [Byte0]: 72
2830 09:31:26.911524 [Byte1]: 72
2831 09:31:26.911576
2832 09:31:26.911634 Set Vref, RX VrefLevel [Byte0]: 73
2833 09:31:26.911692 [Byte1]: 73
2834 09:31:26.911745
2835 09:31:26.911797 Set Vref, RX VrefLevel [Byte0]: 74
2836 09:31:26.911850 [Byte1]: 74
2837 09:31:26.911903
2838 09:31:26.911955 Set Vref, RX VrefLevel [Byte0]: 75
2839 09:31:26.912008 [Byte1]: 75
2840 09:31:26.912060
2841 09:31:26.912112 Set Vref, RX VrefLevel [Byte0]: 76
2842 09:31:26.912164 [Byte1]: 76
2843 09:31:26.912217
2844 09:31:26.912268 Set Vref, RX VrefLevel [Byte0]: 77
2845 09:31:26.912321 [Byte1]: 77
2846 09:31:26.912373
2847 09:31:26.912426 Final RX Vref Byte 0 = 61 to rank0
2848 09:31:26.912479 Final RX Vref Byte 1 = 59 to rank0
2849 09:31:26.912532 Final RX Vref Byte 0 = 61 to rank1
2850 09:31:26.912585 Final RX Vref Byte 1 = 59 to rank1==
2851 09:31:26.912638 Dram Type= 6, Freq= 0, CH_0, rank 0
2852 09:31:26.912690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2853 09:31:26.912743 ==
2854 09:31:26.912811 DQS Delay:
2855 09:31:26.912868 DQS0 = 0, DQS1 = 0
2856 09:31:26.912921 DQM Delay:
2857 09:31:26.912973 DQM0 = 119, DQM1 = 108
2858 09:31:26.913026 DQ Delay:
2859 09:31:26.913078 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2860 09:31:26.913131 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =126
2861 09:31:26.913183 DQ8 =96, DQ9 =94, DQ10 =112, DQ11 =102
2862 09:31:26.913235 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2863 09:31:26.913288
2864 09:31:26.913376
2865 09:31:26.913433 [DQSOSCAuto] RK0, (LSB)MR18= 0xffa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2866 09:31:26.913489 CH0 RK0: MR19=403, MR18=FFA
2867 09:31:26.913543 CH0_RK0: MR19=0x403, MR18=0xFFA, DQSOSC=404, MR23=63, INC=40, DEC=26
2868 09:31:26.913596
2869 09:31:26.913648 ----->DramcWriteLeveling(PI) begin...
2870 09:31:26.913702 ==
2871 09:31:26.913755 Dram Type= 6, Freq= 0, CH_0, rank 1
2872 09:31:26.913807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2873 09:31:26.913860 ==
2874 09:31:26.913913 Write leveling (Byte 0): 32 => 32
2875 09:31:26.913966 Write leveling (Byte 1): 30 => 30
2876 09:31:26.914018 DramcWriteLeveling(PI) end<-----
2877 09:31:26.914070
2878 09:31:26.914122 ==
2879 09:31:26.914182 Dram Type= 6, Freq= 0, CH_0, rank 1
2880 09:31:26.914276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2881 09:31:26.914329 ==
2882 09:31:26.914389 [Gating] SW mode calibration
2883 09:31:26.914455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2884 09:31:26.914546 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2885 09:31:26.914603 0 15 0 | B1->B0 | 2524 3333 | 1 0 | (0 0) (0 0)
2886 09:31:26.914657 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2887 09:31:26.914711 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 09:31:26.914764 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 09:31:26.914817 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 09:31:26.914869 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 09:31:26.914923 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 09:31:26.915167 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2893 09:31:26.915227 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (0 1) (0 0)
2894 09:31:26.915280 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2895 09:31:26.915333 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 09:31:26.915386 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 09:31:26.915439 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 09:31:26.915491 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 09:31:26.915543 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 09:31:26.915596 1 0 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2901 09:31:26.915649 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2902 09:31:26.915703 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 09:31:26.915756 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 09:31:26.915809 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 09:31:26.915861 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 09:31:26.915914 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 09:31:26.915982 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 09:31:26.916039 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2909 09:31:26.916092 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2910 09:31:26.916146 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 09:31:26.916198 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 09:31:26.916251 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 09:31:26.916303 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 09:31:26.916356 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 09:31:26.916437 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 09:31:26.916540 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 09:31:26.916596 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 09:31:26.916650 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 09:31:26.916703 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 09:31:26.916755 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 09:31:26.916809 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 09:31:26.916861 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 09:31:26.916914 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2924 09:31:26.916966 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2925 09:31:26.917019 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2926 09:31:26.917071 Total UI for P1: 0, mck2ui 16
2927 09:31:26.917123 best dqsien dly found for B0: ( 1, 3, 26)
2928 09:31:26.917176 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 09:31:26.917229 Total UI for P1: 0, mck2ui 16
2930 09:31:26.917281 best dqsien dly found for B1: ( 1, 4, 0)
2931 09:31:26.917334 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2932 09:31:26.917387 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2933 09:31:26.917439
2934 09:31:26.917492 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2935 09:31:26.917544 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2936 09:31:26.917597 [Gating] SW calibration Done
2937 09:31:27.037227 ==
2938 09:31:27.037878 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 09:31:27.038395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 09:31:27.038794 ==
2941 09:31:27.039188 RX Vref Scan: 0
2942 09:31:27.039522
2943 09:31:27.039838 RX Vref 0 -> 0, step: 1
2944 09:31:27.040156
2945 09:31:27.040463 RX Delay -40 -> 252, step: 8
2946 09:31:27.040773 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2947 09:31:27.041079 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2948 09:31:27.041413 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2949 09:31:27.041790 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2950 09:31:27.042103 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2951 09:31:27.042463 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2952 09:31:27.042773 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2953 09:31:27.043077 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2954 09:31:27.043379 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2955 09:31:27.043678 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2956 09:31:27.043975 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2957 09:31:27.044275 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2958 09:31:27.044664 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2959 09:31:27.044996 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2960 09:31:27.045357 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2961 09:31:27.045809 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2962 09:31:27.046124 ==
2963 09:31:27.046478 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 09:31:27.046784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 09:31:27.047090 ==
2966 09:31:27.047392 DQS Delay:
2967 09:31:27.047690 DQS0 = 0, DQS1 = 0
2968 09:31:27.047991 DQM Delay:
2969 09:31:27.048418 DQM0 = 116, DQM1 = 108
2970 09:31:27.048729 DQ Delay:
2971 09:31:27.049030 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
2972 09:31:27.049333 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2973 09:31:27.049633 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2974 09:31:27.049935 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2975 09:31:27.050275
2976 09:31:27.050584
2977 09:31:27.050881 ==
2978 09:31:27.051181 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 09:31:27.051586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 09:31:27.051909 ==
2981 09:31:27.052211
2982 09:31:27.052508
2983 09:31:27.052801 TX Vref Scan disable
2984 09:31:27.053100 == TX Byte 0 ==
2985 09:31:27.053400 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2986 09:31:27.053704 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2987 09:31:27.054006 == TX Byte 1 ==
2988 09:31:27.054359 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2989 09:31:27.054669 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2990 09:31:27.055080 ==
2991 09:31:27.055387 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 09:31:27.055692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 09:31:27.055998 ==
2994 09:31:27.056474 TX Vref=22, minBit 0, minWin=26, winSum=427
2995 09:31:27.056907 TX Vref=24, minBit 0, minWin=26, winSum=432
2996 09:31:27.057224 TX Vref=26, minBit 2, minWin=26, winSum=432
2997 09:31:27.057532 TX Vref=28, minBit 1, minWin=27, winSum=440
2998 09:31:27.057863 TX Vref=30, minBit 13, minWin=26, winSum=439
2999 09:31:27.058444 TX Vref=32, minBit 2, minWin=26, winSum=431
3000 09:31:27.059401 [TxChooseVref] Worse bit 1, Min win 27, Win sum 440, Final Vref 28
3001 09:31:27.059759
3002 09:31:27.060073 Final TX Range 1 Vref 28
3003 09:31:27.060384
3004 09:31:27.060686 ==
3005 09:31:27.060990 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 09:31:27.061410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 09:31:27.061754 ==
3008 09:31:27.062276
3009 09:31:27.062536
3010 09:31:27.062789 TX Vref Scan disable
3011 09:31:27.063016 == TX Byte 0 ==
3012 09:31:27.063235 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3013 09:31:27.063451 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3014 09:31:27.063667 == TX Byte 1 ==
3015 09:31:27.063951 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3016 09:31:27.064178 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3017 09:31:27.064408
3018 09:31:27.064683 [DATLAT]
3019 09:31:27.064924 Freq=1200, CH0 RK1
3020 09:31:27.065147
3021 09:31:27.065362 DATLAT Default: 0xd
3022 09:31:27.065574 0, 0xFFFF, sum = 0
3023 09:31:27.065792 1, 0xFFFF, sum = 0
3024 09:31:27.066012 2, 0xFFFF, sum = 0
3025 09:31:27.066262 3, 0xFFFF, sum = 0
3026 09:31:27.066488 4, 0xFFFF, sum = 0
3027 09:31:27.066705 5, 0xFFFF, sum = 0
3028 09:31:27.066922 6, 0xFFFF, sum = 0
3029 09:31:27.067136 7, 0xFFFF, sum = 0
3030 09:31:27.067345 8, 0xFFFF, sum = 0
3031 09:31:27.067505 9, 0xFFFF, sum = 0
3032 09:31:27.067664 10, 0xFFFF, sum = 0
3033 09:31:27.067846 11, 0xFFFF, sum = 0
3034 09:31:27.068036 12, 0x0, sum = 1
3035 09:31:27.068198 13, 0x0, sum = 2
3036 09:31:27.068356 14, 0x0, sum = 3
3037 09:31:27.068514 15, 0x0, sum = 4
3038 09:31:27.068674 best_step = 13
3039 09:31:27.068828
3040 09:31:27.068983 ==
3041 09:31:27.069139 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 09:31:27.069297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 09:31:27.069453 ==
3044 09:31:27.069608 RX Vref Scan: 0
3045 09:31:27.069761
3046 09:31:27.069916 RX Vref 0 -> 0, step: 1
3047 09:31:27.070072
3048 09:31:27.070250 RX Delay -21 -> 252, step: 4
3049 09:31:27.070410 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3050 09:31:27.070566 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3051 09:31:27.070723 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3052 09:31:27.070880 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3053 09:31:27.071064 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3054 09:31:27.071246 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3055 09:31:27.071405 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3056 09:31:27.071560 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3057 09:31:27.071715 iDelay=195, Bit 8, Center 98 (31 ~ 166) 136
3058 09:31:27.071871 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3059 09:31:27.072027 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3060 09:31:27.072182 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3061 09:31:27.072350 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3062 09:31:27.072473 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3063 09:31:27.072596 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3064 09:31:27.072719 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3065 09:31:27.072842 ==
3066 09:31:27.072968 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 09:31:27.073093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 09:31:27.073219 ==
3069 09:31:27.073343 DQS Delay:
3070 09:31:27.073466 DQS0 = 0, DQS1 = 0
3071 09:31:27.073590 DQM Delay:
3072 09:31:27.073714 DQM0 = 116, DQM1 = 108
3073 09:31:27.073838 DQ Delay:
3074 09:31:27.073963 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =112
3075 09:31:27.074110 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3076 09:31:27.074283 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3077 09:31:27.074412 DQ12 =116, DQ13 =114, DQ14 =120, DQ15 =114
3078 09:31:27.074537
3079 09:31:27.074661
3080 09:31:27.074786 [DQSOSCAuto] RK1, (LSB)MR18= 0xde8, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3081 09:31:27.074913 CH0 RK1: MR19=403, MR18=DE8
3082 09:31:27.075040 CH0_RK1: MR19=0x403, MR18=0xDE8, DQSOSC=405, MR23=63, INC=39, DEC=26
3083 09:31:27.075166 [RxdqsGatingPostProcess] freq 1200
3084 09:31:27.075293 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3085 09:31:27.075418 best DQS0 dly(2T, 0.5T) = (0, 11)
3086 09:31:27.075544 best DQS1 dly(2T, 0.5T) = (0, 12)
3087 09:31:27.075721 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3088 09:31:27.075853 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3089 09:31:27.075978 best DQS0 dly(2T, 0.5T) = (0, 11)
3090 09:31:27.076101 best DQS1 dly(2T, 0.5T) = (0, 12)
3091 09:31:27.076226 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3092 09:31:27.076350 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3093 09:31:27.076475 Pre-setting of DQS Precalculation
3094 09:31:27.076599 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3095 09:31:27.076725 ==
3096 09:31:27.076850 Dram Type= 6, Freq= 0, CH_1, rank 0
3097 09:31:27.076974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 09:31:27.077101 ==
3099 09:31:27.077225 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 09:31:27.077362 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3101 09:31:27.077479 [CA 0] Center 37 (7~68) winsize 62
3102 09:31:27.077607 [CA 1] Center 38 (8~68) winsize 61
3103 09:31:27.077712 [CA 2] Center 34 (4~64) winsize 61
3104 09:31:27.077817 [CA 3] Center 33 (3~64) winsize 62
3105 09:31:27.077920 [CA 4] Center 34 (5~64) winsize 60
3106 09:31:27.078024 [CA 5] Center 33 (3~64) winsize 62
3107 09:31:27.078128
3108 09:31:27.078248 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3109 09:31:27.078353
3110 09:31:27.078456 [CATrainingPosCal] consider 1 rank data
3111 09:31:27.078559 u2DelayCellTimex100 = 270/100 ps
3112 09:31:27.078665 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3113 09:31:27.078769 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3114 09:31:27.078874 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3115 09:31:27.079017 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3116 09:31:27.079128 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3117 09:31:27.079233 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3118 09:31:27.079335
3119 09:31:27.079438 CA PerBit enable=1, Macro0, CA PI delay=33
3120 09:31:27.079542
3121 09:31:27.079645 [CBTSetCACLKResult] CA Dly = 33
3122 09:31:27.079751 CS Dly: 6 (0~37)
3123 09:31:27.079854 ==
3124 09:31:27.079959 Dram Type= 6, Freq= 0, CH_1, rank 1
3125 09:31:27.080063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 09:31:27.080168 ==
3127 09:31:27.080271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3128 09:31:27.080375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3129 09:31:27.080478 [CA 0] Center 37 (7~68) winsize 62
3130 09:31:27.080582 [CA 1] Center 38 (8~68) winsize 61
3131 09:31:27.080685 [CA 2] Center 34 (4~65) winsize 62
3132 09:31:27.080806 [CA 3] Center 33 (3~64) winsize 62
3133 09:31:27.080934 [CA 4] Center 34 (4~65) winsize 62
3134 09:31:27.081039 [CA 5] Center 33 (3~64) winsize 62
3135 09:31:27.081142
3136 09:31:27.081485 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3137 09:31:27.081599
3138 09:31:27.081703 [CATrainingPosCal] consider 2 rank data
3139 09:31:27.081807 u2DelayCellTimex100 = 270/100 ps
3140 09:31:27.081911 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3141 09:31:27.082056 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3142 09:31:27.082225 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3143 09:31:27.082346 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3144 09:31:27.082436 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3145 09:31:27.082524 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3146 09:31:27.082612
3147 09:31:27.082700 CA PerBit enable=1, Macro0, CA PI delay=33
3148 09:31:27.082789
3149 09:31:27.082877 [CBTSetCACLKResult] CA Dly = 33
3150 09:31:27.082964 CS Dly: 7 (0~40)
3151 09:31:27.083051
3152 09:31:27.083139 ----->DramcWriteLeveling(PI) begin...
3153 09:31:27.083230 ==
3154 09:31:27.083318 Dram Type= 6, Freq= 0, CH_1, rank 0
3155 09:31:27.083406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 09:31:27.083496 ==
3157 09:31:27.083584 Write leveling (Byte 0): 24 => 24
3158 09:31:27.083673 Write leveling (Byte 1): 26 => 26
3159 09:31:27.083760 DramcWriteLeveling(PI) end<-----
3160 09:31:27.083848
3161 09:31:27.083935 ==
3162 09:31:27.084027 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 09:31:27.084145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 09:31:27.084236 ==
3165 09:31:27.084325 [Gating] SW mode calibration
3166 09:31:27.084413 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3167 09:31:27.084502 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3168 09:31:27.084608 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 09:31:27.084699 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 09:31:27.084789 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 09:31:27.084925 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 09:31:27.085020 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 09:31:27.085109 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 09:31:27.085197 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
3175 09:31:27.085286 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3176 09:31:27.085374 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 09:31:27.085464 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 09:31:27.085552 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 09:31:27.085641 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 09:31:27.085730 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 09:31:27.085818 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 09:31:27.085907 1 0 24 | B1->B0 | 2828 3a3a | 0 0 | (1 1) (0 0)
3183 09:31:27.085995 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 09:31:27.086084 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 09:31:27.086181 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 09:31:27.086271 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 09:31:27.086359 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 09:31:27.086448 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 09:31:27.086536 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 09:31:27.086623 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3191 09:31:27.086711 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3192 09:31:27.086800 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 09:31:27.086888 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 09:31:27.086975 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 09:31:27.087063 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 09:31:27.087151 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 09:31:27.087239 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 09:31:27.087336 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 09:31:27.087412 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 09:31:27.087521 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 09:31:27.087602 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 09:31:27.087679 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 09:31:27.087756 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 09:31:27.087833 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 09:31:27.087910 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 09:31:27.087986 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3207 09:31:27.088063 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3208 09:31:27.088140 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 09:31:27.088217 Total UI for P1: 0, mck2ui 16
3210 09:31:27.088294 best dqsien dly found for B0: ( 1, 3, 26)
3211 09:31:27.088371 Total UI for P1: 0, mck2ui 16
3212 09:31:27.088449 best dqsien dly found for B1: ( 1, 3, 26)
3213 09:31:27.088527 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3214 09:31:27.088604 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3215 09:31:27.088681
3216 09:31:27.088757 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3217 09:31:27.088834 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3218 09:31:27.088910 [Gating] SW calibration Done
3219 09:31:27.088986 ==
3220 09:31:27.089063 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 09:31:27.089140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 09:31:27.089218 ==
3223 09:31:27.089294 RX Vref Scan: 0
3224 09:31:27.089370
3225 09:31:27.089446 RX Vref 0 -> 0, step: 1
3226 09:31:27.089523
3227 09:31:27.089598 RX Delay -40 -> 252, step: 8
3228 09:31:27.089675 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3229 09:31:27.089751 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3230 09:31:27.089828 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3231 09:31:27.089904 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3232 09:31:27.089980 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3233 09:31:27.090058 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3234 09:31:27.090134 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3235 09:31:27.090224 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3236 09:31:27.090302 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3237 09:31:27.090379 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3238 09:31:27.090668 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3239 09:31:27.090755 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3240 09:31:27.090833 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3241 09:31:27.090911 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3242 09:31:27.091000 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3243 09:31:27.091093 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3244 09:31:27.091171 ==
3245 09:31:27.091249 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 09:31:27.091326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 09:31:27.091403 ==
3248 09:31:27.091480 DQS Delay:
3249 09:31:27.091556 DQS0 = 0, DQS1 = 0
3250 09:31:27.091632 DQM Delay:
3251 09:31:27.091708 DQM0 = 118, DQM1 = 109
3252 09:31:27.091838 DQ Delay:
3253 09:31:27.091978 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3254 09:31:27.092062 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3255 09:31:27.092141 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3256 09:31:27.092219 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3257 09:31:27.092296
3258 09:31:27.092383
3259 09:31:27.092451 ==
3260 09:31:27.092519 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 09:31:27.092588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 09:31:27.092657 ==
3263 09:31:27.092725
3264 09:31:27.092792
3265 09:31:27.092859 TX Vref Scan disable
3266 09:31:27.092927 == TX Byte 0 ==
3267 09:31:27.092995 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3268 09:31:27.093064 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3269 09:31:27.093132 == TX Byte 1 ==
3270 09:31:27.093199 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3271 09:31:27.093268 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3272 09:31:27.093336 ==
3273 09:31:27.093404 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 09:31:27.093472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 09:31:27.093540 ==
3276 09:31:27.093607 TX Vref=22, minBit 10, minWin=25, winSum=419
3277 09:31:27.093676 TX Vref=24, minBit 10, minWin=25, winSum=423
3278 09:31:27.093744 TX Vref=26, minBit 2, minWin=26, winSum=436
3279 09:31:27.093812 TX Vref=28, minBit 9, minWin=26, winSum=436
3280 09:31:27.093880 TX Vref=30, minBit 13, minWin=26, winSum=436
3281 09:31:27.093948 TX Vref=32, minBit 9, minWin=26, winSum=431
3282 09:31:27.094016 [TxChooseVref] Worse bit 2, Min win 26, Win sum 436, Final Vref 26
3283 09:31:27.094085
3284 09:31:27.094155 Final TX Range 1 Vref 26
3285 09:31:27.094268
3286 09:31:27.094338 ==
3287 09:31:27.094406 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 09:31:27.094476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 09:31:27.094545 ==
3290 09:31:27.094612
3291 09:31:27.094679
3292 09:31:27.094746 TX Vref Scan disable
3293 09:31:27.094814 == TX Byte 0 ==
3294 09:31:27.094881 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3295 09:31:27.094949 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3296 09:31:27.095016 == TX Byte 1 ==
3297 09:31:27.095083 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3298 09:31:27.095150 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3299 09:31:27.095217
3300 09:31:27.095284 [DATLAT]
3301 09:31:27.095351 Freq=1200, CH1 RK0
3302 09:31:27.095419
3303 09:31:27.095485 DATLAT Default: 0xd
3304 09:31:27.095551 0, 0xFFFF, sum = 0
3305 09:31:27.095620 1, 0xFFFF, sum = 0
3306 09:31:27.095688 2, 0xFFFF, sum = 0
3307 09:31:27.095756 3, 0xFFFF, sum = 0
3308 09:31:27.095824 4, 0xFFFF, sum = 0
3309 09:31:27.095891 5, 0xFFFF, sum = 0
3310 09:31:27.095959 6, 0xFFFF, sum = 0
3311 09:31:27.096026 7, 0xFFFF, sum = 0
3312 09:31:27.096095 8, 0xFFFF, sum = 0
3313 09:31:27.096163 9, 0xFFFF, sum = 0
3314 09:31:27.096231 10, 0xFFFF, sum = 0
3315 09:31:27.096299 11, 0xFFFF, sum = 0
3316 09:31:27.096368 12, 0x0, sum = 1
3317 09:31:27.096435 13, 0x0, sum = 2
3318 09:31:27.096503 14, 0x0, sum = 3
3319 09:31:27.096571 15, 0x0, sum = 4
3320 09:31:27.096639 best_step = 13
3321 09:31:27.096706
3322 09:31:27.096772 ==
3323 09:31:27.096839 Dram Type= 6, Freq= 0, CH_1, rank 0
3324 09:31:27.096907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3325 09:31:27.096975 ==
3326 09:31:27.097042 RX Vref Scan: 1
3327 09:31:27.097109
3328 09:31:27.097175 Set Vref Range= 32 -> 127
3329 09:31:27.097242
3330 09:31:27.097321 RX Vref 32 -> 127, step: 1
3331 09:31:27.097381
3332 09:31:27.097440 RX Delay -21 -> 252, step: 4
3333 09:31:27.097500
3334 09:31:27.097559 Set Vref, RX VrefLevel [Byte0]: 32
3335 09:31:27.097651 [Byte1]: 32
3336 09:31:27.097715
3337 09:31:27.097776 Set Vref, RX VrefLevel [Byte0]: 33
3338 09:31:27.097837 [Byte1]: 33
3339 09:31:27.097900
3340 09:31:27.097961 Set Vref, RX VrefLevel [Byte0]: 34
3341 09:31:27.098022 [Byte1]: 34
3342 09:31:27.098083
3343 09:31:27.098143 Set Vref, RX VrefLevel [Byte0]: 35
3344 09:31:27.098217 [Byte1]: 35
3345 09:31:27.098278
3346 09:31:27.098339 Set Vref, RX VrefLevel [Byte0]: 36
3347 09:31:27.098399 [Byte1]: 36
3348 09:31:27.098459
3349 09:31:27.098519 Set Vref, RX VrefLevel [Byte0]: 37
3350 09:31:27.098579 [Byte1]: 37
3351 09:31:27.098640
3352 09:31:27.098700 Set Vref, RX VrefLevel [Byte0]: 38
3353 09:31:27.098761 [Byte1]: 38
3354 09:31:27.098821
3355 09:31:27.098881 Set Vref, RX VrefLevel [Byte0]: 39
3356 09:31:27.098942 [Byte1]: 39
3357 09:31:27.099001
3358 09:31:27.099061 Set Vref, RX VrefLevel [Byte0]: 40
3359 09:31:27.099121 [Byte1]: 40
3360 09:31:27.099181
3361 09:31:27.099241 Set Vref, RX VrefLevel [Byte0]: 41
3362 09:31:27.099302 [Byte1]: 41
3363 09:31:27.099362
3364 09:31:27.099422 Set Vref, RX VrefLevel [Byte0]: 42
3365 09:31:27.099482 [Byte1]: 42
3366 09:31:27.099542
3367 09:31:27.099602 Set Vref, RX VrefLevel [Byte0]: 43
3368 09:31:27.099662 [Byte1]: 43
3369 09:31:27.099722
3370 09:31:27.099782 Set Vref, RX VrefLevel [Byte0]: 44
3371 09:31:27.099842 [Byte1]: 44
3372 09:31:27.099902
3373 09:31:27.099962 Set Vref, RX VrefLevel [Byte0]: 45
3374 09:31:27.100021 [Byte1]: 45
3375 09:31:27.100081
3376 09:31:27.100141 Set Vref, RX VrefLevel [Byte0]: 46
3377 09:31:27.100201 [Byte1]: 46
3378 09:31:27.100260
3379 09:31:27.100320 Set Vref, RX VrefLevel [Byte0]: 47
3380 09:31:27.100380 [Byte1]: 47
3381 09:31:27.100441
3382 09:31:27.100502 Set Vref, RX VrefLevel [Byte0]: 48
3383 09:31:27.100561 [Byte1]: 48
3384 09:31:27.100621
3385 09:31:27.100681 Set Vref, RX VrefLevel [Byte0]: 49
3386 09:31:27.100741 [Byte1]: 49
3387 09:31:27.100801
3388 09:31:27.100866 Set Vref, RX VrefLevel [Byte0]: 50
3389 09:31:27.100971 [Byte1]: 50
3390 09:31:27.101037
3391 09:31:27.101098 Set Vref, RX VrefLevel [Byte0]: 51
3392 09:31:27.101160 [Byte1]: 51
3393 09:31:27.101220
3394 09:31:27.101280 Set Vref, RX VrefLevel [Byte0]: 52
3395 09:31:27.101340 [Byte1]: 52
3396 09:31:27.101400
3397 09:31:27.101460 Set Vref, RX VrefLevel [Byte0]: 53
3398 09:31:27.101521 [Byte1]: 53
3399 09:31:27.101581
3400 09:31:27.101641 Set Vref, RX VrefLevel [Byte0]: 54
3401 09:31:27.101701 [Byte1]: 54
3402 09:31:27.101761
3403 09:31:27.102021 Set Vref, RX VrefLevel [Byte0]: 55
3404 09:31:27.102088 [Byte1]: 55
3405 09:31:27.102149
3406 09:31:27.102222 Set Vref, RX VrefLevel [Byte0]: 56
3407 09:31:27.102283 [Byte1]: 56
3408 09:31:27.102354
3409 09:31:27.102408 Set Vref, RX VrefLevel [Byte0]: 57
3410 09:31:27.102463 [Byte1]: 57
3411 09:31:27.102518
3412 09:31:27.102572 Set Vref, RX VrefLevel [Byte0]: 58
3413 09:31:27.102627 [Byte1]: 58
3414 09:31:27.102682
3415 09:31:27.102736 Set Vref, RX VrefLevel [Byte0]: 59
3416 09:31:27.102791 [Byte1]: 59
3417 09:31:27.102845
3418 09:31:27.102899 Set Vref, RX VrefLevel [Byte0]: 60
3419 09:31:27.102954 [Byte1]: 60
3420 09:31:27.103008
3421 09:31:27.103062 Set Vref, RX VrefLevel [Byte0]: 61
3422 09:31:27.103117 [Byte1]: 61
3423 09:31:27.103172
3424 09:31:27.103226 Set Vref, RX VrefLevel [Byte0]: 62
3425 09:31:27.103281 [Byte1]: 62
3426 09:31:27.103334
3427 09:31:27.103388 Set Vref, RX VrefLevel [Byte0]: 63
3428 09:31:27.103442 [Byte1]: 63
3429 09:31:27.103496
3430 09:31:27.103550 Set Vref, RX VrefLevel [Byte0]: 64
3431 09:31:27.103605 [Byte1]: 64
3432 09:31:27.103659
3433 09:31:27.103713 Set Vref, RX VrefLevel [Byte0]: 65
3434 09:31:27.103766 [Byte1]: 65
3435 09:31:27.103821
3436 09:31:27.103875 Set Vref, RX VrefLevel [Byte0]: 66
3437 09:31:27.103929 [Byte1]: 66
3438 09:31:27.103983
3439 09:31:27.104037 Final RX Vref Byte 0 = 51 to rank0
3440 09:31:27.104091 Final RX Vref Byte 1 = 59 to rank0
3441 09:31:27.104146 Final RX Vref Byte 0 = 51 to rank1
3442 09:31:27.104201 Final RX Vref Byte 1 = 59 to rank1==
3443 09:31:27.104256 Dram Type= 6, Freq= 0, CH_1, rank 0
3444 09:31:27.104323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 09:31:27.104392 ==
3446 09:31:27.104447 DQS Delay:
3447 09:31:27.104502 DQS0 = 0, DQS1 = 0
3448 09:31:27.104557 DQM Delay:
3449 09:31:27.104611 DQM0 = 116, DQM1 = 111
3450 09:31:27.104666 DQ Delay:
3451 09:31:27.104721 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =110
3452 09:31:27.104776 DQ4 =114, DQ5 =128, DQ6 =126, DQ7 =112
3453 09:31:27.104830 DQ8 =100, DQ9 =100, DQ10 =114, DQ11 =100
3454 09:31:27.104885 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3455 09:31:27.104939
3456 09:31:27.104994
3457 09:31:27.105048 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3458 09:31:27.105104 CH1 RK0: MR19=403, MR18=3F6
3459 09:31:27.105159 CH1_RK0: MR19=0x403, MR18=0x3F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3460 09:31:27.105215
3461 09:31:27.105269 ----->DramcWriteLeveling(PI) begin...
3462 09:31:27.105325 ==
3463 09:31:27.105380 Dram Type= 6, Freq= 0, CH_1, rank 1
3464 09:31:27.105437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 09:31:27.105492 ==
3466 09:31:27.105547 Write leveling (Byte 0): 24 => 24
3467 09:31:27.105602 Write leveling (Byte 1): 27 => 27
3468 09:31:27.105657 DramcWriteLeveling(PI) end<-----
3469 09:31:27.105712
3470 09:31:27.105766 ==
3471 09:31:27.105821 Dram Type= 6, Freq= 0, CH_1, rank 1
3472 09:31:27.105876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3473 09:31:27.105932 ==
3474 09:31:27.105986 [Gating] SW mode calibration
3475 09:31:27.106041 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3476 09:31:27.106097 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3477 09:31:27.106152 0 15 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3478 09:31:27.106218 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 09:31:27.106273 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 09:31:27.106329 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 09:31:27.106384 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 09:31:27.106440 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 09:31:27.106494 0 15 24 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 0)
3484 09:31:27.106549 0 15 28 | B1->B0 | 2525 2424 | 0 0 | (0 1) (1 0)
3485 09:31:27.106604 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 09:31:27.106659 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 09:31:27.106713 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 09:31:27.106768 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 09:31:27.106823 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 09:31:27.106878 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 09:31:27.106934 1 0 24 | B1->B0 | 3838 2727 | 1 0 | (0 0) (0 0)
3492 09:31:27.106988 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3493 09:31:27.107043 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 09:31:27.107098 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 09:31:27.107153 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 09:31:27.107208 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 09:31:27.107286 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 09:31:27.107358 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 09:31:27.107412 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3500 09:31:27.107465 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3501 09:31:27.107518 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 09:31:27.107570 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 09:31:27.107622 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 09:31:27.107674 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 09:31:27.107727 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 09:31:27.107780 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 09:31:27.107832 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 09:31:27.107884 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 09:31:27.107937 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 09:31:27.107989 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 09:31:27.108042 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 09:31:27.108094 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 09:31:27.108146 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 09:31:27.108199 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 09:31:27.108252 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3516 09:31:27.108497 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3517 09:31:27.108558 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 09:31:27.108611 Total UI for P1: 0, mck2ui 16
3519 09:31:27.108664 best dqsien dly found for B0: ( 1, 3, 26)
3520 09:31:27.108717 Total UI for P1: 0, mck2ui 16
3521 09:31:27.108770 best dqsien dly found for B1: ( 1, 3, 26)
3522 09:31:27.108823 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3523 09:31:27.108876 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3524 09:31:27.108928
3525 09:31:27.108980 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3526 09:31:27.109032 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3527 09:31:27.109085 [Gating] SW calibration Done
3528 09:31:27.109137 ==
3529 09:31:27.109189 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 09:31:27.109242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 09:31:27.109295 ==
3532 09:31:27.109347 RX Vref Scan: 0
3533 09:31:27.109399
3534 09:31:27.109451 RX Vref 0 -> 0, step: 1
3535 09:31:27.109504
3536 09:31:27.109556 RX Delay -40 -> 252, step: 8
3537 09:31:27.109609 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3538 09:31:27.109661 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3539 09:31:27.109714 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3540 09:31:27.109766 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3541 09:31:27.109818 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3542 09:31:27.109870 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3543 09:31:27.109923 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3544 09:31:27.109975 iDelay=208, Bit 7, Center 119 (48 ~ 191) 144
3545 09:31:27.110027 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3546 09:31:27.110080 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3547 09:31:27.110132 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3548 09:31:27.110195 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3549 09:31:27.110286 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3550 09:31:27.110338 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3551 09:31:27.110391 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3552 09:31:27.110443 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3553 09:31:27.110495 ==
3554 09:31:27.110548 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 09:31:27.110603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 09:31:27.110681 ==
3557 09:31:27.110736 DQS Delay:
3558 09:31:27.110788 DQS0 = 0, DQS1 = 0
3559 09:31:27.110840 DQM Delay:
3560 09:31:27.110893 DQM0 = 117, DQM1 = 110
3561 09:31:27.110945 DQ Delay:
3562 09:31:27.110998 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3563 09:31:27.111051 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3564 09:31:27.111103 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3565 09:31:27.111157 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3566 09:31:27.111209
3567 09:31:27.111261
3568 09:31:27.111313 ==
3569 09:31:27.111366 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 09:31:27.111418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 09:31:27.111471 ==
3572 09:31:27.111523
3573 09:31:27.111574
3574 09:31:27.111626 TX Vref Scan disable
3575 09:31:27.111679 == TX Byte 0 ==
3576 09:31:27.111731 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3577 09:31:27.111784 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3578 09:31:27.111837 == TX Byte 1 ==
3579 09:31:27.111897 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3580 09:31:27.111953 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3581 09:31:27.112006 ==
3582 09:31:27.112059 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 09:31:27.112111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 09:31:27.112164 ==
3585 09:31:27.112216 TX Vref=22, minBit 2, minWin=26, winSum=427
3586 09:31:27.112269 TX Vref=24, minBit 3, minWin=26, winSum=431
3587 09:31:27.112321 TX Vref=26, minBit 8, minWin=26, winSum=436
3588 09:31:27.112374 TX Vref=28, minBit 8, minWin=26, winSum=432
3589 09:31:27.112426 TX Vref=30, minBit 8, minWin=26, winSum=434
3590 09:31:27.112479 TX Vref=32, minBit 8, minWin=26, winSum=433
3591 09:31:27.112531 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 26
3592 09:31:27.112584
3593 09:31:27.112636 Final TX Range 1 Vref 26
3594 09:31:27.112689
3595 09:31:27.112740 ==
3596 09:31:27.112792 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 09:31:27.112844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 09:31:27.112897 ==
3599 09:31:27.112949
3600 09:31:27.113001
3601 09:31:27.113053 TX Vref Scan disable
3602 09:31:27.113106 == TX Byte 0 ==
3603 09:31:27.113158 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3604 09:31:27.113210 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3605 09:31:27.113262 == TX Byte 1 ==
3606 09:31:27.113314 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3607 09:31:27.113366 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3608 09:31:27.113418
3609 09:31:27.113470 [DATLAT]
3610 09:31:27.113521 Freq=1200, CH1 RK1
3611 09:31:27.113574
3612 09:31:27.113626 DATLAT Default: 0xd
3613 09:31:27.113678 0, 0xFFFF, sum = 0
3614 09:31:27.113732 1, 0xFFFF, sum = 0
3615 09:31:27.113785 2, 0xFFFF, sum = 0
3616 09:31:27.113839 3, 0xFFFF, sum = 0
3617 09:31:27.113892 4, 0xFFFF, sum = 0
3618 09:31:27.113945 5, 0xFFFF, sum = 0
3619 09:31:27.114016 6, 0xFFFF, sum = 0
3620 09:31:27.114103 7, 0xFFFF, sum = 0
3621 09:31:27.114189 8, 0xFFFF, sum = 0
3622 09:31:27.114246 9, 0xFFFF, sum = 0
3623 09:31:27.114299 10, 0xFFFF, sum = 0
3624 09:31:27.114353 11, 0xFFFF, sum = 0
3625 09:31:27.114406 12, 0x0, sum = 1
3626 09:31:27.114460 13, 0x0, sum = 2
3627 09:31:27.114513 14, 0x0, sum = 3
3628 09:31:27.114567 15, 0x0, sum = 4
3629 09:31:27.114619 best_step = 13
3630 09:31:27.114671
3631 09:31:27.114724 ==
3632 09:31:27.114776 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 09:31:27.114829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 09:31:27.114882 ==
3635 09:31:27.114935 RX Vref Scan: 0
3636 09:31:27.114987
3637 09:31:27.115039 RX Vref 0 -> 0, step: 1
3638 09:31:27.115092
3639 09:31:27.115144 RX Delay -21 -> 252, step: 4
3640 09:31:27.115196 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3641 09:31:27.115249 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3642 09:31:27.115302 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3643 09:31:27.115354 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3644 09:31:27.115407 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3645 09:31:27.115459 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3646 09:31:27.115511 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3647 09:31:27.115563 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3648 09:31:27.115615 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3649 09:31:27.115667 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3650 09:31:27.115719 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3651 09:31:27.115772 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3652 09:31:27.115825 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3653 09:31:27.115877 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3654 09:31:27.116121 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3655 09:31:27.116179 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3656 09:31:27.116232 ==
3657 09:31:27.116285 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 09:31:27.116337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 09:31:27.116391 ==
3660 09:31:27.116443 DQS Delay:
3661 09:31:27.116495 DQS0 = 0, DQS1 = 0
3662 09:31:27.116547 DQM Delay:
3663 09:31:27.116599 DQM0 = 117, DQM1 = 110
3664 09:31:27.116651 DQ Delay:
3665 09:31:27.116704 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3666 09:31:27.116756 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =116
3667 09:31:27.116808 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =100
3668 09:31:27.116860 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =120
3669 09:31:27.116912
3670 09:31:27.116963
3671 09:31:27.117016 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 415 ps
3672 09:31:27.117070 CH1 RK1: MR19=303, MR18=F2EC
3673 09:31:27.117122 CH1_RK1: MR19=0x303, MR18=0xF2EC, DQSOSC=415, MR23=63, INC=38, DEC=25
3674 09:31:27.117175 [RxdqsGatingPostProcess] freq 1200
3675 09:31:27.117227 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3676 09:31:27.117280 best DQS0 dly(2T, 0.5T) = (0, 11)
3677 09:31:27.117332 best DQS1 dly(2T, 0.5T) = (0, 11)
3678 09:31:27.117384 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3679 09:31:27.117436 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3680 09:31:27.117488 best DQS0 dly(2T, 0.5T) = (0, 11)
3681 09:31:27.117557 best DQS1 dly(2T, 0.5T) = (0, 11)
3682 09:31:27.117618 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3683 09:31:27.117671 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3684 09:31:27.117724 Pre-setting of DQS Precalculation
3685 09:31:27.117777 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3686 09:31:27.117831 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3687 09:31:27.117884 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3688 09:31:27.117937
3689 09:31:27.118002
3690 09:31:27.118055 [Calibration Summary] 2400 Mbps
3691 09:31:27.118108 CH 0, Rank 0
3692 09:31:27.118168 SW Impedance : PASS
3693 09:31:27.118223 DUTY Scan : NO K
3694 09:31:27.118276 ZQ Calibration : PASS
3695 09:31:27.118328 Jitter Meter : NO K
3696 09:31:27.118382 CBT Training : PASS
3697 09:31:27.118434 Write leveling : PASS
3698 09:31:27.118487 RX DQS gating : PASS
3699 09:31:27.118539 RX DQ/DQS(RDDQC) : PASS
3700 09:31:27.118591 TX DQ/DQS : PASS
3701 09:31:27.118644 RX DATLAT : PASS
3702 09:31:27.118696 RX DQ/DQS(Engine): PASS
3703 09:31:27.118748 TX OE : NO K
3704 09:31:27.118801 All Pass.
3705 09:31:27.118854
3706 09:31:27.118906 CH 0, Rank 1
3707 09:31:27.118958 SW Impedance : PASS
3708 09:31:27.119011 DUTY Scan : NO K
3709 09:31:27.119063 ZQ Calibration : PASS
3710 09:31:27.119115 Jitter Meter : NO K
3711 09:31:27.119167 CBT Training : PASS
3712 09:31:27.119218 Write leveling : PASS
3713 09:31:27.119270 RX DQS gating : PASS
3714 09:31:27.119322 RX DQ/DQS(RDDQC) : PASS
3715 09:31:27.119374 TX DQ/DQS : PASS
3716 09:31:27.119427 RX DATLAT : PASS
3717 09:31:27.119479 RX DQ/DQS(Engine): PASS
3718 09:31:27.119531 TX OE : NO K
3719 09:31:27.119584 All Pass.
3720 09:31:27.119636
3721 09:31:27.119688 CH 1, Rank 0
3722 09:31:27.119740 SW Impedance : PASS
3723 09:31:27.119792 DUTY Scan : NO K
3724 09:31:27.119844 ZQ Calibration : PASS
3725 09:31:27.119896 Jitter Meter : NO K
3726 09:31:27.119948 CBT Training : PASS
3727 09:31:27.120000 Write leveling : PASS
3728 09:31:27.120052 RX DQS gating : PASS
3729 09:31:27.120104 RX DQ/DQS(RDDQC) : PASS
3730 09:31:27.120156 TX DQ/DQS : PASS
3731 09:31:27.120209 RX DATLAT : PASS
3732 09:31:27.120261 RX DQ/DQS(Engine): PASS
3733 09:31:27.120313 TX OE : NO K
3734 09:31:27.120365 All Pass.
3735 09:31:27.120417
3736 09:31:27.120496 CH 1, Rank 1
3737 09:31:27.120551 SW Impedance : PASS
3738 09:31:27.120604 DUTY Scan : NO K
3739 09:31:27.120656 ZQ Calibration : PASS
3740 09:31:27.120709 Jitter Meter : NO K
3741 09:31:27.120762 CBT Training : PASS
3742 09:31:27.120814 Write leveling : PASS
3743 09:31:27.120867 RX DQS gating : PASS
3744 09:31:27.120919 RX DQ/DQS(RDDQC) : PASS
3745 09:31:27.120971 TX DQ/DQS : PASS
3746 09:31:27.121024 RX DATLAT : PASS
3747 09:31:27.121076 RX DQ/DQS(Engine): PASS
3748 09:31:27.121129 TX OE : NO K
3749 09:31:27.121181 All Pass.
3750 09:31:27.121233
3751 09:31:27.121285 DramC Write-DBI off
3752 09:31:27.121338 PER_BANK_REFRESH: Hybrid Mode
3753 09:31:27.121391 TX_TRACKING: ON
3754 09:31:27.121444 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3755 09:31:27.121497 [FAST_K] Save calibration result to emmc
3756 09:31:27.121550 dramc_set_vcore_voltage set vcore to 650000
3757 09:31:27.121602 Read voltage for 600, 5
3758 09:31:27.121654 Vio18 = 0
3759 09:31:27.121706 Vcore = 650000
3760 09:31:27.121759 Vdram = 0
3761 09:31:27.121811 Vddq = 0
3762 09:31:27.121862 Vmddr = 0
3763 09:31:27.121915 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3764 09:31:27.121968 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3765 09:31:27.122021 MEM_TYPE=3, freq_sel=19
3766 09:31:27.122073 sv_algorithm_assistance_LP4_1600
3767 09:31:27.122125 ============ PULL DRAM RESETB DOWN ============
3768 09:31:27.122187 ========== PULL DRAM RESETB DOWN end =========
3769 09:31:27.122241 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3770 09:31:27.122294 ===================================
3771 09:31:27.122347 LPDDR4 DRAM CONFIGURATION
3772 09:31:27.122401 ===================================
3773 09:31:27.122454 EX_ROW_EN[0] = 0x0
3774 09:31:27.122506 EX_ROW_EN[1] = 0x0
3775 09:31:27.122558 LP4Y_EN = 0x0
3776 09:31:27.122610 WORK_FSP = 0x0
3777 09:31:27.122663 WL = 0x2
3778 09:31:27.122715 RL = 0x2
3779 09:31:27.122767 BL = 0x2
3780 09:31:27.122819 RPST = 0x0
3781 09:31:27.122873 RD_PRE = 0x0
3782 09:31:27.122925 WR_PRE = 0x1
3783 09:31:27.122977 WR_PST = 0x0
3784 09:31:27.123029 DBI_WR = 0x0
3785 09:31:27.123081 DBI_RD = 0x0
3786 09:31:27.123134 OTF = 0x1
3787 09:31:27.123186 ===================================
3788 09:31:27.123238 ===================================
3789 09:31:27.123291 ANA top config
3790 09:31:27.123343 ===================================
3791 09:31:27.123396 DLL_ASYNC_EN = 0
3792 09:31:27.123449 ALL_SLAVE_EN = 1
3793 09:31:27.123501 NEW_RANK_MODE = 1
3794 09:31:27.123555 DLL_IDLE_MODE = 1
3795 09:31:27.123607 LP45_APHY_COMB_EN = 1
3796 09:31:27.123659 TX_ODT_DIS = 1
3797 09:31:27.123712 NEW_8X_MODE = 1
3798 09:31:27.123765 ===================================
3799 09:31:27.123817 ===================================
3800 09:31:27.124063 data_rate = 1200
3801 09:31:27.124124 CKR = 1
3802 09:31:27.124180 DQ_P2S_RATIO = 8
3803 09:31:27.124233 ===================================
3804 09:31:27.124286 CA_P2S_RATIO = 8
3805 09:31:27.124338 DQ_CA_OPEN = 0
3806 09:31:27.124391 DQ_SEMI_OPEN = 0
3807 09:31:27.124457 CA_SEMI_OPEN = 0
3808 09:31:27.124512 CA_FULL_RATE = 0
3809 09:31:27.124565 DQ_CKDIV4_EN = 1
3810 09:31:27.124618 CA_CKDIV4_EN = 1
3811 09:31:27.124670 CA_PREDIV_EN = 0
3812 09:31:27.124723 PH8_DLY = 0
3813 09:31:27.124777 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3814 09:31:27.124830 DQ_AAMCK_DIV = 4
3815 09:31:27.124883 CA_AAMCK_DIV = 4
3816 09:31:27.124935 CA_ADMCK_DIV = 4
3817 09:31:27.124988 DQ_TRACK_CA_EN = 0
3818 09:31:27.125040 CA_PICK = 600
3819 09:31:27.125092 CA_MCKIO = 600
3820 09:31:27.125144 MCKIO_SEMI = 0
3821 09:31:27.125198 PLL_FREQ = 2288
3822 09:31:27.125251 DQ_UI_PI_RATIO = 32
3823 09:31:27.125304 CA_UI_PI_RATIO = 0
3824 09:31:27.125357 ===================================
3825 09:31:27.125410 ===================================
3826 09:31:27.125462 memory_type:LPDDR4
3827 09:31:27.125515 GP_NUM : 10
3828 09:31:27.125567 SRAM_EN : 1
3829 09:31:27.125620 MD32_EN : 0
3830 09:31:27.125672 ===================================
3831 09:31:27.125725 [ANA_INIT] >>>>>>>>>>>>>>
3832 09:31:27.125778 <<<<<< [CONFIGURE PHASE]: ANA_TX
3833 09:31:27.125831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3834 09:31:27.125884 ===================================
3835 09:31:27.125937 data_rate = 1200,PCW = 0X5800
3836 09:31:27.125990 ===================================
3837 09:31:27.126042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3838 09:31:27.126096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3839 09:31:27.126148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3840 09:31:27.126212 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3841 09:31:27.126265 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3842 09:31:27.126318 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3843 09:31:27.126370 [ANA_INIT] flow start
3844 09:31:27.126423 [ANA_INIT] PLL >>>>>>>>
3845 09:31:27.126474 [ANA_INIT] PLL <<<<<<<<
3846 09:31:27.126526 [ANA_INIT] MIDPI >>>>>>>>
3847 09:31:27.126579 [ANA_INIT] MIDPI <<<<<<<<
3848 09:31:27.126631 [ANA_INIT] DLL >>>>>>>>
3849 09:31:27.126682 [ANA_INIT] flow end
3850 09:31:27.126734 ============ LP4 DIFF to SE enter ============
3851 09:31:27.126788 ============ LP4 DIFF to SE exit ============
3852 09:31:27.126841 [ANA_INIT] <<<<<<<<<<<<<
3853 09:31:27.126893 [Flow] Enable top DCM control >>>>>
3854 09:31:27.126946 [Flow] Enable top DCM control <<<<<
3855 09:31:27.126999 Enable DLL master slave shuffle
3856 09:31:27.127052 ==============================================================
3857 09:31:27.127105 Gating Mode config
3858 09:31:27.127158 ==============================================================
3859 09:31:27.127211 Config description:
3860 09:31:27.127288 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3861 09:31:27.127347 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3862 09:31:27.127401 SELPH_MODE 0: By rank 1: By Phase
3863 09:31:27.127455 ==============================================================
3864 09:31:27.127508 GAT_TRACK_EN = 1
3865 09:31:27.127561 RX_GATING_MODE = 2
3866 09:31:27.127613 RX_GATING_TRACK_MODE = 2
3867 09:31:27.127666 SELPH_MODE = 1
3868 09:31:27.127718 PICG_EARLY_EN = 1
3869 09:31:27.127771 VALID_LAT_VALUE = 1
3870 09:31:27.127824 ==============================================================
3871 09:31:27.127877 Enter into Gating configuration >>>>
3872 09:31:27.127930 Exit from Gating configuration <<<<
3873 09:31:27.127995 Enter into DVFS_PRE_config >>>>>
3874 09:31:27.137519 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3875 09:31:27.141126 Exit from DVFS_PRE_config <<<<<
3876 09:31:27.144088 Enter into PICG configuration >>>>
3877 09:31:27.147049 Exit from PICG configuration <<<<
3878 09:31:27.150703 [RX_INPUT] configuration >>>>>
3879 09:31:27.154030 [RX_INPUT] configuration <<<<<
3880 09:31:27.156732 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3881 09:31:27.164086 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3882 09:31:27.170148 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3883 09:31:27.177106 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3884 09:31:27.183522 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3885 09:31:27.190042 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3886 09:31:27.193130 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3887 09:31:27.196670 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3888 09:31:27.200606 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3889 09:31:27.207103 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3890 09:31:27.209643 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3891 09:31:27.213736 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3892 09:31:27.216811 ===================================
3893 09:31:27.219957 LPDDR4 DRAM CONFIGURATION
3894 09:31:27.223219 ===================================
3895 09:31:27.223573 EX_ROW_EN[0] = 0x0
3896 09:31:27.226782 EX_ROW_EN[1] = 0x0
3897 09:31:27.229600 LP4Y_EN = 0x0
3898 09:31:27.230012 WORK_FSP = 0x0
3899 09:31:27.233191 WL = 0x2
3900 09:31:27.233601 RL = 0x2
3901 09:31:27.236566 BL = 0x2
3902 09:31:27.237066 RPST = 0x0
3903 09:31:27.239694 RD_PRE = 0x0
3904 09:31:27.240173 WR_PRE = 0x1
3905 09:31:27.243049 WR_PST = 0x0
3906 09:31:27.243504 DBI_WR = 0x0
3907 09:31:27.246731 DBI_RD = 0x0
3908 09:31:27.247280 OTF = 0x1
3909 09:31:27.249641 ===================================
3910 09:31:27.253245 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3911 09:31:27.259475 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3912 09:31:27.262615 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3913 09:31:27.265898 ===================================
3914 09:31:27.269341 LPDDR4 DRAM CONFIGURATION
3915 09:31:27.272431 ===================================
3916 09:31:27.272845 EX_ROW_EN[0] = 0x10
3917 09:31:27.276257 EX_ROW_EN[1] = 0x0
3918 09:31:27.279620 LP4Y_EN = 0x0
3919 09:31:27.280052 WORK_FSP = 0x0
3920 09:31:27.282931 WL = 0x2
3921 09:31:27.283341 RL = 0x2
3922 09:31:27.285833 BL = 0x2
3923 09:31:27.286285 RPST = 0x0
3924 09:31:27.289548 RD_PRE = 0x0
3925 09:31:27.290064 WR_PRE = 0x1
3926 09:31:27.292217 WR_PST = 0x0
3927 09:31:27.292628 DBI_WR = 0x0
3928 09:31:27.295975 DBI_RD = 0x0
3929 09:31:27.296493 OTF = 0x1
3930 09:31:27.298977 ===================================
3931 09:31:27.306119 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3932 09:31:27.310556 nWR fixed to 30
3933 09:31:27.313597 [ModeRegInit_LP4] CH0 RK0
3934 09:31:27.314115 [ModeRegInit_LP4] CH0 RK1
3935 09:31:27.316730 [ModeRegInit_LP4] CH1 RK0
3936 09:31:27.320645 [ModeRegInit_LP4] CH1 RK1
3937 09:31:27.321085 match AC timing 17
3938 09:31:27.326365 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3939 09:31:27.329738 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3940 09:31:27.333273 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3941 09:31:27.339889 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3942 09:31:27.343099 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3943 09:31:27.343518 ==
3944 09:31:27.346843 Dram Type= 6, Freq= 0, CH_0, rank 0
3945 09:31:27.349998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3946 09:31:27.350556 ==
3947 09:31:27.356200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3948 09:31:27.363028 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3949 09:31:27.366594 [CA 0] Center 36 (6~66) winsize 61
3950 09:31:27.369830 [CA 1] Center 36 (6~66) winsize 61
3951 09:31:27.372993 [CA 2] Center 34 (4~65) winsize 62
3952 09:31:27.375912 [CA 3] Center 34 (4~65) winsize 62
3953 09:31:27.379379 [CA 4] Center 33 (3~64) winsize 62
3954 09:31:27.382680 [CA 5] Center 33 (3~64) winsize 62
3955 09:31:27.383240
3956 09:31:27.385969 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3957 09:31:27.386455
3958 09:31:27.389728 [CATrainingPosCal] consider 1 rank data
3959 09:31:27.392922 u2DelayCellTimex100 = 270/100 ps
3960 09:31:27.396120 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3961 09:31:27.399254 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3962 09:31:27.402797 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3963 09:31:27.409038 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3964 09:31:27.412973 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3965 09:31:27.415849 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3966 09:31:27.416403
3967 09:31:27.419125 CA PerBit enable=1, Macro0, CA PI delay=33
3968 09:31:27.419678
3969 09:31:27.421948 [CBTSetCACLKResult] CA Dly = 33
3970 09:31:27.422449 CS Dly: 5 (0~36)
3971 09:31:27.422822 ==
3972 09:31:27.425873 Dram Type= 6, Freq= 0, CH_0, rank 1
3973 09:31:27.432621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 09:31:27.433191 ==
3975 09:31:27.435549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3976 09:31:27.442086 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3977 09:31:27.445331 [CA 0] Center 36 (6~66) winsize 61
3978 09:31:27.448681 [CA 1] Center 36 (6~66) winsize 61
3979 09:31:27.452463 [CA 2] Center 33 (3~64) winsize 62
3980 09:31:27.455221 [CA 3] Center 33 (3~64) winsize 62
3981 09:31:27.458606 [CA 4] Center 33 (2~64) winsize 63
3982 09:31:27.462061 [CA 5] Center 33 (2~64) winsize 63
3983 09:31:27.462660
3984 09:31:27.465404 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3985 09:31:27.465861
3986 09:31:27.468298 [CATrainingPosCal] consider 2 rank data
3987 09:31:27.471752 u2DelayCellTimex100 = 270/100 ps
3988 09:31:27.475335 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3989 09:31:27.481839 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3990 09:31:27.485395 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3991 09:31:27.488621 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3992 09:31:27.491751 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3993 09:31:27.495486 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3994 09:31:27.495942
3995 09:31:27.498308 CA PerBit enable=1, Macro0, CA PI delay=33
3996 09:31:27.498872
3997 09:31:27.501998 [CBTSetCACLKResult] CA Dly = 33
3998 09:31:27.504765 CS Dly: 6 (0~38)
3999 09:31:27.505320
4000 09:31:27.507994 ----->DramcWriteLeveling(PI) begin...
4001 09:31:27.508464 ==
4002 09:31:27.511735 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 09:31:27.515080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 09:31:27.515640 ==
4005 09:31:27.517782 Write leveling (Byte 0): 31 => 31
4006 09:31:27.521268 Write leveling (Byte 1): 29 => 29
4007 09:31:27.525054 DramcWriteLeveling(PI) end<-----
4008 09:31:27.525612
4009 09:31:27.525982 ==
4010 09:31:27.527548 Dram Type= 6, Freq= 0, CH_0, rank 0
4011 09:31:27.530829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 09:31:27.531338 ==
4013 09:31:27.534093 [Gating] SW mode calibration
4014 09:31:27.540753 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4015 09:31:27.547371 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4016 09:31:27.550550 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4017 09:31:27.554479 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4018 09:31:27.560752 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4019 09:31:27.563932 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4020 09:31:27.570402 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (0 0)
4021 09:31:27.573993 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 09:31:27.577156 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 09:31:27.580594 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 09:31:27.587223 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 09:31:27.590726 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 09:31:27.593428 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 09:31:27.600483 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4028 09:31:27.603900 0 10 16 | B1->B0 | 3434 4242 | 0 0 | (0 0) (0 0)
4029 09:31:27.607413 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 09:31:27.614008 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 09:31:27.617574 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 09:31:27.620155 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 09:31:27.627145 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 09:31:27.630261 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 09:31:27.633537 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 09:31:27.640197 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 09:31:27.643210 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 09:31:27.646438 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 09:31:27.652848 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 09:31:27.656748 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 09:31:27.659588 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 09:31:27.666380 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 09:31:27.669589 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 09:31:27.673139 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 09:31:27.679669 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 09:31:27.682426 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 09:31:27.686014 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 09:31:27.692845 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 09:31:27.696051 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 09:31:27.698879 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 09:31:27.706060 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4052 09:31:27.709181 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4053 09:31:27.712484 Total UI for P1: 0, mck2ui 16
4054 09:31:27.715809 best dqsien dly found for B0: ( 0, 13, 12)
4055 09:31:27.719034 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 09:31:27.722578 Total UI for P1: 0, mck2ui 16
4057 09:31:27.725473 best dqsien dly found for B1: ( 0, 13, 14)
4058 09:31:27.728682 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4059 09:31:27.735488 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4060 09:31:27.735941
4061 09:31:27.738905 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4062 09:31:27.741971 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4063 09:31:27.745542 [Gating] SW calibration Done
4064 09:31:27.746092 ==
4065 09:31:27.748681 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 09:31:27.752606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 09:31:27.753066 ==
4068 09:31:27.755181 RX Vref Scan: 0
4069 09:31:27.755633
4070 09:31:27.755994 RX Vref 0 -> 0, step: 1
4071 09:31:27.756336
4072 09:31:27.758523 RX Delay -230 -> 252, step: 16
4073 09:31:27.761834 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4074 09:31:27.768875 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4075 09:31:27.772101 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4076 09:31:27.774781 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4077 09:31:27.778280 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4078 09:31:27.784841 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4079 09:31:27.788251 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4080 09:31:27.791525 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4081 09:31:27.794994 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4082 09:31:27.797938 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4083 09:31:27.805392 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4084 09:31:27.808250 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4085 09:31:27.811573 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4086 09:31:27.814602 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4087 09:31:27.821535 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4088 09:31:27.824417 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4089 09:31:27.824876 ==
4090 09:31:27.828187 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 09:31:27.831510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 09:31:27.832078 ==
4093 09:31:27.834945 DQS Delay:
4094 09:31:27.835498 DQS0 = 0, DQS1 = 0
4095 09:31:27.837844 DQM Delay:
4096 09:31:27.838437 DQM0 = 43, DQM1 = 29
4097 09:31:27.838814 DQ Delay:
4098 09:31:27.841009 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4099 09:31:27.844295 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4100 09:31:27.848236 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4101 09:31:27.851084 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4102 09:31:27.851545
4103 09:31:27.851905
4104 09:31:27.854129 ==
4105 09:31:27.857734 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 09:31:27.860696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 09:31:27.861164 ==
4108 09:31:27.861591
4109 09:31:27.862300
4110 09:31:27.863822 TX Vref Scan disable
4111 09:31:27.864279 == TX Byte 0 ==
4112 09:31:27.870159 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4113 09:31:27.873618 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4114 09:31:27.873927 == TX Byte 1 ==
4115 09:31:27.880519 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4116 09:31:27.883574 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4117 09:31:27.883756 ==
4118 09:31:27.886887 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 09:31:27.890307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 09:31:27.890439 ==
4121 09:31:27.890543
4122 09:31:27.890640
4123 09:31:27.893617 TX Vref Scan disable
4124 09:31:27.896863 == TX Byte 0 ==
4125 09:31:27.899806 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4126 09:31:27.903246 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4127 09:31:27.906890 == TX Byte 1 ==
4128 09:31:27.909701 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4129 09:31:27.913263 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4130 09:31:27.916457
4131 09:31:27.916538 [DATLAT]
4132 09:31:27.916603 Freq=600, CH0 RK0
4133 09:31:27.916664
4134 09:31:27.919842 DATLAT Default: 0x9
4135 09:31:27.919926 0, 0xFFFF, sum = 0
4136 09:31:27.923123 1, 0xFFFF, sum = 0
4137 09:31:27.923206 2, 0xFFFF, sum = 0
4138 09:31:27.926147 3, 0xFFFF, sum = 0
4139 09:31:27.929349 4, 0xFFFF, sum = 0
4140 09:31:27.929434 5, 0xFFFF, sum = 0
4141 09:31:27.932785 6, 0xFFFF, sum = 0
4142 09:31:27.932868 7, 0xFFFF, sum = 0
4143 09:31:27.936166 8, 0x0, sum = 1
4144 09:31:27.936250 9, 0x0, sum = 2
4145 09:31:27.936317 10, 0x0, sum = 3
4146 09:31:27.939506 11, 0x0, sum = 4
4147 09:31:27.939588 best_step = 9
4148 09:31:27.939653
4149 09:31:27.939713 ==
4150 09:31:27.943254 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 09:31:27.949379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 09:31:27.949462 ==
4153 09:31:27.949527 RX Vref Scan: 1
4154 09:31:27.949587
4155 09:31:27.952716 RX Vref 0 -> 0, step: 1
4156 09:31:27.952797
4157 09:31:27.956027 RX Delay -195 -> 252, step: 8
4158 09:31:27.956131
4159 09:31:27.959356 Set Vref, RX VrefLevel [Byte0]: 61
4160 09:31:27.962434 [Byte1]: 59
4161 09:31:27.962517
4162 09:31:27.965870 Final RX Vref Byte 0 = 61 to rank0
4163 09:31:27.969102 Final RX Vref Byte 1 = 59 to rank0
4164 09:31:27.972328 Final RX Vref Byte 0 = 61 to rank1
4165 09:31:27.975793 Final RX Vref Byte 1 = 59 to rank1==
4166 09:31:27.979182 Dram Type= 6, Freq= 0, CH_0, rank 0
4167 09:31:27.982557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 09:31:27.982640 ==
4169 09:31:27.985802 DQS Delay:
4170 09:31:27.985883 DQS0 = 0, DQS1 = 0
4171 09:31:27.988871 DQM Delay:
4172 09:31:27.988953 DQM0 = 42, DQM1 = 32
4173 09:31:27.989018 DQ Delay:
4174 09:31:27.992159 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4175 09:31:27.995409 DQ4 =40, DQ5 =32, DQ6 =52, DQ7 =48
4176 09:31:27.998649 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4177 09:31:28.001989 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4178 09:31:28.002071
4179 09:31:28.005327
4180 09:31:28.012246 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a42, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 389 ps
4181 09:31:28.015336 CH0 RK0: MR19=808, MR18=6A42
4182 09:31:28.021900 CH0_RK0: MR19=0x808, MR18=0x6A42, DQSOSC=389, MR23=63, INC=173, DEC=115
4183 09:31:28.021987
4184 09:31:28.025421 ----->DramcWriteLeveling(PI) begin...
4185 09:31:28.025504 ==
4186 09:31:28.028349 Dram Type= 6, Freq= 0, CH_0, rank 1
4187 09:31:28.031921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 09:31:28.032010 ==
4189 09:31:28.034967 Write leveling (Byte 0): 33 => 33
4190 09:31:28.038128 Write leveling (Byte 1): 33 => 33
4191 09:31:28.041990 DramcWriteLeveling(PI) end<-----
4192 09:31:28.042075
4193 09:31:28.042140 ==
4194 09:31:28.045203 Dram Type= 6, Freq= 0, CH_0, rank 1
4195 09:31:28.048399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 09:31:28.048485 ==
4197 09:31:28.051964 [Gating] SW mode calibration
4198 09:31:28.058025 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4199 09:31:28.064928 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4200 09:31:28.068140 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4201 09:31:28.075112 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4202 09:31:28.077776 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4203 09:31:28.081384 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4204 09:31:28.087801 0 9 16 | B1->B0 | 3030 2828 | 0 0 | (1 1) (0 0)
4205 09:31:28.091205 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 09:31:28.094284 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 09:31:28.097875 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 09:31:28.104575 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 09:31:28.107835 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 09:31:28.114682 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 09:31:28.117603 0 10 12 | B1->B0 | 2323 2828 | 1 0 | (0 0) (0 0)
4212 09:31:28.121159 0 10 16 | B1->B0 | 3939 4141 | 0 0 | (1 1) (0 0)
4213 09:31:28.127489 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 09:31:28.130828 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 09:31:28.134548 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 09:31:28.137384 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 09:31:28.143845 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 09:31:28.147203 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 09:31:28.153923 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4220 09:31:28.157122 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4221 09:31:28.160573 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 09:31:28.164035 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 09:31:28.170670 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 09:31:28.173808 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 09:31:28.177284 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 09:31:28.183437 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 09:31:28.186852 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 09:31:28.190383 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 09:31:28.196985 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 09:31:28.200015 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 09:31:28.203573 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 09:31:28.210373 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 09:31:28.213289 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 09:31:28.216424 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4235 09:31:28.222902 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4236 09:31:28.226733 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4237 09:31:28.229711 Total UI for P1: 0, mck2ui 16
4238 09:31:28.233276 best dqsien dly found for B0: ( 0, 13, 10)
4239 09:31:28.236186 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 09:31:28.239620 Total UI for P1: 0, mck2ui 16
4241 09:31:28.243103 best dqsien dly found for B1: ( 0, 13, 14)
4242 09:31:28.246487 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4243 09:31:28.252950 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4244 09:31:28.253052
4245 09:31:28.256122 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4246 09:31:28.259349 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4247 09:31:28.262678 [Gating] SW calibration Done
4248 09:31:28.262767 ==
4249 09:31:28.266057 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 09:31:28.269602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 09:31:28.269692 ==
4252 09:31:28.272670 RX Vref Scan: 0
4253 09:31:28.272753
4254 09:31:28.272818 RX Vref 0 -> 0, step: 1
4255 09:31:28.272878
4256 09:31:28.276112 RX Delay -230 -> 252, step: 16
4257 09:31:28.279847 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4258 09:31:28.286098 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4259 09:31:28.289548 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4260 09:31:28.292730 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4261 09:31:28.296181 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4262 09:31:28.302640 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4263 09:31:28.306209 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4264 09:31:28.309061 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4265 09:31:28.312352 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4266 09:31:28.315991 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4267 09:31:28.322414 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4268 09:31:28.325508 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4269 09:31:28.328845 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4270 09:31:28.332050 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4271 09:31:28.338928 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4272 09:31:28.341885 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4273 09:31:28.341968 ==
4274 09:31:28.345554 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 09:31:28.348675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 09:31:28.348759 ==
4277 09:31:28.352074 DQS Delay:
4278 09:31:28.352155 DQS0 = 0, DQS1 = 0
4279 09:31:28.355387 DQM Delay:
4280 09:31:28.355467 DQM0 = 42, DQM1 = 35
4281 09:31:28.355531 DQ Delay:
4282 09:31:28.358352 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4283 09:31:28.361861 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4284 09:31:28.365683 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4285 09:31:28.368680 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4286 09:31:28.368764
4287 09:31:28.368881
4288 09:31:28.371792 ==
4289 09:31:28.375307 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 09:31:28.378026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 09:31:28.378126 ==
4292 09:31:28.378222
4293 09:31:28.378282
4294 09:31:28.381418 TX Vref Scan disable
4295 09:31:28.381499 == TX Byte 0 ==
4296 09:31:28.388134 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4297 09:31:28.391743 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4298 09:31:28.391829 == TX Byte 1 ==
4299 09:31:28.398390 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4300 09:31:28.401330 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4301 09:31:28.401413 ==
4302 09:31:28.405320 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 09:31:28.407732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 09:31:28.407813 ==
4305 09:31:28.407877
4306 09:31:28.407936
4307 09:31:28.411189 TX Vref Scan disable
4308 09:31:28.414701 == TX Byte 0 ==
4309 09:31:28.417703 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4310 09:31:28.421165 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4311 09:31:28.424083 == TX Byte 1 ==
4312 09:31:28.427849 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4313 09:31:28.433931 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4314 09:31:28.434018
4315 09:31:28.434083 [DATLAT]
4316 09:31:28.434142 Freq=600, CH0 RK1
4317 09:31:28.434246
4318 09:31:28.437479 DATLAT Default: 0x9
4319 09:31:28.437564 0, 0xFFFF, sum = 0
4320 09:31:28.440945 1, 0xFFFF, sum = 0
4321 09:31:28.441035 2, 0xFFFF, sum = 0
4322 09:31:28.443743 3, 0xFFFF, sum = 0
4323 09:31:28.447711 4, 0xFFFF, sum = 0
4324 09:31:28.447899 5, 0xFFFF, sum = 0
4325 09:31:28.450365 6, 0xFFFF, sum = 0
4326 09:31:28.450471 7, 0xFFFF, sum = 0
4327 09:31:28.454150 8, 0x0, sum = 1
4328 09:31:28.454348 9, 0x0, sum = 2
4329 09:31:28.454462 10, 0x0, sum = 3
4330 09:31:28.457187 11, 0x0, sum = 4
4331 09:31:28.457307 best_step = 9
4332 09:31:28.457417
4333 09:31:28.457532 ==
4334 09:31:28.460582 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 09:31:28.467316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 09:31:28.467414 ==
4337 09:31:28.467480 RX Vref Scan: 0
4338 09:31:28.467541
4339 09:31:28.470457 RX Vref 0 -> 0, step: 1
4340 09:31:28.470537
4341 09:31:28.473908 RX Delay -179 -> 252, step: 8
4342 09:31:28.480470 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4343 09:31:28.483529 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4344 09:31:28.486744 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4345 09:31:28.490148 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4346 09:31:28.493237 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4347 09:31:28.500080 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4348 09:31:28.503438 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4349 09:31:28.506470 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4350 09:31:28.510007 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4351 09:31:28.516320 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4352 09:31:28.519873 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4353 09:31:28.522774 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4354 09:31:28.526591 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4355 09:31:28.532943 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4356 09:31:28.535972 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4357 09:31:28.539170 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4358 09:31:28.539253 ==
4359 09:31:28.542648 Dram Type= 6, Freq= 0, CH_0, rank 1
4360 09:31:28.548836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 09:31:28.548925 ==
4362 09:31:28.548991 DQS Delay:
4363 09:31:28.549050 DQS0 = 0, DQS1 = 0
4364 09:31:28.552590 DQM Delay:
4365 09:31:28.552671 DQM0 = 41, DQM1 = 36
4366 09:31:28.555718 DQ Delay:
4367 09:31:28.559002 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4368 09:31:28.561919 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4369 09:31:28.565440 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4370 09:31:28.568627 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4371 09:31:28.568714
4372 09:31:28.568779
4373 09:31:28.575567 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c10, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4374 09:31:28.578319 CH0 RK1: MR19=808, MR18=5C10
4375 09:31:28.584989 CH0_RK1: MR19=0x808, MR18=0x5C10, DQSOSC=392, MR23=63, INC=170, DEC=113
4376 09:31:28.588589 [RxdqsGatingPostProcess] freq 600
4377 09:31:28.592028 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4378 09:31:28.594769 Pre-setting of DQS Precalculation
4379 09:31:28.601622 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4380 09:31:28.601717 ==
4381 09:31:28.604946 Dram Type= 6, Freq= 0, CH_1, rank 0
4382 09:31:28.608276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 09:31:28.608362 ==
4384 09:31:28.614767 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4385 09:31:28.621202 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4386 09:31:28.624591 [CA 0] Center 35 (5~66) winsize 62
4387 09:31:28.628046 [CA 1] Center 35 (5~66) winsize 62
4388 09:31:28.631239 [CA 2] Center 34 (4~65) winsize 62
4389 09:31:28.634770 [CA 3] Center 33 (3~64) winsize 62
4390 09:31:28.637654 [CA 4] Center 34 (4~65) winsize 62
4391 09:31:28.640980 [CA 5] Center 33 (3~64) winsize 62
4392 09:31:28.641067
4393 09:31:28.644221 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4394 09:31:28.644303
4395 09:31:28.647758 [CATrainingPosCal] consider 1 rank data
4396 09:31:28.651327 u2DelayCellTimex100 = 270/100 ps
4397 09:31:28.654315 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4398 09:31:28.657558 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4399 09:31:28.661125 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4400 09:31:28.663999 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4401 09:31:28.667371 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 09:31:28.673932 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4403 09:31:28.674017
4404 09:31:28.677048 CA PerBit enable=1, Macro0, CA PI delay=33
4405 09:31:28.677130
4406 09:31:28.680412 [CBTSetCACLKResult] CA Dly = 33
4407 09:31:28.680495 CS Dly: 5 (0~36)
4408 09:31:28.680560 ==
4409 09:31:28.683876 Dram Type= 6, Freq= 0, CH_1, rank 1
4410 09:31:28.690277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 09:31:28.690363 ==
4412 09:31:28.693654 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4413 09:31:28.700108 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4414 09:31:28.703308 [CA 0] Center 35 (5~66) winsize 62
4415 09:31:28.707065 [CA 1] Center 36 (6~66) winsize 61
4416 09:31:28.709870 [CA 2] Center 34 (4~65) winsize 62
4417 09:31:28.713529 [CA 3] Center 34 (3~65) winsize 63
4418 09:31:28.716574 [CA 4] Center 34 (4~65) winsize 62
4419 09:31:28.719792 [CA 5] Center 34 (4~65) winsize 62
4420 09:31:28.719874
4421 09:31:28.723147 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4422 09:31:28.723228
4423 09:31:28.726387 [CATrainingPosCal] consider 2 rank data
4424 09:31:28.730018 u2DelayCellTimex100 = 270/100 ps
4425 09:31:28.732930 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4426 09:31:28.739722 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4427 09:31:28.743122 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4428 09:31:28.746458 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4429 09:31:28.749488 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 09:31:28.752896 CA5 delay=34 (4~64),Diff = 1 PI (9 cell)
4431 09:31:28.752979
4432 09:31:28.756485 CA PerBit enable=1, Macro0, CA PI delay=33
4433 09:31:28.756565
4434 09:31:28.759610 [CBTSetCACLKResult] CA Dly = 33
4435 09:31:28.762806 CS Dly: 5 (0~36)
4436 09:31:28.762889
4437 09:31:28.765753 ----->DramcWriteLeveling(PI) begin...
4438 09:31:28.765835 ==
4439 09:31:28.769126 Dram Type= 6, Freq= 0, CH_1, rank 0
4440 09:31:28.772701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4441 09:31:28.772798 ==
4442 09:31:28.775679 Write leveling (Byte 0): 30 => 30
4443 09:31:28.779110 Write leveling (Byte 1): 28 => 28
4444 09:31:28.782754 DramcWriteLeveling(PI) end<-----
4445 09:31:28.782836
4446 09:31:28.782901 ==
4447 09:31:28.786103 Dram Type= 6, Freq= 0, CH_1, rank 0
4448 09:31:28.789424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 09:31:28.789506 ==
4450 09:31:28.792109 [Gating] SW mode calibration
4451 09:31:28.798995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4452 09:31:28.805303 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4453 09:31:28.808877 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4454 09:31:28.812306 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4455 09:31:28.818585 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4456 09:31:28.821862 0 9 12 | B1->B0 | 3232 2f2f | 0 1 | (0 1) (1 0)
4457 09:31:28.825509 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 09:31:28.832062 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 09:31:28.835239 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 09:31:28.838685 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 09:31:28.845797 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 09:31:28.848546 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 09:31:28.851657 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 09:31:28.858474 0 10 12 | B1->B0 | 3333 3a3a | 0 0 | (0 0) (0 0)
4465 09:31:28.861693 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4466 09:31:28.865302 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 09:31:28.871439 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 09:31:28.875012 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 09:31:28.878350 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 09:31:28.884493 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 09:31:28.888528 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 09:31:28.891793 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4473 09:31:28.898126 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 09:31:28.901587 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 09:31:28.904363 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 09:31:28.911104 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 09:31:28.914676 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 09:31:28.917668 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 09:31:28.924271 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 09:31:28.927789 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 09:31:28.931210 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 09:31:28.937555 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 09:31:28.940991 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 09:31:28.944417 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 09:31:28.951004 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 09:31:28.954126 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 09:31:28.957714 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4488 09:31:28.964510 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4489 09:31:28.967709 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 09:31:28.971065 Total UI for P1: 0, mck2ui 16
4491 09:31:28.974075 best dqsien dly found for B0: ( 0, 13, 10)
4492 09:31:28.977076 Total UI for P1: 0, mck2ui 16
4493 09:31:28.980310 best dqsien dly found for B1: ( 0, 13, 12)
4494 09:31:28.983814 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4495 09:31:28.987103 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4496 09:31:28.987185
4497 09:31:28.990696 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4498 09:31:28.993584 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4499 09:31:28.996849 [Gating] SW calibration Done
4500 09:31:28.996930 ==
4501 09:31:29.000436 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 09:31:29.006666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 09:31:29.006751 ==
4504 09:31:29.006815 RX Vref Scan: 0
4505 09:31:29.006875
4506 09:31:29.010337 RX Vref 0 -> 0, step: 1
4507 09:31:29.010417
4508 09:31:29.013691 RX Delay -230 -> 252, step: 16
4509 09:31:29.016700 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4510 09:31:29.019920 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4511 09:31:29.023537 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4512 09:31:29.030124 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4513 09:31:29.033601 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4514 09:31:29.036856 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4515 09:31:29.039991 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4516 09:31:29.046354 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4517 09:31:29.050321 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4518 09:31:29.053091 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4519 09:31:29.056744 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4520 09:31:29.059975 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4521 09:31:29.066293 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4522 09:31:29.069851 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4523 09:31:29.073068 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4524 09:31:29.076229 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4525 09:31:29.079569 ==
4526 09:31:29.082998 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 09:31:29.086372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 09:31:29.086456 ==
4529 09:31:29.086520 DQS Delay:
4530 09:31:29.089856 DQS0 = 0, DQS1 = 0
4531 09:31:29.089937 DQM Delay:
4532 09:31:29.093174 DQM0 = 47, DQM1 = 37
4533 09:31:29.093255 DQ Delay:
4534 09:31:29.096088 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4535 09:31:29.099429 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4536 09:31:29.102879 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4537 09:31:29.105849 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4538 09:31:29.105930
4539 09:31:29.105993
4540 09:31:29.106053 ==
4541 09:31:29.109411 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 09:31:29.112787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 09:31:29.112869 ==
4544 09:31:29.112933
4545 09:31:29.112991
4546 09:31:29.116292 TX Vref Scan disable
4547 09:31:29.119107 == TX Byte 0 ==
4548 09:31:29.122382 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4549 09:31:29.125714 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4550 09:31:29.129344 == TX Byte 1 ==
4551 09:31:29.132279 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4552 09:31:29.135659 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4553 09:31:29.135741 ==
4554 09:31:29.139055 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 09:31:29.145592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 09:31:29.145677 ==
4557 09:31:29.145742
4558 09:31:29.145800
4559 09:31:29.149003 TX Vref Scan disable
4560 09:31:29.149084 == TX Byte 0 ==
4561 09:31:29.155495 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4562 09:31:29.158314 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4563 09:31:29.158396 == TX Byte 1 ==
4564 09:31:29.165170 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4565 09:31:29.168928 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4566 09:31:29.169014
4567 09:31:29.169077 [DATLAT]
4568 09:31:29.171656 Freq=600, CH1 RK0
4569 09:31:29.171737
4570 09:31:29.171800 DATLAT Default: 0x9
4571 09:31:29.175326 0, 0xFFFF, sum = 0
4572 09:31:29.175409 1, 0xFFFF, sum = 0
4573 09:31:29.178458 2, 0xFFFF, sum = 0
4574 09:31:29.181306 3, 0xFFFF, sum = 0
4575 09:31:29.181388 4, 0xFFFF, sum = 0
4576 09:31:29.184775 5, 0xFFFF, sum = 0
4577 09:31:29.184858 6, 0xFFFF, sum = 0
4578 09:31:29.188247 7, 0xFFFF, sum = 0
4579 09:31:29.188328 8, 0x0, sum = 1
4580 09:31:29.191580 9, 0x0, sum = 2
4581 09:31:29.191662 10, 0x0, sum = 3
4582 09:31:29.191727 11, 0x0, sum = 4
4583 09:31:29.194586 best_step = 9
4584 09:31:29.194666
4585 09:31:29.194728 ==
4586 09:31:29.197946 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 09:31:29.201321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 09:31:29.201402 ==
4589 09:31:29.204595 RX Vref Scan: 1
4590 09:31:29.204680
4591 09:31:29.204765 RX Vref 0 -> 0, step: 1
4592 09:31:29.208214
4593 09:31:29.208297 RX Delay -195 -> 252, step: 8
4594 09:31:29.208380
4595 09:31:29.211169 Set Vref, RX VrefLevel [Byte0]: 51
4596 09:31:29.214584 [Byte1]: 59
4597 09:31:29.219462
4598 09:31:29.219544 Final RX Vref Byte 0 = 51 to rank0
4599 09:31:29.222021 Final RX Vref Byte 1 = 59 to rank0
4600 09:31:29.225429 Final RX Vref Byte 0 = 51 to rank1
4601 09:31:29.229016 Final RX Vref Byte 1 = 59 to rank1==
4602 09:31:29.232214 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 09:31:29.238666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 09:31:29.238756 ==
4605 09:31:29.238823 DQS Delay:
4606 09:31:29.242018 DQS0 = 0, DQS1 = 0
4607 09:31:29.242100 DQM Delay:
4608 09:31:29.242189 DQM0 = 47, DQM1 = 38
4609 09:31:29.245543 DQ Delay:
4610 09:31:29.249009 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4611 09:31:29.252266 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4612 09:31:29.255741 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4613 09:31:29.258975 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4614 09:31:29.259057
4615 09:31:29.259121
4616 09:31:29.265298 [DQSOSCAuto] RK0, (LSB)MR18= 0x5035, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4617 09:31:29.268237 CH1 RK0: MR19=808, MR18=5035
4618 09:31:29.274840 CH1_RK0: MR19=0x808, MR18=0x5035, DQSOSC=394, MR23=63, INC=168, DEC=112
4619 09:31:29.274929
4620 09:31:29.278197 ----->DramcWriteLeveling(PI) begin...
4621 09:31:29.278299 ==
4622 09:31:29.281681 Dram Type= 6, Freq= 0, CH_1, rank 1
4623 09:31:29.285056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 09:31:29.285141 ==
4625 09:31:29.288545 Write leveling (Byte 0): 29 => 29
4626 09:31:29.291531 Write leveling (Byte 1): 29 => 29
4627 09:31:29.295019 DramcWriteLeveling(PI) end<-----
4628 09:31:29.295102
4629 09:31:29.295166 ==
4630 09:31:29.298200 Dram Type= 6, Freq= 0, CH_1, rank 1
4631 09:31:29.301641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 09:31:29.305054 ==
4633 09:31:29.305139 [Gating] SW mode calibration
4634 09:31:29.314644 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4635 09:31:29.317761 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4636 09:31:29.321571 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4637 09:31:29.328058 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4638 09:31:29.330825 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4639 09:31:29.334590 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 0) (1 1)
4640 09:31:29.341278 0 9 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4641 09:31:29.344078 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 09:31:29.347626 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 09:31:29.353944 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 09:31:29.357528 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 09:31:29.361233 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 09:31:29.367430 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 09:31:29.370366 0 10 12 | B1->B0 | 3636 2929 | 0 0 | (0 0) (0 0)
4648 09:31:29.373742 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4649 09:31:29.380794 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 09:31:29.383768 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 09:31:29.390092 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 09:31:29.393465 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 09:31:29.396520 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 09:31:29.400296 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 09:31:29.406557 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4656 09:31:29.409796 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4657 09:31:29.413113 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 09:31:29.419637 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 09:31:29.422980 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 09:31:29.429753 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 09:31:29.433107 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 09:31:29.435978 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 09:31:29.442756 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 09:31:29.446219 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 09:31:29.449463 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 09:31:29.455793 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 09:31:29.459230 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 09:31:29.462390 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 09:31:29.468916 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 09:31:29.472160 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 09:31:29.475795 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4672 09:31:29.478779 Total UI for P1: 0, mck2ui 16
4673 09:31:29.482153 best dqsien dly found for B1: ( 0, 13, 10)
4674 09:31:29.489012 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 09:31:29.489098 Total UI for P1: 0, mck2ui 16
4676 09:31:29.491931 best dqsien dly found for B0: ( 0, 13, 12)
4677 09:31:29.498841 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4678 09:31:29.502130 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4679 09:31:29.502267
4680 09:31:29.505592 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4681 09:31:29.508539 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4682 09:31:29.512023 [Gating] SW calibration Done
4683 09:31:29.512105 ==
4684 09:31:29.515078 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 09:31:29.518283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 09:31:29.518366 ==
4687 09:31:29.521620 RX Vref Scan: 0
4688 09:31:29.521695
4689 09:31:29.521758 RX Vref 0 -> 0, step: 1
4690 09:31:29.521817
4691 09:31:29.524867 RX Delay -230 -> 252, step: 16
4692 09:31:29.531958 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4693 09:31:29.535036 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4694 09:31:29.538644 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4695 09:31:29.541367 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4696 09:31:29.545009 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4697 09:31:29.551164 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4698 09:31:29.554347 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4699 09:31:29.558122 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4700 09:31:29.561083 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4701 09:31:29.568013 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4702 09:31:29.571085 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4703 09:31:29.574658 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4704 09:31:29.577794 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4705 09:31:29.584251 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4706 09:31:29.587652 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4707 09:31:29.591213 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4708 09:31:29.591296 ==
4709 09:31:29.593910 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 09:31:29.601025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 09:31:29.601111 ==
4712 09:31:29.601177 DQS Delay:
4713 09:31:29.601238 DQS0 = 0, DQS1 = 0
4714 09:31:29.603850 DQM Delay:
4715 09:31:29.603932 DQM0 = 44, DQM1 = 39
4716 09:31:29.607414 DQ Delay:
4717 09:31:29.610453 DQ0 =57, DQ1 =41, DQ2 =25, DQ3 =41
4718 09:31:29.613757 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =33
4719 09:31:29.613839 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4720 09:31:29.620499 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =49
4721 09:31:29.620586
4722 09:31:29.620652
4723 09:31:29.620712 ==
4724 09:31:29.624043 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 09:31:29.626921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 09:31:29.627004 ==
4727 09:31:29.627070
4728 09:31:29.627130
4729 09:31:29.630262 TX Vref Scan disable
4730 09:31:29.630369 == TX Byte 0 ==
4731 09:31:29.636755 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4732 09:31:29.640510 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4733 09:31:29.640596 == TX Byte 1 ==
4734 09:31:29.646872 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4735 09:31:29.650182 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4736 09:31:29.650266 ==
4737 09:31:29.653556 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 09:31:29.657216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 09:31:29.657300 ==
4740 09:31:29.660149
4741 09:31:29.660230
4742 09:31:29.660295 TX Vref Scan disable
4743 09:31:29.663866 == TX Byte 0 ==
4744 09:31:29.666695 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4745 09:31:29.673487 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4746 09:31:29.673575 == TX Byte 1 ==
4747 09:31:29.677065 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4748 09:31:29.683326 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4749 09:31:29.683414
4750 09:31:29.683481 [DATLAT]
4751 09:31:29.683541 Freq=600, CH1 RK1
4752 09:31:29.683611
4753 09:31:29.686446 DATLAT Default: 0x9
4754 09:31:29.689640 0, 0xFFFF, sum = 0
4755 09:31:29.689752 1, 0xFFFF, sum = 0
4756 09:31:29.693292 2, 0xFFFF, sum = 0
4757 09:31:29.693375 3, 0xFFFF, sum = 0
4758 09:31:29.696583 4, 0xFFFF, sum = 0
4759 09:31:29.696666 5, 0xFFFF, sum = 0
4760 09:31:29.699588 6, 0xFFFF, sum = 0
4761 09:31:29.699672 7, 0xFFFF, sum = 0
4762 09:31:29.702996 8, 0x0, sum = 1
4763 09:31:29.703079 9, 0x0, sum = 2
4764 09:31:29.706319 10, 0x0, sum = 3
4765 09:31:29.706402 11, 0x0, sum = 4
4766 09:31:29.706468 best_step = 9
4767 09:31:29.706528
4768 09:31:29.709784 ==
4769 09:31:29.712736 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 09:31:29.716001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 09:31:29.716085 ==
4772 09:31:29.716150 RX Vref Scan: 0
4773 09:31:29.716211
4774 09:31:29.719481 RX Vref 0 -> 0, step: 1
4775 09:31:29.719563
4776 09:31:29.722857 RX Delay -195 -> 252, step: 8
4777 09:31:29.729374 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4778 09:31:29.732338 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4779 09:31:29.735871 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4780 09:31:29.739319 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4781 09:31:29.745725 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4782 09:31:29.749296 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4783 09:31:29.752649 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4784 09:31:29.756076 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4785 09:31:29.759003 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4786 09:31:29.766003 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4787 09:31:29.768915 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4788 09:31:29.772316 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4789 09:31:29.775390 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4790 09:31:29.782310 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4791 09:31:29.785331 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4792 09:31:29.788580 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4793 09:31:29.788662 ==
4794 09:31:29.792092 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 09:31:29.795200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 09:31:29.798340 ==
4797 09:31:29.798422 DQS Delay:
4798 09:31:29.798487 DQS0 = 0, DQS1 = 0
4799 09:31:29.801752 DQM Delay:
4800 09:31:29.801833 DQM0 = 45, DQM1 = 36
4801 09:31:29.805367 DQ Delay:
4802 09:31:29.808670 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4803 09:31:29.808751 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4804 09:31:29.811675 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4805 09:31:29.818571 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4806 09:31:29.818654
4807 09:31:29.818718
4808 09:31:29.824881 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4809 09:31:29.828392 CH1 RK1: MR19=808, MR18=2C20
4810 09:31:29.834638 CH1_RK1: MR19=0x808, MR18=0x2C20, DQSOSC=401, MR23=63, INC=163, DEC=108
4811 09:31:29.838207 [RxdqsGatingPostProcess] freq 600
4812 09:31:29.841730 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4813 09:31:29.844513 Pre-setting of DQS Precalculation
4814 09:31:29.851200 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4815 09:31:29.857732 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4816 09:31:29.864447 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4817 09:31:29.864550
4818 09:31:29.864615
4819 09:31:29.867680 [Calibration Summary] 1200 Mbps
4820 09:31:29.867763 CH 0, Rank 0
4821 09:31:29.871409 SW Impedance : PASS
4822 09:31:29.874079 DUTY Scan : NO K
4823 09:31:29.874169 ZQ Calibration : PASS
4824 09:31:29.877505 Jitter Meter : NO K
4825 09:31:29.881045 CBT Training : PASS
4826 09:31:29.881126 Write leveling : PASS
4827 09:31:29.884336 RX DQS gating : PASS
4828 09:31:29.887570 RX DQ/DQS(RDDQC) : PASS
4829 09:31:29.887653 TX DQ/DQS : PASS
4830 09:31:29.890664 RX DATLAT : PASS
4831 09:31:29.893978 RX DQ/DQS(Engine): PASS
4832 09:31:29.894061 TX OE : NO K
4833 09:31:29.897336 All Pass.
4834 09:31:29.897417
4835 09:31:29.897482 CH 0, Rank 1
4836 09:31:29.900753 SW Impedance : PASS
4837 09:31:29.900834 DUTY Scan : NO K
4838 09:31:29.904112 ZQ Calibration : PASS
4839 09:31:29.907195 Jitter Meter : NO K
4840 09:31:29.907277 CBT Training : PASS
4841 09:31:29.910501 Write leveling : PASS
4842 09:31:29.913464 RX DQS gating : PASS
4843 09:31:29.913547 RX DQ/DQS(RDDQC) : PASS
4844 09:31:29.916942 TX DQ/DQS : PASS
4845 09:31:29.920407 RX DATLAT : PASS
4846 09:31:29.920488 RX DQ/DQS(Engine): PASS
4847 09:31:29.923285 TX OE : NO K
4848 09:31:29.923366 All Pass.
4849 09:31:29.923431
4850 09:31:29.926814 CH 1, Rank 0
4851 09:31:29.926895 SW Impedance : PASS
4852 09:31:29.930142 DUTY Scan : NO K
4853 09:31:29.933722 ZQ Calibration : PASS
4854 09:31:29.933805 Jitter Meter : NO K
4855 09:31:29.936618 CBT Training : PASS
4856 09:31:29.940343 Write leveling : PASS
4857 09:31:29.940425 RX DQS gating : PASS
4858 09:31:29.943241 RX DQ/DQS(RDDQC) : PASS
4859 09:31:29.943323 TX DQ/DQS : PASS
4860 09:31:29.946700 RX DATLAT : PASS
4861 09:31:29.950273 RX DQ/DQS(Engine): PASS
4862 09:31:29.950356 TX OE : NO K
4863 09:31:29.953535 All Pass.
4864 09:31:29.953617
4865 09:31:29.953681 CH 1, Rank 1
4866 09:31:29.956676 SW Impedance : PASS
4867 09:31:29.956757 DUTY Scan : NO K
4868 09:31:29.959744 ZQ Calibration : PASS
4869 09:31:29.962865 Jitter Meter : NO K
4870 09:31:29.962984 CBT Training : PASS
4871 09:31:29.966538 Write leveling : PASS
4872 09:31:29.969583 RX DQS gating : PASS
4873 09:31:29.969665 RX DQ/DQS(RDDQC) : PASS
4874 09:31:29.973009 TX DQ/DQS : PASS
4875 09:31:29.976082 RX DATLAT : PASS
4876 09:31:29.976164 RX DQ/DQS(Engine): PASS
4877 09:31:29.979546 TX OE : NO K
4878 09:31:29.979638 All Pass.
4879 09:31:29.979708
4880 09:31:29.982794 DramC Write-DBI off
4881 09:31:29.986259 PER_BANK_REFRESH: Hybrid Mode
4882 09:31:29.986346 TX_TRACKING: ON
4883 09:31:29.995963 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4884 09:31:29.999064 [FAST_K] Save calibration result to emmc
4885 09:31:30.002412 dramc_set_vcore_voltage set vcore to 662500
4886 09:31:30.005950 Read voltage for 933, 3
4887 09:31:30.006034 Vio18 = 0
4888 09:31:30.006099 Vcore = 662500
4889 09:31:30.009304 Vdram = 0
4890 09:31:30.009387 Vddq = 0
4891 09:31:30.009453 Vmddr = 0
4892 09:31:30.015724 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4893 09:31:30.019047 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4894 09:31:30.022570 MEM_TYPE=3, freq_sel=17
4895 09:31:30.025934 sv_algorithm_assistance_LP4_1600
4896 09:31:30.029322 ============ PULL DRAM RESETB DOWN ============
4897 09:31:30.032825 ========== PULL DRAM RESETB DOWN end =========
4898 09:31:30.039182 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4899 09:31:30.041990 ===================================
4900 09:31:30.045457 LPDDR4 DRAM CONFIGURATION
4901 09:31:30.048947 ===================================
4902 09:31:30.049035 EX_ROW_EN[0] = 0x0
4903 09:31:30.051914 EX_ROW_EN[1] = 0x0
4904 09:31:30.051997 LP4Y_EN = 0x0
4905 09:31:30.055321 WORK_FSP = 0x0
4906 09:31:30.055401 WL = 0x3
4907 09:31:30.058536 RL = 0x3
4908 09:31:30.058618 BL = 0x2
4909 09:31:30.062167 RPST = 0x0
4910 09:31:30.062280 RD_PRE = 0x0
4911 09:31:30.065516 WR_PRE = 0x1
4912 09:31:30.068344 WR_PST = 0x0
4913 09:31:30.068428 DBI_WR = 0x0
4914 09:31:30.071653 DBI_RD = 0x0
4915 09:31:30.071739 OTF = 0x1
4916 09:31:30.075211 ===================================
4917 09:31:30.078371 ===================================
4918 09:31:30.078454 ANA top config
4919 09:31:30.081949 ===================================
4920 09:31:30.084883 DLL_ASYNC_EN = 0
4921 09:31:30.088246 ALL_SLAVE_EN = 1
4922 09:31:30.091417 NEW_RANK_MODE = 1
4923 09:31:30.094899 DLL_IDLE_MODE = 1
4924 09:31:30.094983 LP45_APHY_COMB_EN = 1
4925 09:31:30.098361 TX_ODT_DIS = 1
4926 09:31:30.101808 NEW_8X_MODE = 1
4927 09:31:30.104622 ===================================
4928 09:31:30.107919 ===================================
4929 09:31:30.111786 data_rate = 1866
4930 09:31:30.114607 CKR = 1
4931 09:31:30.117893 DQ_P2S_RATIO = 8
4932 09:31:30.121126 ===================================
4933 09:31:30.121210 CA_P2S_RATIO = 8
4934 09:31:30.124802 DQ_CA_OPEN = 0
4935 09:31:30.127601 DQ_SEMI_OPEN = 0
4936 09:31:30.130976 CA_SEMI_OPEN = 0
4937 09:31:30.134623 CA_FULL_RATE = 0
4938 09:31:30.137548 DQ_CKDIV4_EN = 1
4939 09:31:30.137630 CA_CKDIV4_EN = 1
4940 09:31:30.141384 CA_PREDIV_EN = 0
4941 09:31:30.144050 PH8_DLY = 0
4942 09:31:30.147501 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4943 09:31:30.150808 DQ_AAMCK_DIV = 4
4944 09:31:30.154144 CA_AAMCK_DIV = 4
4945 09:31:30.154266 CA_ADMCK_DIV = 4
4946 09:31:30.157628 DQ_TRACK_CA_EN = 0
4947 09:31:30.160486 CA_PICK = 933
4948 09:31:30.163835 CA_MCKIO = 933
4949 09:31:30.166963 MCKIO_SEMI = 0
4950 09:31:30.170956 PLL_FREQ = 3732
4951 09:31:30.173710 DQ_UI_PI_RATIO = 32
4952 09:31:30.177163 CA_UI_PI_RATIO = 0
4953 09:31:30.180702 ===================================
4954 09:31:30.184093 ===================================
4955 09:31:30.184176 memory_type:LPDDR4
4956 09:31:30.187096 GP_NUM : 10
4957 09:31:30.190392 SRAM_EN : 1
4958 09:31:30.190476 MD32_EN : 0
4959 09:31:30.193897 ===================================
4960 09:31:30.197216 [ANA_INIT] >>>>>>>>>>>>>>
4961 09:31:30.200480 <<<<<< [CONFIGURE PHASE]: ANA_TX
4962 09:31:30.203523 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4963 09:31:30.206975 ===================================
4964 09:31:30.210430 data_rate = 1866,PCW = 0X8f00
4965 09:31:30.213307 ===================================
4966 09:31:30.216847 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4967 09:31:30.220189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4968 09:31:30.226517 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4969 09:31:30.230023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4970 09:31:30.233238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4971 09:31:30.236406 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4972 09:31:30.239842 [ANA_INIT] flow start
4973 09:31:30.243113 [ANA_INIT] PLL >>>>>>>>
4974 09:31:30.243198 [ANA_INIT] PLL <<<<<<<<
4975 09:31:30.246731 [ANA_INIT] MIDPI >>>>>>>>
4976 09:31:30.249897 [ANA_INIT] MIDPI <<<<<<<<
4977 09:31:30.252773 [ANA_INIT] DLL >>>>>>>>
4978 09:31:30.252855 [ANA_INIT] flow end
4979 09:31:30.256281 ============ LP4 DIFF to SE enter ============
4980 09:31:30.263260 ============ LP4 DIFF to SE exit ============
4981 09:31:30.263347 [ANA_INIT] <<<<<<<<<<<<<
4982 09:31:30.266744 [Flow] Enable top DCM control >>>>>
4983 09:31:30.269551 [Flow] Enable top DCM control <<<<<
4984 09:31:30.273021 Enable DLL master slave shuffle
4985 09:31:30.279835 ==============================================================
4986 09:31:30.279921 Gating Mode config
4987 09:31:30.286086 ==============================================================
4988 09:31:30.289552 Config description:
4989 09:31:30.299474 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4990 09:31:30.305952 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4991 09:31:30.309046 SELPH_MODE 0: By rank 1: By Phase
4992 09:31:30.315883 ==============================================================
4993 09:31:30.318886 GAT_TRACK_EN = 1
4994 09:31:30.322144 RX_GATING_MODE = 2
4995 09:31:30.322280 RX_GATING_TRACK_MODE = 2
4996 09:31:30.326103 SELPH_MODE = 1
4997 09:31:30.328868 PICG_EARLY_EN = 1
4998 09:31:30.332312 VALID_LAT_VALUE = 1
4999 09:31:30.338735 ==============================================================
5000 09:31:30.341960 Enter into Gating configuration >>>>
5001 09:31:30.345280 Exit from Gating configuration <<<<
5002 09:31:30.348534 Enter into DVFS_PRE_config >>>>>
5003 09:31:30.358780 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5004 09:31:30.362357 Exit from DVFS_PRE_config <<<<<
5005 09:31:30.365375 Enter into PICG configuration >>>>
5006 09:31:30.368911 Exit from PICG configuration <<<<
5007 09:31:30.372019 [RX_INPUT] configuration >>>>>
5008 09:31:30.375054 [RX_INPUT] configuration <<<<<
5009 09:31:30.378788 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5010 09:31:30.385475 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5011 09:31:30.392167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5012 09:31:30.398734 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5013 09:31:30.405244 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5014 09:31:30.408712 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5015 09:31:30.414749 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5016 09:31:30.418355 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5017 09:31:30.421698 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5018 09:31:30.424991 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5019 09:31:30.431286 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5020 09:31:30.434920 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5021 09:31:30.438282 ===================================
5022 09:31:30.441403 LPDDR4 DRAM CONFIGURATION
5023 09:31:30.444881 ===================================
5024 09:31:30.444964 EX_ROW_EN[0] = 0x0
5025 09:31:30.447723 EX_ROW_EN[1] = 0x0
5026 09:31:30.447830 LP4Y_EN = 0x0
5027 09:31:30.451453 WORK_FSP = 0x0
5028 09:31:30.451533 WL = 0x3
5029 09:31:30.454397 RL = 0x3
5030 09:31:30.454477 BL = 0x2
5031 09:31:30.457981 RPST = 0x0
5032 09:31:30.461100 RD_PRE = 0x0
5033 09:31:30.461207 WR_PRE = 0x1
5034 09:31:30.464256 WR_PST = 0x0
5035 09:31:30.464353 DBI_WR = 0x0
5036 09:31:30.467907 DBI_RD = 0x0
5037 09:31:30.467989 OTF = 0x1
5038 09:31:30.470962 ===================================
5039 09:31:30.474147 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5040 09:31:30.481121 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5041 09:31:30.484218 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5042 09:31:30.487655 ===================================
5043 09:31:30.491108 LPDDR4 DRAM CONFIGURATION
5044 09:31:30.493917 ===================================
5045 09:31:30.494033 EX_ROW_EN[0] = 0x10
5046 09:31:30.497432 EX_ROW_EN[1] = 0x0
5047 09:31:30.497513 LP4Y_EN = 0x0
5048 09:31:30.500725 WORK_FSP = 0x0
5049 09:31:30.500806 WL = 0x3
5050 09:31:30.504156 RL = 0x3
5051 09:31:30.504237 BL = 0x2
5052 09:31:30.507078 RPST = 0x0
5053 09:31:30.510466 RD_PRE = 0x0
5054 09:31:30.510573 WR_PRE = 0x1
5055 09:31:30.513915 WR_PST = 0x0
5056 09:31:30.513996 DBI_WR = 0x0
5057 09:31:30.517196 DBI_RD = 0x0
5058 09:31:30.517277 OTF = 0x1
5059 09:31:30.520515 ===================================
5060 09:31:30.527275 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5061 09:31:30.530833 nWR fixed to 30
5062 09:31:30.534130 [ModeRegInit_LP4] CH0 RK0
5063 09:31:30.534250 [ModeRegInit_LP4] CH0 RK1
5064 09:31:30.537621 [ModeRegInit_LP4] CH1 RK0
5065 09:31:30.540966 [ModeRegInit_LP4] CH1 RK1
5066 09:31:30.541047 match AC timing 9
5067 09:31:30.547069 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5068 09:31:30.550477 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5069 09:31:30.553574 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5070 09:31:30.560820 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5071 09:31:30.564143 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5072 09:31:30.564225 ==
5073 09:31:30.566990 Dram Type= 6, Freq= 0, CH_0, rank 0
5074 09:31:30.570312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5075 09:31:30.573882 ==
5076 09:31:30.576830 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5077 09:31:30.583290 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5078 09:31:30.586678 [CA 0] Center 37 (7~68) winsize 62
5079 09:31:30.589873 [CA 1] Center 37 (7~68) winsize 62
5080 09:31:30.593343 [CA 2] Center 34 (4~65) winsize 62
5081 09:31:30.597085 [CA 3] Center 35 (5~65) winsize 61
5082 09:31:30.600307 [CA 4] Center 33 (3~64) winsize 62
5083 09:31:30.603179 [CA 5] Center 33 (3~63) winsize 61
5084 09:31:30.603258
5085 09:31:30.606379 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5086 09:31:30.606459
5087 09:31:30.609994 [CATrainingPosCal] consider 1 rank data
5088 09:31:30.613274 u2DelayCellTimex100 = 270/100 ps
5089 09:31:30.616811 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5090 09:31:30.619568 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5091 09:31:30.622811 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5092 09:31:30.629564 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5093 09:31:30.632918 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5094 09:31:30.636475 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5095 09:31:30.636556
5096 09:31:30.639419 CA PerBit enable=1, Macro0, CA PI delay=33
5097 09:31:30.639499
5098 09:31:30.642915 [CBTSetCACLKResult] CA Dly = 33
5099 09:31:30.642996 CS Dly: 7 (0~38)
5100 09:31:30.643060 ==
5101 09:31:30.645889 Dram Type= 6, Freq= 0, CH_0, rank 1
5102 09:31:30.652891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 09:31:30.652974 ==
5104 09:31:30.656255 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5105 09:31:30.662672 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5106 09:31:30.665880 [CA 0] Center 37 (7~68) winsize 62
5107 09:31:30.669239 [CA 1] Center 37 (7~68) winsize 62
5108 09:31:30.672652 [CA 2] Center 34 (4~65) winsize 62
5109 09:31:30.676077 [CA 3] Center 34 (4~65) winsize 62
5110 09:31:30.679073 [CA 4] Center 33 (3~64) winsize 62
5111 09:31:30.682528 [CA 5] Center 32 (2~63) winsize 62
5112 09:31:30.682609
5113 09:31:30.685473 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5114 09:31:30.685553
5115 09:31:30.689160 [CATrainingPosCal] consider 2 rank data
5116 09:31:30.692663 u2DelayCellTimex100 = 270/100 ps
5117 09:31:30.695885 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5118 09:31:30.702357 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5119 09:31:30.705153 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5120 09:31:30.708578 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5121 09:31:30.711865 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5122 09:31:30.715376 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5123 09:31:30.715456
5124 09:31:30.718410 CA PerBit enable=1, Macro0, CA PI delay=33
5125 09:31:30.718491
5126 09:31:30.721556 [CBTSetCACLKResult] CA Dly = 33
5127 09:31:30.725015 CS Dly: 7 (0~39)
5128 09:31:30.725095
5129 09:31:30.728427 ----->DramcWriteLeveling(PI) begin...
5130 09:31:30.728509 ==
5131 09:31:30.731899 Dram Type= 6, Freq= 0, CH_0, rank 0
5132 09:31:30.735291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5133 09:31:30.735372 ==
5134 09:31:30.738117 Write leveling (Byte 0): 33 => 33
5135 09:31:30.741691 Write leveling (Byte 1): 28 => 28
5136 09:31:30.744704 DramcWriteLeveling(PI) end<-----
5137 09:31:30.744825
5138 09:31:30.744930 ==
5139 09:31:30.748199 Dram Type= 6, Freq= 0, CH_0, rank 0
5140 09:31:30.751582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 09:31:30.751674 ==
5142 09:31:30.754641 [Gating] SW mode calibration
5143 09:31:30.761659 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5144 09:31:30.768031 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5145 09:31:30.770986 0 14 0 | B1->B0 | 2322 3333 | 1 1 | (0 0) (1 1)
5146 09:31:30.777790 0 14 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5147 09:31:30.780759 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 09:31:30.784149 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 09:31:30.791028 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 09:31:30.794458 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 09:31:30.797262 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 09:31:30.804227 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5153 09:31:30.806992 0 15 0 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 0)
5154 09:31:30.810775 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 09:31:30.817295 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 09:31:30.820419 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 09:31:30.823904 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 09:31:30.830157 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 09:31:30.833532 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 09:31:30.836579 0 15 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5161 09:31:30.843684 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5162 09:31:30.846667 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 09:31:30.850324 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 09:31:30.856346 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 09:31:30.859809 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 09:31:30.863044 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 09:31:30.869784 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 09:31:30.872985 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5169 09:31:30.876415 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5170 09:31:30.883103 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 09:31:30.886053 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 09:31:30.889574 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 09:31:30.895869 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 09:31:30.899095 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 09:31:30.902535 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 09:31:30.908873 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 09:31:30.912258 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 09:31:30.915563 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 09:31:30.922401 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 09:31:30.925659 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 09:31:30.929208 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 09:31:30.935369 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 09:31:30.938962 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 09:31:30.941929 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5185 09:31:30.945367 Total UI for P1: 0, mck2ui 16
5186 09:31:30.948814 best dqsien dly found for B0: ( 1, 2, 26)
5187 09:31:30.955082 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5188 09:31:30.958421 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 09:31:30.961832 Total UI for P1: 0, mck2ui 16
5190 09:31:30.965115 best dqsien dly found for B1: ( 1, 2, 30)
5191 09:31:30.968405 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5192 09:31:30.972002 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5193 09:31:30.972086
5194 09:31:30.974731 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5195 09:31:30.981418 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5196 09:31:30.981502 [Gating] SW calibration Done
5197 09:31:30.981566 ==
5198 09:31:30.985275 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 09:31:30.991459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 09:31:30.991545 ==
5201 09:31:30.991609 RX Vref Scan: 0
5202 09:31:30.991669
5203 09:31:30.995248 RX Vref 0 -> 0, step: 1
5204 09:31:30.995329
5205 09:31:30.998271 RX Delay -80 -> 252, step: 8
5206 09:31:31.001152 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5207 09:31:31.004673 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5208 09:31:31.008100 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5209 09:31:31.011211 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5210 09:31:31.017853 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5211 09:31:31.021499 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5212 09:31:31.024754 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5213 09:31:31.028173 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5214 09:31:31.031043 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5215 09:31:31.037417 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5216 09:31:31.040644 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5217 09:31:31.044372 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5218 09:31:31.047395 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5219 09:31:31.050899 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5220 09:31:31.057674 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5221 09:31:31.060449 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5222 09:31:31.060532 ==
5223 09:31:31.063856 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 09:31:31.067302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 09:31:31.067386 ==
5226 09:31:31.067450 DQS Delay:
5227 09:31:31.070292 DQS0 = 0, DQS1 = 0
5228 09:31:31.070372 DQM Delay:
5229 09:31:31.073828 DQM0 = 98, DQM1 = 86
5230 09:31:31.073908 DQ Delay:
5231 09:31:31.076900 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =91
5232 09:31:31.080537 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5233 09:31:31.083866 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5234 09:31:31.086857 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95
5235 09:31:31.086937
5236 09:31:31.087000
5237 09:31:31.087059 ==
5238 09:31:31.090392 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 09:31:31.096642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 09:31:31.096732 ==
5241 09:31:31.096796
5242 09:31:31.096854
5243 09:31:31.096911 TX Vref Scan disable
5244 09:31:31.100363 == TX Byte 0 ==
5245 09:31:31.103824 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5246 09:31:31.110332 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5247 09:31:31.110417 == TX Byte 1 ==
5248 09:31:31.113295 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5249 09:31:31.119993 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5250 09:31:31.120078 ==
5251 09:31:31.123215 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 09:31:31.126799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 09:31:31.126906 ==
5254 09:31:31.126998
5255 09:31:31.127086
5256 09:31:31.129854 TX Vref Scan disable
5257 09:31:31.133254 == TX Byte 0 ==
5258 09:31:31.136846 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5259 09:31:31.139941 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5260 09:31:31.143258 == TX Byte 1 ==
5261 09:31:31.146751 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5262 09:31:31.149963 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5263 09:31:31.150070
5264 09:31:31.150168 [DATLAT]
5265 09:31:31.153487 Freq=933, CH0 RK0
5266 09:31:31.153568
5267 09:31:31.156251 DATLAT Default: 0xd
5268 09:31:31.156332 0, 0xFFFF, sum = 0
5269 09:31:31.159673 1, 0xFFFF, sum = 0
5270 09:31:31.159755 2, 0xFFFF, sum = 0
5271 09:31:31.162834 3, 0xFFFF, sum = 0
5272 09:31:31.162916 4, 0xFFFF, sum = 0
5273 09:31:31.166055 5, 0xFFFF, sum = 0
5274 09:31:31.166189 6, 0xFFFF, sum = 0
5275 09:31:31.169518 7, 0xFFFF, sum = 0
5276 09:31:31.169600 8, 0xFFFF, sum = 0
5277 09:31:31.173328 9, 0xFFFF, sum = 0
5278 09:31:31.173410 10, 0x0, sum = 1
5279 09:31:31.176317 11, 0x0, sum = 2
5280 09:31:31.176398 12, 0x0, sum = 3
5281 09:31:31.179900 13, 0x0, sum = 4
5282 09:31:31.179981 best_step = 11
5283 09:31:31.180045
5284 09:31:31.180103 ==
5285 09:31:31.182529 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 09:31:31.186327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 09:31:31.189479 ==
5288 09:31:31.189559 RX Vref Scan: 1
5289 09:31:31.189622
5290 09:31:31.192628 RX Vref 0 -> 0, step: 1
5291 09:31:31.192708
5292 09:31:31.195916 RX Delay -61 -> 252, step: 4
5293 09:31:31.195996
5294 09:31:31.199573 Set Vref, RX VrefLevel [Byte0]: 61
5295 09:31:31.202609 [Byte1]: 59
5296 09:31:31.202692
5297 09:31:31.205573 Final RX Vref Byte 0 = 61 to rank0
5298 09:31:31.209498 Final RX Vref Byte 1 = 59 to rank0
5299 09:31:31.212745 Final RX Vref Byte 0 = 61 to rank1
5300 09:31:31.215543 Final RX Vref Byte 1 = 59 to rank1==
5301 09:31:31.219130 Dram Type= 6, Freq= 0, CH_0, rank 0
5302 09:31:31.222078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 09:31:31.222159 ==
5304 09:31:31.225319 DQS Delay:
5305 09:31:31.225398 DQS0 = 0, DQS1 = 0
5306 09:31:31.225461 DQM Delay:
5307 09:31:31.228546 DQM0 = 97, DQM1 = 87
5308 09:31:31.228640 DQ Delay:
5309 09:31:31.231939 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =94
5310 09:31:31.235261 DQ4 =98, DQ5 =88, DQ6 =108, DQ7 =106
5311 09:31:31.238584 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
5312 09:31:31.242075 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =90
5313 09:31:31.242155
5314 09:31:31.242258
5315 09:31:31.252320 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5316 09:31:31.255573 CH0 RK0: MR19=505, MR18=2E15
5317 09:31:31.258481 CH0_RK0: MR19=0x505, MR18=0x2E15, DQSOSC=407, MR23=63, INC=65, DEC=43
5318 09:31:31.258564
5319 09:31:31.262012 ----->DramcWriteLeveling(PI) begin...
5320 09:31:31.265384 ==
5321 09:31:31.268394 Dram Type= 6, Freq= 0, CH_0, rank 1
5322 09:31:31.271957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 09:31:31.272040 ==
5324 09:31:31.275455 Write leveling (Byte 0): 33 => 33
5325 09:31:31.278478 Write leveling (Byte 1): 30 => 30
5326 09:31:31.282033 DramcWriteLeveling(PI) end<-----
5327 09:31:31.282142
5328 09:31:31.282255 ==
5329 09:31:31.285313 Dram Type= 6, Freq= 0, CH_0, rank 1
5330 09:31:31.288213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 09:31:31.288293 ==
5332 09:31:31.291915 [Gating] SW mode calibration
5333 09:31:31.298395 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5334 09:31:31.304769 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5335 09:31:31.308027 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (0 0)
5336 09:31:31.311443 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 09:31:31.318389 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 09:31:31.320921 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 09:31:31.324342 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 09:31:31.330946 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 09:31:31.334549 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 09:31:31.337857 0 14 28 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 1)
5343 09:31:31.343999 0 15 0 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
5344 09:31:31.347525 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5345 09:31:31.350793 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 09:31:31.357636 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 09:31:31.360433 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 09:31:31.364087 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 09:31:31.370620 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 09:31:31.373937 0 15 28 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
5351 09:31:31.377339 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5352 09:31:31.383688 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 09:31:31.387126 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 09:31:31.390524 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 09:31:31.396838 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 09:31:31.400737 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 09:31:31.403688 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 09:31:31.410562 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5359 09:31:31.413776 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5360 09:31:31.416946 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 09:31:31.423278 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 09:31:31.426812 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 09:31:31.429889 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 09:31:31.437040 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 09:31:31.440034 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 09:31:31.443314 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 09:31:31.449606 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 09:31:31.453096 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 09:31:31.456367 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 09:31:31.463048 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 09:31:31.466598 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 09:31:31.469417 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 09:31:31.476470 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5374 09:31:31.479229 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 09:31:31.482812 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5376 09:31:31.485981 Total UI for P1: 0, mck2ui 16
5377 09:31:31.489657 best dqsien dly found for B0: ( 1, 2, 30)
5378 09:31:31.495808 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 09:31:31.495890 Total UI for P1: 0, mck2ui 16
5380 09:31:31.502903 best dqsien dly found for B1: ( 1, 3, 0)
5381 09:31:31.506040 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5382 09:31:31.509527 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5383 09:31:31.509607
5384 09:31:31.512716 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5385 09:31:31.515855 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5386 09:31:31.519054 [Gating] SW calibration Done
5387 09:31:31.519135 ==
5388 09:31:31.522291 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 09:31:31.525942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 09:31:31.526023 ==
5391 09:31:31.529188 RX Vref Scan: 0
5392 09:31:31.529268
5393 09:31:31.529332 RX Vref 0 -> 0, step: 1
5394 09:31:31.529392
5395 09:31:31.532347 RX Delay -80 -> 252, step: 8
5396 09:31:31.535546 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5397 09:31:31.542377 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5398 09:31:31.545498 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5399 09:31:31.549019 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5400 09:31:31.552274 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5401 09:31:31.555205 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5402 09:31:31.558565 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5403 09:31:31.565181 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5404 09:31:31.568618 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5405 09:31:31.571589 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5406 09:31:31.575151 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5407 09:31:31.578854 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5408 09:31:31.585208 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5409 09:31:31.588222 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5410 09:31:31.591503 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5411 09:31:31.594793 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5412 09:31:31.594873 ==
5413 09:31:31.598425 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 09:31:31.601750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 09:31:31.604576 ==
5416 09:31:31.604658 DQS Delay:
5417 09:31:31.604722 DQS0 = 0, DQS1 = 0
5418 09:31:31.608150 DQM Delay:
5419 09:31:31.608230 DQM0 = 97, DQM1 = 90
5420 09:31:31.611560 DQ Delay:
5421 09:31:31.614689 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5422 09:31:31.618264 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5423 09:31:31.621492 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5424 09:31:31.624682 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5425 09:31:31.624784
5426 09:31:31.624867
5427 09:31:31.624928 ==
5428 09:31:31.627708 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 09:31:31.630861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 09:31:31.630943 ==
5431 09:31:31.631007
5432 09:31:31.631066
5433 09:31:31.634559 TX Vref Scan disable
5434 09:31:31.634640 == TX Byte 0 ==
5435 09:31:31.641246 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5436 09:31:31.644414 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5437 09:31:31.644496 == TX Byte 1 ==
5438 09:31:31.651099 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5439 09:31:31.654052 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5440 09:31:31.654166 ==
5441 09:31:31.657716 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 09:31:31.660981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 09:31:31.661062 ==
5444 09:31:31.661127
5445 09:31:31.664203
5446 09:31:31.664283 TX Vref Scan disable
5447 09:31:31.667327 == TX Byte 0 ==
5448 09:31:31.670658 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5449 09:31:31.674025 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5450 09:31:31.677105 == TX Byte 1 ==
5451 09:31:31.680715 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5452 09:31:31.686993 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5453 09:31:31.687076
5454 09:31:31.687141 [DATLAT]
5455 09:31:31.687201 Freq=933, CH0 RK1
5456 09:31:31.687260
5457 09:31:31.690848 DATLAT Default: 0xb
5458 09:31:31.690930 0, 0xFFFF, sum = 0
5459 09:31:31.693910 1, 0xFFFF, sum = 0
5460 09:31:31.694018 2, 0xFFFF, sum = 0
5461 09:31:31.697123 3, 0xFFFF, sum = 0
5462 09:31:31.700503 4, 0xFFFF, sum = 0
5463 09:31:31.700589 5, 0xFFFF, sum = 0
5464 09:31:31.704089 6, 0xFFFF, sum = 0
5465 09:31:31.704172 7, 0xFFFF, sum = 0
5466 09:31:31.706911 8, 0xFFFF, sum = 0
5467 09:31:31.706994 9, 0xFFFF, sum = 0
5468 09:31:31.710943 10, 0x0, sum = 1
5469 09:31:31.711025 11, 0x0, sum = 2
5470 09:31:31.713723 12, 0x0, sum = 3
5471 09:31:31.713807 13, 0x0, sum = 4
5472 09:31:31.713872 best_step = 11
5473 09:31:31.713932
5474 09:31:31.717117 ==
5475 09:31:31.720332 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 09:31:31.723793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 09:31:31.723874 ==
5478 09:31:31.723938 RX Vref Scan: 0
5479 09:31:31.723997
5480 09:31:31.727079 RX Vref 0 -> 0, step: 1
5481 09:31:31.727161
5482 09:31:31.730348 RX Delay -61 -> 252, step: 4
5483 09:31:31.737128 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5484 09:31:31.740167 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5485 09:31:31.743779 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5486 09:31:31.746905 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5487 09:31:31.750572 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5488 09:31:31.753439 iDelay=203, Bit 5, Center 88 (-9 ~ 186) 196
5489 09:31:31.756711 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5490 09:31:31.763317 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5491 09:31:31.766872 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5492 09:31:31.770138 iDelay=203, Bit 9, Center 76 (-13 ~ 166) 180
5493 09:31:31.773519 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5494 09:31:31.779903 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5495 09:31:31.782828 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5496 09:31:31.786437 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5497 09:31:31.789784 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5498 09:31:31.793245 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5499 09:31:31.793325 ==
5500 09:31:31.796158 Dram Type= 6, Freq= 0, CH_0, rank 1
5501 09:31:31.802685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 09:31:31.802768 ==
5503 09:31:31.802831 DQS Delay:
5504 09:31:31.806059 DQS0 = 0, DQS1 = 0
5505 09:31:31.806157 DQM Delay:
5506 09:31:31.806245 DQM0 = 95, DQM1 = 88
5507 09:31:31.809236 DQ Delay:
5508 09:31:31.812654 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5509 09:31:31.816145 DQ4 =96, DQ5 =88, DQ6 =104, DQ7 =104
5510 09:31:31.819319 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =82
5511 09:31:31.822849 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5512 09:31:31.822930
5513 09:31:31.823031
5514 09:31:31.829324 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5515 09:31:31.832706 CH0 RK1: MR19=504, MR18=2AFB
5516 09:31:31.839367 CH0_RK1: MR19=0x504, MR18=0x2AFB, DQSOSC=408, MR23=63, INC=65, DEC=43
5517 09:31:31.842485 [RxdqsGatingPostProcess] freq 933
5518 09:31:31.848906 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5519 09:31:31.848989 best DQS0 dly(2T, 0.5T) = (0, 10)
5520 09:31:31.852343 best DQS1 dly(2T, 0.5T) = (0, 10)
5521 09:31:31.855714 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5522 09:31:31.859120 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5523 09:31:31.862282 best DQS0 dly(2T, 0.5T) = (0, 10)
5524 09:31:31.865329 best DQS1 dly(2T, 0.5T) = (0, 11)
5525 09:31:31.868836 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5526 09:31:31.872019 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5527 09:31:31.874889 Pre-setting of DQS Precalculation
5528 09:31:31.881834 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5529 09:31:31.881921 ==
5530 09:31:31.885066 Dram Type= 6, Freq= 0, CH_1, rank 0
5531 09:31:31.888045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 09:31:31.888126 ==
5533 09:31:31.894930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5534 09:31:31.901331 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5535 09:31:31.904798 [CA 0] Center 36 (6~67) winsize 62
5536 09:31:31.907883 [CA 1] Center 37 (6~68) winsize 63
5537 09:31:31.911476 [CA 2] Center 34 (4~65) winsize 62
5538 09:31:31.914724 [CA 3] Center 33 (3~64) winsize 62
5539 09:31:31.918092 [CA 4] Center 34 (4~64) winsize 61
5540 09:31:31.918183 [CA 5] Center 33 (3~64) winsize 62
5541 09:31:31.921037
5542 09:31:31.924456 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5543 09:31:31.924537
5544 09:31:31.928004 [CATrainingPosCal] consider 1 rank data
5545 09:31:31.930967 u2DelayCellTimex100 = 270/100 ps
5546 09:31:31.934398 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5547 09:31:31.937968 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5548 09:31:31.941000 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5549 09:31:31.944126 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5550 09:31:31.947707 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5551 09:31:31.950829 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5552 09:31:31.950909
5553 09:31:31.957709 CA PerBit enable=1, Macro0, CA PI delay=33
5554 09:31:31.957789
5555 09:31:31.957853 [CBTSetCACLKResult] CA Dly = 33
5556 09:31:31.960652 CS Dly: 6 (0~37)
5557 09:31:31.960732 ==
5558 09:31:31.964104 Dram Type= 6, Freq= 0, CH_1, rank 1
5559 09:31:31.967496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 09:31:31.967579 ==
5561 09:31:31.973887 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5562 09:31:31.980312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5563 09:31:31.984208 [CA 0] Center 36 (6~67) winsize 62
5564 09:31:31.987087 [CA 1] Center 37 (7~67) winsize 61
5565 09:31:31.990872 [CA 2] Center 34 (4~65) winsize 62
5566 09:31:31.993564 [CA 3] Center 33 (3~64) winsize 62
5567 09:31:31.997213 [CA 4] Center 34 (4~65) winsize 62
5568 09:31:32.000200 [CA 5] Center 33 (3~64) winsize 62
5569 09:31:32.000281
5570 09:31:32.003648 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5571 09:31:32.003730
5572 09:31:32.006765 [CATrainingPosCal] consider 2 rank data
5573 09:31:32.010021 u2DelayCellTimex100 = 270/100 ps
5574 09:31:32.013188 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5575 09:31:32.016660 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5576 09:31:32.019870 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5577 09:31:32.023396 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5578 09:31:32.026386 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5579 09:31:32.033529 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5580 09:31:32.033611
5581 09:31:32.037015 CA PerBit enable=1, Macro0, CA PI delay=33
5582 09:31:32.037096
5583 09:31:32.039804 [CBTSetCACLKResult] CA Dly = 33
5584 09:31:32.039885 CS Dly: 7 (0~39)
5585 09:31:32.039949
5586 09:31:32.043204 ----->DramcWriteLeveling(PI) begin...
5587 09:31:32.043285 ==
5588 09:31:32.046294 Dram Type= 6, Freq= 0, CH_1, rank 0
5589 09:31:32.053303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5590 09:31:32.053387 ==
5591 09:31:32.056342 Write leveling (Byte 0): 27 => 27
5592 09:31:32.059842 Write leveling (Byte 1): 27 => 27
5593 09:31:32.059922 DramcWriteLeveling(PI) end<-----
5594 09:31:32.059986
5595 09:31:32.062873 ==
5596 09:31:32.066201 Dram Type= 6, Freq= 0, CH_1, rank 0
5597 09:31:32.069605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5598 09:31:32.069686 ==
5599 09:31:32.072808 [Gating] SW mode calibration
5600 09:31:32.079449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5601 09:31:32.082837 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5602 09:31:32.089018 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5603 09:31:32.092409 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 09:31:32.095970 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 09:31:32.102649 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 09:31:32.105644 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 09:31:32.109332 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 09:31:32.115773 0 14 24 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 1)
5609 09:31:32.118640 0 14 28 | B1->B0 | 2a2a 2727 | 1 1 | (1 0) (1 0)
5610 09:31:32.122277 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5611 09:31:32.128624 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 09:31:32.132040 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 09:31:32.135467 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 09:31:32.142040 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 09:31:32.145319 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 09:31:32.148770 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5617 09:31:32.155162 0 15 28 | B1->B0 | 3535 3b3b | 0 1 | (0 0) (0 0)
5618 09:31:32.158058 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5619 09:31:32.161330 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 09:31:32.168131 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 09:31:32.171436 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 09:31:32.174839 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 09:31:32.181482 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 09:31:32.184904 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5625 09:31:32.188189 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5626 09:31:32.194373 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5627 09:31:32.197774 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 09:31:32.201131 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 09:31:32.207873 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 09:31:32.210932 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 09:31:32.214349 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 09:31:32.221138 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 09:31:32.224453 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 09:31:32.227484 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 09:31:32.234216 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 09:31:32.237519 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 09:31:32.240609 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 09:31:32.247185 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 09:31:32.250431 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 09:31:32.253812 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5641 09:31:32.259893 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5642 09:31:32.263309 Total UI for P1: 0, mck2ui 16
5643 09:31:32.266689 best dqsien dly found for B0: ( 1, 2, 24)
5644 09:31:32.269939 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5645 09:31:32.276548 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 09:31:32.276639 Total UI for P1: 0, mck2ui 16
5647 09:31:32.279762 best dqsien dly found for B1: ( 1, 2, 30)
5648 09:31:32.286575 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5649 09:31:32.289561 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5650 09:31:32.289643
5651 09:31:32.292853 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5652 09:31:32.296192 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5653 09:31:32.299731 [Gating] SW calibration Done
5654 09:31:32.299812 ==
5655 09:31:32.302597 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 09:31:32.306379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 09:31:32.306471 ==
5658 09:31:32.309508 RX Vref Scan: 0
5659 09:31:32.309589
5660 09:31:32.309652 RX Vref 0 -> 0, step: 1
5661 09:31:32.309711
5662 09:31:32.312902 RX Delay -80 -> 252, step: 8
5663 09:31:32.319538 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5664 09:31:32.322547 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5665 09:31:32.325826 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5666 09:31:32.329176 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5667 09:31:32.332529 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5668 09:31:32.336278 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5669 09:31:32.339414 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5670 09:31:32.345767 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5671 09:31:32.349102 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5672 09:31:32.352514 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5673 09:31:32.355439 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5674 09:31:32.359184 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5675 09:31:32.365518 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5676 09:31:32.368975 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5677 09:31:32.371933 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5678 09:31:32.375079 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5679 09:31:32.375159 ==
5680 09:31:32.378635 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 09:31:32.385162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 09:31:32.385243 ==
5683 09:31:32.385308 DQS Delay:
5684 09:31:32.385368 DQS0 = 0, DQS1 = 0
5685 09:31:32.388699 DQM Delay:
5686 09:31:32.388804 DQM0 = 101, DQM1 = 90
5687 09:31:32.392114 DQ Delay:
5688 09:31:32.395086 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =99
5689 09:31:32.398493 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5690 09:31:32.402078 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5691 09:31:32.404930 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5692 09:31:32.405010
5693 09:31:32.405074
5694 09:31:32.405133 ==
5695 09:31:32.408233 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 09:31:32.411456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 09:31:32.411536 ==
5698 09:31:32.411600
5699 09:31:32.411658
5700 09:31:32.414862 TX Vref Scan disable
5701 09:31:32.418421 == TX Byte 0 ==
5702 09:31:32.421828 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5703 09:31:32.424740 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5704 09:31:32.428236 == TX Byte 1 ==
5705 09:31:32.431295 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5706 09:31:32.434399 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5707 09:31:32.434479 ==
5708 09:31:32.437703 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 09:31:32.444354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 09:31:32.444476 ==
5711 09:31:32.444541
5712 09:31:32.444600
5713 09:31:32.444657 TX Vref Scan disable
5714 09:31:32.448633 == TX Byte 0 ==
5715 09:31:32.451606 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5716 09:31:32.458062 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5717 09:31:32.458143 == TX Byte 1 ==
5718 09:31:32.461427 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5719 09:31:32.467940 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5720 09:31:32.468025
5721 09:31:32.468100 [DATLAT]
5722 09:31:32.468164 Freq=933, CH1 RK0
5723 09:31:32.468222
5724 09:31:32.471223 DATLAT Default: 0xd
5725 09:31:32.474192 0, 0xFFFF, sum = 0
5726 09:31:32.474288 1, 0xFFFF, sum = 0
5727 09:31:32.477678 2, 0xFFFF, sum = 0
5728 09:31:32.477759 3, 0xFFFF, sum = 0
5729 09:31:32.481172 4, 0xFFFF, sum = 0
5730 09:31:32.481262 5, 0xFFFF, sum = 0
5731 09:31:32.484278 6, 0xFFFF, sum = 0
5732 09:31:32.484360 7, 0xFFFF, sum = 0
5733 09:31:32.487426 8, 0xFFFF, sum = 0
5734 09:31:32.487508 9, 0xFFFF, sum = 0
5735 09:31:32.490829 10, 0x0, sum = 1
5736 09:31:32.490911 11, 0x0, sum = 2
5737 09:31:32.493897 12, 0x0, sum = 3
5738 09:31:32.493978 13, 0x0, sum = 4
5739 09:31:32.497502 best_step = 11
5740 09:31:32.497582
5741 09:31:32.497645 ==
5742 09:31:32.500525 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 09:31:32.503845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 09:31:32.503926 ==
5745 09:31:32.506996 RX Vref Scan: 1
5746 09:31:32.507076
5747 09:31:32.507139 RX Vref 0 -> 0, step: 1
5748 09:31:32.507198
5749 09:31:32.510677 RX Delay -69 -> 252, step: 4
5750 09:31:32.510758
5751 09:31:32.513601 Set Vref, RX VrefLevel [Byte0]: 51
5752 09:31:32.517280 [Byte1]: 59
5753 09:31:32.520785
5754 09:31:32.524232 Final RX Vref Byte 0 = 51 to rank0
5755 09:31:32.524312 Final RX Vref Byte 1 = 59 to rank0
5756 09:31:32.527215 Final RX Vref Byte 0 = 51 to rank1
5757 09:31:32.530720 Final RX Vref Byte 1 = 59 to rank1==
5758 09:31:32.533736 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 09:31:32.540293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 09:31:32.540374 ==
5761 09:31:32.540438 DQS Delay:
5762 09:31:32.543760 DQS0 = 0, DQS1 = 0
5763 09:31:32.543839 DQM Delay:
5764 09:31:32.543903 DQM0 = 100, DQM1 = 94
5765 09:31:32.546989 DQ Delay:
5766 09:31:32.550123 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5767 09:31:32.553353 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =96
5768 09:31:32.556539 DQ8 =82, DQ9 =86, DQ10 =92, DQ11 =86
5769 09:31:32.560168 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =104
5770 09:31:32.560274
5771 09:31:32.560339
5772 09:31:32.566563 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5773 09:31:32.569968 CH1 RK0: MR19=505, MR18=1D0D
5774 09:31:32.576947 CH1_RK0: MR19=0x505, MR18=0x1D0D, DQSOSC=412, MR23=63, INC=63, DEC=42
5775 09:31:32.577030
5776 09:31:32.579788 ----->DramcWriteLeveling(PI) begin...
5777 09:31:32.579870 ==
5778 09:31:32.583256 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 09:31:32.589738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 09:31:32.589819 ==
5781 09:31:32.592784 Write leveling (Byte 0): 27 => 27
5782 09:31:32.592864 Write leveling (Byte 1): 28 => 28
5783 09:31:32.596164 DramcWriteLeveling(PI) end<-----
5784 09:31:32.596243
5785 09:31:32.599713 ==
5786 09:31:32.599793 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 09:31:32.606112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 09:31:32.606234 ==
5789 09:31:32.609623 [Gating] SW mode calibration
5790 09:31:32.615952 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5791 09:31:32.619075 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5792 09:31:32.625784 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
5793 09:31:32.629205 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 09:31:32.632497 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 09:31:32.638723 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 09:31:32.642231 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 09:31:32.645672 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 09:31:32.652560 0 14 24 | B1->B0 | 3131 3333 | 1 1 | (1 0) (1 0)
5799 09:31:32.655458 0 14 28 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (0 0)
5800 09:31:32.658595 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
5801 09:31:32.665395 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 09:31:32.668517 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 09:31:32.672037 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 09:31:32.678736 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 09:31:32.681929 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 09:31:32.685242 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5807 09:31:32.691735 0 15 28 | B1->B0 | 3e3e 3332 | 0 1 | (0 0) (0 0)
5808 09:31:32.695035 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 09:31:32.698449 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 09:31:32.704849 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 09:31:32.707991 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 09:31:32.711761 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 09:31:32.717945 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 09:31:32.721264 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 09:31:32.724424 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5816 09:31:32.731417 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 09:31:32.734962 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 09:31:32.737829 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 09:31:32.744932 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 09:31:32.747770 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 09:31:32.750962 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 09:31:32.757944 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 09:31:32.760803 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 09:31:32.764336 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 09:31:32.771221 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 09:31:32.774042 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 09:31:32.777389 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 09:31:32.784544 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 09:31:32.787857 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5830 09:31:32.790816 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5831 09:31:32.797404 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 09:31:32.797490 Total UI for P1: 0, mck2ui 16
5833 09:31:32.804504 best dqsien dly found for B0: ( 1, 2, 26)
5834 09:31:32.804591 Total UI for P1: 0, mck2ui 16
5835 09:31:32.810773 best dqsien dly found for B1: ( 1, 2, 22)
5836 09:31:32.814056 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5837 09:31:32.817093 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5838 09:31:32.817173
5839 09:31:32.820158 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5840 09:31:32.823654 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5841 09:31:32.827137 [Gating] SW calibration Done
5842 09:31:32.827218 ==
5843 09:31:32.830356 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 09:31:32.833252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 09:31:32.833333 ==
5846 09:31:32.836625 RX Vref Scan: 0
5847 09:31:32.836704
5848 09:31:32.836767 RX Vref 0 -> 0, step: 1
5849 09:31:32.840153
5850 09:31:32.840232 RX Delay -80 -> 252, step: 8
5851 09:31:32.846365 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5852 09:31:32.849720 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5853 09:31:32.853135 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5854 09:31:32.856292 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5855 09:31:32.859877 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5856 09:31:32.862811 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5857 09:31:32.869685 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5858 09:31:32.872648 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5859 09:31:32.876143 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5860 09:31:32.879298 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5861 09:31:32.882767 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5862 09:31:32.889396 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5863 09:31:32.892414 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5864 09:31:32.895566 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5865 09:31:32.899260 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5866 09:31:32.902403 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5867 09:31:32.905580 ==
5868 09:31:32.905660 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 09:31:32.912153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 09:31:32.912239 ==
5871 09:31:32.912324 DQS Delay:
5872 09:31:32.915669 DQS0 = 0, DQS1 = 0
5873 09:31:32.915753 DQM Delay:
5874 09:31:32.918952 DQM0 = 100, DQM1 = 91
5875 09:31:32.919035 DQ Delay:
5876 09:31:32.921990 DQ0 =103, DQ1 =99, DQ2 =87, DQ3 =99
5877 09:31:32.925381 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5878 09:31:32.928902 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5879 09:31:32.931840 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5880 09:31:32.931928
5881 09:31:32.932012
5882 09:31:32.932091 ==
5883 09:31:32.935337 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 09:31:32.938983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 09:31:32.939066 ==
5886 09:31:32.941692
5887 09:31:32.941774
5888 09:31:32.941856 TX Vref Scan disable
5889 09:31:32.945065 == TX Byte 0 ==
5890 09:31:32.948600 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5891 09:31:32.951792 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5892 09:31:32.954673 == TX Byte 1 ==
5893 09:31:32.958312 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5894 09:31:32.961587 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5895 09:31:32.964916 ==
5896 09:31:32.968434 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 09:31:32.971310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 09:31:32.971390 ==
5899 09:31:32.971453
5900 09:31:32.971526
5901 09:31:32.974587 TX Vref Scan disable
5902 09:31:32.974667 == TX Byte 0 ==
5903 09:31:32.981349 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5904 09:31:32.984422 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5905 09:31:32.984502 == TX Byte 1 ==
5906 09:31:32.990754 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5907 09:31:32.993997 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5908 09:31:32.994078
5909 09:31:32.994141 [DATLAT]
5910 09:31:32.997639 Freq=933, CH1 RK1
5911 09:31:32.997719
5912 09:31:32.997782 DATLAT Default: 0xb
5913 09:31:33.001118 0, 0xFFFF, sum = 0
5914 09:31:33.001199 1, 0xFFFF, sum = 0
5915 09:31:33.003883 2, 0xFFFF, sum = 0
5916 09:31:33.007544 3, 0xFFFF, sum = 0
5917 09:31:33.007624 4, 0xFFFF, sum = 0
5918 09:31:33.010709 5, 0xFFFF, sum = 0
5919 09:31:33.010790 6, 0xFFFF, sum = 0
5920 09:31:33.014346 7, 0xFFFF, sum = 0
5921 09:31:33.014427 8, 0xFFFF, sum = 0
5922 09:31:33.017267 9, 0xFFFF, sum = 0
5923 09:31:33.017348 10, 0x0, sum = 1
5924 09:31:33.020403 11, 0x0, sum = 2
5925 09:31:33.020484 12, 0x0, sum = 3
5926 09:31:33.023636 13, 0x0, sum = 4
5927 09:31:33.023717 best_step = 11
5928 09:31:33.023779
5929 09:31:33.023838 ==
5930 09:31:33.026949 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 09:31:33.030497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 09:31:33.030578 ==
5933 09:31:33.033626 RX Vref Scan: 0
5934 09:31:33.033705
5935 09:31:33.037170 RX Vref 0 -> 0, step: 1
5936 09:31:33.037250
5937 09:31:33.037314 RX Delay -61 -> 252, step: 4
5938 09:31:33.045112 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5939 09:31:33.048077 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5940 09:31:33.051547 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5941 09:31:33.055146 iDelay=207, Bit 3, Center 100 (15 ~ 186) 172
5942 09:31:33.058021 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5943 09:31:33.064869 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5944 09:31:33.067821 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
5945 09:31:33.071276 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5946 09:31:33.074621 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5947 09:31:33.077899 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5948 09:31:33.081428 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
5949 09:31:33.087723 iDelay=207, Bit 11, Center 82 (-9 ~ 174) 184
5950 09:31:33.091140 iDelay=207, Bit 12, Center 100 (7 ~ 194) 188
5951 09:31:33.094448 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
5952 09:31:33.097780 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
5953 09:31:33.101175 iDelay=207, Bit 15, Center 100 (7 ~ 194) 188
5954 09:31:33.104165 ==
5955 09:31:33.107713 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 09:31:33.111029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 09:31:33.111111 ==
5958 09:31:33.111174 DQS Delay:
5959 09:31:33.113974 DQS0 = 0, DQS1 = 0
5960 09:31:33.114054 DQM Delay:
5961 09:31:33.117778 DQM0 = 101, DQM1 = 92
5962 09:31:33.117881 DQ Delay:
5963 09:31:33.121056 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =100
5964 09:31:33.123967 DQ4 =98, DQ5 =110, DQ6 =116, DQ7 =98
5965 09:31:33.127264 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =82
5966 09:31:33.130633 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =100
5967 09:31:33.130713
5968 09:31:33.130776
5969 09:31:33.140781 [DQSOSCAuto] RK1, (LSB)MR18= 0x802, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5970 09:31:33.140900 CH1 RK1: MR19=505, MR18=802
5971 09:31:33.147177 CH1_RK1: MR19=0x505, MR18=0x802, DQSOSC=419, MR23=63, INC=61, DEC=41
5972 09:31:33.150392 [RxdqsGatingPostProcess] freq 933
5973 09:31:33.157089 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5974 09:31:33.160699 best DQS0 dly(2T, 0.5T) = (0, 10)
5975 09:31:33.164118 best DQS1 dly(2T, 0.5T) = (0, 10)
5976 09:31:33.166895 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5977 09:31:33.170676 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5978 09:31:33.170761 best DQS0 dly(2T, 0.5T) = (0, 10)
5979 09:31:33.173662 best DQS1 dly(2T, 0.5T) = (0, 10)
5980 09:31:33.177427 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5981 09:31:33.180409 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5982 09:31:33.183576 Pre-setting of DQS Precalculation
5983 09:31:33.190004 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5984 09:31:33.196776 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5985 09:31:33.203371 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5986 09:31:33.203454
5987 09:31:33.203518
5988 09:31:33.206869 [Calibration Summary] 1866 Mbps
5989 09:31:33.206950 CH 0, Rank 0
5990 09:31:33.209931 SW Impedance : PASS
5991 09:31:33.213286 DUTY Scan : NO K
5992 09:31:33.213367 ZQ Calibration : PASS
5993 09:31:33.216778 Jitter Meter : NO K
5994 09:31:33.219811 CBT Training : PASS
5995 09:31:33.219893 Write leveling : PASS
5996 09:31:33.223545 RX DQS gating : PASS
5997 09:31:33.226213 RX DQ/DQS(RDDQC) : PASS
5998 09:31:33.226294 TX DQ/DQS : PASS
5999 09:31:33.229826 RX DATLAT : PASS
6000 09:31:33.233152 RX DQ/DQS(Engine): PASS
6001 09:31:33.233233 TX OE : NO K
6002 09:31:33.236327 All Pass.
6003 09:31:33.236408
6004 09:31:33.236473 CH 0, Rank 1
6005 09:31:33.239726 SW Impedance : PASS
6006 09:31:33.239807 DUTY Scan : NO K
6007 09:31:33.242759 ZQ Calibration : PASS
6008 09:31:33.246075 Jitter Meter : NO K
6009 09:31:33.246158 CBT Training : PASS
6010 09:31:33.249567 Write leveling : PASS
6011 09:31:33.252495 RX DQS gating : PASS
6012 09:31:33.252577 RX DQ/DQS(RDDQC) : PASS
6013 09:31:33.256360 TX DQ/DQS : PASS
6014 09:31:33.259588 RX DATLAT : PASS
6015 09:31:33.259669 RX DQ/DQS(Engine): PASS
6016 09:31:33.263166 TX OE : NO K
6017 09:31:33.263247 All Pass.
6018 09:31:33.263319
6019 09:31:33.266170 CH 1, Rank 0
6020 09:31:33.266312 SW Impedance : PASS
6021 09:31:33.269060 DUTY Scan : NO K
6022 09:31:33.272669 ZQ Calibration : PASS
6023 09:31:33.272752 Jitter Meter : NO K
6024 09:31:33.276004 CBT Training : PASS
6025 09:31:33.276086 Write leveling : PASS
6026 09:31:33.278954 RX DQS gating : PASS
6027 09:31:33.282393 RX DQ/DQS(RDDQC) : PASS
6028 09:31:33.282474 TX DQ/DQS : PASS
6029 09:31:33.286243 RX DATLAT : PASS
6030 09:31:33.289449 RX DQ/DQS(Engine): PASS
6031 09:31:33.289535 TX OE : NO K
6032 09:31:33.292380 All Pass.
6033 09:31:33.292461
6034 09:31:33.292525 CH 1, Rank 1
6035 09:31:33.295983 SW Impedance : PASS
6036 09:31:33.296071 DUTY Scan : NO K
6037 09:31:33.299291 ZQ Calibration : PASS
6038 09:31:33.302505 Jitter Meter : NO K
6039 09:31:33.302601 CBT Training : PASS
6040 09:31:33.305407 Write leveling : PASS
6041 09:31:33.308679 RX DQS gating : PASS
6042 09:31:33.308760 RX DQ/DQS(RDDQC) : PASS
6043 09:31:33.312178 TX DQ/DQS : PASS
6044 09:31:33.315181 RX DATLAT : PASS
6045 09:31:33.315274 RX DQ/DQS(Engine): PASS
6046 09:31:33.318697 TX OE : NO K
6047 09:31:33.318778 All Pass.
6048 09:31:33.318843
6049 09:31:33.322265 DramC Write-DBI off
6050 09:31:33.325572 PER_BANK_REFRESH: Hybrid Mode
6051 09:31:33.325677 TX_TRACKING: ON
6052 09:31:33.334902 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6053 09:31:33.338742 [FAST_K] Save calibration result to emmc
6054 09:31:33.341532 dramc_set_vcore_voltage set vcore to 650000
6055 09:31:33.345488 Read voltage for 400, 6
6056 09:31:33.345572 Vio18 = 0
6057 09:31:33.345637 Vcore = 650000
6058 09:31:33.348328 Vdram = 0
6059 09:31:33.348409 Vddq = 0
6060 09:31:33.348474 Vmddr = 0
6061 09:31:33.355032 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6062 09:31:33.358384 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6063 09:31:33.362016 MEM_TYPE=3, freq_sel=20
6064 09:31:33.365088 sv_algorithm_assistance_LP4_800
6065 09:31:33.368434 ============ PULL DRAM RESETB DOWN ============
6066 09:31:33.374937 ========== PULL DRAM RESETB DOWN end =========
6067 09:31:33.378105 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6068 09:31:33.381485 ===================================
6069 09:31:33.384460 LPDDR4 DRAM CONFIGURATION
6070 09:31:33.387885 ===================================
6071 09:31:33.387967 EX_ROW_EN[0] = 0x0
6072 09:31:33.391107 EX_ROW_EN[1] = 0x0
6073 09:31:33.391263 LP4Y_EN = 0x0
6074 09:31:33.394940 WORK_FSP = 0x0
6075 09:31:33.395020 WL = 0x2
6076 09:31:33.397730 RL = 0x2
6077 09:31:33.397810 BL = 0x2
6078 09:31:33.401040 RPST = 0x0
6079 09:31:33.401120 RD_PRE = 0x0
6080 09:31:33.404429 WR_PRE = 0x1
6081 09:31:33.407817 WR_PST = 0x0
6082 09:31:33.407897 DBI_WR = 0x0
6083 09:31:33.411352 DBI_RD = 0x0
6084 09:31:33.411433 OTF = 0x1
6085 09:31:33.414124 ===================================
6086 09:31:33.417519 ===================================
6087 09:31:33.420918 ANA top config
6088 09:31:33.421024 ===================================
6089 09:31:33.424332 DLL_ASYNC_EN = 0
6090 09:31:33.427421 ALL_SLAVE_EN = 1
6091 09:31:33.430705 NEW_RANK_MODE = 1
6092 09:31:33.434217 DLL_IDLE_MODE = 1
6093 09:31:33.434297 LP45_APHY_COMB_EN = 1
6094 09:31:33.437739 TX_ODT_DIS = 1
6095 09:31:33.440861 NEW_8X_MODE = 1
6096 09:31:33.443889 ===================================
6097 09:31:33.447080 ===================================
6098 09:31:33.453767 data_rate = 800
6099 09:31:33.453848 CKR = 1
6100 09:31:33.457119 DQ_P2S_RATIO = 4
6101 09:31:33.460700 ===================================
6102 09:31:33.460798 CA_P2S_RATIO = 4
6103 09:31:33.463560 DQ_CA_OPEN = 0
6104 09:31:33.467022 DQ_SEMI_OPEN = 1
6105 09:31:33.470279 CA_SEMI_OPEN = 1
6106 09:31:33.473591 CA_FULL_RATE = 0
6107 09:31:33.477154 DQ_CKDIV4_EN = 0
6108 09:31:33.477237 CA_CKDIV4_EN = 1
6109 09:31:33.480131 CA_PREDIV_EN = 0
6110 09:31:33.483763 PH8_DLY = 0
6111 09:31:33.486596 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6112 09:31:33.490250 DQ_AAMCK_DIV = 0
6113 09:31:33.493287 CA_AAMCK_DIV = 0
6114 09:31:33.493394 CA_ADMCK_DIV = 4
6115 09:31:33.496563 DQ_TRACK_CA_EN = 0
6116 09:31:33.500048 CA_PICK = 800
6117 09:31:33.503050 CA_MCKIO = 400
6118 09:31:33.506396 MCKIO_SEMI = 400
6119 09:31:33.509703 PLL_FREQ = 3016
6120 09:31:33.513174 DQ_UI_PI_RATIO = 32
6121 09:31:33.515965 CA_UI_PI_RATIO = 32
6122 09:31:33.519431 ===================================
6123 09:31:33.523248 ===================================
6124 09:31:33.523328 memory_type:LPDDR4
6125 09:31:33.526476 GP_NUM : 10
6126 09:31:33.529399 SRAM_EN : 1
6127 09:31:33.529473 MD32_EN : 0
6128 09:31:33.532804 ===================================
6129 09:31:33.536325 [ANA_INIT] >>>>>>>>>>>>>>
6130 09:31:33.539725 <<<<<< [CONFIGURE PHASE]: ANA_TX
6131 09:31:33.542539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6132 09:31:33.546063 ===================================
6133 09:31:33.549341 data_rate = 800,PCW = 0X7400
6134 09:31:33.552441 ===================================
6135 09:31:33.555571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6136 09:31:33.559178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6137 09:31:33.572128 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6138 09:31:33.575882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6139 09:31:33.579458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6140 09:31:33.582124 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6141 09:31:33.585727 [ANA_INIT] flow start
6142 09:31:33.588933 [ANA_INIT] PLL >>>>>>>>
6143 09:31:33.589010 [ANA_INIT] PLL <<<<<<<<
6144 09:31:33.592571 [ANA_INIT] MIDPI >>>>>>>>
6145 09:31:33.595753 [ANA_INIT] MIDPI <<<<<<<<
6146 09:31:33.595832 [ANA_INIT] DLL >>>>>>>>
6147 09:31:33.599203 [ANA_INIT] flow end
6148 09:31:33.602153 ============ LP4 DIFF to SE enter ============
6149 09:31:33.605905 ============ LP4 DIFF to SE exit ============
6150 09:31:33.608671 [ANA_INIT] <<<<<<<<<<<<<
6151 09:31:33.611995 [Flow] Enable top DCM control >>>>>
6152 09:31:33.615329 [Flow] Enable top DCM control <<<<<
6153 09:31:33.618529 Enable DLL master slave shuffle
6154 09:31:33.625678 ==============================================================
6155 09:31:33.625765 Gating Mode config
6156 09:31:33.631821 ==============================================================
6157 09:31:33.631908 Config description:
6158 09:31:33.642338 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6159 09:31:33.648472 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6160 09:31:33.654953 SELPH_MODE 0: By rank 1: By Phase
6161 09:31:33.661571 ==============================================================
6162 09:31:33.661663 GAT_TRACK_EN = 0
6163 09:31:33.665036 RX_GATING_MODE = 2
6164 09:31:33.668411 RX_GATING_TRACK_MODE = 2
6165 09:31:33.671360 SELPH_MODE = 1
6166 09:31:33.674662 PICG_EARLY_EN = 1
6167 09:31:33.677929 VALID_LAT_VALUE = 1
6168 09:31:33.684678 ==============================================================
6169 09:31:33.687979 Enter into Gating configuration >>>>
6170 09:31:33.691412 Exit from Gating configuration <<<<
6171 09:31:33.694265 Enter into DVFS_PRE_config >>>>>
6172 09:31:33.704254 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6173 09:31:33.707625 Exit from DVFS_PRE_config <<<<<
6174 09:31:33.711101 Enter into PICG configuration >>>>
6175 09:31:33.714062 Exit from PICG configuration <<<<
6176 09:31:33.717502 [RX_INPUT] configuration >>>>>
6177 09:31:33.720702 [RX_INPUT] configuration <<<<<
6178 09:31:33.723938 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6179 09:31:33.730453 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6180 09:31:33.737053 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6181 09:31:33.743647 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6182 09:31:33.747036 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6183 09:31:33.753562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6184 09:31:33.760550 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6185 09:31:33.763383 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6186 09:31:33.766623 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6187 09:31:33.770418 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6188 09:31:33.776697 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6189 09:31:33.780167 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6190 09:31:33.783070 ===================================
6191 09:31:33.787115 LPDDR4 DRAM CONFIGURATION
6192 09:31:33.790080 ===================================
6193 09:31:33.790168 EX_ROW_EN[0] = 0x0
6194 09:31:33.793044 EX_ROW_EN[1] = 0x0
6195 09:31:33.793126 LP4Y_EN = 0x0
6196 09:31:33.796572 WORK_FSP = 0x0
6197 09:31:33.796654 WL = 0x2
6198 09:31:33.800059 RL = 0x2
6199 09:31:33.800141 BL = 0x2
6200 09:31:33.802950 RPST = 0x0
6201 09:31:33.803032 RD_PRE = 0x0
6202 09:31:33.806753 WR_PRE = 0x1
6203 09:31:33.806834 WR_PST = 0x0
6204 09:31:33.809732 DBI_WR = 0x0
6205 09:31:33.813254 DBI_RD = 0x0
6206 09:31:33.813336 OTF = 0x1
6207 09:31:33.816236 ===================================
6208 09:31:33.819586 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6209 09:31:33.823102 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6210 09:31:33.829373 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6211 09:31:33.832726 ===================================
6212 09:31:33.836093 LPDDR4 DRAM CONFIGURATION
6213 09:31:33.839759 ===================================
6214 09:31:33.839841 EX_ROW_EN[0] = 0x10
6215 09:31:33.842999 EX_ROW_EN[1] = 0x0
6216 09:31:33.843084 LP4Y_EN = 0x0
6217 09:31:33.846159 WORK_FSP = 0x0
6218 09:31:33.846276 WL = 0x2
6219 09:31:33.849527 RL = 0x2
6220 09:31:33.849607 BL = 0x2
6221 09:31:33.852918 RPST = 0x0
6222 09:31:33.852998 RD_PRE = 0x0
6223 09:31:33.856087 WR_PRE = 0x1
6224 09:31:33.856167 WR_PST = 0x0
6225 09:31:33.859633 DBI_WR = 0x0
6226 09:31:33.862695 DBI_RD = 0x0
6227 09:31:33.862776 OTF = 0x1
6228 09:31:33.866130 ===================================
6229 09:31:33.872803 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6230 09:31:33.875919 nWR fixed to 30
6231 09:31:33.879465 [ModeRegInit_LP4] CH0 RK0
6232 09:31:33.879550 [ModeRegInit_LP4] CH0 RK1
6233 09:31:33.882450 [ModeRegInit_LP4] CH1 RK0
6234 09:31:33.886222 [ModeRegInit_LP4] CH1 RK1
6235 09:31:33.886303 match AC timing 19
6236 09:31:33.892466 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6237 09:31:33.895816 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6238 09:31:33.899077 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6239 09:31:33.906082 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6240 09:31:33.909266 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6241 09:31:33.909351 ==
6242 09:31:33.912190 Dram Type= 6, Freq= 0, CH_0, rank 0
6243 09:31:33.915649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6244 09:31:33.915732 ==
6245 09:31:33.922530 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6246 09:31:33.929345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6247 09:31:33.932671 [CA 0] Center 36 (8~64) winsize 57
6248 09:31:33.935288 [CA 1] Center 36 (8~64) winsize 57
6249 09:31:33.938613 [CA 2] Center 36 (8~64) winsize 57
6250 09:31:33.942276 [CA 3] Center 36 (8~64) winsize 57
6251 09:31:33.945058 [CA 4] Center 36 (8~64) winsize 57
6252 09:31:33.948541 [CA 5] Center 36 (8~64) winsize 57
6253 09:31:33.948621
6254 09:31:33.952075 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6255 09:31:33.952156
6256 09:31:33.955646 [CATrainingPosCal] consider 1 rank data
6257 09:31:33.958658 u2DelayCellTimex100 = 270/100 ps
6258 09:31:33.961703 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 09:31:33.965314 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 09:31:33.968607 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 09:31:33.972015 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 09:31:33.974749 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 09:31:33.978198 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 09:31:33.978293
6265 09:31:33.985162 CA PerBit enable=1, Macro0, CA PI delay=36
6266 09:31:33.985245
6267 09:31:33.985308 [CBTSetCACLKResult] CA Dly = 36
6268 09:31:33.988162 CS Dly: 1 (0~32)
6269 09:31:33.988263 ==
6270 09:31:33.991295 Dram Type= 6, Freq= 0, CH_0, rank 1
6271 09:31:33.994656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 09:31:33.994764 ==
6273 09:31:34.001468 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6274 09:31:34.008185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6275 09:31:34.011347 [CA 0] Center 36 (8~64) winsize 57
6276 09:31:34.014338 [CA 1] Center 36 (8~64) winsize 57
6277 09:31:34.017778 [CA 2] Center 36 (8~64) winsize 57
6278 09:31:34.020990 [CA 3] Center 36 (8~64) winsize 57
6279 09:31:34.021065 [CA 4] Center 36 (8~64) winsize 57
6280 09:31:34.024375 [CA 5] Center 36 (8~64) winsize 57
6281 09:31:34.024451
6282 09:31:34.030863 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6283 09:31:34.030938
6284 09:31:34.034369 [CATrainingPosCal] consider 2 rank data
6285 09:31:34.037515 u2DelayCellTimex100 = 270/100 ps
6286 09:31:34.040691 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 09:31:34.043840 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 09:31:34.047603 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 09:31:34.050309 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 09:31:34.054012 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 09:31:34.057363 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 09:31:34.057470
6293 09:31:34.060334 CA PerBit enable=1, Macro0, CA PI delay=36
6294 09:31:34.060416
6295 09:31:34.063702 [CBTSetCACLKResult] CA Dly = 36
6296 09:31:34.067520 CS Dly: 1 (0~32)
6297 09:31:34.067602
6298 09:31:34.070322 ----->DramcWriteLeveling(PI) begin...
6299 09:31:34.070456 ==
6300 09:31:34.073422 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 09:31:34.076750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 09:31:34.076832 ==
6303 09:31:34.080190 Write leveling (Byte 0): 40 => 8
6304 09:31:34.083163 Write leveling (Byte 1): 32 => 0
6305 09:31:34.086454 DramcWriteLeveling(PI) end<-----
6306 09:31:34.086529
6307 09:31:34.086591 ==
6308 09:31:34.089803 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 09:31:34.093619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 09:31:34.096865 ==
6311 09:31:34.096944 [Gating] SW mode calibration
6312 09:31:34.103029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6313 09:31:34.109749 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6314 09:31:34.113239 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6315 09:31:34.119982 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6316 09:31:34.123215 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 09:31:34.126750 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 09:31:34.133222 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 09:31:34.136747 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 09:31:34.139628 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 09:31:34.146675 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 09:31:34.149941 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 09:31:34.153246 Total UI for P1: 0, mck2ui 16
6324 09:31:34.156728 best dqsien dly found for B0: ( 0, 14, 24)
6325 09:31:34.159650 Total UI for P1: 0, mck2ui 16
6326 09:31:34.163227 best dqsien dly found for B1: ( 0, 14, 24)
6327 09:31:34.166140 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6328 09:31:34.169792 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6329 09:31:34.169873
6330 09:31:34.173164 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6331 09:31:34.176274 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6332 09:31:34.179738 [Gating] SW calibration Done
6333 09:31:34.179837 ==
6334 09:31:34.182979 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 09:31:34.186288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 09:31:34.189465 ==
6337 09:31:34.189545 RX Vref Scan: 0
6338 09:31:34.189609
6339 09:31:34.192944 RX Vref 0 -> 0, step: 1
6340 09:31:34.193024
6341 09:31:34.195727 RX Delay -410 -> 252, step: 16
6342 09:31:34.199059 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6343 09:31:34.202525 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6344 09:31:34.205969 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6345 09:31:34.212516 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6346 09:31:34.215566 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6347 09:31:34.218982 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6348 09:31:34.222218 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6349 09:31:34.228696 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6350 09:31:34.231963 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6351 09:31:34.235312 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6352 09:31:34.242196 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6353 09:31:34.245674 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6354 09:31:34.248665 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6355 09:31:34.252197 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6356 09:31:34.258641 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6357 09:31:34.261605 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6358 09:31:34.261687 ==
6359 09:31:34.265140 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 09:31:34.268675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 09:31:34.268766 ==
6362 09:31:34.271496 DQS Delay:
6363 09:31:34.271604 DQS0 = 43, DQS1 = 59
6364 09:31:34.275248 DQM Delay:
6365 09:31:34.275329 DQM0 = 10, DQM1 = 11
6366 09:31:34.275394 DQ Delay:
6367 09:31:34.278006 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6368 09:31:34.281452 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6369 09:31:34.284801 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6370 09:31:34.288373 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6371 09:31:34.288460
6372 09:31:34.288525
6373 09:31:34.288584 ==
6374 09:31:34.291717 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 09:31:34.297962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 09:31:34.298048 ==
6377 09:31:34.298112
6378 09:31:34.298200
6379 09:31:34.298274 TX Vref Scan disable
6380 09:31:34.301287 == TX Byte 0 ==
6381 09:31:34.304864 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 09:31:34.307767 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 09:31:34.311205 == TX Byte 1 ==
6384 09:31:34.314514 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6385 09:31:34.317841 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6386 09:31:34.321033 ==
6387 09:31:34.324495 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 09:31:34.327621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 09:31:34.327702 ==
6390 09:31:34.327766
6391 09:31:34.327826
6392 09:31:34.331016 TX Vref Scan disable
6393 09:31:34.331097 == TX Byte 0 ==
6394 09:31:34.334473 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 09:31:34.340707 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 09:31:34.340790 == TX Byte 1 ==
6397 09:31:34.343932 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6398 09:31:34.350701 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6399 09:31:34.350785
6400 09:31:34.350850 [DATLAT]
6401 09:31:34.350911 Freq=400, CH0 RK0
6402 09:31:34.350970
6403 09:31:34.354224 DATLAT Default: 0xf
6404 09:31:34.357412 0, 0xFFFF, sum = 0
6405 09:31:34.357495 1, 0xFFFF, sum = 0
6406 09:31:34.360858 2, 0xFFFF, sum = 0
6407 09:31:34.360940 3, 0xFFFF, sum = 0
6408 09:31:34.364071 4, 0xFFFF, sum = 0
6409 09:31:34.364154 5, 0xFFFF, sum = 0
6410 09:31:34.367594 6, 0xFFFF, sum = 0
6411 09:31:34.367678 7, 0xFFFF, sum = 0
6412 09:31:34.370346 8, 0xFFFF, sum = 0
6413 09:31:34.370432 9, 0xFFFF, sum = 0
6414 09:31:34.373774 10, 0xFFFF, sum = 0
6415 09:31:34.373859 11, 0xFFFF, sum = 0
6416 09:31:34.377240 12, 0xFFFF, sum = 0
6417 09:31:34.377324 13, 0x0, sum = 1
6418 09:31:34.380639 14, 0x0, sum = 2
6419 09:31:34.380721 15, 0x0, sum = 3
6420 09:31:34.383607 16, 0x0, sum = 4
6421 09:31:34.383690 best_step = 14
6422 09:31:34.383754
6423 09:31:34.383815 ==
6424 09:31:34.386892 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 09:31:34.393779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 09:31:34.393868 ==
6427 09:31:34.393934 RX Vref Scan: 1
6428 09:31:34.393995
6429 09:31:34.396807 RX Vref 0 -> 0, step: 1
6430 09:31:34.396889
6431 09:31:34.400118 RX Delay -359 -> 252, step: 8
6432 09:31:34.400199
6433 09:31:34.403333 Set Vref, RX VrefLevel [Byte0]: 61
6434 09:31:34.406976 [Byte1]: 59
6435 09:31:34.409912
6436 09:31:34.409993 Final RX Vref Byte 0 = 61 to rank0
6437 09:31:34.413187 Final RX Vref Byte 1 = 59 to rank0
6438 09:31:34.416778 Final RX Vref Byte 0 = 61 to rank1
6439 09:31:34.419636 Final RX Vref Byte 1 = 59 to rank1==
6440 09:31:34.423124 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 09:31:34.430005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 09:31:34.430086 ==
6443 09:31:34.430150 DQS Delay:
6444 09:31:34.433217 DQS0 = 48, DQS1 = 60
6445 09:31:34.433296 DQM Delay:
6446 09:31:34.433360 DQM0 = 11, DQM1 = 10
6447 09:31:34.436516 DQ Delay:
6448 09:31:34.439927 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6449 09:31:34.443348 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6450 09:31:34.443428 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6451 09:31:34.446058 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6452 09:31:34.449791
6453 09:31:34.449870
6454 09:31:34.456256 [DQSOSCAuto] RK0, (LSB)MR18= 0xc286, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6455 09:31:34.459736 CH0 RK0: MR19=C0C, MR18=C286
6456 09:31:34.466463 CH0_RK0: MR19=0xC0C, MR18=0xC286, DQSOSC=385, MR23=63, INC=398, DEC=265
6457 09:31:34.466571 ==
6458 09:31:34.469334 Dram Type= 6, Freq= 0, CH_0, rank 1
6459 09:31:34.472900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 09:31:34.472982 ==
6461 09:31:34.476373 [Gating] SW mode calibration
6462 09:31:34.482707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6463 09:31:34.489025 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6464 09:31:34.492466 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6465 09:31:34.495777 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6466 09:31:34.502584 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 09:31:34.505363 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 09:31:34.508947 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 09:31:34.515623 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 09:31:34.518701 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 09:31:34.522097 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 09:31:34.528928 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 09:31:34.532281 Total UI for P1: 0, mck2ui 16
6474 09:31:34.535330 best dqsien dly found for B0: ( 0, 14, 24)
6475 09:31:34.538601 Total UI for P1: 0, mck2ui 16
6476 09:31:34.541770 best dqsien dly found for B1: ( 0, 14, 24)
6477 09:31:34.545018 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6478 09:31:34.548487 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6479 09:31:34.548566
6480 09:31:34.551445 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6481 09:31:34.554899 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6482 09:31:34.558326 [Gating] SW calibration Done
6483 09:31:34.558406 ==
6484 09:31:34.561683 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 09:31:34.565052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 09:31:34.565133 ==
6487 09:31:34.568389 RX Vref Scan: 0
6488 09:31:34.568469
6489 09:31:34.571742 RX Vref 0 -> 0, step: 1
6490 09:31:34.571823
6491 09:31:34.571888 RX Delay -410 -> 252, step: 16
6492 09:31:34.578111 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6493 09:31:34.581785 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6494 09:31:34.584804 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6495 09:31:34.591512 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6496 09:31:34.594949 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6497 09:31:34.597772 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6498 09:31:34.601217 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6499 09:31:34.607605 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6500 09:31:34.611113 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6501 09:31:34.614660 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6502 09:31:34.617878 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6503 09:31:34.624328 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6504 09:31:34.627980 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6505 09:31:34.630929 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6506 09:31:34.634270 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6507 09:31:34.641190 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6508 09:31:34.641278 ==
6509 09:31:34.644153 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 09:31:34.647860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 09:31:34.647941 ==
6512 09:31:34.648004 DQS Delay:
6513 09:31:34.650917 DQS0 = 43, DQS1 = 59
6514 09:31:34.650997 DQM Delay:
6515 09:31:34.654183 DQM0 = 10, DQM1 = 14
6516 09:31:34.654264 DQ Delay:
6517 09:31:34.657495 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6518 09:31:34.661136 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6519 09:31:34.664164 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6520 09:31:34.667209 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6521 09:31:34.667289
6522 09:31:34.667351
6523 09:31:34.667409 ==
6524 09:31:34.670623 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 09:31:34.673771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 09:31:34.673853 ==
6527 09:31:34.673916
6528 09:31:34.677139
6529 09:31:34.677227 TX Vref Scan disable
6530 09:31:34.680287 == TX Byte 0 ==
6531 09:31:34.683793 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6532 09:31:34.687186 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6533 09:31:34.690694 == TX Byte 1 ==
6534 09:31:34.693714 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6535 09:31:34.696928 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6536 09:31:34.697002 ==
6537 09:31:34.700320 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 09:31:34.703884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 09:31:34.706778 ==
6540 09:31:34.706858
6541 09:31:34.706921
6542 09:31:34.706980 TX Vref Scan disable
6543 09:31:34.710402 == TX Byte 0 ==
6544 09:31:34.713615 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6545 09:31:34.717123 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6546 09:31:34.720400 == TX Byte 1 ==
6547 09:31:34.723617 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6548 09:31:34.727029 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6549 09:31:34.727109
6550 09:31:34.727173 [DATLAT]
6551 09:31:34.730304 Freq=400, CH0 RK1
6552 09:31:34.730384
6553 09:31:34.733244 DATLAT Default: 0xe
6554 09:31:34.733324 0, 0xFFFF, sum = 0
6555 09:31:34.736726 1, 0xFFFF, sum = 0
6556 09:31:34.736807 2, 0xFFFF, sum = 0
6557 09:31:34.739827 3, 0xFFFF, sum = 0
6558 09:31:34.739909 4, 0xFFFF, sum = 0
6559 09:31:34.743582 5, 0xFFFF, sum = 0
6560 09:31:34.743664 6, 0xFFFF, sum = 0
6561 09:31:34.746709 7, 0xFFFF, sum = 0
6562 09:31:34.746791 8, 0xFFFF, sum = 0
6563 09:31:34.749915 9, 0xFFFF, sum = 0
6564 09:31:34.749996 10, 0xFFFF, sum = 0
6565 09:31:34.753496 11, 0xFFFF, sum = 0
6566 09:31:34.753578 12, 0xFFFF, sum = 0
6567 09:31:34.756440 13, 0x0, sum = 1
6568 09:31:34.756523 14, 0x0, sum = 2
6569 09:31:34.759573 15, 0x0, sum = 3
6570 09:31:34.759654 16, 0x0, sum = 4
6571 09:31:34.763009 best_step = 14
6572 09:31:34.763088
6573 09:31:34.763152 ==
6574 09:31:34.766090 Dram Type= 6, Freq= 0, CH_0, rank 1
6575 09:31:34.769339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 09:31:34.769419 ==
6577 09:31:34.772913 RX Vref Scan: 0
6578 09:31:34.772997
6579 09:31:34.773061 RX Vref 0 -> 0, step: 1
6580 09:31:34.773121
6581 09:31:34.776450 RX Delay -359 -> 252, step: 8
6582 09:31:34.784538 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6583 09:31:34.787463 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6584 09:31:34.790901 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6585 09:31:34.797858 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6586 09:31:34.800741 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6587 09:31:34.804455 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6588 09:31:34.807340 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6589 09:31:34.814098 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6590 09:31:34.817578 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6591 09:31:34.820671 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6592 09:31:34.824251 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6593 09:31:34.830356 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6594 09:31:34.833860 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6595 09:31:34.836989 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6596 09:31:34.840545 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6597 09:31:34.847102 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6598 09:31:34.847182 ==
6599 09:31:34.850108 Dram Type= 6, Freq= 0, CH_0, rank 1
6600 09:31:34.853489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 09:31:34.853576 ==
6602 09:31:34.853642 DQS Delay:
6603 09:31:34.856989 DQS0 = 44, DQS1 = 60
6604 09:31:34.857067 DQM Delay:
6605 09:31:34.860045 DQM0 = 7, DQM1 = 14
6606 09:31:34.860124 DQ Delay:
6607 09:31:34.863316 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6608 09:31:34.866720 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6609 09:31:34.870255 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6610 09:31:34.873176 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6611 09:31:34.873258
6612 09:31:34.873321
6613 09:31:34.880366 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf3d, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6614 09:31:34.883769 CH0 RK1: MR19=C0C, MR18=AF3D
6615 09:31:34.889961 CH0_RK1: MR19=0xC0C, MR18=0xAF3D, DQSOSC=388, MR23=63, INC=392, DEC=261
6616 09:31:34.893338 [RxdqsGatingPostProcess] freq 400
6617 09:31:34.899901 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6618 09:31:34.903481 best DQS0 dly(2T, 0.5T) = (0, 10)
6619 09:31:34.906342 best DQS1 dly(2T, 0.5T) = (0, 10)
6620 09:31:34.909664 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6621 09:31:34.913002 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6622 09:31:34.913082 best DQS0 dly(2T, 0.5T) = (0, 10)
6623 09:31:34.916754 best DQS1 dly(2T, 0.5T) = (0, 10)
6624 09:31:34.919361 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6625 09:31:34.922926 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6626 09:31:34.926432 Pre-setting of DQS Precalculation
6627 09:31:34.932734 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6628 09:31:34.932886 ==
6629 09:31:34.936191 Dram Type= 6, Freq= 0, CH_1, rank 0
6630 09:31:34.939708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 09:31:34.939789 ==
6632 09:31:34.945943 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6633 09:31:34.952755 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6634 09:31:34.955723 [CA 0] Center 36 (8~64) winsize 57
6635 09:31:34.958926 [CA 1] Center 36 (8~64) winsize 57
6636 09:31:34.959029 [CA 2] Center 36 (8~64) winsize 57
6637 09:31:34.962598 [CA 3] Center 36 (8~64) winsize 57
6638 09:31:34.965644 [CA 4] Center 36 (8~64) winsize 57
6639 09:31:34.969304 [CA 5] Center 36 (8~64) winsize 57
6640 09:31:34.969385
6641 09:31:34.972386 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6642 09:31:34.975663
6643 09:31:34.979119 [CATrainingPosCal] consider 1 rank data
6644 09:31:34.979199 u2DelayCellTimex100 = 270/100 ps
6645 09:31:34.985363 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 09:31:34.988830 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 09:31:34.992527 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 09:31:34.995274 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 09:31:34.998547 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 09:31:35.002152 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 09:31:35.002269
6652 09:31:35.005134 CA PerBit enable=1, Macro0, CA PI delay=36
6653 09:31:35.005213
6654 09:31:35.008991 [CBTSetCACLKResult] CA Dly = 36
6655 09:31:35.011834 CS Dly: 1 (0~32)
6656 09:31:35.011914 ==
6657 09:31:35.015361 Dram Type= 6, Freq= 0, CH_1, rank 1
6658 09:31:35.018476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 09:31:35.018556 ==
6660 09:31:35.025089 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6661 09:31:35.031691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6662 09:31:35.034730 [CA 0] Center 36 (8~64) winsize 57
6663 09:31:35.034810 [CA 1] Center 36 (8~64) winsize 57
6664 09:31:35.038081 [CA 2] Center 36 (8~64) winsize 57
6665 09:31:35.041553 [CA 3] Center 36 (8~64) winsize 57
6666 09:31:35.044833 [CA 4] Center 36 (8~64) winsize 57
6667 09:31:35.047790 [CA 5] Center 36 (8~64) winsize 57
6668 09:31:35.047870
6669 09:31:35.051156 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6670 09:31:35.051237
6671 09:31:35.057867 [CATrainingPosCal] consider 2 rank data
6672 09:31:35.057948 u2DelayCellTimex100 = 270/100 ps
6673 09:31:35.064572 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 09:31:35.067519 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 09:31:35.070811 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 09:31:35.074094 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 09:31:35.077849 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 09:31:35.080723 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 09:31:35.080803
6680 09:31:35.084383 CA PerBit enable=1, Macro0, CA PI delay=36
6681 09:31:35.084463
6682 09:31:35.087323 [CBTSetCACLKResult] CA Dly = 36
6683 09:31:35.090801 CS Dly: 1 (0~32)
6684 09:31:35.090880
6685 09:31:35.094300 ----->DramcWriteLeveling(PI) begin...
6686 09:31:35.094381 ==
6687 09:31:35.097271 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 09:31:35.100696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 09:31:35.100776 ==
6690 09:31:35.104073 Write leveling (Byte 0): 40 => 8
6691 09:31:35.107605 Write leveling (Byte 1): 32 => 0
6692 09:31:35.110711 DramcWriteLeveling(PI) end<-----
6693 09:31:35.110790
6694 09:31:35.110853 ==
6695 09:31:35.113589 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 09:31:35.116972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 09:31:35.117051 ==
6698 09:31:35.120492 [Gating] SW mode calibration
6699 09:31:35.126758 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6700 09:31:35.133457 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6701 09:31:35.136786 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6702 09:31:35.143082 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6703 09:31:35.146616 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 09:31:35.149716 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 09:31:35.153530 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 09:31:35.159553 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 09:31:35.163180 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 09:31:35.166289 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 09:31:35.173568 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 09:31:35.176506 Total UI for P1: 0, mck2ui 16
6711 09:31:35.179777 best dqsien dly found for B0: ( 0, 14, 24)
6712 09:31:35.183051 Total UI for P1: 0, mck2ui 16
6713 09:31:35.186096 best dqsien dly found for B1: ( 0, 14, 24)
6714 09:31:35.189903 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6715 09:31:35.193074 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6716 09:31:35.193183
6717 09:31:35.196586 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6718 09:31:35.199880 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6719 09:31:35.203131 [Gating] SW calibration Done
6720 09:31:35.203211 ==
6721 09:31:35.206120 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 09:31:35.209401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 09:31:35.209481 ==
6724 09:31:35.213106 RX Vref Scan: 0
6725 09:31:35.213186
6726 09:31:35.216365 RX Vref 0 -> 0, step: 1
6727 09:31:35.216444
6728 09:31:35.216523 RX Delay -410 -> 252, step: 16
6729 09:31:35.222904 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6730 09:31:35.226148 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6731 09:31:35.229621 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6732 09:31:35.232821 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6733 09:31:35.239590 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6734 09:31:35.243239 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6735 09:31:35.245939 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6736 09:31:35.249099 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6737 09:31:35.255978 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6738 09:31:35.259357 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6739 09:31:35.262369 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6740 09:31:35.269207 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6741 09:31:35.272588 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6742 09:31:35.275717 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6743 09:31:35.278822 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6744 09:31:35.285499 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6745 09:31:35.285579 ==
6746 09:31:35.289163 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 09:31:35.292033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 09:31:35.292142 ==
6749 09:31:35.292226 DQS Delay:
6750 09:31:35.295736 DQS0 = 43, DQS1 = 51
6751 09:31:35.295816 DQM Delay:
6752 09:31:35.299138 DQM0 = 12, DQM1 = 14
6753 09:31:35.299217 DQ Delay:
6754 09:31:35.302030 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6755 09:31:35.305494 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6756 09:31:35.308818 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6757 09:31:35.311718 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6758 09:31:35.311797
6759 09:31:35.311860
6760 09:31:35.311921 ==
6761 09:31:35.315585 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 09:31:35.318563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 09:31:35.318643 ==
6764 09:31:35.318707
6765 09:31:35.321984
6766 09:31:35.322088 TX Vref Scan disable
6767 09:31:35.325580 == TX Byte 0 ==
6768 09:31:35.328475 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 09:31:35.331835 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 09:31:35.334855 == TX Byte 1 ==
6771 09:31:35.338418 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6772 09:31:35.341886 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6773 09:31:35.341965 ==
6774 09:31:35.344839 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 09:31:35.348176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 09:31:35.351571 ==
6777 09:31:35.351650
6778 09:31:35.351713
6779 09:31:35.351771 TX Vref Scan disable
6780 09:31:35.354621 == TX Byte 0 ==
6781 09:31:35.358362 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 09:31:35.361440 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 09:31:35.365003 == TX Byte 1 ==
6784 09:31:35.367918 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6785 09:31:35.371299 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6786 09:31:35.371379
6787 09:31:35.374993 [DATLAT]
6788 09:31:35.375072 Freq=400, CH1 RK0
6789 09:31:35.375135
6790 09:31:35.378114 DATLAT Default: 0xf
6791 09:31:35.378247 0, 0xFFFF, sum = 0
6792 09:31:35.381214 1, 0xFFFF, sum = 0
6793 09:31:35.381295 2, 0xFFFF, sum = 0
6794 09:31:35.384358 3, 0xFFFF, sum = 0
6795 09:31:35.384441 4, 0xFFFF, sum = 0
6796 09:31:35.387912 5, 0xFFFF, sum = 0
6797 09:31:35.387993 6, 0xFFFF, sum = 0
6798 09:31:35.391214 7, 0xFFFF, sum = 0
6799 09:31:35.391294 8, 0xFFFF, sum = 0
6800 09:31:35.394721 9, 0xFFFF, sum = 0
6801 09:31:35.398009 10, 0xFFFF, sum = 0
6802 09:31:35.398089 11, 0xFFFF, sum = 0
6803 09:31:35.401145 12, 0xFFFF, sum = 0
6804 09:31:35.401227 13, 0x0, sum = 1
6805 09:31:35.404488 14, 0x0, sum = 2
6806 09:31:35.404562 15, 0x0, sum = 3
6807 09:31:35.404624 16, 0x0, sum = 4
6808 09:31:35.407972 best_step = 14
6809 09:31:35.408051
6810 09:31:35.408113 ==
6811 09:31:35.411243 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 09:31:35.414112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 09:31:35.414227 ==
6814 09:31:35.417496 RX Vref Scan: 1
6815 09:31:35.417574
6816 09:31:35.421247 RX Vref 0 -> 0, step: 1
6817 09:31:35.421325
6818 09:31:35.421388 RX Delay -343 -> 252, step: 8
6819 09:31:35.421447
6820 09:31:35.424145 Set Vref, RX VrefLevel [Byte0]: 51
6821 09:31:35.427332 [Byte1]: 59
6822 09:31:35.432899
6823 09:31:35.433002 Final RX Vref Byte 0 = 51 to rank0
6824 09:31:35.436385 Final RX Vref Byte 1 = 59 to rank0
6825 09:31:35.439364 Final RX Vref Byte 0 = 51 to rank1
6826 09:31:35.442910 Final RX Vref Byte 1 = 59 to rank1==
6827 09:31:35.446024 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 09:31:35.452579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 09:31:35.452661 ==
6830 09:31:35.452726 DQS Delay:
6831 09:31:35.455556 DQS0 = 44, DQS1 = 56
6832 09:31:35.455636 DQM Delay:
6833 09:31:35.455700 DQM0 = 8, DQM1 = 12
6834 09:31:35.459069 DQ Delay:
6835 09:31:35.462622 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6836 09:31:35.465349 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =0
6837 09:31:35.465429 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6838 09:31:35.472363 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =24
6839 09:31:35.472477
6840 09:31:35.472558
6841 09:31:35.478499 [DQSOSCAuto] RK0, (LSB)MR18= 0x9a70, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6842 09:31:35.482250 CH1 RK0: MR19=C0C, MR18=9A70
6843 09:31:35.488789 CH1_RK0: MR19=0xC0C, MR18=0x9A70, DQSOSC=390, MR23=63, INC=388, DEC=258
6844 09:31:35.488870 ==
6845 09:31:35.491814 Dram Type= 6, Freq= 0, CH_1, rank 1
6846 09:31:35.495009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 09:31:35.495090 ==
6848 09:31:35.498348 [Gating] SW mode calibration
6849 09:31:35.504989 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6850 09:31:35.511739 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6851 09:31:35.515039 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6852 09:31:35.518571 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6853 09:31:35.524817 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 09:31:35.528669 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 09:31:35.532166 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 09:31:35.538060 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 09:31:35.541627 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 09:31:35.544755 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 09:31:35.551642 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 09:31:35.551723 Total UI for P1: 0, mck2ui 16
6861 09:31:35.558238 best dqsien dly found for B0: ( 0, 14, 24)
6862 09:31:35.558319 Total UI for P1: 0, mck2ui 16
6863 09:31:35.564510 best dqsien dly found for B1: ( 0, 14, 24)
6864 09:31:35.567893 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6865 09:31:35.571212 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6866 09:31:35.571292
6867 09:31:35.574624 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6868 09:31:35.578003 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6869 09:31:35.581329 [Gating] SW calibration Done
6870 09:31:35.581410 ==
6871 09:31:35.584752 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 09:31:35.587611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 09:31:35.587692 ==
6874 09:31:35.590727 RX Vref Scan: 0
6875 09:31:35.590807
6876 09:31:35.594399 RX Vref 0 -> 0, step: 1
6877 09:31:35.594480
6878 09:31:35.594544 RX Delay -410 -> 252, step: 16
6879 09:31:35.600920 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6880 09:31:35.604270 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6881 09:31:35.607483 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6882 09:31:35.614296 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6883 09:31:35.617488 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6884 09:31:35.620866 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6885 09:31:35.624197 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6886 09:31:35.630349 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6887 09:31:35.634074 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6888 09:31:35.636879 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6889 09:31:35.640506 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6890 09:31:35.646853 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6891 09:31:35.650175 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6892 09:31:35.653757 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6893 09:31:35.656836 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6894 09:31:35.663822 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6895 09:31:35.663903 ==
6896 09:31:35.667215 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 09:31:35.670096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 09:31:35.670218 ==
6899 09:31:35.670283 DQS Delay:
6900 09:31:35.673525 DQS0 = 43, DQS1 = 59
6901 09:31:35.673605 DQM Delay:
6902 09:31:35.676615 DQM0 = 12, DQM1 = 21
6903 09:31:35.676695 DQ Delay:
6904 09:31:35.679753 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6905 09:31:35.683210 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6906 09:31:35.686575 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6907 09:31:35.689760 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6908 09:31:35.689840
6909 09:31:35.689903
6910 09:31:35.689962 ==
6911 09:31:35.693198 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 09:31:35.696669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 09:31:35.696750 ==
6914 09:31:35.699429
6915 09:31:35.699508
6916 09:31:35.699571 TX Vref Scan disable
6917 09:31:35.702677 == TX Byte 0 ==
6918 09:31:35.706306 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6919 09:31:35.709286 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6920 09:31:35.712497 == TX Byte 1 ==
6921 09:31:35.716138 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6922 09:31:35.719483 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6923 09:31:35.719564 ==
6924 09:31:35.722905 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 09:31:35.725951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 09:31:35.729212 ==
6927 09:31:35.729292
6928 09:31:35.729355
6929 09:31:35.729413 TX Vref Scan disable
6930 09:31:35.732682 == TX Byte 0 ==
6931 09:31:35.735793 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6932 09:31:35.739445 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6933 09:31:35.742612 == TX Byte 1 ==
6934 09:31:35.745930 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6935 09:31:35.748869 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6936 09:31:35.748949
6937 09:31:35.752338 [DATLAT]
6938 09:31:35.752418 Freq=400, CH1 RK1
6939 09:31:35.752481
6940 09:31:35.755353 DATLAT Default: 0xe
6941 09:31:35.755433 0, 0xFFFF, sum = 0
6942 09:31:35.758749 1, 0xFFFF, sum = 0
6943 09:31:35.758831 2, 0xFFFF, sum = 0
6944 09:31:35.762307 3, 0xFFFF, sum = 0
6945 09:31:35.762387 4, 0xFFFF, sum = 0
6946 09:31:35.765457 5, 0xFFFF, sum = 0
6947 09:31:35.765537 6, 0xFFFF, sum = 0
6948 09:31:35.768614 7, 0xFFFF, sum = 0
6949 09:31:35.768695 8, 0xFFFF, sum = 0
6950 09:31:35.771936 9, 0xFFFF, sum = 0
6951 09:31:35.775430 10, 0xFFFF, sum = 0
6952 09:31:35.775511 11, 0xFFFF, sum = 0
6953 09:31:35.778686 12, 0xFFFF, sum = 0
6954 09:31:35.778768 13, 0x0, sum = 1
6955 09:31:35.782037 14, 0x0, sum = 2
6956 09:31:35.782145 15, 0x0, sum = 3
6957 09:31:35.782265 16, 0x0, sum = 4
6958 09:31:35.785372 best_step = 14
6959 09:31:35.785451
6960 09:31:35.785515 ==
6961 09:31:35.788608 Dram Type= 6, Freq= 0, CH_1, rank 1
6962 09:31:35.791973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6963 09:31:35.792057 ==
6964 09:31:35.794990 RX Vref Scan: 0
6965 09:31:35.795070
6966 09:31:35.798279 RX Vref 0 -> 0, step: 1
6967 09:31:35.798360
6968 09:31:35.798423 RX Delay -359 -> 252, step: 8
6969 09:31:35.807306 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6970 09:31:35.810134 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6971 09:31:35.813775 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6972 09:31:35.820206 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
6973 09:31:35.823250 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6974 09:31:35.826941 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6975 09:31:35.830523 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
6976 09:31:35.837083 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
6977 09:31:35.839976 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
6978 09:31:35.843304 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6979 09:31:35.846964 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6980 09:31:35.853369 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6981 09:31:35.856538 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6982 09:31:35.859558 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6983 09:31:35.862914 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6984 09:31:35.869885 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
6985 09:31:35.869966 ==
6986 09:31:35.873400 Dram Type= 6, Freq= 0, CH_1, rank 1
6987 09:31:35.876147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6988 09:31:35.876254 ==
6989 09:31:35.876346 DQS Delay:
6990 09:31:35.879670 DQS0 = 44, DQS1 = 60
6991 09:31:35.879750 DQM Delay:
6992 09:31:35.883111 DQM0 = 11, DQM1 = 14
6993 09:31:35.883191 DQ Delay:
6994 09:31:35.886141 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6995 09:31:35.889290 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6996 09:31:35.892838 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6997 09:31:35.895701 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =28
6998 09:31:35.895781
6999 09:31:35.895844
7000 09:31:35.905907 [DQSOSCAuto] RK1, (LSB)MR18= 0x6655, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 396 ps
7001 09:31:35.905994 CH1 RK1: MR19=C0C, MR18=6655
7002 09:31:35.912332 CH1_RK1: MR19=0xC0C, MR18=0x6655, DQSOSC=396, MR23=63, INC=376, DEC=251
7003 09:31:35.916083 [RxdqsGatingPostProcess] freq 400
7004 09:31:35.922387 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7005 09:31:35.925684 best DQS0 dly(2T, 0.5T) = (0, 10)
7006 09:31:35.929078 best DQS1 dly(2T, 0.5T) = (0, 10)
7007 09:31:35.932120 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7008 09:31:35.935778 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7009 09:31:35.938961 best DQS0 dly(2T, 0.5T) = (0, 10)
7010 09:31:35.939248 best DQS1 dly(2T, 0.5T) = (0, 10)
7011 09:31:35.942382 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7012 09:31:35.945367 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7013 09:31:35.948537 Pre-setting of DQS Precalculation
7014 09:31:35.955277 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7015 09:31:35.961750 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7016 09:31:35.968173 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7017 09:31:35.968296
7018 09:31:35.968365
7019 09:31:35.971794 [Calibration Summary] 800 Mbps
7020 09:31:35.974937 CH 0, Rank 0
7021 09:31:35.975036 SW Impedance : PASS
7022 09:31:35.978287 DUTY Scan : NO K
7023 09:31:35.981442 ZQ Calibration : PASS
7024 09:31:35.981570 Jitter Meter : NO K
7025 09:31:35.985242 CBT Training : PASS
7026 09:31:35.988132 Write leveling : PASS
7027 09:31:35.988228 RX DQS gating : PASS
7028 09:31:35.991169 RX DQ/DQS(RDDQC) : PASS
7029 09:31:35.991278 TX DQ/DQS : PASS
7030 09:31:35.994486 RX DATLAT : PASS
7031 09:31:35.998115 RX DQ/DQS(Engine): PASS
7032 09:31:35.998235 TX OE : NO K
7033 09:31:36.001472 All Pass.
7034 09:31:36.001561
7035 09:31:36.001626 CH 0, Rank 1
7036 09:31:36.004421 SW Impedance : PASS
7037 09:31:36.004504 DUTY Scan : NO K
7038 09:31:36.007701 ZQ Calibration : PASS
7039 09:31:36.011464 Jitter Meter : NO K
7040 09:31:36.011553 CBT Training : PASS
7041 09:31:36.015086 Write leveling : NO K
7042 09:31:36.017996 RX DQS gating : PASS
7043 09:31:36.018083 RX DQ/DQS(RDDQC) : PASS
7044 09:31:36.021003 TX DQ/DQS : PASS
7045 09:31:36.024730 RX DATLAT : PASS
7046 09:31:36.024824 RX DQ/DQS(Engine): PASS
7047 09:31:36.027953 TX OE : NO K
7048 09:31:36.028036 All Pass.
7049 09:31:36.028101
7050 09:31:36.031114 CH 1, Rank 0
7051 09:31:36.031196 SW Impedance : PASS
7052 09:31:36.034041 DUTY Scan : NO K
7053 09:31:36.037388 ZQ Calibration : PASS
7054 09:31:36.037472 Jitter Meter : NO K
7055 09:31:36.041046 CBT Training : PASS
7056 09:31:36.044516 Write leveling : PASS
7057 09:31:36.044603 RX DQS gating : PASS
7058 09:31:36.047497 RX DQ/DQS(RDDQC) : PASS
7059 09:31:36.050803 TX DQ/DQS : PASS
7060 09:31:36.050893 RX DATLAT : PASS
7061 09:31:36.054421 RX DQ/DQS(Engine): PASS
7062 09:31:36.057830 TX OE : NO K
7063 09:31:36.057919 All Pass.
7064 09:31:36.057983
7065 09:31:36.058043 CH 1, Rank 1
7066 09:31:36.060772 SW Impedance : PASS
7067 09:31:36.063821 DUTY Scan : NO K
7068 09:31:36.063904 ZQ Calibration : PASS
7069 09:31:36.067316 Jitter Meter : NO K
7070 09:31:36.070769 CBT Training : PASS
7071 09:31:36.070855 Write leveling : NO K
7072 09:31:36.074133 RX DQS gating : PASS
7073 09:31:36.074239 RX DQ/DQS(RDDQC) : PASS
7074 09:31:36.077176 TX DQ/DQS : PASS
7075 09:31:36.080455 RX DATLAT : PASS
7076 09:31:36.080542 RX DQ/DQS(Engine): PASS
7077 09:31:36.083575 TX OE : NO K
7078 09:31:36.083658 All Pass.
7079 09:31:36.083722
7080 09:31:36.087046 DramC Write-DBI off
7081 09:31:36.090172 PER_BANK_REFRESH: Hybrid Mode
7082 09:31:36.090257 TX_TRACKING: ON
7083 09:31:36.100158 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7084 09:31:36.103287 [FAST_K] Save calibration result to emmc
7085 09:31:36.106710 dramc_set_vcore_voltage set vcore to 725000
7086 09:31:36.109994 Read voltage for 1600, 0
7087 09:31:36.110089 Vio18 = 0
7088 09:31:36.113065 Vcore = 725000
7089 09:31:36.113152 Vdram = 0
7090 09:31:36.113217 Vddq = 0
7091 09:31:36.113277 Vmddr = 0
7092 09:31:36.119553 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7093 09:31:36.126283 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7094 09:31:36.126404 MEM_TYPE=3, freq_sel=13
7095 09:31:36.129627 sv_algorithm_assistance_LP4_3733
7096 09:31:36.136149 ============ PULL DRAM RESETB DOWN ============
7097 09:31:36.139621 ========== PULL DRAM RESETB DOWN end =========
7098 09:31:36.142920 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7099 09:31:36.145722 ===================================
7100 09:31:36.149047 LPDDR4 DRAM CONFIGURATION
7101 09:31:36.152597 ===================================
7102 09:31:36.156021 EX_ROW_EN[0] = 0x0
7103 09:31:36.156110 EX_ROW_EN[1] = 0x0
7104 09:31:36.158970 LP4Y_EN = 0x0
7105 09:31:36.159083 WORK_FSP = 0x1
7106 09:31:36.162560 WL = 0x5
7107 09:31:36.162641 RL = 0x5
7108 09:31:36.165926 BL = 0x2
7109 09:31:36.166006 RPST = 0x0
7110 09:31:36.168841 RD_PRE = 0x0
7111 09:31:36.168922 WR_PRE = 0x1
7112 09:31:36.172335 WR_PST = 0x1
7113 09:31:36.172416 DBI_WR = 0x0
7114 09:31:36.175725 DBI_RD = 0x0
7115 09:31:36.175806 OTF = 0x1
7116 09:31:36.179179 ===================================
7117 09:31:36.181897 ===================================
7118 09:31:36.185289 ANA top config
7119 09:31:36.188632 ===================================
7120 09:31:36.191818 DLL_ASYNC_EN = 0
7121 09:31:36.191911 ALL_SLAVE_EN = 0
7122 09:31:36.195342 NEW_RANK_MODE = 1
7123 09:31:36.198754 DLL_IDLE_MODE = 1
7124 09:31:36.201844 LP45_APHY_COMB_EN = 1
7125 09:31:36.205098 TX_ODT_DIS = 0
7126 09:31:36.205189 NEW_8X_MODE = 1
7127 09:31:36.208688 ===================================
7128 09:31:36.211934 ===================================
7129 09:31:36.214764 data_rate = 3200
7130 09:31:36.218560 CKR = 1
7131 09:31:36.221932 DQ_P2S_RATIO = 8
7132 09:31:36.224890 ===================================
7133 09:31:36.228059 CA_P2S_RATIO = 8
7134 09:31:36.231355 DQ_CA_OPEN = 0
7135 09:31:36.231501 DQ_SEMI_OPEN = 0
7136 09:31:36.234446 CA_SEMI_OPEN = 0
7137 09:31:36.238186 CA_FULL_RATE = 0
7138 09:31:36.241165 DQ_CKDIV4_EN = 0
7139 09:31:36.244663 CA_CKDIV4_EN = 0
7140 09:31:36.247998 CA_PREDIV_EN = 0
7141 09:31:36.251249 PH8_DLY = 12
7142 09:31:36.251353 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7143 09:31:36.254425 DQ_AAMCK_DIV = 4
7144 09:31:36.257741 CA_AAMCK_DIV = 4
7145 09:31:36.260782 CA_ADMCK_DIV = 4
7146 09:31:36.264266 DQ_TRACK_CA_EN = 0
7147 09:31:36.267761 CA_PICK = 1600
7148 09:31:36.270752 CA_MCKIO = 1600
7149 09:31:36.270844 MCKIO_SEMI = 0
7150 09:31:36.273744 PLL_FREQ = 3068
7151 09:31:36.277349 DQ_UI_PI_RATIO = 32
7152 09:31:36.280461 CA_UI_PI_RATIO = 0
7153 09:31:36.283669 ===================================
7154 09:31:36.287105 ===================================
7155 09:31:36.290582 memory_type:LPDDR4
7156 09:31:36.290677 GP_NUM : 10
7157 09:31:36.294010 SRAM_EN : 1
7158 09:31:36.296849 MD32_EN : 0
7159 09:31:36.300392 ===================================
7160 09:31:36.300474 [ANA_INIT] >>>>>>>>>>>>>>
7161 09:31:36.303598 <<<<<< [CONFIGURE PHASE]: ANA_TX
7162 09:31:36.307144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7163 09:31:36.310305 ===================================
7164 09:31:36.313924 data_rate = 3200,PCW = 0X7600
7165 09:31:36.316619 ===================================
7166 09:31:36.319857 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7167 09:31:36.326477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7168 09:31:36.329877 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7169 09:31:36.336652 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7170 09:31:36.339824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7171 09:31:36.343202 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7172 09:31:36.346100 [ANA_INIT] flow start
7173 09:31:36.346218 [ANA_INIT] PLL >>>>>>>>
7174 09:31:36.349684 [ANA_INIT] PLL <<<<<<<<
7175 09:31:36.352893 [ANA_INIT] MIDPI >>>>>>>>
7176 09:31:36.352991 [ANA_INIT] MIDPI <<<<<<<<
7177 09:31:36.356711 [ANA_INIT] DLL >>>>>>>>
7178 09:31:36.359752 [ANA_INIT] DLL <<<<<<<<
7179 09:31:36.359846 [ANA_INIT] flow end
7180 09:31:36.366442 ============ LP4 DIFF to SE enter ============
7181 09:31:36.369481 ============ LP4 DIFF to SE exit ============
7182 09:31:36.372761 [ANA_INIT] <<<<<<<<<<<<<
7183 09:31:36.376453 [Flow] Enable top DCM control >>>>>
7184 09:31:36.376560 [Flow] Enable top DCM control <<<<<
7185 09:31:36.379698 Enable DLL master slave shuffle
7186 09:31:36.385942 ==============================================================
7187 09:31:36.389426 Gating Mode config
7188 09:31:36.392435 ==============================================================
7189 09:31:36.395681 Config description:
7190 09:31:36.405649 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7191 09:31:36.412476 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7192 09:31:36.415651 SELPH_MODE 0: By rank 1: By Phase
7193 09:31:36.422447 ==============================================================
7194 09:31:36.425706 GAT_TRACK_EN = 1
7195 09:31:36.429505 RX_GATING_MODE = 2
7196 09:31:36.432379 RX_GATING_TRACK_MODE = 2
7197 09:31:36.435779 SELPH_MODE = 1
7198 09:31:36.438764 PICG_EARLY_EN = 1
7199 09:31:36.438855 VALID_LAT_VALUE = 1
7200 09:31:36.445671 ==============================================================
7201 09:31:36.449003 Enter into Gating configuration >>>>
7202 09:31:36.452365 Exit from Gating configuration <<<<
7203 09:31:36.455048 Enter into DVFS_PRE_config >>>>>
7204 09:31:36.465621 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7205 09:31:36.468406 Exit from DVFS_PRE_config <<<<<
7206 09:31:36.471726 Enter into PICG configuration >>>>
7207 09:31:36.475245 Exit from PICG configuration <<<<
7208 09:31:36.478285 [RX_INPUT] configuration >>>>>
7209 09:31:36.481881 [RX_INPUT] configuration <<<<<
7210 09:31:36.485068 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7211 09:31:36.491809 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7212 09:31:36.498148 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7213 09:31:36.505090 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7214 09:31:36.511540 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7215 09:31:36.518367 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7216 09:31:36.521933 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7217 09:31:36.524697 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7218 09:31:36.528188 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7219 09:31:36.534795 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7220 09:31:36.537983 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7221 09:31:36.541378 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7222 09:31:36.545032 ===================================
7223 09:31:36.547694 LPDDR4 DRAM CONFIGURATION
7224 09:31:36.551138 ===================================
7225 09:31:36.551227 EX_ROW_EN[0] = 0x0
7226 09:31:36.554441 EX_ROW_EN[1] = 0x0
7227 09:31:36.557885 LP4Y_EN = 0x0
7228 09:31:36.557980 WORK_FSP = 0x1
7229 09:31:36.561019 WL = 0x5
7230 09:31:36.561109 RL = 0x5
7231 09:31:36.564403 BL = 0x2
7232 09:31:36.564492 RPST = 0x0
7233 09:31:36.567766 RD_PRE = 0x0
7234 09:31:36.567860 WR_PRE = 0x1
7235 09:31:36.570876 WR_PST = 0x1
7236 09:31:36.570964 DBI_WR = 0x0
7237 09:31:36.574145 DBI_RD = 0x0
7238 09:31:36.574284 OTF = 0x1
7239 09:31:36.577676 ===================================
7240 09:31:36.580645 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7241 09:31:36.587116 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7242 09:31:36.590626 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7243 09:31:36.593830 ===================================
7244 09:31:36.597317 LPDDR4 DRAM CONFIGURATION
7245 09:31:36.600604 ===================================
7246 09:31:36.600708 EX_ROW_EN[0] = 0x10
7247 09:31:36.603736 EX_ROW_EN[1] = 0x0
7248 09:31:36.607407 LP4Y_EN = 0x0
7249 09:31:36.607507 WORK_FSP = 0x1
7250 09:31:36.610405 WL = 0x5
7251 09:31:36.610514 RL = 0x5
7252 09:31:36.613695 BL = 0x2
7253 09:31:36.613787 RPST = 0x0
7254 09:31:36.616876 RD_PRE = 0x0
7255 09:31:36.616968 WR_PRE = 0x1
7256 09:31:36.620139 WR_PST = 0x1
7257 09:31:36.620228 DBI_WR = 0x0
7258 09:31:36.623457 DBI_RD = 0x0
7259 09:31:36.623546 OTF = 0x1
7260 09:31:36.627089 ===================================
7261 09:31:36.633436 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7262 09:31:36.633557 ==
7263 09:31:36.637161 Dram Type= 6, Freq= 0, CH_0, rank 0
7264 09:31:36.643470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7265 09:31:36.643589 ==
7266 09:31:36.643659 [Duty_Offset_Calibration]
7267 09:31:36.646444 B0:1 B1:-1 CA:0
7268 09:31:36.646528
7269 09:31:36.650110 [DutyScan_Calibration_Flow] k_type=0
7270 09:31:36.659207
7271 09:31:36.659343 ==CLK 0==
7272 09:31:36.662376 Final CLK duty delay cell = 0
7273 09:31:36.665921 [0] MAX Duty = 5124%(X100), DQS PI = 22
7274 09:31:36.669360 [0] MIN Duty = 4907%(X100), DQS PI = 4
7275 09:31:36.672490 [0] AVG Duty = 5015%(X100)
7276 09:31:36.672589
7277 09:31:36.675726 CH0 CLK Duty spec in!! Max-Min= 217%
7278 09:31:36.679160 [DutyScan_Calibration_Flow] ====Done====
7279 09:31:36.679258
7280 09:31:36.682545 [DutyScan_Calibration_Flow] k_type=1
7281 09:31:36.698304
7282 09:31:36.698452 ==DQS 0 ==
7283 09:31:36.701566 Final DQS duty delay cell = -4
7284 09:31:36.704944 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7285 09:31:36.708204 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7286 09:31:36.711699 [-4] AVG Duty = 4906%(X100)
7287 09:31:36.711783
7288 09:31:36.711846 ==DQS 1 ==
7289 09:31:36.714913 Final DQS duty delay cell = 0
7290 09:31:36.717900 [0] MAX Duty = 5156%(X100), DQS PI = 2
7291 09:31:36.721364 [0] MIN Duty = 5031%(X100), DQS PI = 18
7292 09:31:36.724944 [0] AVG Duty = 5093%(X100)
7293 09:31:36.725026
7294 09:31:36.727770 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7295 09:31:36.727852
7296 09:31:36.731313 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7297 09:31:36.734401 [DutyScan_Calibration_Flow] ====Done====
7298 09:31:36.734481
7299 09:31:36.737654 [DutyScan_Calibration_Flow] k_type=3
7300 09:31:36.755981
7301 09:31:36.756098 ==DQM 0 ==
7302 09:31:36.759161 Final DQM duty delay cell = 0
7303 09:31:36.762591 [0] MAX Duty = 5124%(X100), DQS PI = 20
7304 09:31:36.765460 [0] MIN Duty = 4907%(X100), DQS PI = 8
7305 09:31:36.768706 [0] AVG Duty = 5015%(X100)
7306 09:31:36.768788
7307 09:31:36.768866 ==DQM 1 ==
7308 09:31:36.772194 Final DQM duty delay cell = 0
7309 09:31:36.775721 [0] MAX Duty = 5000%(X100), DQS PI = 6
7310 09:31:36.778941 [0] MIN Duty = 4782%(X100), DQS PI = 20
7311 09:31:36.782547 [0] AVG Duty = 4891%(X100)
7312 09:31:36.782627
7313 09:31:36.785665 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7314 09:31:36.785744
7315 09:31:36.788664 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7316 09:31:36.791949 [DutyScan_Calibration_Flow] ====Done====
7317 09:31:36.792028
7318 09:31:36.795166 [DutyScan_Calibration_Flow] k_type=2
7319 09:31:36.812367
7320 09:31:36.812455 ==DQ 0 ==
7321 09:31:36.815242 Final DQ duty delay cell = -4
7322 09:31:36.818548 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7323 09:31:36.821872 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7324 09:31:36.825248 [-4] AVG Duty = 4953%(X100)
7325 09:31:36.825330
7326 09:31:36.825392 ==DQ 1 ==
7327 09:31:36.828550 Final DQ duty delay cell = 0
7328 09:31:36.831996 [0] MAX Duty = 5125%(X100), DQS PI = 4
7329 09:31:36.835237 [0] MIN Duty = 5000%(X100), DQS PI = 36
7330 09:31:36.838538 [0] AVG Duty = 5062%(X100)
7331 09:31:36.838630
7332 09:31:36.841749 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7333 09:31:36.841837
7334 09:31:36.845230 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7335 09:31:36.848122 [DutyScan_Calibration_Flow] ====Done====
7336 09:31:36.848206 ==
7337 09:31:36.851842 Dram Type= 6, Freq= 0, CH_1, rank 0
7338 09:31:36.855056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7339 09:31:36.855149 ==
7340 09:31:36.858028 [Duty_Offset_Calibration]
7341 09:31:36.858112 B0:-1 B1:1 CA:2
7342 09:31:36.861654
7343 09:31:36.861738 [DutyScan_Calibration_Flow] k_type=0
7344 09:31:36.872780
7345 09:31:36.872913 ==CLK 0==
7346 09:31:36.875879 Final CLK duty delay cell = 0
7347 09:31:36.879165 [0] MAX Duty = 5156%(X100), DQS PI = 22
7348 09:31:36.882389 [0] MIN Duty = 4969%(X100), DQS PI = 0
7349 09:31:36.885805 [0] AVG Duty = 5062%(X100)
7350 09:31:36.885932
7351 09:31:36.889258 CH1 CLK Duty spec in!! Max-Min= 187%
7352 09:31:36.892549 [DutyScan_Calibration_Flow] ====Done====
7353 09:31:36.892636
7354 09:31:36.895462 [DutyScan_Calibration_Flow] k_type=1
7355 09:31:36.912293
7356 09:31:36.912435 ==DQS 0 ==
7357 09:31:36.915556 Final DQS duty delay cell = 0
7358 09:31:36.919037 [0] MAX Duty = 5156%(X100), DQS PI = 20
7359 09:31:36.922502 [0] MIN Duty = 4907%(X100), DQS PI = 8
7360 09:31:36.925900 [0] AVG Duty = 5031%(X100)
7361 09:31:36.925980
7362 09:31:36.926043 ==DQS 1 ==
7363 09:31:36.928956 Final DQS duty delay cell = 0
7364 09:31:36.932327 [0] MAX Duty = 5093%(X100), DQS PI = 24
7365 09:31:36.935543 [0] MIN Duty = 4969%(X100), DQS PI = 54
7366 09:31:36.939065 [0] AVG Duty = 5031%(X100)
7367 09:31:36.939147
7368 09:31:36.942200 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7369 09:31:36.942293
7370 09:31:36.945200 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7371 09:31:36.948934 [DutyScan_Calibration_Flow] ====Done====
7372 09:31:36.949016
7373 09:31:36.951904 [DutyScan_Calibration_Flow] k_type=3
7374 09:31:36.969141
7375 09:31:36.969254 ==DQM 0 ==
7376 09:31:36.972669 Final DQM duty delay cell = 0
7377 09:31:36.975921 [0] MAX Duty = 5218%(X100), DQS PI = 18
7378 09:31:36.979344 [0] MIN Duty = 5031%(X100), DQS PI = 8
7379 09:31:36.982155 [0] AVG Duty = 5124%(X100)
7380 09:31:36.982278
7381 09:31:36.982342 ==DQM 1 ==
7382 09:31:36.985694 Final DQM duty delay cell = 0
7383 09:31:36.989041 [0] MAX Duty = 5156%(X100), DQS PI = 6
7384 09:31:36.992075 [0] MIN Duty = 4938%(X100), DQS PI = 34
7385 09:31:36.995441 [0] AVG Duty = 5047%(X100)
7386 09:31:36.995525
7387 09:31:36.998920 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7388 09:31:36.999002
7389 09:31:37.002310 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7390 09:31:37.005546 [DutyScan_Calibration_Flow] ====Done====
7391 09:31:37.005627
7392 09:31:37.008304 [DutyScan_Calibration_Flow] k_type=2
7393 09:31:37.025933
7394 09:31:37.026023 ==DQ 0 ==
7395 09:31:37.029343 Final DQ duty delay cell = 0
7396 09:31:37.032739 [0] MAX Duty = 5156%(X100), DQS PI = 28
7397 09:31:37.036308 [0] MIN Duty = 4906%(X100), DQS PI = 10
7398 09:31:37.036389 [0] AVG Duty = 5031%(X100)
7399 09:31:37.039308
7400 09:31:37.039388 ==DQ 1 ==
7401 09:31:37.042312 Final DQ duty delay cell = 0
7402 09:31:37.046143 [0] MAX Duty = 5156%(X100), DQS PI = 10
7403 09:31:37.049144 [0] MIN Duty = 4969%(X100), DQS PI = 56
7404 09:31:37.049227 [0] AVG Duty = 5062%(X100)
7405 09:31:37.052458
7406 09:31:37.055728 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7407 09:31:37.055808
7408 09:31:37.059315 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7409 09:31:37.062503 [DutyScan_Calibration_Flow] ====Done====
7410 09:31:37.065682 nWR fixed to 30
7411 09:31:37.068654 [ModeRegInit_LP4] CH0 RK0
7412 09:31:37.068734 [ModeRegInit_LP4] CH0 RK1
7413 09:31:37.072450 [ModeRegInit_LP4] CH1 RK0
7414 09:31:37.075341 [ModeRegInit_LP4] CH1 RK1
7415 09:31:37.075423 match AC timing 5
7416 09:31:37.081973 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7417 09:31:37.085610 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7418 09:31:37.088887 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7419 09:31:37.095429 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7420 09:31:37.098458 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7421 09:31:37.098540 [MiockJmeterHQA]
7422 09:31:37.098603
7423 09:31:37.101798 [DramcMiockJmeter] u1RxGatingPI = 0
7424 09:31:37.104988 0 : 4253, 4027
7425 09:31:37.105071 4 : 4363, 4138
7426 09:31:37.108943 8 : 4253, 4026
7427 09:31:37.109039 12 : 4363, 4138
7428 09:31:37.111765 16 : 4365, 4139
7429 09:31:37.111847 20 : 4252, 4027
7430 09:31:37.111911 24 : 4250, 4027
7431 09:31:37.114814 28 : 4252, 4027
7432 09:31:37.114896 32 : 4362, 4137
7433 09:31:37.118028 36 : 4253, 4026
7434 09:31:37.118135 40 : 4363, 4138
7435 09:31:37.121383 44 : 4255, 4029
7436 09:31:37.121464 48 : 4252, 4027
7437 09:31:37.124769 52 : 4252, 4027
7438 09:31:37.124850 56 : 4253, 4026
7439 09:31:37.124915 60 : 4363, 4138
7440 09:31:37.128061 64 : 4249, 4027
7441 09:31:37.128142 68 : 4361, 4137
7442 09:31:37.131668 72 : 4249, 4027
7443 09:31:37.131749 76 : 4250, 4027
7444 09:31:37.134607 80 : 4250, 4027
7445 09:31:37.134687 84 : 4361, 4137
7446 09:31:37.138124 88 : 4250, 4026
7447 09:31:37.138254 92 : 4360, 527
7448 09:31:37.138320 96 : 4250, 0
7449 09:31:37.141448 100 : 4253, 0
7450 09:31:37.141555 104 : 4250, 0
7451 09:31:37.144497 108 : 4250, 0
7452 09:31:37.144589 112 : 4250, 0
7453 09:31:37.144665 116 : 4253, 0
7454 09:31:37.147851 120 : 4249, 0
7455 09:31:37.147931 124 : 4252, 0
7456 09:31:37.151058 128 : 4253, 0
7457 09:31:37.151138 132 : 4249, 0
7458 09:31:37.151202 136 : 4252, 0
7459 09:31:37.154286 140 : 4363, 0
7460 09:31:37.154367 144 : 4360, 0
7461 09:31:37.157717 148 : 4361, 0
7462 09:31:37.157797 152 : 4252, 0
7463 09:31:37.157861 156 : 4253, 0
7464 09:31:37.160999 160 : 4249, 0
7465 09:31:37.161080 164 : 4252, 0
7466 09:31:37.161145 168 : 4253, 0
7467 09:31:37.164125 172 : 4249, 0
7468 09:31:37.164206 176 : 4252, 0
7469 09:31:37.167585 180 : 4255, 0
7470 09:31:37.167665 184 : 4249, 0
7471 09:31:37.167729 188 : 4252, 0
7472 09:31:37.170712 192 : 4361, 0
7473 09:31:37.170793 196 : 4360, 0
7474 09:31:37.174435 200 : 4363, 0
7475 09:31:37.174517 204 : 4250, 0
7476 09:31:37.174594 208 : 4250, 0
7477 09:31:37.177663 212 : 4250, 0
7478 09:31:37.177744 216 : 4252, 0
7479 09:31:37.180991 220 : 4250, 0
7480 09:31:37.181099 224 : 4249, 56
7481 09:31:37.181193 228 : 4252, 3418
7482 09:31:37.184058 232 : 4252, 4029
7483 09:31:37.184139 236 : 4250, 4026
7484 09:31:37.187510 240 : 4250, 4027
7485 09:31:37.187591 244 : 4249, 4027
7486 09:31:37.190323 248 : 4250, 4026
7487 09:31:37.190405 252 : 4250, 4027
7488 09:31:37.193830 256 : 4360, 4138
7489 09:31:37.193910 260 : 4360, 4137
7490 09:31:37.197073 264 : 4248, 4024
7491 09:31:37.197185 268 : 4361, 4137
7492 09:31:37.200312 272 : 4360, 4138
7493 09:31:37.200394 276 : 4250, 4027
7494 09:31:37.203615 280 : 4249, 4027
7495 09:31:37.203699 284 : 4250, 4027
7496 09:31:37.206765 288 : 4250, 4027
7497 09:31:37.206848 292 : 4249, 4027
7498 09:31:37.206917 296 : 4250, 4026
7499 09:31:37.210285 300 : 4250, 4026
7500 09:31:37.210367 304 : 4250, 4027
7501 09:31:37.213250 308 : 4360, 4138
7502 09:31:37.213331 312 : 4361, 4137
7503 09:31:37.216777 316 : 4250, 4026
7504 09:31:37.216858 320 : 4361, 4137
7505 09:31:37.220170 324 : 4360, 4138
7506 09:31:37.220253 328 : 4250, 4027
7507 09:31:37.223481 332 : 4250, 4027
7508 09:31:37.223563 336 : 4250, 3915
7509 09:31:37.226868 340 : 4250, 1856
7510 09:31:37.226958
7511 09:31:37.227029 MIOCK jitter meter ch=0
7512 09:31:37.227090
7513 09:31:37.230258 1T = (340-92) = 248 dly cells
7514 09:31:37.236525 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7515 09:31:37.236615 ==
7516 09:31:37.239957 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 09:31:37.243453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 09:31:37.243536 ==
7519 09:31:37.250386 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7520 09:31:37.253106 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7521 09:31:37.256704 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7522 09:31:37.263411 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7523 09:31:37.273067 [CA 0] Center 43 (13~74) winsize 62
7524 09:31:37.276705 [CA 1] Center 43 (13~73) winsize 61
7525 09:31:37.279990 [CA 2] Center 38 (9~68) winsize 60
7526 09:31:37.283193 [CA 3] Center 38 (9~68) winsize 60
7527 09:31:37.286411 [CA 4] Center 36 (7~66) winsize 60
7528 09:31:37.290140 [CA 5] Center 36 (7~65) winsize 59
7529 09:31:37.290265
7530 09:31:37.292748 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7531 09:31:37.292829
7532 09:31:37.296253 [CATrainingPosCal] consider 1 rank data
7533 09:31:37.299607 u2DelayCellTimex100 = 262/100 ps
7534 09:31:37.306301 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7535 09:31:37.309241 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7536 09:31:37.312636 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7537 09:31:37.315771 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7538 09:31:37.319047 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7539 09:31:37.322689 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7540 09:31:37.322799
7541 09:31:37.325778 CA PerBit enable=1, Macro0, CA PI delay=36
7542 09:31:37.325859
7543 09:31:37.329381 [CBTSetCACLKResult] CA Dly = 36
7544 09:31:37.332334 CS Dly: 12 (0~43)
7545 09:31:37.335722 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7546 09:31:37.338831 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7547 09:31:37.338919 ==
7548 09:31:37.342185 Dram Type= 6, Freq= 0, CH_0, rank 1
7549 09:31:37.348970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 09:31:37.349104 ==
7551 09:31:37.352552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7552 09:31:37.358753 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7553 09:31:37.361984 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7554 09:31:37.368574 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7555 09:31:37.376326 [CA 0] Center 43 (13~73) winsize 61
7556 09:31:37.379964 [CA 1] Center 43 (14~73) winsize 60
7557 09:31:37.382960 [CA 2] Center 38 (9~68) winsize 60
7558 09:31:37.386521 [CA 3] Center 38 (9~67) winsize 59
7559 09:31:37.389493 [CA 4] Center 36 (7~65) winsize 59
7560 09:31:37.392625 [CA 5] Center 35 (6~65) winsize 60
7561 09:31:37.392739
7562 09:31:37.396257 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7563 09:31:37.396349
7564 09:31:37.399611 [CATrainingPosCal] consider 2 rank data
7565 09:31:37.402655 u2DelayCellTimex100 = 262/100 ps
7566 09:31:37.409320 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7567 09:31:37.412721 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7568 09:31:37.416140 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7569 09:31:37.419379 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7570 09:31:37.422372 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7571 09:31:37.425891 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7572 09:31:37.425972
7573 09:31:37.429440 CA PerBit enable=1, Macro0, CA PI delay=36
7574 09:31:37.429520
7575 09:31:37.432336 [CBTSetCACLKResult] CA Dly = 36
7576 09:31:37.435633 CS Dly: 12 (0~43)
7577 09:31:37.439200 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7578 09:31:37.442045 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7579 09:31:37.442155
7580 09:31:37.445732 ----->DramcWriteLeveling(PI) begin...
7581 09:31:37.445853 ==
7582 09:31:37.449036 Dram Type= 6, Freq= 0, CH_0, rank 0
7583 09:31:37.455498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 09:31:37.455619 ==
7585 09:31:37.458827 Write leveling (Byte 0): 34 => 34
7586 09:31:37.462081 Write leveling (Byte 1): 27 => 27
7587 09:31:37.462205 DramcWriteLeveling(PI) end<-----
7588 09:31:37.462275
7589 09:31:37.465571 ==
7590 09:31:37.469211 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 09:31:37.471961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 09:31:37.472049 ==
7593 09:31:37.475477 [Gating] SW mode calibration
7594 09:31:37.481757 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7595 09:31:37.485384 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7596 09:31:37.491840 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 09:31:37.495254 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 09:31:37.498480 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 09:31:37.504927 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7600 09:31:37.508380 1 4 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7601 09:31:37.511683 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7602 09:31:37.518479 1 4 24 | B1->B0 | 302f 3434 | 1 1 | (0 0) (1 1)
7603 09:31:37.521679 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 09:31:37.525075 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 09:31:37.531406 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7606 09:31:37.535040 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 09:31:37.538563 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
7608 09:31:37.544668 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7609 09:31:37.548041 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7610 09:31:37.551296 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
7611 09:31:37.557951 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 09:31:37.561000 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 09:31:37.564309 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 09:31:37.570791 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 09:31:37.574142 1 6 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
7616 09:31:37.578055 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7617 09:31:37.584386 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7618 09:31:37.587748 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 09:31:37.591187 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 09:31:37.597577 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 09:31:37.601081 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 09:31:37.603953 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 09:31:37.611030 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7624 09:31:37.614313 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7625 09:31:37.616936 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7626 09:31:37.623754 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7627 09:31:37.627043 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 09:31:37.630613 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 09:31:37.636935 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 09:31:37.640265 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 09:31:37.643686 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 09:31:37.650228 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 09:31:37.653125 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 09:31:37.656471 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 09:31:37.663463 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 09:31:37.666828 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 09:31:37.670137 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 09:31:37.676368 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 09:31:37.680047 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7640 09:31:37.682898 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7641 09:31:37.686532 Total UI for P1: 0, mck2ui 16
7642 09:31:37.689672 best dqsien dly found for B0: ( 1, 9, 12)
7643 09:31:37.696326 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7644 09:31:37.699776 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 09:31:37.703064 Total UI for P1: 0, mck2ui 16
7646 09:31:37.706607 best dqsien dly found for B1: ( 1, 9, 20)
7647 09:31:37.709317 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7648 09:31:37.712576 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7649 09:31:37.712660
7650 09:31:37.716002 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7651 09:31:37.722668 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7652 09:31:37.722783 [Gating] SW calibration Done
7653 09:31:37.722859 ==
7654 09:31:37.725859 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 09:31:37.732487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 09:31:37.732570 ==
7657 09:31:37.732634 RX Vref Scan: 0
7658 09:31:37.732693
7659 09:31:37.735811 RX Vref 0 -> 0, step: 1
7660 09:31:37.735890
7661 09:31:37.739014 RX Delay 0 -> 252, step: 8
7662 09:31:37.742311 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7663 09:31:37.745700 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7664 09:31:37.749271 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7665 09:31:37.755706 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7666 09:31:37.759101 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7667 09:31:37.762573 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7668 09:31:37.765425 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7669 09:31:37.768779 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7670 09:31:37.775634 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7671 09:31:37.778989 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7672 09:31:37.782611 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7673 09:31:37.785530 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7674 09:31:37.789107 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7675 09:31:37.795652 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7676 09:31:37.798697 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7677 09:31:37.802291 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7678 09:31:37.802840 ==
7679 09:31:37.805242 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 09:31:37.808546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 09:31:37.812100 ==
7682 09:31:37.812442 DQS Delay:
7683 09:31:37.812713 DQS0 = 0, DQS1 = 0
7684 09:31:37.815543 DQM Delay:
7685 09:31:37.815887 DQM0 = 133, DQM1 = 126
7686 09:31:37.818471 DQ Delay:
7687 09:31:37.821675 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =131
7688 09:31:37.825274 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
7689 09:31:37.828650 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7690 09:31:37.832236 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7691 09:31:37.832689
7692 09:31:37.832974
7693 09:31:37.833233 ==
7694 09:31:37.834861 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 09:31:37.838478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 09:31:37.838825 ==
7697 09:31:37.839097
7698 09:31:37.841578
7699 09:31:37.841954 TX Vref Scan disable
7700 09:31:37.844941 == TX Byte 0 ==
7701 09:31:37.848214 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7702 09:31:37.851640 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7703 09:31:37.855193 == TX Byte 1 ==
7704 09:31:37.858246 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7705 09:31:37.861357 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7706 09:31:37.861754 ==
7707 09:31:37.865120 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 09:31:37.871489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 09:31:37.871859 ==
7710 09:31:37.884085
7711 09:31:37.887526 TX Vref early break, caculate TX vref
7712 09:31:37.890140 TX Vref=16, minBit 14, minWin=21, winSum=370
7713 09:31:37.893783 TX Vref=18, minBit 2, minWin=23, winSum=379
7714 09:31:37.896874 TX Vref=20, minBit 1, minWin=23, winSum=391
7715 09:31:37.900054 TX Vref=22, minBit 3, minWin=24, winSum=402
7716 09:31:37.903278 TX Vref=24, minBit 4, minWin=24, winSum=407
7717 09:31:37.910278 TX Vref=26, minBit 4, minWin=25, winSum=418
7718 09:31:37.913442 TX Vref=28, minBit 1, minWin=25, winSum=417
7719 09:31:37.916879 TX Vref=30, minBit 5, minWin=24, winSum=411
7720 09:31:37.920126 TX Vref=32, minBit 1, minWin=24, winSum=402
7721 09:31:37.923623 TX Vref=34, minBit 4, minWin=23, winSum=388
7722 09:31:37.930287 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 26
7723 09:31:37.930722
7724 09:31:37.933214 Final TX Range 0 Vref 26
7725 09:31:37.933635
7726 09:31:37.933961 ==
7727 09:31:37.936517 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 09:31:37.939797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 09:31:37.940270 ==
7730 09:31:37.940577
7731 09:31:37.940853
7732 09:31:37.942989 TX Vref Scan disable
7733 09:31:37.949995 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7734 09:31:37.950408 == TX Byte 0 ==
7735 09:31:37.953515 u2DelayCellOfst[0]=14 cells (4 PI)
7736 09:31:37.956341 u2DelayCellOfst[1]=18 cells (5 PI)
7737 09:31:37.960013 u2DelayCellOfst[2]=14 cells (4 PI)
7738 09:31:37.962951 u2DelayCellOfst[3]=14 cells (4 PI)
7739 09:31:37.966260 u2DelayCellOfst[4]=11 cells (3 PI)
7740 09:31:37.969264 u2DelayCellOfst[5]=0 cells (0 PI)
7741 09:31:37.973357 u2DelayCellOfst[6]=22 cells (6 PI)
7742 09:31:37.975982 u2DelayCellOfst[7]=22 cells (6 PI)
7743 09:31:37.979318 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7744 09:31:37.982511 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7745 09:31:37.985825 == TX Byte 1 ==
7746 09:31:37.989159 u2DelayCellOfst[8]=0 cells (0 PI)
7747 09:31:37.993234 u2DelayCellOfst[9]=0 cells (0 PI)
7748 09:31:37.996018 u2DelayCellOfst[10]=3 cells (1 PI)
7749 09:31:37.998793 u2DelayCellOfst[11]=0 cells (0 PI)
7750 09:31:38.002502 u2DelayCellOfst[12]=11 cells (3 PI)
7751 09:31:38.003035 u2DelayCellOfst[13]=11 cells (3 PI)
7752 09:31:38.005736 u2DelayCellOfst[14]=11 cells (3 PI)
7753 09:31:38.008720 u2DelayCellOfst[15]=7 cells (2 PI)
7754 09:31:38.015422 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7755 09:31:38.018767 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7756 09:31:38.022121 DramC Write-DBI on
7757 09:31:38.022594 ==
7758 09:31:38.025583 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 09:31:38.028391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 09:31:38.028806 ==
7761 09:31:38.029116
7762 09:31:38.029397
7763 09:31:38.031583 TX Vref Scan disable
7764 09:31:38.031966 == TX Byte 0 ==
7765 09:31:38.038255 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7766 09:31:38.038647 == TX Byte 1 ==
7767 09:31:38.041411 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7768 09:31:38.044662 DramC Write-DBI off
7769 09:31:38.045192
7770 09:31:38.045628 [DATLAT]
7771 09:31:38.048176 Freq=1600, CH0 RK0
7772 09:31:38.048564
7773 09:31:38.048871 DATLAT Default: 0xf
7774 09:31:38.051192 0, 0xFFFF, sum = 0
7775 09:31:38.054866 1, 0xFFFF, sum = 0
7776 09:31:38.055254 2, 0xFFFF, sum = 0
7777 09:31:38.057760 3, 0xFFFF, sum = 0
7778 09:31:38.058147 4, 0xFFFF, sum = 0
7779 09:31:38.061698 5, 0xFFFF, sum = 0
7780 09:31:38.062087 6, 0xFFFF, sum = 0
7781 09:31:38.064381 7, 0xFFFF, sum = 0
7782 09:31:38.064659 8, 0xFFFF, sum = 0
7783 09:31:38.067644 9, 0xFFFF, sum = 0
7784 09:31:38.067919 10, 0xFFFF, sum = 0
7785 09:31:38.071078 11, 0xFFFF, sum = 0
7786 09:31:38.071294 12, 0xFFFF, sum = 0
7787 09:31:38.074438 13, 0xFFFF, sum = 0
7788 09:31:38.074649 14, 0x0, sum = 1
7789 09:31:38.077824 15, 0x0, sum = 2
7790 09:31:38.078000 16, 0x0, sum = 3
7791 09:31:38.080777 17, 0x0, sum = 4
7792 09:31:38.080925 best_step = 15
7793 09:31:38.081036
7794 09:31:38.081140 ==
7795 09:31:38.084188 Dram Type= 6, Freq= 0, CH_0, rank 0
7796 09:31:38.090463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7797 09:31:38.090610 ==
7798 09:31:38.090700 RX Vref Scan: 1
7799 09:31:38.090782
7800 09:31:38.094158 Set Vref Range= 24 -> 127
7801 09:31:38.094290
7802 09:31:38.097436 RX Vref 24 -> 127, step: 1
7803 09:31:38.097555
7804 09:31:38.097635 RX Delay 11 -> 252, step: 4
7805 09:31:38.100756
7806 09:31:38.100913 Set Vref, RX VrefLevel [Byte0]: 24
7807 09:31:38.104457 [Byte1]: 24
7808 09:31:38.108326
7809 09:31:38.108489 Set Vref, RX VrefLevel [Byte0]: 25
7810 09:31:38.111737 [Byte1]: 25
7811 09:31:38.116089
7812 09:31:38.116273 Set Vref, RX VrefLevel [Byte0]: 26
7813 09:31:38.118944 [Byte1]: 26
7814 09:31:38.123474
7815 09:31:38.123688 Set Vref, RX VrefLevel [Byte0]: 27
7816 09:31:38.127049 [Byte1]: 27
7817 09:31:38.130851
7818 09:31:38.130997 Set Vref, RX VrefLevel [Byte0]: 28
7819 09:31:38.134321 [Byte1]: 28
7820 09:31:38.138379
7821 09:31:38.138500 Set Vref, RX VrefLevel [Byte0]: 29
7822 09:31:38.141792 [Byte1]: 29
7823 09:31:38.146638
7824 09:31:38.147150 Set Vref, RX VrefLevel [Byte0]: 30
7825 09:31:38.149842 [Byte1]: 30
7826 09:31:38.153923
7827 09:31:38.154429 Set Vref, RX VrefLevel [Byte0]: 31
7828 09:31:38.157173 [Byte1]: 31
7829 09:31:38.161568
7830 09:31:38.162050 Set Vref, RX VrefLevel [Byte0]: 32
7831 09:31:38.165495 [Byte1]: 32
7832 09:31:38.169247
7833 09:31:38.169761 Set Vref, RX VrefLevel [Byte0]: 33
7834 09:31:38.172808 [Byte1]: 33
7835 09:31:38.177108
7836 09:31:38.177657 Set Vref, RX VrefLevel [Byte0]: 34
7837 09:31:38.180548 [Byte1]: 34
7838 09:31:38.184451
7839 09:31:38.184934 Set Vref, RX VrefLevel [Byte0]: 35
7840 09:31:38.187944 [Byte1]: 35
7841 09:31:38.191961
7842 09:31:38.192428 Set Vref, RX VrefLevel [Byte0]: 36
7843 09:31:38.195262 [Byte1]: 36
7844 09:31:38.199737
7845 09:31:38.200304 Set Vref, RX VrefLevel [Byte0]: 37
7846 09:31:38.203056 [Byte1]: 37
7847 09:31:38.207544
7848 09:31:38.208181 Set Vref, RX VrefLevel [Byte0]: 38
7849 09:31:38.210626 [Byte1]: 38
7850 09:31:38.215133
7851 09:31:38.218195 Set Vref, RX VrefLevel [Byte0]: 39
7852 09:31:38.218831 [Byte1]: 39
7853 09:31:38.222469
7854 09:31:38.222903 Set Vref, RX VrefLevel [Byte0]: 40
7855 09:31:38.225688 [Byte1]: 40
7856 09:31:38.229773
7857 09:31:38.230058 Set Vref, RX VrefLevel [Byte0]: 41
7858 09:31:38.233203 [Byte1]: 41
7859 09:31:38.237444
7860 09:31:38.237718 Set Vref, RX VrefLevel [Byte0]: 42
7861 09:31:38.240674 [Byte1]: 42
7862 09:31:38.244860
7863 09:31:38.245033 Set Vref, RX VrefLevel [Byte0]: 43
7864 09:31:38.248226 [Byte1]: 43
7865 09:31:38.252690
7866 09:31:38.252850 Set Vref, RX VrefLevel [Byte0]: 44
7867 09:31:38.255736 [Byte1]: 44
7868 09:31:38.260312
7869 09:31:38.260451 Set Vref, RX VrefLevel [Byte0]: 45
7870 09:31:38.263619 [Byte1]: 45
7871 09:31:38.268132
7872 09:31:38.268256 Set Vref, RX VrefLevel [Byte0]: 46
7873 09:31:38.271225 [Byte1]: 46
7874 09:31:38.275575
7875 09:31:38.275665 Set Vref, RX VrefLevel [Byte0]: 47
7876 09:31:38.278731 [Byte1]: 47
7877 09:31:38.282945
7878 09:31:38.283034 Set Vref, RX VrefLevel [Byte0]: 48
7879 09:31:38.286651 [Byte1]: 48
7880 09:31:38.290860
7881 09:31:38.290935 Set Vref, RX VrefLevel [Byte0]: 49
7882 09:31:38.293748 [Byte1]: 49
7883 09:31:38.298508
7884 09:31:38.298614 Set Vref, RX VrefLevel [Byte0]: 50
7885 09:31:38.301936 [Byte1]: 50
7886 09:31:38.305980
7887 09:31:38.306080 Set Vref, RX VrefLevel [Byte0]: 51
7888 09:31:38.309410 [Byte1]: 51
7889 09:31:38.313575
7890 09:31:38.313683 Set Vref, RX VrefLevel [Byte0]: 52
7891 09:31:38.317111 [Byte1]: 52
7892 09:31:38.321331
7893 09:31:38.321422 Set Vref, RX VrefLevel [Byte0]: 53
7894 09:31:38.324323 [Byte1]: 53
7895 09:31:38.328875
7896 09:31:38.328969 Set Vref, RX VrefLevel [Byte0]: 54
7897 09:31:38.331994 [Byte1]: 54
7898 09:31:38.336564
7899 09:31:38.336683 Set Vref, RX VrefLevel [Byte0]: 55
7900 09:31:38.339598 [Byte1]: 55
7901 09:31:38.343772
7902 09:31:38.343853 Set Vref, RX VrefLevel [Byte0]: 56
7903 09:31:38.347235 [Byte1]: 56
7904 09:31:38.351762
7905 09:31:38.351846 Set Vref, RX VrefLevel [Byte0]: 57
7906 09:31:38.355321 [Byte1]: 57
7907 09:31:38.359256
7908 09:31:38.359338 Set Vref, RX VrefLevel [Byte0]: 58
7909 09:31:38.362655 [Byte1]: 58
7910 09:31:38.366588
7911 09:31:38.366670 Set Vref, RX VrefLevel [Byte0]: 59
7912 09:31:38.370229 [Byte1]: 59
7913 09:31:38.374366
7914 09:31:38.374474 Set Vref, RX VrefLevel [Byte0]: 60
7915 09:31:38.377852 [Byte1]: 60
7916 09:31:38.382434
7917 09:31:38.382518 Set Vref, RX VrefLevel [Byte0]: 61
7918 09:31:38.385546 [Byte1]: 61
7919 09:31:38.389537
7920 09:31:38.389650 Set Vref, RX VrefLevel [Byte0]: 62
7921 09:31:38.392862 [Byte1]: 62
7922 09:31:38.397095
7923 09:31:38.397214 Set Vref, RX VrefLevel [Byte0]: 63
7924 09:31:38.400745 [Byte1]: 63
7925 09:31:38.405099
7926 09:31:38.405181 Set Vref, RX VrefLevel [Byte0]: 64
7927 09:31:38.408116 [Byte1]: 64
7928 09:31:38.412716
7929 09:31:38.412796 Set Vref, RX VrefLevel [Byte0]: 65
7930 09:31:38.416219 [Byte1]: 65
7931 09:31:38.420368
7932 09:31:38.420448 Set Vref, RX VrefLevel [Byte0]: 66
7933 09:31:38.423288 [Byte1]: 66
7934 09:31:38.427704
7935 09:31:38.427787 Set Vref, RX VrefLevel [Byte0]: 67
7936 09:31:38.430895 [Byte1]: 67
7937 09:31:38.435597
7938 09:31:38.435683 Set Vref, RX VrefLevel [Byte0]: 68
7939 09:31:38.438504 [Byte1]: 68
7940 09:31:38.443228
7941 09:31:38.443330 Set Vref, RX VrefLevel [Byte0]: 69
7942 09:31:38.446264 [Byte1]: 69
7943 09:31:38.451694
7944 09:31:38.451870 Set Vref, RX VrefLevel [Byte0]: 70
7945 09:31:38.453871 [Byte1]: 70
7946 09:31:38.458108
7947 09:31:38.458225 Set Vref, RX VrefLevel [Byte0]: 71
7948 09:31:38.461605 [Byte1]: 71
7949 09:31:38.466095
7950 09:31:38.466222 Set Vref, RX VrefLevel [Byte0]: 72
7951 09:31:38.469359 [Byte1]: 72
7952 09:31:38.473404
7953 09:31:38.473502 Set Vref, RX VrefLevel [Byte0]: 73
7954 09:31:38.476810 [Byte1]: 73
7955 09:31:38.480920
7956 09:31:38.481026 Set Vref, RX VrefLevel [Byte0]: 74
7957 09:31:38.484211 [Byte1]: 74
7958 09:31:38.488447
7959 09:31:38.488559 Set Vref, RX VrefLevel [Byte0]: 75
7960 09:31:38.491850 [Byte1]: 75
7961 09:31:38.496021
7962 09:31:38.496105 Set Vref, RX VrefLevel [Byte0]: 76
7963 09:31:38.499613 [Byte1]: 76
7964 09:31:38.503783
7965 09:31:38.503886 Set Vref, RX VrefLevel [Byte0]: 77
7966 09:31:38.507246 [Byte1]: 77
7967 09:31:38.511269
7968 09:31:38.511348 Set Vref, RX VrefLevel [Byte0]: 78
7969 09:31:38.514639 [Byte1]: 78
7970 09:31:38.519002
7971 09:31:38.519122 Set Vref, RX VrefLevel [Byte0]: 79
7972 09:31:38.522264 [Byte1]: 79
7973 09:31:38.526386
7974 09:31:38.526500 Final RX Vref Byte 0 = 63 to rank0
7975 09:31:38.529949 Final RX Vref Byte 1 = 59 to rank0
7976 09:31:38.532981 Final RX Vref Byte 0 = 63 to rank1
7977 09:31:38.536587 Final RX Vref Byte 1 = 59 to rank1==
7978 09:31:38.539687 Dram Type= 6, Freq= 0, CH_0, rank 0
7979 09:31:38.546491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7980 09:31:38.546584 ==
7981 09:31:38.546650 DQS Delay:
7982 09:31:38.549771 DQS0 = 0, DQS1 = 0
7983 09:31:38.549876 DQM Delay:
7984 09:31:38.549968 DQM0 = 132, DQM1 = 122
7985 09:31:38.553404 DQ Delay:
7986 09:31:38.556533 DQ0 =130, DQ1 =132, DQ2 =130, DQ3 =130
7987 09:31:38.559512 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
7988 09:31:38.562772 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =118
7989 09:31:38.566037 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
7990 09:31:38.566147
7991 09:31:38.566264
7992 09:31:38.566376
7993 09:31:38.569344 [DramC_TX_OE_Calibration] TA2
7994 09:31:38.572560 Original DQ_B0 (3 6) =30, OEN = 27
7995 09:31:38.576205 Original DQ_B1 (3 6) =30, OEN = 27
7996 09:31:38.579158 24, 0x0, End_B0=24 End_B1=24
7997 09:31:38.582474 25, 0x0, End_B0=25 End_B1=25
7998 09:31:38.582559 26, 0x0, End_B0=26 End_B1=26
7999 09:31:38.586171 27, 0x0, End_B0=27 End_B1=27
8000 09:31:38.589132 28, 0x0, End_B0=28 End_B1=28
8001 09:31:38.592749 29, 0x0, End_B0=29 End_B1=29
8002 09:31:38.592832 30, 0x0, End_B0=30 End_B1=30
8003 09:31:38.595514 31, 0x5151, End_B0=30 End_B1=30
8004 09:31:38.599124 Byte0 end_step=30 best_step=27
8005 09:31:38.602695 Byte1 end_step=30 best_step=27
8006 09:31:38.605557 Byte0 TX OE(2T, 0.5T) = (3, 3)
8007 09:31:38.609331 Byte1 TX OE(2T, 0.5T) = (3, 3)
8008 09:31:38.609453
8009 09:31:38.609524
8010 09:31:38.615384 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8011 09:31:38.618683 CH0 RK0: MR19=303, MR18=2011
8012 09:31:38.625608 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8013 09:31:38.625698
8014 09:31:38.628560 ----->DramcWriteLeveling(PI) begin...
8015 09:31:38.628644 ==
8016 09:31:38.631733 Dram Type= 6, Freq= 0, CH_0, rank 1
8017 09:31:38.634959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8018 09:31:38.635041 ==
8019 09:31:38.638741 Write leveling (Byte 0): 37 => 37
8020 09:31:38.642272 Write leveling (Byte 1): 28 => 28
8021 09:31:38.645565 DramcWriteLeveling(PI) end<-----
8022 09:31:38.645646
8023 09:31:38.645710 ==
8024 09:31:38.648252 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 09:31:38.654758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 09:31:38.654847 ==
8027 09:31:38.654913 [Gating] SW mode calibration
8028 09:31:38.664748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8029 09:31:38.712675 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8030 09:31:38.712886 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 09:31:38.713011 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 09:31:38.713121 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 09:31:38.713229 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 09:31:38.713302 1 4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8035 09:31:38.713363 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8036 09:31:38.713448 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 09:31:38.713536 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 09:31:38.713595 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8039 09:31:38.714250 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8040 09:31:38.717696 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8041 09:31:38.721032 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8042 09:31:38.727217 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8043 09:31:38.730755 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
8044 09:31:38.733924 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8045 09:31:38.740523 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 09:31:38.743799 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 09:31:38.747099 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 09:31:38.753976 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 09:31:38.757067 1 6 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
8050 09:31:38.760267 1 6 16 | B1->B0 | 2424 4444 | 1 0 | (0 0) (0 0)
8051 09:31:38.766872 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8052 09:31:38.770435 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8053 09:31:38.773307 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 09:31:38.779958 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 09:31:38.783479 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 09:31:38.786886 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8057 09:31:38.793409 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8058 09:31:38.796571 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8059 09:31:38.799979 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8060 09:31:38.806487 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 09:31:38.809916 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 09:31:38.813271 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 09:31:38.819813 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 09:31:38.823077 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 09:31:38.826594 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 09:31:38.833093 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 09:31:38.836022 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 09:31:38.839548 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 09:31:38.846035 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 09:31:38.849760 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 09:31:38.852979 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 09:31:38.859084 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8073 09:31:38.862738 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8074 09:31:38.865854 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8075 09:31:38.869025 Total UI for P1: 0, mck2ui 16
8076 09:31:38.872100 best dqsien dly found for B0: ( 1, 9, 10)
8077 09:31:38.878614 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8078 09:31:38.882072 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 09:31:38.885502 Total UI for P1: 0, mck2ui 16
8080 09:31:38.889076 best dqsien dly found for B1: ( 1, 9, 18)
8081 09:31:38.892425 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8082 09:31:38.895710 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8083 09:31:38.895793
8084 09:31:38.898940 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8085 09:31:38.901882 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8086 09:31:38.905567 [Gating] SW calibration Done
8087 09:31:38.905676 ==
8088 09:31:38.909033 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 09:31:38.914979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 09:31:38.915094 ==
8091 09:31:38.915166 RX Vref Scan: 0
8092 09:31:38.915231
8093 09:31:38.918362 RX Vref 0 -> 0, step: 1
8094 09:31:38.918489
8095 09:31:38.921770 RX Delay 0 -> 252, step: 8
8096 09:31:38.924656 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8097 09:31:38.927976 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8098 09:31:38.931382 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8099 09:31:38.935013 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8100 09:31:38.941679 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8101 09:31:38.944705 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8102 09:31:38.947711 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8103 09:31:38.951132 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8104 09:31:38.954656 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8105 09:31:38.960993 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8106 09:31:38.964370 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8107 09:31:38.967650 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8108 09:31:38.970966 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8109 09:31:38.977596 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8110 09:31:38.980634 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8111 09:31:38.984248 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8112 09:31:38.984358 ==
8113 09:31:38.987715 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 09:31:38.990537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 09:31:38.990622 ==
8116 09:31:38.993972 DQS Delay:
8117 09:31:38.994055 DQS0 = 0, DQS1 = 0
8118 09:31:38.997453 DQM Delay:
8119 09:31:38.997564 DQM0 = 132, DQM1 = 127
8120 09:31:39.000685 DQ Delay:
8121 09:31:39.003660 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8122 09:31:39.007132 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8123 09:31:39.010629 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8124 09:31:39.014141 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8125 09:31:39.014247
8126 09:31:39.014312
8127 09:31:39.014372 ==
8128 09:31:39.016921 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 09:31:39.020482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 09:31:39.020580 ==
8131 09:31:39.020659
8132 09:31:39.023859
8133 09:31:39.023942 TX Vref Scan disable
8134 09:31:39.026856 == TX Byte 0 ==
8135 09:31:39.029933 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8136 09:31:39.033275 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8137 09:31:39.036706 == TX Byte 1 ==
8138 09:31:39.040179 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8139 09:31:39.043412 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8140 09:31:39.043504 ==
8141 09:31:39.046623 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 09:31:39.053345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 09:31:39.053466 ==
8144 09:31:39.065857
8145 09:31:39.069189 TX Vref early break, caculate TX vref
8146 09:31:39.072777 TX Vref=16, minBit 3, minWin=22, winSum=379
8147 09:31:39.076166 TX Vref=18, minBit 0, minWin=23, winSum=385
8148 09:31:39.079086 TX Vref=20, minBit 1, minWin=23, winSum=394
8149 09:31:39.082293 TX Vref=22, minBit 3, minWin=24, winSum=406
8150 09:31:39.085704 TX Vref=24, minBit 1, minWin=24, winSum=412
8151 09:31:39.092259 TX Vref=26, minBit 0, minWin=25, winSum=417
8152 09:31:39.095249 TX Vref=28, minBit 0, minWin=24, winSum=409
8153 09:31:39.098708 TX Vref=30, minBit 0, minWin=24, winSum=406
8154 09:31:39.101932 TX Vref=32, minBit 0, minWin=24, winSum=398
8155 09:31:39.105512 TX Vref=34, minBit 7, minWin=23, winSum=393
8156 09:31:39.111710 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 26
8157 09:31:39.111791
8158 09:31:39.115355 Final TX Range 0 Vref 26
8159 09:31:39.115436
8160 09:31:39.115499 ==
8161 09:31:39.118313 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 09:31:39.121791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 09:31:39.121872 ==
8164 09:31:39.121935
8165 09:31:39.125185
8166 09:31:39.125265 TX Vref Scan disable
8167 09:31:39.131426 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8168 09:31:39.131511 == TX Byte 0 ==
8169 09:31:39.135241 u2DelayCellOfst[0]=14 cells (4 PI)
8170 09:31:39.138579 u2DelayCellOfst[1]=18 cells (5 PI)
8171 09:31:39.141369 u2DelayCellOfst[2]=14 cells (4 PI)
8172 09:31:39.144724 u2DelayCellOfst[3]=14 cells (4 PI)
8173 09:31:39.148198 u2DelayCellOfst[4]=11 cells (3 PI)
8174 09:31:39.151253 u2DelayCellOfst[5]=0 cells (0 PI)
8175 09:31:39.155067 u2DelayCellOfst[6]=22 cells (6 PI)
8176 09:31:39.158055 u2DelayCellOfst[7]=22 cells (6 PI)
8177 09:31:39.161022 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8178 09:31:39.164373 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8179 09:31:39.167800 == TX Byte 1 ==
8180 09:31:39.171293 u2DelayCellOfst[8]=0 cells (0 PI)
8181 09:31:39.174566 u2DelayCellOfst[9]=3 cells (1 PI)
8182 09:31:39.177915 u2DelayCellOfst[10]=7 cells (2 PI)
8183 09:31:39.181073 u2DelayCellOfst[11]=3 cells (1 PI)
8184 09:31:39.184241 u2DelayCellOfst[12]=11 cells (3 PI)
8185 09:31:39.187842 u2DelayCellOfst[13]=11 cells (3 PI)
8186 09:31:39.187974 u2DelayCellOfst[14]=18 cells (5 PI)
8187 09:31:39.191160 u2DelayCellOfst[15]=11 cells (3 PI)
8188 09:31:39.197483 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8189 09:31:39.200983 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8190 09:31:39.204510 DramC Write-DBI on
8191 09:31:39.204608 ==
8192 09:31:39.207233 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 09:31:39.210714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 09:31:39.210808 ==
8195 09:31:39.210875
8196 09:31:39.210936
8197 09:31:39.214386 TX Vref Scan disable
8198 09:31:39.214470 == TX Byte 0 ==
8199 09:31:39.220451 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8200 09:31:39.220549 == TX Byte 1 ==
8201 09:31:39.227055 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8202 09:31:39.227156 DramC Write-DBI off
8203 09:31:39.227221
8204 09:31:39.227281 [DATLAT]
8205 09:31:39.230572 Freq=1600, CH0 RK1
8206 09:31:39.230664
8207 09:31:39.233756 DATLAT Default: 0xf
8208 09:31:39.233840 0, 0xFFFF, sum = 0
8209 09:31:39.236756 1, 0xFFFF, sum = 0
8210 09:31:39.236843 2, 0xFFFF, sum = 0
8211 09:31:39.240641 3, 0xFFFF, sum = 0
8212 09:31:39.240748 4, 0xFFFF, sum = 0
8213 09:31:39.243435 5, 0xFFFF, sum = 0
8214 09:31:39.243524 6, 0xFFFF, sum = 0
8215 09:31:39.247003 7, 0xFFFF, sum = 0
8216 09:31:39.247091 8, 0xFFFF, sum = 0
8217 09:31:39.250070 9, 0xFFFF, sum = 0
8218 09:31:39.250197 10, 0xFFFF, sum = 0
8219 09:31:39.253495 11, 0xFFFF, sum = 0
8220 09:31:39.253606 12, 0xFFFF, sum = 0
8221 09:31:39.256795 13, 0xFFFF, sum = 0
8222 09:31:39.256907 14, 0x0, sum = 1
8223 09:31:39.259820 15, 0x0, sum = 2
8224 09:31:39.259911 16, 0x0, sum = 3
8225 09:31:39.263109 17, 0x0, sum = 4
8226 09:31:39.263189 best_step = 15
8227 09:31:39.263252
8228 09:31:39.263315 ==
8229 09:31:39.266602 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 09:31:39.273498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 09:31:39.273582 ==
8232 09:31:39.273661 RX Vref Scan: 0
8233 09:31:39.273754
8234 09:31:39.276661 RX Vref 0 -> 0, step: 1
8235 09:31:39.276771
8236 09:31:39.279728 RX Delay 11 -> 252, step: 4
8237 09:31:39.283279 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8238 09:31:39.286251 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8239 09:31:39.293138 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8240 09:31:39.296372 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8241 09:31:39.299770 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8242 09:31:39.302920 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8243 09:31:39.306440 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8244 09:31:39.313026 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8245 09:31:39.315987 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8246 09:31:39.319641 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8247 09:31:39.322467 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8248 09:31:39.326105 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8249 09:31:39.332592 iDelay=195, Bit 12, Center 128 (75 ~ 182) 108
8250 09:31:39.336130 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8251 09:31:39.339395 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8252 09:31:39.342332 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8253 09:31:39.342412 ==
8254 09:31:39.345484 Dram Type= 6, Freq= 0, CH_0, rank 1
8255 09:31:39.352145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 09:31:39.352226 ==
8257 09:31:39.352290 DQS Delay:
8258 09:31:39.355717 DQS0 = 0, DQS1 = 0
8259 09:31:39.355798 DQM Delay:
8260 09:31:39.359106 DQM0 = 130, DQM1 = 125
8261 09:31:39.359186 DQ Delay:
8262 09:31:39.362311 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =128
8263 09:31:39.365461 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8264 09:31:39.368942 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8265 09:31:39.371720 DQ12 =128, DQ13 =132, DQ14 =136, DQ15 =132
8266 09:31:39.371800
8267 09:31:39.371863
8268 09:31:39.371922
8269 09:31:39.375486 [DramC_TX_OE_Calibration] TA2
8270 09:31:39.378340 Original DQ_B0 (3 6) =30, OEN = 27
8271 09:31:39.381744 Original DQ_B1 (3 6) =30, OEN = 27
8272 09:31:39.385072 24, 0x0, End_B0=24 End_B1=24
8273 09:31:39.388479 25, 0x0, End_B0=25 End_B1=25
8274 09:31:39.388615 26, 0x0, End_B0=26 End_B1=26
8275 09:31:39.392114 27, 0x0, End_B0=27 End_B1=27
8276 09:31:39.395482 28, 0x0, End_B0=28 End_B1=28
8277 09:31:39.398364 29, 0x0, End_B0=29 End_B1=29
8278 09:31:39.402052 30, 0x0, End_B0=30 End_B1=30
8279 09:31:39.402236 31, 0x4141, End_B0=30 End_B1=30
8280 09:31:39.405387 Byte0 end_step=30 best_step=27
8281 09:31:39.408481 Byte1 end_step=30 best_step=27
8282 09:31:39.412019 Byte0 TX OE(2T, 0.5T) = (3, 3)
8283 09:31:39.414671 Byte1 TX OE(2T, 0.5T) = (3, 3)
8284 09:31:39.414867
8285 09:31:39.414994
8286 09:31:39.421499 [DQSOSCAuto] RK1, (LSB)MR18= 0x2004, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8287 09:31:39.425125 CH0 RK1: MR19=303, MR18=2004
8288 09:31:39.431553 CH0_RK1: MR19=0x303, MR18=0x2004, DQSOSC=393, MR23=63, INC=23, DEC=15
8289 09:31:39.435008 [RxdqsGatingPostProcess] freq 1600
8290 09:31:39.441441 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8291 09:31:39.444762 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 09:31:39.444864 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 09:31:39.448025 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 09:31:39.451200 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 09:31:39.454780 best DQS0 dly(2T, 0.5T) = (1, 1)
8296 09:31:39.457483 best DQS1 dly(2T, 0.5T) = (1, 1)
8297 09:31:39.461005 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8298 09:31:39.464548 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8299 09:31:39.467970 Pre-setting of DQS Precalculation
8300 09:31:39.471451 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8301 09:31:39.474559 ==
8302 09:31:39.474678 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 09:31:39.481240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 09:31:39.481377 ==
8305 09:31:39.484686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8306 09:31:39.490855 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8307 09:31:39.494566 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8308 09:31:39.500566 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8309 09:31:39.508864 [CA 0] Center 42 (13~72) winsize 60
8310 09:31:39.512217 [CA 1] Center 42 (13~72) winsize 60
8311 09:31:39.515438 [CA 2] Center 37 (9~66) winsize 58
8312 09:31:39.518708 [CA 3] Center 37 (8~66) winsize 59
8313 09:31:39.521924 [CA 4] Center 38 (8~68) winsize 61
8314 09:31:39.525044 [CA 5] Center 37 (8~67) winsize 60
8315 09:31:39.525221
8316 09:31:39.528370 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8317 09:31:39.528482
8318 09:31:39.535262 [CATrainingPosCal] consider 1 rank data
8319 09:31:39.535678 u2DelayCellTimex100 = 262/100 ps
8320 09:31:39.541893 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8321 09:31:39.545630 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8322 09:31:39.548277 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8323 09:31:39.551752 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8324 09:31:39.555459 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8325 09:31:39.558955 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8326 09:31:39.559356
8327 09:31:39.561977 CA PerBit enable=1, Macro0, CA PI delay=37
8328 09:31:39.562287
8329 09:31:39.564961 [CBTSetCACLKResult] CA Dly = 37
8330 09:31:39.568384 CS Dly: 9 (0~40)
8331 09:31:39.571575 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8332 09:31:39.574651 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8333 09:31:39.574826 ==
8334 09:31:39.578018 Dram Type= 6, Freq= 0, CH_1, rank 1
8335 09:31:39.584916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 09:31:39.585030 ==
8337 09:31:39.587817 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 09:31:39.594555 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 09:31:39.597808 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 09:31:39.604688 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 09:31:39.612033 [CA 0] Center 42 (12~72) winsize 61
8342 09:31:39.615450 [CA 1] Center 42 (13~72) winsize 60
8343 09:31:39.618983 [CA 2] Center 37 (8~67) winsize 60
8344 09:31:39.621931 [CA 3] Center 36 (7~66) winsize 60
8345 09:31:39.625424 [CA 4] Center 37 (7~67) winsize 61
8346 09:31:39.628774 [CA 5] Center 37 (8~67) winsize 60
8347 09:31:39.629155
8348 09:31:39.632056 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8349 09:31:39.632354
8350 09:31:39.635286 [CATrainingPosCal] consider 2 rank data
8351 09:31:39.638899 u2DelayCellTimex100 = 262/100 ps
8352 09:31:39.645203 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8353 09:31:39.648242 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8354 09:31:39.651778 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8355 09:31:39.654762 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8356 09:31:39.658021 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8357 09:31:39.661599 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8358 09:31:39.661757
8359 09:31:39.664797 CA PerBit enable=1, Macro0, CA PI delay=37
8360 09:31:39.664977
8361 09:31:39.667886 [CBTSetCACLKResult] CA Dly = 37
8362 09:31:39.671098 CS Dly: 10 (0~43)
8363 09:31:39.674493 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 09:31:39.677788 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 09:31:39.677978
8366 09:31:39.681531 ----->DramcWriteLeveling(PI) begin...
8367 09:31:39.681726 ==
8368 09:31:39.684227 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 09:31:39.691020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 09:31:39.691196 ==
8371 09:31:39.694419 Write leveling (Byte 0): 23 => 23
8372 09:31:39.697820 Write leveling (Byte 1): 27 => 27
8373 09:31:39.700963 DramcWriteLeveling(PI) end<-----
8374 09:31:39.701143
8375 09:31:39.701283 ==
8376 09:31:39.704110 Dram Type= 6, Freq= 0, CH_1, rank 0
8377 09:31:39.707547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 09:31:39.707680 ==
8379 09:31:39.710547 [Gating] SW mode calibration
8380 09:31:39.717309 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8381 09:31:39.723788 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8382 09:31:39.727485 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 09:31:39.730775 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 09:31:39.737203 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 09:31:39.740478 1 4 12 | B1->B0 | 3030 3434 | 1 0 | (1 1) (0 0)
8386 09:31:39.743963 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 09:31:39.750115 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 09:31:39.753559 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 09:31:39.756851 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 09:31:39.763521 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 09:31:39.767204 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 09:31:39.770421 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8393 09:31:39.776792 1 5 12 | B1->B0 | 3333 2b2b | 1 0 | (1 0) (0 1)
8394 09:31:39.780324 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 09:31:39.783159 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 09:31:39.789826 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 09:31:39.793138 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 09:31:39.796705 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 09:31:39.803045 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 09:31:39.806315 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 09:31:39.809501 1 6 12 | B1->B0 | 3737 4141 | 1 0 | (0 0) (0 0)
8402 09:31:39.816315 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 09:31:39.819781 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 09:31:39.822720 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 09:31:39.829719 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 09:31:39.832689 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 09:31:39.836100 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 09:31:39.842266 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8409 09:31:39.845799 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8410 09:31:39.848981 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8411 09:31:39.855769 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 09:31:39.859113 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 09:31:39.862376 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 09:31:39.868835 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 09:31:39.872537 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 09:31:39.875185 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 09:31:39.881827 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 09:31:39.885485 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 09:31:39.888796 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 09:31:39.895310 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 09:31:39.898633 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 09:31:39.902153 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 09:31:39.908327 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 09:31:39.911761 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 09:31:39.915493 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8426 09:31:39.921485 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 09:31:39.921641 Total UI for P1: 0, mck2ui 16
8428 09:31:39.927903 best dqsien dly found for B0: ( 1, 9, 12)
8429 09:31:39.928081 Total UI for P1: 0, mck2ui 16
8430 09:31:39.935185 best dqsien dly found for B1: ( 1, 9, 12)
8431 09:31:39.938113 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8432 09:31:39.941911 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8433 09:31:39.942359
8434 09:31:39.944704 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8435 09:31:39.948121 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8436 09:31:39.951386 [Gating] SW calibration Done
8437 09:31:39.951797 ==
8438 09:31:39.954451 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 09:31:39.958301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 09:31:39.958716 ==
8441 09:31:39.961292 RX Vref Scan: 0
8442 09:31:39.961715
8443 09:31:39.962038 RX Vref 0 -> 0, step: 1
8444 09:31:39.965140
8445 09:31:39.965638 RX Delay 0 -> 252, step: 8
8446 09:31:39.968076 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8447 09:31:39.974510 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8448 09:31:39.978066 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8449 09:31:39.981264 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8450 09:31:39.984456 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8451 09:31:39.987913 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8452 09:31:39.994357 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8453 09:31:39.997725 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8454 09:31:40.000970 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8455 09:31:40.004871 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8456 09:31:40.010939 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8457 09:31:40.013915 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8458 09:31:40.017673 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8459 09:31:40.020592 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8460 09:31:40.024410 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8461 09:31:40.030503 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8462 09:31:40.030931 ==
8463 09:31:40.033642 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 09:31:40.036887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 09:31:40.037448 ==
8466 09:31:40.037820 DQS Delay:
8467 09:31:40.039877 DQS0 = 0, DQS1 = 0
8468 09:31:40.040283 DQM Delay:
8469 09:31:40.043775 DQM0 = 137, DQM1 = 128
8470 09:31:40.044275 DQ Delay:
8471 09:31:40.047115 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8472 09:31:40.050055 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8473 09:31:40.053360 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
8474 09:31:40.059986 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8475 09:31:40.060498
8476 09:31:40.061021
8477 09:31:40.061529 ==
8478 09:31:40.063485 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 09:31:40.066918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 09:31:40.067338 ==
8481 09:31:40.067665
8482 09:31:40.067963
8483 09:31:40.070035 TX Vref Scan disable
8484 09:31:40.070490 == TX Byte 0 ==
8485 09:31:40.076387 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8486 09:31:40.079870 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8487 09:31:40.080299 == TX Byte 1 ==
8488 09:31:40.086258 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8489 09:31:40.089914 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8490 09:31:40.090505 ==
8491 09:31:40.092848 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 09:31:40.096219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 09:31:40.096668 ==
8494 09:31:40.110455
8495 09:31:40.113371 TX Vref early break, caculate TX vref
8496 09:31:40.116846 TX Vref=16, minBit 6, minWin=21, winSum=371
8497 09:31:40.120290 TX Vref=18, minBit 0, minWin=22, winSum=382
8498 09:31:40.123328 TX Vref=20, minBit 0, minWin=23, winSum=392
8499 09:31:40.126617 TX Vref=22, minBit 0, minWin=24, winSum=406
8500 09:31:40.129554 TX Vref=24, minBit 0, minWin=24, winSum=414
8501 09:31:40.136525 TX Vref=26, minBit 0, minWin=24, winSum=414
8502 09:31:40.139347 TX Vref=28, minBit 0, minWin=25, winSum=417
8503 09:31:40.143128 TX Vref=30, minBit 0, minWin=24, winSum=408
8504 09:31:40.146428 TX Vref=32, minBit 0, minWin=23, winSum=400
8505 09:31:40.149829 TX Vref=34, minBit 0, minWin=23, winSum=395
8506 09:31:40.156008 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8507 09:31:40.156103
8508 09:31:40.159526 Final TX Range 0 Vref 28
8509 09:31:40.159624
8510 09:31:40.159699 ==
8511 09:31:40.162676 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 09:31:40.166082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 09:31:40.166210 ==
8514 09:31:40.166277
8515 09:31:40.166338
8516 09:31:40.169139 TX Vref Scan disable
8517 09:31:40.176014 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8518 09:31:40.176094 == TX Byte 0 ==
8519 09:31:40.178950 u2DelayCellOfst[0]=18 cells (5 PI)
8520 09:31:40.182437 u2DelayCellOfst[1]=11 cells (3 PI)
8521 09:31:40.185436 u2DelayCellOfst[2]=0 cells (0 PI)
8522 09:31:40.188838 u2DelayCellOfst[3]=3 cells (1 PI)
8523 09:31:40.192348 u2DelayCellOfst[4]=7 cells (2 PI)
8524 09:31:40.195752 u2DelayCellOfst[5]=18 cells (5 PI)
8525 09:31:40.198744 u2DelayCellOfst[6]=18 cells (5 PI)
8526 09:31:40.201942 u2DelayCellOfst[7]=7 cells (2 PI)
8527 09:31:40.205344 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8528 09:31:40.208473 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8529 09:31:40.211755 == TX Byte 1 ==
8530 09:31:40.215527 u2DelayCellOfst[8]=0 cells (0 PI)
8531 09:31:40.218530 u2DelayCellOfst[9]=3 cells (1 PI)
8532 09:31:40.221867 u2DelayCellOfst[10]=11 cells (3 PI)
8533 09:31:40.221973 u2DelayCellOfst[11]=7 cells (2 PI)
8534 09:31:40.225107 u2DelayCellOfst[12]=14 cells (4 PI)
8535 09:31:40.228517 u2DelayCellOfst[13]=18 cells (5 PI)
8536 09:31:40.231610 u2DelayCellOfst[14]=18 cells (5 PI)
8537 09:31:40.234944 u2DelayCellOfst[15]=18 cells (5 PI)
8538 09:31:40.241574 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8539 09:31:40.244975 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8540 09:31:40.245056 DramC Write-DBI on
8541 09:31:40.248481 ==
8542 09:31:40.248561 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 09:31:40.254964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 09:31:40.255048 ==
8545 09:31:40.255128
8546 09:31:40.255189
8547 09:31:40.258289 TX Vref Scan disable
8548 09:31:40.258369 == TX Byte 0 ==
8549 09:31:40.264790 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8550 09:31:40.264871 == TX Byte 1 ==
8551 09:31:40.268645 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8552 09:31:40.271484 DramC Write-DBI off
8553 09:31:40.271588
8554 09:31:40.271653 [DATLAT]
8555 09:31:40.274654 Freq=1600, CH1 RK0
8556 09:31:40.274735
8557 09:31:40.274798 DATLAT Default: 0xf
8558 09:31:40.277933 0, 0xFFFF, sum = 0
8559 09:31:40.278014 1, 0xFFFF, sum = 0
8560 09:31:40.281447 2, 0xFFFF, sum = 0
8561 09:31:40.281528 3, 0xFFFF, sum = 0
8562 09:31:40.284317 4, 0xFFFF, sum = 0
8563 09:31:40.284399 5, 0xFFFF, sum = 0
8564 09:31:40.287748 6, 0xFFFF, sum = 0
8565 09:31:40.287829 7, 0xFFFF, sum = 0
8566 09:31:40.291253 8, 0xFFFF, sum = 0
8567 09:31:40.294699 9, 0xFFFF, sum = 0
8568 09:31:40.294780 10, 0xFFFF, sum = 0
8569 09:31:40.297505 11, 0xFFFF, sum = 0
8570 09:31:40.297585 12, 0xFFFF, sum = 0
8571 09:31:40.300955 13, 0xFFFF, sum = 0
8572 09:31:40.301037 14, 0x0, sum = 1
8573 09:31:40.304432 15, 0x0, sum = 2
8574 09:31:40.304554 16, 0x0, sum = 3
8575 09:31:40.307381 17, 0x0, sum = 4
8576 09:31:40.307462 best_step = 15
8577 09:31:40.307525
8578 09:31:40.307630 ==
8579 09:31:40.310628 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 09:31:40.313824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 09:31:40.317346 ==
8582 09:31:40.317449 RX Vref Scan: 1
8583 09:31:40.317541
8584 09:31:40.320779 Set Vref Range= 24 -> 127
8585 09:31:40.320887
8586 09:31:40.324203 RX Vref 24 -> 127, step: 1
8587 09:31:40.324297
8588 09:31:40.324383 RX Delay 11 -> 252, step: 4
8589 09:31:40.324468
8590 09:31:40.327317 Set Vref, RX VrefLevel [Byte0]: 24
8591 09:31:40.331011 [Byte1]: 24
8592 09:31:40.334401
8593 09:31:40.334496 Set Vref, RX VrefLevel [Byte0]: 25
8594 09:31:40.337631 [Byte1]: 25
8595 09:31:40.342322
8596 09:31:40.342404 Set Vref, RX VrefLevel [Byte0]: 26
8597 09:31:40.345429 [Byte1]: 26
8598 09:31:40.349790
8599 09:31:40.349866 Set Vref, RX VrefLevel [Byte0]: 27
8600 09:31:40.353014 [Byte1]: 27
8601 09:31:40.356991
8602 09:31:40.357078 Set Vref, RX VrefLevel [Byte0]: 28
8603 09:31:40.360287 [Byte1]: 28
8604 09:31:40.364781
8605 09:31:40.364870 Set Vref, RX VrefLevel [Byte0]: 29
8606 09:31:40.368070 [Byte1]: 29
8607 09:31:40.372590
8608 09:31:40.372676 Set Vref, RX VrefLevel [Byte0]: 30
8609 09:31:40.375966 [Byte1]: 30
8610 09:31:40.380018
8611 09:31:40.380091 Set Vref, RX VrefLevel [Byte0]: 31
8612 09:31:40.383472 [Byte1]: 31
8613 09:31:40.387503
8614 09:31:40.387580 Set Vref, RX VrefLevel [Byte0]: 32
8615 09:31:40.391112 [Byte1]: 32
8616 09:31:40.395390
8617 09:31:40.395466 Set Vref, RX VrefLevel [Byte0]: 33
8618 09:31:40.398818 [Byte1]: 33
8619 09:31:40.402946
8620 09:31:40.403032 Set Vref, RX VrefLevel [Byte0]: 34
8621 09:31:40.406318 [Byte1]: 34
8622 09:31:40.410729
8623 09:31:40.410804 Set Vref, RX VrefLevel [Byte0]: 35
8624 09:31:40.413711 [Byte1]: 35
8625 09:31:40.418118
8626 09:31:40.418226 Set Vref, RX VrefLevel [Byte0]: 36
8627 09:31:40.421123 [Byte1]: 36
8628 09:31:40.425500
8629 09:31:40.425606 Set Vref, RX VrefLevel [Byte0]: 37
8630 09:31:40.428889 [Byte1]: 37
8631 09:31:40.433358
8632 09:31:40.433433 Set Vref, RX VrefLevel [Byte0]: 38
8633 09:31:40.436927 [Byte1]: 38
8634 09:31:40.440620
8635 09:31:40.440696 Set Vref, RX VrefLevel [Byte0]: 39
8636 09:31:40.444055 [Byte1]: 39
8637 09:31:40.448302
8638 09:31:40.448373 Set Vref, RX VrefLevel [Byte0]: 40
8639 09:31:40.451528 [Byte1]: 40
8640 09:31:40.456205
8641 09:31:40.456280 Set Vref, RX VrefLevel [Byte0]: 41
8642 09:31:40.459526 [Byte1]: 41
8643 09:31:40.463488
8644 09:31:40.463568 Set Vref, RX VrefLevel [Byte0]: 42
8645 09:31:40.467038 [Byte1]: 42
8646 09:31:40.471364
8647 09:31:40.471441 Set Vref, RX VrefLevel [Byte0]: 43
8648 09:31:40.474651 [Byte1]: 43
8649 09:31:40.479121
8650 09:31:40.479199 Set Vref, RX VrefLevel [Byte0]: 44
8651 09:31:40.482603 [Byte1]: 44
8652 09:31:40.486825
8653 09:31:40.486902 Set Vref, RX VrefLevel [Byte0]: 45
8654 09:31:40.490254 [Byte1]: 45
8655 09:31:40.494524
8656 09:31:40.494903 Set Vref, RX VrefLevel [Byte0]: 46
8657 09:31:40.497843 [Byte1]: 46
8658 09:31:40.501974
8659 09:31:40.502582 Set Vref, RX VrefLevel [Byte0]: 47
8660 09:31:40.505500 [Byte1]: 47
8661 09:31:40.509673
8662 09:31:40.510132 Set Vref, RX VrefLevel [Byte0]: 48
8663 09:31:40.512971 [Byte1]: 48
8664 09:31:40.517532
8665 09:31:40.517939 Set Vref, RX VrefLevel [Byte0]: 49
8666 09:31:40.521153 [Byte1]: 49
8667 09:31:40.525701
8668 09:31:40.526273 Set Vref, RX VrefLevel [Byte0]: 50
8669 09:31:40.528750 [Byte1]: 50
8670 09:31:40.533195
8671 09:31:40.533815 Set Vref, RX VrefLevel [Byte0]: 51
8672 09:31:40.536027 [Byte1]: 51
8673 09:31:40.540241
8674 09:31:40.540840 Set Vref, RX VrefLevel [Byte0]: 52
8675 09:31:40.543662 [Byte1]: 52
8676 09:31:40.548026
8677 09:31:40.548543 Set Vref, RX VrefLevel [Byte0]: 53
8678 09:31:40.551213 [Byte1]: 53
8679 09:31:40.555634
8680 09:31:40.556048 Set Vref, RX VrefLevel [Byte0]: 54
8681 09:31:40.558930 [Byte1]: 54
8682 09:31:40.563126
8683 09:31:40.563534 Set Vref, RX VrefLevel [Byte0]: 55
8684 09:31:40.566423 [Byte1]: 55
8685 09:31:40.570913
8686 09:31:40.571321 Set Vref, RX VrefLevel [Byte0]: 56
8687 09:31:40.573891 [Byte1]: 56
8688 09:31:40.578364
8689 09:31:40.578887 Set Vref, RX VrefLevel [Byte0]: 57
8690 09:31:40.581508 [Byte1]: 57
8691 09:31:40.585896
8692 09:31:40.586353 Set Vref, RX VrefLevel [Byte0]: 58
8693 09:31:40.589148 [Byte1]: 58
8694 09:31:40.593510
8695 09:31:40.593916 Set Vref, RX VrefLevel [Byte0]: 59
8696 09:31:40.596522 [Byte1]: 59
8697 09:31:40.601067
8698 09:31:40.601476 Set Vref, RX VrefLevel [Byte0]: 60
8699 09:31:40.604157 [Byte1]: 60
8700 09:31:40.608856
8701 09:31:40.609267 Set Vref, RX VrefLevel [Byte0]: 61
8702 09:31:40.611760 [Byte1]: 61
8703 09:31:40.616363
8704 09:31:40.616795 Set Vref, RX VrefLevel [Byte0]: 62
8705 09:31:40.619863 [Byte1]: 62
8706 09:31:40.623734
8707 09:31:40.624283 Set Vref, RX VrefLevel [Byte0]: 63
8708 09:31:40.627254 [Byte1]: 63
8709 09:31:40.631411
8710 09:31:40.631882 Set Vref, RX VrefLevel [Byte0]: 64
8711 09:31:40.634612 [Byte1]: 64
8712 09:31:40.639284
8713 09:31:40.639721 Set Vref, RX VrefLevel [Byte0]: 65
8714 09:31:40.642532 [Byte1]: 65
8715 09:31:40.646526
8716 09:31:40.646936 Set Vref, RX VrefLevel [Byte0]: 66
8717 09:31:40.649803 [Byte1]: 66
8718 09:31:40.654947
8719 09:31:40.655354 Set Vref, RX VrefLevel [Byte0]: 67
8720 09:31:40.657502 [Byte1]: 67
8721 09:31:40.662294
8722 09:31:40.662583 Set Vref, RX VrefLevel [Byte0]: 68
8723 09:31:40.665060 [Byte1]: 68
8724 09:31:40.669920
8725 09:31:40.670388 Set Vref, RX VrefLevel [Byte0]: 69
8726 09:31:40.672478 [Byte1]: 69
8727 09:31:40.676940
8728 09:31:40.677359 Set Vref, RX VrefLevel [Byte0]: 70
8729 09:31:40.680097 [Byte1]: 70
8730 09:31:40.684585
8731 09:31:40.685001 Set Vref, RX VrefLevel [Byte0]: 71
8732 09:31:40.688094 [Byte1]: 71
8733 09:31:40.692577
8734 09:31:40.692958 Set Vref, RX VrefLevel [Byte0]: 72
8735 09:31:40.695738 [Byte1]: 72
8736 09:31:40.700053
8737 09:31:40.702947 Set Vref, RX VrefLevel [Byte0]: 73
8738 09:31:40.706275 [Byte1]: 73
8739 09:31:40.706569
8740 09:31:40.709593 Set Vref, RX VrefLevel [Byte0]: 74
8741 09:31:40.713344 [Byte1]: 74
8742 09:31:40.713641
8743 09:31:40.716665 Final RX Vref Byte 0 = 52 to rank0
8744 09:31:40.719414 Final RX Vref Byte 1 = 58 to rank0
8745 09:31:40.722805 Final RX Vref Byte 0 = 52 to rank1
8746 09:31:40.725855 Final RX Vref Byte 1 = 58 to rank1==
8747 09:31:40.729414 Dram Type= 6, Freq= 0, CH_1, rank 0
8748 09:31:40.732704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 09:31:40.732994 ==
8750 09:31:40.736040 DQS Delay:
8751 09:31:40.736327 DQS0 = 0, DQS1 = 0
8752 09:31:40.739030 DQM Delay:
8753 09:31:40.739251 DQM0 = 133, DQM1 = 127
8754 09:31:40.739426 DQ Delay:
8755 09:31:40.745766 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8756 09:31:40.749049 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8757 09:31:40.752418 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8758 09:31:40.755713 DQ12 =134, DQ13 =136, DQ14 =136, DQ15 =138
8759 09:31:40.755934
8760 09:31:40.756109
8761 09:31:40.756271
8762 09:31:40.758850 [DramC_TX_OE_Calibration] TA2
8763 09:31:40.762443 Original DQ_B0 (3 6) =30, OEN = 27
8764 09:31:40.765870 Original DQ_B1 (3 6) =30, OEN = 27
8765 09:31:40.766090 24, 0x0, End_B0=24 End_B1=24
8766 09:31:40.768852 25, 0x0, End_B0=25 End_B1=25
8767 09:31:40.772532 26, 0x0, End_B0=26 End_B1=26
8768 09:31:40.775591 27, 0x0, End_B0=27 End_B1=27
8769 09:31:40.778695 28, 0x0, End_B0=28 End_B1=28
8770 09:31:40.779052 29, 0x0, End_B0=29 End_B1=29
8771 09:31:40.782136 30, 0x0, End_B0=30 End_B1=30
8772 09:31:40.785691 31, 0x4141, End_B0=30 End_B1=30
8773 09:31:40.788877 Byte0 end_step=30 best_step=27
8774 09:31:40.792029 Byte1 end_step=30 best_step=27
8775 09:31:40.795360 Byte0 TX OE(2T, 0.5T) = (3, 3)
8776 09:31:40.795773 Byte1 TX OE(2T, 0.5T) = (3, 3)
8777 09:31:40.796106
8778 09:31:40.798816
8779 09:31:40.805301 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8780 09:31:40.808477 CH1 RK0: MR19=303, MR18=1A0F
8781 09:31:40.815437 CH1_RK0: MR19=0x303, MR18=0x1A0F, DQSOSC=396, MR23=63, INC=23, DEC=15
8782 09:31:40.815851
8783 09:31:40.818411 ----->DramcWriteLeveling(PI) begin...
8784 09:31:40.818833 ==
8785 09:31:40.821726 Dram Type= 6, Freq= 0, CH_1, rank 1
8786 09:31:40.825134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8787 09:31:40.825429 ==
8788 09:31:40.828009 Write leveling (Byte 0): 24 => 24
8789 09:31:40.831370 Write leveling (Byte 1): 27 => 27
8790 09:31:40.835195 DramcWriteLeveling(PI) end<-----
8791 09:31:40.835488
8792 09:31:40.835727 ==
8793 09:31:40.838252 Dram Type= 6, Freq= 0, CH_1, rank 1
8794 09:31:40.841291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 09:31:40.841587 ==
8796 09:31:40.844420 [Gating] SW mode calibration
8797 09:31:40.850760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8798 09:31:40.857363 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8799 09:31:40.861022 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 09:31:40.867453 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 09:31:40.870471 1 4 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8802 09:31:40.874392 1 4 12 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8803 09:31:40.880798 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 09:31:40.883856 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 09:31:40.887780 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 09:31:40.894050 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 09:31:40.896968 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 09:31:40.900430 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 09:31:40.906845 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8810 09:31:40.910070 1 5 12 | B1->B0 | 2727 3434 | 0 1 | (0 1) (1 0)
8811 09:31:40.913662 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8812 09:31:40.919730 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 09:31:40.923665 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 09:31:40.926654 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 09:31:40.933111 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 09:31:40.936580 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 09:31:40.939872 1 6 8 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
8818 09:31:40.946643 1 6 12 | B1->B0 | 4545 2424 | 0 0 | (0 0) (0 0)
8819 09:31:40.949529 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 09:31:40.953303 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 09:31:40.959479 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 09:31:40.962776 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 09:31:40.966076 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 09:31:40.972803 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 09:31:40.976062 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8826 09:31:40.979573 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8827 09:31:40.986074 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8828 09:31:40.989310 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 09:31:40.992762 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 09:31:40.999165 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 09:31:41.002240 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 09:31:41.005606 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 09:31:41.012190 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 09:31:41.015407 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 09:31:41.019040 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 09:31:41.025202 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 09:31:41.028749 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 09:31:41.031804 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 09:31:41.038696 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 09:31:41.042311 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 09:31:41.045559 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8842 09:31:41.052269 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8843 09:31:41.055126 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 09:31:41.058438 Total UI for P1: 0, mck2ui 16
8845 09:31:41.061998 best dqsien dly found for B0: ( 1, 9, 12)
8846 09:31:41.065187 Total UI for P1: 0, mck2ui 16
8847 09:31:41.068706 best dqsien dly found for B1: ( 1, 9, 10)
8848 09:31:41.071701 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8849 09:31:41.074931 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8850 09:31:41.075011
8851 09:31:41.078005 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8852 09:31:41.081502 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8853 09:31:41.084566 [Gating] SW calibration Done
8854 09:31:41.084681 ==
8855 09:31:41.088325 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 09:31:41.091491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 09:31:41.094914 ==
8858 09:31:41.094997 RX Vref Scan: 0
8859 09:31:41.095061
8860 09:31:41.097896 RX Vref 0 -> 0, step: 1
8861 09:31:41.098000
8862 09:31:41.101444 RX Delay 0 -> 252, step: 8
8863 09:31:41.105038 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8864 09:31:41.107742 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8865 09:31:41.111307 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8866 09:31:41.114490 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8867 09:31:41.121087 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8868 09:31:41.124122 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8869 09:31:41.127695 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8870 09:31:41.130948 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8871 09:31:41.134019 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8872 09:31:41.140693 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8873 09:31:41.144003 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8874 09:31:41.147244 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8875 09:31:41.150519 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8876 09:31:41.154097 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8877 09:31:41.160977 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8878 09:31:41.163978 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8879 09:31:41.164080 ==
8880 09:31:41.167457 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 09:31:41.170944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 09:31:41.171072 ==
8883 09:31:41.174181 DQS Delay:
8884 09:31:41.174318 DQS0 = 0, DQS1 = 0
8885 09:31:41.177682 DQM Delay:
8886 09:31:41.177840 DQM0 = 136, DQM1 = 129
8887 09:31:41.177925 DQ Delay:
8888 09:31:41.180450 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8889 09:31:41.186864 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8890 09:31:41.190503 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8891 09:31:41.193435 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8892 09:31:41.193516
8893 09:31:41.193578
8894 09:31:41.193636 ==
8895 09:31:41.196624 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 09:31:41.199976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 09:31:41.200057 ==
8898 09:31:41.200120
8899 09:31:41.200178
8900 09:31:41.203326 TX Vref Scan disable
8901 09:31:41.206683 == TX Byte 0 ==
8902 09:31:41.210092 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8903 09:31:41.213513 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8904 09:31:41.217087 == TX Byte 1 ==
8905 09:31:41.220049 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8906 09:31:41.223143 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8907 09:31:41.223225 ==
8908 09:31:41.226663 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 09:31:41.233323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 09:31:41.233418 ==
8911 09:31:41.244744
8912 09:31:41.248085 TX Vref early break, caculate TX vref
8913 09:31:41.251563 TX Vref=16, minBit 1, minWin=22, winSum=387
8914 09:31:41.254390 TX Vref=18, minBit 0, minWin=24, winSum=397
8915 09:31:41.257689 TX Vref=20, minBit 0, minWin=24, winSum=406
8916 09:31:41.260919 TX Vref=22, minBit 0, minWin=24, winSum=409
8917 09:31:41.264119 TX Vref=24, minBit 0, minWin=25, winSum=419
8918 09:31:41.271072 TX Vref=26, minBit 0, minWin=26, winSum=427
8919 09:31:41.274197 TX Vref=28, minBit 0, minWin=25, winSum=421
8920 09:31:41.277375 TX Vref=30, minBit 1, minWin=23, winSum=414
8921 09:31:41.280873 TX Vref=32, minBit 0, minWin=25, winSum=410
8922 09:31:41.284286 TX Vref=34, minBit 0, minWin=23, winSum=398
8923 09:31:41.290785 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
8924 09:31:41.290941
8925 09:31:41.294135 Final TX Range 0 Vref 26
8926 09:31:41.294292
8927 09:31:41.294384 ==
8928 09:31:41.297147 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 09:31:41.300606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 09:31:41.300694 ==
8931 09:31:41.300759
8932 09:31:41.300819
8933 09:31:41.304009 TX Vref Scan disable
8934 09:31:41.310872 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8935 09:31:41.310954 == TX Byte 0 ==
8936 09:31:41.314018 u2DelayCellOfst[0]=22 cells (6 PI)
8937 09:31:41.317659 u2DelayCellOfst[1]=11 cells (3 PI)
8938 09:31:41.320461 u2DelayCellOfst[2]=0 cells (0 PI)
8939 09:31:41.323987 u2DelayCellOfst[3]=7 cells (2 PI)
8940 09:31:41.327233 u2DelayCellOfst[4]=7 cells (2 PI)
8941 09:31:41.330759 u2DelayCellOfst[5]=22 cells (6 PI)
8942 09:31:41.334149 u2DelayCellOfst[6]=22 cells (6 PI)
8943 09:31:41.337038 u2DelayCellOfst[7]=3 cells (1 PI)
8944 09:31:41.340355 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8945 09:31:41.343893 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8946 09:31:41.347002 == TX Byte 1 ==
8947 09:31:41.350377 u2DelayCellOfst[8]=0 cells (0 PI)
8948 09:31:41.350457 u2DelayCellOfst[9]=7 cells (2 PI)
8949 09:31:41.353904 u2DelayCellOfst[10]=14 cells (4 PI)
8950 09:31:41.357348 u2DelayCellOfst[11]=7 cells (2 PI)
8951 09:31:41.360647 u2DelayCellOfst[12]=18 cells (5 PI)
8952 09:31:41.363426 u2DelayCellOfst[13]=18 cells (5 PI)
8953 09:31:41.367145 u2DelayCellOfst[14]=22 cells (6 PI)
8954 09:31:41.370133 u2DelayCellOfst[15]=18 cells (5 PI)
8955 09:31:41.373684 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8956 09:31:41.380357 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8957 09:31:41.380438 DramC Write-DBI on
8958 09:31:41.380500 ==
8959 09:31:41.383288 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 09:31:41.389858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 09:31:41.389948 ==
8962 09:31:41.390012
8963 09:31:41.390071
8964 09:31:41.390127 TX Vref Scan disable
8965 09:31:41.394074 == TX Byte 0 ==
8966 09:31:41.396893 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8967 09:31:41.400456 == TX Byte 1 ==
8968 09:31:41.403886 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8969 09:31:41.406745 DramC Write-DBI off
8970 09:31:41.406853
8971 09:31:41.406955 [DATLAT]
8972 09:31:41.407057 Freq=1600, CH1 RK1
8973 09:31:41.407154
8974 09:31:41.410595 DATLAT Default: 0xf
8975 09:31:41.413860 0, 0xFFFF, sum = 0
8976 09:31:41.413945 1, 0xFFFF, sum = 0
8977 09:31:41.416865 2, 0xFFFF, sum = 0
8978 09:31:41.416949 3, 0xFFFF, sum = 0
8979 09:31:41.420227 4, 0xFFFF, sum = 0
8980 09:31:41.420337 5, 0xFFFF, sum = 0
8981 09:31:41.423874 6, 0xFFFF, sum = 0
8982 09:31:41.423958 7, 0xFFFF, sum = 0
8983 09:31:41.426856 8, 0xFFFF, sum = 0
8984 09:31:41.426941 9, 0xFFFF, sum = 0
8985 09:31:41.430041 10, 0xFFFF, sum = 0
8986 09:31:41.430150 11, 0xFFFF, sum = 0
8987 09:31:41.433423 12, 0xFFFF, sum = 0
8988 09:31:41.433507 13, 0xFFFF, sum = 0
8989 09:31:41.436699 14, 0x0, sum = 1
8990 09:31:41.436809 15, 0x0, sum = 2
8991 09:31:41.439501 16, 0x0, sum = 3
8992 09:31:41.439589 17, 0x0, sum = 4
8993 09:31:41.443044 best_step = 15
8994 09:31:41.443129
8995 09:31:41.443193 ==
8996 09:31:41.446373 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 09:31:41.450110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 09:31:41.450230 ==
8999 09:31:41.453053 RX Vref Scan: 0
9000 09:31:41.453133
9001 09:31:41.453197 RX Vref 0 -> 0, step: 1
9002 09:31:41.453256
9003 09:31:41.456524 RX Delay 11 -> 252, step: 4
9004 09:31:41.463126 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9005 09:31:41.466492 iDelay=203, Bit 1, Center 126 (75 ~ 178) 104
9006 09:31:41.469410 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9007 09:31:41.472598 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9008 09:31:41.475978 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9009 09:31:41.483164 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9010 09:31:41.485846 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9011 09:31:41.489641 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9012 09:31:41.492576 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9013 09:31:41.496153 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9014 09:31:41.503296 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9015 09:31:41.506137 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9016 09:31:41.509293 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9017 09:31:41.512197 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9018 09:31:41.519341 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9019 09:31:41.522496 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9020 09:31:41.522580 ==
9021 09:31:41.525558 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 09:31:41.528759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 09:31:41.528845 ==
9024 09:31:41.532432 DQS Delay:
9025 09:31:41.532516 DQS0 = 0, DQS1 = 0
9026 09:31:41.532600 DQM Delay:
9027 09:31:41.535845 DQM0 = 133, DQM1 = 126
9028 09:31:41.535928 DQ Delay:
9029 09:31:41.538673 DQ0 =138, DQ1 =126, DQ2 =122, DQ3 =130
9030 09:31:41.542024 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9031 09:31:41.548645 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =118
9032 09:31:41.551944 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9033 09:31:41.552054
9034 09:31:41.552139
9035 09:31:41.552218
9036 09:31:41.555489 [DramC_TX_OE_Calibration] TA2
9037 09:31:41.558502 Original DQ_B0 (3 6) =30, OEN = 27
9038 09:31:41.561924 Original DQ_B1 (3 6) =30, OEN = 27
9039 09:31:41.562008 24, 0x0, End_B0=24 End_B1=24
9040 09:31:41.565215 25, 0x0, End_B0=25 End_B1=25
9041 09:31:41.568186 26, 0x0, End_B0=26 End_B1=26
9042 09:31:41.571600 27, 0x0, End_B0=27 End_B1=27
9043 09:31:41.571684 28, 0x0, End_B0=28 End_B1=28
9044 09:31:41.574754 29, 0x0, End_B0=29 End_B1=29
9045 09:31:41.578116 30, 0x0, End_B0=30 End_B1=30
9046 09:31:41.581675 31, 0x4141, End_B0=30 End_B1=30
9047 09:31:41.584825 Byte0 end_step=30 best_step=27
9048 09:31:41.588011 Byte1 end_step=30 best_step=27
9049 09:31:41.588092 Byte0 TX OE(2T, 0.5T) = (3, 3)
9050 09:31:41.591413 Byte1 TX OE(2T, 0.5T) = (3, 3)
9051 09:31:41.591529
9052 09:31:41.591620
9053 09:31:41.601830 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
9054 09:31:41.604776 CH1 RK1: MR19=303, MR18=D0A
9055 09:31:41.607996 CH1_RK1: MR19=0x303, MR18=0xD0A, DQSOSC=403, MR23=63, INC=22, DEC=15
9056 09:31:41.611142 [RxdqsGatingPostProcess] freq 1600
9057 09:31:41.618076 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9058 09:31:41.621496 best DQS0 dly(2T, 0.5T) = (1, 1)
9059 09:31:41.624543 best DQS1 dly(2T, 0.5T) = (1, 1)
9060 09:31:41.627771 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9061 09:31:41.630943 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9062 09:31:41.634548 best DQS0 dly(2T, 0.5T) = (1, 1)
9063 09:31:41.637726 best DQS1 dly(2T, 0.5T) = (1, 1)
9064 09:31:41.637806 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9065 09:31:41.641321 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9066 09:31:41.644118 Pre-setting of DQS Precalculation
9067 09:31:41.651084 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9068 09:31:41.657418 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9069 09:31:41.664239 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9070 09:31:41.664320
9071 09:31:41.664383
9072 09:31:41.667804 [Calibration Summary] 3200 Mbps
9073 09:31:41.670900 CH 0, Rank 0
9074 09:31:41.670980 SW Impedance : PASS
9075 09:31:41.674298 DUTY Scan : NO K
9076 09:31:41.677422 ZQ Calibration : PASS
9077 09:31:41.677502 Jitter Meter : NO K
9078 09:31:41.680550 CBT Training : PASS
9079 09:31:41.680629 Write leveling : PASS
9080 09:31:41.684028 RX DQS gating : PASS
9081 09:31:41.687462 RX DQ/DQS(RDDQC) : PASS
9082 09:31:41.687542 TX DQ/DQS : PASS
9083 09:31:41.690871 RX DATLAT : PASS
9084 09:31:41.693855 RX DQ/DQS(Engine): PASS
9085 09:31:41.693934 TX OE : PASS
9086 09:31:41.697239 All Pass.
9087 09:31:41.697319
9088 09:31:41.697382 CH 0, Rank 1
9089 09:31:41.700843 SW Impedance : PASS
9090 09:31:41.700923 DUTY Scan : NO K
9091 09:31:41.703759 ZQ Calibration : PASS
9092 09:31:41.707246 Jitter Meter : NO K
9093 09:31:41.707325 CBT Training : PASS
9094 09:31:41.710107 Write leveling : PASS
9095 09:31:41.713610 RX DQS gating : PASS
9096 09:31:41.713690 RX DQ/DQS(RDDQC) : PASS
9097 09:31:41.717088 TX DQ/DQS : PASS
9098 09:31:41.720213 RX DATLAT : PASS
9099 09:31:41.720292 RX DQ/DQS(Engine): PASS
9100 09:31:41.723783 TX OE : PASS
9101 09:31:41.723863 All Pass.
9102 09:31:41.723926
9103 09:31:41.726714 CH 1, Rank 0
9104 09:31:41.726793 SW Impedance : PASS
9105 09:31:41.730081 DUTY Scan : NO K
9106 09:31:41.733394 ZQ Calibration : PASS
9107 09:31:41.733474 Jitter Meter : NO K
9108 09:31:41.736818 CBT Training : PASS
9109 09:31:41.740029 Write leveling : PASS
9110 09:31:41.740108 RX DQS gating : PASS
9111 09:31:41.743111 RX DQ/DQS(RDDQC) : PASS
9112 09:31:41.746929 TX DQ/DQS : PASS
9113 09:31:41.747010 RX DATLAT : PASS
9114 09:31:41.749723 RX DQ/DQS(Engine): PASS
9115 09:31:41.749803 TX OE : PASS
9116 09:31:41.753234 All Pass.
9117 09:31:41.753313
9118 09:31:41.753375 CH 1, Rank 1
9119 09:31:41.756704 SW Impedance : PASS
9120 09:31:41.756784 DUTY Scan : NO K
9121 09:31:41.760079 ZQ Calibration : PASS
9122 09:31:41.763019 Jitter Meter : NO K
9123 09:31:41.763098 CBT Training : PASS
9124 09:31:41.766468 Write leveling : PASS
9125 09:31:41.769792 RX DQS gating : PASS
9126 09:31:41.769872 RX DQ/DQS(RDDQC) : PASS
9127 09:31:41.773385 TX DQ/DQS : PASS
9128 09:31:41.776138 RX DATLAT : PASS
9129 09:31:41.776218 RX DQ/DQS(Engine): PASS
9130 09:31:41.779721 TX OE : PASS
9131 09:31:41.779801 All Pass.
9132 09:31:41.779863
9133 09:31:41.783151 DramC Write-DBI on
9134 09:31:41.786597 PER_BANK_REFRESH: Hybrid Mode
9135 09:31:41.786678 TX_TRACKING: ON
9136 09:31:41.796460 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9137 09:31:41.802944 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9138 09:31:41.809618 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9139 09:31:41.816072 [FAST_K] Save calibration result to emmc
9140 09:31:41.816152 sync common calibartion params.
9141 09:31:41.819003 sync cbt_mode0:1, 1:1
9142 09:31:41.822525 dram_init: ddr_geometry: 2
9143 09:31:41.822604 dram_init: ddr_geometry: 2
9144 09:31:41.825948 dram_init: ddr_geometry: 2
9145 09:31:41.829402 0:dram_rank_size:100000000
9146 09:31:41.832346 1:dram_rank_size:100000000
9147 09:31:41.835486 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9148 09:31:41.839020 DFS_SHUFFLE_HW_MODE: ON
9149 09:31:41.842400 dramc_set_vcore_voltage set vcore to 725000
9150 09:31:41.845695 Read voltage for 1600, 0
9151 09:31:41.845775 Vio18 = 0
9152 09:31:41.849059 Vcore = 725000
9153 09:31:41.849139 Vdram = 0
9154 09:31:41.849201 Vddq = 0
9155 09:31:41.849260 Vmddr = 0
9156 09:31:41.852213 switch to 3200 Mbps bootup
9157 09:31:41.855726 [DramcRunTimeConfig]
9158 09:31:41.855805 PHYPLL
9159 09:31:41.858890 DPM_CONTROL_AFTERK: ON
9160 09:31:41.858969 PER_BANK_REFRESH: ON
9161 09:31:41.861972 REFRESH_OVERHEAD_REDUCTION: ON
9162 09:31:41.865596 CMD_PICG_NEW_MODE: OFF
9163 09:31:41.865676 XRTWTW_NEW_MODE: ON
9164 09:31:41.868327 XRTRTR_NEW_MODE: ON
9165 09:31:41.868407 TX_TRACKING: ON
9166 09:31:41.872235 RDSEL_TRACKING: OFF
9167 09:31:41.875126 DQS Precalculation for DVFS: ON
9168 09:31:41.875205 RX_TRACKING: OFF
9169 09:31:41.878661 HW_GATING DBG: ON
9170 09:31:41.878740 ZQCS_ENABLE_LP4: ON
9171 09:31:41.882109 RX_PICG_NEW_MODE: ON
9172 09:31:41.882226 TX_PICG_NEW_MODE: ON
9173 09:31:41.885124 ENABLE_RX_DCM_DPHY: ON
9174 09:31:41.888684 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9175 09:31:41.892403 DUMMY_READ_FOR_TRACKING: OFF
9176 09:31:41.892499 !!! SPM_CONTROL_AFTERK: OFF
9177 09:31:41.895524 !!! SPM could not control APHY
9178 09:31:41.898650 IMPEDANCE_TRACKING: ON
9179 09:31:41.898730 TEMP_SENSOR: ON
9180 09:31:41.901669 HW_SAVE_FOR_SR: OFF
9181 09:31:41.904931 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9182 09:31:41.908341 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9183 09:31:41.908422 Read ODT Tracking: ON
9184 09:31:41.911446 Refresh Rate DeBounce: ON
9185 09:31:41.914949 DFS_NO_QUEUE_FLUSH: ON
9186 09:31:41.918974 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9187 09:31:41.919054 ENABLE_DFS_RUNTIME_MRW: OFF
9188 09:31:41.921813 DDR_RESERVE_NEW_MODE: ON
9189 09:31:41.925122 MR_CBT_SWITCH_FREQ: ON
9190 09:31:41.925202 =========================
9191 09:31:41.945486 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9192 09:31:41.948338 dram_init: ddr_geometry: 2
9193 09:31:41.966746 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9194 09:31:41.970092 dram_init: dram init end (result: 0)
9195 09:31:41.976815 DRAM-K: Full calibration passed in 24626 msecs
9196 09:31:41.980268 MRC: failed to locate region type 0.
9197 09:31:41.980348 DRAM rank0 size:0x100000000,
9198 09:31:41.983490 DRAM rank1 size=0x100000000
9199 09:31:41.993342 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9200 09:31:42.000068 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9201 09:31:42.006137 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9202 09:31:42.016323 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9203 09:31:42.016404 DRAM rank0 size:0x100000000,
9204 09:31:42.019345 DRAM rank1 size=0x100000000
9205 09:31:42.019425 CBMEM:
9206 09:31:42.022678 IMD: root @ 0xfffff000 254 entries.
9207 09:31:42.025993 IMD: root @ 0xffffec00 62 entries.
9208 09:31:42.029336 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9209 09:31:42.036013 WARNING: RO_VPD is uninitialized or empty.
9210 09:31:42.038980 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9211 09:31:42.046568 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9212 09:31:42.059623 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9213 09:31:42.070901 BS: romstage times (exec / console): total (unknown) / 24118 ms
9214 09:31:42.070984
9215 09:31:42.071047
9216 09:31:42.080997 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9217 09:31:42.084135 ARM64: Exception handlers installed.
9218 09:31:42.087501 ARM64: Testing exception
9219 09:31:42.090493 ARM64: Done test exception
9220 09:31:42.090574 Enumerating buses...
9221 09:31:42.094029 Show all devs... Before device enumeration.
9222 09:31:42.097182 Root Device: enabled 1
9223 09:31:42.100940 CPU_CLUSTER: 0: enabled 1
9224 09:31:42.101020 CPU: 00: enabled 1
9225 09:31:42.103791 Compare with tree...
9226 09:31:42.103871 Root Device: enabled 1
9227 09:31:42.107137 CPU_CLUSTER: 0: enabled 1
9228 09:31:42.110595 CPU: 00: enabled 1
9229 09:31:42.110675 Root Device scanning...
9230 09:31:42.113787 scan_static_bus for Root Device
9231 09:31:42.117232 CPU_CLUSTER: 0 enabled
9232 09:31:42.120371 scan_static_bus for Root Device done
9233 09:31:42.123748 scan_bus: bus Root Device finished in 8 msecs
9234 09:31:42.123829 done
9235 09:31:42.130119 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9236 09:31:42.133499 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9237 09:31:42.140487 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9238 09:31:42.146908 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9239 09:31:42.146988 Allocating resources...
9240 09:31:42.150125 Reading resources...
9241 09:31:42.153118 Root Device read_resources bus 0 link: 0
9242 09:31:42.156582 DRAM rank0 size:0x100000000,
9243 09:31:42.156661 DRAM rank1 size=0x100000000
9244 09:31:42.162866 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9245 09:31:42.162946 CPU: 00 missing read_resources
9246 09:31:42.169928 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9247 09:31:42.173185 Root Device read_resources bus 0 link: 0 done
9248 09:31:42.176482 Done reading resources.
9249 09:31:42.179510 Show resources in subtree (Root Device)...After reading.
9250 09:31:42.183301 Root Device child on link 0 CPU_CLUSTER: 0
9251 09:31:42.186463 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 09:31:42.196226 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 09:31:42.196310 CPU: 00
9254 09:31:42.202711 Root Device assign_resources, bus 0 link: 0
9255 09:31:42.205712 CPU_CLUSTER: 0 missing set_resources
9256 09:31:42.209293 Root Device assign_resources, bus 0 link: 0 done
9257 09:31:42.212541 Done setting resources.
9258 09:31:42.215717 Show resources in subtree (Root Device)...After assigning values.
9259 09:31:42.219381 Root Device child on link 0 CPU_CLUSTER: 0
9260 09:31:42.225844 CPU_CLUSTER: 0 child on link 0 CPU: 00
9261 09:31:42.232134 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9262 09:31:42.235466 CPU: 00
9263 09:31:42.235546 Done allocating resources.
9264 09:31:42.242127 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9265 09:31:42.242257 Enabling resources...
9266 09:31:42.245732 done.
9267 09:31:42.248687 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9268 09:31:42.251920 Initializing devices...
9269 09:31:42.252003 Root Device init
9270 09:31:42.255280 init hardware done!
9271 09:31:42.255363 0x00000018: ctrlr->caps
9272 09:31:42.258857 52.000 MHz: ctrlr->f_max
9273 09:31:42.261603 0.400 MHz: ctrlr->f_min
9274 09:31:42.265215 0x40ff8080: ctrlr->voltages
9275 09:31:42.265300 sclk: 390625
9276 09:31:42.265384 Bus Width = 1
9277 09:31:42.268478 sclk: 390625
9278 09:31:42.268562 Bus Width = 1
9279 09:31:42.271892 Early init status = 3
9280 09:31:42.275038 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9281 09:31:42.278351 in-header: 03 fc 00 00 01 00 00 00
9282 09:31:42.281721 in-data: 00
9283 09:31:42.285561 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9284 09:31:42.289573 in-header: 03 fd 00 00 00 00 00 00
9285 09:31:42.292924 in-data:
9286 09:31:42.296595 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9287 09:31:42.299996 in-header: 03 fc 00 00 01 00 00 00
9288 09:31:42.303421 in-data: 00
9289 09:31:42.306270 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9290 09:31:42.311968 in-header: 03 fd 00 00 00 00 00 00
9291 09:31:42.315119 in-data:
9292 09:31:42.318489 [SSUSB] Setting up USB HOST controller...
9293 09:31:42.321833 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9294 09:31:42.324977 [SSUSB] phy power-on done.
9295 09:31:42.328362 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9296 09:31:42.335134 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9297 09:31:42.338217 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9298 09:31:42.345061 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9299 09:31:42.351226 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9300 09:31:42.358096 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9301 09:31:42.364929 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9302 09:31:42.371639 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9303 09:31:42.374392 SPM: binary array size = 0x9dc
9304 09:31:42.377906 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9305 09:31:42.384529 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9306 09:31:42.390884 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9307 09:31:42.397548 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9308 09:31:42.400679 configure_display: Starting display init
9309 09:31:42.435342 anx7625_power_on_init: Init interface.
9310 09:31:42.438365 anx7625_disable_pd_protocol: Disabled PD feature.
9311 09:31:42.441941 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9312 09:31:42.469620 anx7625_start_dp_work: Secure OCM version=00
9313 09:31:42.473149 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9314 09:31:42.487730 sp_tx_get_edid_block: EDID Block = 1
9315 09:31:42.590228 Extracted contents:
9316 09:31:42.593656 header: 00 ff ff ff ff ff ff 00
9317 09:31:42.597163 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9318 09:31:42.600408 version: 01 04
9319 09:31:42.603507 basic params: 95 1f 11 78 0a
9320 09:31:42.606458 chroma info: 76 90 94 55 54 90 27 21 50 54
9321 09:31:42.610055 established: 00 00 00
9322 09:31:42.616730 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9323 09:31:42.623458 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9324 09:31:42.626629 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9325 09:31:42.632924 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9326 09:31:42.639318 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9327 09:31:42.642572 extensions: 00
9328 09:31:42.642651 checksum: fb
9329 09:31:42.642714
9330 09:31:42.649275 Manufacturer: IVO Model 57d Serial Number 0
9331 09:31:42.649356 Made week 0 of 2020
9332 09:31:42.652783 EDID version: 1.4
9333 09:31:42.652888 Digital display
9334 09:31:42.656016 6 bits per primary color channel
9335 09:31:42.659186 DisplayPort interface
9336 09:31:42.659266 Maximum image size: 31 cm x 17 cm
9337 09:31:42.662570 Gamma: 220%
9338 09:31:42.662649 Check DPMS levels
9339 09:31:42.669088 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9340 09:31:42.672405 First detailed timing is preferred timing
9341 09:31:42.675647 Established timings supported:
9342 09:31:42.675726 Standard timings supported:
9343 09:31:42.678820 Detailed timings
9344 09:31:42.683110 Hex of detail: 383680a07038204018303c0035ae10000019
9345 09:31:42.689108 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9346 09:31:42.692647 0780 0798 07c8 0820 hborder 0
9347 09:31:42.695718 0438 043b 0447 0458 vborder 0
9348 09:31:42.698376 -hsync -vsync
9349 09:31:42.698456 Did detailed timing
9350 09:31:42.705946 Hex of detail: 000000000000000000000000000000000000
9351 09:31:42.708502 Manufacturer-specified data, tag 0
9352 09:31:42.711677 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9353 09:31:42.714914 ASCII string: InfoVision
9354 09:31:42.718416 Hex of detail: 000000fe00523134304e574635205248200a
9355 09:31:42.721464 ASCII string: R140NWF5 RH
9356 09:31:42.721543 Checksum
9357 09:31:42.724923 Checksum: 0xfb (valid)
9358 09:31:42.728497 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9359 09:31:42.731451 DSI data_rate: 832800000 bps
9360 09:31:42.738169 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9361 09:31:42.741867 anx7625_parse_edid: pixelclock(138800).
9362 09:31:42.744610 hactive(1920), hsync(48), hfp(24), hbp(88)
9363 09:31:42.748290 vactive(1080), vsync(12), vfp(3), vbp(17)
9364 09:31:42.751078 anx7625_dsi_config: config dsi.
9365 09:31:42.757898 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9366 09:31:42.772506 anx7625_dsi_config: success to config DSI
9367 09:31:42.775362 anx7625_dp_start: MIPI phy setup OK.
9368 09:31:42.778934 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9369 09:31:42.782306 mtk_ddp_mode_set invalid vrefresh 60
9370 09:31:42.785656 main_disp_path_setup
9371 09:31:42.785736 ovl_layer_smi_id_en
9372 09:31:42.788707 ovl_layer_smi_id_en
9373 09:31:42.788788 ccorr_config
9374 09:31:42.788851 aal_config
9375 09:31:42.791896 gamma_config
9376 09:31:42.791976 postmask_config
9377 09:31:42.795161 dither_config
9378 09:31:42.798873 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9379 09:31:42.805269 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9380 09:31:42.808599 Root Device init finished in 552 msecs
9381 09:31:42.811866 CPU_CLUSTER: 0 init
9382 09:31:42.818436 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9383 09:31:42.825299 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9384 09:31:42.825379 APU_MBOX 0x190000b0 = 0x10001
9385 09:31:42.827996 APU_MBOX 0x190001b0 = 0x10001
9386 09:31:42.831508 APU_MBOX 0x190005b0 = 0x10001
9387 09:31:42.834931 APU_MBOX 0x190006b0 = 0x10001
9388 09:31:42.841387 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9389 09:31:42.851071 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9390 09:31:42.863960 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9391 09:31:42.870232 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9392 09:31:42.882123 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9393 09:31:42.890991 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9394 09:31:42.894170 CPU_CLUSTER: 0 init finished in 81 msecs
9395 09:31:42.897506 Devices initialized
9396 09:31:42.901069 Show all devs... After init.
9397 09:31:42.901154 Root Device: enabled 1
9398 09:31:42.904169 CPU_CLUSTER: 0: enabled 1
9399 09:31:42.907739 CPU: 00: enabled 1
9400 09:31:42.910786 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9401 09:31:42.914143 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9402 09:31:42.917755 ELOG: NV offset 0x57f000 size 0x1000
9403 09:31:42.923983 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9404 09:31:42.930738 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9405 09:31:42.934198 ELOG: Event(17) added with size 13 at 2024-06-18 09:31:42 UTC
9406 09:31:42.940391 out: cmd=0x121: 03 db 21 01 00 00 00 00
9407 09:31:42.943944 in-header: 03 62 00 00 2c 00 00 00
9408 09:31:42.957291 in-data: dc 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9409 09:31:42.960112 ELOG: Event(A1) added with size 10 at 2024-06-18 09:31:42 UTC
9410 09:31:42.970166 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9411 09:31:42.973667 ELOG: Event(A0) added with size 9 at 2024-06-18 09:31:42 UTC
9412 09:31:42.979991 ELOG: Event(16) added with size 11 at 2024-06-18 09:31:42 UTC
9413 09:31:43.062131 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9414 09:31:43.065827 elog_add_boot_reason: Logged dev mode boot
9415 09:31:43.072075 BS: BS_POST_DEVICE entry times (exec / console): 81 / 74 ms
9416 09:31:43.072156 Finalize devices...
9417 09:31:43.075439 Devices finalized
9418 09:31:43.078414 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9419 09:31:43.081832 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9420 09:31:43.085358 in-header: 03 07 00 00 08 00 00 00
9421 09:31:43.088769 in-data: aa e4 47 04 13 02 00 00
9422 09:31:43.091781 Chrome EC: UHEPI supported
9423 09:31:43.098451 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9424 09:31:43.102075 in-header: 03 a9 00 00 08 00 00 00
9425 09:31:43.105015 in-data: 84 60 60 08 00 00 00 00
9426 09:31:43.111918 ELOG: Event(91) added with size 10 at 2024-06-18 09:31:42 UTC
9427 09:31:43.114968 Chrome EC: clear events_b mask to 0x0000000020004000
9428 09:31:43.121596 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9429 09:31:43.125306 in-header: 03 fd 00 00 00 00 00 00
9430 09:31:43.128338 in-data:
9431 09:31:43.131857 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9432 09:31:43.135286 Writing coreboot table at 0xffe64000
9433 09:31:43.138684 0. 000000000010a000-0000000000113fff: RAMSTAGE
9434 09:31:43.145390 1. 0000000040000000-00000000400fffff: RAM
9435 09:31:43.148811 2. 0000000040100000-000000004032afff: RAMSTAGE
9436 09:31:43.151650 3. 000000004032b000-00000000545fffff: RAM
9437 09:31:43.155037 4. 0000000054600000-000000005465ffff: BL31
9438 09:31:43.158718 5. 0000000054660000-00000000ffe63fff: RAM
9439 09:31:43.165288 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9440 09:31:43.168230 7. 0000000100000000-000000023fffffff: RAM
9441 09:31:43.171536 Passing 5 GPIOs to payload:
9442 09:31:43.174970 NAME | PORT | POLARITY | VALUE
9443 09:31:43.181762 EC in RW | 0x000000aa | low | undefined
9444 09:31:43.185176 EC interrupt | 0x00000005 | low | undefined
9445 09:31:43.188112 TPM interrupt | 0x000000ab | high | undefined
9446 09:31:43.194983 SD card detect | 0x00000011 | high | undefined
9447 09:31:43.197738 speaker enable | 0x00000093 | high | undefined
9448 09:31:43.201066 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9449 09:31:43.204513 in-header: 03 f9 00 00 02 00 00 00
9450 09:31:43.208010 in-data: 02 00
9451 09:31:43.211008 ADC[4]: Raw value=903400 ID=7
9452 09:31:43.214277 ADC[3]: Raw value=214021 ID=1
9453 09:31:43.214356 RAM Code: 0x71
9454 09:31:43.218194 ADC[6]: Raw value=75036 ID=0
9455 09:31:43.221073 ADC[5]: Raw value=212543 ID=1
9456 09:31:43.221151 SKU Code: 0x1
9457 09:31:43.227892 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a279
9458 09:31:43.227972 coreboot table: 964 bytes.
9459 09:31:43.230918 IMD ROOT 0. 0xfffff000 0x00001000
9460 09:31:43.234420 IMD SMALL 1. 0xffffe000 0x00001000
9461 09:31:43.237438 RO MCACHE 2. 0xffffc000 0x00001104
9462 09:31:43.240769 CONSOLE 3. 0xfff7c000 0x00080000
9463 09:31:43.243944 FMAP 4. 0xfff7b000 0x00000452
9464 09:31:43.247410 TIME STAMP 5. 0xfff7a000 0x00000910
9465 09:31:43.250681 VBOOT WORK 6. 0xfff66000 0x00014000
9466 09:31:43.254172 RAMOOPS 7. 0xffe66000 0x00100000
9467 09:31:43.257128 COREBOOT 8. 0xffe64000 0x00002000
9468 09:31:43.260480 IMD small region:
9469 09:31:43.264035 IMD ROOT 0. 0xffffec00 0x00000400
9470 09:31:43.267359 VPD 1. 0xffffeb80 0x0000006c
9471 09:31:43.270367 MMC STATUS 2. 0xffffeb60 0x00000004
9472 09:31:43.277532 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9473 09:31:43.283809 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9474 09:31:43.322059 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9475 09:31:43.325438 Checking segment from ROM address 0x40100000
9476 09:31:43.328966 Checking segment from ROM address 0x4010001c
9477 09:31:43.335613 Loading segment from ROM address 0x40100000
9478 09:31:43.335692 code (compression=0)
9479 09:31:43.345313 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9480 09:31:43.351729 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9481 09:31:43.351809 it's not compressed!
9482 09:31:43.358633 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9483 09:31:43.364878 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9484 09:31:43.382628 Loading segment from ROM address 0x4010001c
9485 09:31:43.382723 Entry Point 0x80000000
9486 09:31:43.386096 Loaded segments
9487 09:31:43.389368 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9488 09:31:43.395711 Jumping to boot code at 0x80000000(0xffe64000)
9489 09:31:43.402482 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9490 09:31:43.409001 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9491 09:31:43.417124 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9492 09:31:43.420543 Checking segment from ROM address 0x40100000
9493 09:31:43.423519 Checking segment from ROM address 0x4010001c
9494 09:31:43.429925 Loading segment from ROM address 0x40100000
9495 09:31:43.430005 code (compression=1)
9496 09:31:43.436383 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9497 09:31:43.446450 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9498 09:31:43.446531 using LZMA
9499 09:31:43.455249 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9500 09:31:43.461654 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9501 09:31:43.465386 Loading segment from ROM address 0x4010001c
9502 09:31:43.465466 Entry Point 0x54601000
9503 09:31:43.468267 Loaded segments
9504 09:31:43.471699 NOTICE: MT8192 bl31_setup
9505 09:31:43.478677 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9506 09:31:43.481993 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9507 09:31:43.485453 WARNING: region 0:
9508 09:31:43.489002 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 09:31:43.489083 WARNING: region 1:
9510 09:31:43.495236 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9511 09:31:43.499187 WARNING: region 2:
9512 09:31:43.501992 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9513 09:31:43.505186 WARNING: region 3:
9514 09:31:43.508432 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9515 09:31:43.512012 WARNING: region 4:
9516 09:31:43.518802 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9517 09:31:43.518892 WARNING: region 5:
9518 09:31:43.522140 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 09:31:43.525068 WARNING: region 6:
9520 09:31:43.528524 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9521 09:31:43.531956 WARNING: region 7:
9522 09:31:43.534735 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 09:31:43.541836 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9524 09:31:43.544918 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9525 09:31:43.551451 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9526 09:31:43.554824 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9527 09:31:43.558345 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9528 09:31:43.564896 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9529 09:31:43.568283 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9530 09:31:43.571430 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9531 09:31:43.578239 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9532 09:31:43.581375 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9533 09:31:43.588022 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9534 09:31:43.591484 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9535 09:31:43.594489 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9536 09:31:43.601239 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9537 09:31:43.604177 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9538 09:31:43.607946 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9539 09:31:43.613943 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9540 09:31:43.617306 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9541 09:31:43.623966 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9542 09:31:43.627401 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9543 09:31:43.630779 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9544 09:31:43.637275 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9545 09:31:43.640528 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9546 09:31:43.647351 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9547 09:31:43.650675 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9548 09:31:43.654099 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9549 09:31:43.661143 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9550 09:31:43.664104 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9551 09:31:43.670337 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9552 09:31:43.673719 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9553 09:31:43.680519 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9554 09:31:43.684086 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9555 09:31:43.686966 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9556 09:31:43.690453 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9557 09:31:43.696731 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9558 09:31:43.700289 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9559 09:31:43.703587 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9560 09:31:43.706742 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9561 09:31:43.713388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9562 09:31:43.716744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9563 09:31:43.720071 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9564 09:31:43.723310 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9565 09:31:43.730070 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9566 09:31:43.733197 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9567 09:31:43.736856 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9568 09:31:43.739716 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9569 09:31:43.746655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9570 09:31:43.749619 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9571 09:31:43.752918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9572 09:31:43.759486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9573 09:31:43.762798 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9574 09:31:43.769460 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9575 09:31:43.773079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9576 09:31:43.779234 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9577 09:31:43.782344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9578 09:31:43.789129 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9579 09:31:43.792360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9580 09:31:43.795903 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9581 09:31:43.802718 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9582 09:31:43.805993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9583 09:31:43.812372 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9584 09:31:43.815375 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9585 09:31:43.822138 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9586 09:31:43.825342 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9587 09:31:43.832054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9588 09:31:43.835629 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9589 09:31:43.841782 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9590 09:31:43.845082 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9591 09:31:43.848760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9592 09:31:43.855149 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9593 09:31:43.858530 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9594 09:31:43.864778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9595 09:31:43.868445 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9596 09:31:43.874730 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9597 09:31:43.878553 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9598 09:31:43.884637 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9599 09:31:43.888241 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9600 09:31:43.891466 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9601 09:31:43.898347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9602 09:31:43.901184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9603 09:31:43.908023 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9604 09:31:43.911187 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9605 09:31:43.917687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9606 09:31:43.921290 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9607 09:31:43.927613 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9608 09:31:43.931132 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9609 09:31:43.934466 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9610 09:31:43.941299 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9611 09:31:43.944132 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9612 09:31:43.950938 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9613 09:31:43.954447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9614 09:31:43.960934 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9615 09:31:43.964293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9616 09:31:43.971127 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9617 09:31:43.974013 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9618 09:31:43.977263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9619 09:31:43.984244 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9620 09:31:43.987100 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9621 09:31:43.990582 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9622 09:31:43.993968 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9623 09:31:44.000354 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9624 09:31:44.003850 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9625 09:31:44.010641 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9626 09:31:44.013701 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9627 09:31:44.017325 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9628 09:31:44.023422 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9629 09:31:44.027336 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9630 09:31:44.033505 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9631 09:31:44.036855 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9632 09:31:44.040347 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9633 09:31:44.046591 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9634 09:31:44.049932 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9635 09:31:44.056823 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9636 09:31:44.060280 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9637 09:31:44.066802 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9638 09:31:44.070062 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9639 09:31:44.073342 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9640 09:31:44.076740 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9641 09:31:44.083043 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9642 09:31:44.086552 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9643 09:31:44.089546 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9644 09:31:44.096358 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9645 09:31:44.099885 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9646 09:31:44.102729 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9647 09:31:44.106136 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9648 09:31:44.112564 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9649 09:31:44.115868 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9650 09:31:44.122812 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9651 09:31:44.125673 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9652 09:31:44.132400 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9653 09:31:44.135968 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9654 09:31:44.138915 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9655 09:31:44.145866 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9656 09:31:44.148683 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9657 09:31:44.155422 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9658 09:31:44.158972 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9659 09:31:44.162444 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9660 09:31:44.168624 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9661 09:31:44.172303 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9662 09:31:44.178573 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9663 09:31:44.181797 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9664 09:31:44.185218 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9665 09:31:44.191965 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9666 09:31:44.194874 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9667 09:31:44.198402 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9668 09:31:44.205302 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9669 09:31:44.208396 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9670 09:31:44.214837 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9671 09:31:44.218449 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9672 09:31:44.225165 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9673 09:31:44.228115 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9674 09:31:44.231537 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9675 09:31:44.238053 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9676 09:31:44.241301 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9677 09:31:44.248062 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9678 09:31:44.251013 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9679 09:31:44.254320 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9680 09:31:44.261032 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9681 09:31:44.264348 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9682 09:31:44.271226 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9683 09:31:44.273913 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9684 09:31:44.277422 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9685 09:31:44.283852 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9686 09:31:44.287278 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9687 09:31:44.293888 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9688 09:31:44.296992 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9689 09:31:44.300049 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9690 09:31:44.306881 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9691 09:31:44.310269 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9692 09:31:44.316914 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9693 09:31:44.320019 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9694 09:31:44.323486 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9695 09:31:44.329894 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9696 09:31:44.333379 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9697 09:31:44.339529 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9698 09:31:44.343244 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9699 09:31:44.346719 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9700 09:31:44.353054 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9701 09:31:44.356386 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9702 09:31:44.363013 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9703 09:31:44.365832 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9704 09:31:44.369570 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9705 09:31:44.375907 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9706 09:31:44.379351 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9707 09:31:44.385981 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9708 09:31:44.389019 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9709 09:31:44.392519 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9710 09:31:44.399091 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9711 09:31:44.402728 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9712 09:31:44.409102 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9713 09:31:44.412624 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9714 09:31:44.419108 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9715 09:31:44.422450 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9716 09:31:44.425480 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9717 09:31:44.432364 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9718 09:31:44.435417 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9719 09:31:44.442003 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9720 09:31:44.445383 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9721 09:31:44.452092 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9722 09:31:44.455280 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9723 09:31:44.458528 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9724 09:31:44.465057 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9725 09:31:44.468385 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9726 09:31:44.475157 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9727 09:31:44.478116 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9728 09:31:44.485200 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9729 09:31:44.487895 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9730 09:31:44.491291 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9731 09:31:44.497835 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9732 09:31:44.501386 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9733 09:31:44.508051 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9734 09:31:44.511501 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9735 09:31:44.517948 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9736 09:31:44.520923 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9737 09:31:44.524647 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9738 09:31:44.530988 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9739 09:31:44.534529 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9740 09:31:44.540978 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9741 09:31:44.544319 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9742 09:31:44.547551 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9743 09:31:44.554437 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9744 09:31:44.557713 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9745 09:31:44.564381 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9746 09:31:44.567894 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9747 09:31:44.573880 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9748 09:31:44.577598 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9749 09:31:44.580685 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9750 09:31:44.587621 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9751 09:31:44.590589 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9752 09:31:44.593922 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9753 09:31:44.600636 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9754 09:31:44.603819 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9755 09:31:44.607129 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9756 09:31:44.610496 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9757 09:31:44.617120 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9758 09:31:44.620644 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9759 09:31:44.626824 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9760 09:31:44.630041 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9761 09:31:44.633750 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9762 09:31:44.640262 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9763 09:31:44.643364 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9764 09:31:44.646841 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9765 09:31:44.653512 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9766 09:31:44.656425 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9767 09:31:44.659935 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9768 09:31:44.666547 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9769 09:31:44.669756 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9770 09:31:44.676598 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9771 09:31:44.679652 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9772 09:31:44.683289 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9773 09:31:44.689658 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9774 09:31:44.693309 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9775 09:31:44.699775 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9776 09:31:44.703285 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9777 09:31:44.706680 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9778 09:31:44.713204 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9779 09:31:44.716060 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9780 09:31:44.719348 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9781 09:31:44.726284 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9782 09:31:44.729118 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9783 09:31:44.735861 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9784 09:31:44.739061 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9785 09:31:44.742437 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9786 09:31:44.748975 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9787 09:31:44.752601 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9788 09:31:44.755928 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9789 09:31:44.762735 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9790 09:31:44.765452 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9791 09:31:44.769263 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9792 09:31:44.775420 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9793 09:31:44.779163 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9794 09:31:44.782750 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9795 09:31:44.785596 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9796 09:31:44.788697 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9797 09:31:44.795339 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9798 09:31:44.798770 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9799 09:31:44.802338 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9800 09:31:44.808569 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9801 09:31:44.811796 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9802 09:31:44.815317 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9803 09:31:44.818511 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9804 09:31:44.825138 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9805 09:31:44.828402 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9806 09:31:44.834903 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9807 09:31:44.838287 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9808 09:31:44.841711 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9809 09:31:44.847905 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9810 09:31:44.851380 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9811 09:31:44.858195 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9812 09:31:44.861648 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9813 09:31:44.864820 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9814 09:31:44.871649 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9815 09:31:44.874911 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9816 09:31:44.880988 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9817 09:31:44.884505 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9818 09:31:44.891322 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9819 09:31:44.894611 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9820 09:31:44.897784 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9821 09:31:44.904631 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9822 09:31:44.907622 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9823 09:31:44.914485 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9824 09:31:44.917678 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9825 09:31:44.921110 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9826 09:31:44.927817 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9827 09:31:44.931067 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9828 09:31:44.937365 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9829 09:31:44.940810 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9830 09:31:44.943970 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9831 09:31:44.950956 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9832 09:31:44.953874 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9833 09:31:44.960641 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9834 09:31:44.964085 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9835 09:31:44.970661 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9836 09:31:44.973647 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9837 09:31:44.977268 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9838 09:31:44.983743 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9839 09:31:44.986974 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9840 09:31:44.993454 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9841 09:31:44.996903 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9842 09:31:45.003283 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9843 09:31:45.006505 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9844 09:31:45.010355 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9845 09:31:45.016735 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9846 09:31:45.019969 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9847 09:31:45.026608 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9848 09:31:45.030151 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9849 09:31:45.033231 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9850 09:31:45.039986 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9851 09:31:45.043180 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9852 09:31:45.049976 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9853 09:31:45.052851 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9854 09:31:45.056404 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9855 09:31:45.062888 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9856 09:31:45.066308 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9857 09:31:45.072764 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9858 09:31:45.076430 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9859 09:31:45.083148 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9860 09:31:45.086566 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9861 09:31:45.089933 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9862 09:31:45.096333 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9863 09:31:45.099509 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9864 09:31:45.106129 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9865 09:31:45.109447 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9866 09:31:45.116341 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9867 09:31:45.119145 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9868 09:31:45.122773 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9869 09:31:45.129384 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9870 09:31:45.132595 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9871 09:31:45.136061 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9872 09:31:45.142862 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9873 09:31:45.145638 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9874 09:31:45.152153 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9875 09:31:45.155446 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9876 09:31:45.162417 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9877 09:31:45.165829 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9878 09:31:45.168638 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9879 09:31:45.175705 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9880 09:31:45.178878 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9881 09:31:45.185818 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9882 09:31:45.188472 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9883 09:31:45.195474 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9884 09:31:45.198908 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9885 09:31:45.205530 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9886 09:31:45.208312 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9887 09:31:45.211656 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9888 09:31:45.218139 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9889 09:31:45.221533 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9890 09:31:45.228175 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9891 09:31:45.231686 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9892 09:31:45.237958 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9893 09:31:45.241611 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9894 09:31:45.247849 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9895 09:31:45.251193 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9896 09:31:45.254590 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9897 09:31:45.261699 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9898 09:31:45.264536 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9899 09:31:45.271416 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9900 09:31:45.274292 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9901 09:31:45.280808 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9902 09:31:45.284493 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9903 09:31:45.291047 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9904 09:31:45.294508 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9905 09:31:45.297390 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9906 09:31:45.303902 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9907 09:31:45.307920 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9908 09:31:45.314169 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9909 09:31:45.317174 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9910 09:31:45.324368 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9911 09:31:45.327618 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9912 09:31:45.333875 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9913 09:31:45.337231 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9914 09:31:45.340803 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9915 09:31:45.347489 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9916 09:31:45.350651 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9917 09:31:45.357496 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9918 09:31:45.360440 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9919 09:31:45.366811 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9920 09:31:45.370156 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9921 09:31:45.373505 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9922 09:31:45.380406 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9923 09:31:45.383860 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9924 09:31:45.390287 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9925 09:31:45.393421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9926 09:31:45.396781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9927 09:31:45.403770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9928 09:31:45.407307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9929 09:31:45.413409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9930 09:31:45.416954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9931 09:31:45.423156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9932 09:31:45.426652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9933 09:31:45.433404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9934 09:31:45.436340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9935 09:31:45.442887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9936 09:31:45.446742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9937 09:31:45.453247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9938 09:31:45.456462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9939 09:31:45.462616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9940 09:31:45.466424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9941 09:31:45.472474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9942 09:31:45.475988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9943 09:31:45.483062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9944 09:31:45.485876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9945 09:31:45.492675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9946 09:31:45.495986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9947 09:31:45.502754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9948 09:31:45.505572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9949 09:31:45.512550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9950 09:31:45.515885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9951 09:31:45.522472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9952 09:31:45.525767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9953 09:31:45.532129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9954 09:31:45.535399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9955 09:31:45.541887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9956 09:31:45.545639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9957 09:31:45.551826 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9958 09:31:45.551906 INFO: [APUAPC] vio 0
9959 09:31:45.559157 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9960 09:31:45.561798 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9961 09:31:45.565668 INFO: [APUAPC] D0_APC_0: 0x400510
9962 09:31:45.569191 INFO: [APUAPC] D0_APC_1: 0x0
9963 09:31:45.571742 INFO: [APUAPC] D0_APC_2: 0x1540
9964 09:31:45.575493 INFO: [APUAPC] D0_APC_3: 0x0
9965 09:31:45.578513 INFO: [APUAPC] D1_APC_0: 0xffffffff
9966 09:31:45.582056 INFO: [APUAPC] D1_APC_1: 0xffffffff
9967 09:31:45.585353 INFO: [APUAPC] D1_APC_2: 0x3fffff
9968 09:31:45.588788 INFO: [APUAPC] D1_APC_3: 0x0
9969 09:31:45.591742 INFO: [APUAPC] D2_APC_0: 0xffffffff
9970 09:31:45.595131 INFO: [APUAPC] D2_APC_1: 0xffffffff
9971 09:31:45.598341 INFO: [APUAPC] D2_APC_2: 0x3fffff
9972 09:31:45.601640 INFO: [APUAPC] D2_APC_3: 0x0
9973 09:31:45.604974 INFO: [APUAPC] D3_APC_0: 0xffffffff
9974 09:31:45.608501 INFO: [APUAPC] D3_APC_1: 0xffffffff
9975 09:31:45.611954 INFO: [APUAPC] D3_APC_2: 0x3fffff
9976 09:31:45.614781 INFO: [APUAPC] D3_APC_3: 0x0
9977 09:31:45.618320 INFO: [APUAPC] D4_APC_0: 0xffffffff
9978 09:31:45.621888 INFO: [APUAPC] D4_APC_1: 0xffffffff
9979 09:31:45.624870 INFO: [APUAPC] D4_APC_2: 0x3fffff
9980 09:31:45.628040 INFO: [APUAPC] D4_APC_3: 0x0
9981 09:31:45.631559 INFO: [APUAPC] D5_APC_0: 0xffffffff
9982 09:31:45.635069 INFO: [APUAPC] D5_APC_1: 0xffffffff
9983 09:31:45.638505 INFO: [APUAPC] D5_APC_2: 0x3fffff
9984 09:31:45.641368 INFO: [APUAPC] D5_APC_3: 0x0
9985 09:31:45.644372 INFO: [APUAPC] D6_APC_0: 0xffffffff
9986 09:31:45.647912 INFO: [APUAPC] D6_APC_1: 0xffffffff
9987 09:31:45.651039 INFO: [APUAPC] D6_APC_2: 0x3fffff
9988 09:31:45.651118 INFO: [APUAPC] D6_APC_3: 0x0
9989 09:31:45.654416 INFO: [APUAPC] D7_APC_0: 0xffffffff
9990 09:31:45.661368 INFO: [APUAPC] D7_APC_1: 0xffffffff
9991 09:31:45.664295 INFO: [APUAPC] D7_APC_2: 0x3fffff
9992 09:31:45.664374 INFO: [APUAPC] D7_APC_3: 0x0
9993 09:31:45.668032 INFO: [APUAPC] D8_APC_0: 0xffffffff
9994 09:31:45.671401 INFO: [APUAPC] D8_APC_1: 0xffffffff
9995 09:31:45.674111 INFO: [APUAPC] D8_APC_2: 0x3fffff
9996 09:31:45.677422 INFO: [APUAPC] D8_APC_3: 0x0
9997 09:31:45.680802 INFO: [APUAPC] D9_APC_0: 0xffffffff
9998 09:31:45.684341 INFO: [APUAPC] D9_APC_1: 0xffffffff
9999 09:31:45.687679 INFO: [APUAPC] D9_APC_2: 0x3fffff
10000 09:31:45.690710 INFO: [APUAPC] D9_APC_3: 0x0
10001 09:31:45.693981 INFO: [APUAPC] D10_APC_0: 0xffffffff
10002 09:31:45.697496 INFO: [APUAPC] D10_APC_1: 0xffffffff
10003 09:31:45.700796 INFO: [APUAPC] D10_APC_2: 0x3fffff
10004 09:31:45.703831 INFO: [APUAPC] D10_APC_3: 0x0
10005 09:31:45.707126 INFO: [APUAPC] D11_APC_0: 0xffffffff
10006 09:31:45.710502 INFO: [APUAPC] D11_APC_1: 0xffffffff
10007 09:31:45.716894 INFO: [APUAPC] D11_APC_2: 0x3fffff
10008 09:31:45.716973 INFO: [APUAPC] D11_APC_3: 0x0
10009 09:31:45.720423 INFO: [APUAPC] D12_APC_0: 0xffffffff
10010 09:31:45.727331 INFO: [APUAPC] D12_APC_1: 0xffffffff
10011 09:31:45.730114 INFO: [APUAPC] D12_APC_2: 0x3fffff
10012 09:31:45.730257 INFO: [APUAPC] D12_APC_3: 0x0
10013 09:31:45.737201 INFO: [APUAPC] D13_APC_0: 0xffffffff
10014 09:31:45.739943 INFO: [APUAPC] D13_APC_1: 0xffffffff
10015 09:31:45.743796 INFO: [APUAPC] D13_APC_2: 0x3fffff
10016 09:31:45.743875 INFO: [APUAPC] D13_APC_3: 0x0
10017 09:31:45.750117 INFO: [APUAPC] D14_APC_0: 0xffffffff
10018 09:31:45.753794 INFO: [APUAPC] D14_APC_1: 0xffffffff
10019 09:31:45.757223 INFO: [APUAPC] D14_APC_2: 0x3fffff
10020 09:31:45.760020 INFO: [APUAPC] D14_APC_3: 0x0
10021 09:31:45.763613 INFO: [APUAPC] D15_APC_0: 0xffffffff
10022 09:31:45.766531 INFO: [APUAPC] D15_APC_1: 0xffffffff
10023 09:31:45.769837 INFO: [APUAPC] D15_APC_2: 0x3fffff
10024 09:31:45.773532 INFO: [APUAPC] D15_APC_3: 0x0
10025 09:31:45.773602 INFO: [APUAPC] APC_CON: 0x4
10026 09:31:45.776420 INFO: [NOCDAPC] D0_APC_0: 0x0
10027 09:31:45.779750 INFO: [NOCDAPC] D0_APC_1: 0x0
10028 09:31:45.783102 INFO: [NOCDAPC] D1_APC_0: 0x0
10029 09:31:45.786441 INFO: [NOCDAPC] D1_APC_1: 0xfff
10030 09:31:45.789922 INFO: [NOCDAPC] D2_APC_0: 0x0
10031 09:31:45.793384 INFO: [NOCDAPC] D2_APC_1: 0xfff
10032 09:31:45.796131 INFO: [NOCDAPC] D3_APC_0: 0x0
10033 09:31:45.800001 INFO: [NOCDAPC] D3_APC_1: 0xfff
10034 09:31:45.803166 INFO: [NOCDAPC] D4_APC_0: 0x0
10035 09:31:45.803246 INFO: [NOCDAPC] D4_APC_1: 0xfff
10036 09:31:45.806024 INFO: [NOCDAPC] D5_APC_0: 0x0
10037 09:31:45.809548 INFO: [NOCDAPC] D5_APC_1: 0xfff
10038 09:31:45.813003 INFO: [NOCDAPC] D6_APC_0: 0x0
10039 09:31:45.816116 INFO: [NOCDAPC] D6_APC_1: 0xfff
10040 09:31:45.819400 INFO: [NOCDAPC] D7_APC_0: 0x0
10041 09:31:45.822822 INFO: [NOCDAPC] D7_APC_1: 0xfff
10042 09:31:45.826084 INFO: [NOCDAPC] D8_APC_0: 0x0
10043 09:31:45.829672 INFO: [NOCDAPC] D8_APC_1: 0xfff
10044 09:31:45.832626 INFO: [NOCDAPC] D9_APC_0: 0x0
10045 09:31:45.835793 INFO: [NOCDAPC] D9_APC_1: 0xfff
10046 09:31:45.839181 INFO: [NOCDAPC] D10_APC_0: 0x0
10047 09:31:45.842381 INFO: [NOCDAPC] D10_APC_1: 0xfff
10048 09:31:45.842460 INFO: [NOCDAPC] D11_APC_0: 0x0
10049 09:31:45.845704 INFO: [NOCDAPC] D11_APC_1: 0xfff
10050 09:31:45.849260 INFO: [NOCDAPC] D12_APC_0: 0x0
10051 09:31:45.852408 INFO: [NOCDAPC] D12_APC_1: 0xfff
10052 09:31:45.855892 INFO: [NOCDAPC] D13_APC_0: 0x0
10053 09:31:45.859003 INFO: [NOCDAPC] D13_APC_1: 0xfff
10054 09:31:45.862128 INFO: [NOCDAPC] D14_APC_0: 0x0
10055 09:31:45.866118 INFO: [NOCDAPC] D14_APC_1: 0xfff
10056 09:31:45.869230 INFO: [NOCDAPC] D15_APC_0: 0x0
10057 09:31:45.872069 INFO: [NOCDAPC] D15_APC_1: 0xfff
10058 09:31:45.875715 INFO: [NOCDAPC] APC_CON: 0x4
10059 09:31:45.879096 INFO: [APUAPC] set_apusys_apc done
10060 09:31:45.882349 INFO: [DEVAPC] devapc_init done
10061 09:31:45.885750 INFO: GICv3 without legacy support detected.
10062 09:31:45.888906 INFO: ARM GICv3 driver initialized in EL3
10063 09:31:45.892208 INFO: Maximum SPI INTID supported: 639
10064 09:31:45.895802 INFO: BL31: Initializing runtime services
10065 09:31:45.901959 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10066 09:31:45.904989 INFO: SPM: enable CPC mode
10067 09:31:45.912017 INFO: mcdi ready for mcusys-off-idle and system suspend
10068 09:31:45.915397 INFO: BL31: Preparing for EL3 exit to normal world
10069 09:31:45.918465 INFO: Entry point address = 0x80000000
10070 09:31:45.921637 INFO: SPSR = 0x8
10071 09:31:45.926801
10072 09:31:45.926881
10073 09:31:45.926945
10074 09:31:45.930406 Starting depthcharge on Spherion...
10075 09:31:45.930486
10076 09:31:45.930549 Wipe memory regions:
10077 09:31:45.930609
10078 09:31:45.931221 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10079 09:31:45.931316 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10080 09:31:45.931398 Setting prompt string to ['asurada:']
10081 09:31:45.931475 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10082 09:31:45.933306 [0x00000040000000, 0x00000054600000)
10083 09:31:46.056802
10084 09:31:46.056951 [0x00000054660000, 0x00000080000000)
10085 09:31:46.316295
10086 09:31:46.316443 [0x000000821a7280, 0x000000ffe64000)
10087 09:31:47.060391
10088 09:31:47.060539 [0x00000100000000, 0x00000240000000)
10089 09:31:48.950629
10090 09:31:48.954061 Initializing XHCI USB controller at 0x11200000.
10091 09:31:49.992006
10092 09:31:49.995459 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10093 09:31:49.995545
10094 09:31:49.995609
10095 09:31:49.995890 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10097 09:31:50.096246 asurada: tftpboot 192.168.201.1 14407680/tftp-deploy-7ld5grgi/kernel/image.itb 14407680/tftp-deploy-7ld5grgi/kernel/cmdline
10098 09:31:50.096435 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10099 09:31:50.096531 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10100 09:31:50.100881 tftpboot 192.168.201.1 14407680/tftp-deploy-7ld5grgi/kernel/image.ittp-deploy-7ld5grgi/kernel/cmdline
10101 09:31:50.100967
10102 09:31:50.101082 Waiting for link
10103 09:31:50.259097
10104 09:31:50.259246 R8152: Initializing
10105 09:31:50.259314
10106 09:31:50.262431 Version 6 (ocp_data = 5c30)
10107 09:31:50.262513
10108 09:31:50.265931 R8152: Done initializing
10109 09:31:50.266011
10110 09:31:50.266075 Adding net device
10111 09:31:52.171289
10112 09:31:52.171443 done.
10113 09:31:52.171511
10114 09:31:52.171571 MAC: 00:e0:4c:68:02:81
10115 09:31:52.171630
10116 09:31:52.174581 Sending DHCP discover... done.
10117 09:31:52.174662
10118 09:31:52.178307 Waiting for reply... done.
10119 09:31:52.178388
10120 09:31:52.181246 Sending DHCP request... done.
10121 09:31:52.181328
10122 09:31:52.185627 Waiting for reply... done.
10123 09:31:52.185709
10124 09:31:52.185773 My ip is 192.168.201.14
10125 09:31:52.185832
10126 09:31:52.189208 The DHCP server ip is 192.168.201.1
10127 09:31:52.189288
10128 09:31:52.195682 TFTP server IP predefined by user: 192.168.201.1
10129 09:31:52.195763
10130 09:31:52.202632 Bootfile predefined by user: 14407680/tftp-deploy-7ld5grgi/kernel/image.itb
10131 09:31:52.202713
10132 09:31:52.205537 Sending tftp read request... done.
10133 09:31:52.205618
10134 09:31:52.209527 Waiting for the transfer...
10135 09:31:52.209607
10136 09:31:52.778782 00000000 ################################################################
10137 09:31:52.778926
10138 09:31:53.363792 00080000 ################################################################
10139 09:31:53.363985
10140 09:31:53.938289 00100000 ################################################################
10141 09:31:53.938447
10142 09:31:54.515812 00180000 ################################################################
10143 09:31:54.515966
10144 09:31:55.085641 00200000 ################################################################
10145 09:31:55.085798
10146 09:31:55.653059 00280000 ################################################################
10147 09:31:55.653212
10148 09:31:56.218969 00300000 ################################################################
10149 09:31:56.219123
10150 09:31:56.783582 00380000 ################################################################
10151 09:31:56.783738
10152 09:31:57.349746 00400000 ################################################################
10153 09:31:57.349900
10154 09:31:57.933197 00480000 ################################################################
10155 09:31:57.933352
10156 09:31:58.503326 00500000 ################################################################
10157 09:31:58.503475
10158 09:31:59.068442 00580000 ################################################################
10159 09:31:59.068596
10160 09:31:59.645708 00600000 ################################################################
10161 09:31:59.645861
10162 09:32:00.200351 00680000 ################################################################
10163 09:32:00.200523
10164 09:32:00.771600 00700000 ################################################################
10165 09:32:00.771780
10166 09:32:01.337534 00780000 ################################################################
10167 09:32:01.337712
10168 09:32:01.900155 00800000 ################################################################
10169 09:32:01.900305
10170 09:32:02.456455 00880000 ################################################################
10171 09:32:02.456603
10172 09:32:03.050525 00900000 ################################################################
10173 09:32:03.050678
10174 09:32:03.624165 00980000 ################################################################
10175 09:32:03.624314
10176 09:32:04.208231 00a00000 ################################################################
10177 09:32:04.208383
10178 09:32:04.773520 00a80000 ################################################################
10179 09:32:04.773670
10180 09:32:05.349521 00b00000 ################################################################
10181 09:32:05.349670
10182 09:32:05.922282 00b80000 ################################################################
10183 09:32:05.922431
10184 09:32:06.516857 00c00000 ################################################################
10185 09:32:06.517008
10186 09:32:07.090777 00c80000 ################################################################
10187 09:32:07.091250
10188 09:32:07.714974 00d00000 ################################################################
10189 09:32:07.715509
10190 09:32:08.416767 00d80000 ################################################################
10191 09:32:08.417313
10192 09:32:09.111190 00e00000 ################################################################
10193 09:32:09.111712
10194 09:32:09.803375 00e80000 ################################################################
10195 09:32:09.803910
10196 09:32:10.473450 00f00000 ################################################################
10197 09:32:10.474020
10198 09:32:11.165757 00f80000 ################################################################
10199 09:32:11.166295
10200 09:32:11.853873 01000000 ################################################################
10201 09:32:11.854602
10202 09:32:12.543735 01080000 ################################################################
10203 09:32:12.544243
10204 09:32:13.245035 01100000 ################################################################
10205 09:32:13.245604
10206 09:32:13.945322 01180000 ################################################################
10207 09:32:13.945841
10208 09:32:14.650308 01200000 ################################################################
10209 09:32:14.650814
10210 09:32:15.303613 01280000 ################################################################
10211 09:32:15.303998
10212 09:32:15.980706 01300000 ################################################################
10213 09:32:15.981246
10214 09:32:16.689963 01380000 ################################################################
10215 09:32:16.690522
10216 09:32:17.381348 01400000 ################################################################
10217 09:32:17.381873
10218 09:32:18.093962 01480000 ################################################################
10219 09:32:18.094552
10220 09:32:18.783307 01500000 ################################################################
10221 09:32:18.783826
10222 09:32:19.489625 01580000 ################################################################
10223 09:32:19.490156
10224 09:32:20.169951 01600000 ################################################################
10225 09:32:20.170501
10226 09:32:20.801865 01680000 ################################################################
10227 09:32:20.802392
10228 09:32:21.482917 01700000 ################################################################
10229 09:32:21.483474
10230 09:32:22.152938 01780000 ################################################################
10231 09:32:22.153567
10232 09:32:22.853838 01800000 ################################################################
10233 09:32:22.854549
10234 09:32:23.543949 01880000 ################################################################
10235 09:32:23.544488
10236 09:32:24.236374 01900000 ################################################################
10237 09:32:24.236883
10238 09:32:24.936679 01980000 ################################################################
10239 09:32:24.937225
10240 09:32:25.618272 01a00000 ################################################################
10241 09:32:25.618840
10242 09:32:26.256323 01a80000 ################################################################
10243 09:32:26.256988
10244 09:32:26.872420 01b00000 ################################################################
10245 09:32:26.872562
10246 09:32:27.566391 01b80000 ################################################################
10247 09:32:27.566902
10248 09:32:28.268837 01c00000 ################################################################
10249 09:32:28.269348
10250 09:32:28.963745 01c80000 ################################################################
10251 09:32:28.964246
10252 09:32:29.660485 01d00000 ################################################################
10253 09:32:29.661000
10254 09:32:30.329730 01d80000 ################################################################
10255 09:32:30.330367
10256 09:32:31.005072 01e00000 ################################################################
10257 09:32:31.005702
10258 09:32:31.683531 01e80000 ################################################################
10259 09:32:31.683677
10260 09:32:32.212314 01f00000 ################################################################
10261 09:32:32.212467
10262 09:32:32.758902 01f80000 ################################################################
10263 09:32:32.759049
10264 09:32:33.296898 02000000 ################################################################
10265 09:32:33.297044
10266 09:32:33.860274 02080000 ################################################################
10267 09:32:33.860423
10268 09:32:34.415601 02100000 ################################################################
10269 09:32:34.415741
10270 09:32:34.953812 02180000 ################################################################
10271 09:32:34.953952
10272 09:32:35.478199 02200000 ################################################################
10273 09:32:35.478350
10274 09:32:36.000273 02280000 ################################################################
10275 09:32:36.000414
10276 09:32:36.534732 02300000 ################################################################
10277 09:32:36.534875
10278 09:32:37.072879 02380000 ################################################################
10279 09:32:37.073030
10280 09:32:37.601656 02400000 ################################################################
10281 09:32:37.601797
10282 09:32:38.139737 02480000 ################################################################
10283 09:32:38.139873
10284 09:32:38.664386 02500000 ################################################################
10285 09:32:38.664562
10286 09:32:39.186214 02580000 ################################################################
10287 09:32:39.186368
10288 09:32:39.708053 02600000 ################################################################
10289 09:32:39.708217
10290 09:32:40.247192 02680000 ################################################################
10291 09:32:40.247327
10292 09:32:40.775318 02700000 ################################################################
10293 09:32:40.775451
10294 09:32:41.308881 02780000 ################################################################
10295 09:32:41.309014
10296 09:32:41.846349 02800000 ################################################################
10297 09:32:41.846482
10298 09:32:42.369381 02880000 ################################################################
10299 09:32:42.369544
10300 09:32:42.918172 02900000 ################################################################
10301 09:32:42.918330
10302 09:32:43.445048 02980000 ################################################################
10303 09:32:43.445222
10304 09:32:43.985667 02a00000 ################################################################
10305 09:32:43.985846
10306 09:32:44.506887 02a80000 ################################################################
10307 09:32:44.507033
10308 09:32:45.034734 02b00000 ################################################################
10309 09:32:45.034902
10310 09:32:45.567681 02b80000 ################################################################
10311 09:32:45.567848
10312 09:32:46.097097 02c00000 ################################################################
10313 09:32:46.097242
10314 09:32:46.628733 02c80000 ################################################################
10315 09:32:46.628902
10316 09:32:47.155513 02d00000 ################################################################
10317 09:32:47.155683
10318 09:32:47.680557 02d80000 ################################################################
10319 09:32:47.680690
10320 09:32:48.353781 02e00000 ################################################################
10321 09:32:48.354443
10322 09:32:49.039907 02e80000 ################################################################
10323 09:32:49.040447
10324 09:32:49.744040 02f00000 ################################################################
10325 09:32:49.744534
10326 09:32:50.391778 02f80000 ################################################################
10327 09:32:50.391918
10328 09:32:50.960114 03000000 ################################################################
10329 09:32:50.960372
10330 09:32:51.568472 03080000 ################################################################
10331 09:32:51.568723
10332 09:32:52.201998 03100000 ################################################################
10333 09:32:52.202692
10334 09:32:52.873130 03180000 ################################################################
10335 09:32:52.873616
10336 09:32:53.469034 03200000 ################################################################
10337 09:32:53.469553
10338 09:32:54.168597 03280000 ################################################################
10339 09:32:54.169170
10340 09:32:54.869650 03300000 ################################################################
10341 09:32:54.870038
10342 09:32:55.570634 03380000 ################################################################
10343 09:32:55.571199
10344 09:32:56.244121 03400000 ################################################################
10345 09:32:56.244626
10346 09:32:56.923055 03480000 ################################################################
10347 09:32:56.923572
10348 09:32:57.616829 03500000 ################################################################
10349 09:32:57.617484
10350 09:32:58.292329 03580000 ################################################################
10351 09:32:58.292903
10352 09:32:58.947234 03600000 ################################################################
10353 09:32:58.947748
10354 09:32:59.572270 03680000 ################################################################
10355 09:32:59.572823
10356 09:33:00.224668 03700000 ################################################################
10357 09:33:00.225327
10358 09:33:00.796583 03780000 ################################################################
10359 09:33:00.796721
10360 09:33:01.366283 03800000 ################################################################
10361 09:33:01.366491
10362 09:33:02.029583 03880000 ################################################################
10363 09:33:02.030278
10364 09:33:02.714344 03900000 ################################################################
10365 09:33:02.714893
10366 09:33:03.393884 03980000 ################################################################
10367 09:33:03.394297
10368 09:33:04.038842 03a00000 ################################################################
10369 09:33:04.039414
10370 09:33:04.669385 03a80000 ################################################################
10371 09:33:04.669648
10372 09:33:05.311432 03b00000 ################################################################
10373 09:33:05.311905
10374 09:33:05.888844 03b80000 ################################################################
10375 09:33:05.889035
10376 09:33:06.456742 03c00000 ################################################################
10377 09:33:06.456889
10378 09:33:07.081330 03c80000 ################################################################
10379 09:33:07.081494
10380 09:33:07.658684 03d00000 ################################################################
10381 09:33:07.658819
10382 09:33:08.296295 03d80000 ################################################################
10383 09:33:08.296846
10384 09:33:08.960067 03e00000 ################################################################
10385 09:33:08.960319
10386 09:33:09.609573 03e80000 ################################################################
10387 09:33:09.609729
10388 09:33:10.289004 03f00000 ################################################################
10389 09:33:10.289492
10390 09:33:10.911773 03f80000 ################################################################
10391 09:33:10.911937
10392 09:33:11.494476 04000000 ################################################################
10393 09:33:11.494614
10394 09:33:12.052246 04080000 ################################################################
10395 09:33:12.052396
10396 09:33:12.666827 04100000 ################################################################
10397 09:33:12.667390
10398 09:33:13.328089 04180000 ################################################################
10399 09:33:13.328599
10400 09:33:13.987909 04200000 ################################################################
10401 09:33:13.988481
10402 09:33:14.678606 04280000 ################################################################
10403 09:33:14.679109
10404 09:33:15.360269 04300000 ################################################################
10405 09:33:15.360823
10406 09:33:16.047692 04380000 ################################################################
10407 09:33:16.048218
10408 09:33:16.754897 04400000 ################################################################
10409 09:33:16.755422
10410 09:33:17.440962 04480000 ################################################################
10411 09:33:17.441484
10412 09:33:18.132606 04500000 ################################################################
10413 09:33:18.133196
10414 09:33:18.809053 04580000 ################################################################
10415 09:33:18.809555
10416 09:33:19.502378 04600000 ################################################################
10417 09:33:19.503017
10418 09:33:19.842379 04680000 ################################ done.
10419 09:33:19.842926
10420 09:33:19.845622 The bootfile was 74180862 bytes long.
10421 09:33:19.846078
10422 09:33:19.848995 Sending tftp read request... done.
10423 09:33:19.849445
10424 09:33:19.852999 Waiting for the transfer...
10425 09:33:19.853450
10426 09:33:19.853805 00000000 # done.
10427 09:33:19.854148
10428 09:33:19.859551 Command line loaded dynamically from TFTP file: 14407680/tftp-deploy-7ld5grgi/kernel/cmdline
10429 09:33:19.859963
10430 09:33:19.875546 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10431 09:33:19.876065
10432 09:33:19.876390 Loading FIT.
10433 09:33:19.876695
10434 09:33:19.878775 Image ramdisk-1 has 61004844 bytes.
10435 09:33:19.879181
10436 09:33:19.881897 Image fdt-1 has 47258 bytes.
10437 09:33:19.882340
10438 09:33:19.885354 Image kernel-1 has 13126726 bytes.
10439 09:33:19.885761
10440 09:33:19.892639 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10441 09:33:19.893160
10442 09:33:19.911582 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10443 09:33:19.912089
10444 09:33:19.915097 Choosing best match conf-1 for compat google,spherion-rev2.
10445 09:33:19.920757
10446 09:33:19.924788 Connected to device vid:did:rid of 1ae0:0028:00
10447 09:33:19.931704
10448 09:33:19.935408 tpm_get_response: command 0x17b, return code 0x0
10449 09:33:19.935918
10450 09:33:19.938308 ec_init: CrosEC protocol v3 supported (256, 248)
10451 09:33:19.943643
10452 09:33:19.947130 tpm_cleanup: add release locality here.
10453 09:33:19.947599
10454 09:33:19.947929 Shutting down all USB controllers.
10455 09:33:19.950267
10456 09:33:19.950672 Removing current net device
10457 09:33:19.951003
10458 09:33:19.957073 Exiting depthcharge with code 4 at timestamp: 123559781
10459 09:33:19.957484
10460 09:33:19.959955 LZMA decompressing kernel-1 to 0x821a6718
10461 09:33:19.960370
10462 09:33:19.963426 LZMA decompressing kernel-1 to 0x40000000
10463 09:33:21.581830
10464 09:33:21.582436 jumping to kernel
10465 09:33:21.584588 end: 2.2.4 bootloader-commands (duration 00:01:36) [common]
10466 09:33:21.585098 start: 2.2.5 auto-login-action (timeout 00:02:51) [common]
10467 09:33:21.585496 Setting prompt string to ['Linux version [0-9]']
10468 09:33:21.585866 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10469 09:33:21.586521 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10470 09:33:21.664565
10471 09:33:21.667676 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10472 09:33:21.671857 start: 2.2.5.1 login-action (timeout 00:02:51) [common]
10473 09:33:21.672448 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10474 09:33:21.672863 Setting prompt string to []
10475 09:33:21.673273 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10476 09:33:21.673667 Using line separator: #'\n'#
10477 09:33:21.674099 No login prompt set.
10478 09:33:21.674538 Parsing kernel messages
10479 09:33:21.674926 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10480 09:33:21.675502 [login-action] Waiting for messages, (timeout 00:02:51)
10481 09:33:21.675862 Waiting using forced prompt support (timeout 00:01:25)
10482 09:33:21.691030 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
10483 09:33:21.694400 [ 0.000000] random: crng init done
10484 09:33:21.700867 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10485 09:33:21.704698 [ 0.000000] efi: UEFI not found.
10486 09:33:21.711001 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10487 09:33:21.721008 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10488 09:33:21.727723 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10489 09:33:21.737461 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10490 09:33:21.744005 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10491 09:33:21.750826 [ 0.000000] printk: bootconsole [mtk8250] enabled
10492 09:33:21.757078 [ 0.000000] NUMA: No NUMA configuration found
10493 09:33:21.763792 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10494 09:33:21.770350 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10495 09:33:21.770884 [ 0.000000] Zone ranges:
10496 09:33:21.777443 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10497 09:33:21.780332 [ 0.000000] DMA32 empty
10498 09:33:21.786542 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10499 09:33:21.790279 [ 0.000000] Movable zone start for each node
10500 09:33:21.793235 [ 0.000000] Early memory node ranges
10501 09:33:21.799900 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10502 09:33:21.806634 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10503 09:33:21.813332 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10504 09:33:21.819796 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10505 09:33:21.826613 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10506 09:33:21.832963 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10507 09:33:21.889197 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10508 09:33:21.895770 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10509 09:33:21.902370 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10510 09:33:21.905421 [ 0.000000] psci: probing for conduit method from DT.
10511 09:33:21.912017 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10512 09:33:21.915096 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10513 09:33:21.921973 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10514 09:33:21.924973 [ 0.000000] psci: SMC Calling Convention v1.2
10515 09:33:21.931424 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10516 09:33:21.934936 [ 0.000000] Detected VIPT I-cache on CPU0
10517 09:33:21.941460 [ 0.000000] CPU features: detected: GIC system register CPU interface
10518 09:33:21.948379 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10519 09:33:21.954666 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10520 09:33:21.961616 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10521 09:33:21.971098 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10522 09:33:21.977777 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10523 09:33:21.980919 [ 0.000000] alternatives: applying boot alternatives
10524 09:33:21.987611 [ 0.000000] Fallback order for Node 0: 0
10525 09:33:21.994641 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10526 09:33:21.997477 [ 0.000000] Policy zone: Normal
10527 09:33:22.010280 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10528 09:33:22.020158 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10529 09:33:22.033208 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10530 09:33:22.042527 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10531 09:33:22.049157 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10532 09:33:22.052510 <6>[ 0.000000] software IO TLB: area num 8.
10533 09:33:22.108936 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10534 09:33:22.258295 <6>[ 0.000000] Memory: 7904484K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 448284K reserved, 32768K cma-reserved)
10535 09:33:22.265022 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10536 09:33:22.271322 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10537 09:33:22.274559 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10538 09:33:22.281090 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10539 09:33:22.288037 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10540 09:33:22.291066 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10541 09:33:22.301552 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10542 09:33:22.307758 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10543 09:33:22.314109 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10544 09:33:22.320953 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10545 09:33:22.324159 <6>[ 0.000000] GICv3: 608 SPIs implemented
10546 09:33:22.327484 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10547 09:33:22.334070 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10548 09:33:22.337556 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10549 09:33:22.344214 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10550 09:33:22.357053 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10551 09:33:22.370499 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10552 09:33:22.377117 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10553 09:33:22.384961 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10554 09:33:22.398367 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10555 09:33:22.404509 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10556 09:33:22.411072 <6>[ 0.009178] Console: colour dummy device 80x25
10557 09:33:22.421440 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10558 09:33:22.427853 <6>[ 0.024415] pid_max: default: 32768 minimum: 301
10559 09:33:22.431125 <6>[ 0.029285] LSM: Security Framework initializing
10560 09:33:22.437413 <6>[ 0.034223] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10561 09:33:22.447418 <6>[ 0.042038] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10562 09:33:22.457286 <6>[ 0.051511] cblist_init_generic: Setting adjustable number of callback queues.
10563 09:33:22.463681 <6>[ 0.059002] cblist_init_generic: Setting shift to 3 and lim to 1.
10564 09:33:22.470665 <6>[ 0.065342] cblist_init_generic: Setting adjustable number of callback queues.
10565 09:33:22.477405 <6>[ 0.072768] cblist_init_generic: Setting shift to 3 and lim to 1.
10566 09:33:22.480339 <6>[ 0.079209] rcu: Hierarchical SRCU implementation.
10567 09:33:22.487343 <6>[ 0.084255] rcu: Max phase no-delay instances is 1000.
10568 09:33:22.493409 <6>[ 0.091273] EFI services will not be available.
10569 09:33:22.496944 <6>[ 0.096230] smp: Bringing up secondary CPUs ...
10570 09:33:22.505584 <6>[ 0.101306] Detected VIPT I-cache on CPU1
10571 09:33:22.512410 <6>[ 0.101377] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10572 09:33:22.519133 <6>[ 0.101407] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10573 09:33:22.522031 <6>[ 0.101745] Detected VIPT I-cache on CPU2
10574 09:33:22.532205 <6>[ 0.101799] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10575 09:33:22.538483 <6>[ 0.101817] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10576 09:33:22.541852 <6>[ 0.102077] Detected VIPT I-cache on CPU3
10577 09:33:22.548790 <6>[ 0.102125] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10578 09:33:22.555267 <6>[ 0.102140] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10579 09:33:22.561745 <6>[ 0.102444] CPU features: detected: Spectre-v4
10580 09:33:22.565190 <6>[ 0.102450] CPU features: detected: Spectre-BHB
10581 09:33:22.568263 <6>[ 0.102456] Detected PIPT I-cache on CPU4
10582 09:33:22.575403 <6>[ 0.102516] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10583 09:33:22.581381 <6>[ 0.102533] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10584 09:33:22.588349 <6>[ 0.102826] Detected PIPT I-cache on CPU5
10585 09:33:22.595106 <6>[ 0.102888] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10586 09:33:22.601455 <6>[ 0.102904] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10587 09:33:22.604934 <6>[ 0.103185] Detected PIPT I-cache on CPU6
10588 09:33:22.611080 <6>[ 0.103251] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10589 09:33:22.621076 <6>[ 0.103267] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10590 09:33:22.624281 <6>[ 0.103563] Detected PIPT I-cache on CPU7
10591 09:33:22.631429 <6>[ 0.103628] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10592 09:33:22.637572 <6>[ 0.103644] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10593 09:33:22.641310 <6>[ 0.103691] smp: Brought up 1 node, 8 CPUs
10594 09:33:22.647710 <6>[ 0.245139] SMP: Total of 8 processors activated.
10595 09:33:22.654256 <6>[ 0.250090] CPU features: detected: 32-bit EL0 Support
10596 09:33:22.660900 <6>[ 0.255454] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10597 09:33:22.667305 <6>[ 0.264255] CPU features: detected: Common not Private translations
10598 09:33:22.674134 <6>[ 0.270730] CPU features: detected: CRC32 instructions
10599 09:33:22.680941 <6>[ 0.276082] CPU features: detected: RCpc load-acquire (LDAPR)
10600 09:33:22.683765 <6>[ 0.282042] CPU features: detected: LSE atomic instructions
10601 09:33:22.690085 <6>[ 0.287824] CPU features: detected: Privileged Access Never
10602 09:33:22.697077 <6>[ 0.293603] CPU features: detected: RAS Extension Support
10603 09:33:22.703752 <6>[ 0.299247] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10604 09:33:22.707176 <6>[ 0.306467] CPU: All CPU(s) started at EL2
10605 09:33:22.713025 <6>[ 0.310783] alternatives: applying system-wide alternatives
10606 09:33:22.724026 <6>[ 0.321627] devtmpfs: initialized
10607 09:33:22.739567 <6>[ 0.330583] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10608 09:33:22.746303 <6>[ 0.340540] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10609 09:33:22.752419 <6>[ 0.348560] pinctrl core: initialized pinctrl subsystem
10610 09:33:22.755834 <6>[ 0.355241] DMI not present or invalid.
10611 09:33:22.762140 <6>[ 0.359654] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10612 09:33:22.772071 <6>[ 0.366510] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10613 09:33:22.779128 <6>[ 0.374082] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10614 09:33:22.789163 <6>[ 0.382301] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10615 09:33:22.792305 <6>[ 0.390542] audit: initializing netlink subsys (disabled)
10616 09:33:22.802330 <5>[ 0.396236] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10617 09:33:22.808718 <6>[ 0.396955] thermal_sys: Registered thermal governor 'step_wise'
10618 09:33:22.815309 <6>[ 0.404203] thermal_sys: Registered thermal governor 'power_allocator'
10619 09:33:22.818583 <6>[ 0.410461] cpuidle: using governor menu
10620 09:33:22.825024 <6>[ 0.421424] NET: Registered PF_QIPCRTR protocol family
10621 09:33:22.831926 <6>[ 0.426908] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10622 09:33:22.838490 <6>[ 0.434011] ASID allocator initialised with 32768 entries
10623 09:33:22.842319 <6>[ 0.440591] Serial: AMBA PL011 UART driver
10624 09:33:22.852202 <4>[ 0.449470] Trying to register duplicate clock ID: 134
10625 09:33:22.911974 <6>[ 0.512689] KASLR enabled
10626 09:33:22.925990 <6>[ 0.520436] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10627 09:33:22.933053 <6>[ 0.527448] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10628 09:33:22.939219 <6>[ 0.533940] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10629 09:33:22.945830 <6>[ 0.540947] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10630 09:33:22.952602 <6>[ 0.547436] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10631 09:33:22.958923 <6>[ 0.554442] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10632 09:33:22.965976 <6>[ 0.560931] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10633 09:33:22.972339 <6>[ 0.567937] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10634 09:33:22.975741 <6>[ 0.575390] ACPI: Interpreter disabled.
10635 09:33:22.984699 <6>[ 0.581827] iommu: Default domain type: Translated
10636 09:33:22.991169 <6>[ 0.586939] iommu: DMA domain TLB invalidation policy: strict mode
10637 09:33:22.994124 <5>[ 0.593602] SCSI subsystem initialized
10638 09:33:23.000818 <6>[ 0.597766] usbcore: registered new interface driver usbfs
10639 09:33:23.007396 <6>[ 0.603500] usbcore: registered new interface driver hub
10640 09:33:23.010951 <6>[ 0.609053] usbcore: registered new device driver usb
10641 09:33:23.017891 <6>[ 0.615152] pps_core: LinuxPPS API ver. 1 registered
10642 09:33:23.027837 <6>[ 0.620345] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10643 09:33:23.031093 <6>[ 0.629694] PTP clock support registered
10644 09:33:23.033965 <6>[ 0.633938] EDAC MC: Ver: 3.0.0
10645 09:33:23.041525 <6>[ 0.639097] FPGA manager framework
10646 09:33:23.048040 <6>[ 0.642786] Advanced Linux Sound Architecture Driver Initialized.
10647 09:33:23.051142 <6>[ 0.649575] vgaarb: loaded
10648 09:33:23.058213 <6>[ 0.652725] clocksource: Switched to clocksource arch_sys_counter
10649 09:33:23.061350 <5>[ 0.659146] VFS: Disk quotas dquot_6.6.0
10650 09:33:23.067820 <6>[ 0.663332] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10651 09:33:23.070767 <6>[ 0.670525] pnp: PnP ACPI: disabled
10652 09:33:23.079495 <6>[ 0.677247] NET: Registered PF_INET protocol family
10653 09:33:23.089244 <6>[ 0.682841] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10654 09:33:23.100818 <6>[ 0.695165] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10655 09:33:23.110889 <6>[ 0.703981] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10656 09:33:23.117495 <6>[ 0.711952] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10657 09:33:23.127446 <6>[ 0.720652] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10658 09:33:23.133739 <6>[ 0.730403] TCP: Hash tables configured (established 65536 bind 65536)
10659 09:33:23.140891 <6>[ 0.737266] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10660 09:33:23.150439 <6>[ 0.744465] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10661 09:33:23.156996 <6>[ 0.752168] NET: Registered PF_UNIX/PF_LOCAL protocol family
10662 09:33:23.163357 <6>[ 0.758314] RPC: Registered named UNIX socket transport module.
10663 09:33:23.166792 <6>[ 0.764470] RPC: Registered udp transport module.
10664 09:33:23.172982 <6>[ 0.769403] RPC: Registered tcp transport module.
10665 09:33:23.179282 <6>[ 0.774335] RPC: Registered tcp NFSv4.1 backchannel transport module.
10666 09:33:23.183041 <6>[ 0.781002] PCI: CLS 0 bytes, default 64
10667 09:33:23.186212 <6>[ 0.785292] Unpacking initramfs...
10668 09:33:23.196180 <6>[ 0.789374] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10669 09:33:23.202691 <6>[ 0.798027] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10670 09:33:23.209177 <6>[ 0.806902] kvm [1]: IPA Size Limit: 40 bits
10671 09:33:23.212193 <6>[ 0.811432] kvm [1]: GICv3: no GICV resource entry
10672 09:33:23.219171 <6>[ 0.816451] kvm [1]: disabling GICv2 emulation
10673 09:33:23.225918 <6>[ 0.821137] kvm [1]: GIC system register CPU interface enabled
10674 09:33:23.228963 <6>[ 0.827307] kvm [1]: vgic interrupt IRQ18
10675 09:33:23.235659 <6>[ 0.831663] kvm [1]: VHE mode initialized successfully
10676 09:33:23.238857 <5>[ 0.838244] Initialise system trusted keyrings
10677 09:33:23.248944 <6>[ 0.843047] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10678 09:33:23.255713 <6>[ 0.853230] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10679 09:33:23.262032 <5>[ 0.859668] NFS: Registering the id_resolver key type
10680 09:33:23.265499 <5>[ 0.864978] Key type id_resolver registered
10681 09:33:23.272144 <5>[ 0.869395] Key type id_legacy registered
10682 09:33:23.278616 <6>[ 0.873674] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10683 09:33:23.285410 <6>[ 0.880597] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10684 09:33:23.291825 <6>[ 0.888363] 9p: Installing v9fs 9p2000 file system support
10685 09:33:23.329525 <5>[ 0.926973] Key type asymmetric registered
10686 09:33:23.332944 <5>[ 0.931303] Asymmetric key parser 'x509' registered
10687 09:33:23.342341 <6>[ 0.936442] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10688 09:33:23.345856 <6>[ 0.944055] io scheduler mq-deadline registered
10689 09:33:23.349278 <6>[ 0.948815] io scheduler kyber registered
10690 09:33:23.368346 <6>[ 0.966042] EINJ: ACPI disabled.
10691 09:33:23.401846 <4>[ 0.992616] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10692 09:33:23.411458 <4>[ 1.003234] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10693 09:33:23.426798 <6>[ 1.024251] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10694 09:33:23.434830 <6>[ 1.032304] printk: console [ttyS0] disabled
10695 09:33:23.462517 <6>[ 1.056930] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10696 09:33:23.469018 <6>[ 1.066406] printk: console [ttyS0] enabled
10697 09:33:23.473800 <6>[ 1.066406] printk: console [ttyS0] enabled
10698 09:33:23.478935 <6>[ 1.075300] printk: bootconsole [mtk8250] disabled
10699 09:33:23.482213 <6>[ 1.075300] printk: bootconsole [mtk8250] disabled
10700 09:33:23.489135 <6>[ 1.086339] SuperH (H)SCI(F) driver initialized
10701 09:33:23.492410 <6>[ 1.091612] msm_serial: driver initialized
10702 09:33:23.506086 <6>[ 1.100557] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10703 09:33:23.516149 <6>[ 1.109109] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10704 09:33:23.522917 <6>[ 1.117652] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10705 09:33:23.533030 <6>[ 1.126278] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10706 09:33:23.542548 <6>[ 1.134986] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10707 09:33:23.549629 <6>[ 1.143699] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10708 09:33:23.558865 <6>[ 1.152239] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10709 09:33:23.565501 <6>[ 1.161038] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10710 09:33:23.575418 <6>[ 1.169580] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10711 09:33:23.587610 <6>[ 1.185146] loop: module loaded
10712 09:33:23.593926 <6>[ 1.190990] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10713 09:33:23.616719 <4>[ 1.214202] mtk-pmic-keys: Failed to locate of_node [id: -1]
10714 09:33:23.623528 <6>[ 1.221045] megasas: 07.719.03.00-rc1
10715 09:33:23.633130 <6>[ 1.230583] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10716 09:33:23.643068 <6>[ 1.240133] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10717 09:33:23.659447 <6>[ 1.256706] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10718 09:33:23.719561 <6>[ 1.310505] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10719 09:33:25.923578 <6>[ 3.521472] Freeing initrd memory: 59572K
10720 09:33:25.935525 <6>[ 3.533417] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10721 09:33:25.946617 <6>[ 3.544371] tun: Universal TUN/TAP device driver, 1.6
10722 09:33:25.950073 <6>[ 3.550444] thunder_xcv, ver 1.0
10723 09:33:25.952764 <6>[ 3.553950] thunder_bgx, ver 1.0
10724 09:33:25.956088 <6>[ 3.557446] nicpf, ver 1.0
10725 09:33:25.967084 <6>[ 3.561471] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10726 09:33:25.970254 <6>[ 3.568947] hns3: Copyright (c) 2017 Huawei Corporation.
10727 09:33:25.977093 <6>[ 3.574533] hclge is initializing
10728 09:33:25.980806 <6>[ 3.578108] e1000: Intel(R) PRO/1000 Network Driver
10729 09:33:25.986895 <6>[ 3.583237] e1000: Copyright (c) 1999-2006 Intel Corporation.
10730 09:33:25.990027 <6>[ 3.589250] e1000e: Intel(R) PRO/1000 Network Driver
10731 09:33:25.996860 <6>[ 3.594465] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10732 09:33:26.003865 <6>[ 3.600654] igb: Intel(R) Gigabit Ethernet Network Driver
10733 09:33:26.010077 <6>[ 3.606304] igb: Copyright (c) 2007-2014 Intel Corporation.
10734 09:33:26.016806 <6>[ 3.612139] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10735 09:33:26.023474 <6>[ 3.618658] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10736 09:33:26.026628 <6>[ 3.625116] sky2: driver version 1.30
10737 09:33:26.032865 <6>[ 3.630054] usbcore: registered new device driver r8152-cfgselector
10738 09:33:26.039543 <6>[ 3.636588] usbcore: registered new interface driver r8152
10739 09:33:26.046037 <6>[ 3.642411] VFIO - User Level meta-driver version: 0.3
10740 09:33:26.052487 <6>[ 3.650643] usbcore: registered new interface driver usb-storage
10741 09:33:26.059357 <6>[ 3.657088] usbcore: registered new device driver onboard-usb-hub
10742 09:33:26.068484 <6>[ 3.666281] mt6397-rtc mt6359-rtc: registered as rtc0
10743 09:33:26.078577 <6>[ 3.671748] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-18T09:33:25 UTC (1718703205)
10744 09:33:26.081422 <6>[ 3.681315] i2c_dev: i2c /dev entries driver
10745 09:33:26.095556 <4>[ 3.693332] cpu cpu0: supply cpu not found, using dummy regulator
10746 09:33:26.102355 <4>[ 3.699760] cpu cpu1: supply cpu not found, using dummy regulator
10747 09:33:26.108752 <4>[ 3.706167] cpu cpu2: supply cpu not found, using dummy regulator
10748 09:33:26.115328 <4>[ 3.712569] cpu cpu3: supply cpu not found, using dummy regulator
10749 09:33:26.122218 <4>[ 3.718967] cpu cpu4: supply cpu not found, using dummy regulator
10750 09:33:26.128058 <4>[ 3.725384] cpu cpu5: supply cpu not found, using dummy regulator
10751 09:33:26.135158 <4>[ 3.731784] cpu cpu6: supply cpu not found, using dummy regulator
10752 09:33:26.141368 <4>[ 3.738183] cpu cpu7: supply cpu not found, using dummy regulator
10753 09:33:26.161296 <6>[ 3.758830] cpu cpu0: EM: created perf domain
10754 09:33:26.164488 <6>[ 3.763776] cpu cpu4: EM: created perf domain
10755 09:33:26.171283 <6>[ 3.769368] sdhci: Secure Digital Host Controller Interface driver
10756 09:33:26.178408 <6>[ 3.775798] sdhci: Copyright(c) Pierre Ossman
10757 09:33:26.185011 <6>[ 3.780753] Synopsys Designware Multimedia Card Interface Driver
10758 09:33:26.191243 <6>[ 3.787403] sdhci-pltfm: SDHCI platform and OF driver helper
10759 09:33:26.194448 <6>[ 3.787528] mmc0: CQHCI version 5.10
10760 09:33:26.201480 <6>[ 3.797890] ledtrig-cpu: registered to indicate activity on CPUs
10761 09:33:26.208088 <6>[ 3.804943] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10762 09:33:26.214351 <6>[ 3.811995] usbcore: registered new interface driver usbhid
10763 09:33:26.217754 <6>[ 3.817818] usbhid: USB HID core driver
10764 09:33:26.227718 <6>[ 3.822012] spi_master spi0: will run message pump with realtime priority
10765 09:33:26.268688 <6>[ 3.860074] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10766 09:33:26.287411 <6>[ 3.875042] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10767 09:33:26.294383 <6>[ 3.889549] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10768 09:33:26.297941 <6>[ 3.895878] cros-ec-spi spi0.0: Chrome EC device registered
10769 09:33:26.304479 <6>[ 3.901891] mmc0: Command Queue Engine enabled
10770 09:33:26.311043 <6>[ 3.906621] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10771 09:33:26.317571 <6>[ 3.914317] mmcblk0: mmc0:0001 DA4128 116 GiB
10772 09:33:26.325487 <6>[ 3.923333] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10773 09:33:26.332984 <6>[ 3.931040] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10774 09:33:26.343367 <6>[ 3.934767] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10775 09:33:26.346454 <6>[ 3.937006] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10776 09:33:26.352786 <6>[ 3.946973] NET: Registered PF_PACKET protocol family
10777 09:33:26.359670 <6>[ 3.951498] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10778 09:33:26.362926 <6>[ 3.956193] 9pnet: Installing 9P2000 support
10779 09:33:26.369549 <5>[ 3.967189] Key type dns_resolver registered
10780 09:33:26.372718 <6>[ 3.972146] registered taskstats version 1
10781 09:33:26.379388 <5>[ 3.976523] Loading compiled-in X.509 certificates
10782 09:33:26.407953 <4>[ 3.999548] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10783 09:33:26.418265 <4>[ 4.010299] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10784 09:33:26.433513 <6>[ 4.031554] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10785 09:33:26.440923 <6>[ 4.038566] xhci-mtk 11200000.usb: xHCI Host Controller
10786 09:33:26.447177 <6>[ 4.044081] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10787 09:33:26.457321 <6>[ 4.051945] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10788 09:33:26.464252 <6>[ 4.061385] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10789 09:33:26.470257 <6>[ 4.067472] xhci-mtk 11200000.usb: xHCI Host Controller
10790 09:33:26.477329 <6>[ 4.072958] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10791 09:33:26.483812 <6>[ 4.080708] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10792 09:33:26.490713 <6>[ 4.088570] hub 1-0:1.0: USB hub found
10793 09:33:26.494125 <6>[ 4.092620] hub 1-0:1.0: 1 port detected
10794 09:33:26.504025 <6>[ 4.096974] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10795 09:33:26.506864 <6>[ 4.105708] hub 2-0:1.0: USB hub found
10796 09:33:26.510337 <6>[ 4.109746] hub 2-0:1.0: 1 port detected
10797 09:33:26.518655 <6>[ 4.116795] mtk-msdc 11f70000.mmc: Got CD GPIO
10798 09:33:26.533798 <6>[ 4.127891] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10799 09:33:26.543316 <6>[ 4.136273] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10800 09:33:26.549501 <6>[ 4.144614] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10801 09:33:26.559682 <6>[ 4.152957] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10802 09:33:26.566560 <6>[ 4.161296] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10803 09:33:26.576296 <6>[ 4.169634] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10804 09:33:26.582999 <6>[ 4.177974] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10805 09:33:26.592728 <6>[ 4.186313] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10806 09:33:26.599492 <6>[ 4.194651] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10807 09:33:26.609613 <6>[ 4.202990] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10808 09:33:26.616184 <6>[ 4.211327] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10809 09:33:26.626350 <6>[ 4.219670] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10810 09:33:26.632837 <6>[ 4.228009] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10811 09:33:26.642624 <6>[ 4.236346] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10812 09:33:26.649028 <6>[ 4.244691] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10813 09:33:26.655725 <6>[ 4.253444] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10814 09:33:26.663128 <6>[ 4.260672] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10815 09:33:26.669952 <6>[ 4.267511] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10816 09:33:26.680342 <6>[ 4.274369] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10817 09:33:26.686568 <6>[ 4.281341] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10818 09:33:26.693381 <6>[ 4.288252] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10819 09:33:26.702937 <6>[ 4.297390] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10820 09:33:26.712799 <6>[ 4.306510] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10821 09:33:26.723166 <6>[ 4.315804] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10822 09:33:26.732385 <6>[ 4.325270] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10823 09:33:26.742149 <6>[ 4.334738] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10824 09:33:26.748937 <6>[ 4.343857] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10825 09:33:26.758775 <6>[ 4.353324] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10826 09:33:26.768948 <6>[ 4.362444] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10827 09:33:26.778850 <6>[ 4.371744] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10828 09:33:26.789050 <6>[ 4.381905] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10829 09:33:26.798848 <6>[ 4.393559] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10830 09:33:26.926455 <6>[ 4.521025] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10831 09:33:27.080897 <6>[ 4.678851] hub 1-1:1.0: USB hub found
10832 09:33:27.084339 <6>[ 4.683374] hub 1-1:1.0: 4 ports detected
10833 09:33:27.096095 <6>[ 4.693985] hub 1-1:1.0: USB hub found
10834 09:33:27.099406 <6>[ 4.698363] hub 1-1:1.0: 4 ports detected
10835 09:33:27.206552 <6>[ 4.801310] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10836 09:33:27.233143 <6>[ 4.830779] hub 2-1:1.0: USB hub found
10837 09:33:27.235813 <6>[ 4.835272] hub 2-1:1.0: 3 ports detected
10838 09:33:27.247423 <6>[ 4.845142] hub 2-1:1.0: USB hub found
10839 09:33:27.250131 <6>[ 4.849570] hub 2-1:1.0: 3 ports detected
10840 09:33:27.418404 <6>[ 5.012995] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10841 09:33:27.550615 <6>[ 5.148525] hub 1-1.4:1.0: USB hub found
10842 09:33:27.553786 <6>[ 5.153206] hub 1-1.4:1.0: 2 ports detected
10843 09:33:27.567088 <6>[ 5.165016] hub 1-1.4:1.0: USB hub found
10844 09:33:27.570484 <6>[ 5.169619] hub 1-1.4:1.0: 2 ports detected
10845 09:33:27.630857 <6>[ 5.225248] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10846 09:33:27.738685 <6>[ 5.333676] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10847 09:33:27.775077 <4>[ 5.369742] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10848 09:33:27.784776 <4>[ 5.378843] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10849 09:33:27.824648 <6>[ 5.422565] r8152 2-1.3:1.0 eth0: v1.12.13
10850 09:33:27.866107 <6>[ 5.461063] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10851 09:33:28.061793 <6>[ 5.656876] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10852 09:33:29.499982 <6>[ 7.098678] r8152 2-1.3:1.0 eth0: carrier on
10853 09:33:31.607076 <5>[ 7.124835] Sending DHCP requests .., OK
10854 09:33:31.612816 <6>[ 9.209128] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10855 09:33:31.616528 <6>[ 9.217425] IP-Config: Complete:
10856 09:33:31.629686 <6>[ 9.220922] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10857 09:33:31.636103 <6>[ 9.231632] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10858 09:33:31.642687 <6>[ 9.240247] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10859 09:33:31.649137 <6>[ 9.240256] nameserver0=192.168.201.1
10860 09:33:31.652805 <6>[ 9.252396] clk: Disabling unused clocks
10861 09:33:31.656734 <6>[ 9.257941] ALSA device list:
10862 09:33:31.662959 <6>[ 9.261191] No soundcards found.
10863 09:33:31.670664 <6>[ 9.268975] Freeing unused kernel memory: 8512K
10864 09:33:31.673588 <6>[ 9.273909] Run /init as init process
10865 09:33:31.707035 <6>[ 9.305684] NET: Registered PF_INET6 protocol family
10866 09:33:31.714195 <6>[ 9.312584] Segment Routing with IPv6
10867 09:33:31.717808 <6>[ 9.316558] In-situ OAM (IOAM) with IPv6
10868 09:33:31.762904 <30>[ 9.334994] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10869 09:33:31.770137 <30>[ 9.368276] systemd[1]: Detected architecture arm64.
10870 09:33:31.770718
10871 09:33:31.776108 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10872 09:33:31.776642
10873 09:33:31.790519 <30>[ 9.389089] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10874 09:33:31.936488 <30>[ 9.531839] systemd[1]: Queued start job for default target graphical.target.
10875 09:33:31.983689 <30>[ 9.579018] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10876 09:33:31.990003 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10877 09:33:32.010708 <30>[ 9.605620] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10878 09:33:32.020380 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10879 09:33:32.038726 <30>[ 9.633758] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10880 09:33:32.048533 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10881 09:33:32.066442 <30>[ 9.661503] systemd[1]: Created slice user.slice - User and Session Slice.
10882 09:33:32.073012 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10883 09:33:32.093784 <30>[ 9.685214] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10884 09:33:32.103001 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10885 09:33:32.121251 <30>[ 9.713234] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10886 09:33:32.127754 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10887 09:33:32.156027 <30>[ 9.741576] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10888 09:33:32.166735 <30>[ 9.761474] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10889 09:33:32.173066 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10890 09:33:32.190249 <30>[ 9.785441] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10891 09:33:32.200442 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10892 09:33:32.218592 <30>[ 9.813520] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10893 09:33:32.227991 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10894 09:33:32.242844 <30>[ 9.841526] systemd[1]: Reached target paths.target - Path Units.
10895 09:33:32.253361 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10896 09:33:32.270519 <30>[ 9.865508] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10897 09:33:32.276749 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10898 09:33:32.290866 <30>[ 9.889134] systemd[1]: Reached target slices.target - Slice Units.
10899 09:33:32.300503 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10900 09:33:32.314916 <30>[ 9.913148] systemd[1]: Reached target swap.target - Swaps.
10901 09:33:32.321063 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10902 09:33:32.342261 <30>[ 9.937096] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10903 09:33:32.351547 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10904 09:33:32.370713 <30>[ 9.965985] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10905 09:33:32.381013 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10906 09:33:32.400025 <30>[ 9.995041] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10907 09:33:32.409653 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10908 09:33:32.426214 <30>[ 10.021647] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10909 09:33:32.435968 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10910 09:33:32.454721 <30>[ 10.049675] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10911 09:33:32.461381 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10912 09:33:32.478662 <30>[ 10.073671] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10913 09:33:32.488062 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10914 09:33:32.506865 <30>[ 10.101501] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10915 09:33:32.516176 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10916 09:33:32.569966 <30>[ 10.165282] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10917 09:33:32.576746 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10918 09:33:32.595836 <30>[ 10.191038] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10919 09:33:32.602131 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10920 09:33:32.624499 <30>[ 10.219576] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10921 09:33:32.630939 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10922 09:33:32.656259 <30>[ 10.245255] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10923 09:33:32.669968 <30>[ 10.265378] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10924 09:33:32.679649 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10925 09:33:32.703094 <30>[ 10.298573] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10926 09:33:32.710135 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10927 09:33:32.735255 <30>[ 10.330286] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10928 09:33:32.745077 Startin<6>[ 10.339675] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10929 09:33:32.751532 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10930 09:33:32.775530 <30>[ 10.370522] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10931 09:33:32.782126 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10932 09:33:32.842380 <30>[ 10.437706] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10933 09:33:32.851944 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10934 09:33:32.875446 <30>[ 10.470793] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10935 09:33:32.882337 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10936 09:33:32.938094 <30>[ 10.533605] systemd[1]: Starting systemd-journald.service - Journal Service...
10937 09:33:32.944853 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10938 09:33:32.965074 <30>[ 10.560373] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10939 09:33:32.971884 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10940 09:33:32.996105 <30>[ 10.587945] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10941 09:33:33.002352 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10942 09:33:33.026372 <30>[ 10.621701] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10943 09:33:33.035922 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10944 09:33:33.057364 <30>[ 10.652457] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10945 09:33:33.067260 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10946 09:33:33.092547 <30>[ 10.687996] systemd[1]: Started systemd-journald.service - Journal Service.
10947 09:33:33.099437 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10948 09:33:33.122283 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10949 09:33:33.139387 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10950 09:33:33.158613 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10951 09:33:33.178752 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10952 09:33:33.199379 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10953 09:33:33.219643 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10954 09:33:33.239125 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10955 09:33:33.260608 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10956 09:33:33.281224 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10957 09:33:33.300724 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10958 09:33:33.323495 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10959 09:33:33.348441 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10960 09:33:33.366240 See 'systemctl status systemd-remount-fs.service' for details.
10961 09:33:33.390986 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10962 09:33:33.416697 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10963 09:33:33.482365 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10964 09:33:33.506652 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10965 09:33:33.526755 <46>[ 11.122259] systemd-journald[195]: Received client request to flush runtime journal.
10966 09:33:33.533514 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10967 09:33:33.558427 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10968 09:33:33.583624 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10969 09:33:33.616235 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10970 09:33:33.639184 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10971 09:33:33.659288 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10972 09:33:33.679248 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10973 09:33:33.698996 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10974 09:33:33.758973 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10975 09:33:33.786538 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10976 09:33:33.802055 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10977 09:33:33.821510 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10978 09:33:33.866269 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10979 09:33:33.887061 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10980 09:33:33.914132 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10981 09:33:33.939146 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10982 09:33:33.984815 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10983 09:33:34.151905 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10984 09:33:34.178844 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10985 09:33:34.212925 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10986 09:33:34.240138 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10987 09:33:34.260030 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10988 09:33:34.279410 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10989 09:33:34.305310 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Se<6>[ 11.899432] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10990 09:33:34.305856 t.
10991 09:33:34.315315 <3>[ 11.908627] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10992 09:33:34.321197 <6>[ 11.915333] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10993 09:33:34.328003 <6>[ 11.915564] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10994 09:33:34.337703 <6>[ 11.915570] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10995 09:33:34.344460 <4>[ 11.915642] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10996 09:33:34.354153 <6>[ 11.916134] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10997 09:33:34.360944 <6>[ 11.916136] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10998 09:33:34.370455 <3>[ 11.917357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10999 09:33:34.377267 <6>[ 11.924414] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
11000 09:33:34.387241 <6>[ 11.924429] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
11001 09:33:34.393646 <6>[ 11.924438] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
11002 09:33:34.403821 <6>[ 11.924444] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
11003 09:33:34.410410 <6>[ 11.924937] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11004 09:33:34.420214 <3>[ 11.933032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11005 09:33:34.426907 <3>[ 11.939731] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11006 09:33:34.436748 <6>[ 11.940922] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11007 09:33:34.443416 <3>[ 11.950217] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11008 09:33:34.453179 <6>[ 11.965699] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11009 09:33:34.459694 <3>[ 11.966317] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11010 09:33:34.466214 <6>[ 11.987717] remoteproc remoteproc0: scp is available
11011 09:33:34.473285 <4>[ 11.987943] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11012 09:33:34.479618 <3>[ 11.989942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11013 09:33:34.486637 <6>[ 11.997790] remoteproc remoteproc0: powering up scp
11014 09:33:34.493094 <3>[ 12.006860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11015 09:33:34.503363 <4>[ 12.007586] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11016 09:33:34.509841 <6>[ 12.015615] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11017 09:33:34.516232 <6>[ 12.015654] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11018 09:33:34.522845 <3>[ 12.023862] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11019 09:33:34.529838 <6>[ 12.023976] mc: Linux media interface: v0.10
11020 09:33:34.536701 <6>[ 12.057008] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11021 09:33:34.540214 <6>[ 12.057609] videodev: Linux video capture interface: v2.00
11022 09:33:34.549983 <3>[ 12.064177] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11023 09:33:34.556631 <6>[ 12.082193] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11024 09:33:34.566198 <4>[ 12.082879] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11025 09:33:34.569756 <4>[ 12.082879] Fallback method does not support PEC.
11026 09:33:34.579864 <3>[ 12.084778] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11027 09:33:34.587491 <3>[ 12.084785] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11028 09:33:34.594062 <3>[ 12.084924] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11029 09:33:34.600804 <6>[ 12.089933] pci_bus 0000:00: root bus resource [bus 00-ff]
11030 09:33:34.607510 <3>[ 12.098010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11031 09:33:34.617537 <3>[ 12.099851] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11032 09:33:34.624634 <6>[ 12.105305] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11033 09:33:34.631865 <3>[ 12.113729] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11034 09:33:34.641730 <6>[ 12.119375] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11035 09:33:34.652418 <3>[ 12.127453] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11036 09:33:34.655125 <6>[ 12.131996] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11037 09:33:34.665376 <6>[ 12.133519] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11038 09:33:34.675631 <6>[ 12.133927] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11039 09:33:34.685813 <3>[ 12.138517] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11040 09:33:34.692599 <3>[ 12.139617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11041 09:33:34.703073 <3>[ 12.139637] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11042 09:33:34.709418 <3>[ 12.140874] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11043 09:33:34.716662 <6>[ 12.141540] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11044 09:33:34.726151 <6>[ 12.141618] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11045 09:33:34.733420 <6>[ 12.141626] remoteproc remoteproc0: remote processor scp is now up
11046 09:33:34.740532 <6>[ 12.143868] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11047 09:33:34.750310 <6>[ 12.145375] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11048 09:33:34.757008 <6>[ 12.164768] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11049 09:33:34.760555 <6>[ 12.174238] pci 0000:00:00.0: supports D1 D2
11050 09:33:34.767279 <6>[ 12.174248] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11051 09:33:34.776856 <6>[ 12.175647] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11052 09:33:34.779907 <6>[ 12.183182] Bluetooth: Core ver 2.22
11053 09:33:34.790100 <6>[ 12.186183] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11054 09:33:34.793720 <6>[ 12.190721] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11055 09:33:34.803383 <3>[ 12.194520] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11056 09:33:34.812918 <3>[ 12.195228] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
11057 09:33:34.816461 <6>[ 12.198840] NET: Registered PF_BLUETOOTH protocol family
11058 09:33:34.826650 <6>[ 12.204511] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11059 09:33:34.833094 <3>[ 12.208762] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11060 09:33:34.842934 <3>[ 12.209633] power_supply sbs-5-000b: driver failed to report `health' property: -6
11061 09:33:34.849496 <6>[ 12.212566] Bluetooth: HCI device and connection manager initialized
11062 09:33:34.856022 <6>[ 12.214070] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11063 09:33:34.865998 <6>[ 12.215106] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11064 09:33:34.872548 <6>[ 12.215216] usbcore: registered new interface driver uvcvideo
11065 09:33:34.882224 <6>[ 12.221351] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11066 09:33:34.885795 <6>[ 12.228474] Bluetooth: HCI socket layer initialized
11067 09:33:34.895940 <3>[ 12.231869] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11068 09:33:34.902380 <6>[ 12.236551] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11069 09:33:34.909222 <6>[ 12.246446] Bluetooth: L2CAP socket layer initialized
11070 09:33:34.915894 <3>[ 12.253705] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11071 09:33:34.922024 <6>[ 12.254629] pci 0000:01:00.0: supports D1 D2
11072 09:33:34.929025 <6>[ 12.255136] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11073 09:33:34.932133 <6>[ 12.260787] Bluetooth: SCO socket layer initialized
11074 09:33:34.938258 <6>[ 12.270848] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11075 09:33:34.948572 <3>[ 12.274552] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11076 09:33:34.955012 <6>[ 12.352792] usbcore: registered new interface driver btusb
11077 09:33:34.965119 <4>[ 12.353481] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11078 09:33:34.971380 <3>[ 12.353494] Bluetooth: hci0: Failed to load firmware file (-2)
11079 09:33:34.974782 <3>[ 12.353497] Bluetooth: hci0: Failed to set up firmware (-2)
11080 09:33:34.988110 <4>[ 12.353501] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11081 09:33:34.995051 <6>[ 12.376850] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11082 09:33:35.001046 <6>[ 12.597441] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11083 09:33:35.011173 <6>[ 12.597446] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11084 09:33:35.018072 <6>[ 12.597455] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11085 09:33:35.024326 <6>[ 12.597467] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11086 09:33:35.034309 <6>[ 12.597480] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11087 09:33:35.037490 <6>[ 12.597492] pci 0000:00:00.0: PCI bridge to [bus 01]
11088 09:33:35.047342 <6>[ 12.597498] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11089 09:33:35.054077 <6>[ 12.597650] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11090 09:33:35.060961 [[0;32m OK [<6>[ 12.657616] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11091 09:33:35.067046 0m] Started [0;<6>[ 12.665384] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11092 09:33:35.073956 1;39mfstrim.timer[0m - Discard unused blocks once a week.
11093 09:33:35.093311 [[0;32m OK [0m] Reached targ<5>[ 12.687562] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11094 09:33:35.097039 et [0;1;39mtimers.target[0m - Timer Units.
11095 09:33:35.113119 <5>[ 12.708505] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11096 09:33:35.119655 <5>[ 12.716227] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11097 09:33:35.129787 <4>[ 12.724861] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11098 09:33:35.136088 <6>[ 12.733793] cfg80211: failed to load regulatory.db
11099 09:33:35.142413 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11100 09:33:35.163096 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11101 09:33:35.188058 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11102 09:33:35.197803 <6>[ 12.792954] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11103 09:33:35.204322 <6>[ 12.800511] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11104 09:33:35.222258 <6>[ 12.821017] mt7921e 0000:01:00.0: ASIC revision: 79610010
11105 09:33:35.240293 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11106 09:33:35.277130 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11107 09:33:35.306832 <46>[ 12.889132] systemd-journald[195]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.2 (1540 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11108 09:33:35.322901 <46>[ 12.910474] systemd-journald[195]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11109 09:33:35.330199 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11110 09:33:35.339607 <6>[ 12.934092] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11111 09:33:35.340104 <6>[ 12.934092]
11112 09:33:35.346734 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11113 09:33:35.380491 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11114 09:33:35.438480 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11115 09:33:35.461867 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11116 09:33:35.482071 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11117 09:33:35.502321 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11118 09:33:35.554912 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11119 09:33:35.576133 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11120 09:33:35.594249 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11121 09:33:35.605027 <6>[ 13.201248] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11122 09:33:35.615041 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11123 09:33:35.634216 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11124 09:33:35.687531 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11125 09:33:35.712133 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11126 09:33:35.737993 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11127 09:33:35.804177 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11128 09:33:35.824262 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11129 09:33:35.852338 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11130 09:33:35.903332
11131 09:33:35.906464 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11132 09:33:35.906929
11133 09:33:35.910084 debian-bookworm-arm64 login: root (automatic login)
11134 09:33:35.910683
11135 09:33:35.922203 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
11136 09:33:35.922762
11137 09:33:35.929124 The programs included with the Debian GNU/Linux system are free software;
11138 09:33:35.935007 the exact distribution terms for each program are described in the
11139 09:33:35.938586 individual files in /usr/share/doc/*/copyright.
11140 09:33:35.939135
11141 09:33:35.944997 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11142 09:33:35.948341 permitted by applicable law.
11143 09:33:35.949849 Matched prompt #10: / #
11145 09:33:35.950992 Setting prompt string to ['/ #']
11146 09:33:35.951454 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11148 09:33:35.952541 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11149 09:33:35.953101 start: 2.2.6 expect-shell-connection (timeout 00:02:37) [common]
11150 09:33:35.953518 Setting prompt string to ['/ #']
11151 09:33:35.953867 Forcing a shell prompt, looking for ['/ #']
11153 09:33:36.004800 / #
11154 09:33:36.005426 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11155 09:33:36.005836 Waiting using forced prompt support (timeout 00:02:30)
11156 09:33:36.011095
11157 09:33:36.012122 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11158 09:33:36.012698 start: 2.2.7 export-device-env (timeout 00:02:36) [common]
11159 09:33:36.013205 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11160 09:33:36.013699 end: 2.2 depthcharge-retry (duration 00:02:24) [common]
11161 09:33:36.014206 end: 2 depthcharge-action (duration 00:02:24) [common]
11162 09:33:36.014805 start: 3 lava-test-retry (timeout 00:07:12) [common]
11163 09:33:36.015275 start: 3.1 lava-test-shell (timeout 00:07:12) [common]
11164 09:33:36.015693 Using namespace: common
11166 09:33:36.116864 / # #
11167 09:33:36.117503 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11168 09:33:36.123552 #
11169 09:33:36.124432 Using /lava-14407680
11171 09:33:36.225684 / # export SHELL=/bin/sh
11172 09:33:36.232372 export SHELL=/bin/sh
11174 09:33:36.334024 / # . /lava-14407680/environment
11175 09:33:36.341070 . /lava-14407680/environment
11177 09:33:36.442793 / # /lava-14407680/bin/lava-test-runner /lava-14407680/0
11178 09:33:36.443470 Test shell timeout: 10s (minimum of the action and connection timeout)
11179 09:33:36.449976 /lava-14407680/bin/lava-test-runner /lava-14407680/0
11180 09:33:36.475604 + export TESTRUN<8>[ 14.072694] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 14407680_1.5.2.3.1>
11181 09:33:36.476436 Received signal: <STARTRUN> 0_igt-gpu-panfrost 14407680_1.5.2.3.1
11182 09:33:36.476847 Starting test lava.0_igt-gpu-panfrost (14407680_1.5.2.3.1)
11183 09:33:36.477277 Skipping test definition patterns.
11184 09:33:36.479134 _ID=0_igt-gpu-panfrost
11185 09:33:36.485260 + cd /la<6>[ 14.081683] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11186 09:33:36.488958 va-14407680/0/tests/0_igt-gpu-panfrost
11187 09:33:36.489545 + cat uuid
11188 09:33:36.492645 + UUID=14407680_1.5.2.3.1
11189 09:33:36.493202 + set +x
11190 09:33:36.502265 + IGT_FORCE_DRIVER=panfrost /usr/bin/ig<8>[ 14.098467] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11191 09:33:36.503118 Received signal: <TESTSET> START panfrost_gem_new
11192 09:33:36.503614 Starting test_set panfrost_gem_new
11193 09:33:36.508766 t-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11194 09:33:36.521180 <14>[ 14.120158] [IGT] panfrost_gem_new: executing
11195 09:33:36.527896 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.127488] [IGT] panfrost_gem_new: exiting, ret=77
11196 09:33:36.530881 h64) (Linux: 6.1.92-cip22 aarch64)
11197 09:33:36.544439 Using IGT_SRANDOM=1718703216 for randomisati<8>[ 14.139129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11198 09:33:36.545072 on
11199 09:33:36.545763 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11201 09:33:36.554586 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11202 09:33:36.555142 Test requirement: !(fd<0)
11203 09:33:36.560381 No known gpu found for chipset flags 0x32 (panfrost)
11204 09:33:36.564123 Last errno: 2, No such file or directory
11205 09:33:36.567218 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11206 09:33:36.574256 <14>[ 14.172229] [IGT] panfrost_gem_new: executing
11207 09:33:36.583742 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.180583] [IGT] panfrost_gem_new: exiting, ret=77
11208 09:33:36.584360 .92-cip22 aarch64)
11209 09:33:36.586923 Using IGT_SRANDOM=1718703216 for randomisation
11210 09:33:36.600005 Test require<8>[ 14.192471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11211 09:33:36.600828 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11213 09:33:36.603396 ment not met in function drm_open_driver, file ../lib/drmtest.c:694:
11214 09:33:36.603876 Test requirement: !(fd<0)
11215 09:33:36.610203 No known gpu found for chipset flags 0x32 (panfrost)
11216 09:33:36.613683 Last errno: 2, No such file or directory
11217 09:33:36.616638 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11218 09:33:36.623492 <14>[ 14.222638] [IGT] panfrost_gem_new: executing
11219 09:33:36.633751 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.230666] [IGT] panfrost_gem_new: exiting, ret=77
11220 09:33:36.634345 .92-cip22 aarch64)
11221 09:33:36.646864 Using IGT_SRANDOM=1718703216 for randomisati<8>[ 14.242285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11222 09:33:36.647330 on
11223 09:33:36.647947 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11225 09:33:36.653412 Test requirement not met in <8>[ 14.251339] <LAVA_SIGNAL_TESTSET STOP>
11226 09:33:36.654242 Received signal: <TESTSET> STOP
11227 09:33:36.654652 Closing test_set panfrost_gem_new
11228 09:33:36.656594 function drm_open_driver, file ../lib/drmtest.c:694:
11229 09:33:36.659915 Test requirement: !(fd<0)
11230 09:33:36.663605 No known gpu found for chipset flags 0x32 (panfrost)
11231 09:33:36.666380 Last errno: 2, No such file or directory
11232 09:33:36.676213 [1mSubtest gem<8>[ 14.273082] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11233 09:33:36.676631 -new-zeroed: SKIP (0.000s)[0m
11234 09:33:36.677219 Received signal: <TESTSET> START panfrost_get_param
11235 09:33:36.677556 Starting test_set panfrost_get_param
11236 09:33:36.696981 <14>[ 14.296012] [IGT] panfrost_get_param: executing
11237 09:33:36.706656 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.303265] [IGT] panfrost_get_param: exiting, ret=77
11238 09:33:36.707194 h64) (Linux: 6.1.92-cip22 aarch64)
11239 09:33:36.716648 Using IGT_SRANDOM=1718703216<8>[ 14.313689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11240 09:33:36.717325 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11242 09:33:36.719935 for randomisation
11243 09:33:36.726598 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11244 09:33:36.729889 Test requirement: !(fd<0)
11245 09:33:36.736050 No known gpu found for chipset <14>[ 14.335691] [IGT] panfrost_get_param: executing
11246 09:33:36.739603 flags 0x32 (panfrost)
11247 09:33:36.745979 Last errn<14>[ 14.342897] [IGT] panfrost_get_param: exiting, ret=77
11248 09:33:36.746477 o: 2, No such file or directory
11249 09:33:36.756559 [1mSubtest base-params: SKIP (<8>[ 14.353294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11250 09:33:36.757236 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11252 09:33:36.759450 0.000s)[0m
11253 09:33:36.765855 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11254 09:33:36.769414 Using IGT_SRANDOM=1718703216 for randomisation
11255 09:33:36.776044 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11256 09:33:36.779215 Test requirement: !(fd<0)
11257 09:33:36.785759 No known gpu found for chipset flags 0x32 (panfros<14>[ 14.385484] [IGT] panfrost_get_param: executing
11258 09:33:36.789322 t)
11259 09:33:36.792570 Last errno: 2, No such file or directory
11260 09:33:36.795857 [<14>[ 14.394766] [IGT] panfrost_get_param: exiting, ret=77
11261 09:33:36.802306 1mSubtest get-bad-param: SKIP (0.000s)[0m
11262 09:33:36.812020 IGT-Version: 1.28-ga44ebfe (aarch64)<8>[ 14.406564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11263 09:33:36.812710 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11265 09:33:36.815743 (Linux: 6.1.92-cip22 aarch64)
11266 09:33:36.818534 <8>[ 14.416791] <LAVA_SIGNAL_TESTSET STOP>
11267 09:33:36.819203 Received signal: <TESTSET> STOP
11268 09:33:36.819550 Closing test_set panfrost_get_param
11269 09:33:36.822248 Using IGT_SRANDOM=1718703216 for randomisation
11270 09:33:36.828750 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11271 09:33:36.832033 Test requirement: !(fd<0)
11272 09:33:36.842194 No known gpu found for chipset flags 0x32 (panfrost<8>[ 14.438809] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11273 09:33:36.842824 )
11274 09:33:36.843474 Received signal: <TESTSET> START panfrost_prime
11275 09:33:36.843854 Starting test_set panfrost_prime
11276 09:33:36.845545 Last errno: 2, No such file or directory
11277 09:33:36.848408 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11278 09:33:36.860413 <14>[ 14.459521] [IGT] panfrost_prime: executing
11279 09:33:36.866909 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.466255] [IGT] panfrost_prime: exiting, ret=77
11280 09:33:36.870238 h64) (Linux: 6.1.92-cip22 aarch64)
11281 09:33:36.879961 Using IGT_SRANDOM=1718703216<8>[ 14.476465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11282 09:33:36.880755 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11284 09:33:36.886848 for randomisati<8>[ 14.486239] <LAVA_SIGNAL_TESTSET STOP>
11285 09:33:36.887308 on
11286 09:33:36.887926 Received signal: <TESTSET> STOP
11287 09:33:36.888308 Closing test_set panfrost_prime
11288 09:33:36.893202 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11289 09:33:36.896591 Test requirement: !(fd<0)
11290 09:33:36.900012 No known gpu found for chipset flags 0x32 (panfrost)
11291 09:33:36.909590 Last errno: 2, No such fi<8>[ 14.506756] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11292 09:33:36.910006 le or directory
11293 09:33:36.910639 Received signal: <TESTSET> START panfrost_submit
11294 09:33:36.910985 Starting test_set panfrost_submit
11295 09:33:36.913249 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11296 09:33:36.926775 <14>[ 14.525855] [IGT] panfrost_submit: executing
11297 09:33:36.933309 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.532610] [IGT] panfrost_submit: exiting, ret=77
11298 09:33:36.936728 h64) (Linux: 6.1.92-cip22 aarch64)
11299 09:33:36.946051 Using IGT_SRANDOM=1718703216<8>[ 14.543236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11300 09:33:36.946855 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11302 09:33:36.950093 for randomisation
11303 09:33:36.956464 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11304 09:33:36.959565 Test requirement: !(fd<0)
11305 09:33:36.966628 No known gpu found for chipset <14>[ 14.564511] [IGT] panfrost_submit: executing
11306 09:33:36.967072 flags 0x32 (panfrost)
11307 09:33:36.972459 Last errn<14>[ 14.571849] [IGT] panfrost_submit: exiting, ret=77
11308 09:33:36.976326 o: 2, No such file or directory
11309 09:33:36.986129 [1mSubtest pan-submit: SKIP (0<8>[ 14.581921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11310 09:33:36.987003 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11312 09:33:36.989311 .000s)[0m
11313 09:33:36.993020 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11314 09:33:36.999482 Using IGT_SRANDOM=1718703216 for randomisation
11315 09:33:37.005785 Test requirement not met in func<14>[ 14.604346] [IGT] panfrost_submit: executing
11316 09:33:37.012732 tion drm_open_driver, file ../li<14>[ 14.611670] [IGT] panfrost_submit: exiting, ret=77
11317 09:33:37.015683 b/drmtest.c:694:
11318 09:33:37.019119 Test requirement: !(fd<0)
11319 09:33:37.029090 No known gpu found <8>[ 14.622077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11320 09:33:37.029918 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11322 09:33:37.031902 for chipset flags 0x32 (panfrost)
11323 09:33:37.035648 Last errno: 2, No such file or directory
11324 09:33:37.038957 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11325 09:33:37.045532 IGT-Version: 1.28-ga44ebfe (<14>[ 14.644885] [IGT] panfrost_submit: executing
11326 09:33:37.055022 aarch64) (Linux: 6.1.92-cip22 aa<14>[ 14.652293] [IGT] panfrost_submit: exiting, ret=77
11327 09:33:37.055459 rch64)
11328 09:33:37.058959 Using IGT_SRANDOM=1718703217 for randomisation
11329 09:33:37.068791 Test req<8>[ 14.662955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11330 09:33:37.069628 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11332 09:33:37.075038 uirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11333 09:33:37.077952 Test requirement: !(fd<0)
11334 09:33:37.081315 No known gpu found for chipset flags 0x32 (panfrost)
11335 09:33:37.088379 Last <14>[ 14.686188] [IGT] panfrost_submit: executing
11336 09:33:37.094759 errno: 2, No such file or direct<14>[ 14.693419] [IGT] panfrost_submit: exiting, ret=77
11337 09:33:37.095221 ory
11338 09:33:37.107914 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0<8>[ 14.703650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11339 09:33:37.108752 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11341 09:33:37.111529 m
11342 09:33:37.114375 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11343 09:33:37.121244 Using IGT_SRANDOM=1718703217 for randomisation
11344 09:33:37.127527 Test requirement not met in function drm_<14>[ 14.727258] [IGT] panfrost_submit: executing
11345 09:33:37.137609 open_driver, file ../lib/drmtest<14>[ 14.734349] [IGT] panfrost_submit: exiting, ret=77
11346 09:33:37.138089 .c:694:
11347 09:33:37.138516 Test requirement: !(fd<0)
11348 09:33:37.150996 No known gpu found for chipset flags 0x32 (p<8>[ 14.746280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11349 09:33:37.151551 anfrost)
11350 09:33:37.152189 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11352 09:33:37.157801 Last errno: 2, No such file or directory
11353 09:33:37.160909 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11354 09:33:37.167368 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11355 09:33:37.170231 Using IGT_SRANDOM=1718703217 for randomisation
11356 09:33:37.180417 Test requirement not met in function drm<14>[ 14.778708] [IGT] panfrost_submit: executing
11357 09:33:37.183466 _open_driver, file ../lib/drmtest.c:694:
11358 09:33:37.190459 Test r<14>[ 14.787151] [IGT] panfrost_submit: exiting, ret=77
11359 09:33:37.190971 equirement: !(fd<0)
11360 09:33:37.197062 No known gpu found for chipset flags 0x32 (panfrost)
11361 09:33:37.203325 Last errno: 2, No suc<8>[ 14.800251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11362 09:33:37.204052 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11364 09:33:37.206932 h file or directory
11365 09:33:37.209879 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11366 09:33:37.216868 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11367 09:33:37.223314 Using IGT_SRANDOM=171<14>[ 14.822070] [IGT] panfrost_submit: executing
11368 09:33:37.226722 8703217 for randomisation
11369 09:33:37.233101 Test <14>[ 14.830515] [IGT] panfrost_submit: exiting, ret=77
11370 09:33:37.246338 requirement not met in function drm_open_driver, file ../lib/drm<8>[ 14.840268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11371 09:33:37.246861 test.c:694:
11372 09:33:37.247494 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11374 09:33:37.249600 Test requirement: !(fd<0)
11375 09:33:37.252927 No known gpu found for chipset flags 0x32 (panfrost)
11376 09:33:37.256061 Last errno: 2, No such file or directory
11377 09:33:37.262805 [1mSubtest pan-submit-e<14>[ 14.863000] [IGT] panfrost_submit: executing
11378 09:33:37.273107 rror-bad-out-sync: SKIP (0.000s)<14>[ 14.870125] [IGT] panfrost_submit: exiting, ret=77
11379 09:33:37.273535 [0m
11380 09:33:37.286137 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 <8>[ 14.880203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11381 09:33:37.286676 aarch64)
11382 09:33:37.287279 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11384 09:33:37.292258 Using IGT_SRANDOM=1718<8>[ 14.890800] <LAVA_SIGNAL_TESTSET STOP>
11385 09:33:37.292936 Received signal: <TESTSET> STOP
11386 09:33:37.293286 Closing test_set panfrost_submit
11387 09:33:37.299093 703217 for rando<8>[ 14.897227] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 14407680_1.5.2.3.1>
11388 09:33:37.299855 Received signal: <ENDRUN> 0_igt-gpu-panfrost 14407680_1.5.2.3.1
11389 09:33:37.300259 Ending use of test pattern.
11390 09:33:37.300580 Ending test lava.0_igt-gpu-panfrost (14407680_1.5.2.3.1), duration 0.82
11392 09:33:37.302113 misation
11393 09:33:37.309008 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11394 09:33:37.312628 Test requirement: !(fd<0)
11395 09:33:37.315731 No known gpu found for chipset flags 0x32 (panfrost)
11396 09:33:37.318719 Last errno: 2, No such file or directory
11397 09:33:37.322673 [1mSubtest pan-reset: SKIP (0.000s)[0m
11398 09:33:37.328677 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11399 09:33:37.331959 Using IGT_SRANDOM=1718703217 for randomisation
11400 09:33:37.338527 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11401 09:33:37.342099 Test requirement: !(fd<0)
11402 09:33:37.345256 No known gpu found for chipset flags 0x32 (panfrost)
11403 09:33:37.352001 Last errno: 2, No such file or directory
11404 09:33:37.355048 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11405 09:33:37.361495 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11406 09:33:37.364691 Using IGT_SRANDOM=1718703217 for randomisation
11407 09:33:37.371598 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11408 09:33:37.374965 Test requirement: !(fd<0)
11409 09:33:37.378419 No known gpu found for chipset flags 0x32 (panfrost)
11410 09:33:37.381378 Last errno: 2, No such file or directory
11411 09:33:37.387943 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11412 09:33:37.388407 + set +x
11413 09:33:37.391532 <LAVA_TEST_RUNNER EXIT>
11414 09:33:37.392272 ok: lava_test_shell seems to have completed
11415 09:33:37.393998 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11416 09:33:37.394568 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11417 09:33:37.395088 end: 3 lava-test-retry (duration 00:00:01) [common]
11418 09:33:37.395595 start: 4 finalize (timeout 00:07:10) [common]
11419 09:33:37.396035 start: 4.1 power-off (timeout 00:00:30) [common]
11420 09:33:37.396866 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11421 09:33:37.650249 >> Command sent successfully.
11422 09:33:37.661498 Returned 0 in 0 seconds
11423 09:33:37.762821 end: 4.1 power-off (duration 00:00:00) [common]
11425 09:33:37.764366 start: 4.2 read-feedback (timeout 00:07:10) [common]
11426 09:33:37.765732 Listened to connection for namespace 'common' for up to 1s
11427 09:33:38.766405 Finalising connection for namespace 'common'
11428 09:33:38.767088 Disconnecting from shell: Finalise
11429 09:33:38.767528 / #
11430 09:33:38.868548 end: 4.2 read-feedback (duration 00:00:01) [common]
11431 09:33:38.869273 end: 4 finalize (duration 00:00:01) [common]
11432 09:33:38.869861 Cleaning after the job
11433 09:33:38.870421 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/ramdisk
11434 09:33:38.901608 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/kernel
11435 09:33:38.930017 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/dtb
11436 09:33:38.930313 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407680/tftp-deploy-7ld5grgi/modules
11437 09:33:38.937213 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407680
11438 09:33:39.044855 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407680
11439 09:33:39.045045 Job finished correctly