Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 09:23:34.663085 lava-dispatcher, installed at version: 2024.03
2 09:23:34.663277 start: 0 validate
3 09:23:34.663411 Start time: 2024-06-18 09:23:34.663402+00:00 (UTC)
4 09:23:34.663542 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:23:34.663673 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:23:34.916237 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:23:34.916970 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:23:35.184866 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:23:35.185663 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:24:35.501182 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:24:35.501427 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:24:35.997962 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:24:35.998142 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:24:36.256213 validate duration: 61.59
16 09:24:36.256494 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:24:36.256597 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:24:36.256685 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:24:36.256808 Not decompressing ramdisk as can be used compressed.
20 09:24:36.256893 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 09:24:36.256963 saving as /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/ramdisk/initrd.cpio.gz
22 09:24:36.257034 total size: 5628169 (5 MB)
23 09:24:39.639098 progress 0 % (0 MB)
24 09:24:39.640729 progress 5 % (0 MB)
25 09:24:39.642323 progress 10 % (0 MB)
26 09:24:39.643714 progress 15 % (0 MB)
27 09:24:39.645338 progress 20 % (1 MB)
28 09:24:39.646743 progress 25 % (1 MB)
29 09:24:39.648283 progress 30 % (1 MB)
30 09:24:39.649856 progress 35 % (1 MB)
31 09:24:39.651246 progress 40 % (2 MB)
32 09:24:39.652787 progress 45 % (2 MB)
33 09:24:39.654204 progress 50 % (2 MB)
34 09:24:39.655763 progress 55 % (2 MB)
35 09:24:39.657412 progress 60 % (3 MB)
36 09:24:39.658869 progress 65 % (3 MB)
37 09:24:39.660397 progress 70 % (3 MB)
38 09:24:39.661808 progress 75 % (4 MB)
39 09:24:39.663326 progress 80 % (4 MB)
40 09:24:39.664679 progress 85 % (4 MB)
41 09:24:39.666241 progress 90 % (4 MB)
42 09:24:39.667754 progress 95 % (5 MB)
43 09:24:39.669133 progress 100 % (5 MB)
44 09:24:39.669393 5 MB downloaded in 3.41 s (1.57 MB/s)
45 09:24:39.669549 end: 1.1.1 http-download (duration 00:00:03) [common]
47 09:24:39.669784 end: 1.1 download-retry (duration 00:00:03) [common]
48 09:24:39.669876 start: 1.2 download-retry (timeout 00:09:57) [common]
49 09:24:39.669960 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 09:24:39.670115 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:24:39.670218 saving as /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/kernel/Image
52 09:24:39.670309 total size: 54813184 (52 MB)
53 09:24:39.670385 No compression specified
54 09:25:19.943036 progress 0 % (0 MB)
55 09:25:19.989209 progress 5 % (2 MB)
56 09:25:20.006916 progress 10 % (5 MB)
57 09:25:20.021490 progress 15 % (7 MB)
58 09:25:20.036126 progress 20 % (10 MB)
59 09:25:20.050613 progress 25 % (13 MB)
60 09:25:20.065019 progress 30 % (15 MB)
61 09:25:20.079516 progress 35 % (18 MB)
62 09:25:20.094320 progress 40 % (20 MB)
63 09:25:20.109108 progress 45 % (23 MB)
64 09:25:20.123960 progress 50 % (26 MB)
65 09:25:20.138640 progress 55 % (28 MB)
66 09:25:20.154138 progress 60 % (31 MB)
67 09:25:20.168546 progress 65 % (34 MB)
68 09:25:20.182999 progress 70 % (36 MB)
69 09:25:20.198421 progress 75 % (39 MB)
70 09:25:20.213842 progress 80 % (41 MB)
71 09:25:20.228289 progress 85 % (44 MB)
72 09:25:20.242850 progress 90 % (47 MB)
73 09:25:20.257442 progress 95 % (49 MB)
74 09:25:20.271356 progress 100 % (52 MB)
75 09:25:20.271602 52 MB downloaded in 40.60 s (1.29 MB/s)
76 09:25:20.271768 end: 1.2.1 http-download (duration 00:00:41) [common]
78 09:25:20.272013 end: 1.2 download-retry (duration 00:00:41) [common]
79 09:25:20.272110 start: 1.3 download-retry (timeout 00:09:16) [common]
80 09:25:20.272197 start: 1.3.1 http-download (timeout 00:09:16) [common]
81 09:25:20.272333 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:25:20.272410 saving as /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/dtb/mt8192-asurada-spherion-r0.dtb
83 09:25:20.272487 total size: 47258 (0 MB)
84 09:25:20.272573 No compression specified
85 09:25:20.531661 progress 69 % (0 MB)
86 09:25:20.533325 progress 100 % (0 MB)
87 09:25:20.534242 0 MB downloaded in 0.26 s (0.17 MB/s)
88 09:25:20.534990 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:25:20.536381 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:25:20.536840 start: 1.4 download-retry (timeout 00:09:16) [common]
92 09:25:20.537380 start: 1.4.1 http-download (timeout 00:09:16) [common]
93 09:25:20.538030 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 09:25:20.538389 saving as /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/nfsrootfs/full.rootfs.tar
95 09:25:20.538750 total size: 120894716 (115 MB)
96 09:25:20.539072 Using unxz to decompress xz
97 09:25:20.799668 progress 0 % (0 MB)
98 09:25:21.155009 progress 5 % (5 MB)
99 09:25:21.508612 progress 10 % (11 MB)
100 09:25:21.902406 progress 15 % (17 MB)
101 09:25:22.245907 progress 20 % (23 MB)
102 09:25:22.550073 progress 25 % (28 MB)
103 09:25:22.921188 progress 30 % (34 MB)
104 09:25:23.270696 progress 35 % (40 MB)
105 09:25:23.437813 progress 40 % (46 MB)
106 09:25:23.620116 progress 45 % (51 MB)
107 09:25:23.940966 progress 50 % (57 MB)
108 09:25:24.326361 progress 55 % (63 MB)
109 09:25:24.680953 progress 60 % (69 MB)
110 09:25:25.033469 progress 65 % (74 MB)
111 09:25:25.393220 progress 70 % (80 MB)
112 09:25:25.765298 progress 75 % (86 MB)
113 09:25:26.113775 progress 80 % (92 MB)
114 09:25:26.455616 progress 85 % (98 MB)
115 09:25:26.814880 progress 90 % (103 MB)
116 09:25:27.153327 progress 95 % (109 MB)
117 09:25:27.521192 progress 100 % (115 MB)
118 09:25:27.526895 115 MB downloaded in 6.99 s (16.50 MB/s)
119 09:25:27.527158 end: 1.4.1 http-download (duration 00:00:07) [common]
121 09:25:27.527421 end: 1.4 download-retry (duration 00:00:07) [common]
122 09:25:27.527511 start: 1.5 download-retry (timeout 00:09:09) [common]
123 09:25:27.527598 start: 1.5.1 http-download (timeout 00:09:09) [common]
124 09:25:27.527763 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:25:27.527835 saving as /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/modules/modules.tar
126 09:25:27.527896 total size: 8619356 (8 MB)
127 09:25:27.527960 Using unxz to decompress xz
128 09:25:27.780510 progress 0 % (0 MB)
129 09:25:27.800888 progress 5 % (0 MB)
130 09:25:27.826577 progress 10 % (0 MB)
131 09:25:27.852043 progress 15 % (1 MB)
132 09:25:27.876819 progress 20 % (1 MB)
133 09:25:27.902090 progress 25 % (2 MB)
134 09:25:27.927163 progress 30 % (2 MB)
135 09:25:27.952377 progress 35 % (2 MB)
136 09:25:27.977993 progress 40 % (3 MB)
137 09:25:28.003816 progress 45 % (3 MB)
138 09:25:28.029742 progress 50 % (4 MB)
139 09:25:28.055781 progress 55 % (4 MB)
140 09:25:28.081059 progress 60 % (4 MB)
141 09:25:28.106784 progress 65 % (5 MB)
142 09:25:28.136201 progress 70 % (5 MB)
143 09:25:28.162185 progress 75 % (6 MB)
144 09:25:28.185820 progress 80 % (6 MB)
145 09:25:28.209663 progress 85 % (7 MB)
146 09:25:28.233884 progress 90 % (7 MB)
147 09:25:28.262694 progress 95 % (7 MB)
148 09:25:28.293662 progress 100 % (8 MB)
149 09:25:28.298369 8 MB downloaded in 0.77 s (10.67 MB/s)
150 09:25:28.298616 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:25:28.298880 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:25:28.298971 start: 1.6 prepare-tftp-overlay (timeout 00:09:08) [common]
154 09:25:28.299071 start: 1.6.1 extract-nfsrootfs (timeout 00:09:08) [common]
155 09:25:31.713387 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14407630/extract-nfsrootfs-mb0x_k8b
156 09:25:31.713599 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 09:25:31.713702 start: 1.6.2 lava-overlay (timeout 00:09:05) [common]
158 09:25:31.713877 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy
159 09:25:31.714007 makedir: /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin
160 09:25:31.714107 makedir: /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/tests
161 09:25:31.714204 makedir: /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/results
162 09:25:31.714305 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-add-keys
163 09:25:31.714443 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-add-sources
164 09:25:31.714571 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-background-process-start
165 09:25:31.714701 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-background-process-stop
166 09:25:31.714825 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-common-functions
167 09:25:31.714957 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-echo-ipv4
168 09:25:31.715082 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-install-packages
169 09:25:31.715206 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-installed-packages
170 09:25:31.715326 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-os-build
171 09:25:31.715447 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-probe-channel
172 09:25:31.715572 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-probe-ip
173 09:25:31.715693 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-target-ip
174 09:25:31.715811 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-target-mac
175 09:25:31.715931 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-target-storage
176 09:25:31.716053 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-test-case
177 09:25:31.716174 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-test-event
178 09:25:31.716292 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-test-feedback
179 09:25:31.716410 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-test-raise
180 09:25:31.716528 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-test-reference
181 09:25:31.716648 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-test-runner
182 09:25:31.716766 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-test-set
183 09:25:31.716886 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-test-shell
184 09:25:31.717010 Updating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-add-keys (debian)
185 09:25:31.717158 Updating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-add-sources (debian)
186 09:25:31.717457 Updating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-install-packages (debian)
187 09:25:31.717598 Updating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-installed-packages (debian)
188 09:25:31.717742 Updating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/bin/lava-os-build (debian)
189 09:25:31.717861 Creating /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/environment
190 09:25:31.717964 LAVA metadata
191 09:25:31.718030 - LAVA_JOB_ID=14407630
192 09:25:31.718092 - LAVA_DISPATCHER_IP=192.168.201.1
193 09:25:31.718188 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:05) [common]
194 09:25:31.718253 skipped lava-vland-overlay
195 09:25:31.718326 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 09:25:31.718402 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:05) [common]
197 09:25:31.718461 skipped lava-multinode-overlay
198 09:25:31.718530 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 09:25:31.718605 start: 1.6.2.3 test-definition (timeout 00:09:05) [common]
200 09:25:31.718675 Loading test definitions
201 09:25:31.718759 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:05) [common]
202 09:25:31.718826 Using /lava-14407630 at stage 0
203 09:25:31.719101 uuid=14407630_1.6.2.3.1 testdef=None
204 09:25:31.719186 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 09:25:31.719267 start: 1.6.2.3.2 test-overlay (timeout 00:09:05) [common]
206 09:25:31.719705 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 09:25:31.719920 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:05) [common]
209 09:25:31.720452 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 09:25:31.720677 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:05) [common]
212 09:25:31.721193 runner path: /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/0/tests/0_timesync-off test_uuid 14407630_1.6.2.3.1
213 09:25:31.721389 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 09:25:31.721610 start: 1.6.2.3.5 git-repo-action (timeout 00:09:05) [common]
216 09:25:31.721679 Using /lava-14407630 at stage 0
217 09:25:31.721772 Fetching tests from https://github.com/kernelci/test-definitions.git
218 09:25:31.721856 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/0/tests/1_kselftest-alsa'
219 09:25:36.611814 Running '/usr/bin/git checkout kernelci.org
220 09:25:36.758102 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 09:25:36.758894 uuid=14407630_1.6.2.3.5 testdef=None
222 09:25:36.759057 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 09:25:36.759295 start: 1.6.2.3.6 test-overlay (timeout 00:08:59) [common]
225 09:25:36.760060 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 09:25:36.760303 start: 1.6.2.3.7 test-install-overlay (timeout 00:08:59) [common]
228 09:25:36.761333 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 09:25:36.761571 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:08:59) [common]
231 09:25:36.762488 runner path: /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/0/tests/1_kselftest-alsa test_uuid 14407630_1.6.2.3.5
232 09:25:36.762580 BOARD='mt8192-asurada-spherion-r0'
233 09:25:36.762645 BRANCH='cip'
234 09:25:36.762703 SKIPFILE='/dev/null'
235 09:25:36.762759 SKIP_INSTALL='True'
236 09:25:36.762813 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 09:25:36.762868 TST_CASENAME=''
238 09:25:36.762922 TST_CMDFILES='alsa'
239 09:25:36.763057 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 09:25:36.763264 Creating lava-test-runner.conf files
242 09:25:36.763326 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407630/lava-overlay-mzuo2kvy/lava-14407630/0 for stage 0
243 09:25:36.763415 - 0_timesync-off
244 09:25:36.763481 - 1_kselftest-alsa
245 09:25:36.763579 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 09:25:36.763666 start: 1.6.2.4 compress-overlay (timeout 00:08:59) [common]
247 09:25:44.317269 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 09:25:44.317426 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:08:52) [common]
249 09:25:44.317522 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 09:25:44.317615 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 09:25:44.317702 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:52) [common]
252 09:25:44.482158 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 09:25:44.482544 start: 1.6.4 extract-modules (timeout 00:08:52) [common]
254 09:25:44.482660 extracting modules file /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407630/extract-nfsrootfs-mb0x_k8b
255 09:25:44.708018 extracting modules file /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407630/extract-overlay-ramdisk-kpgtqz97/ramdisk
256 09:25:44.932198 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 09:25:44.932368 start: 1.6.5 apply-overlay-tftp (timeout 00:08:51) [common]
258 09:25:44.932466 [common] Applying overlay to NFS
259 09:25:44.932535 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407630/compress-overlay-fkl6l7dh/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407630/extract-nfsrootfs-mb0x_k8b
260 09:25:45.861980 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 09:25:45.862149 start: 1.6.6 configure-preseed-file (timeout 00:08:50) [common]
262 09:25:45.862245 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 09:25:45.862335 start: 1.6.7 compress-ramdisk (timeout 00:08:50) [common]
264 09:25:45.862418 Building ramdisk /var/lib/lava/dispatcher/tmp/14407630/extract-overlay-ramdisk-kpgtqz97/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407630/extract-overlay-ramdisk-kpgtqz97/ramdisk
265 09:25:46.207364 >> 130466 blocks
266 09:25:48.234801 rename /var/lib/lava/dispatcher/tmp/14407630/extract-overlay-ramdisk-kpgtqz97/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/ramdisk/ramdisk.cpio.gz
267 09:25:48.235245 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 09:25:48.235371 start: 1.6.8 prepare-kernel (timeout 00:08:48) [common]
269 09:25:48.235493 start: 1.6.8.1 prepare-fit (timeout 00:08:48) [common]
270 09:25:48.235596 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/kernel/Image']
271 09:26:02.383150 Returned 0 in 14 seconds
272 09:26:02.483770 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/kernel/image.itb
273 09:26:02.837013 output: FIT description: Kernel Image image with one or more FDT blobs
274 09:26:02.837429 output: Created: Tue Jun 18 10:26:02 2024
275 09:26:02.837510 output: Image 0 (kernel-1)
276 09:26:02.837579 output: Description:
277 09:26:02.837643 output: Created: Tue Jun 18 10:26:02 2024
278 09:26:02.837700 output: Type: Kernel Image
279 09:26:02.837761 output: Compression: lzma compressed
280 09:26:02.837818 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
281 09:26:02.837876 output: Architecture: AArch64
282 09:26:02.837938 output: OS: Linux
283 09:26:02.837995 output: Load Address: 0x00000000
284 09:26:02.838049 output: Entry Point: 0x00000000
285 09:26:02.838104 output: Hash algo: crc32
286 09:26:02.838158 output: Hash value: 4137a6e7
287 09:26:02.838213 output: Image 1 (fdt-1)
288 09:26:02.838266 output: Description: mt8192-asurada-spherion-r0
289 09:26:02.838319 output: Created: Tue Jun 18 10:26:02 2024
290 09:26:02.838374 output: Type: Flat Device Tree
291 09:26:02.838427 output: Compression: uncompressed
292 09:26:02.838478 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 09:26:02.838531 output: Architecture: AArch64
294 09:26:02.838583 output: Hash algo: crc32
295 09:26:02.838634 output: Hash value: 0f8e4d2e
296 09:26:02.838686 output: Image 2 (ramdisk-1)
297 09:26:02.838737 output: Description: unavailable
298 09:26:02.838788 output: Created: Tue Jun 18 10:26:02 2024
299 09:26:02.838840 output: Type: RAMDisk Image
300 09:26:02.838908 output: Compression: Unknown Compression
301 09:26:02.838973 output: Data Size: 18734435 Bytes = 18295.35 KiB = 17.87 MiB
302 09:26:02.839025 output: Architecture: AArch64
303 09:26:02.839077 output: OS: Linux
304 09:26:02.839158 output: Load Address: unavailable
305 09:26:02.839209 output: Entry Point: unavailable
306 09:26:02.839260 output: Hash algo: crc32
307 09:26:02.839311 output: Hash value: c7a4337b
308 09:26:02.839364 output: Default Configuration: 'conf-1'
309 09:26:02.839419 output: Configuration 0 (conf-1)
310 09:26:02.839471 output: Description: mt8192-asurada-spherion-r0
311 09:26:02.839522 output: Kernel: kernel-1
312 09:26:02.839573 output: Init Ramdisk: ramdisk-1
313 09:26:02.839625 output: FDT: fdt-1
314 09:26:02.839676 output: Loadables: kernel-1
315 09:26:02.839728 output:
316 09:26:02.839932 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 09:26:02.840027 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 09:26:02.840132 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 09:26:02.840223 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:33) [common]
320 09:26:02.840302 No LXC device requested
321 09:26:02.840378 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 09:26:02.840465 start: 1.8 deploy-device-env (timeout 00:08:33) [common]
323 09:26:02.840541 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 09:26:02.840607 Checking files for TFTP limit of 4294967296 bytes.
325 09:26:02.841104 end: 1 tftp-deploy (duration 00:01:27) [common]
326 09:26:02.841211 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 09:26:02.841344 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 09:26:02.841471 substitutions:
329 09:26:02.841540 - {DTB}: 14407630/tftp-deploy-pu_owxyt/dtb/mt8192-asurada-spherion-r0.dtb
330 09:26:02.841604 - {INITRD}: 14407630/tftp-deploy-pu_owxyt/ramdisk/ramdisk.cpio.gz
331 09:26:02.841663 - {KERNEL}: 14407630/tftp-deploy-pu_owxyt/kernel/Image
332 09:26:02.841720 - {LAVA_MAC}: None
333 09:26:02.841775 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14407630/extract-nfsrootfs-mb0x_k8b
334 09:26:02.841831 - {NFS_SERVER_IP}: 192.168.201.1
335 09:26:02.841885 - {PRESEED_CONFIG}: None
336 09:26:02.841939 - {PRESEED_LOCAL}: None
337 09:26:02.841992 - {RAMDISK}: 14407630/tftp-deploy-pu_owxyt/ramdisk/ramdisk.cpio.gz
338 09:26:02.842046 - {ROOT_PART}: None
339 09:26:02.842098 - {ROOT}: None
340 09:26:02.842151 - {SERVER_IP}: 192.168.201.1
341 09:26:02.842203 - {TEE}: None
342 09:26:02.842255 Parsed boot commands:
343 09:26:02.842306 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 09:26:02.842481 Parsed boot commands: tftpboot 192.168.201.1 14407630/tftp-deploy-pu_owxyt/kernel/image.itb 14407630/tftp-deploy-pu_owxyt/kernel/cmdline
345 09:26:02.842571 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 09:26:02.842651 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 09:26:02.842738 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 09:26:02.842819 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 09:26:02.842885 Not connected, no need to disconnect.
350 09:26:02.842956 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 09:26:02.843039 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 09:26:02.843103 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 09:26:02.847427 Setting prompt string to ['lava-test: # ']
354 09:26:02.847895 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 09:26:02.848032 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 09:26:02.848177 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 09:26:02.848356 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 09:26:02.848608 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
359 09:26:16.899224 Returned 0 in 14 seconds
360 09:26:16.999934 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 09:26:17.000307 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 09:26:17.000407 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 09:26:17.000492 Setting prompt string to 'Starting depthcharge on Spherion...'
365 09:26:17.000559 Changing prompt to 'Starting depthcharge on Spherion...'
366 09:26:17.000625 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 09:26:17.001142 [Enter `^Ec?' for help]
368 09:26:17.001279
369 09:26:17.001371
370 09:26:17.001456 F0: 102B 0000
371 09:26:17.001547
372 09:26:17.001636 F3: 1001 0000 [0200]
373 09:26:17.001727
374 09:26:17.001813 F3: 1001 0000
375 09:26:17.001904
376 09:26:17.001991 F7: 102D 0000
377 09:26:17.002075
378 09:26:17.002158 F1: 0000 0000
379 09:26:17.002243
380 09:26:17.002303 V0: 0000 0000 [0001]
381 09:26:17.002357
382 09:26:17.002411 00: 0007 8000
383 09:26:17.002501
384 09:26:17.002585 01: 0000 0000
385 09:26:17.002659
386 09:26:17.002714 BP: 0C00 0209 [0000]
387 09:26:17.002786
388 09:26:17.002866 G0: 1182 0000
389 09:26:17.002939
390 09:26:17.002994 EC: 0000 0021 [4000]
391 09:26:17.003048
392 09:26:17.003101 S7: 0000 0000 [0000]
393 09:26:17.003161
394 09:26:17.003215 CC: 0000 0000 [0001]
395 09:26:17.003268
396 09:26:17.003325 T0: 0000 0040 [010F]
397 09:26:17.003381
398 09:26:17.003433 Jump to BL
399 09:26:17.003486
400 09:26:17.003550
401 09:26:17.003632
402 09:26:17.003748 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 09:26:17.003835 ARM64: Exception handlers installed.
404 09:26:17.003918 ARM64: Testing exception
405 09:26:17.004001 ARM64: Done test exception
406 09:26:17.004085 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 09:26:17.004190 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 09:26:17.004291 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 09:26:17.004376 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 09:26:17.004460 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 09:26:17.004544 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 09:26:17.004629 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 09:26:17.004713 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 09:26:17.004797 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 09:26:17.004880 WDT: Last reset was cold boot
416 09:26:17.004963 SPI1(PAD0) initialized at 2873684 Hz
417 09:26:17.005045 SPI5(PAD0) initialized at 992727 Hz
418 09:26:17.005128 VBOOT: Loading verstage.
419 09:26:17.005211 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 09:26:17.005322 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 09:26:17.005378 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 09:26:17.005433 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 09:26:17.005487 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 09:26:17.005540 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 09:26:17.005594 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 09:26:17.005647
427 09:26:17.005699
428 09:26:17.005751 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 09:26:17.005804 ARM64: Exception handlers installed.
430 09:26:17.005857 ARM64: Testing exception
431 09:26:17.005908 ARM64: Done test exception
432 09:26:17.005961 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 09:26:17.006014 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 09:26:17.006067 Probing TPM: . done!
435 09:26:17.006119 TPM ready after 0 ms
436 09:26:17.006171 Connected to device vid:did:rid of 1ae0:0028:00
437 09:26:17.006225 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
438 09:26:17.006278 Initialized TPM device CR50 revision 0
439 09:26:17.006331 tlcl_send_startup: Startup return code is 0
440 09:26:17.006384 TPM: setup succeeded
441 09:26:17.006436 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 09:26:17.006488 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 09:26:17.006541 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 09:26:17.006593 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 09:26:17.006646 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 09:26:17.006735 in-header: 03 07 00 00 08 00 00 00
447 09:26:17.006787 in-data: aa e4 47 04 13 02 00 00
448 09:26:17.006839 Chrome EC: UHEPI supported
449 09:26:17.006890 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 09:26:17.006943 in-header: 03 a9 00 00 08 00 00 00
451 09:26:17.006996 in-data: 84 60 60 08 00 00 00 00
452 09:26:17.007048 Phase 1
453 09:26:17.007100 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 09:26:17.007153 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 09:26:17.007207 VB2:vb2_check_recovery() Recovery was requested manually
456 09:26:17.007259 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 09:26:17.007312 Recovery requested (1009000e)
458 09:26:17.007364 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 09:26:17.007417 tlcl_extend: response is 0
460 09:26:17.007470 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 09:26:17.007522 tlcl_extend: response is 0
462 09:26:17.007575 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 09:26:17.007628 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
464 09:26:17.007680 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 09:26:17.007733
466 09:26:17.007786
467 09:26:17.007838 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 09:26:17.007892 ARM64: Exception handlers installed.
469 09:26:17.007944 ARM64: Testing exception
470 09:26:17.007996 ARM64: Done test exception
471 09:26:17.008048 pmic_efuse_setting: Set efuses in 11 msecs
472 09:26:17.008100 pmwrap_interface_init: Select PMIF_VLD_RDY
473 09:26:17.008153 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 09:26:17.008205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 09:26:17.008452 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 09:26:17.008586 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 09:26:17.008715 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 09:26:17.008843 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 09:26:17.008972 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 09:26:17.009100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 09:26:17.009230 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 09:26:17.009400 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 09:26:17.009528 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 09:26:17.009614 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 09:26:17.009671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 09:26:17.009725 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 09:26:17.009779 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 09:26:17.009833 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 09:26:17.009886 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 09:26:17.009947 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 09:26:17.010002 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 09:26:17.010055 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 09:26:17.010116 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 09:26:17.010171 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 09:26:17.010224 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 09:26:17.010277 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 09:26:17.010333 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 09:26:17.010386 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 09:26:17.010438 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 09:26:17.010491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 09:26:17.010544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 09:26:17.010597 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 09:26:17.010650 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 09:26:17.010702 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 09:26:17.010755 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 09:26:17.010808 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 09:26:17.010860 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 09:26:17.010913 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 09:26:17.010966 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 09:26:17.011018 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 09:26:17.011070 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 09:26:17.011122 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 09:26:17.011175 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 09:26:17.011228 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 09:26:17.011280 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 09:26:17.011332 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 09:26:17.011384 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 09:26:17.011437 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 09:26:17.011489 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 09:26:17.011549 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 09:26:17.011604 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 09:26:17.011657 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 09:26:17.011709 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 09:26:17.011769 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 09:26:17.011824 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 09:26:17.011877 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 09:26:17.011937 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 09:26:17.011993 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 09:26:17.012047 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 09:26:17.012100 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 09:26:17.012185 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 09:26:17.012268 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
533 09:26:17.012352 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 09:26:17.012438 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
535 09:26:17.012521 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 09:26:17.012605 [RTC]rtc_get_frequency_meter,154: input=15, output=853
537 09:26:17.012688 [RTC]rtc_get_frequency_meter,154: input=7, output=725
538 09:26:17.012771 [RTC]rtc_get_frequency_meter,154: input=11, output=789
539 09:26:17.012855 [RTC]rtc_get_frequency_meter,154: input=13, output=821
540 09:26:17.012938 [RTC]rtc_get_frequency_meter,154: input=12, output=805
541 09:26:17.013021 [RTC]rtc_get_frequency_meter,154: input=11, output=789
542 09:26:17.013104 [RTC]rtc_get_frequency_meter,154: input=12, output=806
543 09:26:17.013187 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
544 09:26:17.013294 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
545 09:26:17.013580 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 09:26:17.013640 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 09:26:17.013695 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 09:26:17.013749 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 09:26:17.013801 ADC[4]: Raw value=904064 ID=7
550 09:26:17.013855 ADC[3]: Raw value=213916 ID=1
551 09:26:17.013907 RAM Code: 0x71
552 09:26:17.013960 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 09:26:17.014014 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 09:26:17.014067 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 09:26:17.014121 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 09:26:17.014175 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 09:26:17.014228 in-header: 03 07 00 00 08 00 00 00
558 09:26:17.014281 in-data: aa e4 47 04 13 02 00 00
559 09:26:17.014334 Chrome EC: UHEPI supported
560 09:26:17.014386 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 09:26:17.014439 in-header: 03 a9 00 00 08 00 00 00
562 09:26:17.014491 in-data: 84 60 60 08 00 00 00 00
563 09:26:17.014543 MRC: failed to locate region type 0.
564 09:26:17.014595 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 09:26:17.014648 DRAM-K: Running full calibration
566 09:26:17.014701 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 09:26:17.014753 header.status = 0x0
568 09:26:17.014805 header.version = 0x6 (expected: 0x6)
569 09:26:17.014857 header.size = 0xd00 (expected: 0xd00)
570 09:26:17.014909 header.flags = 0x0
571 09:26:17.014961 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 09:26:17.015013 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
573 09:26:17.015066 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 09:26:17.015119 dram_init: ddr_geometry: 2
575 09:26:17.015171 [EMI] MDL number = 2
576 09:26:17.015224 [EMI] Get MDL freq = 0
577 09:26:17.015276 dram_init: ddr_type: 0
578 09:26:17.015328 is_discrete_lpddr4: 1
579 09:26:17.015381 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 09:26:17.015433
581 09:26:17.015485
582 09:26:17.015536 [Bian_co] ETT version 0.0.0.1
583 09:26:17.015589 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 09:26:17.015642
585 09:26:17.015694 dramc_set_vcore_voltage set vcore to 650000
586 09:26:17.015746 Read voltage for 800, 4
587 09:26:17.015798 Vio18 = 0
588 09:26:17.015849 Vcore = 650000
589 09:26:17.015901 Vdram = 0
590 09:26:17.015953 Vddq = 0
591 09:26:17.016005 Vmddr = 0
592 09:26:17.016056 dram_init: config_dvfs: 1
593 09:26:17.016108 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 09:26:17.016161 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 09:26:17.016214 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 09:26:17.016266 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 09:26:17.016319 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 09:26:17.016371 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 09:26:17.016424 MEM_TYPE=3, freq_sel=18
600 09:26:17.016476 sv_algorithm_assistance_LP4_1600
601 09:26:17.016556 ============ PULL DRAM RESETB DOWN ============
602 09:26:17.016650 ========== PULL DRAM RESETB DOWN end =========
603 09:26:17.016734 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 09:26:17.016802 ===================================
605 09:26:17.016855 LPDDR4 DRAM CONFIGURATION
606 09:26:17.016907 ===================================
607 09:26:17.016960 EX_ROW_EN[0] = 0x0
608 09:26:17.017012 EX_ROW_EN[1] = 0x0
609 09:26:17.017064 LP4Y_EN = 0x0
610 09:26:17.017116 WORK_FSP = 0x0
611 09:26:17.017168 WL = 0x2
612 09:26:17.017219 RL = 0x2
613 09:26:17.017319 BL = 0x2
614 09:26:17.017373 RPST = 0x0
615 09:26:17.017425 RD_PRE = 0x0
616 09:26:17.017477 WR_PRE = 0x1
617 09:26:17.017529 WR_PST = 0x0
618 09:26:17.017581 DBI_WR = 0x0
619 09:26:17.017633 DBI_RD = 0x0
620 09:26:17.017717 OTF = 0x1
621 09:26:17.017769 ===================================
622 09:26:17.017822 ===================================
623 09:26:17.017875 ANA top config
624 09:26:17.017927 ===================================
625 09:26:17.017979 DLL_ASYNC_EN = 0
626 09:26:17.018047 ALL_SLAVE_EN = 1
627 09:26:17.018114 NEW_RANK_MODE = 1
628 09:26:17.018167 DLL_IDLE_MODE = 1
629 09:26:17.018218 LP45_APHY_COMB_EN = 1
630 09:26:17.018271 TX_ODT_DIS = 1
631 09:26:17.018322 NEW_8X_MODE = 1
632 09:26:17.018375 ===================================
633 09:26:17.018458 ===================================
634 09:26:17.018511 data_rate = 1600
635 09:26:17.018563 CKR = 1
636 09:26:17.018615 DQ_P2S_RATIO = 8
637 09:26:17.018667 ===================================
638 09:26:17.018720 CA_P2S_RATIO = 8
639 09:26:17.018772 DQ_CA_OPEN = 0
640 09:26:17.018855 DQ_SEMI_OPEN = 0
641 09:26:17.018907 CA_SEMI_OPEN = 0
642 09:26:17.018959 CA_FULL_RATE = 0
643 09:26:17.019011 DQ_CKDIV4_EN = 1
644 09:26:17.019063 CA_CKDIV4_EN = 1
645 09:26:17.019115 CA_PREDIV_EN = 0
646 09:26:17.019198 PH8_DLY = 0
647 09:26:17.019250 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 09:26:17.019301 DQ_AAMCK_DIV = 4
649 09:26:17.019353 CA_AAMCK_DIV = 4
650 09:26:17.019405 CA_ADMCK_DIV = 4
651 09:26:17.019457 DQ_TRACK_CA_EN = 0
652 09:26:17.019509 CA_PICK = 800
653 09:26:17.019578 CA_MCKIO = 800
654 09:26:17.019643 MCKIO_SEMI = 0
655 09:26:17.019695 PLL_FREQ = 3068
656 09:26:17.019747 DQ_UI_PI_RATIO = 32
657 09:26:17.019829 CA_UI_PI_RATIO = 0
658 09:26:17.019881 ===================================
659 09:26:17.019934 ===================================
660 09:26:17.019986 memory_type:LPDDR4
661 09:26:17.020038 GP_NUM : 10
662 09:26:17.020090 SRAM_EN : 1
663 09:26:17.020142 MD32_EN : 0
664 09:26:17.020194 ===================================
665 09:26:17.020461 [ANA_INIT] >>>>>>>>>>>>>>
666 09:26:17.020593 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 09:26:17.020725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 09:26:17.020853 ===================================
669 09:26:17.020982 data_rate = 1600,PCW = 0X7600
670 09:26:17.021110 ===================================
671 09:26:17.021238 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 09:26:17.021404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 09:26:17.021536 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 09:26:17.021613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 09:26:17.021670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 09:26:17.021724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 09:26:17.021778 [ANA_INIT] flow start
678 09:26:17.021832 [ANA_INIT] PLL >>>>>>>>
679 09:26:17.021885 [ANA_INIT] PLL <<<<<<<<
680 09:26:17.021938 [ANA_INIT] MIDPI >>>>>>>>
681 09:26:17.021990 [ANA_INIT] MIDPI <<<<<<<<
682 09:26:17.022043 [ANA_INIT] DLL >>>>>>>>
683 09:26:17.022095 [ANA_INIT] flow end
684 09:26:17.022148 ============ LP4 DIFF to SE enter ============
685 09:26:17.022201 ============ LP4 DIFF to SE exit ============
686 09:26:17.022255 [ANA_INIT] <<<<<<<<<<<<<
687 09:26:17.022307 [Flow] Enable top DCM control >>>>>
688 09:26:17.022359 [Flow] Enable top DCM control <<<<<
689 09:26:17.022411 Enable DLL master slave shuffle
690 09:26:17.022464 ==============================================================
691 09:26:17.022516 Gating Mode config
692 09:26:17.022569 ==============================================================
693 09:26:17.022621 Config description:
694 09:26:17.022674 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 09:26:17.022727 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 09:26:17.022780 SELPH_MODE 0: By rank 1: By Phase
697 09:26:17.022833 ==============================================================
698 09:26:17.022886 GAT_TRACK_EN = 1
699 09:26:17.022939 RX_GATING_MODE = 2
700 09:26:17.022991 RX_GATING_TRACK_MODE = 2
701 09:26:17.023043 SELPH_MODE = 1
702 09:26:17.023095 PICG_EARLY_EN = 1
703 09:26:17.023147 VALID_LAT_VALUE = 1
704 09:26:17.023199 ==============================================================
705 09:26:17.023251 Enter into Gating configuration >>>>
706 09:26:17.023304 Exit from Gating configuration <<<<
707 09:26:17.023356 Enter into DVFS_PRE_config >>>>>
708 09:26:17.023408 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 09:26:17.023465 Exit from DVFS_PRE_config <<<<<
710 09:26:17.023518 Enter into PICG configuration >>>>
711 09:26:17.023571 Exit from PICG configuration <<<<
712 09:26:17.023623 [RX_INPUT] configuration >>>>>
713 09:26:17.023676 [RX_INPUT] configuration <<<<<
714 09:26:17.023728 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 09:26:17.023781 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 09:26:17.023834 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 09:26:17.023886 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 09:26:17.023939 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 09:26:17.023992 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 09:26:17.024044 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 09:26:17.024096 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 09:26:17.024149 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 09:26:17.024201 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 09:26:17.024253 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 09:26:17.024305 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 09:26:17.024358 ===================================
727 09:26:17.024410 LPDDR4 DRAM CONFIGURATION
728 09:26:17.024462 ===================================
729 09:26:17.024514 EX_ROW_EN[0] = 0x0
730 09:26:17.024566 EX_ROW_EN[1] = 0x0
731 09:26:17.024619 LP4Y_EN = 0x0
732 09:26:17.024671 WORK_FSP = 0x0
733 09:26:17.024723 WL = 0x2
734 09:26:17.024775 RL = 0x2
735 09:26:17.024826 BL = 0x2
736 09:26:17.024878 RPST = 0x0
737 09:26:17.024930 RD_PRE = 0x0
738 09:26:17.024981 WR_PRE = 0x1
739 09:26:17.025033 WR_PST = 0x0
740 09:26:17.025084 DBI_WR = 0x0
741 09:26:17.025137 DBI_RD = 0x0
742 09:26:17.025188 OTF = 0x1
743 09:26:17.025241 ===================================
744 09:26:17.025342 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 09:26:17.025396 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 09:26:17.025449 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 09:26:17.025501 ===================================
748 09:26:17.025554 LPDDR4 DRAM CONFIGURATION
749 09:26:17.025606 ===================================
750 09:26:17.025659 EX_ROW_EN[0] = 0x10
751 09:26:17.025711 EX_ROW_EN[1] = 0x0
752 09:26:17.025762 LP4Y_EN = 0x0
753 09:26:17.025815 WORK_FSP = 0x0
754 09:26:17.025866 WL = 0x2
755 09:26:17.025919 RL = 0x2
756 09:26:17.025971 BL = 0x2
757 09:26:17.026023 RPST = 0x0
758 09:26:17.026075 RD_PRE = 0x0
759 09:26:17.026127 WR_PRE = 0x1
760 09:26:17.026179 WR_PST = 0x0
761 09:26:17.026230 DBI_WR = 0x0
762 09:26:17.026282 DBI_RD = 0x0
763 09:26:17.026334 OTF = 0x1
764 09:26:17.026386 ===================================
765 09:26:17.026439 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 09:26:17.026492 nWR fixed to 40
767 09:26:17.026545 [ModeRegInit_LP4] CH0 RK0
768 09:26:17.026596 [ModeRegInit_LP4] CH0 RK1
769 09:26:17.026648 [ModeRegInit_LP4] CH1 RK0
770 09:26:17.026700 [ModeRegInit_LP4] CH1 RK1
771 09:26:17.026751 match AC timing 13
772 09:26:17.026803 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 09:26:17.027050 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 09:26:17.027181 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 09:26:17.027312 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 09:26:17.027441 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 09:26:17.027569 [EMI DOE] emi_dcm 0
778 09:26:17.027633 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 09:26:17.027688 ==
780 09:26:17.027741 Dram Type= 6, Freq= 0, CH_0, rank 0
781 09:26:17.027795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 09:26:17.027849 ==
783 09:26:17.027901 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 09:26:17.027954 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 09:26:17.028007 [CA 0] Center 38 (7~69) winsize 63
786 09:26:17.028059 [CA 1] Center 37 (6~68) winsize 63
787 09:26:17.028112 [CA 2] Center 34 (4~65) winsize 62
788 09:26:17.028164 [CA 3] Center 34 (4~65) winsize 62
789 09:26:17.028216 [CA 4] Center 33 (3~64) winsize 62
790 09:26:17.028269 [CA 5] Center 33 (3~64) winsize 62
791 09:26:17.028321
792 09:26:17.028373 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 09:26:17.028425
794 09:26:17.028477 [CATrainingPosCal] consider 1 rank data
795 09:26:17.028529 u2DelayCellTimex100 = 270/100 ps
796 09:26:17.028582 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
797 09:26:17.028634 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
798 09:26:17.028687 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 09:26:17.028775 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
800 09:26:17.028828 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
801 09:26:17.028880 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 09:26:17.028959
803 09:26:17.029011 CA PerBit enable=1, Macro0, CA PI delay=33
804 09:26:17.029063
805 09:26:17.029115 [CBTSetCACLKResult] CA Dly = 33
806 09:26:17.029167 CS Dly: 5 (0~36)
807 09:26:17.029219 ==
808 09:26:17.029293 Dram Type= 6, Freq= 0, CH_0, rank 1
809 09:26:17.029376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 09:26:17.029443 ==
811 09:26:17.029495 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 09:26:17.029548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 09:26:17.029600 [CA 0] Center 38 (7~69) winsize 63
814 09:26:17.029652 [CA 1] Center 37 (7~68) winsize 62
815 09:26:17.029704 [CA 2] Center 35 (4~66) winsize 63
816 09:26:17.029787 [CA 3] Center 35 (4~66) winsize 63
817 09:26:17.029839 [CA 4] Center 34 (3~65) winsize 63
818 09:26:17.029891 [CA 5] Center 33 (3~64) winsize 62
819 09:26:17.029943
820 09:26:17.029995 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 09:26:17.030047
822 09:26:17.030099 [CATrainingPosCal] consider 2 rank data
823 09:26:17.030181 u2DelayCellTimex100 = 270/100 ps
824 09:26:17.030234 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
825 09:26:17.030286 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 09:26:17.030338 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
827 09:26:17.030390 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 09:26:17.030442 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 09:26:17.030510 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 09:26:17.030575
831 09:26:17.030627 CA PerBit enable=1, Macro0, CA PI delay=33
832 09:26:17.030679
833 09:26:17.030760 [CBTSetCACLKResult] CA Dly = 33
834 09:26:17.030812 CS Dly: 6 (0~38)
835 09:26:17.030864
836 09:26:17.030938 ----->DramcWriteLeveling(PI) begin...
837 09:26:17.031008 ==
838 09:26:17.031061 Dram Type= 6, Freq= 0, CH_0, rank 0
839 09:26:17.031129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 09:26:17.031197 ==
841 09:26:17.031249 Write leveling (Byte 0): 30 => 30
842 09:26:17.031302 Write leveling (Byte 1): 26 => 26
843 09:26:17.031354 DramcWriteLeveling(PI) end<-----
844 09:26:17.031407
845 09:26:17.031459 ==
846 09:26:17.031541 Dram Type= 6, Freq= 0, CH_0, rank 0
847 09:26:17.031593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 09:26:17.031646 ==
849 09:26:17.031698 [Gating] SW mode calibration
850 09:26:17.031750 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 09:26:17.031803 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 09:26:17.031855 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 09:26:17.031935 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
854 09:26:17.031988 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 09:26:17.032040 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 09:26:17.032093 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 09:26:17.032145 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 09:26:17.032228 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 09:26:17.032280 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 09:26:17.032333 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 09:26:17.032385 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 09:26:17.032437 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 09:26:17.032489 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 09:26:17.032541 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 09:26:17.032622 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 09:26:17.032674 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 09:26:17.032726 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 09:26:17.032778 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 09:26:17.032831 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 09:26:17.032883 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
871 09:26:17.032934 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 09:26:17.033032 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 09:26:17.033115 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 09:26:17.033169 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 09:26:17.033222 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 09:26:17.033301 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 09:26:17.033368 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 09:26:17.033434 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
879 09:26:17.033486 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
880 09:26:17.033538 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 09:26:17.033806 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 09:26:17.033940 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 09:26:17.034096 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 09:26:17.034223 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
885 09:26:17.034351 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
886 09:26:17.034424 0 10 8 | B1->B0 | 3232 2323 | 1 0 | (1 0) (1 0)
887 09:26:17.034479 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 09:26:17.034533 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 09:26:17.034585 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 09:26:17.034638 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 09:26:17.034690 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 09:26:17.034743 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 09:26:17.034796 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
894 09:26:17.034849 0 11 8 | B1->B0 | 2929 4343 | 1 0 | (0 0) (1 1)
895 09:26:17.034902 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
896 09:26:17.034955 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 09:26:17.035008 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 09:26:17.035060 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 09:26:17.035112 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 09:26:17.035163 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 09:26:17.035215 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 09:26:17.035268 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
903 09:26:17.035320 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 09:26:17.035372 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 09:26:17.035424 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 09:26:17.035476 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 09:26:17.035528 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 09:26:17.035617 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 09:26:17.035669 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 09:26:17.035722 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 09:26:17.035812 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 09:26:17.035867 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 09:26:17.035920 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 09:26:17.035972 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 09:26:17.036024 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 09:26:17.036077 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 09:26:17.036129 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 09:26:17.036181 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
919 09:26:17.036267 Total UI for P1: 0, mck2ui 16
920 09:26:17.036320 best dqsien dly found for B0: ( 0, 14, 4)
921 09:26:17.036372 Total UI for P1: 0, mck2ui 16
922 09:26:17.036425 best dqsien dly found for B1: ( 0, 14, 6)
923 09:26:17.036477 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
924 09:26:17.036528 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
925 09:26:17.036580
926 09:26:17.036667 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
927 09:26:17.036720 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
928 09:26:17.036772 [Gating] SW calibration Done
929 09:26:17.036840 ==
930 09:26:17.036908 Dram Type= 6, Freq= 0, CH_0, rank 0
931 09:26:17.036960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
932 09:26:17.037041 ==
933 09:26:17.037107 RX Vref Scan: 0
934 09:26:17.037160
935 09:26:17.037213 RX Vref 0 -> 0, step: 1
936 09:26:17.037272
937 09:26:17.037338 RX Delay -130 -> 252, step: 16
938 09:26:17.037418 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
939 09:26:17.037485 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
940 09:26:17.037538 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
941 09:26:17.037590 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
942 09:26:17.037671 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
943 09:26:17.037723 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
944 09:26:17.037775 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
945 09:26:17.037827 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
946 09:26:17.037880 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
947 09:26:17.037932 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
948 09:26:17.037984 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
949 09:26:17.038036 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
950 09:26:17.038088 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
951 09:26:17.038140 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
952 09:26:17.038201 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
953 09:26:17.038255 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
954 09:26:17.038307 ==
955 09:26:17.038365 Dram Type= 6, Freq= 0, CH_0, rank 0
956 09:26:17.038457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 09:26:17.038510 ==
958 09:26:17.038573 DQS Delay:
959 09:26:17.038625 DQS0 = 0, DQS1 = 0
960 09:26:17.038678 DQM Delay:
961 09:26:17.038734 DQM0 = 88, DQM1 = 74
962 09:26:17.038817 DQ Delay:
963 09:26:17.038869 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
964 09:26:17.038921 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
965 09:26:17.038974 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
966 09:26:17.039026 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
967 09:26:17.039078
968 09:26:17.039130
969 09:26:17.039211 ==
970 09:26:17.039263 Dram Type= 6, Freq= 0, CH_0, rank 0
971 09:26:17.039314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
972 09:26:17.039366 ==
973 09:26:17.039418
974 09:26:17.039469
975 09:26:17.039534 TX Vref Scan disable
976 09:26:17.039600 == TX Byte 0 ==
977 09:26:17.039652 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
978 09:26:17.039705 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
979 09:26:17.039757 == TX Byte 1 ==
980 09:26:17.039809 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
981 09:26:17.039861 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
982 09:26:17.039927 ==
983 09:26:17.039992 Dram Type= 6, Freq= 0, CH_0, rank 0
984 09:26:17.040044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
985 09:26:17.040097 ==
986 09:26:17.040149 TX Vref=22, minBit 1, minWin=26, winSum=435
987 09:26:17.040201 TX Vref=24, minBit 1, minWin=26, winSum=439
988 09:26:17.040253 TX Vref=26, minBit 0, minWin=27, winSum=446
989 09:26:17.040549 TX Vref=28, minBit 2, minWin=27, winSum=449
990 09:26:17.040714 TX Vref=30, minBit 1, minWin=28, winSum=451
991 09:26:17.040843 TX Vref=32, minBit 1, minWin=27, winSum=447
992 09:26:17.040986 [TxChooseVref] Worse bit 1, Min win 28, Win sum 451, Final Vref 30
993 09:26:17.041146
994 09:26:17.041263 Final TX Range 1 Vref 30
995 09:26:17.041340
996 09:26:17.041395 ==
997 09:26:17.041464 Dram Type= 6, Freq= 0, CH_0, rank 0
998 09:26:17.041520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
999 09:26:17.041606 ==
1000 09:26:17.041661
1001 09:26:17.041713
1002 09:26:17.041766 TX Vref Scan disable
1003 09:26:17.041825 == TX Byte 0 ==
1004 09:26:17.041879 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1005 09:26:17.041932 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1006 09:26:17.041990 == TX Byte 1 ==
1007 09:26:17.042044 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1008 09:26:17.042125 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1009 09:26:17.042195
1010 09:26:17.042277 [DATLAT]
1011 09:26:17.042361 Freq=800, CH0 RK0
1012 09:26:17.042445
1013 09:26:17.042561 DATLAT Default: 0xa
1014 09:26:17.042644 0, 0xFFFF, sum = 0
1015 09:26:17.042730 1, 0xFFFF, sum = 0
1016 09:26:17.042787 2, 0xFFFF, sum = 0
1017 09:26:17.042856 3, 0xFFFF, sum = 0
1018 09:26:17.042951 4, 0xFFFF, sum = 0
1019 09:26:17.043020 5, 0xFFFF, sum = 0
1020 09:26:17.043088 6, 0xFFFF, sum = 0
1021 09:26:17.043141 7, 0xFFFF, sum = 0
1022 09:26:17.043194 8, 0xFFFF, sum = 0
1023 09:26:17.043247 9, 0x0, sum = 1
1024 09:26:17.043304 10, 0x0, sum = 2
1025 09:26:17.043361 11, 0x0, sum = 3
1026 09:26:17.043416 12, 0x0, sum = 4
1027 09:26:17.043483 best_step = 10
1028 09:26:17.043549
1029 09:26:17.043601 ==
1030 09:26:17.043653 Dram Type= 6, Freq= 0, CH_0, rank 0
1031 09:26:17.043705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1032 09:26:17.043757 ==
1033 09:26:17.043808 RX Vref Scan: 1
1034 09:26:17.043874
1035 09:26:17.043938 Set Vref Range= 32 -> 127
1036 09:26:17.043990
1037 09:26:17.044040 RX Vref 32 -> 127, step: 1
1038 09:26:17.044092
1039 09:26:17.044143 RX Delay -111 -> 252, step: 8
1040 09:26:17.044194
1041 09:26:17.044260 Set Vref, RX VrefLevel [Byte0]: 32
1042 09:26:17.044325 [Byte1]: 32
1043 09:26:17.044377
1044 09:26:17.044428 Set Vref, RX VrefLevel [Byte0]: 33
1045 09:26:17.044508 [Byte1]: 33
1046 09:26:17.044559
1047 09:26:17.044610 Set Vref, RX VrefLevel [Byte0]: 34
1048 09:26:17.044662 [Byte1]: 34
1049 09:26:17.044713
1050 09:26:17.044792 Set Vref, RX VrefLevel [Byte0]: 35
1051 09:26:17.044849 [Byte1]: 35
1052 09:26:17.044916
1053 09:26:17.044981 Set Vref, RX VrefLevel [Byte0]: 36
1054 09:26:17.045036 [Byte1]: 36
1055 09:26:17.045089
1056 09:26:17.045140 Set Vref, RX VrefLevel [Byte0]: 37
1057 09:26:17.045192 [Byte1]: 37
1058 09:26:17.045243
1059 09:26:17.045331 Set Vref, RX VrefLevel [Byte0]: 38
1060 09:26:17.045383 [Byte1]: 38
1061 09:26:17.045435
1062 09:26:17.045486 Set Vref, RX VrefLevel [Byte0]: 39
1063 09:26:17.045537 [Byte1]: 39
1064 09:26:17.045588
1065 09:26:17.045639 Set Vref, RX VrefLevel [Byte0]: 40
1066 09:26:17.045690 [Byte1]: 40
1067 09:26:17.045741
1068 09:26:17.045792 Set Vref, RX VrefLevel [Byte0]: 41
1069 09:26:17.045843 [Byte1]: 41
1070 09:26:17.045894
1071 09:26:17.045983 Set Vref, RX VrefLevel [Byte0]: 42
1072 09:26:17.046036 [Byte1]: 42
1073 09:26:17.046088
1074 09:26:17.046139 Set Vref, RX VrefLevel [Byte0]: 43
1075 09:26:17.046191 [Byte1]: 43
1076 09:26:17.046243
1077 09:26:17.046294 Set Vref, RX VrefLevel [Byte0]: 44
1078 09:26:17.046345 [Byte1]: 44
1079 09:26:17.046397
1080 09:26:17.046448 Set Vref, RX VrefLevel [Byte0]: 45
1081 09:26:17.046513 [Byte1]: 45
1082 09:26:17.046578
1083 09:26:17.046629 Set Vref, RX VrefLevel [Byte0]: 46
1084 09:26:17.046696 [Byte1]: 46
1085 09:26:17.046762
1086 09:26:17.046813 Set Vref, RX VrefLevel [Byte0]: 47
1087 09:26:17.046864 [Byte1]: 47
1088 09:26:17.046915
1089 09:26:17.046966 Set Vref, RX VrefLevel [Byte0]: 48
1090 09:26:17.047020 [Byte1]: 48
1091 09:26:17.047072
1092 09:26:17.047160 Set Vref, RX VrefLevel [Byte0]: 49
1093 09:26:17.047211 [Byte1]: 49
1094 09:26:17.047262
1095 09:26:17.047314 Set Vref, RX VrefLevel [Byte0]: 50
1096 09:26:17.047365 [Byte1]: 50
1097 09:26:17.047416
1098 09:26:17.047468 Set Vref, RX VrefLevel [Byte0]: 51
1099 09:26:17.047547 [Byte1]: 51
1100 09:26:17.047598
1101 09:26:17.047649 Set Vref, RX VrefLevel [Byte0]: 52
1102 09:26:17.047701 [Byte1]: 52
1103 09:26:17.047752
1104 09:26:17.047803 Set Vref, RX VrefLevel [Byte0]: 53
1105 09:26:17.047854 [Byte1]: 53
1106 09:26:17.047927
1107 09:26:17.047993 Set Vref, RX VrefLevel [Byte0]: 54
1108 09:26:17.048045 [Byte1]: 54
1109 09:26:17.048096
1110 09:26:17.048147 Set Vref, RX VrefLevel [Byte0]: 55
1111 09:26:17.048198 [Byte1]: 55
1112 09:26:17.048249
1113 09:26:17.048327 Set Vref, RX VrefLevel [Byte0]: 56
1114 09:26:17.048378 [Byte1]: 56
1115 09:26:17.048429
1116 09:26:17.048480 Set Vref, RX VrefLevel [Byte0]: 57
1117 09:26:17.048531 [Byte1]: 57
1118 09:26:17.048582
1119 09:26:17.048632 Set Vref, RX VrefLevel [Byte0]: 58
1120 09:26:17.048684 [Byte1]: 58
1121 09:26:17.048749
1122 09:26:17.048813 Set Vref, RX VrefLevel [Byte0]: 59
1123 09:26:17.048864 [Byte1]: 59
1124 09:26:17.048915
1125 09:26:17.048981 Set Vref, RX VrefLevel [Byte0]: 60
1126 09:26:17.049033 [Byte1]: 60
1127 09:26:17.049121
1128 09:26:17.049205 Set Vref, RX VrefLevel [Byte0]: 61
1129 09:26:17.049313 [Byte1]: 61
1130 09:26:17.049369
1131 09:26:17.049421 Set Vref, RX VrefLevel [Byte0]: 62
1132 09:26:17.049473 [Byte1]: 62
1133 09:26:17.049554
1134 09:26:17.049606 Set Vref, RX VrefLevel [Byte0]: 63
1135 09:26:17.049657 [Byte1]: 63
1136 09:26:17.049709
1137 09:26:17.049760 Set Vref, RX VrefLevel [Byte0]: 64
1138 09:26:17.049811 [Byte1]: 64
1139 09:26:17.049862
1140 09:26:17.049942 Set Vref, RX VrefLevel [Byte0]: 65
1141 09:26:17.049994 [Byte1]: 65
1142 09:26:17.050044
1143 09:26:17.050095 Set Vref, RX VrefLevel [Byte0]: 66
1144 09:26:17.050147 [Byte1]: 66
1145 09:26:17.050203
1146 09:26:17.050256 Set Vref, RX VrefLevel [Byte0]: 67
1147 09:26:17.050315 [Byte1]: 67
1148 09:26:17.050383
1149 09:26:17.050449 Set Vref, RX VrefLevel [Byte0]: 68
1150 09:26:17.050507 [Byte1]: 68
1151 09:26:17.050560
1152 09:26:17.050611 Set Vref, RX VrefLevel [Byte0]: 69
1153 09:26:17.050662 [Byte1]: 69
1154 09:26:17.050714
1155 09:26:17.050765 Set Vref, RX VrefLevel [Byte0]: 70
1156 09:26:17.050816 [Byte1]: 70
1157 09:26:17.050867
1158 09:26:17.051127 Set Vref, RX VrefLevel [Byte0]: 71
1159 09:26:17.051270 [Byte1]: 71
1160 09:26:17.051409
1161 09:26:17.051549 Set Vref, RX VrefLevel [Byte0]: 72
1162 09:26:17.051673 [Byte1]: 72
1163 09:26:17.051821
1164 09:26:17.051882 Set Vref, RX VrefLevel [Byte0]: 73
1165 09:26:17.051938 [Byte1]: 73
1166 09:26:17.051991
1167 09:26:17.052043 Set Vref, RX VrefLevel [Byte0]: 74
1168 09:26:17.052100 [Byte1]: 74
1169 09:26:17.052167
1170 09:26:17.052232 Set Vref, RX VrefLevel [Byte0]: 75
1171 09:26:17.052283 [Byte1]: 75
1172 09:26:17.052335
1173 09:26:17.052386 Final RX Vref Byte 0 = 57 to rank0
1174 09:26:17.052438 Final RX Vref Byte 1 = 60 to rank0
1175 09:26:17.052489 Final RX Vref Byte 0 = 57 to rank1
1176 09:26:17.052558 Final RX Vref Byte 1 = 60 to rank1==
1177 09:26:17.052624 Dram Type= 6, Freq= 0, CH_0, rank 0
1178 09:26:17.052676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1179 09:26:17.052728 ==
1180 09:26:17.052779 DQS Delay:
1181 09:26:17.052831 DQS0 = 0, DQS1 = 0
1182 09:26:17.052882 DQM Delay:
1183 09:26:17.052933 DQM0 = 88, DQM1 = 77
1184 09:26:17.052988 DQ Delay:
1185 09:26:17.053041 DQ0 =88, DQ1 =88, DQ2 =88, DQ3 =84
1186 09:26:17.053093 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1187 09:26:17.053144 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1188 09:26:17.053208 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1189 09:26:17.053268
1190 09:26:17.053334
1191 09:26:17.053399 [DQSOSCAuto] RK0, (LSB)MR18= 0x352e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
1192 09:26:17.053465 CH0 RK0: MR19=606, MR18=352E
1193 09:26:17.053517 CH0_RK0: MR19=0x606, MR18=0x352E, DQSOSC=396, MR23=63, INC=94, DEC=62
1194 09:26:17.053584
1195 09:26:17.053649 ----->DramcWriteLeveling(PI) begin...
1196 09:26:17.053701 ==
1197 09:26:17.053753 Dram Type= 6, Freq= 0, CH_0, rank 1
1198 09:26:17.053804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1199 09:26:17.053856 ==
1200 09:26:17.053908 Write leveling (Byte 0): 30 => 30
1201 09:26:17.053976 Write leveling (Byte 1): 29 => 29
1202 09:26:17.054040 DramcWriteLeveling(PI) end<-----
1203 09:26:17.054092
1204 09:26:17.054143 ==
1205 09:26:17.054194 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 09:26:17.054246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 09:26:17.054297 ==
1208 09:26:17.054348 [Gating] SW mode calibration
1209 09:26:17.054415 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1210 09:26:17.054484 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1211 09:26:17.054536 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1212 09:26:17.054587 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1213 09:26:17.054640 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 09:26:17.054691 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 09:26:17.054751 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 09:26:17.054817 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 09:26:17.054882 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 09:26:17.054941 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 09:26:17.054994 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 09:26:17.055045 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 09:26:17.055097 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 09:26:17.055155 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 09:26:17.055250 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 09:26:17.055320 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 09:26:17.055400 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 09:26:17.055451 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 09:26:17.055503 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 09:26:17.055554 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1229 09:26:17.055606 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1230 09:26:17.055658 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 09:26:17.055710 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 09:26:17.055760 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 09:26:17.055829 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 09:26:17.055901 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 09:26:17.055953 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 09:26:17.056004 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 09:26:17.056056 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
1238 09:26:17.056107 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1239 09:26:17.056159 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 09:26:17.056239 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 09:26:17.056291 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 09:26:17.056343 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 09:26:17.056422 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 09:26:17.056473 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
1245 09:26:17.056525 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
1246 09:26:17.056576 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 09:26:17.056657 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 09:26:17.056708 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 09:26:17.056759 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 09:26:17.056811 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 09:26:17.056863 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 09:26:17.056913 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1253 09:26:17.056965 0 11 8 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
1254 09:26:17.057016 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1255 09:26:17.057095 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 09:26:17.057146 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 09:26:17.057198 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 09:26:17.057250 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 09:26:17.057338 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 09:26:17.057390 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1261 09:26:17.057636 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 09:26:17.057695 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 09:26:17.057748 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 09:26:17.057800 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 09:26:17.057852 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 09:26:17.057904 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 09:26:17.057955 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 09:26:17.058021 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 09:26:17.058087 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 09:26:17.058138 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 09:26:17.058191 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 09:26:17.058243 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 09:26:17.058322 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 09:26:17.058374 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 09:26:17.058449 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1276 09:26:17.058502 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1277 09:26:17.058596 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1278 09:26:17.058685 Total UI for P1: 0, mck2ui 16
1279 09:26:17.058737 best dqsien dly found for B0: ( 0, 14, 2)
1280 09:26:17.058789 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 09:26:17.058841 Total UI for P1: 0, mck2ui 16
1282 09:26:17.058893 best dqsien dly found for B1: ( 0, 14, 8)
1283 09:26:17.058944 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1284 09:26:17.058996 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1285 09:26:17.059076
1286 09:26:17.059128 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1287 09:26:17.059179 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1288 09:26:17.059230 [Gating] SW calibration Done
1289 09:26:17.059282 ==
1290 09:26:17.059333 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 09:26:17.059399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 09:26:17.059465 ==
1293 09:26:17.059516 RX Vref Scan: 0
1294 09:26:17.059568
1295 09:26:17.059618 RX Vref 0 -> 0, step: 1
1296 09:26:17.059670
1297 09:26:17.059721 RX Delay -130 -> 252, step: 16
1298 09:26:17.059773 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1299 09:26:17.059824 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1300 09:26:17.059905 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1301 09:26:17.059957 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1302 09:26:17.060009 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1303 09:26:17.060060 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1304 09:26:17.060112 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1305 09:26:17.060163 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1306 09:26:17.060214 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1307 09:26:17.060294 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1308 09:26:17.060346 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1309 09:26:17.060397 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1310 09:26:17.060463 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1311 09:26:17.060527 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1312 09:26:17.060579 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1313 09:26:17.060630 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1314 09:26:17.060681 ==
1315 09:26:17.060733 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 09:26:17.060784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 09:26:17.060836 ==
1318 09:26:17.060887 DQS Delay:
1319 09:26:17.060939 DQS0 = 0, DQS1 = 0
1320 09:26:17.060990 DQM Delay:
1321 09:26:17.061042 DQM0 = 90, DQM1 = 76
1322 09:26:17.061092 DQ Delay:
1323 09:26:17.061144 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
1324 09:26:17.061195 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1325 09:26:17.061247 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1326 09:26:17.061338 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1327 09:26:17.061390
1328 09:26:17.061441
1329 09:26:17.061492 ==
1330 09:26:17.061544 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 09:26:17.061595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 09:26:17.061647 ==
1333 09:26:17.061699
1334 09:26:17.061749
1335 09:26:17.061800 TX Vref Scan disable
1336 09:26:17.061852 == TX Byte 0 ==
1337 09:26:17.061903 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1338 09:26:17.061955 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1339 09:26:17.062006 == TX Byte 1 ==
1340 09:26:17.062058 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1341 09:26:17.062109 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1342 09:26:17.062161 ==
1343 09:26:17.062212 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 09:26:17.062264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 09:26:17.062316 ==
1346 09:26:17.062368 TX Vref=22, minBit 5, minWin=26, winSum=439
1347 09:26:17.062420 TX Vref=24, minBit 0, minWin=27, winSum=443
1348 09:26:17.062471 TX Vref=26, minBit 1, minWin=27, winSum=443
1349 09:26:17.062523 TX Vref=28, minBit 1, minWin=27, winSum=447
1350 09:26:17.062575 TX Vref=30, minBit 0, minWin=28, winSum=449
1351 09:26:17.062626 TX Vref=32, minBit 2, minWin=27, winSum=448
1352 09:26:17.062678 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 30
1353 09:26:17.062730
1354 09:26:17.062781 Final TX Range 1 Vref 30
1355 09:26:17.062833
1356 09:26:17.062884 ==
1357 09:26:17.062935 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 09:26:17.062986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 09:26:17.063038 ==
1360 09:26:17.063089
1361 09:26:17.063140
1362 09:26:17.063190 TX Vref Scan disable
1363 09:26:17.063241 == TX Byte 0 ==
1364 09:26:17.063292 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1365 09:26:17.063343 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1366 09:26:17.063394 == TX Byte 1 ==
1367 09:26:17.063445 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1368 09:26:17.063495 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1369 09:26:17.063546
1370 09:26:17.063596 [DATLAT]
1371 09:26:17.063647 Freq=800, CH0 RK1
1372 09:26:17.063698
1373 09:26:17.063748 DATLAT Default: 0xa
1374 09:26:17.063799 0, 0xFFFF, sum = 0
1375 09:26:17.063851 1, 0xFFFF, sum = 0
1376 09:26:17.063902 2, 0xFFFF, sum = 0
1377 09:26:17.063954 3, 0xFFFF, sum = 0
1378 09:26:17.064006 4, 0xFFFF, sum = 0
1379 09:26:17.064057 5, 0xFFFF, sum = 0
1380 09:26:17.064108 6, 0xFFFF, sum = 0
1381 09:26:17.064160 7, 0xFFFF, sum = 0
1382 09:26:17.064212 8, 0xFFFF, sum = 0
1383 09:26:17.064264 9, 0x0, sum = 1
1384 09:26:17.064316 10, 0x0, sum = 2
1385 09:26:17.064367 11, 0x0, sum = 3
1386 09:26:17.064419 12, 0x0, sum = 4
1387 09:26:17.064471 best_step = 10
1388 09:26:17.064521
1389 09:26:17.064571 ==
1390 09:26:17.064622 Dram Type= 6, Freq= 0, CH_0, rank 1
1391 09:26:17.064673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1392 09:26:17.064724 ==
1393 09:26:17.064775 RX Vref Scan: 0
1394 09:26:17.064825
1395 09:26:17.065073 RX Vref 0 -> 0, step: 1
1396 09:26:17.065206
1397 09:26:17.065372 RX Delay -95 -> 252, step: 8
1398 09:26:17.065499 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1399 09:26:17.065625 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1400 09:26:17.065753 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1401 09:26:17.065878 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1402 09:26:17.066004 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1403 09:26:17.066129 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1404 09:26:17.066205 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1405 09:26:17.066259 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1406 09:26:17.066312 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1407 09:26:17.066364 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1408 09:26:17.066415 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1409 09:26:17.066466 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1410 09:26:17.066518 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1411 09:26:17.066569 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1412 09:26:17.066620 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1413 09:26:17.066672 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1414 09:26:17.066723 ==
1415 09:26:17.066775 Dram Type= 6, Freq= 0, CH_0, rank 1
1416 09:26:17.066826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 09:26:17.066877 ==
1418 09:26:17.066928 DQS Delay:
1419 09:26:17.066979 DQS0 = 0, DQS1 = 0
1420 09:26:17.067030 DQM Delay:
1421 09:26:17.067080 DQM0 = 87, DQM1 = 76
1422 09:26:17.067131 DQ Delay:
1423 09:26:17.067200 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1424 09:26:17.067255 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1425 09:26:17.067306 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1426 09:26:17.067358 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1427 09:26:17.067408
1428 09:26:17.067459
1429 09:26:17.067510 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1430 09:26:17.067562 CH0 RK1: MR19=606, MR18=2F2D
1431 09:26:17.067613 CH0_RK1: MR19=0x606, MR18=0x2F2D, DQSOSC=397, MR23=63, INC=93, DEC=62
1432 09:26:17.067665 [RxdqsGatingPostProcess] freq 800
1433 09:26:17.067716 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1434 09:26:17.067768 Pre-setting of DQS Precalculation
1435 09:26:17.067819 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1436 09:26:17.067870 ==
1437 09:26:17.067921 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 09:26:17.067972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 09:26:17.068024 ==
1440 09:26:17.068075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1441 09:26:17.068127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1442 09:26:17.068179 [CA 0] Center 36 (6~67) winsize 62
1443 09:26:17.068234 [CA 1] Center 37 (6~68) winsize 63
1444 09:26:17.068286 [CA 2] Center 35 (5~65) winsize 61
1445 09:26:17.068338 [CA 3] Center 34 (4~65) winsize 62
1446 09:26:17.068389 [CA 4] Center 34 (4~65) winsize 62
1447 09:26:17.068447 [CA 5] Center 33 (3~64) winsize 62
1448 09:26:17.068499
1449 09:26:17.068550 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1450 09:26:17.068608
1451 09:26:17.068667 [CATrainingPosCal] consider 1 rank data
1452 09:26:17.068719 u2DelayCellTimex100 = 270/100 ps
1453 09:26:17.068770 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1454 09:26:17.068821 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1455 09:26:17.068877 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1456 09:26:17.068929 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1457 09:26:17.068980 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1458 09:26:17.069033 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1459 09:26:17.069084
1460 09:26:17.069136 CA PerBit enable=1, Macro0, CA PI delay=33
1461 09:26:17.069186
1462 09:26:17.069237 [CBTSetCACLKResult] CA Dly = 33
1463 09:26:17.069327 CS Dly: 5 (0~36)
1464 09:26:17.069379 ==
1465 09:26:17.069430 Dram Type= 6, Freq= 0, CH_1, rank 1
1466 09:26:17.069482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1467 09:26:17.069533 ==
1468 09:26:17.069614 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1469 09:26:17.069665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1470 09:26:17.069716 [CA 0] Center 36 (6~67) winsize 62
1471 09:26:17.069767 [CA 1] Center 37 (7~68) winsize 62
1472 09:26:17.069818 [CA 2] Center 34 (4~65) winsize 62
1473 09:26:17.069870 [CA 3] Center 34 (3~65) winsize 63
1474 09:26:17.069920 [CA 4] Center 34 (3~65) winsize 63
1475 09:26:17.069971 [CA 5] Center 33 (3~64) winsize 62
1476 09:26:17.070022
1477 09:26:17.070072 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1478 09:26:17.070123
1479 09:26:17.070174 [CATrainingPosCal] consider 2 rank data
1480 09:26:17.070224 u2DelayCellTimex100 = 270/100 ps
1481 09:26:17.070277 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1482 09:26:17.070328 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
1483 09:26:17.070380 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1484 09:26:17.070431 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1485 09:26:17.070482 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1486 09:26:17.070533 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1487 09:26:17.070584
1488 09:26:17.070634 CA PerBit enable=1, Macro0, CA PI delay=33
1489 09:26:17.070685
1490 09:26:17.070736 [CBTSetCACLKResult] CA Dly = 33
1491 09:26:17.070787 CS Dly: 5 (0~37)
1492 09:26:17.070838
1493 09:26:17.070889 ----->DramcWriteLeveling(PI) begin...
1494 09:26:17.070941 ==
1495 09:26:17.070992 Dram Type= 6, Freq= 0, CH_1, rank 0
1496 09:26:17.071043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1497 09:26:17.071094 ==
1498 09:26:17.071145 Write leveling (Byte 0): 23 => 23
1499 09:26:17.071197 Write leveling (Byte 1): 28 => 28
1500 09:26:17.071248 DramcWriteLeveling(PI) end<-----
1501 09:26:17.071299
1502 09:26:17.071349 ==
1503 09:26:17.071400 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 09:26:17.071451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 09:26:17.071502 ==
1506 09:26:17.071553 [Gating] SW mode calibration
1507 09:26:17.071604 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1508 09:26:17.071656 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1509 09:26:17.071706 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1510 09:26:17.071758 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1511 09:26:17.071809 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 09:26:17.071860 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 09:26:17.071910 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 09:26:17.072161 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 09:26:17.072292 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 09:26:17.072416 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 09:26:17.072541 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 09:26:17.072666 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 09:26:17.072739 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 09:26:17.072792 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 09:26:17.072844 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 09:26:17.072896 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 09:26:17.072973 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 09:26:17.073054 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 09:26:17.073138 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 09:26:17.073221 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1527 09:26:17.073331 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1528 09:26:17.073386 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 09:26:17.073437 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 09:26:17.073489 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 09:26:17.073545 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 09:26:17.073597 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 09:26:17.073648 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 09:26:17.073699 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1535 09:26:17.073750 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1536 09:26:17.073801 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 09:26:17.073852 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 09:26:17.073903 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 09:26:17.073954 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 09:26:17.074005 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 09:26:17.074056 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 09:26:17.074107 0 10 4 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 0)
1543 09:26:17.074158 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
1544 09:26:17.074210 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 09:26:17.074261 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 09:26:17.074312 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 09:26:17.074363 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 09:26:17.074415 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 09:26:17.074472 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 09:26:17.074523 0 11 4 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 0)
1551 09:26:17.074574 0 11 8 | B1->B0 | 4040 4444 | 0 0 | (0 0) (0 0)
1552 09:26:17.074626 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 09:26:17.074677 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 09:26:17.074728 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 09:26:17.074779 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 09:26:17.074830 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 09:26:17.074881 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 09:26:17.074938 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1559 09:26:17.074990 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1560 09:26:17.075041 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 09:26:17.075092 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 09:26:17.075149 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 09:26:17.075201 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 09:26:17.075252 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 09:26:17.075307 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 09:26:17.075359 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 09:26:17.075410 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 09:26:17.075461 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 09:26:17.075517 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 09:26:17.075569 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 09:26:17.075620 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 09:26:17.075677 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 09:26:17.075758 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 09:26:17.075839 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1575 09:26:17.075920 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 09:26:17.076001 Total UI for P1: 0, mck2ui 16
1577 09:26:17.076064 best dqsien dly found for B0: ( 0, 14, 4)
1578 09:26:17.076118 Total UI for P1: 0, mck2ui 16
1579 09:26:17.076169 best dqsien dly found for B1: ( 0, 14, 4)
1580 09:26:17.076221 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1581 09:26:17.076273 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1582 09:26:17.076323
1583 09:26:17.076374 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1584 09:26:17.076425 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1585 09:26:17.076476 [Gating] SW calibration Done
1586 09:26:17.076527 ==
1587 09:26:17.076579 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 09:26:17.076630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 09:26:17.076682 ==
1590 09:26:17.076733 RX Vref Scan: 0
1591 09:26:17.076784
1592 09:26:17.076834 RX Vref 0 -> 0, step: 1
1593 09:26:17.076885
1594 09:26:17.076941 RX Delay -130 -> 252, step: 16
1595 09:26:17.076996 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1596 09:26:17.077047 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1597 09:26:17.077119 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1598 09:26:17.077202 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1599 09:26:17.077309 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1600 09:26:17.077406 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1601 09:26:17.077491 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1602 09:26:17.077557 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1603 09:26:17.077838 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1604 09:26:17.077970 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1605 09:26:17.078098 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1606 09:26:17.078223 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1607 09:26:17.078349 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1608 09:26:17.078438 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1609 09:26:17.078493 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1610 09:26:17.078545 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1611 09:26:17.078597 ==
1612 09:26:17.078649 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 09:26:17.078701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 09:26:17.078752 ==
1615 09:26:17.078803 DQS Delay:
1616 09:26:17.078879 DQS0 = 0, DQS1 = 0
1617 09:26:17.078959 DQM Delay:
1618 09:26:17.079067 DQM0 = 88, DQM1 = 79
1619 09:26:17.079120 DQ Delay:
1620 09:26:17.079171 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1621 09:26:17.079229 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1622 09:26:17.079281 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1623 09:26:17.079333 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1624 09:26:17.079387
1625 09:26:17.079467
1626 09:26:17.079547 ==
1627 09:26:17.079629 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 09:26:17.079710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 09:26:17.079790 ==
1630 09:26:17.079874
1631 09:26:17.079957
1632 09:26:17.080039 TX Vref Scan disable
1633 09:26:17.080121 == TX Byte 0 ==
1634 09:26:17.080201 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1635 09:26:17.080263 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1636 09:26:17.080316 == TX Byte 1 ==
1637 09:26:17.080367 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1638 09:26:17.080435 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1639 09:26:17.080516 ==
1640 09:26:17.080599 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 09:26:17.080681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 09:26:17.080761 ==
1643 09:26:17.080844 TX Vref=22, minBit 3, minWin=26, winSum=439
1644 09:26:17.080925 TX Vref=24, minBit 4, minWin=27, winSum=449
1645 09:26:17.081010 TX Vref=26, minBit 1, minWin=27, winSum=448
1646 09:26:17.081092 TX Vref=28, minBit 5, minWin=27, winSum=455
1647 09:26:17.081178 TX Vref=30, minBit 6, minWin=27, winSum=454
1648 09:26:17.081294 TX Vref=32, minBit 0, minWin=27, winSum=453
1649 09:26:17.081350 [TxChooseVref] Worse bit 5, Min win 27, Win sum 455, Final Vref 28
1650 09:26:17.081402
1651 09:26:17.081454 Final TX Range 1 Vref 28
1652 09:26:17.081505
1653 09:26:17.081556 ==
1654 09:26:17.081606 Dram Type= 6, Freq= 0, CH_1, rank 0
1655 09:26:17.081657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1656 09:26:17.081709 ==
1657 09:26:17.081759
1658 09:26:17.081810
1659 09:26:17.081860 TX Vref Scan disable
1660 09:26:17.081912 == TX Byte 0 ==
1661 09:26:17.081963 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1662 09:26:17.082014 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1663 09:26:17.082065 == TX Byte 1 ==
1664 09:26:17.082117 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1665 09:26:17.082168 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1666 09:26:17.082220
1667 09:26:17.082271 [DATLAT]
1668 09:26:17.082323 Freq=800, CH1 RK0
1669 09:26:17.082374
1670 09:26:17.082424 DATLAT Default: 0xa
1671 09:26:17.082475 0, 0xFFFF, sum = 0
1672 09:26:17.082527 1, 0xFFFF, sum = 0
1673 09:26:17.082578 2, 0xFFFF, sum = 0
1674 09:26:17.082630 3, 0xFFFF, sum = 0
1675 09:26:17.082682 4, 0xFFFF, sum = 0
1676 09:26:17.082734 5, 0xFFFF, sum = 0
1677 09:26:17.082785 6, 0xFFFF, sum = 0
1678 09:26:17.082837 7, 0xFFFF, sum = 0
1679 09:26:17.082888 8, 0xFFFF, sum = 0
1680 09:26:17.082940 9, 0x0, sum = 1
1681 09:26:17.082991 10, 0x0, sum = 2
1682 09:26:17.083043 11, 0x0, sum = 3
1683 09:26:17.083095 12, 0x0, sum = 4
1684 09:26:17.083146 best_step = 10
1685 09:26:17.083196
1686 09:26:17.083247 ==
1687 09:26:17.083298 Dram Type= 6, Freq= 0, CH_1, rank 0
1688 09:26:17.083349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1689 09:26:17.083401 ==
1690 09:26:17.083451 RX Vref Scan: 1
1691 09:26:17.083502
1692 09:26:17.083553 Set Vref Range= 32 -> 127
1693 09:26:17.083603
1694 09:26:17.083654 RX Vref 32 -> 127, step: 1
1695 09:26:17.083705
1696 09:26:17.083755 RX Delay -95 -> 252, step: 8
1697 09:26:17.083806
1698 09:26:17.083856 Set Vref, RX VrefLevel [Byte0]: 32
1699 09:26:17.083907 [Byte1]: 32
1700 09:26:17.083958
1701 09:26:17.084009 Set Vref, RX VrefLevel [Byte0]: 33
1702 09:26:17.084059 [Byte1]: 33
1703 09:26:17.084110
1704 09:26:17.084161 Set Vref, RX VrefLevel [Byte0]: 34
1705 09:26:17.084212 [Byte1]: 34
1706 09:26:17.084263
1707 09:26:17.084313 Set Vref, RX VrefLevel [Byte0]: 35
1708 09:26:17.084364 [Byte1]: 35
1709 09:26:17.084415
1710 09:26:17.084466 Set Vref, RX VrefLevel [Byte0]: 36
1711 09:26:17.084516 [Byte1]: 36
1712 09:26:17.084567
1713 09:26:17.084618 Set Vref, RX VrefLevel [Byte0]: 37
1714 09:26:17.084669 [Byte1]: 37
1715 09:26:17.084720
1716 09:26:17.084771 Set Vref, RX VrefLevel [Byte0]: 38
1717 09:26:17.084822 [Byte1]: 38
1718 09:26:17.084872
1719 09:26:17.084923 Set Vref, RX VrefLevel [Byte0]: 39
1720 09:26:17.084974 [Byte1]: 39
1721 09:26:17.085025
1722 09:26:17.085075 Set Vref, RX VrefLevel [Byte0]: 40
1723 09:26:17.085152 [Byte1]: 40
1724 09:26:17.085203
1725 09:26:17.085259 Set Vref, RX VrefLevel [Byte0]: 41
1726 09:26:17.085357 [Byte1]: 41
1727 09:26:17.085437
1728 09:26:17.085517 Set Vref, RX VrefLevel [Byte0]: 42
1729 09:26:17.085595 [Byte1]: 42
1730 09:26:17.085649
1731 09:26:17.085700 Set Vref, RX VrefLevel [Byte0]: 43
1732 09:26:17.085752 [Byte1]: 43
1733 09:26:17.085803
1734 09:26:17.085854 Set Vref, RX VrefLevel [Byte0]: 44
1735 09:26:17.085905 [Byte1]: 44
1736 09:26:17.085956
1737 09:26:17.086007 Set Vref, RX VrefLevel [Byte0]: 45
1738 09:26:17.086057 [Byte1]: 45
1739 09:26:17.086109
1740 09:26:17.086159 Set Vref, RX VrefLevel [Byte0]: 46
1741 09:26:17.086210 [Byte1]: 46
1742 09:26:17.086260
1743 09:26:17.086311 Set Vref, RX VrefLevel [Byte0]: 47
1744 09:26:17.086361 [Byte1]: 47
1745 09:26:17.086412
1746 09:26:17.086463 Set Vref, RX VrefLevel [Byte0]: 48
1747 09:26:17.086513 [Byte1]: 48
1748 09:26:17.086564
1749 09:26:17.086615 Set Vref, RX VrefLevel [Byte0]: 49
1750 09:26:17.086665 [Byte1]: 49
1751 09:26:17.086716
1752 09:26:17.086767 Set Vref, RX VrefLevel [Byte0]: 50
1753 09:26:17.086817 [Byte1]: 50
1754 09:26:17.086868
1755 09:26:17.086918 Set Vref, RX VrefLevel [Byte0]: 51
1756 09:26:17.086983 [Byte1]: 51
1757 09:26:17.087036
1758 09:26:17.087087 Set Vref, RX VrefLevel [Byte0]: 52
1759 09:26:17.087141 [Byte1]: 52
1760 09:26:17.087193
1761 09:26:17.087244 Set Vref, RX VrefLevel [Byte0]: 53
1762 09:26:17.087295 [Byte1]: 53
1763 09:26:17.087367
1764 09:26:17.087432 Set Vref, RX VrefLevel [Byte0]: 54
1765 09:26:17.087686 [Byte1]: 54
1766 09:26:17.087823
1767 09:26:17.087949 Set Vref, RX VrefLevel [Byte0]: 55
1768 09:26:17.088078 [Byte1]: 55
1769 09:26:17.088204
1770 09:26:17.088329 Set Vref, RX VrefLevel [Byte0]: 56
1771 09:26:17.088391 [Byte1]: 56
1772 09:26:17.088472
1773 09:26:17.088553 Set Vref, RX VrefLevel [Byte0]: 57
1774 09:26:17.088634 [Byte1]: 57
1775 09:26:17.088714
1776 09:26:17.088794 Set Vref, RX VrefLevel [Byte0]: 58
1777 09:26:17.088875 [Byte1]: 58
1778 09:26:17.088955
1779 09:26:17.089039 Set Vref, RX VrefLevel [Byte0]: 59
1780 09:26:17.089119 [Byte1]: 59
1781 09:26:17.089199
1782 09:26:17.089315 Set Vref, RX VrefLevel [Byte0]: 60
1783 09:26:17.089370 [Byte1]: 60
1784 09:26:17.089421
1785 09:26:17.089472 Set Vref, RX VrefLevel [Byte0]: 61
1786 09:26:17.089524 [Byte1]: 61
1787 09:26:17.089575
1788 09:26:17.089626 Set Vref, RX VrefLevel [Byte0]: 62
1789 09:26:17.089677 [Byte1]: 62
1790 09:26:17.089752
1791 09:26:17.089832 Set Vref, RX VrefLevel [Byte0]: 63
1792 09:26:17.089912 [Byte1]: 63
1793 09:26:17.089965
1794 09:26:17.090016 Set Vref, RX VrefLevel [Byte0]: 64
1795 09:26:17.090067 [Byte1]: 64
1796 09:26:17.090121
1797 09:26:17.090173 Set Vref, RX VrefLevel [Byte0]: 65
1798 09:26:17.090224 [Byte1]: 65
1799 09:26:17.090275
1800 09:26:17.090326 Set Vref, RX VrefLevel [Byte0]: 66
1801 09:26:17.090377 [Byte1]: 66
1802 09:26:17.090427
1803 09:26:17.090478 Set Vref, RX VrefLevel [Byte0]: 67
1804 09:26:17.090529 [Byte1]: 67
1805 09:26:17.090618
1806 09:26:17.090668 Set Vref, RX VrefLevel [Byte0]: 68
1807 09:26:17.090718 [Byte1]: 68
1808 09:26:17.090769
1809 09:26:17.090829 Set Vref, RX VrefLevel [Byte0]: 69
1810 09:26:17.090910 [Byte1]: 69
1811 09:26:17.090990
1812 09:26:17.091070 Set Vref, RX VrefLevel [Byte0]: 70
1813 09:26:17.091153 [Byte1]: 70
1814 09:26:17.091208
1815 09:26:17.091262 Set Vref, RX VrefLevel [Byte0]: 71
1816 09:26:17.091314 [Byte1]: 71
1817 09:26:17.091365
1818 09:26:17.091415 Set Vref, RX VrefLevel [Byte0]: 72
1819 09:26:17.091466 [Byte1]: 72
1820 09:26:17.091517
1821 09:26:17.091568 Final RX Vref Byte 0 = 61 to rank0
1822 09:26:17.091619 Final RX Vref Byte 1 = 56 to rank0
1823 09:26:17.091670 Final RX Vref Byte 0 = 61 to rank1
1824 09:26:17.091721 Final RX Vref Byte 1 = 56 to rank1==
1825 09:26:17.091772 Dram Type= 6, Freq= 0, CH_1, rank 0
1826 09:26:17.091824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1827 09:26:17.091875 ==
1828 09:26:17.091925 DQS Delay:
1829 09:26:17.091976 DQS0 = 0, DQS1 = 0
1830 09:26:17.092028 DQM Delay:
1831 09:26:17.092094 DQM0 = 84, DQM1 = 78
1832 09:26:17.092146 DQ Delay:
1833 09:26:17.092197 DQ0 =88, DQ1 =80, DQ2 =72, DQ3 =84
1834 09:26:17.092248 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1835 09:26:17.092299 DQ8 =64, DQ9 =68, DQ10 =76, DQ11 =72
1836 09:26:17.092350 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1837 09:26:17.092400
1838 09:26:17.092451
1839 09:26:17.092501 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f32, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1840 09:26:17.092556 CH1 RK0: MR19=606, MR18=1F32
1841 09:26:17.092607 CH1_RK0: MR19=0x606, MR18=0x1F32, DQSOSC=397, MR23=63, INC=93, DEC=62
1842 09:26:17.092659
1843 09:26:17.092709 ----->DramcWriteLeveling(PI) begin...
1844 09:26:17.092760 ==
1845 09:26:17.092812 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 09:26:17.092865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 09:26:17.092917 ==
1848 09:26:17.092967 Write leveling (Byte 0): 24 => 24
1849 09:26:17.093018 Write leveling (Byte 1): 29 => 29
1850 09:26:17.093069 DramcWriteLeveling(PI) end<-----
1851 09:26:17.093120
1852 09:26:17.093170 ==
1853 09:26:17.093221 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 09:26:17.093311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 09:26:17.093365 ==
1856 09:26:17.093415 [Gating] SW mode calibration
1857 09:26:17.093466 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1858 09:26:17.093518 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1859 09:26:17.093570 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1860 09:26:17.093622 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1861 09:26:17.093673 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1862 09:26:17.093724 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 09:26:17.093775 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 09:26:17.093826 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 09:26:17.093877 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 09:26:17.093928 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 09:26:17.093979 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 09:26:17.094029 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 09:26:17.094080 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 09:26:17.094132 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 09:26:17.094183 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 09:26:17.094234 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 09:26:17.094285 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 09:26:17.094336 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 09:26:17.094387 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1876 09:26:17.094439 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1877 09:26:17.094490 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 09:26:17.094541 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 09:26:17.094592 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 09:26:17.094643 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 09:26:17.094694 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 09:26:17.094744 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 09:26:17.094795 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 09:26:17.094845 0 9 4 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
1885 09:26:17.094896 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
1886 09:26:17.094947 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 09:26:17.095000 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 09:26:17.095051 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 09:26:17.095298 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 09:26:17.095429 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 09:26:17.095553 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
1892 09:26:17.095680 0 10 4 | B1->B0 | 3131 2e2e | 1 1 | (1 1) (1 0)
1893 09:26:17.095808 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1894 09:26:17.095890 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 09:26:17.095944 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 09:26:17.095997 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 09:26:17.096049 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 09:26:17.096101 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 09:26:17.096153 0 11 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1900 09:26:17.096217 0 11 4 | B1->B0 | 2e2e 3f3f | 0 1 | (0 0) (0 0)
1901 09:26:17.096270 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1902 09:26:17.096321 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 09:26:17.096393 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 09:26:17.096475 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 09:26:17.096567 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 09:26:17.096652 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 09:26:17.096741 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1908 09:26:17.096835 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1909 09:26:17.096892 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1910 09:26:17.096945 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 09:26:17.096997 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 09:26:17.097048 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 09:26:17.097100 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 09:26:17.097152 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 09:26:17.097204 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 09:26:17.097287 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 09:26:17.097355 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 09:26:17.097407 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 09:26:17.097458 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 09:26:17.097510 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 09:26:17.097561 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 09:26:17.097628 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 09:26:17.097681 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 09:26:17.097732 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1925 09:26:17.097784 Total UI for P1: 0, mck2ui 16
1926 09:26:17.097855 best dqsien dly found for B0: ( 0, 14, 2)
1927 09:26:17.097914 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1928 09:26:17.097996 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 09:26:17.098048 Total UI for P1: 0, mck2ui 16
1930 09:26:17.098109 best dqsien dly found for B1: ( 0, 14, 6)
1931 09:26:17.098165 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1932 09:26:17.098217 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1933 09:26:17.098269
1934 09:26:17.098336 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1935 09:26:17.098388 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1936 09:26:17.098439 [Gating] SW calibration Done
1937 09:26:17.098494 ==
1938 09:26:17.098548 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 09:26:17.098600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 09:26:17.098652 ==
1941 09:26:17.098708 RX Vref Scan: 0
1942 09:26:17.098761
1943 09:26:17.098812 RX Vref 0 -> 0, step: 1
1944 09:26:17.098863
1945 09:26:17.098943 RX Delay -130 -> 252, step: 16
1946 09:26:17.099025 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1947 09:26:17.099115 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1948 09:26:17.099197 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1949 09:26:17.099279 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1950 09:26:17.099359 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1951 09:26:17.099440 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1952 09:26:17.099521 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1953 09:26:17.099601 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1954 09:26:17.099682 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1955 09:26:17.099762 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1956 09:26:17.099843 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1957 09:26:17.099924 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1958 09:26:17.100004 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1959 09:26:17.100085 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1960 09:26:17.100165 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1961 09:26:17.100246 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1962 09:26:17.100344 ==
1963 09:26:17.100438 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 09:26:17.100519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 09:26:17.100599 ==
1966 09:26:17.100679 DQS Delay:
1967 09:26:17.100759 DQS0 = 0, DQS1 = 0
1968 09:26:17.100839 DQM Delay:
1969 09:26:17.100919 DQM0 = 80, DQM1 = 78
1970 09:26:17.100998 DQ Delay:
1971 09:26:17.101079 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =69
1972 09:26:17.101159 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1973 09:26:17.101240 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1974 09:26:17.101337 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1975 09:26:17.101390
1976 09:26:17.101440
1977 09:26:17.101491 ==
1978 09:26:17.101541 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 09:26:17.101593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 09:26:17.101645 ==
1981 09:26:17.101696
1982 09:26:17.101745
1983 09:26:17.101796 TX Vref Scan disable
1984 09:26:17.101847 == TX Byte 0 ==
1985 09:26:17.101898 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1986 09:26:17.252389 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1987 09:26:17.252527 == TX Byte 1 ==
1988 09:26:17.252594 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1989 09:26:17.252654 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1990 09:26:17.252711 ==
1991 09:26:17.252768 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 09:26:17.252822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 09:26:17.252876 ==
1994 09:26:17.252929 TX Vref=22, minBit 1, minWin=27, winSum=448
1995 09:26:17.252983 TX Vref=24, minBit 1, minWin=27, winSum=447
1996 09:26:17.253036 TX Vref=26, minBit 1, minWin=27, winSum=448
1997 09:26:17.253327 TX Vref=28, minBit 5, minWin=27, winSum=454
1998 09:26:17.253492 TX Vref=30, minBit 5, minWin=27, winSum=452
1999 09:26:17.253622 TX Vref=32, minBit 4, minWin=27, winSum=453
2000 09:26:17.253752 [TxChooseVref] Worse bit 5, Min win 27, Win sum 454, Final Vref 28
2001 09:26:17.253912
2002 09:26:17.253979 Final TX Range 1 Vref 28
2003 09:26:17.254034
2004 09:26:17.254087 ==
2005 09:26:17.254140 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 09:26:17.254193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 09:26:17.254245 ==
2008 09:26:17.254297
2009 09:26:17.254348
2010 09:26:17.254400 TX Vref Scan disable
2011 09:26:17.254452 == TX Byte 0 ==
2012 09:26:17.254503 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2013 09:26:17.254555 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2014 09:26:17.254607 == TX Byte 1 ==
2015 09:26:17.254658 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2016 09:26:17.254709 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2017 09:26:17.254760
2018 09:26:17.254811 [DATLAT]
2019 09:26:17.254862 Freq=800, CH1 RK1
2020 09:26:17.254913
2021 09:26:17.254965 DATLAT Default: 0xa
2022 09:26:17.255015 0, 0xFFFF, sum = 0
2023 09:26:17.255068 1, 0xFFFF, sum = 0
2024 09:26:17.255120 2, 0xFFFF, sum = 0
2025 09:26:17.255172 3, 0xFFFF, sum = 0
2026 09:26:17.255223 4, 0xFFFF, sum = 0
2027 09:26:17.255275 5, 0xFFFF, sum = 0
2028 09:26:17.255326 6, 0xFFFF, sum = 0
2029 09:26:17.255378 7, 0xFFFF, sum = 0
2030 09:26:17.255429 8, 0xFFFF, sum = 0
2031 09:26:17.255481 9, 0x0, sum = 1
2032 09:26:17.255532 10, 0x0, sum = 2
2033 09:26:17.255585 11, 0x0, sum = 3
2034 09:26:17.255636 12, 0x0, sum = 4
2035 09:26:17.255687 best_step = 10
2036 09:26:17.255738
2037 09:26:17.255788 ==
2038 09:26:17.255839 Dram Type= 6, Freq= 0, CH_1, rank 1
2039 09:26:17.255891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2040 09:26:17.255942 ==
2041 09:26:17.255993 RX Vref Scan: 0
2042 09:26:17.256043
2043 09:26:17.256094 RX Vref 0 -> 0, step: 1
2044 09:26:17.256144
2045 09:26:17.256195 RX Delay -95 -> 252, step: 8
2046 09:26:17.256246 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2047 09:26:17.256298 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2048 09:26:17.256349 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2049 09:26:17.256400 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2050 09:26:17.256451 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2051 09:26:17.256502 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2052 09:26:17.256553 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2053 09:26:17.256603 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2054 09:26:17.256654 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2055 09:26:17.256705 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2056 09:26:17.256756 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2057 09:26:17.256807 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2058 09:26:17.256858 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2059 09:26:17.256909 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2060 09:26:17.256960 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2061 09:26:17.257011 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2062 09:26:17.257063 ==
2063 09:26:17.257114 Dram Type= 6, Freq= 0, CH_1, rank 1
2064 09:26:17.257165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2065 09:26:17.257232 ==
2066 09:26:17.257309 DQS Delay:
2067 09:26:17.257361 DQS0 = 0, DQS1 = 0
2068 09:26:17.257412 DQM Delay:
2069 09:26:17.257463 DQM0 = 86, DQM1 = 81
2070 09:26:17.257514 DQ Delay:
2071 09:26:17.257564 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2072 09:26:17.257615 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2073 09:26:17.257666 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
2074 09:26:17.257717 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2075 09:26:17.257768
2076 09:26:17.257818
2077 09:26:17.257869 [DQSOSCAuto] RK1, (LSB)MR18= 0x213d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2078 09:26:17.257922 CH1 RK1: MR19=606, MR18=213D
2079 09:26:17.257973 CH1_RK1: MR19=0x606, MR18=0x213D, DQSOSC=394, MR23=63, INC=95, DEC=63
2080 09:26:17.258027 [RxdqsGatingPostProcess] freq 800
2081 09:26:17.258078 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2082 09:26:17.258129 Pre-setting of DQS Precalculation
2083 09:26:17.258181 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2084 09:26:17.258232 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2085 09:26:17.258285 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2086 09:26:17.258337
2087 09:26:17.258388
2088 09:26:17.258438 [Calibration Summary] 1600 Mbps
2089 09:26:17.258490 CH 0, Rank 0
2090 09:26:17.258541 SW Impedance : PASS
2091 09:26:17.258592 DUTY Scan : NO K
2092 09:26:17.258643 ZQ Calibration : PASS
2093 09:26:17.258694 Jitter Meter : NO K
2094 09:26:17.258745 CBT Training : PASS
2095 09:26:17.258796 Write leveling : PASS
2096 09:26:17.258847 RX DQS gating : PASS
2097 09:26:17.258898 RX DQ/DQS(RDDQC) : PASS
2098 09:26:17.258949 TX DQ/DQS : PASS
2099 09:26:17.259001 RX DATLAT : PASS
2100 09:26:17.259052 RX DQ/DQS(Engine): PASS
2101 09:26:17.259103 TX OE : NO K
2102 09:26:17.259154 All Pass.
2103 09:26:17.259221
2104 09:26:17.259274 CH 0, Rank 1
2105 09:26:17.259343 SW Impedance : PASS
2106 09:26:17.259395 DUTY Scan : NO K
2107 09:26:17.259446 ZQ Calibration : PASS
2108 09:26:17.259497 Jitter Meter : NO K
2109 09:26:17.259548 CBT Training : PASS
2110 09:26:17.259599 Write leveling : PASS
2111 09:26:17.259650 RX DQS gating : PASS
2112 09:26:17.259700 RX DQ/DQS(RDDQC) : PASS
2113 09:26:17.259751 TX DQ/DQS : PASS
2114 09:26:17.259802 RX DATLAT : PASS
2115 09:26:17.259853 RX DQ/DQS(Engine): PASS
2116 09:26:17.259903 TX OE : NO K
2117 09:26:17.259955 All Pass.
2118 09:26:17.260005
2119 09:26:17.260056 CH 1, Rank 0
2120 09:26:17.260108 SW Impedance : PASS
2121 09:26:17.260159 DUTY Scan : NO K
2122 09:26:17.260210 ZQ Calibration : PASS
2123 09:26:17.260261 Jitter Meter : NO K
2124 09:26:17.260313 CBT Training : PASS
2125 09:26:17.260363 Write leveling : PASS
2126 09:26:17.260414 RX DQS gating : PASS
2127 09:26:17.260464 RX DQ/DQS(RDDQC) : PASS
2128 09:26:17.260515 TX DQ/DQS : PASS
2129 09:26:17.260567 RX DATLAT : PASS
2130 09:26:17.260618 RX DQ/DQS(Engine): PASS
2131 09:26:17.260668 TX OE : NO K
2132 09:26:17.260720 All Pass.
2133 09:26:17.260771
2134 09:26:17.260822 CH 1, Rank 1
2135 09:26:17.260872 SW Impedance : PASS
2136 09:26:17.260923 DUTY Scan : NO K
2137 09:26:17.260974 ZQ Calibration : PASS
2138 09:26:17.261025 Jitter Meter : NO K
2139 09:26:17.261076 CBT Training : PASS
2140 09:26:17.261127 Write leveling : PASS
2141 09:26:17.261179 RX DQS gating : PASS
2142 09:26:17.261230 RX DQ/DQS(RDDQC) : PASS
2143 09:26:17.261320 TX DQ/DQS : PASS
2144 09:26:17.261373 RX DATLAT : PASS
2145 09:26:17.261424 RX DQ/DQS(Engine): PASS
2146 09:26:17.261475 TX OE : NO K
2147 09:26:17.261526 All Pass.
2148 09:26:17.261577
2149 09:26:17.261628 DramC Write-DBI off
2150 09:26:17.261679 PER_BANK_REFRESH: Hybrid Mode
2151 09:26:17.261931 TX_TRACKING: ON
2152 09:26:17.262065 [GetDramInforAfterCalByMRR] Vendor 6.
2153 09:26:17.262194 [GetDramInforAfterCalByMRR] Revision 606.
2154 09:26:17.262320 [GetDramInforAfterCalByMRR] Revision 2 0.
2155 09:26:17.262446 MR0 0x3b3b
2156 09:26:17.262516 MR8 0x5151
2157 09:26:17.262570 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2158 09:26:17.262623
2159 09:26:17.262675 MR0 0x3b3b
2160 09:26:17.262727 MR8 0x5151
2161 09:26:17.262779 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2162 09:26:17.262830
2163 09:26:17.262882 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2164 09:26:17.262935 [FAST_K] Save calibration result to emmc
2165 09:26:17.262986 [FAST_K] Save calibration result to emmc
2166 09:26:17.263039 dram_init: config_dvfs: 1
2167 09:26:17.263090 dramc_set_vcore_voltage set vcore to 662500
2168 09:26:17.263142 Read voltage for 1200, 2
2169 09:26:17.263194 Vio18 = 0
2170 09:26:17.263246 Vcore = 662500
2171 09:26:17.263297 Vdram = 0
2172 09:26:17.263349 Vddq = 0
2173 09:26:17.263400 Vmddr = 0
2174 09:26:17.263451 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2175 09:26:17.263503 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2176 09:26:17.263555 MEM_TYPE=3, freq_sel=15
2177 09:26:17.263606 sv_algorithm_assistance_LP4_1600
2178 09:26:17.263658 ============ PULL DRAM RESETB DOWN ============
2179 09:26:17.263710 ========== PULL DRAM RESETB DOWN end =========
2180 09:26:17.263762 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2181 09:26:17.263814 ===================================
2182 09:26:17.263866 LPDDR4 DRAM CONFIGURATION
2183 09:26:17.263918 ===================================
2184 09:26:17.263970 EX_ROW_EN[0] = 0x0
2185 09:26:17.264021 EX_ROW_EN[1] = 0x0
2186 09:26:17.264072 LP4Y_EN = 0x0
2187 09:26:17.264124 WORK_FSP = 0x0
2188 09:26:17.264175 WL = 0x4
2189 09:26:17.264226 RL = 0x4
2190 09:26:17.264277 BL = 0x2
2191 09:26:17.264328 RPST = 0x0
2192 09:26:17.264379 RD_PRE = 0x0
2193 09:26:17.264430 WR_PRE = 0x1
2194 09:26:17.264481 WR_PST = 0x0
2195 09:26:17.264532 DBI_WR = 0x0
2196 09:26:17.264583 DBI_RD = 0x0
2197 09:26:17.264634 OTF = 0x1
2198 09:26:17.264685 ===================================
2199 09:26:17.264737 ===================================
2200 09:26:17.264788 ANA top config
2201 09:26:17.264840 ===================================
2202 09:26:17.264891 DLL_ASYNC_EN = 0
2203 09:26:17.264943 ALL_SLAVE_EN = 0
2204 09:26:17.264994 NEW_RANK_MODE = 1
2205 09:26:17.265046 DLL_IDLE_MODE = 1
2206 09:26:17.265097 LP45_APHY_COMB_EN = 1
2207 09:26:17.265148 TX_ODT_DIS = 1
2208 09:26:17.265199 NEW_8X_MODE = 1
2209 09:26:17.265251 ===================================
2210 09:26:17.265344 ===================================
2211 09:26:17.265395 data_rate = 2400
2212 09:26:17.265447 CKR = 1
2213 09:26:17.265498 DQ_P2S_RATIO = 8
2214 09:26:17.265550 ===================================
2215 09:26:17.265602 CA_P2S_RATIO = 8
2216 09:26:17.265653 DQ_CA_OPEN = 0
2217 09:26:17.265705 DQ_SEMI_OPEN = 0
2218 09:26:17.265756 CA_SEMI_OPEN = 0
2219 09:26:17.265807 CA_FULL_RATE = 0
2220 09:26:17.265859 DQ_CKDIV4_EN = 0
2221 09:26:17.265911 CA_CKDIV4_EN = 0
2222 09:26:17.265962 CA_PREDIV_EN = 0
2223 09:26:17.266013 PH8_DLY = 17
2224 09:26:17.266065 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2225 09:26:17.266116 DQ_AAMCK_DIV = 4
2226 09:26:17.266168 CA_AAMCK_DIV = 4
2227 09:26:17.266219 CA_ADMCK_DIV = 4
2228 09:26:17.266270 DQ_TRACK_CA_EN = 0
2229 09:26:17.266322 CA_PICK = 1200
2230 09:26:17.266374 CA_MCKIO = 1200
2231 09:26:17.266426 MCKIO_SEMI = 0
2232 09:26:17.266477 PLL_FREQ = 2366
2233 09:26:17.266528 DQ_UI_PI_RATIO = 32
2234 09:26:17.266580 CA_UI_PI_RATIO = 0
2235 09:26:17.266631 ===================================
2236 09:26:17.266682 ===================================
2237 09:26:17.266734 memory_type:LPDDR4
2238 09:26:17.266785 GP_NUM : 10
2239 09:26:17.266837 SRAM_EN : 1
2240 09:26:17.266888 MD32_EN : 0
2241 09:26:17.266939 ===================================
2242 09:26:17.266991 [ANA_INIT] >>>>>>>>>>>>>>
2243 09:26:17.267043 <<<<<< [CONFIGURE PHASE]: ANA_TX
2244 09:26:17.267094 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2245 09:26:17.267146 ===================================
2246 09:26:17.267228 data_rate = 2400,PCW = 0X5b00
2247 09:26:17.267279 ===================================
2248 09:26:17.267331 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2249 09:26:17.267383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2250 09:26:17.267439 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2251 09:26:17.267507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2252 09:26:17.267560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2253 09:26:17.267611 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2254 09:26:17.267663 [ANA_INIT] flow start
2255 09:26:17.267715 [ANA_INIT] PLL >>>>>>>>
2256 09:26:17.267767 [ANA_INIT] PLL <<<<<<<<
2257 09:26:17.267818 [ANA_INIT] MIDPI >>>>>>>>
2258 09:26:17.267869 [ANA_INIT] MIDPI <<<<<<<<
2259 09:26:17.267921 [ANA_INIT] DLL >>>>>>>>
2260 09:26:17.267972 [ANA_INIT] DLL <<<<<<<<
2261 09:26:17.268023 [ANA_INIT] flow end
2262 09:26:17.268074 ============ LP4 DIFF to SE enter ============
2263 09:26:17.268126 ============ LP4 DIFF to SE exit ============
2264 09:26:17.268178 [ANA_INIT] <<<<<<<<<<<<<
2265 09:26:17.268229 [Flow] Enable top DCM control >>>>>
2266 09:26:17.268280 [Flow] Enable top DCM control <<<<<
2267 09:26:17.268331 Enable DLL master slave shuffle
2268 09:26:17.268383 ==============================================================
2269 09:26:17.268434 Gating Mode config
2270 09:26:17.268486 ==============================================================
2271 09:26:17.268538 Config description:
2272 09:26:17.268589 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2273 09:26:17.268642 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2274 09:26:17.268889 SELPH_MODE 0: By rank 1: By Phase
2275 09:26:17.268982 ==============================================================
2276 09:26:17.269036 GAT_TRACK_EN = 1
2277 09:26:17.269088 RX_GATING_MODE = 2
2278 09:26:17.269140 RX_GATING_TRACK_MODE = 2
2279 09:26:17.269192 SELPH_MODE = 1
2280 09:26:17.269243 PICG_EARLY_EN = 1
2281 09:26:17.269335 VALID_LAT_VALUE = 1
2282 09:26:17.269388 ==============================================================
2283 09:26:17.269441 Enter into Gating configuration >>>>
2284 09:26:17.269493 Exit from Gating configuration <<<<
2285 09:26:17.269544 Enter into DVFS_PRE_config >>>>>
2286 09:26:17.269596 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2287 09:26:17.269649 Exit from DVFS_PRE_config <<<<<
2288 09:26:17.269701 Enter into PICG configuration >>>>
2289 09:26:17.269753 Exit from PICG configuration <<<<
2290 09:26:17.269805 [RX_INPUT] configuration >>>>>
2291 09:26:17.269856 [RX_INPUT] configuration <<<<<
2292 09:26:17.269907 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2293 09:26:17.269960 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2294 09:26:17.270012 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2295 09:26:17.270065 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2296 09:26:17.270116 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2297 09:26:17.270168 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2298 09:26:17.270221 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2299 09:26:17.270273 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2300 09:26:17.270324 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2301 09:26:17.270376 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2302 09:26:17.270428 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2303 09:26:17.270480 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2304 09:26:17.270531 ===================================
2305 09:26:17.270583 LPDDR4 DRAM CONFIGURATION
2306 09:26:17.270634 ===================================
2307 09:26:17.270686 EX_ROW_EN[0] = 0x0
2308 09:26:17.270737 EX_ROW_EN[1] = 0x0
2309 09:26:17.270789 LP4Y_EN = 0x0
2310 09:26:17.270840 WORK_FSP = 0x0
2311 09:26:17.270892 WL = 0x4
2312 09:26:17.270943 RL = 0x4
2313 09:26:17.270994 BL = 0x2
2314 09:26:17.271045 RPST = 0x0
2315 09:26:17.271096 RD_PRE = 0x0
2316 09:26:17.271148 WR_PRE = 0x1
2317 09:26:17.271198 WR_PST = 0x0
2318 09:26:17.271250 DBI_WR = 0x0
2319 09:26:17.271301 DBI_RD = 0x0
2320 09:26:17.271352 OTF = 0x1
2321 09:26:17.271404 ===================================
2322 09:26:17.271455 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2323 09:26:17.271512 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2324 09:26:17.271574 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 09:26:17.271627 ===================================
2326 09:26:17.271683 LPDDR4 DRAM CONFIGURATION
2327 09:26:17.271737 ===================================
2328 09:26:17.271789 EX_ROW_EN[0] = 0x10
2329 09:26:17.271840 EX_ROW_EN[1] = 0x0
2330 09:26:17.271900 LP4Y_EN = 0x0
2331 09:26:17.271953 WORK_FSP = 0x0
2332 09:26:17.272004 WL = 0x4
2333 09:26:17.272058 RL = 0x4
2334 09:26:17.272111 BL = 0x2
2335 09:26:17.272163 RPST = 0x0
2336 09:26:17.272215 RD_PRE = 0x0
2337 09:26:17.272270 WR_PRE = 0x1
2338 09:26:17.272321 WR_PST = 0x0
2339 09:26:17.272372 DBI_WR = 0x0
2340 09:26:17.272424 DBI_RD = 0x0
2341 09:26:17.272475 OTF = 0x1
2342 09:26:17.272526 ===================================
2343 09:26:17.272578 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2344 09:26:17.272638 ==
2345 09:26:17.272691 Dram Type= 6, Freq= 0, CH_0, rank 0
2346 09:26:17.272743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2347 09:26:17.272796 ==
2348 09:26:17.272847 [Duty_Offset_Calibration]
2349 09:26:17.272899 B0:2 B1:0 CA:4
2350 09:26:17.272950
2351 09:26:17.273001 [DutyScan_Calibration_Flow] k_type=0
2352 09:26:17.273053
2353 09:26:17.273104 ==CLK 0==
2354 09:26:17.273156 Final CLK duty delay cell = 0
2355 09:26:17.273207 [0] MAX Duty = 5156%(X100), DQS PI = 14
2356 09:26:17.273300 [0] MIN Duty = 4969%(X100), DQS PI = 8
2357 09:26:17.273353 [0] AVG Duty = 5062%(X100)
2358 09:26:17.273404
2359 09:26:17.273455 CH0 CLK Duty spec in!! Max-Min= 187%
2360 09:26:17.273506 [DutyScan_Calibration_Flow] ====Done====
2361 09:26:17.273557
2362 09:26:17.273608 [DutyScan_Calibration_Flow] k_type=1
2363 09:26:17.273659
2364 09:26:17.273710 ==DQS 0 ==
2365 09:26:17.273761 Final DQS duty delay cell = 0
2366 09:26:17.273844 [0] MAX Duty = 5156%(X100), DQS PI = 18
2367 09:26:17.273895 [0] MIN Duty = 5093%(X100), DQS PI = 0
2368 09:26:17.273946 [0] AVG Duty = 5124%(X100)
2369 09:26:17.273997
2370 09:26:17.274047 ==DQS 1 ==
2371 09:26:17.274097 Final DQS duty delay cell = 0
2372 09:26:17.274154 [0] MAX Duty = 5125%(X100), DQS PI = 52
2373 09:26:17.274206 [0] MIN Duty = 4969%(X100), DQS PI = 62
2374 09:26:17.274257 [0] AVG Duty = 5047%(X100)
2375 09:26:17.274312
2376 09:26:17.274364 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2377 09:26:17.274414
2378 09:26:17.274465 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2379 09:26:17.274523 [DutyScan_Calibration_Flow] ====Done====
2380 09:26:17.274574
2381 09:26:17.274625 [DutyScan_Calibration_Flow] k_type=3
2382 09:26:17.274676
2383 09:26:17.274735 ==DQM 0 ==
2384 09:26:17.274787 Final DQM duty delay cell = 0
2385 09:26:17.274838 [0] MAX Duty = 5125%(X100), DQS PI = 20
2386 09:26:17.274893 [0] MIN Duty = 4844%(X100), DQS PI = 52
2387 09:26:17.274944 [0] AVG Duty = 4984%(X100)
2388 09:26:17.274995
2389 09:26:17.275089 ==DQM 1 ==
2390 09:26:17.275171 Final DQM duty delay cell = 0
2391 09:26:17.275246 [0] MAX Duty = 4969%(X100), DQS PI = 2
2392 09:26:17.275300 [0] MIN Duty = 4875%(X100), DQS PI = 18
2393 09:26:17.275351 [0] AVG Duty = 4922%(X100)
2394 09:26:17.275403
2395 09:26:17.275454 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2396 09:26:17.275505
2397 09:26:17.275556 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2398 09:26:17.275608 [DutyScan_Calibration_Flow] ====Done====
2399 09:26:17.275659
2400 09:26:17.275710 [DutyScan_Calibration_Flow] k_type=2
2401 09:26:17.275760
2402 09:26:17.275811 ==DQ 0 ==
2403 09:26:17.275862 Final DQ duty delay cell = 0
2404 09:26:17.275914 [0] MAX Duty = 5156%(X100), DQS PI = 18
2405 09:26:17.275966 [0] MIN Duty = 4969%(X100), DQS PI = 52
2406 09:26:17.276228 [0] AVG Duty = 5062%(X100)
2407 09:26:17.276418
2408 09:26:17.276555 ==DQ 1 ==
2409 09:26:17.276711 Final DQ duty delay cell = 0
2410 09:26:17.276870 [0] MAX Duty = 5125%(X100), DQS PI = 4
2411 09:26:17.277013 [0] MIN Duty = 4938%(X100), DQS PI = 14
2412 09:26:17.277142 [0] AVG Duty = 5031%(X100)
2413 09:26:17.277279
2414 09:26:17.277450 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2415 09:26:17.277592
2416 09:26:17.277711 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2417 09:26:17.277796 [DutyScan_Calibration_Flow] ====Done====
2418 09:26:17.277849 ==
2419 09:26:17.277901 Dram Type= 6, Freq= 0, CH_1, rank 0
2420 09:26:17.277982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2421 09:26:17.278035 ==
2422 09:26:17.278087 [Duty_Offset_Calibration]
2423 09:26:17.278166 B0:0 B1:-1 CA:3
2424 09:26:17.278221
2425 09:26:17.278274 [DutyScan_Calibration_Flow] k_type=0
2426 09:26:17.278353
2427 09:26:17.278406 ==CLK 0==
2428 09:26:17.278457 Final CLK duty delay cell = -4
2429 09:26:17.278509 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2430 09:26:17.278561 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2431 09:26:17.278621 [-4] AVG Duty = 4938%(X100)
2432 09:26:17.278684
2433 09:26:17.278736 CH1 CLK Duty spec in!! Max-Min= 124%
2434 09:26:17.278788 [DutyScan_Calibration_Flow] ====Done====
2435 09:26:17.278839
2436 09:26:17.278893 [DutyScan_Calibration_Flow] k_type=1
2437 09:26:17.278944
2438 09:26:17.278995 ==DQS 0 ==
2439 09:26:17.279049 Final DQS duty delay cell = 0
2440 09:26:17.279106 [0] MAX Duty = 5156%(X100), DQS PI = 18
2441 09:26:17.279158 [0] MIN Duty = 4876%(X100), DQS PI = 38
2442 09:26:17.279209 [0] AVG Duty = 5016%(X100)
2443 09:26:17.279265
2444 09:26:17.279316 ==DQS 1 ==
2445 09:26:17.279367 Final DQS duty delay cell = 0
2446 09:26:17.279421 [0] MAX Duty = 5156%(X100), DQS PI = 8
2447 09:26:17.279474 [0] MIN Duty = 5031%(X100), DQS PI = 18
2448 09:26:17.279525 [0] AVG Duty = 5093%(X100)
2449 09:26:17.279576
2450 09:26:17.279636 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2451 09:26:17.279688
2452 09:26:17.279738 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2453 09:26:17.279790 [DutyScan_Calibration_Flow] ====Done====
2454 09:26:17.279844
2455 09:26:17.279894 [DutyScan_Calibration_Flow] k_type=3
2456 09:26:17.279945
2457 09:26:17.279999 ==DQM 0 ==
2458 09:26:17.280050 Final DQM duty delay cell = 0
2459 09:26:17.280102 [0] MAX Duty = 5031%(X100), DQS PI = 28
2460 09:26:17.280153 [0] MIN Duty = 4782%(X100), DQS PI = 38
2461 09:26:17.280204 [0] AVG Duty = 4906%(X100)
2462 09:26:17.280254
2463 09:26:17.280305 ==DQM 1 ==
2464 09:26:17.280355 Final DQM duty delay cell = 4
2465 09:26:17.280406 [4] MAX Duty = 5187%(X100), DQS PI = 30
2466 09:26:17.280457 [4] MIN Duty = 5062%(X100), DQS PI = 2
2467 09:26:17.280508 [4] AVG Duty = 5124%(X100)
2468 09:26:17.280558
2469 09:26:17.280608 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2470 09:26:17.280659
2471 09:26:17.280709 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2472 09:26:17.280760 [DutyScan_Calibration_Flow] ====Done====
2473 09:26:17.280812
2474 09:26:17.280862 [DutyScan_Calibration_Flow] k_type=2
2475 09:26:17.280913
2476 09:26:17.280963 ==DQ 0 ==
2477 09:26:17.281014 Final DQ duty delay cell = -4
2478 09:26:17.281065 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2479 09:26:17.281116 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2480 09:26:17.281167 [-4] AVG Duty = 4922%(X100)
2481 09:26:17.281217
2482 09:26:17.281308 ==DQ 1 ==
2483 09:26:17.281390 Final DQ duty delay cell = 4
2484 09:26:17.281471 [4] MAX Duty = 5156%(X100), DQS PI = 10
2485 09:26:17.281552 [4] MIN Duty = 5031%(X100), DQS PI = 62
2486 09:26:17.281633 [4] AVG Duty = 5093%(X100)
2487 09:26:17.281713
2488 09:26:17.281793 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2489 09:26:17.281874
2490 09:26:17.281955 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2491 09:26:17.282035 [DutyScan_Calibration_Flow] ====Done====
2492 09:26:17.282116 nWR fixed to 30
2493 09:26:17.282197 [ModeRegInit_LP4] CH0 RK0
2494 09:26:17.282277 [ModeRegInit_LP4] CH0 RK1
2495 09:26:17.282361 [ModeRegInit_LP4] CH1 RK0
2496 09:26:17.282443 [ModeRegInit_LP4] CH1 RK1
2497 09:26:17.282524 match AC timing 7
2498 09:26:17.282578 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2499 09:26:17.282630 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2500 09:26:17.282681 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2501 09:26:17.282733 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2502 09:26:17.282784 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2503 09:26:17.282836 ==
2504 09:26:17.282887 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 09:26:17.282938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 09:26:17.282989 ==
2507 09:26:17.283040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2508 09:26:17.283092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2509 09:26:17.283144 [CA 0] Center 39 (9~70) winsize 62
2510 09:26:17.283195 [CA 1] Center 38 (8~69) winsize 62
2511 09:26:17.283246 [CA 2] Center 35 (5~66) winsize 62
2512 09:26:17.283297 [CA 3] Center 35 (4~66) winsize 63
2513 09:26:17.283348 [CA 4] Center 33 (3~64) winsize 62
2514 09:26:17.283399 [CA 5] Center 33 (3~63) winsize 61
2515 09:26:17.283454
2516 09:26:17.283506 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2517 09:26:17.283557
2518 09:26:17.283607 [CATrainingPosCal] consider 1 rank data
2519 09:26:17.283658 u2DelayCellTimex100 = 270/100 ps
2520 09:26:17.283709 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2521 09:26:17.283761 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2522 09:26:17.283811 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2523 09:26:17.283862 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2524 09:26:17.283913 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2525 09:26:17.283964 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2526 09:26:17.284014
2527 09:26:17.284065 CA PerBit enable=1, Macro0, CA PI delay=33
2528 09:26:17.284116
2529 09:26:17.284167 [CBTSetCACLKResult] CA Dly = 33
2530 09:26:17.284218 CS Dly: 7 (0~38)
2531 09:26:17.284268 ==
2532 09:26:17.284318 Dram Type= 6, Freq= 0, CH_0, rank 1
2533 09:26:17.284369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 09:26:17.284420 ==
2535 09:26:17.284471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2536 09:26:17.284523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2537 09:26:17.284574 [CA 0] Center 39 (9~70) winsize 62
2538 09:26:17.284625 [CA 1] Center 39 (9~70) winsize 62
2539 09:26:17.284676 [CA 2] Center 35 (5~66) winsize 62
2540 09:26:17.284726 [CA 3] Center 35 (5~66) winsize 62
2541 09:26:17.284777 [CA 4] Center 34 (4~65) winsize 62
2542 09:26:17.284836 [CA 5] Center 33 (3~64) winsize 62
2543 09:26:17.284887
2544 09:26:17.284937 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2545 09:26:17.284989
2546 09:26:17.285044 [CATrainingPosCal] consider 2 rank data
2547 09:26:17.285095 u2DelayCellTimex100 = 270/100 ps
2548 09:26:17.285146 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2549 09:26:17.285400 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2550 09:26:17.285530 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2551 09:26:17.285656 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2552 09:26:17.285782 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2553 09:26:17.285908 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2554 09:26:17.285984
2555 09:26:17.286039 CA PerBit enable=1, Macro0, CA PI delay=33
2556 09:26:17.286092
2557 09:26:17.286143 [CBTSetCACLKResult] CA Dly = 33
2558 09:26:17.286196 CS Dly: 8 (0~41)
2559 09:26:17.286247
2560 09:26:17.286298 ----->DramcWriteLeveling(PI) begin...
2561 09:26:17.286351 ==
2562 09:26:17.286402 Dram Type= 6, Freq= 0, CH_0, rank 0
2563 09:26:17.286454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 09:26:17.286505 ==
2565 09:26:17.286557 Write leveling (Byte 0): 30 => 30
2566 09:26:17.286608 Write leveling (Byte 1): 25 => 25
2567 09:26:17.286659 DramcWriteLeveling(PI) end<-----
2568 09:26:17.286710
2569 09:26:17.286761 ==
2570 09:26:17.286813 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 09:26:17.286864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 09:26:17.286915 ==
2573 09:26:17.286966 [Gating] SW mode calibration
2574 09:26:17.287018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2575 09:26:17.287070 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2576 09:26:17.287122 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2577 09:26:17.287179 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2578 09:26:17.287231 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 09:26:17.287283 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 09:26:17.287338 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 09:26:17.287391 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 09:26:17.287442 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2583 09:26:17.287494 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2584 09:26:17.287545 1 0 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
2585 09:26:17.287595 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2586 09:26:17.287646 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 09:26:17.287697 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 09:26:17.287748 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 09:26:17.287799 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 09:26:17.287850 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2591 09:26:17.287901 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2592 09:26:17.287952 1 1 0 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2593 09:26:17.288003 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 09:26:17.288070 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 09:26:17.288152 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 09:26:17.288238 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 09:26:17.288294 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 09:26:17.288346 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2599 09:26:17.288398 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2600 09:26:17.288458 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2601 09:26:17.288517 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 09:26:17.288572 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 09:26:17.288633 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 09:26:17.288691 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 09:26:17.288777 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 09:26:17.288865 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 09:26:17.288952 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 09:26:17.289039 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 09:26:17.289125 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 09:26:17.289211 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 09:26:17.289349 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 09:26:17.289436 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 09:26:17.289518 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 09:26:17.289599 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2615 09:26:17.289680 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2616 09:26:17.289761 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2617 09:26:17.289841 Total UI for P1: 0, mck2ui 16
2618 09:26:17.289926 best dqsien dly found for B0: ( 1, 3, 26)
2619 09:26:17.290010 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 09:26:17.290092 Total UI for P1: 0, mck2ui 16
2621 09:26:17.290173 best dqsien dly found for B1: ( 1, 4, 0)
2622 09:26:17.290254 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2623 09:26:17.290338 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2624 09:26:17.290419
2625 09:26:17.290495 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2626 09:26:17.290549 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2627 09:26:17.290600 [Gating] SW calibration Done
2628 09:26:17.290651 ==
2629 09:26:17.290716 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 09:26:17.290798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 09:26:17.290882 ==
2632 09:26:17.290964 RX Vref Scan: 0
2633 09:26:17.291047
2634 09:26:17.291134 RX Vref 0 -> 0, step: 1
2635 09:26:17.291220
2636 09:26:17.291305 RX Delay -40 -> 252, step: 8
2637 09:26:17.291394 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2638 09:26:17.291484 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2639 09:26:17.291569 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2640 09:26:17.291654 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2641 09:26:17.291738 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2642 09:26:17.291820 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2643 09:26:17.291905 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2644 09:26:17.291991 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2645 09:26:17.292075 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2646 09:26:17.292157 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
2647 09:26:17.292243 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2648 09:26:17.292334 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2649 09:26:17.292417 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2650 09:26:17.292503 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2651 09:26:17.292787 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2652 09:26:17.292923 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2653 09:26:17.293051 ==
2654 09:26:17.293176 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 09:26:17.293351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 09:26:17.293441 ==
2657 09:26:17.293523 DQS Delay:
2658 09:26:17.293604 DQS0 = 0, DQS1 = 0
2659 09:26:17.293685 DQM Delay:
2660 09:26:17.293766 DQM0 = 119, DQM1 = 106
2661 09:26:17.293846 DQ Delay:
2662 09:26:17.293926 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2663 09:26:17.294008 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2664 09:26:17.294088 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2665 09:26:17.294169 DQ12 =119, DQ13 =111, DQ14 =115, DQ15 =111
2666 09:26:17.294249
2667 09:26:17.294329
2668 09:26:17.294409 ==
2669 09:26:17.294489 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 09:26:17.294571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 09:26:17.294651 ==
2672 09:26:17.294731
2673 09:26:17.294810
2674 09:26:17.294890 TX Vref Scan disable
2675 09:26:17.294970 == TX Byte 0 ==
2676 09:26:17.295051 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2677 09:26:17.295132 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2678 09:26:17.295213 == TX Byte 1 ==
2679 09:26:17.295294 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2680 09:26:17.295376 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2681 09:26:17.295459 ==
2682 09:26:17.295540 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 09:26:17.295621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 09:26:17.295702 ==
2685 09:26:17.295782 TX Vref=22, minBit 1, minWin=25, winSum=415
2686 09:26:17.295864 TX Vref=24, minBit 3, minWin=25, winSum=411
2687 09:26:17.295945 TX Vref=26, minBit 7, minWin=25, winSum=418
2688 09:26:17.296026 TX Vref=28, minBit 4, minWin=25, winSum=427
2689 09:26:17.296108 TX Vref=30, minBit 0, minWin=26, winSum=430
2690 09:26:17.296189 TX Vref=32, minBit 0, minWin=26, winSum=428
2691 09:26:17.296271 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 30
2692 09:26:17.296351
2693 09:26:17.296431 Final TX Range 1 Vref 30
2694 09:26:17.296512
2695 09:26:17.296591 ==
2696 09:26:17.296672 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 09:26:17.296753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 09:26:17.296836 ==
2699 09:26:17.296916
2700 09:26:17.297015
2701 09:26:17.297127 TX Vref Scan disable
2702 09:26:17.297216 == TX Byte 0 ==
2703 09:26:17.297333 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2704 09:26:17.297416 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2705 09:26:17.297497 == TX Byte 1 ==
2706 09:26:17.297577 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2707 09:26:17.297658 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2708 09:26:17.297739
2709 09:26:17.297819 [DATLAT]
2710 09:26:17.297899 Freq=1200, CH0 RK0
2711 09:26:17.297979
2712 09:26:17.298059 DATLAT Default: 0xd
2713 09:26:17.298139 0, 0xFFFF, sum = 0
2714 09:26:17.298222 1, 0xFFFF, sum = 0
2715 09:26:17.298304 2, 0xFFFF, sum = 0
2716 09:26:17.298386 3, 0xFFFF, sum = 0
2717 09:26:17.298468 4, 0xFFFF, sum = 0
2718 09:26:17.298550 5, 0xFFFF, sum = 0
2719 09:26:17.298632 6, 0xFFFF, sum = 0
2720 09:26:17.298714 7, 0xFFFF, sum = 0
2721 09:26:17.298796 8, 0xFFFF, sum = 0
2722 09:26:17.298879 9, 0xFFFF, sum = 0
2723 09:26:17.298961 10, 0xFFFF, sum = 0
2724 09:26:17.299043 11, 0xFFFF, sum = 0
2725 09:26:17.299126 12, 0x0, sum = 1
2726 09:26:17.299208 13, 0x0, sum = 2
2727 09:26:17.299331 14, 0x0, sum = 3
2728 09:26:17.299413 15, 0x0, sum = 4
2729 09:26:17.299495 best_step = 13
2730 09:26:17.299575
2731 09:26:17.299654 ==
2732 09:26:17.299735 Dram Type= 6, Freq= 0, CH_0, rank 0
2733 09:26:17.299816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2734 09:26:17.299896 ==
2735 09:26:17.299977 RX Vref Scan: 1
2736 09:26:17.300056
2737 09:26:17.300136 Set Vref Range= 32 -> 127
2738 09:26:17.300216
2739 09:26:17.300295 RX Vref 32 -> 127, step: 1
2740 09:26:17.300375
2741 09:26:17.300455 RX Delay -29 -> 252, step: 4
2742 09:26:17.300535
2743 09:26:17.300615 Set Vref, RX VrefLevel [Byte0]: 32
2744 09:26:17.300696 [Byte1]: 32
2745 09:26:17.300776
2746 09:26:17.300856 Set Vref, RX VrefLevel [Byte0]: 33
2747 09:26:17.300936 [Byte1]: 33
2748 09:26:17.301016
2749 09:26:17.301096 Set Vref, RX VrefLevel [Byte0]: 34
2750 09:26:17.301177 [Byte1]: 34
2751 09:26:17.301261
2752 09:26:17.301346 Set Vref, RX VrefLevel [Byte0]: 35
2753 09:26:17.301397 [Byte1]: 35
2754 09:26:17.301449
2755 09:26:17.301500 Set Vref, RX VrefLevel [Byte0]: 36
2756 09:26:17.301551 [Byte1]: 36
2757 09:26:17.301603
2758 09:26:17.301653 Set Vref, RX VrefLevel [Byte0]: 37
2759 09:26:17.301704 [Byte1]: 37
2760 09:26:17.301755
2761 09:26:17.301806 Set Vref, RX VrefLevel [Byte0]: 38
2762 09:26:17.301856 [Byte1]: 38
2763 09:26:17.301907
2764 09:26:17.301957 Set Vref, RX VrefLevel [Byte0]: 39
2765 09:26:17.302008 [Byte1]: 39
2766 09:26:17.302060
2767 09:26:17.302110 Set Vref, RX VrefLevel [Byte0]: 40
2768 09:26:17.302162 [Byte1]: 40
2769 09:26:17.302212
2770 09:26:17.302263 Set Vref, RX VrefLevel [Byte0]: 41
2771 09:26:17.302313 [Byte1]: 41
2772 09:26:17.302364
2773 09:26:17.302414 Set Vref, RX VrefLevel [Byte0]: 42
2774 09:26:17.302465 [Byte1]: 42
2775 09:26:17.302516
2776 09:26:17.302566 Set Vref, RX VrefLevel [Byte0]: 43
2777 09:26:17.302617 [Byte1]: 43
2778 09:26:17.302668
2779 09:26:17.302718 Set Vref, RX VrefLevel [Byte0]: 44
2780 09:26:17.302769 [Byte1]: 44
2781 09:26:17.302820
2782 09:26:17.302870 Set Vref, RX VrefLevel [Byte0]: 45
2783 09:26:17.302921 [Byte1]: 45
2784 09:26:17.302971
2785 09:26:17.303022 Set Vref, RX VrefLevel [Byte0]: 46
2786 09:26:17.303072 [Byte1]: 46
2787 09:26:17.303123
2788 09:26:17.303173 Set Vref, RX VrefLevel [Byte0]: 47
2789 09:26:17.303224 [Byte1]: 47
2790 09:26:17.303275
2791 09:26:17.303325 Set Vref, RX VrefLevel [Byte0]: 48
2792 09:26:17.303375 [Byte1]: 48
2793 09:26:17.303426
2794 09:26:17.303477 Set Vref, RX VrefLevel [Byte0]: 49
2795 09:26:17.303528 [Byte1]: 49
2796 09:26:17.303579
2797 09:26:17.303629 Set Vref, RX VrefLevel [Byte0]: 50
2798 09:26:17.303680 [Byte1]: 50
2799 09:26:17.303730
2800 09:26:17.303781 Set Vref, RX VrefLevel [Byte0]: 51
2801 09:26:17.303831 [Byte1]: 51
2802 09:26:17.303881
2803 09:26:17.303931 Set Vref, RX VrefLevel [Byte0]: 52
2804 09:26:17.303982 [Byte1]: 52
2805 09:26:17.304032
2806 09:26:17.304083 Set Vref, RX VrefLevel [Byte0]: 53
2807 09:26:17.304134 [Byte1]: 53
2808 09:26:17.304185
2809 09:26:17.304236 Set Vref, RX VrefLevel [Byte0]: 54
2810 09:26:17.304286 [Byte1]: 54
2811 09:26:17.304337
2812 09:26:17.304387 Set Vref, RX VrefLevel [Byte0]: 55
2813 09:26:17.304438 [Byte1]: 55
2814 09:26:17.304488
2815 09:26:17.304538 Set Vref, RX VrefLevel [Byte0]: 56
2816 09:26:17.304589 [Byte1]: 56
2817 09:26:17.304639
2818 09:26:17.304886 Set Vref, RX VrefLevel [Byte0]: 57
2819 09:26:17.305020 [Byte1]: 57
2820 09:26:17.305144
2821 09:26:17.305311 Set Vref, RX VrefLevel [Byte0]: 58
2822 09:26:17.305443 [Byte1]: 58
2823 09:26:17.305509
2824 09:26:17.305562 Set Vref, RX VrefLevel [Byte0]: 59
2825 09:26:17.305615 [Byte1]: 59
2826 09:26:17.305666
2827 09:26:17.305717 Set Vref, RX VrefLevel [Byte0]: 60
2828 09:26:17.305769 [Byte1]: 60
2829 09:26:17.305821
2830 09:26:17.305872 Set Vref, RX VrefLevel [Byte0]: 61
2831 09:26:17.305923 [Byte1]: 61
2832 09:26:17.305974
2833 09:26:17.306025 Set Vref, RX VrefLevel [Byte0]: 62
2834 09:26:17.306077 [Byte1]: 62
2835 09:26:17.306127
2836 09:26:17.306178 Set Vref, RX VrefLevel [Byte0]: 63
2837 09:26:17.306229 [Byte1]: 63
2838 09:26:17.306279
2839 09:26:17.306340 Set Vref, RX VrefLevel [Byte0]: 64
2840 09:26:17.306397 [Byte1]: 64
2841 09:26:17.306451
2842 09:26:17.306502 Set Vref, RX VrefLevel [Byte0]: 65
2843 09:26:17.306553 [Byte1]: 65
2844 09:26:17.306608
2845 09:26:17.306661 Set Vref, RX VrefLevel [Byte0]: 66
2846 09:26:17.306712 [Byte1]: 66
2847 09:26:17.306762
2848 09:26:17.306813 Set Vref, RX VrefLevel [Byte0]: 67
2849 09:26:17.306864 [Byte1]: 67
2850 09:26:17.306916
2851 09:26:17.306967 Set Vref, RX VrefLevel [Byte0]: 68
2852 09:26:17.307018 [Byte1]: 68
2853 09:26:17.307069
2854 09:26:17.307120 Final RX Vref Byte 0 = 56 to rank0
2855 09:26:17.307172 Final RX Vref Byte 1 = 52 to rank0
2856 09:26:17.307222 Final RX Vref Byte 0 = 56 to rank1
2857 09:26:17.307274 Final RX Vref Byte 1 = 52 to rank1==
2858 09:26:17.307325 Dram Type= 6, Freq= 0, CH_0, rank 0
2859 09:26:17.307376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2860 09:26:17.307435 ==
2861 09:26:17.307487 DQS Delay:
2862 09:26:17.307538 DQS0 = 0, DQS1 = 0
2863 09:26:17.307589 DQM Delay:
2864 09:26:17.307640 DQM0 = 119, DQM1 = 105
2865 09:26:17.307691 DQ Delay:
2866 09:26:17.307742 DQ0 =120, DQ1 =118, DQ2 =116, DQ3 =116
2867 09:26:17.307794 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =122
2868 09:26:17.307845 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2869 09:26:17.307895 DQ12 =116, DQ13 =110, DQ14 =116, DQ15 =114
2870 09:26:17.307946
2871 09:26:17.307996
2872 09:26:17.308047 [DQSOSCAuto] RK0, (LSB)MR18= 0x2fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
2873 09:26:17.308099 CH0 RK0: MR19=403, MR18=2FE
2874 09:26:17.308150 CH0_RK0: MR19=0x403, MR18=0x2FE, DQSOSC=409, MR23=63, INC=39, DEC=26
2875 09:26:17.308202
2876 09:26:17.308253 ----->DramcWriteLeveling(PI) begin...
2877 09:26:17.308305 ==
2878 09:26:17.308356 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 09:26:17.308408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 09:26:17.308459 ==
2881 09:26:17.308510 Write leveling (Byte 0): 32 => 32
2882 09:26:17.308562 Write leveling (Byte 1): 26 => 26
2883 09:26:17.308613 DramcWriteLeveling(PI) end<-----
2884 09:26:17.308664
2885 09:26:17.308715 ==
2886 09:26:17.308765 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 09:26:17.308816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 09:26:17.308868 ==
2889 09:26:17.308919 [Gating] SW mode calibration
2890 09:26:17.308969 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2891 09:26:17.309021 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2892 09:26:17.309073 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2893 09:26:17.309125 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2894 09:26:17.309175 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 09:26:17.309226 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 09:26:17.309315 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 09:26:17.309368 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 09:26:17.309418 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2899 09:26:17.309469 0 15 28 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 0)
2900 09:26:17.309520 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2901 09:26:17.309571 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 09:26:17.309622 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 09:26:17.309673 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 09:26:17.309724 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 09:26:17.309775 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 09:26:17.309826 1 0 24 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2907 09:26:17.309877 1 0 28 | B1->B0 | 2828 4444 | 0 1 | (1 1) (0 0)
2908 09:26:17.309929 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 09:26:17.309980 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 09:26:17.310031 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 09:26:17.310082 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 09:26:17.310138 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 09:26:17.310189 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 09:26:17.310241 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2915 09:26:17.310298 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2916 09:26:17.310351 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2917 09:26:17.310402 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 09:26:17.310454 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 09:26:17.310505 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 09:26:17.310556 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 09:26:17.310613 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 09:26:17.310666 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 09:26:17.310717 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 09:26:17.310769 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 09:26:17.310851 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 09:26:17.310933 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 09:26:17.311014 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 09:26:17.311094 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 09:26:17.311175 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 09:26:17.311238 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2931 09:26:17.311491 Total UI for P1: 0, mck2ui 16
2932 09:26:17.311620 best dqsien dly found for B0: ( 1, 3, 22)
2933 09:26:17.311745 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2934 09:26:17.311872 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 09:26:17.311999 Total UI for P1: 0, mck2ui 16
2936 09:26:17.312107 best dqsien dly found for B1: ( 1, 3, 28)
2937 09:26:17.312162 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2938 09:26:17.312214 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2939 09:26:17.312266
2940 09:26:17.312316 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2941 09:26:17.312368 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2942 09:26:17.312419 [Gating] SW calibration Done
2943 09:26:17.312470 ==
2944 09:26:17.312521 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 09:26:17.312572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 09:26:17.312628 ==
2947 09:26:17.312681 RX Vref Scan: 0
2948 09:26:17.312732
2949 09:26:17.312783 RX Vref 0 -> 0, step: 1
2950 09:26:17.312847
2951 09:26:17.312927 RX Delay -40 -> 252, step: 8
2952 09:26:17.313010 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2953 09:26:17.313093 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2954 09:26:17.313174 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2955 09:26:17.313265 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2956 09:26:17.313382 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2957 09:26:17.313466 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2958 09:26:17.313547 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2959 09:26:17.313632 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2960 09:26:17.313713 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2961 09:26:17.313783 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2962 09:26:17.313836 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2963 09:26:17.313888 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2964 09:26:17.313939 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2965 09:26:17.313995 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2966 09:26:17.314047 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2967 09:26:17.314099 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2968 09:26:17.314150 ==
2969 09:26:17.314210 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 09:26:17.314262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 09:26:17.314314 ==
2972 09:26:17.314372 DQS Delay:
2973 09:26:17.314453 DQS0 = 0, DQS1 = 0
2974 09:26:17.314533 DQM Delay:
2975 09:26:17.314618 DQM0 = 119, DQM1 = 107
2976 09:26:17.314698 DQ Delay:
2977 09:26:17.314783 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2978 09:26:17.314865 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2979 09:26:17.314924 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2980 09:26:17.314978 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2981 09:26:17.315029
2982 09:26:17.315080
2983 09:26:17.315139 ==
2984 09:26:17.315191 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 09:26:17.315243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 09:26:17.315296 ==
2987 09:26:17.315350
2988 09:26:17.315401
2989 09:26:17.315451 TX Vref Scan disable
2990 09:26:17.315532 == TX Byte 0 ==
2991 09:26:17.315613 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2992 09:26:17.315698 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2993 09:26:17.315779 == TX Byte 1 ==
2994 09:26:17.315862 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2995 09:26:17.315943 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2996 09:26:17.316024 ==
2997 09:26:17.316107 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 09:26:17.316188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 09:26:17.316269 ==
3000 09:26:17.316349 TX Vref=22, minBit 10, minWin=25, winSum=417
3001 09:26:17.316431 TX Vref=24, minBit 14, minWin=25, winSum=423
3002 09:26:17.508941 TX Vref=26, minBit 1, minWin=26, winSum=425
3003 09:26:17.509108 TX Vref=28, minBit 13, minWin=25, winSum=426
3004 09:26:17.509203 TX Vref=30, minBit 0, minWin=26, winSum=426
3005 09:26:17.509335 TX Vref=32, minBit 4, minWin=26, winSum=426
3006 09:26:17.509425 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
3007 09:26:17.509514
3008 09:26:17.509599 Final TX Range 1 Vref 30
3009 09:26:17.509685
3010 09:26:17.509769 ==
3011 09:26:17.509826 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 09:26:17.509883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 09:26:17.509938 ==
3014 09:26:17.509991
3015 09:26:17.510043
3016 09:26:17.510094 TX Vref Scan disable
3017 09:26:17.510146 == TX Byte 0 ==
3018 09:26:17.510198 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3019 09:26:17.510251 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3020 09:26:17.510303 == TX Byte 1 ==
3021 09:26:17.510355 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3022 09:26:17.510407 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3023 09:26:17.510458
3024 09:26:17.510508 [DATLAT]
3025 09:26:17.510559 Freq=1200, CH0 RK1
3026 09:26:17.510611
3027 09:26:17.510661 DATLAT Default: 0xd
3028 09:26:17.510712 0, 0xFFFF, sum = 0
3029 09:26:17.510765 1, 0xFFFF, sum = 0
3030 09:26:17.510818 2, 0xFFFF, sum = 0
3031 09:26:17.510871 3, 0xFFFF, sum = 0
3032 09:26:17.510923 4, 0xFFFF, sum = 0
3033 09:26:17.510975 5, 0xFFFF, sum = 0
3034 09:26:17.511028 6, 0xFFFF, sum = 0
3035 09:26:17.511080 7, 0xFFFF, sum = 0
3036 09:26:17.511133 8, 0xFFFF, sum = 0
3037 09:26:17.511185 9, 0xFFFF, sum = 0
3038 09:26:17.511237 10, 0xFFFF, sum = 0
3039 09:26:17.511290 11, 0xFFFF, sum = 0
3040 09:26:17.511341 12, 0x0, sum = 1
3041 09:26:17.511393 13, 0x0, sum = 2
3042 09:26:17.511445 14, 0x0, sum = 3
3043 09:26:17.511513 15, 0x0, sum = 4
3044 09:26:17.511579 best_step = 13
3045 09:26:17.511682
3046 09:26:17.511749 ==
3047 09:26:17.511801 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 09:26:17.511861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 09:26:17.511914 ==
3050 09:26:17.511965 RX Vref Scan: 0
3051 09:26:17.512020
3052 09:26:17.512073 RX Vref 0 -> 0, step: 1
3053 09:26:17.512124
3054 09:26:17.512175 RX Delay -21 -> 252, step: 4
3055 09:26:17.512254 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3056 09:26:17.512335 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3057 09:26:17.512416 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3058 09:26:17.512497 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3059 09:26:17.512577 iDelay=195, Bit 4, Center 122 (59 ~ 186) 128
3060 09:26:17.512659 iDelay=195, Bit 5, Center 112 (47 ~ 178) 132
3061 09:26:17.512739 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3062 09:26:17.512824 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
3063 09:26:17.512905 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3064 09:26:17.512986 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3065 09:26:17.513067 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3066 09:26:17.513164 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3067 09:26:17.513247 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3068 09:26:17.513325 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3069 09:26:17.513589 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3070 09:26:17.513721 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3071 09:26:17.513849 ==
3072 09:26:17.513983 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 09:26:17.514111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 09:26:17.514173 ==
3075 09:26:17.514227 DQS Delay:
3076 09:26:17.514280 DQS0 = 0, DQS1 = 0
3077 09:26:17.514332 DQM Delay:
3078 09:26:17.514383 DQM0 = 118, DQM1 = 107
3079 09:26:17.514435 DQ Delay:
3080 09:26:17.514486 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3081 09:26:17.514538 DQ4 =122, DQ5 =112, DQ6 =128, DQ7 =124
3082 09:26:17.514589 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =98
3083 09:26:17.514641 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
3084 09:26:17.514692
3085 09:26:17.514743
3086 09:26:17.514794 [DQSOSCAuto] RK1, (LSB)MR18= 0xfe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
3087 09:26:17.514846 CH0 RK1: MR19=403, MR18=FE
3088 09:26:17.514897 CH0_RK1: MR19=0x403, MR18=0xFE, DQSOSC=410, MR23=63, INC=39, DEC=26
3089 09:26:17.514949 [RxdqsGatingPostProcess] freq 1200
3090 09:26:17.515000 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3091 09:26:17.515051 best DQS0 dly(2T, 0.5T) = (0, 11)
3092 09:26:17.515103 best DQS1 dly(2T, 0.5T) = (0, 12)
3093 09:26:17.515154 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3094 09:26:17.515205 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3095 09:26:17.515256 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 09:26:17.515307 best DQS1 dly(2T, 0.5T) = (0, 11)
3097 09:26:17.515358 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 09:26:17.515409 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3099 09:26:17.515460 Pre-setting of DQS Precalculation
3100 09:26:17.515512 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3101 09:26:17.515564 ==
3102 09:26:17.515615 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 09:26:17.515667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 09:26:17.515718 ==
3105 09:26:17.515769 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3106 09:26:17.515821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3107 09:26:17.515874 [CA 0] Center 38 (8~68) winsize 61
3108 09:26:17.515925 [CA 1] Center 37 (7~68) winsize 62
3109 09:26:17.515977 [CA 2] Center 35 (6~65) winsize 60
3110 09:26:17.516028 [CA 3] Center 34 (4~64) winsize 61
3111 09:26:17.516079 [CA 4] Center 34 (4~64) winsize 61
3112 09:26:17.516130 [CA 5] Center 33 (3~64) winsize 62
3113 09:26:17.516181
3114 09:26:17.516232 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3115 09:26:17.516284
3116 09:26:17.516335 [CATrainingPosCal] consider 1 rank data
3117 09:26:17.516386 u2DelayCellTimex100 = 270/100 ps
3118 09:26:17.516438 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3119 09:26:17.516490 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3120 09:26:17.516541 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3121 09:26:17.516592 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 09:26:17.516644 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 09:26:17.516696 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3124 09:26:17.516747
3125 09:26:17.516798 CA PerBit enable=1, Macro0, CA PI delay=33
3126 09:26:17.516849
3127 09:26:17.516900 [CBTSetCACLKResult] CA Dly = 33
3128 09:26:17.516952 CS Dly: 5 (0~36)
3129 09:26:17.517004 ==
3130 09:26:17.517055 Dram Type= 6, Freq= 0, CH_1, rank 1
3131 09:26:17.517106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 09:26:17.517158 ==
3133 09:26:17.517210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 09:26:17.517287 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3135 09:26:17.517356 [CA 0] Center 38 (8~68) winsize 61
3136 09:26:17.517443 [CA 1] Center 38 (7~69) winsize 63
3137 09:26:17.517495 [CA 2] Center 35 (5~65) winsize 61
3138 09:26:17.517546 [CA 3] Center 33 (3~64) winsize 62
3139 09:26:17.517598 [CA 4] Center 34 (4~64) winsize 61
3140 09:26:17.517650 [CA 5] Center 33 (3~63) winsize 61
3141 09:26:17.517701
3142 09:26:17.517751 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3143 09:26:17.517803
3144 09:26:17.517854 [CATrainingPosCal] consider 2 rank data
3145 09:26:17.517906 u2DelayCellTimex100 = 270/100 ps
3146 09:26:17.517957 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3147 09:26:17.518009 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3148 09:26:17.518060 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3149 09:26:17.518112 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 09:26:17.518163 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 09:26:17.518214 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3152 09:26:17.518265
3153 09:26:17.518317 CA PerBit enable=1, Macro0, CA PI delay=33
3154 09:26:17.518368
3155 09:26:17.518419 [CBTSetCACLKResult] CA Dly = 33
3156 09:26:17.518471 CS Dly: 6 (0~38)
3157 09:26:17.518522
3158 09:26:17.518572 ----->DramcWriteLeveling(PI) begin...
3159 09:26:17.518625 ==
3160 09:26:17.518676 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 09:26:17.518728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 09:26:17.518780 ==
3163 09:26:17.518831 Write leveling (Byte 0): 24 => 24
3164 09:26:17.518883 Write leveling (Byte 1): 27 => 27
3165 09:26:17.518934 DramcWriteLeveling(PI) end<-----
3166 09:26:17.518985
3167 09:26:17.519036 ==
3168 09:26:17.519087 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 09:26:17.519138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 09:26:17.519190 ==
3171 09:26:17.519241 [Gating] SW mode calibration
3172 09:26:17.519292 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3173 09:26:17.519345 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3174 09:26:17.519397 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
3175 09:26:17.519449 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 09:26:17.519517 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 09:26:17.519600 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 09:26:17.519653 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 09:26:17.519719 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 09:26:17.519771 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
3181 09:26:17.519822 0 15 28 | B1->B0 | 2929 2525 | 1 0 | (1 1) (1 0)
3182 09:26:17.519888 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 09:26:17.519964 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 09:26:17.520040 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 09:26:17.520108 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 09:26:17.520160 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 09:26:17.520412 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 09:26:17.520542 1 0 24 | B1->B0 | 2626 3535 | 0 0 | (0 0) (0 0)
3189 09:26:17.520629 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
3190 09:26:17.520685 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 09:26:17.520737 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 09:26:17.520790 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 09:26:17.520842 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 09:26:17.520894 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 09:26:17.520946 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 09:26:17.520998 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3197 09:26:17.521050 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3198 09:26:17.521101 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 09:26:17.521153 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 09:26:17.521205 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 09:26:17.521280 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 09:26:17.521349 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 09:26:17.521401 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 09:26:17.521453 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 09:26:17.521509 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 09:26:17.521563 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 09:26:17.521615 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 09:26:17.521667 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 09:26:17.521718 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 09:26:17.521777 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 09:26:17.521829 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 09:26:17.521881 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3213 09:26:17.521933 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3214 09:26:17.521985 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 09:26:17.522036 Total UI for P1: 0, mck2ui 16
3216 09:26:17.522088 best dqsien dly found for B0: ( 1, 3, 26)
3217 09:26:17.522140 Total UI for P1: 0, mck2ui 16
3218 09:26:17.522192 best dqsien dly found for B1: ( 1, 3, 28)
3219 09:26:17.522244 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3220 09:26:17.522296 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3221 09:26:17.522348
3222 09:26:17.522399 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3223 09:26:17.522451 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3224 09:26:17.522502 [Gating] SW calibration Done
3225 09:26:17.522554 ==
3226 09:26:17.522610 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 09:26:17.522664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 09:26:17.522715 ==
3229 09:26:17.522767 RX Vref Scan: 0
3230 09:26:17.522818
3231 09:26:17.522870 RX Vref 0 -> 0, step: 1
3232 09:26:17.522920
3233 09:26:17.522972 RX Delay -40 -> 252, step: 8
3234 09:26:17.523024 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3235 09:26:17.523076 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3236 09:26:17.523128 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3237 09:26:17.523179 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3238 09:26:17.523231 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3239 09:26:17.523282 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3240 09:26:17.523334 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3241 09:26:17.523386 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3242 09:26:17.523437 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3243 09:26:17.523509 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3244 09:26:17.523562 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3245 09:26:17.523614 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3246 09:26:17.523666 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3247 09:26:17.523718 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3248 09:26:17.523770 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3249 09:26:17.523821 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3250 09:26:17.523873 ==
3251 09:26:17.523925 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 09:26:17.523977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 09:26:17.524028 ==
3254 09:26:17.524079 DQS Delay:
3255 09:26:17.524130 DQS0 = 0, DQS1 = 0
3256 09:26:17.524182 DQM Delay:
3257 09:26:17.524233 DQM0 = 116, DQM1 = 112
3258 09:26:17.524284 DQ Delay:
3259 09:26:17.524335 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =119
3260 09:26:17.524388 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3261 09:26:17.524439 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3262 09:26:17.524490 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3263 09:26:17.524542
3264 09:26:17.524593
3265 09:26:17.524644 ==
3266 09:26:17.524700 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 09:26:17.524753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 09:26:17.524805 ==
3269 09:26:17.524857
3270 09:26:17.524935
3271 09:26:17.525016 TX Vref Scan disable
3272 09:26:17.525098 == TX Byte 0 ==
3273 09:26:17.525180 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3274 09:26:17.525284 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3275 09:26:17.525354 == TX Byte 1 ==
3276 09:26:17.525406 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3277 09:26:17.525458 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3278 09:26:17.525510 ==
3279 09:26:17.525562 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 09:26:17.525614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 09:26:17.525667 ==
3282 09:26:17.525717 TX Vref=22, minBit 3, minWin=24, winSum=411
3283 09:26:17.525769 TX Vref=24, minBit 10, minWin=25, winSum=422
3284 09:26:17.525829 TX Vref=26, minBit 9, minWin=25, winSum=421
3285 09:26:17.525882 TX Vref=28, minBit 11, minWin=25, winSum=424
3286 09:26:17.525934 TX Vref=30, minBit 11, minWin=26, winSum=431
3287 09:26:17.525986 TX Vref=32, minBit 11, minWin=25, winSum=429
3288 09:26:17.526039 [TxChooseVref] Worse bit 11, Min win 26, Win sum 431, Final Vref 30
3289 09:26:17.526091
3290 09:26:17.526142 Final TX Range 1 Vref 30
3291 09:26:17.526193
3292 09:26:17.526245 ==
3293 09:26:17.526296 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 09:26:17.526348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 09:26:17.526400 ==
3296 09:26:17.526452
3297 09:26:17.526503
3298 09:26:17.526554 TX Vref Scan disable
3299 09:26:17.526637 == TX Byte 0 ==
3300 09:26:17.526688 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3301 09:26:17.526739 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3302 09:26:17.526791 == TX Byte 1 ==
3303 09:26:17.527034 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3304 09:26:17.527092 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3305 09:26:17.527165
3306 09:26:17.527219 [DATLAT]
3307 09:26:17.527271 Freq=1200, CH1 RK0
3308 09:26:17.527323
3309 09:26:17.527374 DATLAT Default: 0xd
3310 09:26:17.527426 0, 0xFFFF, sum = 0
3311 09:26:17.527478 1, 0xFFFF, sum = 0
3312 09:26:17.527531 2, 0xFFFF, sum = 0
3313 09:26:17.527584 3, 0xFFFF, sum = 0
3314 09:26:17.527636 4, 0xFFFF, sum = 0
3315 09:26:17.527689 5, 0xFFFF, sum = 0
3316 09:26:17.527742 6, 0xFFFF, sum = 0
3317 09:26:17.527794 7, 0xFFFF, sum = 0
3318 09:26:17.527845 8, 0xFFFF, sum = 0
3319 09:26:17.527897 9, 0xFFFF, sum = 0
3320 09:26:17.527950 10, 0xFFFF, sum = 0
3321 09:26:17.528002 11, 0xFFFF, sum = 0
3322 09:26:17.528054 12, 0x0, sum = 1
3323 09:26:17.528106 13, 0x0, sum = 2
3324 09:26:17.528159 14, 0x0, sum = 3
3325 09:26:17.528211 15, 0x0, sum = 4
3326 09:26:17.528263 best_step = 13
3327 09:26:17.528314
3328 09:26:17.528365 ==
3329 09:26:17.528417 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 09:26:17.528468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 09:26:17.528520 ==
3332 09:26:17.528571 RX Vref Scan: 1
3333 09:26:17.528623
3334 09:26:17.528673 Set Vref Range= 32 -> 127
3335 09:26:17.528724
3336 09:26:17.528775 RX Vref 32 -> 127, step: 1
3337 09:26:17.528827
3338 09:26:17.528878 RX Delay -13 -> 252, step: 4
3339 09:26:17.528930
3340 09:26:17.528981 Set Vref, RX VrefLevel [Byte0]: 32
3341 09:26:17.529032 [Byte1]: 32
3342 09:26:17.529083
3343 09:26:17.529134 Set Vref, RX VrefLevel [Byte0]: 33
3344 09:26:17.529186 [Byte1]: 33
3345 09:26:17.529237
3346 09:26:17.529327 Set Vref, RX VrefLevel [Byte0]: 34
3347 09:26:17.529379 [Byte1]: 34
3348 09:26:17.529430
3349 09:26:17.529482 Set Vref, RX VrefLevel [Byte0]: 35
3350 09:26:17.529534 [Byte1]: 35
3351 09:26:17.529585
3352 09:26:17.529636 Set Vref, RX VrefLevel [Byte0]: 36
3353 09:26:17.529688 [Byte1]: 36
3354 09:26:17.529739
3355 09:26:17.529790 Set Vref, RX VrefLevel [Byte0]: 37
3356 09:26:17.529841 [Byte1]: 37
3357 09:26:17.529893
3358 09:26:17.529944 Set Vref, RX VrefLevel [Byte0]: 38
3359 09:26:17.529996 [Byte1]: 38
3360 09:26:17.530047
3361 09:26:17.530098 Set Vref, RX VrefLevel [Byte0]: 39
3362 09:26:17.530150 [Byte1]: 39
3363 09:26:17.530201
3364 09:26:17.530272 Set Vref, RX VrefLevel [Byte0]: 40
3365 09:26:17.530325 [Byte1]: 40
3366 09:26:17.530377
3367 09:26:17.530429 Set Vref, RX VrefLevel [Byte0]: 41
3368 09:26:17.530480 [Byte1]: 41
3369 09:26:17.530530
3370 09:26:17.530581 Set Vref, RX VrefLevel [Byte0]: 42
3371 09:26:17.530632 [Byte1]: 42
3372 09:26:17.530684
3373 09:26:17.530734 Set Vref, RX VrefLevel [Byte0]: 43
3374 09:26:17.530785 [Byte1]: 43
3375 09:26:17.530836
3376 09:26:17.530887 Set Vref, RX VrefLevel [Byte0]: 44
3377 09:26:17.530938 [Byte1]: 44
3378 09:26:17.530989
3379 09:26:17.531040 Set Vref, RX VrefLevel [Byte0]: 45
3380 09:26:17.531091 [Byte1]: 45
3381 09:26:17.531142
3382 09:26:17.531192 Set Vref, RX VrefLevel [Byte0]: 46
3383 09:26:17.531243 [Byte1]: 46
3384 09:26:17.531294
3385 09:26:17.531345 Set Vref, RX VrefLevel [Byte0]: 47
3386 09:26:17.531430 [Byte1]: 47
3387 09:26:17.531481
3388 09:26:17.531532 Set Vref, RX VrefLevel [Byte0]: 48
3389 09:26:17.531583 [Byte1]: 48
3390 09:26:17.531633
3391 09:26:17.531684 Set Vref, RX VrefLevel [Byte0]: 49
3392 09:26:17.531735 [Byte1]: 49
3393 09:26:17.531785
3394 09:26:17.531836 Set Vref, RX VrefLevel [Byte0]: 50
3395 09:26:17.531887 [Byte1]: 50
3396 09:26:17.531938
3397 09:26:17.531989 Set Vref, RX VrefLevel [Byte0]: 51
3398 09:26:17.532040 [Byte1]: 51
3399 09:26:17.532090
3400 09:26:17.532140 Set Vref, RX VrefLevel [Byte0]: 52
3401 09:26:17.532191 [Byte1]: 52
3402 09:26:17.532242
3403 09:26:17.532292 Set Vref, RX VrefLevel [Byte0]: 53
3404 09:26:17.532344 [Byte1]: 53
3405 09:26:17.532395
3406 09:26:17.532445 Set Vref, RX VrefLevel [Byte0]: 54
3407 09:26:17.532495 [Byte1]: 54
3408 09:26:17.532546
3409 09:26:17.532596 Set Vref, RX VrefLevel [Byte0]: 55
3410 09:26:17.532647 [Byte1]: 55
3411 09:26:17.532697
3412 09:26:17.532747 Set Vref, RX VrefLevel [Byte0]: 56
3413 09:26:17.532798 [Byte1]: 56
3414 09:26:17.532849
3415 09:26:17.532900 Set Vref, RX VrefLevel [Byte0]: 57
3416 09:26:17.532950 [Byte1]: 57
3417 09:26:17.533001
3418 09:26:17.533051 Set Vref, RX VrefLevel [Byte0]: 58
3419 09:26:17.533102 [Byte1]: 58
3420 09:26:17.533152
3421 09:26:17.533203 Set Vref, RX VrefLevel [Byte0]: 59
3422 09:26:17.533253 [Byte1]: 59
3423 09:26:17.533343
3424 09:26:17.533394 Set Vref, RX VrefLevel [Byte0]: 60
3425 09:26:17.533445 [Byte1]: 60
3426 09:26:17.533496
3427 09:26:17.533547 Set Vref, RX VrefLevel [Byte0]: 61
3428 09:26:17.533598 [Byte1]: 61
3429 09:26:17.533651
3430 09:26:17.533716 Set Vref, RX VrefLevel [Byte0]: 62
3431 09:26:17.533768 [Byte1]: 62
3432 09:26:17.533819
3433 09:26:17.533870 Set Vref, RX VrefLevel [Byte0]: 63
3434 09:26:17.533921 [Byte1]: 63
3435 09:26:17.533972
3436 09:26:17.534022 Set Vref, RX VrefLevel [Byte0]: 64
3437 09:26:17.534073 [Byte1]: 64
3438 09:26:17.534124
3439 09:26:17.534174 Set Vref, RX VrefLevel [Byte0]: 65
3440 09:26:17.534225 [Byte1]: 65
3441 09:26:17.534276
3442 09:26:17.534327 Final RX Vref Byte 0 = 52 to rank0
3443 09:26:17.534378 Final RX Vref Byte 1 = 49 to rank0
3444 09:26:17.534430 Final RX Vref Byte 0 = 52 to rank1
3445 09:26:17.534481 Final RX Vref Byte 1 = 49 to rank1==
3446 09:26:17.534533 Dram Type= 6, Freq= 0, CH_1, rank 0
3447 09:26:17.534585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 09:26:17.534642 ==
3449 09:26:17.534694 DQS Delay:
3450 09:26:17.534745 DQS0 = 0, DQS1 = 0
3451 09:26:17.534796 DQM Delay:
3452 09:26:17.534855 DQM0 = 114, DQM1 = 112
3453 09:26:17.534906 DQ Delay:
3454 09:26:17.534957 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3455 09:26:17.535016 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3456 09:26:17.535070 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3457 09:26:17.535122 DQ12 =120, DQ13 =120, DQ14 =116, DQ15 =122
3458 09:26:17.535173
3459 09:26:17.535225
3460 09:26:17.535277 [DQSOSCAuto] RK0, (LSB)MR18= 0xf906, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 412 ps
3461 09:26:17.535330 CH1 RK0: MR19=304, MR18=F906
3462 09:26:17.535479 CH1_RK0: MR19=0x304, MR18=0xF906, DQSOSC=407, MR23=63, INC=39, DEC=26
3463 09:26:17.535547
3464 09:26:17.535600 ----->DramcWriteLeveling(PI) begin...
3465 09:26:17.535654 ==
3466 09:26:17.535705 Dram Type= 6, Freq= 0, CH_1, rank 1
3467 09:26:17.535756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 09:26:17.535810 ==
3469 09:26:17.536059 Write leveling (Byte 0): 27 => 27
3470 09:26:17.536147 Write leveling (Byte 1): 27 => 27
3471 09:26:17.536229 DramcWriteLeveling(PI) end<-----
3472 09:26:17.536309
3473 09:26:17.536368 ==
3474 09:26:17.536420 Dram Type= 6, Freq= 0, CH_1, rank 1
3475 09:26:17.536472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3476 09:26:17.536527 ==
3477 09:26:17.536579 [Gating] SW mode calibration
3478 09:26:17.536630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3479 09:26:17.536682 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3480 09:26:17.536734 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3481 09:26:17.536786 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 09:26:17.536853 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 09:26:17.536908 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 09:26:17.536959 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 09:26:17.537012 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3486 09:26:17.537063 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
3487 09:26:17.537114 0 15 28 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
3488 09:26:17.537165 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 09:26:17.537216 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 09:26:17.537297 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 09:26:17.537393 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 09:26:17.537474 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 09:26:17.537560 1 0 20 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
3494 09:26:17.537633 1 0 24 | B1->B0 | 2727 4646 | 1 0 | (0 0) (0 0)
3495 09:26:17.537707 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3496 09:26:17.537761 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 09:26:17.537812 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 09:26:17.537864 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 09:26:17.537915 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 09:26:17.537966 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 09:26:17.538017 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 09:26:17.538068 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3503 09:26:17.538120 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3504 09:26:17.538171 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 09:26:17.538223 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 09:26:17.538274 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 09:26:17.538325 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 09:26:17.538377 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 09:26:17.538428 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 09:26:17.538479 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 09:26:17.538530 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 09:26:17.538581 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 09:26:17.538632 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 09:26:17.538683 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 09:26:17.538734 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 09:26:17.538785 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 09:26:17.538836 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 09:26:17.538888 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3519 09:26:17.538940 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3520 09:26:17.538991 Total UI for P1: 0, mck2ui 16
3521 09:26:17.539042 best dqsien dly found for B0: ( 1, 3, 24)
3522 09:26:17.539093 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3523 09:26:17.539145 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 09:26:17.539195 Total UI for P1: 0, mck2ui 16
3525 09:26:17.539247 best dqsien dly found for B1: ( 1, 3, 28)
3526 09:26:17.539297 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3527 09:26:17.539349 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3528 09:26:17.539399
3529 09:26:17.539450 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3530 09:26:17.539500 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3531 09:26:17.539551 [Gating] SW calibration Done
3532 09:26:17.539602 ==
3533 09:26:17.539653 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 09:26:17.539704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 09:26:17.539759 ==
3536 09:26:17.539822 RX Vref Scan: 0
3537 09:26:17.539875
3538 09:26:17.539925 RX Vref 0 -> 0, step: 1
3539 09:26:17.539976
3540 09:26:17.540026 RX Delay -40 -> 252, step: 8
3541 09:26:17.540078 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3542 09:26:17.540129 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3543 09:26:17.540179 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3544 09:26:17.540230 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3545 09:26:17.540282 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3546 09:26:17.540332 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3547 09:26:17.540383 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3548 09:26:17.540434 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3549 09:26:17.540485 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3550 09:26:17.540536 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3551 09:26:17.540586 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3552 09:26:17.540637 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3553 09:26:17.540688 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3554 09:26:17.540739 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3555 09:26:17.540789 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3556 09:26:17.540841 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3557 09:26:17.540892 ==
3558 09:26:17.540943 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 09:26:17.540994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 09:26:17.541045 ==
3561 09:26:17.541096 DQS Delay:
3562 09:26:17.541147 DQS0 = 0, DQS1 = 0
3563 09:26:17.541198 DQM Delay:
3564 09:26:17.541248 DQM0 = 114, DQM1 = 111
3565 09:26:17.541341 DQ Delay:
3566 09:26:17.541393 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3567 09:26:17.541444 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3568 09:26:17.541494 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3569 09:26:17.541545 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3570 09:26:17.541596
3571 09:26:17.541646
3572 09:26:17.541891 ==
3573 09:26:17.541947 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 09:26:17.542000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 09:26:17.542052 ==
3576 09:26:17.542102
3577 09:26:17.542153
3578 09:26:17.542203 TX Vref Scan disable
3579 09:26:17.542254 == TX Byte 0 ==
3580 09:26:17.542305 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3581 09:26:17.542356 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3582 09:26:17.542407 == TX Byte 1 ==
3583 09:26:17.542458 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3584 09:26:17.542508 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3585 09:26:17.542559 ==
3586 09:26:17.542610 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 09:26:17.542661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 09:26:17.542712 ==
3589 09:26:17.542763 TX Vref=22, minBit 0, minWin=26, winSum=423
3590 09:26:17.542814 TX Vref=24, minBit 0, minWin=26, winSum=425
3591 09:26:17.542866 TX Vref=26, minBit 0, minWin=26, winSum=427
3592 09:26:17.542917 TX Vref=28, minBit 9, minWin=26, winSum=432
3593 09:26:17.542969 TX Vref=30, minBit 1, minWin=26, winSum=432
3594 09:26:17.543020 TX Vref=32, minBit 9, minWin=25, winSum=426
3595 09:26:17.543071 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 28
3596 09:26:17.543122
3597 09:26:17.543173 Final TX Range 1 Vref 28
3598 09:26:17.543225
3599 09:26:17.543275 ==
3600 09:26:17.543326 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 09:26:17.543376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 09:26:17.543440 ==
3603 09:26:17.543494
3604 09:26:17.543545
3605 09:26:17.543596 TX Vref Scan disable
3606 09:26:17.543647 == TX Byte 0 ==
3607 09:26:17.543698 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3608 09:26:17.543749 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3609 09:26:17.543800 == TX Byte 1 ==
3610 09:26:17.543863 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3611 09:26:17.543917 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3612 09:26:17.543968
3613 09:26:17.544027 [DATLAT]
3614 09:26:17.544079 Freq=1200, CH1 RK1
3615 09:26:17.544130
3616 09:26:17.544187 DATLAT Default: 0xd
3617 09:26:17.544240 0, 0xFFFF, sum = 0
3618 09:26:17.544292 1, 0xFFFF, sum = 0
3619 09:26:17.544345 2, 0xFFFF, sum = 0
3620 09:26:17.544410 3, 0xFFFF, sum = 0
3621 09:26:17.544472 4, 0xFFFF, sum = 0
3622 09:26:17.544528 5, 0xFFFF, sum = 0
3623 09:26:17.544586 6, 0xFFFF, sum = 0
3624 09:26:17.544663 7, 0xFFFF, sum = 0
3625 09:26:17.544745 8, 0xFFFF, sum = 0
3626 09:26:17.544831 9, 0xFFFF, sum = 0
3627 09:26:17.544918 10, 0xFFFF, sum = 0
3628 09:26:17.545003 11, 0xFFFF, sum = 0
3629 09:26:17.545090 12, 0x0, sum = 1
3630 09:26:17.545174 13, 0x0, sum = 2
3631 09:26:17.545264 14, 0x0, sum = 3
3632 09:26:17.545386 15, 0x0, sum = 4
3633 09:26:17.545475 best_step = 13
3634 09:26:17.545560
3635 09:26:17.545641 ==
3636 09:26:17.545725 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 09:26:17.545811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 09:26:17.545892 ==
3639 09:26:17.545972 RX Vref Scan: 0
3640 09:26:17.546052
3641 09:26:17.546135 RX Vref 0 -> 0, step: 1
3642 09:26:17.546216
3643 09:26:17.546298 RX Delay -13 -> 252, step: 4
3644 09:26:17.546382 iDelay=191, Bit 0, Center 116 (47 ~ 186) 140
3645 09:26:17.546463 iDelay=191, Bit 1, Center 112 (43 ~ 182) 140
3646 09:26:17.546543 iDelay=191, Bit 2, Center 108 (43 ~ 174) 132
3647 09:26:17.546624 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3648 09:26:17.546705 iDelay=191, Bit 4, Center 116 (47 ~ 186) 140
3649 09:26:17.546786 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3650 09:26:17.546866 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3651 09:26:17.546943 iDelay=191, Bit 7, Center 114 (47 ~ 182) 136
3652 09:26:17.546996 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3653 09:26:17.547048 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3654 09:26:17.547099 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3655 09:26:17.547150 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3656 09:26:17.547201 iDelay=191, Bit 12, Center 120 (59 ~ 182) 124
3657 09:26:17.547252 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3658 09:26:17.547303 iDelay=191, Bit 14, Center 116 (55 ~ 178) 124
3659 09:26:17.547355 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3660 09:26:17.547406 ==
3661 09:26:17.547457 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 09:26:17.547509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 09:26:17.547560 ==
3664 09:26:17.547611 DQS Delay:
3665 09:26:17.547662 DQS0 = 0, DQS1 = 0
3666 09:26:17.547713 DQM Delay:
3667 09:26:17.547764 DQM0 = 115, DQM1 = 112
3668 09:26:17.547815 DQ Delay:
3669 09:26:17.547865 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =112
3670 09:26:17.547917 DQ4 =116, DQ5 =122, DQ6 =122, DQ7 =114
3671 09:26:17.547968 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3672 09:26:17.548050 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3673 09:26:17.548133
3674 09:26:17.548212
3675 09:26:17.548299 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0e, (MSB)MR19= 0x304, tDQSOscB0 = 404 ps tDQSOscB1 = 412 ps
3676 09:26:17.548357 CH1 RK1: MR19=304, MR18=FB0E
3677 09:26:17.548419 CH1_RK1: MR19=0x304, MR18=0xFB0E, DQSOSC=404, MR23=63, INC=40, DEC=26
3678 09:26:17.548507 [RxdqsGatingPostProcess] freq 1200
3679 09:26:17.548593 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3680 09:26:17.548679 best DQS0 dly(2T, 0.5T) = (0, 11)
3681 09:26:17.548761 best DQS1 dly(2T, 0.5T) = (0, 11)
3682 09:26:17.548842 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3683 09:26:17.548922 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3684 09:26:17.549003 best DQS0 dly(2T, 0.5T) = (0, 11)
3685 09:26:17.549085 best DQS1 dly(2T, 0.5T) = (0, 11)
3686 09:26:17.549168 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3687 09:26:17.549253 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3688 09:26:17.549353 Pre-setting of DQS Precalculation
3689 09:26:17.549435 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3690 09:26:17.549519 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3691 09:26:17.549586 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3692 09:26:17.549648
3693 09:26:17.549728
3694 09:26:17.549815 [Calibration Summary] 2400 Mbps
3695 09:26:17.549896 CH 0, Rank 0
3696 09:26:17.549982 SW Impedance : PASS
3697 09:26:17.550064 DUTY Scan : NO K
3698 09:26:17.550152 ZQ Calibration : PASS
3699 09:26:17.550236 Jitter Meter : NO K
3700 09:26:17.550316 CBT Training : PASS
3701 09:26:17.550397 Write leveling : PASS
3702 09:26:17.550477 RX DQS gating : PASS
3703 09:26:17.550557 RX DQ/DQS(RDDQC) : PASS
3704 09:26:17.550637 TX DQ/DQS : PASS
3705 09:26:17.550718 RX DATLAT : PASS
3706 09:26:17.550803 RX DQ/DQS(Engine): PASS
3707 09:26:17.550890 TX OE : NO K
3708 09:26:17.550974 All Pass.
3709 09:26:17.551054
3710 09:26:17.551140 CH 0, Rank 1
3711 09:26:17.551220 SW Impedance : PASS
3712 09:26:17.551306 DUTY Scan : NO K
3713 09:26:17.551584 ZQ Calibration : PASS
3714 09:26:17.551670 Jitter Meter : NO K
3715 09:26:17.551752 CBT Training : PASS
3716 09:26:17.551833 Write leveling : PASS
3717 09:26:17.551913 RX DQS gating : PASS
3718 09:26:17.551994 RX DQ/DQS(RDDQC) : PASS
3719 09:26:17.552074 TX DQ/DQS : PASS
3720 09:26:17.552155 RX DATLAT : PASS
3721 09:26:17.552236 RX DQ/DQS(Engine): PASS
3722 09:26:17.552316 TX OE : NO K
3723 09:26:17.552397 All Pass.
3724 09:26:17.552476
3725 09:26:17.552556 CH 1, Rank 0
3726 09:26:17.552636 SW Impedance : PASS
3727 09:26:17.552716 DUTY Scan : NO K
3728 09:26:17.552796 ZQ Calibration : PASS
3729 09:26:17.552876 Jitter Meter : NO K
3730 09:26:17.552956 CBT Training : PASS
3731 09:26:17.553036 Write leveling : PASS
3732 09:26:17.553125 RX DQS gating : PASS
3733 09:26:17.553206 RX DQ/DQS(RDDQC) : PASS
3734 09:26:17.553288 TX DQ/DQS : PASS
3735 09:26:17.553342 RX DATLAT : PASS
3736 09:26:17.553394 RX DQ/DQS(Engine): PASS
3737 09:26:17.553446 TX OE : NO K
3738 09:26:17.553497 All Pass.
3739 09:26:17.553549
3740 09:26:17.553599 CH 1, Rank 1
3741 09:26:17.553650 SW Impedance : PASS
3742 09:26:17.553701 DUTY Scan : NO K
3743 09:26:17.553752 ZQ Calibration : PASS
3744 09:26:17.553803 Jitter Meter : NO K
3745 09:26:17.553854 CBT Training : PASS
3746 09:26:17.553905 Write leveling : PASS
3747 09:26:17.553956 RX DQS gating : PASS
3748 09:26:17.554007 RX DQ/DQS(RDDQC) : PASS
3749 09:26:17.554058 TX DQ/DQS : PASS
3750 09:26:17.554109 RX DATLAT : PASS
3751 09:26:17.554160 RX DQ/DQS(Engine): PASS
3752 09:26:17.554210 TX OE : NO K
3753 09:26:17.554261 All Pass.
3754 09:26:17.554313
3755 09:26:17.554363 DramC Write-DBI off
3756 09:26:17.554414 PER_BANK_REFRESH: Hybrid Mode
3757 09:26:17.554465 TX_TRACKING: ON
3758 09:26:17.554517 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3759 09:26:17.554569 [FAST_K] Save calibration result to emmc
3760 09:26:17.554620 dramc_set_vcore_voltage set vcore to 650000
3761 09:26:17.554672 Read voltage for 600, 5
3762 09:26:17.554722 Vio18 = 0
3763 09:26:17.554773 Vcore = 650000
3764 09:26:17.554825 Vdram = 0
3765 09:26:17.554877 Vddq = 0
3766 09:26:17.554927 Vmddr = 0
3767 09:26:17.554978 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3768 09:26:17.555042 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3769 09:26:17.555096 MEM_TYPE=3, freq_sel=19
3770 09:26:17.555147 sv_algorithm_assistance_LP4_1600
3771 09:26:17.555199 ============ PULL DRAM RESETB DOWN ============
3772 09:26:17.555261 ========== PULL DRAM RESETB DOWN end =========
3773 09:26:17.555314 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3774 09:26:17.555366 ===================================
3775 09:26:17.555423 LPDDR4 DRAM CONFIGURATION
3776 09:26:17.555492 ===================================
3777 09:26:17.555557 EX_ROW_EN[0] = 0x0
3778 09:26:17.555608 EX_ROW_EN[1] = 0x0
3779 09:26:17.555658 LP4Y_EN = 0x0
3780 09:26:17.555709 WORK_FSP = 0x0
3781 09:26:17.555760 WL = 0x2
3782 09:26:17.555811 RL = 0x2
3783 09:26:17.555861 BL = 0x2
3784 09:26:17.555912 RPST = 0x0
3785 09:26:17.555962 RD_PRE = 0x0
3786 09:26:17.556013 WR_PRE = 0x1
3787 09:26:17.556063 WR_PST = 0x0
3788 09:26:17.556114 DBI_WR = 0x0
3789 09:26:17.556165 DBI_RD = 0x0
3790 09:26:17.556216 OTF = 0x1
3791 09:26:17.556268 ===================================
3792 09:26:17.556319 ===================================
3793 09:26:17.556370 ANA top config
3794 09:26:17.556421 ===================================
3795 09:26:17.556472 DLL_ASYNC_EN = 0
3796 09:26:17.556523 ALL_SLAVE_EN = 1
3797 09:26:17.556574 NEW_RANK_MODE = 1
3798 09:26:17.556625 DLL_IDLE_MODE = 1
3799 09:26:17.556677 LP45_APHY_COMB_EN = 1
3800 09:26:17.556727 TX_ODT_DIS = 1
3801 09:26:17.556778 NEW_8X_MODE = 1
3802 09:26:17.556837 ===================================
3803 09:26:17.556897 ===================================
3804 09:26:17.556949 data_rate = 1200
3805 09:26:17.557001 CKR = 1
3806 09:26:17.557052 DQ_P2S_RATIO = 8
3807 09:26:17.557103 ===================================
3808 09:26:17.557153 CA_P2S_RATIO = 8
3809 09:26:17.557204 DQ_CA_OPEN = 0
3810 09:26:17.557255 DQ_SEMI_OPEN = 0
3811 09:26:17.557318 CA_SEMI_OPEN = 0
3812 09:26:17.557369 CA_FULL_RATE = 0
3813 09:26:17.557420 DQ_CKDIV4_EN = 1
3814 09:26:17.557471 CA_CKDIV4_EN = 1
3815 09:26:17.557522 CA_PREDIV_EN = 0
3816 09:26:17.557573 PH8_DLY = 0
3817 09:26:17.557624 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3818 09:26:17.557675 DQ_AAMCK_DIV = 4
3819 09:26:17.557725 CA_AAMCK_DIV = 4
3820 09:26:17.557776 CA_ADMCK_DIV = 4
3821 09:26:17.557827 DQ_TRACK_CA_EN = 0
3822 09:26:17.557878 CA_PICK = 600
3823 09:26:17.557929 CA_MCKIO = 600
3824 09:26:17.557980 MCKIO_SEMI = 0
3825 09:26:17.558031 PLL_FREQ = 2288
3826 09:26:17.558081 DQ_UI_PI_RATIO = 32
3827 09:26:17.558132 CA_UI_PI_RATIO = 0
3828 09:26:17.558183 ===================================
3829 09:26:17.558234 ===================================
3830 09:26:17.558285 memory_type:LPDDR4
3831 09:26:17.558336 GP_NUM : 10
3832 09:26:17.558387 SRAM_EN : 1
3833 09:26:17.558438 MD32_EN : 0
3834 09:26:17.558488 ===================================
3835 09:26:17.558539 [ANA_INIT] >>>>>>>>>>>>>>
3836 09:26:17.558590 <<<<<< [CONFIGURE PHASE]: ANA_TX
3837 09:26:17.558641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3838 09:26:17.558691 ===================================
3839 09:26:17.558742 data_rate = 1200,PCW = 0X5800
3840 09:26:17.558793 ===================================
3841 09:26:17.558844 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3842 09:26:17.558895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3843 09:26:17.558947 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3844 09:26:17.558999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3845 09:26:17.559051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3846 09:26:17.559101 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3847 09:26:17.559152 [ANA_INIT] flow start
3848 09:26:17.559203 [ANA_INIT] PLL >>>>>>>>
3849 09:26:17.559254 [ANA_INIT] PLL <<<<<<<<
3850 09:26:17.559305 [ANA_INIT] MIDPI >>>>>>>>
3851 09:26:17.559355 [ANA_INIT] MIDPI <<<<<<<<
3852 09:26:17.559406 [ANA_INIT] DLL >>>>>>>>
3853 09:26:17.559456 [ANA_INIT] flow end
3854 09:26:17.559695 ============ LP4 DIFF to SE enter ============
3855 09:26:17.559765 ============ LP4 DIFF to SE exit ============
3856 09:26:17.559821 [ANA_INIT] <<<<<<<<<<<<<
3857 09:26:17.559873 [Flow] Enable top DCM control >>>>>
3858 09:26:17.559925 [Flow] Enable top DCM control <<<<<
3859 09:26:17.559977 Enable DLL master slave shuffle
3860 09:26:17.560029 ==============================================================
3861 09:26:17.560081 Gating Mode config
3862 09:26:17.560132 ==============================================================
3863 09:26:17.560184 Config description:
3864 09:26:17.560235 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3865 09:26:17.560288 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3866 09:26:17.560340 SELPH_MODE 0: By rank 1: By Phase
3867 09:26:17.560391 ==============================================================
3868 09:26:17.560443 GAT_TRACK_EN = 1
3869 09:26:17.560500 RX_GATING_MODE = 2
3870 09:26:17.560554 RX_GATING_TRACK_MODE = 2
3871 09:26:17.560605 SELPH_MODE = 1
3872 09:26:17.560656 PICG_EARLY_EN = 1
3873 09:26:17.560708 VALID_LAT_VALUE = 1
3874 09:26:17.560759 ==============================================================
3875 09:26:17.560811 Enter into Gating configuration >>>>
3876 09:26:17.560863 Exit from Gating configuration <<<<
3877 09:26:17.560914 Enter into DVFS_PRE_config >>>>>
3878 09:26:17.560966 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3879 09:26:17.561019 Exit from DVFS_PRE_config <<<<<
3880 09:26:17.561071 Enter into PICG configuration >>>>
3881 09:26:17.561122 Exit from PICG configuration <<<<
3882 09:26:17.561173 [RX_INPUT] configuration >>>>>
3883 09:26:17.561224 [RX_INPUT] configuration <<<<<
3884 09:26:17.561283 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3885 09:26:17.561349 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3886 09:26:17.566158 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3887 09:26:17.573112 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3888 09:26:17.579717 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3889 09:26:17.585896 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3890 09:26:17.589606 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3891 09:26:17.592534 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3892 09:26:17.596317 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3893 09:26:17.602574 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3894 09:26:17.605594 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3895 09:26:17.609177 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3896 09:26:17.612324 ===================================
3897 09:26:17.615787 LPDDR4 DRAM CONFIGURATION
3898 09:26:17.618821 ===================================
3899 09:26:17.618902 EX_ROW_EN[0] = 0x0
3900 09:26:17.622448 EX_ROW_EN[1] = 0x0
3901 09:26:17.625469 LP4Y_EN = 0x0
3902 09:26:17.625549 WORK_FSP = 0x0
3903 09:26:17.629077 WL = 0x2
3904 09:26:17.629158 RL = 0x2
3905 09:26:17.632309 BL = 0x2
3906 09:26:17.632390 RPST = 0x0
3907 09:26:17.635310 RD_PRE = 0x0
3908 09:26:17.635390 WR_PRE = 0x1
3909 09:26:17.638272 WR_PST = 0x0
3910 09:26:17.638353 DBI_WR = 0x0
3911 09:26:17.641705 DBI_RD = 0x0
3912 09:26:17.641786 OTF = 0x1
3913 09:26:17.645189 ===================================
3914 09:26:17.651774 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3915 09:26:17.654769 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3916 09:26:17.658549 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3917 09:26:17.661570 ===================================
3918 09:26:17.664409 LPDDR4 DRAM CONFIGURATION
3919 09:26:17.667853 ===================================
3920 09:26:17.671416 EX_ROW_EN[0] = 0x10
3921 09:26:17.671491 EX_ROW_EN[1] = 0x0
3922 09:26:17.674446 LP4Y_EN = 0x0
3923 09:26:17.674515 WORK_FSP = 0x0
3924 09:26:17.677875 WL = 0x2
3925 09:26:17.677953 RL = 0x2
3926 09:26:17.680997 BL = 0x2
3927 09:26:17.681069 RPST = 0x0
3928 09:26:17.684813 RD_PRE = 0x0
3929 09:26:17.684884 WR_PRE = 0x1
3930 09:26:17.687699 WR_PST = 0x0
3931 09:26:17.687775 DBI_WR = 0x0
3932 09:26:17.691331 DBI_RD = 0x0
3933 09:26:17.691400 OTF = 0x1
3934 09:26:17.694421 ===================================
3935 09:26:17.701205 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3936 09:26:17.706057 nWR fixed to 30
3937 09:26:17.709088 [ModeRegInit_LP4] CH0 RK0
3938 09:26:17.709169 [ModeRegInit_LP4] CH0 RK1
3939 09:26:17.712744 [ModeRegInit_LP4] CH1 RK0
3940 09:26:17.716198 [ModeRegInit_LP4] CH1 RK1
3941 09:26:17.716279 match AC timing 17
3942 09:26:17.722308 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3943 09:26:17.725726 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3944 09:26:17.729345 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3945 09:26:17.735496 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3946 09:26:17.739362 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3947 09:26:17.739444 ==
3948 09:26:17.742384 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 09:26:17.745278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3950 09:26:17.745387 ==
3951 09:26:17.752265 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3952 09:26:17.758968 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3953 09:26:17.762050 [CA 0] Center 36 (6~67) winsize 62
3954 09:26:17.765112 [CA 1] Center 36 (6~67) winsize 62
3955 09:26:17.768716 [CA 2] Center 34 (4~65) winsize 62
3956 09:26:17.771836 [CA 3] Center 34 (4~65) winsize 62
3957 09:26:17.775610 [CA 4] Center 33 (3~64) winsize 62
3958 09:26:17.778581 [CA 5] Center 33 (3~64) winsize 62
3959 09:26:17.778663
3960 09:26:17.781717 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3961 09:26:17.781799
3962 09:26:17.785313 [CATrainingPosCal] consider 1 rank data
3963 09:26:17.788833 u2DelayCellTimex100 = 270/100 ps
3964 09:26:17.791679 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3965 09:26:17.794953 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3966 09:26:17.798292 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3967 09:26:17.802023 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3968 09:26:17.808032 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3969 09:26:17.811628 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3970 09:26:17.811704
3971 09:26:17.814692 CA PerBit enable=1, Macro0, CA PI delay=33
3972 09:26:17.814762
3973 09:26:17.818412 [CBTSetCACLKResult] CA Dly = 33
3974 09:26:17.818480 CS Dly: 4 (0~35)
3975 09:26:17.818542 ==
3976 09:26:17.821414 Dram Type= 6, Freq= 0, CH_0, rank 1
3977 09:26:17.828168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 09:26:17.828348 ==
3979 09:26:17.831685 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3980 09:26:17.837791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3981 09:26:17.841393 [CA 0] Center 36 (6~67) winsize 62
3982 09:26:17.844329 [CA 1] Center 36 (6~67) winsize 62
3983 09:26:17.848125 [CA 2] Center 34 (4~65) winsize 62
3984 09:26:17.851036 [CA 3] Center 34 (3~65) winsize 63
3985 09:26:17.854300 [CA 4] Center 33 (3~64) winsize 62
3986 09:26:17.857833 [CA 5] Center 33 (3~64) winsize 62
3987 09:26:17.857919
3988 09:26:17.860820 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3989 09:26:17.860984
3990 09:26:17.864216 [CATrainingPosCal] consider 2 rank data
3991 09:26:17.867849 u2DelayCellTimex100 = 270/100 ps
3992 09:26:17.870922 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3993 09:26:17.877776 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3994 09:26:17.880971 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3995 09:26:17.883993 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3996 09:26:17.887547 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3997 09:26:17.890637 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 09:26:17.890718
3999 09:26:17.893647 CA PerBit enable=1, Macro0, CA PI delay=33
4000 09:26:17.893729
4001 09:26:17.897210 [CBTSetCACLKResult] CA Dly = 33
4002 09:26:17.901142 CS Dly: 5 (0~38)
4003 09:26:17.901226
4004 09:26:17.903781 ----->DramcWriteLeveling(PI) begin...
4005 09:26:17.903864 ==
4006 09:26:17.907066 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 09:26:17.910369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 09:26:17.910456 ==
4009 09:26:17.913938 Write leveling (Byte 0): 31 => 31
4010 09:26:17.916819 Write leveling (Byte 1): 30 => 30
4011 09:26:17.920586 DramcWriteLeveling(PI) end<-----
4012 09:26:17.920669
4013 09:26:17.920734 ==
4014 09:26:17.923737 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 09:26:17.926819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 09:26:17.926904 ==
4017 09:26:17.930028 [Gating] SW mode calibration
4018 09:26:17.936841 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4019 09:26:17.943292 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4020 09:26:17.946654 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 09:26:17.950212 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4022 09:26:17.956942 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 09:26:17.959836 0 9 12 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 0)
4024 09:26:17.963429 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (1 1) (0 0)
4025 09:26:17.969964 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 09:26:17.973032 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 09:26:17.976592 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 09:26:17.983335 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 09:26:17.986448 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 09:26:17.990112 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 09:26:17.996736 0 10 12 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
4032 09:26:17.999902 0 10 16 | B1->B0 | 3939 4545 | 0 1 | (0 0) (0 0)
4033 09:26:18.002931 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 09:26:18.009674 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 09:26:18.013148 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 09:26:18.016025 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 09:26:18.022685 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 09:26:18.025725 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 09:26:18.029520 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 09:26:18.035697 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4041 09:26:18.039366 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 09:26:18.042820 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 09:26:18.048779 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 09:26:18.052093 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 09:26:18.055468 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 09:26:18.062454 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 09:26:18.065579 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 09:26:18.068540 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 09:26:18.075634 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 09:26:18.079071 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 09:26:18.082274 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 09:26:18.088353 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 09:26:18.092205 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 09:26:18.095041 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 09:26:18.101732 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4056 09:26:18.104798 Total UI for P1: 0, mck2ui 16
4057 09:26:18.108539 best dqsien dly found for B0: ( 0, 13, 10)
4058 09:26:18.111622 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4059 09:26:18.115088 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 09:26:18.118287 Total UI for P1: 0, mck2ui 16
4061 09:26:18.121416 best dqsien dly found for B1: ( 0, 13, 14)
4062 09:26:18.124822 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4063 09:26:18.131560 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4064 09:26:18.131642
4065 09:26:18.134649 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4066 09:26:18.137983 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4067 09:26:18.141902 [Gating] SW calibration Done
4068 09:26:18.141984 ==
4069 09:26:18.144912 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 09:26:18.147967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 09:26:18.148049 ==
4072 09:26:18.151139 RX Vref Scan: 0
4073 09:26:18.151221
4074 09:26:18.151286 RX Vref 0 -> 0, step: 1
4075 09:26:18.151346
4076 09:26:18.154775 RX Delay -230 -> 252, step: 16
4077 09:26:18.157765 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4078 09:26:18.164867 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4079 09:26:18.167834 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4080 09:26:18.171406 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4081 09:26:18.174351 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4082 09:26:18.177906 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4083 09:26:18.184329 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4084 09:26:18.188015 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4085 09:26:18.191136 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4086 09:26:18.194196 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4087 09:26:18.200756 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4088 09:26:18.204373 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4089 09:26:18.207477 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4090 09:26:18.210634 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4091 09:26:18.217384 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4092 09:26:18.220449 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4093 09:26:18.220532 ==
4094 09:26:18.223622 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 09:26:18.227332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 09:26:18.227414 ==
4097 09:26:18.230358 DQS Delay:
4098 09:26:18.230439 DQS0 = 0, DQS1 = 0
4099 09:26:18.230504 DQM Delay:
4100 09:26:18.233497 DQM0 = 48, DQM1 = 38
4101 09:26:18.233578 DQ Delay:
4102 09:26:18.237504 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4103 09:26:18.240655 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4104 09:26:18.243580 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4105 09:26:18.246893 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4106 09:26:18.246975
4107 09:26:18.247039
4108 09:26:18.247100 ==
4109 09:26:18.250439 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 09:26:18.257081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 09:26:18.257190 ==
4112 09:26:18.257287
4113 09:26:18.257350
4114 09:26:18.257408 TX Vref Scan disable
4115 09:26:18.260665 == TX Byte 0 ==
4116 09:26:18.263861 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4117 09:26:18.270758 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4118 09:26:18.270842 == TX Byte 1 ==
4119 09:26:18.273899 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4120 09:26:18.280411 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4121 09:26:18.280492 ==
4122 09:26:18.283929 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 09:26:18.286999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 09:26:18.287083 ==
4125 09:26:18.287148
4126 09:26:18.287208
4127 09:26:18.290510 TX Vref Scan disable
4128 09:26:18.293563 == TX Byte 0 ==
4129 09:26:18.297373 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4130 09:26:18.300407 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4131 09:26:18.303936 == TX Byte 1 ==
4132 09:26:18.306831 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4133 09:26:18.310463 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4134 09:26:18.310546
4135 09:26:18.310610 [DATLAT]
4136 09:26:18.313572 Freq=600, CH0 RK0
4137 09:26:18.313654
4138 09:26:18.316656 DATLAT Default: 0x9
4139 09:26:18.316737 0, 0xFFFF, sum = 0
4140 09:26:18.320355 1, 0xFFFF, sum = 0
4141 09:26:18.320438 2, 0xFFFF, sum = 0
4142 09:26:18.323221 3, 0xFFFF, sum = 0
4143 09:26:18.323304 4, 0xFFFF, sum = 0
4144 09:26:18.327010 5, 0xFFFF, sum = 0
4145 09:26:18.327093 6, 0xFFFF, sum = 0
4146 09:26:18.330093 7, 0xFFFF, sum = 0
4147 09:26:18.330177 8, 0x0, sum = 1
4148 09:26:18.333136 9, 0x0, sum = 2
4149 09:26:18.333234 10, 0x0, sum = 3
4150 09:26:18.336393 11, 0x0, sum = 4
4151 09:26:18.336475 best_step = 9
4152 09:26:18.336540
4153 09:26:18.336599 ==
4154 09:26:18.340047 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 09:26:18.343221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 09:26:18.343303 ==
4157 09:26:18.346221 RX Vref Scan: 1
4158 09:26:18.346291
4159 09:26:18.349855 RX Vref 0 -> 0, step: 1
4160 09:26:18.349937
4161 09:26:18.350001 RX Delay -179 -> 252, step: 8
4162 09:26:18.353021
4163 09:26:18.353102 Set Vref, RX VrefLevel [Byte0]: 56
4164 09:26:18.356442 [Byte1]: 52
4165 09:26:18.361174
4166 09:26:18.361263 Final RX Vref Byte 0 = 56 to rank0
4167 09:26:18.364687 Final RX Vref Byte 1 = 52 to rank0
4168 09:26:18.367707 Final RX Vref Byte 0 = 56 to rank1
4169 09:26:18.370913 Final RX Vref Byte 1 = 52 to rank1==
4170 09:26:18.374328 Dram Type= 6, Freq= 0, CH_0, rank 0
4171 09:26:18.380816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 09:26:18.380899 ==
4173 09:26:18.380964 DQS Delay:
4174 09:26:18.384382 DQS0 = 0, DQS1 = 0
4175 09:26:18.384463 DQM Delay:
4176 09:26:18.384543 DQM0 = 44, DQM1 = 36
4177 09:26:18.387581 DQ Delay:
4178 09:26:18.391137 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4179 09:26:18.393969 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4180 09:26:18.397667 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4181 09:26:18.400833 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4182 09:26:18.400915
4183 09:26:18.400979
4184 09:26:18.407548 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4185 09:26:18.410691 CH0 RK0: MR19=808, MR18=4B43
4186 09:26:18.417198 CH0_RK0: MR19=0x808, MR18=0x4B43, DQSOSC=395, MR23=63, INC=168, DEC=112
4187 09:26:18.417302
4188 09:26:18.420405 ----->DramcWriteLeveling(PI) begin...
4189 09:26:18.420487 ==
4190 09:26:18.424177 Dram Type= 6, Freq= 0, CH_0, rank 1
4191 09:26:18.427112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 09:26:18.427194 ==
4193 09:26:18.430885 Write leveling (Byte 0): 32 => 32
4194 09:26:18.433961 Write leveling (Byte 1): 29 => 29
4195 09:26:18.437045 DramcWriteLeveling(PI) end<-----
4196 09:26:18.437127
4197 09:26:18.437192 ==
4198 09:26:18.440768 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 09:26:18.443839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 09:26:18.446904 ==
4201 09:26:18.446986 [Gating] SW mode calibration
4202 09:26:18.457377 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4203 09:26:18.460461 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4204 09:26:18.463690 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4205 09:26:18.470108 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4206 09:26:18.473504 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 09:26:18.476860 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
4208 09:26:18.483180 0 9 16 | B1->B0 | 2f2f 2626 | 1 0 | (1 1) (0 0)
4209 09:26:18.486491 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 09:26:18.489754 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 09:26:18.496468 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 09:26:18.499761 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 09:26:18.502839 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 09:26:18.509551 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 09:26:18.513077 0 10 12 | B1->B0 | 2525 3333 | 1 0 | (0 0) (0 0)
4216 09:26:18.516114 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4217 09:26:18.522685 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 09:26:18.525820 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 09:26:18.529380 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 09:26:18.536106 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 09:26:18.539330 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 09:26:18.542336 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4223 09:26:18.549107 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4224 09:26:18.552254 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4225 09:26:18.555930 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 09:26:18.562141 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 09:26:18.565828 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 09:26:18.568862 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 09:26:18.575586 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 09:26:18.579225 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 09:26:18.582307 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 09:26:18.588972 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 09:26:18.592291 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 09:26:18.595919 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 09:26:18.602100 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 09:26:18.605010 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 09:26:18.608343 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 09:26:18.615227 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 09:26:18.618523 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4240 09:26:18.621717 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 09:26:18.625321 Total UI for P1: 0, mck2ui 16
4242 09:26:18.628062 best dqsien dly found for B0: ( 0, 13, 12)
4243 09:26:18.631829 Total UI for P1: 0, mck2ui 16
4244 09:26:18.634987 best dqsien dly found for B1: ( 0, 13, 14)
4245 09:26:18.637935 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4246 09:26:18.641621 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4247 09:26:18.644843
4248 09:26:18.647727 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4249 09:26:18.651487 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4250 09:26:18.654617 [Gating] SW calibration Done
4251 09:26:18.654696 ==
4252 09:26:18.657676 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 09:26:18.661362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 09:26:18.661462 ==
4255 09:26:18.664527 RX Vref Scan: 0
4256 09:26:18.664601
4257 09:26:18.664663 RX Vref 0 -> 0, step: 1
4258 09:26:18.664764
4259 09:26:18.667672 RX Delay -230 -> 252, step: 16
4260 09:26:18.670735 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4261 09:26:18.677685 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4262 09:26:18.680799 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4263 09:26:18.683865 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4264 09:26:18.687775 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4265 09:26:18.693828 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4266 09:26:18.697545 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4267 09:26:18.701120 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4268 09:26:18.703737 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4269 09:26:18.710315 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4270 09:26:18.713782 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4271 09:26:18.717239 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4272 09:26:18.720738 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4273 09:26:18.726698 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4274 09:26:18.730260 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4275 09:26:18.733714 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4276 09:26:18.733791 ==
4277 09:26:18.736861 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 09:26:18.739860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 09:26:18.739966 ==
4280 09:26:18.743172 DQS Delay:
4281 09:26:18.743277 DQS0 = 0, DQS1 = 0
4282 09:26:18.746991 DQM Delay:
4283 09:26:18.747099 DQM0 = 44, DQM1 = 36
4284 09:26:18.747205 DQ Delay:
4285 09:26:18.750061 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4286 09:26:18.753433 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =49
4287 09:26:18.756523 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4288 09:26:18.760313 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4289 09:26:18.760396
4290 09:26:18.760460
4291 09:26:18.763397 ==
4292 09:26:18.766486 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 09:26:18.769617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 09:26:18.769697 ==
4295 09:26:18.769761
4296 09:26:18.769820
4297 09:26:18.773233 TX Vref Scan disable
4298 09:26:18.773355 == TX Byte 0 ==
4299 09:26:18.780164 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4300 09:26:18.783125 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4301 09:26:18.783230 == TX Byte 1 ==
4302 09:26:18.790041 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4303 09:26:18.793144 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4304 09:26:18.793245 ==
4305 09:26:18.796185 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 09:26:18.799331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 09:26:18.799447 ==
4308 09:26:18.799545
4309 09:26:18.799643
4310 09:26:18.802526 TX Vref Scan disable
4311 09:26:18.806070 == TX Byte 0 ==
4312 09:26:18.809210 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4313 09:26:18.812568 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4314 09:26:18.815876 == TX Byte 1 ==
4315 09:26:18.819195 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4316 09:26:18.825771 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4317 09:26:18.825852
4318 09:26:18.825916 [DATLAT]
4319 09:26:18.825977 Freq=600, CH0 RK1
4320 09:26:18.826038
4321 09:26:18.829215 DATLAT Default: 0x9
4322 09:26:18.829311 0, 0xFFFF, sum = 0
4323 09:26:18.832585 1, 0xFFFF, sum = 0
4324 09:26:18.832668 2, 0xFFFF, sum = 0
4325 09:26:18.836051 3, 0xFFFF, sum = 0
4326 09:26:18.839146 4, 0xFFFF, sum = 0
4327 09:26:18.839229 5, 0xFFFF, sum = 0
4328 09:26:18.842226 6, 0xFFFF, sum = 0
4329 09:26:18.842310 7, 0xFFFF, sum = 0
4330 09:26:18.845991 8, 0x0, sum = 1
4331 09:26:18.846073 9, 0x0, sum = 2
4332 09:26:18.846165 10, 0x0, sum = 3
4333 09:26:18.848869 11, 0x0, sum = 4
4334 09:26:18.848984 best_step = 9
4335 09:26:18.849077
4336 09:26:18.852397 ==
4337 09:26:18.852515 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 09:26:18.858768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 09:26:18.858876 ==
4340 09:26:18.858969 RX Vref Scan: 0
4341 09:26:18.859058
4342 09:26:18.862152 RX Vref 0 -> 0, step: 1
4343 09:26:18.862224
4344 09:26:18.865565 RX Delay -179 -> 252, step: 8
4345 09:26:18.871777 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4346 09:26:18.874945 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4347 09:26:18.878560 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4348 09:26:18.881824 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4349 09:26:18.884911 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4350 09:26:18.891758 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4351 09:26:18.894922 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4352 09:26:18.898065 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4353 09:26:18.901752 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4354 09:26:18.907802 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4355 09:26:18.911547 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4356 09:26:18.914620 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4357 09:26:18.917788 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4358 09:26:18.924483 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4359 09:26:18.927866 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4360 09:26:18.931173 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4361 09:26:18.931258 ==
4362 09:26:18.934111 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 09:26:18.937474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 09:26:18.941156 ==
4365 09:26:18.941300 DQS Delay:
4366 09:26:18.941368 DQS0 = 0, DQS1 = 0
4367 09:26:18.944252 DQM Delay:
4368 09:26:18.944332 DQM0 = 43, DQM1 = 37
4369 09:26:18.947647 DQ Delay:
4370 09:26:18.947727 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4371 09:26:18.951125 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =48
4372 09:26:18.954412 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4373 09:26:18.957658 DQ12 =40, DQ13 =44, DQ14 =48, DQ15 =44
4374 09:26:18.957740
4375 09:26:18.960992
4376 09:26:18.967650 [DQSOSCAuto] RK1, (LSB)MR18= 0x433f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4377 09:26:18.970975 CH0 RK1: MR19=808, MR18=433F
4378 09:26:18.977295 CH0_RK1: MR19=0x808, MR18=0x433F, DQSOSC=397, MR23=63, INC=166, DEC=110
4379 09:26:18.981030 [RxdqsGatingPostProcess] freq 600
4380 09:26:18.984109 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4381 09:26:18.987480 Pre-setting of DQS Precalculation
4382 09:26:18.994105 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4383 09:26:18.994231 ==
4384 09:26:18.997068 Dram Type= 6, Freq= 0, CH_1, rank 0
4385 09:26:19.000920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 09:26:19.001029 ==
4387 09:26:19.006961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4388 09:26:19.010693 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4389 09:26:19.014279 [CA 0] Center 36 (6~66) winsize 61
4390 09:26:19.017805 [CA 1] Center 36 (6~66) winsize 61
4391 09:26:19.020899 [CA 2] Center 35 (5~65) winsize 61
4392 09:26:19.024728 [CA 3] Center 34 (4~65) winsize 62
4393 09:26:19.027883 [CA 4] Center 34 (4~65) winsize 62
4394 09:26:19.030827 [CA 5] Center 34 (3~65) winsize 63
4395 09:26:19.030928
4396 09:26:19.034258 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4397 09:26:19.034360
4398 09:26:19.037860 [CATrainingPosCal] consider 1 rank data
4399 09:26:19.040708 u2DelayCellTimex100 = 270/100 ps
4400 09:26:19.044292 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4401 09:26:19.050886 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4402 09:26:19.054072 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4403 09:26:19.057724 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4404 09:26:19.060531 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4405 09:26:19.063885 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4406 09:26:19.064030
4407 09:26:19.067515 CA PerBit enable=1, Macro0, CA PI delay=34
4408 09:26:19.067681
4409 09:26:19.070799 [CBTSetCACLKResult] CA Dly = 34
4410 09:26:19.073798 CS Dly: 4 (0~35)
4411 09:26:19.073968 ==
4412 09:26:19.077240 Dram Type= 6, Freq= 0, CH_1, rank 1
4413 09:26:19.080543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 09:26:19.080737 ==
4415 09:26:19.087388 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4416 09:26:19.090479 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4417 09:26:19.095086 [CA 0] Center 36 (6~66) winsize 61
4418 09:26:19.098053 [CA 1] Center 35 (5~66) winsize 62
4419 09:26:19.101251 [CA 2] Center 34 (4~65) winsize 62
4420 09:26:19.105004 [CA 3] Center 33 (3~64) winsize 62
4421 09:26:19.107951 [CA 4] Center 34 (4~65) winsize 62
4422 09:26:19.111235 [CA 5] Center 33 (3~64) winsize 62
4423 09:26:19.111696
4424 09:26:19.114618 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4425 09:26:19.114727
4426 09:26:19.117760 [CATrainingPosCal] consider 2 rank data
4427 09:26:19.120846 u2DelayCellTimex100 = 270/100 ps
4428 09:26:19.124571 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4429 09:26:19.130885 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4430 09:26:19.134613 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4431 09:26:19.137581 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4432 09:26:19.140881 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 09:26:19.144050 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 09:26:19.144163
4435 09:26:19.147536 CA PerBit enable=1, Macro0, CA PI delay=33
4436 09:26:19.147651
4437 09:26:19.150959 [CBTSetCACLKResult] CA Dly = 33
4438 09:26:19.154302 CS Dly: 5 (0~37)
4439 09:26:19.154407
4440 09:26:19.157239 ----->DramcWriteLeveling(PI) begin...
4441 09:26:19.157330 ==
4442 09:26:19.160848 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 09:26:19.164519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 09:26:19.164671 ==
4445 09:26:19.167487 Write leveling (Byte 0): 30 => 30
4446 09:26:19.171165 Write leveling (Byte 1): 29 => 29
4447 09:26:19.173907 DramcWriteLeveling(PI) end<-----
4448 09:26:19.174017
4449 09:26:19.174110 ==
4450 09:26:19.177520 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 09:26:19.180887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 09:26:19.181001 ==
4453 09:26:19.183924 [Gating] SW mode calibration
4454 09:26:19.190450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4455 09:26:19.197117 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4456 09:26:19.200235 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4457 09:26:19.203472 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 09:26:19.210153 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 09:26:19.213337 0 9 12 | B1->B0 | 3030 2a2a | 0 0 | (0 0) (1 1)
4460 09:26:19.216951 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 09:26:19.223124 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 09:26:19.226755 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 09:26:19.229884 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 09:26:19.236727 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 09:26:19.239975 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 09:26:19.243320 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4467 09:26:19.249791 0 10 12 | B1->B0 | 3434 3939 | 0 0 | (0 0) (0 0)
4468 09:26:19.253445 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 09:26:19.256313 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 09:26:19.263184 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 09:26:19.266050 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 09:26:19.269737 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 09:26:19.276689 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 09:26:19.279564 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 09:26:19.283179 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4476 09:26:19.289112 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 09:26:19.292807 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 09:26:19.295687 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 09:26:19.302281 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 09:26:19.306136 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 09:26:19.309063 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 09:26:19.316150 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 09:26:19.319114 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 09:26:19.322868 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 09:26:19.329085 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 09:26:19.332759 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 09:26:19.335812 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 09:26:19.342572 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 09:26:19.345756 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 09:26:19.348725 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 09:26:19.355559 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4492 09:26:19.355668 Total UI for P1: 0, mck2ui 16
4493 09:26:19.361906 best dqsien dly found for B0: ( 0, 13, 10)
4494 09:26:19.365090 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 09:26:19.368697 Total UI for P1: 0, mck2ui 16
4496 09:26:19.372008 best dqsien dly found for B1: ( 0, 13, 14)
4497 09:26:19.375410 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4498 09:26:19.378392 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4499 09:26:19.378476
4500 09:26:19.381748 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4501 09:26:19.388328 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4502 09:26:19.388412 [Gating] SW calibration Done
4503 09:26:19.388479 ==
4504 09:26:19.391850 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 09:26:19.398128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 09:26:19.398214 ==
4507 09:26:19.398281 RX Vref Scan: 0
4508 09:26:19.398343
4509 09:26:19.401144 RX Vref 0 -> 0, step: 1
4510 09:26:19.401229
4511 09:26:19.404928 RX Delay -230 -> 252, step: 16
4512 09:26:19.407911 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4513 09:26:19.411185 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4514 09:26:19.417834 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4515 09:26:19.421370 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4516 09:26:19.424550 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4517 09:26:19.427598 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4518 09:26:19.431315 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4519 09:26:19.437393 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4520 09:26:19.441137 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4521 09:26:19.444235 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4522 09:26:19.447248 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4523 09:26:19.454137 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4524 09:26:19.457320 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4525 09:26:19.460509 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4526 09:26:19.463949 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4527 09:26:19.470532 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4528 09:26:19.470621 ==
4529 09:26:19.474115 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 09:26:19.477163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 09:26:19.477273 ==
4532 09:26:19.477354 DQS Delay:
4533 09:26:19.480387 DQS0 = 0, DQS1 = 0
4534 09:26:19.480470 DQM Delay:
4535 09:26:19.483781 DQM0 = 42, DQM1 = 39
4536 09:26:19.483864 DQ Delay:
4537 09:26:19.486991 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4538 09:26:19.490512 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4539 09:26:19.493895 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4540 09:26:19.497349 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4541 09:26:19.497432
4542 09:26:19.497496
4543 09:26:19.497556 ==
4544 09:26:19.500134 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 09:26:19.503715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 09:26:19.506831 ==
4547 09:26:19.506950
4548 09:26:19.507014
4549 09:26:19.507074 TX Vref Scan disable
4550 09:26:19.509939 == TX Byte 0 ==
4551 09:26:19.513548 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4552 09:26:19.519963 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4553 09:26:19.520046 == TX Byte 1 ==
4554 09:26:19.523275 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4555 09:26:19.530006 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4556 09:26:19.530089 ==
4557 09:26:19.533214 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 09:26:19.536352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 09:26:19.536459 ==
4560 09:26:19.536559
4561 09:26:19.536647
4562 09:26:19.539427 TX Vref Scan disable
4563 09:26:19.543214 == TX Byte 0 ==
4564 09:26:19.546365 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4565 09:26:19.549420 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4566 09:26:19.552504 == TX Byte 1 ==
4567 09:26:19.556177 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4568 09:26:19.559290 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4569 09:26:19.559398
4570 09:26:19.562588 [DATLAT]
4571 09:26:19.562668 Freq=600, CH1 RK0
4572 09:26:19.562732
4573 09:26:19.566015 DATLAT Default: 0x9
4574 09:26:19.566096 0, 0xFFFF, sum = 0
4575 09:26:19.569166 1, 0xFFFF, sum = 0
4576 09:26:19.569313 2, 0xFFFF, sum = 0
4577 09:26:19.572622 3, 0xFFFF, sum = 0
4578 09:26:19.572703 4, 0xFFFF, sum = 0
4579 09:26:19.575760 5, 0xFFFF, sum = 0
4580 09:26:19.575862 6, 0xFFFF, sum = 0
4581 09:26:19.579239 7, 0xFFFF, sum = 0
4582 09:26:19.579343 8, 0x0, sum = 1
4583 09:26:19.582121 9, 0x0, sum = 2
4584 09:26:19.582222 10, 0x0, sum = 3
4585 09:26:19.585212 11, 0x0, sum = 4
4586 09:26:19.585348 best_step = 9
4587 09:26:19.585420
4588 09:26:19.585478 ==
4589 09:26:19.588911 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 09:26:19.592232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 09:26:19.595722 ==
4592 09:26:19.595828 RX Vref Scan: 1
4593 09:26:19.595922
4594 09:26:19.598788 RX Vref 0 -> 0, step: 1
4595 09:26:19.598885
4596 09:26:19.601987 RX Delay -179 -> 252, step: 8
4597 09:26:19.602098
4598 09:26:19.605444 Set Vref, RX VrefLevel [Byte0]: 52
4599 09:26:19.605529 [Byte1]: 49
4600 09:26:19.610163
4601 09:26:19.610245 Final RX Vref Byte 0 = 52 to rank0
4602 09:26:19.613855 Final RX Vref Byte 1 = 49 to rank0
4603 09:26:19.617045 Final RX Vref Byte 0 = 52 to rank1
4604 09:26:19.620148 Final RX Vref Byte 1 = 49 to rank1==
4605 09:26:19.623793 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 09:26:19.630254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 09:26:19.630338 ==
4608 09:26:19.630403 DQS Delay:
4609 09:26:19.633544 DQS0 = 0, DQS1 = 0
4610 09:26:19.633620 DQM Delay:
4611 09:26:19.633752 DQM0 = 42, DQM1 = 34
4612 09:26:19.636753 DQ Delay:
4613 09:26:19.640128 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4614 09:26:19.643141 DQ4 =36, DQ5 =52, DQ6 =52, DQ7 =36
4615 09:26:19.646342 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4616 09:26:19.650134 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4617 09:26:19.650283
4618 09:26:19.650374
4619 09:26:19.656251 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f49, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 400 ps
4620 09:26:19.659417 CH1 RK0: MR19=808, MR18=2F49
4621 09:26:19.666375 CH1_RK0: MR19=0x808, MR18=0x2F49, DQSOSC=396, MR23=63, INC=167, DEC=111
4622 09:26:19.666585
4623 09:26:19.669727 ----->DramcWriteLeveling(PI) begin...
4624 09:26:19.669864 ==
4625 09:26:19.672874 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 09:26:19.676255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 09:26:19.676393 ==
4628 09:26:19.679297 Write leveling (Byte 0): 30 => 30
4629 09:26:19.682649 Write leveling (Byte 1): 32 => 32
4630 09:26:19.686435 DramcWriteLeveling(PI) end<-----
4631 09:26:19.686550
4632 09:26:19.686642 ==
4633 09:26:19.689790 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 09:26:19.695815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 09:26:19.695937 ==
4636 09:26:19.696031 [Gating] SW mode calibration
4637 09:26:19.705917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4638 09:26:19.708817 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4639 09:26:19.712151 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4640 09:26:19.719264 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 09:26:19.722234 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 09:26:19.725833 0 9 12 | B1->B0 | 3131 2b2b | 1 0 | (0 0) (0 0)
4643 09:26:19.732125 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 09:26:19.735592 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 09:26:19.739170 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 09:26:19.745482 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 09:26:19.748929 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 09:26:19.752004 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 09:26:19.758850 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
4650 09:26:19.761933 0 10 12 | B1->B0 | 3030 4141 | 0 0 | (0 0) (0 0)
4651 09:26:19.765104 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4652 09:26:19.771899 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 09:26:19.775529 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 09:26:19.778621 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 09:26:19.785225 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 09:26:19.788274 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 09:26:19.791990 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 09:26:19.798419 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 09:26:19.801490 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 09:26:19.805071 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 09:26:19.811639 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 09:26:19.814902 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 09:26:19.818268 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 09:26:19.824554 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 09:26:19.828195 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 09:26:19.831387 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 09:26:19.838164 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 09:26:19.841180 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 09:26:19.844535 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 09:26:19.851015 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 09:26:19.854381 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 09:26:19.858155 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 09:26:19.864363 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 09:26:19.868078 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4675 09:26:19.871259 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 09:26:19.874225 Total UI for P1: 0, mck2ui 16
4677 09:26:19.877794 best dqsien dly found for B0: ( 0, 13, 12)
4678 09:26:19.880920 Total UI for P1: 0, mck2ui 16
4679 09:26:19.884736 best dqsien dly found for B1: ( 0, 13, 12)
4680 09:26:19.887536 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4681 09:26:19.890732 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4682 09:26:19.893847
4683 09:26:19.897399 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4684 09:26:19.900517 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4685 09:26:19.904098 [Gating] SW calibration Done
4686 09:26:19.904213 ==
4687 09:26:19.907140 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 09:26:19.910673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 09:26:19.910787 ==
4690 09:26:19.910883 RX Vref Scan: 0
4691 09:26:19.914075
4692 09:26:19.914175 RX Vref 0 -> 0, step: 1
4693 09:26:19.914266
4694 09:26:19.916978 RX Delay -230 -> 252, step: 16
4695 09:26:19.920680 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4696 09:26:19.927030 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4697 09:26:19.930044 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4698 09:26:19.933636 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4699 09:26:19.936774 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4700 09:26:19.943678 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4701 09:26:19.946602 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4702 09:26:19.950086 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4703 09:26:19.953608 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4704 09:26:19.956542 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4705 09:26:19.963104 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4706 09:26:19.966801 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4707 09:26:19.969946 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4708 09:26:19.972988 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4709 09:26:19.979896 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4710 09:26:19.982881 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4711 09:26:19.982965 ==
4712 09:26:19.986695 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 09:26:19.989635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 09:26:19.989726 ==
4715 09:26:19.992802 DQS Delay:
4716 09:26:19.992915 DQS0 = 0, DQS1 = 0
4717 09:26:19.993018 DQM Delay:
4718 09:26:19.996360 DQM0 = 42, DQM1 = 38
4719 09:26:19.996492 DQ Delay:
4720 09:26:19.999537 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4721 09:26:20.002589 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4722 09:26:20.006123 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4723 09:26:20.009636 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4724 09:26:20.009730
4725 09:26:20.009799
4726 09:26:20.009861 ==
4727 09:26:20.012655 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 09:26:20.019156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 09:26:20.019283 ==
4730 09:26:20.019382
4731 09:26:20.019483
4732 09:26:20.022588 TX Vref Scan disable
4733 09:26:20.022702 == TX Byte 0 ==
4734 09:26:20.025715 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4735 09:26:20.032785 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4736 09:26:20.032928 == TX Byte 1 ==
4737 09:26:20.038948 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4738 09:26:20.042564 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4739 09:26:20.042654 ==
4740 09:26:20.045731 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 09:26:20.048896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 09:26:20.048981 ==
4743 09:26:20.049047
4744 09:26:20.049108
4745 09:26:20.051970 TX Vref Scan disable
4746 09:26:20.055507 == TX Byte 0 ==
4747 09:26:20.058902 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4748 09:26:20.061888 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4749 09:26:20.065482 == TX Byte 1 ==
4750 09:26:20.068461 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4751 09:26:20.071690 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4752 09:26:20.071806
4753 09:26:20.075288 [DATLAT]
4754 09:26:20.075395 Freq=600, CH1 RK1
4755 09:26:20.075493
4756 09:26:20.078311 DATLAT Default: 0x9
4757 09:26:20.078420 0, 0xFFFF, sum = 0
4758 09:26:20.082242 1, 0xFFFF, sum = 0
4759 09:26:20.082329 2, 0xFFFF, sum = 0
4760 09:26:20.084982 3, 0xFFFF, sum = 0
4761 09:26:20.085076 4, 0xFFFF, sum = 0
4762 09:26:20.088067 5, 0xFFFF, sum = 0
4763 09:26:20.091653 6, 0xFFFF, sum = 0
4764 09:26:20.091745 7, 0xFFFF, sum = 0
4765 09:26:20.094827 8, 0x0, sum = 1
4766 09:26:20.094947 9, 0x0, sum = 2
4767 09:26:20.095017 10, 0x0, sum = 3
4768 09:26:20.097966 11, 0x0, sum = 4
4769 09:26:20.098043 best_step = 9
4770 09:26:20.098111
4771 09:26:20.098191 ==
4772 09:26:20.101550 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 09:26:20.108404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 09:26:20.108506 ==
4775 09:26:20.108585 RX Vref Scan: 0
4776 09:26:20.108647
4777 09:26:20.111293 RX Vref 0 -> 0, step: 1
4778 09:26:20.111370
4779 09:26:20.114905 RX Delay -179 -> 252, step: 8
4780 09:26:20.118413 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4781 09:26:20.124918 iDelay=205, Bit 1, Center 32 (-131 ~ 196) 328
4782 09:26:20.127860 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4783 09:26:20.131389 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4784 09:26:20.134480 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4785 09:26:20.141022 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4786 09:26:20.144441 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4787 09:26:20.148000 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4788 09:26:20.151279 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4789 09:26:20.154300 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4790 09:26:20.160877 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4791 09:26:20.164349 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4792 09:26:20.167838 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4793 09:26:20.170945 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4794 09:26:20.177516 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4795 09:26:20.181090 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4796 09:26:20.181228 ==
4797 09:26:20.184239 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 09:26:20.187838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 09:26:20.187938 ==
4800 09:26:20.190700 DQS Delay:
4801 09:26:20.190787 DQS0 = 0, DQS1 = 0
4802 09:26:20.194389 DQM Delay:
4803 09:26:20.194478 DQM0 = 36, DQM1 = 35
4804 09:26:20.194544 DQ Delay:
4805 09:26:20.197481 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4806 09:26:20.201140 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4807 09:26:20.204208 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4808 09:26:20.207370 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4809 09:26:20.207545
4810 09:26:20.207660
4811 09:26:20.217177 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4812 09:26:20.220749 CH1 RK1: MR19=808, MR18=3C61
4813 09:26:20.227301 CH1_RK1: MR19=0x808, MR18=0x3C61, DQSOSC=391, MR23=63, INC=171, DEC=114
4814 09:26:20.227450 [RxdqsGatingPostProcess] freq 600
4815 09:26:20.233775 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4816 09:26:20.237296 Pre-setting of DQS Precalculation
4817 09:26:20.240392 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4818 09:26:20.250462 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4819 09:26:20.256957 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4820 09:26:20.257105
4821 09:26:20.257175
4822 09:26:20.260074 [Calibration Summary] 1200 Mbps
4823 09:26:20.260175 CH 0, Rank 0
4824 09:26:20.263257 SW Impedance : PASS
4825 09:26:20.263367 DUTY Scan : NO K
4826 09:26:20.266936 ZQ Calibration : PASS
4827 09:26:20.269884 Jitter Meter : NO K
4828 09:26:20.269996 CBT Training : PASS
4829 09:26:20.273243 Write leveling : PASS
4830 09:26:20.276830 RX DQS gating : PASS
4831 09:26:20.277012 RX DQ/DQS(RDDQC) : PASS
4832 09:26:20.279674 TX DQ/DQS : PASS
4833 09:26:20.283251 RX DATLAT : PASS
4834 09:26:20.283401 RX DQ/DQS(Engine): PASS
4835 09:26:20.286417 TX OE : NO K
4836 09:26:20.286561 All Pass.
4837 09:26:20.286663
4838 09:26:20.290152 CH 0, Rank 1
4839 09:26:20.290328 SW Impedance : PASS
4840 09:26:20.293210 DUTY Scan : NO K
4841 09:26:20.296319 ZQ Calibration : PASS
4842 09:26:20.296453 Jitter Meter : NO K
4843 09:26:20.299449 CBT Training : PASS
4844 09:26:20.303007 Write leveling : PASS
4845 09:26:20.303170 RX DQS gating : PASS
4846 09:26:20.305989 RX DQ/DQS(RDDQC) : PASS
4847 09:26:20.309851 TX DQ/DQS : PASS
4848 09:26:20.309984 RX DATLAT : PASS
4849 09:26:20.312794 RX DQ/DQS(Engine): PASS
4850 09:26:20.315912 TX OE : NO K
4851 09:26:20.316044 All Pass.
4852 09:26:20.316155
4853 09:26:20.316248 CH 1, Rank 0
4854 09:26:20.319548 SW Impedance : PASS
4855 09:26:20.322667 DUTY Scan : NO K
4856 09:26:20.322845 ZQ Calibration : PASS
4857 09:26:20.326180 Jitter Meter : NO K
4858 09:26:20.329731 CBT Training : PASS
4859 09:26:20.329908 Write leveling : PASS
4860 09:26:20.332533 RX DQS gating : PASS
4861 09:26:20.335423 RX DQ/DQS(RDDQC) : PASS
4862 09:26:20.335553 TX DQ/DQS : PASS
4863 09:26:20.338869 RX DATLAT : PASS
4864 09:26:20.342489 RX DQ/DQS(Engine): PASS
4865 09:26:20.342645 TX OE : NO K
4866 09:26:20.342775 All Pass.
4867 09:26:20.345628
4868 09:26:20.345745 CH 1, Rank 1
4869 09:26:20.349586 SW Impedance : PASS
4870 09:26:20.349691 DUTY Scan : NO K
4871 09:26:20.352214 ZQ Calibration : PASS
4872 09:26:20.355837 Jitter Meter : NO K
4873 09:26:20.355957 CBT Training : PASS
4874 09:26:20.358987 Write leveling : PASS
4875 09:26:20.359105 RX DQS gating : PASS
4876 09:26:20.362174 RX DQ/DQS(RDDQC) : PASS
4877 09:26:20.365790 TX DQ/DQS : PASS
4878 09:26:20.365943 RX DATLAT : PASS
4879 09:26:20.368897 RX DQ/DQS(Engine): PASS
4880 09:26:20.372005 TX OE : NO K
4881 09:26:20.372097 All Pass.
4882 09:26:20.372186
4883 09:26:20.375681 DramC Write-DBI off
4884 09:26:20.375771 PER_BANK_REFRESH: Hybrid Mode
4885 09:26:20.378893 TX_TRACKING: ON
4886 09:26:20.388206 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4887 09:26:20.391879 [FAST_K] Save calibration result to emmc
4888 09:26:20.394882 dramc_set_vcore_voltage set vcore to 662500
4889 09:26:20.394976 Read voltage for 933, 3
4890 09:26:20.398487 Vio18 = 0
4891 09:26:20.398594 Vcore = 662500
4892 09:26:20.398705 Vdram = 0
4893 09:26:20.401432 Vddq = 0
4894 09:26:20.401545 Vmddr = 0
4895 09:26:20.408121 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4896 09:26:20.411809 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4897 09:26:20.414945 MEM_TYPE=3, freq_sel=17
4898 09:26:20.418079 sv_algorithm_assistance_LP4_1600
4899 09:26:20.421788 ============ PULL DRAM RESETB DOWN ============
4900 09:26:20.424881 ========== PULL DRAM RESETB DOWN end =========
4901 09:26:20.431398 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4902 09:26:20.434946 ===================================
4903 09:26:20.435046 LPDDR4 DRAM CONFIGURATION
4904 09:26:20.437995 ===================================
4905 09:26:20.440992 EX_ROW_EN[0] = 0x0
4906 09:26:20.444362 EX_ROW_EN[1] = 0x0
4907 09:26:20.444479 LP4Y_EN = 0x0
4908 09:26:20.447694 WORK_FSP = 0x0
4909 09:26:20.447780 WL = 0x3
4910 09:26:20.451388 RL = 0x3
4911 09:26:20.451473 BL = 0x2
4912 09:26:20.454263 RPST = 0x0
4913 09:26:20.454351 RD_PRE = 0x0
4914 09:26:20.458051 WR_PRE = 0x1
4915 09:26:20.458138 WR_PST = 0x0
4916 09:26:20.461036 DBI_WR = 0x0
4917 09:26:20.461123 DBI_RD = 0x0
4918 09:26:20.464427 OTF = 0x1
4919 09:26:20.467439 ===================================
4920 09:26:20.471051 ===================================
4921 09:26:20.471140 ANA top config
4922 09:26:20.473990 ===================================
4923 09:26:20.477115 DLL_ASYNC_EN = 0
4924 09:26:20.480669 ALL_SLAVE_EN = 1
4925 09:26:20.484069 NEW_RANK_MODE = 1
4926 09:26:20.484157 DLL_IDLE_MODE = 1
4927 09:26:20.487063 LP45_APHY_COMB_EN = 1
4928 09:26:20.490777 TX_ODT_DIS = 1
4929 09:26:20.493751 NEW_8X_MODE = 1
4930 09:26:20.497306 ===================================
4931 09:26:20.500435 ===================================
4932 09:26:20.503975 data_rate = 1866
4933 09:26:20.504064 CKR = 1
4934 09:26:20.507075 DQ_P2S_RATIO = 8
4935 09:26:20.510654 ===================================
4936 09:26:20.513659 CA_P2S_RATIO = 8
4937 09:26:20.516862 DQ_CA_OPEN = 0
4938 09:26:20.520382 DQ_SEMI_OPEN = 0
4939 09:26:20.523622 CA_SEMI_OPEN = 0
4940 09:26:20.523711 CA_FULL_RATE = 0
4941 09:26:20.526729 DQ_CKDIV4_EN = 1
4942 09:26:20.530423 CA_CKDIV4_EN = 1
4943 09:26:20.533537 CA_PREDIV_EN = 0
4944 09:26:20.536500 PH8_DLY = 0
4945 09:26:20.539928 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4946 09:26:20.543490 DQ_AAMCK_DIV = 4
4947 09:26:20.543576 CA_AAMCK_DIV = 4
4948 09:26:20.546641 CA_ADMCK_DIV = 4
4949 09:26:20.550158 DQ_TRACK_CA_EN = 0
4950 09:26:20.552956 CA_PICK = 933
4951 09:26:20.556398 CA_MCKIO = 933
4952 09:26:20.559444 MCKIO_SEMI = 0
4953 09:26:20.563186 PLL_FREQ = 3732
4954 09:26:20.563273 DQ_UI_PI_RATIO = 32
4955 09:26:20.566244 CA_UI_PI_RATIO = 0
4956 09:26:20.569832 ===================================
4957 09:26:20.572903 ===================================
4958 09:26:20.576447 memory_type:LPDDR4
4959 09:26:20.579515 GP_NUM : 10
4960 09:26:20.579596 SRAM_EN : 1
4961 09:26:20.582698 MD32_EN : 0
4962 09:26:20.586030 ===================================
4963 09:26:20.589462 [ANA_INIT] >>>>>>>>>>>>>>
4964 09:26:20.592521 <<<<<< [CONFIGURE PHASE]: ANA_TX
4965 09:26:20.596213 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4966 09:26:20.599009 ===================================
4967 09:26:20.599095 data_rate = 1866,PCW = 0X8f00
4968 09:26:20.602714 ===================================
4969 09:26:20.605842 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4970 09:26:20.612508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4971 09:26:20.618978 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4972 09:26:20.621971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4973 09:26:20.625758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4974 09:26:20.628806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4975 09:26:20.631953 [ANA_INIT] flow start
4976 09:26:20.635074 [ANA_INIT] PLL >>>>>>>>
4977 09:26:20.635160 [ANA_INIT] PLL <<<<<<<<
4978 09:26:20.638969 [ANA_INIT] MIDPI >>>>>>>>
4979 09:26:20.641817 [ANA_INIT] MIDPI <<<<<<<<
4980 09:26:20.641904 [ANA_INIT] DLL >>>>>>>>
4981 09:26:20.645410 [ANA_INIT] flow end
4982 09:26:20.648266 ============ LP4 DIFF to SE enter ============
4983 09:26:20.654945 ============ LP4 DIFF to SE exit ============
4984 09:26:20.655040 [ANA_INIT] <<<<<<<<<<<<<
4985 09:26:20.658304 [Flow] Enable top DCM control >>>>>
4986 09:26:20.661912 [Flow] Enable top DCM control <<<<<
4987 09:26:20.665021 Enable DLL master slave shuffle
4988 09:26:20.671634 ==============================================================
4989 09:26:20.671746 Gating Mode config
4990 09:26:20.678055 ==============================================================
4991 09:26:20.681701 Config description:
4992 09:26:20.687726 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4993 09:26:20.694412 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4994 09:26:20.700901 SELPH_MODE 0: By rank 1: By Phase
4995 09:26:20.708020 ==============================================================
4996 09:26:20.710914 GAT_TRACK_EN = 1
4997 09:26:20.710998 RX_GATING_MODE = 2
4998 09:26:20.714475 RX_GATING_TRACK_MODE = 2
4999 09:26:20.717592 SELPH_MODE = 1
5000 09:26:20.721508 PICG_EARLY_EN = 1
5001 09:26:20.724256 VALID_LAT_VALUE = 1
5002 09:26:20.731119 ==============================================================
5003 09:26:20.734316 Enter into Gating configuration >>>>
5004 09:26:20.737280 Exit from Gating configuration <<<<
5005 09:26:20.740960 Enter into DVFS_PRE_config >>>>>
5006 09:26:20.750696 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5007 09:26:20.754238 Exit from DVFS_PRE_config <<<<<
5008 09:26:20.757193 Enter into PICG configuration >>>>
5009 09:26:20.760728 Exit from PICG configuration <<<<
5010 09:26:20.764388 [RX_INPUT] configuration >>>>>
5011 09:26:20.767398 [RX_INPUT] configuration <<<<<
5012 09:26:20.770843 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5013 09:26:20.776963 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5014 09:26:20.783563 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5015 09:26:20.790551 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5016 09:26:20.793781 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 09:26:20.800094 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 09:26:20.803605 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5019 09:26:20.809780 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5020 09:26:20.813210 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5021 09:26:20.817177 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5022 09:26:20.820241 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5023 09:26:20.826576 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 09:26:20.829786 ===================================
5025 09:26:20.832805 LPDDR4 DRAM CONFIGURATION
5026 09:26:20.836550 ===================================
5027 09:26:20.836669 EX_ROW_EN[0] = 0x0
5028 09:26:20.839569 EX_ROW_EN[1] = 0x0
5029 09:26:20.839655 LP4Y_EN = 0x0
5030 09:26:20.842706 WORK_FSP = 0x0
5031 09:26:20.842792 WL = 0x3
5032 09:26:20.846329 RL = 0x3
5033 09:26:20.846414 BL = 0x2
5034 09:26:20.849468 RPST = 0x0
5035 09:26:20.849580 RD_PRE = 0x0
5036 09:26:20.852538 WR_PRE = 0x1
5037 09:26:20.856089 WR_PST = 0x0
5038 09:26:20.856172 DBI_WR = 0x0
5039 09:26:20.859259 DBI_RD = 0x0
5040 09:26:20.859341 OTF = 0x1
5041 09:26:20.862763 ===================================
5042 09:26:20.865754 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5043 09:26:20.872378 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5044 09:26:20.875337 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 09:26:20.879112 ===================================
5046 09:26:20.882021 LPDDR4 DRAM CONFIGURATION
5047 09:26:20.885521 ===================================
5048 09:26:20.885604 EX_ROW_EN[0] = 0x10
5049 09:26:20.888526 EX_ROW_EN[1] = 0x0
5050 09:26:20.888608 LP4Y_EN = 0x0
5051 09:26:20.892143 WORK_FSP = 0x0
5052 09:26:20.892225 WL = 0x3
5053 09:26:20.895272 RL = 0x3
5054 09:26:20.898363 BL = 0x2
5055 09:26:20.898449 RPST = 0x0
5056 09:26:20.902128 RD_PRE = 0x0
5057 09:26:20.902218 WR_PRE = 0x1
5058 09:26:20.905565 WR_PST = 0x0
5059 09:26:20.905642 DBI_WR = 0x0
5060 09:26:20.908796 DBI_RD = 0x0
5061 09:26:20.908927 OTF = 0x1
5062 09:26:20.911898 ===================================
5063 09:26:20.918441 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5064 09:26:20.923053 nWR fixed to 30
5065 09:26:20.925936 [ModeRegInit_LP4] CH0 RK0
5066 09:26:20.926022 [ModeRegInit_LP4] CH0 RK1
5067 09:26:20.929044 [ModeRegInit_LP4] CH1 RK0
5068 09:26:20.932082 [ModeRegInit_LP4] CH1 RK1
5069 09:26:20.932191 match AC timing 9
5070 09:26:20.939028 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5071 09:26:20.942217 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5072 09:26:20.945801 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5073 09:26:20.951946 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5074 09:26:20.955525 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5075 09:26:20.955615 ==
5076 09:26:20.958800 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 09:26:20.961740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 09:26:20.961826 ==
5079 09:26:20.968775 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5080 09:26:20.974889 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5081 09:26:20.978569 [CA 0] Center 38 (7~69) winsize 63
5082 09:26:20.981572 [CA 1] Center 37 (7~68) winsize 62
5083 09:26:20.985084 [CA 2] Center 35 (5~65) winsize 61
5084 09:26:20.988613 [CA 3] Center 34 (4~65) winsize 62
5085 09:26:20.991869 [CA 4] Center 33 (3~64) winsize 62
5086 09:26:20.995209 [CA 5] Center 33 (3~63) winsize 61
5087 09:26:20.995287
5088 09:26:20.998321 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5089 09:26:20.998423
5090 09:26:21.001819 [CATrainingPosCal] consider 1 rank data
5091 09:26:21.004784 u2DelayCellTimex100 = 270/100 ps
5092 09:26:21.007821 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5093 09:26:21.011247 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5094 09:26:21.014725 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5095 09:26:21.021434 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5096 09:26:21.024483 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5097 09:26:21.027976 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5098 09:26:21.028059
5099 09:26:21.031218 CA PerBit enable=1, Macro0, CA PI delay=33
5100 09:26:21.031326
5101 09:26:21.034415 [CBTSetCACLKResult] CA Dly = 33
5102 09:26:21.034498 CS Dly: 6 (0~37)
5103 09:26:21.034563 ==
5104 09:26:21.037552 Dram Type= 6, Freq= 0, CH_0, rank 1
5105 09:26:21.044264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 09:26:21.044348 ==
5107 09:26:21.047840 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5108 09:26:21.054227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5109 09:26:21.057814 [CA 0] Center 38 (8~69) winsize 62
5110 09:26:21.060918 [CA 1] Center 38 (7~69) winsize 63
5111 09:26:21.064014 [CA 2] Center 35 (5~65) winsize 61
5112 09:26:21.067556 [CA 3] Center 34 (4~65) winsize 62
5113 09:26:21.070717 [CA 4] Center 33 (3~64) winsize 62
5114 09:26:21.074508 [CA 5] Center 32 (2~63) winsize 62
5115 09:26:21.074591
5116 09:26:21.077374 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5117 09:26:21.077458
5118 09:26:21.080572 [CATrainingPosCal] consider 2 rank data
5119 09:26:21.083682 u2DelayCellTimex100 = 270/100 ps
5120 09:26:21.087241 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5121 09:26:21.094136 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5122 09:26:21.096950 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5123 09:26:21.100280 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5124 09:26:21.103467 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5125 09:26:21.107009 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5126 09:26:21.107096
5127 09:26:21.110294 CA PerBit enable=1, Macro0, CA PI delay=33
5128 09:26:21.110379
5129 09:26:21.114012 [CBTSetCACLKResult] CA Dly = 33
5130 09:26:21.116977 CS Dly: 7 (0~39)
5131 09:26:21.117087
5132 09:26:21.120369 ----->DramcWriteLeveling(PI) begin...
5133 09:26:21.120456 ==
5134 09:26:21.123317 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 09:26:21.127016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 09:26:21.127102 ==
5137 09:26:21.130241 Write leveling (Byte 0): 34 => 34
5138 09:26:21.133298 Write leveling (Byte 1): 25 => 25
5139 09:26:21.136803 DramcWriteLeveling(PI) end<-----
5140 09:26:21.136907
5141 09:26:21.137020 ==
5142 09:26:21.139749 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 09:26:21.143428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 09:26:21.143548 ==
5145 09:26:21.146495 [Gating] SW mode calibration
5146 09:26:21.153441 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5147 09:26:21.160127 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5148 09:26:21.163213 0 14 0 | B1->B0 | 2525 3433 | 1 1 | (1 1) (1 1)
5149 09:26:21.166678 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 09:26:21.173042 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 09:26:21.176131 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 09:26:21.179853 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 09:26:21.186368 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 09:26:21.189752 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5155 09:26:21.192826 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
5156 09:26:21.199609 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
5157 09:26:21.202690 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5158 09:26:21.206193 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 09:26:21.212491 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 09:26:21.215861 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 09:26:21.219172 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 09:26:21.225778 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 09:26:21.229048 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5164 09:26:21.232487 1 0 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
5165 09:26:21.238835 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 09:26:21.242418 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 09:26:21.245565 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 09:26:21.251982 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 09:26:21.255377 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 09:26:21.258969 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 09:26:21.265058 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5172 09:26:21.268885 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5173 09:26:21.271914 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 09:26:21.278796 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 09:26:21.281886 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 09:26:21.284868 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 09:26:21.292143 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 09:26:21.294988 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 09:26:21.298508 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 09:26:21.305174 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 09:26:21.308222 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 09:26:21.311343 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 09:26:21.317971 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 09:26:21.321161 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 09:26:21.324399 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 09:26:21.331358 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5187 09:26:21.334634 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5188 09:26:21.337973 Total UI for P1: 0, mck2ui 16
5189 09:26:21.341104 best dqsien dly found for B0: ( 1, 2, 24)
5190 09:26:21.344268 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5191 09:26:21.350961 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 09:26:21.354580 Total UI for P1: 0, mck2ui 16
5193 09:26:21.357561 best dqsien dly found for B1: ( 1, 3, 0)
5194 09:26:21.361162 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5195 09:26:21.364604 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5196 09:26:21.364699
5197 09:26:21.367623 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5198 09:26:21.370864 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5199 09:26:21.374458 [Gating] SW calibration Done
5200 09:26:21.374541 ==
5201 09:26:21.377593 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 09:26:21.380776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 09:26:21.380855 ==
5204 09:26:21.383824 RX Vref Scan: 0
5205 09:26:21.383914
5206 09:26:21.386903 RX Vref 0 -> 0, step: 1
5207 09:26:21.387028
5208 09:26:21.387106 RX Delay -80 -> 252, step: 8
5209 09:26:21.393867 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5210 09:26:21.396842 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5211 09:26:21.400570 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5212 09:26:21.403404 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5213 09:26:21.406764 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5214 09:26:21.410535 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5215 09:26:21.416815 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5216 09:26:21.420453 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5217 09:26:21.423394 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5218 09:26:21.426431 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5219 09:26:21.430139 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5220 09:26:21.436397 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5221 09:26:21.440095 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5222 09:26:21.443199 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5223 09:26:21.446683 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5224 09:26:21.449623 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5225 09:26:21.452950 ==
5226 09:26:21.453027 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 09:26:21.459775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 09:26:21.459864 ==
5229 09:26:21.459930 DQS Delay:
5230 09:26:21.463100 DQS0 = 0, DQS1 = 0
5231 09:26:21.463234 DQM Delay:
5232 09:26:21.466365 DQM0 = 102, DQM1 = 87
5233 09:26:21.466441 DQ Delay:
5234 09:26:21.469177 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5235 09:26:21.472821 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =107
5236 09:26:21.475968 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5237 09:26:21.479650 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5238 09:26:21.479765
5239 09:26:21.479847
5240 09:26:21.479907 ==
5241 09:26:21.482834 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 09:26:21.485976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 09:26:21.489095 ==
5244 09:26:21.489182
5245 09:26:21.489247
5246 09:26:21.489352 TX Vref Scan disable
5247 09:26:21.492869 == TX Byte 0 ==
5248 09:26:21.495898 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5249 09:26:21.499033 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5250 09:26:21.502742 == TX Byte 1 ==
5251 09:26:21.505873 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5252 09:26:21.509000 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5253 09:26:21.512500 ==
5254 09:26:21.515859 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 09:26:21.518816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 09:26:21.518931 ==
5257 09:26:21.519026
5258 09:26:21.519118
5259 09:26:21.521953 TX Vref Scan disable
5260 09:26:21.522042 == TX Byte 0 ==
5261 09:26:21.528399 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5262 09:26:21.531935 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5263 09:26:21.532025 == TX Byte 1 ==
5264 09:26:21.538644 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5265 09:26:21.541941 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5266 09:26:21.542035
5267 09:26:21.542104 [DATLAT]
5268 09:26:21.544952 Freq=933, CH0 RK0
5269 09:26:21.545030
5270 09:26:21.545093 DATLAT Default: 0xd
5271 09:26:21.548531 0, 0xFFFF, sum = 0
5272 09:26:21.551594 1, 0xFFFF, sum = 0
5273 09:26:21.551672 2, 0xFFFF, sum = 0
5274 09:26:21.554793 3, 0xFFFF, sum = 0
5275 09:26:21.554881 4, 0xFFFF, sum = 0
5276 09:26:21.558446 5, 0xFFFF, sum = 0
5277 09:26:21.558536 6, 0xFFFF, sum = 0
5278 09:26:21.561244 7, 0xFFFF, sum = 0
5279 09:26:21.561343 8, 0xFFFF, sum = 0
5280 09:26:21.564781 9, 0xFFFF, sum = 0
5281 09:26:21.564882 10, 0x0, sum = 1
5282 09:26:21.567907 11, 0x0, sum = 2
5283 09:26:21.567989 12, 0x0, sum = 3
5284 09:26:21.571492 13, 0x0, sum = 4
5285 09:26:21.571575 best_step = 11
5286 09:26:21.571650
5287 09:26:21.571713 ==
5288 09:26:21.574283 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 09:26:21.578032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 09:26:21.581205 ==
5291 09:26:21.581299 RX Vref Scan: 1
5292 09:26:21.581365
5293 09:26:21.584424 RX Vref 0 -> 0, step: 1
5294 09:26:21.584532
5295 09:26:21.587487 RX Delay -69 -> 252, step: 4
5296 09:26:21.587565
5297 09:26:21.587640 Set Vref, RX VrefLevel [Byte0]: 56
5298 09:26:21.591238 [Byte1]: 52
5299 09:26:21.596158
5300 09:26:21.596251 Final RX Vref Byte 0 = 56 to rank0
5301 09:26:21.599286 Final RX Vref Byte 1 = 52 to rank0
5302 09:26:21.603120 Final RX Vref Byte 0 = 56 to rank1
5303 09:26:21.606185 Final RX Vref Byte 1 = 52 to rank1==
5304 09:26:21.609249 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 09:26:21.615998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 09:26:21.616084 ==
5307 09:26:21.616152 DQS Delay:
5308 09:26:21.618998 DQS0 = 0, DQS1 = 0
5309 09:26:21.619108 DQM Delay:
5310 09:26:21.619184 DQM0 = 103, DQM1 = 90
5311 09:26:21.622417 DQ Delay:
5312 09:26:21.625841 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =100
5313 09:26:21.628841 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =108
5314 09:26:21.632564 DQ8 =82, DQ9 =76, DQ10 =90, DQ11 =86
5315 09:26:21.635521 DQ12 =98, DQ13 =92, DQ14 =98, DQ15 =98
5316 09:26:21.635601
5317 09:26:21.635666
5318 09:26:21.642518 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5319 09:26:21.645561 CH0 RK0: MR19=505, MR18=1A15
5320 09:26:21.652183 CH0_RK0: MR19=0x505, MR18=0x1A15, DQSOSC=413, MR23=63, INC=63, DEC=42
5321 09:26:21.652273
5322 09:26:21.655203 ----->DramcWriteLeveling(PI) begin...
5323 09:26:21.655291 ==
5324 09:26:21.658454 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 09:26:21.662002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 09:26:21.665027 ==
5327 09:26:21.665158 Write leveling (Byte 0): 31 => 31
5328 09:26:21.668714 Write leveling (Byte 1): 28 => 28
5329 09:26:21.671780 DramcWriteLeveling(PI) end<-----
5330 09:26:21.671865
5331 09:26:21.671954 ==
5332 09:26:21.675212 Dram Type= 6, Freq= 0, CH_0, rank 1
5333 09:26:21.681899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 09:26:21.682016 ==
5335 09:26:21.684746 [Gating] SW mode calibration
5336 09:26:21.691532 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5337 09:26:21.694677 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5338 09:26:21.701455 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
5339 09:26:21.704615 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5340 09:26:21.708332 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 09:26:21.714529 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 09:26:21.718129 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 09:26:21.721243 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 09:26:21.728072 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5345 09:26:21.730944 0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
5346 09:26:21.734408 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5347 09:26:21.740867 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 09:26:21.743953 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 09:26:21.747298 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 09:26:21.754094 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 09:26:21.757594 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 09:26:21.760480 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5353 09:26:21.767005 0 15 28 | B1->B0 | 2727 3f3f | 0 0 | (0 0) (0 0)
5354 09:26:21.770680 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5355 09:26:21.773897 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 09:26:21.780071 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 09:26:21.783504 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 09:26:21.786918 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 09:26:21.793809 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 09:26:21.796822 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5361 09:26:21.800288 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5362 09:26:21.806874 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5363 09:26:21.810191 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 09:26:21.813570 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 09:26:21.819727 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 09:26:21.823321 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 09:26:21.826289 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 09:26:21.833144 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 09:26:21.836587 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 09:26:21.839715 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 09:26:21.845958 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 09:26:21.849709 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 09:26:21.852580 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 09:26:21.859242 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 09:26:21.862876 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 09:26:21.865834 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5377 09:26:21.872614 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5378 09:26:21.875588 Total UI for P1: 0, mck2ui 16
5379 09:26:21.879286 best dqsien dly found for B0: ( 1, 2, 24)
5380 09:26:21.882376 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 09:26:21.885533 Total UI for P1: 0, mck2ui 16
5382 09:26:21.889136 best dqsien dly found for B1: ( 1, 2, 28)
5383 09:26:21.892587 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5384 09:26:21.896037 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5385 09:26:21.896121
5386 09:26:21.899090 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5387 09:26:21.901995 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5388 09:26:21.905592 [Gating] SW calibration Done
5389 09:26:21.905678 ==
5390 09:26:21.908731 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 09:26:21.915386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 09:26:21.915471 ==
5393 09:26:21.915537 RX Vref Scan: 0
5394 09:26:21.915598
5395 09:26:21.918279 RX Vref 0 -> 0, step: 1
5396 09:26:21.918361
5397 09:26:21.921761 RX Delay -80 -> 252, step: 8
5398 09:26:21.925034 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5399 09:26:21.928381 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5400 09:26:21.931379 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5401 09:26:21.935107 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5402 09:26:21.941643 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5403 09:26:21.944749 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5404 09:26:21.948062 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5405 09:26:21.951579 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5406 09:26:21.954609 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5407 09:26:21.961548 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5408 09:26:21.964950 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5409 09:26:21.967982 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5410 09:26:21.971609 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5411 09:26:21.974462 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5412 09:26:21.978048 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5413 09:26:21.984364 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5414 09:26:21.984480 ==
5415 09:26:21.987442 Dram Type= 6, Freq= 0, CH_0, rank 1
5416 09:26:21.991168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5417 09:26:21.991250 ==
5418 09:26:21.991315 DQS Delay:
5419 09:26:21.994022 DQS0 = 0, DQS1 = 0
5420 09:26:21.994108 DQM Delay:
5421 09:26:21.997673 DQM0 = 100, DQM1 = 88
5422 09:26:21.997777 DQ Delay:
5423 09:26:22.000967 DQ0 =99, DQ1 =103, DQ2 =99, DQ3 =95
5424 09:26:22.004034 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5425 09:26:22.007488 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5426 09:26:22.011047 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5427 09:26:22.011227
5428 09:26:22.011361
5429 09:26:22.011477 ==
5430 09:26:22.014116 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 09:26:22.020276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 09:26:22.020368 ==
5433 09:26:22.020433
5434 09:26:22.020493
5435 09:26:22.020566 TX Vref Scan disable
5436 09:26:22.024101 == TX Byte 0 ==
5437 09:26:22.027710 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5438 09:26:22.034120 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5439 09:26:22.034200 == TX Byte 1 ==
5440 09:26:22.037236 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5441 09:26:22.043832 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5442 09:26:22.043913 ==
5443 09:26:22.046928 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 09:26:22.050494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 09:26:22.050573 ==
5446 09:26:22.050636
5447 09:26:22.050710
5448 09:26:22.053507 TX Vref Scan disable
5449 09:26:22.056846 == TX Byte 0 ==
5450 09:26:22.060391 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5451 09:26:22.064069 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5452 09:26:22.067103 == TX Byte 1 ==
5453 09:26:22.070346 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5454 09:26:22.073637 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5455 09:26:22.073719
5456 09:26:22.073785 [DATLAT]
5457 09:26:22.076736 Freq=933, CH0 RK1
5458 09:26:22.076833
5459 09:26:22.079791 DATLAT Default: 0xb
5460 09:26:22.079877 0, 0xFFFF, sum = 0
5461 09:26:22.083412 1, 0xFFFF, sum = 0
5462 09:26:22.083499 2, 0xFFFF, sum = 0
5463 09:26:22.086361 3, 0xFFFF, sum = 0
5464 09:26:22.086449 4, 0xFFFF, sum = 0
5465 09:26:22.089728 5, 0xFFFF, sum = 0
5466 09:26:22.089851 6, 0xFFFF, sum = 0
5467 09:26:22.092780 7, 0xFFFF, sum = 0
5468 09:26:22.092860 8, 0xFFFF, sum = 0
5469 09:26:22.096447 9, 0xFFFF, sum = 0
5470 09:26:22.096535 10, 0x0, sum = 1
5471 09:26:22.099393 11, 0x0, sum = 2
5472 09:26:22.099479 12, 0x0, sum = 3
5473 09:26:22.103076 13, 0x0, sum = 4
5474 09:26:22.103162 best_step = 11
5475 09:26:22.103228
5476 09:26:22.103290 ==
5477 09:26:22.106144 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 09:26:22.109814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 09:26:22.112762 ==
5480 09:26:22.112837 RX Vref Scan: 0
5481 09:26:22.112902
5482 09:26:22.116203 RX Vref 0 -> 0, step: 1
5483 09:26:22.116279
5484 09:26:22.119572 RX Delay -61 -> 252, step: 4
5485 09:26:22.122890 iDelay=195, Bit 0, Center 100 (15 ~ 186) 172
5486 09:26:22.125952 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5487 09:26:22.132607 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5488 09:26:22.135732 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5489 09:26:22.139453 iDelay=195, Bit 4, Center 102 (15 ~ 190) 176
5490 09:26:22.142377 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5491 09:26:22.145737 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5492 09:26:22.153121 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5493 09:26:22.155399 iDelay=195, Bit 8, Center 82 (-5 ~ 170) 176
5494 09:26:22.158593 iDelay=195, Bit 9, Center 80 (-5 ~ 166) 172
5495 09:26:22.162114 iDelay=195, Bit 10, Center 92 (7 ~ 178) 172
5496 09:26:22.165098 iDelay=195, Bit 11, Center 84 (-1 ~ 170) 172
5497 09:26:22.172246 iDelay=195, Bit 12, Center 98 (15 ~ 182) 168
5498 09:26:22.175245 iDelay=195, Bit 13, Center 96 (11 ~ 182) 172
5499 09:26:22.178726 iDelay=195, Bit 14, Center 104 (19 ~ 190) 172
5500 09:26:22.181681 iDelay=195, Bit 15, Center 100 (15 ~ 186) 172
5501 09:26:22.181823 ==
5502 09:26:22.185035 Dram Type= 6, Freq= 0, CH_0, rank 1
5503 09:26:22.188753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 09:26:22.191722 ==
5505 09:26:22.191804 DQS Delay:
5506 09:26:22.191868 DQS0 = 0, DQS1 = 0
5507 09:26:22.195197 DQM Delay:
5508 09:26:22.195277 DQM0 = 100, DQM1 = 92
5509 09:26:22.198528 DQ Delay:
5510 09:26:22.201733 DQ0 =100, DQ1 =102, DQ2 =96, DQ3 =98
5511 09:26:22.205140 DQ4 =102, DQ5 =92, DQ6 =108, DQ7 =108
5512 09:26:22.208368 DQ8 =82, DQ9 =80, DQ10 =92, DQ11 =84
5513 09:26:22.211508 DQ12 =98, DQ13 =96, DQ14 =104, DQ15 =100
5514 09:26:22.211593
5515 09:26:22.211659
5516 09:26:22.218051 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5517 09:26:22.221174 CH0 RK1: MR19=505, MR18=1A17
5518 09:26:22.228233 CH0_RK1: MR19=0x505, MR18=0x1A17, DQSOSC=413, MR23=63, INC=63, DEC=42
5519 09:26:22.231328 [RxdqsGatingPostProcess] freq 933
5520 09:26:22.237804 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5521 09:26:22.237896 best DQS0 dly(2T, 0.5T) = (0, 10)
5522 09:26:22.241372 best DQS1 dly(2T, 0.5T) = (0, 11)
5523 09:26:22.244457 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5524 09:26:22.248077 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5525 09:26:22.251152 best DQS0 dly(2T, 0.5T) = (0, 10)
5526 09:26:22.254155 best DQS1 dly(2T, 0.5T) = (0, 10)
5527 09:26:22.257688 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5528 09:26:22.261011 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5529 09:26:22.264181 Pre-setting of DQS Precalculation
5530 09:26:22.270861 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5531 09:26:22.270947 ==
5532 09:26:22.274363 Dram Type= 6, Freq= 0, CH_1, rank 0
5533 09:26:22.277529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 09:26:22.277637 ==
5535 09:26:22.283843 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5536 09:26:22.290938 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5537 09:26:22.294037 [CA 0] Center 36 (6~67) winsize 62
5538 09:26:22.297154 [CA 1] Center 36 (6~67) winsize 62
5539 09:26:22.300166 [CA 2] Center 34 (4~65) winsize 62
5540 09:26:22.303588 [CA 3] Center 34 (4~64) winsize 61
5541 09:26:22.306959 [CA 4] Center 34 (4~65) winsize 62
5542 09:26:22.307049 [CA 5] Center 33 (3~64) winsize 62
5543 09:26:22.310539
5544 09:26:22.313681 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5545 09:26:22.313767
5546 09:26:22.316579 [CATrainingPosCal] consider 1 rank data
5547 09:26:22.320413 u2DelayCellTimex100 = 270/100 ps
5548 09:26:22.323536 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5549 09:26:22.326584 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5550 09:26:22.329869 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5551 09:26:22.333552 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5552 09:26:22.336723 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5553 09:26:22.339855 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5554 09:26:22.339941
5555 09:26:22.346517 CA PerBit enable=1, Macro0, CA PI delay=33
5556 09:26:22.346638
5557 09:26:22.346727 [CBTSetCACLKResult] CA Dly = 33
5558 09:26:22.349571 CS Dly: 5 (0~36)
5559 09:26:22.349656 ==
5560 09:26:22.353346 Dram Type= 6, Freq= 0, CH_1, rank 1
5561 09:26:22.356432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 09:26:22.356518 ==
5563 09:26:22.363300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5564 09:26:22.369386 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5565 09:26:22.372786 [CA 0] Center 36 (6~66) winsize 61
5566 09:26:22.375998 [CA 1] Center 36 (6~67) winsize 62
5567 09:26:22.379460 [CA 2] Center 34 (4~65) winsize 62
5568 09:26:22.382695 [CA 3] Center 33 (3~64) winsize 62
5569 09:26:22.386241 [CA 4] Center 33 (3~64) winsize 62
5570 09:26:22.389439 [CA 5] Center 33 (3~64) winsize 62
5571 09:26:22.389527
5572 09:26:22.392452 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5573 09:26:22.392562
5574 09:26:22.396028 [CATrainingPosCal] consider 2 rank data
5575 09:26:22.399547 u2DelayCellTimex100 = 270/100 ps
5576 09:26:22.402479 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5577 09:26:22.406174 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5578 09:26:22.409072 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5579 09:26:22.412522 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5580 09:26:22.415803 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5581 09:26:22.422291 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5582 09:26:22.422375
5583 09:26:22.426013 CA PerBit enable=1, Macro0, CA PI delay=33
5584 09:26:22.426096
5585 09:26:22.429063 [CBTSetCACLKResult] CA Dly = 33
5586 09:26:22.429159 CS Dly: 5 (0~37)
5587 09:26:22.429226
5588 09:26:22.432278 ----->DramcWriteLeveling(PI) begin...
5589 09:26:22.432361 ==
5590 09:26:22.435196 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 09:26:22.442392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 09:26:22.442480 ==
5593 09:26:22.445186 Write leveling (Byte 0): 26 => 26
5594 09:26:22.448789 Write leveling (Byte 1): 28 => 28
5595 09:26:22.448871 DramcWriteLeveling(PI) end<-----
5596 09:26:22.448936
5597 09:26:22.451803 ==
5598 09:26:22.455482 Dram Type= 6, Freq= 0, CH_1, rank 0
5599 09:26:22.458694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5600 09:26:22.458776 ==
5601 09:26:22.461703 [Gating] SW mode calibration
5602 09:26:22.468437 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5603 09:26:22.471498 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5604 09:26:22.478228 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5605 09:26:22.481157 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 09:26:22.484627 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 09:26:22.491257 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 09:26:22.494784 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 09:26:22.498195 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 09:26:22.504250 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5611 09:26:22.508003 0 14 28 | B1->B0 | 2b2b 2323 | 0 1 | (0 1) (1 0)
5612 09:26:22.510980 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5613 09:26:22.517487 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 09:26:22.520825 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 09:26:22.524156 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 09:26:22.530701 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 09:26:22.534446 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 09:26:22.537539 0 15 24 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
5619 09:26:22.543653 0 15 28 | B1->B0 | 3939 4444 | 0 0 | (1 1) (0 0)
5620 09:26:22.547718 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 09:26:22.553708 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 09:26:22.557245 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 09:26:22.560465 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 09:26:22.563510 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 09:26:22.570275 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 09:26:22.573390 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 09:26:22.580135 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5628 09:26:22.583216 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 09:26:22.586331 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 09:26:22.593175 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 09:26:22.596238 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 09:26:22.599936 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 09:26:22.606615 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 09:26:22.609639 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 09:26:22.612777 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 09:26:22.619586 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 09:26:22.622984 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 09:26:22.626290 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 09:26:22.633049 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 09:26:22.636279 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 09:26:22.639423 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 09:26:22.645763 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 09:26:22.649406 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5644 09:26:22.652459 Total UI for P1: 0, mck2ui 16
5645 09:26:22.655923 best dqsien dly found for B1: ( 1, 2, 26)
5646 09:26:22.658884 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5647 09:26:22.662564 Total UI for P1: 0, mck2ui 16
5648 09:26:22.665616 best dqsien dly found for B0: ( 1, 2, 28)
5649 09:26:22.668739 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5650 09:26:22.672414 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5651 09:26:22.672500
5652 09:26:22.675447 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5653 09:26:22.682240 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5654 09:26:22.682325 [Gating] SW calibration Done
5655 09:26:22.685416 ==
5656 09:26:22.685502 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 09:26:22.692142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 09:26:22.692229 ==
5659 09:26:22.692315 RX Vref Scan: 0
5660 09:26:22.692396
5661 09:26:22.695156 RX Vref 0 -> 0, step: 1
5662 09:26:22.695241
5663 09:26:22.698806 RX Delay -80 -> 252, step: 8
5664 09:26:22.701826 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5665 09:26:22.705041 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5666 09:26:22.708720 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5667 09:26:22.714884 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5668 09:26:22.718126 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5669 09:26:22.721710 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5670 09:26:22.724898 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5671 09:26:22.728233 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5672 09:26:22.731416 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5673 09:26:22.738113 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5674 09:26:22.741468 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5675 09:26:22.744901 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5676 09:26:22.747946 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5677 09:26:22.751175 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5678 09:26:22.757898 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5679 09:26:22.761139 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5680 09:26:22.761225 ==
5681 09:26:22.764466 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 09:26:22.767675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 09:26:22.767775 ==
5684 09:26:22.771016 DQS Delay:
5685 09:26:22.771090 DQS0 = 0, DQS1 = 0
5686 09:26:22.771168 DQM Delay:
5687 09:26:22.774052 DQM0 = 100, DQM1 = 95
5688 09:26:22.774128 DQ Delay:
5689 09:26:22.777726 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5690 09:26:22.780837 DQ4 =99, DQ5 =107, DQ6 =111, DQ7 =99
5691 09:26:22.783994 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =87
5692 09:26:22.787594 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5693 09:26:22.787678
5694 09:26:22.790771
5695 09:26:22.790842 ==
5696 09:26:22.793980 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 09:26:22.797767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 09:26:22.797847 ==
5699 09:26:22.797910
5700 09:26:22.797969
5701 09:26:22.800897 TX Vref Scan disable
5702 09:26:22.800969 == TX Byte 0 ==
5703 09:26:22.807528 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5704 09:26:22.810559 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5705 09:26:22.810639 == TX Byte 1 ==
5706 09:26:22.817413 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5707 09:26:22.820448 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5708 09:26:22.820532 ==
5709 09:26:22.823679 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 09:26:22.826778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 09:26:22.826861 ==
5712 09:26:22.826927
5713 09:26:22.826988
5714 09:26:22.830450 TX Vref Scan disable
5715 09:26:22.833522 == TX Byte 0 ==
5716 09:26:22.836918 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5717 09:26:22.840106 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5718 09:26:22.843768 == TX Byte 1 ==
5719 09:26:22.846649 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5720 09:26:22.849881 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5721 09:26:22.849965
5722 09:26:22.853429 [DATLAT]
5723 09:26:22.853511 Freq=933, CH1 RK0
5724 09:26:22.853576
5725 09:26:22.856974 DATLAT Default: 0xd
5726 09:26:22.857057 0, 0xFFFF, sum = 0
5727 09:26:22.859801 1, 0xFFFF, sum = 0
5728 09:26:22.859892 2, 0xFFFF, sum = 0
5729 09:26:22.863271 3, 0xFFFF, sum = 0
5730 09:26:22.863355 4, 0xFFFF, sum = 0
5731 09:26:22.866397 5, 0xFFFF, sum = 0
5732 09:26:22.866481 6, 0xFFFF, sum = 0
5733 09:26:22.869912 7, 0xFFFF, sum = 0
5734 09:26:22.873191 8, 0xFFFF, sum = 0
5735 09:26:22.873332 9, 0xFFFF, sum = 0
5736 09:26:22.876332 10, 0x0, sum = 1
5737 09:26:22.876416 11, 0x0, sum = 2
5738 09:26:22.876482 12, 0x0, sum = 3
5739 09:26:22.879882 13, 0x0, sum = 4
5740 09:26:22.879964 best_step = 11
5741 09:26:22.880029
5742 09:26:22.880088 ==
5743 09:26:22.882923 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 09:26:22.889352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 09:26:22.889435 ==
5746 09:26:22.889500 RX Vref Scan: 1
5747 09:26:22.889560
5748 09:26:22.893061 RX Vref 0 -> 0, step: 1
5749 09:26:22.893143
5750 09:26:22.895896 RX Delay -61 -> 252, step: 4
5751 09:26:22.895979
5752 09:26:22.899049 Set Vref, RX VrefLevel [Byte0]: 52
5753 09:26:22.902800 [Byte1]: 49
5754 09:26:22.902883
5755 09:26:22.906012 Final RX Vref Byte 0 = 52 to rank0
5756 09:26:22.909115 Final RX Vref Byte 1 = 49 to rank0
5757 09:26:22.912408 Final RX Vref Byte 0 = 52 to rank1
5758 09:26:22.915542 Final RX Vref Byte 1 = 49 to rank1==
5759 09:26:22.919273 Dram Type= 6, Freq= 0, CH_1, rank 0
5760 09:26:22.925486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 09:26:22.925575 ==
5762 09:26:22.925641 DQS Delay:
5763 09:26:22.925706 DQS0 = 0, DQS1 = 0
5764 09:26:22.929092 DQM Delay:
5765 09:26:22.929217 DQM0 = 98, DQM1 = 94
5766 09:26:22.932213 DQ Delay:
5767 09:26:22.935831 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =98
5768 09:26:22.939000 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5769 09:26:22.942109 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5770 09:26:22.945255 DQ12 =100, DQ13 =104, DQ14 =100, DQ15 =104
5771 09:26:22.945369
5772 09:26:22.945432
5773 09:26:22.951956 [DQSOSCAuto] RK0, (LSB)MR18= 0x919, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 419 ps
5774 09:26:22.955245 CH1 RK0: MR19=505, MR18=919
5775 09:26:22.961672 CH1_RK0: MR19=0x505, MR18=0x919, DQSOSC=413, MR23=63, INC=63, DEC=42
5776 09:26:22.961765
5777 09:26:22.965283 ----->DramcWriteLeveling(PI) begin...
5778 09:26:22.965362 ==
5779 09:26:22.968151 Dram Type= 6, Freq= 0, CH_1, rank 1
5780 09:26:22.971817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 09:26:22.971905 ==
5782 09:26:22.974979 Write leveling (Byte 0): 25 => 25
5783 09:26:22.978025 Write leveling (Byte 1): 27 => 27
5784 09:26:22.981456 DramcWriteLeveling(PI) end<-----
5785 09:26:22.981530
5786 09:26:22.981604 ==
5787 09:26:22.985052 Dram Type= 6, Freq= 0, CH_1, rank 1
5788 09:26:22.988145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 09:26:22.991738 ==
5790 09:26:22.991818 [Gating] SW mode calibration
5791 09:26:23.001535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5792 09:26:23.004828 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5793 09:26:23.007931 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 09:26:23.014219 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 09:26:23.017934 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 09:26:23.021031 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 09:26:23.027812 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 09:26:23.030850 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 09:26:23.033964 0 14 24 | B1->B0 | 3232 2e2e | 1 0 | (1 1) (0 0)
5800 09:26:23.040911 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
5801 09:26:23.044535 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 09:26:23.047389 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 09:26:23.054145 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 09:26:23.057132 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 09:26:23.060805 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 09:26:23.067025 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 09:26:23.070093 0 15 24 | B1->B0 | 2b2b 3535 | 1 1 | (0 0) (0 0)
5808 09:26:23.073522 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5809 09:26:23.080246 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 09:26:23.083861 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 09:26:23.086677 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 09:26:23.093701 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 09:26:23.096772 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 09:26:23.099978 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 09:26:23.106672 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5816 09:26:23.109660 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5817 09:26:23.112983 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 09:26:23.119694 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 09:26:23.122955 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 09:26:23.126507 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 09:26:23.133071 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 09:26:23.136010 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 09:26:23.139670 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 09:26:23.145846 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 09:26:23.149486 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 09:26:23.153039 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 09:26:23.159472 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 09:26:23.162615 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 09:26:23.165820 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 09:26:23.172706 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 09:26:23.176148 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5832 09:26:23.179274 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5833 09:26:23.186014 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 09:26:23.189044 Total UI for P1: 0, mck2ui 16
5835 09:26:23.191952 best dqsien dly found for B0: ( 1, 2, 26)
5836 09:26:23.195561 Total UI for P1: 0, mck2ui 16
5837 09:26:23.198473 best dqsien dly found for B1: ( 1, 2, 30)
5838 09:26:23.202298 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5839 09:26:23.205443 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5840 09:26:23.205519
5841 09:26:23.208572 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5842 09:26:23.212340 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5843 09:26:23.215251 [Gating] SW calibration Done
5844 09:26:23.215339 ==
5845 09:26:23.218336 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 09:26:23.222053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 09:26:23.225313 ==
5848 09:26:23.225391 RX Vref Scan: 0
5849 09:26:23.225455
5850 09:26:23.228466 RX Vref 0 -> 0, step: 1
5851 09:26:23.228550
5852 09:26:23.228613 RX Delay -80 -> 252, step: 8
5853 09:26:23.235257 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5854 09:26:23.238499 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5855 09:26:23.241998 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5856 09:26:23.244930 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5857 09:26:23.248532 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5858 09:26:23.251555 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5859 09:26:23.258261 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5860 09:26:23.261754 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5861 09:26:23.265312 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5862 09:26:23.268363 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5863 09:26:23.271627 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5864 09:26:23.277817 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5865 09:26:23.281188 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5866 09:26:23.284501 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5867 09:26:23.287601 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5868 09:26:23.291226 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5869 09:26:23.291310 ==
5870 09:26:23.294490 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 09:26:23.300852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 09:26:23.300940 ==
5873 09:26:23.301006 DQS Delay:
5874 09:26:23.304336 DQS0 = 0, DQS1 = 0
5875 09:26:23.304422 DQM Delay:
5876 09:26:23.307505 DQM0 = 97, DQM1 = 94
5877 09:26:23.307620 DQ Delay:
5878 09:26:23.311227 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5879 09:26:23.314284 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5880 09:26:23.317285 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5881 09:26:23.320998 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5882 09:26:23.321081
5883 09:26:23.321145
5884 09:26:23.321205 ==
5885 09:26:23.324015 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 09:26:23.327756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 09:26:23.327841 ==
5888 09:26:23.327905
5889 09:26:23.330904
5890 09:26:23.330985 TX Vref Scan disable
5891 09:26:23.333910 == TX Byte 0 ==
5892 09:26:23.337061 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5893 09:26:23.340704 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5894 09:26:23.344120 == TX Byte 1 ==
5895 09:26:23.347343 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5896 09:26:23.350307 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5897 09:26:23.350386 ==
5898 09:26:23.353782 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 09:26:23.360669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 09:26:23.360746 ==
5901 09:26:23.360820
5902 09:26:23.360881
5903 09:26:23.360938 TX Vref Scan disable
5904 09:26:23.364392 == TX Byte 0 ==
5905 09:26:23.368132 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5906 09:26:23.374509 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5907 09:26:23.374594 == TX Byte 1 ==
5908 09:26:23.377693 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5909 09:26:23.384626 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5910 09:26:23.384703
5911 09:26:23.384767 [DATLAT]
5912 09:26:23.384840 Freq=933, CH1 RK1
5913 09:26:23.384902
5914 09:26:23.388092 DATLAT Default: 0xb
5915 09:26:23.388164 0, 0xFFFF, sum = 0
5916 09:26:23.390911 1, 0xFFFF, sum = 0
5917 09:26:23.394292 2, 0xFFFF, sum = 0
5918 09:26:23.394401 3, 0xFFFF, sum = 0
5919 09:26:23.398172 4, 0xFFFF, sum = 0
5920 09:26:23.398252 5, 0xFFFF, sum = 0
5921 09:26:23.401609 6, 0xFFFF, sum = 0
5922 09:26:23.401688 7, 0xFFFF, sum = 0
5923 09:26:23.404729 8, 0xFFFF, sum = 0
5924 09:26:23.404820 9, 0xFFFF, sum = 0
5925 09:26:23.407611 10, 0x0, sum = 1
5926 09:26:23.407724 11, 0x0, sum = 2
5927 09:26:23.410889 12, 0x0, sum = 3
5928 09:26:23.410967 13, 0x0, sum = 4
5929 09:26:23.411039 best_step = 11
5930 09:26:23.414281
5931 09:26:23.414359 ==
5932 09:26:23.417297 Dram Type= 6, Freq= 0, CH_1, rank 1
5933 09:26:23.420959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5934 09:26:23.421048 ==
5935 09:26:23.421112 RX Vref Scan: 0
5936 09:26:23.421173
5937 09:26:23.423943 RX Vref 0 -> 0, step: 1
5938 09:26:23.424019
5939 09:26:23.427681 RX Delay -53 -> 252, step: 4
5940 09:26:23.433923 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5941 09:26:23.437626 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5942 09:26:23.440799 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5943 09:26:23.443855 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5944 09:26:23.447607 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5945 09:26:23.450598 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5946 09:26:23.457369 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5947 09:26:23.460734 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5948 09:26:23.464225 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5949 09:26:23.467233 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5950 09:26:23.470899 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5951 09:26:23.473931 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5952 09:26:23.480473 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5953 09:26:23.483537 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5954 09:26:23.487293 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5955 09:26:23.490421 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5956 09:26:23.490504 ==
5957 09:26:23.493376 Dram Type= 6, Freq= 0, CH_1, rank 1
5958 09:26:23.500381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5959 09:26:23.500469 ==
5960 09:26:23.500535 DQS Delay:
5961 09:26:23.503647 DQS0 = 0, DQS1 = 0
5962 09:26:23.503737 DQM Delay:
5963 09:26:23.503809 DQM0 = 97, DQM1 = 92
5964 09:26:23.506649 DQ Delay:
5965 09:26:23.509855 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =96
5966 09:26:23.513134 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5967 09:26:23.516454 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =86
5968 09:26:23.520152 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =100
5969 09:26:23.520265
5970 09:26:23.520367
5971 09:26:23.526323 [DQSOSCAuto] RK1, (LSB)MR18= 0x1329, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5972 09:26:23.530240 CH1 RK1: MR19=505, MR18=1329
5973 09:26:23.536502 CH1_RK1: MR19=0x505, MR18=0x1329, DQSOSC=408, MR23=63, INC=65, DEC=43
5974 09:26:23.539648 [RxdqsGatingPostProcess] freq 933
5975 09:26:23.546063 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5976 09:26:23.549694 best DQS0 dly(2T, 0.5T) = (0, 10)
5977 09:26:23.549771 best DQS1 dly(2T, 0.5T) = (0, 10)
5978 09:26:23.552817 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5979 09:26:23.555962 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5980 09:26:23.559602 best DQS0 dly(2T, 0.5T) = (0, 10)
5981 09:26:23.563065 best DQS1 dly(2T, 0.5T) = (0, 10)
5982 09:26:23.565906 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5983 09:26:23.569170 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5984 09:26:23.572682 Pre-setting of DQS Precalculation
5985 09:26:23.579072 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5986 09:26:23.585516 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5987 09:26:23.592500 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5988 09:26:23.592595
5989 09:26:23.592662
5990 09:26:23.595652 [Calibration Summary] 1866 Mbps
5991 09:26:23.595725 CH 0, Rank 0
5992 09:26:23.598726 SW Impedance : PASS
5993 09:26:23.602583 DUTY Scan : NO K
5994 09:26:23.602660 ZQ Calibration : PASS
5995 09:26:23.605682 Jitter Meter : NO K
5996 09:26:23.609528 CBT Training : PASS
5997 09:26:23.609618 Write leveling : PASS
5998 09:26:23.612446 RX DQS gating : PASS
5999 09:26:23.615905 RX DQ/DQS(RDDQC) : PASS
6000 09:26:23.615986 TX DQ/DQS : PASS
6001 09:26:23.618705 RX DATLAT : PASS
6002 09:26:23.622234 RX DQ/DQS(Engine): PASS
6003 09:26:23.622309 TX OE : NO K
6004 09:26:23.625651 All Pass.
6005 09:26:23.625725
6006 09:26:23.625798 CH 0, Rank 1
6007 09:26:23.628800 SW Impedance : PASS
6008 09:26:23.628873 DUTY Scan : NO K
6009 09:26:23.632291 ZQ Calibration : PASS
6010 09:26:23.635158 Jitter Meter : NO K
6011 09:26:23.635233 CBT Training : PASS
6012 09:26:23.638804 Write leveling : PASS
6013 09:26:23.638878 RX DQS gating : PASS
6014 09:26:23.642224 RX DQ/DQS(RDDQC) : PASS
6015 09:26:23.645232 TX DQ/DQS : PASS
6016 09:26:23.645354 RX DATLAT : PASS
6017 09:26:23.649048 RX DQ/DQS(Engine): PASS
6018 09:26:23.652062 TX OE : NO K
6019 09:26:23.652140 All Pass.
6020 09:26:23.652204
6021 09:26:23.652275 CH 1, Rank 0
6022 09:26:23.655136 SW Impedance : PASS
6023 09:26:23.658909 DUTY Scan : NO K
6024 09:26:23.658999 ZQ Calibration : PASS
6025 09:26:23.661958 Jitter Meter : NO K
6026 09:26:23.665109 CBT Training : PASS
6027 09:26:23.665251 Write leveling : PASS
6028 09:26:23.668206 RX DQS gating : PASS
6029 09:26:23.671659 RX DQ/DQS(RDDQC) : PASS
6030 09:26:23.671736 TX DQ/DQS : PASS
6031 09:26:23.675117 RX DATLAT : PASS
6032 09:26:23.678190 RX DQ/DQS(Engine): PASS
6033 09:26:23.678279 TX OE : NO K
6034 09:26:23.681589 All Pass.
6035 09:26:23.681674
6036 09:26:23.681739 CH 1, Rank 1
6037 09:26:23.685148 SW Impedance : PASS
6038 09:26:23.685270 DUTY Scan : NO K
6039 09:26:23.687927 ZQ Calibration : PASS
6040 09:26:23.691230 Jitter Meter : NO K
6041 09:26:23.691306 CBT Training : PASS
6042 09:26:23.694928 Write leveling : PASS
6043 09:26:23.698156 RX DQS gating : PASS
6044 09:26:23.698234 RX DQ/DQS(RDDQC) : PASS
6045 09:26:23.701392 TX DQ/DQS : PASS
6046 09:26:23.704421 RX DATLAT : PASS
6047 09:26:23.704511 RX DQ/DQS(Engine): PASS
6048 09:26:23.708113 TX OE : NO K
6049 09:26:23.708207 All Pass.
6050 09:26:23.708273
6051 09:26:23.711132 DramC Write-DBI off
6052 09:26:23.714273 PER_BANK_REFRESH: Hybrid Mode
6053 09:26:23.714358 TX_TRACKING: ON
6054 09:26:23.724626 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6055 09:26:23.727536 [FAST_K] Save calibration result to emmc
6056 09:26:23.731525 dramc_set_vcore_voltage set vcore to 650000
6057 09:26:23.734170 Read voltage for 400, 6
6058 09:26:23.734270 Vio18 = 0
6059 09:26:23.734336 Vcore = 650000
6060 09:26:23.737770 Vdram = 0
6061 09:26:23.737855 Vddq = 0
6062 09:26:23.737920 Vmddr = 0
6063 09:26:23.743885 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6064 09:26:23.747226 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6065 09:26:23.750777 MEM_TYPE=3, freq_sel=20
6066 09:26:23.753858 sv_algorithm_assistance_LP4_800
6067 09:26:23.757716 ============ PULL DRAM RESETB DOWN ============
6068 09:26:23.760866 ========== PULL DRAM RESETB DOWN end =========
6069 09:26:23.767042 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6070 09:26:23.770809 ===================================
6071 09:26:23.773788 LPDDR4 DRAM CONFIGURATION
6072 09:26:23.776882 ===================================
6073 09:26:23.776959 EX_ROW_EN[0] = 0x0
6074 09:26:23.780496 EX_ROW_EN[1] = 0x0
6075 09:26:23.780634 LP4Y_EN = 0x0
6076 09:26:23.783322 WORK_FSP = 0x0
6077 09:26:23.783411 WL = 0x2
6078 09:26:23.786881 RL = 0x2
6079 09:26:23.786971 BL = 0x2
6080 09:26:23.790188 RPST = 0x0
6081 09:26:23.790264 RD_PRE = 0x0
6082 09:26:23.793788 WR_PRE = 0x1
6083 09:26:23.793867 WR_PST = 0x0
6084 09:26:23.796575 DBI_WR = 0x0
6085 09:26:23.796664 DBI_RD = 0x0
6086 09:26:23.799945 OTF = 0x1
6087 09:26:23.803339 ===================================
6088 09:26:23.806481 ===================================
6089 09:26:23.806561 ANA top config
6090 09:26:23.810328 ===================================
6091 09:26:23.813123 DLL_ASYNC_EN = 0
6092 09:26:23.816405 ALL_SLAVE_EN = 1
6093 09:26:23.820153 NEW_RANK_MODE = 1
6094 09:26:23.823376 DLL_IDLE_MODE = 1
6095 09:26:23.823458 LP45_APHY_COMB_EN = 1
6096 09:26:23.826515 TX_ODT_DIS = 1
6097 09:26:23.829422 NEW_8X_MODE = 1
6098 09:26:23.832875 ===================================
6099 09:26:23.836225 ===================================
6100 09:26:23.839325 data_rate = 800
6101 09:26:23.842621 CKR = 1
6102 09:26:23.845921 DQ_P2S_RATIO = 4
6103 09:26:23.849104 ===================================
6104 09:26:23.849220 CA_P2S_RATIO = 4
6105 09:26:23.852712 DQ_CA_OPEN = 0
6106 09:26:23.855783 DQ_SEMI_OPEN = 1
6107 09:26:23.859455 CA_SEMI_OPEN = 1
6108 09:26:23.862272 CA_FULL_RATE = 0
6109 09:26:23.865878 DQ_CKDIV4_EN = 0
6110 09:26:23.865957 CA_CKDIV4_EN = 1
6111 09:26:23.868969 CA_PREDIV_EN = 0
6112 09:26:23.872167 PH8_DLY = 0
6113 09:26:23.875850 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6114 09:26:23.879062 DQ_AAMCK_DIV = 0
6115 09:26:23.882144 CA_AAMCK_DIV = 0
6116 09:26:23.882222 CA_ADMCK_DIV = 4
6117 09:26:23.885248 DQ_TRACK_CA_EN = 0
6118 09:26:23.888925 CA_PICK = 800
6119 09:26:23.892001 CA_MCKIO = 400
6120 09:26:23.895384 MCKIO_SEMI = 400
6121 09:26:23.898883 PLL_FREQ = 3016
6122 09:26:23.901909 DQ_UI_PI_RATIO = 32
6123 09:26:23.905442 CA_UI_PI_RATIO = 32
6124 09:26:23.908406 ===================================
6125 09:26:23.911738 ===================================
6126 09:26:23.911824 memory_type:LPDDR4
6127 09:26:23.915260 GP_NUM : 10
6128 09:26:23.918881 SRAM_EN : 1
6129 09:26:23.918971 MD32_EN : 0
6130 09:26:23.921918 ===================================
6131 09:26:23.924992 [ANA_INIT] >>>>>>>>>>>>>>
6132 09:26:23.928278 <<<<<< [CONFIGURE PHASE]: ANA_TX
6133 09:26:23.931970 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6134 09:26:23.934978 ===================================
6135 09:26:23.938612 data_rate = 800,PCW = 0X7400
6136 09:26:23.942111 ===================================
6137 09:26:23.945200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6138 09:26:23.948621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6139 09:26:23.961477 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6140 09:26:23.965104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6141 09:26:23.967857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6142 09:26:23.971290 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6143 09:26:23.974782 [ANA_INIT] flow start
6144 09:26:23.974885 [ANA_INIT] PLL >>>>>>>>
6145 09:26:23.977892 [ANA_INIT] PLL <<<<<<<<
6146 09:26:23.981483 [ANA_INIT] MIDPI >>>>>>>>
6147 09:26:23.984557 [ANA_INIT] MIDPI <<<<<<<<
6148 09:26:23.984677 [ANA_INIT] DLL >>>>>>>>
6149 09:26:23.987831 [ANA_INIT] flow end
6150 09:26:23.991387 ============ LP4 DIFF to SE enter ============
6151 09:26:23.994413 ============ LP4 DIFF to SE exit ============
6152 09:26:23.998009 [ANA_INIT] <<<<<<<<<<<<<
6153 09:26:24.001498 [Flow] Enable top DCM control >>>>>
6154 09:26:24.004256 [Flow] Enable top DCM control <<<<<
6155 09:26:24.007893 Enable DLL master slave shuffle
6156 09:26:24.014002 ==============================================================
6157 09:26:24.014090 Gating Mode config
6158 09:26:24.020901 ==============================================================
6159 09:26:24.021006 Config description:
6160 09:26:24.030824 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6161 09:26:24.037666 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6162 09:26:24.044207 SELPH_MODE 0: By rank 1: By Phase
6163 09:26:24.047308 ==============================================================
6164 09:26:24.051018 GAT_TRACK_EN = 0
6165 09:26:24.053860 RX_GATING_MODE = 2
6166 09:26:24.057418 RX_GATING_TRACK_MODE = 2
6167 09:26:24.060599 SELPH_MODE = 1
6168 09:26:24.063929 PICG_EARLY_EN = 1
6169 09:26:24.067476 VALID_LAT_VALUE = 1
6170 09:26:24.073657 ==============================================================
6171 09:26:24.077125 Enter into Gating configuration >>>>
6172 09:26:24.080408 Exit from Gating configuration <<<<
6173 09:26:24.084034 Enter into DVFS_PRE_config >>>>>
6174 09:26:24.093967 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6175 09:26:24.097098 Exit from DVFS_PRE_config <<<<<
6176 09:26:24.100037 Enter into PICG configuration >>>>
6177 09:26:24.103716 Exit from PICG configuration <<<<
6178 09:26:24.106535 [RX_INPUT] configuration >>>>>
6179 09:26:24.106643 [RX_INPUT] configuration <<<<<
6180 09:26:24.113631 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6181 09:26:24.119788 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6182 09:26:24.126446 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6183 09:26:24.129996 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6184 09:26:24.136503 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6185 09:26:24.142956 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6186 09:26:24.146402 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6187 09:26:24.153225 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6188 09:26:24.156241 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6189 09:26:24.159464 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6190 09:26:24.162925 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6191 09:26:24.169099 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6192 09:26:24.172782 ===================================
6193 09:26:24.172880 LPDDR4 DRAM CONFIGURATION
6194 09:26:24.175733 ===================================
6195 09:26:24.179634 EX_ROW_EN[0] = 0x0
6196 09:26:24.182783 EX_ROW_EN[1] = 0x0
6197 09:26:24.182869 LP4Y_EN = 0x0
6198 09:26:24.185670 WORK_FSP = 0x0
6199 09:26:24.185743 WL = 0x2
6200 09:26:24.189074 RL = 0x2
6201 09:26:24.189174 BL = 0x2
6202 09:26:24.192190 RPST = 0x0
6203 09:26:24.192267 RD_PRE = 0x0
6204 09:26:24.195863 WR_PRE = 0x1
6205 09:26:24.195948 WR_PST = 0x0
6206 09:26:24.198951 DBI_WR = 0x0
6207 09:26:24.199027 DBI_RD = 0x0
6208 09:26:24.202085 OTF = 0x1
6209 09:26:24.205717 ===================================
6210 09:26:24.208745 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6211 09:26:24.211870 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6212 09:26:24.218866 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6213 09:26:24.221781 ===================================
6214 09:26:24.221862 LPDDR4 DRAM CONFIGURATION
6215 09:26:24.225619 ===================================
6216 09:26:24.228622 EX_ROW_EN[0] = 0x10
6217 09:26:24.231712 EX_ROW_EN[1] = 0x0
6218 09:26:24.231788 LP4Y_EN = 0x0
6219 09:26:24.235448 WORK_FSP = 0x0
6220 09:26:24.235552 WL = 0x2
6221 09:26:24.238560 RL = 0x2
6222 09:26:24.238643 BL = 0x2
6223 09:26:24.241568 RPST = 0x0
6224 09:26:24.241658 RD_PRE = 0x0
6225 09:26:24.244951 WR_PRE = 0x1
6226 09:26:24.245035 WR_PST = 0x0
6227 09:26:24.248504 DBI_WR = 0x0
6228 09:26:24.248616 DBI_RD = 0x0
6229 09:26:24.251654 OTF = 0x1
6230 09:26:24.255112 ===================================
6231 09:26:24.261391 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6232 09:26:24.265103 nWR fixed to 30
6233 09:26:24.268114 [ModeRegInit_LP4] CH0 RK0
6234 09:26:24.268191 [ModeRegInit_LP4] CH0 RK1
6235 09:26:24.271636 [ModeRegInit_LP4] CH1 RK0
6236 09:26:24.274541 [ModeRegInit_LP4] CH1 RK1
6237 09:26:24.274616 match AC timing 19
6238 09:26:24.281548 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6239 09:26:24.284641 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6240 09:26:24.287729 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6241 09:26:24.294279 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6242 09:26:24.297629 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6243 09:26:24.297740 ==
6244 09:26:24.301090 Dram Type= 6, Freq= 0, CH_0, rank 0
6245 09:26:24.304146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 09:26:24.304227 ==
6247 09:26:24.311127 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6248 09:26:24.317491 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6249 09:26:24.321136 [CA 0] Center 36 (8~64) winsize 57
6250 09:26:24.324148 [CA 1] Center 36 (8~64) winsize 57
6251 09:26:24.327431 [CA 2] Center 36 (8~64) winsize 57
6252 09:26:24.330382 [CA 3] Center 36 (8~64) winsize 57
6253 09:26:24.334270 [CA 4] Center 36 (8~64) winsize 57
6254 09:26:24.337409 [CA 5] Center 36 (8~64) winsize 57
6255 09:26:24.337492
6256 09:26:24.340547 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6257 09:26:24.340630
6258 09:26:24.343611 [CATrainingPosCal] consider 1 rank data
6259 09:26:24.347261 u2DelayCellTimex100 = 270/100 ps
6260 09:26:24.350289 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 09:26:24.353248 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 09:26:24.356788 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 09:26:24.360127 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 09:26:24.363198 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 09:26:24.366510 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 09:26:24.366606
6267 09:26:24.373284 CA PerBit enable=1, Macro0, CA PI delay=36
6268 09:26:24.373390
6269 09:26:24.376432 [CBTSetCACLKResult] CA Dly = 36
6270 09:26:24.376508 CS Dly: 1 (0~32)
6271 09:26:24.376573 ==
6272 09:26:24.380094 Dram Type= 6, Freq= 0, CH_0, rank 1
6273 09:26:24.383077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 09:26:24.383155 ==
6275 09:26:24.389791 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6276 09:26:24.396794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6277 09:26:24.399849 [CA 0] Center 36 (8~64) winsize 57
6278 09:26:24.402853 [CA 1] Center 36 (8~64) winsize 57
6279 09:26:24.406226 [CA 2] Center 36 (8~64) winsize 57
6280 09:26:24.409653 [CA 3] Center 36 (8~64) winsize 57
6281 09:26:24.412747 [CA 4] Center 36 (8~64) winsize 57
6282 09:26:24.412839 [CA 5] Center 36 (8~64) winsize 57
6283 09:26:24.416523
6284 09:26:24.419661 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6285 09:26:24.419749
6286 09:26:24.422794 [CATrainingPosCal] consider 2 rank data
6287 09:26:24.425907 u2DelayCellTimex100 = 270/100 ps
6288 09:26:24.429596 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 09:26:24.432582 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 09:26:24.435956 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 09:26:24.439241 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 09:26:24.442923 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 09:26:24.445939 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 09:26:24.446027
6295 09:26:24.449095 CA PerBit enable=1, Macro0, CA PI delay=36
6296 09:26:24.452741
6297 09:26:24.452817 [CBTSetCACLKResult] CA Dly = 36
6298 09:26:24.455880 CS Dly: 1 (0~32)
6299 09:26:24.455968
6300 09:26:24.458918 ----->DramcWriteLeveling(PI) begin...
6301 09:26:24.459004 ==
6302 09:26:24.462188 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 09:26:24.465397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 09:26:24.465475 ==
6305 09:26:24.468911 Write leveling (Byte 0): 40 => 8
6306 09:26:24.472044 Write leveling (Byte 1): 40 => 8
6307 09:26:24.475390 DramcWriteLeveling(PI) end<-----
6308 09:26:24.475469
6309 09:26:24.475533 ==
6310 09:26:24.478960 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 09:26:24.482307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 09:26:24.485177 ==
6313 09:26:24.485300 [Gating] SW mode calibration
6314 09:26:24.494933 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6315 09:26:24.498487 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6316 09:26:24.501928 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6317 09:26:24.508335 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6318 09:26:24.511460 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6319 09:26:24.514848 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6320 09:26:24.521319 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 09:26:24.524563 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 09:26:24.528276 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 09:26:24.534565 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 09:26:24.537684 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 09:26:24.541356 Total UI for P1: 0, mck2ui 16
6326 09:26:24.544767 best dqsien dly found for B0: ( 0, 14, 24)
6327 09:26:24.547573 Total UI for P1: 0, mck2ui 16
6328 09:26:24.551300 best dqsien dly found for B1: ( 0, 14, 24)
6329 09:26:24.554320 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6330 09:26:24.557584 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6331 09:26:24.557656
6332 09:26:24.561123 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6333 09:26:24.567402 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6334 09:26:24.567524 [Gating] SW calibration Done
6335 09:26:24.567615 ==
6336 09:26:24.571053 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 09:26:24.577384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 09:26:24.577508 ==
6339 09:26:24.577601 RX Vref Scan: 0
6340 09:26:24.577695
6341 09:26:24.581077 RX Vref 0 -> 0, step: 1
6342 09:26:24.581179
6343 09:26:24.583902 RX Delay -410 -> 252, step: 16
6344 09:26:24.587267 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6345 09:26:24.590500 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6346 09:26:24.597195 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6347 09:26:24.600779 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6348 09:26:24.603806 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6349 09:26:24.606784 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6350 09:26:24.613774 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6351 09:26:24.616700 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6352 09:26:24.620148 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6353 09:26:24.626876 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6354 09:26:24.629772 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6355 09:26:24.633422 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6356 09:26:24.636539 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6357 09:26:24.643348 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6358 09:26:24.646376 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6359 09:26:24.649997 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6360 09:26:24.650069 ==
6361 09:26:24.653021 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 09:26:24.659836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 09:26:24.659942 ==
6364 09:26:24.660034 DQS Delay:
6365 09:26:24.662886 DQS0 = 35, DQS1 = 59
6366 09:26:24.662958 DQM Delay:
6367 09:26:24.663022 DQM0 = 4, DQM1 = 17
6368 09:26:24.666082 DQ Delay:
6369 09:26:24.669629 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6370 09:26:24.669699 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6371 09:26:24.672881 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6372 09:26:24.676665 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6373 09:26:24.676752
6374 09:26:24.676821
6375 09:26:24.679760 ==
6376 09:26:24.682895 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 09:26:24.685941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 09:26:24.686043 ==
6379 09:26:24.686123
6380 09:26:24.686197
6381 09:26:24.689574 TX Vref Scan disable
6382 09:26:24.689685 == TX Byte 0 ==
6383 09:26:24.692746 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 09:26:24.699111 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 09:26:24.699255 == TX Byte 1 ==
6386 09:26:24.702560 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6387 09:26:24.709159 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6388 09:26:24.709378 ==
6389 09:26:24.712458 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 09:26:24.715840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 09:26:24.716043 ==
6392 09:26:24.716203
6393 09:26:24.716350
6394 09:26:24.719202 TX Vref Scan disable
6395 09:26:24.719550 == TX Byte 0 ==
6396 09:26:24.725408 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 09:26:24.729054 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 09:26:24.729150 == TX Byte 1 ==
6399 09:26:24.732492 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 09:26:24.738678 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 09:26:24.738826
6402 09:26:24.738902 [DATLAT]
6403 09:26:24.741829 Freq=400, CH0 RK0
6404 09:26:24.741925
6405 09:26:24.742000 DATLAT Default: 0xf
6406 09:26:24.745469 0, 0xFFFF, sum = 0
6407 09:26:24.745573 1, 0xFFFF, sum = 0
6408 09:26:24.748584 2, 0xFFFF, sum = 0
6409 09:26:24.748697 3, 0xFFFF, sum = 0
6410 09:26:24.752367 4, 0xFFFF, sum = 0
6411 09:26:24.752499 5, 0xFFFF, sum = 0
6412 09:26:24.755298 6, 0xFFFF, sum = 0
6413 09:26:24.755413 7, 0xFFFF, sum = 0
6414 09:26:24.758491 8, 0xFFFF, sum = 0
6415 09:26:24.758624 9, 0xFFFF, sum = 0
6416 09:26:24.761816 10, 0xFFFF, sum = 0
6417 09:26:24.761942 11, 0xFFFF, sum = 0
6418 09:26:24.765385 12, 0xFFFF, sum = 0
6419 09:26:24.768520 13, 0x0, sum = 1
6420 09:26:24.768680 14, 0x0, sum = 2
6421 09:26:24.768814 15, 0x0, sum = 3
6422 09:26:24.771629 16, 0x0, sum = 4
6423 09:26:24.771846 best_step = 14
6424 09:26:24.772034
6425 09:26:24.775383 ==
6426 09:26:24.778558 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 09:26:24.781342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 09:26:24.781417 ==
6429 09:26:24.781480 RX Vref Scan: 1
6430 09:26:24.781540
6431 09:26:24.784851 RX Vref 0 -> 0, step: 1
6432 09:26:24.784926
6433 09:26:24.787949 RX Delay -359 -> 252, step: 8
6434 09:26:24.788049
6435 09:26:24.791066 Set Vref, RX VrefLevel [Byte0]: 56
6436 09:26:24.794716 [Byte1]: 52
6437 09:26:24.798524
6438 09:26:24.798599 Final RX Vref Byte 0 = 56 to rank0
6439 09:26:24.801600 Final RX Vref Byte 1 = 52 to rank0
6440 09:26:24.805206 Final RX Vref Byte 0 = 56 to rank1
6441 09:26:24.808039 Final RX Vref Byte 1 = 52 to rank1==
6442 09:26:24.811728 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 09:26:24.818112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 09:26:24.818192 ==
6445 09:26:24.818259 DQS Delay:
6446 09:26:24.821501 DQS0 = 44, DQS1 = 60
6447 09:26:24.821601 DQM Delay:
6448 09:26:24.821691 DQM0 = 10, DQM1 = 16
6449 09:26:24.824815 DQ Delay:
6450 09:26:24.828054 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6451 09:26:24.831224 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6452 09:26:24.834308 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6453 09:26:24.837744 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6454 09:26:24.837818
6455 09:26:24.837880
6456 09:26:24.844345 [DQSOSCAuto] RK0, (LSB)MR18= 0x9f93, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
6457 09:26:24.847762 CH0 RK0: MR19=C0C, MR18=9F93
6458 09:26:24.854325 CH0_RK0: MR19=0xC0C, MR18=0x9F93, DQSOSC=389, MR23=63, INC=390, DEC=260
6459 09:26:24.854444 ==
6460 09:26:24.857376 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 09:26:24.861009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 09:26:24.861092 ==
6463 09:26:24.864375 [Gating] SW mode calibration
6464 09:26:24.870652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6465 09:26:24.877366 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6466 09:26:24.880391 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6467 09:26:24.886599 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6468 09:26:24.890459 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6469 09:26:24.893534 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6470 09:26:24.900134 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 09:26:24.903229 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 09:26:24.906695 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 09:26:24.913342 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 09:26:24.916383 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 09:26:24.919477 Total UI for P1: 0, mck2ui 16
6476 09:26:24.923176 best dqsien dly found for B0: ( 0, 14, 24)
6477 09:26:24.926263 Total UI for P1: 0, mck2ui 16
6478 09:26:24.929725 best dqsien dly found for B1: ( 0, 14, 24)
6479 09:26:24.932976 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6480 09:26:24.935884 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6481 09:26:24.935968
6482 09:26:24.939545 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6483 09:26:24.942406 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6484 09:26:24.945700 [Gating] SW calibration Done
6485 09:26:24.945783 ==
6486 09:26:24.948941 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 09:26:24.955708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 09:26:24.955793 ==
6489 09:26:24.955859 RX Vref Scan: 0
6490 09:26:24.955920
6491 09:26:24.958761 RX Vref 0 -> 0, step: 1
6492 09:26:24.958844
6493 09:26:24.962154 RX Delay -410 -> 252, step: 16
6494 09:26:24.965945 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6495 09:26:24.968915 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6496 09:26:24.975805 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6497 09:26:24.979016 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6498 09:26:24.982449 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6499 09:26:24.985695 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6500 09:26:24.992073 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6501 09:26:24.995065 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6502 09:26:24.998765 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6503 09:26:25.001844 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6504 09:26:25.008678 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6505 09:26:25.011646 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6506 09:26:25.015065 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6507 09:26:25.021378 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6508 09:26:25.025127 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6509 09:26:25.028150 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6510 09:26:25.028233 ==
6511 09:26:25.031255 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 09:26:25.034569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 09:26:25.034662 ==
6514 09:26:25.038116 DQS Delay:
6515 09:26:25.038199 DQS0 = 35, DQS1 = 51
6516 09:26:25.041139 DQM Delay:
6517 09:26:25.041251 DQM0 = 6, DQM1 = 10
6518 09:26:25.044442 DQ Delay:
6519 09:26:25.044525 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6520 09:26:25.047937 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6521 09:26:25.050958 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6522 09:26:25.054520 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6523 09:26:25.054602
6524 09:26:25.054667
6525 09:26:25.054728 ==
6526 09:26:25.057521 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 09:26:25.064124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 09:26:25.064208 ==
6529 09:26:25.064273
6530 09:26:25.064333
6531 09:26:25.064390 TX Vref Scan disable
6532 09:26:25.067410 == TX Byte 0 ==
6533 09:26:25.070680 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6534 09:26:25.074366 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6535 09:26:25.077506 == TX Byte 1 ==
6536 09:26:25.081114 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6537 09:26:25.084004 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6538 09:26:25.087476 ==
6539 09:26:25.091034 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 09:26:25.094512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 09:26:25.094595 ==
6542 09:26:25.094660
6543 09:26:25.094756
6544 09:26:25.097173 TX Vref Scan disable
6545 09:26:25.097314 == TX Byte 0 ==
6546 09:26:25.100260 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6547 09:26:25.107085 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6548 09:26:25.107169 == TX Byte 1 ==
6549 09:26:25.110219 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6550 09:26:25.117201 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6551 09:26:25.117324
6552 09:26:25.117390 [DATLAT]
6553 09:26:25.117451 Freq=400, CH0 RK1
6554 09:26:25.117509
6555 09:26:25.120119 DATLAT Default: 0xe
6556 09:26:25.123270 0, 0xFFFF, sum = 0
6557 09:26:25.123355 1, 0xFFFF, sum = 0
6558 09:26:25.126976 2, 0xFFFF, sum = 0
6559 09:26:25.127060 3, 0xFFFF, sum = 0
6560 09:26:25.130076 4, 0xFFFF, sum = 0
6561 09:26:25.130160 5, 0xFFFF, sum = 0
6562 09:26:25.133180 6, 0xFFFF, sum = 0
6563 09:26:25.133324 7, 0xFFFF, sum = 0
6564 09:26:25.136290 8, 0xFFFF, sum = 0
6565 09:26:25.136375 9, 0xFFFF, sum = 0
6566 09:26:25.139974 10, 0xFFFF, sum = 0
6567 09:26:25.140058 11, 0xFFFF, sum = 0
6568 09:26:25.142920 12, 0xFFFF, sum = 0
6569 09:26:25.143005 13, 0x0, sum = 1
6570 09:26:25.146219 14, 0x0, sum = 2
6571 09:26:25.146302 15, 0x0, sum = 3
6572 09:26:25.149922 16, 0x0, sum = 4
6573 09:26:25.150006 best_step = 14
6574 09:26:25.150071
6575 09:26:25.150132 ==
6576 09:26:25.152906 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 09:26:25.159525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 09:26:25.159609 ==
6579 09:26:25.159674 RX Vref Scan: 0
6580 09:26:25.159734
6581 09:26:25.163038 RX Vref 0 -> 0, step: 1
6582 09:26:25.163131
6583 09:26:25.166060 RX Delay -343 -> 252, step: 8
6584 09:26:25.173023 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6585 09:26:25.176029 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6586 09:26:25.179541 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6587 09:26:25.182553 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
6588 09:26:25.189248 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6589 09:26:25.192731 iDelay=217, Bit 5, Center -44 (-279 ~ 192) 472
6590 09:26:25.195849 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6591 09:26:25.199301 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6592 09:26:25.205607 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6593 09:26:25.208847 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6594 09:26:25.212385 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6595 09:26:25.219162 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6596 09:26:25.222186 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6597 09:26:25.225351 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6598 09:26:25.228665 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6599 09:26:25.235483 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6600 09:26:25.235562 ==
6601 09:26:25.238536 Dram Type= 6, Freq= 0, CH_0, rank 1
6602 09:26:25.241711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 09:26:25.241787 ==
6604 09:26:25.241850 DQS Delay:
6605 09:26:25.245287 DQS0 = 44, DQS1 = 60
6606 09:26:25.245375 DQM Delay:
6607 09:26:25.248363 DQM0 = 10, DQM1 = 15
6608 09:26:25.248435 DQ Delay:
6609 09:26:25.251821 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6610 09:26:25.255090 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6611 09:26:25.258254 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6612 09:26:25.261730 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6613 09:26:25.261805
6614 09:26:25.261867
6615 09:26:25.271737 [DQSOSCAuto] RK1, (LSB)MR18= 0x8b86, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6616 09:26:25.271843 CH0 RK1: MR19=C0C, MR18=8B86
6617 09:26:25.277927 CH0_RK1: MR19=0xC0C, MR18=0x8B86, DQSOSC=392, MR23=63, INC=384, DEC=256
6618 09:26:25.281589 [RxdqsGatingPostProcess] freq 400
6619 09:26:25.288192 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6620 09:26:25.291232 best DQS0 dly(2T, 0.5T) = (0, 10)
6621 09:26:25.294724 best DQS1 dly(2T, 0.5T) = (0, 10)
6622 09:26:25.297709 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6623 09:26:25.301009 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6624 09:26:25.304430 best DQS0 dly(2T, 0.5T) = (0, 10)
6625 09:26:25.307774 best DQS1 dly(2T, 0.5T) = (0, 10)
6626 09:26:25.307875 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6627 09:26:25.311155 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6628 09:26:25.314602 Pre-setting of DQS Precalculation
6629 09:26:25.320644 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6630 09:26:25.320716 ==
6631 09:26:25.324378 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 09:26:25.327468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 09:26:25.327566 ==
6634 09:26:25.333947 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6635 09:26:25.341145 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6636 09:26:25.344338 [CA 0] Center 36 (8~64) winsize 57
6637 09:26:25.347410 [CA 1] Center 36 (8~64) winsize 57
6638 09:26:25.351079 [CA 2] Center 36 (8~64) winsize 57
6639 09:26:25.351148 [CA 3] Center 36 (8~64) winsize 57
6640 09:26:25.354062 [CA 4] Center 36 (8~64) winsize 57
6641 09:26:25.357493 [CA 5] Center 36 (8~64) winsize 57
6642 09:26:25.357576
6643 09:26:25.363608 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6644 09:26:25.363691
6645 09:26:25.367324 [CATrainingPosCal] consider 1 rank data
6646 09:26:25.370573 u2DelayCellTimex100 = 270/100 ps
6647 09:26:25.373831 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 09:26:25.377417 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 09:26:25.380526 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 09:26:25.383859 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 09:26:25.387294 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 09:26:25.390645 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 09:26:25.390757
6654 09:26:25.393600 CA PerBit enable=1, Macro0, CA PI delay=36
6655 09:26:25.393723
6656 09:26:25.396677 [CBTSetCACLKResult] CA Dly = 36
6657 09:26:25.400509 CS Dly: 1 (0~32)
6658 09:26:25.400727 ==
6659 09:26:25.403916 Dram Type= 6, Freq= 0, CH_1, rank 1
6660 09:26:25.406765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 09:26:25.406967 ==
6662 09:26:25.413422 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6663 09:26:25.420467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6664 09:26:25.423277 [CA 0] Center 36 (8~64) winsize 57
6665 09:26:25.426679 [CA 1] Center 36 (8~64) winsize 57
6666 09:26:25.427056 [CA 2] Center 36 (8~64) winsize 57
6667 09:26:25.430519 [CA 3] Center 36 (8~64) winsize 57
6668 09:26:25.433556 [CA 4] Center 36 (8~64) winsize 57
6669 09:26:25.436575 [CA 5] Center 36 (8~64) winsize 57
6670 09:26:25.436999
6671 09:26:25.440129 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6672 09:26:25.440555
6673 09:26:25.446699 [CATrainingPosCal] consider 2 rank data
6674 09:26:25.447128 u2DelayCellTimex100 = 270/100 ps
6675 09:26:25.453567 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 09:26:25.456546 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 09:26:25.460289 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 09:26:25.463379 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 09:26:25.466632 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 09:26:25.470267 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 09:26:25.470788
6682 09:26:25.473296 CA PerBit enable=1, Macro0, CA PI delay=36
6683 09:26:25.473729
6684 09:26:25.476271 [CBTSetCACLKResult] CA Dly = 36
6685 09:26:25.479575 CS Dly: 1 (0~32)
6686 09:26:25.480167
6687 09:26:25.483037 ----->DramcWriteLeveling(PI) begin...
6688 09:26:25.483601 ==
6689 09:26:25.486209 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 09:26:25.489553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 09:26:25.490087 ==
6692 09:26:25.492873 Write leveling (Byte 0): 40 => 8
6693 09:26:25.496221 Write leveling (Byte 1): 40 => 8
6694 09:26:25.499432 DramcWriteLeveling(PI) end<-----
6695 09:26:25.499863
6696 09:26:25.500197 ==
6697 09:26:25.502565 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 09:26:25.505638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 09:26:25.506156 ==
6700 09:26:25.509035 [Gating] SW mode calibration
6701 09:26:25.515765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6702 09:26:25.522463 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6703 09:26:25.525324 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6704 09:26:25.532116 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6705 09:26:25.535133 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6706 09:26:25.538685 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6707 09:26:25.545559 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 09:26:25.548984 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 09:26:25.551831 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 09:26:25.558873 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 09:26:25.561937 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 09:26:25.565073 Total UI for P1: 0, mck2ui 16
6713 09:26:25.568595 best dqsien dly found for B0: ( 0, 14, 24)
6714 09:26:25.571489 Total UI for P1: 0, mck2ui 16
6715 09:26:25.575016 best dqsien dly found for B1: ( 0, 14, 24)
6716 09:26:25.577883 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6717 09:26:25.581534 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6718 09:26:25.582001
6719 09:26:25.584618 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6720 09:26:25.587622 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6721 09:26:25.591124 [Gating] SW calibration Done
6722 09:26:25.591606 ==
6723 09:26:25.594423 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 09:26:25.598112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 09:26:25.601074 ==
6726 09:26:25.601655 RX Vref Scan: 0
6727 09:26:25.602193
6728 09:26:25.604620 RX Vref 0 -> 0, step: 1
6729 09:26:25.605211
6730 09:26:25.608086 RX Delay -410 -> 252, step: 16
6731 09:26:25.611287 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6732 09:26:25.614676 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6733 09:26:25.617612 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6734 09:26:25.624176 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6735 09:26:25.628063 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6736 09:26:25.630956 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6737 09:26:25.634411 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6738 09:26:25.641006 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6739 09:26:25.644455 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6740 09:26:25.647450 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6741 09:26:25.650966 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6742 09:26:25.657740 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6743 09:26:25.660257 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6744 09:26:25.664055 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6745 09:26:25.670229 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6746 09:26:25.673869 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6747 09:26:25.674374 ==
6748 09:26:25.677018 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 09:26:25.680066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 09:26:25.680489 ==
6751 09:26:25.683484 DQS Delay:
6752 09:26:25.683904 DQS0 = 43, DQS1 = 51
6753 09:26:25.687044 DQM Delay:
6754 09:26:25.687467 DQM0 = 13, DQM1 = 13
6755 09:26:25.687813 DQ Delay:
6756 09:26:25.690186 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6757 09:26:25.692878 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6758 09:26:25.696472 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6759 09:26:25.699437 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6760 09:26:25.699519
6761 09:26:25.699584
6762 09:26:25.699672 ==
6763 09:26:25.702743 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 09:26:25.709181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 09:26:25.709322 ==
6766 09:26:25.709389
6767 09:26:25.709450
6768 09:26:25.709507 TX Vref Scan disable
6769 09:26:25.712673 == TX Byte 0 ==
6770 09:26:25.716129 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 09:26:25.719163 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 09:26:25.722766 == TX Byte 1 ==
6773 09:26:25.725833 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 09:26:25.728956 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 09:26:25.732647 ==
6776 09:26:25.732729 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 09:26:25.739121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 09:26:25.739206 ==
6779 09:26:25.739271
6780 09:26:25.739333
6781 09:26:25.742159 TX Vref Scan disable
6782 09:26:25.742259 == TX Byte 0 ==
6783 09:26:25.745958 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 09:26:25.752271 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 09:26:25.752362 == TX Byte 1 ==
6786 09:26:25.755473 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 09:26:25.762666 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 09:26:25.762814
6789 09:26:25.762911 [DATLAT]
6790 09:26:25.763005 Freq=400, CH1 RK0
6791 09:26:25.763095
6792 09:26:25.765857 DATLAT Default: 0xf
6793 09:26:25.765970 0, 0xFFFF, sum = 0
6794 09:26:25.768910 1, 0xFFFF, sum = 0
6795 09:26:25.772071 2, 0xFFFF, sum = 0
6796 09:26:25.772187 3, 0xFFFF, sum = 0
6797 09:26:25.775683 4, 0xFFFF, sum = 0
6798 09:26:25.775794 5, 0xFFFF, sum = 0
6799 09:26:25.778745 6, 0xFFFF, sum = 0
6800 09:26:25.778853 7, 0xFFFF, sum = 0
6801 09:26:25.781803 8, 0xFFFF, sum = 0
6802 09:26:25.781906 9, 0xFFFF, sum = 0
6803 09:26:25.785504 10, 0xFFFF, sum = 0
6804 09:26:25.785584 11, 0xFFFF, sum = 0
6805 09:26:25.788354 12, 0xFFFF, sum = 0
6806 09:26:25.788435 13, 0x0, sum = 1
6807 09:26:25.791914 14, 0x0, sum = 2
6808 09:26:25.792022 15, 0x0, sum = 3
6809 09:26:25.795058 16, 0x0, sum = 4
6810 09:26:25.795159 best_step = 14
6811 09:26:25.795253
6812 09:26:25.795341 ==
6813 09:26:25.798171 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 09:26:25.805036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 09:26:25.805139 ==
6816 09:26:25.805236 RX Vref Scan: 1
6817 09:26:25.805377
6818 09:26:25.808534 RX Vref 0 -> 0, step: 1
6819 09:26:25.808612
6820 09:26:25.811354 RX Delay -343 -> 252, step: 8
6821 09:26:25.811456
6822 09:26:25.814882 Set Vref, RX VrefLevel [Byte0]: 52
6823 09:26:25.817941 [Byte1]: 49
6824 09:26:25.818044
6825 09:26:25.821399 Final RX Vref Byte 0 = 52 to rank0
6826 09:26:25.824808 Final RX Vref Byte 1 = 49 to rank0
6827 09:26:25.828152 Final RX Vref Byte 0 = 52 to rank1
6828 09:26:25.831227 Final RX Vref Byte 1 = 49 to rank1==
6829 09:26:25.834896 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 09:26:25.838108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 09:26:25.841166 ==
6832 09:26:25.841292 DQS Delay:
6833 09:26:25.841376 DQS0 = 44, DQS1 = 56
6834 09:26:25.844773 DQM Delay:
6835 09:26:25.844902 DQM0 = 12, DQM1 = 15
6836 09:26:25.847823 DQ Delay:
6837 09:26:25.847934 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6838 09:26:25.850989 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6839 09:26:25.854639 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6840 09:26:25.857696 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6841 09:26:25.857777
6842 09:26:25.857840
6843 09:26:25.867995 [DQSOSCAuto] RK0, (LSB)MR18= 0x7299, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6844 09:26:25.870883 CH1 RK0: MR19=C0C, MR18=7299
6845 09:26:25.877514 CH1_RK0: MR19=0xC0C, MR18=0x7299, DQSOSC=390, MR23=63, INC=388, DEC=258
6846 09:26:25.877597 ==
6847 09:26:25.881140 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 09:26:25.884322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 09:26:25.884415 ==
6850 09:26:25.887425 [Gating] SW mode calibration
6851 09:26:25.893998 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6852 09:26:25.900604 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6853 09:26:25.903656 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6854 09:26:25.907307 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6855 09:26:25.913991 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6856 09:26:25.916912 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6857 09:26:25.920755 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 09:26:25.926738 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 09:26:25.930321 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 09:26:25.933418 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 09:26:25.940318 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 09:26:25.940398 Total UI for P1: 0, mck2ui 16
6863 09:26:25.946604 best dqsien dly found for B0: ( 0, 14, 24)
6864 09:26:25.946686 Total UI for P1: 0, mck2ui 16
6865 09:26:25.950239 best dqsien dly found for B1: ( 0, 14, 24)
6866 09:26:25.956832 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6867 09:26:25.960003 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6868 09:26:25.960085
6869 09:26:25.963102 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6870 09:26:25.966098 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6871 09:26:25.969844 [Gating] SW calibration Done
6872 09:26:25.969925 ==
6873 09:26:25.972852 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 09:26:25.976399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 09:26:25.976481 ==
6876 09:26:25.979187 RX Vref Scan: 0
6877 09:26:25.979268
6878 09:26:25.979332 RX Vref 0 -> 0, step: 1
6879 09:26:25.982705
6880 09:26:25.982832 RX Delay -410 -> 252, step: 16
6881 09:26:25.989145 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6882 09:26:25.992578 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6883 09:26:25.995638 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6884 09:26:25.999189 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6885 09:26:26.005688 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6886 09:26:26.009220 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6887 09:26:26.012467 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6888 09:26:26.015552 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6889 09:26:26.022276 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6890 09:26:26.025854 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6891 09:26:26.028598 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6892 09:26:26.035571 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6893 09:26:26.038634 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6894 09:26:26.042150 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6895 09:26:26.045018 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6896 09:26:26.051756 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6897 09:26:26.051863 ==
6898 09:26:26.054762 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 09:26:26.058379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 09:26:26.058480 ==
6901 09:26:26.058579 DQS Delay:
6902 09:26:26.061918 DQS0 = 43, DQS1 = 51
6903 09:26:26.062019 DQM Delay:
6904 09:26:26.064672 DQM0 = 8, DQM1 = 13
6905 09:26:26.064770 DQ Delay:
6906 09:26:26.068321 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6907 09:26:26.071492 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6908 09:26:26.074698 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6909 09:26:26.078406 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6910 09:26:26.078516
6911 09:26:26.078609
6912 09:26:26.078712 ==
6913 09:26:26.081501 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 09:26:26.084433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 09:26:26.084508 ==
6916 09:26:26.088387
6917 09:26:26.088479
6918 09:26:26.088545 TX Vref Scan disable
6919 09:26:26.091643 == TX Byte 0 ==
6920 09:26:26.094888 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6921 09:26:26.097625 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6922 09:26:26.100917 == TX Byte 1 ==
6923 09:26:26.104201 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6924 09:26:26.107534 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6925 09:26:26.107610 ==
6926 09:26:26.110955 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 09:26:26.113980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 09:26:26.117133 ==
6929 09:26:26.117248
6930 09:26:26.117354
6931 09:26:26.117429 TX Vref Scan disable
6932 09:26:26.120494 == TX Byte 0 ==
6933 09:26:26.124222 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6934 09:26:26.127186 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6935 09:26:26.130257 == TX Byte 1 ==
6936 09:26:26.133860 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6937 09:26:26.137186 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6938 09:26:26.137291
6939 09:26:26.140487 [DATLAT]
6940 09:26:26.140562 Freq=400, CH1 RK1
6941 09:26:26.140632
6942 09:26:26.143837 DATLAT Default: 0xe
6943 09:26:26.143938 0, 0xFFFF, sum = 0
6944 09:26:26.146696 1, 0xFFFF, sum = 0
6945 09:26:26.146804 2, 0xFFFF, sum = 0
6946 09:26:26.150209 3, 0xFFFF, sum = 0
6947 09:26:26.150367 4, 0xFFFF, sum = 0
6948 09:26:26.153786 5, 0xFFFF, sum = 0
6949 09:26:26.153862 6, 0xFFFF, sum = 0
6950 09:26:26.156688 7, 0xFFFF, sum = 0
6951 09:26:26.156793 8, 0xFFFF, sum = 0
6952 09:26:26.160339 9, 0xFFFF, sum = 0
6953 09:26:26.160445 10, 0xFFFF, sum = 0
6954 09:26:26.163482 11, 0xFFFF, sum = 0
6955 09:26:26.167148 12, 0xFFFF, sum = 0
6956 09:26:26.167253 13, 0x0, sum = 1
6957 09:26:26.170049 14, 0x0, sum = 2
6958 09:26:26.170171 15, 0x0, sum = 3
6959 09:26:26.170240 16, 0x0, sum = 4
6960 09:26:26.173176 best_step = 14
6961 09:26:26.173279
6962 09:26:26.173347 ==
6963 09:26:26.176712 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 09:26:26.179892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 09:26:26.180000 ==
6966 09:26:26.183611 RX Vref Scan: 0
6967 09:26:26.183740
6968 09:26:26.183840 RX Vref 0 -> 0, step: 1
6969 09:26:26.186666
6970 09:26:26.186782 RX Delay -343 -> 252, step: 8
6971 09:26:26.195094 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6972 09:26:26.198228 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6973 09:26:26.201832 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6974 09:26:26.205271 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6975 09:26:26.211803 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6976 09:26:26.215181 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6977 09:26:26.218016 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6978 09:26:26.221835 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6979 09:26:26.228418 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6980 09:26:26.231548 iDelay=217, Bit 9, Center -48 (-287 ~ 192) 480
6981 09:26:26.234710 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6982 09:26:26.241469 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6983 09:26:26.244487 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6984 09:26:26.247925 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6985 09:26:26.251082 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6986 09:26:26.257884 iDelay=217, Bit 15, Center -32 (-271 ~ 208) 480
6987 09:26:26.257989 ==
6988 09:26:26.261175 Dram Type= 6, Freq= 0, CH_1, rank 1
6989 09:26:26.264476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6990 09:26:26.264556 ==
6991 09:26:26.264654 DQS Delay:
6992 09:26:26.267806 DQS0 = 48, DQS1 = 56
6993 09:26:26.267911 DQM Delay:
6994 09:26:26.270861 DQM0 = 12, DQM1 = 15
6995 09:26:26.270963 DQ Delay:
6996 09:26:26.274490 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6997 09:26:26.277693 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6998 09:26:26.280875 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6999 09:26:26.284617 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7000 09:26:26.284691
7001 09:26:26.284753
7002 09:26:26.294084 [DQSOSCAuto] RK1, (LSB)MR18= 0x79b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
7003 09:26:26.294191 CH1 RK1: MR19=C0C, MR18=79B0
7004 09:26:26.300526 CH1_RK1: MR19=0xC0C, MR18=0x79B0, DQSOSC=387, MR23=63, INC=394, DEC=262
7005 09:26:26.304185 [RxdqsGatingPostProcess] freq 400
7006 09:26:26.310274 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7007 09:26:26.313813 best DQS0 dly(2T, 0.5T) = (0, 10)
7008 09:26:26.317182 best DQS1 dly(2T, 0.5T) = (0, 10)
7009 09:26:26.320142 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7010 09:26:26.323612 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7011 09:26:26.327042 best DQS0 dly(2T, 0.5T) = (0, 10)
7012 09:26:26.327142 best DQS1 dly(2T, 0.5T) = (0, 10)
7013 09:26:26.330599 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7014 09:26:26.333808 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7015 09:26:26.336947 Pre-setting of DQS Precalculation
7016 09:26:26.343645 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7017 09:26:26.349924 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7018 09:26:26.356811 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7019 09:26:26.356917
7020 09:26:26.357012
7021 09:26:26.360198 [Calibration Summary] 800 Mbps
7022 09:26:26.363133 CH 0, Rank 0
7023 09:26:26.363233 SW Impedance : PASS
7024 09:26:26.366491 DUTY Scan : NO K
7025 09:26:26.369707 ZQ Calibration : PASS
7026 09:26:26.369798 Jitter Meter : NO K
7027 09:26:26.373209 CBT Training : PASS
7028 09:26:26.376543 Write leveling : PASS
7029 09:26:26.376617 RX DQS gating : PASS
7030 09:26:26.379928 RX DQ/DQS(RDDQC) : PASS
7031 09:26:26.380029 TX DQ/DQS : PASS
7032 09:26:26.382860 RX DATLAT : PASS
7033 09:26:26.386520 RX DQ/DQS(Engine): PASS
7034 09:26:26.386622 TX OE : NO K
7035 09:26:26.389734 All Pass.
7036 09:26:26.389838
7037 09:26:26.389930 CH 0, Rank 1
7038 09:26:26.392732 SW Impedance : PASS
7039 09:26:26.392832 DUTY Scan : NO K
7040 09:26:26.396395 ZQ Calibration : PASS
7041 09:26:26.399474 Jitter Meter : NO K
7042 09:26:26.399580 CBT Training : PASS
7043 09:26:26.402488 Write leveling : NO K
7044 09:26:26.405748 RX DQS gating : PASS
7045 09:26:26.405849 RX DQ/DQS(RDDQC) : PASS
7046 09:26:26.409459 TX DQ/DQS : PASS
7047 09:26:26.412354 RX DATLAT : PASS
7048 09:26:26.412473 RX DQ/DQS(Engine): PASS
7049 09:26:26.415938 TX OE : NO K
7050 09:26:26.416009 All Pass.
7051 09:26:26.416070
7052 09:26:26.418994 CH 1, Rank 0
7053 09:26:26.419075 SW Impedance : PASS
7054 09:26:26.422417 DUTY Scan : NO K
7055 09:26:26.425897 ZQ Calibration : PASS
7056 09:26:26.425979 Jitter Meter : NO K
7057 09:26:26.428880 CBT Training : PASS
7058 09:26:26.432425 Write leveling : PASS
7059 09:26:26.432527 RX DQS gating : PASS
7060 09:26:26.435344 RX DQ/DQS(RDDQC) : PASS
7061 09:26:26.439118 TX DQ/DQS : PASS
7062 09:26:26.439226 RX DATLAT : PASS
7063 09:26:26.442329 RX DQ/DQS(Engine): PASS
7064 09:26:26.445523 TX OE : NO K
7065 09:26:26.445610 All Pass.
7066 09:26:26.445675
7067 09:26:26.445735 CH 1, Rank 1
7068 09:26:26.448494 SW Impedance : PASS
7069 09:26:26.452279 DUTY Scan : NO K
7070 09:26:26.452380 ZQ Calibration : PASS
7071 09:26:26.455407 Jitter Meter : NO K
7072 09:26:26.458555 CBT Training : PASS
7073 09:26:26.458661 Write leveling : NO K
7074 09:26:26.461593 RX DQS gating : PASS
7075 09:26:26.465032 RX DQ/DQS(RDDQC) : PASS
7076 09:26:26.465132 TX DQ/DQS : PASS
7077 09:26:26.468523 RX DATLAT : PASS
7078 09:26:26.468597 RX DQ/DQS(Engine): PASS
7079 09:26:26.471752 TX OE : NO K
7080 09:26:26.471851 All Pass.
7081 09:26:26.471944
7082 09:26:26.475260 DramC Write-DBI off
7083 09:26:26.478063 PER_BANK_REFRESH: Hybrid Mode
7084 09:26:26.478162 TX_TRACKING: ON
7085 09:26:26.488222 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7086 09:26:26.491343 [FAST_K] Save calibration result to emmc
7087 09:26:26.494798 dramc_set_vcore_voltage set vcore to 725000
7088 09:26:26.498164 Read voltage for 1600, 0
7089 09:26:26.498239 Vio18 = 0
7090 09:26:26.501769 Vcore = 725000
7091 09:26:26.501846 Vdram = 0
7092 09:26:26.501908 Vddq = 0
7093 09:26:26.501997 Vmddr = 0
7094 09:26:26.507873 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7095 09:26:26.514953 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7096 09:26:26.515034 MEM_TYPE=3, freq_sel=13
7097 09:26:26.517915 sv_algorithm_assistance_LP4_3733
7098 09:26:26.521003 ============ PULL DRAM RESETB DOWN ============
7099 09:26:26.527851 ========== PULL DRAM RESETB DOWN end =========
7100 09:26:26.531081 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7101 09:26:26.534494 ===================================
7102 09:26:26.537546 LPDDR4 DRAM CONFIGURATION
7103 09:26:26.541050 ===================================
7104 09:26:26.541131 EX_ROW_EN[0] = 0x0
7105 09:26:26.544142 EX_ROW_EN[1] = 0x0
7106 09:26:26.547305 LP4Y_EN = 0x0
7107 09:26:26.547387 WORK_FSP = 0x1
7108 09:26:26.550460 WL = 0x5
7109 09:26:26.550541 RL = 0x5
7110 09:26:26.554176 BL = 0x2
7111 09:26:26.554257 RPST = 0x0
7112 09:26:26.557205 RD_PRE = 0x0
7113 09:26:26.557292 WR_PRE = 0x1
7114 09:26:26.560340 WR_PST = 0x1
7115 09:26:26.560422 DBI_WR = 0x0
7116 09:26:26.564065 DBI_RD = 0x0
7117 09:26:26.564147 OTF = 0x1
7118 09:26:26.567185 ===================================
7119 09:26:26.570305 ===================================
7120 09:26:26.573897 ANA top config
7121 09:26:26.576849 ===================================
7122 09:26:26.580259 DLL_ASYNC_EN = 0
7123 09:26:26.580340 ALL_SLAVE_EN = 0
7124 09:26:26.583726 NEW_RANK_MODE = 1
7125 09:26:26.586954 DLL_IDLE_MODE = 1
7126 09:26:26.590493 LP45_APHY_COMB_EN = 1
7127 09:26:26.590575 TX_ODT_DIS = 0
7128 09:26:26.593897 NEW_8X_MODE = 1
7129 09:26:26.596940 ===================================
7130 09:26:26.600035 ===================================
7131 09:26:26.603272 data_rate = 3200
7132 09:26:26.606802 CKR = 1
7133 09:26:26.609850 DQ_P2S_RATIO = 8
7134 09:26:26.613042 ===================================
7135 09:26:26.616715 CA_P2S_RATIO = 8
7136 09:26:26.619738 DQ_CA_OPEN = 0
7137 09:26:26.619820 DQ_SEMI_OPEN = 0
7138 09:26:26.623321 CA_SEMI_OPEN = 0
7139 09:26:26.626470 CA_FULL_RATE = 0
7140 09:26:26.629459 DQ_CKDIV4_EN = 0
7141 09:26:26.632712 CA_CKDIV4_EN = 0
7142 09:26:26.636267 CA_PREDIV_EN = 0
7143 09:26:26.636350 PH8_DLY = 12
7144 09:26:26.639751 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7145 09:26:26.643126 DQ_AAMCK_DIV = 4
7146 09:26:26.646014 CA_AAMCK_DIV = 4
7147 09:26:26.649479 CA_ADMCK_DIV = 4
7148 09:26:26.652504 DQ_TRACK_CA_EN = 0
7149 09:26:26.656280 CA_PICK = 1600
7150 09:26:26.656362 CA_MCKIO = 1600
7151 09:26:26.659417 MCKIO_SEMI = 0
7152 09:26:26.662425 PLL_FREQ = 3068
7153 09:26:26.665598 DQ_UI_PI_RATIO = 32
7154 09:26:26.669209 CA_UI_PI_RATIO = 0
7155 09:26:26.672261 ===================================
7156 09:26:26.675332 ===================================
7157 09:26:26.678830 memory_type:LPDDR4
7158 09:26:26.678920 GP_NUM : 10
7159 09:26:26.682346 SRAM_EN : 1
7160 09:26:26.685408 MD32_EN : 0
7161 09:26:26.688444 ===================================
7162 09:26:26.688526 [ANA_INIT] >>>>>>>>>>>>>>
7163 09:26:26.691948 <<<<<< [CONFIGURE PHASE]: ANA_TX
7164 09:26:26.695335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7165 09:26:26.698272 ===================================
7166 09:26:26.701716 data_rate = 3200,PCW = 0X7600
7167 09:26:26.705304 ===================================
7168 09:26:26.708270 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7169 09:26:26.714906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7170 09:26:26.718676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7171 09:26:26.724798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7172 09:26:26.728552 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7173 09:26:26.731845 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7174 09:26:26.731928 [ANA_INIT] flow start
7175 09:26:26.734954 [ANA_INIT] PLL >>>>>>>>
7176 09:26:26.738091 [ANA_INIT] PLL <<<<<<<<
7177 09:26:26.741647 [ANA_INIT] MIDPI >>>>>>>>
7178 09:26:26.741729 [ANA_INIT] MIDPI <<<<<<<<
7179 09:26:26.744695 [ANA_INIT] DLL >>>>>>>>
7180 09:26:26.748168 [ANA_INIT] DLL <<<<<<<<
7181 09:26:26.748250 [ANA_INIT] flow end
7182 09:26:26.751513 ============ LP4 DIFF to SE enter ============
7183 09:26:26.757817 ============ LP4 DIFF to SE exit ============
7184 09:26:26.757900 [ANA_INIT] <<<<<<<<<<<<<
7185 09:26:26.761363 [Flow] Enable top DCM control >>>>>
7186 09:26:26.764585 [Flow] Enable top DCM control <<<<<
7187 09:26:26.767712 Enable DLL master slave shuffle
7188 09:26:26.774503 ==============================================================
7189 09:26:26.777678 Gating Mode config
7190 09:26:26.780921 ==============================================================
7191 09:26:26.784431 Config description:
7192 09:26:26.794201 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7193 09:26:26.800696 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7194 09:26:26.803946 SELPH_MODE 0: By rank 1: By Phase
7195 09:26:26.810978 ==============================================================
7196 09:26:26.813940 GAT_TRACK_EN = 1
7197 09:26:26.816977 RX_GATING_MODE = 2
7198 09:26:26.820624 RX_GATING_TRACK_MODE = 2
7199 09:26:26.823799 SELPH_MODE = 1
7200 09:26:26.823901 PICG_EARLY_EN = 1
7201 09:26:26.826836 VALID_LAT_VALUE = 1
7202 09:26:26.833541 ==============================================================
7203 09:26:26.837186 Enter into Gating configuration >>>>
7204 09:26:26.840262 Exit from Gating configuration <<<<
7205 09:26:26.843350 Enter into DVFS_PRE_config >>>>>
7206 09:26:26.853108 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7207 09:26:26.856455 Exit from DVFS_PRE_config <<<<<
7208 09:26:26.860041 Enter into PICG configuration >>>>
7209 09:26:26.862930 Exit from PICG configuration <<<<
7210 09:26:26.866494 [RX_INPUT] configuration >>>>>
7211 09:26:26.869729 [RX_INPUT] configuration <<<<<
7212 09:26:26.876241 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7213 09:26:26.879985 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7214 09:26:26.886807 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7215 09:26:26.892640 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7216 09:26:26.899651 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7217 09:26:26.906406 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7218 09:26:26.909291 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7219 09:26:26.912601 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7220 09:26:26.915920 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7221 09:26:26.923035 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7222 09:26:26.925869 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7223 09:26:26.929010 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7224 09:26:26.932770 ===================================
7225 09:26:26.935702 LPDDR4 DRAM CONFIGURATION
7226 09:26:26.938892 ===================================
7227 09:26:26.942498 EX_ROW_EN[0] = 0x0
7228 09:26:26.942605 EX_ROW_EN[1] = 0x0
7229 09:26:26.945645 LP4Y_EN = 0x0
7230 09:26:26.945753 WORK_FSP = 0x1
7231 09:26:26.948722 WL = 0x5
7232 09:26:26.948832 RL = 0x5
7233 09:26:26.952471 BL = 0x2
7234 09:26:26.952556 RPST = 0x0
7235 09:26:26.955404 RD_PRE = 0x0
7236 09:26:26.955521 WR_PRE = 0x1
7237 09:26:26.958992 WR_PST = 0x1
7238 09:26:26.959116 DBI_WR = 0x0
7239 09:26:26.962446 DBI_RD = 0x0
7240 09:26:26.962602 OTF = 0x1
7241 09:26:26.965615 ===================================
7242 09:26:26.971965 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7243 09:26:26.975574 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7244 09:26:26.978618 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7245 09:26:26.981817 ===================================
7246 09:26:26.985412 LPDDR4 DRAM CONFIGURATION
7247 09:26:26.988605 ===================================
7248 09:26:26.988680 EX_ROW_EN[0] = 0x10
7249 09:26:26.992168 EX_ROW_EN[1] = 0x0
7250 09:26:26.995138 LP4Y_EN = 0x0
7251 09:26:26.995244 WORK_FSP = 0x1
7252 09:26:26.998778 WL = 0x5
7253 09:26:26.998881 RL = 0x5
7254 09:26:27.001857 BL = 0x2
7255 09:26:27.001934 RPST = 0x0
7256 09:26:27.004910 RD_PRE = 0x0
7257 09:26:27.005010 WR_PRE = 0x1
7258 09:26:27.008816 WR_PST = 0x1
7259 09:26:27.008921 DBI_WR = 0x0
7260 09:26:27.011713 DBI_RD = 0x0
7261 09:26:27.011813 OTF = 0x1
7262 09:26:27.015247 ===================================
7263 09:26:27.021769 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7264 09:26:27.021850 ==
7265 09:26:27.024799 Dram Type= 6, Freq= 0, CH_0, rank 0
7266 09:26:27.031418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7267 09:26:27.031531 ==
7268 09:26:27.031637 [Duty_Offset_Calibration]
7269 09:26:27.034478 B0:2 B1:0 CA:4
7270 09:26:27.034571
7271 09:26:27.037829 [DutyScan_Calibration_Flow] k_type=0
7272 09:26:27.046306
7273 09:26:27.046421 ==CLK 0==
7274 09:26:27.050046 Final CLK duty delay cell = -4
7275 09:26:27.053119 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7276 09:26:27.056780 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7277 09:26:27.059650 [-4] AVG Duty = 4937%(X100)
7278 09:26:27.059761
7279 09:26:27.063310 CH0 CLK Duty spec in!! Max-Min= 187%
7280 09:26:27.066214 [DutyScan_Calibration_Flow] ====Done====
7281 09:26:27.066315
7282 09:26:27.069239 [DutyScan_Calibration_Flow] k_type=1
7283 09:26:27.086687
7284 09:26:27.086797 ==DQS 0 ==
7285 09:26:27.089855 Final DQS duty delay cell = 0
7286 09:26:27.093594 [0] MAX Duty = 5218%(X100), DQS PI = 38
7287 09:26:27.096447 [0] MIN Duty = 5093%(X100), DQS PI = 10
7288 09:26:27.100103 [0] AVG Duty = 5155%(X100)
7289 09:26:27.100201
7290 09:26:27.100291 ==DQS 1 ==
7291 09:26:27.103046 Final DQS duty delay cell = 0
7292 09:26:27.106230 [0] MAX Duty = 5187%(X100), DQS PI = 2
7293 09:26:27.110035 [0] MIN Duty = 4938%(X100), DQS PI = 58
7294 09:26:27.113138 [0] AVG Duty = 5062%(X100)
7295 09:26:27.113273
7296 09:26:27.116084 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7297 09:26:27.116193
7298 09:26:27.119840 CH0 DQS 1 Duty spec in!! Max-Min= 249%
7299 09:26:27.122855 [DutyScan_Calibration_Flow] ====Done====
7300 09:26:27.122957
7301 09:26:27.126328 [DutyScan_Calibration_Flow] k_type=3
7302 09:26:27.143801
7303 09:26:27.143907 ==DQM 0 ==
7304 09:26:27.147129 Final DQM duty delay cell = 0
7305 09:26:27.150245 [0] MAX Duty = 5124%(X100), DQS PI = 22
7306 09:26:27.153854 [0] MIN Duty = 4844%(X100), DQS PI = 54
7307 09:26:27.156931 [0] AVG Duty = 4984%(X100)
7308 09:26:27.157031
7309 09:26:27.157123 ==DQM 1 ==
7310 09:26:27.160029 Final DQM duty delay cell = 0
7311 09:26:27.163624 [0] MAX Duty = 4969%(X100), DQS PI = 2
7312 09:26:27.167272 [0] MIN Duty = 4844%(X100), DQS PI = 10
7313 09:26:27.170341 [0] AVG Duty = 4906%(X100)
7314 09:26:27.170418
7315 09:26:27.173896 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7316 09:26:27.173973
7317 09:26:27.177044 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7318 09:26:27.180135 [DutyScan_Calibration_Flow] ====Done====
7319 09:26:27.180213
7320 09:26:27.183605 [DutyScan_Calibration_Flow] k_type=2
7321 09:26:27.201201
7322 09:26:27.201347 ==DQ 0 ==
7323 09:26:27.204637 Final DQ duty delay cell = 0
7324 09:26:27.207495 [0] MAX Duty = 5156%(X100), DQS PI = 26
7325 09:26:27.210612 [0] MIN Duty = 4938%(X100), DQS PI = 12
7326 09:26:27.210716 [0] AVG Duty = 5047%(X100)
7327 09:26:27.214293
7328 09:26:27.214401 ==DQ 1 ==
7329 09:26:27.217398 Final DQ duty delay cell = 0
7330 09:26:27.220975 [0] MAX Duty = 5187%(X100), DQS PI = 4
7331 09:26:27.224070 [0] MIN Duty = 4907%(X100), DQS PI = 32
7332 09:26:27.224171 [0] AVG Duty = 5047%(X100)
7333 09:26:27.227112
7334 09:26:27.230632 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7335 09:26:27.230740
7336 09:26:27.233965 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7337 09:26:27.237573 [DutyScan_Calibration_Flow] ====Done====
7338 09:26:27.237648 ==
7339 09:26:27.240439 Dram Type= 6, Freq= 0, CH_1, rank 0
7340 09:26:27.243919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7341 09:26:27.244022 ==
7342 09:26:27.247064 [Duty_Offset_Calibration]
7343 09:26:27.247169 B0:0 B1:-1 CA:3
7344 09:26:27.247261
7345 09:26:27.250169 [DutyScan_Calibration_Flow] k_type=0
7346 09:26:27.261115
7347 09:26:27.261222 ==CLK 0==
7348 09:26:27.264696 Final CLK duty delay cell = 0
7349 09:26:27.267688 [0] MAX Duty = 5187%(X100), DQS PI = 28
7350 09:26:27.271176 [0] MIN Duty = 5000%(X100), DQS PI = 56
7351 09:26:27.271281 [0] AVG Duty = 5093%(X100)
7352 09:26:27.274404
7353 09:26:27.277998 CH1 CLK Duty spec in!! Max-Min= 187%
7354 09:26:27.280977 [DutyScan_Calibration_Flow] ====Done====
7355 09:26:27.281102
7356 09:26:27.284673 [DutyScan_Calibration_Flow] k_type=1
7357 09:26:27.300150
7358 09:26:27.300263 ==DQS 0 ==
7359 09:26:27.303263 Final DQS duty delay cell = 0
7360 09:26:27.306787 [0] MAX Duty = 5218%(X100), DQS PI = 30
7361 09:26:27.309755 [0] MIN Duty = 4907%(X100), DQS PI = 56
7362 09:26:27.313456 [0] AVG Duty = 5062%(X100)
7363 09:26:27.313544
7364 09:26:27.313657 ==DQS 1 ==
7365 09:26:27.316509 Final DQS duty delay cell = -4
7366 09:26:27.319661 [-4] MAX Duty = 4969%(X100), DQS PI = 8
7367 09:26:27.323333 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7368 09:26:27.326415 [-4] AVG Duty = 4891%(X100)
7369 09:26:27.326518
7370 09:26:27.329879 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7371 09:26:27.329979
7372 09:26:27.332880 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7373 09:26:27.336017 [DutyScan_Calibration_Flow] ====Done====
7374 09:26:27.336118
7375 09:26:27.339691 [DutyScan_Calibration_Flow] k_type=3
7376 09:26:27.357222
7377 09:26:27.357336 ==DQM 0 ==
7378 09:26:27.360306 Final DQM duty delay cell = 0
7379 09:26:27.364005 [0] MAX Duty = 5031%(X100), DQS PI = 30
7380 09:26:27.367301 [0] MIN Duty = 4782%(X100), DQS PI = 40
7381 09:26:27.370173 [0] AVG Duty = 4906%(X100)
7382 09:26:27.370274
7383 09:26:27.370368 ==DQM 1 ==
7384 09:26:27.373756 Final DQM duty delay cell = 0
7385 09:26:27.377349 [0] MAX Duty = 4969%(X100), DQS PI = 30
7386 09:26:27.380246 [0] MIN Duty = 4813%(X100), DQS PI = 60
7387 09:26:27.383753 [0] AVG Duty = 4891%(X100)
7388 09:26:27.383872
7389 09:26:27.386816 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7390 09:26:27.386912
7391 09:26:27.390024 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7392 09:26:27.393679 [DutyScan_Calibration_Flow] ====Done====
7393 09:26:27.393762
7394 09:26:27.396816 [DutyScan_Calibration_Flow] k_type=2
7395 09:26:27.413660
7396 09:26:27.413762 ==DQ 0 ==
7397 09:26:27.416769 Final DQ duty delay cell = -4
7398 09:26:27.419832 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7399 09:26:27.423593 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7400 09:26:27.426710 [-4] AVG Duty = 4891%(X100)
7401 09:26:27.426810
7402 09:26:27.426913 ==DQ 1 ==
7403 09:26:27.430043 Final DQ duty delay cell = 0
7404 09:26:27.433199 [0] MAX Duty = 5031%(X100), DQS PI = 30
7405 09:26:27.436923 [0] MIN Duty = 4844%(X100), DQS PI = 60
7406 09:26:27.439962 [0] AVG Duty = 4937%(X100)
7407 09:26:27.440066
7408 09:26:27.443451 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7409 09:26:27.443561
7410 09:26:27.446532 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7411 09:26:27.449712 [DutyScan_Calibration_Flow] ====Done====
7412 09:26:27.453172 nWR fixed to 30
7413 09:26:27.456667 [ModeRegInit_LP4] CH0 RK0
7414 09:26:27.456767 [ModeRegInit_LP4] CH0 RK1
7415 09:26:27.459678 [ModeRegInit_LP4] CH1 RK0
7416 09:26:27.463468 [ModeRegInit_LP4] CH1 RK1
7417 09:26:27.463577 match AC timing 5
7418 09:26:27.469748 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7419 09:26:27.473346 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7420 09:26:27.476302 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7421 09:26:27.483062 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7422 09:26:27.486262 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7423 09:26:27.486366 [MiockJmeterHQA]
7424 09:26:27.486459
7425 09:26:27.489489 [DramcMiockJmeter] u1RxGatingPI = 0
7426 09:26:27.493017 0 : 4258, 4029
7427 09:26:27.493128 4 : 4257, 4029
7428 09:26:27.496157 8 : 4367, 4140
7429 09:26:27.496261 12 : 4252, 4027
7430 09:26:27.499311 16 : 4253, 4026
7431 09:26:27.499413 20 : 4253, 4027
7432 09:26:27.499520 24 : 4253, 4026
7433 09:26:27.503030 28 : 4252, 4027
7434 09:26:27.503132 32 : 4255, 4029
7435 09:26:27.505945 36 : 4363, 4137
7436 09:26:27.506048 40 : 4252, 4027
7437 09:26:27.509047 44 : 4253, 4026
7438 09:26:27.509163 48 : 4252, 4027
7439 09:26:27.512573 52 : 4255, 4029
7440 09:26:27.512680 56 : 4250, 4026
7441 09:26:27.512774 60 : 4360, 4137
7442 09:26:27.516239 64 : 4250, 4026
7443 09:26:27.516348 68 : 4252, 4029
7444 09:26:27.519228 72 : 4250, 4027
7445 09:26:27.519331 76 : 4252, 4029
7446 09:26:27.522344 80 : 4250, 4027
7447 09:26:27.522435 84 : 4257, 4031
7448 09:26:27.526069 88 : 4250, 4027
7449 09:26:27.526153 92 : 4250, 4027
7450 09:26:27.526219 96 : 4252, 2295
7451 09:26:27.529177 100 : 4250, 0
7452 09:26:27.529283 104 : 4250, 0
7453 09:26:27.532296 108 : 4252, 0
7454 09:26:27.532379 112 : 4249, 0
7455 09:26:27.532445 116 : 4250, 0
7456 09:26:27.535888 120 : 4253, 0
7457 09:26:27.535971 124 : 4360, 0
7458 09:26:27.538890 128 : 4250, 0
7459 09:26:27.538973 132 : 4360, 0
7460 09:26:27.539038 136 : 4250, 0
7461 09:26:27.542047 140 : 4361, 0
7462 09:26:27.542129 144 : 4250, 0
7463 09:26:27.545709 148 : 4252, 0
7464 09:26:27.545792 152 : 4249, 0
7465 09:26:27.545857 156 : 4250, 0
7466 09:26:27.548678 160 : 4253, 0
7467 09:26:27.548760 164 : 4249, 0
7468 09:26:27.552391 168 : 4250, 0
7469 09:26:27.552473 172 : 4252, 0
7470 09:26:27.552539 176 : 4250, 0
7471 09:26:27.555510 180 : 4361, 0
7472 09:26:27.555594 184 : 4250, 0
7473 09:26:27.555659 188 : 4255, 0
7474 09:26:27.559016 192 : 4361, 0
7475 09:26:27.559099 196 : 4360, 0
7476 09:26:27.561995 200 : 4255, 0
7477 09:26:27.562078 204 : 4250, 0
7478 09:26:27.562144 208 : 4255, 0
7479 09:26:27.565684 212 : 4255, 0
7480 09:26:27.565766 216 : 4250, 0
7481 09:26:27.568832 220 : 4250, 757
7482 09:26:27.568915 224 : 4360, 4128
7483 09:26:27.571885 228 : 4250, 4027
7484 09:26:27.571968 232 : 4361, 4137
7485 09:26:27.575328 236 : 4363, 4137
7486 09:26:27.575410 240 : 4250, 4027
7487 09:26:27.575476 244 : 4250, 4027
7488 09:26:27.578349 248 : 4255, 4031
7489 09:26:27.578432 252 : 4250, 4026
7490 09:26:27.582095 256 : 4249, 4027
7491 09:26:27.582178 260 : 4250, 4027
7492 09:26:27.585223 264 : 4255, 4031
7493 09:26:27.585343 268 : 4250, 4026
7494 09:26:27.588316 272 : 4361, 4137
7495 09:26:27.588399 276 : 4361, 4137
7496 09:26:27.591714 280 : 4250, 4026
7497 09:26:27.591797 284 : 4250, 4026
7498 09:26:27.595372 288 : 4361, 4137
7499 09:26:27.595455 292 : 4250, 4027
7500 09:26:27.598049 296 : 4250, 4026
7501 09:26:27.598132 300 : 4250, 4026
7502 09:26:27.602006 304 : 4250, 4027
7503 09:26:27.602088 308 : 4250, 4027
7504 09:26:27.602154 312 : 4250, 4027
7505 09:26:27.604759 316 : 4250, 4027
7506 09:26:27.604841 320 : 4250, 4026
7507 09:26:27.608138 324 : 4361, 4137
7508 09:26:27.608221 328 : 4360, 4138
7509 09:26:27.611767 332 : 4247, 3947
7510 09:26:27.611849 336 : 4250, 1569
7511 09:26:27.611914
7512 09:26:27.615177 MIOCK jitter meter ch=0
7513 09:26:27.615259
7514 09:26:27.618274 1T = (336-100) = 236 dly cells
7515 09:26:27.624858 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7516 09:26:27.624941 ==
7517 09:26:27.628006 Dram Type= 6, Freq= 0, CH_0, rank 0
7518 09:26:27.631040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7519 09:26:27.631122 ==
7520 09:26:27.637851 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7521 09:26:27.641397 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7522 09:26:27.644499 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7523 09:26:27.651195 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7524 09:26:27.660035 [CA 0] Center 44 (14~74) winsize 61
7525 09:26:27.663061 [CA 1] Center 43 (13~74) winsize 62
7526 09:26:27.666656 [CA 2] Center 38 (9~68) winsize 60
7527 09:26:27.669891 [CA 3] Center 38 (9~68) winsize 60
7528 09:26:27.672958 [CA 4] Center 36 (7~66) winsize 60
7529 09:26:27.676624 [CA 5] Center 36 (6~66) winsize 61
7530 09:26:27.676726
7531 09:26:27.680113 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7532 09:26:27.680215
7533 09:26:27.686321 [CATrainingPosCal] consider 1 rank data
7534 09:26:27.686423 u2DelayCellTimex100 = 275/100 ps
7535 09:26:27.693039 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7536 09:26:27.696128 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7537 09:26:27.699862 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7538 09:26:27.703281 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7539 09:26:27.706304 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7540 09:26:27.709871 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7541 09:26:27.709946
7542 09:26:27.712750 CA PerBit enable=1, Macro0, CA PI delay=36
7543 09:26:27.712877
7544 09:26:27.716011 [CBTSetCACLKResult] CA Dly = 36
7545 09:26:27.719681 CS Dly: 10 (0~41)
7546 09:26:27.722635 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7547 09:26:27.726141 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7548 09:26:27.726223 ==
7549 09:26:27.729440 Dram Type= 6, Freq= 0, CH_0, rank 1
7550 09:26:27.736113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 09:26:27.736223 ==
7552 09:26:27.739159 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7553 09:26:27.745900 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7554 09:26:27.748948 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7555 09:26:27.755927 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7556 09:26:27.763557 [CA 0] Center 44 (14~75) winsize 62
7557 09:26:27.766666 [CA 1] Center 44 (14~74) winsize 61
7558 09:26:27.770283 [CA 2] Center 39 (10~69) winsize 60
7559 09:26:27.773406 [CA 3] Center 39 (10~68) winsize 59
7560 09:26:27.776552 [CA 4] Center 37 (7~67) winsize 61
7561 09:26:27.779645 [CA 5] Center 36 (6~66) winsize 61
7562 09:26:27.779717
7563 09:26:27.783152 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7564 09:26:27.783237
7565 09:26:27.789890 [CATrainingPosCal] consider 2 rank data
7566 09:26:27.789965 u2DelayCellTimex100 = 275/100 ps
7567 09:26:27.796754 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7568 09:26:27.799718 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7569 09:26:27.802900 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7570 09:26:27.806615 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7571 09:26:27.809656 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7572 09:26:27.812692 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7573 09:26:27.812790
7574 09:26:27.816300 CA PerBit enable=1, Macro0, CA PI delay=36
7575 09:26:27.816391
7576 09:26:27.819860 [CBTSetCACLKResult] CA Dly = 36
7577 09:26:27.822700 CS Dly: 11 (0~43)
7578 09:26:27.826015 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7579 09:26:27.829151 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7580 09:26:27.829284
7581 09:26:27.832834 ----->DramcWriteLeveling(PI) begin...
7582 09:26:27.835944 ==
7583 09:26:27.839281 Dram Type= 6, Freq= 0, CH_0, rank 0
7584 09:26:27.842729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 09:26:27.842835 ==
7586 09:26:27.845891 Write leveling (Byte 0): 35 => 35
7587 09:26:27.849190 Write leveling (Byte 1): 26 => 26
7588 09:26:27.852846 DramcWriteLeveling(PI) end<-----
7589 09:26:27.852945
7590 09:26:27.853043 ==
7591 09:26:27.855900 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 09:26:27.859491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 09:26:27.859591 ==
7594 09:26:27.862698 [Gating] SW mode calibration
7595 09:26:27.869344 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7596 09:26:27.875505 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7597 09:26:27.879000 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 09:26:27.882059 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 09:26:27.888900 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7600 09:26:27.892242 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7601 09:26:27.895413 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7602 09:26:27.902236 1 4 20 | B1->B0 | 2726 3434 | 1 1 | (0 0) (1 1)
7603 09:26:27.905408 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 09:26:27.908455 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 09:26:27.914982 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7606 09:26:27.918638 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 09:26:27.921699 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
7608 09:26:27.928668 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7609 09:26:27.931642 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7610 09:26:27.934793 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
7611 09:26:27.941460 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7612 09:26:27.945099 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 09:26:27.948104 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 09:26:27.954793 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 09:26:27.958089 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7616 09:26:27.961377 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7617 09:26:27.968115 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7618 09:26:27.971353 1 6 20 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7619 09:26:27.974301 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 09:26:27.980733 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 09:26:27.984254 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 09:26:27.987356 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 09:26:27.994089 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7624 09:26:27.997580 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7625 09:26:28.000436 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7626 09:26:28.007182 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7627 09:26:28.010322 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7628 09:26:28.014095 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 09:26:28.020872 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 09:26:28.024004 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 09:26:28.026910 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 09:26:28.033828 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 09:26:28.036680 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 09:26:28.040272 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 09:26:28.046963 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 09:26:28.050096 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 09:26:28.053797 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 09:26:28.059916 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 09:26:28.063354 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7640 09:26:28.066291 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7641 09:26:28.073090 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7642 09:26:28.073196 Total UI for P1: 0, mck2ui 16
7643 09:26:28.079608 best dqsien dly found for B0: ( 1, 9, 10)
7644 09:26:28.083406 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7645 09:26:28.086323 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 09:26:28.089863 Total UI for P1: 0, mck2ui 16
7647 09:26:28.092789 best dqsien dly found for B1: ( 1, 9, 20)
7648 09:26:28.096443 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7649 09:26:28.099571 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7650 09:26:28.099669
7651 09:26:28.106251 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7652 09:26:28.109361 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7653 09:26:28.112370 [Gating] SW calibration Done
7654 09:26:28.112441 ==
7655 09:26:28.116178 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 09:26:28.119293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 09:26:28.119393 ==
7658 09:26:28.122806 RX Vref Scan: 0
7659 09:26:28.122916
7660 09:26:28.123009 RX Vref 0 -> 0, step: 1
7661 09:26:28.123106
7662 09:26:28.125908 RX Delay 0 -> 252, step: 8
7663 09:26:28.128978 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7664 09:26:28.132630 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7665 09:26:28.139183 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7666 09:26:28.142220 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7667 09:26:28.145770 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7668 09:26:28.148915 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7669 09:26:28.152005 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7670 09:26:28.158812 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7671 09:26:28.161827 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7672 09:26:28.165490 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7673 09:26:28.168438 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7674 09:26:28.174964 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7675 09:26:28.178337 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7676 09:26:28.181799 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7677 09:26:28.184652 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7678 09:26:28.188248 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7679 09:26:28.191219 ==
7680 09:26:28.194756 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 09:26:28.197720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 09:26:28.197811 ==
7683 09:26:28.197889 DQS Delay:
7684 09:26:28.201424 DQS0 = 0, DQS1 = 0
7685 09:26:28.201498 DQM Delay:
7686 09:26:28.204839 DQM0 = 131, DQM1 = 127
7687 09:26:28.204937 DQ Delay:
7688 09:26:28.207568 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7689 09:26:28.211132 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7690 09:26:28.214179 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7691 09:26:28.218023 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
7692 09:26:28.218104
7693 09:26:28.218168
7694 09:26:28.221183 ==
7695 09:26:28.224331 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 09:26:28.227845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 09:26:28.227928 ==
7698 09:26:28.227992
7699 09:26:28.228053
7700 09:26:28.231211 TX Vref Scan disable
7701 09:26:28.231293 == TX Byte 0 ==
7702 09:26:28.237800 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7703 09:26:28.240544 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7704 09:26:28.240625 == TX Byte 1 ==
7705 09:26:28.247385 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7706 09:26:28.250890 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7707 09:26:28.250973 ==
7708 09:26:28.253890 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 09:26:28.257563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 09:26:28.257645 ==
7711 09:26:28.271456
7712 09:26:28.275016 TX Vref early break, caculate TX vref
7713 09:26:28.277959 TX Vref=16, minBit 3, minWin=22, winSum=372
7714 09:26:28.281735 TX Vref=18, minBit 8, minWin=22, winSum=378
7715 09:26:28.284699 TX Vref=20, minBit 8, minWin=22, winSum=388
7716 09:26:28.287791 TX Vref=22, minBit 1, minWin=24, winSum=401
7717 09:26:28.291188 TX Vref=24, minBit 6, minWin=24, winSum=408
7718 09:26:28.297674 TX Vref=26, minBit 1, minWin=25, winSum=416
7719 09:26:28.301347 TX Vref=28, minBit 0, minWin=25, winSum=417
7720 09:26:28.304235 TX Vref=30, minBit 2, minWin=25, winSum=417
7721 09:26:28.307707 TX Vref=32, minBit 1, minWin=24, winSum=405
7722 09:26:28.310884 TX Vref=34, minBit 2, minWin=23, winSum=393
7723 09:26:28.317361 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
7724 09:26:28.317446
7725 09:26:28.320981 Final TX Range 0 Vref 28
7726 09:26:28.321063
7727 09:26:28.321128 ==
7728 09:26:28.324102 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 09:26:28.327651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 09:26:28.327733 ==
7731 09:26:28.327798
7732 09:26:28.327857
7733 09:26:28.330565 TX Vref Scan disable
7734 09:26:28.337445 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7735 09:26:28.337527 == TX Byte 0 ==
7736 09:26:28.340444 u2DelayCellOfst[0]=14 cells (4 PI)
7737 09:26:28.344008 u2DelayCellOfst[1]=17 cells (5 PI)
7738 09:26:28.347154 u2DelayCellOfst[2]=14 cells (4 PI)
7739 09:26:28.350194 u2DelayCellOfst[3]=14 cells (4 PI)
7740 09:26:28.353791 u2DelayCellOfst[4]=10 cells (3 PI)
7741 09:26:28.357117 u2DelayCellOfst[5]=0 cells (0 PI)
7742 09:26:28.360674 u2DelayCellOfst[6]=21 cells (6 PI)
7743 09:26:28.363677 u2DelayCellOfst[7]=21 cells (6 PI)
7744 09:26:28.366714 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7745 09:26:28.370295 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7746 09:26:28.373858 == TX Byte 1 ==
7747 09:26:28.377059 u2DelayCellOfst[8]=0 cells (0 PI)
7748 09:26:28.380685 u2DelayCellOfst[9]=0 cells (0 PI)
7749 09:26:28.383960 u2DelayCellOfst[10]=7 cells (2 PI)
7750 09:26:28.384042 u2DelayCellOfst[11]=0 cells (0 PI)
7751 09:26:28.386677 u2DelayCellOfst[12]=7 cells (2 PI)
7752 09:26:28.390422 u2DelayCellOfst[13]=7 cells (2 PI)
7753 09:26:28.393510 u2DelayCellOfst[14]=14 cells (4 PI)
7754 09:26:28.396538 u2DelayCellOfst[15]=10 cells (3 PI)
7755 09:26:28.403328 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7756 09:26:28.406740 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7757 09:26:28.406821 DramC Write-DBI on
7758 09:26:28.409759 ==
7759 09:26:28.409840 Dram Type= 6, Freq= 0, CH_0, rank 0
7760 09:26:28.416367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7761 09:26:28.416452 ==
7762 09:26:28.416528
7763 09:26:28.416592
7764 09:26:28.419755 TX Vref Scan disable
7765 09:26:28.419837 == TX Byte 0 ==
7766 09:26:28.426426 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7767 09:26:28.426609 == TX Byte 1 ==
7768 09:26:28.429463 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7769 09:26:28.432473 DramC Write-DBI off
7770 09:26:28.432554
7771 09:26:28.432618 [DATLAT]
7772 09:26:28.436052 Freq=1600, CH0 RK0
7773 09:26:28.436134
7774 09:26:28.436198 DATLAT Default: 0xf
7775 09:26:28.439098 0, 0xFFFF, sum = 0
7776 09:26:28.439181 1, 0xFFFF, sum = 0
7777 09:26:28.442693 2, 0xFFFF, sum = 0
7778 09:26:28.442775 3, 0xFFFF, sum = 0
7779 09:26:28.445692 4, 0xFFFF, sum = 0
7780 09:26:28.449338 5, 0xFFFF, sum = 0
7781 09:26:28.449445 6, 0xFFFF, sum = 0
7782 09:26:28.452353 7, 0xFFFF, sum = 0
7783 09:26:28.452450 8, 0xFFFF, sum = 0
7784 09:26:28.456132 9, 0xFFFF, sum = 0
7785 09:26:28.456214 10, 0xFFFF, sum = 0
7786 09:26:28.459143 11, 0xFFFF, sum = 0
7787 09:26:28.459229 12, 0xFFFF, sum = 0
7788 09:26:28.462668 13, 0xFFFF, sum = 0
7789 09:26:28.462750 14, 0x0, sum = 1
7790 09:26:28.465641 15, 0x0, sum = 2
7791 09:26:28.465724 16, 0x0, sum = 3
7792 09:26:28.469022 17, 0x0, sum = 4
7793 09:26:28.469176 best_step = 15
7794 09:26:28.469314
7795 09:26:28.469378 ==
7796 09:26:28.472172 Dram Type= 6, Freq= 0, CH_0, rank 0
7797 09:26:28.475815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7798 09:26:28.478770 ==
7799 09:26:28.478961 RX Vref Scan: 1
7800 09:26:28.479087
7801 09:26:28.482300 Set Vref Range= 24 -> 127
7802 09:26:28.482391
7803 09:26:28.485404 RX Vref 24 -> 127, step: 1
7804 09:26:28.485499
7805 09:26:28.485569 RX Delay 11 -> 252, step: 4
7806 09:26:28.485630
7807 09:26:28.489054 Set Vref, RX VrefLevel [Byte0]: 24
7808 09:26:28.491896 [Byte1]: 24
7809 09:26:28.495817
7810 09:26:28.495926 Set Vref, RX VrefLevel [Byte0]: 25
7811 09:26:28.499567 [Byte1]: 25
7812 09:26:28.503961
7813 09:26:28.504063 Set Vref, RX VrefLevel [Byte0]: 26
7814 09:26:28.507011 [Byte1]: 26
7815 09:26:28.511433
7816 09:26:28.511537 Set Vref, RX VrefLevel [Byte0]: 27
7817 09:26:28.514837 [Byte1]: 27
7818 09:26:28.518789
7819 09:26:28.518900 Set Vref, RX VrefLevel [Byte0]: 28
7820 09:26:28.522246 [Byte1]: 28
7821 09:26:28.526304
7822 09:26:28.526410 Set Vref, RX VrefLevel [Byte0]: 29
7823 09:26:28.530014 [Byte1]: 29
7824 09:26:28.534444
7825 09:26:28.534554 Set Vref, RX VrefLevel [Byte0]: 30
7826 09:26:28.537402 [Byte1]: 30
7827 09:26:28.541642
7828 09:26:28.541754 Set Vref, RX VrefLevel [Byte0]: 31
7829 09:26:28.545188 [Byte1]: 31
7830 09:26:28.549794
7831 09:26:28.549880 Set Vref, RX VrefLevel [Byte0]: 32
7832 09:26:28.552706 [Byte1]: 32
7833 09:26:28.556940
7834 09:26:28.557043 Set Vref, RX VrefLevel [Byte0]: 33
7835 09:26:28.559964 [Byte1]: 33
7836 09:26:28.564254
7837 09:26:28.564354 Set Vref, RX VrefLevel [Byte0]: 34
7838 09:26:28.567848 [Byte1]: 34
7839 09:26:28.571990
7840 09:26:28.572095 Set Vref, RX VrefLevel [Byte0]: 35
7841 09:26:28.575477 [Byte1]: 35
7842 09:26:28.580058
7843 09:26:28.580157 Set Vref, RX VrefLevel [Byte0]: 36
7844 09:26:28.582943 [Byte1]: 36
7845 09:26:28.587696
7846 09:26:28.587812 Set Vref, RX VrefLevel [Byte0]: 37
7847 09:26:28.590767 [Byte1]: 37
7848 09:26:28.595016
7849 09:26:28.595125 Set Vref, RX VrefLevel [Byte0]: 38
7850 09:26:28.598344 [Byte1]: 38
7851 09:26:28.602613
7852 09:26:28.602717 Set Vref, RX VrefLevel [Byte0]: 39
7853 09:26:28.605806 [Byte1]: 39
7854 09:26:28.610121
7855 09:26:28.610229 Set Vref, RX VrefLevel [Byte0]: 40
7856 09:26:28.613787 [Byte1]: 40
7857 09:26:28.617922
7858 09:26:28.618001 Set Vref, RX VrefLevel [Byte0]: 41
7859 09:26:28.620908 [Byte1]: 41
7860 09:26:28.625275
7861 09:26:28.625370 Set Vref, RX VrefLevel [Byte0]: 42
7862 09:26:28.628940 [Byte1]: 42
7863 09:26:28.633325
7864 09:26:28.633406 Set Vref, RX VrefLevel [Byte0]: 43
7865 09:26:28.636149 [Byte1]: 43
7866 09:26:28.640877
7867 09:26:28.640958 Set Vref, RX VrefLevel [Byte0]: 44
7868 09:26:28.643852 [Byte1]: 44
7869 09:26:28.648538
7870 09:26:28.648619 Set Vref, RX VrefLevel [Byte0]: 45
7871 09:26:28.651732 [Byte1]: 45
7872 09:26:28.655830
7873 09:26:28.655911 Set Vref, RX VrefLevel [Byte0]: 46
7874 09:26:28.659425 [Byte1]: 46
7875 09:26:28.663850
7876 09:26:28.663934 Set Vref, RX VrefLevel [Byte0]: 47
7877 09:26:28.666827 [Byte1]: 47
7878 09:26:28.671125
7879 09:26:28.671236 Set Vref, RX VrefLevel [Byte0]: 48
7880 09:26:28.674222 [Byte1]: 48
7881 09:26:28.678512
7882 09:26:28.678619 Set Vref, RX VrefLevel [Byte0]: 49
7883 09:26:28.682138 [Byte1]: 49
7884 09:26:28.686212
7885 09:26:28.686313 Set Vref, RX VrefLevel [Byte0]: 50
7886 09:26:28.689506 [Byte1]: 50
7887 09:26:28.694005
7888 09:26:28.694086 Set Vref, RX VrefLevel [Byte0]: 51
7889 09:26:28.696986 [Byte1]: 51
7890 09:26:28.701337
7891 09:26:28.701411 Set Vref, RX VrefLevel [Byte0]: 52
7892 09:26:28.704903 [Byte1]: 52
7893 09:26:28.709381
7894 09:26:28.709474 Set Vref, RX VrefLevel [Byte0]: 53
7895 09:26:28.712361 [Byte1]: 53
7896 09:26:28.716720
7897 09:26:28.716834 Set Vref, RX VrefLevel [Byte0]: 54
7898 09:26:28.723385 [Byte1]: 54
7899 09:26:28.723492
7900 09:26:28.726497 Set Vref, RX VrefLevel [Byte0]: 55
7901 09:26:28.730094 [Byte1]: 55
7902 09:26:28.730177
7903 09:26:28.733010 Set Vref, RX VrefLevel [Byte0]: 56
7904 09:26:28.736402 [Byte1]: 56
7905 09:26:28.739715
7906 09:26:28.739814 Set Vref, RX VrefLevel [Byte0]: 57
7907 09:26:28.743008 [Byte1]: 57
7908 09:26:28.747505
7909 09:26:28.747608 Set Vref, RX VrefLevel [Byte0]: 58
7910 09:26:28.750896 [Byte1]: 58
7911 09:26:28.754726
7912 09:26:28.754827 Set Vref, RX VrefLevel [Byte0]: 59
7913 09:26:28.758337 [Byte1]: 59
7914 09:26:28.762640
7915 09:26:28.762739 Set Vref, RX VrefLevel [Byte0]: 60
7916 09:26:28.765654 [Byte1]: 60
7917 09:26:28.770023
7918 09:26:28.770101 Set Vref, RX VrefLevel [Byte0]: 61
7919 09:26:28.773182 [Byte1]: 61
7920 09:26:28.777630
7921 09:26:28.777705 Set Vref, RX VrefLevel [Byte0]: 62
7922 09:26:28.781114 [Byte1]: 62
7923 09:26:28.785442
7924 09:26:28.785534 Set Vref, RX VrefLevel [Byte0]: 63
7925 09:26:28.788530 [Byte1]: 63
7926 09:26:28.792791
7927 09:26:28.792899 Set Vref, RX VrefLevel [Byte0]: 64
7928 09:26:28.796285 [Byte1]: 64
7929 09:26:28.800827
7930 09:26:28.800929 Set Vref, RX VrefLevel [Byte0]: 65
7931 09:26:28.803641 [Byte1]: 65
7932 09:26:28.808453
7933 09:26:28.808537 Set Vref, RX VrefLevel [Byte0]: 66
7934 09:26:28.811446 [Byte1]: 66
7935 09:26:28.815623
7936 09:26:28.815766 Set Vref, RX VrefLevel [Byte0]: 67
7937 09:26:28.819245 [Byte1]: 67
7938 09:26:28.823517
7939 09:26:28.823599 Set Vref, RX VrefLevel [Byte0]: 68
7940 09:26:28.826784 [Byte1]: 68
7941 09:26:28.831030
7942 09:26:28.831110 Set Vref, RX VrefLevel [Byte0]: 69
7943 09:26:28.834116 [Byte1]: 69
7944 09:26:28.838409
7945 09:26:28.838495 Set Vref, RX VrefLevel [Byte0]: 70
7946 09:26:28.842165 [Byte1]: 70
7947 09:26:28.846396
7948 09:26:28.846474 Set Vref, RX VrefLevel [Byte0]: 71
7949 09:26:28.849286 [Byte1]: 71
7950 09:26:28.853802
7951 09:26:28.853873 Set Vref, RX VrefLevel [Byte0]: 72
7952 09:26:28.856976 [Byte1]: 72
7953 09:26:28.861769
7954 09:26:28.861844 Set Vref, RX VrefLevel [Byte0]: 73
7955 09:26:28.864630 [Byte1]: 73
7956 09:26:28.869234
7957 09:26:28.869356 Set Vref, RX VrefLevel [Byte0]: 74
7958 09:26:28.872513 [Byte1]: 74
7959 09:26:28.876874
7960 09:26:28.876977 Final RX Vref Byte 0 = 55 to rank0
7961 09:26:28.880030 Final RX Vref Byte 1 = 59 to rank0
7962 09:26:28.882996 Final RX Vref Byte 0 = 55 to rank1
7963 09:26:28.886695 Final RX Vref Byte 1 = 59 to rank1==
7964 09:26:28.889797 Dram Type= 6, Freq= 0, CH_0, rank 0
7965 09:26:28.896518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7966 09:26:28.896631 ==
7967 09:26:28.896723 DQS Delay:
7968 09:26:28.899650 DQS0 = 0, DQS1 = 0
7969 09:26:28.899756 DQM Delay:
7970 09:26:28.899845 DQM0 = 128, DQM1 = 124
7971 09:26:28.903116 DQ Delay:
7972 09:26:28.906057 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7973 09:26:28.909470 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =134
7974 09:26:28.912822 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7975 09:26:28.916280 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =130
7976 09:26:28.916404
7977 09:26:28.916480
7978 09:26:28.916558
7979 09:26:28.919617 [DramC_TX_OE_Calibration] TA2
7980 09:26:28.922483 Original DQ_B0 (3 6) =30, OEN = 27
7981 09:26:28.926179 Original DQ_B1 (3 6) =30, OEN = 27
7982 09:26:28.929406 24, 0x0, End_B0=24 End_B1=24
7983 09:26:28.932528 25, 0x0, End_B0=25 End_B1=25
7984 09:26:28.932610 26, 0x0, End_B0=26 End_B1=26
7985 09:26:28.936267 27, 0x0, End_B0=27 End_B1=27
7986 09:26:28.939375 28, 0x0, End_B0=28 End_B1=28
7987 09:26:28.942537 29, 0x0, End_B0=29 End_B1=29
7988 09:26:28.942650 30, 0x0, End_B0=30 End_B1=30
7989 09:26:28.945476 31, 0x4141, End_B0=30 End_B1=30
7990 09:26:28.949262 Byte0 end_step=30 best_step=27
7991 09:26:28.952239 Byte1 end_step=30 best_step=27
7992 09:26:28.955773 Byte0 TX OE(2T, 0.5T) = (3, 3)
7993 09:26:28.958858 Byte1 TX OE(2T, 0.5T) = (3, 3)
7994 09:26:28.958974
7995 09:26:28.959070
7996 09:26:28.965238 [DQSOSCAuto] RK0, (LSB)MR18= 0x1815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7997 09:26:28.968733 CH0 RK0: MR19=303, MR18=1815
7998 09:26:28.975271 CH0_RK0: MR19=0x303, MR18=0x1815, DQSOSC=397, MR23=63, INC=23, DEC=15
7999 09:26:28.975385
8000 09:26:28.979145 ----->DramcWriteLeveling(PI) begin...
8001 09:26:28.979258 ==
8002 09:26:28.982129 Dram Type= 6, Freq= 0, CH_0, rank 1
8003 09:26:28.985167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 09:26:28.985283 ==
8005 09:26:28.988282 Write leveling (Byte 0): 33 => 33
8006 09:26:28.991945 Write leveling (Byte 1): 25 => 25
8007 09:26:28.995074 DramcWriteLeveling(PI) end<-----
8008 09:26:28.995183
8009 09:26:28.995277 ==
8010 09:26:28.998297 Dram Type= 6, Freq= 0, CH_0, rank 1
8011 09:26:29.004813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 09:26:29.004915 ==
8013 09:26:29.005013 [Gating] SW mode calibration
8014 09:26:29.014974 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8015 09:26:29.017929 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8016 09:26:29.024425 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 09:26:29.027945 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 09:26:29.031191 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8019 09:26:29.037553 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8020 09:26:29.041415 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8021 09:26:29.044403 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 09:26:29.051425 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 09:26:29.054422 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8024 09:26:29.057509 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 09:26:29.064329 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 09:26:29.067356 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8027 09:26:29.070966 1 5 12 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
8028 09:26:29.077646 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8029 09:26:29.080780 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8030 09:26:29.083834 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 09:26:29.090766 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 09:26:29.093976 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 09:26:29.097200 1 6 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8034 09:26:29.103547 1 6 8 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8035 09:26:29.107017 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8036 09:26:29.110147 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8037 09:26:29.116773 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8038 09:26:29.120469 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 09:26:29.123456 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 09:26:29.130402 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 09:26:29.133369 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8042 09:26:29.136467 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8043 09:26:29.143034 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8044 09:26:29.146294 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8045 09:26:29.149923 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8046 09:26:29.156166 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8047 09:26:29.159856 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 09:26:29.162870 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 09:26:29.169741 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 09:26:29.172727 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 09:26:29.176464 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 09:26:29.182694 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 09:26:29.185864 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 09:26:29.189480 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 09:26:29.196154 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 09:26:29.199148 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 09:26:29.202348 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 09:26:29.208837 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8059 09:26:29.212250 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8060 09:26:29.215664 Total UI for P1: 0, mck2ui 16
8061 09:26:29.218834 best dqsien dly found for B0: ( 1, 9, 8)
8062 09:26:29.222019 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8063 09:26:29.228441 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8064 09:26:29.231878 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8065 09:26:29.235135 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 09:26:29.238921 Total UI for P1: 0, mck2ui 16
8067 09:26:29.241862 best dqsien dly found for B1: ( 1, 9, 22)
8068 09:26:29.245559 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8069 09:26:29.248679 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8070 09:26:29.248780
8071 09:26:29.252214 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8072 09:26:29.258651 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8073 09:26:29.258729 [Gating] SW calibration Done
8074 09:26:29.261696 ==
8075 09:26:29.265167 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 09:26:29.268314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 09:26:29.268413 ==
8078 09:26:29.268505 RX Vref Scan: 0
8079 09:26:29.268592
8080 09:26:29.271392 RX Vref 0 -> 0, step: 1
8081 09:26:29.271501
8082 09:26:29.275190 RX Delay 0 -> 252, step: 8
8083 09:26:29.278326 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8084 09:26:29.281953 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8085 09:26:29.284826 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8086 09:26:29.291436 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8087 09:26:29.295218 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8088 09:26:29.298194 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8089 09:26:29.301927 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8090 09:26:29.305050 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8091 09:26:29.311254 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8092 09:26:29.314910 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8093 09:26:29.317877 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8094 09:26:29.321461 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8095 09:26:29.327777 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8096 09:26:29.330989 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8097 09:26:29.334258 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8098 09:26:29.338225 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8099 09:26:29.338324 ==
8100 09:26:29.341433 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 09:26:29.347363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 09:26:29.347468 ==
8103 09:26:29.347567 DQS Delay:
8104 09:26:29.351259 DQS0 = 0, DQS1 = 0
8105 09:26:29.351369 DQM Delay:
8106 09:26:29.351462 DQM0 = 132, DQM1 = 127
8107 09:26:29.354257 DQ Delay:
8108 09:26:29.357224 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8109 09:26:29.360704 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =135
8110 09:26:29.364318 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8111 09:26:29.367135 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8112 09:26:29.367239
8113 09:26:29.367332
8114 09:26:29.367420 ==
8115 09:26:29.370491 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 09:26:29.377549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 09:26:29.377978 ==
8118 09:26:29.378360
8119 09:26:29.378676
8120 09:26:29.379019 TX Vref Scan disable
8121 09:26:29.381182 == TX Byte 0 ==
8122 09:26:29.384283 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8123 09:26:29.391085 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8124 09:26:29.391606 == TX Byte 1 ==
8125 09:26:29.393806 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8126 09:26:29.400849 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8127 09:26:29.401429 ==
8128 09:26:29.403907 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 09:26:29.406926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 09:26:29.407552 ==
8131 09:26:29.421737
8132 09:26:29.425161 TX Vref early break, caculate TX vref
8133 09:26:29.428715 TX Vref=16, minBit 8, minWin=23, winSum=385
8134 09:26:29.431848 TX Vref=18, minBit 1, minWin=24, winSum=388
8135 09:26:29.435118 TX Vref=20, minBit 1, minWin=24, winSum=395
8136 09:26:29.438119 TX Vref=22, minBit 9, minWin=24, winSum=405
8137 09:26:29.441805 TX Vref=24, minBit 1, minWin=25, winSum=410
8138 09:26:29.447977 TX Vref=26, minBit 4, minWin=25, winSum=416
8139 09:26:29.451409 TX Vref=28, minBit 8, minWin=25, winSum=416
8140 09:26:29.454627 TX Vref=30, minBit 1, minWin=25, winSum=412
8141 09:26:29.458317 TX Vref=32, minBit 0, minWin=25, winSum=407
8142 09:26:29.461360 TX Vref=34, minBit 6, minWin=24, winSum=396
8143 09:26:29.467903 TX Vref=36, minBit 12, minWin=23, winSum=388
8144 09:26:29.471406 [TxChooseVref] Worse bit 4, Min win 25, Win sum 416, Final Vref 26
8145 09:26:29.472102
8146 09:26:29.474483 Final TX Range 0 Vref 26
8147 09:26:29.475087
8148 09:26:29.475607 ==
8149 09:26:29.477855 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 09:26:29.481105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 09:26:29.481677 ==
8152 09:26:29.484047
8153 09:26:29.484486
8154 09:26:29.484818 TX Vref Scan disable
8155 09:26:29.491479 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8156 09:26:29.491910 == TX Byte 0 ==
8157 09:26:29.494309 u2DelayCellOfst[0]=14 cells (4 PI)
8158 09:26:29.497389 u2DelayCellOfst[1]=14 cells (4 PI)
8159 09:26:29.500799 u2DelayCellOfst[2]=10 cells (3 PI)
8160 09:26:29.504541 u2DelayCellOfst[3]=10 cells (3 PI)
8161 09:26:29.507667 u2DelayCellOfst[4]=7 cells (2 PI)
8162 09:26:29.510804 u2DelayCellOfst[5]=0 cells (0 PI)
8163 09:26:29.514277 u2DelayCellOfst[6]=17 cells (5 PI)
8164 09:26:29.517295 u2DelayCellOfst[7]=17 cells (5 PI)
8165 09:26:29.520443 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8166 09:26:29.524016 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8167 09:26:29.527018 == TX Byte 1 ==
8168 09:26:29.530453 u2DelayCellOfst[8]=3 cells (1 PI)
8169 09:26:29.533684 u2DelayCellOfst[9]=0 cells (0 PI)
8170 09:26:29.537166 u2DelayCellOfst[10]=7 cells (2 PI)
8171 09:26:29.540234 u2DelayCellOfst[11]=7 cells (2 PI)
8172 09:26:29.543258 u2DelayCellOfst[12]=10 cells (3 PI)
8173 09:26:29.546990 u2DelayCellOfst[13]=10 cells (3 PI)
8174 09:26:29.550062 u2DelayCellOfst[14]=14 cells (4 PI)
8175 09:26:29.553886 u2DelayCellOfst[15]=14 cells (4 PI)
8176 09:26:29.556921 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8177 09:26:29.560085 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8178 09:26:29.563514 DramC Write-DBI on
8179 09:26:29.564202 ==
8180 09:26:29.566429 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 09:26:29.570097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 09:26:29.570559 ==
8183 09:26:29.570916
8184 09:26:29.571278
8185 09:26:29.573075 TX Vref Scan disable
8186 09:26:29.576737 == TX Byte 0 ==
8187 09:26:29.579751 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8188 09:26:29.580208 == TX Byte 1 ==
8189 09:26:29.586609 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8190 09:26:29.587086 DramC Write-DBI off
8191 09:26:29.587621
8192 09:26:29.588128 [DATLAT]
8193 09:26:29.589803 Freq=1600, CH0 RK1
8194 09:26:29.590195
8195 09:26:29.593018 DATLAT Default: 0xf
8196 09:26:29.593544 0, 0xFFFF, sum = 0
8197 09:26:29.596660 1, 0xFFFF, sum = 0
8198 09:26:29.597080 2, 0xFFFF, sum = 0
8199 09:26:29.599542 3, 0xFFFF, sum = 0
8200 09:26:29.600012 4, 0xFFFF, sum = 0
8201 09:26:29.602929 5, 0xFFFF, sum = 0
8202 09:26:29.603352 6, 0xFFFF, sum = 0
8203 09:26:29.606503 7, 0xFFFF, sum = 0
8204 09:26:29.607073 8, 0xFFFF, sum = 0
8205 09:26:29.609516 9, 0xFFFF, sum = 0
8206 09:26:29.609939 10, 0xFFFF, sum = 0
8207 09:26:29.612674 11, 0xFFFF, sum = 0
8208 09:26:29.613104 12, 0xFFFF, sum = 0
8209 09:26:29.616085 13, 0xFFFF, sum = 0
8210 09:26:29.616566 14, 0x0, sum = 1
8211 09:26:29.619497 15, 0x0, sum = 2
8212 09:26:29.619925 16, 0x0, sum = 3
8213 09:26:29.622491 17, 0x0, sum = 4
8214 09:26:29.622915 best_step = 15
8215 09:26:29.623244
8216 09:26:29.623553 ==
8217 09:26:29.626217 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 09:26:29.632386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 09:26:29.632822 ==
8220 09:26:29.633161 RX Vref Scan: 0
8221 09:26:29.633540
8222 09:26:29.636073 RX Vref 0 -> 0, step: 1
8223 09:26:29.636490
8224 09:26:29.639081 RX Delay 11 -> 252, step: 4
8225 09:26:29.642200 iDelay=187, Bit 0, Center 124 (75 ~ 174) 100
8226 09:26:29.645922 iDelay=187, Bit 1, Center 132 (79 ~ 186) 108
8227 09:26:29.652668 iDelay=187, Bit 2, Center 124 (71 ~ 178) 108
8228 09:26:29.655653 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8229 09:26:29.659266 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8230 09:26:29.662462 iDelay=187, Bit 5, Center 118 (63 ~ 174) 112
8231 09:26:29.665489 iDelay=187, Bit 6, Center 136 (87 ~ 186) 100
8232 09:26:29.672352 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8233 09:26:29.675338 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8234 09:26:29.679160 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8235 09:26:29.682102 iDelay=187, Bit 10, Center 124 (71 ~ 178) 108
8236 09:26:29.685077 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8237 09:26:29.692120 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8238 09:26:29.695628 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8239 09:26:29.698749 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8240 09:26:29.702378 iDelay=187, Bit 15, Center 132 (79 ~ 186) 108
8241 09:26:29.702800 ==
8242 09:26:29.705761 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 09:26:29.712079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 09:26:29.712519 ==
8245 09:26:29.712857 DQS Delay:
8246 09:26:29.715327 DQS0 = 0, DQS1 = 0
8247 09:26:29.715745 DQM Delay:
8248 09:26:29.716076 DQM0 = 128, DQM1 = 123
8249 09:26:29.718537 DQ Delay:
8250 09:26:29.721372 DQ0 =124, DQ1 =132, DQ2 =124, DQ3 =126
8251 09:26:29.725004 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8252 09:26:29.728678 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8253 09:26:29.731257 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =132
8254 09:26:29.731696
8255 09:26:29.732034
8256 09:26:29.732344
8257 09:26:29.734675 [DramC_TX_OE_Calibration] TA2
8258 09:26:29.738282 Original DQ_B0 (3 6) =30, OEN = 27
8259 09:26:29.741326 Original DQ_B1 (3 6) =30, OEN = 27
8260 09:26:29.744839 24, 0x0, End_B0=24 End_B1=24
8261 09:26:29.747766 25, 0x0, End_B0=25 End_B1=25
8262 09:26:29.748194 26, 0x0, End_B0=26 End_B1=26
8263 09:26:29.751150 27, 0x0, End_B0=27 End_B1=27
8264 09:26:29.754907 28, 0x0, End_B0=28 End_B1=28
8265 09:26:29.757887 29, 0x0, End_B0=29 End_B1=29
8266 09:26:29.758320 30, 0x0, End_B0=30 End_B1=30
8267 09:26:29.760960 31, 0x4141, End_B0=30 End_B1=30
8268 09:26:29.764601 Byte0 end_step=30 best_step=27
8269 09:26:29.767646 Byte1 end_step=30 best_step=27
8270 09:26:29.770942 Byte0 TX OE(2T, 0.5T) = (3, 3)
8271 09:26:29.774347 Byte1 TX OE(2T, 0.5T) = (3, 3)
8272 09:26:29.774774
8273 09:26:29.775110
8274 09:26:29.781073 [DQSOSCAuto] RK1, (LSB)MR18= 0x1411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
8275 09:26:29.784192 CH0 RK1: MR19=303, MR18=1411
8276 09:26:29.791058 CH0_RK1: MR19=0x303, MR18=0x1411, DQSOSC=399, MR23=63, INC=23, DEC=15
8277 09:26:29.794182 [RxdqsGatingPostProcess] freq 1600
8278 09:26:29.800925 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8279 09:26:29.801456 best DQS0 dly(2T, 0.5T) = (1, 1)
8280 09:26:29.804083 best DQS1 dly(2T, 0.5T) = (1, 1)
8281 09:26:29.807334 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8282 09:26:29.810900 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8283 09:26:29.813880 best DQS0 dly(2T, 0.5T) = (1, 1)
8284 09:26:29.817397 best DQS1 dly(2T, 0.5T) = (1, 1)
8285 09:26:29.820608 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8286 09:26:29.824207 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8287 09:26:29.827143 Pre-setting of DQS Precalculation
8288 09:26:29.830740 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8289 09:26:29.831168 ==
8290 09:26:29.834195 Dram Type= 6, Freq= 0, CH_1, rank 0
8291 09:26:29.840438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 09:26:29.840884 ==
8293 09:26:29.843679 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 09:26:29.850560 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 09:26:29.853819 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 09:26:29.860116 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 09:26:29.868101 [CA 0] Center 42 (12~72) winsize 61
8298 09:26:29.871770 [CA 1] Center 42 (12~73) winsize 62
8299 09:26:29.874869 [CA 2] Center 39 (10~68) winsize 59
8300 09:26:29.878529 [CA 3] Center 37 (8~67) winsize 60
8301 09:26:29.881517 [CA 4] Center 38 (8~69) winsize 62
8302 09:26:29.884543 [CA 5] Center 37 (7~67) winsize 61
8303 09:26:29.884976
8304 09:26:29.888288 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8305 09:26:29.888710
8306 09:26:29.894481 [CATrainingPosCal] consider 1 rank data
8307 09:26:29.895087 u2DelayCellTimex100 = 275/100 ps
8308 09:26:29.901214 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8309 09:26:29.904386 CA1 delay=42 (12~73),Diff = 5 PI (17 cell)
8310 09:26:29.907926 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
8311 09:26:29.911092 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8312 09:26:29.914252 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8313 09:26:29.917949 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8314 09:26:29.918628
8315 09:26:29.920979 CA PerBit enable=1, Macro0, CA PI delay=37
8316 09:26:29.921576
8317 09:26:29.924549 [CBTSetCACLKResult] CA Dly = 37
8318 09:26:29.927427 CS Dly: 9 (0~40)
8319 09:26:29.931032 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 09:26:29.934472 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 09:26:29.935180 ==
8322 09:26:29.937587 Dram Type= 6, Freq= 0, CH_1, rank 1
8323 09:26:29.944558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 09:26:29.945070 ==
8325 09:26:29.947727 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8326 09:26:29.954206 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8327 09:26:29.957432 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8328 09:26:29.963752 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8329 09:26:29.971488 [CA 0] Center 42 (12~72) winsize 61
8330 09:26:29.974657 [CA 1] Center 43 (14~72) winsize 59
8331 09:26:29.978124 [CA 2] Center 38 (9~68) winsize 60
8332 09:26:29.981381 [CA 3] Center 37 (8~67) winsize 60
8333 09:26:29.984778 [CA 4] Center 37 (8~67) winsize 60
8334 09:26:29.987819 [CA 5] Center 37 (7~67) winsize 61
8335 09:26:29.988439
8336 09:26:29.991531 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8337 09:26:29.992150
8338 09:26:29.994452 [CATrainingPosCal] consider 2 rank data
8339 09:26:29.998121 u2DelayCellTimex100 = 275/100 ps
8340 09:26:30.004795 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8341 09:26:30.007895 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8342 09:26:30.011130 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
8343 09:26:30.014112 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8344 09:26:30.017929 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8345 09:26:30.020982 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8346 09:26:30.021560
8347 09:26:30.024524 CA PerBit enable=1, Macro0, CA PI delay=37
8348 09:26:30.025109
8349 09:26:30.027401 [CBTSetCACLKResult] CA Dly = 37
8350 09:26:30.030641 CS Dly: 10 (0~42)
8351 09:26:30.034391 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8352 09:26:30.037490 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8353 09:26:30.038212
8354 09:26:30.040979 ----->DramcWriteLeveling(PI) begin...
8355 09:26:30.041560 ==
8356 09:26:30.044012 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 09:26:30.050418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 09:26:30.051041 ==
8359 09:26:30.054247 Write leveling (Byte 0): 23 => 23
8360 09:26:30.057281 Write leveling (Byte 1): 26 => 26
8361 09:26:30.060474 DramcWriteLeveling(PI) end<-----
8362 09:26:30.060983
8363 09:26:30.061515 ==
8364 09:26:30.064059 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 09:26:30.066933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 09:26:30.067525 ==
8367 09:26:30.070213 [Gating] SW mode calibration
8368 09:26:30.077322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8369 09:26:30.080426 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8370 09:26:30.086969 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 09:26:30.089894 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 09:26:30.093153 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 09:26:30.099848 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8374 09:26:30.103427 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 09:26:30.106456 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 09:26:30.113238 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 09:26:30.116269 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 09:26:30.119453 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 09:26:30.126208 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 09:26:30.129554 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
8381 09:26:30.132871 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8382 09:26:30.139876 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 09:26:30.142793 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 09:26:30.145881 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 09:26:30.153230 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 09:26:30.156172 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 09:26:30.159197 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 09:26:30.166012 1 6 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8389 09:26:30.168951 1 6 12 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8390 09:26:30.175619 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 09:26:30.179105 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 09:26:30.182644 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 09:26:30.186056 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 09:26:30.192453 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 09:26:30.195896 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 09:26:30.198771 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 09:26:30.205582 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8398 09:26:30.209079 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 09:26:30.215465 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 09:26:30.218475 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 09:26:30.222292 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 09:26:30.228375 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 09:26:30.232100 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 09:26:30.235304 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 09:26:30.242030 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 09:26:30.245117 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 09:26:30.248068 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 09:26:30.255277 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 09:26:30.258243 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 09:26:30.261709 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 09:26:30.267788 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 09:26:30.271704 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8413 09:26:30.274478 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8414 09:26:30.281242 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 09:26:30.281797 Total UI for P1: 0, mck2ui 16
8416 09:26:30.288068 best dqsien dly found for B0: ( 1, 9, 10)
8417 09:26:30.288712 Total UI for P1: 0, mck2ui 16
8418 09:26:30.291033 best dqsien dly found for B1: ( 1, 9, 12)
8419 09:26:30.297368 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8420 09:26:30.300670 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8421 09:26:30.301104
8422 09:26:30.304222 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8423 09:26:30.307318 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8424 09:26:30.310917 [Gating] SW calibration Done
8425 09:26:30.311249 ==
8426 09:26:30.313943 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 09:26:30.317229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 09:26:30.317486 ==
8429 09:26:30.320850 RX Vref Scan: 0
8430 09:26:30.321094
8431 09:26:30.321335 RX Vref 0 -> 0, step: 1
8432 09:26:30.321474
8433 09:26:30.323913 RX Delay 0 -> 252, step: 8
8434 09:26:30.327107 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8435 09:26:30.333912 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8436 09:26:30.337022 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8437 09:26:30.340606 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8438 09:26:30.343744 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8439 09:26:30.346800 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8440 09:26:30.353340 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8441 09:26:30.356995 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8442 09:26:30.360039 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8443 09:26:30.363602 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8444 09:26:30.366466 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8445 09:26:30.373096 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8446 09:26:30.376969 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8447 09:26:30.379990 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8448 09:26:30.383106 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8449 09:26:30.389875 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8450 09:26:30.390064 ==
8451 09:26:30.393015 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 09:26:30.396672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 09:26:30.396875 ==
8454 09:26:30.397041 DQS Delay:
8455 09:26:30.399813 DQS0 = 0, DQS1 = 0
8456 09:26:30.400071 DQM Delay:
8457 09:26:30.402992 DQM0 = 136, DQM1 = 130
8458 09:26:30.403318 DQ Delay:
8459 09:26:30.406408 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8460 09:26:30.409931 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8461 09:26:30.413245 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8462 09:26:30.416087 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8463 09:26:30.419901
8464 09:26:30.420321
8465 09:26:30.420650 ==
8466 09:26:30.423074 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 09:26:30.426040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 09:26:30.426496 ==
8469 09:26:30.426855
8470 09:26:30.427228
8471 09:26:30.429619 TX Vref Scan disable
8472 09:26:30.430028 == TX Byte 0 ==
8473 09:26:30.435665 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8474 09:26:30.439379 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8475 09:26:30.440089 == TX Byte 1 ==
8476 09:26:30.445726 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8477 09:26:30.448935 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8478 09:26:30.449427 ==
8479 09:26:30.452454 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 09:26:30.455717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 09:26:30.456142 ==
8482 09:26:30.470662
8483 09:26:30.474052 TX Vref early break, caculate TX vref
8484 09:26:30.477174 TX Vref=16, minBit 8, minWin=21, winSum=368
8485 09:26:30.480248 TX Vref=18, minBit 6, minWin=23, winSum=381
8486 09:26:30.483879 TX Vref=20, minBit 8, minWin=23, winSum=390
8487 09:26:30.487015 TX Vref=22, minBit 8, minWin=23, winSum=396
8488 09:26:30.490261 TX Vref=24, minBit 9, minWin=23, winSum=406
8489 09:26:30.496981 TX Vref=26, minBit 9, minWin=24, winSum=415
8490 09:26:30.500609 TX Vref=28, minBit 8, minWin=25, winSum=417
8491 09:26:30.503655 TX Vref=30, minBit 0, minWin=25, winSum=416
8492 09:26:30.506769 TX Vref=32, minBit 11, minWin=24, winSum=405
8493 09:26:30.510618 TX Vref=34, minBit 9, minWin=23, winSum=399
8494 09:26:30.513522 TX Vref=36, minBit 11, minWin=22, winSum=381
8495 09:26:30.519800 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
8496 09:26:30.520322
8497 09:26:30.523183 Final TX Range 0 Vref 28
8498 09:26:30.523873
8499 09:26:30.524508 ==
8500 09:26:30.526707 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 09:26:30.530411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 09:26:30.530835 ==
8503 09:26:30.533240
8504 09:26:30.533712
8505 09:26:30.534048 TX Vref Scan disable
8506 09:26:30.539674 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8507 09:26:30.540096 == TX Byte 0 ==
8508 09:26:30.543479 u2DelayCellOfst[0]=14 cells (4 PI)
8509 09:26:30.546526 u2DelayCellOfst[1]=10 cells (3 PI)
8510 09:26:30.549620 u2DelayCellOfst[2]=0 cells (0 PI)
8511 09:26:30.553245 u2DelayCellOfst[3]=7 cells (2 PI)
8512 09:26:30.556257 u2DelayCellOfst[4]=10 cells (3 PI)
8513 09:26:30.559746 u2DelayCellOfst[5]=17 cells (5 PI)
8514 09:26:30.563100 u2DelayCellOfst[6]=17 cells (5 PI)
8515 09:26:30.566332 u2DelayCellOfst[7]=7 cells (2 PI)
8516 09:26:30.569866 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8517 09:26:30.572893 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8518 09:26:30.575908 == TX Byte 1 ==
8519 09:26:30.579726 u2DelayCellOfst[8]=0 cells (0 PI)
8520 09:26:30.582609 u2DelayCellOfst[9]=3 cells (1 PI)
8521 09:26:30.585865 u2DelayCellOfst[10]=10 cells (3 PI)
8522 09:26:30.589586 u2DelayCellOfst[11]=3 cells (1 PI)
8523 09:26:30.592654 u2DelayCellOfst[12]=14 cells (4 PI)
8524 09:26:30.595637 u2DelayCellOfst[13]=14 cells (4 PI)
8525 09:26:30.599316 u2DelayCellOfst[14]=17 cells (5 PI)
8526 09:26:30.602414 u2DelayCellOfst[15]=17 cells (5 PI)
8527 09:26:30.605616 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8528 09:26:30.609227 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8529 09:26:30.612303 DramC Write-DBI on
8530 09:26:30.612834 ==
8531 09:26:30.615812 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 09:26:30.619001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 09:26:30.619474 ==
8534 09:26:30.619916
8535 09:26:30.620464
8536 09:26:30.622074 TX Vref Scan disable
8537 09:26:30.622799 == TX Byte 0 ==
8538 09:26:30.628997 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8539 09:26:30.629749 == TX Byte 1 ==
8540 09:26:30.632479 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8541 09:26:30.635209 DramC Write-DBI off
8542 09:26:30.635912
8543 09:26:30.636522 [DATLAT]
8544 09:26:30.638885 Freq=1600, CH1 RK0
8545 09:26:30.639445
8546 09:26:30.639966 DATLAT Default: 0xf
8547 09:26:30.642763 0, 0xFFFF, sum = 0
8548 09:26:30.645399 1, 0xFFFF, sum = 0
8549 09:26:30.646014 2, 0xFFFF, sum = 0
8550 09:26:30.648273 3, 0xFFFF, sum = 0
8551 09:26:30.648608 4, 0xFFFF, sum = 0
8552 09:26:30.651871 5, 0xFFFF, sum = 0
8553 09:26:30.652304 6, 0xFFFF, sum = 0
8554 09:26:30.655071 7, 0xFFFF, sum = 0
8555 09:26:30.655495 8, 0xFFFF, sum = 0
8556 09:26:30.658092 9, 0xFFFF, sum = 0
8557 09:26:30.658516 10, 0xFFFF, sum = 0
8558 09:26:30.661892 11, 0xFFFF, sum = 0
8559 09:26:30.662319 12, 0xFFFF, sum = 0
8560 09:26:30.664976 13, 0xFFFF, sum = 0
8561 09:26:30.665442 14, 0x0, sum = 1
8562 09:26:30.668092 15, 0x0, sum = 2
8563 09:26:30.668535 16, 0x0, sum = 3
8564 09:26:30.671641 17, 0x0, sum = 4
8565 09:26:30.672087 best_step = 15
8566 09:26:30.672490
8567 09:26:30.672870 ==
8568 09:26:30.674752 Dram Type= 6, Freq= 0, CH_1, rank 0
8569 09:26:30.681324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8570 09:26:30.681777 ==
8571 09:26:30.682209 RX Vref Scan: 1
8572 09:26:30.682620
8573 09:26:30.684571 Set Vref Range= 24 -> 127
8574 09:26:30.685014
8575 09:26:30.687814 RX Vref 24 -> 127, step: 1
8576 09:26:30.688249
8577 09:26:30.691234 RX Delay 19 -> 252, step: 4
8578 09:26:30.691606
8579 09:26:30.694879 Set Vref, RX VrefLevel [Byte0]: 24
8580 09:26:30.695365 [Byte1]: 24
8581 09:26:30.698671
8582 09:26:30.698983 Set Vref, RX VrefLevel [Byte0]: 25
8583 09:26:30.702280 [Byte1]: 25
8584 09:26:30.706394
8585 09:26:30.706750 Set Vref, RX VrefLevel [Byte0]: 26
8586 09:26:30.709973 [Byte1]: 26
8587 09:26:30.714357
8588 09:26:30.714657 Set Vref, RX VrefLevel [Byte0]: 27
8589 09:26:30.717529 [Byte1]: 27
8590 09:26:30.721552
8591 09:26:30.721851 Set Vref, RX VrefLevel [Byte0]: 28
8592 09:26:30.724702 [Byte1]: 28
8593 09:26:30.729534
8594 09:26:30.729977 Set Vref, RX VrefLevel [Byte0]: 29
8595 09:26:30.732327 [Byte1]: 29
8596 09:26:30.736985
8597 09:26:30.737412 Set Vref, RX VrefLevel [Byte0]: 30
8598 09:26:30.739933 [Byte1]: 30
8599 09:26:30.744249
8600 09:26:30.744618 Set Vref, RX VrefLevel [Byte0]: 31
8601 09:26:30.747673 [Byte1]: 31
8602 09:26:30.752017
8603 09:26:30.752425 Set Vref, RX VrefLevel [Byte0]: 32
8604 09:26:30.755220 [Byte1]: 32
8605 09:26:30.759365
8606 09:26:30.762567 Set Vref, RX VrefLevel [Byte0]: 33
8607 09:26:30.762974 [Byte1]: 33
8608 09:26:30.766854
8609 09:26:30.767240 Set Vref, RX VrefLevel [Byte0]: 34
8610 09:26:30.770408 [Byte1]: 34
8611 09:26:30.774694
8612 09:26:30.775092 Set Vref, RX VrefLevel [Byte0]: 35
8613 09:26:30.777920 [Byte1]: 35
8614 09:26:30.782173
8615 09:26:30.782487 Set Vref, RX VrefLevel [Byte0]: 36
8616 09:26:30.785135 [Byte1]: 36
8617 09:26:30.789447
8618 09:26:30.789528 Set Vref, RX VrefLevel [Byte0]: 37
8619 09:26:30.793068 [Byte1]: 37
8620 09:26:30.797404
8621 09:26:30.797479 Set Vref, RX VrefLevel [Byte0]: 38
8622 09:26:30.800232 [Byte1]: 38
8623 09:26:30.804605
8624 09:26:30.804718 Set Vref, RX VrefLevel [Byte0]: 39
8625 09:26:30.807906 [Byte1]: 39
8626 09:26:30.812362
8627 09:26:30.812441 Set Vref, RX VrefLevel [Byte0]: 40
8628 09:26:30.815377 [Byte1]: 40
8629 09:26:30.820023
8630 09:26:30.820167 Set Vref, RX VrefLevel [Byte0]: 41
8631 09:26:30.823213 [Byte1]: 41
8632 09:26:30.827433
8633 09:26:30.827538 Set Vref, RX VrefLevel [Byte0]: 42
8634 09:26:30.830627 [Byte1]: 42
8635 09:26:30.834907
8636 09:26:30.835013 Set Vref, RX VrefLevel [Byte0]: 43
8637 09:26:30.838350 [Byte1]: 43
8638 09:26:30.842628
8639 09:26:30.842730 Set Vref, RX VrefLevel [Byte0]: 44
8640 09:26:30.845794 [Byte1]: 44
8641 09:26:30.850252
8642 09:26:30.850351 Set Vref, RX VrefLevel [Byte0]: 45
8643 09:26:30.853619 [Byte1]: 45
8644 09:26:30.857844
8645 09:26:30.857921 Set Vref, RX VrefLevel [Byte0]: 46
8646 09:26:30.861003 [Byte1]: 46
8647 09:26:30.865444
8648 09:26:30.865539 Set Vref, RX VrefLevel [Byte0]: 47
8649 09:26:30.868501 [Byte1]: 47
8650 09:26:30.872868
8651 09:26:30.872976 Set Vref, RX VrefLevel [Byte0]: 48
8652 09:26:30.875843 [Byte1]: 48
8653 09:26:30.880176
8654 09:26:30.880281 Set Vref, RX VrefLevel [Byte0]: 49
8655 09:26:30.883906 [Byte1]: 49
8656 09:26:30.888201
8657 09:26:30.888313 Set Vref, RX VrefLevel [Byte0]: 50
8658 09:26:30.894557 [Byte1]: 50
8659 09:26:30.894659
8660 09:26:30.897723 Set Vref, RX VrefLevel [Byte0]: 51
8661 09:26:30.900807 [Byte1]: 51
8662 09:26:30.900907
8663 09:26:30.904559 Set Vref, RX VrefLevel [Byte0]: 52
8664 09:26:30.907519 [Byte1]: 52
8665 09:26:30.907624
8666 09:26:30.910976 Set Vref, RX VrefLevel [Byte0]: 53
8667 09:26:30.914063 [Byte1]: 53
8668 09:26:30.918171
8669 09:26:30.918280 Set Vref, RX VrefLevel [Byte0]: 54
8670 09:26:30.921776 [Byte1]: 54
8671 09:26:30.925973
8672 09:26:30.926092 Set Vref, RX VrefLevel [Byte0]: 55
8673 09:26:30.928989 [Byte1]: 55
8674 09:26:30.933625
8675 09:26:30.933729 Set Vref, RX VrefLevel [Byte0]: 56
8676 09:26:30.936450 [Byte1]: 56
8677 09:26:30.941132
8678 09:26:30.941239 Set Vref, RX VrefLevel [Byte0]: 57
8679 09:26:30.944507 [Byte1]: 57
8680 09:26:30.948637
8681 09:26:30.948739 Set Vref, RX VrefLevel [Byte0]: 58
8682 09:26:30.951741 [Byte1]: 58
8683 09:26:30.956170
8684 09:26:30.956246 Set Vref, RX VrefLevel [Byte0]: 59
8685 09:26:30.959497 [Byte1]: 59
8686 09:26:30.963810
8687 09:26:30.963912 Set Vref, RX VrefLevel [Byte0]: 60
8688 09:26:30.966820 [Byte1]: 60
8689 09:26:30.971518
8690 09:26:30.971620 Set Vref, RX VrefLevel [Byte0]: 61
8691 09:26:30.974802 [Byte1]: 61
8692 09:26:30.979129
8693 09:26:30.979232 Set Vref, RX VrefLevel [Byte0]: 62
8694 09:26:30.982052 [Byte1]: 62
8695 09:26:30.986384
8696 09:26:30.986487 Set Vref, RX VrefLevel [Byte0]: 63
8697 09:26:30.989592 [Byte1]: 63
8698 09:26:30.994052
8699 09:26:30.994127 Set Vref, RX VrefLevel [Byte0]: 64
8700 09:26:30.997429 [Byte1]: 64
8701 09:26:31.001252
8702 09:26:31.001435 Set Vref, RX VrefLevel [Byte0]: 65
8703 09:26:31.004907 [Byte1]: 65
8704 09:26:31.009156
8705 09:26:31.009234 Set Vref, RX VrefLevel [Byte0]: 66
8706 09:26:31.012196 [Byte1]: 66
8707 09:26:31.017019
8708 09:26:31.017124 Set Vref, RX VrefLevel [Byte0]: 67
8709 09:26:31.020158 [Byte1]: 67
8710 09:26:31.024252
8711 09:26:31.024360 Set Vref, RX VrefLevel [Byte0]: 68
8712 09:26:31.027393 [Byte1]: 68
8713 09:26:31.032140
8714 09:26:31.032242 Set Vref, RX VrefLevel [Byte0]: 69
8715 09:26:31.035225 [Byte1]: 69
8716 09:26:31.039347
8717 09:26:31.039450 Set Vref, RX VrefLevel [Byte0]: 70
8718 09:26:31.043042 [Byte1]: 70
8719 09:26:31.047434
8720 09:26:31.047536 Set Vref, RX VrefLevel [Byte0]: 71
8721 09:26:31.050678 [Byte1]: 71
8722 09:26:31.054748
8723 09:26:31.054842 Final RX Vref Byte 0 = 60 to rank0
8724 09:26:31.058232 Final RX Vref Byte 1 = 61 to rank0
8725 09:26:31.061358 Final RX Vref Byte 0 = 60 to rank1
8726 09:26:31.064273 Final RX Vref Byte 1 = 61 to rank1==
8727 09:26:31.067680 Dram Type= 6, Freq= 0, CH_1, rank 0
8728 09:26:31.074201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8729 09:26:31.074378 ==
8730 09:26:31.074538 DQS Delay:
8731 09:26:31.077424 DQS0 = 0, DQS1 = 0
8732 09:26:31.077575 DQM Delay:
8733 09:26:31.077698 DQM0 = 133, DQM1 = 128
8734 09:26:31.081028 DQ Delay:
8735 09:26:31.084024 DQ0 =140, DQ1 =130, DQ2 =120, DQ3 =132
8736 09:26:31.087567 DQ4 =130, DQ5 =142, DQ6 =144, DQ7 =130
8737 09:26:31.091075 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =120
8738 09:26:31.094050 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8739 09:26:31.094292
8740 09:26:31.094494
8741 09:26:31.094763
8742 09:26:31.097175 [DramC_TX_OE_Calibration] TA2
8743 09:26:31.101075 Original DQ_B0 (3 6) =30, OEN = 27
8744 09:26:31.104151 Original DQ_B1 (3 6) =30, OEN = 27
8745 09:26:31.107184 24, 0x0, End_B0=24 End_B1=24
8746 09:26:31.111046 25, 0x0, End_B0=25 End_B1=25
8747 09:26:31.111589 26, 0x0, End_B0=26 End_B1=26
8748 09:26:31.114061 27, 0x0, End_B0=27 End_B1=27
8749 09:26:31.117111 28, 0x0, End_B0=28 End_B1=28
8750 09:26:31.120855 29, 0x0, End_B0=29 End_B1=29
8751 09:26:31.123671 30, 0x0, End_B0=30 End_B1=30
8752 09:26:31.124390 31, 0x4141, End_B0=30 End_B1=30
8753 09:26:31.126848 Byte0 end_step=30 best_step=27
8754 09:26:31.130698 Byte1 end_step=30 best_step=27
8755 09:26:31.133826 Byte0 TX OE(2T, 0.5T) = (3, 3)
8756 09:26:31.136738 Byte1 TX OE(2T, 0.5T) = (3, 3)
8757 09:26:31.137371
8758 09:26:31.137850
8759 09:26:31.143426 [DQSOSCAuto] RK0, (LSB)MR18= 0xf19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8760 09:26:31.147156 CH1 RK0: MR19=303, MR18=F19
8761 09:26:31.153385 CH1_RK0: MR19=0x303, MR18=0xF19, DQSOSC=397, MR23=63, INC=23, DEC=15
8762 09:26:31.153931
8763 09:26:31.156537 ----->DramcWriteLeveling(PI) begin...
8764 09:26:31.157180 ==
8765 09:26:31.160122 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 09:26:31.163192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 09:26:31.163798 ==
8768 09:26:31.166664 Write leveling (Byte 0): 24 => 24
8769 09:26:31.169674 Write leveling (Byte 1): 27 => 27
8770 09:26:31.173441 DramcWriteLeveling(PI) end<-----
8771 09:26:31.174010
8772 09:26:31.174559 ==
8773 09:26:31.176456 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 09:26:31.183137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 09:26:31.183740 ==
8776 09:26:31.184277 [Gating] SW mode calibration
8777 09:26:31.192738 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8778 09:26:31.196527 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8779 09:26:31.202836 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 09:26:31.206302 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 09:26:31.209371 1 4 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8782 09:26:31.215988 1 4 12 | B1->B0 | 2726 3434 | 1 1 | (0 0) (1 1)
8783 09:26:31.219033 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 09:26:31.222660 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 09:26:31.229044 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 09:26:31.232066 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 09:26:31.235744 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 09:26:31.242261 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8789 09:26:31.245232 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
8790 09:26:31.249154 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8791 09:26:31.255103 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8792 09:26:31.258907 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 09:26:31.261923 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 09:26:31.268705 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 09:26:31.271605 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 09:26:31.275086 1 6 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
8797 09:26:31.281931 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8798 09:26:31.285070 1 6 12 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8799 09:26:31.288195 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 09:26:31.295059 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 09:26:31.298151 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 09:26:31.301844 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 09:26:31.308231 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 09:26:31.311181 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8805 09:26:31.314649 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8806 09:26:31.321671 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8807 09:26:31.324872 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 09:26:31.327910 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 09:26:31.334362 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 09:26:31.338016 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 09:26:31.341195 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 09:26:31.347545 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 09:26:31.351013 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 09:26:31.354667 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 09:26:31.357748 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 09:26:31.364577 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 09:26:31.367503 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 09:26:31.374392 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 09:26:31.377161 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 09:26:31.380622 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 09:26:31.387449 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8822 09:26:31.390579 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 09:26:31.393648 Total UI for P1: 0, mck2ui 16
8824 09:26:31.397322 best dqsien dly found for B0: ( 1, 9, 8)
8825 09:26:31.400418 Total UI for P1: 0, mck2ui 16
8826 09:26:31.403451 best dqsien dly found for B1: ( 1, 9, 10)
8827 09:26:31.407132 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8828 09:26:31.410218 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8829 09:26:31.410827
8830 09:26:31.413800 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8831 09:26:31.416806 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8832 09:26:31.420423 [Gating] SW calibration Done
8833 09:26:31.421080 ==
8834 09:26:31.423256 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 09:26:31.427023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 09:26:31.430306 ==
8837 09:26:31.430897 RX Vref Scan: 0
8838 09:26:31.431434
8839 09:26:31.433324 RX Vref 0 -> 0, step: 1
8840 09:26:31.433923
8841 09:26:31.434467 RX Delay 0 -> 252, step: 8
8842 09:26:31.439839 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8843 09:26:31.443338 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8844 09:26:31.446608 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8845 09:26:31.449699 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8846 09:26:31.456365 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8847 09:26:31.459385 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8848 09:26:31.463174 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8849 09:26:31.466020 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8850 09:26:31.469779 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8851 09:26:31.475850 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8852 09:26:31.479728 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8853 09:26:31.482657 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8854 09:26:31.486096 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8855 09:26:31.489115 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8856 09:26:31.495862 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8857 09:26:31.499657 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8858 09:26:31.500263 ==
8859 09:26:31.502605 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 09:26:31.505769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 09:26:31.506244 ==
8862 09:26:31.509398 DQS Delay:
8863 09:26:31.509853 DQS0 = 0, DQS1 = 0
8864 09:26:31.510235 DQM Delay:
8865 09:26:31.512290 DQM0 = 133, DQM1 = 130
8866 09:26:31.512895 DQ Delay:
8867 09:26:31.515393 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =131
8868 09:26:31.518839 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8869 09:26:31.525484 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8870 09:26:31.529008 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8871 09:26:31.529549
8872 09:26:31.529997
8873 09:26:31.530597 ==
8874 09:26:31.532054 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 09:26:31.535832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 09:26:31.536505 ==
8877 09:26:31.536914
8878 09:26:31.537469
8879 09:26:31.538847 TX Vref Scan disable
8880 09:26:31.541920 == TX Byte 0 ==
8881 09:26:31.545523 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8882 09:26:31.548555 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8883 09:26:31.552260 == TX Byte 1 ==
8884 09:26:31.555137 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8885 09:26:31.558529 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8886 09:26:31.559024 ==
8887 09:26:31.562066 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 09:26:31.568176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 09:26:31.568676 ==
8890 09:26:31.580653
8891 09:26:31.584327 TX Vref early break, caculate TX vref
8892 09:26:31.587352 TX Vref=16, minBit 9, minWin=21, winSum=377
8893 09:26:31.590748 TX Vref=18, minBit 9, minWin=21, winSum=387
8894 09:26:31.594517 TX Vref=20, minBit 9, minWin=22, winSum=392
8895 09:26:31.597498 TX Vref=22, minBit 9, minWin=23, winSum=399
8896 09:26:31.600698 TX Vref=24, minBit 9, minWin=23, winSum=408
8897 09:26:31.607429 TX Vref=26, minBit 9, minWin=24, winSum=415
8898 09:26:31.610550 TX Vref=28, minBit 9, minWin=25, winSum=422
8899 09:26:31.613506 TX Vref=30, minBit 9, minWin=24, winSum=417
8900 09:26:31.617374 TX Vref=32, minBit 0, minWin=24, winSum=411
8901 09:26:31.620256 TX Vref=34, minBit 9, minWin=23, winSum=402
8902 09:26:31.623841 TX Vref=36, minBit 8, minWin=23, winSum=397
8903 09:26:31.630323 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 28
8904 09:26:31.630965
8905 09:26:31.633843 Final TX Range 0 Vref 28
8906 09:26:31.634284
8907 09:26:31.634614 ==
8908 09:26:31.636944 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 09:26:31.639973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 09:26:31.640397 ==
8911 09:26:31.643645
8912 09:26:31.644100
8913 09:26:31.644518 TX Vref Scan disable
8914 09:26:31.649914 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8915 09:26:31.650372 == TX Byte 0 ==
8916 09:26:31.653516 u2DelayCellOfst[0]=14 cells (4 PI)
8917 09:26:31.656538 u2DelayCellOfst[1]=10 cells (3 PI)
8918 09:26:31.659817 u2DelayCellOfst[2]=0 cells (0 PI)
8919 09:26:31.662831 u2DelayCellOfst[3]=7 cells (2 PI)
8920 09:26:31.666555 u2DelayCellOfst[4]=7 cells (2 PI)
8921 09:26:31.669412 u2DelayCellOfst[5]=17 cells (5 PI)
8922 09:26:31.673078 u2DelayCellOfst[6]=14 cells (4 PI)
8923 09:26:31.676179 u2DelayCellOfst[7]=7 cells (2 PI)
8924 09:26:31.679759 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8925 09:26:31.682602 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8926 09:26:31.686351 == TX Byte 1 ==
8927 09:26:31.689605 u2DelayCellOfst[8]=0 cells (0 PI)
8928 09:26:31.692813 u2DelayCellOfst[9]=3 cells (1 PI)
8929 09:26:31.696284 u2DelayCellOfst[10]=10 cells (3 PI)
8930 09:26:31.699707 u2DelayCellOfst[11]=7 cells (2 PI)
8931 09:26:31.699789 u2DelayCellOfst[12]=14 cells (4 PI)
8932 09:26:31.702616 u2DelayCellOfst[13]=14 cells (4 PI)
8933 09:26:31.705749 u2DelayCellOfst[14]=14 cells (4 PI)
8934 09:26:31.709427 u2DelayCellOfst[15]=14 cells (4 PI)
8935 09:26:31.716098 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8936 09:26:31.719225 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8937 09:26:31.722299 DramC Write-DBI on
8938 09:26:31.722381 ==
8939 09:26:31.725370 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 09:26:31.728976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 09:26:31.729081 ==
8942 09:26:31.729174
8943 09:26:31.729287
8944 09:26:31.732333 TX Vref Scan disable
8945 09:26:31.732410 == TX Byte 0 ==
8946 09:26:31.738717 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8947 09:26:31.738795 == TX Byte 1 ==
8948 09:26:31.742452 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8949 09:26:31.745700 DramC Write-DBI off
8950 09:26:31.745779
8951 09:26:31.745842 [DATLAT]
8952 09:26:31.749032 Freq=1600, CH1 RK1
8953 09:26:31.749130
8954 09:26:31.749226 DATLAT Default: 0xf
8955 09:26:31.752121 0, 0xFFFF, sum = 0
8956 09:26:31.752232 1, 0xFFFF, sum = 0
8957 09:26:31.755180 2, 0xFFFF, sum = 0
8958 09:26:31.755289 3, 0xFFFF, sum = 0
8959 09:26:31.758909 4, 0xFFFF, sum = 0
8960 09:26:31.761811 5, 0xFFFF, sum = 0
8961 09:26:31.761886 6, 0xFFFF, sum = 0
8962 09:26:31.764939 7, 0xFFFF, sum = 0
8963 09:26:31.765013 8, 0xFFFF, sum = 0
8964 09:26:31.768398 9, 0xFFFF, sum = 0
8965 09:26:31.768472 10, 0xFFFF, sum = 0
8966 09:26:31.771946 11, 0xFFFF, sum = 0
8967 09:26:31.772022 12, 0xFFFF, sum = 0
8968 09:26:31.774874 13, 0xFFFF, sum = 0
8969 09:26:31.774948 14, 0x0, sum = 1
8970 09:26:31.778542 15, 0x0, sum = 2
8971 09:26:31.778616 16, 0x0, sum = 3
8972 09:26:31.781547 17, 0x0, sum = 4
8973 09:26:31.781620 best_step = 15
8974 09:26:31.781680
8975 09:26:31.781737 ==
8976 09:26:31.785222 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 09:26:31.791262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 09:26:31.791344 ==
8979 09:26:31.791408 RX Vref Scan: 0
8980 09:26:31.791467
8981 09:26:31.794915 RX Vref 0 -> 0, step: 1
8982 09:26:31.794996
8983 09:26:31.798357 RX Delay 19 -> 252, step: 4
8984 09:26:31.801148 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8985 09:26:31.804666 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8986 09:26:31.807916 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8987 09:26:31.814397 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8988 09:26:31.817965 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8989 09:26:31.821575 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8990 09:26:31.824585 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8991 09:26:31.827700 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8992 09:26:31.834279 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8993 09:26:31.837765 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8994 09:26:31.841197 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8995 09:26:31.844730 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8996 09:26:31.848002 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8997 09:26:31.854292 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8998 09:26:31.857655 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8999 09:26:31.860776 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9000 09:26:31.860873 ==
9001 09:26:31.863883 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 09:26:31.870510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 09:26:31.870589 ==
9004 09:26:31.870658 DQS Delay:
9005 09:26:31.870721 DQS0 = 0, DQS1 = 0
9006 09:26:31.874050 DQM Delay:
9007 09:26:31.874123 DQM0 = 131, DQM1 = 128
9008 09:26:31.877151 DQ Delay:
9009 09:26:31.880729 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
9010 09:26:31.883815 DQ4 =128, DQ5 =142, DQ6 =140, DQ7 =128
9011 09:26:31.886853 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
9012 09:26:31.890474 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =136
9013 09:26:31.890549
9014 09:26:31.890615
9015 09:26:31.890675
9016 09:26:31.893619 [DramC_TX_OE_Calibration] TA2
9017 09:26:31.897245 Original DQ_B0 (3 6) =30, OEN = 27
9018 09:26:31.900293 Original DQ_B1 (3 6) =30, OEN = 27
9019 09:26:31.903711 24, 0x0, End_B0=24 End_B1=24
9020 09:26:31.903788 25, 0x0, End_B0=25 End_B1=25
9021 09:26:31.906772 26, 0x0, End_B0=26 End_B1=26
9022 09:26:31.910311 27, 0x0, End_B0=27 End_B1=27
9023 09:26:31.913415 28, 0x0, End_B0=28 End_B1=28
9024 09:26:31.916656 29, 0x0, End_B0=29 End_B1=29
9025 09:26:31.916761 30, 0x0, End_B0=30 End_B1=30
9026 09:26:31.919799 31, 0x4141, End_B0=30 End_B1=30
9027 09:26:31.923144 Byte0 end_step=30 best_step=27
9028 09:26:31.926675 Byte1 end_step=30 best_step=27
9029 09:26:31.929748 Byte0 TX OE(2T, 0.5T) = (3, 3)
9030 09:26:31.933567 Byte1 TX OE(2T, 0.5T) = (3, 3)
9031 09:26:31.933647
9032 09:26:31.933710
9033 09:26:31.939827 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9034 09:26:31.942928 CH1 RK1: MR19=303, MR18=E1C
9035 09:26:31.949727 CH1_RK1: MR19=0x303, MR18=0xE1C, DQSOSC=395, MR23=63, INC=23, DEC=15
9036 09:26:31.953016 [RxdqsGatingPostProcess] freq 1600
9037 09:26:31.956113 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9038 09:26:31.959512 best DQS0 dly(2T, 0.5T) = (1, 1)
9039 09:26:31.962665 best DQS1 dly(2T, 0.5T) = (1, 1)
9040 09:26:31.966289 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9041 09:26:31.969472 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9042 09:26:31.972418 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 09:26:31.976117 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 09:26:31.979088 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 09:26:31.982615 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 09:26:31.985641 Pre-setting of DQS Precalculation
9047 09:26:31.989262 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9048 09:26:31.999018 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9049 09:26:32.005743 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9050 09:26:32.005824
9051 09:26:32.005887
9052 09:26:32.008716 [Calibration Summary] 3200 Mbps
9053 09:26:32.008785 CH 0, Rank 0
9054 09:26:32.012314 SW Impedance : PASS
9055 09:26:32.012391 DUTY Scan : NO K
9056 09:26:32.015336 ZQ Calibration : PASS
9057 09:26:32.019053 Jitter Meter : NO K
9058 09:26:32.019126 CBT Training : PASS
9059 09:26:32.022176 Write leveling : PASS
9060 09:26:32.025403 RX DQS gating : PASS
9061 09:26:32.025475 RX DQ/DQS(RDDQC) : PASS
9062 09:26:32.028715 TX DQ/DQS : PASS
9063 09:26:32.032055 RX DATLAT : PASS
9064 09:26:32.032126 RX DQ/DQS(Engine): PASS
9065 09:26:32.035419 TX OE : PASS
9066 09:26:32.035526 All Pass.
9067 09:26:32.035618
9068 09:26:32.038403 CH 0, Rank 1
9069 09:26:32.038506 SW Impedance : PASS
9070 09:26:32.041846 DUTY Scan : NO K
9071 09:26:32.044905 ZQ Calibration : PASS
9072 09:26:32.044983 Jitter Meter : NO K
9073 09:26:32.048612 CBT Training : PASS
9074 09:26:32.051695 Write leveling : PASS
9075 09:26:32.051771 RX DQS gating : PASS
9076 09:26:32.054706 RX DQ/DQS(RDDQC) : PASS
9077 09:26:32.054779 TX DQ/DQS : PASS
9078 09:26:32.058204 RX DATLAT : PASS
9079 09:26:32.061683 RX DQ/DQS(Engine): PASS
9080 09:26:32.061786 TX OE : PASS
9081 09:26:32.065071 All Pass.
9082 09:26:32.065169
9083 09:26:32.065289 CH 1, Rank 0
9084 09:26:32.068295 SW Impedance : PASS
9085 09:26:32.068374 DUTY Scan : NO K
9086 09:26:32.071735 ZQ Calibration : PASS
9087 09:26:32.074720 Jitter Meter : NO K
9088 09:26:32.074791 CBT Training : PASS
9089 09:26:32.077946 Write leveling : PASS
9090 09:26:32.081573 RX DQS gating : PASS
9091 09:26:32.081648 RX DQ/DQS(RDDQC) : PASS
9092 09:26:32.084493 TX DQ/DQS : PASS
9093 09:26:32.087804 RX DATLAT : PASS
9094 09:26:32.087874 RX DQ/DQS(Engine): PASS
9095 09:26:32.091379 TX OE : PASS
9096 09:26:32.091450 All Pass.
9097 09:26:32.091516
9098 09:26:32.094351 CH 1, Rank 1
9099 09:26:32.094422 SW Impedance : PASS
9100 09:26:32.098157 DUTY Scan : NO K
9101 09:26:32.101148 ZQ Calibration : PASS
9102 09:26:32.101244 Jitter Meter : NO K
9103 09:26:32.104255 CBT Training : PASS
9104 09:26:32.107372 Write leveling : PASS
9105 09:26:32.107441 RX DQS gating : PASS
9106 09:26:32.111022 RX DQ/DQS(RDDQC) : PASS
9107 09:26:32.114531 TX DQ/DQS : PASS
9108 09:26:32.114627 RX DATLAT : PASS
9109 09:26:32.117815 RX DQ/DQS(Engine): PASS
9110 09:26:32.120953 TX OE : PASS
9111 09:26:32.121047 All Pass.
9112 09:26:32.121121
9113 09:26:32.121190 DramC Write-DBI on
9114 09:26:32.124086 PER_BANK_REFRESH: Hybrid Mode
9115 09:26:32.127132 TX_TRACKING: ON
9116 09:26:32.134025 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9117 09:26:32.144063 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9118 09:26:32.150765 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9119 09:26:32.153792 [FAST_K] Save calibration result to emmc
9120 09:26:32.157006 sync common calibartion params.
9121 09:26:32.160692 sync cbt_mode0:1, 1:1
9122 09:26:32.160774 dram_init: ddr_geometry: 2
9123 09:26:32.163795 dram_init: ddr_geometry: 2
9124 09:26:32.167084 dram_init: ddr_geometry: 2
9125 09:26:32.167167 0:dram_rank_size:100000000
9126 09:26:32.170383 1:dram_rank_size:100000000
9127 09:26:32.177163 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9128 09:26:32.179895 DFS_SHUFFLE_HW_MODE: ON
9129 09:26:32.183500 dramc_set_vcore_voltage set vcore to 725000
9130 09:26:32.183626 Read voltage for 1600, 0
9131 09:26:32.186545 Vio18 = 0
9132 09:26:32.186665 Vcore = 725000
9133 09:26:32.186766 Vdram = 0
9134 09:26:32.190044 Vddq = 0
9135 09:26:32.190198 Vmddr = 0
9136 09:26:32.193328 switch to 3200 Mbps bootup
9137 09:26:32.193510 [DramcRunTimeConfig]
9138 09:26:32.196631 PHYPLL
9139 09:26:32.196786 DPM_CONTROL_AFTERK: ON
9140 09:26:32.200250 PER_BANK_REFRESH: ON
9141 09:26:32.203411 REFRESH_OVERHEAD_REDUCTION: ON
9142 09:26:32.203663 CMD_PICG_NEW_MODE: OFF
9143 09:26:32.206496 XRTWTW_NEW_MODE: ON
9144 09:26:32.206737 XRTRTR_NEW_MODE: ON
9145 09:26:32.209737 TX_TRACKING: ON
9146 09:26:32.210034 RDSEL_TRACKING: OFF
9147 09:26:32.213483 DQS Precalculation for DVFS: ON
9148 09:26:32.216663 RX_TRACKING: OFF
9149 09:26:32.217048 HW_GATING DBG: ON
9150 09:26:32.220312 ZQCS_ENABLE_LP4: ON
9151 09:26:32.220810 RX_PICG_NEW_MODE: ON
9152 09:26:32.223305 TX_PICG_NEW_MODE: ON
9153 09:26:32.223724 ENABLE_RX_DCM_DPHY: ON
9154 09:26:32.226616 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9155 09:26:32.229811 DUMMY_READ_FOR_TRACKING: OFF
9156 09:26:32.233452 !!! SPM_CONTROL_AFTERK: OFF
9157 09:26:32.236384 !!! SPM could not control APHY
9158 09:26:32.236828 IMPEDANCE_TRACKING: ON
9159 09:26:32.239589 TEMP_SENSOR: ON
9160 09:26:32.240055 HW_SAVE_FOR_SR: OFF
9161 09:26:32.243252 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9162 09:26:32.246237 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9163 09:26:32.249499 Read ODT Tracking: ON
9164 09:26:32.253250 Refresh Rate DeBounce: ON
9165 09:26:32.253745 DFS_NO_QUEUE_FLUSH: ON
9166 09:26:32.256144 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9167 09:26:32.259614 ENABLE_DFS_RUNTIME_MRW: OFF
9168 09:26:32.262798 DDR_RESERVE_NEW_MODE: ON
9169 09:26:32.263227 MR_CBT_SWITCH_FREQ: ON
9170 09:26:32.266063 =========================
9171 09:26:32.285181 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9172 09:26:32.288728 dram_init: ddr_geometry: 2
9173 09:26:32.306817 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9174 09:26:32.309987 dram_init: dram init end (result: 0)
9175 09:26:32.316805 DRAM-K: Full calibration passed in 24404 msecs
9176 09:26:32.319896 MRC: failed to locate region type 0.
9177 09:26:32.320424 DRAM rank0 size:0x100000000,
9178 09:26:32.322957 DRAM rank1 size=0x100000000
9179 09:26:32.333133 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9180 09:26:32.339512 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9181 09:26:32.349849 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9182 09:26:32.356140 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9183 09:26:32.356599 DRAM rank0 size:0x100000000,
9184 09:26:32.359151 DRAM rank1 size=0x100000000
9185 09:26:32.359604 CBMEM:
9186 09:26:32.362780 IMD: root @ 0xfffff000 254 entries.
9187 09:26:32.365959 IMD: root @ 0xffffec00 62 entries.
9188 09:26:32.372580 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9189 09:26:32.375500 WARNING: RO_VPD is uninitialized or empty.
9190 09:26:32.378792 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9191 09:26:32.387366 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9192 09:26:32.399890 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9193 09:26:32.411068 BS: romstage times (exec / console): total (unknown) / 23930 ms
9194 09:26:32.411725
9195 09:26:32.412276
9196 09:26:32.421325 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9197 09:26:32.424322 ARM64: Exception handlers installed.
9198 09:26:32.427494 ARM64: Testing exception
9199 09:26:32.430650 ARM64: Done test exception
9200 09:26:32.431104 Enumerating buses...
9201 09:26:32.434272 Show all devs... Before device enumeration.
9202 09:26:32.437509 Root Device: enabled 1
9203 09:26:32.440838 CPU_CLUSTER: 0: enabled 1
9204 09:26:32.441288 CPU: 00: enabled 1
9205 09:26:32.443845 Compare with tree...
9206 09:26:32.444296 Root Device: enabled 1
9207 09:26:32.447432 CPU_CLUSTER: 0: enabled 1
9208 09:26:32.450532 CPU: 00: enabled 1
9209 09:26:32.451057 Root Device scanning...
9210 09:26:32.453686 scan_static_bus for Root Device
9211 09:26:32.457478 CPU_CLUSTER: 0 enabled
9212 09:26:32.460623 scan_static_bus for Root Device done
9213 09:26:32.463659 scan_bus: bus Root Device finished in 8 msecs
9214 09:26:32.464133 done
9215 09:26:32.470469 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9216 09:26:32.473444 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9217 09:26:32.480134 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9218 09:26:32.483750 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9219 09:26:32.486921 Allocating resources...
9220 09:26:32.490154 Reading resources...
9221 09:26:32.493650 Root Device read_resources bus 0 link: 0
9222 09:26:32.496626 DRAM rank0 size:0x100000000,
9223 09:26:32.497076 DRAM rank1 size=0x100000000
9224 09:26:32.503626 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9225 09:26:32.504048 CPU: 00 missing read_resources
9226 09:26:32.510090 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9227 09:26:32.513114 Root Device read_resources bus 0 link: 0 done
9228 09:26:32.516341 Done reading resources.
9229 09:26:32.519896 Show resources in subtree (Root Device)...After reading.
9230 09:26:32.522910 Root Device child on link 0 CPU_CLUSTER: 0
9231 09:26:32.526307 CPU_CLUSTER: 0 child on link 0 CPU: 00
9232 09:26:32.536084 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9233 09:26:32.536523 CPU: 00
9234 09:26:32.539764 Root Device assign_resources, bus 0 link: 0
9235 09:26:32.542891 CPU_CLUSTER: 0 missing set_resources
9236 09:26:32.549737 Root Device assign_resources, bus 0 link: 0 done
9237 09:26:32.550271 Done setting resources.
9238 09:26:32.556199 Show resources in subtree (Root Device)...After assigning values.
9239 09:26:32.559301 Root Device child on link 0 CPU_CLUSTER: 0
9240 09:26:32.563057 CPU_CLUSTER: 0 child on link 0 CPU: 00
9241 09:26:32.572767 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9242 09:26:32.572849 CPU: 00
9243 09:26:32.575757 Done allocating resources.
9244 09:26:32.582549 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9245 09:26:32.582631 Enabling resources...
9246 09:26:32.585604 done.
9247 09:26:32.588500 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9248 09:26:32.592105 Initializing devices...
9249 09:26:32.592186 Root Device init
9250 09:26:32.595281 init hardware done!
9251 09:26:32.595361 0x00000018: ctrlr->caps
9252 09:26:32.598649 52.000 MHz: ctrlr->f_max
9253 09:26:32.601944 0.400 MHz: ctrlr->f_min
9254 09:26:32.602027 0x40ff8080: ctrlr->voltages
9255 09:26:32.605332 sclk: 390625
9256 09:26:32.605443 Bus Width = 1
9257 09:26:32.608383 sclk: 390625
9258 09:26:32.608468 Bus Width = 1
9259 09:26:32.611977 Early init status = 3
9260 09:26:32.614895 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9261 09:26:32.619397 in-header: 03 fc 00 00 01 00 00 00
9262 09:26:32.622139 in-data: 00
9263 09:26:32.625507 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9264 09:26:32.631192 in-header: 03 fd 00 00 00 00 00 00
9265 09:26:32.634600 in-data:
9266 09:26:32.638222 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9267 09:26:32.642684 in-header: 03 fc 00 00 01 00 00 00
9268 09:26:32.645604 in-data: 00
9269 09:26:32.648602 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9270 09:26:32.654722 in-header: 03 fd 00 00 00 00 00 00
9271 09:26:32.658066 in-data:
9272 09:26:32.661107 [SSUSB] Setting up USB HOST controller...
9273 09:26:32.664348 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9274 09:26:32.667544 [SSUSB] phy power-on done.
9275 09:26:32.671264 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9276 09:26:32.677598 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9277 09:26:32.681301 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9278 09:26:32.687479 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9279 09:26:32.694349 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9280 09:26:32.701161 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9281 09:26:32.707496 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9282 09:26:32.714507 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9283 09:26:32.717725 SPM: binary array size = 0x9dc
9284 09:26:32.720835 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9285 09:26:32.727530 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9286 09:26:32.733786 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9287 09:26:32.740340 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9288 09:26:32.743425 configure_display: Starting display init
9289 09:26:32.778299 anx7625_power_on_init: Init interface.
9290 09:26:32.781978 anx7625_disable_pd_protocol: Disabled PD feature.
9291 09:26:32.785128 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9292 09:26:32.812579 anx7625_start_dp_work: Secure OCM version=00
9293 09:26:32.815440 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9294 09:26:32.830227 sp_tx_get_edid_block: EDID Block = 1
9295 09:26:32.933282 Extracted contents:
9296 09:26:32.936066 header: 00 ff ff ff ff ff ff 00
9297 09:26:32.939370 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9298 09:26:32.942685 version: 01 04
9299 09:26:32.946189 basic params: 95 1f 11 78 0a
9300 09:26:32.949731 chroma info: 76 90 94 55 54 90 27 21 50 54
9301 09:26:32.952713 established: 00 00 00
9302 09:26:32.959613 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9303 09:26:32.965821 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9304 09:26:32.969112 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9305 09:26:32.975736 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9306 09:26:32.982350 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9307 09:26:32.985459 extensions: 00
9308 09:26:32.985553 checksum: fb
9309 09:26:32.985631
9310 09:26:32.989267 Manufacturer: IVO Model 57d Serial Number 0
9311 09:26:32.992335 Made week 0 of 2020
9312 09:26:32.995345 EDID version: 1.4
9313 09:26:32.995451 Digital display
9314 09:26:32.998988 6 bits per primary color channel
9315 09:26:32.999112 DisplayPort interface
9316 09:26:33.002082 Maximum image size: 31 cm x 17 cm
9317 09:26:33.005762 Gamma: 220%
9318 09:26:33.005917 Check DPMS levels
9319 09:26:33.011977 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9320 09:26:33.015044 First detailed timing is preferred timing
9321 09:26:33.018613 Established timings supported:
9322 09:26:33.018828 Standard timings supported:
9323 09:26:33.021749 Detailed timings
9324 09:26:33.025304 Hex of detail: 383680a07038204018303c0035ae10000019
9325 09:26:33.032264 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9326 09:26:33.035320 0780 0798 07c8 0820 hborder 0
9327 09:26:33.038436 0438 043b 0447 0458 vborder 0
9328 09:26:33.042094 -hsync -vsync
9329 09:26:33.042548 Did detailed timing
9330 09:26:33.048569 Hex of detail: 000000000000000000000000000000000000
9331 09:26:33.052117 Manufacturer-specified data, tag 0
9332 09:26:33.055570 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9333 09:26:33.058993 ASCII string: InfoVision
9334 09:26:33.061360 Hex of detail: 000000fe00523134304e574635205248200a
9335 09:26:33.065168 ASCII string: R140NWF5 RH
9336 09:26:33.065673 Checksum
9337 09:26:33.068665 Checksum: 0xfb (valid)
9338 09:26:33.071769 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9339 09:26:33.074873 DSI data_rate: 832800000 bps
9340 09:26:33.081407 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9341 09:26:33.084900 anx7625_parse_edid: pixelclock(138800).
9342 09:26:33.087625 hactive(1920), hsync(48), hfp(24), hbp(88)
9343 09:26:33.091232 vactive(1080), vsync(12), vfp(3), vbp(17)
9344 09:26:33.094286 anx7625_dsi_config: config dsi.
9345 09:26:33.100959 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9346 09:26:33.115505 anx7625_dsi_config: success to config DSI
9347 09:26:33.118555 anx7625_dp_start: MIPI phy setup OK.
9348 09:26:33.121760 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9349 09:26:33.125386 mtk_ddp_mode_set invalid vrefresh 60
9350 09:26:33.128256 main_disp_path_setup
9351 09:26:33.128731 ovl_layer_smi_id_en
9352 09:26:33.131829 ovl_layer_smi_id_en
9353 09:26:33.132286 ccorr_config
9354 09:26:33.132621 aal_config
9355 09:26:33.134932 gamma_config
9356 09:26:33.135367 postmask_config
9357 09:26:33.138677 dither_config
9358 09:26:33.141742 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9359 09:26:33.147962 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9360 09:26:33.151574 Root Device init finished in 555 msecs
9361 09:26:33.154393 CPU_CLUSTER: 0 init
9362 09:26:33.161706 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9363 09:26:33.168086 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9364 09:26:33.168538 APU_MBOX 0x190000b0 = 0x10001
9365 09:26:33.171449 APU_MBOX 0x190001b0 = 0x10001
9366 09:26:33.174558 APU_MBOX 0x190005b0 = 0x10001
9367 09:26:33.177762 APU_MBOX 0x190006b0 = 0x10001
9368 09:26:33.184234 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9369 09:26:33.194167 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9370 09:26:33.206407 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9371 09:26:33.213139 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9372 09:26:33.224661 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9373 09:26:33.233786 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9374 09:26:33.237422 CPU_CLUSTER: 0 init finished in 81 msecs
9375 09:26:33.240646 Devices initialized
9376 09:26:33.243758 Show all devs... After init.
9377 09:26:33.244194 Root Device: enabled 1
9378 09:26:33.247366 CPU_CLUSTER: 0: enabled 1
9379 09:26:33.250464 CPU: 00: enabled 1
9380 09:26:33.253599 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9381 09:26:33.257150 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9382 09:26:33.260699 ELOG: NV offset 0x57f000 size 0x1000
9383 09:26:33.267072 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9384 09:26:33.273765 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9385 09:26:33.277387 ELOG: Event(17) added with size 13 at 2024-06-18 09:26:33 UTC
9386 09:26:33.283533 out: cmd=0x121: 03 db 21 01 00 00 00 00
9387 09:26:33.286998 in-header: 03 fa 00 00 2c 00 00 00
9388 09:26:33.296695 in-data: 43 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9389 09:26:33.303072 ELOG: Event(A1) added with size 10 at 2024-06-18 09:26:33 UTC
9390 09:26:33.309753 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9391 09:26:33.316583 ELOG: Event(A0) added with size 9 at 2024-06-18 09:26:33 UTC
9392 09:26:33.319506 elog_add_boot_reason: Logged dev mode boot
9393 09:26:33.326293 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9394 09:26:33.326823 Finalize devices...
9395 09:26:33.329708 Devices finalized
9396 09:26:33.332821 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9397 09:26:33.336140 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9398 09:26:33.339280 in-header: 03 07 00 00 08 00 00 00
9399 09:26:33.342875 in-data: aa e4 47 04 13 02 00 00
9400 09:26:33.345965 Chrome EC: UHEPI supported
9401 09:26:33.352763 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9402 09:26:33.355865 in-header: 03 a9 00 00 08 00 00 00
9403 09:26:33.359700 in-data: 84 60 60 08 00 00 00 00
9404 09:26:33.365716 ELOG: Event(91) added with size 10 at 2024-06-18 09:26:33 UTC
9405 09:26:33.369254 Chrome EC: clear events_b mask to 0x0000000020004000
9406 09:26:33.375719 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9407 09:26:33.380373 in-header: 03 fd 00 00 00 00 00 00
9408 09:26:33.383214 in-data:
9409 09:26:33.386418 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9410 09:26:33.390095 Writing coreboot table at 0xffe64000
9411 09:26:33.396416 0. 000000000010a000-0000000000113fff: RAMSTAGE
9412 09:26:33.400028 1. 0000000040000000-00000000400fffff: RAM
9413 09:26:33.403239 2. 0000000040100000-000000004032afff: RAMSTAGE
9414 09:26:33.406793 3. 000000004032b000-00000000545fffff: RAM
9415 09:26:33.409762 4. 0000000054600000-000000005465ffff: BL31
9416 09:26:33.413024 5. 0000000054660000-00000000ffe63fff: RAM
9417 09:26:33.419798 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9418 09:26:33.422978 7. 0000000100000000-000000023fffffff: RAM
9419 09:26:33.426670 Passing 5 GPIOs to payload:
9420 09:26:33.429394 NAME | PORT | POLARITY | VALUE
9421 09:26:33.436050 EC in RW | 0x000000aa | low | undefined
9422 09:26:33.439254 EC interrupt | 0x00000005 | low | undefined
9423 09:26:33.446159 TPM interrupt | 0x000000ab | high | undefined
9424 09:26:33.449244 SD card detect | 0x00000011 | high | undefined
9425 09:26:33.452270 speaker enable | 0x00000093 | high | undefined
9426 09:26:33.455881 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9427 09:26:33.459558 in-header: 03 f9 00 00 02 00 00 00
9428 09:26:33.462524 in-data: 02 00
9429 09:26:33.466115 ADC[4]: Raw value=901477 ID=7
9430 09:26:33.468699 ADC[3]: Raw value=213546 ID=1
9431 09:26:33.468780 RAM Code: 0x71
9432 09:26:33.472513 ADC[6]: Raw value=75000 ID=0
9433 09:26:33.475798 ADC[5]: Raw value=213546 ID=1
9434 09:26:33.475869 SKU Code: 0x1
9435 09:26:33.482248 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cccd
9436 09:26:33.482691 coreboot table: 964 bytes.
9437 09:26:33.485891 IMD ROOT 0. 0xfffff000 0x00001000
9438 09:26:33.489108 IMD SMALL 1. 0xffffe000 0x00001000
9439 09:26:33.492153 RO MCACHE 2. 0xffffc000 0x00001104
9440 09:26:33.496159 CONSOLE 3. 0xfff7c000 0x00080000
9441 09:26:33.498984 FMAP 4. 0xfff7b000 0x00000452
9442 09:26:33.502444 TIME STAMP 5. 0xfff7a000 0x00000910
9443 09:26:33.505586 VBOOT WORK 6. 0xfff66000 0x00014000
9444 09:26:33.508707 RAMOOPS 7. 0xffe66000 0x00100000
9445 09:26:33.512416 COREBOOT 8. 0xffe64000 0x00002000
9446 09:26:33.515544 IMD small region:
9447 09:26:33.518617 IMD ROOT 0. 0xffffec00 0x00000400
9448 09:26:33.522221 VPD 1. 0xffffeb80 0x0000006c
9449 09:26:33.525344 MMC STATUS 2. 0xffffeb60 0x00000004
9450 09:26:33.532075 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9451 09:26:33.538663 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9452 09:26:33.576953 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9453 09:26:33.580261 Checking segment from ROM address 0x40100000
9454 09:26:33.583750 Checking segment from ROM address 0x4010001c
9455 09:26:33.590020 Loading segment from ROM address 0x40100000
9456 09:26:33.590441 code (compression=0)
9457 09:26:33.599752 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9458 09:26:33.606354 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9459 09:26:33.609719 it's not compressed!
9460 09:26:33.613144 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9461 09:26:33.619284 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9462 09:26:33.637201 Loading segment from ROM address 0x4010001c
9463 09:26:33.637694 Entry Point 0x80000000
9464 09:26:33.640383 Loaded segments
9465 09:26:33.644199 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9466 09:26:33.650743 Jumping to boot code at 0x80000000(0xffe64000)
9467 09:26:33.657341 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9468 09:26:33.663728 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9469 09:26:33.671592 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9470 09:26:33.675140 Checking segment from ROM address 0x40100000
9471 09:26:33.678075 Checking segment from ROM address 0x4010001c
9472 09:26:33.684800 Loading segment from ROM address 0x40100000
9473 09:26:33.685217 code (compression=1)
9474 09:26:33.691786 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9475 09:26:33.701033 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9476 09:26:33.701658 using LZMA
9477 09:26:33.710054 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9478 09:26:33.716814 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9479 09:26:33.720129 Loading segment from ROM address 0x4010001c
9480 09:26:33.720648 Entry Point 0x54601000
9481 09:26:33.723133 Loaded segments
9482 09:26:33.726561 NOTICE: MT8192 bl31_setup
9483 09:26:33.733781 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9484 09:26:33.736967 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9485 09:26:33.740085 WARNING: region 0:
9486 09:26:33.743602 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 09:26:33.744021 WARNING: region 1:
9488 09:26:33.750466 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9489 09:26:33.754060 WARNING: region 2:
9490 09:26:33.756908 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9491 09:26:33.760416 WARNING: region 3:
9492 09:26:33.763536 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9493 09:26:33.767204 WARNING: region 4:
9494 09:26:33.773385 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9495 09:26:33.773823 WARNING: region 5:
9496 09:26:33.776960 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 09:26:33.779725 WARNING: region 6:
9498 09:26:33.783389 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 09:26:33.786656 WARNING: region 7:
9500 09:26:33.790007 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 09:26:33.796351 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9502 09:26:33.799854 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9503 09:26:33.806703 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9504 09:26:33.809871 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9505 09:26:33.813190 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9506 09:26:33.819316 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9507 09:26:33.822920 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9508 09:26:33.826466 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9509 09:26:33.832804 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9510 09:26:33.836539 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9511 09:26:33.842729 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9512 09:26:33.846390 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9513 09:26:33.849338 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9514 09:26:33.856082 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9515 09:26:33.858950 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9516 09:26:33.862496 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9517 09:26:33.869368 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9518 09:26:33.872488 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9519 09:26:33.879255 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9520 09:26:33.882256 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9521 09:26:33.885695 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9522 09:26:33.892367 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9523 09:26:33.895492 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9524 09:26:33.902056 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9525 09:26:33.904918 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9526 09:26:33.908512 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9527 09:26:33.914727 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9528 09:26:33.918293 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9529 09:26:33.924537 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9530 09:26:33.927781 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9531 09:26:33.934958 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9532 09:26:33.937909 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9533 09:26:33.941487 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9534 09:26:33.944447 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9535 09:26:33.951383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9536 09:26:33.954368 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9537 09:26:33.957441 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9538 09:26:33.961102 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9539 09:26:33.967468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9540 09:26:33.971050 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9541 09:26:33.974502 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9542 09:26:33.977654 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9543 09:26:33.984417 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9544 09:26:33.987477 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9545 09:26:33.990972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9546 09:26:33.997401 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9547 09:26:34.001048 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9548 09:26:34.004164 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9549 09:26:34.010792 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9550 09:26:34.013846 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9551 09:26:34.017003 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9552 09:26:34.023727 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9553 09:26:34.026853 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9554 09:26:34.034051 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9555 09:26:34.036785 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9556 09:26:34.043578 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9557 09:26:34.046719 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9558 09:26:34.053332 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9559 09:26:34.056722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9560 09:26:34.060164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9561 09:26:34.066764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9562 09:26:34.069684 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9563 09:26:34.076684 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9564 09:26:34.079594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9565 09:26:34.086425 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9566 09:26:34.089495 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9567 09:26:34.096394 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9568 09:26:34.099311 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9569 09:26:34.106241 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9570 09:26:34.109348 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9571 09:26:34.112284 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9572 09:26:34.119692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9573 09:26:34.122977 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9574 09:26:34.129520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9575 09:26:34.132492 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9576 09:26:34.139385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9577 09:26:34.142505 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9578 09:26:34.149152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9579 09:26:34.152509 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9580 09:26:34.155744 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9581 09:26:34.162057 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9582 09:26:34.165706 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9583 09:26:34.171960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9584 09:26:34.175347 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9585 09:26:34.181976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9586 09:26:34.185385 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9587 09:26:34.188970 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9588 09:26:34.195102 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9589 09:26:34.198451 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9590 09:26:34.204993 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9591 09:26:34.208363 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9592 09:26:34.215255 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9593 09:26:34.218288 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9594 09:26:34.225093 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9595 09:26:34.228615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9596 09:26:34.234669 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9597 09:26:34.238308 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9598 09:26:34.241452 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9599 09:26:34.244570 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9600 09:26:34.251254 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9601 09:26:34.254324 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9602 09:26:34.258067 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9603 09:26:34.264773 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9604 09:26:34.267533 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9605 09:26:34.274458 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9606 09:26:34.277966 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9607 09:26:34.281382 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9608 09:26:34.287650 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9609 09:26:34.290978 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9610 09:26:34.297884 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9611 09:26:34.300961 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9612 09:26:34.303876 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9613 09:26:34.310641 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9614 09:26:34.314159 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9615 09:26:34.320394 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9616 09:26:34.323953 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9617 09:26:34.327024 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9618 09:26:34.333633 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9619 09:26:34.336696 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9620 09:26:34.340408 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9621 09:26:34.343482 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9622 09:26:34.350510 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9623 09:26:34.353738 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9624 09:26:34.356761 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9625 09:26:34.363067 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9626 09:26:34.366886 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9627 09:26:34.369901 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9628 09:26:34.376349 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9629 09:26:34.379960 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9630 09:26:34.386113 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9631 09:26:34.389938 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9632 09:26:34.393150 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9633 09:26:34.399301 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9634 09:26:34.402776 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9635 09:26:34.409607 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9636 09:26:34.412874 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9637 09:26:34.416029 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9638 09:26:34.422659 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9639 09:26:34.426003 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9640 09:26:34.432479 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9641 09:26:34.436181 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9642 09:26:34.439439 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9643 09:26:34.446135 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9644 09:26:34.449149 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9645 09:26:34.455892 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9646 09:26:34.459507 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9647 09:26:34.462688 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9648 09:26:34.469366 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9649 09:26:34.472571 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9650 09:26:34.479084 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9651 09:26:34.482406 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9652 09:26:34.485483 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9653 09:26:34.492300 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9654 09:26:34.495403 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9655 09:26:34.502148 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9656 09:26:34.505291 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9657 09:26:34.508283 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9658 09:26:34.515258 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9659 09:26:34.518752 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9660 09:26:34.525429 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9661 09:26:34.528321 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9662 09:26:34.531403 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9663 09:26:34.538325 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9664 09:26:34.541835 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9665 09:26:34.548198 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9666 09:26:34.551359 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9667 09:26:34.554652 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9668 09:26:34.561342 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9669 09:26:34.564533 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9670 09:26:34.571045 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9671 09:26:34.574223 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9672 09:26:34.581066 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9673 09:26:34.584199 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9674 09:26:34.587287 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9675 09:26:34.593816 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9676 09:26:34.597640 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9677 09:26:34.603742 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9678 09:26:34.607373 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9679 09:26:34.610478 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9680 09:26:34.617239 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9681 09:26:34.620333 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9682 09:26:34.626968 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9683 09:26:34.630481 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9684 09:26:34.633476 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9685 09:26:34.640214 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9686 09:26:34.643811 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9687 09:26:34.646701 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9688 09:26:34.653695 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9689 09:26:34.656703 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9690 09:26:34.663310 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9691 09:26:34.666665 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9692 09:26:34.673126 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9693 09:26:34.676656 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9694 09:26:34.680014 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9695 09:26:34.686321 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9696 09:26:34.689639 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9697 09:26:34.696257 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9698 09:26:34.699816 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9699 09:26:34.706004 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9700 09:26:34.709692 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9701 09:26:34.712640 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9702 09:26:34.719490 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9703 09:26:34.722525 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9704 09:26:34.729363 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9705 09:26:34.732365 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9706 09:26:34.739377 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9707 09:26:34.742390 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9708 09:26:34.745447 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9709 09:26:34.752169 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9710 09:26:34.755652 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9711 09:26:34.761753 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9712 09:26:34.765327 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9713 09:26:34.772089 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9714 09:26:34.775257 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9715 09:26:34.778389 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9716 09:26:34.785185 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9717 09:26:34.788232 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9718 09:26:34.795083 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9719 09:26:34.798262 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9720 09:26:34.804778 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9721 09:26:34.808001 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9722 09:26:34.811689 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9723 09:26:34.818232 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9724 09:26:34.821186 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9725 09:26:34.827958 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9726 09:26:34.831696 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9727 09:26:34.837919 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9728 09:26:34.841248 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9729 09:26:34.844991 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9730 09:26:34.851393 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9731 09:26:34.854643 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9732 09:26:34.857782 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9733 09:26:34.861404 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9734 09:26:34.867650 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9735 09:26:34.870793 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9736 09:26:34.874374 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9737 09:26:34.880661 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9738 09:26:34.883706 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9739 09:26:34.887460 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9740 09:26:34.894105 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9741 09:26:34.897195 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9742 09:26:34.903621 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9743 09:26:34.907428 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9744 09:26:34.910421 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9745 09:26:34.917252 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9746 09:26:34.920585 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9747 09:26:34.927324 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9748 09:26:34.930323 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9749 09:26:34.933576 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9750 09:26:34.940189 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9751 09:26:34.943336 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9752 09:26:34.946822 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9753 09:26:34.953317 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9754 09:26:34.956748 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9755 09:26:34.959857 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9756 09:26:34.966623 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9757 09:26:34.969769 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9758 09:26:34.976314 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9759 09:26:34.979640 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9760 09:26:34.982911 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9761 09:26:34.989619 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9762 09:26:34.992684 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9763 09:26:34.999454 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9764 09:26:35.002663 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9765 09:26:35.005743 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9766 09:26:35.012551 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9767 09:26:35.015680 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9768 09:26:35.018769 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9769 09:26:35.025347 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9770 09:26:35.028866 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9771 09:26:35.032450 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9772 09:26:35.035401 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9773 09:26:35.042203 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9774 09:26:35.045673 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9775 09:26:35.048758 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9776 09:26:35.052084 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9777 09:26:35.058821 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9778 09:26:35.062156 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9779 09:26:35.065372 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9780 09:26:35.068482 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9781 09:26:35.075335 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9782 09:26:35.078497 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9783 09:26:35.081613 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9784 09:26:35.088669 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9785 09:26:35.091296 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9786 09:26:35.098059 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9787 09:26:35.101913 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9788 09:26:35.108097 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9789 09:26:35.111765 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9790 09:26:35.114680 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9791 09:26:35.121413 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9792 09:26:35.124477 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9793 09:26:35.130986 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9794 09:26:35.134677 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9795 09:26:35.141385 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9796 09:26:35.144239 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9797 09:26:35.147915 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9798 09:26:35.153985 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9799 09:26:35.157728 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9800 09:26:35.164226 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9801 09:26:35.167511 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9802 09:26:35.170594 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9803 09:26:35.177199 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9804 09:26:35.180580 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9805 09:26:35.186917 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9806 09:26:35.190511 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9807 09:26:35.197051 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9808 09:26:35.200489 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9809 09:26:35.203810 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9810 09:26:35.210240 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9811 09:26:35.213384 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9812 09:26:35.220060 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9813 09:26:35.223750 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9814 09:26:35.226779 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9815 09:26:35.233492 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9816 09:26:35.236267 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9817 09:26:35.243380 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9818 09:26:35.246367 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9819 09:26:35.252945 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9820 09:26:35.256513 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9821 09:26:35.262623 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9822 09:26:35.266258 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9823 09:26:35.269465 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9824 09:26:35.275786 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9825 09:26:35.279535 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9826 09:26:35.286168 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9827 09:26:35.289291 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9828 09:26:35.292601 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9829 09:26:35.299148 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9830 09:26:35.302429 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9831 09:26:35.308710 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9832 09:26:35.312334 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9833 09:26:35.315777 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9834 09:26:35.322380 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9835 09:26:35.325414 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9836 09:26:35.332290 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9837 09:26:35.335212 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9838 09:26:35.341710 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9839 09:26:35.345392 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9840 09:26:35.348395 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9841 09:26:35.355025 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9842 09:26:35.358143 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9843 09:26:35.364893 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9844 09:26:35.368631 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9845 09:26:35.374924 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9846 09:26:35.378072 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9847 09:26:35.381659 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9848 09:26:35.387737 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9849 09:26:35.391443 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9850 09:26:35.398205 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9851 09:26:35.401051 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9852 09:26:35.404590 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9853 09:26:35.411085 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9854 09:26:35.414267 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9855 09:26:35.421242 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9856 09:26:35.424415 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9857 09:26:35.431049 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9858 09:26:35.434728 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9859 09:26:35.440874 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9860 09:26:35.443895 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9861 09:26:35.447535 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9862 09:26:35.454041 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9863 09:26:35.457553 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9864 09:26:35.463742 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9865 09:26:35.467289 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9866 09:26:35.473517 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9867 09:26:35.477238 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9868 09:26:35.483550 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9869 09:26:35.487258 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9870 09:26:35.490257 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9871 09:26:35.497055 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9872 09:26:35.500187 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9873 09:26:35.506999 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9874 09:26:35.510297 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9875 09:26:35.516410 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9876 09:26:35.519768 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9877 09:26:35.526410 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9878 09:26:35.529857 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9879 09:26:35.533104 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9880 09:26:35.539495 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9881 09:26:35.542724 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9882 09:26:35.549354 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9883 09:26:35.552640 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9884 09:26:35.559047 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9885 09:26:35.562526 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9886 09:26:35.569280 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9887 09:26:35.572227 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9888 09:26:35.576016 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9889 09:26:35.582249 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9890 09:26:35.585387 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9891 09:26:35.592088 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9892 09:26:35.595760 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9893 09:26:35.601888 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9894 09:26:35.605667 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9895 09:26:35.611738 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9896 09:26:35.615138 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9897 09:26:35.618855 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9898 09:26:35.625600 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9899 09:26:35.628427 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9900 09:26:35.635079 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9901 09:26:35.638635 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9902 09:26:35.644800 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9903 09:26:35.648558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9904 09:26:35.651450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9905 09:26:35.657976 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9906 09:26:35.661485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9907 09:26:35.668754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9908 09:26:35.671407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9909 09:26:35.678053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9910 09:26:35.681510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9911 09:26:35.687603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9912 09:26:35.691365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9913 09:26:35.697573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9914 09:26:35.701241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9915 09:26:35.707401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9916 09:26:35.711061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9917 09:26:35.717264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9918 09:26:35.720789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9919 09:26:35.727102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9920 09:26:35.730831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9921 09:26:35.737165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9922 09:26:35.740381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9923 09:26:35.746862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9924 09:26:35.750307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9925 09:26:35.756896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9926 09:26:35.760371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9927 09:26:35.766720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9928 09:26:35.770348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9929 09:26:35.776593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9930 09:26:35.780052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9931 09:26:35.786410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9932 09:26:35.789755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9933 09:26:35.796359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9934 09:26:35.799903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9935 09:26:35.806116 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9936 09:26:35.806224 INFO: [APUAPC] vio 0
9937 09:26:35.813559 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9938 09:26:35.816637 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9939 09:26:35.819742 INFO: [APUAPC] D0_APC_0: 0x400510
9940 09:26:35.823395 INFO: [APUAPC] D0_APC_1: 0x0
9941 09:26:35.826327 INFO: [APUAPC] D0_APC_2: 0x1540
9942 09:26:35.829739 INFO: [APUAPC] D0_APC_3: 0x0
9943 09:26:35.833238 INFO: [APUAPC] D1_APC_0: 0xffffffff
9944 09:26:35.836302 INFO: [APUAPC] D1_APC_1: 0xffffffff
9945 09:26:35.839396 INFO: [APUAPC] D1_APC_2: 0x3fffff
9946 09:26:35.842928 INFO: [APUAPC] D1_APC_3: 0x0
9947 09:26:35.846231 INFO: [APUAPC] D2_APC_0: 0xffffffff
9948 09:26:35.849335 INFO: [APUAPC] D2_APC_1: 0xffffffff
9949 09:26:35.852879 INFO: [APUAPC] D2_APC_2: 0x3fffff
9950 09:26:35.855792 INFO: [APUAPC] D2_APC_3: 0x0
9951 09:26:35.859235 INFO: [APUAPC] D3_APC_0: 0xffffffff
9952 09:26:35.862660 INFO: [APUAPC] D3_APC_1: 0xffffffff
9953 09:26:35.865767 INFO: [APUAPC] D3_APC_2: 0x3fffff
9954 09:26:35.869171 INFO: [APUAPC] D3_APC_3: 0x0
9955 09:26:35.872722 INFO: [APUAPC] D4_APC_0: 0xffffffff
9956 09:26:35.875477 INFO: [APUAPC] D4_APC_1: 0xffffffff
9957 09:26:35.879186 INFO: [APUAPC] D4_APC_2: 0x3fffff
9958 09:26:35.882357 INFO: [APUAPC] D4_APC_3: 0x0
9959 09:26:35.885925 INFO: [APUAPC] D5_APC_0: 0xffffffff
9960 09:26:35.888959 INFO: [APUAPC] D5_APC_1: 0xffffffff
9961 09:26:35.892161 INFO: [APUAPC] D5_APC_2: 0x3fffff
9962 09:26:35.895869 INFO: [APUAPC] D5_APC_3: 0x0
9963 09:26:35.898984 INFO: [APUAPC] D6_APC_0: 0xffffffff
9964 09:26:35.902580 INFO: [APUAPC] D6_APC_1: 0xffffffff
9965 09:26:35.905319 INFO: [APUAPC] D6_APC_2: 0x3fffff
9966 09:26:35.905396 INFO: [APUAPC] D6_APC_3: 0x0
9967 09:26:35.912230 INFO: [APUAPC] D7_APC_0: 0xffffffff
9968 09:26:35.915076 INFO: [APUAPC] D7_APC_1: 0xffffffff
9969 09:26:35.918802 INFO: [APUAPC] D7_APC_2: 0x3fffff
9970 09:26:35.918889 INFO: [APUAPC] D7_APC_3: 0x0
9971 09:26:35.924889 INFO: [APUAPC] D8_APC_0: 0xffffffff
9972 09:26:35.928598 INFO: [APUAPC] D8_APC_1: 0xffffffff
9973 09:26:35.931793 INFO: [APUAPC] D8_APC_2: 0x3fffff
9974 09:26:35.931877 INFO: [APUAPC] D8_APC_3: 0x0
9975 09:26:35.934818 INFO: [APUAPC] D9_APC_0: 0xffffffff
9976 09:26:35.941847 INFO: [APUAPC] D9_APC_1: 0xffffffff
9977 09:26:35.944953 INFO: [APUAPC] D9_APC_2: 0x3fffff
9978 09:26:35.945029 INFO: [APUAPC] D9_APC_3: 0x0
9979 09:26:35.948115 INFO: [APUAPC] D10_APC_0: 0xffffffff
9980 09:26:35.954752 INFO: [APUAPC] D10_APC_1: 0xffffffff
9981 09:26:35.957964 INFO: [APUAPC] D10_APC_2: 0x3fffff
9982 09:26:35.958046 INFO: [APUAPC] D10_APC_3: 0x0
9983 09:26:35.964495 INFO: [APUAPC] D11_APC_0: 0xffffffff
9984 09:26:35.968040 INFO: [APUAPC] D11_APC_1: 0xffffffff
9985 09:26:35.971041 INFO: [APUAPC] D11_APC_2: 0x3fffff
9986 09:26:35.974447 INFO: [APUAPC] D11_APC_3: 0x0
9987 09:26:35.978080 INFO: [APUAPC] D12_APC_0: 0xffffffff
9988 09:26:35.980952 INFO: [APUAPC] D12_APC_1: 0xffffffff
9989 09:26:35.984404 INFO: [APUAPC] D12_APC_2: 0x3fffff
9990 09:26:35.988073 INFO: [APUAPC] D12_APC_3: 0x0
9991 09:26:35.990997 INFO: [APUAPC] D13_APC_0: 0xffffffff
9992 09:26:35.994632 INFO: [APUAPC] D13_APC_1: 0xffffffff
9993 09:26:35.997732 INFO: [APUAPC] D13_APC_2: 0x3fffff
9994 09:26:36.000816 INFO: [APUAPC] D13_APC_3: 0x0
9995 09:26:36.004448 INFO: [APUAPC] D14_APC_0: 0xffffffff
9996 09:26:36.007577 INFO: [APUAPC] D14_APC_1: 0xffffffff
9997 09:26:36.010687 INFO: [APUAPC] D14_APC_2: 0x3fffff
9998 09:26:36.014360 INFO: [APUAPC] D14_APC_3: 0x0
9999 09:26:36.017186 INFO: [APUAPC] D15_APC_0: 0xffffffff
10000 09:26:36.020631 INFO: [APUAPC] D15_APC_1: 0xffffffff
10001 09:26:36.023735 INFO: [APUAPC] D15_APC_2: 0x3fffff
10002 09:26:36.027042 INFO: [APUAPC] D15_APC_3: 0x0
10003 09:26:36.030640 INFO: [APUAPC] APC_CON: 0x4
10004 09:26:36.030727 INFO: [NOCDAPC] D0_APC_0: 0x0
10005 09:26:36.033663 INFO: [NOCDAPC] D0_APC_1: 0x0
10006 09:26:36.037198 INFO: [NOCDAPC] D1_APC_0: 0x0
10007 09:26:36.040291 INFO: [NOCDAPC] D1_APC_1: 0xfff
10008 09:26:36.043920 INFO: [NOCDAPC] D2_APC_0: 0x0
10009 09:26:36.047313 INFO: [NOCDAPC] D2_APC_1: 0xfff
10010 09:26:36.050377 INFO: [NOCDAPC] D3_APC_0: 0x0
10011 09:26:36.053470 INFO: [NOCDAPC] D3_APC_1: 0xfff
10012 09:26:36.057111 INFO: [NOCDAPC] D4_APC_0: 0x0
10013 09:26:36.060165 INFO: [NOCDAPC] D4_APC_1: 0xfff
10014 09:26:36.063428 INFO: [NOCDAPC] D5_APC_0: 0x0
10015 09:26:36.066897 INFO: [NOCDAPC] D5_APC_1: 0xfff
10016 09:26:36.067006 INFO: [NOCDAPC] D6_APC_0: 0x0
10017 09:26:36.069850 INFO: [NOCDAPC] D6_APC_1: 0xfff
10018 09:26:36.073227 INFO: [NOCDAPC] D7_APC_0: 0x0
10019 09:26:36.076718 INFO: [NOCDAPC] D7_APC_1: 0xfff
10020 09:26:36.079809 INFO: [NOCDAPC] D8_APC_0: 0x0
10021 09:26:36.082911 INFO: [NOCDAPC] D8_APC_1: 0xfff
10022 09:26:36.086351 INFO: [NOCDAPC] D9_APC_0: 0x0
10023 09:26:36.089840 INFO: [NOCDAPC] D9_APC_1: 0xfff
10024 09:26:36.092700 INFO: [NOCDAPC] D10_APC_0: 0x0
10025 09:26:36.096049 INFO: [NOCDAPC] D10_APC_1: 0xfff
10026 09:26:36.099192 INFO: [NOCDAPC] D11_APC_0: 0x0
10027 09:26:36.102935 INFO: [NOCDAPC] D11_APC_1: 0xfff
10028 09:26:36.106150 INFO: [NOCDAPC] D12_APC_0: 0x0
10029 09:26:36.109200 INFO: [NOCDAPC] D12_APC_1: 0xfff
10030 09:26:36.109311 INFO: [NOCDAPC] D13_APC_0: 0x0
10031 09:26:36.112379 INFO: [NOCDAPC] D13_APC_1: 0xfff
10032 09:26:36.116023 INFO: [NOCDAPC] D14_APC_0: 0x0
10033 09:26:36.119238 INFO: [NOCDAPC] D14_APC_1: 0xfff
10034 09:26:36.122831 INFO: [NOCDAPC] D15_APC_0: 0x0
10035 09:26:36.126122 INFO: [NOCDAPC] D15_APC_1: 0xfff
10036 09:26:36.129127 INFO: [NOCDAPC] APC_CON: 0x4
10037 09:26:36.132483 INFO: [APUAPC] set_apusys_apc done
10038 09:26:36.135705 INFO: [DEVAPC] devapc_init done
10039 09:26:36.138698 INFO: GICv3 without legacy support detected.
10040 09:26:36.145412 INFO: ARM GICv3 driver initialized in EL3
10041 09:26:36.149140 INFO: Maximum SPI INTID supported: 639
10042 09:26:36.152124 INFO: BL31: Initializing runtime services
10043 09:26:36.158419 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10044 09:26:36.158499 INFO: SPM: enable CPC mode
10045 09:26:36.165115 INFO: mcdi ready for mcusys-off-idle and system suspend
10046 09:26:36.168636 INFO: BL31: Preparing for EL3 exit to normal world
10047 09:26:36.174941 INFO: Entry point address = 0x80000000
10048 09:26:36.175019 INFO: SPSR = 0x8
10049 09:26:36.181285
10050 09:26:36.181371
10051 09:26:36.181434
10052 09:26:36.184938 Starting depthcharge on Spherion...
10053 09:26:36.185013
10054 09:26:36.185097 Wipe memory regions:
10055 09:26:36.185220
10056 09:26:36.185895 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10057 09:26:36.185997 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10058 09:26:36.186082 Setting prompt string to ['asurada:']
10059 09:26:36.186170 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10060 09:26:36.187960 [0x00000040000000, 0x00000054600000)
10061 09:26:36.310322
10062 09:26:36.310445 [0x00000054660000, 0x00000080000000)
10063 09:26:36.570936
10064 09:26:36.571467 [0x000000821a7280, 0x000000ffe64000)
10065 09:26:37.315766
10066 09:26:37.315905 [0x00000100000000, 0x00000240000000)
10067 09:26:39.206180
10068 09:26:39.209032 Initializing XHCI USB controller at 0x11200000.
10069 09:26:40.247631
10070 09:26:40.250586 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10071 09:26:40.250674
10072 09:26:40.250748
10073 09:26:40.251033 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10075 09:26:40.351393 asurada: tftpboot 192.168.201.1 14407630/tftp-deploy-pu_owxyt/kernel/image.itb 14407630/tftp-deploy-pu_owxyt/kernel/cmdline
10076 09:26:40.351555 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10077 09:26:40.351650 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10078 09:26:40.355651 tftpboot 192.168.201.1 14407630/tftp-deploy-pu_owxyt/kernel/image.itp-deploy-pu_owxyt/kernel/cmdline
10079 09:26:40.355761
10080 09:26:40.355855 Waiting for link
10081 09:26:40.514027
10082 09:26:40.514174 R8152: Initializing
10083 09:26:40.514245
10084 09:26:40.517381 Version 6 (ocp_data = 5c30)
10085 09:26:40.517459
10086 09:26:40.520495 R8152: Done initializing
10087 09:26:40.520600
10088 09:26:40.520707 Adding net device
10089 09:26:42.614954
10090 09:26:42.615111 done.
10091 09:26:42.615183
10092 09:26:42.615254 MAC: 00:24:32:30:7c:7b
10093 09:26:42.615320
10094 09:26:42.618000 Sending DHCP discover... done.
10095 09:26:42.618077
10096 09:26:42.621158 Waiting for reply... done.
10097 09:26:42.621292
10098 09:26:42.624230 Sending DHCP request... done.
10099 09:26:42.624329
10100 09:26:42.627929 Waiting for reply... done.
10101 09:26:42.628042
10102 09:26:42.628132 My ip is 192.168.201.14
10103 09:26:42.628222
10104 09:26:42.631088 The DHCP server ip is 192.168.201.1
10105 09:26:42.631172
10106 09:26:42.637861 TFTP server IP predefined by user: 192.168.201.1
10107 09:26:42.637972
10108 09:26:42.644180 Bootfile predefined by user: 14407630/tftp-deploy-pu_owxyt/kernel/image.itb
10109 09:26:42.644258
10110 09:26:42.647194 Sending tftp read request... done.
10111 09:26:42.647272
10112 09:26:42.651486 Waiting for the transfer...
10113 09:26:42.651575
10114 09:26:43.202481 00000000 ################################################################
10115 09:26:43.202626
10116 09:26:43.771884 00080000 ################################################################
10117 09:26:43.772028
10118 09:26:44.348072 00100000 ################################################################
10119 09:26:44.348221
10120 09:26:44.928095 00180000 ################################################################
10121 09:26:44.928242
10122 09:26:45.573885 00200000 ################################################################
10123 09:26:45.574020
10124 09:26:46.145275 00280000 ################################################################
10125 09:26:46.145477
10126 09:26:46.724394 00300000 ################################################################
10127 09:26:46.724539
10128 09:26:47.294004 00380000 ################################################################
10129 09:26:47.294142
10130 09:26:47.853479 00400000 ################################################################
10131 09:26:47.853615
10132 09:26:48.414891 00480000 ################################################################
10133 09:26:48.415025
10134 09:26:49.053758 00500000 ################################################################
10135 09:26:49.053907
10136 09:26:49.648457 00580000 ################################################################
10137 09:26:49.648596
10138 09:26:50.230761 00600000 ################################################################
10139 09:26:50.230914
10140 09:26:50.809014 00680000 ################################################################
10141 09:26:50.809608
10142 09:26:51.450550 00700000 ################################################################
10143 09:26:51.450694
10144 09:26:52.029075 00780000 ################################################################
10145 09:26:52.029251
10146 09:26:52.695707 00800000 ################################################################
10147 09:26:52.696203
10148 09:26:53.361466 00880000 ################################################################
10149 09:26:53.361988
10150 09:26:54.034591 00900000 ################################################################
10151 09:26:54.035081
10152 09:26:54.746277 00980000 ################################################################
10153 09:26:54.746779
10154 09:26:55.389882 00a00000 ################################################################
10155 09:26:55.390551
10156 09:26:56.061558 00a80000 ################################################################
10157 09:26:56.062098
10158 09:26:56.724496 00b00000 ################################################################
10159 09:26:56.724989
10160 09:26:57.401210 00b80000 ################################################################
10161 09:26:57.401759
10162 09:26:58.092983 00c00000 ################################################################
10163 09:26:58.093266
10164 09:26:58.742662 00c80000 ################################################################
10165 09:26:58.743219
10166 09:26:59.423814 00d00000 ################################################################
10167 09:26:59.424368
10168 09:27:00.010483 00d80000 ################################################################
10169 09:27:00.010634
10170 09:27:00.583907 00e00000 ################################################################
10171 09:27:00.584052
10172 09:27:01.149703 00e80000 ################################################################
10173 09:27:01.149854
10174 09:27:01.794501 00f00000 ################################################################
10175 09:27:01.795047
10176 09:27:02.496745 00f80000 ################################################################
10177 09:27:02.497397
10178 09:27:03.209547 01000000 ################################################################
10179 09:27:03.210091
10180 09:27:03.877228 01080000 ################################################################
10181 09:27:03.877584
10182 09:27:04.505597 01100000 ################################################################
10183 09:27:04.505745
10184 09:27:05.127203 01180000 ################################################################
10185 09:27:05.127695
10186 09:27:05.773169 01200000 ################################################################
10187 09:27:05.773746
10188 09:27:06.390505 01280000 ################################################################
10189 09:27:06.391026
10190 09:27:07.062480 01300000 ################################################################
10191 09:27:07.063185
10192 09:27:07.642928 01380000 ################################################################
10193 09:27:07.643119
10194 09:27:08.196008 01400000 ################################################################
10195 09:27:08.196157
10196 09:27:08.753878 01480000 ################################################################
10197 09:27:08.754034
10198 09:27:09.305176 01500000 ################################################################
10199 09:27:09.305348
10200 09:27:09.849800 01580000 ################################################################
10201 09:27:09.849951
10202 09:27:10.397718 01600000 ################################################################
10203 09:27:10.397868
10204 09:27:10.955240 01680000 ################################################################
10205 09:27:10.955395
10206 09:27:11.514388 01700000 ################################################################
10207 09:27:11.514535
10208 09:27:12.060666 01780000 ################################################################
10209 09:27:12.060823
10210 09:27:12.617753 01800000 ################################################################
10211 09:27:12.617909
10212 09:27:13.154545 01880000 ################################################################
10213 09:27:13.154729
10214 09:27:13.680903 01900000 ################################################################
10215 09:27:13.681056
10216 09:27:14.302282 01980000 ################################################################
10217 09:27:14.302429
10218 09:27:14.852770 01a00000 ################################################################
10219 09:27:14.852914
10220 09:27:15.406796 01a80000 ################################################################
10221 09:27:15.406945
10222 09:27:15.949281 01b00000 ################################################################
10223 09:27:15.949446
10224 09:27:16.480747 01b80000 ################################################################
10225 09:27:16.480905
10226 09:27:17.020271 01c00000 ################################################################
10227 09:27:17.020417
10228 09:27:17.567955 01c80000 ################################################################
10229 09:27:17.568099
10230 09:27:18.174774 01d00000 ################################################################
10231 09:27:18.174934
10232 09:27:18.735137 01d80000 ################################################################
10233 09:27:18.735286
10234 09:27:19.203324 01e00000 ######################################################## done.
10235 09:27:19.206762
10236 09:27:19.206866 The bootfile was 31910454 bytes long.
10237 09:27:19.210388
10238 09:27:19.210467 Sending tftp read request... done.
10239 09:27:19.210541
10240 09:27:19.213561 Waiting for the transfer...
10241 09:27:19.213651
10242 09:27:19.216612 00000000 # done.
10243 09:27:19.216712
10244 09:27:19.223107 Command line loaded dynamically from TFTP file: 14407630/tftp-deploy-pu_owxyt/kernel/cmdline
10245 09:27:19.223192
10246 09:27:19.245873 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407630/extract-nfsrootfs-mb0x_k8b,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10247 09:27:19.245966
10248 09:27:19.246031 Loading FIT.
10249 09:27:19.246093
10250 09:27:19.249511 Image ramdisk-1 has 18734435 bytes.
10251 09:27:19.249594
10252 09:27:19.252869 Image fdt-1 has 47258 bytes.
10253 09:27:19.252977
10254 09:27:19.255964 Image kernel-1 has 13126726 bytes.
10255 09:27:19.256072
10256 09:27:19.265911 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10257 09:27:19.265995
10258 09:27:19.282297 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10259 09:27:19.282389
10260 09:27:19.289044 Choosing best match conf-1 for compat google,spherion-rev2.
10261 09:27:19.289128
10262 09:27:19.296898 Connected to device vid:did:rid of 1ae0:0028:00
10263 09:27:19.304664
10264 09:27:19.308245 tpm_get_response: command 0x17b, return code 0x0
10265 09:27:19.308346
10266 09:27:19.314777 ec_init: CrosEC protocol v3 supported (256, 248)
10267 09:27:19.314876
10268 09:27:19.317823 tpm_cleanup: add release locality here.
10269 09:27:19.317923
10270 09:27:19.321277 Shutting down all USB controllers.
10271 09:27:19.321375
10272 09:27:19.324479 Removing current net device
10273 09:27:19.324560
10274 09:27:19.328021 Exiting depthcharge with code 4 at timestamp: 72371255
10275 09:27:19.328121
10276 09:27:19.334759 LZMA decompressing kernel-1 to 0x821a6718
10277 09:27:19.334858
10278 09:27:19.337769 LZMA decompressing kernel-1 to 0x40000000
10279 09:27:20.954915
10280 09:27:20.955068 jumping to kernel
10281 09:27:20.955546 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10282 09:27:20.955645 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10283 09:27:20.955731 Setting prompt string to ['Linux version [0-9]']
10284 09:27:20.955807 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10285 09:27:20.955875 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10286 09:27:21.036860
10287 09:27:21.039956 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10288 09:27:21.043763 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10289 09:27:21.043897 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10290 09:27:21.043986 Setting prompt string to []
10291 09:27:21.044075 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10292 09:27:21.044150 Using line separator: #'\n'#
10293 09:27:21.044218 No login prompt set.
10294 09:27:21.044281 Parsing kernel messages
10295 09:27:21.044336 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10296 09:27:21.044455 [login-action] Waiting for messages, (timeout 00:03:42)
10297 09:27:21.044523 Waiting using forced prompt support (timeout 00:01:51)
10298 09:27:21.063231 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
10299 09:27:21.066701 [ 0.000000] random: crng init done
10300 09:27:21.072922 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10301 09:27:21.076677 [ 0.000000] efi: UEFI not found.
10302 09:27:21.083154 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10303 09:27:21.089653 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10304 09:27:21.099699 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10305 09:27:21.109883 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10306 09:27:21.116370 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10307 09:27:21.122920 [ 0.000000] printk: bootconsole [mtk8250] enabled
10308 09:27:21.129510 [ 0.000000] NUMA: No NUMA configuration found
10309 09:27:21.136284 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10310 09:27:21.139582 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10311 09:27:21.142852 [ 0.000000] Zone ranges:
10312 09:27:21.149264 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10313 09:27:21.152492 [ 0.000000] DMA32 empty
10314 09:27:21.159080 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10315 09:27:21.162784 [ 0.000000] Movable zone start for each node
10316 09:27:21.165823 [ 0.000000] Early memory node ranges
10317 09:27:21.172603 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10318 09:27:21.179231 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10319 09:27:21.185437 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10320 09:27:21.192117 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10321 09:27:21.199074 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10322 09:27:21.205529 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10323 09:27:21.261156 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10324 09:27:21.267731 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10325 09:27:21.274447 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10326 09:27:21.277976 [ 0.000000] psci: probing for conduit method from DT.
10327 09:27:21.284717 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10328 09:27:21.288032 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10329 09:27:21.294608 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10330 09:27:21.298324 [ 0.000000] psci: SMC Calling Convention v1.2
10331 09:27:21.304939 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10332 09:27:21.307676 [ 0.000000] Detected VIPT I-cache on CPU0
10333 09:27:21.314297 [ 0.000000] CPU features: detected: GIC system register CPU interface
10334 09:27:21.321129 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10335 09:27:21.327631 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10336 09:27:21.334452 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10337 09:27:21.341106 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10338 09:27:21.347918 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10339 09:27:21.355010 [ 0.000000] alternatives: applying boot alternatives
10340 09:27:21.360974 [ 0.000000] Fallback order for Node 0: 0
10341 09:27:21.367654 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10342 09:27:21.370616 [ 0.000000] Policy zone: Normal
10343 09:27:21.394095 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407630/extract-nfsrootfs-mb0x_k8b,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10344 09:27:21.403945 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10345 09:27:21.414543 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10346 09:27:21.424312 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10347 09:27:21.430988 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10348 09:27:21.434477 <6>[ 0.000000] software IO TLB: area num 8.
10349 09:27:21.490642 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10350 09:27:21.640279 <6>[ 0.000000] Memory: 7945756K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407012K reserved, 32768K cma-reserved)
10351 09:27:21.646749 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10352 09:27:21.653436 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10353 09:27:21.656381 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10354 09:27:21.663217 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10355 09:27:21.669704 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10356 09:27:21.676427 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10357 09:27:21.683195 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10358 09:27:21.689835 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10359 09:27:21.695677 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10360 09:27:21.702334 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10361 09:27:21.705949 <6>[ 0.000000] GICv3: 608 SPIs implemented
10362 09:27:21.709002 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10363 09:27:21.715920 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10364 09:27:21.718951 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10365 09:27:21.725863 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10366 09:27:21.738966 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10367 09:27:21.751929 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10368 09:27:21.758593 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10369 09:27:21.767077 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10370 09:27:21.780182 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10371 09:27:21.786927 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10372 09:27:21.793427 <6>[ 0.009226] Console: colour dummy device 80x25
10373 09:27:21.803481 <6>[ 0.013952] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10374 09:27:21.810048 <6>[ 0.024394] pid_max: default: 32768 minimum: 301
10375 09:27:21.813121 <6>[ 0.029267] LSM: Security Framework initializing
10376 09:27:21.819720 <6>[ 0.034205] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10377 09:27:21.829850 <6>[ 0.041988] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10378 09:27:21.836425 <6>[ 0.051455] cblist_init_generic: Setting adjustable number of callback queues.
10379 09:27:21.842932 <6>[ 0.058895] cblist_init_generic: Setting shift to 3 and lim to 1.
10380 09:27:21.853086 <6>[ 0.065234] cblist_init_generic: Setting adjustable number of callback queues.
10381 09:27:21.859559 <6>[ 0.072666] cblist_init_generic: Setting shift to 3 and lim to 1.
10382 09:27:21.862590 <6>[ 0.079067] rcu: Hierarchical SRCU implementation.
10383 09:27:21.869903 <6>[ 0.084082] rcu: Max phase no-delay instances is 1000.
10384 09:27:21.876226 <6>[ 0.091119] EFI services will not be available.
10385 09:27:21.879122 <6>[ 0.096076] smp: Bringing up secondary CPUs ...
10386 09:27:21.887656 <6>[ 0.101127] Detected VIPT I-cache on CPU1
10387 09:27:21.894361 <6>[ 0.101202] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10388 09:27:21.900848 <6>[ 0.101233] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10389 09:27:21.903879 <6>[ 0.101572] Detected VIPT I-cache on CPU2
10390 09:27:21.913692 <6>[ 0.101626] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10391 09:27:21.920192 <6>[ 0.101646] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10392 09:27:21.923884 <6>[ 0.101902] Detected VIPT I-cache on CPU3
10393 09:27:21.930591 <6>[ 0.101949] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10394 09:27:21.936845 <6>[ 0.101964] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10395 09:27:21.943729 <6>[ 0.102268] CPU features: detected: Spectre-v4
10396 09:27:21.946909 <6>[ 0.102274] CPU features: detected: Spectre-BHB
10397 09:27:21.949981 <6>[ 0.102279] Detected PIPT I-cache on CPU4
10398 09:27:21.956578 <6>[ 0.102337] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10399 09:27:21.963303 <6>[ 0.102354] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10400 09:27:21.969797 <6>[ 0.102649] Detected PIPT I-cache on CPU5
10401 09:27:21.976577 <6>[ 0.102711] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10402 09:27:21.983419 <6>[ 0.102728] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10403 09:27:21.986378 <6>[ 0.103010] Detected PIPT I-cache on CPU6
10404 09:27:21.992929 <6>[ 0.103076] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10405 09:27:21.999728 <6>[ 0.103092] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10406 09:27:22.006287 <6>[ 0.103389] Detected PIPT I-cache on CPU7
10407 09:27:22.013093 <6>[ 0.103455] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10408 09:27:22.019615 <6>[ 0.103471] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10409 09:27:22.022829 <6>[ 0.103518] smp: Brought up 1 node, 8 CPUs
10410 09:27:22.029219 <6>[ 0.244854] SMP: Total of 8 processors activated.
10411 09:27:22.032895 <6>[ 0.249805] CPU features: detected: 32-bit EL0 Support
10412 09:27:22.042814 <6>[ 0.255169] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10413 09:27:22.049028 <6>[ 0.263970] CPU features: detected: Common not Private translations
10414 09:27:22.055774 <6>[ 0.270446] CPU features: detected: CRC32 instructions
10415 09:27:22.062427 <6>[ 0.275798] CPU features: detected: RCpc load-acquire (LDAPR)
10416 09:27:22.065648 <6>[ 0.281795] CPU features: detected: LSE atomic instructions
10417 09:27:22.072017 <6>[ 0.287576] CPU features: detected: Privileged Access Never
10418 09:27:22.078583 <6>[ 0.293391] CPU features: detected: RAS Extension Support
10419 09:27:22.085250 <6>[ 0.299000] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10420 09:27:22.088840 <6>[ 0.306219] CPU: All CPU(s) started at EL2
10421 09:27:22.095005 <6>[ 0.310563] alternatives: applying system-wide alternatives
10422 09:27:22.105263 <6>[ 0.321435] devtmpfs: initialized
10423 09:27:22.117681 <6>[ 0.330265] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10424 09:27:22.127320 <6>[ 0.340227] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10425 09:27:22.134094 <6>[ 0.348243] pinctrl core: initialized pinctrl subsystem
10426 09:27:22.137389 <6>[ 0.354935] DMI not present or invalid.
10427 09:27:22.144272 <6>[ 0.359346] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10428 09:27:22.150873 <6>[ 0.366218] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10429 09:27:22.161120 <6>[ 0.373804] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10430 09:27:22.167926 <6>[ 0.382025] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10431 09:27:22.174300 <6>[ 0.390269] audit: initializing netlink subsys (disabled)
10432 09:27:22.184057 <5>[ 0.395964] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10433 09:27:22.190745 <6>[ 0.396697] thermal_sys: Registered thermal governor 'step_wise'
10434 09:27:22.197241 <6>[ 0.403931] thermal_sys: Registered thermal governor 'power_allocator'
10435 09:27:22.200823 <6>[ 0.410186] cpuidle: using governor menu
10436 09:27:22.203977 <6>[ 0.421146] NET: Registered PF_QIPCRTR protocol family
10437 09:27:22.214192 <6>[ 0.426635] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10438 09:27:22.217165 <6>[ 0.433737] ASID allocator initialised with 32768 entries
10439 09:27:22.224601 <6>[ 0.440323] Serial: AMBA PL011 UART driver
10440 09:27:22.232980 <4>[ 0.449158] Trying to register duplicate clock ID: 134
10441 09:27:22.291567 <6>[ 0.510647] KASLR enabled
10442 09:27:22.305906 <6>[ 0.518376] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10443 09:27:22.312178 <6>[ 0.525391] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10444 09:27:22.319036 <6>[ 0.531877] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10445 09:27:22.325596 <6>[ 0.538879] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10446 09:27:22.332313 <6>[ 0.545366] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10447 09:27:22.338921 <6>[ 0.552370] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10448 09:27:22.345581 <6>[ 0.558856] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10449 09:27:22.352056 <6>[ 0.565859] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10450 09:27:22.355104 <6>[ 0.573365] ACPI: Interpreter disabled.
10451 09:27:22.363588 <6>[ 0.579772] iommu: Default domain type: Translated
10452 09:27:22.370380 <6>[ 0.584885] iommu: DMA domain TLB invalidation policy: strict mode
10453 09:27:22.373830 <5>[ 0.591544] SCSI subsystem initialized
10454 09:27:22.380554 <6>[ 0.595708] usbcore: registered new interface driver usbfs
10455 09:27:22.386858 <6>[ 0.601440] usbcore: registered new interface driver hub
10456 09:27:22.390290 <6>[ 0.606993] usbcore: registered new device driver usb
10457 09:27:22.396834 <6>[ 0.613092] pps_core: LinuxPPS API ver. 1 registered
10458 09:27:22.407187 <6>[ 0.618286] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10459 09:27:22.410098 <6>[ 0.627633] PTP clock support registered
10460 09:27:22.413431 <6>[ 0.631879] EDAC MC: Ver: 3.0.0
10461 09:27:22.422027 <6>[ 0.637045] FPGA manager framework
10462 09:27:22.427722 <6>[ 0.640732] Advanced Linux Sound Architecture Driver Initialized.
10463 09:27:22.430625 <6>[ 0.647512] vgaarb: loaded
10464 09:27:22.437575 <6>[ 0.650668] clocksource: Switched to clocksource arch_sys_counter
10465 09:27:22.440540 <5>[ 0.657107] VFS: Disk quotas dquot_6.6.0
10466 09:27:22.447063 <6>[ 0.661291] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10467 09:27:22.450786 <6>[ 0.668483] pnp: PnP ACPI: disabled
10468 09:27:22.459142 <6>[ 0.675198] NET: Registered PF_INET protocol family
10469 09:27:22.468781 <6>[ 0.680797] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10470 09:27:22.480534 <6>[ 0.693138] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10471 09:27:22.490294 <6>[ 0.701953] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10472 09:27:22.496653 <6>[ 0.709925] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10473 09:27:22.506895 <6>[ 0.718626] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10474 09:27:22.513432 <6>[ 0.728382] TCP: Hash tables configured (established 65536 bind 65536)
10475 09:27:22.519789 <6>[ 0.735244] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10476 09:27:22.529656 <6>[ 0.742442] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10477 09:27:22.536635 <6>[ 0.750143] NET: Registered PF_UNIX/PF_LOCAL protocol family
10478 09:27:22.543629 <6>[ 0.756298] RPC: Registered named UNIX socket transport module.
10479 09:27:22.546798 <6>[ 0.762450] RPC: Registered udp transport module.
10480 09:27:22.553083 <6>[ 0.767381] RPC: Registered tcp transport module.
10481 09:27:22.559409 <6>[ 0.772313] RPC: Registered tcp NFSv4.1 backchannel transport module.
10482 09:27:22.563071 <6>[ 0.778982] PCI: CLS 0 bytes, default 64
10483 09:27:22.565793 <6>[ 0.783317] Unpacking initramfs...
10484 09:27:22.589926 <6>[ 0.802784] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10485 09:27:22.599824 <6>[ 0.811433] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10486 09:27:22.603088 <6>[ 0.820278] kvm [1]: IPA Size Limit: 40 bits
10487 09:27:22.609995 <6>[ 0.824813] kvm [1]: GICv3: no GICV resource entry
10488 09:27:22.613368 <6>[ 0.829833] kvm [1]: disabling GICv2 emulation
10489 09:27:22.619788 <6>[ 0.834523] kvm [1]: GIC system register CPU interface enabled
10490 09:27:22.622913 <6>[ 0.840681] kvm [1]: vgic interrupt IRQ18
10491 09:27:22.629411 <6>[ 0.845033] kvm [1]: VHE mode initialized successfully
10492 09:27:22.636170 <5>[ 0.851524] Initialise system trusted keyrings
10493 09:27:22.642792 <6>[ 0.856360] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10494 09:27:22.650548 <6>[ 0.866322] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10495 09:27:22.656604 <5>[ 0.872730] NFS: Registering the id_resolver key type
10496 09:27:22.660369 <5>[ 0.878033] Key type id_resolver registered
10497 09:27:22.667155 <5>[ 0.882446] Key type id_legacy registered
10498 09:27:22.673216 <6>[ 0.886724] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10499 09:27:22.680076 <6>[ 0.893646] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10500 09:27:22.686728 <6>[ 0.901362] 9p: Installing v9fs 9p2000 file system support
10501 09:27:22.722197 <5>[ 0.938411] Key type asymmetric registered
10502 09:27:22.725583 <5>[ 0.942744] Asymmetric key parser 'x509' registered
10503 09:27:22.735688 <6>[ 0.947889] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10504 09:27:22.738803 <6>[ 0.955501] io scheduler mq-deadline registered
10505 09:27:22.742297 <6>[ 0.960278] io scheduler kyber registered
10506 09:27:22.761253 <6>[ 0.977304] EINJ: ACPI disabled.
10507 09:27:22.794306 <4>[ 1.003378] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10508 09:27:22.803636 <4>[ 1.013997] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10509 09:27:22.818755 <6>[ 1.035139] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10510 09:27:22.827012 <6>[ 1.043183] printk: console [ttyS0] disabled
10511 09:27:22.855057 <6>[ 1.067805] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10512 09:27:22.861870 <6>[ 1.077279] printk: console [ttyS0] enabled
10513 09:27:22.864795 <6>[ 1.077279] printk: console [ttyS0] enabled
10514 09:27:22.871553 <6>[ 1.086173] printk: bootconsole [mtk8250] disabled
10515 09:27:22.874629 <6>[ 1.086173] printk: bootconsole [mtk8250] disabled
10516 09:27:22.881173 <6>[ 1.097469] SuperH (H)SCI(F) driver initialized
10517 09:27:22.884729 <6>[ 1.102771] msm_serial: driver initialized
10518 09:27:22.898979 <6>[ 1.111777] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10519 09:27:22.908593 <6>[ 1.120332] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10520 09:27:22.915372 <6>[ 1.128874] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10521 09:27:22.925091 <6>[ 1.137504] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10522 09:27:22.935276 <6>[ 1.146216] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10523 09:27:22.941987 <6>[ 1.154936] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10524 09:27:22.952073 <6>[ 1.163478] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10525 09:27:22.958572 <6>[ 1.172282] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10526 09:27:22.968412 <6>[ 1.180824] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10527 09:27:22.980248 <6>[ 1.196269] loop: module loaded
10528 09:27:22.986802 <6>[ 1.202301] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10529 09:27:23.009631 <4>[ 1.225482] mtk-pmic-keys: Failed to locate of_node [id: -1]
10530 09:27:23.016080 <6>[ 1.232161] megasas: 07.719.03.00-rc1
10531 09:27:23.025778 <6>[ 1.241877] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10532 09:27:23.038033 <6>[ 1.254045] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10533 09:27:23.054942 <6>[ 1.270777] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10534 09:27:23.111294 <6>[ 1.320713] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10535 09:27:23.359797 <6>[ 1.575776] Freeing initrd memory: 18292K
10536 09:27:23.371185 <6>[ 1.587514] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10537 09:27:23.382608 <6>[ 1.598517] tun: Universal TUN/TAP device driver, 1.6
10538 09:27:23.385622 <6>[ 1.604596] thunder_xcv, ver 1.0
10539 09:27:23.388838 <6>[ 1.608102] thunder_bgx, ver 1.0
10540 09:27:23.392189 <6>[ 1.611596] nicpf, ver 1.0
10541 09:27:23.403010 <6>[ 1.615639] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10542 09:27:23.406086 <6>[ 1.623114] hns3: Copyright (c) 2017 Huawei Corporation.
10543 09:27:23.412911 <6>[ 1.628702] hclge is initializing
10544 09:27:23.415895 <6>[ 1.632283] e1000: Intel(R) PRO/1000 Network Driver
10545 09:27:23.423029 <6>[ 1.637412] e1000: Copyright (c) 1999-2006 Intel Corporation.
10546 09:27:23.425956 <6>[ 1.643429] e1000e: Intel(R) PRO/1000 Network Driver
10547 09:27:23.432903 <6>[ 1.648644] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10548 09:27:23.439380 <6>[ 1.654832] igb: Intel(R) Gigabit Ethernet Network Driver
10549 09:27:23.446182 <6>[ 1.660481] igb: Copyright (c) 2007-2014 Intel Corporation.
10550 09:27:23.452325 <6>[ 1.666317] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10551 09:27:23.459010 <6>[ 1.672835] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10552 09:27:23.462111 <6>[ 1.679296] sky2: driver version 1.30
10553 09:27:23.468859 <6>[ 1.684230] usbcore: registered new device driver r8152-cfgselector
10554 09:27:23.475314 <6>[ 1.690764] usbcore: registered new interface driver r8152
10555 09:27:23.482270 <6>[ 1.696581] VFIO - User Level meta-driver version: 0.3
10556 09:27:23.488524 <6>[ 1.704836] usbcore: registered new interface driver usb-storage
10557 09:27:23.495518 <6>[ 1.711277] usbcore: registered new device driver onboard-usb-hub
10558 09:27:23.504414 <6>[ 1.720456] mt6397-rtc mt6359-rtc: registered as rtc0
10559 09:27:23.514142 <6>[ 1.725925] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-18T09:27:23 UTC (1718702843)
10560 09:27:23.517558 <6>[ 1.735491] i2c_dev: i2c /dev entries driver
10561 09:27:23.531488 <4>[ 1.747474] cpu cpu0: supply cpu not found, using dummy regulator
10562 09:27:23.538053 <4>[ 1.753904] cpu cpu1: supply cpu not found, using dummy regulator
10563 09:27:23.544283 <4>[ 1.760313] cpu cpu2: supply cpu not found, using dummy regulator
10564 09:27:23.550886 <4>[ 1.766714] cpu cpu3: supply cpu not found, using dummy regulator
10565 09:27:23.557551 <4>[ 1.773129] cpu cpu4: supply cpu not found, using dummy regulator
10566 09:27:23.564372 <4>[ 1.779528] cpu cpu5: supply cpu not found, using dummy regulator
10567 09:27:23.571129 <4>[ 1.785924] cpu cpu6: supply cpu not found, using dummy regulator
10568 09:27:23.577796 <4>[ 1.792320] cpu cpu7: supply cpu not found, using dummy regulator
10569 09:27:23.597034 <6>[ 1.812964] cpu cpu0: EM: created perf domain
10570 09:27:23.600501 <6>[ 1.817891] cpu cpu4: EM: created perf domain
10571 09:27:23.607787 <6>[ 1.823494] sdhci: Secure Digital Host Controller Interface driver
10572 09:27:23.613791 <6>[ 1.829925] sdhci: Copyright(c) Pierre Ossman
10573 09:27:23.620623 <6>[ 1.834884] Synopsys Designware Multimedia Card Interface Driver
10574 09:27:23.627227 <6>[ 1.841517] sdhci-pltfm: SDHCI platform and OF driver helper
10575 09:27:23.630333 <6>[ 1.841555] mmc0: CQHCI version 5.10
10576 09:27:23.636828 <6>[ 1.851854] ledtrig-cpu: registered to indicate activity on CPUs
10577 09:27:23.643996 <6>[ 1.858868] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10578 09:27:23.650072 <6>[ 1.865933] usbcore: registered new interface driver usbhid
10579 09:27:23.653507 <6>[ 1.871764] usbhid: USB HID core driver
10580 09:27:23.660553 <6>[ 1.875950] spi_master spi0: will run message pump with realtime priority
10581 09:27:23.704628 <6>[ 1.914144] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10582 09:27:23.723288 <6>[ 1.929615] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10583 09:27:23.726539 <6>[ 1.939798] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10584 09:27:23.735551 <6>[ 1.951270] cros-ec-spi spi0.0: Chrome EC device registered
10585 09:27:23.741902 <6>[ 1.957296] mmc0: Command Queue Engine enabled
10586 09:27:23.748469 <6>[ 1.962047] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10587 09:27:23.752192 <6>[ 1.969610] mmcblk0: mmc0:0001 DA4128 116 GiB
10588 09:27:23.762407 <6>[ 1.978813] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10589 09:27:23.769953 <6>[ 1.985739] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10590 09:27:23.779842 <6>[ 1.990331] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10591 09:27:23.782840 <6>[ 1.991845] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10592 09:27:23.789588 <6>[ 2.001600] NET: Registered PF_PACKET protocol family
10593 09:27:23.796361 <6>[ 2.006250] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10594 09:27:23.799354 <6>[ 2.010991] 9pnet: Installing 9P2000 support
10595 09:27:23.806139 <5>[ 2.021979] Key type dns_resolver registered
10596 09:27:23.809101 <6>[ 2.026993] registered taskstats version 1
10597 09:27:23.816260 <5>[ 2.031379] Loading compiled-in X.509 certificates
10598 09:27:23.846624 <4>[ 2.055874] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10599 09:27:23.856034 <4>[ 2.066833] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10600 09:27:23.870224 <6>[ 2.086607] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10601 09:27:23.877157 <6>[ 2.093530] xhci-mtk 11200000.usb: xHCI Host Controller
10602 09:27:23.884172 <6>[ 2.099053] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10603 09:27:23.893904 <6>[ 2.106910] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10604 09:27:23.900820 <6>[ 2.116340] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10605 09:27:23.907289 <6>[ 2.122522] xhci-mtk 11200000.usb: xHCI Host Controller
10606 09:27:23.913896 <6>[ 2.128013] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10607 09:27:23.920458 <6>[ 2.135663] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10608 09:27:23.927275 <6>[ 2.143474] hub 1-0:1.0: USB hub found
10609 09:27:23.930978 <6>[ 2.147498] hub 1-0:1.0: 1 port detected
10610 09:27:23.937095 <6>[ 2.151774] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10611 09:27:23.944375 <6>[ 2.160499] hub 2-0:1.0: USB hub found
10612 09:27:23.947410 <6>[ 2.164520] hub 2-0:1.0: 1 port detected
10613 09:27:23.954430 <6>[ 2.170769] mtk-msdc 11f70000.mmc: Got CD GPIO
10614 09:27:23.969963 <6>[ 2.182462] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10615 09:27:23.979760 <6>[ 2.190846] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10616 09:27:23.986166 <6>[ 2.199186] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10617 09:27:23.995947 <6>[ 2.207524] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10618 09:27:24.002562 <6>[ 2.215861] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10619 09:27:24.012680 <6>[ 2.224199] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10620 09:27:24.019318 <6>[ 2.232536] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10621 09:27:24.028956 <6>[ 2.240873] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10622 09:27:24.035694 <6>[ 2.249211] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10623 09:27:24.045684 <6>[ 2.257549] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10624 09:27:24.052100 <6>[ 2.265887] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10625 09:27:24.061990 <6>[ 2.274230] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10626 09:27:24.068515 <6>[ 2.282567] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10627 09:27:24.078932 <6>[ 2.290905] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10628 09:27:24.085046 <6>[ 2.299242] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10629 09:27:24.091742 <6>[ 2.307945] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10630 09:27:24.099171 <6>[ 2.315133] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10631 09:27:24.105925 <6>[ 2.321916] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10632 09:27:24.115751 <6>[ 2.328684] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10633 09:27:24.122193 <6>[ 2.335613] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10634 09:27:24.128983 <6>[ 2.342457] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10635 09:27:24.138848 <6>[ 2.351588] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10636 09:27:24.148617 <6>[ 2.360707] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10637 09:27:24.158305 <6>[ 2.370000] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10638 09:27:24.168223 <6>[ 2.379467] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10639 09:27:24.178553 <6>[ 2.388936] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10640 09:27:24.185072 <6>[ 2.398055] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10641 09:27:24.194887 <6>[ 2.407522] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10642 09:27:24.204877 <6>[ 2.416647] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10643 09:27:24.214605 <6>[ 2.425952] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10644 09:27:24.224397 <6>[ 2.436113] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10645 09:27:24.235049 <6>[ 2.447835] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10646 09:27:24.242701 <6>[ 2.459005] Trying to probe devices needed for running init ...
10647 09:27:24.253088 <3>[ 2.466223] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10648 09:27:24.361862 <6>[ 2.574982] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10649 09:27:24.516051 <6>[ 2.732160] hub 1-1:1.0: USB hub found
10650 09:27:24.519252 <6>[ 2.736615] hub 1-1:1.0: 4 ports detected
10651 09:27:24.529392 <6>[ 2.745823] hub 1-1:1.0: USB hub found
10652 09:27:24.533110 <6>[ 2.750078] hub 1-1:1.0: 4 ports detected
10653 09:27:24.642356 <6>[ 2.855294] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10654 09:27:24.670022 <6>[ 2.886037] hub 2-1:1.0: USB hub found
10655 09:27:24.672943 <6>[ 2.890597] hub 2-1:1.0: 3 ports detected
10656 09:27:24.685421 <6>[ 2.901670] hub 2-1:1.0: USB hub found
10657 09:27:24.688453 <6>[ 2.906078] hub 2-1:1.0: 3 ports detected
10658 09:27:24.853727 <6>[ 3.066988] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10659 09:27:24.986592 <6>[ 3.202874] hub 1-1.4:1.0: USB hub found
10660 09:27:24.990087 <6>[ 3.207539] hub 1-1.4:1.0: 2 ports detected
10661 09:27:25.002538 <6>[ 3.219076] hub 1-1.4:1.0: USB hub found
10662 09:27:25.005930 <6>[ 3.223645] hub 1-1.4:1.0: 2 ports detected
10663 09:27:25.065838 <6>[ 3.279178] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10664 09:27:25.174493 <6>[ 3.387621] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10665 09:27:25.210776 <4>[ 3.423991] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10666 09:27:25.220566 <4>[ 3.433114] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10667 09:27:25.256296 <6>[ 3.472558] r8152 2-1.3:1.0 eth0: v1.12.13
10668 09:27:25.301505 <6>[ 3.514779] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10669 09:27:25.498094 <6>[ 3.710986] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10670 09:27:26.857140 <6>[ 5.073815] r8152 2-1.3:1.0 eth0: carrier on
10671 09:27:29.518494 <5>[ 5.102764] Sending DHCP requests .., OK
10672 09:27:29.525318 <6>[ 7.739050] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10673 09:27:29.528320 <6>[ 7.747344] IP-Config: Complete:
10674 09:27:29.541363 <6>[ 7.750839] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10675 09:27:29.547845 <6>[ 7.761544] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10676 09:27:29.554539 <6>[ 7.770161] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10677 09:27:29.561503 <6>[ 7.770170] nameserver0=192.168.201.1
10678 09:27:29.564525 <6>[ 7.782313] clk: Disabling unused clocks
10679 09:27:29.568185 <6>[ 7.787828] ALSA device list:
10680 09:27:29.574806 <6>[ 7.791078] No soundcards found.
10681 09:27:29.582460 <6>[ 7.798940] Freeing unused kernel memory: 8512K
10682 09:27:29.585747 <6>[ 7.803898] Run /init as init process
10683 09:27:29.596015 Loading, please wait...
10684 09:27:29.621917 Starting systemd-udevd version 252.22-1~deb12u1
10685 09:27:29.904795 <6>[ 8.118521] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10686 09:27:29.914885 <6>[ 8.127563] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10687 09:27:29.927906 <6>[ 8.141552] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10688 09:27:29.939388 <6>[ 8.156118] remoteproc remoteproc0: scp is available
10689 09:27:29.949474 <6>[ 8.157074] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10690 09:27:29.953023 <6>[ 8.161705] remoteproc remoteproc0: powering up scp
10691 09:27:29.962599 <6>[ 8.163645] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10692 09:27:29.969504 <6>[ 8.167277] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10693 09:27:29.979629 <6>[ 8.167283] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10694 09:27:29.986479 <4>[ 8.167374] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10695 09:27:29.996474 <6>[ 8.167874] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10696 09:27:30.002243 <6>[ 8.167876] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10697 09:27:30.012355 <6>[ 8.168082] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10698 09:27:30.018660 <6>[ 8.168099] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10699 09:27:30.025294 <6>[ 8.168105] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10700 09:27:30.035497 <6>[ 8.168110] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10701 09:27:30.045274 <3>[ 8.179621] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 09:27:30.051998 <6>[ 8.183487] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10703 09:27:30.058723 <6>[ 8.183530] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10704 09:27:30.065471 <4>[ 8.216765] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10705 09:27:30.075160 <3>[ 8.224554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 09:27:30.081764 <4>[ 8.233125] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10707 09:27:30.085295 <6>[ 8.237773] mc: Linux media interface: v0.10
10708 09:27:30.092601 <3>[ 8.241900] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 09:27:30.102572 <6>[ 8.251998] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10710 09:27:30.109577 <3>[ 8.258448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 09:27:30.119382 <4>[ 8.281498] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10712 09:27:30.123496 <4>[ 8.281498] Fallback method does not support PEC.
10713 09:27:30.132848 <3>[ 8.287708] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 09:27:30.139189 <6>[ 8.299983] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10715 09:27:30.146276 <3>[ 8.303004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 09:27:30.152715 <6>[ 8.307495] pci_bus 0000:00: root bus resource [bus 00-ff]
10717 09:27:30.159385 <6>[ 8.308742] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10718 09:27:30.166165 <6>[ 8.308778] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10719 09:27:30.172844 <6>[ 8.308785] remoteproc remoteproc0: remote processor scp is now up
10720 09:27:30.182667 <3>[ 8.312509] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10721 09:27:30.192036 <3>[ 8.315573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 09:27:30.198729 <3>[ 8.315579] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 09:27:30.205444 <3>[ 8.315631] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 09:27:30.215657 <3>[ 8.315669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 09:27:30.222307 <6>[ 8.323564] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10726 09:27:30.232012 <6>[ 8.324686] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10727 09:27:30.238841 <6>[ 8.326952] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10728 09:27:30.244954 <3>[ 8.331360] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 09:27:30.255175 <3>[ 8.336127] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10730 09:27:30.264875 <6>[ 8.344991] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10731 09:27:30.274597 <3>[ 8.353071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 09:27:30.284754 <6>[ 8.359625] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10733 09:27:30.291013 <6>[ 8.359959] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10734 09:27:30.298024 <6>[ 8.360071] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10735 09:27:30.307815 <6>[ 8.362749] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10736 09:27:30.317553 <3>[ 8.368065] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 09:27:30.324168 <6>[ 8.373764] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10738 09:27:30.330846 <6>[ 8.374567] videodev: Linux video capture interface: v2.00
10739 09:27:30.337606 <3>[ 8.380785] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 09:27:30.341046 <6>[ 8.389372] pci 0000:00:00.0: supports D1 D2
10741 09:27:30.350552 <3>[ 8.395734] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 09:27:30.357535 <6>[ 8.404515] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10743 09:27:30.363757 <3>[ 8.412598] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 09:27:30.367125 <6>[ 8.413068] Bluetooth: Core ver 2.22
10745 09:27:30.373705 <6>[ 8.413126] NET: Registered PF_BLUETOOTH protocol family
10746 09:27:30.380309 <6>[ 8.413127] Bluetooth: HCI device and connection manager initialized
10747 09:27:30.387012 <6>[ 8.413141] Bluetooth: HCI socket layer initialized
10748 09:27:30.390534 <6>[ 8.413145] Bluetooth: L2CAP socket layer initialized
10749 09:27:30.396658 <6>[ 8.413152] Bluetooth: SCO socket layer initialized
10750 09:27:30.403826 <6>[ 8.422041] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10751 09:27:30.413849 <3>[ 8.428749] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 09:27:30.420036 <6>[ 8.436959] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10753 09:27:30.426747 <3>[ 8.444002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 09:27:30.433503 <6>[ 8.452250] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10755 09:27:30.443256 <6>[ 8.453278] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10756 09:27:30.453311 <6>[ 8.454497] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10757 09:27:30.459759 <6>[ 8.454683] usbcore: registered new interface driver uvcvideo
10758 09:27:30.466452 <6>[ 8.477756] usbcore: registered new interface driver btusb
10759 09:27:30.476364 <4>[ 8.478333] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10760 09:27:30.482935 <3>[ 8.478347] Bluetooth: hci0: Failed to load firmware file (-2)
10761 09:27:30.489138 <3>[ 8.478352] Bluetooth: hci0: Failed to set up firmware (-2)
10762 09:27:30.498953 <4>[ 8.478358] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10763 09:27:30.505692 <6>[ 8.487239] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10764 09:27:30.512292 <6>[ 8.505902] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10765 09:27:30.519047 <6>[ 8.511657] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10766 09:27:30.526051 <6>[ 8.742037] pci 0000:01:00.0: supports D1 D2
10767 09:27:30.532092 <6>[ 8.746560] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10768 09:27:30.553674 <6>[ 8.766883] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10769 09:27:30.559949 <6>[ 8.773804] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10770 09:27:30.566436 <6>[ 8.781882] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10771 09:27:30.576390 <6>[ 8.789879] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10772 09:27:30.583039 <6>[ 8.797879] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10773 09:27:30.593255 <6>[ 8.805880] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10774 09:27:30.596035 <6>[ 8.813879] pci 0000:00:00.0: PCI bridge to [bus 01]
10775 09:27:30.606378 <6>[ 8.819095] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10776 09:27:30.612542 <6>[ 8.827206] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10777 09:27:30.619482 <6>[ 8.834026] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10778 09:27:30.626133 <6>[ 8.840805] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10779 09:27:30.640756 <5>[ 8.854322] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10780 09:27:30.663671 <5>[ 8.877433] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10781 09:27:30.670342 <5>[ 8.884986] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10782 09:27:30.680154 <4>[ 8.893443] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10783 09:27:30.686679 <6>[ 8.902330] cfg80211: failed to load regulatory.db
10784 09:27:30.733002 <6>[ 8.946474] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10785 09:27:30.739623 <6>[ 8.953982] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10786 09:27:30.763905 <6>[ 8.980617] mt7921e 0000:01:00.0: ASIC revision: 79610010
10787 09:27:30.865235 <6>[ 9.078647] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10788 09:27:30.868323 <6>[ 9.078647]
10789 09:27:30.879280 Begin: Loading essential drivers ... done.
10790 09:27:30.882392 Begin: Running /scripts/init-premount ... done.
10791 09:27:30.889158 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10792 09:27:30.898959 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10793 09:27:30.901952 Device /sys/class/net/eth0 found
10794 09:27:30.902035 done.
10795 09:27:30.908865 Begin: Waiting up to 180 secs for any network device to become available ... done.
10796 09:27:30.966105 IP-Config: eth0 hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10797 09:27:30.973673 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10798 09:27:30.980322 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10799 09:27:30.986416 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10800 09:27:30.993430 host : mt8192-asurada-spherion-r0-cbg-2
10801 09:27:30.999845 domain : lava-rack
10802 09:27:31.003332 rootserver: 192.168.201.1 rootpath:
10803 09:27:31.006241 filename :
10804 09:27:31.128011 done.
10805 09:27:31.134836 <6>[ 9.348843] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10806 09:27:31.141113 Begin: Running /scripts/nfs-bottom ... done.
10807 09:27:31.165541 Begin: Running /scripts/init-bottom ... done.
10808 09:27:32.521365 <6>[ 10.738533] NET: Registered PF_INET6 protocol family
10809 09:27:32.528314 <6>[ 10.745395] Segment Routing with IPv6
10810 09:27:32.531260 <6>[ 10.749390] In-situ OAM (IOAM) with IPv6
10811 09:27:32.702938 <30>[ 10.893770] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10812 09:27:32.709520 <30>[ 10.926948] systemd[1]: Detected architecture arm64.
10813 09:27:32.718004
10814 09:27:32.721364 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10815 09:27:32.721448
10816 09:27:32.743116 <30>[ 10.960375] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10817 09:27:33.835301 <30>[ 12.049502] systemd[1]: Queued start job for default target graphical.target.
10818 09:27:33.874485 <30>[ 12.087787] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10819 09:27:33.880442 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10820 09:27:33.901495 <30>[ 12.115465] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10821 09:27:33.908137 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10822 09:27:33.930792 <30>[ 12.144736] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10823 09:27:33.940213 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10824 09:27:33.958048 <30>[ 12.172279] systemd[1]: Created slice user.slice - User and Session Slice.
10825 09:27:33.964871 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10826 09:27:33.989020 <30>[ 12.199835] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10827 09:27:33.999082 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10828 09:27:34.016574 <30>[ 12.227197] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10829 09:27:34.023066 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10830 09:27:34.051368 <30>[ 12.255629] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10831 09:27:34.061717 <30>[ 12.275543] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10832 09:27:34.067718 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10833 09:27:34.085329 <30>[ 12.299350] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10834 09:27:34.095282 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10835 09:27:34.113235 <30>[ 12.327043] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10836 09:27:34.122992 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10837 09:27:34.138146 <30>[ 12.355507] systemd[1]: Reached target paths.target - Path Units.
10838 09:27:34.148102 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10839 09:27:34.165369 <30>[ 12.379433] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10840 09:27:34.172223 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10841 09:27:34.185483 <30>[ 12.402955] systemd[1]: Reached target slices.target - Slice Units.
10842 09:27:34.195793 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10843 09:27:34.210390 <30>[ 12.427437] systemd[1]: Reached target swap.target - Swaps.
10844 09:27:34.216776 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10845 09:27:34.236978 <30>[ 12.451068] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10846 09:27:34.246656 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10847 09:27:34.265368 <30>[ 12.479441] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10848 09:27:34.275436 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10849 09:27:34.297428 <30>[ 12.510934] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10850 09:27:34.307278 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10851 09:27:34.326837 <30>[ 12.540654] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10852 09:27:34.336864 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10853 09:27:34.354043 <30>[ 12.567598] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10854 09:27:34.360420 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10855 09:27:34.378971 <30>[ 12.592584] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10856 09:27:34.390950 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10857 09:27:34.407940 <30>[ 12.621967] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10858 09:27:34.417597 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10859 09:27:34.433380 <30>[ 12.647439] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10860 09:27:34.443110 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10861 09:27:34.493400 <30>[ 12.707473] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10862 09:27:34.500119 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10863 09:27:34.519075 <30>[ 12.733382] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10864 09:27:34.526111 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10865 09:27:34.548350 <30>[ 12.762258] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10866 09:27:34.554474 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10867 09:27:34.579874 <30>[ 12.787317] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10868 09:27:34.595254 <30>[ 12.809633] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10869 09:27:34.605100 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10870 09:27:34.626562 <30>[ 12.840909] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10871 09:27:34.633216 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10872 09:27:34.659532 <30>[ 12.873147] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10873 09:27:34.665972 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10874 09:27:34.691653 <30>[ 12.905666] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10875 09:27:34.697971 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10876 09:27:34.721579 <30>[ 12.935513] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10877 09:27:34.731759 <6>[ 12.937124] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10878 09:27:34.737773 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10879 09:27:34.762971 <30>[ 12.977093] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10880 09:27:34.769558 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10881 09:27:34.795814 <30>[ 13.009665] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10882 09:27:34.801954 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10883 09:27:34.818624 <6>[ 13.036199] fuse: init (API version 7.37)
10884 09:27:34.857824 <30>[ 13.072008] systemd[1]: Starting systemd-journald.service - Journal Service...
10885 09:27:34.864611 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10886 09:27:34.899178 <30>[ 13.113380] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10887 09:27:34.905663 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10888 09:27:34.933504 <30>[ 13.144405] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10889 09:27:34.940117 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10890 09:27:34.965573 <30>[ 13.179727] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10891 09:27:34.975251 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10892 09:27:35.037786 <30>[ 13.251831] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10893 09:27:35.047524 <3>[ 13.253898] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 09:27:35.054185 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10895 09:27:35.076574 <3>[ 13.290644] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 09:27:35.083226 <30>[ 13.291661] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10897 09:27:35.093189 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10898 09:27:35.110210 <30>[ 13.323748] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10899 09:27:35.123955 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.<3>[ 13.335917] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 09:27:35.127422 mount[…- POSIX Message Queue File System.
10901 09:27:35.146163 <30>[ 13.359148] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10902 09:27:35.152831 <3>[ 13.365183] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 09:27:35.162640 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10904 09:27:35.181753 <30>[ 13.395470] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10905 09:27:35.191799 <3>[ 13.396248] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 09:27:35.198098 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10907 09:27:35.219262 <30>[ 13.432810] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10908 09:27:35.225404 <3>[ 13.435244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 09:27:35.235261 <30>[ 13.441042] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10910 09:27:35.242051 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10911 09:27:35.256683 <3>[ 13.470513] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 09:27:35.266060 <30>[ 13.480254] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10913 09:27:35.273472 <30>[ 13.487953] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10914 09:27:35.286610 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m <3>[ 13.500823] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 09:27:35.289698 - Load Kernel Module dm_mod.
10916 09:27:35.306672 <30>[ 13.524041] systemd[1]: modprobe@drm.service: Deactivated successfully.
10917 09:27:35.317386 <3>[ 13.531464] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 09:27:35.324111 <30>[ 13.531717] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10919 09:27:35.334021 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10920 09:27:35.347290 <3>[ 13.561400] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 09:27:35.357555 <30>[ 13.571846] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10922 09:27:35.368566 <30>[ 13.580166] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10923 09:27:35.378564 [[0;32m OK [0m] Finished [0<3>[ 13.591044] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 09:27:35.385014 ;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10925 09:27:35.402474 <30>[ 13.615788] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10926 09:27:35.408679 <30>[ 13.623591] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10927 09:27:35.418792 <3>[ 13.625362] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 09:27:35.425661 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10929 09:27:35.446035 <30>[ 13.660226] systemd[1]: modprobe@loop.service: Deactivated successfully.
10930 09:27:35.452932 <30>[ 13.668357] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10931 09:27:35.463491 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10932 09:27:35.481728 <30>[ 13.695789] systemd[1]: Started systemd-journald.service - Journal Service.
10933 09:27:35.488324 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10934 09:27:35.507328 <4>[ 13.714878] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10935 09:27:35.517272 <3>[ 13.730557] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10936 09:27:35.523827 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10937 09:27:35.544030 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10938 09:27:35.562380 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10939 09:27:35.582065 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10940 09:27:35.604093 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10941 09:27:35.657574 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10942 09:27:35.683277 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10943 09:27:35.708072 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10944 09:27:35.734663 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10945 09:27:35.775143 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10946 09:27:35.781456 <46>[ 13.996097] systemd-journald[307]: Received client request to flush runtime journal.
10947 09:27:35.801485 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10948 09:27:35.836856 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10949 09:27:35.857932 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10950 09:27:35.879128 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10951 09:27:36.561176 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10952 09:27:36.894136 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10953 09:27:36.949969 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10954 09:27:37.197227 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10955 09:27:37.307093 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10956 09:27:37.325618 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10957 09:27:37.344686 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10958 09:27:37.384792 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10959 09:27:37.407455 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10960 09:27:37.624241 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10961 09:27:37.690757 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10962 09:27:37.773812 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10963 09:27:38.041846 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10964 09:27:38.061206 <6>[ 16.279085] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10965 09:27:38.095617 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10966 09:27:38.209405 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10967 09:27:38.228687 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10968 09:27:38.245986 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10969 09:27:38.297148 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10970 09:27:38.334762 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10971 09:27:38.364245 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10972 09:27:38.382678 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10973 09:27:38.404615 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10974 09:27:38.421572 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10975 09:27:38.466208 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10976 09:27:38.486491 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10977 09:27:38.551388 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10978 09:27:38.572787 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10979 09:27:38.589108 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10980 09:27:38.604489 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10981 09:27:38.629330 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10982 09:27:38.651766 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10983 09:27:38.668919 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10984 09:27:38.697209 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10985 09:27:38.715670 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10986 09:27:38.732641 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10987 09:27:38.750558 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10988 09:27:38.768876 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10989 09:27:38.784895 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10990 09:27:38.822131 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10991 09:27:38.855849 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10992 09:27:38.937808 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10993 09:27:38.968871 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10994 09:27:39.041854 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10995 09:27:39.102467 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10996 09:27:39.129051 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10997 09:27:39.148670 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10998 09:27:39.166340 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10999 09:27:39.282037 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11000 09:27:39.303296 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11001 09:27:39.322564 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11002 09:27:39.341573 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11003 09:27:39.387266 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11004 09:27:39.441120 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11005 09:27:39.536742
11006 09:27:39.539900 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11007 09:27:39.540000
11008 09:27:39.542930 debian-bookworm-arm64 login: root (automatic login)
11009 09:27:39.543028
11010 09:27:39.872767 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
11011 09:27:39.872916
11012 09:27:39.879337 The programs included with the Debian GNU/Linux system are free software;
11013 09:27:39.885845 the exact distribution terms for each program are described in the
11014 09:27:39.889362 individual files in /usr/share/doc/*/copyright.
11015 09:27:39.889455
11016 09:27:39.895886 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11017 09:27:39.899549 permitted by applicable law.
11018 09:27:41.044056 Matched prompt #10: / #
11020 09:27:41.044350 Setting prompt string to ['/ #']
11021 09:27:41.044448 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11023 09:27:41.044657 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11024 09:27:41.044747 start: 2.2.6 expect-shell-connection (timeout 00:03:22) [common]
11025 09:27:41.044817 Setting prompt string to ['/ #']
11026 09:27:41.044878 Forcing a shell prompt, looking for ['/ #']
11028 09:27:41.095110 / #
11029 09:27:41.095286 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11030 09:27:41.095376 Waiting using forced prompt support (timeout 00:02:30)
11031 09:27:41.100308
11032 09:27:41.100626 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11033 09:27:41.100730 start: 2.2.7 export-device-env (timeout 00:03:22) [common]
11035 09:27:41.201109 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407630/extract-nfsrootfs-mb0x_k8b'
11036 09:27:41.205944 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407630/extract-nfsrootfs-mb0x_k8b'
11038 09:27:41.306551 / # export NFS_SERVER_IP='192.168.201.1'
11039 09:27:41.311779 export NFS_SERVER_IP='192.168.201.1'
11040 09:27:41.312071 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11041 09:27:41.312171 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
11042 09:27:41.312260 end: 2 depthcharge-action (duration 00:01:38) [common]
11043 09:27:41.312351 start: 3 lava-test-retry (timeout 00:06:55) [common]
11044 09:27:41.312440 start: 3.1 lava-test-shell (timeout 00:06:55) [common]
11045 09:27:41.312514 Using namespace: common
11047 09:27:41.412843 / # #
11048 09:27:41.413018 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11049 09:27:41.417682 #
11050 09:27:41.417951 Using /lava-14407630
11052 09:27:41.518285 / # export SHELL=/bin/bash
11053 09:27:41.523943 export SHELL=/bin/bash
11055 09:27:41.624488 / # . /lava-14407630/environment
11056 09:27:41.629933 . /lava-14407630/environment
11058 09:27:41.736269 / # /lava-14407630/bin/lava-test-runner /lava-14407630/0
11059 09:27:41.736451 Test shell timeout: 10s (minimum of the action and connection timeout)
11060 09:27:41.741704 /lava-14407630/bin/lava-test-runner /lava-14407630/0
11061 09:27:41.997833 + export TESTRUN_ID=0_timesync-off
11062 09:27:42.001187 + TESTRUN_ID=0_timesync-off
11063 09:27:42.004295 + cd /lava-14407630/0/tests/0_timesync-off
11064 09:27:42.007376 ++ cat uuid
11065 09:27:42.012040 + UUID=14407630_1.6.2.3.1
11066 09:27:42.012126 + set +x
11067 09:27:42.018556 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14407630_1.6.2.3.1>
11068 09:27:42.018888 Received signal: <STARTRUN> 0_timesync-off 14407630_1.6.2.3.1
11069 09:27:42.018963 Starting test lava.0_timesync-off (14407630_1.6.2.3.1)
11070 09:27:42.019066 Skipping test definition patterns.
11071 09:27:42.022054 + systemctl stop systemd-timesyncd
11072 09:27:42.086347 + set +x
11073 09:27:42.089156 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14407630_1.6.2.3.1>
11074 09:27:42.089489 Received signal: <ENDRUN> 0_timesync-off 14407630_1.6.2.3.1
11075 09:27:42.089576 Ending use of test pattern.
11076 09:27:42.089638 Ending test lava.0_timesync-off (14407630_1.6.2.3.1), duration 0.07
11078 09:27:42.179189 + export TESTRUN_ID=1_kselftest-alsa
11079 09:27:42.182336 + TESTRUN_ID=1_kselftest-alsa
11080 09:27:42.189219 + cd /lava-14407630/0/tests/1_kselftest-alsa
11081 09:27:42.189329 ++ cat uuid
11082 09:27:42.195601 + UUID=14407630_1.6.2.3.5
11083 09:27:42.195690 + set +x
11084 09:27:42.202478 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14407630_1.6.2.3.5>
11085 09:27:42.202750 Received signal: <STARTRUN> 1_kselftest-alsa 14407630_1.6.2.3.5
11086 09:27:42.202832 Starting test lava.1_kselftest-alsa (14407630_1.6.2.3.5)
11087 09:27:42.202918 Skipping test definition patterns.
11088 09:27:42.205661 + cd ./automated/linux/kselftest/
11089 09:27:42.231604 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11090 09:27:42.284466 INFO: install_deps skipped
11091 09:27:42.805627 --2024-06-18 09:27:42-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11092 09:27:42.822908 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11093 09:27:42.953316 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11094 09:27:43.082013 HTTP request sent, awaiting response... 200 OK
11095 09:27:43.085653 Length: 1642672 (1.6M) [application/octet-stream]
11096 09:27:43.088795 Saving to: 'kselftest_armhf.tar.gz'
11097 09:27:43.088886
11098 09:27:43.088952
11099 09:27:43.338463 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11100 09:27:43.604602 kselftest_armhf.tar 2%[ ] 47.81K 187KB/s
11101 09:27:43.851955 kselftest_armhf.tar 9%[> ] 153.86K 295KB/s
11102 09:27:44.108184 kselftest_armhf.tar 26%[====> ] 422.53K 549KB/s
11103 09:27:44.364990 kselftest_armhf.tar 41%[=======> ] 661.51K 645KB/s
11104 09:27:44.622090 kselftest_armhf.tar 57%[==========> ] 921.70K 719KB/s
11105 09:27:44.879387 kselftest_armhf.tar 74%[=============> ] 1.17M 775KB/s
11106 09:27:44.894987 kselftest_armhf.tar 92%[=================> ] 1.44M 821KB/s
11107 09:27:44.901740 kselftest_armhf.tar 100%[===================>] 1.57M 885KB/s in 1.8s
11108 09:27:44.901894
11109 09:27:45.047205 2024-06-18 09:27:44 (885 KB/s) - 'kselftest_armhf.tar.gz' saved [1642672/1642672]
11110 09:27:45.047338
11111 09:27:49.538302 skiplist:
11112 09:27:49.541073 ========================================
11113 09:27:49.544333 ========================================
11114 09:27:49.595364 alsa:mixer-test
11115 09:27:49.616984 ============== Tests to run ===============
11116 09:27:49.617183 alsa:mixer-test
11117 09:27:49.623286 ===========End Tests to run ===============
11118 09:27:49.626648 shardfile-alsa pass
11119 09:27:49.734125 <12>[ 27.953392] kselftest: Running tests in alsa
11120 09:27:49.743234 TAP version 13
11121 09:27:49.757357 1..1
11122 09:27:49.772837 # selftests: alsa: mixer-test
11123 09:27:50.283177 # TAP version 13
11124 09:27:50.283363 # 1..0
11125 09:27:50.290395 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11126 09:27:50.293442 ok 1 selftests: alsa: mixer-test
11127 09:27:51.719658 alsa_mixer-test pass
11128 09:27:51.797006 + ../../utils/send-to-lava.sh ./output/result.txt
11129 09:27:51.872862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11130 09:27:51.873223 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11132 09:27:51.928008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11133 09:27:51.928182 + set +x
11134 09:27:51.928457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11136 09:27:51.934656 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14407630_1.6.2.3.5>
11137 09:27:51.934922 Received signal: <ENDRUN> 1_kselftest-alsa 14407630_1.6.2.3.5
11138 09:27:51.934998 Ending use of test pattern.
11139 09:27:51.935060 Ending test lava.1_kselftest-alsa (14407630_1.6.2.3.5), duration 9.73
11141 09:27:51.937936 <LAVA_TEST_RUNNER EXIT>
11142 09:27:51.938189 ok: lava_test_shell seems to have completed
11143 09:27:51.938291 alsa_mixer-test: pass
shardfile-alsa: pass
11144 09:27:51.938380 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11145 09:27:51.938470 end: 3 lava-test-retry (duration 00:00:11) [common]
11146 09:27:51.938561 start: 4 finalize (timeout 00:06:44) [common]
11147 09:27:51.938651 start: 4.1 power-off (timeout 00:00:30) [common]
11148 09:27:51.938801 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11149 09:27:52.138194 >> Command sent successfully.
11150 09:27:52.140611 Returned 0 in 0 seconds
11151 09:27:52.241031 end: 4.1 power-off (duration 00:00:00) [common]
11153 09:27:52.241447 start: 4.2 read-feedback (timeout 00:06:44) [common]
11154 09:27:52.241709 Listened to connection for namespace 'common' for up to 1s
11155 09:27:53.242683 Finalising connection for namespace 'common'
11156 09:27:53.242864 Disconnecting from shell: Finalise
11157 09:27:53.242951 / #
11158 09:27:53.343268 end: 4.2 read-feedback (duration 00:00:01) [common]
11159 09:27:53.343461 end: 4 finalize (duration 00:00:01) [common]
11160 09:27:53.343577 Cleaning after the job
11161 09:27:53.343683 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/ramdisk
11162 09:27:53.345690 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/kernel
11163 09:27:53.356848 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/dtb
11164 09:27:53.357110 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/nfsrootfs
11165 09:27:53.420133 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407630/tftp-deploy-pu_owxyt/modules
11166 09:27:53.425887 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407630
11167 09:27:53.995168 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407630
11168 09:27:53.995370 Job finished correctly