Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 21
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 09:24:59.184167 lava-dispatcher, installed at version: 2024.03
2 09:24:59.184397 start: 0 validate
3 09:24:59.184528 Start time: 2024-06-18 09:24:59.184520+00:00 (UTC)
4 09:24:59.184700 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:24:59.184826 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:24:59.435525 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:24:59.435762 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:25:20.708008 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:25:20.708241 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:25:20.967906 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:25:20.968151 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:25:21.488970 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:25:21.489144 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:25:23.500035 validate duration: 24.32
16 09:25:23.501223 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:25:23.501729 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:25:23.502172 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:25:23.502730 Not decompressing ramdisk as can be used compressed.
20 09:25:23.503168 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 09:25:23.503525 saving as /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/ramdisk/initrd.cpio.gz
22 09:25:23.503867 total size: 5628169 (5 MB)
23 09:25:23.771306 progress 0 % (0 MB)
24 09:25:23.781018 progress 5 % (0 MB)
25 09:25:23.791362 progress 10 % (0 MB)
26 09:25:23.799431 progress 15 % (0 MB)
27 09:25:23.805296 progress 20 % (1 MB)
28 09:25:23.809423 progress 25 % (1 MB)
29 09:25:23.813359 progress 30 % (1 MB)
30 09:25:23.816536 progress 35 % (1 MB)
31 09:25:23.819268 progress 40 % (2 MB)
32 09:25:23.821827 progress 45 % (2 MB)
33 09:25:23.824221 progress 50 % (2 MB)
34 09:25:23.826709 progress 55 % (2 MB)
35 09:25:23.828823 progress 60 % (3 MB)
36 09:25:23.830513 progress 65 % (3 MB)
37 09:25:23.832375 progress 70 % (3 MB)
38 09:25:23.833954 progress 75 % (4 MB)
39 09:25:23.835637 progress 80 % (4 MB)
40 09:25:23.837149 progress 85 % (4 MB)
41 09:25:23.838755 progress 90 % (4 MB)
42 09:25:23.840289 progress 95 % (5 MB)
43 09:25:23.841695 progress 100 % (5 MB)
44 09:25:23.841918 5 MB downloaded in 0.34 s (15.88 MB/s)
45 09:25:23.842077 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:25:23.842328 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:25:23.842417 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:25:23.842505 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:25:23.842640 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:25:23.842715 saving as /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/kernel/Image
52 09:25:23.842793 total size: 54813184 (52 MB)
53 09:25:23.842856 No compression specified
54 09:25:23.843938 progress 0 % (0 MB)
55 09:25:23.857573 progress 5 % (2 MB)
56 09:25:23.871295 progress 10 % (5 MB)
57 09:25:23.884768 progress 15 % (7 MB)
58 09:25:23.898409 progress 20 % (10 MB)
59 09:25:23.912016 progress 25 % (13 MB)
60 09:25:23.925813 progress 30 % (15 MB)
61 09:25:23.939548 progress 35 % (18 MB)
62 09:25:23.953225 progress 40 % (20 MB)
63 09:25:23.966746 progress 45 % (23 MB)
64 09:25:23.980293 progress 50 % (26 MB)
65 09:25:24.002955 progress 55 % (28 MB)
66 09:25:24.017062 progress 60 % (31 MB)
67 09:25:24.031593 progress 65 % (34 MB)
68 09:25:24.045700 progress 70 % (36 MB)
69 09:25:24.059736 progress 75 % (39 MB)
70 09:25:24.073769 progress 80 % (41 MB)
71 09:25:24.087574 progress 85 % (44 MB)
72 09:25:24.101625 progress 90 % (47 MB)
73 09:25:24.115851 progress 95 % (49 MB)
74 09:25:24.130495 progress 100 % (52 MB)
75 09:25:24.130754 52 MB downloaded in 0.29 s (181.53 MB/s)
76 09:25:24.130911 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:25:24.131151 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:25:24.131240 start: 1.3 download-retry (timeout 00:09:59) [common]
80 09:25:24.131326 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 09:25:24.131460 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:25:24.131530 saving as /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/dtb/mt8192-asurada-spherion-r0.dtb
83 09:25:24.131593 total size: 47258 (0 MB)
84 09:25:24.131657 No compression specified
85 09:25:24.132791 progress 69 % (0 MB)
86 09:25:24.133060 progress 100 % (0 MB)
87 09:25:24.133215 0 MB downloaded in 0.00 s (27.82 MB/s)
88 09:25:24.133338 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:25:24.133568 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:25:24.133654 start: 1.4 download-retry (timeout 00:09:59) [common]
92 09:25:24.133738 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 09:25:24.133848 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 09:25:24.133916 saving as /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/nfsrootfs/full.rootfs.tar
95 09:25:24.133977 total size: 120894716 (115 MB)
96 09:25:24.134040 Using unxz to decompress xz
97 09:25:24.137697 progress 0 % (0 MB)
98 09:25:24.484941 progress 5 % (5 MB)
99 09:25:24.842975 progress 10 % (11 MB)
100 09:25:25.195438 progress 15 % (17 MB)
101 09:25:25.522260 progress 20 % (23 MB)
102 09:25:25.814919 progress 25 % (28 MB)
103 09:25:26.175101 progress 30 % (34 MB)
104 09:25:26.515091 progress 35 % (40 MB)
105 09:25:26.681614 progress 40 % (46 MB)
106 09:25:26.860608 progress 45 % (51 MB)
107 09:25:27.179791 progress 50 % (57 MB)
108 09:25:27.557752 progress 55 % (63 MB)
109 09:25:27.901802 progress 60 % (69 MB)
110 09:25:28.248740 progress 65 % (74 MB)
111 09:25:28.594212 progress 70 % (80 MB)
112 09:25:28.955357 progress 75 % (86 MB)
113 09:25:29.298765 progress 80 % (92 MB)
114 09:25:29.640836 progress 85 % (98 MB)
115 09:25:29.998062 progress 90 % (103 MB)
116 09:25:30.328263 progress 95 % (109 MB)
117 09:25:30.700272 progress 100 % (115 MB)
118 09:25:30.705858 115 MB downloaded in 6.57 s (17.54 MB/s)
119 09:25:30.706126 end: 1.4.1 http-download (duration 00:00:07) [common]
121 09:25:30.706402 end: 1.4 download-retry (duration 00:00:07) [common]
122 09:25:30.706498 start: 1.5 download-retry (timeout 00:09:53) [common]
123 09:25:30.706588 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 09:25:30.706744 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:25:30.706817 saving as /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/modules/modules.tar
126 09:25:30.706881 total size: 8619356 (8 MB)
127 09:25:30.706947 Using unxz to decompress xz
128 09:25:30.710726 progress 0 % (0 MB)
129 09:25:30.730933 progress 5 % (0 MB)
130 09:25:30.755514 progress 10 % (0 MB)
131 09:25:30.780689 progress 15 % (1 MB)
132 09:25:30.805443 progress 20 % (1 MB)
133 09:25:30.831665 progress 25 % (2 MB)
134 09:25:30.864466 progress 30 % (2 MB)
135 09:25:30.891165 progress 35 % (2 MB)
136 09:25:30.915955 progress 40 % (3 MB)
137 09:25:30.941235 progress 45 % (3 MB)
138 09:25:30.965320 progress 50 % (4 MB)
139 09:25:30.990823 progress 55 % (4 MB)
140 09:25:31.015931 progress 60 % (4 MB)
141 09:25:31.040691 progress 65 % (5 MB)
142 09:25:31.069859 progress 70 % (5 MB)
143 09:25:31.095305 progress 75 % (6 MB)
144 09:25:31.120321 progress 80 % (6 MB)
145 09:25:31.144129 progress 85 % (7 MB)
146 09:25:31.168132 progress 90 % (7 MB)
147 09:25:31.196903 progress 95 % (7 MB)
148 09:25:31.227641 progress 100 % (8 MB)
149 09:25:31.232483 8 MB downloaded in 0.53 s (15.64 MB/s)
150 09:25:31.232773 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:25:31.233058 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:25:31.233158 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 09:25:31.233256 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 09:25:34.625174 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14407618/extract-nfsrootfs-voawszzn
156 09:25:34.625385 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 09:25:34.625493 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 09:25:34.625679 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl
159 09:25:34.625807 makedir: /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin
160 09:25:34.625906 makedir: /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/tests
161 09:25:34.626002 makedir: /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/results
162 09:25:34.626106 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-add-keys
163 09:25:34.626262 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-add-sources
164 09:25:34.626387 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-background-process-start
165 09:25:34.626520 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-background-process-stop
166 09:25:34.626694 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-common-functions
167 09:25:34.626818 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-echo-ipv4
168 09:25:34.626940 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-install-packages
169 09:25:34.627060 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-installed-packages
170 09:25:34.627224 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-os-build
171 09:25:34.627377 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-probe-channel
172 09:25:34.627528 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-probe-ip
173 09:25:34.627664 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-target-ip
174 09:25:34.627828 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-target-mac
175 09:25:34.627949 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-target-storage
176 09:25:34.628072 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-test-case
177 09:25:34.628201 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-test-event
178 09:25:34.628329 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-test-feedback
179 09:25:34.628450 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-test-raise
180 09:25:34.628592 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-test-reference
181 09:25:34.628724 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-test-runner
182 09:25:34.628848 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-test-set
183 09:25:34.629005 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-test-shell
184 09:25:34.629125 Updating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-add-keys (debian)
185 09:25:34.629331 Updating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-add-sources (debian)
186 09:25:34.629501 Updating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-install-packages (debian)
187 09:25:34.629668 Updating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-installed-packages (debian)
188 09:25:34.629858 Updating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/bin/lava-os-build (debian)
189 09:25:34.629974 Creating /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/environment
190 09:25:34.630067 LAVA metadata
191 09:25:34.630164 - LAVA_JOB_ID=14407618
192 09:25:34.630241 - LAVA_DISPATCHER_IP=192.168.201.1
193 09:25:34.630396 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 09:25:34.630493 skipped lava-vland-overlay
195 09:25:34.630630 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 09:25:34.630759 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 09:25:34.630860 skipped lava-multinode-overlay
198 09:25:34.630957 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 09:25:34.631044 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 09:25:34.631123 Loading test definitions
201 09:25:34.631221 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 09:25:34.631296 Using /lava-14407618 at stage 0
203 09:25:34.631574 uuid=14407618_1.6.2.3.1 testdef=None
204 09:25:34.631679 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 09:25:34.631764 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 09:25:34.632248 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 09:25:34.632478 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 09:25:34.633154 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 09:25:34.633457 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 09:25:34.634054 runner path: /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/0/tests/0_timesync-off test_uuid 14407618_1.6.2.3.1
213 09:25:34.634221 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 09:25:34.634447 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 09:25:34.634522 Using /lava-14407618 at stage 0
217 09:25:34.634619 Fetching tests from https://github.com/kernelci/test-definitions.git
218 09:25:34.634708 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/0/tests/1_kselftest-dt'
219 09:25:37.150361 Running '/usr/bin/git checkout kernelci.org
220 09:25:37.257698 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 09:25:37.258422 uuid=14407618_1.6.2.3.5 testdef=None
222 09:25:37.258589 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 09:25:37.258830 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 09:25:37.259574 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 09:25:37.259858 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 09:25:37.260993 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 09:25:37.261243 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 09:25:37.262235 runner path: /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/0/tests/1_kselftest-dt test_uuid 14407618_1.6.2.3.5
232 09:25:37.262327 BOARD='mt8192-asurada-spherion-r0'
233 09:25:37.262395 BRANCH='cip'
234 09:25:37.262457 SKIPFILE='/dev/null'
235 09:25:37.262519 SKIP_INSTALL='True'
236 09:25:37.262577 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 09:25:37.262636 TST_CASENAME=''
238 09:25:37.262694 TST_CMDFILES='dt'
239 09:25:37.262833 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 09:25:37.263044 Creating lava-test-runner.conf files
242 09:25:37.263111 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407618/lava-overlay-1xlx5lpl/lava-14407618/0 for stage 0
243 09:25:37.263203 - 0_timesync-off
244 09:25:37.263271 - 1_kselftest-dt
245 09:25:37.263366 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 09:25:37.263456 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 09:25:44.858580 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 09:25:44.858742 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 09:25:44.858837 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 09:25:44.858936 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 09:25:44.859028 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 09:25:45.018652 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 09:25:45.019042 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 09:25:45.019155 extracting modules file /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407618/extract-nfsrootfs-voawszzn
255 09:25:45.223266 extracting modules file /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407618/extract-overlay-ramdisk-01tqq_k6/ramdisk
256 09:25:45.432932 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 09:25:45.433111 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 09:25:45.433215 [common] Applying overlay to NFS
259 09:25:45.433290 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407618/compress-overlay-3ag6grt3/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407618/extract-nfsrootfs-voawszzn
260 09:25:46.354825 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 09:25:46.355095 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 09:25:46.355204 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 09:25:46.355299 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 09:25:46.355385 Building ramdisk /var/lib/lava/dispatcher/tmp/14407618/extract-overlay-ramdisk-01tqq_k6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407618/extract-overlay-ramdisk-01tqq_k6/ramdisk
265 09:25:46.653760 >> 130466 blocks
266 09:25:48.686075 rename /var/lib/lava/dispatcher/tmp/14407618/extract-overlay-ramdisk-01tqq_k6/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/ramdisk/ramdisk.cpio.gz
267 09:25:48.686515 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 09:25:48.686647 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 09:25:48.686750 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 09:25:48.686870 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/kernel/Image']
271 09:26:02.609322 Returned 0 in 13 seconds
272 09:26:02.709944 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/kernel/image.itb
273 09:26:03.057736 output: FIT description: Kernel Image image with one or more FDT blobs
274 09:26:03.058103 output: Created: Tue Jun 18 10:26:02 2024
275 09:26:03.058183 output: Image 0 (kernel-1)
276 09:26:03.058252 output: Description:
277 09:26:03.058319 output: Created: Tue Jun 18 10:26:02 2024
278 09:26:03.058384 output: Type: Kernel Image
279 09:26:03.058449 output: Compression: lzma compressed
280 09:26:03.058515 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
281 09:26:03.058578 output: Architecture: AArch64
282 09:26:03.058636 output: OS: Linux
283 09:26:03.058701 output: Load Address: 0x00000000
284 09:26:03.058758 output: Entry Point: 0x00000000
285 09:26:03.058823 output: Hash algo: crc32
286 09:26:03.058883 output: Hash value: 4137a6e7
287 09:26:03.058940 output: Image 1 (fdt-1)
288 09:26:03.058997 output: Description: mt8192-asurada-spherion-r0
289 09:26:03.059054 output: Created: Tue Jun 18 10:26:02 2024
290 09:26:03.059113 output: Type: Flat Device Tree
291 09:26:03.059169 output: Compression: uncompressed
292 09:26:03.059224 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 09:26:03.059280 output: Architecture: AArch64
294 09:26:03.059358 output: Hash algo: crc32
295 09:26:03.059428 output: Hash value: 0f8e4d2e
296 09:26:03.059484 output: Image 2 (ramdisk-1)
297 09:26:03.059539 output: Description: unavailable
298 09:26:03.059594 output: Created: Tue Jun 18 10:26:02 2024
299 09:26:03.059651 output: Type: RAMDisk Image
300 09:26:03.059706 output: Compression: Unknown Compression
301 09:26:03.059761 output: Data Size: 18749110 Bytes = 18309.68 KiB = 17.88 MiB
302 09:26:03.059817 output: Architecture: AArch64
303 09:26:03.059873 output: OS: Linux
304 09:26:03.059928 output: Load Address: unavailable
305 09:26:03.059984 output: Entry Point: unavailable
306 09:26:03.060039 output: Hash algo: crc32
307 09:26:03.060095 output: Hash value: 7f734b9a
308 09:26:03.060150 output: Default Configuration: 'conf-1'
309 09:26:03.060206 output: Configuration 0 (conf-1)
310 09:26:03.060261 output: Description: mt8192-asurada-spherion-r0
311 09:26:03.060316 output: Kernel: kernel-1
312 09:26:03.060371 output: Init Ramdisk: ramdisk-1
313 09:26:03.060426 output: FDT: fdt-1
314 09:26:03.060481 output: Loadables: kernel-1
315 09:26:03.060536 output:
316 09:26:03.060759 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 09:26:03.060866 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 09:26:03.060977 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 09:26:03.061070 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 09:26:03.061147 No LXC device requested
321 09:26:03.061228 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 09:26:03.061317 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 09:26:03.061408 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 09:26:03.061477 Checking files for TFTP limit of 4294967296 bytes.
325 09:26:03.061980 end: 1 tftp-deploy (duration 00:00:40) [common]
326 09:26:03.062092 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 09:26:03.062188 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 09:26:03.062314 substitutions:
329 09:26:03.062383 - {DTB}: 14407618/tftp-deploy-hb8xxyhl/dtb/mt8192-asurada-spherion-r0.dtb
330 09:26:03.062449 - {INITRD}: 14407618/tftp-deploy-hb8xxyhl/ramdisk/ramdisk.cpio.gz
331 09:26:03.062513 - {KERNEL}: 14407618/tftp-deploy-hb8xxyhl/kernel/Image
332 09:26:03.062573 - {LAVA_MAC}: None
333 09:26:03.062632 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14407618/extract-nfsrootfs-voawszzn
334 09:26:03.062691 - {NFS_SERVER_IP}: 192.168.201.1
335 09:26:03.062749 - {PRESEED_CONFIG}: None
336 09:26:03.062807 - {PRESEED_LOCAL}: None
337 09:26:03.062864 - {RAMDISK}: 14407618/tftp-deploy-hb8xxyhl/ramdisk/ramdisk.cpio.gz
338 09:26:03.062920 - {ROOT_PART}: None
339 09:26:03.062977 - {ROOT}: None
340 09:26:03.063037 - {SERVER_IP}: 192.168.201.1
341 09:26:03.063093 - {TEE}: None
342 09:26:03.063150 Parsed boot commands:
343 09:26:03.063206 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 09:26:03.063419 Parsed boot commands: tftpboot 192.168.201.1 14407618/tftp-deploy-hb8xxyhl/kernel/image.itb 14407618/tftp-deploy-hb8xxyhl/kernel/cmdline
345 09:26:03.063512 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 09:26:03.063599 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 09:26:03.063693 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 09:26:03.063783 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 09:26:03.063859 Not connected, no need to disconnect.
350 09:26:03.063936 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 09:26:03.064018 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 09:26:03.064089 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 09:26:03.067594 Setting prompt string to ['lava-test: # ']
354 09:26:03.067979 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 09:26:03.068127 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 09:26:03.068272 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 09:26:03.068432 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 09:26:03.068744 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
359 09:26:16.609110 Returned 0 in 13 seconds
360 09:26:16.709736 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 09:26:16.710063 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 09:26:16.710170 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 09:26:16.710277 Setting prompt string to 'Starting depthcharge on Spherion...'
365 09:26:16.710351 Changing prompt to 'Starting depthcharge on Spherion...'
366 09:26:16.710424 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 09:26:16.710828 [Enter `^Ec?' for help]
368 09:26:16.710907
369 09:26:16.710976
370 09:26:16.711042 F0: 102B 0000
371 09:26:16.711108
372 09:26:16.711170 F3: 1001 0000 [0200]
373 09:26:16.711233
374 09:26:16.711291 F3: 1001 0000
375 09:26:16.711351
376 09:26:16.711408 F7: 102D 0000
377 09:26:16.711465
378 09:26:16.711523 F1: 0000 0000
379 09:26:16.711579
380 09:26:16.711635 V0: 0000 0000 [0001]
381 09:26:16.711692
382 09:26:16.711748 00: 0007 8000
383 09:26:16.711809
384 09:26:16.711865 01: 0000 0000
385 09:26:16.711923
386 09:26:16.711979 BP: 0C00 0209 [0000]
387 09:26:16.712036
388 09:26:16.712091 G0: 1182 0000
389 09:26:16.712147
390 09:26:16.712204 EC: 0000 0021 [4000]
391 09:26:16.712261
392 09:26:16.712316 S7: 0000 0000 [0000]
393 09:26:16.712373
394 09:26:16.712429 CC: 0000 0000 [0001]
395 09:26:16.712485
396 09:26:16.712541 T0: 0000 0040 [010F]
397 09:26:16.712645
398 09:26:16.712702 Jump to BL
399 09:26:16.712758
400 09:26:16.712814
401 09:26:16.712869
402 09:26:16.712926 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 09:26:16.712987 ARM64: Exception handlers installed.
404 09:26:16.713045 ARM64: Testing exception
405 09:26:16.713102 ARM64: Done test exception
406 09:26:16.713158 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 09:26:16.713214 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 09:26:16.713272 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 09:26:16.713329 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 09:26:16.713386 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 09:26:16.713442 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 09:26:16.713499 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 09:26:16.713556 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 09:26:16.713613 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 09:26:16.713670 WDT: Last reset was cold boot
416 09:26:16.713726 SPI1(PAD0) initialized at 2873684 Hz
417 09:26:16.713783 SPI5(PAD0) initialized at 992727 Hz
418 09:26:16.713838 VBOOT: Loading verstage.
419 09:26:16.713894 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 09:26:16.713951 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 09:26:16.714008 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 09:26:16.714065 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 09:26:16.714122 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 09:26:16.714179 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 09:26:16.714236 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 09:26:16.714292
427 09:26:16.714348
428 09:26:16.714403 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 09:26:16.714460 ARM64: Exception handlers installed.
430 09:26:16.714516 ARM64: Testing exception
431 09:26:16.714571 ARM64: Done test exception
432 09:26:16.714627 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 09:26:16.714684 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 09:26:16.714740 Probing TPM: . done!
435 09:26:16.714797 TPM ready after 0 ms
436 09:26:16.714854 Connected to device vid:did:rid of 1ae0:0028:00
437 09:26:16.714910 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
438 09:26:16.714967 Initialized TPM device CR50 revision 0
439 09:26:16.715024 tlcl_send_startup: Startup return code is 0
440 09:26:16.715080 TPM: setup succeeded
441 09:26:16.715136 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 09:26:16.715192 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 09:26:16.715248 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 09:26:16.715305 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 09:26:16.715361 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 09:26:16.715418 in-header: 03 07 00 00 08 00 00 00
447 09:26:16.715474 in-data: aa e4 47 04 13 02 00 00
448 09:26:16.715530 Chrome EC: UHEPI supported
449 09:26:16.715586 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 09:26:16.715643 in-header: 03 a9 00 00 08 00 00 00
451 09:26:16.715699 in-data: 84 60 60 08 00 00 00 00
452 09:26:16.715755 Phase 1
453 09:26:16.715810 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 09:26:16.715867 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 09:26:16.715923 VB2:vb2_check_recovery() Recovery was requested manually
456 09:26:16.715980 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 09:26:16.716036 Recovery requested (1009000e)
458 09:26:16.716092 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 09:26:16.716149 tlcl_extend: response is 0
460 09:26:16.716205 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 09:26:16.716261 tlcl_extend: response is 0
462 09:26:16.716318 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 09:26:16.716375 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 09:26:16.716431 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 09:26:16.716488
466 09:26:16.716543
467 09:26:16.716644 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 09:26:16.716702 ARM64: Exception handlers installed.
469 09:26:16.716758 ARM64: Testing exception
470 09:26:16.716814 ARM64: Done test exception
471 09:26:16.716871 pmic_efuse_setting: Set efuses in 11 msecs
472 09:26:16.716927 pmwrap_interface_init: Select PMIF_VLD_RDY
473 09:26:16.716983 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 09:26:16.717040 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 09:26:16.717283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 09:26:16.717346 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 09:26:16.717403 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 09:26:16.717460 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 09:26:16.717516 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 09:26:16.717573 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 09:26:16.717630 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 09:26:16.717686 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 09:26:16.717742 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 09:26:16.717798 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 09:26:16.717854 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 09:26:16.717910 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 09:26:16.717967 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 09:26:16.718023 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 09:26:16.718079 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 09:26:16.718136 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 09:26:16.718192 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 09:26:16.718248 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 09:26:16.718305 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 09:26:16.718361 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 09:26:16.718418 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 09:26:16.718474 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 09:26:16.718530 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 09:26:16.718586 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 09:26:16.718642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 09:26:16.718699 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 09:26:16.718755 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 09:26:16.718812 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 09:26:16.718869 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 09:26:16.718925 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 09:26:16.718982 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 09:26:16.719038 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 09:26:16.719095 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 09:26:16.719151 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 09:26:16.719207 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 09:26:16.719264 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 09:26:16.719320 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 09:26:16.719376 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 09:26:16.719432 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 09:26:16.719489 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 09:26:16.719545 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 09:26:16.719601 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 09:26:16.719657 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 09:26:16.719713 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 09:26:16.719770 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 09:26:16.719825 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 09:26:16.719881 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 09:26:16.719937 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 09:26:16.719993 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 09:26:16.720049 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 09:26:16.720106 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 09:26:16.720163 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 09:26:16.720220 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 09:26:16.720277 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 09:26:16.720333 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 09:26:16.720390 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 09:26:16.720446 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 09:26:16.720503 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2d
533 09:26:16.720588 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 09:26:16.720661 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 09:26:16.720718 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 09:26:16.720775 [RTC]rtc_get_frequency_meter,154: input=15, output=772
537 09:26:16.720832 [RTC]rtc_get_frequency_meter,154: input=23, output=956
538 09:26:16.720889 [RTC]rtc_get_frequency_meter,154: input=19, output=866
539 09:26:16.720945 [RTC]rtc_get_frequency_meter,154: input=17, output=819
540 09:26:16.721001 [RTC]rtc_get_frequency_meter,154: input=16, output=794
541 09:26:16.721057 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
542 09:26:16.721131 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
543 09:26:16.721200 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
544 09:26:16.721257 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
545 09:26:16.721499 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
546 09:26:16.721562 ADC[4]: Raw value=902876 ID=7
547 09:26:16.721620 ADC[3]: Raw value=212810 ID=1
548 09:26:16.721677 RAM Code: 0x71
549 09:26:16.721734 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
550 09:26:16.721791 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
551 09:26:16.721849 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
552 09:26:16.721906 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
553 09:26:16.721963 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
554 09:26:16.722019 in-header: 03 07 00 00 08 00 00 00
555 09:26:16.722076 in-data: aa e4 47 04 13 02 00 00
556 09:26:16.722132 Chrome EC: UHEPI supported
557 09:26:16.722188 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
558 09:26:16.722245 in-header: 03 a9 00 00 08 00 00 00
559 09:26:16.722301 in-data: 84 60 60 08 00 00 00 00
560 09:26:16.722357 MRC: failed to locate region type 0.
561 09:26:16.722444 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
562 09:26:16.722501 DRAM-K: Running full calibration
563 09:26:16.722557 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
564 09:26:16.722613 header.status = 0x0
565 09:26:16.722669 header.version = 0x6 (expected: 0x6)
566 09:26:16.722724 header.size = 0xd00 (expected: 0xd00)
567 09:26:16.722780 header.flags = 0x0
568 09:26:16.722836 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
569 09:26:16.722893 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
570 09:26:16.722950 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
571 09:26:16.723006 dram_init: ddr_geometry: 2
572 09:26:16.723062 [EMI] MDL number = 2
573 09:26:16.723118 [EMI] Get MDL freq = 0
574 09:26:16.723173 dram_init: ddr_type: 0
575 09:26:16.723229 is_discrete_lpddr4: 1
576 09:26:16.723284 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
577 09:26:16.723340
578 09:26:16.723396
579 09:26:16.723452 [Bian_co] ETT version 0.0.0.1
580 09:26:16.723508 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
581 09:26:16.723564
582 09:26:16.723619 dramc_set_vcore_voltage set vcore to 650000
583 09:26:16.723676 Read voltage for 800, 4
584 09:26:16.723731 Vio18 = 0
585 09:26:16.723787 Vcore = 650000
586 09:26:16.723842 Vdram = 0
587 09:26:16.723898 Vddq = 0
588 09:26:16.723954 Vmddr = 0
589 09:26:16.724009 dram_init: config_dvfs: 1
590 09:26:16.724065 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
591 09:26:16.724121 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
592 09:26:16.724177 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
593 09:26:16.724233 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
594 09:26:16.724291 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
595 09:26:16.724347 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
596 09:26:16.724434 MEM_TYPE=3, freq_sel=18
597 09:26:16.724489 sv_algorithm_assistance_LP4_1600
598 09:26:16.724564 ============ PULL DRAM RESETB DOWN ============
599 09:26:16.724643 ========== PULL DRAM RESETB DOWN end =========
600 09:26:16.724700 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
601 09:26:16.724757 ===================================
602 09:26:16.724813 LPDDR4 DRAM CONFIGURATION
603 09:26:16.724869 ===================================
604 09:26:16.724925 EX_ROW_EN[0] = 0x0
605 09:26:16.724981 EX_ROW_EN[1] = 0x0
606 09:26:16.725037 LP4Y_EN = 0x0
607 09:26:16.725093 WORK_FSP = 0x0
608 09:26:16.725148 WL = 0x2
609 09:26:16.725204 RL = 0x2
610 09:26:16.725260 BL = 0x2
611 09:26:16.725315 RPST = 0x0
612 09:26:16.725371 RD_PRE = 0x0
613 09:26:16.725456 WR_PRE = 0x1
614 09:26:16.725511 WR_PST = 0x0
615 09:26:16.725567 DBI_WR = 0x0
616 09:26:16.725626 DBI_RD = 0x0
617 09:26:16.725681 OTF = 0x1
618 09:26:16.725738 ===================================
619 09:26:16.725794 ===================================
620 09:26:16.725851 ANA top config
621 09:26:16.725907 ===================================
622 09:26:16.725964 DLL_ASYNC_EN = 0
623 09:26:16.726020 ALL_SLAVE_EN = 1
624 09:26:16.726076 NEW_RANK_MODE = 1
625 09:26:16.726134 DLL_IDLE_MODE = 1
626 09:26:16.726195 LP45_APHY_COMB_EN = 1
627 09:26:16.726258 TX_ODT_DIS = 1
628 09:26:16.726315 NEW_8X_MODE = 1
629 09:26:16.726373 ===================================
630 09:26:16.726430 ===================================
631 09:26:16.726501 data_rate = 1600
632 09:26:16.726572 CKR = 1
633 09:26:16.726628 DQ_P2S_RATIO = 8
634 09:26:16.726684 ===================================
635 09:26:16.726740 CA_P2S_RATIO = 8
636 09:26:16.726795 DQ_CA_OPEN = 0
637 09:26:16.726851 DQ_SEMI_OPEN = 0
638 09:26:16.726907 CA_SEMI_OPEN = 0
639 09:26:16.726962 CA_FULL_RATE = 0
640 09:26:16.727017 DQ_CKDIV4_EN = 1
641 09:26:16.727073 CA_CKDIV4_EN = 1
642 09:26:16.727129 CA_PREDIV_EN = 0
643 09:26:16.727184 PH8_DLY = 0
644 09:26:16.727240 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
645 09:26:16.727295 DQ_AAMCK_DIV = 4
646 09:26:16.727351 CA_AAMCK_DIV = 4
647 09:26:16.727407 CA_ADMCK_DIV = 4
648 09:26:16.727462 DQ_TRACK_CA_EN = 0
649 09:26:16.727518 CA_PICK = 800
650 09:26:16.727575 CA_MCKIO = 800
651 09:26:16.727631 MCKIO_SEMI = 0
652 09:26:16.727687 PLL_FREQ = 3068
653 09:26:16.727743 DQ_UI_PI_RATIO = 32
654 09:26:16.727798 CA_UI_PI_RATIO = 0
655 09:26:16.727853 ===================================
656 09:26:16.727910 ===================================
657 09:26:16.727966 memory_type:LPDDR4
658 09:26:16.728021 GP_NUM : 10
659 09:26:16.728076 SRAM_EN : 1
660 09:26:16.728133 MD32_EN : 0
661 09:26:16.728189 ===================================
662 09:26:16.728245 [ANA_INIT] >>>>>>>>>>>>>>
663 09:26:16.728301 <<<<<< [CONFIGURE PHASE]: ANA_TX
664 09:26:16.728359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
665 09:26:16.728415 ===================================
666 09:26:16.728676 data_rate = 1600,PCW = 0X7600
667 09:26:16.728743 ===================================
668 09:26:16.728865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
669 09:26:16.728968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
670 09:26:16.729057 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 09:26:16.729145 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
672 09:26:16.729232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
673 09:26:16.729318 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
674 09:26:16.729405 [ANA_INIT] flow start
675 09:26:16.729465 [ANA_INIT] PLL >>>>>>>>
676 09:26:16.729522 [ANA_INIT] PLL <<<<<<<<
677 09:26:16.729578 [ANA_INIT] MIDPI >>>>>>>>
678 09:26:16.729634 [ANA_INIT] MIDPI <<<<<<<<
679 09:26:16.729690 [ANA_INIT] DLL >>>>>>>>
680 09:26:16.729747 [ANA_INIT] flow end
681 09:26:16.729803 ============ LP4 DIFF to SE enter ============
682 09:26:16.729860 ============ LP4 DIFF to SE exit ============
683 09:26:16.729917 [ANA_INIT] <<<<<<<<<<<<<
684 09:26:16.729973 [Flow] Enable top DCM control >>>>>
685 09:26:16.730029 [Flow] Enable top DCM control <<<<<
686 09:26:16.730085 Enable DLL master slave shuffle
687 09:26:16.730141 ==============================================================
688 09:26:16.730197 Gating Mode config
689 09:26:16.730253 ==============================================================
690 09:26:16.730309 Config description:
691 09:26:16.730365 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
692 09:26:16.730423 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
693 09:26:16.730479 SELPH_MODE 0: By rank 1: By Phase
694 09:26:16.730536 ==============================================================
695 09:26:16.730593 GAT_TRACK_EN = 1
696 09:26:16.730649 RX_GATING_MODE = 2
697 09:26:16.730705 RX_GATING_TRACK_MODE = 2
698 09:26:16.730760 SELPH_MODE = 1
699 09:26:16.730816 PICG_EARLY_EN = 1
700 09:26:16.730872 VALID_LAT_VALUE = 1
701 09:26:16.730927 ==============================================================
702 09:26:16.730983 Enter into Gating configuration >>>>
703 09:26:16.731040 Exit from Gating configuration <<<<
704 09:26:16.731095 Enter into DVFS_PRE_config >>>>>
705 09:26:16.731152 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
706 09:26:16.731213 Exit from DVFS_PRE_config <<<<<
707 09:26:16.731268 Enter into PICG configuration >>>>
708 09:26:16.731324 Exit from PICG configuration <<<<
709 09:26:16.731381 [RX_INPUT] configuration >>>>>
710 09:26:16.731436 [RX_INPUT] configuration <<<<<
711 09:26:16.731492 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
712 09:26:16.731549 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
713 09:26:16.731605 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
714 09:26:16.731661 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
715 09:26:16.731718 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
716 09:26:16.731773 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
717 09:26:16.731829 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
718 09:26:16.731885 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
719 09:26:16.731941 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
720 09:26:16.731997 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
721 09:26:16.732053 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
722 09:26:16.732108 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
723 09:26:16.732165 ===================================
724 09:26:16.732221 LPDDR4 DRAM CONFIGURATION
725 09:26:16.732276 ===================================
726 09:26:16.732333 EX_ROW_EN[0] = 0x0
727 09:26:16.732389 EX_ROW_EN[1] = 0x0
728 09:26:16.732445 LP4Y_EN = 0x0
729 09:26:16.732501 WORK_FSP = 0x0
730 09:26:16.732615 WL = 0x2
731 09:26:16.732687 RL = 0x2
732 09:26:16.732743 BL = 0x2
733 09:26:16.732799 RPST = 0x0
734 09:26:16.732855 RD_PRE = 0x0
735 09:26:16.732910 WR_PRE = 0x1
736 09:26:16.732966 WR_PST = 0x0
737 09:26:16.733021 DBI_WR = 0x0
738 09:26:16.733076 DBI_RD = 0x0
739 09:26:16.733131 OTF = 0x1
740 09:26:16.733188 ===================================
741 09:26:16.733244 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
742 09:26:16.733300 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
743 09:26:16.733356 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
744 09:26:16.733413 ===================================
745 09:26:16.733468 LPDDR4 DRAM CONFIGURATION
746 09:26:16.733523 ===================================
747 09:26:16.733579 EX_ROW_EN[0] = 0x10
748 09:26:16.733635 EX_ROW_EN[1] = 0x0
749 09:26:16.733690 LP4Y_EN = 0x0
750 09:26:16.733746 WORK_FSP = 0x0
751 09:26:16.733801 WL = 0x2
752 09:26:16.733856 RL = 0x2
753 09:26:16.733911 BL = 0x2
754 09:26:16.733967 RPST = 0x0
755 09:26:16.734022 RD_PRE = 0x0
756 09:26:16.734077 WR_PRE = 0x1
757 09:26:16.734133 WR_PST = 0x0
758 09:26:16.734188 DBI_WR = 0x0
759 09:26:16.734243 DBI_RD = 0x0
760 09:26:16.734299 OTF = 0x1
761 09:26:16.734354 ===================================
762 09:26:16.734410 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
763 09:26:16.734466 nWR fixed to 40
764 09:26:16.734522 [ModeRegInit_LP4] CH0 RK0
765 09:26:16.734578 [ModeRegInit_LP4] CH0 RK1
766 09:26:16.734633 [ModeRegInit_LP4] CH1 RK0
767 09:26:16.734688 [ModeRegInit_LP4] CH1 RK1
768 09:26:16.734744 match AC timing 13
769 09:26:16.734799 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
770 09:26:16.734856 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
771 09:26:16.734912 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
772 09:26:16.734968 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
773 09:26:16.735217 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
774 09:26:16.735283 [EMI DOE] emi_dcm 0
775 09:26:16.735341 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
776 09:26:16.735413 ==
777 09:26:16.735492 Dram Type= 6, Freq= 0, CH_0, rank 0
778 09:26:16.735580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 09:26:16.735638 ==
780 09:26:16.735729 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
781 09:26:16.735786 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
782 09:26:16.735843 [CA 0] Center 38 (7~69) winsize 63
783 09:26:16.735899 [CA 1] Center 38 (7~69) winsize 63
784 09:26:16.735956 [CA 2] Center 35 (5~66) winsize 62
785 09:26:16.736012 [CA 3] Center 35 (5~66) winsize 62
786 09:26:16.736068 [CA 4] Center 35 (4~66) winsize 63
787 09:26:16.736124 [CA 5] Center 33 (3~64) winsize 62
788 09:26:16.736179
789 09:26:16.736243 [CmdBusTrainingLP45] Vref(ca) range 1: 32
790 09:26:16.736330
791 09:26:16.736408 [CATrainingPosCal] consider 1 rank data
792 09:26:16.736467 u2DelayCellTimex100 = 270/100 ps
793 09:26:16.736525 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
794 09:26:16.736611 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
795 09:26:16.736668 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
796 09:26:16.736725 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
797 09:26:16.736797 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
798 09:26:16.736885 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
799 09:26:16.736954
800 09:26:16.737010 CA PerBit enable=1, Macro0, CA PI delay=33
801 09:26:16.737067
802 09:26:16.737123 [CBTSetCACLKResult] CA Dly = 33
803 09:26:16.737179 CS Dly: 6 (0~37)
804 09:26:16.737235 ==
805 09:26:16.737291 Dram Type= 6, Freq= 0, CH_0, rank 1
806 09:26:16.737348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
807 09:26:16.737404 ==
808 09:26:16.737460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
809 09:26:16.737517 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
810 09:26:16.737573 [CA 0] Center 38 (7~69) winsize 63
811 09:26:16.737629 [CA 1] Center 38 (8~69) winsize 62
812 09:26:16.737685 [CA 2] Center 36 (6~67) winsize 62
813 09:26:16.737741 [CA 3] Center 35 (5~66) winsize 62
814 09:26:16.737797 [CA 4] Center 35 (4~66) winsize 63
815 09:26:16.737853 [CA 5] Center 34 (4~65) winsize 62
816 09:26:16.737909
817 09:26:16.737964 [CmdBusTrainingLP45] Vref(ca) range 1: 30
818 09:26:16.738020
819 09:26:16.738076 [CATrainingPosCal] consider 2 rank data
820 09:26:16.738132 u2DelayCellTimex100 = 270/100 ps
821 09:26:16.738189 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
822 09:26:16.738245 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
823 09:26:16.738301 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
824 09:26:16.738388 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
825 09:26:16.738476 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
826 09:26:16.738532 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
827 09:26:16.738588
828 09:26:16.738643 CA PerBit enable=1, Macro0, CA PI delay=34
829 09:26:16.738699
830 09:26:16.738754 [CBTSetCACLKResult] CA Dly = 34
831 09:26:16.738810 CS Dly: 6 (0~38)
832 09:26:16.738865
833 09:26:16.738921 ----->DramcWriteLeveling(PI) begin...
834 09:26:16.738978 ==
835 09:26:16.739057 Dram Type= 6, Freq= 0, CH_0, rank 0
836 09:26:16.739118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
837 09:26:16.739176 ==
838 09:26:16.739232 Write leveling (Byte 0): 32 => 32
839 09:26:16.739289 Write leveling (Byte 1): 27 => 27
840 09:26:16.739345 DramcWriteLeveling(PI) end<-----
841 09:26:16.739401
842 09:26:16.739472 ==
843 09:26:16.739544 Dram Type= 6, Freq= 0, CH_0, rank 0
844 09:26:16.739600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
845 09:26:16.739656 ==
846 09:26:16.739712 [Gating] SW mode calibration
847 09:26:16.739768 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
848 09:26:16.739825 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
849 09:26:16.739881 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
850 09:26:16.739938 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
851 09:26:16.739994 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
852 09:26:16.740050 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 09:26:16.740106 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 09:26:16.740162 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 09:26:16.740218 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 09:26:16.740274 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 09:26:16.740330 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 09:26:16.740406 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 09:26:16.740464 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 09:26:16.740521 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 09:26:16.740611 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 09:26:16.740668 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 09:26:16.740725 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 09:26:16.740782 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 09:26:16.740838 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
866 09:26:16.740894 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
867 09:26:16.740950 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
868 09:26:16.741006 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 09:26:16.741062 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 09:26:16.741119 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 09:26:16.741204 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 09:26:16.741261 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 09:26:16.741317 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 09:26:16.741373 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
875 09:26:16.741429 0 9 8 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
876 09:26:16.741486 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
877 09:26:16.741542 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 09:26:16.741598 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 09:26:16.741654 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 09:26:16.741711 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 09:26:16.741961 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
882 09:26:16.742079 0 10 4 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
883 09:26:16.742137 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (0 0) (0 0)
884 09:26:16.742195 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
885 09:26:16.742253 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 09:26:16.742310 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 09:26:16.742367 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 09:26:16.742424 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 09:26:16.742482 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 09:26:16.742552 0 11 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
891 09:26:16.742668 0 11 8 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
892 09:26:16.742745 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
893 09:26:16.742803 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 09:26:16.742860 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 09:26:16.742917 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 09:26:16.742972 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 09:26:16.743029 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 09:26:16.743084 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
899 09:26:16.743141 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
900 09:26:16.743197 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 09:26:16.743253 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 09:26:16.743309 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 09:26:16.743365 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 09:26:16.743421 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 09:26:16.743477 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 09:26:16.743533 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 09:26:16.743589 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 09:26:16.743645 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 09:26:16.743701 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 09:26:16.743758 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 09:26:16.743814 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 09:26:16.743875 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 09:26:16.743931 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 09:26:16.743987 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
915 09:26:16.744043 Total UI for P1: 0, mck2ui 16
916 09:26:16.744100 best dqsien dly found for B0: ( 0, 14, 2)
917 09:26:16.744157 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
918 09:26:16.744213 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
919 09:26:16.744270 Total UI for P1: 0, mck2ui 16
920 09:26:16.744326 best dqsien dly found for B1: ( 0, 14, 8)
921 09:26:16.744382 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
922 09:26:16.744438 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
923 09:26:16.744511
924 09:26:16.744593 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
925 09:26:16.744651 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
926 09:26:16.744707 [Gating] SW calibration Done
927 09:26:16.744763 ==
928 09:26:16.744819 Dram Type= 6, Freq= 0, CH_0, rank 0
929 09:26:16.744875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 09:26:16.744932 ==
931 09:26:16.744988 RX Vref Scan: 0
932 09:26:16.745043
933 09:26:16.745099 RX Vref 0 -> 0, step: 1
934 09:26:16.745154
935 09:26:16.745210 RX Delay -130 -> 252, step: 16
936 09:26:16.745266 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
937 09:26:16.745322 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
938 09:26:16.745378 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
939 09:26:16.745460 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
940 09:26:16.745518 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
941 09:26:16.745575 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
942 09:26:16.745630 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
943 09:26:16.745687 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
944 09:26:16.745742 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
945 09:26:16.745798 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
946 09:26:16.745854 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
947 09:26:16.745911 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
948 09:26:16.745967 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
949 09:26:16.746023 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
950 09:26:16.746095 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
951 09:26:16.746180 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
952 09:26:16.746250 ==
953 09:26:16.746352 Dram Type= 6, Freq= 0, CH_0, rank 0
954 09:26:16.746410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
955 09:26:16.746468 ==
956 09:26:16.746525 DQS Delay:
957 09:26:16.746582 DQS0 = 0, DQS1 = 0
958 09:26:16.746639 DQM Delay:
959 09:26:16.746696 DQM0 = 91, DQM1 = 80
960 09:26:16.746754 DQ Delay:
961 09:26:16.746811 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
962 09:26:16.746868 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
963 09:26:16.746925 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
964 09:26:16.746982 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
965 09:26:16.747039
966 09:26:16.747096
967 09:26:16.747152 ==
968 09:26:16.747209 Dram Type= 6, Freq= 0, CH_0, rank 0
969 09:26:16.747266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 09:26:16.747323 ==
971 09:26:16.747380
972 09:26:16.747436
973 09:26:16.747492 TX Vref Scan disable
974 09:26:16.747549 == TX Byte 0 ==
975 09:26:16.747606 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
976 09:26:16.747663 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
977 09:26:16.747720 == TX Byte 1 ==
978 09:26:16.747777 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
979 09:26:16.747834 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
980 09:26:16.747892 ==
981 09:26:16.747949 Dram Type= 6, Freq= 0, CH_0, rank 0
982 09:26:16.748006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 09:26:16.748064 ==
984 09:26:16.748121 TX Vref=22, minBit 6, minWin=27, winSum=444
985 09:26:16.748178 TX Vref=24, minBit 10, minWin=27, winSum=447
986 09:26:16.748235 TX Vref=26, minBit 0, minWin=28, winSum=453
987 09:26:16.748293 TX Vref=28, minBit 5, minWin=28, winSum=456
988 09:26:16.748350 TX Vref=30, minBit 6, minWin=28, winSum=459
989 09:26:16.748602 TX Vref=32, minBit 11, minWin=27, winSum=455
990 09:26:16.748665 [TxChooseVref] Worse bit 6, Min win 28, Win sum 459, Final Vref 30
991 09:26:16.748723
992 09:26:16.748779 Final TX Range 1 Vref 30
993 09:26:16.748836
994 09:26:16.748892 ==
995 09:26:16.748948 Dram Type= 6, Freq= 0, CH_0, rank 0
996 09:26:16.749004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
997 09:26:16.749077 ==
998 09:26:16.749148
999 09:26:16.749203
1000 09:26:16.749258 TX Vref Scan disable
1001 09:26:16.749315 == TX Byte 0 ==
1002 09:26:16.749371 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1003 09:26:16.749428 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1004 09:26:16.749484 == TX Byte 1 ==
1005 09:26:16.749556 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1006 09:26:16.749652 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1007 09:26:16.749725
1008 09:26:16.749780 [DATLAT]
1009 09:26:16.749836 Freq=800, CH0 RK0
1010 09:26:16.749892
1011 09:26:16.749949 DATLAT Default: 0xa
1012 09:26:16.750006 0, 0xFFFF, sum = 0
1013 09:26:16.750064 1, 0xFFFF, sum = 0
1014 09:26:16.750122 2, 0xFFFF, sum = 0
1015 09:26:16.750179 3, 0xFFFF, sum = 0
1016 09:26:16.750238 4, 0xFFFF, sum = 0
1017 09:26:16.750295 5, 0xFFFF, sum = 0
1018 09:26:16.750352 6, 0xFFFF, sum = 0
1019 09:26:16.750408 7, 0xFFFF, sum = 0
1020 09:26:16.750508 8, 0xFFFF, sum = 0
1021 09:26:16.750608 9, 0x0, sum = 1
1022 09:26:16.750692 10, 0x0, sum = 2
1023 09:26:16.750748 11, 0x0, sum = 3
1024 09:26:16.750805 12, 0x0, sum = 4
1025 09:26:16.750868 best_step = 10
1026 09:26:16.750925
1027 09:26:16.750981 ==
1028 09:26:16.751036 Dram Type= 6, Freq= 0, CH_0, rank 0
1029 09:26:16.751093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1030 09:26:16.751149 ==
1031 09:26:16.751235 RX Vref Scan: 1
1032 09:26:16.751297
1033 09:26:16.751354 Set Vref Range= 32 -> 127
1034 09:26:16.751409
1035 09:26:16.751472 RX Vref 32 -> 127, step: 1
1036 09:26:16.751529
1037 09:26:16.751584 RX Delay -79 -> 252, step: 8
1038 09:26:16.751639
1039 09:26:16.751695 Set Vref, RX VrefLevel [Byte0]: 32
1040 09:26:16.751750 [Byte1]: 32
1041 09:26:16.751805
1042 09:26:16.751860 Set Vref, RX VrefLevel [Byte0]: 33
1043 09:26:16.751916 [Byte1]: 33
1044 09:26:16.751971
1045 09:26:16.752026 Set Vref, RX VrefLevel [Byte0]: 34
1046 09:26:16.752081 [Byte1]: 34
1047 09:26:16.752136
1048 09:26:16.752191 Set Vref, RX VrefLevel [Byte0]: 35
1049 09:26:16.752247 [Byte1]: 35
1050 09:26:16.752302
1051 09:26:16.752358 Set Vref, RX VrefLevel [Byte0]: 36
1052 09:26:16.752413 [Byte1]: 36
1053 09:26:16.752468
1054 09:26:16.752523 Set Vref, RX VrefLevel [Byte0]: 37
1055 09:26:16.752620 [Byte1]: 37
1056 09:26:16.752675
1057 09:26:16.752730 Set Vref, RX VrefLevel [Byte0]: 38
1058 09:26:16.752792 [Byte1]: 38
1059 09:26:16.752852
1060 09:26:16.752910 Set Vref, RX VrefLevel [Byte0]: 39
1061 09:26:16.752972 [Byte1]: 39
1062 09:26:16.753028
1063 09:26:16.753084 Set Vref, RX VrefLevel [Byte0]: 40
1064 09:26:16.753139 [Byte1]: 40
1065 09:26:16.753194
1066 09:26:16.753255 Set Vref, RX VrefLevel [Byte0]: 41
1067 09:26:16.753318 [Byte1]: 41
1068 09:26:16.753375
1069 09:26:16.753430 Set Vref, RX VrefLevel [Byte0]: 42
1070 09:26:16.753485 [Byte1]: 42
1071 09:26:16.753541
1072 09:26:16.753596 Set Vref, RX VrefLevel [Byte0]: 43
1073 09:26:16.753651 [Byte1]: 43
1074 09:26:16.753706
1075 09:26:16.753761 Set Vref, RX VrefLevel [Byte0]: 44
1076 09:26:16.753816 [Byte1]: 44
1077 09:26:16.753871
1078 09:26:16.753927 Set Vref, RX VrefLevel [Byte0]: 45
1079 09:26:16.753982 [Byte1]: 45
1080 09:26:16.754037
1081 09:26:16.754092 Set Vref, RX VrefLevel [Byte0]: 46
1082 09:26:16.754148 [Byte1]: 46
1083 09:26:16.754203
1084 09:26:16.754257 Set Vref, RX VrefLevel [Byte0]: 47
1085 09:26:16.754312 [Byte1]: 47
1086 09:26:16.754367
1087 09:26:16.754422 Set Vref, RX VrefLevel [Byte0]: 48
1088 09:26:16.754477 [Byte1]: 48
1089 09:26:16.754533
1090 09:26:16.754588 Set Vref, RX VrefLevel [Byte0]: 49
1091 09:26:16.754643 [Byte1]: 49
1092 09:26:16.754698
1093 09:26:16.754753 Set Vref, RX VrefLevel [Byte0]: 50
1094 09:26:16.754808 [Byte1]: 50
1095 09:26:16.754863
1096 09:26:16.754918 Set Vref, RX VrefLevel [Byte0]: 51
1097 09:26:16.754973 [Byte1]: 51
1098 09:26:16.755028
1099 09:26:16.755083 Set Vref, RX VrefLevel [Byte0]: 52
1100 09:26:16.755138 [Byte1]: 52
1101 09:26:16.755194
1102 09:26:16.755249 Set Vref, RX VrefLevel [Byte0]: 53
1103 09:26:16.755304 [Byte1]: 53
1104 09:26:16.755359
1105 09:26:16.755413 Set Vref, RX VrefLevel [Byte0]: 54
1106 09:26:16.755468 [Byte1]: 54
1107 09:26:16.755523
1108 09:26:16.755578 Set Vref, RX VrefLevel [Byte0]: 55
1109 09:26:16.755633 [Byte1]: 55
1110 09:26:16.755688
1111 09:26:16.755743 Set Vref, RX VrefLevel [Byte0]: 56
1112 09:26:16.755798 [Byte1]: 56
1113 09:26:16.755853
1114 09:26:16.755908 Set Vref, RX VrefLevel [Byte0]: 57
1115 09:26:16.755963 [Byte1]: 57
1116 09:26:16.756021
1117 09:26:16.756097 Set Vref, RX VrefLevel [Byte0]: 58
1118 09:26:16.756171 [Byte1]: 58
1119 09:26:16.756248
1120 09:26:16.756350 Set Vref, RX VrefLevel [Byte0]: 59
1121 09:26:16.756451 [Byte1]: 59
1122 09:26:16.756535
1123 09:26:16.756639 Set Vref, RX VrefLevel [Byte0]: 60
1124 09:26:16.756696 [Byte1]: 60
1125 09:26:16.756752
1126 09:26:16.756807 Set Vref, RX VrefLevel [Byte0]: 61
1127 09:26:16.756862 [Byte1]: 61
1128 09:26:16.756918
1129 09:26:16.756973 Set Vref, RX VrefLevel [Byte0]: 62
1130 09:26:16.757029 [Byte1]: 62
1131 09:26:16.757085
1132 09:26:16.757144 Set Vref, RX VrefLevel [Byte0]: 63
1133 09:26:16.757204 [Byte1]: 63
1134 09:26:16.757262
1135 09:26:16.757317 Set Vref, RX VrefLevel [Byte0]: 64
1136 09:26:16.757373 [Byte1]: 64
1137 09:26:16.757428
1138 09:26:16.757483 Set Vref, RX VrefLevel [Byte0]: 65
1139 09:26:16.757540 [Byte1]: 65
1140 09:26:16.757595
1141 09:26:16.757650 Set Vref, RX VrefLevel [Byte0]: 66
1142 09:26:16.757705 [Byte1]: 66
1143 09:26:16.757760
1144 09:26:16.757815 Set Vref, RX VrefLevel [Byte0]: 67
1145 09:26:16.757871 [Byte1]: 67
1146 09:26:16.757926
1147 09:26:16.757980 Set Vref, RX VrefLevel [Byte0]: 68
1148 09:26:16.758036 [Byte1]: 68
1149 09:26:16.758092
1150 09:26:16.758147 Set Vref, RX VrefLevel [Byte0]: 69
1151 09:26:16.758202 [Byte1]: 69
1152 09:26:16.758257
1153 09:26:16.758312 Set Vref, RX VrefLevel [Byte0]: 70
1154 09:26:16.758367 [Byte1]: 70
1155 09:26:16.758423
1156 09:26:16.758477 Set Vref, RX VrefLevel [Byte0]: 71
1157 09:26:16.758532 [Byte1]: 71
1158 09:26:16.758588
1159 09:26:16.758643 Set Vref, RX VrefLevel [Byte0]: 72
1160 09:26:16.758903 [Byte1]: 72
1161 09:26:16.758989
1162 09:26:16.759095 Set Vref, RX VrefLevel [Byte0]: 73
1163 09:26:16.759199 [Byte1]: 73
1164 09:26:16.759313
1165 09:26:16.759414 Set Vref, RX VrefLevel [Byte0]: 74
1166 09:26:16.759499 [Byte1]: 74
1167 09:26:16.759582
1168 09:26:16.759667 Set Vref, RX VrefLevel [Byte0]: 75
1169 09:26:16.759751 [Byte1]: 75
1170 09:26:16.759835
1171 09:26:16.759919 Set Vref, RX VrefLevel [Byte0]: 76
1172 09:26:16.760004 [Byte1]: 76
1173 09:26:16.760088
1174 09:26:16.760172 Set Vref, RX VrefLevel [Byte0]: 77
1175 09:26:16.760256 [Byte1]: 77
1176 09:26:16.760339
1177 09:26:16.760423 Set Vref, RX VrefLevel [Byte0]: 78
1178 09:26:16.760507 [Byte1]: 78
1179 09:26:16.760634
1180 09:26:16.760719 Set Vref, RX VrefLevel [Byte0]: 79
1181 09:26:16.760804 [Byte1]: 79
1182 09:26:16.760887
1183 09:26:16.760971 Final RX Vref Byte 0 = 62 to rank0
1184 09:26:16.761056 Final RX Vref Byte 1 = 63 to rank0
1185 09:26:16.761141 Final RX Vref Byte 0 = 62 to rank1
1186 09:26:16.761226 Final RX Vref Byte 1 = 63 to rank1==
1187 09:26:16.761310 Dram Type= 6, Freq= 0, CH_0, rank 0
1188 09:26:16.761395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 09:26:16.761510 ==
1190 09:26:16.761594 DQS Delay:
1191 09:26:16.761678 DQS0 = 0, DQS1 = 0
1192 09:26:16.761761 DQM Delay:
1193 09:26:16.761845 DQM0 = 93, DQM1 = 82
1194 09:26:16.761929 DQ Delay:
1195 09:26:16.762012 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1196 09:26:16.762097 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1197 09:26:16.762181 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1198 09:26:16.762265 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1199 09:26:16.762348
1200 09:26:16.762462
1201 09:26:16.762547 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1202 09:26:16.762632 CH0 RK0: MR19=606, MR18=3D38
1203 09:26:16.762748 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1204 09:26:16.762848
1205 09:26:16.762946 ----->DramcWriteLeveling(PI) begin...
1206 09:26:16.763031 ==
1207 09:26:16.763115 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 09:26:16.763200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 09:26:16.763284 ==
1210 09:26:16.763369 Write leveling (Byte 0): 30 => 30
1211 09:26:16.763453 Write leveling (Byte 1): 30 => 30
1212 09:26:16.763537 DramcWriteLeveling(PI) end<-----
1213 09:26:16.763621
1214 09:26:16.763704 ==
1215 09:26:16.763788 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 09:26:16.763872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 09:26:16.763956 ==
1218 09:26:16.764040 [Gating] SW mode calibration
1219 09:26:16.764126 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1220 09:26:16.764214 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1221 09:26:16.764299 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1222 09:26:16.764384 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1223 09:26:16.764469 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 09:26:16.764577 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 09:26:16.764650 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 09:26:16.764705 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 09:26:16.764760 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 09:26:16.764815 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 09:26:16.764870 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 09:26:16.764924 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 09:26:16.764979 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 09:26:16.765033 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 09:26:16.765088 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 09:26:16.765143 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 09:26:16.765199 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 09:26:16.765270 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 09:26:16.765369 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1238 09:26:16.765424 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1239 09:26:16.765479 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 09:26:16.765535 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 09:26:16.765590 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 09:26:16.765646 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 09:26:16.765701 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 09:26:16.765755 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 09:26:16.765810 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 09:26:16.765865 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1247 09:26:16.765920 0 9 8 | B1->B0 | 2e2d 3434 | 1 1 | (1 1) (1 1)
1248 09:26:16.765991 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 09:26:16.766060 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 09:26:16.766116 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 09:26:16.766188 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 09:26:16.766288 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 09:26:16.766343 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 09:26:16.766398 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
1255 09:26:16.766453 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1256 09:26:16.766508 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 09:26:16.766563 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 09:26:16.766618 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 09:26:16.766674 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 09:26:16.766729 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 09:26:16.766784 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 09:26:16.766839 0 11 4 | B1->B0 | 2727 3030 | 0 0 | (0 0) (0 0)
1263 09:26:16.766894 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1264 09:26:16.766950 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 09:26:16.767005 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 09:26:16.767060 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 09:26:16.767307 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 09:26:16.767368 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 09:26:16.767425 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 09:26:16.767481 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1271 09:26:16.767536 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1272 09:26:16.767591 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 09:26:16.767646 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 09:26:16.767702 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 09:26:16.767757 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 09:26:16.767813 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 09:26:16.767869 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 09:26:16.767924 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 09:26:16.767980 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 09:26:16.768036 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 09:26:16.768091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 09:26:16.768147 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 09:26:16.768203 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 09:26:16.768258 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 09:26:16.768329 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1286 09:26:16.768400 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1287 09:26:16.768456 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1288 09:26:16.768511 Total UI for P1: 0, mck2ui 16
1289 09:26:16.768607 best dqsien dly found for B0: ( 0, 14, 2)
1290 09:26:16.768664 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1291 09:26:16.768719 Total UI for P1: 0, mck2ui 16
1292 09:26:16.768775 best dqsien dly found for B1: ( 0, 14, 6)
1293 09:26:16.768830 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1294 09:26:16.768885 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1295 09:26:16.768940
1296 09:26:16.768995 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1297 09:26:16.769066 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1298 09:26:16.769153 [Gating] SW calibration Done
1299 09:26:16.769210 ==
1300 09:26:16.769266 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 09:26:16.769323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 09:26:16.769380 ==
1303 09:26:16.769449 RX Vref Scan: 0
1304 09:26:16.769504
1305 09:26:16.769558 RX Vref 0 -> 0, step: 1
1306 09:26:16.769613
1307 09:26:16.769668 RX Delay -130 -> 252, step: 16
1308 09:26:16.769723 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1309 09:26:16.769779 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1310 09:26:16.769835 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1311 09:26:16.769891 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1312 09:26:16.769946 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1313 09:26:16.770001 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1314 09:26:16.770056 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1315 09:26:16.770112 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1316 09:26:16.770167 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1317 09:26:16.770222 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1318 09:26:16.770278 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1319 09:26:16.770363 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1320 09:26:16.770448 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1321 09:26:16.770504 iDelay=206, Bit 13, Center 77 (-34 ~ 189) 224
1322 09:26:16.770559 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1323 09:26:16.770614 iDelay=206, Bit 15, Center 85 (-18 ~ 189) 208
1324 09:26:16.770669 ==
1325 09:26:16.770724 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 09:26:16.770779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 09:26:16.770835 ==
1328 09:26:16.770890 DQS Delay:
1329 09:26:16.770945 DQS0 = 0, DQS1 = 0
1330 09:26:16.771000 DQM Delay:
1331 09:26:16.771055 DQM0 = 87, DQM1 = 77
1332 09:26:16.771110 DQ Delay:
1333 09:26:16.771165 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1334 09:26:16.771220 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1335 09:26:16.771276 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =77
1336 09:26:16.771331 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =85
1337 09:26:16.771386
1338 09:26:16.771440
1339 09:26:16.771495 ==
1340 09:26:16.771550 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 09:26:16.771605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 09:26:16.771661 ==
1343 09:26:16.771716
1344 09:26:16.771771
1345 09:26:16.771825 TX Vref Scan disable
1346 09:26:16.771880 == TX Byte 0 ==
1347 09:26:16.771936 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1348 09:26:16.771991 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1349 09:26:16.772047 == TX Byte 1 ==
1350 09:26:16.772102 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1351 09:26:16.772157 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1352 09:26:16.772212 ==
1353 09:26:16.772267 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 09:26:16.772322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 09:26:16.772377 ==
1356 09:26:16.772433 TX Vref=22, minBit 11, minWin=26, winSum=444
1357 09:26:16.772489 TX Vref=24, minBit 8, minWin=27, winSum=450
1358 09:26:16.772545 TX Vref=26, minBit 8, minWin=27, winSum=454
1359 09:26:16.772640 TX Vref=28, minBit 8, minWin=27, winSum=456
1360 09:26:16.772695 TX Vref=30, minBit 8, minWin=27, winSum=456
1361 09:26:16.772766 TX Vref=32, minBit 8, minWin=28, winSum=457
1362 09:26:16.772835 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 32
1363 09:26:16.772888
1364 09:26:16.772941 Final TX Range 1 Vref 32
1365 09:26:16.772995
1366 09:26:16.773048 ==
1367 09:26:16.773101 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 09:26:16.773154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 09:26:16.773225 ==
1370 09:26:16.773308
1371 09:26:16.773362
1372 09:26:16.773415 TX Vref Scan disable
1373 09:26:16.773469 == TX Byte 0 ==
1374 09:26:16.773524 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1375 09:26:16.773591 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1376 09:26:16.773645 == TX Byte 1 ==
1377 09:26:16.773697 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1378 09:26:16.773751 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1379 09:26:16.773804
1380 09:26:16.773858 [DATLAT]
1381 09:26:16.773911 Freq=800, CH0 RK1
1382 09:26:16.773964
1383 09:26:16.774016 DATLAT Default: 0xa
1384 09:26:16.774069 0, 0xFFFF, sum = 0
1385 09:26:16.774123 1, 0xFFFF, sum = 0
1386 09:26:16.774193 2, 0xFFFF, sum = 0
1387 09:26:16.774261 3, 0xFFFF, sum = 0
1388 09:26:16.774360 4, 0xFFFF, sum = 0
1389 09:26:16.774430 5, 0xFFFF, sum = 0
1390 09:26:16.774485 6, 0xFFFF, sum = 0
1391 09:26:16.774540 7, 0xFFFF, sum = 0
1392 09:26:16.774594 8, 0xFFFF, sum = 0
1393 09:26:16.774843 9, 0x0, sum = 1
1394 09:26:16.774905 10, 0x0, sum = 2
1395 09:26:16.774961 11, 0x0, sum = 3
1396 09:26:16.775017 12, 0x0, sum = 4
1397 09:26:16.775085 best_step = 10
1398 09:26:16.775137
1399 09:26:16.775190 ==
1400 09:26:16.775243 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 09:26:16.775297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 09:26:16.775350 ==
1403 09:26:16.775403 RX Vref Scan: 0
1404 09:26:16.775456
1405 09:26:16.775510 RX Vref 0 -> 0, step: 1
1406 09:26:16.775563
1407 09:26:16.775616 RX Delay -95 -> 252, step: 8
1408 09:26:16.775669 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1409 09:26:16.775722 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1410 09:26:16.775776 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1411 09:26:16.775829 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1412 09:26:16.775912 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1413 09:26:16.775981 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1414 09:26:16.776049 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1415 09:26:16.776101 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1416 09:26:16.776154 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1417 09:26:16.776207 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1418 09:26:16.776261 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1419 09:26:16.776314 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1420 09:26:16.776367 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1421 09:26:16.776420 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1422 09:26:16.776474 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1423 09:26:16.776527 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1424 09:26:16.776626 ==
1425 09:26:16.776680 Dram Type= 6, Freq= 0, CH_0, rank 1
1426 09:26:16.776733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 09:26:16.776786 ==
1428 09:26:16.776839 DQS Delay:
1429 09:26:16.776892 DQS0 = 0, DQS1 = 0
1430 09:26:16.776961 DQM Delay:
1431 09:26:16.777045 DQM0 = 90, DQM1 = 80
1432 09:26:16.777142 DQ Delay:
1433 09:26:16.777224 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1434 09:26:16.777277 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1435 09:26:16.777330 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1436 09:26:16.777383 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =84
1437 09:26:16.777436
1438 09:26:16.777489
1439 09:26:16.777542 [DQSOSCAuto] RK1, (LSB)MR18= 0x4822, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1440 09:26:16.777596 CH0 RK1: MR19=606, MR18=4822
1441 09:26:16.777650 CH0_RK1: MR19=0x606, MR18=0x4822, DQSOSC=391, MR23=63, INC=96, DEC=64
1442 09:26:16.777703 [RxdqsGatingPostProcess] freq 800
1443 09:26:16.777757 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1444 09:26:16.777811 Pre-setting of DQS Precalculation
1445 09:26:16.777864 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1446 09:26:16.777917 ==
1447 09:26:16.777970 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 09:26:16.778024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 09:26:16.778078 ==
1450 09:26:16.778131 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 09:26:16.778184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 09:26:16.778238 [CA 0] Center 36 (6~67) winsize 62
1453 09:26:16.778291 [CA 1] Center 36 (6~67) winsize 62
1454 09:26:16.778344 [CA 2] Center 34 (4~65) winsize 62
1455 09:26:16.778397 [CA 3] Center 34 (4~65) winsize 62
1456 09:26:16.778454 [CA 4] Center 34 (4~65) winsize 62
1457 09:26:16.778558 [CA 5] Center 34 (3~65) winsize 63
1458 09:26:16.778621
1459 09:26:16.778675 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1460 09:26:16.778758
1461 09:26:16.778814 [CATrainingPosCal] consider 1 rank data
1462 09:26:16.778867 u2DelayCellTimex100 = 270/100 ps
1463 09:26:16.778920 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 09:26:16.779007 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1465 09:26:16.779060 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 09:26:16.779113 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 09:26:16.779168 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 09:26:16.779221 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1469 09:26:16.779303
1470 09:26:16.779357 CA PerBit enable=1, Macro0, CA PI delay=34
1471 09:26:16.779410
1472 09:26:16.779462 [CBTSetCACLKResult] CA Dly = 34
1473 09:26:16.779516 CS Dly: 5 (0~36)
1474 09:26:16.779568 ==
1475 09:26:16.779620 Dram Type= 6, Freq= 0, CH_1, rank 1
1476 09:26:16.779674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 09:26:16.779728 ==
1478 09:26:16.779781 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1479 09:26:16.779835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1480 09:26:16.779889 [CA 0] Center 36 (6~67) winsize 62
1481 09:26:16.779942 [CA 1] Center 37 (6~68) winsize 63
1482 09:26:16.779996 [CA 2] Center 35 (4~66) winsize 63
1483 09:26:16.780049 [CA 3] Center 34 (4~65) winsize 62
1484 09:26:16.780102 [CA 4] Center 34 (4~65) winsize 62
1485 09:26:16.780155 [CA 5] Center 33 (3~64) winsize 62
1486 09:26:16.780208
1487 09:26:16.780260 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1488 09:26:16.780313
1489 09:26:16.780366 [CATrainingPosCal] consider 2 rank data
1490 09:26:16.780419 u2DelayCellTimex100 = 270/100 ps
1491 09:26:16.780473 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1492 09:26:16.780525 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1493 09:26:16.780619 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1494 09:26:16.780673 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1495 09:26:16.780726 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1496 09:26:16.780779 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1497 09:26:16.780861
1498 09:26:16.780960 CA PerBit enable=1, Macro0, CA PI delay=33
1499 09:26:16.781027
1500 09:26:16.781080 [CBTSetCACLKResult] CA Dly = 33
1501 09:26:16.781133 CS Dly: 6 (0~38)
1502 09:26:16.781186
1503 09:26:16.781239 ----->DramcWriteLeveling(PI) begin...
1504 09:26:16.781293 ==
1505 09:26:16.781346 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 09:26:16.781400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 09:26:16.781454 ==
1508 09:26:16.781507 Write leveling (Byte 0): 25 => 25
1509 09:26:16.781560 Write leveling (Byte 1): 32 => 32
1510 09:26:16.781614 DramcWriteLeveling(PI) end<-----
1511 09:26:16.781667
1512 09:26:16.781750 ==
1513 09:26:16.781803 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 09:26:16.781856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 09:26:16.781909 ==
1516 09:26:16.781961 [Gating] SW mode calibration
1517 09:26:16.782015 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1518 09:26:16.782069 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1519 09:26:16.782122 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1520 09:26:16.782378 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1521 09:26:16.782497 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1522 09:26:16.782554 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 09:26:16.782609 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 09:26:16.782693 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 09:26:16.782760 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 09:26:16.782813 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 09:26:16.782887 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 09:26:16.782956 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 09:26:16.783010 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 09:26:16.783063 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 09:26:16.783116 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 09:26:16.783169 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 09:26:16.783222 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 09:26:16.783275 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 09:26:16.783328 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1536 09:26:16.783381 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1537 09:26:16.783434 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 09:26:16.783487 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 09:26:16.783540 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 09:26:16.783593 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 09:26:16.783646 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 09:26:16.783699 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 09:26:16.783752 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 09:26:16.783805 0 9 4 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
1545 09:26:16.783858 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1546 09:26:16.783910 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 09:26:16.783963 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 09:26:16.784016 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 09:26:16.784069 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 09:26:16.784121 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 09:26:16.784174 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1552 09:26:16.784227 0 10 4 | B1->B0 | 2f2f 2b2b | 1 0 | (1 1) (1 0)
1553 09:26:16.784280 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 09:26:16.784333 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 09:26:16.784387 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 09:26:16.784440 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 09:26:16.784527 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 09:26:16.784644 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 09:26:16.784700 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1560 09:26:16.784754 0 11 4 | B1->B0 | 3434 3a3a | 1 0 | (1 1) (0 0)
1561 09:26:16.784807 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 09:26:16.784860 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 09:26:16.784913 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 09:26:16.784966 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 09:26:16.785019 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 09:26:16.785073 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 09:26:16.785126 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1568 09:26:16.785179 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1569 09:26:16.785233 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 09:26:16.785286 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 09:26:16.785339 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 09:26:16.785392 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 09:26:16.785446 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 09:26:16.785498 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 09:26:16.785551 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 09:26:16.785603 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 09:26:16.785657 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 09:26:16.785710 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 09:26:16.785763 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 09:26:16.785816 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 09:26:16.785869 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 09:26:16.785922 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 09:26:16.785975 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1584 09:26:16.786028 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1585 09:26:16.786082 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1586 09:26:16.786135 Total UI for P1: 0, mck2ui 16
1587 09:26:16.786188 best dqsien dly found for B0: ( 0, 14, 2)
1588 09:26:16.786242 Total UI for P1: 0, mck2ui 16
1589 09:26:16.786296 best dqsien dly found for B1: ( 0, 14, 6)
1590 09:26:16.786350 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1591 09:26:16.786403 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1592 09:26:16.786467
1593 09:26:16.786554 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1594 09:26:16.786613 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1595 09:26:16.786667 [Gating] SW calibration Done
1596 09:26:16.786719 ==
1597 09:26:16.786773 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 09:26:16.786826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 09:26:16.786881 ==
1600 09:26:16.786935 RX Vref Scan: 0
1601 09:26:16.786988
1602 09:26:16.787042 RX Vref 0 -> 0, step: 1
1603 09:26:16.787094
1604 09:26:16.787147 RX Delay -130 -> 252, step: 16
1605 09:26:16.787200 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1606 09:26:16.787254 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1607 09:26:16.787306 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1608 09:26:16.787360 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1609 09:26:16.787608 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1610 09:26:16.787667 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1611 09:26:16.787722 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1612 09:26:16.787775 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1613 09:26:16.787828 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1614 09:26:16.787882 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1615 09:26:16.787935 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1616 09:26:16.787989 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1617 09:26:16.788042 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1618 09:26:16.788096 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1619 09:26:16.788149 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1620 09:26:16.788202 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1621 09:26:16.788255 ==
1622 09:26:16.788309 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 09:26:16.788362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 09:26:16.788416 ==
1625 09:26:16.788469 DQS Delay:
1626 09:26:16.788539 DQS0 = 0, DQS1 = 0
1627 09:26:16.788619 DQM Delay:
1628 09:26:16.788673 DQM0 = 90, DQM1 = 85
1629 09:26:16.788727 DQ Delay:
1630 09:26:16.788781 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1631 09:26:16.788834 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =93
1632 09:26:16.788887 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1633 09:26:16.788940 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1634 09:26:16.788993
1635 09:26:16.789045
1636 09:26:16.789097 ==
1637 09:26:16.789151 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 09:26:16.789204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 09:26:16.789258 ==
1640 09:26:16.789312
1641 09:26:16.789364
1642 09:26:16.789473 TX Vref Scan disable
1643 09:26:16.789557 == TX Byte 0 ==
1644 09:26:16.789610 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1645 09:26:16.789663 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1646 09:26:16.789716 == TX Byte 1 ==
1647 09:26:16.789769 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1648 09:26:16.789821 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1649 09:26:16.789875 ==
1650 09:26:16.789928 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 09:26:16.789981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 09:26:16.790034 ==
1653 09:26:16.790087 TX Vref=22, minBit 8, minWin=27, winSum=450
1654 09:26:16.790140 TX Vref=24, minBit 15, minWin=27, winSum=454
1655 09:26:16.790194 TX Vref=26, minBit 15, minWin=27, winSum=455
1656 09:26:16.790248 TX Vref=28, minBit 8, minWin=27, winSum=457
1657 09:26:16.790301 TX Vref=30, minBit 8, minWin=28, winSum=461
1658 09:26:16.790354 TX Vref=32, minBit 12, minWin=27, winSum=457
1659 09:26:16.790409 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
1660 09:26:16.790462
1661 09:26:16.790517 Final TX Range 1 Vref 30
1662 09:26:16.790570
1663 09:26:16.790623 ==
1664 09:26:16.790676 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 09:26:16.790745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 09:26:16.790799 ==
1667 09:26:16.790852
1668 09:26:16.790913
1669 09:26:16.790967 TX Vref Scan disable
1670 09:26:16.791022 == TX Byte 0 ==
1671 09:26:16.791083 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1672 09:26:16.791138 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1673 09:26:16.791191 == TX Byte 1 ==
1674 09:26:16.791243 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1675 09:26:16.791309 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1676 09:26:16.791362
1677 09:26:16.791415 [DATLAT]
1678 09:26:16.791477 Freq=800, CH1 RK0
1679 09:26:16.791530
1680 09:26:16.791583 DATLAT Default: 0xa
1681 09:26:16.791639 0, 0xFFFF, sum = 0
1682 09:26:16.791694 1, 0xFFFF, sum = 0
1683 09:26:16.791748 2, 0xFFFF, sum = 0
1684 09:26:16.791805 3, 0xFFFF, sum = 0
1685 09:26:16.791860 4, 0xFFFF, sum = 0
1686 09:26:16.791914 5, 0xFFFF, sum = 0
1687 09:26:16.791968 6, 0xFFFF, sum = 0
1688 09:26:16.792023 7, 0xFFFF, sum = 0
1689 09:26:16.792078 8, 0xFFFF, sum = 0
1690 09:26:16.792132 9, 0x0, sum = 1
1691 09:26:16.792186 10, 0x0, sum = 2
1692 09:26:16.792240 11, 0x0, sum = 3
1693 09:26:16.792294 12, 0x0, sum = 4
1694 09:26:16.792348 best_step = 10
1695 09:26:16.792401
1696 09:26:16.792454 ==
1697 09:26:16.792507 Dram Type= 6, Freq= 0, CH_1, rank 0
1698 09:26:16.792602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1699 09:26:16.792672 ==
1700 09:26:16.792772 RX Vref Scan: 1
1701 09:26:16.792857
1702 09:26:16.792911 Set Vref Range= 32 -> 127
1703 09:26:16.792966
1704 09:26:16.793020 RX Vref 32 -> 127, step: 1
1705 09:26:16.793074
1706 09:26:16.793141 RX Delay -95 -> 252, step: 8
1707 09:26:16.793194
1708 09:26:16.793247 Set Vref, RX VrefLevel [Byte0]: 32
1709 09:26:16.793301 [Byte1]: 32
1710 09:26:16.793355
1711 09:26:16.793409 Set Vref, RX VrefLevel [Byte0]: 33
1712 09:26:16.793462 [Byte1]: 33
1713 09:26:16.793515
1714 09:26:16.793568 Set Vref, RX VrefLevel [Byte0]: 34
1715 09:26:16.793622 [Byte1]: 34
1716 09:26:16.793675
1717 09:26:16.793727 Set Vref, RX VrefLevel [Byte0]: 35
1718 09:26:16.793780 [Byte1]: 35
1719 09:26:16.793833
1720 09:26:16.793886 Set Vref, RX VrefLevel [Byte0]: 36
1721 09:26:16.793939 [Byte1]: 36
1722 09:26:16.793992
1723 09:26:16.794045 Set Vref, RX VrefLevel [Byte0]: 37
1724 09:26:16.794098 [Byte1]: 37
1725 09:26:16.794151
1726 09:26:16.794204 Set Vref, RX VrefLevel [Byte0]: 38
1727 09:26:16.794257 [Byte1]: 38
1728 09:26:16.794310
1729 09:26:16.794364 Set Vref, RX VrefLevel [Byte0]: 39
1730 09:26:16.794417 [Byte1]: 39
1731 09:26:16.794470
1732 09:26:16.794523 Set Vref, RX VrefLevel [Byte0]: 40
1733 09:26:16.794577 [Byte1]: 40
1734 09:26:16.794630
1735 09:26:16.794683 Set Vref, RX VrefLevel [Byte0]: 41
1736 09:26:16.794736 [Byte1]: 41
1737 09:26:16.794789
1738 09:26:16.794841 Set Vref, RX VrefLevel [Byte0]: 42
1739 09:26:16.794894 [Byte1]: 42
1740 09:26:16.794948
1741 09:26:16.795001 Set Vref, RX VrefLevel [Byte0]: 43
1742 09:26:16.795054 [Byte1]: 43
1743 09:26:16.795107
1744 09:26:16.795160 Set Vref, RX VrefLevel [Byte0]: 44
1745 09:26:16.795213 [Byte1]: 44
1746 09:26:16.795265
1747 09:26:16.795318 Set Vref, RX VrefLevel [Byte0]: 45
1748 09:26:16.795370 [Byte1]: 45
1749 09:26:16.795424
1750 09:26:16.795477 Set Vref, RX VrefLevel [Byte0]: 46
1751 09:26:16.795530 [Byte1]: 46
1752 09:26:16.795582
1753 09:26:16.795635 Set Vref, RX VrefLevel [Byte0]: 47
1754 09:26:16.795688 [Byte1]: 47
1755 09:26:16.795741
1756 09:26:16.795794 Set Vref, RX VrefLevel [Byte0]: 48
1757 09:26:16.795875 [Byte1]: 48
1758 09:26:16.795929
1759 09:26:16.795982 Set Vref, RX VrefLevel [Byte0]: 49
1760 09:26:16.796035 [Byte1]: 49
1761 09:26:16.796088
1762 09:26:16.796140 Set Vref, RX VrefLevel [Byte0]: 50
1763 09:26:16.796194 [Byte1]: 50
1764 09:26:16.796247
1765 09:26:16.796299 Set Vref, RX VrefLevel [Byte0]: 51
1766 09:26:16.796352 [Byte1]: 51
1767 09:26:16.796405
1768 09:26:16.796665 Set Vref, RX VrefLevel [Byte0]: 52
1769 09:26:16.796725 [Byte1]: 52
1770 09:26:16.796780
1771 09:26:16.796833 Set Vref, RX VrefLevel [Byte0]: 53
1772 09:26:16.796887 [Byte1]: 53
1773 09:26:16.796940
1774 09:26:16.797010 Set Vref, RX VrefLevel [Byte0]: 54
1775 09:26:16.797077 [Byte1]: 54
1776 09:26:16.797130
1777 09:26:16.797182 Set Vref, RX VrefLevel [Byte0]: 55
1778 09:26:16.797235 [Byte1]: 55
1779 09:26:16.797289
1780 09:26:16.797342 Set Vref, RX VrefLevel [Byte0]: 56
1781 09:26:16.797394 [Byte1]: 56
1782 09:26:16.797447
1783 09:26:16.797499 Set Vref, RX VrefLevel [Byte0]: 57
1784 09:26:16.797552 [Byte1]: 57
1785 09:26:16.797606
1786 09:26:16.797659 Set Vref, RX VrefLevel [Byte0]: 58
1787 09:26:16.797712 [Byte1]: 58
1788 09:26:16.797765
1789 09:26:16.797819 Set Vref, RX VrefLevel [Byte0]: 59
1790 09:26:16.797872 [Byte1]: 59
1791 09:26:16.797925
1792 09:26:16.797978 Set Vref, RX VrefLevel [Byte0]: 60
1793 09:26:16.798031 [Byte1]: 60
1794 09:26:16.798084
1795 09:26:16.798136 Set Vref, RX VrefLevel [Byte0]: 61
1796 09:26:16.798190 [Byte1]: 61
1797 09:26:16.798243
1798 09:26:16.798312 Set Vref, RX VrefLevel [Byte0]: 62
1799 09:26:16.798381 [Byte1]: 62
1800 09:26:16.798450
1801 09:26:16.798503 Set Vref, RX VrefLevel [Byte0]: 63
1802 09:26:16.798556 [Byte1]: 63
1803 09:26:16.798610
1804 09:26:16.798662 Set Vref, RX VrefLevel [Byte0]: 64
1805 09:26:16.798715 [Byte1]: 64
1806 09:26:16.798769
1807 09:26:16.798822 Set Vref, RX VrefLevel [Byte0]: 65
1808 09:26:16.798875 [Byte1]: 65
1809 09:26:16.798944
1810 09:26:16.799027 Set Vref, RX VrefLevel [Byte0]: 66
1811 09:26:16.799082 [Byte1]: 66
1812 09:26:16.799180
1813 09:26:16.799294 Set Vref, RX VrefLevel [Byte0]: 67
1814 09:26:16.799407 [Byte1]: 67
1815 09:26:16.799460
1816 09:26:16.799512 Set Vref, RX VrefLevel [Byte0]: 68
1817 09:26:16.799565 [Byte1]: 68
1818 09:26:16.799618
1819 09:26:16.799672 Set Vref, RX VrefLevel [Byte0]: 69
1820 09:26:16.799725 [Byte1]: 69
1821 09:26:16.799778
1822 09:26:16.799830 Set Vref, RX VrefLevel [Byte0]: 70
1823 09:26:16.799882 [Byte1]: 70
1824 09:26:16.799935
1825 09:26:16.799988 Set Vref, RX VrefLevel [Byte0]: 71
1826 09:26:16.800040 [Byte1]: 71
1827 09:26:16.800093
1828 09:26:16.800146 Set Vref, RX VrefLevel [Byte0]: 72
1829 09:26:16.800199 [Byte1]: 72
1830 09:26:16.800252
1831 09:26:16.800305 Set Vref, RX VrefLevel [Byte0]: 73
1832 09:26:16.800359 [Byte1]: 73
1833 09:26:16.800411
1834 09:26:16.800464 Set Vref, RX VrefLevel [Byte0]: 74
1835 09:26:16.800517 [Byte1]: 74
1836 09:26:16.800606
1837 09:26:16.800675 Set Vref, RX VrefLevel [Byte0]: 75
1838 09:26:16.800728 [Byte1]: 75
1839 09:26:16.800781
1840 09:26:16.800835 Set Vref, RX VrefLevel [Byte0]: 76
1841 09:26:16.800889 [Byte1]: 76
1842 09:26:16.800942
1843 09:26:16.800995 Set Vref, RX VrefLevel [Byte0]: 77
1844 09:26:16.801048 [Byte1]: 77
1845 09:26:16.801102
1846 09:26:16.801155 Set Vref, RX VrefLevel [Byte0]: 78
1847 09:26:16.801207 [Byte1]: 78
1848 09:26:16.801260
1849 09:26:16.801313 Final RX Vref Byte 0 = 51 to rank0
1850 09:26:16.801367 Final RX Vref Byte 1 = 59 to rank0
1851 09:26:16.801421 Final RX Vref Byte 0 = 51 to rank1
1852 09:26:16.801474 Final RX Vref Byte 1 = 59 to rank1==
1853 09:26:16.801527 Dram Type= 6, Freq= 0, CH_1, rank 0
1854 09:26:16.801581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 09:26:16.801635 ==
1856 09:26:16.801688 DQS Delay:
1857 09:26:16.801741 DQS0 = 0, DQS1 = 0
1858 09:26:16.801794 DQM Delay:
1859 09:26:16.801847 DQM0 = 92, DQM1 = 81
1860 09:26:16.801900 DQ Delay:
1861 09:26:16.801953 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1862 09:26:16.802006 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1863 09:26:16.802060 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1864 09:26:16.802113 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1865 09:26:16.802165
1866 09:26:16.802218
1867 09:26:16.802271 [DQSOSCAuto] RK0, (LSB)MR18= 0x3451, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1868 09:26:16.802325 CH1 RK0: MR19=606, MR18=3451
1869 09:26:16.802379 CH1_RK0: MR19=0x606, MR18=0x3451, DQSOSC=389, MR23=63, INC=97, DEC=65
1870 09:26:16.802433
1871 09:26:16.802486 ----->DramcWriteLeveling(PI) begin...
1872 09:26:16.802578 ==
1873 09:26:16.802634 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 09:26:16.802688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1875 09:26:16.802741 ==
1876 09:26:16.802794 Write leveling (Byte 0): 27 => 27
1877 09:26:16.802859 Write leveling (Byte 1): 27 => 27
1878 09:26:16.802913 DramcWriteLeveling(PI) end<-----
1879 09:26:16.802966
1880 09:26:16.803032 ==
1881 09:26:16.803085 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 09:26:16.803139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 09:26:16.803206 ==
1884 09:26:16.803260 [Gating] SW mode calibration
1885 09:26:16.803313 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1886 09:26:16.803376 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1887 09:26:16.803432 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1888 09:26:16.803485 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1889 09:26:16.803539 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 09:26:16.803601 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 09:26:16.803655 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 09:26:16.803709 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 09:26:16.803766 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 09:26:16.803819 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 09:26:16.803872 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 09:26:16.803927 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 09:26:16.803980 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 09:26:16.804034 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 09:26:16.804087 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 09:26:16.804141 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 09:26:16.804195 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 09:26:16.804247 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 09:26:16.804301 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 09:26:16.804565 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1905 09:26:16.804631 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1906 09:26:16.804687 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 09:26:16.804742 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 09:26:16.804797 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 09:26:16.804852 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 09:26:16.804907 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 09:26:16.804962 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 09:26:16.805017 0 9 4 | B1->B0 | 2525 2424 | 1 0 | (1 1) (0 0)
1913 09:26:16.805071 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 09:26:16.805126 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 09:26:16.805181 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 09:26:16.805236 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 09:26:16.805290 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 09:26:16.805345 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 09:26:16.805400 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1920 09:26:16.805455 0 10 4 | B1->B0 | 2b2b 3131 | 0 1 | (0 0) (0 1)
1921 09:26:16.805509 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 09:26:16.805563 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 09:26:16.805618 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 09:26:16.805673 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 09:26:16.805727 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 09:26:16.805782 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 09:26:16.805836 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1928 09:26:16.805891 0 11 4 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 0)
1929 09:26:16.805946 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 09:26:16.806000 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 09:26:16.806067 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 09:26:16.806120 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 09:26:16.806173 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 09:26:16.806225 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 09:26:16.806278 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 09:26:16.806331 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1937 09:26:16.806385 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 09:26:16.806438 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 09:26:16.806491 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 09:26:16.806545 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 09:26:16.806598 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 09:26:16.806651 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 09:26:16.806704 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 09:26:16.806757 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 09:26:16.806810 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 09:26:16.806863 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 09:26:16.806917 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 09:26:16.806987 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 09:26:16.807043 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 09:26:16.807098 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 09:26:16.807165 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 09:26:16.807278 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1953 09:26:16.807375 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1954 09:26:16.807431 Total UI for P1: 0, mck2ui 16
1955 09:26:16.807485 best dqsien dly found for B0: ( 0, 14, 4)
1956 09:26:16.807539 Total UI for P1: 0, mck2ui 16
1957 09:26:16.807593 best dqsien dly found for B1: ( 0, 14, 4)
1958 09:26:16.807647 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1959 09:26:16.807701 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1960 09:26:16.807754
1961 09:26:16.807807 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1962 09:26:16.807860 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1963 09:26:16.807913 [Gating] SW calibration Done
1964 09:26:16.807967 ==
1965 09:26:16.808020 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 09:26:16.808073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 09:26:16.808127 ==
1968 09:26:16.808180 RX Vref Scan: 0
1969 09:26:16.808233
1970 09:26:16.808286 RX Vref 0 -> 0, step: 1
1971 09:26:16.808339
1972 09:26:16.808392 RX Delay -130 -> 252, step: 16
1973 09:26:16.808445 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1974 09:26:16.808515 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1975 09:26:16.808598 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1976 09:26:16.808653 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1977 09:26:16.808707 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1978 09:26:16.808760 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1979 09:26:16.808813 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1980 09:26:16.808867 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1981 09:26:16.808920 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1982 09:26:16.808974 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1983 09:26:16.809026 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1984 09:26:16.809080 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1985 09:26:16.809134 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1986 09:26:16.809187 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1987 09:26:17.006564 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1988 09:26:17.006720 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1989 09:26:17.006823 ==
1990 09:26:17.006918 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 09:26:17.006990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 09:26:17.007052 ==
1993 09:26:17.007111 DQS Delay:
1994 09:26:17.007168 DQS0 = 0, DQS1 = 0
1995 09:26:17.007225 DQM Delay:
1996 09:26:17.007281 DQM0 = 90, DQM1 = 85
1997 09:26:17.007338 DQ Delay:
1998 09:26:17.007394 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1999 09:26:17.007451 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
2000 09:26:17.007507 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
2001 09:26:17.007790 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
2002 09:26:17.007859
2003 09:26:17.007917
2004 09:26:17.007972 ==
2005 09:26:17.008028 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 09:26:17.008083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 09:26:17.008140 ==
2008 09:26:17.008194
2009 09:26:17.008250
2010 09:26:17.008304 TX Vref Scan disable
2011 09:26:17.008358 == TX Byte 0 ==
2012 09:26:17.008413 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2013 09:26:17.008469 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2014 09:26:17.008523 == TX Byte 1 ==
2015 09:26:17.008590 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2016 09:26:17.008647 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2017 09:26:17.008702 ==
2018 09:26:17.008756 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 09:26:17.008811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 09:26:17.008867 ==
2021 09:26:17.008923 TX Vref=22, minBit 0, minWin=28, winSum=456
2022 09:26:17.008978 TX Vref=24, minBit 7, minWin=28, winSum=459
2023 09:26:17.009033 TX Vref=26, minBit 15, minWin=27, winSum=458
2024 09:26:17.009088 TX Vref=28, minBit 13, minWin=28, winSum=462
2025 09:26:17.009142 TX Vref=30, minBit 8, minWin=28, winSum=461
2026 09:26:17.009197 TX Vref=32, minBit 8, minWin=28, winSum=459
2027 09:26:17.009252 [TxChooseVref] Worse bit 13, Min win 28, Win sum 462, Final Vref 28
2028 09:26:17.009307
2029 09:26:17.009361 Final TX Range 1 Vref 28
2030 09:26:17.009416
2031 09:26:17.009470 ==
2032 09:26:17.009524 Dram Type= 6, Freq= 0, CH_1, rank 1
2033 09:26:17.009579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2034 09:26:17.009634 ==
2035 09:26:17.009689
2036 09:26:17.009742
2037 09:26:17.009796 TX Vref Scan disable
2038 09:26:17.009851 == TX Byte 0 ==
2039 09:26:17.009906 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2040 09:26:17.009961 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2041 09:26:17.010016 == TX Byte 1 ==
2042 09:26:17.010070 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2043 09:26:17.010125 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2044 09:26:17.010179
2045 09:26:17.010233 [DATLAT]
2046 09:26:17.010287 Freq=800, CH1 RK1
2047 09:26:17.010342
2048 09:26:17.010396 DATLAT Default: 0xa
2049 09:26:17.010450 0, 0xFFFF, sum = 0
2050 09:26:17.010506 1, 0xFFFF, sum = 0
2051 09:26:17.010561 2, 0xFFFF, sum = 0
2052 09:26:17.010616 3, 0xFFFF, sum = 0
2053 09:26:17.010671 4, 0xFFFF, sum = 0
2054 09:26:17.010726 5, 0xFFFF, sum = 0
2055 09:26:17.010781 6, 0xFFFF, sum = 0
2056 09:26:17.010836 7, 0xFFFF, sum = 0
2057 09:26:17.010891 8, 0xFFFF, sum = 0
2058 09:26:17.010947 9, 0x0, sum = 1
2059 09:26:17.011002 10, 0x0, sum = 2
2060 09:26:17.011058 11, 0x0, sum = 3
2061 09:26:17.011116 12, 0x0, sum = 4
2062 09:26:17.011209 best_step = 10
2063 09:26:17.011297
2064 09:26:17.011380 ==
2065 09:26:17.011455 Dram Type= 6, Freq= 0, CH_1, rank 1
2066 09:26:17.011513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2067 09:26:17.011569 ==
2068 09:26:17.011624 RX Vref Scan: 0
2069 09:26:17.011680
2070 09:26:17.011733 RX Vref 0 -> 0, step: 1
2071 09:26:17.011787
2072 09:26:17.011841 RX Delay -95 -> 252, step: 8
2073 09:26:17.011896 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2074 09:26:17.011951 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2075 09:26:17.012006 iDelay=209, Bit 2, Center 76 (-31 ~ 184) 216
2076 09:26:17.012066 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2077 09:26:17.012121 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2078 09:26:17.012176 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2079 09:26:17.012230 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2080 09:26:17.012285 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2081 09:26:17.012348 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2082 09:26:17.012405 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2083 09:26:17.012462 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2084 09:26:17.012519 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2085 09:26:17.012585 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2086 09:26:17.012643 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2087 09:26:17.012699 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2088 09:26:17.012755 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2089 09:26:17.012810 ==
2090 09:26:17.012866 Dram Type= 6, Freq= 0, CH_1, rank 1
2091 09:26:17.012923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2092 09:26:17.012980 ==
2093 09:26:17.013036 DQS Delay:
2094 09:26:17.013092 DQS0 = 0, DQS1 = 0
2095 09:26:17.013148 DQM Delay:
2096 09:26:17.013204 DQM0 = 90, DQM1 = 83
2097 09:26:17.013261 DQ Delay:
2098 09:26:17.013318 DQ0 =92, DQ1 =88, DQ2 =76, DQ3 =88
2099 09:26:17.013375 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2100 09:26:17.013431 DQ8 =68, DQ9 =76, DQ10 =80, DQ11 =80
2101 09:26:17.013488 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2102 09:26:17.013544
2103 09:26:17.013601
2104 09:26:17.013656 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2105 09:26:17.013714 CH1 RK1: MR19=606, MR18=3C13
2106 09:26:17.013771 CH1_RK1: MR19=0x606, MR18=0x3C13, DQSOSC=394, MR23=63, INC=95, DEC=63
2107 09:26:17.013828 [RxdqsGatingPostProcess] freq 800
2108 09:26:17.013885 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2109 09:26:17.013942 Pre-setting of DQS Precalculation
2110 09:26:17.013999 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2111 09:26:17.014056 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2112 09:26:17.014114 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2113 09:26:17.014171
2114 09:26:17.014227
2115 09:26:17.014283 [Calibration Summary] 1600 Mbps
2116 09:26:17.014339 CH 0, Rank 0
2117 09:26:17.014396 SW Impedance : PASS
2118 09:26:17.014452 DUTY Scan : NO K
2119 09:26:17.014509 ZQ Calibration : PASS
2120 09:26:17.014569 Jitter Meter : NO K
2121 09:26:17.014626 CBT Training : PASS
2122 09:26:17.014682 Write leveling : PASS
2123 09:26:17.014739 RX DQS gating : PASS
2124 09:26:17.014795 RX DQ/DQS(RDDQC) : PASS
2125 09:26:17.014851 TX DQ/DQS : PASS
2126 09:26:17.014910 RX DATLAT : PASS
2127 09:26:17.015012 RX DQ/DQS(Engine): PASS
2128 09:26:17.015080 TX OE : NO K
2129 09:26:17.015139 All Pass.
2130 09:26:17.015196
2131 09:26:17.015252 CH 0, Rank 1
2132 09:26:17.015309 SW Impedance : PASS
2133 09:26:17.015365 DUTY Scan : NO K
2134 09:26:17.015421 ZQ Calibration : PASS
2135 09:26:17.015478 Jitter Meter : NO K
2136 09:26:17.015535 CBT Training : PASS
2137 09:26:17.015594 Write leveling : PASS
2138 09:26:17.015687 RX DQS gating : PASS
2139 09:26:17.015777 RX DQ/DQS(RDDQC) : PASS
2140 09:26:17.015863 TX DQ/DQS : PASS
2141 09:26:17.015942 RX DATLAT : PASS
2142 09:26:17.016001 RX DQ/DQS(Engine): PASS
2143 09:26:17.016059 TX OE : NO K
2144 09:26:17.016116 All Pass.
2145 09:26:17.016173
2146 09:26:17.016229 CH 1, Rank 0
2147 09:26:17.016286 SW Impedance : PASS
2148 09:26:17.016343 DUTY Scan : NO K
2149 09:26:17.016400 ZQ Calibration : PASS
2150 09:26:17.016655 Jitter Meter : NO K
2151 09:26:17.016720 CBT Training : PASS
2152 09:26:17.016778 Write leveling : PASS
2153 09:26:17.016835 RX DQS gating : PASS
2154 09:26:17.016891 RX DQ/DQS(RDDQC) : PASS
2155 09:26:17.016946 TX DQ/DQS : PASS
2156 09:26:17.017002 RX DATLAT : PASS
2157 09:26:17.017059 RX DQ/DQS(Engine): PASS
2158 09:26:17.017114 TX OE : NO K
2159 09:26:17.017171 All Pass.
2160 09:26:17.017227
2161 09:26:17.017283 CH 1, Rank 1
2162 09:26:17.017338 SW Impedance : PASS
2163 09:26:17.017394 DUTY Scan : NO K
2164 09:26:17.017449 ZQ Calibration : PASS
2165 09:26:17.017505 Jitter Meter : NO K
2166 09:26:17.017561 CBT Training : PASS
2167 09:26:17.017618 Write leveling : PASS
2168 09:26:17.017674 RX DQS gating : PASS
2169 09:26:17.017731 RX DQ/DQS(RDDQC) : PASS
2170 09:26:17.017788 TX DQ/DQS : PASS
2171 09:26:17.017844 RX DATLAT : PASS
2172 09:26:17.017901 RX DQ/DQS(Engine): PASS
2173 09:26:17.017958 TX OE : NO K
2174 09:26:17.018014 All Pass.
2175 09:26:17.018070
2176 09:26:17.018126 DramC Write-DBI off
2177 09:26:17.018182 PER_BANK_REFRESH: Hybrid Mode
2178 09:26:17.018239 TX_TRACKING: ON
2179 09:26:17.018296 [GetDramInforAfterCalByMRR] Vendor 6.
2180 09:26:17.018353 [GetDramInforAfterCalByMRR] Revision 606.
2181 09:26:17.018409 [GetDramInforAfterCalByMRR] Revision 2 0.
2182 09:26:17.018465 MR0 0x3b3b
2183 09:26:17.018521 MR8 0x5151
2184 09:26:17.018577 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2185 09:26:17.018633
2186 09:26:17.018690 MR0 0x3b3b
2187 09:26:17.018746 MR8 0x5151
2188 09:26:17.018802 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2189 09:26:17.018859
2190 09:26:17.018916 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2191 09:26:17.018974 [FAST_K] Save calibration result to emmc
2192 09:26:17.019030 [FAST_K] Save calibration result to emmc
2193 09:26:17.019087 dram_init: config_dvfs: 1
2194 09:26:17.019143 dramc_set_vcore_voltage set vcore to 662500
2195 09:26:17.019200 Read voltage for 1200, 2
2196 09:26:17.019257 Vio18 = 0
2197 09:26:17.019313 Vcore = 662500
2198 09:26:17.019369 Vdram = 0
2199 09:26:17.019426 Vddq = 0
2200 09:26:17.019482 Vmddr = 0
2201 09:26:17.019538 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2202 09:26:17.019594 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2203 09:26:17.019651 MEM_TYPE=3, freq_sel=15
2204 09:26:17.019707 sv_algorithm_assistance_LP4_1600
2205 09:26:17.019764 ============ PULL DRAM RESETB DOWN ============
2206 09:26:17.019821 ========== PULL DRAM RESETB DOWN end =========
2207 09:26:17.019878 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2208 09:26:17.019935 ===================================
2209 09:26:17.019992 LPDDR4 DRAM CONFIGURATION
2210 09:26:17.020049 ===================================
2211 09:26:17.020106 EX_ROW_EN[0] = 0x0
2212 09:26:17.020163 EX_ROW_EN[1] = 0x0
2213 09:26:17.020219 LP4Y_EN = 0x0
2214 09:26:17.020275 WORK_FSP = 0x0
2215 09:26:17.020331 WL = 0x4
2216 09:26:17.020393 RL = 0x4
2217 09:26:17.020484 BL = 0x2
2218 09:26:17.020581 RPST = 0x0
2219 09:26:17.020670 RD_PRE = 0x0
2220 09:26:17.020739 WR_PRE = 0x1
2221 09:26:17.020798 WR_PST = 0x0
2222 09:26:17.020853 DBI_WR = 0x0
2223 09:26:17.020909 DBI_RD = 0x0
2224 09:26:17.020964 OTF = 0x1
2225 09:26:17.021020 ===================================
2226 09:26:17.021076 ===================================
2227 09:26:17.021132 ANA top config
2228 09:26:17.021189 ===================================
2229 09:26:17.021245 DLL_ASYNC_EN = 0
2230 09:26:17.021302 ALL_SLAVE_EN = 0
2231 09:26:17.021358 NEW_RANK_MODE = 1
2232 09:26:17.021416 DLL_IDLE_MODE = 1
2233 09:26:17.021472 LP45_APHY_COMB_EN = 1
2234 09:26:17.021528 TX_ODT_DIS = 1
2235 09:26:17.021585 NEW_8X_MODE = 1
2236 09:26:17.021642 ===================================
2237 09:26:17.021698 ===================================
2238 09:26:17.021755 data_rate = 2400
2239 09:26:17.021812 CKR = 1
2240 09:26:17.021869 DQ_P2S_RATIO = 8
2241 09:26:17.021925 ===================================
2242 09:26:17.021983 CA_P2S_RATIO = 8
2243 09:26:17.022039 DQ_CA_OPEN = 0
2244 09:26:17.022095 DQ_SEMI_OPEN = 0
2245 09:26:17.022151 CA_SEMI_OPEN = 0
2246 09:26:17.022207 CA_FULL_RATE = 0
2247 09:26:17.022264 DQ_CKDIV4_EN = 0
2248 09:26:17.022320 CA_CKDIV4_EN = 0
2249 09:26:17.022376 CA_PREDIV_EN = 0
2250 09:26:17.022432 PH8_DLY = 17
2251 09:26:17.022488 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2252 09:26:17.022545 DQ_AAMCK_DIV = 4
2253 09:26:17.022601 CA_AAMCK_DIV = 4
2254 09:26:17.022657 CA_ADMCK_DIV = 4
2255 09:26:17.022713 DQ_TRACK_CA_EN = 0
2256 09:26:17.022770 CA_PICK = 1200
2257 09:26:17.022826 CA_MCKIO = 1200
2258 09:26:17.022882 MCKIO_SEMI = 0
2259 09:26:17.022939 PLL_FREQ = 2366
2260 09:26:17.022995 DQ_UI_PI_RATIO = 32
2261 09:26:17.023051 CA_UI_PI_RATIO = 0
2262 09:26:17.023106 ===================================
2263 09:26:17.023163 ===================================
2264 09:26:17.023220 memory_type:LPDDR4
2265 09:26:17.023276 GP_NUM : 10
2266 09:26:17.023332 SRAM_EN : 1
2267 09:26:17.023388 MD32_EN : 0
2268 09:26:17.023445 ===================================
2269 09:26:17.023502 [ANA_INIT] >>>>>>>>>>>>>>
2270 09:26:17.023558 <<<<<< [CONFIGURE PHASE]: ANA_TX
2271 09:26:17.023614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2272 09:26:17.023671 ===================================
2273 09:26:17.023727 data_rate = 2400,PCW = 0X5b00
2274 09:26:17.023783 ===================================
2275 09:26:17.023839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2276 09:26:17.023896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2277 09:26:17.023954 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2278 09:26:17.024010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2279 09:26:17.024067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2280 09:26:17.024123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2281 09:26:17.024180 [ANA_INIT] flow start
2282 09:26:17.024236 [ANA_INIT] PLL >>>>>>>>
2283 09:26:17.024292 [ANA_INIT] PLL <<<<<<<<
2284 09:26:17.024348 [ANA_INIT] MIDPI >>>>>>>>
2285 09:26:17.024404 [ANA_INIT] MIDPI <<<<<<<<
2286 09:26:17.024460 [ANA_INIT] DLL >>>>>>>>
2287 09:26:17.024516 [ANA_INIT] DLL <<<<<<<<
2288 09:26:17.024585 [ANA_INIT] flow end
2289 09:26:17.024845 ============ LP4 DIFF to SE enter ============
2290 09:26:17.024912 ============ LP4 DIFF to SE exit ============
2291 09:26:17.024970 [ANA_INIT] <<<<<<<<<<<<<
2292 09:26:17.025027 [Flow] Enable top DCM control >>>>>
2293 09:26:17.025083 [Flow] Enable top DCM control <<<<<
2294 09:26:17.025141 Enable DLL master slave shuffle
2295 09:26:17.025197 ==============================================================
2296 09:26:17.025255 Gating Mode config
2297 09:26:17.025311 ==============================================================
2298 09:26:17.025368 Config description:
2299 09:26:17.025428 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2300 09:26:17.025523 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2301 09:26:17.025616 SELPH_MODE 0: By rank 1: By Phase
2302 09:26:17.025702 ==============================================================
2303 09:26:17.025775 GAT_TRACK_EN = 1
2304 09:26:17.025833 RX_GATING_MODE = 2
2305 09:26:17.025891 RX_GATING_TRACK_MODE = 2
2306 09:26:17.025948 SELPH_MODE = 1
2307 09:26:17.026005 PICG_EARLY_EN = 1
2308 09:26:17.026062 VALID_LAT_VALUE = 1
2309 09:26:17.026119 ==============================================================
2310 09:26:17.026177 Enter into Gating configuration >>>>
2311 09:26:17.026234 Exit from Gating configuration <<<<
2312 09:26:17.026291 Enter into DVFS_PRE_config >>>>>
2313 09:26:17.026348 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2314 09:26:17.026406 Exit from DVFS_PRE_config <<<<<
2315 09:26:17.026462 Enter into PICG configuration >>>>
2316 09:26:17.026518 Exit from PICG configuration <<<<
2317 09:26:17.026575 [RX_INPUT] configuration >>>>>
2318 09:26:17.026632 [RX_INPUT] configuration <<<<<
2319 09:26:17.026700 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2320 09:26:17.026759 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2321 09:26:17.026816 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2322 09:26:17.026873 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2323 09:26:17.026930 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2324 09:26:17.026986 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2325 09:26:17.027043 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2326 09:26:17.027099 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2327 09:26:17.027157 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2328 09:26:17.027214 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2329 09:26:17.027270 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2330 09:26:17.027327 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2331 09:26:17.027384 ===================================
2332 09:26:17.027440 LPDDR4 DRAM CONFIGURATION
2333 09:26:17.027496 ===================================
2334 09:26:17.027553 EX_ROW_EN[0] = 0x0
2335 09:26:17.027609 EX_ROW_EN[1] = 0x0
2336 09:26:17.027665 LP4Y_EN = 0x0
2337 09:26:17.027721 WORK_FSP = 0x0
2338 09:26:17.027777 WL = 0x4
2339 09:26:17.027834 RL = 0x4
2340 09:26:17.027890 BL = 0x2
2341 09:26:17.027946 RPST = 0x0
2342 09:26:17.028002 RD_PRE = 0x0
2343 09:26:17.028059 WR_PRE = 0x1
2344 09:26:17.028114 WR_PST = 0x0
2345 09:26:17.028170 DBI_WR = 0x0
2346 09:26:17.028225 DBI_RD = 0x0
2347 09:26:17.028281 OTF = 0x1
2348 09:26:17.028338 ===================================
2349 09:26:17.028395 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2350 09:26:17.028451 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2351 09:26:17.028507 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2352 09:26:17.028583 ===================================
2353 09:26:17.028642 LPDDR4 DRAM CONFIGURATION
2354 09:26:17.028702 ===================================
2355 09:26:17.028792 EX_ROW_EN[0] = 0x10
2356 09:26:17.028862 EX_ROW_EN[1] = 0x0
2357 09:26:17.028920 LP4Y_EN = 0x0
2358 09:26:17.028977 WORK_FSP = 0x0
2359 09:26:17.029034 WL = 0x4
2360 09:26:17.029091 RL = 0x4
2361 09:26:17.029145 BL = 0x2
2362 09:26:17.029200 RPST = 0x0
2363 09:26:17.029254 RD_PRE = 0x0
2364 09:26:17.029317 WR_PRE = 0x1
2365 09:26:17.029407 WR_PST = 0x0
2366 09:26:17.029495 DBI_WR = 0x0
2367 09:26:17.029579 DBI_RD = 0x0
2368 09:26:17.029655 OTF = 0x1
2369 09:26:17.029713 ===================================
2370 09:26:17.029770 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2371 09:26:17.029826 ==
2372 09:26:17.029880 Dram Type= 6, Freq= 0, CH_0, rank 0
2373 09:26:17.029935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 09:26:17.029990 ==
2375 09:26:17.030045 [Duty_Offset_Calibration]
2376 09:26:17.030099 B0:2 B1:0 CA:1
2377 09:26:17.030154
2378 09:26:17.030208 [DutyScan_Calibration_Flow] k_type=0
2379 09:26:17.030262
2380 09:26:17.030316 ==CLK 0==
2381 09:26:17.030370 Final CLK duty delay cell = -4
2382 09:26:17.030425 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2383 09:26:17.030479 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2384 09:26:17.030534 [-4] AVG Duty = 4953%(X100)
2385 09:26:17.030588
2386 09:26:17.030642 CH0 CLK Duty spec in!! Max-Min= 156%
2387 09:26:17.030696 [DutyScan_Calibration_Flow] ====Done====
2388 09:26:17.030750
2389 09:26:17.030804 [DutyScan_Calibration_Flow] k_type=1
2390 09:26:17.030859
2391 09:26:17.030917 ==DQS 0 ==
2392 09:26:17.030972 Final DQS duty delay cell = 0
2393 09:26:17.031027 [0] MAX Duty = 5187%(X100), DQS PI = 32
2394 09:26:17.031083 [0] MIN Duty = 4938%(X100), DQS PI = 0
2395 09:26:17.031137 [0] AVG Duty = 5062%(X100)
2396 09:26:17.031190
2397 09:26:17.031244 ==DQS 1 ==
2398 09:26:17.031298 Final DQS duty delay cell = -4
2399 09:26:17.031353 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2400 09:26:17.031408 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2401 09:26:17.031461 [-4] AVG Duty = 5031%(X100)
2402 09:26:17.031515
2403 09:26:17.031569 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2404 09:26:17.031625
2405 09:26:17.031679 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2406 09:26:17.031734 [DutyScan_Calibration_Flow] ====Done====
2407 09:26:17.031787
2408 09:26:17.032035 [DutyScan_Calibration_Flow] k_type=3
2409 09:26:17.032096
2410 09:26:17.032152 ==DQM 0 ==
2411 09:26:17.032207 Final DQM duty delay cell = 0
2412 09:26:17.032263 [0] MAX Duty = 5062%(X100), DQS PI = 24
2413 09:26:17.032317 [0] MIN Duty = 4813%(X100), DQS PI = 0
2414 09:26:17.032372 [0] AVG Duty = 4937%(X100)
2415 09:26:17.032426
2416 09:26:17.032480 ==DQM 1 ==
2417 09:26:17.032534 Final DQM duty delay cell = 0
2418 09:26:17.032601 [0] MAX Duty = 5187%(X100), DQS PI = 46
2419 09:26:17.032657 [0] MIN Duty = 5000%(X100), DQS PI = 12
2420 09:26:17.032712 [0] AVG Duty = 5093%(X100)
2421 09:26:17.032766
2422 09:26:17.032820 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2423 09:26:17.032874
2424 09:26:17.032928 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2425 09:26:17.032983 [DutyScan_Calibration_Flow] ====Done====
2426 09:26:17.033037
2427 09:26:17.033091 [DutyScan_Calibration_Flow] k_type=2
2428 09:26:17.033146
2429 09:26:17.033199 ==DQ 0 ==
2430 09:26:17.033254 Final DQ duty delay cell = -4
2431 09:26:17.033308 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2432 09:26:17.033363 [-4] MIN Duty = 4844%(X100), DQS PI = 16
2433 09:26:17.033418 [-4] AVG Duty = 4937%(X100)
2434 09:26:17.033472
2435 09:26:17.033526 ==DQ 1 ==
2436 09:26:17.033581 Final DQ duty delay cell = 4
2437 09:26:17.033636 [4] MAX Duty = 5093%(X100), DQS PI = 4
2438 09:26:17.033708 [4] MIN Duty = 5031%(X100), DQS PI = 0
2439 09:26:17.033783 [4] AVG Duty = 5062%(X100)
2440 09:26:17.033876
2441 09:26:17.033965 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2442 09:26:17.034058
2443 09:26:17.034126 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2444 09:26:17.034183 [DutyScan_Calibration_Flow] ====Done====
2445 09:26:17.034251 ==
2446 09:26:17.034307 Dram Type= 6, Freq= 0, CH_1, rank 0
2447 09:26:17.034365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 09:26:17.034425 ==
2449 09:26:17.034480 [Duty_Offset_Calibration]
2450 09:26:17.034535 B0:0 B1:-1 CA:2
2451 09:26:17.034592
2452 09:26:17.034646 [DutyScan_Calibration_Flow] k_type=0
2453 09:26:17.034701
2454 09:26:17.034756 ==CLK 0==
2455 09:26:17.034811 Final CLK duty delay cell = 0
2456 09:26:17.034866 [0] MAX Duty = 5156%(X100), DQS PI = 10
2457 09:26:17.034922 [0] MIN Duty = 4938%(X100), DQS PI = 44
2458 09:26:17.034976 [0] AVG Duty = 5047%(X100)
2459 09:26:17.035031
2460 09:26:17.035086 CH1 CLK Duty spec in!! Max-Min= 218%
2461 09:26:17.035140 [DutyScan_Calibration_Flow] ====Done====
2462 09:26:17.035195
2463 09:26:17.035248 [DutyScan_Calibration_Flow] k_type=1
2464 09:26:17.035303
2465 09:26:17.035357 ==DQS 0 ==
2466 09:26:17.035411 Final DQS duty delay cell = 0
2467 09:26:17.035467 [0] MAX Duty = 5093%(X100), DQS PI = 24
2468 09:26:17.035521 [0] MIN Duty = 4969%(X100), DQS PI = 0
2469 09:26:17.035576 [0] AVG Duty = 5031%(X100)
2470 09:26:17.035631
2471 09:26:17.035685 ==DQS 1 ==
2472 09:26:17.035739 Final DQS duty delay cell = 0
2473 09:26:17.035794 [0] MAX Duty = 5156%(X100), DQS PI = 0
2474 09:26:17.035849 [0] MIN Duty = 4844%(X100), DQS PI = 36
2475 09:26:17.035903 [0] AVG Duty = 5000%(X100)
2476 09:26:17.035957
2477 09:26:17.036011 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2478 09:26:17.036066
2479 09:26:17.036120 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2480 09:26:17.036189 [DutyScan_Calibration_Flow] ====Done====
2481 09:26:17.036242
2482 09:26:17.036295 [DutyScan_Calibration_Flow] k_type=3
2483 09:26:17.036347
2484 09:26:17.036400 ==DQM 0 ==
2485 09:26:17.036453 Final DQM duty delay cell = 4
2486 09:26:17.036506 [4] MAX Duty = 5093%(X100), DQS PI = 22
2487 09:26:17.036599 [4] MIN Duty = 4938%(X100), DQS PI = 42
2488 09:26:17.036654 [4] AVG Duty = 5015%(X100)
2489 09:26:17.036708
2490 09:26:17.036762 ==DQM 1 ==
2491 09:26:17.036815 Final DQM duty delay cell = -4
2492 09:26:17.036869 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2493 09:26:17.036923 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2494 09:26:17.036976 [-4] AVG Duty = 4875%(X100)
2495 09:26:17.037029
2496 09:26:17.037082 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2497 09:26:17.037135
2498 09:26:17.037187 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2499 09:26:17.037241 [DutyScan_Calibration_Flow] ====Done====
2500 09:26:17.037294
2501 09:26:17.037347 [DutyScan_Calibration_Flow] k_type=2
2502 09:26:17.037400
2503 09:26:17.037453 ==DQ 0 ==
2504 09:26:17.037506 Final DQ duty delay cell = 0
2505 09:26:17.037560 [0] MAX Duty = 5031%(X100), DQS PI = 20
2506 09:26:17.037613 [0] MIN Duty = 4938%(X100), DQS PI = 0
2507 09:26:17.037667 [0] AVG Duty = 4984%(X100)
2508 09:26:17.037720
2509 09:26:17.037773 ==DQ 1 ==
2510 09:26:17.037827 Final DQ duty delay cell = 0
2511 09:26:17.037880 [0] MAX Duty = 5031%(X100), DQS PI = 0
2512 09:26:17.037933 [0] MIN Duty = 4813%(X100), DQS PI = 34
2513 09:26:17.037986 [0] AVG Duty = 4922%(X100)
2514 09:26:17.038039
2515 09:26:17.038092 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2516 09:26:17.038176
2517 09:26:17.038260 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2518 09:26:17.038345 [DutyScan_Calibration_Flow] ====Done====
2519 09:26:17.038426 nWR fixed to 30
2520 09:26:17.038484 [ModeRegInit_LP4] CH0 RK0
2521 09:26:17.038539 [ModeRegInit_LP4] CH0 RK1
2522 09:26:17.038592 [ModeRegInit_LP4] CH1 RK0
2523 09:26:17.038646 [ModeRegInit_LP4] CH1 RK1
2524 09:26:17.038699 match AC timing 7
2525 09:26:17.038753 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2526 09:26:17.038807 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2527 09:26:17.038861 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2528 09:26:17.038915 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2529 09:26:17.038969 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2530 09:26:17.039023 ==
2531 09:26:17.039077 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 09:26:17.039131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 09:26:17.039184 ==
2534 09:26:17.039237 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2535 09:26:17.039290 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2536 09:26:17.039344 [CA 0] Center 38 (7~69) winsize 63
2537 09:26:17.039397 [CA 1] Center 38 (8~69) winsize 62
2538 09:26:17.039469 [CA 2] Center 35 (4~66) winsize 63
2539 09:26:17.039524 [CA 3] Center 35 (4~66) winsize 63
2540 09:26:17.039578 [CA 4] Center 34 (4~65) winsize 62
2541 09:26:17.039631 [CA 5] Center 33 (3~64) winsize 62
2542 09:26:17.039684
2543 09:26:17.039737 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2544 09:26:17.039791
2545 09:26:17.039843 [CATrainingPosCal] consider 1 rank data
2546 09:26:17.039896 u2DelayCellTimex100 = 270/100 ps
2547 09:26:17.039949 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2548 09:26:17.040002 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2549 09:26:17.040056 CA2 delay=35 (4~66),Diff = 2 PI (9 cell)
2550 09:26:17.040110 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2551 09:26:17.040163 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2552 09:26:17.040216 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2553 09:26:17.040269
2554 09:26:17.040322 CA PerBit enable=1, Macro0, CA PI delay=33
2555 09:26:17.040375
2556 09:26:17.040427 [CBTSetCACLKResult] CA Dly = 33
2557 09:26:17.040480 CS Dly: 6 (0~37)
2558 09:26:17.040533 ==
2559 09:26:17.040827 Dram Type= 6, Freq= 0, CH_0, rank 1
2560 09:26:17.040887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2561 09:26:17.040942 ==
2562 09:26:17.040996 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2563 09:26:17.041051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2564 09:26:17.041104 [CA 0] Center 39 (8~70) winsize 63
2565 09:26:17.041158 [CA 1] Center 38 (8~69) winsize 62
2566 09:26:17.041212 [CA 2] Center 35 (5~66) winsize 62
2567 09:26:17.041265 [CA 3] Center 35 (5~66) winsize 62
2568 09:26:17.041319 [CA 4] Center 34 (4~65) winsize 62
2569 09:26:17.041372 [CA 5] Center 34 (4~64) winsize 61
2570 09:26:17.041426
2571 09:26:17.041479 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2572 09:26:17.041532
2573 09:26:17.041585 [CATrainingPosCal] consider 2 rank data
2574 09:26:17.041638 u2DelayCellTimex100 = 270/100 ps
2575 09:26:17.041691 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2576 09:26:17.041745 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2577 09:26:17.041798 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2578 09:26:17.041851 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2579 09:26:17.041905 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2580 09:26:17.041958 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2581 09:26:17.042012
2582 09:26:17.042065 CA PerBit enable=1, Macro0, CA PI delay=34
2583 09:26:17.042118
2584 09:26:17.042171 [CBTSetCACLKResult] CA Dly = 34
2585 09:26:17.042223 CS Dly: 7 (0~39)
2586 09:26:17.042276
2587 09:26:17.042329 ----->DramcWriteLeveling(PI) begin...
2588 09:26:17.042384 ==
2589 09:26:17.042437 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 09:26:17.042491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 09:26:17.042574 ==
2592 09:26:17.042658 Write leveling (Byte 0): 33 => 33
2593 09:26:17.042743 Write leveling (Byte 1): 31 => 31
2594 09:26:17.042824 DramcWriteLeveling(PI) end<-----
2595 09:26:17.042881
2596 09:26:17.042936 ==
2597 09:26:17.042990 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 09:26:17.043044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 09:26:17.043098 ==
2600 09:26:17.043152 [Gating] SW mode calibration
2601 09:26:17.043205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2602 09:26:17.043259 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2603 09:26:17.043313 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2604 09:26:17.043366 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
2605 09:26:17.043420 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 09:26:17.043473 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 09:26:17.043527 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 09:26:17.043581 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 09:26:17.043635 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2610 09:26:17.043689 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2611 09:26:17.043742 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2612 09:26:17.043796 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 09:26:17.043849 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 09:26:17.043903 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 09:26:17.043956 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 09:26:17.044009 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 09:26:17.044063 1 0 24 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
2618 09:26:17.044116 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2619 09:26:17.044170 1 1 0 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
2620 09:26:17.044223 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 09:26:17.044277 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 09:26:17.044330 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 09:26:17.044383 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 09:26:17.044436 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 09:26:17.044490 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2626 09:26:17.044543 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2627 09:26:17.044642 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2628 09:26:17.044695 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 09:26:17.044749 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 09:26:17.044802 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 09:26:17.044856 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 09:26:17.044909 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 09:26:17.044962 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 09:26:17.045015 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 09:26:17.045068 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 09:26:17.045121 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 09:26:17.045175 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 09:26:17.045228 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 09:26:17.045282 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 09:26:17.045336 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 09:26:17.045389 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 09:26:17.045443 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2643 09:26:17.045498 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2644 09:26:17.045551 Total UI for P1: 0, mck2ui 16
2645 09:26:17.045605 best dqsien dly found for B0: ( 1, 3, 28)
2646 09:26:17.045659 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2647 09:26:17.045715 Total UI for P1: 0, mck2ui 16
2648 09:26:17.045769 best dqsien dly found for B1: ( 1, 4, 0)
2649 09:26:17.045822 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2650 09:26:17.045880 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2651 09:26:17.045933
2652 09:26:17.045986 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2653 09:26:17.046042 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2654 09:26:17.046095 [Gating] SW calibration Done
2655 09:26:17.046149 ==
2656 09:26:17.046202 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 09:26:17.046257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 09:26:17.046311 ==
2659 09:26:17.046365 RX Vref Scan: 0
2660 09:26:17.046422
2661 09:26:17.046475 RX Vref 0 -> 0, step: 1
2662 09:26:17.046527
2663 09:26:17.046580 RX Delay -40 -> 252, step: 8
2664 09:26:17.046836 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
2665 09:26:17.046924 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2666 09:26:17.046994 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2667 09:26:17.047048 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2668 09:26:17.047102 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2669 09:26:17.047155 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2670 09:26:17.047208 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2671 09:26:17.047262 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2672 09:26:17.047331 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2673 09:26:17.047457 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2674 09:26:17.047544 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2675 09:26:17.047627 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2676 09:26:17.047729 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2677 09:26:17.047786 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2678 09:26:17.047839 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2679 09:26:17.047894 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2680 09:26:17.047962 ==
2681 09:26:17.048030 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 09:26:17.048084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 09:26:17.048137 ==
2684 09:26:17.048190 DQS Delay:
2685 09:26:17.048258 DQS0 = 0, DQS1 = 0
2686 09:26:17.048326 DQM Delay:
2687 09:26:17.048379 DQM0 = 122, DQM1 = 110
2688 09:26:17.048432 DQ Delay:
2689 09:26:17.048486 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2690 09:26:17.048564 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2691 09:26:17.048632 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2692 09:26:17.048686 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2693 09:26:17.048739
2694 09:26:17.048791
2695 09:26:17.048843 ==
2696 09:26:17.048896 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 09:26:17.048950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 09:26:17.049003 ==
2699 09:26:17.049056
2700 09:26:17.049109
2701 09:26:17.049162 TX Vref Scan disable
2702 09:26:17.049215 == TX Byte 0 ==
2703 09:26:17.049268 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2704 09:26:17.049322 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2705 09:26:17.049374 == TX Byte 1 ==
2706 09:26:17.049428 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2707 09:26:17.049481 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2708 09:26:17.049534 ==
2709 09:26:17.049588 Dram Type= 6, Freq= 0, CH_0, rank 0
2710 09:26:17.049641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2711 09:26:17.049695 ==
2712 09:26:17.049748 TX Vref=22, minBit 6, minWin=24, winSum=411
2713 09:26:17.049802 TX Vref=24, minBit 0, minWin=25, winSum=415
2714 09:26:17.049856 TX Vref=26, minBit 0, minWin=25, winSum=418
2715 09:26:17.049909 TX Vref=28, minBit 1, minWin=25, winSum=422
2716 09:26:17.049978 TX Vref=30, minBit 5, minWin=25, winSum=425
2717 09:26:17.050045 TX Vref=32, minBit 1, minWin=25, winSum=421
2718 09:26:17.050099 [TxChooseVref] Worse bit 5, Min win 25, Win sum 425, Final Vref 30
2719 09:26:17.050152
2720 09:26:17.050205 Final TX Range 1 Vref 30
2721 09:26:17.050259
2722 09:26:17.050312 ==
2723 09:26:17.050365 Dram Type= 6, Freq= 0, CH_0, rank 0
2724 09:26:17.050418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2725 09:26:17.050471 ==
2726 09:26:17.050524
2727 09:26:17.050577
2728 09:26:17.050630 TX Vref Scan disable
2729 09:26:17.050684 == TX Byte 0 ==
2730 09:26:17.050751 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2731 09:26:17.050807 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2732 09:26:17.050860 == TX Byte 1 ==
2733 09:26:17.050914 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2734 09:26:17.050968 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2735 09:26:17.051021
2736 09:26:17.051074 [DATLAT]
2737 09:26:17.051128 Freq=1200, CH0 RK0
2738 09:26:17.051181
2739 09:26:17.051233 DATLAT Default: 0xd
2740 09:26:17.051286 0, 0xFFFF, sum = 0
2741 09:26:17.051341 1, 0xFFFF, sum = 0
2742 09:26:17.051395 2, 0xFFFF, sum = 0
2743 09:26:17.051449 3, 0xFFFF, sum = 0
2744 09:26:17.051503 4, 0xFFFF, sum = 0
2745 09:26:17.051558 5, 0xFFFF, sum = 0
2746 09:26:17.051612 6, 0xFFFF, sum = 0
2747 09:26:17.051665 7, 0xFFFF, sum = 0
2748 09:26:17.051719 8, 0xFFFF, sum = 0
2749 09:26:17.051774 9, 0xFFFF, sum = 0
2750 09:26:17.051896 10, 0xFFFF, sum = 0
2751 09:26:17.051985 11, 0xFFFF, sum = 0
2752 09:26:17.052069 12, 0x0, sum = 1
2753 09:26:17.052138 13, 0x0, sum = 2
2754 09:26:17.052194 14, 0x0, sum = 3
2755 09:26:17.052250 15, 0x0, sum = 4
2756 09:26:17.052305 best_step = 13
2757 09:26:17.052358
2758 09:26:17.052411 ==
2759 09:26:17.052465 Dram Type= 6, Freq= 0, CH_0, rank 0
2760 09:26:17.052519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2761 09:26:17.052612 ==
2762 09:26:17.052667 RX Vref Scan: 1
2763 09:26:17.052743
2764 09:26:17.052797 Set Vref Range= 32 -> 127
2765 09:26:17.052851
2766 09:26:17.052905 RX Vref 32 -> 127, step: 1
2767 09:26:17.052959
2768 09:26:17.053011 RX Delay -13 -> 252, step: 4
2769 09:26:17.053065
2770 09:26:17.053118 Set Vref, RX VrefLevel [Byte0]: 32
2771 09:26:17.053171 [Byte1]: 32
2772 09:26:17.053224
2773 09:26:17.053277 Set Vref, RX VrefLevel [Byte0]: 33
2774 09:26:17.053330 [Byte1]: 33
2775 09:26:17.053383
2776 09:26:17.053436 Set Vref, RX VrefLevel [Byte0]: 34
2777 09:26:17.053489 [Byte1]: 34
2778 09:26:17.053543
2779 09:26:17.053596 Set Vref, RX VrefLevel [Byte0]: 35
2780 09:26:17.053649 [Byte1]: 35
2781 09:26:17.053702
2782 09:26:17.053756 Set Vref, RX VrefLevel [Byte0]: 36
2783 09:26:17.053809 [Byte1]: 36
2784 09:26:17.053862
2785 09:26:17.053914 Set Vref, RX VrefLevel [Byte0]: 37
2786 09:26:17.053968 [Byte1]: 37
2787 09:26:17.054021
2788 09:26:17.054074 Set Vref, RX VrefLevel [Byte0]: 38
2789 09:26:17.054127 [Byte1]: 38
2790 09:26:17.054181
2791 09:26:17.054234 Set Vref, RX VrefLevel [Byte0]: 39
2792 09:26:17.054287 [Byte1]: 39
2793 09:26:17.054340
2794 09:26:17.054393 Set Vref, RX VrefLevel [Byte0]: 40
2795 09:26:17.054446 [Byte1]: 40
2796 09:26:17.054499
2797 09:26:17.054552 Set Vref, RX VrefLevel [Byte0]: 41
2798 09:26:17.054605 [Byte1]: 41
2799 09:26:17.054658
2800 09:26:17.054724 Set Vref, RX VrefLevel [Byte0]: 42
2801 09:26:17.054810 [Byte1]: 42
2802 09:26:17.054869
2803 09:26:17.054923 Set Vref, RX VrefLevel [Byte0]: 43
2804 09:26:17.054977 [Byte1]: 43
2805 09:26:17.055030
2806 09:26:17.055083 Set Vref, RX VrefLevel [Byte0]: 44
2807 09:26:17.055136 [Byte1]: 44
2808 09:26:17.055190
2809 09:26:17.055243 Set Vref, RX VrefLevel [Byte0]: 45
2810 09:26:17.055297 [Byte1]: 45
2811 09:26:17.055350
2812 09:26:17.055402 Set Vref, RX VrefLevel [Byte0]: 46
2813 09:26:17.055471 [Byte1]: 46
2814 09:26:17.055537
2815 09:26:17.055589 Set Vref, RX VrefLevel [Byte0]: 47
2816 09:26:17.055642 [Byte1]: 47
2817 09:26:17.055696
2818 09:26:17.055748 Set Vref, RX VrefLevel [Byte0]: 48
2819 09:26:17.055801 [Byte1]: 48
2820 09:26:17.055854
2821 09:26:17.056101 Set Vref, RX VrefLevel [Byte0]: 49
2822 09:26:17.056196 [Byte1]: 49
2823 09:26:17.056250
2824 09:26:17.056303 Set Vref, RX VrefLevel [Byte0]: 50
2825 09:26:17.056357 [Byte1]: 50
2826 09:26:17.056410
2827 09:26:17.056493 Set Vref, RX VrefLevel [Byte0]: 51
2828 09:26:17.056620 [Byte1]: 51
2829 09:26:17.056706
2830 09:26:17.056776 Set Vref, RX VrefLevel [Byte0]: 52
2831 09:26:17.056832 [Byte1]: 52
2832 09:26:17.056887
2833 09:26:17.056940 Set Vref, RX VrefLevel [Byte0]: 53
2834 09:26:17.056994 [Byte1]: 53
2835 09:26:17.057047
2836 09:26:17.057100 Set Vref, RX VrefLevel [Byte0]: 54
2837 09:26:17.057154 [Byte1]: 54
2838 09:26:17.057208
2839 09:26:17.057261 Set Vref, RX VrefLevel [Byte0]: 55
2840 09:26:17.057315 [Byte1]: 55
2841 09:26:17.057368
2842 09:26:17.057421 Set Vref, RX VrefLevel [Byte0]: 56
2843 09:26:17.057475 [Byte1]: 56
2844 09:26:17.057528
2845 09:26:17.057581 Set Vref, RX VrefLevel [Byte0]: 57
2846 09:26:17.057634 [Byte1]: 57
2847 09:26:17.057687
2848 09:26:17.057740 Set Vref, RX VrefLevel [Byte0]: 58
2849 09:26:17.057793 [Byte1]: 58
2850 09:26:17.057846
2851 09:26:17.057899 Set Vref, RX VrefLevel [Byte0]: 59
2852 09:26:17.057952 [Byte1]: 59
2853 09:26:17.058006
2854 09:26:17.058058 Set Vref, RX VrefLevel [Byte0]: 60
2855 09:26:17.058111 [Byte1]: 60
2856 09:26:17.058177
2857 09:26:17.058231 Set Vref, RX VrefLevel [Byte0]: 61
2858 09:26:17.058285 [Byte1]: 61
2859 09:26:17.058339
2860 09:26:17.058392 Set Vref, RX VrefLevel [Byte0]: 62
2861 09:26:17.058447 [Byte1]: 62
2862 09:26:17.058500
2863 09:26:17.058580 Set Vref, RX VrefLevel [Byte0]: 63
2864 09:26:17.058634 [Byte1]: 63
2865 09:26:17.058687
2866 09:26:17.058740 Set Vref, RX VrefLevel [Byte0]: 64
2867 09:26:17.058794 [Byte1]: 64
2868 09:26:17.058847
2869 09:26:17.058901 Set Vref, RX VrefLevel [Byte0]: 65
2870 09:26:17.058954 [Byte1]: 65
2871 09:26:17.059007
2872 09:26:17.059060 Set Vref, RX VrefLevel [Byte0]: 66
2873 09:26:17.059113 [Byte1]: 66
2874 09:26:17.059166
2875 09:26:17.059219 Set Vref, RX VrefLevel [Byte0]: 67
2876 09:26:17.059272 [Byte1]: 67
2877 09:26:17.059325
2878 09:26:17.059378 Set Vref, RX VrefLevel [Byte0]: 68
2879 09:26:17.059432 [Byte1]: 68
2880 09:26:17.059485
2881 09:26:17.059538 Set Vref, RX VrefLevel [Byte0]: 69
2882 09:26:17.059592 [Byte1]: 69
2883 09:26:17.059644
2884 09:26:17.059697 Set Vref, RX VrefLevel [Byte0]: 70
2885 09:26:17.059750 [Byte1]: 70
2886 09:26:17.059803
2887 09:26:17.059857 Final RX Vref Byte 0 = 59 to rank0
2888 09:26:17.059910 Final RX Vref Byte 1 = 50 to rank0
2889 09:26:17.059963 Final RX Vref Byte 0 = 59 to rank1
2890 09:26:17.060017 Final RX Vref Byte 1 = 50 to rank1==
2891 09:26:17.060070 Dram Type= 6, Freq= 0, CH_0, rank 0
2892 09:26:17.060124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 09:26:17.060178 ==
2894 09:26:17.060232 DQS Delay:
2895 09:26:17.060286 DQS0 = 0, DQS1 = 0
2896 09:26:17.060339 DQM Delay:
2897 09:26:17.060392 DQM0 = 122, DQM1 = 109
2898 09:26:17.060445 DQ Delay:
2899 09:26:17.060499 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2900 09:26:17.060579 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2901 09:26:17.060648 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2902 09:26:17.060701 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2903 09:26:17.060755
2904 09:26:17.060808
2905 09:26:17.060861 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 404 ps
2906 09:26:17.060915 CH0 RK0: MR19=404, MR18=F0B
2907 09:26:17.060969 CH0_RK0: MR19=0x404, MR18=0xF0B, DQSOSC=404, MR23=63, INC=40, DEC=26
2908 09:26:17.061022
2909 09:26:17.061075 ----->DramcWriteLeveling(PI) begin...
2910 09:26:17.061130 ==
2911 09:26:17.061184 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 09:26:17.061278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 09:26:17.061366 ==
2914 09:26:17.061454 Write leveling (Byte 0): 35 => 35
2915 09:26:17.061536 Write leveling (Byte 1): 31 => 31
2916 09:26:17.061605 DramcWriteLeveling(PI) end<-----
2917 09:26:17.061660
2918 09:26:17.061727 ==
2919 09:26:17.061824 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 09:26:17.061877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 09:26:17.061931 ==
2922 09:26:17.061985 [Gating] SW mode calibration
2923 09:26:17.062038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2924 09:26:17.062092 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2925 09:26:17.062145 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
2926 09:26:17.062199 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 09:26:17.062252 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 09:26:17.062305 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 09:26:17.062359 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 09:26:17.062413 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 09:26:17.062466 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 09:26:17.062519 0 15 28 | B1->B0 | 3131 2e2e | 0 0 | (0 1) (0 1)
2933 09:26:17.062573 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 09:26:17.062626 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 09:26:17.062679 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 09:26:17.062732 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 09:26:17.062786 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 09:26:17.062845 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 09:26:17.062900 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 09:26:17.062953 1 0 28 | B1->B0 | 3a3a 4343 | 0 0 | (0 0) (0 0)
2941 09:26:17.063006 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 09:26:17.063060 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 09:26:17.063113 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 09:26:17.063166 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 09:26:17.063219 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 09:26:17.063273 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 09:26:17.063326 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 09:26:17.063379 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2949 09:26:17.063624 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 09:26:17.063683 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 09:26:17.063751 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 09:26:17.063820 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 09:26:17.063874 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 09:26:17.063928 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 09:26:17.063981 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 09:26:17.064049 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 09:26:17.064118 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 09:26:17.064171 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 09:26:17.064224 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 09:26:17.064278 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 09:26:17.064345 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 09:26:17.064412 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 09:26:17.064466 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 09:26:17.064518 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2965 09:26:17.064607 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 09:26:17.064662 Total UI for P1: 0, mck2ui 16
2967 09:26:17.064716 best dqsien dly found for B0: ( 1, 3, 28)
2968 09:26:17.064770 Total UI for P1: 0, mck2ui 16
2969 09:26:17.064824 best dqsien dly found for B1: ( 1, 3, 30)
2970 09:26:17.064878 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2971 09:26:17.064931 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2972 09:26:17.064984
2973 09:26:17.065037 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2974 09:26:17.065090 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2975 09:26:17.065144 [Gating] SW calibration Done
2976 09:26:17.065197 ==
2977 09:26:17.065250 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 09:26:17.065304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 09:26:17.065358 ==
2980 09:26:17.065411 RX Vref Scan: 0
2981 09:26:17.065464
2982 09:26:17.065517 RX Vref 0 -> 0, step: 1
2983 09:26:17.065586
2984 09:26:17.065689 RX Delay -40 -> 252, step: 8
2985 09:26:17.065774 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2986 09:26:17.065858 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2987 09:26:17.065933 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2988 09:26:17.065990 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2989 09:26:17.066044 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2990 09:26:17.066098 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2991 09:26:17.066152 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2992 09:26:17.066206 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2993 09:26:17.066259 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2994 09:26:17.066313 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2995 09:26:17.066366 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2996 09:26:17.066420 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2997 09:26:17.066473 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2998 09:26:17.066526 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2999 09:26:17.066579 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3000 09:26:17.066632 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3001 09:26:17.066685 ==
3002 09:26:17.066739 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 09:26:17.066792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 09:26:17.266622 ==
3005 09:26:17.266754 DQS Delay:
3006 09:26:17.266821 DQS0 = 0, DQS1 = 0
3007 09:26:17.266883 DQM Delay:
3008 09:26:17.266956 DQM0 = 120, DQM1 = 108
3009 09:26:17.267029 DQ Delay:
3010 09:26:17.267085 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3011 09:26:17.267141 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3012 09:26:17.267195 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3013 09:26:17.267250 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3014 09:26:17.267305
3015 09:26:17.267358
3016 09:26:17.267412 ==
3017 09:26:17.267466 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 09:26:17.267520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 09:26:17.267575 ==
3020 09:26:17.267629
3021 09:26:17.267682
3022 09:26:17.267735 TX Vref Scan disable
3023 09:26:17.267805 == TX Byte 0 ==
3024 09:26:17.267872 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3025 09:26:17.267926 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3026 09:26:17.267979 == TX Byte 1 ==
3027 09:26:17.268032 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3028 09:26:17.268086 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3029 09:26:17.268140 ==
3030 09:26:17.268193 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 09:26:17.268246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 09:26:17.268300 ==
3033 09:26:17.268354 TX Vref=22, minBit 4, minWin=23, winSum=406
3034 09:26:17.268409 TX Vref=24, minBit 2, minWin=24, winSum=413
3035 09:26:17.268463 TX Vref=26, minBit 7, minWin=24, winSum=417
3036 09:26:17.268517 TX Vref=28, minBit 1, minWin=25, winSum=421
3037 09:26:17.268619 TX Vref=30, minBit 2, minWin=25, winSum=422
3038 09:26:17.268675 TX Vref=32, minBit 1, minWin=25, winSum=421
3039 09:26:17.268730 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 30
3040 09:26:17.268785
3041 09:26:17.268839 Final TX Range 1 Vref 30
3042 09:26:17.268892
3043 09:26:17.268961 ==
3044 09:26:17.269029 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 09:26:17.269083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 09:26:17.269137 ==
3047 09:26:17.269191
3048 09:26:17.269244
3049 09:26:17.269298 TX Vref Scan disable
3050 09:26:17.269351 == TX Byte 0 ==
3051 09:26:17.269405 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3052 09:26:17.269459 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3053 09:26:17.269512 == TX Byte 1 ==
3054 09:26:17.269565 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3055 09:26:17.269619 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3056 09:26:17.269673
3057 09:26:17.269726 [DATLAT]
3058 09:26:17.269780 Freq=1200, CH0 RK1
3059 09:26:17.269833
3060 09:26:17.269887 DATLAT Default: 0xd
3061 09:26:17.269940 0, 0xFFFF, sum = 0
3062 09:26:17.269995 1, 0xFFFF, sum = 0
3063 09:26:17.270049 2, 0xFFFF, sum = 0
3064 09:26:17.270103 3, 0xFFFF, sum = 0
3065 09:26:17.270157 4, 0xFFFF, sum = 0
3066 09:26:17.270212 5, 0xFFFF, sum = 0
3067 09:26:17.270266 6, 0xFFFF, sum = 0
3068 09:26:17.270349 7, 0xFFFF, sum = 0
3069 09:26:17.270404 8, 0xFFFF, sum = 0
3070 09:26:17.270458 9, 0xFFFF, sum = 0
3071 09:26:17.270513 10, 0xFFFF, sum = 0
3072 09:26:17.270567 11, 0xFFFF, sum = 0
3073 09:26:17.270621 12, 0x0, sum = 1
3074 09:26:17.270676 13, 0x0, sum = 2
3075 09:26:17.270759 14, 0x0, sum = 3
3076 09:26:17.270813 15, 0x0, sum = 4
3077 09:26:17.270867 best_step = 13
3078 09:26:17.270920
3079 09:26:17.270973 ==
3080 09:26:17.271026 Dram Type= 6, Freq= 0, CH_0, rank 1
3081 09:26:17.271080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 09:26:17.271360 ==
3083 09:26:17.271423 RX Vref Scan: 0
3084 09:26:17.271478
3085 09:26:17.271533 RX Vref 0 -> 0, step: 1
3086 09:26:17.271588
3087 09:26:17.271642 RX Delay -21 -> 252, step: 4
3088 09:26:17.271697 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3089 09:26:17.271752 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3090 09:26:17.271821 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3091 09:26:17.271874 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3092 09:26:17.271928 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3093 09:26:17.271981 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3094 09:26:17.272034 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3095 09:26:17.272087 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3096 09:26:17.272140 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3097 09:26:17.272193 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3098 09:26:17.272247 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3099 09:26:17.272301 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3100 09:26:17.272354 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3101 09:26:17.272408 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3102 09:26:17.272461 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3103 09:26:17.272514 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3104 09:26:17.272609 ==
3105 09:26:17.272665 Dram Type= 6, Freq= 0, CH_0, rank 1
3106 09:26:17.272718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 09:26:17.272775 ==
3108 09:26:17.272829 DQS Delay:
3109 09:26:17.272884 DQS0 = 0, DQS1 = 0
3110 09:26:17.272938 DQM Delay:
3111 09:26:17.272993 DQM0 = 119, DQM1 = 107
3112 09:26:17.273046 DQ Delay:
3113 09:26:17.273111 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =116
3114 09:26:17.273170 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3115 09:26:17.273225 DQ8 =98, DQ9 =96, DQ10 =108, DQ11 =104
3116 09:26:17.273280 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3117 09:26:17.273334
3118 09:26:17.273389
3119 09:26:17.273444 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 401 ps
3120 09:26:17.273501 CH0 RK1: MR19=403, MR18=15FB
3121 09:26:17.273557 CH0_RK1: MR19=0x403, MR18=0x15FB, DQSOSC=401, MR23=63, INC=40, DEC=27
3122 09:26:17.273613 [RxdqsGatingPostProcess] freq 1200
3123 09:26:17.273668 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3124 09:26:17.273723 best DQS0 dly(2T, 0.5T) = (0, 11)
3125 09:26:17.273778 best DQS1 dly(2T, 0.5T) = (0, 12)
3126 09:26:17.273833 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3127 09:26:17.273918 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3128 09:26:17.273974 best DQS0 dly(2T, 0.5T) = (0, 11)
3129 09:26:17.274030 best DQS1 dly(2T, 0.5T) = (0, 11)
3130 09:26:17.274085 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3131 09:26:17.274140 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3132 09:26:17.274196 Pre-setting of DQS Precalculation
3133 09:26:17.274252 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3134 09:26:17.274306 ==
3135 09:26:17.274362 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 09:26:17.274417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 09:26:17.274473 ==
3138 09:26:17.274528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3139 09:26:17.274584 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3140 09:26:17.274640 [CA 0] Center 37 (7~68) winsize 62
3141 09:26:17.274696 [CA 1] Center 37 (7~68) winsize 62
3142 09:26:17.274750 [CA 2] Center 35 (5~65) winsize 61
3143 09:26:17.274836 [CA 3] Center 34 (4~65) winsize 62
3144 09:26:17.274891 [CA 4] Center 34 (4~64) winsize 61
3145 09:26:17.274946 [CA 5] Center 33 (3~64) winsize 62
3146 09:26:17.275000
3147 09:26:17.275055 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3148 09:26:17.275158
3149 09:26:17.275243 [CATrainingPosCal] consider 1 rank data
3150 09:26:17.275307 u2DelayCellTimex100 = 270/100 ps
3151 09:26:17.275364 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3152 09:26:17.275421 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3153 09:26:17.275476 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3154 09:26:17.275533 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3155 09:26:17.275588 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3156 09:26:17.275643 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3157 09:26:17.275698
3158 09:26:17.275753 CA PerBit enable=1, Macro0, CA PI delay=33
3159 09:26:17.275809
3160 09:26:17.275865 [CBTSetCACLKResult] CA Dly = 33
3161 09:26:17.275920 CS Dly: 5 (0~36)
3162 09:26:17.275975 ==
3163 09:26:17.276030 Dram Type= 6, Freq= 0, CH_1, rank 1
3164 09:26:17.276085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 09:26:17.276141 ==
3166 09:26:17.276196 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3167 09:26:17.276252 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3168 09:26:17.276307 [CA 0] Center 38 (8~68) winsize 61
3169 09:26:17.276363 [CA 1] Center 38 (7~69) winsize 63
3170 09:26:17.276417 [CA 2] Center 35 (5~66) winsize 62
3171 09:26:17.276473 [CA 3] Center 35 (5~65) winsize 61
3172 09:26:17.276528 [CA 4] Center 34 (4~64) winsize 61
3173 09:26:17.276630 [CA 5] Center 34 (4~64) winsize 61
3174 09:26:17.276686
3175 09:26:17.276741 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3176 09:26:17.276797
3177 09:26:17.276851 [CATrainingPosCal] consider 2 rank data
3178 09:26:17.276906 u2DelayCellTimex100 = 270/100 ps
3179 09:26:17.276962 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3180 09:26:17.277018 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3181 09:26:17.277089 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3182 09:26:17.277159 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3183 09:26:17.277214 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3184 09:26:17.277270 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3185 09:26:17.277324
3186 09:26:17.277379 CA PerBit enable=1, Macro0, CA PI delay=34
3187 09:26:17.277434
3188 09:26:17.277489 [CBTSetCACLKResult] CA Dly = 34
3189 09:26:17.277545 CS Dly: 6 (0~39)
3190 09:26:17.277600
3191 09:26:17.277655 ----->DramcWriteLeveling(PI) begin...
3192 09:26:17.277710 ==
3193 09:26:17.277766 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 09:26:17.277821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 09:26:17.277877 ==
3196 09:26:17.277932 Write leveling (Byte 0): 26 => 26
3197 09:26:17.277988 Write leveling (Byte 1): 28 => 28
3198 09:26:17.278043 DramcWriteLeveling(PI) end<-----
3199 09:26:17.278098
3200 09:26:17.278152 ==
3201 09:26:17.278207 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 09:26:17.278262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 09:26:17.278318 ==
3204 09:26:17.278372 [Gating] SW mode calibration
3205 09:26:17.278650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3206 09:26:17.278729 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3207 09:26:17.278790 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 09:26:17.278847 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 09:26:17.278904 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 09:26:17.278971 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 09:26:17.279028 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 09:26:17.279088 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3213 09:26:17.279145 0 15 24 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (1 0)
3214 09:26:17.279201 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 09:26:17.279257 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 09:26:17.279313 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 09:26:17.279370 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 09:26:17.279426 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 09:26:17.279482 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 09:26:17.279538 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 09:26:17.279594 1 0 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3222 09:26:17.279649 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 09:26:17.279704 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 09:26:17.279760 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 09:26:17.279815 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 09:26:17.279871 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 09:26:17.279927 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 09:26:17.279982 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3229 09:26:17.280038 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3230 09:26:17.280094 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3231 09:26:17.280150 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 09:26:17.280204 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 09:26:17.280260 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 09:26:17.280315 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 09:26:17.280371 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 09:26:17.280426 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 09:26:17.280482 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 09:26:17.280537 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 09:26:17.280635 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 09:26:17.280691 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 09:26:17.280764 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 09:26:17.280864 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 09:26:17.280920 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 09:26:17.280975 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3245 09:26:17.281031 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3246 09:26:17.281149 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3247 09:26:17.281232 Total UI for P1: 0, mck2ui 16
3248 09:26:17.281291 best dqsien dly found for B0: ( 1, 3, 22)
3249 09:26:17.281348 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3250 09:26:17.281405 Total UI for P1: 0, mck2ui 16
3251 09:26:17.281461 best dqsien dly found for B1: ( 1, 3, 26)
3252 09:26:17.281517 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3253 09:26:17.281572 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3254 09:26:17.281628
3255 09:26:17.281682 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3256 09:26:17.281738 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3257 09:26:17.281794 [Gating] SW calibration Done
3258 09:26:17.281849 ==
3259 09:26:17.281905 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 09:26:17.281961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 09:26:17.282017 ==
3262 09:26:17.282072 RX Vref Scan: 0
3263 09:26:17.282127
3264 09:26:17.282182 RX Vref 0 -> 0, step: 1
3265 09:26:17.282237
3266 09:26:17.282292 RX Delay -40 -> 252, step: 8
3267 09:26:17.282347 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3268 09:26:17.282403 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3269 09:26:17.282460 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3270 09:26:17.282516 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3271 09:26:17.282571 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3272 09:26:17.282626 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3273 09:26:17.282681 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3274 09:26:17.282736 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3275 09:26:17.282791 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3276 09:26:17.282846 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3277 09:26:17.282903 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3278 09:26:17.282960 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3279 09:26:17.283016 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3280 09:26:17.283071 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3281 09:26:17.283126 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3282 09:26:17.283181 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3283 09:26:17.283236 ==
3284 09:26:17.283291 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 09:26:17.283347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 09:26:17.283431 ==
3287 09:26:17.283486 DQS Delay:
3288 09:26:17.283540 DQS0 = 0, DQS1 = 0
3289 09:26:17.283596 DQM Delay:
3290 09:26:17.283651 DQM0 = 119, DQM1 = 113
3291 09:26:17.283705 DQ Delay:
3292 09:26:17.283760 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3293 09:26:17.283815 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3294 09:26:17.283870 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3295 09:26:17.283925 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3296 09:26:17.284008
3297 09:26:17.284063
3298 09:26:17.284117 ==
3299 09:26:17.284173 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 09:26:17.284229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 09:26:17.284285 ==
3302 09:26:17.284340
3303 09:26:17.284394
3304 09:26:17.284449 TX Vref Scan disable
3305 09:26:17.284504 == TX Byte 0 ==
3306 09:26:17.284584 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3307 09:26:17.284655 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3308 09:26:17.284710 == TX Byte 1 ==
3309 09:26:17.284766 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3310 09:26:17.285021 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3311 09:26:17.285085 ==
3312 09:26:17.285142 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 09:26:17.285198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 09:26:17.285254 ==
3315 09:26:17.285309 TX Vref=22, minBit 10, minWin=24, winSum=406
3316 09:26:17.285366 TX Vref=24, minBit 10, minWin=24, winSum=410
3317 09:26:17.285422 TX Vref=26, minBit 3, minWin=25, winSum=414
3318 09:26:17.285477 TX Vref=28, minBit 10, minWin=25, winSum=422
3319 09:26:17.285533 TX Vref=30, minBit 10, minWin=25, winSum=424
3320 09:26:17.285589 TX Vref=32, minBit 10, minWin=25, winSum=425
3321 09:26:17.285645 [TxChooseVref] Worse bit 10, Min win 25, Win sum 425, Final Vref 32
3322 09:26:17.285701
3323 09:26:17.285756 Final TX Range 1 Vref 32
3324 09:26:17.285811
3325 09:26:17.285866 ==
3326 09:26:17.285921 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 09:26:17.285977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 09:26:17.286033 ==
3329 09:26:17.286088
3330 09:26:17.286143
3331 09:26:17.286197 TX Vref Scan disable
3332 09:26:17.286252 == TX Byte 0 ==
3333 09:26:17.286308 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3334 09:26:17.286363 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3335 09:26:17.286419 == TX Byte 1 ==
3336 09:26:17.286474 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3337 09:26:17.286530 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3338 09:26:17.286585
3339 09:26:17.286640 [DATLAT]
3340 09:26:17.286696 Freq=1200, CH1 RK0
3341 09:26:17.286751
3342 09:26:17.286806 DATLAT Default: 0xd
3343 09:26:17.286861 0, 0xFFFF, sum = 0
3344 09:26:17.286917 1, 0xFFFF, sum = 0
3345 09:26:17.286974 2, 0xFFFF, sum = 0
3346 09:26:17.287031 3, 0xFFFF, sum = 0
3347 09:26:17.287087 4, 0xFFFF, sum = 0
3348 09:26:17.287180 5, 0xFFFF, sum = 0
3349 09:26:17.287236 6, 0xFFFF, sum = 0
3350 09:26:17.287293 7, 0xFFFF, sum = 0
3351 09:26:17.287349 8, 0xFFFF, sum = 0
3352 09:26:17.287404 9, 0xFFFF, sum = 0
3353 09:26:17.287460 10, 0xFFFF, sum = 0
3354 09:26:17.287516 11, 0xFFFF, sum = 0
3355 09:26:17.287572 12, 0x0, sum = 1
3356 09:26:17.287628 13, 0x0, sum = 2
3357 09:26:17.287684 14, 0x0, sum = 3
3358 09:26:17.287740 15, 0x0, sum = 4
3359 09:26:17.287796 best_step = 13
3360 09:26:17.287851
3361 09:26:17.287905 ==
3362 09:26:17.287958 Dram Type= 6, Freq= 0, CH_1, rank 0
3363 09:26:17.288012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3364 09:26:17.288065 ==
3365 09:26:17.288118 RX Vref Scan: 1
3366 09:26:17.288171
3367 09:26:17.288224 Set Vref Range= 32 -> 127
3368 09:26:17.288277
3369 09:26:17.288330 RX Vref 32 -> 127, step: 1
3370 09:26:17.288383
3371 09:26:17.288436 RX Delay -13 -> 252, step: 4
3372 09:26:17.288489
3373 09:26:17.288542 Set Vref, RX VrefLevel [Byte0]: 32
3374 09:26:17.288643 [Byte1]: 32
3375 09:26:17.288697
3376 09:26:17.288750 Set Vref, RX VrefLevel [Byte0]: 33
3377 09:26:17.288804 [Byte1]: 33
3378 09:26:17.288857
3379 09:26:17.288911 Set Vref, RX VrefLevel [Byte0]: 34
3380 09:26:17.288964 [Byte1]: 34
3381 09:26:17.289017
3382 09:26:17.289070 Set Vref, RX VrefLevel [Byte0]: 35
3383 09:26:17.289124 [Byte1]: 35
3384 09:26:17.289177
3385 09:26:17.289230 Set Vref, RX VrefLevel [Byte0]: 36
3386 09:26:17.289283 [Byte1]: 36
3387 09:26:17.289336
3388 09:26:17.289389 Set Vref, RX VrefLevel [Byte0]: 37
3389 09:26:17.289442 [Byte1]: 37
3390 09:26:17.289495
3391 09:26:17.289548 Set Vref, RX VrefLevel [Byte0]: 38
3392 09:26:17.289601 [Byte1]: 38
3393 09:26:17.289654
3394 09:26:17.289706 Set Vref, RX VrefLevel [Byte0]: 39
3395 09:26:17.289759 [Byte1]: 39
3396 09:26:17.289813
3397 09:26:17.289866 Set Vref, RX VrefLevel [Byte0]: 40
3398 09:26:17.289919 [Byte1]: 40
3399 09:26:17.289972
3400 09:26:17.290025 Set Vref, RX VrefLevel [Byte0]: 41
3401 09:26:17.290078 [Byte1]: 41
3402 09:26:17.290132
3403 09:26:17.290185 Set Vref, RX VrefLevel [Byte0]: 42
3404 09:26:17.290238 [Byte1]: 42
3405 09:26:17.290292
3406 09:26:17.290345 Set Vref, RX VrefLevel [Byte0]: 43
3407 09:26:17.290399 [Byte1]: 43
3408 09:26:17.290452
3409 09:26:17.290505 Set Vref, RX VrefLevel [Byte0]: 44
3410 09:26:17.290559 [Byte1]: 44
3411 09:26:17.290648
3412 09:26:17.290721 Set Vref, RX VrefLevel [Byte0]: 45
3413 09:26:17.290824 [Byte1]: 45
3414 09:26:17.290878
3415 09:26:17.290931 Set Vref, RX VrefLevel [Byte0]: 46
3416 09:26:17.291020 [Byte1]: 46
3417 09:26:17.291073
3418 09:26:17.291127 Set Vref, RX VrefLevel [Byte0]: 47
3419 09:26:17.291180 [Byte1]: 47
3420 09:26:17.291233
3421 09:26:17.291286 Set Vref, RX VrefLevel [Byte0]: 48
3422 09:26:17.291339 [Byte1]: 48
3423 09:26:17.291392
3424 09:26:17.291444 Set Vref, RX VrefLevel [Byte0]: 49
3425 09:26:17.291498 [Byte1]: 49
3426 09:26:17.291551
3427 09:26:17.291604 Set Vref, RX VrefLevel [Byte0]: 50
3428 09:26:17.291657 [Byte1]: 50
3429 09:26:17.291710
3430 09:26:17.291763 Set Vref, RX VrefLevel [Byte0]: 51
3431 09:26:17.291816 [Byte1]: 51
3432 09:26:17.291870
3433 09:26:17.291923 Set Vref, RX VrefLevel [Byte0]: 52
3434 09:26:17.291976 [Byte1]: 52
3435 09:26:17.292029
3436 09:26:17.292082 Set Vref, RX VrefLevel [Byte0]: 53
3437 09:26:17.292135 [Byte1]: 53
3438 09:26:17.292188
3439 09:26:17.292242 Set Vref, RX VrefLevel [Byte0]: 54
3440 09:26:17.292295 [Byte1]: 54
3441 09:26:17.292349
3442 09:26:17.292402 Set Vref, RX VrefLevel [Byte0]: 55
3443 09:26:17.292455 [Byte1]: 55
3444 09:26:17.292508
3445 09:26:17.292593 Set Vref, RX VrefLevel [Byte0]: 56
3446 09:26:17.292662 [Byte1]: 56
3447 09:26:17.292716
3448 09:26:17.292769 Set Vref, RX VrefLevel [Byte0]: 57
3449 09:26:17.292826 [Byte1]: 57
3450 09:26:17.292883
3451 09:26:17.292953 Set Vref, RX VrefLevel [Byte0]: 58
3452 09:26:17.293007 [Byte1]: 58
3453 09:26:17.293063
3454 09:26:17.293116 Set Vref, RX VrefLevel [Byte0]: 59
3455 09:26:17.293169 [Byte1]: 59
3456 09:26:17.293229
3457 09:26:17.293283 Set Vref, RX VrefLevel [Byte0]: 60
3458 09:26:17.293337 [Byte1]: 60
3459 09:26:17.293393
3460 09:26:17.293446 Set Vref, RX VrefLevel [Byte0]: 61
3461 09:26:17.293499 [Byte1]: 61
3462 09:26:17.293552
3463 09:26:17.293609 Set Vref, RX VrefLevel [Byte0]: 62
3464 09:26:17.293662 [Byte1]: 62
3465 09:26:17.293714
3466 09:26:17.293769 Set Vref, RX VrefLevel [Byte0]: 63
3467 09:26:17.293822 [Byte1]: 63
3468 09:26:17.293875
3469 09:26:17.293927 Set Vref, RX VrefLevel [Byte0]: 64
3470 09:26:17.293984 [Byte1]: 64
3471 09:26:17.294037
3472 09:26:17.294090 Set Vref, RX VrefLevel [Byte0]: 65
3473 09:26:17.294145 [Byte1]: 65
3474 09:26:17.294197
3475 09:26:17.294250 Set Vref, RX VrefLevel [Byte0]: 66
3476 09:26:17.294499 [Byte1]: 66
3477 09:26:17.294560
3478 09:26:17.294614 Set Vref, RX VrefLevel [Byte0]: 67
3479 09:26:17.294668 [Byte1]: 67
3480 09:26:17.294722
3481 09:26:17.294774 Final RX Vref Byte 0 = 51 to rank0
3482 09:26:17.294828 Final RX Vref Byte 1 = 53 to rank0
3483 09:26:17.294882 Final RX Vref Byte 0 = 51 to rank1
3484 09:26:17.294936 Final RX Vref Byte 1 = 53 to rank1==
3485 09:26:17.294989 Dram Type= 6, Freq= 0, CH_1, rank 0
3486 09:26:17.295042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 09:26:17.295096 ==
3488 09:26:17.295149 DQS Delay:
3489 09:26:17.295204 DQS0 = 0, DQS1 = 0
3490 09:26:17.295258 DQM Delay:
3491 09:26:17.295311 DQM0 = 119, DQM1 = 112
3492 09:26:17.295364 DQ Delay:
3493 09:26:17.295418 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3494 09:26:17.295471 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3495 09:26:17.295525 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3496 09:26:17.295578 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3497 09:26:17.295631
3498 09:26:17.295684
3499 09:26:17.295738 [DQSOSCAuto] RK0, (LSB)MR18= 0x71a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 407 ps
3500 09:26:17.295793 CH1 RK0: MR19=404, MR18=71A
3501 09:26:17.295846 CH1_RK0: MR19=0x404, MR18=0x71A, DQSOSC=400, MR23=63, INC=40, DEC=27
3502 09:26:17.295900
3503 09:26:17.295953 ----->DramcWriteLeveling(PI) begin...
3504 09:26:17.296007 ==
3505 09:26:17.296060 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 09:26:17.296113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 09:26:17.296167 ==
3508 09:26:17.296220 Write leveling (Byte 0): 25 => 25
3509 09:26:17.296274 Write leveling (Byte 1): 29 => 29
3510 09:26:17.296328 DramcWriteLeveling(PI) end<-----
3511 09:26:17.296381
3512 09:26:17.296433 ==
3513 09:26:17.296486 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 09:26:17.296539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 09:26:17.296642 ==
3516 09:26:17.296696 [Gating] SW mode calibration
3517 09:26:17.296750 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3518 09:26:17.296804 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3519 09:26:17.296859 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 09:26:17.296913 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 09:26:17.296967 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 09:26:17.297021 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 09:26:17.297075 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 09:26:17.297128 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 09:26:17.297181 0 15 24 | B1->B0 | 2626 3434 | 1 1 | (1 0) (1 0)
3526 09:26:17.297234 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 0)
3527 09:26:17.297288 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 09:26:17.297346 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 09:26:17.297401 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 09:26:17.297455 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 09:26:17.297509 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 09:26:17.297562 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3533 09:26:17.297616 1 0 24 | B1->B0 | 3939 2828 | 0 0 | (0 0) (0 0)
3534 09:26:17.297669 1 0 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (1 1)
3535 09:26:17.297722 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 09:26:17.297775 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 09:26:17.297829 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 09:26:17.297882 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 09:26:17.297936 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 09:26:17.297989 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 09:26:17.298043 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3542 09:26:17.298096 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3543 09:26:17.298150 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 09:26:17.298203 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 09:26:17.298256 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 09:26:17.298309 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 09:26:17.298363 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 09:26:17.298417 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 09:26:17.298470 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 09:26:17.298524 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 09:26:17.298578 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 09:26:17.298631 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 09:26:17.298684 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 09:26:17.298737 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 09:26:17.298790 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 09:26:17.298844 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 09:26:17.298897 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3558 09:26:17.298950 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3559 09:26:17.299003 Total UI for P1: 0, mck2ui 16
3560 09:26:17.299057 best dqsien dly found for B0: ( 1, 3, 24)
3561 09:26:17.299111 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3562 09:26:17.299165 Total UI for P1: 0, mck2ui 16
3563 09:26:17.299218 best dqsien dly found for B1: ( 1, 3, 26)
3564 09:26:17.299273 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3565 09:26:17.299326 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3566 09:26:17.299380
3567 09:26:17.299433 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3568 09:26:17.299486 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3569 09:26:17.299540 [Gating] SW calibration Done
3570 09:26:17.299593 ==
3571 09:26:17.299647 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 09:26:17.299701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 09:26:17.299754 ==
3574 09:26:17.299807 RX Vref Scan: 0
3575 09:26:17.299860
3576 09:26:17.299913 RX Vref 0 -> 0, step: 1
3577 09:26:17.299966
3578 09:26:17.300020 RX Delay -40 -> 252, step: 8
3579 09:26:17.300073 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3580 09:26:17.300126 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3581 09:26:17.300180 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3582 09:26:17.300233 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3583 09:26:17.300479 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3584 09:26:17.300539 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3585 09:26:17.300635 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3586 09:26:17.300689 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3587 09:26:17.300743 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3588 09:26:17.300797 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3589 09:26:17.300852 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3590 09:26:17.300905 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3591 09:26:17.300959 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3592 09:26:17.301013 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3593 09:26:17.301066 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3594 09:26:17.301120 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3595 09:26:17.301173 ==
3596 09:26:17.301227 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 09:26:17.301281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 09:26:17.301335 ==
3599 09:26:17.301389 DQS Delay:
3600 09:26:17.301443 DQS0 = 0, DQS1 = 0
3601 09:26:17.301505 DQM Delay:
3602 09:26:17.301562 DQM0 = 120, DQM1 = 112
3603 09:26:17.301615 DQ Delay:
3604 09:26:17.301669 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3605 09:26:17.301723 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3606 09:26:17.301776 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3607 09:26:17.301830 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3608 09:26:17.301883
3609 09:26:17.301936
3610 09:26:17.301989 ==
3611 09:26:17.302043 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 09:26:17.302096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 09:26:17.302150 ==
3614 09:26:17.302203
3615 09:26:17.302256
3616 09:26:17.302308 TX Vref Scan disable
3617 09:26:17.302362 == TX Byte 0 ==
3618 09:26:17.302415 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3619 09:26:17.302470 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3620 09:26:17.302524 == TX Byte 1 ==
3621 09:26:17.302577 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3622 09:26:17.302630 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3623 09:26:17.302684 ==
3624 09:26:17.302737 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 09:26:17.302789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 09:26:17.302842 ==
3627 09:26:17.302896 TX Vref=22, minBit 1, minWin=25, winSum=418
3628 09:26:17.302949 TX Vref=24, minBit 1, minWin=25, winSum=415
3629 09:26:17.303003 TX Vref=26, minBit 1, minWin=26, winSum=427
3630 09:26:17.303057 TX Vref=28, minBit 1, minWin=26, winSum=428
3631 09:26:17.303110 TX Vref=30, minBit 1, minWin=26, winSum=430
3632 09:26:17.303163 TX Vref=32, minBit 1, minWin=26, winSum=426
3633 09:26:17.303216 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3634 09:26:17.303270
3635 09:26:17.303323 Final TX Range 1 Vref 30
3636 09:26:17.303376
3637 09:26:17.303429 ==
3638 09:26:17.303482 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 09:26:17.303536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 09:26:17.303590 ==
3641 09:26:17.303643
3642 09:26:17.303695
3643 09:26:17.303748 TX Vref Scan disable
3644 09:26:17.303802 == TX Byte 0 ==
3645 09:26:17.303855 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3646 09:26:17.303909 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3647 09:26:17.303962 == TX Byte 1 ==
3648 09:26:17.304015 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3649 09:26:17.304068 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3650 09:26:17.304122
3651 09:26:17.304175 [DATLAT]
3652 09:26:17.304227 Freq=1200, CH1 RK1
3653 09:26:17.304281
3654 09:26:17.304334 DATLAT Default: 0xd
3655 09:26:17.304386 0, 0xFFFF, sum = 0
3656 09:26:17.304440 1, 0xFFFF, sum = 0
3657 09:26:17.304494 2, 0xFFFF, sum = 0
3658 09:26:17.304556 3, 0xFFFF, sum = 0
3659 09:26:17.304647 4, 0xFFFF, sum = 0
3660 09:26:17.304701 5, 0xFFFF, sum = 0
3661 09:26:17.304755 6, 0xFFFF, sum = 0
3662 09:26:17.304809 7, 0xFFFF, sum = 0
3663 09:26:17.304865 8, 0xFFFF, sum = 0
3664 09:26:17.304919 9, 0xFFFF, sum = 0
3665 09:26:17.304973 10, 0xFFFF, sum = 0
3666 09:26:17.305031 11, 0xFFFF, sum = 0
3667 09:26:17.305085 12, 0x0, sum = 1
3668 09:26:17.305140 13, 0x0, sum = 2
3669 09:26:17.305194 14, 0x0, sum = 3
3670 09:26:17.305248 15, 0x0, sum = 4
3671 09:26:17.305301 best_step = 13
3672 09:26:17.305354
3673 09:26:17.305407 ==
3674 09:26:17.305461 Dram Type= 6, Freq= 0, CH_1, rank 1
3675 09:26:17.305514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3676 09:26:17.305569 ==
3677 09:26:17.305623 RX Vref Scan: 0
3678 09:26:17.305676
3679 09:26:17.305732 RX Vref 0 -> 0, step: 1
3680 09:26:17.305786
3681 09:26:17.305839 RX Delay -13 -> 252, step: 4
3682 09:26:17.305892 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3683 09:26:17.305947 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3684 09:26:17.306001 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3685 09:26:17.306055 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3686 09:26:17.306108 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3687 09:26:17.306162 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3688 09:26:17.306215 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3689 09:26:17.306269 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3690 09:26:17.306323 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3691 09:26:17.306376 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3692 09:26:17.306429 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3693 09:26:17.306482 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3694 09:26:17.306535 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3695 09:26:17.306589 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3696 09:26:17.306641 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3697 09:26:17.306695 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3698 09:26:17.306748 ==
3699 09:26:17.306802 Dram Type= 6, Freq= 0, CH_1, rank 1
3700 09:26:17.306855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3701 09:26:17.306909 ==
3702 09:26:17.306962 DQS Delay:
3703 09:26:17.307015 DQS0 = 0, DQS1 = 0
3704 09:26:17.307096 DQM Delay:
3705 09:26:17.307151 DQM0 = 119, DQM1 = 113
3706 09:26:17.307204 DQ Delay:
3707 09:26:17.307258 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3708 09:26:17.307314 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3709 09:26:17.307368 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
3710 09:26:17.307422 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3711 09:26:17.307475
3712 09:26:17.307528
3713 09:26:17.307581 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3714 09:26:17.307635 CH1 RK1: MR19=403, MR18=DF2
3715 09:26:17.307688 CH1_RK1: MR19=0x403, MR18=0xDF2, DQSOSC=405, MR23=63, INC=39, DEC=26
3716 09:26:17.307742 [RxdqsGatingPostProcess] freq 1200
3717 09:26:17.307796 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3718 09:26:17.307855 best DQS0 dly(2T, 0.5T) = (0, 11)
3719 09:26:17.307910 best DQS1 dly(2T, 0.5T) = (0, 11)
3720 09:26:17.307963 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3721 09:26:17.308246 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3722 09:26:17.308310 best DQS0 dly(2T, 0.5T) = (0, 11)
3723 09:26:17.308367 best DQS1 dly(2T, 0.5T) = (0, 11)
3724 09:26:17.308421 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3725 09:26:17.308476 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3726 09:26:17.308530 Pre-setting of DQS Precalculation
3727 09:26:17.308633 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3728 09:26:17.308689 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3729 09:26:17.308745 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3730 09:26:17.308799
3731 09:26:17.308853
3732 09:26:17.308907 [Calibration Summary] 2400 Mbps
3733 09:26:17.308961 CH 0, Rank 0
3734 09:26:17.309015 SW Impedance : PASS
3735 09:26:17.309070 DUTY Scan : NO K
3736 09:26:17.309123 ZQ Calibration : PASS
3737 09:26:17.309177 Jitter Meter : NO K
3738 09:26:17.309231 CBT Training : PASS
3739 09:26:17.309284 Write leveling : PASS
3740 09:26:17.309338 RX DQS gating : PASS
3741 09:26:17.309392 RX DQ/DQS(RDDQC) : PASS
3742 09:26:17.309445 TX DQ/DQS : PASS
3743 09:26:17.309499 RX DATLAT : PASS
3744 09:26:17.309552 RX DQ/DQS(Engine): PASS
3745 09:26:17.309605 TX OE : NO K
3746 09:26:17.309658 All Pass.
3747 09:26:17.309712
3748 09:26:17.309766 CH 0, Rank 1
3749 09:26:17.309819 SW Impedance : PASS
3750 09:26:17.309872 DUTY Scan : NO K
3751 09:26:17.309926 ZQ Calibration : PASS
3752 09:26:17.309979 Jitter Meter : NO K
3753 09:26:17.310033 CBT Training : PASS
3754 09:26:17.310085 Write leveling : PASS
3755 09:26:17.310139 RX DQS gating : PASS
3756 09:26:17.310192 RX DQ/DQS(RDDQC) : PASS
3757 09:26:17.310246 TX DQ/DQS : PASS
3758 09:26:17.310300 RX DATLAT : PASS
3759 09:26:17.310353 RX DQ/DQS(Engine): PASS
3760 09:26:17.310406 TX OE : NO K
3761 09:26:17.310459 All Pass.
3762 09:26:17.310513
3763 09:26:17.310566 CH 1, Rank 0
3764 09:26:17.310619 SW Impedance : PASS
3765 09:26:17.310673 DUTY Scan : NO K
3766 09:26:17.310726 ZQ Calibration : PASS
3767 09:26:17.310779 Jitter Meter : NO K
3768 09:26:17.310833 CBT Training : PASS
3769 09:26:17.310886 Write leveling : PASS
3770 09:26:17.310940 RX DQS gating : PASS
3771 09:26:17.310993 RX DQ/DQS(RDDQC) : PASS
3772 09:26:17.311046 TX DQ/DQS : PASS
3773 09:26:17.311099 RX DATLAT : PASS
3774 09:26:17.311153 RX DQ/DQS(Engine): PASS
3775 09:26:17.311206 TX OE : NO K
3776 09:26:17.311258 All Pass.
3777 09:26:17.311312
3778 09:26:17.311365 CH 1, Rank 1
3779 09:26:17.311418 SW Impedance : PASS
3780 09:26:17.311472 DUTY Scan : NO K
3781 09:26:17.311524 ZQ Calibration : PASS
3782 09:26:17.311578 Jitter Meter : NO K
3783 09:26:17.311631 CBT Training : PASS
3784 09:26:17.311684 Write leveling : PASS
3785 09:26:17.311736 RX DQS gating : PASS
3786 09:26:17.311789 RX DQ/DQS(RDDQC) : PASS
3787 09:26:17.311842 TX DQ/DQS : PASS
3788 09:26:17.311896 RX DATLAT : PASS
3789 09:26:17.311949 RX DQ/DQS(Engine): PASS
3790 09:26:17.312002 TX OE : NO K
3791 09:26:17.312056 All Pass.
3792 09:26:17.312109
3793 09:26:17.312162 DramC Write-DBI off
3794 09:26:17.312215 PER_BANK_REFRESH: Hybrid Mode
3795 09:26:17.312268 TX_TRACKING: ON
3796 09:26:17.312322 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3797 09:26:17.312377 [FAST_K] Save calibration result to emmc
3798 09:26:17.312431 dramc_set_vcore_voltage set vcore to 650000
3799 09:26:17.312484 Read voltage for 600, 5
3800 09:26:17.312537 Vio18 = 0
3801 09:26:17.312642 Vcore = 650000
3802 09:26:17.312696 Vdram = 0
3803 09:26:17.312749 Vddq = 0
3804 09:26:17.312803 Vmddr = 0
3805 09:26:17.312856 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3806 09:26:17.312909 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3807 09:26:17.312963 MEM_TYPE=3, freq_sel=19
3808 09:26:17.313016 sv_algorithm_assistance_LP4_1600
3809 09:26:17.313070 ============ PULL DRAM RESETB DOWN ============
3810 09:26:17.313124 ========== PULL DRAM RESETB DOWN end =========
3811 09:26:17.313178 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3812 09:26:17.313232 ===================================
3813 09:26:17.313285 LPDDR4 DRAM CONFIGURATION
3814 09:26:17.313338 ===================================
3815 09:26:17.313391 EX_ROW_EN[0] = 0x0
3816 09:26:17.313444 EX_ROW_EN[1] = 0x0
3817 09:26:17.313498 LP4Y_EN = 0x0
3818 09:26:17.313551 WORK_FSP = 0x0
3819 09:26:17.313605 WL = 0x2
3820 09:26:17.313658 RL = 0x2
3821 09:26:17.313711 BL = 0x2
3822 09:26:17.313764 RPST = 0x0
3823 09:26:17.313817 RD_PRE = 0x0
3824 09:26:17.313869 WR_PRE = 0x1
3825 09:26:17.313922 WR_PST = 0x0
3826 09:26:17.313975 DBI_WR = 0x0
3827 09:26:17.314027 DBI_RD = 0x0
3828 09:26:17.314081 OTF = 0x1
3829 09:26:17.314135 ===================================
3830 09:26:17.314189 ===================================
3831 09:26:17.314242 ANA top config
3832 09:26:17.314295 ===================================
3833 09:26:17.314348 DLL_ASYNC_EN = 0
3834 09:26:17.314401 ALL_SLAVE_EN = 1
3835 09:26:17.314454 NEW_RANK_MODE = 1
3836 09:26:17.314508 DLL_IDLE_MODE = 1
3837 09:26:17.314561 LP45_APHY_COMB_EN = 1
3838 09:26:17.314614 TX_ODT_DIS = 1
3839 09:26:17.314668 NEW_8X_MODE = 1
3840 09:26:17.314722 ===================================
3841 09:26:17.314776 ===================================
3842 09:26:17.314829 data_rate = 1200
3843 09:26:17.314882 CKR = 1
3844 09:26:17.314935 DQ_P2S_RATIO = 8
3845 09:26:17.314988 ===================================
3846 09:26:17.315041 CA_P2S_RATIO = 8
3847 09:26:17.315094 DQ_CA_OPEN = 0
3848 09:26:17.315147 DQ_SEMI_OPEN = 0
3849 09:26:17.315200 CA_SEMI_OPEN = 0
3850 09:26:17.315253 CA_FULL_RATE = 0
3851 09:26:17.315306 DQ_CKDIV4_EN = 1
3852 09:26:17.315360 CA_CKDIV4_EN = 1
3853 09:26:17.315413 CA_PREDIV_EN = 0
3854 09:26:17.315466 PH8_DLY = 0
3855 09:26:17.315519 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3856 09:26:17.315572 DQ_AAMCK_DIV = 4
3857 09:26:17.315625 CA_AAMCK_DIV = 4
3858 09:26:17.315678 CA_ADMCK_DIV = 4
3859 09:26:17.315731 DQ_TRACK_CA_EN = 0
3860 09:26:17.315785 CA_PICK = 600
3861 09:26:17.315839 CA_MCKIO = 600
3862 09:26:17.315892 MCKIO_SEMI = 0
3863 09:26:17.315946 PLL_FREQ = 2288
3864 09:26:17.315999 DQ_UI_PI_RATIO = 32
3865 09:26:17.316053 CA_UI_PI_RATIO = 0
3866 09:26:17.316106 ===================================
3867 09:26:17.316352 ===================================
3868 09:26:17.316415 memory_type:LPDDR4
3869 09:26:17.316470 GP_NUM : 10
3870 09:26:17.316525 SRAM_EN : 1
3871 09:26:17.316628 MD32_EN : 0
3872 09:26:17.316683 ===================================
3873 09:26:17.316737 [ANA_INIT] >>>>>>>>>>>>>>
3874 09:26:17.316791 <<<<<< [CONFIGURE PHASE]: ANA_TX
3875 09:26:17.316845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3876 09:26:17.316899 ===================================
3877 09:26:17.316954 data_rate = 1200,PCW = 0X5800
3878 09:26:17.317008 ===================================
3879 09:26:17.317062 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3880 09:26:17.317116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3881 09:26:17.317170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3882 09:26:17.317224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3883 09:26:17.317277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3884 09:26:17.317331 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3885 09:26:17.317385 [ANA_INIT] flow start
3886 09:26:17.317438 [ANA_INIT] PLL >>>>>>>>
3887 09:26:17.317492 [ANA_INIT] PLL <<<<<<<<
3888 09:26:17.317545 [ANA_INIT] MIDPI >>>>>>>>
3889 09:26:17.317600 [ANA_INIT] MIDPI <<<<<<<<
3890 09:26:17.317653 [ANA_INIT] DLL >>>>>>>>
3891 09:26:17.317706 [ANA_INIT] flow end
3892 09:26:17.317759 ============ LP4 DIFF to SE enter ============
3893 09:26:17.317813 ============ LP4 DIFF to SE exit ============
3894 09:26:17.317867 [ANA_INIT] <<<<<<<<<<<<<
3895 09:26:17.317921 [Flow] Enable top DCM control >>>>>
3896 09:26:17.317974 [Flow] Enable top DCM control <<<<<
3897 09:26:17.318027 Enable DLL master slave shuffle
3898 09:26:17.318080 ==============================================================
3899 09:26:17.318134 Gating Mode config
3900 09:26:17.318188 ==============================================================
3901 09:26:17.318241 Config description:
3902 09:26:17.318294 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3903 09:26:17.318349 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3904 09:26:17.318403 SELPH_MODE 0: By rank 1: By Phase
3905 09:26:17.318457 ==============================================================
3906 09:26:17.318524 GAT_TRACK_EN = 1
3907 09:26:17.320367 RX_GATING_MODE = 2
3908 09:26:17.320429 RX_GATING_TRACK_MODE = 2
3909 09:26:17.324176 SELPH_MODE = 1
3910 09:26:17.327019 PICG_EARLY_EN = 1
3911 09:26:17.330277 VALID_LAT_VALUE = 1
3912 09:26:17.337226 ==============================================================
3913 09:26:17.340430 Enter into Gating configuration >>>>
3914 09:26:17.343859 Exit from Gating configuration <<<<
3915 09:26:17.346928 Enter into DVFS_PRE_config >>>>>
3916 09:26:17.356874 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3917 09:26:17.360572 Exit from DVFS_PRE_config <<<<<
3918 09:26:17.363787 Enter into PICG configuration >>>>
3919 09:26:17.367151 Exit from PICG configuration <<<<
3920 09:26:17.370464 [RX_INPUT] configuration >>>>>
3921 09:26:17.373537 [RX_INPUT] configuration <<<<<
3922 09:26:17.376972 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3923 09:26:17.383560 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3924 09:26:17.390406 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3925 09:26:17.396908 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3926 09:26:17.400332 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3927 09:26:17.406954 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3928 09:26:17.410287 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3929 09:26:17.416889 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3930 09:26:17.419940 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3931 09:26:17.423289 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3932 09:26:17.427182 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3933 09:26:17.433703 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3934 09:26:17.436843 ===================================
3935 09:26:17.436926 LPDDR4 DRAM CONFIGURATION
3936 09:26:17.440049 ===================================
3937 09:26:17.443426 EX_ROW_EN[0] = 0x0
3938 09:26:17.446682 EX_ROW_EN[1] = 0x0
3939 09:26:17.446765 LP4Y_EN = 0x0
3940 09:26:17.450508 WORK_FSP = 0x0
3941 09:26:17.450591 WL = 0x2
3942 09:26:17.453356 RL = 0x2
3943 09:26:17.453440 BL = 0x2
3944 09:26:17.457123 RPST = 0x0
3945 09:26:17.457208 RD_PRE = 0x0
3946 09:26:17.460470 WR_PRE = 0x1
3947 09:26:17.460593 WR_PST = 0x0
3948 09:26:17.463644 DBI_WR = 0x0
3949 09:26:17.463746 DBI_RD = 0x0
3950 09:26:17.466958 OTF = 0x1
3951 09:26:17.470265 ===================================
3952 09:26:17.473591 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3953 09:26:17.476740 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3954 09:26:17.483625 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3955 09:26:17.486666 ===================================
3956 09:26:17.486746 LPDDR4 DRAM CONFIGURATION
3957 09:26:17.489859 ===================================
3958 09:26:17.493468 EX_ROW_EN[0] = 0x10
3959 09:26:17.496706 EX_ROW_EN[1] = 0x0
3960 09:26:17.496780 LP4Y_EN = 0x0
3961 09:26:17.499883 WORK_FSP = 0x0
3962 09:26:17.499961 WL = 0x2
3963 09:26:17.503666 RL = 0x2
3964 09:26:17.503766 BL = 0x2
3965 09:26:17.506987 RPST = 0x0
3966 09:26:17.507086 RD_PRE = 0x0
3967 09:26:17.510321 WR_PRE = 0x1
3968 09:26:17.510426 WR_PST = 0x0
3969 09:26:17.513647 DBI_WR = 0x0
3970 09:26:17.513726 DBI_RD = 0x0
3971 09:26:17.516949 OTF = 0x1
3972 09:26:17.520129 ===================================
3973 09:26:17.526699 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3974 09:26:17.529842 nWR fixed to 30
3975 09:26:17.529942 [ModeRegInit_LP4] CH0 RK0
3976 09:26:17.533184 [ModeRegInit_LP4] CH0 RK1
3977 09:26:17.536375 [ModeRegInit_LP4] CH1 RK0
3978 09:26:17.536451 [ModeRegInit_LP4] CH1 RK1
3979 09:26:17.540114 match AC timing 17
3980 09:26:17.543364 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3981 09:26:17.546700 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3982 09:26:17.553247 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3983 09:26:17.556624 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3984 09:26:17.563186 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3985 09:26:17.563286 ==
3986 09:26:17.566357 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 09:26:17.570173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 09:26:17.570246 ==
3989 09:26:17.576752 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3990 09:26:17.579903 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3991 09:26:17.584196 [CA 0] Center 36 (6~67) winsize 62
3992 09:26:17.587918 [CA 1] Center 36 (6~67) winsize 62
3993 09:26:17.591193 [CA 2] Center 34 (4~65) winsize 62
3994 09:26:17.594243 [CA 3] Center 34 (3~65) winsize 63
3995 09:26:17.597640 [CA 4] Center 34 (3~65) winsize 63
3996 09:26:17.601188 [CA 5] Center 33 (2~64) winsize 63
3997 09:26:17.601269
3998 09:26:17.604784 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3999 09:26:17.604858
4000 09:26:17.607867 [CATrainingPosCal] consider 1 rank data
4001 09:26:17.611320 u2DelayCellTimex100 = 270/100 ps
4002 09:26:17.614675 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4003 09:26:17.617902 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4004 09:26:17.624227 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4005 09:26:17.627548 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4006 09:26:17.630909 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4007 09:26:17.634226 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4008 09:26:17.634304
4009 09:26:17.637534 CA PerBit enable=1, Macro0, CA PI delay=33
4010 09:26:17.637607
4011 09:26:17.641334 [CBTSetCACLKResult] CA Dly = 33
4012 09:26:17.641410 CS Dly: 5 (0~36)
4013 09:26:17.641473 ==
4014 09:26:17.644604 Dram Type= 6, Freq= 0, CH_0, rank 1
4015 09:26:17.651185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 09:26:17.651286 ==
4017 09:26:17.654463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4018 09:26:17.660996 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4019 09:26:17.664321 [CA 0] Center 36 (6~67) winsize 62
4020 09:26:17.668110 [CA 1] Center 36 (6~67) winsize 62
4021 09:26:17.671464 [CA 2] Center 35 (5~66) winsize 62
4022 09:26:17.674260 [CA 3] Center 35 (4~66) winsize 63
4023 09:26:17.677645 [CA 4] Center 34 (3~65) winsize 63
4024 09:26:17.680911 [CA 5] Center 34 (3~65) winsize 63
4025 09:26:17.680986
4026 09:26:17.684685 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4027 09:26:17.684764
4028 09:26:17.687704 [CATrainingPosCal] consider 2 rank data
4029 09:26:17.690959 u2DelayCellTimex100 = 270/100 ps
4030 09:26:17.694740 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4031 09:26:17.697908 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4032 09:26:17.704697 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4033 09:26:17.707773 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4034 09:26:17.710999 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4035 09:26:17.714275 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4036 09:26:17.714359
4037 09:26:17.717995 CA PerBit enable=1, Macro0, CA PI delay=33
4038 09:26:17.718082
4039 09:26:17.721303 [CBTSetCACLKResult] CA Dly = 33
4040 09:26:17.721382 CS Dly: 5 (0~37)
4041 09:26:17.721447
4042 09:26:17.724544 ----->DramcWriteLeveling(PI) begin...
4043 09:26:17.727843 ==
4044 09:26:17.731154 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 09:26:17.734448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 09:26:17.734530 ==
4047 09:26:17.737754 Write leveling (Byte 0): 33 => 33
4048 09:26:17.740975 Write leveling (Byte 1): 31 => 31
4049 09:26:17.744225 DramcWriteLeveling(PI) end<-----
4050 09:26:17.744316
4051 09:26:17.744378 ==
4052 09:26:17.748034 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 09:26:17.750857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 09:26:17.750931 ==
4055 09:26:17.754148 [Gating] SW mode calibration
4056 09:26:17.761311 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4057 09:26:17.764582 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4058 09:26:17.771136 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 09:26:17.774233 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4060 09:26:17.777978 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4061 09:26:17.784102 0 9 12 | B1->B0 | 3333 2b2b | 1 0 | (1 1) (1 0)
4062 09:26:17.787945 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
4063 09:26:17.791097 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 09:26:17.797905 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 09:26:17.801108 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 09:26:17.804373 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 09:26:17.811035 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 09:26:17.814642 0 10 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
4069 09:26:17.817958 0 10 12 | B1->B0 | 2e2e 3e3e | 0 0 | (0 0) (1 1)
4070 09:26:17.824311 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4071 09:26:17.828120 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 09:26:17.831364 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 09:26:17.838059 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 09:26:17.841310 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 09:26:17.844667 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 09:26:17.847938 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 09:26:17.854570 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4078 09:26:17.857814 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4079 09:26:17.861183 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 09:26:17.868230 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 09:26:17.871410 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 09:26:17.874652 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 09:26:17.881108 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 09:26:17.884414 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 09:26:17.887664 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 09:26:17.894799 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 09:26:17.898157 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 09:26:17.901130 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 09:26:17.907846 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 09:26:17.911485 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 09:26:17.914574 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 09:26:17.921302 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 09:26:17.924613 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4094 09:26:17.927844 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4095 09:26:17.931196 Total UI for P1: 0, mck2ui 16
4096 09:26:17.934408 best dqsien dly found for B0: ( 0, 13, 12)
4097 09:26:17.941154 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4098 09:26:17.941234 Total UI for P1: 0, mck2ui 16
4099 09:26:17.944276 best dqsien dly found for B1: ( 0, 13, 16)
4100 09:26:17.950854 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4101 09:26:17.954115 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4102 09:26:17.954206
4103 09:26:17.957944 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4104 09:26:17.961315 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4105 09:26:17.964535 [Gating] SW calibration Done
4106 09:26:17.964645 ==
4107 09:26:17.967743 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 09:26:17.971121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 09:26:17.971219 ==
4110 09:26:17.974277 RX Vref Scan: 0
4111 09:26:17.974374
4112 09:26:17.974465 RX Vref 0 -> 0, step: 1
4113 09:26:17.974551
4114 09:26:17.977480 RX Delay -230 -> 252, step: 16
4115 09:26:17.980775 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4116 09:26:17.987866 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4117 09:26:17.991074 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4118 09:26:17.994441 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4119 09:26:17.997874 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4120 09:26:18.004215 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4121 09:26:18.007802 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4122 09:26:18.011237 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4123 09:26:18.014319 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4124 09:26:18.017402 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4125 09:26:18.024169 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4126 09:26:18.027489 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4127 09:26:18.030847 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4128 09:26:18.034297 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4129 09:26:18.041199 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4130 09:26:18.044487 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4131 09:26:18.044628 ==
4132 09:26:18.047782 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 09:26:18.050846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 09:26:18.050947 ==
4135 09:26:18.054172 DQS Delay:
4136 09:26:18.054287 DQS0 = 0, DQS1 = 0
4137 09:26:18.054368 DQM Delay:
4138 09:26:18.057477 DQM0 = 49, DQM1 = 40
4139 09:26:18.057551 DQ Delay:
4140 09:26:18.060717 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =41
4141 09:26:18.063936 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4142 09:26:18.067236 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4143 09:26:18.070913 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41
4144 09:26:18.071012
4145 09:26:18.071091
4146 09:26:18.071187 ==
4147 09:26:18.074180 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 09:26:18.080774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 09:26:18.080851 ==
4150 09:26:18.080937
4151 09:26:18.081014
4152 09:26:18.081088 TX Vref Scan disable
4153 09:26:18.084369 == TX Byte 0 ==
4154 09:26:18.087725 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4155 09:26:18.094353 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4156 09:26:18.094434 == TX Byte 1 ==
4157 09:26:18.097709 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4158 09:26:18.100991 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4159 09:26:18.104279 ==
4160 09:26:18.107487 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 09:26:18.110712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 09:26:18.110819 ==
4163 09:26:18.110923
4164 09:26:18.111022
4165 09:26:18.114362 TX Vref Scan disable
4166 09:26:18.114475 == TX Byte 0 ==
4167 09:26:18.120822 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4168 09:26:18.123909 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4169 09:26:18.127426 == TX Byte 1 ==
4170 09:26:18.130687 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4171 09:26:18.134002 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4172 09:26:18.134102
4173 09:26:18.134203 [DATLAT]
4174 09:26:18.137302 Freq=600, CH0 RK0
4175 09:26:18.137409
4176 09:26:18.137508 DATLAT Default: 0x9
4177 09:26:18.140544 0, 0xFFFF, sum = 0
4178 09:26:18.140675 1, 0xFFFF, sum = 0
4179 09:26:18.144001 2, 0xFFFF, sum = 0
4180 09:26:18.147325 3, 0xFFFF, sum = 0
4181 09:26:18.147435 4, 0xFFFF, sum = 0
4182 09:26:18.150664 5, 0xFFFF, sum = 0
4183 09:26:18.150787 6, 0xFFFF, sum = 0
4184 09:26:18.153851 7, 0xFFFF, sum = 0
4185 09:26:18.153960 8, 0x0, sum = 1
4186 09:26:18.154062 9, 0x0, sum = 2
4187 09:26:18.157156 10, 0x0, sum = 3
4188 09:26:18.157263 11, 0x0, sum = 4
4189 09:26:18.160477 best_step = 9
4190 09:26:18.160671
4191 09:26:18.160767 ==
4192 09:26:18.163749 Dram Type= 6, Freq= 0, CH_0, rank 0
4193 09:26:18.167580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 09:26:18.167686 ==
4195 09:26:18.170860 RX Vref Scan: 1
4196 09:26:18.170959
4197 09:26:18.171049 RX Vref 0 -> 0, step: 1
4198 09:26:18.171140
4199 09:26:18.174184 RX Delay -179 -> 252, step: 8
4200 09:26:18.174280
4201 09:26:18.177498 Set Vref, RX VrefLevel [Byte0]: 59
4202 09:26:18.180769 [Byte1]: 50
4203 09:26:18.184479
4204 09:26:18.184604 Final RX Vref Byte 0 = 59 to rank0
4205 09:26:18.188306 Final RX Vref Byte 1 = 50 to rank0
4206 09:26:18.191104 Final RX Vref Byte 0 = 59 to rank1
4207 09:26:18.194920 Final RX Vref Byte 1 = 50 to rank1==
4208 09:26:18.198214 Dram Type= 6, Freq= 0, CH_0, rank 0
4209 09:26:18.204673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 09:26:18.204758 ==
4211 09:26:18.204825 DQS Delay:
4212 09:26:18.204886 DQS0 = 0, DQS1 = 0
4213 09:26:18.207840 DQM Delay:
4214 09:26:18.207923 DQM0 = 48, DQM1 = 38
4215 09:26:18.211157 DQ Delay:
4216 09:26:18.214833 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4217 09:26:18.214918 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4218 09:26:18.218456 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =36
4219 09:26:18.221453 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =44
4220 09:26:18.224719
4221 09:26:18.224803
4222 09:26:18.231412 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e58, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4223 09:26:18.234477 CH0 RK0: MR19=808, MR18=5E58
4224 09:26:18.241616 CH0_RK0: MR19=0x808, MR18=0x5E58, DQSOSC=392, MR23=63, INC=170, DEC=113
4225 09:26:18.241700
4226 09:26:18.244765 ----->DramcWriteLeveling(PI) begin...
4227 09:26:18.244851 ==
4228 09:26:18.248146 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 09:26:18.251432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 09:26:18.251524 ==
4231 09:26:18.254594 Write leveling (Byte 0): 32 => 32
4232 09:26:18.257875 Write leveling (Byte 1): 29 => 29
4233 09:26:18.261627 DramcWriteLeveling(PI) end<-----
4234 09:26:18.261711
4235 09:26:18.261778 ==
4236 09:26:18.264810 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 09:26:18.268173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 09:26:18.268257 ==
4239 09:26:18.271493 [Gating] SW mode calibration
4240 09:26:18.277930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4241 09:26:18.284478 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4242 09:26:18.287845 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 09:26:18.291190 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 09:26:18.297796 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4245 09:26:18.301184 0 9 12 | B1->B0 | 3333 3333 | 0 0 | (0 1) (0 1)
4246 09:26:18.304473 0 9 16 | B1->B0 | 2b2b 2525 | 1 0 | (1 0) (1 0)
4247 09:26:18.311033 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 09:26:18.314280 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 09:26:18.317524 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 09:26:18.324315 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 09:26:18.327479 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 09:26:18.330762 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 09:26:18.337796 0 10 12 | B1->B0 | 2d2d 3131 | 0 0 | (0 0) (0 0)
4254 09:26:18.340900 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4255 09:26:18.344158 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 09:26:18.350863 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 09:26:18.354051 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 09:26:18.357750 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 09:26:18.364245 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 09:26:18.367402 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 09:26:18.370661 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4262 09:26:18.377274 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 09:26:18.380477 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 09:26:18.383799 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 09:26:18.390791 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 09:26:18.394106 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 09:26:18.397395 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 09:26:18.403914 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 09:26:18.407286 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 09:26:18.410657 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 09:26:18.417273 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 09:26:18.420461 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 09:26:18.423769 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 09:26:18.430448 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 09:26:18.433847 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 09:26:18.437115 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 09:26:18.443993 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4278 09:26:18.447238 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4279 09:26:18.450505 Total UI for P1: 0, mck2ui 16
4280 09:26:18.453667 best dqsien dly found for B0: ( 0, 13, 12)
4281 09:26:18.457082 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 09:26:18.460365 Total UI for P1: 0, mck2ui 16
4283 09:26:18.463609 best dqsien dly found for B1: ( 0, 13, 16)
4284 09:26:18.467369 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4285 09:26:18.470608 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4286 09:26:18.470692
4287 09:26:18.473877 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4288 09:26:18.480505 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4289 09:26:18.480610 [Gating] SW calibration Done
4290 09:26:18.480715 ==
4291 09:26:18.483747 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 09:26:18.490236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 09:26:18.490321 ==
4294 09:26:18.490387 RX Vref Scan: 0
4295 09:26:18.490448
4296 09:26:18.493796 RX Vref 0 -> 0, step: 1
4297 09:26:18.493880
4298 09:26:18.497054 RX Delay -230 -> 252, step: 16
4299 09:26:18.500268 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4300 09:26:18.504048 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4301 09:26:18.507321 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4302 09:26:18.513726 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4303 09:26:18.517020 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4304 09:26:18.520233 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4305 09:26:18.523528 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4306 09:26:18.527362 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4307 09:26:18.533822 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4308 09:26:18.537000 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4309 09:26:18.540355 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4310 09:26:18.543681 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4311 09:26:18.550539 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4312 09:26:18.553796 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4313 09:26:18.556953 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4314 09:26:18.560738 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4315 09:26:18.560815 ==
4316 09:26:18.563985 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 09:26:18.570398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 09:26:18.570475 ==
4319 09:26:18.570540 DQS Delay:
4320 09:26:18.573690 DQS0 = 0, DQS1 = 0
4321 09:26:18.573763 DQM Delay:
4322 09:26:18.573833 DQM0 = 47, DQM1 = 42
4323 09:26:18.576964 DQ Delay:
4324 09:26:18.580750 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4325 09:26:18.583922 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4326 09:26:18.587153 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4327 09:26:18.590338 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4328 09:26:18.590413
4329 09:26:18.590476
4330 09:26:18.590542 ==
4331 09:26:18.593627 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 09:26:18.597476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 09:26:18.597550 ==
4334 09:26:18.597620
4335 09:26:18.597676
4336 09:26:18.600764 TX Vref Scan disable
4337 09:26:18.600836 == TX Byte 0 ==
4338 09:26:18.607356 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4339 09:26:18.610537 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4340 09:26:18.610616 == TX Byte 1 ==
4341 09:26:18.616881 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4342 09:26:18.620593 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4343 09:26:18.620693 ==
4344 09:26:18.623961 Dram Type= 6, Freq= 0, CH_0, rank 1
4345 09:26:18.627362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 09:26:18.627447 ==
4347 09:26:18.627517
4348 09:26:18.630633
4349 09:26:18.630716 TX Vref Scan disable
4350 09:26:18.633875 == TX Byte 0 ==
4351 09:26:18.637031 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4352 09:26:18.643944 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4353 09:26:18.644029 == TX Byte 1 ==
4354 09:26:18.647227 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4355 09:26:18.653931 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4356 09:26:18.654015
4357 09:26:18.654082 [DATLAT]
4358 09:26:18.654143 Freq=600, CH0 RK1
4359 09:26:18.654209
4360 09:26:18.657125 DATLAT Default: 0x9
4361 09:26:18.657208 0, 0xFFFF, sum = 0
4362 09:26:18.660465 1, 0xFFFF, sum = 0
4363 09:26:18.660556 2, 0xFFFF, sum = 0
4364 09:26:18.663830 3, 0xFFFF, sum = 0
4365 09:26:18.666943 4, 0xFFFF, sum = 0
4366 09:26:18.667027 5, 0xFFFF, sum = 0
4367 09:26:18.670244 6, 0xFFFF, sum = 0
4368 09:26:18.670328 7, 0xFFFF, sum = 0
4369 09:26:18.673998 8, 0x0, sum = 1
4370 09:26:18.674082 9, 0x0, sum = 2
4371 09:26:18.674147 10, 0x0, sum = 3
4372 09:26:18.677265 11, 0x0, sum = 4
4373 09:26:18.677348 best_step = 9
4374 09:26:18.677413
4375 09:26:18.677472 ==
4376 09:26:18.680468 Dram Type= 6, Freq= 0, CH_0, rank 1
4377 09:26:18.686965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 09:26:18.687048 ==
4379 09:26:18.687114 RX Vref Scan: 0
4380 09:26:18.687204
4381 09:26:18.690292 RX Vref 0 -> 0, step: 1
4382 09:26:18.690373
4383 09:26:18.693570 RX Delay -179 -> 252, step: 8
4384 09:26:18.696849 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4385 09:26:18.703893 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4386 09:26:18.707165 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4387 09:26:18.710505 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4388 09:26:18.713825 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4389 09:26:18.716987 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4390 09:26:18.720284 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4391 09:26:18.727173 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4392 09:26:18.730413 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4393 09:26:18.733640 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4394 09:26:18.736840 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4395 09:26:18.743859 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4396 09:26:18.747140 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4397 09:26:18.750416 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4398 09:26:18.753482 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4399 09:26:18.760240 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4400 09:26:18.760322 ==
4401 09:26:18.763572 Dram Type= 6, Freq= 0, CH_0, rank 1
4402 09:26:18.766824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 09:26:18.766921 ==
4404 09:26:18.766988 DQS Delay:
4405 09:26:18.770141 DQS0 = 0, DQS1 = 0
4406 09:26:18.770223 DQM Delay:
4407 09:26:18.773490 DQM0 = 48, DQM1 = 39
4408 09:26:18.773575 DQ Delay:
4409 09:26:18.776768 DQ0 =44, DQ1 =48, DQ2 =48, DQ3 =44
4410 09:26:18.780109 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4411 09:26:18.783796 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4412 09:26:18.787122 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =48
4413 09:26:18.787203
4414 09:26:18.787267
4415 09:26:18.793662 [DQSOSCAuto] RK1, (LSB)MR18= 0x6937, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4416 09:26:18.796876 CH0 RK1: MR19=808, MR18=6937
4417 09:26:18.803490 CH0_RK1: MR19=0x808, MR18=0x6937, DQSOSC=390, MR23=63, INC=172, DEC=114
4418 09:26:18.806787 [RxdqsGatingPostProcess] freq 600
4419 09:26:18.813914 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4420 09:26:18.813997 Pre-setting of DQS Precalculation
4421 09:26:18.820326 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4422 09:26:18.820408 ==
4423 09:26:18.823620 Dram Type= 6, Freq= 0, CH_1, rank 0
4424 09:26:18.826797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 09:26:18.826880 ==
4426 09:26:18.833734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4427 09:26:18.840222 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4428 09:26:18.843457 [CA 0] Center 35 (5~66) winsize 62
4429 09:26:18.846749 [CA 1] Center 35 (5~66) winsize 62
4430 09:26:18.850383 [CA 2] Center 34 (3~65) winsize 63
4431 09:26:18.853508 [CA 3] Center 33 (3~64) winsize 62
4432 09:26:18.856625 [CA 4] Center 34 (3~65) winsize 63
4433 09:26:18.860337 [CA 5] Center 33 (3~64) winsize 62
4434 09:26:18.860439
4435 09:26:18.863587 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4436 09:26:18.863659
4437 09:26:18.866805 [CATrainingPosCal] consider 1 rank data
4438 09:26:18.869938 u2DelayCellTimex100 = 270/100 ps
4439 09:26:18.873328 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 09:26:18.876526 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4441 09:26:18.880289 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4442 09:26:18.883587 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4443 09:26:18.886802 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4444 09:26:18.890019 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4445 09:26:18.890089
4446 09:26:18.897015 CA PerBit enable=1, Macro0, CA PI delay=33
4447 09:26:18.897090
4448 09:26:18.897152 [CBTSetCACLKResult] CA Dly = 33
4449 09:26:18.900291 CS Dly: 4 (0~35)
4450 09:26:18.900367 ==
4451 09:26:18.903426 Dram Type= 6, Freq= 0, CH_1, rank 1
4452 09:26:18.906821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 09:26:18.906919 ==
4454 09:26:18.913242 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4455 09:26:18.919691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4456 09:26:18.923367 [CA 0] Center 35 (5~66) winsize 62
4457 09:26:18.926606 [CA 1] Center 35 (5~66) winsize 62
4458 09:26:18.929853 [CA 2] Center 34 (4~65) winsize 62
4459 09:26:18.933114 [CA 3] Center 34 (4~64) winsize 61
4460 09:26:18.936284 [CA 4] Center 34 (4~64) winsize 61
4461 09:26:18.940051 [CA 5] Center 33 (3~64) winsize 62
4462 09:26:18.940147
4463 09:26:18.943147 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4464 09:26:18.943244
4465 09:26:18.946410 [CATrainingPosCal] consider 2 rank data
4466 09:26:18.949726 u2DelayCellTimex100 = 270/100 ps
4467 09:26:18.953399 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4468 09:26:18.956462 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4469 09:26:18.959763 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4470 09:26:18.962996 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4471 09:26:18.966638 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4472 09:26:18.969822 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4473 09:26:18.973024
4474 09:26:18.976270 CA PerBit enable=1, Macro0, CA PI delay=33
4475 09:26:18.976370
4476 09:26:18.979622 [CBTSetCACLKResult] CA Dly = 33
4477 09:26:18.979721 CS Dly: 5 (0~37)
4478 09:26:18.979811
4479 09:26:18.983395 ----->DramcWriteLeveling(PI) begin...
4480 09:26:18.983480 ==
4481 09:26:18.986735 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 09:26:18.990039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 09:26:18.993293 ==
4484 09:26:18.993390 Write leveling (Byte 0): 29 => 29
4485 09:26:18.996514 Write leveling (Byte 1): 29 => 29
4486 09:26:18.999845 DramcWriteLeveling(PI) end<-----
4487 09:26:18.999915
4488 09:26:18.999975 ==
4489 09:26:19.003224 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 09:26:19.009782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 09:26:19.009880 ==
4492 09:26:19.009972 [Gating] SW mode calibration
4493 09:26:19.019528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4494 09:26:19.023275 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4495 09:26:19.026491 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4496 09:26:19.033026 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4497 09:26:19.036324 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4498 09:26:19.039568 0 9 12 | B1->B0 | 2d2d 2a2a | 1 0 | (1 1) (1 0)
4499 09:26:19.046595 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 09:26:19.049918 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 09:26:19.053202 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 09:26:19.059515 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 09:26:19.063250 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 09:26:19.066537 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 09:26:19.072667 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4506 09:26:19.076327 0 10 12 | B1->B0 | 3939 3838 | 0 0 | (0 0) (0 0)
4507 09:26:19.079602 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 09:26:19.086051 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 09:26:19.089756 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 09:26:19.092934 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 09:26:19.099391 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 09:26:19.102758 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 09:26:19.106403 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4514 09:26:19.112908 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4515 09:26:19.116192 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 09:26:19.119413 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 09:26:19.125955 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 09:26:19.129233 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 09:26:19.132462 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 09:26:19.139064 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 09:26:19.142294 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 09:26:19.146049 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 09:26:19.149390 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 09:26:19.156291 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 09:26:19.159966 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 09:26:19.162644 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 09:26:19.169421 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 09:26:19.172528 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 09:26:19.176143 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4530 09:26:19.182827 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 09:26:19.185949 Total UI for P1: 0, mck2ui 16
4532 09:26:19.189252 best dqsien dly found for B0: ( 0, 13, 8)
4533 09:26:19.189453 Total UI for P1: 0, mck2ui 16
4534 09:26:19.196178 best dqsien dly found for B1: ( 0, 13, 10)
4535 09:26:19.199323 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4536 09:26:19.202635 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4537 09:26:19.202720
4538 09:26:19.205892 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4539 09:26:19.209562 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4540 09:26:19.212847 [Gating] SW calibration Done
4541 09:26:19.212932 ==
4542 09:26:19.216273 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 09:26:19.219499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 09:26:19.219584 ==
4545 09:26:19.222706 RX Vref Scan: 0
4546 09:26:19.222821
4547 09:26:19.222918 RX Vref 0 -> 0, step: 1
4548 09:26:19.222994
4549 09:26:19.225998 RX Delay -230 -> 252, step: 16
4550 09:26:19.229289 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4551 09:26:19.235953 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4552 09:26:19.239172 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4553 09:26:19.242884 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4554 09:26:19.246111 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4555 09:26:19.252591 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4556 09:26:19.256456 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4557 09:26:19.259651 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4558 09:26:19.262972 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4559 09:26:19.266202 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4560 09:26:19.272923 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4561 09:26:19.276264 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4562 09:26:19.279482 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4563 09:26:19.282536 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4564 09:26:19.289331 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4565 09:26:19.292583 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4566 09:26:19.292680 ==
4567 09:26:19.295856 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 09:26:19.299039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 09:26:19.299124 ==
4570 09:26:19.302826 DQS Delay:
4571 09:26:19.302910 DQS0 = 0, DQS1 = 0
4572 09:26:19.302978 DQM Delay:
4573 09:26:19.306128 DQM0 = 53, DQM1 = 43
4574 09:26:19.306212 DQ Delay:
4575 09:26:19.309310 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4576 09:26:19.312465 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4577 09:26:19.315797 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4578 09:26:19.318993 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4579 09:26:19.319064
4580 09:26:19.319128
4581 09:26:19.319190 ==
4582 09:26:19.322823 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 09:26:19.326014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 09:26:19.329314 ==
4585 09:26:19.329384
4586 09:26:19.329447
4587 09:26:19.329507 TX Vref Scan disable
4588 09:26:19.332460 == TX Byte 0 ==
4589 09:26:19.335690 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4590 09:26:19.338938 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4591 09:26:19.342270 == TX Byte 1 ==
4592 09:26:19.346123 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4593 09:26:19.349302 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4594 09:26:19.352562 ==
4595 09:26:19.355735 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 09:26:19.358946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 09:26:19.359014 ==
4598 09:26:19.359075
4599 09:26:19.359132
4600 09:26:19.362315 TX Vref Scan disable
4601 09:26:19.362385 == TX Byte 0 ==
4602 09:26:19.369324 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4603 09:26:19.372473 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4604 09:26:19.372555 == TX Byte 1 ==
4605 09:26:19.379266 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4606 09:26:19.382421 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4607 09:26:19.382497
4608 09:26:19.382559 [DATLAT]
4609 09:26:19.385690 Freq=600, CH1 RK0
4610 09:26:19.385760
4611 09:26:19.385822 DATLAT Default: 0x9
4612 09:26:19.389218 0, 0xFFFF, sum = 0
4613 09:26:19.389290 1, 0xFFFF, sum = 0
4614 09:26:19.392166 2, 0xFFFF, sum = 0
4615 09:26:19.392245 3, 0xFFFF, sum = 0
4616 09:26:19.396044 4, 0xFFFF, sum = 0
4617 09:26:19.396123 5, 0xFFFF, sum = 0
4618 09:26:19.399286 6, 0xFFFF, sum = 0
4619 09:26:19.402572 7, 0xFFFF, sum = 0
4620 09:26:19.402643 8, 0x0, sum = 1
4621 09:26:19.402706 9, 0x0, sum = 2
4622 09:26:19.405811 10, 0x0, sum = 3
4623 09:26:19.405879 11, 0x0, sum = 4
4624 09:26:19.409087 best_step = 9
4625 09:26:19.409159
4626 09:26:19.409220 ==
4627 09:26:19.412232 Dram Type= 6, Freq= 0, CH_1, rank 0
4628 09:26:19.415454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 09:26:19.415528 ==
4630 09:26:19.419345 RX Vref Scan: 1
4631 09:26:19.419417
4632 09:26:19.419477 RX Vref 0 -> 0, step: 1
4633 09:26:19.419536
4634 09:26:19.422489 RX Delay -163 -> 252, step: 8
4635 09:26:19.422558
4636 09:26:19.425840 Set Vref, RX VrefLevel [Byte0]: 51
4637 09:26:19.429138 [Byte1]: 53
4638 09:26:19.432765
4639 09:26:19.432837 Final RX Vref Byte 0 = 51 to rank0
4640 09:26:19.435918 Final RX Vref Byte 1 = 53 to rank0
4641 09:26:19.439696 Final RX Vref Byte 0 = 51 to rank1
4642 09:26:19.442900 Final RX Vref Byte 1 = 53 to rank1==
4643 09:26:19.446105 Dram Type= 6, Freq= 0, CH_1, rank 0
4644 09:26:19.452496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 09:26:19.452579 ==
4646 09:26:19.452702 DQS Delay:
4647 09:26:19.452762 DQS0 = 0, DQS1 = 0
4648 09:26:19.455829 DQM Delay:
4649 09:26:19.455899 DQM0 = 49, DQM1 = 41
4650 09:26:19.459237 DQ Delay:
4651 09:26:19.462958 DQ0 =56, DQ1 =48, DQ2 =36, DQ3 =44
4652 09:26:19.466204 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4653 09:26:19.469488 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4654 09:26:19.472236 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4655 09:26:19.472307
4656 09:26:19.472368
4657 09:26:19.479041 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4658 09:26:19.482545 CH1 RK0: MR19=808, MR18=4C73
4659 09:26:19.489110 CH1_RK0: MR19=0x808, MR18=0x4C73, DQSOSC=388, MR23=63, INC=174, DEC=116
4660 09:26:19.489191
4661 09:26:19.492571 ----->DramcWriteLeveling(PI) begin...
4662 09:26:19.492683 ==
4663 09:26:19.495620 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 09:26:19.499250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 09:26:19.499325 ==
4666 09:26:19.502500 Write leveling (Byte 0): 28 => 28
4667 09:26:19.505751 Write leveling (Byte 1): 31 => 31
4668 09:26:19.509064 DramcWriteLeveling(PI) end<-----
4669 09:26:19.509137
4670 09:26:19.509200 ==
4671 09:26:19.512369 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 09:26:19.515516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 09:26:19.515669 ==
4674 09:26:19.518986 [Gating] SW mode calibration
4675 09:26:19.525626 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4676 09:26:19.532200 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4677 09:26:19.535433 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4678 09:26:19.542456 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4679 09:26:19.545678 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4680 09:26:19.548938 0 9 12 | B1->B0 | 2727 3131 | 0 0 | (0 0) (1 1)
4681 09:26:19.552246 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 09:26:19.558744 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 09:26:19.562112 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 09:26:19.565270 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 09:26:19.572311 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 09:26:19.575717 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 09:26:19.578773 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4688 09:26:19.585513 0 10 12 | B1->B0 | 3a3a 2f2f | 0 0 | (0 0) (0 0)
4689 09:26:19.589208 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 09:26:19.592518 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 09:26:19.599273 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 09:26:19.602339 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 09:26:19.605512 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 09:26:19.612037 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 09:26:19.615888 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 09:26:19.619153 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 09:26:19.625846 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 09:26:19.629062 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 09:26:19.632326 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 09:26:19.639352 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 09:26:19.642472 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 09:26:19.645822 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 09:26:19.649155 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 09:26:19.655615 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 09:26:19.658935 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 09:26:19.662221 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 09:26:19.669360 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 09:26:19.672601 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 09:26:19.675375 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 09:26:19.682472 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 09:26:19.685500 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 09:26:19.688597 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4713 09:26:19.692133 Total UI for P1: 0, mck2ui 16
4714 09:26:19.695429 best dqsien dly found for B0: ( 0, 13, 10)
4715 09:26:19.702369 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 09:26:19.702444 Total UI for P1: 0, mck2ui 16
4717 09:26:19.708605 best dqsien dly found for B1: ( 0, 13, 12)
4718 09:26:19.711931 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4719 09:26:19.715237 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4720 09:26:19.715337
4721 09:26:19.718932 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4722 09:26:19.722242 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4723 09:26:19.725503 [Gating] SW calibration Done
4724 09:26:19.725574 ==
4725 09:26:19.728570 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 09:26:19.731901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 09:26:19.731975 ==
4728 09:26:19.735748 RX Vref Scan: 0
4729 09:26:19.735824
4730 09:26:19.735891 RX Vref 0 -> 0, step: 1
4731 09:26:19.735955
4732 09:26:19.738854 RX Delay -230 -> 252, step: 16
4733 09:26:19.745276 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4734 09:26:19.748578 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4735 09:26:19.752277 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4736 09:26:19.755015 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4737 09:26:19.758356 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4738 09:26:19.765418 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4739 09:26:19.768773 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4740 09:26:19.772206 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4741 09:26:19.775368 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4742 09:26:19.781952 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4743 09:26:19.785257 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4744 09:26:19.788468 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4745 09:26:19.791658 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4746 09:26:19.798186 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4747 09:26:19.801388 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4748 09:26:19.805126 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4749 09:26:19.805201 ==
4750 09:26:19.808111 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 09:26:19.811596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 09:26:19.811701 ==
4753 09:26:19.814790 DQS Delay:
4754 09:26:19.814887 DQS0 = 0, DQS1 = 0
4755 09:26:19.818158 DQM Delay:
4756 09:26:19.818258 DQM0 = 49, DQM1 = 47
4757 09:26:19.818348 DQ Delay:
4758 09:26:19.821274 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4759 09:26:19.824971 DQ4 =49, DQ5 =57, DQ6 =49, DQ7 =49
4760 09:26:19.828391 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4761 09:26:19.831641 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4762 09:26:19.831743
4763 09:26:19.831839
4764 09:26:19.835041 ==
4765 09:26:19.838296 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 09:26:19.841511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 09:26:19.841586 ==
4768 09:26:19.841651
4769 09:26:19.841748
4770 09:26:19.844724 TX Vref Scan disable
4771 09:26:19.844824 == TX Byte 0 ==
4772 09:26:19.851431 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4773 09:26:19.854657 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4774 09:26:19.854761 == TX Byte 1 ==
4775 09:26:19.861471 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4776 09:26:19.864829 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4777 09:26:19.864906 ==
4778 09:26:19.868212 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 09:26:19.871642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 09:26:19.871749 ==
4781 09:26:19.871829
4782 09:26:19.871969
4783 09:26:19.874850 TX Vref Scan disable
4784 09:26:19.878202 == TX Byte 0 ==
4785 09:26:19.881514 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4786 09:26:19.884694 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4787 09:26:19.888052 == TX Byte 1 ==
4788 09:26:19.891355 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4789 09:26:19.894490 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4790 09:26:19.894590
4791 09:26:19.897974 [DATLAT]
4792 09:26:19.898078 Freq=600, CH1 RK1
4793 09:26:19.898142
4794 09:26:19.901189 DATLAT Default: 0x9
4795 09:26:19.901263 0, 0xFFFF, sum = 0
4796 09:26:19.904411 1, 0xFFFF, sum = 0
4797 09:26:19.904511 2, 0xFFFF, sum = 0
4798 09:26:19.907768 3, 0xFFFF, sum = 0
4799 09:26:19.907865 4, 0xFFFF, sum = 0
4800 09:26:19.911433 5, 0xFFFF, sum = 0
4801 09:26:19.911520 6, 0xFFFF, sum = 0
4802 09:26:19.914865 7, 0xFFFF, sum = 0
4803 09:26:19.914974 8, 0x0, sum = 1
4804 09:26:19.918149 9, 0x0, sum = 2
4805 09:26:19.918258 10, 0x0, sum = 3
4806 09:26:19.921392 11, 0x0, sum = 4
4807 09:26:19.921483 best_step = 9
4808 09:26:19.921549
4809 09:26:19.921609 ==
4810 09:26:19.924612 Dram Type= 6, Freq= 0, CH_1, rank 1
4811 09:26:19.927894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4812 09:26:19.931179 ==
4813 09:26:19.931264 RX Vref Scan: 0
4814 09:26:19.931331
4815 09:26:19.934352 RX Vref 0 -> 0, step: 1
4816 09:26:19.934436
4817 09:26:19.938096 RX Delay -163 -> 252, step: 8
4818 09:26:19.941356 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4819 09:26:19.944711 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4820 09:26:19.951213 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4821 09:26:19.954463 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4822 09:26:19.957601 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4823 09:26:19.961401 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4824 09:26:19.964716 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4825 09:26:19.967877 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4826 09:26:19.974820 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4827 09:26:19.977635 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4828 09:26:19.981389 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4829 09:26:19.984796 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4830 09:26:19.991156 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4831 09:26:19.994509 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4832 09:26:19.998172 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4833 09:26:20.001217 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4834 09:26:20.001301 ==
4835 09:26:20.004401 Dram Type= 6, Freq= 0, CH_1, rank 1
4836 09:26:20.008299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4837 09:26:20.011464 ==
4838 09:26:20.011548 DQS Delay:
4839 09:26:20.011616 DQS0 = 0, DQS1 = 0
4840 09:26:20.014744 DQM Delay:
4841 09:26:20.014828 DQM0 = 50, DQM1 = 44
4842 09:26:20.017817 DQ Delay:
4843 09:26:20.017901 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =48
4844 09:26:20.021355 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4845 09:26:20.024537 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4846 09:26:20.027838 DQ12 =48, DQ13 =52, DQ14 =48, DQ15 =56
4847 09:26:20.027923
4848 09:26:20.031650
4849 09:26:20.038056 [DQSOSCAuto] RK1, (LSB)MR18= 0x6129, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4850 09:26:20.041399 CH1 RK1: MR19=808, MR18=6129
4851 09:26:20.047968 CH1_RK1: MR19=0x808, MR18=0x6129, DQSOSC=391, MR23=63, INC=171, DEC=114
4852 09:26:20.051182 [RxdqsGatingPostProcess] freq 600
4853 09:26:20.054968 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4854 09:26:20.058233 Pre-setting of DQS Precalculation
4855 09:26:20.061542 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4856 09:26:20.071371 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4857 09:26:20.077833 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4858 09:26:20.077918
4859 09:26:20.077986
4860 09:26:20.081115 [Calibration Summary] 1200 Mbps
4861 09:26:20.081199 CH 0, Rank 0
4862 09:26:20.084440 SW Impedance : PASS
4863 09:26:20.084526 DUTY Scan : NO K
4864 09:26:20.087802 ZQ Calibration : PASS
4865 09:26:20.090949 Jitter Meter : NO K
4866 09:26:20.091034 CBT Training : PASS
4867 09:26:20.094732 Write leveling : PASS
4868 09:26:20.098123 RX DQS gating : PASS
4869 09:26:20.098208 RX DQ/DQS(RDDQC) : PASS
4870 09:26:20.101254 TX DQ/DQS : PASS
4871 09:26:20.104485 RX DATLAT : PASS
4872 09:26:20.104594 RX DQ/DQS(Engine): PASS
4873 09:26:20.107753 TX OE : NO K
4874 09:26:20.107837 All Pass.
4875 09:26:20.107904
4876 09:26:20.111325 CH 0, Rank 1
4877 09:26:20.111437 SW Impedance : PASS
4878 09:26:20.114545 DUTY Scan : NO K
4879 09:26:20.117841 ZQ Calibration : PASS
4880 09:26:20.117926 Jitter Meter : NO K
4881 09:26:20.121072 CBT Training : PASS
4882 09:26:20.124662 Write leveling : PASS
4883 09:26:20.124778 RX DQS gating : PASS
4884 09:26:20.127879 RX DQ/DQS(RDDQC) : PASS
4885 09:26:20.127963 TX DQ/DQS : PASS
4886 09:26:20.131019 RX DATLAT : PASS
4887 09:26:20.134765 RX DQ/DQS(Engine): PASS
4888 09:26:20.134879 TX OE : NO K
4889 09:26:20.138089 All Pass.
4890 09:26:20.138173
4891 09:26:20.138240 CH 1, Rank 0
4892 09:26:20.141458 SW Impedance : PASS
4893 09:26:20.141543 DUTY Scan : NO K
4894 09:26:20.144245 ZQ Calibration : PASS
4895 09:26:20.147947 Jitter Meter : NO K
4896 09:26:20.148031 CBT Training : PASS
4897 09:26:20.151265 Write leveling : PASS
4898 09:26:20.154579 RX DQS gating : PASS
4899 09:26:20.154664 RX DQ/DQS(RDDQC) : PASS
4900 09:26:20.157857 TX DQ/DQS : PASS
4901 09:26:20.161074 RX DATLAT : PASS
4902 09:26:20.161157 RX DQ/DQS(Engine): PASS
4903 09:26:20.164379 TX OE : NO K
4904 09:26:20.164463 All Pass.
4905 09:26:20.164529
4906 09:26:20.168118 CH 1, Rank 1
4907 09:26:20.168201 SW Impedance : PASS
4908 09:26:20.171358 DUTY Scan : NO K
4909 09:26:20.171443 ZQ Calibration : PASS
4910 09:26:20.174513 Jitter Meter : NO K
4911 09:26:20.177805 CBT Training : PASS
4912 09:26:20.177884 Write leveling : PASS
4913 09:26:20.181107 RX DQS gating : PASS
4914 09:26:20.184261 RX DQ/DQS(RDDQC) : PASS
4915 09:26:20.184334 TX DQ/DQS : PASS
4916 09:26:20.188127 RX DATLAT : PASS
4917 09:26:20.191336 RX DQ/DQS(Engine): PASS
4918 09:26:20.191409 TX OE : NO K
4919 09:26:20.194520 All Pass.
4920 09:26:20.194592
4921 09:26:20.194653 DramC Write-DBI off
4922 09:26:20.197746 PER_BANK_REFRESH: Hybrid Mode
4923 09:26:20.197818 TX_TRACKING: ON
4924 09:26:20.207532 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4925 09:26:20.211226 [FAST_K] Save calibration result to emmc
4926 09:26:20.214351 dramc_set_vcore_voltage set vcore to 662500
4927 09:26:20.217439 Read voltage for 933, 3
4928 09:26:20.217519 Vio18 = 0
4929 09:26:20.220813 Vcore = 662500
4930 09:26:20.220893 Vdram = 0
4931 09:26:20.220958 Vddq = 0
4932 09:26:20.224601 Vmddr = 0
4933 09:26:20.227749 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4934 09:26:20.234399 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4935 09:26:20.234486 MEM_TYPE=3, freq_sel=17
4936 09:26:20.237540 sv_algorithm_assistance_LP4_1600
4937 09:26:20.244169 ============ PULL DRAM RESETB DOWN ============
4938 09:26:20.247477 ========== PULL DRAM RESETB DOWN end =========
4939 09:26:20.250685 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4940 09:26:20.253911 ===================================
4941 09:26:20.257689 LPDDR4 DRAM CONFIGURATION
4942 09:26:20.260927 ===================================
4943 09:26:20.261011 EX_ROW_EN[0] = 0x0
4944 09:26:20.264068 EX_ROW_EN[1] = 0x0
4945 09:26:20.267384 LP4Y_EN = 0x0
4946 09:26:20.267468 WORK_FSP = 0x0
4947 09:26:20.270679 WL = 0x3
4948 09:26:20.270789 RL = 0x3
4949 09:26:20.274059 BL = 0x2
4950 09:26:20.274143 RPST = 0x0
4951 09:26:20.277333 RD_PRE = 0x0
4952 09:26:20.277417 WR_PRE = 0x1
4953 09:26:20.280496 WR_PST = 0x0
4954 09:26:20.280616 DBI_WR = 0x0
4955 09:26:20.283819 DBI_RD = 0x0
4956 09:26:20.283903 OTF = 0x1
4957 09:26:20.287213 ===================================
4958 09:26:20.290390 ===================================
4959 09:26:20.293743 ANA top config
4960 09:26:20.297027 ===================================
4961 09:26:20.297101 DLL_ASYNC_EN = 0
4962 09:26:20.300337 ALL_SLAVE_EN = 1
4963 09:26:20.303486 NEW_RANK_MODE = 1
4964 09:26:20.306755 DLL_IDLE_MODE = 1
4965 09:26:20.310118 LP45_APHY_COMB_EN = 1
4966 09:26:20.310219 TX_ODT_DIS = 1
4967 09:26:20.313399 NEW_8X_MODE = 1
4968 09:26:20.317074 ===================================
4969 09:26:20.320111 ===================================
4970 09:26:20.323290 data_rate = 1866
4971 09:26:20.327042 CKR = 1
4972 09:26:20.330181 DQ_P2S_RATIO = 8
4973 09:26:20.333445 ===================================
4974 09:26:20.333516 CA_P2S_RATIO = 8
4975 09:26:20.337164 DQ_CA_OPEN = 0
4976 09:26:20.340107 DQ_SEMI_OPEN = 0
4977 09:26:20.343298 CA_SEMI_OPEN = 0
4978 09:26:20.347088 CA_FULL_RATE = 0
4979 09:26:20.350338 DQ_CKDIV4_EN = 1
4980 09:26:20.350412 CA_CKDIV4_EN = 1
4981 09:26:20.353548 CA_PREDIV_EN = 0
4982 09:26:20.356806 PH8_DLY = 0
4983 09:26:20.360139 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4984 09:26:20.363316 DQ_AAMCK_DIV = 4
4985 09:26:20.366636 CA_AAMCK_DIV = 4
4986 09:26:20.366732 CA_ADMCK_DIV = 4
4987 09:26:20.369883 DQ_TRACK_CA_EN = 0
4988 09:26:20.373522 CA_PICK = 933
4989 09:26:20.376631 CA_MCKIO = 933
4990 09:26:20.380174 MCKIO_SEMI = 0
4991 09:26:20.383159 PLL_FREQ = 3732
4992 09:26:20.386494 DQ_UI_PI_RATIO = 32
4993 09:26:20.386593 CA_UI_PI_RATIO = 0
4994 09:26:20.390313 ===================================
4995 09:26:20.393606 ===================================
4996 09:26:20.396762 memory_type:LPDDR4
4997 09:26:20.400198 GP_NUM : 10
4998 09:26:20.400354 SRAM_EN : 1
4999 09:26:20.403373 MD32_EN : 0
5000 09:26:20.406607 ===================================
5001 09:26:20.410416 [ANA_INIT] >>>>>>>>>>>>>>
5002 09:26:20.413711 <<<<<< [CONFIGURE PHASE]: ANA_TX
5003 09:26:20.416901 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5004 09:26:20.420099 ===================================
5005 09:26:20.420200 data_rate = 1866,PCW = 0X8f00
5006 09:26:20.423320 ===================================
5007 09:26:20.426979 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5008 09:26:20.433442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5009 09:26:20.440257 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5010 09:26:20.443278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5011 09:26:20.446566 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5012 09:26:20.450438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5013 09:26:20.453701 [ANA_INIT] flow start
5014 09:26:20.453802 [ANA_INIT] PLL >>>>>>>>
5015 09:26:20.456953 [ANA_INIT] PLL <<<<<<<<
5016 09:26:20.460113 [ANA_INIT] MIDPI >>>>>>>>
5017 09:26:20.463272 [ANA_INIT] MIDPI <<<<<<<<
5018 09:26:20.463372 [ANA_INIT] DLL >>>>>>>>
5019 09:26:20.467036 [ANA_INIT] flow end
5020 09:26:20.470402 ============ LP4 DIFF to SE enter ============
5021 09:26:20.473236 ============ LP4 DIFF to SE exit ============
5022 09:26:20.477050 [ANA_INIT] <<<<<<<<<<<<<
5023 09:26:20.480343 [Flow] Enable top DCM control >>>>>
5024 09:26:20.483566 [Flow] Enable top DCM control <<<<<
5025 09:26:20.486802 Enable DLL master slave shuffle
5026 09:26:20.493330 ==============================================================
5027 09:26:20.493406 Gating Mode config
5028 09:26:20.500406 ==============================================================
5029 09:26:20.500508 Config description:
5030 09:26:20.510124 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5031 09:26:20.516794 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5032 09:26:20.523367 SELPH_MODE 0: By rank 1: By Phase
5033 09:26:20.527178 ==============================================================
5034 09:26:20.529992 GAT_TRACK_EN = 1
5035 09:26:20.533679 RX_GATING_MODE = 2
5036 09:26:20.536934 RX_GATING_TRACK_MODE = 2
5037 09:26:20.540204 SELPH_MODE = 1
5038 09:26:20.543582 PICG_EARLY_EN = 1
5039 09:26:20.546672 VALID_LAT_VALUE = 1
5040 09:26:20.550274 ==============================================================
5041 09:26:20.553472 Enter into Gating configuration >>>>
5042 09:26:20.556728 Exit from Gating configuration <<<<
5043 09:26:20.560080 Enter into DVFS_PRE_config >>>>>
5044 09:26:20.573528 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5045 09:26:20.573632 Exit from DVFS_PRE_config <<<<<
5046 09:26:20.576722 Enter into PICG configuration >>>>
5047 09:26:20.580075 Exit from PICG configuration <<<<
5048 09:26:20.583589 [RX_INPUT] configuration >>>>>
5049 09:26:20.586659 [RX_INPUT] configuration <<<<<
5050 09:26:20.593273 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5051 09:26:20.596617 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5052 09:26:20.603051 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5053 09:26:20.610075 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5054 09:26:20.616523 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5055 09:26:20.623111 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5056 09:26:20.626416 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5057 09:26:20.630119 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5058 09:26:20.633284 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5059 09:26:20.639965 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5060 09:26:20.643247 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5061 09:26:20.646499 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5062 09:26:20.649666 ===================================
5063 09:26:20.653258 LPDDR4 DRAM CONFIGURATION
5064 09:26:20.656523 ===================================
5065 09:26:20.659764 EX_ROW_EN[0] = 0x0
5066 09:26:20.659861 EX_ROW_EN[1] = 0x0
5067 09:26:20.662957 LP4Y_EN = 0x0
5068 09:26:20.663052 WORK_FSP = 0x0
5069 09:26:20.666182 WL = 0x3
5070 09:26:20.666252 RL = 0x3
5071 09:26:20.669927 BL = 0x2
5072 09:26:20.670001 RPST = 0x0
5073 09:26:20.673225 RD_PRE = 0x0
5074 09:26:20.673320 WR_PRE = 0x1
5075 09:26:20.676413 WR_PST = 0x0
5076 09:26:20.676509 DBI_WR = 0x0
5077 09:26:20.679595 DBI_RD = 0x0
5078 09:26:20.679690 OTF = 0x1
5079 09:26:20.682872 ===================================
5080 09:26:20.686252 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5081 09:26:20.692786 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5082 09:26:20.696383 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5083 09:26:20.699706 ===================================
5084 09:26:20.702913 LPDDR4 DRAM CONFIGURATION
5085 09:26:20.706162 ===================================
5086 09:26:20.706232 EX_ROW_EN[0] = 0x10
5087 09:26:20.709852 EX_ROW_EN[1] = 0x0
5088 09:26:20.713125 LP4Y_EN = 0x0
5089 09:26:20.713224 WORK_FSP = 0x0
5090 09:26:20.716366 WL = 0x3
5091 09:26:20.716465 RL = 0x3
5092 09:26:20.719636 BL = 0x2
5093 09:26:20.719711 RPST = 0x0
5094 09:26:20.722927 RD_PRE = 0x0
5095 09:26:20.723022 WR_PRE = 0x1
5096 09:26:20.726074 WR_PST = 0x0
5097 09:26:20.726169 DBI_WR = 0x0
5098 09:26:20.729612 DBI_RD = 0x0
5099 09:26:20.729685 OTF = 0x1
5100 09:26:20.732953 ===================================
5101 09:26:20.739519 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5102 09:26:20.743720 nWR fixed to 30
5103 09:26:20.746889 [ModeRegInit_LP4] CH0 RK0
5104 09:26:20.746985 [ModeRegInit_LP4] CH0 RK1
5105 09:26:20.750204 [ModeRegInit_LP4] CH1 RK0
5106 09:26:20.753446 [ModeRegInit_LP4] CH1 RK1
5107 09:26:20.753545 match AC timing 9
5108 09:26:20.770591 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5109 09:26:20.770704 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5110 09:26:20.770801 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5111 09:26:20.773711 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5112 09:26:20.777047 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5113 09:26:20.777121 ==
5114 09:26:20.780250 Dram Type= 6, Freq= 0, CH_0, rank 0
5115 09:26:20.783540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 09:26:20.783636 ==
5117 09:26:20.790061 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5118 09:26:20.796694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5119 09:26:20.800416 [CA 0] Center 38 (7~69) winsize 63
5120 09:26:20.803559 [CA 1] Center 38 (8~69) winsize 62
5121 09:26:20.806771 [CA 2] Center 35 (5~66) winsize 62
5122 09:26:20.809962 [CA 3] Center 35 (5~66) winsize 62
5123 09:26:20.813284 [CA 4] Center 35 (5~65) winsize 61
5124 09:26:20.816938 [CA 5] Center 33 (3~64) winsize 62
5125 09:26:20.817021
5126 09:26:20.820292 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5127 09:26:20.820390
5128 09:26:20.823546 [CATrainingPosCal] consider 1 rank data
5129 09:26:20.826809 u2DelayCellTimex100 = 270/100 ps
5130 09:26:20.829902 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5131 09:26:20.833648 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5132 09:26:20.836966 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5133 09:26:20.840271 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5134 09:26:20.843502 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5135 09:26:20.846716 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5136 09:26:20.846811
5137 09:26:20.853749 CA PerBit enable=1, Macro0, CA PI delay=33
5138 09:26:20.853853
5139 09:26:20.857007 [CBTSetCACLKResult] CA Dly = 33
5140 09:26:20.857105 CS Dly: 6 (0~37)
5141 09:26:20.857196 ==
5142 09:26:20.860197 Dram Type= 6, Freq= 0, CH_0, rank 1
5143 09:26:20.863816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 09:26:20.863912 ==
5145 09:26:20.870209 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5146 09:26:20.876739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5147 09:26:20.880111 [CA 0] Center 38 (7~69) winsize 63
5148 09:26:20.883342 [CA 1] Center 38 (8~69) winsize 62
5149 09:26:20.886916 [CA 2] Center 36 (6~66) winsize 61
5150 09:26:20.890204 [CA 3] Center 35 (5~66) winsize 62
5151 09:26:20.893336 [CA 4] Center 34 (4~65) winsize 62
5152 09:26:20.896507 [CA 5] Center 34 (4~64) winsize 61
5153 09:26:20.896623
5154 09:26:20.900258 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5155 09:26:20.900333
5156 09:26:20.903468 [CATrainingPosCal] consider 2 rank data
5157 09:26:20.906496 u2DelayCellTimex100 = 270/100 ps
5158 09:26:20.909682 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5159 09:26:20.913581 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5160 09:26:20.916652 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5161 09:26:20.919704 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5162 09:26:20.923074 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5163 09:26:20.930107 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5164 09:26:20.930184
5165 09:26:20.933307 CA PerBit enable=1, Macro0, CA PI delay=34
5166 09:26:20.933382
5167 09:26:20.936503 [CBTSetCACLKResult] CA Dly = 34
5168 09:26:20.936621 CS Dly: 7 (0~39)
5169 09:26:20.936685
5170 09:26:20.939854 ----->DramcWriteLeveling(PI) begin...
5171 09:26:20.939925 ==
5172 09:26:20.943256 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 09:26:20.946384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 09:26:20.949672 ==
5175 09:26:20.949799 Write leveling (Byte 0): 33 => 33
5176 09:26:20.953221 Write leveling (Byte 1): 29 => 29
5177 09:26:20.956465 DramcWriteLeveling(PI) end<-----
5178 09:26:20.956597
5179 09:26:20.956689 ==
5180 09:26:20.959784 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 09:26:20.966638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 09:26:20.966711 ==
5183 09:26:20.966775 [Gating] SW mode calibration
5184 09:26:20.976636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5185 09:26:20.979923 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5186 09:26:20.986413 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5187 09:26:20.989787 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 09:26:20.993103 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 09:26:20.996351 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 09:26:21.002923 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 09:26:21.006135 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 09:26:21.009451 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5193 09:26:21.016539 0 14 28 | B1->B0 | 3030 2323 | 0 0 | (0 0) (1 0)
5194 09:26:21.019710 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5195 09:26:21.023051 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 09:26:21.029459 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 09:26:21.033184 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 09:26:21.036400 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 09:26:21.042945 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 09:26:21.046089 0 15 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5201 09:26:21.049877 0 15 28 | B1->B0 | 2c2c 4444 | 0 0 | (0 0) (0 0)
5202 09:26:21.056423 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5203 09:26:21.059568 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 09:26:21.062881 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 09:26:21.069179 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 09:26:21.072897 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 09:26:21.076071 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 09:26:21.083123 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 09:26:21.086460 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5210 09:26:21.089692 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5211 09:26:21.096187 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 09:26:21.099524 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 09:26:21.102807 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 09:26:21.109262 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 09:26:21.112511 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 09:26:21.115740 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 09:26:21.122745 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 09:26:21.125930 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 09:26:21.129281 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 09:26:21.132608 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 09:26:21.139522 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 09:26:21.142776 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 09:26:21.146003 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 09:26:21.152503 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5225 09:26:21.156319 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5226 09:26:21.159616 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 09:26:21.162683 Total UI for P1: 0, mck2ui 16
5228 09:26:21.165814 best dqsien dly found for B0: ( 1, 2, 26)
5229 09:26:21.169688 Total UI for P1: 0, mck2ui 16
5230 09:26:21.172818 best dqsien dly found for B1: ( 1, 2, 28)
5231 09:26:21.176236 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5232 09:26:21.179244 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5233 09:26:21.179339
5234 09:26:21.185735 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5235 09:26:21.189451 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5236 09:26:21.189555 [Gating] SW calibration Done
5237 09:26:21.192690 ==
5238 09:26:21.195913 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 09:26:21.199095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 09:26:21.199168 ==
5241 09:26:21.199229 RX Vref Scan: 0
5242 09:26:21.199288
5243 09:26:21.202462 RX Vref 0 -> 0, step: 1
5244 09:26:21.202528
5245 09:26:21.205761 RX Delay -80 -> 252, step: 8
5246 09:26:21.209081 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5247 09:26:21.212218 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5248 09:26:21.216076 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5249 09:26:21.222474 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5250 09:26:21.225666 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5251 09:26:21.228962 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5252 09:26:21.232281 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5253 09:26:21.235459 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5254 09:26:21.242584 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5255 09:26:21.245804 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5256 09:26:21.249054 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5257 09:26:21.252356 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5258 09:26:21.256160 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5259 09:26:21.259362 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5260 09:26:21.265857 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5261 09:26:21.269088 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5262 09:26:21.269198 ==
5263 09:26:21.272252 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 09:26:21.276093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 09:26:21.276187 ==
5266 09:26:21.276255 DQS Delay:
5267 09:26:21.279176 DQS0 = 0, DQS1 = 0
5268 09:26:21.279317 DQM Delay:
5269 09:26:21.282618 DQM0 = 106, DQM1 = 89
5270 09:26:21.282700 DQ Delay:
5271 09:26:21.285783 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =103
5272 09:26:21.289401 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5273 09:26:21.292537 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =87
5274 09:26:21.295984 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5275 09:26:21.296102
5276 09:26:21.296201
5277 09:26:21.296263 ==
5278 09:26:21.299222 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 09:26:21.305760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 09:26:21.305846 ==
5281 09:26:21.305914
5282 09:26:21.305976
5283 09:26:21.306037 TX Vref Scan disable
5284 09:26:21.309122 == TX Byte 0 ==
5285 09:26:21.312337 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5286 09:26:21.316046 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5287 09:26:21.319288 == TX Byte 1 ==
5288 09:26:21.322640 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5289 09:26:21.329032 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5290 09:26:21.329133 ==
5291 09:26:21.332324 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 09:26:21.335655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 09:26:21.335740 ==
5294 09:26:21.335807
5295 09:26:21.335870
5296 09:26:21.339378 TX Vref Scan disable
5297 09:26:21.339462 == TX Byte 0 ==
5298 09:26:21.345874 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5299 09:26:21.349250 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5300 09:26:21.349335 == TX Byte 1 ==
5301 09:26:21.355757 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5302 09:26:21.359105 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5303 09:26:21.359190
5304 09:26:21.359257 [DATLAT]
5305 09:26:21.362439 Freq=933, CH0 RK0
5306 09:26:21.362602
5307 09:26:21.362702 DATLAT Default: 0xd
5308 09:26:21.365785 0, 0xFFFF, sum = 0
5309 09:26:21.365873 1, 0xFFFF, sum = 0
5310 09:26:21.368941 2, 0xFFFF, sum = 0
5311 09:26:21.369027 3, 0xFFFF, sum = 0
5312 09:26:21.372544 4, 0xFFFF, sum = 0
5313 09:26:21.372651 5, 0xFFFF, sum = 0
5314 09:26:21.376054 6, 0xFFFF, sum = 0
5315 09:26:21.376153 7, 0xFFFF, sum = 0
5316 09:26:21.379266 8, 0xFFFF, sum = 0
5317 09:26:21.382386 9, 0xFFFF, sum = 0
5318 09:26:21.382471 10, 0x0, sum = 1
5319 09:26:21.382540 11, 0x0, sum = 2
5320 09:26:21.385954 12, 0x0, sum = 3
5321 09:26:21.386038 13, 0x0, sum = 4
5322 09:26:21.389011 best_step = 11
5323 09:26:21.389113
5324 09:26:21.389192 ==
5325 09:26:21.392173 Dram Type= 6, Freq= 0, CH_0, rank 0
5326 09:26:21.395871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 09:26:21.395956 ==
5328 09:26:21.399229 RX Vref Scan: 1
5329 09:26:21.399351
5330 09:26:21.399446 RX Vref 0 -> 0, step: 1
5331 09:26:21.399536
5332 09:26:21.402602 RX Delay -61 -> 252, step: 4
5333 09:26:21.402687
5334 09:26:21.405892 Set Vref, RX VrefLevel [Byte0]: 59
5335 09:26:21.409174 [Byte1]: 50
5336 09:26:21.413466
5337 09:26:21.413565 Final RX Vref Byte 0 = 59 to rank0
5338 09:26:21.416512 Final RX Vref Byte 1 = 50 to rank0
5339 09:26:21.419893 Final RX Vref Byte 0 = 59 to rank1
5340 09:26:21.423095 Final RX Vref Byte 1 = 50 to rank1==
5341 09:26:21.426461 Dram Type= 6, Freq= 0, CH_0, rank 0
5342 09:26:21.432865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 09:26:21.432951 ==
5344 09:26:21.433018 DQS Delay:
5345 09:26:21.433078 DQS0 = 0, DQS1 = 0
5346 09:26:21.436751 DQM Delay:
5347 09:26:21.436833 DQM0 = 107, DQM1 = 92
5348 09:26:21.439978 DQ Delay:
5349 09:26:21.443190 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5350 09:26:21.446349 DQ4 =108, DQ5 =100, DQ6 =118, DQ7 =114
5351 09:26:21.449637 DQ8 =86, DQ9 =80, DQ10 =92, DQ11 =92
5352 09:26:21.452871 DQ12 =98, DQ13 =92, DQ14 =102, DQ15 =98
5353 09:26:21.452955
5354 09:26:21.453021
5355 09:26:21.459368 [DQSOSCAuto] RK0, (LSB)MR18= 0x2824, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5356 09:26:21.462652 CH0 RK0: MR19=505, MR18=2824
5357 09:26:21.469792 CH0_RK0: MR19=0x505, MR18=0x2824, DQSOSC=409, MR23=63, INC=64, DEC=43
5358 09:26:21.469902
5359 09:26:21.473148 ----->DramcWriteLeveling(PI) begin...
5360 09:26:21.473247 ==
5361 09:26:21.476393 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 09:26:21.479436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 09:26:21.479564 ==
5364 09:26:21.482656 Write leveling (Byte 0): 32 => 32
5365 09:26:21.486509 Write leveling (Byte 1): 31 => 31
5366 09:26:21.489770 DramcWriteLeveling(PI) end<-----
5367 09:26:21.489883
5368 09:26:21.489944 ==
5369 09:26:21.492721 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 09:26:21.496442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 09:26:21.499597 ==
5372 09:26:21.499695 [Gating] SW mode calibration
5373 09:26:21.509673 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5374 09:26:21.512958 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5375 09:26:21.516282 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 09:26:21.522625 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 09:26:21.526001 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 09:26:21.529236 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 09:26:21.536314 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 09:26:21.539637 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 09:26:21.542823 0 14 24 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 1)
5382 09:26:21.549803 0 14 28 | B1->B0 | 2d2d 2424 | 0 0 | (1 1) (0 0)
5383 09:26:21.553146 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 09:26:21.556369 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 09:26:21.563026 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 09:26:21.566298 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 09:26:21.569605 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 09:26:21.572939 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 09:26:21.579384 0 15 24 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
5390 09:26:21.582985 0 15 28 | B1->B0 | 3e3e 4444 | 0 0 | (0 0) (0 0)
5391 09:26:21.586157 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 09:26:21.592692 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 09:26:21.596259 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 09:26:21.599451 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 09:26:21.606154 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 09:26:21.609430 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 09:26:21.612712 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 09:26:21.619777 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5399 09:26:21.623084 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 09:26:21.626398 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 09:26:21.632911 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 09:26:21.636219 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 09:26:21.639577 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 09:26:21.646496 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 09:26:21.649763 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 09:26:21.652939 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 09:26:21.659485 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 09:26:21.662878 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 09:26:21.666133 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 09:26:21.672755 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 09:26:21.676055 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 09:26:21.679390 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 09:26:21.685811 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5414 09:26:21.689412 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5415 09:26:21.692700 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 09:26:21.695871 Total UI for P1: 0, mck2ui 16
5417 09:26:21.699467 best dqsien dly found for B0: ( 1, 2, 26)
5418 09:26:21.702656 Total UI for P1: 0, mck2ui 16
5419 09:26:21.706202 best dqsien dly found for B1: ( 1, 2, 28)
5420 09:26:21.709386 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5421 09:26:21.712740 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5422 09:26:21.712841
5423 09:26:21.715940 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5424 09:26:21.719188 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5425 09:26:21.722882 [Gating] SW calibration Done
5426 09:26:21.723043 ==
5427 09:26:21.725922 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 09:26:21.732389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 09:26:21.732499 ==
5430 09:26:21.732640 RX Vref Scan: 0
5431 09:26:21.732706
5432 09:26:21.736163 RX Vref 0 -> 0, step: 1
5433 09:26:21.736305
5434 09:26:21.739330 RX Delay -80 -> 252, step: 8
5435 09:26:21.742720 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5436 09:26:21.745946 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5437 09:26:21.749268 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5438 09:26:21.752295 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5439 09:26:21.759342 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5440 09:26:21.762685 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5441 09:26:21.766106 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5442 09:26:21.769315 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5443 09:26:21.772754 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5444 09:26:21.775837 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5445 09:26:21.782440 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5446 09:26:21.785797 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5447 09:26:21.789146 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5448 09:26:21.792227 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5449 09:26:21.795411 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5450 09:26:21.799197 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5451 09:26:21.802425 ==
5452 09:26:21.805973 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 09:26:21.809116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 09:26:21.809206 ==
5455 09:26:21.809275 DQS Delay:
5456 09:26:21.812278 DQS0 = 0, DQS1 = 0
5457 09:26:21.812362 DQM Delay:
5458 09:26:21.815454 DQM0 = 104, DQM1 = 90
5459 09:26:21.815539 DQ Delay:
5460 09:26:21.818818 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5461 09:26:21.822536 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5462 09:26:21.825726 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5463 09:26:21.829035 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5464 09:26:21.829113
5465 09:26:21.829192
5466 09:26:21.829255 ==
5467 09:26:21.832277 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 09:26:21.835556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 09:26:21.835671 ==
5470 09:26:21.835770
5471 09:26:21.838723
5472 09:26:21.838874 TX Vref Scan disable
5473 09:26:21.842081 == TX Byte 0 ==
5474 09:26:21.845846 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5475 09:26:21.849136 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5476 09:26:21.852338 == TX Byte 1 ==
5477 09:26:21.855579 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5478 09:26:21.858857 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5479 09:26:21.858944 ==
5480 09:26:21.862225 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 09:26:21.868712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 09:26:21.868803 ==
5483 09:26:21.868887
5484 09:26:21.868974
5485 09:26:21.869051 TX Vref Scan disable
5486 09:26:21.872641 == TX Byte 0 ==
5487 09:26:21.876014 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5488 09:26:21.882697 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5489 09:26:21.882775 == TX Byte 1 ==
5490 09:26:21.885895 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5491 09:26:21.892477 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5492 09:26:21.892601
5493 09:26:21.892669 [DATLAT]
5494 09:26:21.892772 Freq=933, CH0 RK1
5495 09:26:21.892834
5496 09:26:21.896071 DATLAT Default: 0xb
5497 09:26:21.896146 0, 0xFFFF, sum = 0
5498 09:26:21.899491 1, 0xFFFF, sum = 0
5499 09:26:21.899592 2, 0xFFFF, sum = 0
5500 09:26:21.902703 3, 0xFFFF, sum = 0
5501 09:26:21.906061 4, 0xFFFF, sum = 0
5502 09:26:21.906155 5, 0xFFFF, sum = 0
5503 09:26:21.909149 6, 0xFFFF, sum = 0
5504 09:26:21.909241 7, 0xFFFF, sum = 0
5505 09:26:21.912663 8, 0xFFFF, sum = 0
5506 09:26:21.912764 9, 0xFFFF, sum = 0
5507 09:26:21.916184 10, 0x0, sum = 1
5508 09:26:21.916286 11, 0x0, sum = 2
5509 09:26:21.916384 12, 0x0, sum = 3
5510 09:26:21.919441 13, 0x0, sum = 4
5511 09:26:21.919542 best_step = 11
5512 09:26:21.919639
5513 09:26:21.919730 ==
5514 09:26:21.922795 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 09:26:21.929388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 09:26:21.929488 ==
5517 09:26:21.929585 RX Vref Scan: 0
5518 09:26:21.929678
5519 09:26:21.932450 RX Vref 0 -> 0, step: 1
5520 09:26:21.932554
5521 09:26:21.935794 RX Delay -53 -> 252, step: 4
5522 09:26:21.939495 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5523 09:26:21.945913 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5524 09:26:21.949331 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5525 09:26:21.953082 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5526 09:26:21.956206 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5527 09:26:21.959440 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5528 09:26:21.962814 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5529 09:26:21.969385 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5530 09:26:21.973196 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5531 09:26:21.976443 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5532 09:26:21.979690 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5533 09:26:21.982972 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5534 09:26:21.989428 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5535 09:26:21.992707 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5536 09:26:21.996370 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5537 09:26:21.999393 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5538 09:26:21.999479 ==
5539 09:26:22.002906 Dram Type= 6, Freq= 0, CH_0, rank 1
5540 09:26:22.006173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 09:26:22.009394 ==
5542 09:26:22.009479 DQS Delay:
5543 09:26:22.009547 DQS0 = 0, DQS1 = 0
5544 09:26:22.012558 DQM Delay:
5545 09:26:22.012643 DQM0 = 103, DQM1 = 92
5546 09:26:22.016159 DQ Delay:
5547 09:26:22.019211 DQ0 =102, DQ1 =106, DQ2 =100, DQ3 =98
5548 09:26:22.022849 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =112
5549 09:26:22.026153 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =90
5550 09:26:22.029366 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5551 09:26:22.029452
5552 09:26:22.029519
5553 09:26:22.035812 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5554 09:26:22.039418 CH0 RK1: MR19=505, MR18=2F11
5555 09:26:22.046052 CH0_RK1: MR19=0x505, MR18=0x2F11, DQSOSC=407, MR23=63, INC=65, DEC=43
5556 09:26:22.049336 [RxdqsGatingPostProcess] freq 933
5557 09:26:22.052591 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5558 09:26:22.055769 best DQS0 dly(2T, 0.5T) = (0, 10)
5559 09:26:22.059395 best DQS1 dly(2T, 0.5T) = (0, 10)
5560 09:26:22.062673 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5561 09:26:22.065981 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5562 09:26:22.069141 best DQS0 dly(2T, 0.5T) = (0, 10)
5563 09:26:22.072451 best DQS1 dly(2T, 0.5T) = (0, 10)
5564 09:26:22.075607 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5565 09:26:22.079414 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5566 09:26:22.082706 Pre-setting of DQS Precalculation
5567 09:26:22.085896 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5568 09:26:22.085972 ==
5569 09:26:22.089319 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 09:26:22.095816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 09:26:22.095893 ==
5572 09:26:22.099045 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5573 09:26:22.105820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5574 09:26:22.109021 [CA 0] Center 37 (7~68) winsize 62
5575 09:26:22.112229 [CA 1] Center 37 (7~68) winsize 62
5576 09:26:22.115509 [CA 2] Center 35 (5~66) winsize 62
5577 09:26:22.119058 [CA 3] Center 34 (4~65) winsize 62
5578 09:26:22.122148 [CA 4] Center 34 (4~65) winsize 62
5579 09:26:22.125812 [CA 5] Center 34 (4~65) winsize 62
5580 09:26:22.125891
5581 09:26:22.129064 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5582 09:26:22.129139
5583 09:26:22.132418 [CATrainingPosCal] consider 1 rank data
5584 09:26:22.135625 u2DelayCellTimex100 = 270/100 ps
5585 09:26:22.138969 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5586 09:26:22.142203 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5587 09:26:22.148765 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5588 09:26:22.152067 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5589 09:26:22.155864 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5590 09:26:22.158999 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5591 09:26:22.159076
5592 09:26:22.162274 CA PerBit enable=1, Macro0, CA PI delay=34
5593 09:26:22.162347
5594 09:26:22.165554 [CBTSetCACLKResult] CA Dly = 34
5595 09:26:22.165633 CS Dly: 6 (0~37)
5596 09:26:22.165695 ==
5597 09:26:22.168738 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 09:26:22.175887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 09:26:22.175963 ==
5600 09:26:22.179073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5601 09:26:22.185646 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5602 09:26:22.188861 [CA 0] Center 38 (8~68) winsize 61
5603 09:26:22.192119 [CA 1] Center 38 (8~68) winsize 61
5604 09:26:22.195419 [CA 2] Center 35 (5~66) winsize 62
5605 09:26:22.198747 [CA 3] Center 35 (5~65) winsize 61
5606 09:26:22.201898 [CA 4] Center 35 (5~65) winsize 61
5607 09:26:22.205135 [CA 5] Center 35 (5~65) winsize 61
5608 09:26:22.205214
5609 09:26:22.208900 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5610 09:26:22.208975
5611 09:26:22.212035 [CATrainingPosCal] consider 2 rank data
5612 09:26:22.215116 u2DelayCellTimex100 = 270/100 ps
5613 09:26:22.218739 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5614 09:26:22.225243 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5615 09:26:22.228874 CA2 delay=35 (5~66),Diff = 0 PI (0 cell)
5616 09:26:22.232119 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5617 09:26:22.235352 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5618 09:26:22.238506 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5619 09:26:22.238595
5620 09:26:22.241774 CA PerBit enable=1, Macro0, CA PI delay=35
5621 09:26:22.241845
5622 09:26:22.245002 [CBTSetCACLKResult] CA Dly = 35
5623 09:26:22.245084 CS Dly: 7 (0~39)
5624 09:26:22.248707
5625 09:26:22.248774 ----->DramcWriteLeveling(PI) begin...
5626 09:26:22.252195 ==
5627 09:26:22.255514 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 09:26:22.258733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 09:26:22.258802 ==
5630 09:26:22.261895 Write leveling (Byte 0): 25 => 25
5631 09:26:22.265130 Write leveling (Byte 1): 30 => 30
5632 09:26:22.268524 DramcWriteLeveling(PI) end<-----
5633 09:26:22.268624
5634 09:26:22.268686 ==
5635 09:26:22.271777 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 09:26:22.274887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 09:26:22.274960 ==
5638 09:26:22.278646 [Gating] SW mode calibration
5639 09:26:22.285247 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5640 09:26:22.291819 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5641 09:26:22.295261 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 09:26:22.298577 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 09:26:22.304834 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 09:26:22.308719 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 09:26:22.311933 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 09:26:22.318240 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5647 09:26:22.321852 0 14 24 | B1->B0 | 3030 3030 | 1 0 | (1 1) (0 0)
5648 09:26:22.325241 0 14 28 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
5649 09:26:22.328356 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 09:26:22.334664 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 09:26:22.338410 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 09:26:22.341629 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 09:26:22.348442 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 09:26:22.351783 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 09:26:22.354993 0 15 24 | B1->B0 | 2626 2726 | 0 1 | (0 0) (0 0)
5656 09:26:22.361315 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5657 09:26:22.365153 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 09:26:22.368357 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 09:26:22.374810 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 09:26:22.378205 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 09:26:22.381478 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 09:26:22.387921 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5663 09:26:22.391659 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5664 09:26:22.394969 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 09:26:22.401498 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 09:26:22.404678 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 09:26:22.407792 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 09:26:22.414412 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 09:26:22.417767 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 09:26:22.421510 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 09:26:22.427711 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 09:26:22.431051 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 09:26:22.434770 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 09:26:22.441044 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 09:26:22.444739 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 09:26:22.447997 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 09:26:22.454434 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 09:26:22.457718 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 09:26:22.460979 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5680 09:26:22.464818 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5681 09:26:22.467996 Total UI for P1: 0, mck2ui 16
5682 09:26:22.471323 best dqsien dly found for B0: ( 1, 2, 24)
5683 09:26:22.477920 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 09:26:22.481278 Total UI for P1: 0, mck2ui 16
5685 09:26:22.484469 best dqsien dly found for B1: ( 1, 2, 26)
5686 09:26:22.487787 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5687 09:26:22.491171 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5688 09:26:22.491255
5689 09:26:22.494327 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5690 09:26:22.497603 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5691 09:26:22.500909 [Gating] SW calibration Done
5692 09:26:22.500992 ==
5693 09:26:22.504226 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 09:26:22.507554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 09:26:22.507638 ==
5696 09:26:22.510815 RX Vref Scan: 0
5697 09:26:22.510899
5698 09:26:22.514346 RX Vref 0 -> 0, step: 1
5699 09:26:22.514500
5700 09:26:22.514581 RX Delay -80 -> 252, step: 8
5701 09:26:22.520978 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5702 09:26:22.524203 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5703 09:26:22.527341 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5704 09:26:22.531017 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5705 09:26:22.534306 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5706 09:26:22.537650 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5707 09:26:22.544421 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5708 09:26:22.547734 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5709 09:26:22.550952 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5710 09:26:22.554224 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5711 09:26:22.557422 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5712 09:26:22.564381 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5713 09:26:22.567626 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5714 09:26:22.570876 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5715 09:26:22.574139 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5716 09:26:22.577923 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5717 09:26:22.578008 ==
5718 09:26:22.581202 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 09:26:22.587394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 09:26:22.587475 ==
5721 09:26:22.587542 DQS Delay:
5722 09:26:22.590527 DQS0 = 0, DQS1 = 0
5723 09:26:22.590642 DQM Delay:
5724 09:26:22.590734 DQM0 = 103, DQM1 = 96
5725 09:26:22.594374 DQ Delay:
5726 09:26:22.597123 DQ0 =103, DQ1 =99, DQ2 =91, DQ3 =103
5727 09:26:22.600865 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5728 09:26:22.604306 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5729 09:26:22.607596 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5730 09:26:22.607694
5731 09:26:22.607785
5732 09:26:22.607874 ==
5733 09:26:22.610814 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 09:26:22.614119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 09:26:22.614284 ==
5736 09:26:22.617563
5737 09:26:22.617649
5738 09:26:22.617715 TX Vref Scan disable
5739 09:26:22.620321 == TX Byte 0 ==
5740 09:26:22.623587 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5741 09:26:22.627325 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5742 09:26:22.630519 == TX Byte 1 ==
5743 09:26:22.633696 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5744 09:26:22.637506 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5745 09:26:22.637593 ==
5746 09:26:22.640199 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 09:26:22.647011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 09:26:22.647124 ==
5749 09:26:22.647222
5750 09:26:22.647322
5751 09:26:22.647413 TX Vref Scan disable
5752 09:26:22.651466 == TX Byte 0 ==
5753 09:26:22.654683 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5754 09:26:22.657756 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5755 09:26:22.661025 == TX Byte 1 ==
5756 09:26:22.664725 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5757 09:26:22.671263 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5758 09:26:22.671367
5759 09:26:22.671461 [DATLAT]
5760 09:26:22.671560 Freq=933, CH1 RK0
5761 09:26:22.671649
5762 09:26:22.674458 DATLAT Default: 0xd
5763 09:26:22.674550 0, 0xFFFF, sum = 0
5764 09:26:22.677848 1, 0xFFFF, sum = 0
5765 09:26:22.677927 2, 0xFFFF, sum = 0
5766 09:26:22.681027 3, 0xFFFF, sum = 0
5767 09:26:22.681100 4, 0xFFFF, sum = 0
5768 09:26:22.684738 5, 0xFFFF, sum = 0
5769 09:26:22.688114 6, 0xFFFF, sum = 0
5770 09:26:22.688204 7, 0xFFFF, sum = 0
5771 09:26:22.691292 8, 0xFFFF, sum = 0
5772 09:26:22.691394 9, 0xFFFF, sum = 0
5773 09:26:22.694597 10, 0x0, sum = 1
5774 09:26:22.694701 11, 0x0, sum = 2
5775 09:26:22.697899 12, 0x0, sum = 3
5776 09:26:22.697999 13, 0x0, sum = 4
5777 09:26:22.698093 best_step = 11
5778 09:26:22.698182
5779 09:26:22.701164 ==
5780 09:26:22.704410 Dram Type= 6, Freq= 0, CH_1, rank 0
5781 09:26:22.707819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 09:26:22.707920 ==
5783 09:26:22.708021 RX Vref Scan: 1
5784 09:26:22.708112
5785 09:26:22.711138 RX Vref 0 -> 0, step: 1
5786 09:26:22.711234
5787 09:26:22.714379 RX Delay -53 -> 252, step: 4
5788 09:26:22.714483
5789 09:26:22.717635 Set Vref, RX VrefLevel [Byte0]: 51
5790 09:26:22.720913 [Byte1]: 53
5791 09:26:22.720989
5792 09:26:22.724233 Final RX Vref Byte 0 = 51 to rank0
5793 09:26:22.728032 Final RX Vref Byte 1 = 53 to rank0
5794 09:26:22.731350 Final RX Vref Byte 0 = 51 to rank1
5795 09:26:22.734578 Final RX Vref Byte 1 = 53 to rank1==
5796 09:26:22.737748 Dram Type= 6, Freq= 0, CH_1, rank 0
5797 09:26:22.741007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 09:26:22.741084 ==
5799 09:26:22.744297 DQS Delay:
5800 09:26:22.744397 DQS0 = 0, DQS1 = 0
5801 09:26:22.747608 DQM Delay:
5802 09:26:22.747715 DQM0 = 104, DQM1 = 98
5803 09:26:22.747808 DQ Delay:
5804 09:26:22.750836 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5805 09:26:22.754281 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5806 09:26:22.757929 DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =94
5807 09:26:22.764372 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =104
5808 09:26:22.764476
5809 09:26:22.764602
5810 09:26:22.771358 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5811 09:26:22.774610 CH1 RK0: MR19=505, MR18=1B33
5812 09:26:22.780904 CH1_RK0: MR19=0x505, MR18=0x1B33, DQSOSC=405, MR23=63, INC=66, DEC=44
5813 09:26:22.780985
5814 09:26:22.784263 ----->DramcWriteLeveling(PI) begin...
5815 09:26:22.784365 ==
5816 09:26:22.787524 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 09:26:22.791248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 09:26:22.791325 ==
5819 09:26:22.794531 Write leveling (Byte 0): 27 => 27
5820 09:26:22.797824 Write leveling (Byte 1): 27 => 27
5821 09:26:22.801281 DramcWriteLeveling(PI) end<-----
5822 09:26:22.801356
5823 09:26:22.801421 ==
5824 09:26:22.804591 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 09:26:22.807883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 09:26:22.807960 ==
5827 09:26:22.811123 [Gating] SW mode calibration
5828 09:26:22.817602 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5829 09:26:22.824491 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5830 09:26:22.827725 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 09:26:22.831002 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 09:26:22.837609 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 09:26:22.840815 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 09:26:22.844126 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 09:26:22.851178 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 09:26:22.854304 0 14 24 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (1 0)
5837 09:26:22.857890 0 14 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 1)
5838 09:26:22.864288 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5839 09:26:22.867493 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 09:26:22.870798 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 09:26:22.877722 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 09:26:22.881130 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 09:26:22.884352 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 09:26:22.890857 0 15 24 | B1->B0 | 2e2d 2323 | 1 0 | (0 0) (0 0)
5845 09:26:22.894102 0 15 28 | B1->B0 | 4343 3939 | 0 0 | (0 0) (0 0)
5846 09:26:22.897320 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 09:26:22.903997 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 09:26:22.907368 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 09:26:22.910698 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 09:26:22.917765 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 09:26:22.921057 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 09:26:22.924311 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 09:26:22.930985 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5854 09:26:22.934161 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 09:26:22.937532 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 09:26:22.944009 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 09:26:22.947935 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 09:26:22.950934 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 09:26:22.954229 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 09:26:22.961205 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 09:26:22.964308 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 09:26:22.967302 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 09:26:22.974009 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 09:26:22.977107 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 09:26:22.980377 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 09:26:22.987007 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 09:26:22.990711 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 09:26:22.993779 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 09:26:23.000401 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5870 09:26:23.003707 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 09:26:23.007049 Total UI for P1: 0, mck2ui 16
5872 09:26:23.010277 best dqsien dly found for B0: ( 1, 2, 28)
5873 09:26:23.013615 Total UI for P1: 0, mck2ui 16
5874 09:26:23.016933 best dqsien dly found for B1: ( 1, 2, 28)
5875 09:26:23.020251 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5876 09:26:23.023423 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5877 09:26:23.023502
5878 09:26:23.027219 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5879 09:26:23.030036 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5880 09:26:23.033716 [Gating] SW calibration Done
5881 09:26:23.033797 ==
5882 09:26:23.036873 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 09:26:23.043506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 09:26:23.043662 ==
5885 09:26:23.043757 RX Vref Scan: 0
5886 09:26:23.043847
5887 09:26:23.046818 RX Vref 0 -> 0, step: 1
5888 09:26:23.046920
5889 09:26:23.050381 RX Delay -80 -> 252, step: 8
5890 09:26:23.053636 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5891 09:26:23.056769 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5892 09:26:23.060045 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5893 09:26:23.063311 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5894 09:26:23.070165 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5895 09:26:23.073359 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5896 09:26:23.076953 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5897 09:26:23.080225 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5898 09:26:23.083470 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5899 09:26:23.086809 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5900 09:26:23.093249 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5901 09:26:23.097111 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5902 09:26:23.100362 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5903 09:26:23.103699 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5904 09:26:23.106516 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5905 09:26:23.113210 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5906 09:26:23.113289 ==
5907 09:26:23.116442 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 09:26:23.119776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 09:26:23.119852 ==
5910 09:26:23.119918 DQS Delay:
5911 09:26:23.123037 DQS0 = 0, DQS1 = 0
5912 09:26:23.123111 DQM Delay:
5913 09:26:23.126773 DQM0 = 102, DQM1 = 95
5914 09:26:23.126844 DQ Delay:
5915 09:26:23.130060 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5916 09:26:23.133260 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =103
5917 09:26:23.136520 DQ8 =83, DQ9 =87, DQ10 =91, DQ11 =87
5918 09:26:23.139635 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5919 09:26:23.139705
5920 09:26:23.139768
5921 09:26:23.139828 ==
5922 09:26:23.142928 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 09:26:23.149404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 09:26:23.149480 ==
5925 09:26:23.149543
5926 09:26:23.149601
5927 09:26:23.149657 TX Vref Scan disable
5928 09:26:23.153265 == TX Byte 0 ==
5929 09:26:23.156417 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5930 09:26:23.163210 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5931 09:26:23.163287 == TX Byte 1 ==
5932 09:26:23.166624 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5933 09:26:23.169681 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5934 09:26:23.172867 ==
5935 09:26:23.176474 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 09:26:23.179620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 09:26:23.179695 ==
5938 09:26:23.179758
5939 09:26:23.179817
5940 09:26:23.183184 TX Vref Scan disable
5941 09:26:23.183255 == TX Byte 0 ==
5942 09:26:23.189671 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5943 09:26:23.192864 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5944 09:26:23.192934 == TX Byte 1 ==
5945 09:26:23.199823 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5946 09:26:23.202623 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5947 09:26:23.202695
5948 09:26:23.202758 [DATLAT]
5949 09:26:23.206396 Freq=933, CH1 RK1
5950 09:26:23.206467
5951 09:26:23.206526 DATLAT Default: 0xb
5952 09:26:23.209683 0, 0xFFFF, sum = 0
5953 09:26:23.209753 1, 0xFFFF, sum = 0
5954 09:26:23.212879 2, 0xFFFF, sum = 0
5955 09:26:23.212958 3, 0xFFFF, sum = 0
5956 09:26:23.216062 4, 0xFFFF, sum = 0
5957 09:26:23.216134 5, 0xFFFF, sum = 0
5958 09:26:23.219434 6, 0xFFFF, sum = 0
5959 09:26:23.219509 7, 0xFFFF, sum = 0
5960 09:26:23.222632 8, 0xFFFF, sum = 0
5961 09:26:23.226333 9, 0xFFFF, sum = 0
5962 09:26:23.226406 10, 0x0, sum = 1
5963 09:26:23.226469 11, 0x0, sum = 2
5964 09:26:23.229582 12, 0x0, sum = 3
5965 09:26:23.229654 13, 0x0, sum = 4
5966 09:26:23.232852 best_step = 11
5967 09:26:23.232937
5968 09:26:23.232996 ==
5969 09:26:23.236182 Dram Type= 6, Freq= 0, CH_1, rank 1
5970 09:26:23.239506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5971 09:26:23.239578 ==
5972 09:26:23.242710 RX Vref Scan: 0
5973 09:26:23.242776
5974 09:26:23.242838 RX Vref 0 -> 0, step: 1
5975 09:26:23.242896
5976 09:26:23.246030 RX Delay -53 -> 252, step: 4
5977 09:26:23.253535 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5978 09:26:23.256698 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5979 09:26:23.259893 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5980 09:26:23.263501 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5981 09:26:23.266574 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5982 09:26:23.273556 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5983 09:26:23.276736 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5984 09:26:23.279748 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5985 09:26:23.283402 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5986 09:26:23.286925 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5987 09:26:23.290120 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5988 09:26:23.296566 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5989 09:26:23.299802 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5990 09:26:23.303195 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5991 09:26:23.306520 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5992 09:26:23.309792 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5993 09:26:23.313508 ==
5994 09:26:23.316730 Dram Type= 6, Freq= 0, CH_1, rank 1
5995 09:26:23.320155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5996 09:26:23.320232 ==
5997 09:26:23.320295 DQS Delay:
5998 09:26:23.323435 DQS0 = 0, DQS1 = 0
5999 09:26:23.323509 DQM Delay:
6000 09:26:23.326670 DQM0 = 104, DQM1 = 97
6001 09:26:23.326743 DQ Delay:
6002 09:26:23.329916 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
6003 09:26:23.333228 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
6004 09:26:23.336487 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =92
6005 09:26:23.340147 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =106
6006 09:26:23.340220
6007 09:26:23.340281
6008 09:26:23.349883 [DQSOSCAuto] RK1, (LSB)MR18= 0x2906, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
6009 09:26:23.349974 CH1 RK1: MR19=505, MR18=2906
6010 09:26:23.356500 CH1_RK1: MR19=0x505, MR18=0x2906, DQSOSC=408, MR23=63, INC=65, DEC=43
6011 09:26:23.359796 [RxdqsGatingPostProcess] freq 933
6012 09:26:23.366728 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6013 09:26:23.369659 best DQS0 dly(2T, 0.5T) = (0, 10)
6014 09:26:23.373166 best DQS1 dly(2T, 0.5T) = (0, 10)
6015 09:26:23.376328 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6016 09:26:23.379626 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6017 09:26:23.379711 best DQS0 dly(2T, 0.5T) = (0, 10)
6018 09:26:23.383319 best DQS1 dly(2T, 0.5T) = (0, 10)
6019 09:26:23.386330 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6020 09:26:23.389760 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6021 09:26:23.392928 Pre-setting of DQS Precalculation
6022 09:26:23.400112 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6023 09:26:23.406613 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6024 09:26:23.413207 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6025 09:26:23.413293
6026 09:26:23.413359
6027 09:26:23.416438 [Calibration Summary] 1866 Mbps
6028 09:26:23.416524 CH 0, Rank 0
6029 09:26:23.419835 SW Impedance : PASS
6030 09:26:23.423044 DUTY Scan : NO K
6031 09:26:23.423151 ZQ Calibration : PASS
6032 09:26:23.426259 Jitter Meter : NO K
6033 09:26:23.429895 CBT Training : PASS
6034 09:26:23.430007 Write leveling : PASS
6035 09:26:23.433197 RX DQS gating : PASS
6036 09:26:23.436469 RX DQ/DQS(RDDQC) : PASS
6037 09:26:23.436588 TX DQ/DQS : PASS
6038 09:26:23.439754 RX DATLAT : PASS
6039 09:26:23.443037 RX DQ/DQS(Engine): PASS
6040 09:26:23.443148 TX OE : NO K
6041 09:26:23.443241 All Pass.
6042 09:26:23.443330
6043 09:26:23.446238 CH 0, Rank 1
6044 09:26:23.446342 SW Impedance : PASS
6045 09:26:23.449595 DUTY Scan : NO K
6046 09:26:23.453432 ZQ Calibration : PASS
6047 09:26:23.453539 Jitter Meter : NO K
6048 09:26:23.456179 CBT Training : PASS
6049 09:26:23.460089 Write leveling : PASS
6050 09:26:23.460163 RX DQS gating : PASS
6051 09:26:23.463355 RX DQ/DQS(RDDQC) : PASS
6052 09:26:23.466713 TX DQ/DQS : PASS
6053 09:26:23.466786 RX DATLAT : PASS
6054 09:26:23.469799 RX DQ/DQS(Engine): PASS
6055 09:26:23.473330 TX OE : NO K
6056 09:26:23.473435 All Pass.
6057 09:26:23.473527
6058 09:26:23.473616 CH 1, Rank 0
6059 09:26:23.476328 SW Impedance : PASS
6060 09:26:23.479909 DUTY Scan : NO K
6061 09:26:23.479985 ZQ Calibration : PASS
6062 09:26:23.483265 Jitter Meter : NO K
6063 09:26:23.486619 CBT Training : PASS
6064 09:26:23.486690 Write leveling : PASS
6065 09:26:23.489650 RX DQS gating : PASS
6066 09:26:23.489725 RX DQ/DQS(RDDQC) : PASS
6067 09:26:23.493344 TX DQ/DQS : PASS
6068 09:26:23.496326 RX DATLAT : PASS
6069 09:26:23.496400 RX DQ/DQS(Engine): PASS
6070 09:26:23.500180 TX OE : NO K
6071 09:26:23.500283 All Pass.
6072 09:26:23.500375
6073 09:26:23.503372 CH 1, Rank 1
6074 09:26:23.503476 SW Impedance : PASS
6075 09:26:23.506478 DUTY Scan : NO K
6076 09:26:23.509714 ZQ Calibration : PASS
6077 09:26:23.509791 Jitter Meter : NO K
6078 09:26:23.512870 CBT Training : PASS
6079 09:26:23.516193 Write leveling : PASS
6080 09:26:23.516264 RX DQS gating : PASS
6081 09:26:23.519476 RX DQ/DQS(RDDQC) : PASS
6082 09:26:23.523293 TX DQ/DQS : PASS
6083 09:26:23.523399 RX DATLAT : PASS
6084 09:26:23.526128 RX DQ/DQS(Engine): PASS
6085 09:26:23.529822 TX OE : NO K
6086 09:26:23.529926 All Pass.
6087 09:26:23.530022
6088 09:26:23.530115 DramC Write-DBI off
6089 09:26:23.533144 PER_BANK_REFRESH: Hybrid Mode
6090 09:26:23.536364 TX_TRACKING: ON
6091 09:26:23.542825 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6092 09:26:23.546157 [FAST_K] Save calibration result to emmc
6093 09:26:23.553235 dramc_set_vcore_voltage set vcore to 650000
6094 09:26:23.553341 Read voltage for 400, 6
6095 09:26:23.556481 Vio18 = 0
6096 09:26:23.556620 Vcore = 650000
6097 09:26:23.556717 Vdram = 0
6098 09:26:23.556810 Vddq = 0
6099 09:26:23.559379 Vmddr = 0
6100 09:26:23.562679 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6101 09:26:23.569559 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6102 09:26:23.572698 MEM_TYPE=3, freq_sel=20
6103 09:26:23.572805 sv_algorithm_assistance_LP4_800
6104 09:26:23.579312 ============ PULL DRAM RESETB DOWN ============
6105 09:26:23.582886 ========== PULL DRAM RESETB DOWN end =========
6106 09:26:23.585992 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6107 09:26:23.589127 ===================================
6108 09:26:23.593000 LPDDR4 DRAM CONFIGURATION
6109 09:26:23.595996 ===================================
6110 09:26:23.599129 EX_ROW_EN[0] = 0x0
6111 09:26:23.599238 EX_ROW_EN[1] = 0x0
6112 09:26:23.602704 LP4Y_EN = 0x0
6113 09:26:23.602805 WORK_FSP = 0x0
6114 09:26:23.605946 WL = 0x2
6115 09:26:23.606038 RL = 0x2
6116 09:26:23.609157 BL = 0x2
6117 09:26:23.609229 RPST = 0x0
6118 09:26:23.612386 RD_PRE = 0x0
6119 09:26:23.612521 WR_PRE = 0x1
6120 09:26:23.615740 WR_PST = 0x0
6121 09:26:23.615838 DBI_WR = 0x0
6122 09:26:23.619264 DBI_RD = 0x0
6123 09:26:23.622511 OTF = 0x1
6124 09:26:23.622616 ===================================
6125 09:26:23.625735 ===================================
6126 09:26:23.628959 ANA top config
6127 09:26:23.632209 ===================================
6128 09:26:23.636089 DLL_ASYNC_EN = 0
6129 09:26:23.636175 ALL_SLAVE_EN = 1
6130 09:26:23.639299 NEW_RANK_MODE = 1
6131 09:26:23.642608 DLL_IDLE_MODE = 1
6132 09:26:23.645846 LP45_APHY_COMB_EN = 1
6133 09:26:23.649058 TX_ODT_DIS = 1
6134 09:26:23.649143 NEW_8X_MODE = 1
6135 09:26:23.652340 ===================================
6136 09:26:23.655499 ===================================
6137 09:26:23.659320 data_rate = 800
6138 09:26:23.662689 CKR = 1
6139 09:26:23.665959 DQ_P2S_RATIO = 4
6140 09:26:23.669184 ===================================
6141 09:26:23.672376 CA_P2S_RATIO = 4
6142 09:26:23.675681 DQ_CA_OPEN = 0
6143 09:26:23.675765 DQ_SEMI_OPEN = 1
6144 09:26:23.678849 CA_SEMI_OPEN = 1
6145 09:26:23.682566 CA_FULL_RATE = 0
6146 09:26:23.685568 DQ_CKDIV4_EN = 0
6147 09:26:23.689244 CA_CKDIV4_EN = 1
6148 09:26:23.689355 CA_PREDIV_EN = 0
6149 09:26:23.692369 PH8_DLY = 0
6150 09:26:23.695655 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6151 09:26:23.698826 DQ_AAMCK_DIV = 0
6152 09:26:23.702495 CA_AAMCK_DIV = 0
6153 09:26:23.705536 CA_ADMCK_DIV = 4
6154 09:26:23.705659 DQ_TRACK_CA_EN = 0
6155 09:26:23.709205 CA_PICK = 800
6156 09:26:23.712373 CA_MCKIO = 400
6157 09:26:23.715648 MCKIO_SEMI = 400
6158 09:26:23.719104 PLL_FREQ = 3016
6159 09:26:23.722355 DQ_UI_PI_RATIO = 32
6160 09:26:23.725726 CA_UI_PI_RATIO = 32
6161 09:26:23.728927 ===================================
6162 09:26:23.732172 ===================================
6163 09:26:23.732274 memory_type:LPDDR4
6164 09:26:23.735482 GP_NUM : 10
6165 09:26:23.739192 SRAM_EN : 1
6166 09:26:23.739265 MD32_EN : 0
6167 09:26:23.742371 ===================================
6168 09:26:23.745661 [ANA_INIT] >>>>>>>>>>>>>>
6169 09:26:23.748914 <<<<<< [CONFIGURE PHASE]: ANA_TX
6170 09:26:23.752099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6171 09:26:23.755895 ===================================
6172 09:26:23.759318 data_rate = 800,PCW = 0X7400
6173 09:26:23.762592 ===================================
6174 09:26:23.765854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6175 09:26:23.769009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6176 09:26:23.782374 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6177 09:26:23.785611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6178 09:26:23.789161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6179 09:26:23.792312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6180 09:26:23.795476 [ANA_INIT] flow start
6181 09:26:23.795571 [ANA_INIT] PLL >>>>>>>>
6182 09:26:23.799209 [ANA_INIT] PLL <<<<<<<<
6183 09:26:23.802412 [ANA_INIT] MIDPI >>>>>>>>
6184 09:26:23.805565 [ANA_INIT] MIDPI <<<<<<<<
6185 09:26:23.805649 [ANA_INIT] DLL >>>>>>>>
6186 09:26:23.808985 [ANA_INIT] flow end
6187 09:26:23.812500 ============ LP4 DIFF to SE enter ============
6188 09:26:23.815753 ============ LP4 DIFF to SE exit ============
6189 09:26:23.818997 [ANA_INIT] <<<<<<<<<<<<<
6190 09:26:23.822739 [Flow] Enable top DCM control >>>>>
6191 09:26:23.825983 [Flow] Enable top DCM control <<<<<
6192 09:26:23.829319 Enable DLL master slave shuffle
6193 09:26:23.832505 ==============================================================
6194 09:26:23.835709 Gating Mode config
6195 09:26:23.842702 ==============================================================
6196 09:26:23.842804 Config description:
6197 09:26:23.852482 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6198 09:26:23.859055 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6199 09:26:23.865735 SELPH_MODE 0: By rank 1: By Phase
6200 09:26:23.869209 ==============================================================
6201 09:26:23.872423 GAT_TRACK_EN = 0
6202 09:26:23.875616 RX_GATING_MODE = 2
6203 09:26:23.879057 RX_GATING_TRACK_MODE = 2
6204 09:26:23.882280 SELPH_MODE = 1
6205 09:26:23.885385 PICG_EARLY_EN = 1
6206 09:26:23.889245 VALID_LAT_VALUE = 1
6207 09:26:23.892465 ==============================================================
6208 09:26:23.895588 Enter into Gating configuration >>>>
6209 09:26:23.899259 Exit from Gating configuration <<<<
6210 09:26:23.902447 Enter into DVFS_PRE_config >>>>>
6211 09:26:23.915852 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6212 09:26:23.915975 Exit from DVFS_PRE_config <<<<<
6213 09:26:23.918903 Enter into PICG configuration >>>>
6214 09:26:23.921997 Exit from PICG configuration <<<<
6215 09:26:23.925797 [RX_INPUT] configuration >>>>>
6216 09:26:23.929074 [RX_INPUT] configuration <<<<<
6217 09:26:23.935582 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6218 09:26:23.939286 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6219 09:26:23.945691 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6220 09:26:23.952108 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6221 09:26:23.959136 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6222 09:26:23.965770 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6223 09:26:23.969048 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6224 09:26:23.972408 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6225 09:26:23.975597 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6226 09:26:23.982598 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6227 09:26:23.985830 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6228 09:26:23.989089 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6229 09:26:23.992270 ===================================
6230 09:26:23.995532 LPDDR4 DRAM CONFIGURATION
6231 09:26:23.999173 ===================================
6232 09:26:23.999272 EX_ROW_EN[0] = 0x0
6233 09:26:24.002322 EX_ROW_EN[1] = 0x0
6234 09:26:24.005503 LP4Y_EN = 0x0
6235 09:26:24.005605 WORK_FSP = 0x0
6236 09:26:24.008761 WL = 0x2
6237 09:26:24.008837 RL = 0x2
6238 09:26:24.012065 BL = 0x2
6239 09:26:24.012164 RPST = 0x0
6240 09:26:24.015293 RD_PRE = 0x0
6241 09:26:24.015393 WR_PRE = 0x1
6242 09:26:24.019025 WR_PST = 0x0
6243 09:26:24.019131 DBI_WR = 0x0
6244 09:26:24.022097 DBI_RD = 0x0
6245 09:26:24.022199 OTF = 0x1
6246 09:26:24.025267 ===================================
6247 09:26:24.028504 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6248 09:26:24.035521 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6249 09:26:24.038714 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6250 09:26:24.041949 ===================================
6251 09:26:24.045170 LPDDR4 DRAM CONFIGURATION
6252 09:26:24.048449 ===================================
6253 09:26:24.048571 EX_ROW_EN[0] = 0x10
6254 09:26:24.051743 EX_ROW_EN[1] = 0x0
6255 09:26:24.051818 LP4Y_EN = 0x0
6256 09:26:24.055536 WORK_FSP = 0x0
6257 09:26:24.055636 WL = 0x2
6258 09:26:24.058790 RL = 0x2
6259 09:26:24.062093 BL = 0x2
6260 09:26:24.062172 RPST = 0x0
6261 09:26:24.065451 RD_PRE = 0x0
6262 09:26:24.065526 WR_PRE = 0x1
6263 09:26:24.068301 WR_PST = 0x0
6264 09:26:24.068402 DBI_WR = 0x0
6265 09:26:24.071532 DBI_RD = 0x0
6266 09:26:24.071645 OTF = 0x1
6267 09:26:24.075341 ===================================
6268 09:26:24.081934 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6269 09:26:24.085699 nWR fixed to 30
6270 09:26:24.089059 [ModeRegInit_LP4] CH0 RK0
6271 09:26:24.089135 [ModeRegInit_LP4] CH0 RK1
6272 09:26:24.092218 [ModeRegInit_LP4] CH1 RK0
6273 09:26:24.095972 [ModeRegInit_LP4] CH1 RK1
6274 09:26:24.096046 match AC timing 19
6275 09:26:24.102402 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6276 09:26:24.105614 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6277 09:26:24.109225 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6278 09:26:24.115575 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6279 09:26:24.118836 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6280 09:26:24.118945 ==
6281 09:26:24.122180 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 09:26:24.125338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 09:26:24.125417 ==
6284 09:26:24.132270 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6285 09:26:24.138764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6286 09:26:24.142080 [CA 0] Center 36 (8~64) winsize 57
6287 09:26:24.145284 [CA 1] Center 36 (8~64) winsize 57
6288 09:26:24.148559 [CA 2] Center 36 (8~64) winsize 57
6289 09:26:24.148644 [CA 3] Center 36 (8~64) winsize 57
6290 09:26:24.152399 [CA 4] Center 36 (8~64) winsize 57
6291 09:26:24.155578 [CA 5] Center 36 (8~64) winsize 57
6292 09:26:24.155658
6293 09:26:24.162221 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6294 09:26:24.162305
6295 09:26:24.165507 [CATrainingPosCal] consider 1 rank data
6296 09:26:24.165584 u2DelayCellTimex100 = 270/100 ps
6297 09:26:24.172127 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 09:26:24.175397 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 09:26:24.178702 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 09:26:24.181878 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 09:26:24.185301 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 09:26:24.188990 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 09:26:24.189063
6304 09:26:24.192288 CA PerBit enable=1, Macro0, CA PI delay=36
6305 09:26:24.192361
6306 09:26:24.195446 [CBTSetCACLKResult] CA Dly = 36
6307 09:26:24.198670 CS Dly: 1 (0~32)
6308 09:26:24.198744 ==
6309 09:26:24.202318 Dram Type= 6, Freq= 0, CH_0, rank 1
6310 09:26:24.205563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 09:26:24.205637 ==
6312 09:26:24.211894 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6313 09:26:24.215695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6314 09:26:24.218791 [CA 0] Center 36 (8~64) winsize 57
6315 09:26:24.222055 [CA 1] Center 36 (8~64) winsize 57
6316 09:26:24.225743 [CA 2] Center 36 (8~64) winsize 57
6317 09:26:24.229169 [CA 3] Center 36 (8~64) winsize 57
6318 09:26:24.232277 [CA 4] Center 36 (8~64) winsize 57
6319 09:26:24.235580 [CA 5] Center 36 (8~64) winsize 57
6320 09:26:24.235661
6321 09:26:24.238696 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6322 09:26:24.238771
6323 09:26:24.242089 [CATrainingPosCal] consider 2 rank data
6324 09:26:24.245770 u2DelayCellTimex100 = 270/100 ps
6325 09:26:24.248881 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 09:26:24.252185 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 09:26:24.255509 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 09:26:24.258677 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 09:26:24.265273 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 09:26:24.268997 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 09:26:24.269097
6332 09:26:24.272338 CA PerBit enable=1, Macro0, CA PI delay=36
6333 09:26:24.272439
6334 09:26:24.275434 [CBTSetCACLKResult] CA Dly = 36
6335 09:26:24.275519 CS Dly: 1 (0~32)
6336 09:26:24.275615
6337 09:26:24.278809 ----->DramcWriteLeveling(PI) begin...
6338 09:26:24.278910 ==
6339 09:26:24.282083 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 09:26:24.288407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 09:26:24.288519 ==
6342 09:26:24.292150 Write leveling (Byte 0): 40 => 8
6343 09:26:24.292226 Write leveling (Byte 1): 32 => 0
6344 09:26:24.295436 DramcWriteLeveling(PI) end<-----
6345 09:26:24.295508
6346 09:26:24.295570 ==
6347 09:26:24.298557 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 09:26:24.305461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 09:26:24.305546 ==
6350 09:26:24.308796 [Gating] SW mode calibration
6351 09:26:24.315322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6352 09:26:24.318387 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6353 09:26:24.325228 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6354 09:26:24.328439 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6355 09:26:24.331686 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 09:26:24.338647 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 09:26:24.341865 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6358 09:26:24.345225 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 09:26:24.351579 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 09:26:24.354799 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 09:26:24.358112 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6362 09:26:24.361894 Total UI for P1: 0, mck2ui 16
6363 09:26:24.365079 best dqsien dly found for B0: ( 0, 14, 24)
6364 09:26:24.368308 Total UI for P1: 0, mck2ui 16
6365 09:26:24.371631 best dqsien dly found for B1: ( 0, 14, 24)
6366 09:26:24.374905 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6367 09:26:24.378374 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6368 09:26:24.378457
6369 09:26:24.381578 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6370 09:26:24.388051 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6371 09:26:24.388168 [Gating] SW calibration Done
6372 09:26:24.391739 ==
6373 09:26:24.391858 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 09:26:24.398004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 09:26:24.398089 ==
6376 09:26:24.398156 RX Vref Scan: 0
6377 09:26:24.398219
6378 09:26:24.401719 RX Vref 0 -> 0, step: 1
6379 09:26:24.401817
6380 09:26:24.404985 RX Delay -410 -> 252, step: 16
6381 09:26:24.408232 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6382 09:26:24.411434 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6383 09:26:24.417994 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6384 09:26:24.421193 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6385 09:26:24.424848 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6386 09:26:24.427901 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6387 09:26:24.434858 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6388 09:26:24.438220 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6389 09:26:24.441384 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6390 09:26:24.444889 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6391 09:26:24.451444 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6392 09:26:24.454689 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6393 09:26:24.457884 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6394 09:26:24.461188 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6395 09:26:24.467762 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6396 09:26:24.471065 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6397 09:26:24.471149 ==
6398 09:26:24.474850 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 09:26:24.478132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 09:26:24.478217 ==
6401 09:26:24.481440 DQS Delay:
6402 09:26:24.481523 DQS0 = 27, DQS1 = 43
6403 09:26:24.484732 DQM Delay:
6404 09:26:24.484814 DQM0 = 12, DQM1 = 11
6405 09:26:24.484880 DQ Delay:
6406 09:26:24.488033 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6407 09:26:24.491295 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6408 09:26:24.494518 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6409 09:26:24.497637 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6410 09:26:24.497719
6411 09:26:24.497783
6412 09:26:24.497843 ==
6413 09:26:24.501495 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 09:26:24.507872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 09:26:24.507955 ==
6416 09:26:24.508020
6417 09:26:24.508080
6418 09:26:24.508154 TX Vref Scan disable
6419 09:26:24.511163 == TX Byte 0 ==
6420 09:26:24.514377 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6421 09:26:24.517640 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6422 09:26:24.521069 == TX Byte 1 ==
6423 09:26:24.524293 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6424 09:26:24.527515 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6425 09:26:24.527598 ==
6426 09:26:24.531180 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 09:26:24.537507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 09:26:24.537590 ==
6429 09:26:24.537655
6430 09:26:24.537715
6431 09:26:24.540758 TX Vref Scan disable
6432 09:26:24.540840 == TX Byte 0 ==
6433 09:26:24.544453 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6434 09:26:24.550674 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6435 09:26:24.550758 == TX Byte 1 ==
6436 09:26:24.554412 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6437 09:26:24.560838 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6438 09:26:24.560921
6439 09:26:24.560987 [DATLAT]
6440 09:26:24.561047 Freq=400, CH0 RK0
6441 09:26:24.561106
6442 09:26:24.564082 DATLAT Default: 0xf
6443 09:26:24.564171 0, 0xFFFF, sum = 0
6444 09:26:24.567348 1, 0xFFFF, sum = 0
6445 09:26:24.567435 2, 0xFFFF, sum = 0
6446 09:26:24.570596 3, 0xFFFF, sum = 0
6447 09:26:24.573883 4, 0xFFFF, sum = 0
6448 09:26:24.573969 5, 0xFFFF, sum = 0
6449 09:26:24.577681 6, 0xFFFF, sum = 0
6450 09:26:24.577767 7, 0xFFFF, sum = 0
6451 09:26:24.580943 8, 0xFFFF, sum = 0
6452 09:26:24.581029 9, 0xFFFF, sum = 0
6453 09:26:24.584233 10, 0xFFFF, sum = 0
6454 09:26:24.584318 11, 0xFFFF, sum = 0
6455 09:26:24.587482 12, 0xFFFF, sum = 0
6456 09:26:24.587585 13, 0x0, sum = 1
6457 09:26:24.590762 14, 0x0, sum = 2
6458 09:26:24.590848 15, 0x0, sum = 3
6459 09:26:24.593985 16, 0x0, sum = 4
6460 09:26:24.594071 best_step = 14
6461 09:26:24.594137
6462 09:26:24.594197 ==
6463 09:26:24.597258 Dram Type= 6, Freq= 0, CH_0, rank 0
6464 09:26:24.600451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 09:26:24.603791 ==
6466 09:26:24.603875 RX Vref Scan: 1
6467 09:26:24.603975
6468 09:26:24.607100 RX Vref 0 -> 0, step: 1
6469 09:26:24.607185
6470 09:26:24.610796 RX Delay -327 -> 252, step: 8
6471 09:26:24.610881
6472 09:26:24.610947 Set Vref, RX VrefLevel [Byte0]: 59
6473 09:26:24.614085 [Byte1]: 50
6474 09:26:24.619558
6475 09:26:24.619643 Final RX Vref Byte 0 = 59 to rank0
6476 09:26:24.622748 Final RX Vref Byte 1 = 50 to rank0
6477 09:26:24.626029 Final RX Vref Byte 0 = 59 to rank1
6478 09:26:24.629742 Final RX Vref Byte 1 = 50 to rank1==
6479 09:26:24.633096 Dram Type= 6, Freq= 0, CH_0, rank 0
6480 09:26:24.639407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 09:26:24.639481 ==
6482 09:26:24.639543 DQS Delay:
6483 09:26:24.639606 DQS0 = 28, DQS1 = 48
6484 09:26:24.643111 DQM Delay:
6485 09:26:24.643181 DQM0 = 11, DQM1 = 14
6486 09:26:24.646394 DQ Delay:
6487 09:26:24.649555 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6488 09:26:24.649625 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6489 09:26:24.652788 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6490 09:26:24.656315 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6491 09:26:24.656384
6492 09:26:24.656445
6493 09:26:24.666214 [DQSOSCAuto] RK0, (LSB)MR18= 0xb5ad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6494 09:26:24.669418 CH0 RK0: MR19=C0C, MR18=B5AD
6495 09:26:24.676075 CH0_RK0: MR19=0xC0C, MR18=0xB5AD, DQSOSC=387, MR23=63, INC=394, DEC=262
6496 09:26:24.676150 ==
6497 09:26:24.679760 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 09:26:24.683060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 09:26:24.683143 ==
6500 09:26:24.685844 [Gating] SW mode calibration
6501 09:26:24.692925 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6502 09:26:24.696222 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6503 09:26:24.702768 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6504 09:26:24.706075 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6505 09:26:24.709258 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 09:26:24.716241 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 09:26:24.719385 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 09:26:24.722600 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 09:26:24.729428 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 09:26:24.732704 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 09:26:24.735857 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6512 09:26:24.739663 Total UI for P1: 0, mck2ui 16
6513 09:26:24.742779 best dqsien dly found for B0: ( 0, 14, 24)
6514 09:26:24.745909 Total UI for P1: 0, mck2ui 16
6515 09:26:24.749699 best dqsien dly found for B1: ( 0, 14, 24)
6516 09:26:24.752969 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6517 09:26:24.756167 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6518 09:26:24.756251
6519 09:26:24.762827 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6520 09:26:24.766108 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6521 09:26:24.766193 [Gating] SW calibration Done
6522 09:26:24.769293 ==
6523 09:26:24.772507 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 09:26:24.775818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 09:26:24.775903 ==
6526 09:26:24.775970 RX Vref Scan: 0
6527 09:26:24.776030
6528 09:26:24.779200 RX Vref 0 -> 0, step: 1
6529 09:26:24.779284
6530 09:26:24.782538 RX Delay -410 -> 252, step: 16
6531 09:26:24.785754 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6532 09:26:24.792305 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6533 09:26:24.796145 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6534 09:26:24.799299 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6535 09:26:24.802468 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6536 09:26:24.805719 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6537 09:26:24.812670 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6538 09:26:24.815754 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6539 09:26:24.819522 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6540 09:26:24.822706 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6541 09:26:24.829147 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6542 09:26:24.832380 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6543 09:26:24.836152 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6544 09:26:24.842708 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6545 09:26:24.845854 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6546 09:26:24.849146 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6547 09:26:24.849230 ==
6548 09:26:24.852840 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 09:26:24.856153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 09:26:24.856238 ==
6551 09:26:24.859325 DQS Delay:
6552 09:26:24.859425 DQS0 = 27, DQS1 = 43
6553 09:26:24.862369 DQM Delay:
6554 09:26:24.862479 DQM0 = 9, DQM1 = 13
6555 09:26:24.862646 DQ Delay:
6556 09:26:24.866054 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6557 09:26:24.869379 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6558 09:26:24.872518 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6559 09:26:24.875702 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6560 09:26:24.875786
6561 09:26:24.875851
6562 09:26:24.875911 ==
6563 09:26:24.879075 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 09:26:24.882784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 09:26:24.886033 ==
6566 09:26:24.886134
6567 09:26:24.886231
6568 09:26:24.886308 TX Vref Scan disable
6569 09:26:24.889270 == TX Byte 0 ==
6570 09:26:24.892434 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6571 09:26:24.895703 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6572 09:26:24.899023 == TX Byte 1 ==
6573 09:26:24.902735 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6574 09:26:24.905920 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6575 09:26:24.906004 ==
6576 09:26:24.909169 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 09:26:24.915737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 09:26:24.915822 ==
6579 09:26:24.915887
6580 09:26:24.915947
6581 09:26:24.916005 TX Vref Scan disable
6582 09:26:24.919049 == TX Byte 0 ==
6583 09:26:24.922701 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6584 09:26:24.925941 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6585 09:26:24.929249 == TX Byte 1 ==
6586 09:26:24.932401 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6587 09:26:24.936174 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6588 09:26:24.936258
6589 09:26:24.939348 [DATLAT]
6590 09:26:24.939431 Freq=400, CH0 RK1
6591 09:26:24.939498
6592 09:26:24.942631 DATLAT Default: 0xe
6593 09:26:24.942730 0, 0xFFFF, sum = 0
6594 09:26:24.945914 1, 0xFFFF, sum = 0
6595 09:26:24.945998 2, 0xFFFF, sum = 0
6596 09:26:24.949095 3, 0xFFFF, sum = 0
6597 09:26:24.949179 4, 0xFFFF, sum = 0
6598 09:26:24.952783 5, 0xFFFF, sum = 0
6599 09:26:24.952868 6, 0xFFFF, sum = 0
6600 09:26:24.955973 7, 0xFFFF, sum = 0
6601 09:26:24.956057 8, 0xFFFF, sum = 0
6602 09:26:24.959283 9, 0xFFFF, sum = 0
6603 09:26:24.959368 10, 0xFFFF, sum = 0
6604 09:26:24.962483 11, 0xFFFF, sum = 0
6605 09:26:24.962568 12, 0xFFFF, sum = 0
6606 09:26:24.966229 13, 0x0, sum = 1
6607 09:26:24.966329 14, 0x0, sum = 2
6608 09:26:24.969267 15, 0x0, sum = 3
6609 09:26:24.969352 16, 0x0, sum = 4
6610 09:26:24.972436 best_step = 14
6611 09:26:24.972519
6612 09:26:24.972630 ==
6613 09:26:24.976198 Dram Type= 6, Freq= 0, CH_0, rank 1
6614 09:26:24.979292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 09:26:24.979380 ==
6616 09:26:24.982688 RX Vref Scan: 0
6617 09:26:24.982770
6618 09:26:24.982836 RX Vref 0 -> 0, step: 1
6619 09:26:24.982924
6620 09:26:24.985911 RX Delay -327 -> 252, step: 8
6621 09:26:24.993455 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6622 09:26:24.996777 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6623 09:26:24.999932 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6624 09:26:25.006812 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6625 09:26:25.010146 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6626 09:26:25.013347 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6627 09:26:25.016716 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6628 09:26:25.019928 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6629 09:26:25.026944 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6630 09:26:25.030202 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6631 09:26:25.033401 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6632 09:26:25.036714 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6633 09:26:25.043334 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6634 09:26:25.047150 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6635 09:26:25.050288 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6636 09:26:25.056738 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6637 09:26:25.056868 ==
6638 09:26:25.060075 Dram Type= 6, Freq= 0, CH_0, rank 1
6639 09:26:25.063680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 09:26:25.063798 ==
6641 09:26:25.063867 DQS Delay:
6642 09:26:25.066978 DQS0 = 28, DQS1 = 44
6643 09:26:25.067065 DQM Delay:
6644 09:26:25.070313 DQM0 = 9, DQM1 = 14
6645 09:26:25.070398 DQ Delay:
6646 09:26:25.073536 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6647 09:26:25.076725 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6648 09:26:25.080141 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6649 09:26:25.083444 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6650 09:26:25.083589
6651 09:26:25.083660
6652 09:26:25.090097 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6653 09:26:25.093329 CH0 RK1: MR19=C0C, MR18=BF71
6654 09:26:25.099868 CH0_RK1: MR19=0xC0C, MR18=0xBF71, DQSOSC=386, MR23=63, INC=396, DEC=264
6655 09:26:25.103674 [RxdqsGatingPostProcess] freq 400
6656 09:26:25.106889 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6657 09:26:25.110162 best DQS0 dly(2T, 0.5T) = (0, 10)
6658 09:26:25.113366 best DQS1 dly(2T, 0.5T) = (0, 10)
6659 09:26:25.116544 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6660 09:26:25.119915 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6661 09:26:25.123259 best DQS0 dly(2T, 0.5T) = (0, 10)
6662 09:26:25.126435 best DQS1 dly(2T, 0.5T) = (0, 10)
6663 09:26:25.130289 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6664 09:26:25.133566 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6665 09:26:25.136931 Pre-setting of DQS Precalculation
6666 09:26:25.140192 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6667 09:26:25.143568 ==
6668 09:26:25.143673 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 09:26:25.150039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 09:26:25.150122 ==
6671 09:26:25.153400 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6672 09:26:25.159998 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6673 09:26:25.163282 [CA 0] Center 36 (8~64) winsize 57
6674 09:26:25.166431 [CA 1] Center 36 (8~64) winsize 57
6675 09:26:25.170162 [CA 2] Center 36 (8~64) winsize 57
6676 09:26:25.173209 [CA 3] Center 36 (8~64) winsize 57
6677 09:26:25.176559 [CA 4] Center 36 (8~64) winsize 57
6678 09:26:25.180194 [CA 5] Center 36 (8~64) winsize 57
6679 09:26:25.180295
6680 09:26:25.183265 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6681 09:26:25.183365
6682 09:26:25.186901 [CATrainingPosCal] consider 1 rank data
6683 09:26:25.190148 u2DelayCellTimex100 = 270/100 ps
6684 09:26:25.193433 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 09:26:25.196723 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 09:26:25.199925 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 09:26:25.203345 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 09:26:25.206392 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 09:26:25.210159 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 09:26:25.213372
6691 09:26:25.216643 CA PerBit enable=1, Macro0, CA PI delay=36
6692 09:26:25.216743
6693 09:26:25.219874 [CBTSetCACLKResult] CA Dly = 36
6694 09:26:25.219984 CS Dly: 1 (0~32)
6695 09:26:25.220084 ==
6696 09:26:25.223210 Dram Type= 6, Freq= 0, CH_1, rank 1
6697 09:26:25.226432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 09:26:25.226536 ==
6699 09:26:25.233063 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6700 09:26:25.240099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6701 09:26:25.243436 [CA 0] Center 36 (8~64) winsize 57
6702 09:26:25.246673 [CA 1] Center 36 (8~64) winsize 57
6703 09:26:25.249846 [CA 2] Center 36 (8~64) winsize 57
6704 09:26:25.253233 [CA 3] Center 36 (8~64) winsize 57
6705 09:26:25.256426 [CA 4] Center 36 (8~64) winsize 57
6706 09:26:25.256540 [CA 5] Center 36 (8~64) winsize 57
6707 09:26:25.259746
6708 09:26:25.262928 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6709 09:26:25.263014
6710 09:26:25.266653 [CATrainingPosCal] consider 2 rank data
6711 09:26:25.269881 u2DelayCellTimex100 = 270/100 ps
6712 09:26:25.272956 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 09:26:25.276691 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 09:26:25.279806 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 09:26:25.283066 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 09:26:25.286231 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 09:26:25.289914 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 09:26:25.289995
6719 09:26:25.293180 CA PerBit enable=1, Macro0, CA PI delay=36
6720 09:26:25.293280
6721 09:26:25.296481 [CBTSetCACLKResult] CA Dly = 36
6722 09:26:25.299939 CS Dly: 1 (0~32)
6723 09:26:25.300038
6724 09:26:25.303201 ----->DramcWriteLeveling(PI) begin...
6725 09:26:25.303277 ==
6726 09:26:25.306507 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 09:26:25.309763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 09:26:25.309837 ==
6729 09:26:25.312911 Write leveling (Byte 0): 40 => 8
6730 09:26:25.316157 Write leveling (Byte 1): 32 => 0
6731 09:26:25.319428 DramcWriteLeveling(PI) end<-----
6732 09:26:25.319529
6733 09:26:25.319593 ==
6734 09:26:25.323265 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 09:26:25.326416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 09:26:25.326501 ==
6737 09:26:25.329548 [Gating] SW mode calibration
6738 09:26:25.336057 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6739 09:26:25.342726 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6740 09:26:25.345917 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6741 09:26:25.349731 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6742 09:26:25.356241 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 09:26:25.359407 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 09:26:25.362726 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6745 09:26:25.369636 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 09:26:25.372671 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 09:26:25.375786 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 09:26:25.382594 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6749 09:26:25.385853 Total UI for P1: 0, mck2ui 16
6750 09:26:25.389184 best dqsien dly found for B0: ( 0, 14, 24)
6751 09:26:25.392763 Total UI for P1: 0, mck2ui 16
6752 09:26:25.395878 best dqsien dly found for B1: ( 0, 14, 24)
6753 09:26:25.399098 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6754 09:26:25.402349 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6755 09:26:25.402433
6756 09:26:25.406098 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6757 09:26:25.409300 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6758 09:26:25.412517 [Gating] SW calibration Done
6759 09:26:25.412620 ==
6760 09:26:25.415782 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 09:26:25.419012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 09:26:25.419096 ==
6763 09:26:25.422661 RX Vref Scan: 0
6764 09:26:25.422747
6765 09:26:25.422827 RX Vref 0 -> 0, step: 1
6766 09:26:25.425850
6767 09:26:25.425933 RX Delay -410 -> 252, step: 16
6768 09:26:25.432821 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6769 09:26:25.435948 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6770 09:26:25.439208 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6771 09:26:25.442899 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6772 09:26:25.449535 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6773 09:26:25.452880 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6774 09:26:25.456278 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6775 09:26:25.459457 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6776 09:26:25.466024 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6777 09:26:25.469281 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6778 09:26:25.472413 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6779 09:26:25.475956 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6780 09:26:25.482613 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6781 09:26:25.485750 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6782 09:26:25.489436 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6783 09:26:25.492630 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6784 09:26:25.495864 ==
6785 09:26:25.495966 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 09:26:25.502974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 09:26:25.503053 ==
6788 09:26:25.503117 DQS Delay:
6789 09:26:25.506168 DQS0 = 27, DQS1 = 43
6790 09:26:25.506243 DQM Delay:
6791 09:26:25.509415 DQM0 = 7, DQM1 = 17
6792 09:26:25.509489 DQ Delay:
6793 09:26:25.512828 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6794 09:26:25.516017 DQ4 =8, DQ5 =8, DQ6 =16, DQ7 =0
6795 09:26:25.516116 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6796 09:26:25.522362 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6797 09:26:25.522468
6798 09:26:25.522560
6799 09:26:25.522648 ==
6800 09:26:25.526076 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 09:26:25.529277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 09:26:25.529366 ==
6803 09:26:25.529441
6804 09:26:25.529504
6805 09:26:25.532503 TX Vref Scan disable
6806 09:26:25.532658 == TX Byte 0 ==
6807 09:26:25.535862 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6808 09:26:25.542361 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6809 09:26:25.542444 == TX Byte 1 ==
6810 09:26:25.545627 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6811 09:26:25.552312 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6812 09:26:25.552414 ==
6813 09:26:25.555651 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 09:26:25.559501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 09:26:25.559587 ==
6816 09:26:25.559654
6817 09:26:25.559715
6818 09:26:25.562631 TX Vref Scan disable
6819 09:26:25.562714 == TX Byte 0 ==
6820 09:26:25.569216 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6821 09:26:25.572412 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6822 09:26:25.572522 == TX Byte 1 ==
6823 09:26:25.578824 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6824 09:26:25.582131 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6825 09:26:25.582215
6826 09:26:25.582281 [DATLAT]
6827 09:26:25.585561 Freq=400, CH1 RK0
6828 09:26:25.585645
6829 09:26:25.585710 DATLAT Default: 0xf
6830 09:26:25.588793 0, 0xFFFF, sum = 0
6831 09:26:25.588878 1, 0xFFFF, sum = 0
6832 09:26:25.592455 2, 0xFFFF, sum = 0
6833 09:26:25.592542 3, 0xFFFF, sum = 0
6834 09:26:25.595652 4, 0xFFFF, sum = 0
6835 09:26:25.595762 5, 0xFFFF, sum = 0
6836 09:26:25.598932 6, 0xFFFF, sum = 0
6837 09:26:25.599048 7, 0xFFFF, sum = 0
6838 09:26:25.602238 8, 0xFFFF, sum = 0
6839 09:26:25.602323 9, 0xFFFF, sum = 0
6840 09:26:25.605553 10, 0xFFFF, sum = 0
6841 09:26:25.605638 11, 0xFFFF, sum = 0
6842 09:26:25.608866 12, 0xFFFF, sum = 0
6843 09:26:25.612450 13, 0x0, sum = 1
6844 09:26:25.612599 14, 0x0, sum = 2
6845 09:26:25.612697 15, 0x0, sum = 3
6846 09:26:25.615783 16, 0x0, sum = 4
6847 09:26:25.615873 best_step = 14
6848 09:26:25.615939
6849 09:26:25.616000 ==
6850 09:26:25.619004 Dram Type= 6, Freq= 0, CH_1, rank 0
6851 09:26:25.625444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 09:26:25.625530 ==
6853 09:26:25.625597 RX Vref Scan: 1
6854 09:26:25.625659
6855 09:26:25.629194 RX Vref 0 -> 0, step: 1
6856 09:26:25.629277
6857 09:26:25.632342 RX Delay -327 -> 252, step: 8
6858 09:26:25.632425
6859 09:26:25.635666 Set Vref, RX VrefLevel [Byte0]: 51
6860 09:26:25.639081 [Byte1]: 53
6861 09:26:25.639166
6862 09:26:25.642316 Final RX Vref Byte 0 = 51 to rank0
6863 09:26:25.645563 Final RX Vref Byte 1 = 53 to rank0
6864 09:26:25.649274 Final RX Vref Byte 0 = 51 to rank1
6865 09:26:25.652527 Final RX Vref Byte 1 = 53 to rank1==
6866 09:26:25.655804 Dram Type= 6, Freq= 0, CH_1, rank 0
6867 09:26:25.659067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 09:26:25.662325 ==
6869 09:26:25.662411 DQS Delay:
6870 09:26:25.662479 DQS0 = 32, DQS1 = 40
6871 09:26:25.665571 DQM Delay:
6872 09:26:25.665656 DQM0 = 10, DQM1 = 13
6873 09:26:25.668899 DQ Delay:
6874 09:26:25.668985 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6875 09:26:25.672217 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6876 09:26:25.675502 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6877 09:26:25.678757 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6878 09:26:25.678843
6879 09:26:25.678911
6880 09:26:25.688753 [DQSOSCAuto] RK0, (LSB)MR18= 0xa3dd, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 389 ps
6881 09:26:25.692421 CH1 RK0: MR19=C0C, MR18=A3DD
6882 09:26:25.698769 CH1_RK0: MR19=0xC0C, MR18=0xA3DD, DQSOSC=382, MR23=63, INC=404, DEC=269
6883 09:26:25.698855 ==
6884 09:26:25.702115 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 09:26:25.705246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 09:26:25.705332 ==
6887 09:26:25.708510 [Gating] SW mode calibration
6888 09:26:25.715480 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6889 09:26:25.718638 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6890 09:26:25.725194 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6891 09:26:25.728486 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6892 09:26:25.731660 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 09:26:25.738649 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 09:26:25.741880 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6895 09:26:25.745198 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 09:26:25.751649 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 09:26:25.754854 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 09:26:25.758188 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6899 09:26:25.761920 Total UI for P1: 0, mck2ui 16
6900 09:26:25.765155 best dqsien dly found for B0: ( 0, 14, 24)
6901 09:26:25.768394 Total UI for P1: 0, mck2ui 16
6902 09:26:25.771738 best dqsien dly found for B1: ( 0, 14, 24)
6903 09:26:25.775063 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6904 09:26:25.778347 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6905 09:26:25.778433
6906 09:26:25.785372 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6907 09:26:25.788519 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6908 09:26:25.791907 [Gating] SW calibration Done
6909 09:26:25.791990 ==
6910 09:26:25.795119 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 09:26:25.798695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 09:26:25.798779 ==
6913 09:26:25.798846 RX Vref Scan: 0
6914 09:26:25.798908
6915 09:26:25.801882 RX Vref 0 -> 0, step: 1
6916 09:26:25.801965
6917 09:26:25.805136 RX Delay -410 -> 252, step: 16
6918 09:26:25.808224 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6919 09:26:25.811771 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6920 09:26:25.818745 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6921 09:26:25.821941 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6922 09:26:25.825128 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6923 09:26:25.828250 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6924 09:26:25.835249 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6925 09:26:25.838362 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6926 09:26:25.841696 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6927 09:26:25.845392 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6928 09:26:25.851898 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6929 09:26:25.855157 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6930 09:26:25.858469 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6931 09:26:25.861717 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6932 09:26:25.868781 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6933 09:26:25.872085 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6934 09:26:25.872192 ==
6935 09:26:25.875360 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 09:26:25.878125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 09:26:25.878195 ==
6938 09:26:25.881884 DQS Delay:
6939 09:26:25.881964 DQS0 = 35, DQS1 = 43
6940 09:26:25.885151 DQM Delay:
6941 09:26:25.885235 DQM0 = 16, DQM1 = 18
6942 09:26:25.885305 DQ Delay:
6943 09:26:25.888469 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6944 09:26:25.891680 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6945 09:26:25.894984 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6946 09:26:25.898243 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6947 09:26:25.898317
6948 09:26:25.898387
6949 09:26:25.901849 ==
6950 09:26:25.901933 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 09:26:25.908327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 09:26:25.908406 ==
6953 09:26:25.908471
6954 09:26:25.908531
6955 09:26:25.911694 TX Vref Scan disable
6956 09:26:25.911786 == TX Byte 0 ==
6957 09:26:25.914728 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6958 09:26:25.918508 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6959 09:26:25.921726 == TX Byte 1 ==
6960 09:26:25.924879 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6961 09:26:25.928076 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6962 09:26:25.928153 ==
6963 09:26:25.931766 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 09:26:25.938195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 09:26:25.938287 ==
6966 09:26:25.938352
6967 09:26:25.938411
6968 09:26:25.941401 TX Vref Scan disable
6969 09:26:25.941469 == TX Byte 0 ==
6970 09:26:25.944667 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6971 09:26:25.948408 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6972 09:26:25.951732 == TX Byte 1 ==
6973 09:26:25.955040 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6974 09:26:25.958296 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6975 09:26:25.958399
6976 09:26:25.961695 [DATLAT]
6977 09:26:25.961764 Freq=400, CH1 RK1
6978 09:26:25.961826
6979 09:26:25.964908 DATLAT Default: 0xe
6980 09:26:25.964982 0, 0xFFFF, sum = 0
6981 09:26:25.968068 1, 0xFFFF, sum = 0
6982 09:26:25.968145 2, 0xFFFF, sum = 0
6983 09:26:25.971344 3, 0xFFFF, sum = 0
6984 09:26:25.971424 4, 0xFFFF, sum = 0
6985 09:26:25.974571 5, 0xFFFF, sum = 0
6986 09:26:25.974647 6, 0xFFFF, sum = 0
6987 09:26:25.978390 7, 0xFFFF, sum = 0
6988 09:26:25.978481 8, 0xFFFF, sum = 0
6989 09:26:25.981691 9, 0xFFFF, sum = 0
6990 09:26:25.984458 10, 0xFFFF, sum = 0
6991 09:26:25.984534 11, 0xFFFF, sum = 0
6992 09:26:25.988225 12, 0xFFFF, sum = 0
6993 09:26:25.988297 13, 0x0, sum = 1
6994 09:26:25.991501 14, 0x0, sum = 2
6995 09:26:25.991583 15, 0x0, sum = 3
6996 09:26:25.994687 16, 0x0, sum = 4
6997 09:26:25.994773 best_step = 14
6998 09:26:25.994840
6999 09:26:25.994902 ==
7000 09:26:25.998081 Dram Type= 6, Freq= 0, CH_1, rank 1
7001 09:26:26.001256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7002 09:26:26.001340 ==
7003 09:26:26.004425 RX Vref Scan: 0
7004 09:26:26.004557
7005 09:26:26.008039 RX Vref 0 -> 0, step: 1
7006 09:26:26.008137
7007 09:26:26.008203 RX Delay -327 -> 252, step: 8
7008 09:26:26.016688 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
7009 09:26:26.020266 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
7010 09:26:26.023331 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7011 09:26:26.026556 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
7012 09:26:26.033332 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7013 09:26:26.036425 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
7014 09:26:26.039683 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
7015 09:26:26.043423 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7016 09:26:26.049828 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7017 09:26:26.053174 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7018 09:26:26.056291 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7019 09:26:26.060030 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7020 09:26:26.066499 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7021 09:26:26.069628 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7022 09:26:26.073010 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7023 09:26:26.079704 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7024 09:26:26.079788 ==
7025 09:26:26.083030 Dram Type= 6, Freq= 0, CH_1, rank 1
7026 09:26:26.086236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7027 09:26:26.086351 ==
7028 09:26:26.086418 DQS Delay:
7029 09:26:26.089512 DQS0 = 32, DQS1 = 36
7030 09:26:26.089598 DQM Delay:
7031 09:26:26.093234 DQM0 = 12, DQM1 = 11
7032 09:26:26.093318 DQ Delay:
7033 09:26:26.096499 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7034 09:26:26.099721 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
7035 09:26:26.103008 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7036 09:26:26.106275 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7037 09:26:26.106359
7038 09:26:26.106425
7039 09:26:26.112689 [DQSOSCAuto] RK1, (LSB)MR18= 0xb059, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
7040 09:26:26.116026 CH1 RK1: MR19=C0C, MR18=B059
7041 09:26:26.122910 CH1_RK1: MR19=0xC0C, MR18=0xB059, DQSOSC=387, MR23=63, INC=394, DEC=262
7042 09:26:26.126075 [RxdqsGatingPostProcess] freq 400
7043 09:26:26.132955 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7044 09:26:26.133049 best DQS0 dly(2T, 0.5T) = (0, 10)
7045 09:26:26.136186 best DQS1 dly(2T, 0.5T) = (0, 10)
7046 09:26:26.139334 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7047 09:26:26.142623 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7048 09:26:26.145901 best DQS0 dly(2T, 0.5T) = (0, 10)
7049 09:26:26.149134 best DQS1 dly(2T, 0.5T) = (0, 10)
7050 09:26:26.152830 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7051 09:26:26.156100 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7052 09:26:26.159462 Pre-setting of DQS Precalculation
7053 09:26:26.165906 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7054 09:26:26.172292 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7055 09:26:26.178894 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7056 09:26:26.178997
7057 09:26:26.179089
7058 09:26:26.182226 [Calibration Summary] 800 Mbps
7059 09:26:26.182338 CH 0, Rank 0
7060 09:26:26.185458 SW Impedance : PASS
7061 09:26:26.188688 DUTY Scan : NO K
7062 09:26:26.188830 ZQ Calibration : PASS
7063 09:26:26.192450 Jitter Meter : NO K
7064 09:26:26.192560 CBT Training : PASS
7065 09:26:26.195663 Write leveling : PASS
7066 09:26:26.198908 RX DQS gating : PASS
7067 09:26:26.199011 RX DQ/DQS(RDDQC) : PASS
7068 09:26:26.202208 TX DQ/DQS : PASS
7069 09:26:26.205453 RX DATLAT : PASS
7070 09:26:26.205528 RX DQ/DQS(Engine): PASS
7071 09:26:26.209227 TX OE : NO K
7072 09:26:26.209303 All Pass.
7073 09:26:26.209366
7074 09:26:26.212373 CH 0, Rank 1
7075 09:26:26.212471 SW Impedance : PASS
7076 09:26:26.215607 DUTY Scan : NO K
7077 09:26:26.218934 ZQ Calibration : PASS
7078 09:26:26.219033 Jitter Meter : NO K
7079 09:26:26.222318 CBT Training : PASS
7080 09:26:26.225486 Write leveling : NO K
7081 09:26:26.225587 RX DQS gating : PASS
7082 09:26:26.229158 RX DQ/DQS(RDDQC) : PASS
7083 09:26:26.232791 TX DQ/DQS : PASS
7084 09:26:26.232866 RX DATLAT : PASS
7085 09:26:26.235814 RX DQ/DQS(Engine): PASS
7086 09:26:26.235886 TX OE : NO K
7087 09:26:26.239096 All Pass.
7088 09:26:26.239210
7089 09:26:26.239310 CH 1, Rank 0
7090 09:26:26.242390 SW Impedance : PASS
7091 09:26:26.242477 DUTY Scan : NO K
7092 09:26:26.245611 ZQ Calibration : PASS
7093 09:26:26.248811 Jitter Meter : NO K
7094 09:26:26.248928 CBT Training : PASS
7095 09:26:26.252026 Write leveling : PASS
7096 09:26:26.255803 RX DQS gating : PASS
7097 09:26:26.255888 RX DQ/DQS(RDDQC) : PASS
7098 09:26:26.259093 TX DQ/DQS : PASS
7099 09:26:26.262340 RX DATLAT : PASS
7100 09:26:26.262454 RX DQ/DQS(Engine): PASS
7101 09:26:26.265557 TX OE : NO K
7102 09:26:26.265641 All Pass.
7103 09:26:26.265708
7104 09:26:26.268845 CH 1, Rank 1
7105 09:26:26.268929 SW Impedance : PASS
7106 09:26:26.272156 DUTY Scan : NO K
7107 09:26:26.275294 ZQ Calibration : PASS
7108 09:26:26.275378 Jitter Meter : NO K
7109 09:26:26.279230 CBT Training : PASS
7110 09:26:26.281880 Write leveling : NO K
7111 09:26:26.281964 RX DQS gating : PASS
7112 09:26:26.285361 RX DQ/DQS(RDDQC) : PASS
7113 09:26:26.288591 TX DQ/DQS : PASS
7114 09:26:26.288690 RX DATLAT : PASS
7115 09:26:26.292206 RX DQ/DQS(Engine): PASS
7116 09:26:26.292307 TX OE : NO K
7117 09:26:26.295449 All Pass.
7118 09:26:26.295533
7119 09:26:26.295599 DramC Write-DBI off
7120 09:26:26.298647 PER_BANK_REFRESH: Hybrid Mode
7121 09:26:26.301863 TX_TRACKING: ON
7122 09:26:26.308794 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7123 09:26:26.312097 [FAST_K] Save calibration result to emmc
7124 09:26:26.318573 dramc_set_vcore_voltage set vcore to 725000
7125 09:26:26.318677 Read voltage for 1600, 0
7126 09:26:26.318770 Vio18 = 0
7127 09:26:26.321775 Vcore = 725000
7128 09:26:26.321869 Vdram = 0
7129 09:26:26.321936 Vddq = 0
7130 09:26:26.325595 Vmddr = 0
7131 09:26:26.328672 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7132 09:26:26.335042 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7133 09:26:26.335153 MEM_TYPE=3, freq_sel=13
7134 09:26:26.338617 sv_algorithm_assistance_LP4_3733
7135 09:26:26.345404 ============ PULL DRAM RESETB DOWN ============
7136 09:26:26.348487 ========== PULL DRAM RESETB DOWN end =========
7137 09:26:26.351681 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7138 09:26:26.354916 ===================================
7139 09:26:26.358236 LPDDR4 DRAM CONFIGURATION
7140 09:26:26.361366 ===================================
7141 09:26:26.365122 EX_ROW_EN[0] = 0x0
7142 09:26:26.365204 EX_ROW_EN[1] = 0x0
7143 09:26:26.368433 LP4Y_EN = 0x0
7144 09:26:26.368538 WORK_FSP = 0x1
7145 09:26:26.371613 WL = 0x5
7146 09:26:26.371714 RL = 0x5
7147 09:26:26.374871 BL = 0x2
7148 09:26:26.374968 RPST = 0x0
7149 09:26:26.378185 RD_PRE = 0x0
7150 09:26:26.378269 WR_PRE = 0x1
7151 09:26:26.381431 WR_PST = 0x1
7152 09:26:26.381515 DBI_WR = 0x0
7153 09:26:26.384700 DBI_RD = 0x0
7154 09:26:26.384785 OTF = 0x1
7155 09:26:26.388072 ===================================
7156 09:26:26.391342 ===================================
7157 09:26:26.395100 ANA top config
7158 09:26:26.398323 ===================================
7159 09:26:26.401723 DLL_ASYNC_EN = 0
7160 09:26:26.401816 ALL_SLAVE_EN = 0
7161 09:26:26.404885 NEW_RANK_MODE = 1
7162 09:26:26.408131 DLL_IDLE_MODE = 1
7163 09:26:26.411881 LP45_APHY_COMB_EN = 1
7164 09:26:26.411965 TX_ODT_DIS = 0
7165 09:26:26.415136 NEW_8X_MODE = 1
7166 09:26:26.418357 ===================================
7167 09:26:26.421677 ===================================
7168 09:26:26.424745 data_rate = 3200
7169 09:26:26.428094 CKR = 1
7170 09:26:26.431775 DQ_P2S_RATIO = 8
7171 09:26:26.435121 ===================================
7172 09:26:26.438210 CA_P2S_RATIO = 8
7173 09:26:26.438291 DQ_CA_OPEN = 0
7174 09:26:26.441847 DQ_SEMI_OPEN = 0
7175 09:26:26.444832 CA_SEMI_OPEN = 0
7176 09:26:26.448041 CA_FULL_RATE = 0
7177 09:26:26.451799 DQ_CKDIV4_EN = 0
7178 09:26:26.454882 CA_CKDIV4_EN = 0
7179 09:26:26.454964 CA_PREDIV_EN = 0
7180 09:26:26.458136 PH8_DLY = 12
7181 09:26:26.461824 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7182 09:26:26.465005 DQ_AAMCK_DIV = 4
7183 09:26:26.468235 CA_AAMCK_DIV = 4
7184 09:26:26.471464 CA_ADMCK_DIV = 4
7185 09:26:26.471548 DQ_TRACK_CA_EN = 0
7186 09:26:26.475122 CA_PICK = 1600
7187 09:26:26.478388 CA_MCKIO = 1600
7188 09:26:26.481502 MCKIO_SEMI = 0
7189 09:26:26.484716 PLL_FREQ = 3068
7190 09:26:26.488046 DQ_UI_PI_RATIO = 32
7191 09:26:26.491373 CA_UI_PI_RATIO = 0
7192 09:26:26.494677 ===================================
7193 09:26:26.498386 ===================================
7194 09:26:26.498496 memory_type:LPDDR4
7195 09:26:26.501611 GP_NUM : 10
7196 09:26:26.504800 SRAM_EN : 1
7197 09:26:26.504907 MD32_EN : 0
7198 09:26:26.508149 ===================================
7199 09:26:26.511403 [ANA_INIT] >>>>>>>>>>>>>>
7200 09:26:26.514707 <<<<<< [CONFIGURE PHASE]: ANA_TX
7201 09:26:26.518483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7202 09:26:26.521708 ===================================
7203 09:26:26.524943 data_rate = 3200,PCW = 0X7600
7204 09:26:26.528136 ===================================
7205 09:26:26.531727 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7206 09:26:26.534865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7207 09:26:26.541319 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7208 09:26:26.544983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7209 09:26:26.548105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7210 09:26:26.551645 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7211 09:26:26.554684 [ANA_INIT] flow start
7212 09:26:26.558510 [ANA_INIT] PLL >>>>>>>>
7213 09:26:26.558615 [ANA_INIT] PLL <<<<<<<<
7214 09:26:26.561667 [ANA_INIT] MIDPI >>>>>>>>
7215 09:26:26.564868 [ANA_INIT] MIDPI <<<<<<<<
7216 09:26:26.564970 [ANA_INIT] DLL >>>>>>>>
7217 09:26:26.568119 [ANA_INIT] DLL <<<<<<<<
7218 09:26:26.571394 [ANA_INIT] flow end
7219 09:26:26.574707 ============ LP4 DIFF to SE enter ============
7220 09:26:26.578003 ============ LP4 DIFF to SE exit ============
7221 09:26:26.581756 [ANA_INIT] <<<<<<<<<<<<<
7222 09:26:26.585086 [Flow] Enable top DCM control >>>>>
7223 09:26:26.588233 [Flow] Enable top DCM control <<<<<
7224 09:26:26.591537 Enable DLL master slave shuffle
7225 09:26:26.594765 ==============================================================
7226 09:26:26.598008 Gating Mode config
7227 09:26:26.601727 ==============================================================
7228 09:26:26.605074 Config description:
7229 09:26:26.614756 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7230 09:26:26.621741 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7231 09:26:26.625053 SELPH_MODE 0: By rank 1: By Phase
7232 09:26:26.631619 ==============================================================
7233 09:26:26.634781 GAT_TRACK_EN = 1
7234 09:26:26.637949 RX_GATING_MODE = 2
7235 09:26:26.641659 RX_GATING_TRACK_MODE = 2
7236 09:26:26.644914 SELPH_MODE = 1
7237 09:26:26.648091 PICG_EARLY_EN = 1
7238 09:26:26.648178 VALID_LAT_VALUE = 1
7239 09:26:26.654810 ==============================================================
7240 09:26:26.658306 Enter into Gating configuration >>>>
7241 09:26:26.661553 Exit from Gating configuration <<<<
7242 09:26:26.664821 Enter into DVFS_PRE_config >>>>>
7243 09:26:26.674431 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7244 09:26:26.677873 Exit from DVFS_PRE_config <<<<<
7245 09:26:26.681113 Enter into PICG configuration >>>>
7246 09:26:26.684846 Exit from PICG configuration <<<<
7247 09:26:26.688260 [RX_INPUT] configuration >>>>>
7248 09:26:26.691501 [RX_INPUT] configuration <<<<<
7249 09:26:26.698126 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7250 09:26:26.701357 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7251 09:26:26.707799 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7252 09:26:26.714663 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7253 09:26:26.721064 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7254 09:26:26.727556 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7255 09:26:26.730966 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7256 09:26:26.734172 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7257 09:26:26.737966 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7258 09:26:26.744241 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7259 09:26:26.747533 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7260 09:26:26.751259 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7261 09:26:26.754183 ===================================
7262 09:26:26.757738 LPDDR4 DRAM CONFIGURATION
7263 09:26:26.761216 ===================================
7264 09:26:26.761301 EX_ROW_EN[0] = 0x0
7265 09:26:26.764252 EX_ROW_EN[1] = 0x0
7266 09:26:26.764336 LP4Y_EN = 0x0
7267 09:26:26.767941 WORK_FSP = 0x1
7268 09:26:26.768024 WL = 0x5
7269 09:26:26.771240 RL = 0x5
7270 09:26:26.774127 BL = 0x2
7271 09:26:26.774211 RPST = 0x0
7272 09:26:26.777408 RD_PRE = 0x0
7273 09:26:26.777493 WR_PRE = 0x1
7274 09:26:26.780729 WR_PST = 0x1
7275 09:26:26.780814 DBI_WR = 0x0
7276 09:26:26.784496 DBI_RD = 0x0
7277 09:26:26.784602 OTF = 0x1
7278 09:26:26.787871 ===================================
7279 09:26:26.790722 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7280 09:26:26.797811 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7281 09:26:26.800584 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7282 09:26:26.804272 ===================================
7283 09:26:26.807494 LPDDR4 DRAM CONFIGURATION
7284 09:26:26.811209 ===================================
7285 09:26:26.811312 EX_ROW_EN[0] = 0x10
7286 09:26:26.814466 EX_ROW_EN[1] = 0x0
7287 09:26:26.814541 LP4Y_EN = 0x0
7288 09:26:26.817687 WORK_FSP = 0x1
7289 09:26:26.817764 WL = 0x5
7290 09:26:26.820926 RL = 0x5
7291 09:26:26.821027 BL = 0x2
7292 09:26:26.824315 RPST = 0x0
7293 09:26:26.824426 RD_PRE = 0x0
7294 09:26:26.827570 WR_PRE = 0x1
7295 09:26:26.827671 WR_PST = 0x1
7296 09:26:26.830873 DBI_WR = 0x0
7297 09:26:26.834129 DBI_RD = 0x0
7298 09:26:26.834237 OTF = 0x1
7299 09:26:26.837287 ===================================
7300 09:26:26.844035 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7301 09:26:26.844141 ==
7302 09:26:26.847560 Dram Type= 6, Freq= 0, CH_0, rank 0
7303 09:26:26.850743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7304 09:26:26.850837 ==
7305 09:26:26.854058 [Duty_Offset_Calibration]
7306 09:26:26.854147 B0:2 B1:0 CA:1
7307 09:26:26.854213
7308 09:26:26.857658 [DutyScan_Calibration_Flow] k_type=0
7309 09:26:26.867738
7310 09:26:26.867821 ==CLK 0==
7311 09:26:26.871365 Final CLK duty delay cell = -4
7312 09:26:26.874562 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7313 09:26:26.877814 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7314 09:26:26.881593 [-4] AVG Duty = 4906%(X100)
7315 09:26:26.881686
7316 09:26:26.884791 CH0 CLK Duty spec in!! Max-Min= 187%
7317 09:26:26.888110 [DutyScan_Calibration_Flow] ====Done====
7318 09:26:26.888185
7319 09:26:26.891422 [DutyScan_Calibration_Flow] k_type=1
7320 09:26:26.907142
7321 09:26:26.907225 ==DQS 0 ==
7322 09:26:26.910350 Final DQS duty delay cell = 0
7323 09:26:26.913703 [0] MAX Duty = 5218%(X100), DQS PI = 30
7324 09:26:26.916956 [0] MIN Duty = 4938%(X100), DQS PI = 62
7325 09:26:26.920338 [0] AVG Duty = 5078%(X100)
7326 09:26:26.920440
7327 09:26:26.920508 ==DQS 1 ==
7328 09:26:26.924027 Final DQS duty delay cell = -4
7329 09:26:26.927231 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7330 09:26:26.930574 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7331 09:26:26.933811 [-4] AVG Duty = 4969%(X100)
7332 09:26:26.933890
7333 09:26:26.937080 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7334 09:26:26.937157
7335 09:26:26.940335 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7336 09:26:26.944088 [DutyScan_Calibration_Flow] ====Done====
7337 09:26:26.944173
7338 09:26:26.947374 [DutyScan_Calibration_Flow] k_type=3
7339 09:26:26.964705
7340 09:26:26.964786 ==DQM 0 ==
7341 09:26:26.968121 Final DQM duty delay cell = 0
7342 09:26:26.971639 [0] MAX Duty = 5124%(X100), DQS PI = 26
7343 09:26:26.974604 [0] MIN Duty = 4813%(X100), DQS PI = 52
7344 09:26:26.978219 [0] AVG Duty = 4968%(X100)
7345 09:26:26.978300
7346 09:26:26.978368 ==DQM 1 ==
7347 09:26:26.981182 Final DQM duty delay cell = 0
7348 09:26:26.984583 [0] MAX Duty = 5249%(X100), DQS PI = 30
7349 09:26:26.988339 [0] MIN Duty = 5000%(X100), DQS PI = 20
7350 09:26:26.991595 [0] AVG Duty = 5124%(X100)
7351 09:26:26.991678
7352 09:26:26.994861 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7353 09:26:26.994939
7354 09:26:26.998293 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7355 09:26:27.001560 [DutyScan_Calibration_Flow] ====Done====
7356 09:26:27.001675
7357 09:26:27.004816 [DutyScan_Calibration_Flow] k_type=2
7358 09:26:27.022191
7359 09:26:27.022310 ==DQ 0 ==
7360 09:26:27.025349 Final DQ duty delay cell = 0
7361 09:26:27.028575 [0] MAX Duty = 5124%(X100), DQS PI = 34
7362 09:26:27.031796 [0] MIN Duty = 4969%(X100), DQS PI = 16
7363 09:26:27.031883 [0] AVG Duty = 5046%(X100)
7364 09:26:27.035141
7365 09:26:27.035221 ==DQ 1 ==
7366 09:26:27.038999 Final DQ duty delay cell = 0
7367 09:26:27.042297 [0] MAX Duty = 4938%(X100), DQS PI = 24
7368 09:26:27.045542 [0] MIN Duty = 4875%(X100), DQS PI = 10
7369 09:26:27.045626 [0] AVG Duty = 4906%(X100)
7370 09:26:27.045694
7371 09:26:27.048758 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7372 09:26:27.048861
7373 09:26:27.051894 CH0 DQ 1 Duty spec in!! Max-Min= 63%
7374 09:26:27.058834 [DutyScan_Calibration_Flow] ====Done====
7375 09:26:27.058957 ==
7376 09:26:27.062023 Dram Type= 6, Freq= 0, CH_1, rank 0
7377 09:26:27.065270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7378 09:26:27.065364 ==
7379 09:26:27.068829 [Duty_Offset_Calibration]
7380 09:26:27.068907 B0:0 B1:-1 CA:2
7381 09:26:27.068975
7382 09:26:27.071790 [DutyScan_Calibration_Flow] k_type=0
7383 09:26:27.082116
7384 09:26:27.082200 ==CLK 0==
7385 09:26:27.085715 Final CLK duty delay cell = 0
7386 09:26:27.088949 [0] MAX Duty = 5156%(X100), DQS PI = 10
7387 09:26:27.092120 [0] MIN Duty = 4938%(X100), DQS PI = 44
7388 09:26:27.092202 [0] AVG Duty = 5047%(X100)
7389 09:26:27.095416
7390 09:26:27.098673 CH1 CLK Duty spec in!! Max-Min= 218%
7391 09:26:27.102401 [DutyScan_Calibration_Flow] ====Done====
7392 09:26:27.102483
7393 09:26:27.105689 [DutyScan_Calibration_Flow] k_type=1
7394 09:26:27.122233
7395 09:26:27.122312 ==DQS 0 ==
7396 09:26:27.125486 Final DQS duty delay cell = 0
7397 09:26:27.128682 [0] MAX Duty = 5124%(X100), DQS PI = 26
7398 09:26:27.131945 [0] MIN Duty = 4969%(X100), DQS PI = 2
7399 09:26:27.132015 [0] AVG Duty = 5046%(X100)
7400 09:26:27.135274
7401 09:26:27.135342 ==DQS 1 ==
7402 09:26:27.138584 Final DQS duty delay cell = 0
7403 09:26:27.141770 [0] MAX Duty = 5187%(X100), DQS PI = 0
7404 09:26:27.145567 [0] MIN Duty = 4844%(X100), DQS PI = 34
7405 09:26:27.145642 [0] AVG Duty = 5015%(X100)
7406 09:26:27.148733
7407 09:26:27.151889 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7408 09:26:27.151989
7409 09:26:27.155218 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7410 09:26:27.158524 [DutyScan_Calibration_Flow] ====Done====
7411 09:26:27.158607
7412 09:26:27.161728 [DutyScan_Calibration_Flow] k_type=3
7413 09:26:27.179360
7414 09:26:27.179443 ==DQM 0 ==
7415 09:26:27.182876 Final DQM duty delay cell = 4
7416 09:26:27.186026 [4] MAX Duty = 5125%(X100), DQS PI = 24
7417 09:26:27.189553 [4] MIN Duty = 4969%(X100), DQS PI = 32
7418 09:26:27.189630 [4] AVG Duty = 5047%(X100)
7419 09:26:27.192857
7420 09:26:27.192939 ==DQM 1 ==
7421 09:26:27.196226 Final DQM duty delay cell = 0
7422 09:26:27.199500 [0] MAX Duty = 5281%(X100), DQS PI = 58
7423 09:26:27.202830 [0] MIN Duty = 4876%(X100), DQS PI = 34
7424 09:26:27.202912 [0] AVG Duty = 5078%(X100)
7425 09:26:27.206166
7426 09:26:27.209419 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7427 09:26:27.209498
7428 09:26:27.212652 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7429 09:26:27.216224 [DutyScan_Calibration_Flow] ====Done====
7430 09:26:27.216330
7431 09:26:27.219521 [DutyScan_Calibration_Flow] k_type=2
7432 09:26:27.236282
7433 09:26:27.236393 ==DQ 0 ==
7434 09:26:27.239682 Final DQ duty delay cell = 0
7435 09:26:27.242952 [0] MAX Duty = 5062%(X100), DQS PI = 20
7436 09:26:27.246216 [0] MIN Duty = 4969%(X100), DQS PI = 2
7437 09:26:27.246299 [0] AVG Duty = 5015%(X100)
7438 09:26:27.250111
7439 09:26:27.250193 ==DQ 1 ==
7440 09:26:27.253151 Final DQ duty delay cell = 0
7441 09:26:27.256396 [0] MAX Duty = 5062%(X100), DQS PI = 2
7442 09:26:27.259654 [0] MIN Duty = 4813%(X100), DQS PI = 34
7443 09:26:27.259735 [0] AVG Duty = 4937%(X100)
7444 09:26:27.259800
7445 09:26:27.262871 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7446 09:26:27.266552
7447 09:26:27.269796 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7448 09:26:27.272962 [DutyScan_Calibration_Flow] ====Done====
7449 09:26:27.276742 nWR fixed to 30
7450 09:26:27.276830 [ModeRegInit_LP4] CH0 RK0
7451 09:26:27.279870 [ModeRegInit_LP4] CH0 RK1
7452 09:26:27.283353 [ModeRegInit_LP4] CH1 RK0
7453 09:26:27.283430 [ModeRegInit_LP4] CH1 RK1
7454 09:26:27.286560 match AC timing 5
7455 09:26:27.289603 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7456 09:26:27.293343 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7457 09:26:27.299762 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7458 09:26:27.302997 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7459 09:26:27.309560 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7460 09:26:27.309637 [MiockJmeterHQA]
7461 09:26:27.309706
7462 09:26:27.312922 [DramcMiockJmeter] u1RxGatingPI = 0
7463 09:26:27.316154 0 : 4368, 4140
7464 09:26:27.316238 4 : 4252, 4027
7465 09:26:27.316304 8 : 4252, 4027
7466 09:26:27.319418 12 : 4363, 4137
7467 09:26:27.319496 16 : 4255, 4029
7468 09:26:27.323246 20 : 4363, 4137
7469 09:26:27.323328 24 : 4252, 4027
7470 09:26:27.326545 28 : 4253, 4027
7471 09:26:27.326630 32 : 4253, 4027
7472 09:26:27.326696 36 : 4253, 4026
7473 09:26:27.329705 40 : 4363, 4138
7474 09:26:27.329797 44 : 4366, 4139
7475 09:26:27.332912 48 : 4365, 4140
7476 09:26:27.332997 52 : 4252, 4027
7477 09:26:27.336153 56 : 4255, 4029
7478 09:26:27.336228 60 : 4253, 4029
7479 09:26:27.339412 64 : 4363, 4138
7480 09:26:27.339488 68 : 4360, 4138
7481 09:26:27.339594 72 : 4363, 4140
7482 09:26:27.342656 76 : 4252, 4029
7483 09:26:27.342733 80 : 4253, 4029
7484 09:26:27.346374 84 : 4250, 4027
7485 09:26:27.346480 88 : 4252, 3647
7486 09:26:27.349700 92 : 4360, 0
7487 09:26:27.349783 96 : 4253, 0
7488 09:26:27.349852 100 : 4363, 0
7489 09:26:27.353169 104 : 4361, 0
7490 09:26:27.353260 108 : 4360, 0
7491 09:26:27.353328 112 : 4250, 0
7492 09:26:27.356343 116 : 4250, 0
7493 09:26:27.356453 120 : 4249, 0
7494 09:26:27.359616 124 : 4250, 0
7495 09:26:27.359692 128 : 4250, 0
7496 09:26:27.359756 132 : 4249, 0
7497 09:26:27.362772 136 : 4250, 0
7498 09:26:27.362853 140 : 4253, 0
7499 09:26:27.365999 144 : 4249, 0
7500 09:26:27.366076 148 : 4250, 0
7501 09:26:27.366140 152 : 4255, 0
7502 09:26:27.369504 156 : 4360, 0
7503 09:26:27.369580 160 : 4250, 0
7504 09:26:27.372645 164 : 4361, 0
7505 09:26:27.372721 168 : 4250, 0
7506 09:26:27.372785 172 : 4249, 0
7507 09:26:27.375899 176 : 4250, 0
7508 09:26:27.375980 180 : 4250, 0
7509 09:26:27.379242 184 : 4254, 0
7510 09:26:27.379371 188 : 4250, 0
7511 09:26:27.379481 192 : 4253, 0
7512 09:26:27.382414 196 : 4250, 0
7513 09:26:27.382505 200 : 4250, 1
7514 09:26:27.386039 204 : 4255, 2424
7515 09:26:27.386123 208 : 4253, 4029
7516 09:26:27.386192 212 : 4250, 4027
7517 09:26:27.389335 216 : 4363, 4140
7518 09:26:27.389415 220 : 4250, 4027
7519 09:26:27.392425 224 : 4253, 4029
7520 09:26:27.392504 228 : 4363, 4140
7521 09:26:27.396057 232 : 4361, 4138
7522 09:26:27.396138 236 : 4248, 4024
7523 09:26:27.399117 240 : 4250, 4027
7524 09:26:27.399233 244 : 4253, 4029
7525 09:26:27.402525 248 : 4250, 4027
7526 09:26:27.402651 252 : 4250, 4027
7527 09:26:27.405890 256 : 4363, 4140
7528 09:26:27.406008 260 : 4253, 4029
7529 09:26:27.409339 264 : 4250, 4027
7530 09:26:27.409439 268 : 4363, 4140
7531 09:26:27.409532 272 : 4250, 4027
7532 09:26:27.412711 276 : 4253, 4029
7533 09:26:27.412798 280 : 4360, 4138
7534 09:26:27.415867 284 : 4361, 4138
7535 09:26:27.415939 288 : 4250, 4027
7536 09:26:27.419149 292 : 4250, 4027
7537 09:26:27.419224 296 : 4253, 4029
7538 09:26:27.422414 300 : 4250, 4027
7539 09:26:27.422518 304 : 4250, 4027
7540 09:26:27.425688 308 : 4363, 4140
7541 09:26:27.425771 312 : 4253, 3943
7542 09:26:27.429072 316 : 4250, 1854
7543 09:26:27.429153
7544 09:26:27.429218 MIOCK jitter meter ch=0
7545 09:26:27.429280
7546 09:26:27.432071 1T = (316-92) = 224 dly cells
7547 09:26:27.439118 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7548 09:26:27.439203 ==
7549 09:26:27.442386 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 09:26:27.445637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 09:26:27.445717 ==
7552 09:26:27.452237 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7553 09:26:27.455573 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7554 09:26:27.458790 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7555 09:26:27.465564 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7556 09:26:27.475189 [CA 0] Center 42 (12~73) winsize 62
7557 09:26:27.478715 [CA 1] Center 42 (12~72) winsize 61
7558 09:26:27.481898 [CA 2] Center 37 (7~67) winsize 61
7559 09:26:27.485150 [CA 3] Center 37 (7~67) winsize 61
7560 09:26:27.488433 [CA 4] Center 36 (6~66) winsize 61
7561 09:26:27.491954 [CA 5] Center 35 (5~65) winsize 61
7562 09:26:27.492031
7563 09:26:27.495067 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7564 09:26:27.495147
7565 09:26:27.498593 [CATrainingPosCal] consider 1 rank data
7566 09:26:27.501613 u2DelayCellTimex100 = 290/100 ps
7567 09:26:27.505193 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7568 09:26:27.511926 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7569 09:26:27.515183 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7570 09:26:27.518391 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7571 09:26:27.521663 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7572 09:26:27.525380 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7573 09:26:27.525469
7574 09:26:27.528486 CA PerBit enable=1, Macro0, CA PI delay=35
7575 09:26:27.528594
7576 09:26:27.531775 [CBTSetCACLKResult] CA Dly = 35
7577 09:26:27.534969 CS Dly: 9 (0~40)
7578 09:26:27.538164 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7579 09:26:27.541916 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7580 09:26:27.541997 ==
7581 09:26:27.545140 Dram Type= 6, Freq= 0, CH_0, rank 1
7582 09:26:27.548373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 09:26:27.548476 ==
7584 09:26:27.554907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7585 09:26:27.558192 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7586 09:26:27.564644 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7587 09:26:27.568122 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7588 09:26:27.578326 [CA 0] Center 43 (13~74) winsize 62
7589 09:26:27.581901 [CA 1] Center 43 (13~73) winsize 61
7590 09:26:27.584973 [CA 2] Center 38 (9~68) winsize 60
7591 09:26:27.588242 [CA 3] Center 38 (9~68) winsize 60
7592 09:26:27.592103 [CA 4] Center 37 (7~67) winsize 61
7593 09:26:27.595349 [CA 5] Center 36 (6~66) winsize 61
7594 09:26:27.595425
7595 09:26:27.598636 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7596 09:26:27.598709
7597 09:26:27.601750 [CATrainingPosCal] consider 2 rank data
7598 09:26:27.605205 u2DelayCellTimex100 = 290/100 ps
7599 09:26:27.608426 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7600 09:26:27.615063 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7601 09:26:27.618243 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7602 09:26:27.621892 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7603 09:26:27.625200 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7604 09:26:27.628420 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7605 09:26:27.628542
7606 09:26:27.631719 CA PerBit enable=1, Macro0, CA PI delay=35
7607 09:26:27.631808
7608 09:26:27.634984 [CBTSetCACLKResult] CA Dly = 35
7609 09:26:27.638324 CS Dly: 10 (0~43)
7610 09:26:27.641526 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7611 09:26:27.644784 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7612 09:26:27.644857
7613 09:26:27.648121 ----->DramcWriteLeveling(PI) begin...
7614 09:26:27.648192 ==
7615 09:26:27.651876 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 09:26:27.655103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 09:26:27.658417 ==
7618 09:26:27.658489 Write leveling (Byte 0): 36 => 36
7619 09:26:27.661626 Write leveling (Byte 1): 33 => 33
7620 09:26:27.664919 DramcWriteLeveling(PI) end<-----
7621 09:26:27.665002
7622 09:26:27.665069 ==
7623 09:26:27.668189 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 09:26:27.674760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 09:26:27.674848 ==
7626 09:26:27.678552 [Gating] SW mode calibration
7627 09:26:27.685202 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7628 09:26:27.688325 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7629 09:26:27.695265 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 09:26:27.698399 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 09:26:27.701703 1 4 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7632 09:26:27.704851 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7633 09:26:27.711612 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7634 09:26:27.714796 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7635 09:26:27.718493 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 09:26:27.724993 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 09:26:27.728241 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 09:26:27.731495 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 09:26:27.738087 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
7640 09:26:27.741317 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7641 09:26:27.744662 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7642 09:26:27.751236 1 5 20 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
7643 09:26:27.754592 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 09:26:27.758376 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 09:26:27.764714 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 09:26:27.768121 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 09:26:27.771356 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7648 09:26:27.778054 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7649 09:26:27.781330 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
7650 09:26:27.784510 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7651 09:26:27.791548 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 09:26:27.794726 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 09:26:27.798378 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 09:26:27.804973 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 09:26:27.808201 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 09:26:27.811335 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7657 09:26:27.814977 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7658 09:26:27.821754 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7659 09:26:27.824996 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 09:26:27.828205 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 09:26:27.834805 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 09:26:27.838051 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 09:26:27.841759 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 09:26:27.848162 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 09:26:27.851452 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 09:26:27.854732 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 09:26:27.861800 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 09:26:27.864948 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 09:26:27.868197 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 09:26:27.874824 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 09:26:27.878078 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7672 09:26:27.881266 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7673 09:26:27.888288 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7674 09:26:27.888367 Total UI for P1: 0, mck2ui 16
7675 09:26:27.894790 best dqsien dly found for B0: ( 1, 9, 10)
7676 09:26:27.897920 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7677 09:26:27.901517 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 09:26:27.904737 Total UI for P1: 0, mck2ui 16
7679 09:26:27.908405 best dqsien dly found for B1: ( 1, 9, 18)
7680 09:26:27.911593 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7681 09:26:27.914789 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7682 09:26:27.914862
7683 09:26:27.917987 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7684 09:26:27.924848 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7685 09:26:27.924935 [Gating] SW calibration Done
7686 09:26:27.925002 ==
7687 09:26:27.928111 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 09:26:27.934614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 09:26:27.934698 ==
7690 09:26:27.934765 RX Vref Scan: 0
7691 09:26:27.934826
7692 09:26:27.938324 RX Vref 0 -> 0, step: 1
7693 09:26:27.938408
7694 09:26:27.941627 RX Delay 0 -> 252, step: 8
7695 09:26:27.944839 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7696 09:26:27.948058 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7697 09:26:27.951327 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7698 09:26:27.954626 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7699 09:26:27.961144 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7700 09:26:27.964892 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7701 09:26:27.968139 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7702 09:26:27.971430 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7703 09:26:27.974793 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7704 09:26:27.981248 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7705 09:26:27.984992 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7706 09:26:27.987716 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7707 09:26:27.991548 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7708 09:26:27.994765 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7709 09:26:28.001054 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7710 09:26:28.004704 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7711 09:26:28.004788 ==
7712 09:26:28.007778 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 09:26:28.011544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 09:26:28.011629 ==
7715 09:26:28.014483 DQS Delay:
7716 09:26:28.014566 DQS0 = 0, DQS1 = 0
7717 09:26:28.014632 DQM Delay:
7718 09:26:28.018208 DQM0 = 138, DQM1 = 127
7719 09:26:28.018291 DQ Delay:
7720 09:26:28.021505 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7721 09:26:28.024507 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7722 09:26:28.028162 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7723 09:26:28.034647 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7724 09:26:28.034732
7725 09:26:28.034799
7726 09:26:28.034859 ==
7727 09:26:28.037887 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 09:26:28.041229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 09:26:28.041313 ==
7730 09:26:28.041379
7731 09:26:28.041439
7732 09:26:28.044937 TX Vref Scan disable
7733 09:26:28.045020 == TX Byte 0 ==
7734 09:26:28.051467 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7735 09:26:28.054767 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7736 09:26:28.054851 == TX Byte 1 ==
7737 09:26:28.061375 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7738 09:26:28.064513 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7739 09:26:28.064626 ==
7740 09:26:28.067774 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 09:26:28.070905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 09:26:28.070990 ==
7743 09:26:28.085058
7744 09:26:28.088412 TX Vref early break, caculate TX vref
7745 09:26:28.091662 TX Vref=16, minBit 7, minWin=22, winSum=378
7746 09:26:28.095032 TX Vref=18, minBit 6, minWin=23, winSum=389
7747 09:26:28.098311 TX Vref=20, minBit 0, minWin=24, winSum=397
7748 09:26:28.101480 TX Vref=22, minBit 0, minWin=24, winSum=411
7749 09:26:28.104690 TX Vref=24, minBit 4, minWin=25, winSum=416
7750 09:26:28.111456 TX Vref=26, minBit 0, minWin=25, winSum=421
7751 09:26:28.114607 TX Vref=28, minBit 1, minWin=26, winSum=428
7752 09:26:28.118303 TX Vref=30, minBit 0, minWin=26, winSum=421
7753 09:26:28.121363 TX Vref=32, minBit 7, minWin=24, winSum=410
7754 09:26:28.124715 TX Vref=34, minBit 2, minWin=24, winSum=400
7755 09:26:28.131586 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
7756 09:26:28.131688
7757 09:26:28.134658 Final TX Range 0 Vref 28
7758 09:26:28.134766
7759 09:26:28.134856 ==
7760 09:26:28.137886 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 09:26:28.141144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 09:26:28.141245 ==
7763 09:26:28.141345
7764 09:26:28.141435
7765 09:26:28.144449 TX Vref Scan disable
7766 09:26:28.151309 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7767 09:26:28.151412 == TX Byte 0 ==
7768 09:26:28.154481 u2DelayCellOfst[0]=10 cells (3 PI)
7769 09:26:28.158311 u2DelayCellOfst[1]=16 cells (5 PI)
7770 09:26:28.161121 u2DelayCellOfst[2]=10 cells (3 PI)
7771 09:26:28.164822 u2DelayCellOfst[3]=10 cells (3 PI)
7772 09:26:28.168081 u2DelayCellOfst[4]=6 cells (2 PI)
7773 09:26:28.171420 u2DelayCellOfst[5]=0 cells (0 PI)
7774 09:26:28.174667 u2DelayCellOfst[6]=16 cells (5 PI)
7775 09:26:28.174740 u2DelayCellOfst[7]=13 cells (4 PI)
7776 09:26:28.181189 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7777 09:26:28.184340 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7778 09:26:28.184449 == TX Byte 1 ==
7779 09:26:28.188118 u2DelayCellOfst[8]=3 cells (1 PI)
7780 09:26:28.191354 u2DelayCellOfst[9]=0 cells (0 PI)
7781 09:26:28.194532 u2DelayCellOfst[10]=6 cells (2 PI)
7782 09:26:28.197754 u2DelayCellOfst[11]=3 cells (1 PI)
7783 09:26:28.201453 u2DelayCellOfst[12]=13 cells (4 PI)
7784 09:26:28.204872 u2DelayCellOfst[13]=10 cells (3 PI)
7785 09:26:28.208167 u2DelayCellOfst[14]=13 cells (4 PI)
7786 09:26:28.211313 u2DelayCellOfst[15]=10 cells (3 PI)
7787 09:26:28.214801 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7788 09:26:28.221243 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7789 09:26:28.221353 DramC Write-DBI on
7790 09:26:28.221444 ==
7791 09:26:28.224777 Dram Type= 6, Freq= 0, CH_0, rank 0
7792 09:26:28.228075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7793 09:26:28.228174 ==
7794 09:26:28.231204
7795 09:26:28.231303
7796 09:26:28.231392 TX Vref Scan disable
7797 09:26:28.234354 == TX Byte 0 ==
7798 09:26:28.237950 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7799 09:26:28.241217 == TX Byte 1 ==
7800 09:26:28.244433 Update DQM dly =730 (2 ,6, 26) DQM OEN =(3 ,3)
7801 09:26:28.244529 DramC Write-DBI off
7802 09:26:28.244615
7803 09:26:28.247712 [DATLAT]
7804 09:26:28.247782 Freq=1600, CH0 RK0
7805 09:26:28.247842
7806 09:26:28.251437 DATLAT Default: 0xf
7807 09:26:28.251534 0, 0xFFFF, sum = 0
7808 09:26:28.254624 1, 0xFFFF, sum = 0
7809 09:26:28.254726 2, 0xFFFF, sum = 0
7810 09:26:28.257941 3, 0xFFFF, sum = 0
7811 09:26:28.258043 4, 0xFFFF, sum = 0
7812 09:26:28.261218 5, 0xFFFF, sum = 0
7813 09:26:28.261293 6, 0xFFFF, sum = 0
7814 09:26:28.264495 7, 0xFFFF, sum = 0
7815 09:26:28.267700 8, 0xFFFF, sum = 0
7816 09:26:28.267799 9, 0xFFFF, sum = 0
7817 09:26:28.270953 10, 0xFFFF, sum = 0
7818 09:26:28.271051 11, 0xFFFF, sum = 0
7819 09:26:28.274267 12, 0xFFFF, sum = 0
7820 09:26:28.274365 13, 0xFFFF, sum = 0
7821 09:26:28.277494 14, 0x0, sum = 1
7822 09:26:28.277568 15, 0x0, sum = 2
7823 09:26:28.280759 16, 0x0, sum = 3
7824 09:26:28.280844 17, 0x0, sum = 4
7825 09:26:28.284034 best_step = 15
7826 09:26:28.284137
7827 09:26:28.284225 ==
7828 09:26:28.287682 Dram Type= 6, Freq= 0, CH_0, rank 0
7829 09:26:28.290825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7830 09:26:28.290931 ==
7831 09:26:28.291022 RX Vref Scan: 1
7832 09:26:28.291112
7833 09:26:28.294130 Set Vref Range= 24 -> 127
7834 09:26:28.294213
7835 09:26:28.297409 RX Vref 24 -> 127, step: 1
7836 09:26:28.297491
7837 09:26:28.300738 RX Delay 19 -> 252, step: 4
7838 09:26:28.300842
7839 09:26:28.303778 Set Vref, RX VrefLevel [Byte0]: 24
7840 09:26:28.307641 [Byte1]: 24
7841 09:26:28.307717
7842 09:26:28.310961 Set Vref, RX VrefLevel [Byte0]: 25
7843 09:26:28.314136 [Byte1]: 25
7844 09:26:28.314243
7845 09:26:28.317247 Set Vref, RX VrefLevel [Byte0]: 26
7846 09:26:28.320993 [Byte1]: 26
7847 09:26:28.324806
7848 09:26:28.324890 Set Vref, RX VrefLevel [Byte0]: 27
7849 09:26:28.327610 [Byte1]: 27
7850 09:26:28.331921
7851 09:26:28.332014 Set Vref, RX VrefLevel [Byte0]: 28
7852 09:26:28.335584 [Byte1]: 28
7853 09:26:28.339746
7854 09:26:28.339830 Set Vref, RX VrefLevel [Byte0]: 29
7855 09:26:28.342770 [Byte1]: 29
7856 09:26:28.347090
7857 09:26:28.347174 Set Vref, RX VrefLevel [Byte0]: 30
7858 09:26:28.350302 [Byte1]: 30
7859 09:26:28.355135
7860 09:26:28.355218 Set Vref, RX VrefLevel [Byte0]: 31
7861 09:26:28.358392 [Byte1]: 31
7862 09:26:28.362229
7863 09:26:28.362314 Set Vref, RX VrefLevel [Byte0]: 32
7864 09:26:28.365596 [Byte1]: 32
7865 09:26:28.369864
7866 09:26:28.369950 Set Vref, RX VrefLevel [Byte0]: 33
7867 09:26:28.372997 [Byte1]: 33
7868 09:26:28.377367
7869 09:26:28.377450 Set Vref, RX VrefLevel [Byte0]: 34
7870 09:26:28.380620 [Byte1]: 34
7871 09:26:28.384998
7872 09:26:28.385081 Set Vref, RX VrefLevel [Byte0]: 35
7873 09:26:28.388311 [Byte1]: 35
7874 09:26:28.392482
7875 09:26:28.392602 Set Vref, RX VrefLevel [Byte0]: 36
7876 09:26:28.396311 [Byte1]: 36
7877 09:26:28.400459
7878 09:26:28.400590 Set Vref, RX VrefLevel [Byte0]: 37
7879 09:26:28.403338 [Byte1]: 37
7880 09:26:28.407662
7881 09:26:28.407746 Set Vref, RX VrefLevel [Byte0]: 38
7882 09:26:28.410906 [Byte1]: 38
7883 09:26:28.415334
7884 09:26:28.415417 Set Vref, RX VrefLevel [Byte0]: 39
7885 09:26:28.418849 [Byte1]: 39
7886 09:26:28.422980
7887 09:26:28.423064 Set Vref, RX VrefLevel [Byte0]: 40
7888 09:26:28.426221 [Byte1]: 40
7889 09:26:28.430303
7890 09:26:28.430387 Set Vref, RX VrefLevel [Byte0]: 41
7891 09:26:28.433930 [Byte1]: 41
7892 09:26:28.438214
7893 09:26:28.438315 Set Vref, RX VrefLevel [Byte0]: 42
7894 09:26:28.441533 [Byte1]: 42
7895 09:26:28.445745
7896 09:26:28.445829 Set Vref, RX VrefLevel [Byte0]: 43
7897 09:26:28.448793 [Byte1]: 43
7898 09:26:28.453034
7899 09:26:28.453118 Set Vref, RX VrefLevel [Byte0]: 44
7900 09:26:28.456311 [Byte1]: 44
7901 09:26:28.460724
7902 09:26:28.460808 Set Vref, RX VrefLevel [Byte0]: 45
7903 09:26:28.464071 [Byte1]: 45
7904 09:26:28.468391
7905 09:26:28.468476 Set Vref, RX VrefLevel [Byte0]: 46
7906 09:26:28.471618 [Byte1]: 46
7907 09:26:28.475904
7908 09:26:28.475988 Set Vref, RX VrefLevel [Byte0]: 47
7909 09:26:28.479225 [Byte1]: 47
7910 09:26:28.483638
7911 09:26:28.483722 Set Vref, RX VrefLevel [Byte0]: 48
7912 09:26:28.486825 [Byte1]: 48
7913 09:26:28.491200
7914 09:26:28.491284 Set Vref, RX VrefLevel [Byte0]: 49
7915 09:26:28.494496 [Byte1]: 49
7916 09:26:28.498783
7917 09:26:28.498867 Set Vref, RX VrefLevel [Byte0]: 50
7918 09:26:28.502078 [Byte1]: 50
7919 09:26:28.506344
7920 09:26:28.506428 Set Vref, RX VrefLevel [Byte0]: 51
7921 09:26:28.509605 [Byte1]: 51
7922 09:26:28.514017
7923 09:26:28.514100 Set Vref, RX VrefLevel [Byte0]: 52
7924 09:26:28.517223 [Byte1]: 52
7925 09:26:28.521570
7926 09:26:28.521654 Set Vref, RX VrefLevel [Byte0]: 53
7927 09:26:28.524669 [Byte1]: 53
7928 09:26:28.528846
7929 09:26:28.528960 Set Vref, RX VrefLevel [Byte0]: 54
7930 09:26:28.531971 [Byte1]: 54
7931 09:26:28.536792
7932 09:26:28.536893 Set Vref, RX VrefLevel [Byte0]: 55
7933 09:26:28.539823 [Byte1]: 55
7934 09:26:28.544061
7935 09:26:28.544168 Set Vref, RX VrefLevel [Byte0]: 56
7936 09:26:28.547342 [Byte1]: 56
7937 09:26:28.551489
7938 09:26:28.551610 Set Vref, RX VrefLevel [Byte0]: 57
7939 09:26:28.555156 [Byte1]: 57
7940 09:26:28.559448
7941 09:26:28.559558 Set Vref, RX VrefLevel [Byte0]: 58
7942 09:26:28.562637 [Byte1]: 58
7943 09:26:28.567140
7944 09:26:28.567256 Set Vref, RX VrefLevel [Byte0]: 59
7945 09:26:28.570321 [Byte1]: 59
7946 09:26:28.574172
7947 09:26:28.574277 Set Vref, RX VrefLevel [Byte0]: 60
7948 09:26:28.577928 [Byte1]: 60
7949 09:26:28.581699
7950 09:26:28.581805 Set Vref, RX VrefLevel [Byte0]: 61
7951 09:26:28.585424 [Byte1]: 61
7952 09:26:28.589807
7953 09:26:28.589906 Set Vref, RX VrefLevel [Byte0]: 62
7954 09:26:28.592536 [Byte1]: 62
7955 09:26:28.596870
7956 09:26:28.596944 Set Vref, RX VrefLevel [Byte0]: 63
7957 09:26:28.600169 [Byte1]: 63
7958 09:26:28.604668
7959 09:26:28.604740 Set Vref, RX VrefLevel [Byte0]: 64
7960 09:26:28.607933 [Byte1]: 64
7961 09:26:28.612239
7962 09:26:28.612342 Set Vref, RX VrefLevel [Byte0]: 65
7963 09:26:28.615548 [Byte1]: 65
7964 09:26:28.619822
7965 09:26:28.619925 Set Vref, RX VrefLevel [Byte0]: 66
7966 09:26:28.623123 [Byte1]: 66
7967 09:26:28.627323
7968 09:26:28.627429 Set Vref, RX VrefLevel [Byte0]: 67
7969 09:26:28.630487 [Byte1]: 67
7970 09:26:28.635235
7971 09:26:28.635348 Set Vref, RX VrefLevel [Byte0]: 68
7972 09:26:28.638479 [Byte1]: 68
7973 09:26:28.642579
7974 09:26:28.642662 Set Vref, RX VrefLevel [Byte0]: 69
7975 09:26:28.645680 [Byte1]: 69
7976 09:26:28.650209
7977 09:26:28.650293 Set Vref, RX VrefLevel [Byte0]: 70
7978 09:26:28.653530 [Byte1]: 70
7979 09:26:28.657753
7980 09:26:28.657836 Set Vref, RX VrefLevel [Byte0]: 71
7981 09:26:28.664012 [Byte1]: 71
7982 09:26:28.664096
7983 09:26:28.667359 Set Vref, RX VrefLevel [Byte0]: 72
7984 09:26:28.670723 [Byte1]: 72
7985 09:26:28.670807
7986 09:26:28.673892 Set Vref, RX VrefLevel [Byte0]: 73
7987 09:26:28.677147 [Byte1]: 73
7988 09:26:28.677263
7989 09:26:28.680374 Set Vref, RX VrefLevel [Byte0]: 74
7990 09:26:28.684160 [Byte1]: 74
7991 09:26:28.687911
7992 09:26:28.688009 Set Vref, RX VrefLevel [Byte0]: 75
7993 09:26:28.691176 [Byte1]: 75
7994 09:26:28.695601
7995 09:26:28.695688 Set Vref, RX VrefLevel [Byte0]: 76
7996 09:26:28.698873 [Byte1]: 76
7997 09:26:28.703256
7998 09:26:28.703339 Set Vref, RX VrefLevel [Byte0]: 77
7999 09:26:28.706451 [Byte1]: 77
8000 09:26:28.710793
8001 09:26:28.710876 Set Vref, RX VrefLevel [Byte0]: 78
8002 09:26:28.713994 [Byte1]: 78
8003 09:26:28.718402
8004 09:26:28.718486 Set Vref, RX VrefLevel [Byte0]: 79
8005 09:26:28.721715 [Byte1]: 79
8006 09:26:28.726032
8007 09:26:28.726115 Final RX Vref Byte 0 = 60 to rank0
8008 09:26:28.729250 Final RX Vref Byte 1 = 63 to rank0
8009 09:26:28.732509 Final RX Vref Byte 0 = 60 to rank1
8010 09:26:28.735779 Final RX Vref Byte 1 = 63 to rank1==
8011 09:26:28.738946 Dram Type= 6, Freq= 0, CH_0, rank 0
8012 09:26:28.745498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8013 09:26:28.745591 ==
8014 09:26:28.745657 DQS Delay:
8015 09:26:28.745718 DQS0 = 0, DQS1 = 0
8016 09:26:28.749348 DQM Delay:
8017 09:26:28.749431 DQM0 = 136, DQM1 = 124
8018 09:26:28.752339 DQ Delay:
8019 09:26:28.756035 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
8020 09:26:28.759295 DQ4 =138, DQ5 =124, DQ6 =146, DQ7 =144
8021 09:26:28.762561 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8022 09:26:28.765702 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =134
8023 09:26:28.765785
8024 09:26:28.765852
8025 09:26:28.765911
8026 09:26:28.768980 [DramC_TX_OE_Calibration] TA2
8027 09:26:28.772259 Original DQ_B0 (3 6) =30, OEN = 27
8028 09:26:28.775941 Original DQ_B1 (3 6) =30, OEN = 27
8029 09:26:28.779284 24, 0x0, End_B0=24 End_B1=24
8030 09:26:28.779371 25, 0x0, End_B0=25 End_B1=25
8031 09:26:28.782483 26, 0x0, End_B0=26 End_B1=26
8032 09:26:28.785699 27, 0x0, End_B0=27 End_B1=27
8033 09:26:28.789019 28, 0x0, End_B0=28 End_B1=28
8034 09:26:28.789106 29, 0x0, End_B0=29 End_B1=29
8035 09:26:28.792284 30, 0x0, End_B0=30 End_B1=30
8036 09:26:28.795452 31, 0x4141, End_B0=30 End_B1=30
8037 09:26:28.799217 Byte0 end_step=30 best_step=27
8038 09:26:28.802464 Byte1 end_step=30 best_step=27
8039 09:26:28.805824 Byte0 TX OE(2T, 0.5T) = (3, 3)
8040 09:26:28.805910 Byte1 TX OE(2T, 0.5T) = (3, 3)
8041 09:26:28.809153
8042 09:26:28.809238
8043 09:26:28.815556 [DQSOSCAuto] RK0, (LSB)MR18= 0x201e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
8044 09:26:28.818779 CH0 RK0: MR19=303, MR18=201E
8045 09:26:28.825782 CH0_RK0: MR19=0x303, MR18=0x201E, DQSOSC=393, MR23=63, INC=23, DEC=15
8046 09:26:28.825869
8047 09:26:28.829045 ----->DramcWriteLeveling(PI) begin...
8048 09:26:28.829132 ==
8049 09:26:28.832319 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 09:26:28.835523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 09:26:28.835609 ==
8052 09:26:28.839351 Write leveling (Byte 0): 38 => 38
8053 09:26:28.842606 Write leveling (Byte 1): 31 => 31
8054 09:26:28.845645 DramcWriteLeveling(PI) end<-----
8055 09:26:28.845730
8056 09:26:28.845815 ==
8057 09:26:28.849335 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 09:26:28.852471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 09:26:28.852596 ==
8060 09:26:28.855513 [Gating] SW mode calibration
8061 09:26:28.862510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8062 09:26:28.868796 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8063 09:26:28.872139 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 09:26:28.875425 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 09:26:28.881918 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8066 09:26:28.885245 1 4 12 | B1->B0 | 2929 3434 | 1 0 | (1 1) (0 0)
8067 09:26:28.888978 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 09:26:28.895455 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 09:26:28.898684 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 09:26:28.901899 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 09:26:28.908827 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 09:26:28.912122 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8073 09:26:28.915351 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8074 09:26:28.921905 1 5 12 | B1->B0 | 3333 2525 | 1 0 | (1 0) (1 0)
8075 09:26:28.925285 1 5 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8076 09:26:28.928438 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 09:26:28.935389 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 09:26:28.938551 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 09:26:28.941777 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 09:26:28.948490 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 09:26:28.951662 1 6 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
8082 09:26:28.955262 1 6 12 | B1->B0 | 2d2d 4343 | 0 0 | (0 0) (0 0)
8083 09:26:28.961577 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 09:26:28.965040 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 09:26:28.968486 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 09:26:28.971784 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 09:26:28.978723 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 09:26:28.981963 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 09:26:28.985170 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8090 09:26:28.991761 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8091 09:26:28.995052 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8092 09:26:28.998818 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 09:26:29.005335 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 09:26:29.008533 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 09:26:29.012030 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 09:26:29.018551 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 09:26:29.021836 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 09:26:29.025144 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 09:26:29.031639 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 09:26:29.035402 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 09:26:29.038669 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 09:26:29.045048 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 09:26:29.048353 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 09:26:29.051958 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 09:26:29.058282 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 09:26:29.061886 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8107 09:26:29.065355 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8108 09:26:29.068413 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 09:26:29.071927 Total UI for P1: 0, mck2ui 16
8110 09:26:29.075054 best dqsien dly found for B0: ( 1, 9, 14)
8111 09:26:29.078648 Total UI for P1: 0, mck2ui 16
8112 09:26:29.081811 best dqsien dly found for B1: ( 1, 9, 14)
8113 09:26:29.085149 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8114 09:26:29.088391 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8115 09:26:29.091632
8116 09:26:29.095453 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8117 09:26:29.098780 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8118 09:26:29.102157 [Gating] SW calibration Done
8119 09:26:29.102249 ==
8120 09:26:29.105337 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 09:26:29.108583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 09:26:29.108667 ==
8123 09:26:29.108736 RX Vref Scan: 0
8124 09:26:29.111948
8125 09:26:29.112032 RX Vref 0 -> 0, step: 1
8126 09:26:29.112102
8127 09:26:29.115176 RX Delay 0 -> 252, step: 8
8128 09:26:29.118493 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8129 09:26:29.121735 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8130 09:26:29.128853 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8131 09:26:29.132031 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8132 09:26:29.135385 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8133 09:26:29.138589 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8134 09:26:29.141812 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8135 09:26:29.148727 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8136 09:26:29.151939 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8137 09:26:29.155186 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8138 09:26:29.158423 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8139 09:26:29.161642 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8140 09:26:29.168346 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8141 09:26:29.171912 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8142 09:26:29.175072 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8143 09:26:29.178136 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8144 09:26:29.178220 ==
8145 09:26:29.181365 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 09:26:29.188446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 09:26:29.188564 ==
8148 09:26:29.188648 DQS Delay:
8149 09:26:29.188756 DQS0 = 0, DQS1 = 0
8150 09:26:29.191716 DQM Delay:
8151 09:26:29.191799 DQM0 = 136, DQM1 = 125
8152 09:26:29.194891 DQ Delay:
8153 09:26:29.198244 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8154 09:26:29.202088 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8155 09:26:29.205352 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =123
8156 09:26:29.208541 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8157 09:26:29.208645
8158 09:26:29.208727
8159 09:26:29.208791 ==
8160 09:26:29.211825 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 09:26:29.215088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 09:26:29.215172 ==
8163 09:26:29.218410
8164 09:26:29.218493
8165 09:26:29.218558 TX Vref Scan disable
8166 09:26:29.221638 == TX Byte 0 ==
8167 09:26:29.224851 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8168 09:26:29.228320 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8169 09:26:29.231591 == TX Byte 1 ==
8170 09:26:29.235262 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8171 09:26:29.238472 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8172 09:26:29.238556 ==
8173 09:26:29.241728 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 09:26:29.248246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 09:26:29.248330 ==
8176 09:26:29.260711
8177 09:26:29.264007 TX Vref early break, caculate TX vref
8178 09:26:29.267219 TX Vref=16, minBit 0, minWin=23, winSum=384
8179 09:26:29.270805 TX Vref=18, minBit 8, minWin=23, winSum=396
8180 09:26:29.273836 TX Vref=20, minBit 0, minWin=24, winSum=408
8181 09:26:29.277162 TX Vref=22, minBit 0, minWin=25, winSum=412
8182 09:26:29.280712 TX Vref=24, minBit 8, minWin=25, winSum=425
8183 09:26:29.287367 TX Vref=26, minBit 1, minWin=26, winSum=429
8184 09:26:29.290635 TX Vref=28, minBit 0, minWin=26, winSum=433
8185 09:26:29.293867 TX Vref=30, minBit 0, minWin=26, winSum=424
8186 09:26:29.297607 TX Vref=32, minBit 0, minWin=26, winSum=421
8187 09:26:29.300935 TX Vref=34, minBit 0, minWin=25, winSum=409
8188 09:26:29.307376 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 28
8189 09:26:29.307480
8190 09:26:29.310425 Final TX Range 0 Vref 28
8191 09:26:29.310520
8192 09:26:29.310610 ==
8193 09:26:29.313673 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 09:26:29.317509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 09:26:29.317618 ==
8196 09:26:29.317709
8197 09:26:29.317796
8198 09:26:29.320793 TX Vref Scan disable
8199 09:26:29.327102 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8200 09:26:29.327207 == TX Byte 0 ==
8201 09:26:29.330365 u2DelayCellOfst[0]=13 cells (4 PI)
8202 09:26:29.333598 u2DelayCellOfst[1]=20 cells (6 PI)
8203 09:26:29.337302 u2DelayCellOfst[2]=13 cells (4 PI)
8204 09:26:29.340482 u2DelayCellOfst[3]=13 cells (4 PI)
8205 09:26:29.343716 u2DelayCellOfst[4]=10 cells (3 PI)
8206 09:26:29.347118 u2DelayCellOfst[5]=0 cells (0 PI)
8207 09:26:29.350351 u2DelayCellOfst[6]=20 cells (6 PI)
8208 09:26:29.350456 u2DelayCellOfst[7]=20 cells (6 PI)
8209 09:26:29.357351 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8210 09:26:29.360563 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8211 09:26:29.360677 == TX Byte 1 ==
8212 09:26:29.363900 u2DelayCellOfst[8]=3 cells (1 PI)
8213 09:26:29.367295 u2DelayCellOfst[9]=0 cells (0 PI)
8214 09:26:29.370429 u2DelayCellOfst[10]=6 cells (2 PI)
8215 09:26:29.373676 u2DelayCellOfst[11]=3 cells (1 PI)
8216 09:26:29.377218 u2DelayCellOfst[12]=13 cells (4 PI)
8217 09:26:29.380384 u2DelayCellOfst[13]=13 cells (4 PI)
8218 09:26:29.383918 u2DelayCellOfst[14]=13 cells (4 PI)
8219 09:26:29.387154 u2DelayCellOfst[15]=10 cells (3 PI)
8220 09:26:29.390231 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8221 09:26:29.397055 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8222 09:26:29.397140 DramC Write-DBI on
8223 09:26:29.397206 ==
8224 09:26:29.400311 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 09:26:29.403695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 09:26:29.403782 ==
8227 09:26:29.406861
8228 09:26:29.406943
8229 09:26:29.407008 TX Vref Scan disable
8230 09:26:29.410165 == TX Byte 0 ==
8231 09:26:29.413889 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8232 09:26:29.417178 == TX Byte 1 ==
8233 09:26:29.420334 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8234 09:26:29.423539 DramC Write-DBI off
8235 09:26:29.423622
8236 09:26:29.423687 [DATLAT]
8237 09:26:29.423747 Freq=1600, CH0 RK1
8238 09:26:29.423805
8239 09:26:29.426801 DATLAT Default: 0xf
8240 09:26:29.426883 0, 0xFFFF, sum = 0
8241 09:26:29.430043 1, 0xFFFF, sum = 0
8242 09:26:29.430127 2, 0xFFFF, sum = 0
8243 09:26:29.433798 3, 0xFFFF, sum = 0
8244 09:26:29.437148 4, 0xFFFF, sum = 0
8245 09:26:29.437232 5, 0xFFFF, sum = 0
8246 09:26:29.440320 6, 0xFFFF, sum = 0
8247 09:26:29.440404 7, 0xFFFF, sum = 0
8248 09:26:29.443585 8, 0xFFFF, sum = 0
8249 09:26:29.443669 9, 0xFFFF, sum = 0
8250 09:26:29.446901 10, 0xFFFF, sum = 0
8251 09:26:29.446985 11, 0xFFFF, sum = 0
8252 09:26:29.450113 12, 0xFFFF, sum = 0
8253 09:26:29.450197 13, 0xFFFF, sum = 0
8254 09:26:29.453919 14, 0x0, sum = 1
8255 09:26:29.454002 15, 0x0, sum = 2
8256 09:26:29.457252 16, 0x0, sum = 3
8257 09:26:29.457336 17, 0x0, sum = 4
8258 09:26:29.460464 best_step = 15
8259 09:26:29.460553
8260 09:26:29.460632 ==
8261 09:26:29.463689 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 09:26:29.466931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 09:26:29.467015 ==
8264 09:26:29.467080 RX Vref Scan: 0
8265 09:26:29.467140
8266 09:26:29.470175 RX Vref 0 -> 0, step: 1
8267 09:26:29.470258
8268 09:26:29.473826 RX Delay 19 -> 252, step: 4
8269 09:26:29.477085 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8270 09:26:29.483646 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8271 09:26:29.486817 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8272 09:26:29.489969 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8273 09:26:29.493762 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8274 09:26:29.496654 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8275 09:26:29.500209 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8276 09:26:29.506960 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8277 09:26:29.510256 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8278 09:26:29.513501 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8279 09:26:29.516711 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8280 09:26:29.519917 iDelay=191, Bit 11, Center 118 (71 ~ 166) 96
8281 09:26:29.526482 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8282 09:26:29.529689 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8283 09:26:29.532940 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8284 09:26:29.536271 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8285 09:26:29.539984 ==
8286 09:26:29.540089 Dram Type= 6, Freq= 0, CH_0, rank 1
8287 09:26:29.546347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 09:26:29.546453 ==
8289 09:26:29.546542 DQS Delay:
8290 09:26:29.549685 DQS0 = 0, DQS1 = 0
8291 09:26:29.549756 DQM Delay:
8292 09:26:29.553293 DQM0 = 133, DQM1 = 122
8293 09:26:29.553399 DQ Delay:
8294 09:26:29.556497 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8295 09:26:29.559731 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8296 09:26:29.562935 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =118
8297 09:26:29.566252 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8298 09:26:29.566324
8299 09:26:29.566400
8300 09:26:29.566457
8301 09:26:29.569512 [DramC_TX_OE_Calibration] TA2
8302 09:26:29.572821 Original DQ_B0 (3 6) =30, OEN = 27
8303 09:26:29.576476 Original DQ_B1 (3 6) =30, OEN = 27
8304 09:26:29.579665 24, 0x0, End_B0=24 End_B1=24
8305 09:26:29.582823 25, 0x0, End_B0=25 End_B1=25
8306 09:26:29.582922 26, 0x0, End_B0=26 End_B1=26
8307 09:26:29.586233 27, 0x0, End_B0=27 End_B1=27
8308 09:26:29.589298 28, 0x0, End_B0=28 End_B1=28
8309 09:26:29.593204 29, 0x0, End_B0=29 End_B1=29
8310 09:26:29.593313 30, 0x0, End_B0=30 End_B1=30
8311 09:26:29.596393 31, 0x4141, End_B0=30 End_B1=30
8312 09:26:29.599604 Byte0 end_step=30 best_step=27
8313 09:26:29.603122 Byte1 end_step=30 best_step=27
8314 09:26:29.606094 Byte0 TX OE(2T, 0.5T) = (3, 3)
8315 09:26:29.609731 Byte1 TX OE(2T, 0.5T) = (3, 3)
8316 09:26:29.609810
8317 09:26:29.609942
8318 09:26:29.616071 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8319 09:26:29.619244 CH0 RK1: MR19=303, MR18=210E
8320 09:26:29.626235 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8321 09:26:29.629560 [RxdqsGatingPostProcess] freq 1600
8322 09:26:29.632729 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8323 09:26:29.636164 best DQS0 dly(2T, 0.5T) = (1, 1)
8324 09:26:29.639396 best DQS1 dly(2T, 0.5T) = (1, 1)
8325 09:26:29.642614 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8326 09:26:29.646314 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8327 09:26:29.649489 best DQS0 dly(2T, 0.5T) = (1, 1)
8328 09:26:29.652827 best DQS1 dly(2T, 0.5T) = (1, 1)
8329 09:26:29.656163 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8330 09:26:29.659384 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8331 09:26:29.662556 Pre-setting of DQS Precalculation
8332 09:26:29.666271 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8333 09:26:29.666343 ==
8334 09:26:29.669537 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 09:26:29.672832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 09:26:29.676059 ==
8337 09:26:29.679270 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 09:26:29.683430 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 09:26:29.689592 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 09:26:29.696032 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 09:26:29.703031 [CA 0] Center 42 (13~72) winsize 60
8342 09:26:29.706205 [CA 1] Center 42 (12~72) winsize 61
8343 09:26:29.709794 [CA 2] Center 38 (9~68) winsize 60
8344 09:26:29.712894 [CA 3] Center 37 (8~67) winsize 60
8345 09:26:29.716103 [CA 4] Center 37 (8~67) winsize 60
8346 09:26:29.719850 [CA 5] Center 37 (7~67) winsize 61
8347 09:26:29.719966
8348 09:26:29.723169 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8349 09:26:29.723245
8350 09:26:29.726385 [CATrainingPosCal] consider 1 rank data
8351 09:26:29.729572 u2DelayCellTimex100 = 290/100 ps
8352 09:26:29.733291 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8353 09:26:29.739800 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8354 09:26:29.743030 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8355 09:26:29.746325 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8356 09:26:29.749488 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8357 09:26:29.752782 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8358 09:26:29.752862
8359 09:26:29.756531 CA PerBit enable=1, Macro0, CA PI delay=37
8360 09:26:29.756654
8361 09:26:29.760046 [CBTSetCACLKResult] CA Dly = 37
8362 09:26:29.760128 CS Dly: 9 (0~40)
8363 09:26:29.766303 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 09:26:29.769626 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 09:26:29.769735 ==
8366 09:26:29.773095 Dram Type= 6, Freq= 0, CH_1, rank 1
8367 09:26:29.776457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 09:26:29.776591 ==
8369 09:26:29.783160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8370 09:26:29.786512 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8371 09:26:29.792772 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8372 09:26:29.796269 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8373 09:26:29.806158 [CA 0] Center 43 (14~72) winsize 59
8374 09:26:29.809434 [CA 1] Center 42 (12~72) winsize 61
8375 09:26:29.812842 [CA 2] Center 38 (9~68) winsize 60
8376 09:26:29.816448 [CA 3] Center 37 (8~67) winsize 60
8377 09:26:29.819514 [CA 4] Center 38 (9~68) winsize 60
8378 09:26:29.822613 [CA 5] Center 37 (8~67) winsize 60
8379 09:26:29.822721
8380 09:26:29.826220 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8381 09:26:29.826338
8382 09:26:29.829468 [CATrainingPosCal] consider 2 rank data
8383 09:26:29.832793 u2DelayCellTimex100 = 290/100 ps
8384 09:26:29.835877 CA0 delay=43 (14~72),Diff = 6 PI (20 cell)
8385 09:26:29.842542 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8386 09:26:29.846428 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8387 09:26:29.849761 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8388 09:26:29.852530 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8389 09:26:29.855964 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8390 09:26:29.856099
8391 09:26:29.859486 CA PerBit enable=1, Macro0, CA PI delay=37
8392 09:26:29.859569
8393 09:26:29.862640 [CBTSetCACLKResult] CA Dly = 37
8394 09:26:29.862748 CS Dly: 9 (0~41)
8395 09:26:29.869438 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8396 09:26:29.872706 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8397 09:26:29.872796
8398 09:26:29.876019 ----->DramcWriteLeveling(PI) begin...
8399 09:26:29.876116 ==
8400 09:26:29.879192 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 09:26:29.882528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 09:26:29.885711 ==
8403 09:26:29.885780 Write leveling (Byte 0): 24 => 24
8404 09:26:29.888994 Write leveling (Byte 1): 27 => 27
8405 09:26:29.892337 DramcWriteLeveling(PI) end<-----
8406 09:26:29.892409
8407 09:26:29.892470 ==
8408 09:26:29.896196 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 09:26:29.902690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 09:26:29.902798 ==
8411 09:26:29.902889 [Gating] SW mode calibration
8412 09:26:29.912612 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8413 09:26:29.915984 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8414 09:26:29.919129 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 09:26:29.925992 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 09:26:29.929185 1 4 8 | B1->B0 | 2a2a 2d2d | 0 1 | (0 0) (0 0)
8417 09:26:29.932431 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 09:26:29.939202 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 09:26:29.942485 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 09:26:29.945962 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 09:26:29.952177 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 09:26:29.956157 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 09:26:29.958919 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 09:26:29.966005 1 5 8 | B1->B0 | 2e2e 2a2a | 0 1 | (0 0) (1 0)
8425 09:26:29.969204 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8426 09:26:29.972658 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 09:26:29.979321 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 09:26:29.982695 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 09:26:29.985856 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 09:26:29.992389 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 09:26:29.995755 1 6 4 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
8432 09:26:29.999281 1 6 8 | B1->B0 | 4141 4242 | 0 0 | (1 1) (1 1)
8433 09:26:30.005897 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 09:26:30.009273 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 09:26:30.012555 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 09:26:30.015856 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 09:26:30.022506 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 09:26:30.025940 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 09:26:30.029080 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8440 09:26:30.035828 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8441 09:26:30.039294 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8442 09:26:30.042413 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 09:26:30.048609 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 09:26:30.051929 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 09:26:30.055799 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 09:26:30.062442 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 09:26:30.065752 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 09:26:30.068858 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 09:26:30.075529 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 09:26:30.078749 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 09:26:30.082501 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 09:26:30.088891 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 09:26:30.092106 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 09:26:30.095320 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 09:26:30.101859 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 09:26:30.105746 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8457 09:26:30.109060 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8458 09:26:30.115680 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 09:26:30.115768 Total UI for P1: 0, mck2ui 16
8460 09:26:30.122183 best dqsien dly found for B0: ( 1, 9, 10)
8461 09:26:30.122261 Total UI for P1: 0, mck2ui 16
8462 09:26:30.125399 best dqsien dly found for B1: ( 1, 9, 10)
8463 09:26:30.132060 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8464 09:26:30.135615 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8465 09:26:30.135694
8466 09:26:30.138683 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8467 09:26:30.142179 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8468 09:26:30.145289 [Gating] SW calibration Done
8469 09:26:30.145373 ==
8470 09:26:30.148687 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 09:26:30.152087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 09:26:30.152171 ==
8473 09:26:30.155248 RX Vref Scan: 0
8474 09:26:30.155331
8475 09:26:30.155398 RX Vref 0 -> 0, step: 1
8476 09:26:30.155460
8477 09:26:30.158559 RX Delay 0 -> 252, step: 8
8478 09:26:30.162345 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8479 09:26:30.165658 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8480 09:26:30.172301 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8481 09:26:30.175600 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8482 09:26:30.178434 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8483 09:26:30.181779 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8484 09:26:30.185075 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8485 09:26:30.192160 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8486 09:26:30.195429 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8487 09:26:30.198811 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8488 09:26:30.202005 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8489 09:26:30.205302 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8490 09:26:30.212005 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8491 09:26:30.215278 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8492 09:26:30.218516 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8493 09:26:30.221815 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8494 09:26:30.221915 ==
8495 09:26:30.225175 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 09:26:30.231864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 09:26:30.231976 ==
8498 09:26:30.232069 DQS Delay:
8499 09:26:30.232165 DQS0 = 0, DQS1 = 0
8500 09:26:30.235474 DQM Delay:
8501 09:26:30.235571 DQM0 = 136, DQM1 = 130
8502 09:26:30.238619 DQ Delay:
8503 09:26:30.242147 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8504 09:26:30.245193 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8505 09:26:30.248543 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8506 09:26:30.251799 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8507 09:26:30.251900
8508 09:26:30.251991
8509 09:26:30.252088 ==
8510 09:26:30.255535 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 09:26:30.258763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 09:26:30.258871 ==
8513 09:26:30.262025
8514 09:26:30.262113
8515 09:26:30.262205 TX Vref Scan disable
8516 09:26:30.265124 == TX Byte 0 ==
8517 09:26:30.268756 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8518 09:26:30.271606 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8519 09:26:30.275346 == TX Byte 1 ==
8520 09:26:30.278751 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8521 09:26:30.282034 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8522 09:26:30.282135 ==
8523 09:26:30.284913 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 09:26:30.291553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 09:26:30.291639 ==
8526 09:26:30.303086
8527 09:26:30.306828 TX Vref early break, caculate TX vref
8528 09:26:30.310010 TX Vref=16, minBit 10, minWin=22, winSum=375
8529 09:26:30.313361 TX Vref=18, minBit 10, minWin=22, winSum=386
8530 09:26:30.316535 TX Vref=20, minBit 10, minWin=23, winSum=390
8531 09:26:30.319872 TX Vref=22, minBit 10, minWin=23, winSum=399
8532 09:26:30.323328 TX Vref=24, minBit 9, minWin=24, winSum=413
8533 09:26:30.329849 TX Vref=26, minBit 13, minWin=25, winSum=422
8534 09:26:30.333094 TX Vref=28, minBit 14, minWin=25, winSum=426
8535 09:26:30.336752 TX Vref=30, minBit 10, minWin=24, winSum=418
8536 09:26:30.340018 TX Vref=32, minBit 12, minWin=24, winSum=405
8537 09:26:30.343331 TX Vref=34, minBit 13, minWin=23, winSum=400
8538 09:26:30.349703 [TxChooseVref] Worse bit 14, Min win 25, Win sum 426, Final Vref 28
8539 09:26:30.349782
8540 09:26:30.353118 Final TX Range 0 Vref 28
8541 09:26:30.353191
8542 09:26:30.353252 ==
8543 09:26:30.356827 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 09:26:30.359988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 09:26:30.360104 ==
8546 09:26:30.360201
8547 09:26:30.363362
8548 09:26:30.363464 TX Vref Scan disable
8549 09:26:30.370262 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8550 09:26:30.370339 == TX Byte 0 ==
8551 09:26:30.373440 u2DelayCellOfst[0]=13 cells (4 PI)
8552 09:26:30.376721 u2DelayCellOfst[1]=10 cells (3 PI)
8553 09:26:30.379865 u2DelayCellOfst[2]=0 cells (0 PI)
8554 09:26:30.383283 u2DelayCellOfst[3]=6 cells (2 PI)
8555 09:26:30.386578 u2DelayCellOfst[4]=6 cells (2 PI)
8556 09:26:30.389767 u2DelayCellOfst[5]=16 cells (5 PI)
8557 09:26:30.393062 u2DelayCellOfst[6]=16 cells (5 PI)
8558 09:26:30.396856 u2DelayCellOfst[7]=3 cells (1 PI)
8559 09:26:30.400209 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8560 09:26:30.403494 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8561 09:26:30.406645 == TX Byte 1 ==
8562 09:26:30.409978 u2DelayCellOfst[8]=0 cells (0 PI)
8563 09:26:30.410071 u2DelayCellOfst[9]=6 cells (2 PI)
8564 09:26:30.412864 u2DelayCellOfst[10]=10 cells (3 PI)
8565 09:26:30.416198 u2DelayCellOfst[11]=6 cells (2 PI)
8566 09:26:30.419512 u2DelayCellOfst[12]=16 cells (5 PI)
8567 09:26:30.422943 u2DelayCellOfst[13]=20 cells (6 PI)
8568 09:26:30.426309 u2DelayCellOfst[14]=23 cells (7 PI)
8569 09:26:30.429649 u2DelayCellOfst[15]=20 cells (6 PI)
8570 09:26:30.436198 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8571 09:26:30.439529 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8572 09:26:30.439642 DramC Write-DBI on
8573 09:26:30.439740 ==
8574 09:26:30.442865 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 09:26:30.449299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 09:26:30.449390 ==
8577 09:26:30.449463
8578 09:26:30.449529
8579 09:26:30.449591 TX Vref Scan disable
8580 09:26:30.453522 == TX Byte 0 ==
8581 09:26:30.456777 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8582 09:26:30.460143 == TX Byte 1 ==
8583 09:26:30.463287 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8584 09:26:30.466716 DramC Write-DBI off
8585 09:26:30.466794
8586 09:26:30.466873 [DATLAT]
8587 09:26:30.466940 Freq=1600, CH1 RK0
8588 09:26:30.467002
8589 09:26:30.470005 DATLAT Default: 0xf
8590 09:26:30.470113 0, 0xFFFF, sum = 0
8591 09:26:30.473380 1, 0xFFFF, sum = 0
8592 09:26:30.476575 2, 0xFFFF, sum = 0
8593 09:26:30.476657 3, 0xFFFF, sum = 0
8594 09:26:30.479906 4, 0xFFFF, sum = 0
8595 09:26:30.480014 5, 0xFFFF, sum = 0
8596 09:26:30.483186 6, 0xFFFF, sum = 0
8597 09:26:30.483296 7, 0xFFFF, sum = 0
8598 09:26:30.486640 8, 0xFFFF, sum = 0
8599 09:26:30.486750 9, 0xFFFF, sum = 0
8600 09:26:30.489963 10, 0xFFFF, sum = 0
8601 09:26:30.490040 11, 0xFFFF, sum = 0
8602 09:26:30.493189 12, 0xFFFF, sum = 0
8603 09:26:30.493271 13, 0xFFFF, sum = 0
8604 09:26:30.497013 14, 0x0, sum = 1
8605 09:26:30.497092 15, 0x0, sum = 2
8606 09:26:30.500279 16, 0x0, sum = 3
8607 09:26:30.500391 17, 0x0, sum = 4
8608 09:26:30.503566 best_step = 15
8609 09:26:30.503667
8610 09:26:30.503761 ==
8611 09:26:30.506829 Dram Type= 6, Freq= 0, CH_1, rank 0
8612 09:26:30.510122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8613 09:26:30.510207 ==
8614 09:26:30.510278 RX Vref Scan: 1
8615 09:26:30.513059
8616 09:26:30.513131 Set Vref Range= 24 -> 127
8617 09:26:30.513199
8618 09:26:30.516298 RX Vref 24 -> 127, step: 1
8619 09:26:30.516397
8620 09:26:30.519682 RX Delay 19 -> 252, step: 4
8621 09:26:30.519758
8622 09:26:30.523099 Set Vref, RX VrefLevel [Byte0]: 24
8623 09:26:30.526336 [Byte1]: 24
8624 09:26:30.526413
8625 09:26:30.530166 Set Vref, RX VrefLevel [Byte0]: 25
8626 09:26:30.533410 [Byte1]: 25
8627 09:26:30.533493
8628 09:26:30.536661 Set Vref, RX VrefLevel [Byte0]: 26
8629 09:26:30.539857 [Byte1]: 26
8630 09:26:30.543669
8631 09:26:30.543773 Set Vref, RX VrefLevel [Byte0]: 27
8632 09:26:30.546772 [Byte1]: 27
8633 09:26:30.551154
8634 09:26:30.551263 Set Vref, RX VrefLevel [Byte0]: 28
8635 09:26:30.554622 [Byte1]: 28
8636 09:26:30.558736
8637 09:26:30.558845 Set Vref, RX VrefLevel [Byte0]: 29
8638 09:26:30.562079 [Byte1]: 29
8639 09:26:30.566240
8640 09:26:30.566322 Set Vref, RX VrefLevel [Byte0]: 30
8641 09:26:30.569594 [Byte1]: 30
8642 09:26:30.573958
8643 09:26:30.574055 Set Vref, RX VrefLevel [Byte0]: 31
8644 09:26:30.577303 [Byte1]: 31
8645 09:26:30.581322
8646 09:26:30.581430 Set Vref, RX VrefLevel [Byte0]: 32
8647 09:26:30.584712 [Byte1]: 32
8648 09:26:30.589044
8649 09:26:30.589122 Set Vref, RX VrefLevel [Byte0]: 33
8650 09:26:30.592263 [Byte1]: 33
8651 09:26:30.596798
8652 09:26:30.596875 Set Vref, RX VrefLevel [Byte0]: 34
8653 09:26:30.600073 [Byte1]: 34
8654 09:26:30.604533
8655 09:26:30.604648 Set Vref, RX VrefLevel [Byte0]: 35
8656 09:26:30.607293 [Byte1]: 35
8657 09:26:30.611536
8658 09:26:30.611613 Set Vref, RX VrefLevel [Byte0]: 36
8659 09:26:30.614980 [Byte1]: 36
8660 09:26:30.619335
8661 09:26:30.619441 Set Vref, RX VrefLevel [Byte0]: 37
8662 09:26:30.622618 [Byte1]: 37
8663 09:26:30.627095
8664 09:26:30.627176 Set Vref, RX VrefLevel [Byte0]: 38
8665 09:26:30.630565 [Byte1]: 38
8666 09:26:30.634257
8667 09:26:30.634348 Set Vref, RX VrefLevel [Byte0]: 39
8668 09:26:30.637594 [Byte1]: 39
8669 09:26:30.642011
8670 09:26:30.642129 Set Vref, RX VrefLevel [Byte0]: 40
8671 09:26:30.645243 [Byte1]: 40
8672 09:26:30.649701
8673 09:26:30.649895 Set Vref, RX VrefLevel [Byte0]: 41
8674 09:26:30.652944 [Byte1]: 41
8675 09:26:30.657175
8676 09:26:30.657291 Set Vref, RX VrefLevel [Byte0]: 42
8677 09:26:30.660358 [Byte1]: 42
8678 09:26:30.664732
8679 09:26:30.664817 Set Vref, RX VrefLevel [Byte0]: 43
8680 09:26:30.668452 [Byte1]: 43
8681 09:26:30.672286
8682 09:26:30.672371 Set Vref, RX VrefLevel [Byte0]: 44
8683 09:26:30.675535 [Byte1]: 44
8684 09:26:30.680364
8685 09:26:30.680482 Set Vref, RX VrefLevel [Byte0]: 45
8686 09:26:30.683019 [Byte1]: 45
8687 09:26:30.687521
8688 09:26:30.687606 Set Vref, RX VrefLevel [Byte0]: 46
8689 09:26:30.690929 [Byte1]: 46
8690 09:26:30.695241
8691 09:26:30.695351 Set Vref, RX VrefLevel [Byte0]: 47
8692 09:26:30.698555 [Byte1]: 47
8693 09:26:30.702848
8694 09:26:30.702952 Set Vref, RX VrefLevel [Byte0]: 48
8695 09:26:30.706255 [Byte1]: 48
8696 09:26:30.709938
8697 09:26:30.713684 Set Vref, RX VrefLevel [Byte0]: 49
8698 09:26:30.713766 [Byte1]: 49
8699 09:26:30.717598
8700 09:26:30.717669 Set Vref, RX VrefLevel [Byte0]: 50
8701 09:26:30.720851 [Byte1]: 50
8702 09:26:30.725292
8703 09:26:30.725393 Set Vref, RX VrefLevel [Byte0]: 51
8704 09:26:30.728633 [Byte1]: 51
8705 09:26:30.733076
8706 09:26:30.733184 Set Vref, RX VrefLevel [Byte0]: 52
8707 09:26:30.736232 [Byte1]: 52
8708 09:26:30.740802
8709 09:26:30.740882 Set Vref, RX VrefLevel [Byte0]: 53
8710 09:26:30.744099 [Byte1]: 53
8711 09:26:30.748322
8712 09:26:30.748394 Set Vref, RX VrefLevel [Byte0]: 54
8713 09:26:30.751223 [Byte1]: 54
8714 09:26:30.755659
8715 09:26:30.755744 Set Vref, RX VrefLevel [Byte0]: 55
8716 09:26:30.758900 [Byte1]: 55
8717 09:26:30.763107
8718 09:26:30.763195 Set Vref, RX VrefLevel [Byte0]: 56
8719 09:26:30.766629 [Byte1]: 56
8720 09:26:30.771068
8721 09:26:30.771183 Set Vref, RX VrefLevel [Byte0]: 57
8722 09:26:30.773869 [Byte1]: 57
8723 09:26:30.778225
8724 09:26:30.778341 Set Vref, RX VrefLevel [Byte0]: 58
8725 09:26:30.781708 [Byte1]: 58
8726 09:26:30.786081
8727 09:26:30.786191 Set Vref, RX VrefLevel [Byte0]: 59
8728 09:26:30.789484 [Byte1]: 59
8729 09:26:30.793320
8730 09:26:30.793451 Set Vref, RX VrefLevel [Byte0]: 60
8731 09:26:30.796768 [Byte1]: 60
8732 09:26:30.801017
8733 09:26:30.801116 Set Vref, RX VrefLevel [Byte0]: 61
8734 09:26:30.804327 [Byte1]: 61
8735 09:26:30.808718
8736 09:26:30.808831 Set Vref, RX VrefLevel [Byte0]: 62
8737 09:26:30.812027 [Byte1]: 62
8738 09:26:30.816449
8739 09:26:30.816531 Set Vref, RX VrefLevel [Byte0]: 63
8740 09:26:30.819737 [Byte1]: 63
8741 09:26:30.823647
8742 09:26:30.823759 Set Vref, RX VrefLevel [Byte0]: 64
8743 09:26:30.826913 [Byte1]: 64
8744 09:26:30.831368
8745 09:26:30.831451 Set Vref, RX VrefLevel [Byte0]: 65
8746 09:26:30.834671 [Byte1]: 65
8747 09:26:30.839129
8748 09:26:30.839206 Set Vref, RX VrefLevel [Byte0]: 66
8749 09:26:30.842451 [Byte1]: 66
8750 09:26:30.846709
8751 09:26:30.846833 Set Vref, RX VrefLevel [Byte0]: 67
8752 09:26:30.849994 [Byte1]: 67
8753 09:26:30.853944
8754 09:26:30.854063 Set Vref, RX VrefLevel [Byte0]: 68
8755 09:26:30.857480 [Byte1]: 68
8756 09:26:30.861419
8757 09:26:30.861537 Set Vref, RX VrefLevel [Byte0]: 69
8758 09:26:30.865164 [Byte1]: 69
8759 09:26:30.869263
8760 09:26:30.869376 Set Vref, RX VrefLevel [Byte0]: 70
8761 09:26:30.872396 [Byte1]: 70
8762 09:26:30.876675
8763 09:26:30.876762 Set Vref, RX VrefLevel [Byte0]: 71
8764 09:26:30.879864 [Byte1]: 71
8765 09:26:30.884353
8766 09:26:30.884470 Set Vref, RX VrefLevel [Byte0]: 72
8767 09:26:30.887583 [Byte1]: 72
8768 09:26:30.892130
8769 09:26:30.892242 Set Vref, RX VrefLevel [Byte0]: 73
8770 09:26:30.895449 [Byte1]: 73
8771 09:26:30.899290
8772 09:26:30.899404 Set Vref, RX VrefLevel [Byte0]: 74
8773 09:26:30.902644 [Byte1]: 74
8774 09:26:30.906957
8775 09:26:30.907043 Final RX Vref Byte 0 = 59 to rank0
8776 09:26:30.910354 Final RX Vref Byte 1 = 61 to rank0
8777 09:26:30.913651 Final RX Vref Byte 0 = 59 to rank1
8778 09:26:30.917331 Final RX Vref Byte 1 = 61 to rank1==
8779 09:26:30.920566 Dram Type= 6, Freq= 0, CH_1, rank 0
8780 09:26:30.927195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8781 09:26:30.927311 ==
8782 09:26:30.927426 DQS Delay:
8783 09:26:30.927540 DQS0 = 0, DQS1 = 0
8784 09:26:30.930511 DQM Delay:
8785 09:26:30.930627 DQM0 = 134, DQM1 = 129
8786 09:26:30.933890 DQ Delay:
8787 09:26:30.937131 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8788 09:26:30.940495 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =132
8789 09:26:30.943894 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8790 09:26:30.947039 DQ12 =140, DQ13 =134, DQ14 =134, DQ15 =138
8791 09:26:30.947123
8792 09:26:30.947192
8793 09:26:30.947255
8794 09:26:30.950292 [DramC_TX_OE_Calibration] TA2
8795 09:26:30.953495 Original DQ_B0 (3 6) =30, OEN = 27
8796 09:26:30.957409 Original DQ_B1 (3 6) =30, OEN = 27
8797 09:26:30.960544 24, 0x0, End_B0=24 End_B1=24
8798 09:26:30.960636 25, 0x0, End_B0=25 End_B1=25
8799 09:26:30.963908 26, 0x0, End_B0=26 End_B1=26
8800 09:26:30.967209 27, 0x0, End_B0=27 End_B1=27
8801 09:26:30.970444 28, 0x0, End_B0=28 End_B1=28
8802 09:26:30.970528 29, 0x0, End_B0=29 End_B1=29
8803 09:26:30.973739 30, 0x0, End_B0=30 End_B1=30
8804 09:26:30.976877 31, 0x4141, End_B0=30 End_B1=30
8805 09:26:30.980444 Byte0 end_step=30 best_step=27
8806 09:26:30.983812 Byte1 end_step=30 best_step=27
8807 09:26:30.987221 Byte0 TX OE(2T, 0.5T) = (3, 3)
8808 09:26:30.987303 Byte1 TX OE(2T, 0.5T) = (3, 3)
8809 09:26:30.987370
8810 09:26:30.990447
8811 09:26:30.996997 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8812 09:26:31.000391 CH1 RK0: MR19=303, MR18=1826
8813 09:26:31.006991 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8814 09:26:31.007072
8815 09:26:31.010262 ----->DramcWriteLeveling(PI) begin...
8816 09:26:31.010342 ==
8817 09:26:31.013780 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 09:26:31.016948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 09:26:31.017037 ==
8820 09:26:31.019975 Write leveling (Byte 0): 22 => 22
8821 09:26:31.023315 Write leveling (Byte 1): 30 => 30
8822 09:26:31.026785 DramcWriteLeveling(PI) end<-----
8823 09:26:31.026865
8824 09:26:31.026938 ==
8825 09:26:31.030178 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 09:26:31.033390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 09:26:31.033474 ==
8828 09:26:31.036754 [Gating] SW mode calibration
8829 09:26:31.043485 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8830 09:26:31.050084 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8831 09:26:31.053352 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 09:26:31.056640 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 09:26:31.063160 1 4 8 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
8834 09:26:31.066581 1 4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8835 09:26:31.069787 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 09:26:31.076320 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 09:26:31.080162 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 09:26:31.083273 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 09:26:31.090257 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 09:26:31.093115 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8841 09:26:31.096284 1 5 8 | B1->B0 | 2828 3434 | 0 1 | (1 0) (1 0)
8842 09:26:31.102996 1 5 12 | B1->B0 | 2323 2c2c | 0 1 | (1 0) (1 0)
8843 09:26:31.106346 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 09:26:31.110152 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 09:26:31.116619 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 09:26:31.119787 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 09:26:31.123148 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 09:26:31.129585 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 09:26:31.133306 1 6 8 | B1->B0 | 4545 2323 | 0 0 | (0 0) (0 0)
8850 09:26:31.136490 1 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8851 09:26:31.143077 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 09:26:31.146347 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 09:26:31.149526 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 09:26:31.156252 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 09:26:31.159497 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 09:26:31.162866 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 09:26:31.166150 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8858 09:26:31.172810 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8859 09:26:31.176494 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 09:26:31.179589 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 09:26:31.186061 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 09:26:31.189589 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 09:26:31.192784 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 09:26:31.199336 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 09:26:31.203096 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 09:26:31.206245 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 09:26:31.212681 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 09:26:31.216032 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 09:26:31.219802 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 09:26:31.225935 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 09:26:31.229281 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 09:26:31.232537 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8873 09:26:31.239285 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8874 09:26:31.242589 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 09:26:31.245841 Total UI for P1: 0, mck2ui 16
8876 09:26:31.249272 best dqsien dly found for B0: ( 1, 9, 8)
8877 09:26:31.252462 Total UI for P1: 0, mck2ui 16
8878 09:26:31.255801 best dqsien dly found for B1: ( 1, 9, 6)
8879 09:26:31.259170 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8880 09:26:31.262469 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8881 09:26:31.262546
8882 09:26:31.266139 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8883 09:26:31.269288 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8884 09:26:31.272648 [Gating] SW calibration Done
8885 09:26:31.272732 ==
8886 09:26:31.275801 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 09:26:31.279458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 09:26:31.279538 ==
8889 09:26:31.282676 RX Vref Scan: 0
8890 09:26:31.282753
8891 09:26:31.285830 RX Vref 0 -> 0, step: 1
8892 09:26:31.285907
8893 09:26:31.285972 RX Delay 0 -> 252, step: 8
8894 09:26:31.292852 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8895 09:26:31.296089 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8896 09:26:31.299326 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8897 09:26:31.303088 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8898 09:26:31.305854 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8899 09:26:31.312510 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8900 09:26:31.315769 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8901 09:26:31.319131 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8902 09:26:31.322409 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8903 09:26:31.326014 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8904 09:26:31.332556 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8905 09:26:31.335883 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8906 09:26:31.339278 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8907 09:26:31.342508 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8908 09:26:31.345750 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8909 09:26:31.352877 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8910 09:26:31.352963 ==
8911 09:26:31.356101 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 09:26:31.359302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 09:26:31.359388 ==
8914 09:26:31.359457 DQS Delay:
8915 09:26:31.362551 DQS0 = 0, DQS1 = 0
8916 09:26:31.362662 DQM Delay:
8917 09:26:31.365794 DQM0 = 136, DQM1 = 132
8918 09:26:31.365885 DQ Delay:
8919 09:26:31.369070 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8920 09:26:31.372289 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8921 09:26:31.376089 DQ8 =115, DQ9 =119, DQ10 =127, DQ11 =127
8922 09:26:31.379341 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8923 09:26:31.379455
8924 09:26:31.379553
8925 09:26:31.382667 ==
8926 09:26:31.385868 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 09:26:31.389077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 09:26:31.389163 ==
8929 09:26:31.389232
8930 09:26:31.389294
8931 09:26:31.392184 TX Vref Scan disable
8932 09:26:31.392314 == TX Byte 0 ==
8933 09:26:31.395799 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8934 09:26:31.402571 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8935 09:26:31.402657 == TX Byte 1 ==
8936 09:26:31.405785 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8937 09:26:31.412377 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8938 09:26:31.412464 ==
8939 09:26:31.415757 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 09:26:31.419104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 09:26:31.419210 ==
8942 09:26:31.432880
8943 09:26:31.436199 TX Vref early break, caculate TX vref
8944 09:26:31.439351 TX Vref=16, minBit 9, minWin=21, winSum=380
8945 09:26:31.442535 TX Vref=18, minBit 9, minWin=22, winSum=386
8946 09:26:31.445777 TX Vref=20, minBit 8, minWin=23, winSum=396
8947 09:26:31.449508 TX Vref=22, minBit 8, minWin=24, winSum=406
8948 09:26:31.452790 TX Vref=24, minBit 8, minWin=24, winSum=408
8949 09:26:31.459416 TX Vref=26, minBit 9, minWin=24, winSum=418
8950 09:26:31.462601 TX Vref=28, minBit 10, minWin=24, winSum=414
8951 09:26:31.465882 TX Vref=30, minBit 8, minWin=24, winSum=410
8952 09:26:31.469145 TX Vref=32, minBit 8, minWin=24, winSum=401
8953 09:26:31.472895 TX Vref=34, minBit 9, minWin=23, winSum=395
8954 09:26:31.479486 [TxChooseVref] Worse bit 9, Min win 24, Win sum 418, Final Vref 26
8955 09:26:31.479588
8956 09:26:31.482728 Final TX Range 0 Vref 26
8957 09:26:31.482827
8958 09:26:31.482920 ==
8959 09:26:31.485979 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 09:26:31.489291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 09:26:31.489390 ==
8962 09:26:31.489480
8963 09:26:31.489554
8964 09:26:31.492613 TX Vref Scan disable
8965 09:26:31.499328 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8966 09:26:31.499434 == TX Byte 0 ==
8967 09:26:31.502603 u2DelayCellOfst[0]=20 cells (6 PI)
8968 09:26:31.505630 u2DelayCellOfst[1]=13 cells (4 PI)
8969 09:26:31.509312 u2DelayCellOfst[2]=0 cells (0 PI)
8970 09:26:31.512553 u2DelayCellOfst[3]=6 cells (2 PI)
8971 09:26:31.515711 u2DelayCellOfst[4]=10 cells (3 PI)
8972 09:26:31.519021 u2DelayCellOfst[5]=20 cells (6 PI)
8973 09:26:31.522804 u2DelayCellOfst[6]=16 cells (5 PI)
8974 09:26:31.522905 u2DelayCellOfst[7]=6 cells (2 PI)
8975 09:26:31.529168 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8976 09:26:31.532321 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8977 09:26:31.532426 == TX Byte 1 ==
8978 09:26:31.535651 u2DelayCellOfst[8]=0 cells (0 PI)
8979 09:26:31.538961 u2DelayCellOfst[9]=3 cells (1 PI)
8980 09:26:31.542233 u2DelayCellOfst[10]=6 cells (2 PI)
8981 09:26:31.545439 u2DelayCellOfst[11]=3 cells (1 PI)
8982 09:26:31.548740 u2DelayCellOfst[12]=13 cells (4 PI)
8983 09:26:31.552468 u2DelayCellOfst[13]=16 cells (5 PI)
8984 09:26:31.555775 u2DelayCellOfst[14]=16 cells (5 PI)
8985 09:26:31.559049 u2DelayCellOfst[15]=16 cells (5 PI)
8986 09:26:31.562219 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8987 09:26:31.568602 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8988 09:26:31.568695 DramC Write-DBI on
8989 09:26:31.568788 ==
8990 09:26:31.571875 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 09:26:31.575144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 09:26:31.578465 ==
8993 09:26:31.578557
8994 09:26:31.578623
8995 09:26:31.578682 TX Vref Scan disable
8996 09:26:31.582236 == TX Byte 0 ==
8997 09:26:31.585423 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8998 09:26:31.588686 == TX Byte 1 ==
8999 09:26:31.592000 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
9000 09:26:31.592099 DramC Write-DBI off
9001 09:26:31.595254
9002 09:26:31.595350 [DATLAT]
9003 09:26:31.595443 Freq=1600, CH1 RK1
9004 09:26:31.595534
9005 09:26:31.599055 DATLAT Default: 0xf
9006 09:26:31.599154 0, 0xFFFF, sum = 0
9007 09:26:31.602163 1, 0xFFFF, sum = 0
9008 09:26:31.605333 2, 0xFFFF, sum = 0
9009 09:26:31.605444 3, 0xFFFF, sum = 0
9010 09:26:31.608482 4, 0xFFFF, sum = 0
9011 09:26:31.608614 5, 0xFFFF, sum = 0
9012 09:26:31.612253 6, 0xFFFF, sum = 0
9013 09:26:31.612359 7, 0xFFFF, sum = 0
9014 09:26:31.615445 8, 0xFFFF, sum = 0
9015 09:26:31.615549 9, 0xFFFF, sum = 0
9016 09:26:31.618888 10, 0xFFFF, sum = 0
9017 09:26:31.618994 11, 0xFFFF, sum = 0
9018 09:26:31.622093 12, 0xFFFF, sum = 0
9019 09:26:31.622195 13, 0xFFFF, sum = 0
9020 09:26:31.625262 14, 0x0, sum = 1
9021 09:26:31.625364 15, 0x0, sum = 2
9022 09:26:31.628983 16, 0x0, sum = 3
9023 09:26:31.629093 17, 0x0, sum = 4
9024 09:26:31.632254 best_step = 15
9025 09:26:31.632354
9026 09:26:31.632448 ==
9027 09:26:31.635448 Dram Type= 6, Freq= 0, CH_1, rank 1
9028 09:26:31.638734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9029 09:26:31.638837 ==
9030 09:26:31.638928 RX Vref Scan: 0
9031 09:26:31.642043
9032 09:26:31.642149 RX Vref 0 -> 0, step: 1
9033 09:26:31.642245
9034 09:26:31.645326 RX Delay 19 -> 252, step: 4
9035 09:26:31.648651 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9036 09:26:31.655050 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9037 09:26:31.658779 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9038 09:26:31.661980 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9039 09:26:31.665247 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9040 09:26:31.668481 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9041 09:26:31.671819 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9042 09:26:31.678297 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
9043 09:26:31.681689 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9044 09:26:31.685023 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9045 09:26:31.688650 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9046 09:26:31.691930 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9047 09:26:31.698450 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9048 09:26:31.701735 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9049 09:26:31.704820 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9050 09:26:31.708510 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9051 09:26:31.708651 ==
9052 09:26:31.711804 Dram Type= 6, Freq= 0, CH_1, rank 1
9053 09:26:31.718159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9054 09:26:31.718275 ==
9055 09:26:31.718373 DQS Delay:
9056 09:26:31.721807 DQS0 = 0, DQS1 = 0
9057 09:26:31.721923 DQM Delay:
9058 09:26:31.722026 DQM0 = 133, DQM1 = 130
9059 09:26:31.724771 DQ Delay:
9060 09:26:31.728017 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9061 09:26:31.731389 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
9062 09:26:31.735056 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =124
9063 09:26:31.738235 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9064 09:26:31.738362
9065 09:26:31.738432
9066 09:26:31.738493
9067 09:26:31.741515 [DramC_TX_OE_Calibration] TA2
9068 09:26:31.744821 Original DQ_B0 (3 6) =30, OEN = 27
9069 09:26:31.748229 Original DQ_B1 (3 6) =30, OEN = 27
9070 09:26:31.751485 24, 0x0, End_B0=24 End_B1=24
9071 09:26:31.751606 25, 0x0, End_B0=25 End_B1=25
9072 09:26:31.754905 26, 0x0, End_B0=26 End_B1=26
9073 09:26:31.758253 27, 0x0, End_B0=27 End_B1=27
9074 09:26:31.761713 28, 0x0, End_B0=28 End_B1=28
9075 09:26:31.765031 29, 0x0, End_B0=29 End_B1=29
9076 09:26:31.765133 30, 0x0, End_B0=30 End_B1=30
9077 09:26:31.768334 31, 0x5151, End_B0=30 End_B1=30
9078 09:26:31.771672 Byte0 end_step=30 best_step=27
9079 09:26:31.774886 Byte1 end_step=30 best_step=27
9080 09:26:31.778252 Byte0 TX OE(2T, 0.5T) = (3, 3)
9081 09:26:31.781596 Byte1 TX OE(2T, 0.5T) = (3, 3)
9082 09:26:31.781680
9083 09:26:31.781748
9084 09:26:31.788258 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9085 09:26:31.791396 CH1 RK1: MR19=303, MR18=1E09
9086 09:26:31.797960 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9087 09:26:31.801195 [RxdqsGatingPostProcess] freq 1600
9088 09:26:31.805150 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9089 09:26:31.808339 best DQS0 dly(2T, 0.5T) = (1, 1)
9090 09:26:31.811512 best DQS1 dly(2T, 0.5T) = (1, 1)
9091 09:26:31.814791 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9092 09:26:31.818030 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9093 09:26:31.821464 best DQS0 dly(2T, 0.5T) = (1, 1)
9094 09:26:31.824677 best DQS1 dly(2T, 0.5T) = (1, 1)
9095 09:26:31.828388 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9096 09:26:31.831467 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9097 09:26:31.835044 Pre-setting of DQS Precalculation
9098 09:26:31.838089 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9099 09:26:31.845073 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9100 09:26:31.851127 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9101 09:26:31.851243
9102 09:26:31.854545
9103 09:26:31.854634 [Calibration Summary] 3200 Mbps
9104 09:26:31.857831 CH 0, Rank 0
9105 09:26:31.857918 SW Impedance : PASS
9106 09:26:31.861280 DUTY Scan : NO K
9107 09:26:31.864669 ZQ Calibration : PASS
9108 09:26:31.864756 Jitter Meter : NO K
9109 09:26:31.867950 CBT Training : PASS
9110 09:26:31.871290 Write leveling : PASS
9111 09:26:31.871377 RX DQS gating : PASS
9112 09:26:31.874529 RX DQ/DQS(RDDQC) : PASS
9113 09:26:31.877970 TX DQ/DQS : PASS
9114 09:26:31.878081 RX DATLAT : PASS
9115 09:26:31.881196 RX DQ/DQS(Engine): PASS
9116 09:26:31.884556 TX OE : PASS
9117 09:26:31.884672 All Pass.
9118 09:26:31.884779
9119 09:26:31.884879 CH 0, Rank 1
9120 09:26:31.888018 SW Impedance : PASS
9121 09:26:31.891308 DUTY Scan : NO K
9122 09:26:31.891394 ZQ Calibration : PASS
9123 09:26:31.894665 Jitter Meter : NO K
9124 09:26:31.894781 CBT Training : PASS
9125 09:26:31.897776 Write leveling : PASS
9126 09:26:31.901201 RX DQS gating : PASS
9127 09:26:31.901287 RX DQ/DQS(RDDQC) : PASS
9128 09:26:31.904414 TX DQ/DQS : PASS
9129 09:26:31.907741 RX DATLAT : PASS
9130 09:26:31.907827 RX DQ/DQS(Engine): PASS
9131 09:26:31.911025 TX OE : PASS
9132 09:26:31.911111 All Pass.
9133 09:26:31.911180
9134 09:26:31.914734 CH 1, Rank 0
9135 09:26:31.914820 SW Impedance : PASS
9136 09:26:31.918109 DUTY Scan : NO K
9137 09:26:31.921304 ZQ Calibration : PASS
9138 09:26:31.921392 Jitter Meter : NO K
9139 09:26:31.924497 CBT Training : PASS
9140 09:26:31.927724 Write leveling : PASS
9141 09:26:31.927810 RX DQS gating : PASS
9142 09:26:31.931333 RX DQ/DQS(RDDQC) : PASS
9143 09:26:31.934568 TX DQ/DQS : PASS
9144 09:26:31.934656 RX DATLAT : PASS
9145 09:26:31.937698 RX DQ/DQS(Engine): PASS
9146 09:26:31.941193 TX OE : PASS
9147 09:26:31.941303 All Pass.
9148 09:26:31.941398
9149 09:26:31.941491 CH 1, Rank 1
9150 09:26:31.944293 SW Impedance : PASS
9151 09:26:31.944401 DUTY Scan : NO K
9152 09:26:31.947939 ZQ Calibration : PASS
9153 09:26:31.951203 Jitter Meter : NO K
9154 09:26:31.951308 CBT Training : PASS
9155 09:26:31.954409 Write leveling : PASS
9156 09:26:31.957654 RX DQS gating : PASS
9157 09:26:31.957731 RX DQ/DQS(RDDQC) : PASS
9158 09:26:31.961035 TX DQ/DQS : PASS
9159 09:26:31.964282 RX DATLAT : PASS
9160 09:26:31.964384 RX DQ/DQS(Engine): PASS
9161 09:26:31.967991 TX OE : PASS
9162 09:26:31.968078 All Pass.
9163 09:26:31.968170
9164 09:26:31.971123 DramC Write-DBI on
9165 09:26:31.974482 PER_BANK_REFRESH: Hybrid Mode
9166 09:26:31.974562 TX_TRACKING: ON
9167 09:26:31.984254 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9168 09:26:31.990946 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9169 09:26:31.997613 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9170 09:26:32.001043 [FAST_K] Save calibration result to emmc
9171 09:26:32.004169 sync common calibartion params.
9172 09:26:32.007389 sync cbt_mode0:1, 1:1
9173 09:26:32.010637 dram_init: ddr_geometry: 2
9174 09:26:32.010743 dram_init: ddr_geometry: 2
9175 09:26:32.014312 dram_init: ddr_geometry: 2
9176 09:26:32.017625 0:dram_rank_size:100000000
9177 09:26:32.020904 1:dram_rank_size:100000000
9178 09:26:32.024130 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9179 09:26:32.027443 DFS_SHUFFLE_HW_MODE: ON
9180 09:26:32.031355 dramc_set_vcore_voltage set vcore to 725000
9181 09:26:32.034414 Read voltage for 1600, 0
9182 09:26:32.034524 Vio18 = 0
9183 09:26:32.034627 Vcore = 725000
9184 09:26:32.037562 Vdram = 0
9185 09:26:32.037659 Vddq = 0
9186 09:26:32.037753 Vmddr = 0
9187 09:26:32.041232 switch to 3200 Mbps bootup
9188 09:26:32.041330 [DramcRunTimeConfig]
9189 09:26:32.044289 PHYPLL
9190 09:26:32.044391 DPM_CONTROL_AFTERK: ON
9191 09:26:32.047806 PER_BANK_REFRESH: ON
9192 09:26:32.051048 REFRESH_OVERHEAD_REDUCTION: ON
9193 09:26:32.051147 CMD_PICG_NEW_MODE: OFF
9194 09:26:32.054340 XRTWTW_NEW_MODE: ON
9195 09:26:32.054416 XRTRTR_NEW_MODE: ON
9196 09:26:32.057675 TX_TRACKING: ON
9197 09:26:32.057773 RDSEL_TRACKING: OFF
9198 09:26:32.061045 DQS Precalculation for DVFS: ON
9199 09:26:32.064375 RX_TRACKING: OFF
9200 09:26:32.064476 HW_GATING DBG: ON
9201 09:26:32.067596 ZQCS_ENABLE_LP4: ON
9202 09:26:32.067681 RX_PICG_NEW_MODE: ON
9203 09:26:32.070986 TX_PICG_NEW_MODE: ON
9204 09:26:32.074234 ENABLE_RX_DCM_DPHY: ON
9205 09:26:32.074317 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9206 09:26:32.077559 DUMMY_READ_FOR_TRACKING: OFF
9207 09:26:32.081072 !!! SPM_CONTROL_AFTERK: OFF
9208 09:26:32.084309 !!! SPM could not control APHY
9209 09:26:32.084410 IMPEDANCE_TRACKING: ON
9210 09:26:32.087733 TEMP_SENSOR: ON
9211 09:26:32.087813 HW_SAVE_FOR_SR: OFF
9212 09:26:32.090992 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9213 09:26:32.094403 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9214 09:26:32.097243 Read ODT Tracking: ON
9215 09:26:32.100494 Refresh Rate DeBounce: ON
9216 09:26:32.100631 DFS_NO_QUEUE_FLUSH: ON
9217 09:26:32.104047 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9218 09:26:32.107190 ENABLE_DFS_RUNTIME_MRW: OFF
9219 09:26:32.110568 DDR_RESERVE_NEW_MODE: ON
9220 09:26:32.110659 MR_CBT_SWITCH_FREQ: ON
9221 09:26:32.113892 =========================
9222 09:26:32.133250 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9223 09:26:32.136305 dram_init: ddr_geometry: 2
9224 09:26:32.154573 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9225 09:26:32.158330 dram_init: dram init end (result: 0)
9226 09:26:32.164824 DRAM-K: Full calibration passed in 24525 msecs
9227 09:26:32.168026 MRC: failed to locate region type 0.
9228 09:26:32.168111 DRAM rank0 size:0x100000000,
9229 09:26:32.171355 DRAM rank1 size=0x100000000
9230 09:26:32.181391 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9231 09:26:32.187795 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9232 09:26:32.194431 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9233 09:26:32.201401 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9234 09:26:32.204675 DRAM rank0 size:0x100000000,
9235 09:26:32.207921 DRAM rank1 size=0x100000000
9236 09:26:32.208006 CBMEM:
9237 09:26:32.211048 IMD: root @ 0xfffff000 254 entries.
9238 09:26:32.214364 IMD: root @ 0xffffec00 62 entries.
9239 09:26:32.217698 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9240 09:26:32.221477 WARNING: RO_VPD is uninitialized or empty.
9241 09:26:32.227852 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9242 09:26:32.234485 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9243 09:26:32.247577 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9244 09:26:32.258769 BS: romstage times (exec / console): total (unknown) / 24023 ms
9245 09:26:32.258853
9246 09:26:32.258920
9247 09:26:32.268754 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9248 09:26:32.272056 ARM64: Exception handlers installed.
9249 09:26:32.275366 ARM64: Testing exception
9250 09:26:32.279125 ARM64: Done test exception
9251 09:26:32.279208 Enumerating buses...
9252 09:26:32.282346 Show all devs... Before device enumeration.
9253 09:26:32.285760 Root Device: enabled 1
9254 09:26:32.289001 CPU_CLUSTER: 0: enabled 1
9255 09:26:32.289084 CPU: 00: enabled 1
9256 09:26:32.292389 Compare with tree...
9257 09:26:32.292461 Root Device: enabled 1
9258 09:26:32.295752 CPU_CLUSTER: 0: enabled 1
9259 09:26:32.298709 CPU: 00: enabled 1
9260 09:26:32.298792 Root Device scanning...
9261 09:26:32.302507 scan_static_bus for Root Device
9262 09:26:32.305523 CPU_CLUSTER: 0 enabled
9263 09:26:32.308817 scan_static_bus for Root Device done
9264 09:26:32.312245 scan_bus: bus Root Device finished in 8 msecs
9265 09:26:32.312329 done
9266 09:26:32.318632 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9267 09:26:32.322329 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9268 09:26:32.328938 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9269 09:26:32.332178 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9270 09:26:32.335509 Allocating resources...
9271 09:26:32.335593 Reading resources...
9272 09:26:32.341951 Root Device read_resources bus 0 link: 0
9273 09:26:32.342036 DRAM rank0 size:0x100000000,
9274 09:26:32.345606 DRAM rank1 size=0x100000000
9275 09:26:32.348766 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9276 09:26:32.352030 CPU: 00 missing read_resources
9277 09:26:32.355348 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9278 09:26:32.362149 Root Device read_resources bus 0 link: 0 done
9279 09:26:32.362234 Done reading resources.
9280 09:26:32.368833 Show resources in subtree (Root Device)...After reading.
9281 09:26:32.372027 Root Device child on link 0 CPU_CLUSTER: 0
9282 09:26:32.375236 CPU_CLUSTER: 0 child on link 0 CPU: 00
9283 09:26:32.385608 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9284 09:26:32.385686 CPU: 00
9285 09:26:32.388841 Root Device assign_resources, bus 0 link: 0
9286 09:26:32.391765 CPU_CLUSTER: 0 missing set_resources
9287 09:26:32.395159 Root Device assign_resources, bus 0 link: 0 done
9288 09:26:32.398452 Done setting resources.
9289 09:26:32.405465 Show resources in subtree (Root Device)...After assigning values.
9290 09:26:32.408790 Root Device child on link 0 CPU_CLUSTER: 0
9291 09:26:32.411978 CPU_CLUSTER: 0 child on link 0 CPU: 00
9292 09:26:32.421874 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9293 09:26:32.421953 CPU: 00
9294 09:26:32.425493 Done allocating resources.
9295 09:26:32.428716 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9296 09:26:32.431949 Enabling resources...
9297 09:26:32.432031 done.
9298 09:26:32.438519 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9299 09:26:32.438611 Initializing devices...
9300 09:26:32.441876 Root Device init
9301 09:26:32.441960 init hardware done!
9302 09:26:32.445096 0x00000018: ctrlr->caps
9303 09:26:32.448216 52.000 MHz: ctrlr->f_max
9304 09:26:32.448302 0.400 MHz: ctrlr->f_min
9305 09:26:32.451961 0x40ff8080: ctrlr->voltages
9306 09:26:32.452047 sclk: 390625
9307 09:26:32.455282 Bus Width = 1
9308 09:26:32.455395 sclk: 390625
9309 09:26:32.455463 Bus Width = 1
9310 09:26:32.458717 Early init status = 3
9311 09:26:32.465050 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9312 09:26:32.468081 in-header: 03 fc 00 00 01 00 00 00
9313 09:26:32.471837 in-data: 00
9314 09:26:32.474656 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9315 09:26:32.479829 in-header: 03 fd 00 00 00 00 00 00
9316 09:26:32.483166 in-data:
9317 09:26:32.486503 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9318 09:26:32.490954 in-header: 03 fc 00 00 01 00 00 00
9319 09:26:32.493755 in-data: 00
9320 09:26:32.496992 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9321 09:26:32.503081 in-header: 03 fd 00 00 00 00 00 00
9322 09:26:32.506357 in-data:
9323 09:26:32.510114 [SSUSB] Setting up USB HOST controller...
9324 09:26:32.513323 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9325 09:26:32.516696 [SSUSB] phy power-on done.
9326 09:26:32.519925 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9327 09:26:32.526582 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9328 09:26:32.529660 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9329 09:26:32.536405 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9330 09:26:32.543371 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9331 09:26:32.549662 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9332 09:26:32.556134 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9333 09:26:32.563027 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9334 09:26:32.563112 SPM: binary array size = 0x9dc
9335 09:26:32.569604 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9336 09:26:32.576416 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9337 09:26:32.583018 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9338 09:26:32.586605 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9339 09:26:32.590112 configure_display: Starting display init
9340 09:26:32.626551 anx7625_power_on_init: Init interface.
9341 09:26:32.629728 anx7625_disable_pd_protocol: Disabled PD feature.
9342 09:26:32.633166 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9343 09:26:32.660529 anx7625_start_dp_work: Secure OCM version=00
9344 09:26:32.664476 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9345 09:26:32.678998 sp_tx_get_edid_block: EDID Block = 1
9346 09:26:32.781639 Extracted contents:
9347 09:26:32.784779 header: 00 ff ff ff ff ff ff 00
9348 09:26:32.787832 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9349 09:26:32.791038 version: 01 04
9350 09:26:32.794710 basic params: 95 1f 11 78 0a
9351 09:26:32.798093 chroma info: 76 90 94 55 54 90 27 21 50 54
9352 09:26:32.801392 established: 00 00 00
9353 09:26:32.808054 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9354 09:26:32.811010 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9355 09:26:32.817679 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9356 09:26:32.824198 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9357 09:26:32.830891 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9358 09:26:32.834289 extensions: 00
9359 09:26:32.834375 checksum: fb
9360 09:26:32.834460
9361 09:26:32.837990 Manufacturer: IVO Model 57d Serial Number 0
9362 09:26:32.841328 Made week 0 of 2020
9363 09:26:32.841412 EDID version: 1.4
9364 09:26:32.844663 Digital display
9365 09:26:32.847901 6 bits per primary color channel
9366 09:26:32.847984 DisplayPort interface
9367 09:26:32.851208 Maximum image size: 31 cm x 17 cm
9368 09:26:32.854687 Gamma: 220%
9369 09:26:32.854768 Check DPMS levels
9370 09:26:32.857942 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9371 09:26:32.861201 First detailed timing is preferred timing
9372 09:26:32.864390 Established timings supported:
9373 09:26:32.867602 Standard timings supported:
9374 09:26:32.867710 Detailed timings
9375 09:26:32.874366 Hex of detail: 383680a07038204018303c0035ae10000019
9376 09:26:32.877566 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9377 09:26:32.884510 0780 0798 07c8 0820 hborder 0
9378 09:26:32.887806 0438 043b 0447 0458 vborder 0
9379 09:26:32.891027 -hsync -vsync
9380 09:26:32.891136 Did detailed timing
9381 09:26:32.894213 Hex of detail: 000000000000000000000000000000000000
9382 09:26:32.897777 Manufacturer-specified data, tag 0
9383 09:26:32.904199 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9384 09:26:32.904311 ASCII string: InfoVision
9385 09:26:32.910955 Hex of detail: 000000fe00523134304e574635205248200a
9386 09:26:32.914086 ASCII string: R140NWF5 RH
9387 09:26:32.914167 Checksum
9388 09:26:32.914231 Checksum: 0xfb (valid)
9389 09:26:32.920746 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9390 09:26:32.924076 DSI data_rate: 832800000 bps
9391 09:26:32.927546 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9392 09:26:32.934286 anx7625_parse_edid: pixelclock(138800).
9393 09:26:32.937722 hactive(1920), hsync(48), hfp(24), hbp(88)
9394 09:26:32.940973 vactive(1080), vsync(12), vfp(3), vbp(17)
9395 09:26:32.944319 anx7625_dsi_config: config dsi.
9396 09:26:32.950859 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9397 09:26:32.963709 anx7625_dsi_config: success to config DSI
9398 09:26:32.966967 anx7625_dp_start: MIPI phy setup OK.
9399 09:26:32.970079 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9400 09:26:32.973806 mtk_ddp_mode_set invalid vrefresh 60
9401 09:26:32.977011 main_disp_path_setup
9402 09:26:32.977093 ovl_layer_smi_id_en
9403 09:26:32.980520 ovl_layer_smi_id_en
9404 09:26:32.980615 ccorr_config
9405 09:26:32.980685 aal_config
9406 09:26:32.983808 gamma_config
9407 09:26:32.983978 postmask_config
9408 09:26:32.987124 dither_config
9409 09:26:32.990375 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9410 09:26:32.996759 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9411 09:26:33.000448 Root Device init finished in 555 msecs
9412 09:26:33.000628 CPU_CLUSTER: 0 init
9413 09:26:33.010063 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9414 09:26:33.013380 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9415 09:26:33.017108 APU_MBOX 0x190000b0 = 0x10001
9416 09:26:33.020340 APU_MBOX 0x190001b0 = 0x10001
9417 09:26:33.023507 APU_MBOX 0x190005b0 = 0x10001
9418 09:26:33.027058 APU_MBOX 0x190006b0 = 0x10001
9419 09:26:33.030388 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9420 09:26:33.042680 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9421 09:26:33.055204 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9422 09:26:33.061881 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9423 09:26:33.073333 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9424 09:26:33.082137 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9425 09:26:33.085523 CPU_CLUSTER: 0 init finished in 81 msecs
9426 09:26:33.088861 Devices initialized
9427 09:26:33.092113 Show all devs... After init.
9428 09:26:33.092190 Root Device: enabled 1
9429 09:26:33.095368 CPU_CLUSTER: 0: enabled 1
9430 09:26:33.098740 CPU: 00: enabled 1
9431 09:26:33.101998 BS: BS_DEV_INIT run times (exec / console): 214 / 447 ms
9432 09:26:33.106233 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9433 09:26:33.108894 ELOG: NV offset 0x57f000 size 0x1000
9434 09:26:33.115187 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9435 09:26:33.122136 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9436 09:26:33.125285 ELOG: Event(17) added with size 13 at 2024-06-18 09:25:07 UTC
9437 09:26:33.128578 out: cmd=0x121: 03 db 21 01 00 00 00 00
9438 09:26:33.133096 in-header: 03 57 00 00 2c 00 00 00
9439 09:26:33.145917 in-data: e8 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9440 09:26:33.152489 ELOG: Event(A1) added with size 10 at 2024-06-18 09:25:07 UTC
9441 09:26:33.159219 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9442 09:26:33.166314 ELOG: Event(A0) added with size 9 at 2024-06-18 09:25:07 UTC
9443 09:26:33.169619 elog_add_boot_reason: Logged dev mode boot
9444 09:26:33.172852 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9445 09:26:33.176132 Finalize devices...
9446 09:26:33.176235 Devices finalized
9447 09:26:33.182968 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9448 09:26:33.185722 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9449 09:26:33.189183 in-header: 03 07 00 00 08 00 00 00
9450 09:26:33.192422 in-data: aa e4 47 04 13 02 00 00
9451 09:26:33.195676 Chrome EC: UHEPI supported
9452 09:26:33.202327 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9453 09:26:33.206122 in-header: 03 a9 00 00 08 00 00 00
9454 09:26:33.209385 in-data: 84 60 60 08 00 00 00 00
9455 09:26:33.212518 ELOG: Event(91) added with size 10 at 2024-06-18 09:25:07 UTC
9456 09:26:33.219180 Chrome EC: clear events_b mask to 0x0000000020004000
9457 09:26:33.226159 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9458 09:26:33.229510 in-header: 03 fd 00 00 00 00 00 00
9459 09:26:33.229587 in-data:
9460 09:26:33.236158 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9461 09:26:33.239925 Writing coreboot table at 0xffe64000
9462 09:26:33.243143 0. 000000000010a000-0000000000113fff: RAMSTAGE
9463 09:26:33.246447 1. 0000000040000000-00000000400fffff: RAM
9464 09:26:33.249725 2. 0000000040100000-000000004032afff: RAMSTAGE
9465 09:26:33.253146 3. 000000004032b000-00000000545fffff: RAM
9466 09:26:33.259590 4. 0000000054600000-000000005465ffff: BL31
9467 09:26:33.263332 5. 0000000054660000-00000000ffe63fff: RAM
9468 09:26:33.266459 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9469 09:26:33.269743 7. 0000000100000000-000000023fffffff: RAM
9470 09:26:33.273070 Passing 5 GPIOs to payload:
9471 09:26:33.279441 NAME | PORT | POLARITY | VALUE
9472 09:26:33.282834 EC in RW | 0x000000aa | low | undefined
9473 09:26:33.286489 EC interrupt | 0x00000005 | low | undefined
9474 09:26:33.293018 TPM interrupt | 0x000000ab | high | undefined
9475 09:26:33.296336 SD card detect | 0x00000011 | high | undefined
9476 09:26:33.303578 speaker enable | 0x00000093 | high | undefined
9477 09:26:33.306752 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9478 09:26:33.309933 in-header: 03 f9 00 00 02 00 00 00
9479 09:26:33.310018 in-data: 02 00
9480 09:26:33.313140 ADC[4]: Raw value=901401 ID=7
9481 09:26:33.316204 ADC[3]: Raw value=213179 ID=1
9482 09:26:33.316316 RAM Code: 0x71
9483 09:26:33.319489 ADC[6]: Raw value=74502 ID=0
9484 09:26:33.322741 ADC[5]: Raw value=212072 ID=1
9485 09:26:33.322853 SKU Code: 0x1
9486 09:26:33.329811 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a45c
9487 09:26:33.332993 coreboot table: 964 bytes.
9488 09:26:33.336290 IMD ROOT 0. 0xfffff000 0x00001000
9489 09:26:33.339579 IMD SMALL 1. 0xffffe000 0x00001000
9490 09:26:33.342820 RO MCACHE 2. 0xffffc000 0x00001104
9491 09:26:33.342905 CONSOLE 3. 0xfff7c000 0x00080000
9492 09:26:33.346020 FMAP 4. 0xfff7b000 0x00000452
9493 09:26:33.349792 TIME STAMP 5. 0xfff7a000 0x00000910
9494 09:26:33.352769 VBOOT WORK 6. 0xfff66000 0x00014000
9495 09:26:33.355927 RAMOOPS 7. 0xffe66000 0x00100000
9496 09:26:33.359186 COREBOOT 8. 0xffe64000 0x00002000
9497 09:26:33.362770 IMD small region:
9498 09:26:33.365899 IMD ROOT 0. 0xffffec00 0x00000400
9499 09:26:33.369247 VPD 1. 0xffffeb80 0x0000006c
9500 09:26:33.372574 MMC STATUS 2. 0xffffeb60 0x00000004
9501 09:26:33.379657 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9502 09:26:33.385930 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9503 09:26:33.424627 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9504 09:26:33.427838 Checking segment from ROM address 0x40100000
9505 09:26:33.431213 Checking segment from ROM address 0x4010001c
9506 09:26:33.437813 Loading segment from ROM address 0x40100000
9507 09:26:33.437900 code (compression=0)
9508 09:26:33.447790 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9509 09:26:33.454851 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9510 09:26:33.454961 it's not compressed!
9511 09:26:33.461127 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9512 09:26:33.464355 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9513 09:26:33.484722 Loading segment from ROM address 0x4010001c
9514 09:26:33.484808 Entry Point 0x80000000
9515 09:26:33.488570 Loaded segments
9516 09:26:33.491234 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9517 09:26:33.498334 Jumping to boot code at 0x80000000(0xffe64000)
9518 09:26:33.504923 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9519 09:26:33.511501 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9520 09:26:33.519263 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9521 09:26:33.522905 Checking segment from ROM address 0x40100000
9522 09:26:33.526053 Checking segment from ROM address 0x4010001c
9523 09:26:33.532920 Loading segment from ROM address 0x40100000
9524 09:26:33.533008 code (compression=1)
9525 09:26:33.539577 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9526 09:26:33.549388 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9527 09:26:33.549474 using LZMA
9528 09:26:33.557633 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9529 09:26:33.564602 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9530 09:26:33.567826 Loading segment from ROM address 0x4010001c
9531 09:26:33.567945 Entry Point 0x54601000
9532 09:26:33.571188 Loaded segments
9533 09:26:33.574481 NOTICE: MT8192 bl31_setup
9534 09:26:33.581207 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9535 09:26:33.584906 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9536 09:26:33.588101 WARNING: region 0:
9537 09:26:33.591509 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9538 09:26:33.591594 WARNING: region 1:
9539 09:26:33.598120 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9540 09:26:33.601552 WARNING: region 2:
9541 09:26:33.604640 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9542 09:26:33.608338 WARNING: region 3:
9543 09:26:33.611714 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9544 09:26:33.614803 WARNING: region 4:
9545 09:26:33.621345 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9546 09:26:33.621430 WARNING: region 5:
9547 09:26:33.624531 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 09:26:33.628322 WARNING: region 6:
9549 09:26:33.631413 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9550 09:26:33.631498 WARNING: region 7:
9551 09:26:33.638117 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9552 09:26:33.644528 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9553 09:26:33.648670 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9554 09:26:33.651261 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9555 09:26:33.657923 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9556 09:26:33.661522 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9557 09:26:33.664791 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9558 09:26:33.671394 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9559 09:26:33.675124 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9560 09:26:33.681480 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9561 09:26:33.684733 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9562 09:26:33.687920 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9563 09:26:33.694462 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9564 09:26:33.698221 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9565 09:26:33.701540 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9566 09:26:33.707928 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9567 09:26:33.711201 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9568 09:26:33.714711 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9569 09:26:33.721254 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9570 09:26:33.724896 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9571 09:26:33.731280 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9572 09:26:33.734516 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9573 09:26:33.737900 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9574 09:26:33.744564 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9575 09:26:33.747718 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9576 09:26:33.754678 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9577 09:26:33.757993 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9578 09:26:33.761286 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9579 09:26:33.767763 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9580 09:26:33.771323 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9581 09:26:33.777841 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9582 09:26:33.781223 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9583 09:26:33.784463 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9584 09:26:33.791020 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9585 09:26:33.794328 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9586 09:26:33.798143 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9587 09:26:33.801399 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9588 09:26:33.807838 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9589 09:26:33.811123 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9590 09:26:33.814361 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9591 09:26:33.817653 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9592 09:26:33.824368 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9593 09:26:33.828240 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9594 09:26:33.831397 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9595 09:26:33.834571 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9596 09:26:33.841354 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9597 09:26:33.844573 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9598 09:26:33.847820 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9599 09:26:33.850850 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9600 09:26:33.858208 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9601 09:26:33.861335 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9602 09:26:33.867923 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9603 09:26:33.871147 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9604 09:26:33.877595 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9605 09:26:33.880938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9606 09:26:33.884640 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9607 09:26:33.890927 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9608 09:26:33.894218 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9609 09:26:33.901441 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9610 09:26:33.904218 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9611 09:26:33.911297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9612 09:26:33.914415 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9613 09:26:33.917695 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9614 09:26:33.924245 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9615 09:26:33.927488 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9616 09:26:33.934610 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9617 09:26:33.937984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9618 09:26:33.944655 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9619 09:26:33.947722 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9620 09:26:33.951152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9621 09:26:33.957843 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9622 09:26:33.960983 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9623 09:26:33.967916 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9624 09:26:33.971217 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9625 09:26:33.977776 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9626 09:26:33.981077 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9627 09:26:33.984389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9628 09:26:33.990763 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9629 09:26:33.994099 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9630 09:26:34.001209 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9631 09:26:34.004451 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9632 09:26:34.010915 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9633 09:26:34.014217 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9634 09:26:34.020561 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9635 09:26:34.024450 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9636 09:26:34.027763 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9637 09:26:34.034316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9638 09:26:34.037509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9639 09:26:34.044457 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9640 09:26:34.047611 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9641 09:26:34.050822 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9642 09:26:34.057607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9643 09:26:34.060754 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9644 09:26:34.067555 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9645 09:26:34.070844 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9646 09:26:34.077287 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9647 09:26:34.080914 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9648 09:26:34.084200 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9649 09:26:34.090708 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9650 09:26:34.094348 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9651 09:26:34.097602 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9652 09:26:34.100661 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9653 09:26:34.107500 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9654 09:26:34.110776 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9655 09:26:34.117207 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9656 09:26:34.120970 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9657 09:26:34.124413 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9658 09:26:34.130876 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9659 09:26:34.134259 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9660 09:26:34.140856 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9661 09:26:34.144343 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9662 09:26:34.147858 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9663 09:26:34.154065 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9664 09:26:34.157668 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9665 09:26:34.164519 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9666 09:26:34.167656 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9667 09:26:34.170698 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9668 09:26:34.174503 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9669 09:26:34.180761 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9670 09:26:34.184017 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9671 09:26:34.187296 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9672 09:26:34.194390 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9673 09:26:34.197659 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9674 09:26:34.200823 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9675 09:26:34.204135 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9676 09:26:34.210634 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9677 09:26:34.214421 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9678 09:26:34.220835 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9679 09:26:34.224071 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9680 09:26:34.227685 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9681 09:26:34.233997 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9682 09:26:34.237363 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9683 09:26:34.243874 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9684 09:26:34.247769 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9685 09:26:34.250901 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9686 09:26:34.257044 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9687 09:26:34.260927 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9688 09:26:34.267274 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9689 09:26:34.270885 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9690 09:26:34.273938 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9691 09:26:34.280422 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9692 09:26:34.284189 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9693 09:26:34.287444 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9694 09:26:34.294128 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9695 09:26:34.297212 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9696 09:26:34.303837 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9697 09:26:34.307164 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9698 09:26:34.310740 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9699 09:26:34.317384 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9700 09:26:34.320584 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9701 09:26:34.327209 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9702 09:26:34.330248 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9703 09:26:34.333643 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9704 09:26:34.340262 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9705 09:26:34.343596 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9706 09:26:34.347311 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9707 09:26:34.353497 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9708 09:26:34.357280 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9709 09:26:34.363858 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9710 09:26:34.366911 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9711 09:26:34.370633 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9712 09:26:34.377231 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9713 09:26:34.380753 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9714 09:26:34.387347 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9715 09:26:34.390563 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9716 09:26:34.393952 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9717 09:26:34.400850 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9718 09:26:34.404236 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9719 09:26:34.407359 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9720 09:26:34.413832 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9721 09:26:34.417340 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9722 09:26:34.423671 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9723 09:26:34.427527 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9724 09:26:34.430295 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9725 09:26:34.437354 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9726 09:26:34.440613 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9727 09:26:34.447318 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9728 09:26:34.450370 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9729 09:26:34.453697 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9730 09:26:34.460389 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9731 09:26:34.463790 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9732 09:26:34.470562 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9733 09:26:34.473723 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9734 09:26:34.477107 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9735 09:26:34.484044 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9736 09:26:34.487187 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9737 09:26:34.490301 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9738 09:26:34.496889 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9739 09:26:34.500256 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9740 09:26:34.506654 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9741 09:26:34.510012 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9742 09:26:34.516502 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9743 09:26:34.520368 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9744 09:26:34.523529 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9745 09:26:34.530097 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9746 09:26:34.533363 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9747 09:26:34.539870 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9748 09:26:34.543207 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9749 09:26:34.546615 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9750 09:26:34.553296 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9751 09:26:34.556655 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9752 09:26:34.563186 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9753 09:26:34.566873 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9754 09:26:34.573203 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9755 09:26:34.576968 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9756 09:26:34.579953 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9757 09:26:34.586845 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9758 09:26:34.590109 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9759 09:26:34.596716 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9760 09:26:34.599960 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9761 09:26:34.603403 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9762 09:26:34.610046 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9763 09:26:34.613219 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9764 09:26:34.619824 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9765 09:26:34.623242 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9766 09:26:34.626581 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9767 09:26:34.633497 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9768 09:26:34.636838 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9769 09:26:34.643326 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9770 09:26:34.646613 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9771 09:26:34.653101 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9772 09:26:34.656934 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9773 09:26:34.659778 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9774 09:26:34.666937 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9775 09:26:34.670140 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9776 09:26:34.676673 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9777 09:26:34.679882 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9778 09:26:34.683259 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9779 09:26:34.689860 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9780 09:26:34.693113 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9781 09:26:34.696775 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9782 09:26:34.703350 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9783 09:26:34.706388 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9784 09:26:34.710094 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9785 09:26:34.713295 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9786 09:26:34.719996 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9787 09:26:34.723310 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9788 09:26:34.726510 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9789 09:26:34.732989 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9790 09:26:34.736206 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9791 09:26:34.739997 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9792 09:26:34.746577 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9793 09:26:34.749997 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9794 09:26:34.756450 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9795 09:26:34.759750 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9796 09:26:34.763022 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9797 09:26:34.770010 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9798 09:26:34.773300 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9799 09:26:34.776656 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9800 09:26:34.783340 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9801 09:26:34.786608 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9802 09:26:34.790028 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9803 09:26:34.796873 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9804 09:26:34.799955 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9805 09:26:34.803529 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9806 09:26:34.810242 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9807 09:26:34.813458 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9808 09:26:34.819773 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9809 09:26:34.823528 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9810 09:26:34.826725 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9811 09:26:34.833238 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9812 09:26:34.836468 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9813 09:26:34.840332 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9814 09:26:34.846782 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9815 09:26:34.850364 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9816 09:26:34.853199 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9817 09:26:34.860316 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9818 09:26:34.863733 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9819 09:26:34.870442 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9820 09:26:34.873545 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9821 09:26:34.876766 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9822 09:26:34.880095 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9823 09:26:34.883406 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9824 09:26:34.890241 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9825 09:26:34.893629 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9826 09:26:34.896446 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9827 09:26:34.900127 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9828 09:26:34.906237 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9829 09:26:34.910123 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9830 09:26:34.913388 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9831 09:26:34.916682 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9832 09:26:34.923234 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9833 09:26:34.926611 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9834 09:26:34.929820 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9835 09:26:34.936694 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9836 09:26:34.939558 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9837 09:26:34.946515 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9838 09:26:34.949810 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9839 09:26:34.956459 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9840 09:26:34.959821 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9841 09:26:34.963098 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9842 09:26:34.969694 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9843 09:26:34.972824 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9844 09:26:34.979888 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9845 09:26:34.983134 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9846 09:26:34.986299 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9847 09:26:34.992648 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9848 09:26:34.996250 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9849 09:26:35.002897 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9850 09:26:35.006373 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9851 09:26:35.009563 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9852 09:26:35.016193 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9853 09:26:35.019480 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9854 09:26:35.026131 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9855 09:26:35.029439 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9856 09:26:35.035940 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9857 09:26:35.039619 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9858 09:26:35.042524 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9859 09:26:35.049179 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9860 09:26:35.052670 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9861 09:26:35.059439 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9862 09:26:35.062729 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9863 09:26:35.065959 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9864 09:26:35.072442 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9865 09:26:35.076199 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9866 09:26:35.079407 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9867 09:26:35.085955 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9868 09:26:35.089371 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9869 09:26:35.095787 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9870 09:26:35.099593 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9871 09:26:35.105829 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9872 09:26:35.109544 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9873 09:26:35.112509 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9874 09:26:35.119429 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9875 09:26:35.122562 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9876 09:26:35.129199 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9877 09:26:35.132447 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9878 09:26:35.136163 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9879 09:26:35.142514 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9880 09:26:35.145803 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9881 09:26:35.149622 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9882 09:26:35.156089 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9883 09:26:35.159263 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9884 09:26:35.165894 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9885 09:26:35.169341 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9886 09:26:35.175683 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9887 09:26:35.179580 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9888 09:26:35.182742 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9889 09:26:35.189240 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9890 09:26:35.192729 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9891 09:26:35.199446 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9892 09:26:35.202631 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9893 09:26:35.205737 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9894 09:26:35.212416 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9895 09:26:35.215520 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9896 09:26:35.222295 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9897 09:26:35.226092 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9898 09:26:35.229334 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9899 09:26:35.235669 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9900 09:26:35.238911 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9901 09:26:35.246048 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9902 09:26:35.249283 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9903 09:26:35.255736 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9904 09:26:35.259095 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9905 09:26:35.262186 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9906 09:26:35.268864 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9907 09:26:35.272255 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9908 09:26:35.278994 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9909 09:26:35.282072 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9910 09:26:35.288584 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9911 09:26:35.291894 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9912 09:26:35.295739 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9913 09:26:35.302086 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9914 09:26:35.305453 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9915 09:26:35.311792 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9916 09:26:35.315590 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9917 09:26:35.322213 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9918 09:26:35.325182 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9919 09:26:35.328816 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9920 09:26:35.335112 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9921 09:26:35.338413 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9922 09:26:35.345302 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9923 09:26:35.348532 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9924 09:26:35.355380 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9925 09:26:35.358655 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9926 09:26:35.362097 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9927 09:26:35.368664 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9928 09:26:35.371932 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9929 09:26:35.378538 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9930 09:26:35.381998 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9931 09:26:35.388494 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9932 09:26:35.391763 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9933 09:26:35.394959 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9934 09:26:35.402157 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9935 09:26:35.405457 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9936 09:26:35.411867 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9937 09:26:35.414923 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9938 09:26:35.421481 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9939 09:26:35.425101 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9940 09:26:35.428148 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9941 09:26:35.435138 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9942 09:26:35.438286 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9943 09:26:35.444771 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9944 09:26:35.448719 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9945 09:26:35.455239 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9946 09:26:35.458631 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9947 09:26:35.461805 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9948 09:26:35.468331 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9949 09:26:35.472054 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9950 09:26:35.478696 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9951 09:26:35.481902 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9952 09:26:35.488659 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9953 09:26:35.491752 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9954 09:26:35.495038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9955 09:26:35.502097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9956 09:26:35.505314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9957 09:26:35.511923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9958 09:26:35.515309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9959 09:26:35.522319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9960 09:26:35.525252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9961 09:26:35.529056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9962 09:26:35.535742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9963 09:26:35.538694 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9964 09:26:35.545550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9965 09:26:35.548761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9966 09:26:35.555800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9967 09:26:35.558878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9968 09:26:35.565540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9969 09:26:35.568759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9970 09:26:35.575461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9971 09:26:35.578707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9972 09:26:35.585501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9973 09:26:35.588786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9974 09:26:35.595350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9975 09:26:35.599083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9976 09:26:35.605230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9977 09:26:35.609128 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9978 09:26:35.615735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9979 09:26:35.619070 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9980 09:26:35.625470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9981 09:26:35.629000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9982 09:26:35.635337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9983 09:26:35.638922 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9984 09:26:35.645677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9985 09:26:35.648662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9986 09:26:35.652604 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9987 09:26:35.655255 INFO: [APUAPC] vio 0
9988 09:26:35.658963 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9989 09:26:35.666020 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9990 09:26:35.669361 INFO: [APUAPC] D0_APC_0: 0x400510
9991 09:26:35.672595 INFO: [APUAPC] D0_APC_1: 0x0
9992 09:26:35.675849 INFO: [APUAPC] D0_APC_2: 0x1540
9993 09:26:35.675933 INFO: [APUAPC] D0_APC_3: 0x0
9994 09:26:35.679171 INFO: [APUAPC] D1_APC_0: 0xffffffff
9995 09:26:35.682458 INFO: [APUAPC] D1_APC_1: 0xffffffff
9996 09:26:35.685675 INFO: [APUAPC] D1_APC_2: 0x3fffff
9997 09:26:35.689106 INFO: [APUAPC] D1_APC_3: 0x0
9998 09:26:35.692363 INFO: [APUAPC] D2_APC_0: 0xffffffff
9999 09:26:35.695984 INFO: [APUAPC] D2_APC_1: 0xffffffff
10000 09:26:35.699202 INFO: [APUAPC] D2_APC_2: 0x3fffff
10001 09:26:35.702524 INFO: [APUAPC] D2_APC_3: 0x0
10002 09:26:35.705763 INFO: [APUAPC] D3_APC_0: 0xffffffff
10003 09:26:35.708958 INFO: [APUAPC] D3_APC_1: 0xffffffff
10004 09:26:35.712161 INFO: [APUAPC] D3_APC_2: 0x3fffff
10005 09:26:35.715434 INFO: [APUAPC] D3_APC_3: 0x0
10006 09:26:35.718821 INFO: [APUAPC] D4_APC_0: 0xffffffff
10007 09:26:35.722092 INFO: [APUAPC] D4_APC_1: 0xffffffff
10008 09:26:35.725403 INFO: [APUAPC] D4_APC_2: 0x3fffff
10009 09:26:35.729019 INFO: [APUAPC] D4_APC_3: 0x0
10010 09:26:35.732376 INFO: [APUAPC] D5_APC_0: 0xffffffff
10011 09:26:35.735336 INFO: [APUAPC] D5_APC_1: 0xffffffff
10012 09:26:35.738802 INFO: [APUAPC] D5_APC_2: 0x3fffff
10013 09:26:35.742403 INFO: [APUAPC] D5_APC_3: 0x0
10014 09:26:35.745560 INFO: [APUAPC] D6_APC_0: 0xffffffff
10015 09:26:35.748690 INFO: [APUAPC] D6_APC_1: 0xffffffff
10016 09:26:35.752125 INFO: [APUAPC] D6_APC_2: 0x3fffff
10017 09:26:35.755793 INFO: [APUAPC] D6_APC_3: 0x0
10018 09:26:35.758702 INFO: [APUAPC] D7_APC_0: 0xffffffff
10019 09:26:35.762394 INFO: [APUAPC] D7_APC_1: 0xffffffff
10020 09:26:35.765737 INFO: [APUAPC] D7_APC_2: 0x3fffff
10021 09:26:35.768875 INFO: [APUAPC] D7_APC_3: 0x0
10022 09:26:35.772642 INFO: [APUAPC] D8_APC_0: 0xffffffff
10023 09:26:35.775819 INFO: [APUAPC] D8_APC_1: 0xffffffff
10024 09:26:35.779152 INFO: [APUAPC] D8_APC_2: 0x3fffff
10025 09:26:35.782435 INFO: [APUAPC] D8_APC_3: 0x0
10026 09:26:35.785796 INFO: [APUAPC] D9_APC_0: 0xffffffff
10027 09:26:35.789077 INFO: [APUAPC] D9_APC_1: 0xffffffff
10028 09:26:35.792202 INFO: [APUAPC] D9_APC_2: 0x3fffff
10029 09:26:35.795531 INFO: [APUAPC] D9_APC_3: 0x0
10030 09:26:35.799387 INFO: [APUAPC] D10_APC_0: 0xffffffff
10031 09:26:35.802561 INFO: [APUAPC] D10_APC_1: 0xffffffff
10032 09:26:35.805844 INFO: [APUAPC] D10_APC_2: 0x3fffff
10033 09:26:35.809036 INFO: [APUAPC] D10_APC_3: 0x0
10034 09:26:35.812350 INFO: [APUAPC] D11_APC_0: 0xffffffff
10035 09:26:35.815637 INFO: [APUAPC] D11_APC_1: 0xffffffff
10036 09:26:35.818749 INFO: [APUAPC] D11_APC_2: 0x3fffff
10037 09:26:35.822509 INFO: [APUAPC] D11_APC_3: 0x0
10038 09:26:35.825449 INFO: [APUAPC] D12_APC_0: 0xffffffff
10039 09:26:35.829285 INFO: [APUAPC] D12_APC_1: 0xffffffff
10040 09:26:35.832507 INFO: [APUAPC] D12_APC_2: 0x3fffff
10041 09:26:35.835787 INFO: [APUAPC] D12_APC_3: 0x0
10042 09:26:35.839240 INFO: [APUAPC] D13_APC_0: 0xffffffff
10043 09:26:35.842093 INFO: [APUAPC] D13_APC_1: 0xffffffff
10044 09:26:35.845622 INFO: [APUAPC] D13_APC_2: 0x3fffff
10045 09:26:35.848979 INFO: [APUAPC] D13_APC_3: 0x0
10046 09:26:35.852061 INFO: [APUAPC] D14_APC_0: 0xffffffff
10047 09:26:35.855858 INFO: [APUAPC] D14_APC_1: 0xffffffff
10048 09:26:35.858930 INFO: [APUAPC] D14_APC_2: 0x3fffff
10049 09:26:35.862259 INFO: [APUAPC] D14_APC_3: 0x0
10050 09:26:35.865568 INFO: [APUAPC] D15_APC_0: 0xffffffff
10051 09:26:35.868850 INFO: [APUAPC] D15_APC_1: 0xffffffff
10052 09:26:35.872162 INFO: [APUAPC] D15_APC_2: 0x3fffff
10053 09:26:35.875567 INFO: [APUAPC] D15_APC_3: 0x0
10054 09:26:35.878900 INFO: [APUAPC] APC_CON: 0x4
10055 09:26:35.879577 INFO: [NOCDAPC] D0_APC_0: 0x0
10056 09:26:35.882071 INFO: [NOCDAPC] D0_APC_1: 0x0
10057 09:26:35.885345 INFO: [NOCDAPC] D1_APC_0: 0x0
10058 09:26:35.888507 INFO: [NOCDAPC] D1_APC_1: 0xfff
10059 09:26:35.891788 INFO: [NOCDAPC] D2_APC_0: 0x0
10060 09:26:35.895500 INFO: [NOCDAPC] D2_APC_1: 0xfff
10061 09:26:35.898837 INFO: [NOCDAPC] D3_APC_0: 0x0
10062 09:26:35.902053 INFO: [NOCDAPC] D3_APC_1: 0xfff
10063 09:26:35.905512 INFO: [NOCDAPC] D4_APC_0: 0x0
10064 09:26:35.908803 INFO: [NOCDAPC] D4_APC_1: 0xfff
10065 09:26:35.911948 INFO: [NOCDAPC] D5_APC_0: 0x0
10066 09:26:35.912421 INFO: [NOCDAPC] D5_APC_1: 0xfff
10067 09:26:35.915155 INFO: [NOCDAPC] D6_APC_0: 0x0
10068 09:26:35.918377 INFO: [NOCDAPC] D6_APC_1: 0xfff
10069 09:26:35.922323 INFO: [NOCDAPC] D7_APC_0: 0x0
10070 09:26:35.925555 INFO: [NOCDAPC] D7_APC_1: 0xfff
10071 09:26:35.928833 INFO: [NOCDAPC] D8_APC_0: 0x0
10072 09:26:35.932122 INFO: [NOCDAPC] D8_APC_1: 0xfff
10073 09:26:35.935181 INFO: [NOCDAPC] D9_APC_0: 0x0
10074 09:26:35.938607 INFO: [NOCDAPC] D9_APC_1: 0xfff
10075 09:26:35.942118 INFO: [NOCDAPC] D10_APC_0: 0x0
10076 09:26:35.945243 INFO: [NOCDAPC] D10_APC_1: 0xfff
10077 09:26:35.945690 INFO: [NOCDAPC] D11_APC_0: 0x0
10078 09:26:35.948214 INFO: [NOCDAPC] D11_APC_1: 0xfff
10079 09:26:35.951730 INFO: [NOCDAPC] D12_APC_0: 0x0
10080 09:26:35.955325 INFO: [NOCDAPC] D12_APC_1: 0xfff
10081 09:26:35.958760 INFO: [NOCDAPC] D13_APC_0: 0x0
10082 09:26:35.961584 INFO: [NOCDAPC] D13_APC_1: 0xfff
10083 09:26:35.964970 INFO: [NOCDAPC] D14_APC_0: 0x0
10084 09:26:35.968092 INFO: [NOCDAPC] D14_APC_1: 0xfff
10085 09:26:35.971435 INFO: [NOCDAPC] D15_APC_0: 0x0
10086 09:26:35.975267 INFO: [NOCDAPC] D15_APC_1: 0xfff
10087 09:26:35.978659 INFO: [NOCDAPC] APC_CON: 0x4
10088 09:26:35.981835 INFO: [APUAPC] set_apusys_apc done
10089 09:26:35.985136 INFO: [DEVAPC] devapc_init done
10090 09:26:35.988330 INFO: GICv3 without legacy support detected.
10091 09:26:35.991581 INFO: ARM GICv3 driver initialized in EL3
10092 09:26:35.994780 INFO: Maximum SPI INTID supported: 639
10093 09:26:36.001878 INFO: BL31: Initializing runtime services
10094 09:26:36.005137 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10095 09:26:36.008466 INFO: SPM: enable CPC mode
10096 09:26:36.014908 INFO: mcdi ready for mcusys-off-idle and system suspend
10097 09:26:36.018134 INFO: BL31: Preparing for EL3 exit to normal world
10098 09:26:36.021481 INFO: Entry point address = 0x80000000
10099 09:26:36.024672 INFO: SPSR = 0x8
10100 09:26:36.029567
10101 09:26:36.030017
10102 09:26:36.030355
10103 09:26:36.033407 Starting depthcharge on Spherion...
10104 09:26:36.033834
10105 09:26:36.034170 Wipe memory regions:
10106 09:26:36.034485
10107 09:26:36.036723 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10108 09:26:36.037228 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10109 09:26:36.037774 Setting prompt string to ['asurada:']
10110 09:26:36.038318 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10111 09:26:36.038978 [0x00000040000000, 0x00000054600000)
10112 09:26:36.158887
10113 09:26:36.159403 [0x00000054660000, 0x00000080000000)
10114 09:26:36.419182
10115 09:26:36.419675 [0x000000821a7280, 0x000000ffe64000)
10116 09:26:37.163821
10117 09:26:37.163988 [0x00000100000000, 0x00000240000000)
10118 09:26:39.053945
10119 09:26:39.057260 Initializing XHCI USB controller at 0x11200000.
10120 09:26:40.095577
10121 09:26:40.098771 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10122 09:26:40.098861
10123 09:26:40.098927
10124 09:26:40.099214 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10126 09:26:40.199536 asurada: tftpboot 192.168.201.1 14407618/tftp-deploy-hb8xxyhl/kernel/image.itb 14407618/tftp-deploy-hb8xxyhl/kernel/cmdline
10127 09:26:40.199668 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10128 09:26:40.199751 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10129 09:26:40.203665 tftpboot 192.168.201.1 14407618/tftp-deploy-hb8xxyhl/kernel/image.itp-deploy-hb8xxyhl/kernel/cmdline
10130 09:26:40.203750
10131 09:26:40.203816 Waiting for link
10132 09:26:40.362319
10133 09:26:40.362815 R8152: Initializing
10134 09:26:40.363260
10135 09:26:40.365604 Version 9 (ocp_data = 6010)
10136 09:26:40.366135
10137 09:26:40.368921 R8152: Done initializing
10138 09:26:40.369388
10139 09:26:40.369755 Adding net device
10140 09:26:42.316995
10141 09:26:42.317233 done.
10142 09:26:42.317384
10143 09:26:42.317523 MAC: 00:e0:4c:72:2d:d6
10144 09:26:42.317655
10145 09:26:42.319670 Sending DHCP discover... done.
10146 09:26:42.319853
10147 09:26:46.283330 Waiting for reply... done.
10148 09:26:46.283899
10149 09:26:46.284269 Sending DHCP request... done.
10150 09:26:46.284640
10151 09:26:46.292729 Waiting for reply... done.
10152 09:26:46.293280
10153 09:26:46.293643 My ip is 192.168.201.21
10154 09:26:46.294045
10155 09:26:46.295795 The DHCP server ip is 192.168.201.1
10156 09:26:46.296356
10157 09:26:46.302376 TFTP server IP predefined by user: 192.168.201.1
10158 09:26:46.302938
10159 09:26:46.308994 Bootfile predefined by user: 14407618/tftp-deploy-hb8xxyhl/kernel/image.itb
10160 09:26:46.309572
10161 09:26:46.311930 Sending tftp read request... done.
10162 09:26:46.312395
10163 09:26:46.316755 Waiting for the transfer...
10164 09:26:46.317341
10165 09:26:46.612990 00000000 ################################################################
10166 09:26:46.613130
10167 09:26:46.879052 00080000 ################################################################
10168 09:26:46.879186
10169 09:26:47.148722 00100000 ################################################################
10170 09:26:47.148868
10171 09:26:47.414179 00180000 ################################################################
10172 09:26:47.414319
10173 09:26:47.674335 00200000 ################################################################
10174 09:26:47.674476
10175 09:26:47.934482 00280000 ################################################################
10176 09:26:47.934618
10177 09:26:48.185449 00300000 ################################################################
10178 09:26:48.185590
10179 09:26:48.462187 00380000 ################################################################
10180 09:26:48.462334
10181 09:26:48.728293 00400000 ################################################################
10182 09:26:48.728435
10183 09:26:48.992962 00480000 ################################################################
10184 09:26:48.993102
10185 09:26:49.253208 00500000 ################################################################
10186 09:26:49.253359
10187 09:26:49.505425 00580000 ################################################################
10188 09:26:49.505567
10189 09:26:49.755183 00600000 ################################################################
10190 09:26:49.755342
10191 09:26:50.010049 00680000 ################################################################
10192 09:26:50.010189
10193 09:26:50.261307 00700000 ################################################################
10194 09:26:50.261444
10195 09:26:50.518670 00780000 ################################################################
10196 09:26:50.518837
10197 09:26:50.767347 00800000 ################################################################
10198 09:26:50.767508
10199 09:26:51.031975 00880000 ################################################################
10200 09:26:51.032122
10201 09:26:51.304860 00900000 ################################################################
10202 09:26:51.305004
10203 09:26:51.565419 00980000 ################################################################
10204 09:26:51.565602
10205 09:26:51.816482 00a00000 ################################################################
10206 09:26:51.816666
10207 09:26:52.070328 00a80000 ################################################################
10208 09:26:52.070492
10209 09:26:52.342994 00b00000 ################################################################
10210 09:26:52.343160
10211 09:26:52.595201 00b80000 ################################################################
10212 09:26:52.595393
10213 09:26:52.857827 00c00000 ################################################################
10214 09:26:52.857979
10215 09:26:53.113579 00c80000 ################################################################
10216 09:26:53.113726
10217 09:26:53.875562 00d00000 ################################################################
10218 09:26:53.876108
10219 09:26:53.876622 00d80000 ################################################################
10220 09:26:53.877291
10221 09:26:53.939847 00e00000 ################################################################
10222 09:26:53.940033
10223 09:26:54.236465 00e80000 ################################################################
10224 09:26:54.236614
10225 09:26:54.524288 00f00000 ################################################################
10226 09:26:54.524426
10227 09:26:54.795117 00f80000 ################################################################
10228 09:26:54.795269
10229 09:26:55.082537 01000000 ################################################################
10230 09:26:55.082710
10231 09:26:55.350607 01080000 ################################################################
10232 09:26:55.350755
10233 09:26:55.603919 01100000 ################################################################
10234 09:26:55.604085
10235 09:26:55.850642 01180000 ################################################################
10236 09:26:55.850842
10237 09:26:56.123629 01200000 ################################################################
10238 09:26:56.123776
10239 09:26:56.373076 01280000 ################################################################
10240 09:26:56.373228
10241 09:26:56.620695 01300000 ################################################################
10242 09:26:56.620864
10243 09:26:56.870179 01380000 ################################################################
10244 09:26:56.870339
10245 09:26:57.114241 01400000 ################################################################
10246 09:26:57.114420
10247 09:26:57.352391 01480000 ################################################################
10248 09:26:57.352578
10249 09:26:57.598189 01500000 ################################################################
10250 09:26:57.598330
10251 09:26:57.841205 01580000 ################################################################
10252 09:26:57.841357
10253 09:26:58.078116 01600000 ################################################################
10254 09:26:58.078274
10255 09:26:58.319832 01680000 ################################################################
10256 09:26:58.319977
10257 09:26:58.585482 01700000 ################################################################
10258 09:26:58.585640
10259 09:26:58.829537 01780000 ################################################################
10260 09:26:58.829699
10261 09:26:59.075466 01800000 ################################################################
10262 09:26:59.075653
10263 09:26:59.387495 01880000 ################################################################
10264 09:26:59.388228
10265 09:26:59.686152 01900000 ################################################################
10266 09:26:59.686425
10267 09:26:59.974488 01980000 ################################################################
10268 09:26:59.974629
10269 09:27:00.267320 01a00000 ################################################################
10270 09:27:00.267472
10271 09:27:00.562518 01a80000 ################################################################
10272 09:27:00.562661
10273 09:27:00.845954 01b00000 ################################################################
10274 09:27:00.846099
10275 09:27:01.136536 01b80000 ################################################################
10276 09:27:01.136691
10277 09:27:01.416423 01c00000 ################################################################
10278 09:27:01.416587
10279 09:27:01.670324 01c80000 ################################################################
10280 09:27:01.670477
10281 09:27:01.949924 01d00000 ################################################################
10282 09:27:01.950070
10283 09:27:02.234965 01d80000 ################################################################
10284 09:27:02.235120
10285 09:27:02.476768 01e00000 ########################################################## done.
10286 09:27:02.476919
10287 09:27:02.479722 The bootfile was 31925130 bytes long.
10288 09:27:02.479814
10289 09:27:02.483344 Sending tftp read request... done.
10290 09:27:02.483531
10291 09:27:02.486617 Waiting for the transfer...
10292 09:27:02.486774
10293 09:27:02.486858 00000000 # done.
10294 09:27:02.486935
10295 09:27:02.493232 Command line loaded dynamically from TFTP file: 14407618/tftp-deploy-hb8xxyhl/kernel/cmdline
10296 09:27:02.493418
10297 09:27:02.516257 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407618/extract-nfsrootfs-voawszzn,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10298 09:27:02.516518
10299 09:27:02.519214 Loading FIT.
10300 09:27:02.519298
10301 09:27:02.519400 Image ramdisk-1 has 18749110 bytes.
10302 09:27:02.522696
10303 09:27:02.522780 Image fdt-1 has 47258 bytes.
10304 09:27:02.522847
10305 09:27:02.526259 Image kernel-1 has 13126726 bytes.
10306 09:27:02.526730
10307 09:27:02.536065 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10308 09:27:02.536541
10309 09:27:02.552666 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10310 09:27:02.553167
10311 09:27:02.559582 Choosing best match conf-1 for compat google,spherion-rev2.
10312 09:27:02.563069
10313 09:27:02.567931 Connected to device vid:did:rid of 1ae0:0028:00
10314 09:27:02.576294
10315 09:27:02.579146 tpm_get_response: command 0x17b, return code 0x0
10316 09:27:02.579786
10317 09:27:02.582726 ec_init: CrosEC protocol v3 supported (256, 248)
10318 09:27:02.587215
10319 09:27:02.590772 tpm_cleanup: add release locality here.
10320 09:27:02.591351
10321 09:27:02.591723 Shutting down all USB controllers.
10322 09:27:02.593796
10323 09:27:02.594262 Removing current net device
10324 09:27:02.594637
10325 09:27:02.600632 Exiting depthcharge with code 4 at timestamp: 55894640
10326 09:27:02.601212
10327 09:27:02.603847 LZMA decompressing kernel-1 to 0x821a6718
10328 09:27:02.604416
10329 09:27:02.606846 LZMA decompressing kernel-1 to 0x40000000
10330 09:27:04.224782
10331 09:27:04.225351 jumping to kernel
10332 09:27:04.227186 end: 2.2.4 bootloader-commands (duration 00:00:28) [common]
10333 09:27:04.227805 start: 2.2.5 auto-login-action (timeout 00:03:59) [common]
10334 09:27:04.228232 Setting prompt string to ['Linux version [0-9]']
10335 09:27:04.228625 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10336 09:27:04.228991 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10337 09:27:04.308208
10338 09:27:04.311626 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10339 09:27:04.315202 start: 2.2.5.1 login-action (timeout 00:03:59) [common]
10340 09:27:04.315501 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10341 09:27:04.315682 Setting prompt string to []
10342 09:27:04.315866 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10343 09:27:04.316045 Using line separator: #'\n'#
10344 09:27:04.316191 No login prompt set.
10345 09:27:04.316340 Parsing kernel messages
10346 09:27:04.316478 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10347 09:27:04.316756 [login-action] Waiting for messages, (timeout 00:03:59)
10348 09:27:04.316919 Waiting using forced prompt support (timeout 00:01:59)
10349 09:27:04.334962 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
10350 09:27:04.338044 [ 0.000000] random: crng init done
10351 09:27:04.344935 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10352 09:27:04.348260 [ 0.000000] efi: UEFI not found.
10353 09:27:04.354449 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10354 09:27:04.361105 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10355 09:27:04.371028 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10356 09:27:04.380784 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10357 09:27:04.387849 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10358 09:27:04.394148 [ 0.000000] printk: bootconsole [mtk8250] enabled
10359 09:27:04.400902 [ 0.000000] NUMA: No NUMA configuration found
10360 09:27:04.408095 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10361 09:27:04.411130 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10362 09:27:04.413941 [ 0.000000] Zone ranges:
10363 09:27:04.420991 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10364 09:27:04.424415 [ 0.000000] DMA32 empty
10365 09:27:04.430996 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10366 09:27:04.434718 [ 0.000000] Movable zone start for each node
10367 09:27:04.437633 [ 0.000000] Early memory node ranges
10368 09:27:04.443879 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10369 09:27:04.451021 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10370 09:27:04.456898 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10371 09:27:04.463822 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10372 09:27:04.467185 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10373 09:27:04.476644 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10374 09:27:04.532791 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10375 09:27:04.539828 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10376 09:27:04.546047 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10377 09:27:04.549344 [ 0.000000] psci: probing for conduit method from DT.
10378 09:27:04.556182 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10379 09:27:04.559602 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10380 09:27:04.565847 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10381 09:27:04.569053 [ 0.000000] psci: SMC Calling Convention v1.2
10382 09:27:04.575845 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10383 09:27:04.578898 [ 0.000000] Detected VIPT I-cache on CPU0
10384 09:27:04.585372 [ 0.000000] CPU features: detected: GIC system register CPU interface
10385 09:27:04.592461 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10386 09:27:04.599199 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10387 09:27:04.605676 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10388 09:27:04.615579 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10389 09:27:04.621862 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10390 09:27:04.625253 [ 0.000000] alternatives: applying boot alternatives
10391 09:27:04.631969 [ 0.000000] Fallback order for Node 0: 0
10392 09:27:04.638288 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10393 09:27:04.641893 [ 0.000000] Policy zone: Normal
10394 09:27:04.664819 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407618/extract-nfsrootfs-voawszzn,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10395 09:27:04.674469 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10396 09:27:04.685878 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10397 09:27:04.695830 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10398 09:27:04.702447 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10399 09:27:04.705657 <6>[ 0.000000] software IO TLB: area num 8.
10400 09:27:04.762106 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10401 09:27:04.911571 <6>[ 0.000000] Memory: 7945752K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407016K reserved, 32768K cma-reserved)
10402 09:27:04.917964 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10403 09:27:04.924798 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10404 09:27:04.928058 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10405 09:27:04.935095 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10406 09:27:04.941467 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10407 09:27:04.944837 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10408 09:27:04.954172 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10409 09:27:04.961243 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10410 09:27:04.967712 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10411 09:27:04.974480 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10412 09:27:04.977788 <6>[ 0.000000] GICv3: 608 SPIs implemented
10413 09:27:04.981319 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10414 09:27:04.987681 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10415 09:27:04.990936 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10416 09:27:04.997884 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10417 09:27:05.010623 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10418 09:27:05.023606 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10419 09:27:05.030068 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10420 09:27:05.038111 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10421 09:27:05.051078 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10422 09:27:05.057941 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10423 09:27:05.064314 <6>[ 0.009230] Console: colour dummy device 80x25
10424 09:27:05.073951 <6>[ 0.013958] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10425 09:27:05.081117 <6>[ 0.024400] pid_max: default: 32768 minimum: 301
10426 09:27:05.084334 <6>[ 0.029271] LSM: Security Framework initializing
10427 09:27:05.090974 <6>[ 0.034211] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10428 09:27:05.100739 <6>[ 0.042074] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10429 09:27:05.110802 <6>[ 0.051491] cblist_init_generic: Setting adjustable number of callback queues.
10430 09:27:05.114062 <6>[ 0.058980] cblist_init_generic: Setting shift to 3 and lim to 1.
10431 09:27:05.123690 <6>[ 0.065319] cblist_init_generic: Setting adjustable number of callback queues.
10432 09:27:05.130238 <6>[ 0.072746] cblist_init_generic: Setting shift to 3 and lim to 1.
10433 09:27:05.133690 <6>[ 0.079147] rcu: Hierarchical SRCU implementation.
10434 09:27:05.140362 <6>[ 0.084163] rcu: Max phase no-delay instances is 1000.
10435 09:27:05.146961 <6>[ 0.091196] EFI services will not be available.
10436 09:27:05.150170 <6>[ 0.096152] smp: Bringing up secondary CPUs ...
10437 09:27:05.158797 <6>[ 0.101203] Detected VIPT I-cache on CPU1
10438 09:27:05.165628 <6>[ 0.101275] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10439 09:27:05.172182 <6>[ 0.101305] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10440 09:27:05.175341 <6>[ 0.101642] Detected VIPT I-cache on CPU2
10441 09:27:05.181610 <6>[ 0.101693] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10442 09:27:05.191666 <6>[ 0.101709] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10443 09:27:05.195009 <6>[ 0.101967] Detected VIPT I-cache on CPU3
10444 09:27:05.201963 <6>[ 0.102013] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10445 09:27:05.208035 <6>[ 0.102027] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10446 09:27:05.211885 <6>[ 0.102332] CPU features: detected: Spectre-v4
10447 09:27:05.218372 <6>[ 0.102338] CPU features: detected: Spectre-BHB
10448 09:27:05.221847 <6>[ 0.102343] Detected PIPT I-cache on CPU4
10449 09:27:05.228297 <6>[ 0.102400] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10450 09:27:05.235130 <6>[ 0.102416] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10451 09:27:05.241553 <6>[ 0.102709] Detected PIPT I-cache on CPU5
10452 09:27:05.248312 <6>[ 0.102772] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10453 09:27:05.254777 <6>[ 0.102789] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10454 09:27:05.257947 <6>[ 0.103073] Detected PIPT I-cache on CPU6
10455 09:27:05.264912 <6>[ 0.103138] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10456 09:27:05.271531 <6>[ 0.103154] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10457 09:27:05.277927 <6>[ 0.103450] Detected PIPT I-cache on CPU7
10458 09:27:05.284414 <6>[ 0.103516] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10459 09:27:05.290952 <6>[ 0.103531] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10460 09:27:05.294176 <6>[ 0.103579] smp: Brought up 1 node, 8 CPUs
10461 09:27:05.300983 <6>[ 0.244974] SMP: Total of 8 processors activated.
10462 09:27:05.304299 <6>[ 0.249926] CPU features: detected: 32-bit EL0 Support
10463 09:27:05.314144 <6>[ 0.255322] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10464 09:27:05.320602 <6>[ 0.264177] CPU features: detected: Common not Private translations
10465 09:27:05.327137 <6>[ 0.270653] CPU features: detected: CRC32 instructions
10466 09:27:05.330945 <6>[ 0.276005] CPU features: detected: RCpc load-acquire (LDAPR)
10467 09:27:05.336971 <6>[ 0.281965] CPU features: detected: LSE atomic instructions
10468 09:27:05.344340 <6>[ 0.287746] CPU features: detected: Privileged Access Never
10469 09:27:05.350298 <6>[ 0.293526] CPU features: detected: RAS Extension Support
10470 09:27:05.356867 <6>[ 0.299169] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10471 09:27:05.360148 <6>[ 0.306389] CPU: All CPU(s) started at EL2
10472 09:27:05.367122 <6>[ 0.310706] alternatives: applying system-wide alternatives
10473 09:27:05.377062 <6>[ 0.321559] devtmpfs: initialized
10474 09:27:05.392926 <6>[ 0.330488] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10475 09:27:05.399400 <6>[ 0.340451] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10476 09:27:05.405799 <6>[ 0.348465] pinctrl core: initialized pinctrl subsystem
10477 09:27:05.408941 <6>[ 0.355159] DMI not present or invalid.
10478 09:27:05.415289 <6>[ 0.359570] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10479 09:27:05.425344 <6>[ 0.366392] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10480 09:27:05.431897 <6>[ 0.373979] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10481 09:27:05.441921 <6>[ 0.382194] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10482 09:27:05.445199 <6>[ 0.390436] audit: initializing netlink subsys (disabled)
10483 09:27:05.455395 <5>[ 0.396130] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10484 09:27:05.461935 <6>[ 0.396853] thermal_sys: Registered thermal governor 'step_wise'
10485 09:27:05.468929 <6>[ 0.404094] thermal_sys: Registered thermal governor 'power_allocator'
10486 09:27:05.472183 <6>[ 0.410348] cpuidle: using governor menu
10487 09:27:05.478266 <6>[ 0.421306] NET: Registered PF_QIPCRTR protocol family
10488 09:27:05.485282 <6>[ 0.426795] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10489 09:27:05.488605 <6>[ 0.433900] ASID allocator initialised with 32768 entries
10490 09:27:05.496098 <6>[ 0.440486] Serial: AMBA PL011 UART driver
10491 09:27:05.504959 <4>[ 0.449327] Trying to register duplicate clock ID: 134
10492 09:27:05.564437 <6>[ 0.512528] KASLR enabled
10493 09:27:05.578716 <6>[ 0.520213] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10494 09:27:05.585586 <6>[ 0.527229] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10495 09:27:05.592138 <6>[ 0.533716] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10496 09:27:05.598679 <6>[ 0.540721] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10497 09:27:05.605199 <6>[ 0.547207] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10498 09:27:05.611969 <6>[ 0.554213] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10499 09:27:05.618377 <6>[ 0.560698] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10500 09:27:05.624893 <6>[ 0.567701] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10501 09:27:05.628260 <6>[ 0.575169] ACPI: Interpreter disabled.
10502 09:27:05.637120 <6>[ 0.581597] iommu: Default domain type: Translated
10503 09:27:05.643689 <6>[ 0.586743] iommu: DMA domain TLB invalidation policy: strict mode
10504 09:27:05.647314 <5>[ 0.593406] SCSI subsystem initialized
10505 09:27:05.653775 <6>[ 0.597652] usbcore: registered new interface driver usbfs
10506 09:27:05.660260 <6>[ 0.603385] usbcore: registered new interface driver hub
10507 09:27:05.663569 <6>[ 0.608934] usbcore: registered new device driver usb
10508 09:27:05.670507 <6>[ 0.615055] pps_core: LinuxPPS API ver. 1 registered
10509 09:27:05.680338 <6>[ 0.620250] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10510 09:27:05.683588 <6>[ 0.629594] PTP clock support registered
10511 09:27:05.686914 <6>[ 0.633832] EDAC MC: Ver: 3.0.0
10512 09:27:05.694421 <6>[ 0.639030] FPGA manager framework
10513 09:27:05.700770 <6>[ 0.642707] Advanced Linux Sound Architecture Driver Initialized.
10514 09:27:05.703896 <6>[ 0.649488] vgaarb: loaded
10515 09:27:05.710736 <6>[ 0.652642] clocksource: Switched to clocksource arch_sys_counter
10516 09:27:05.713812 <5>[ 0.659089] VFS: Disk quotas dquot_6.6.0
10517 09:27:05.720707 <6>[ 0.663273] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10518 09:27:05.723882 <6>[ 0.670467] pnp: PnP ACPI: disabled
10519 09:27:05.732426 <6>[ 0.677208] NET: Registered PF_INET protocol family
10520 09:27:05.739244 <6>[ 0.682802] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10521 09:27:05.753908 <6>[ 0.695122] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10522 09:27:05.764331 <6>[ 0.703936] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10523 09:27:05.770564 <6>[ 0.711906] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10524 09:27:05.777347 <6>[ 0.720609] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10525 09:27:05.789261 <6>[ 0.730361] TCP: Hash tables configured (established 65536 bind 65536)
10526 09:27:05.795484 <6>[ 0.737232] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10527 09:27:05.802329 <6>[ 0.744430] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10528 09:27:05.808878 <6>[ 0.752136] NET: Registered PF_UNIX/PF_LOCAL protocol family
10529 09:27:05.814987 <6>[ 0.758283] RPC: Registered named UNIX socket transport module.
10530 09:27:05.818657 <6>[ 0.764439] RPC: Registered udp transport module.
10531 09:27:05.825237 <6>[ 0.769371] RPC: Registered tcp transport module.
10532 09:27:05.831950 <6>[ 0.774304] RPC: Registered tcp NFSv4.1 backchannel transport module.
10533 09:27:05.835127 <6>[ 0.780969] PCI: CLS 0 bytes, default 64
10534 09:27:05.838311 <6>[ 0.785329] Unpacking initramfs...
10535 09:27:05.847850 <6>[ 0.789048] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10536 09:27:05.854821 <6>[ 0.797668] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10537 09:27:05.861880 <6>[ 0.806468] kvm [1]: IPA Size Limit: 40 bits
10538 09:27:05.865007 <6>[ 0.811000] kvm [1]: GICv3: no GICV resource entry
10539 09:27:05.871629 <6>[ 0.816021] kvm [1]: disabling GICv2 emulation
10540 09:27:05.878455 <6>[ 0.820710] kvm [1]: GIC system register CPU interface enabled
10541 09:27:05.881429 <6>[ 0.826867] kvm [1]: vgic interrupt IRQ18
10542 09:27:05.888773 <6>[ 0.832694] kvm [1]: VHE mode initialized successfully
10543 09:27:05.895344 <5>[ 0.839110] Initialise system trusted keyrings
10544 09:27:05.901589 <6>[ 0.843900] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10545 09:27:05.909335 <6>[ 0.853883] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10546 09:27:05.916081 <5>[ 0.860280] NFS: Registering the id_resolver key type
10547 09:27:05.918926 <5>[ 0.865580] Key type id_resolver registered
10548 09:27:05.925788 <5>[ 0.869994] Key type id_legacy registered
10549 09:27:05.932243 <6>[ 0.874272] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10550 09:27:05.938994 <6>[ 0.881196] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10551 09:27:05.945172 <6>[ 0.888900] 9p: Installing v9fs 9p2000 file system support
10552 09:27:05.982349 <5>[ 0.927217] Key type asymmetric registered
10553 09:27:05.986075 <5>[ 0.931547] Asymmetric key parser 'x509' registered
10554 09:27:05.996090 <6>[ 0.936681] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10555 09:27:05.998891 <6>[ 0.944298] io scheduler mq-deadline registered
10556 09:27:06.002488 <6>[ 0.949060] io scheduler kyber registered
10557 09:27:06.021199 <6>[ 0.966098] EINJ: ACPI disabled.
10558 09:27:06.053967 <4>[ 0.992158] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10559 09:27:06.064191 <4>[ 1.002768] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10560 09:27:06.078724 <6>[ 1.023773] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10561 09:27:06.086831 <6>[ 1.031759] printk: console [ttyS0] disabled
10562 09:27:06.114678 <6>[ 1.056391] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10563 09:27:06.121186 <6>[ 1.065861] printk: console [ttyS0] enabled
10564 09:27:06.125075 <6>[ 1.065861] printk: console [ttyS0] enabled
10565 09:27:06.131542 <6>[ 1.074755] printk: bootconsole [mtk8250] disabled
10566 09:27:06.134886 <6>[ 1.074755] printk: bootconsole [mtk8250] disabled
10567 09:27:06.141438 <6>[ 1.085788] SuperH (H)SCI(F) driver initialized
10568 09:27:06.144524 <6>[ 1.091078] msm_serial: driver initialized
10569 09:27:06.158681 <6>[ 1.099998] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10570 09:27:06.168799 <6>[ 1.108546] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10571 09:27:06.175405 <6>[ 1.117088] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10572 09:27:06.185537 <6>[ 1.125715] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10573 09:27:06.191757 <6>[ 1.134421] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10574 09:27:06.201450 <6>[ 1.143135] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10575 09:27:06.211776 <6>[ 1.151677] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10576 09:27:06.218262 <6>[ 1.160473] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10577 09:27:06.227736 <6>[ 1.169016] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10578 09:27:06.239824 <6>[ 1.185106] loop: module loaded
10579 09:27:06.246802 <6>[ 1.191051] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10580 09:27:06.269720 <4>[ 1.214475] mtk-pmic-keys: Failed to locate of_node [id: -1]
10581 09:27:06.276473 <6>[ 1.221268] megasas: 07.719.03.00-rc1
10582 09:27:06.286032 <6>[ 1.230914] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10583 09:27:06.299797 <6>[ 1.244016] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10584 09:27:06.315756 <6>[ 1.259897] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10585 09:27:06.370821 <6>[ 1.309345] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10586 09:27:06.626847 <6>[ 1.572021] Freeing initrd memory: 18304K
10587 09:27:06.638563 <6>[ 1.583505] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10588 09:27:06.649363 <6>[ 1.594371] tun: Universal TUN/TAP device driver, 1.6
10589 09:27:06.653062 <6>[ 1.600432] thunder_xcv, ver 1.0
10590 09:27:06.656358 <6>[ 1.603935] thunder_bgx, ver 1.0
10591 09:27:06.659716 <6>[ 1.607434] nicpf, ver 1.0
10592 09:27:06.669851 <6>[ 1.611458] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10593 09:27:06.673484 <6>[ 1.618935] hns3: Copyright (c) 2017 Huawei Corporation.
10594 09:27:06.676755 <6>[ 1.624524] hclge is initializing
10595 09:27:06.683434 <6>[ 1.628103] e1000: Intel(R) PRO/1000 Network Driver
10596 09:27:06.690061 <6>[ 1.633233] e1000: Copyright (c) 1999-2006 Intel Corporation.
10597 09:27:06.693255 <6>[ 1.639247] e1000e: Intel(R) PRO/1000 Network Driver
10598 09:27:06.700211 <6>[ 1.644463] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10599 09:27:06.706684 <6>[ 1.650651] igb: Intel(R) Gigabit Ethernet Network Driver
10600 09:27:06.713606 <6>[ 1.656302] igb: Copyright (c) 2007-2014 Intel Corporation.
10601 09:27:06.719824 <6>[ 1.662140] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10602 09:27:06.726309 <6>[ 1.668659] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10603 09:27:06.729648 <6>[ 1.675119] sky2: driver version 1.30
10604 09:27:06.736202 <6>[ 1.680053] usbcore: registered new device driver r8152-cfgselector
10605 09:27:06.743262 <6>[ 1.686589] usbcore: registered new interface driver r8152
10606 09:27:06.746373 <6>[ 1.692403] VFIO - User Level meta-driver version: 0.3
10607 09:27:06.755754 <6>[ 1.700644] usbcore: registered new interface driver usb-storage
10608 09:27:06.762165 <6>[ 1.707082] usbcore: registered new device driver onboard-usb-hub
10609 09:27:06.771056 <6>[ 1.716197] mt6397-rtc mt6359-rtc: registered as rtc0
10610 09:27:06.781156 <6>[ 1.721663] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-18T09:25:41 UTC (1718702741)
10611 09:27:06.784370 <6>[ 1.731228] i2c_dev: i2c /dev entries driver
10612 09:27:06.798281 <4>[ 1.743173] cpu cpu0: supply cpu not found, using dummy regulator
10613 09:27:06.804845 <4>[ 1.749597] cpu cpu1: supply cpu not found, using dummy regulator
10614 09:27:06.811568 <4>[ 1.756009] cpu cpu2: supply cpu not found, using dummy regulator
10615 09:27:06.818569 <4>[ 1.762408] cpu cpu3: supply cpu not found, using dummy regulator
10616 09:27:06.824813 <4>[ 1.768830] cpu cpu4: supply cpu not found, using dummy regulator
10617 09:27:06.832426 <4>[ 1.775228] cpu cpu5: supply cpu not found, using dummy regulator
10618 09:27:06.838666 <4>[ 1.781624] cpu cpu6: supply cpu not found, using dummy regulator
10619 09:27:06.845199 <4>[ 1.788023] cpu cpu7: supply cpu not found, using dummy regulator
10620 09:27:06.863852 <6>[ 1.808680] cpu cpu0: EM: created perf domain
10621 09:27:06.867038 <6>[ 1.813616] cpu cpu4: EM: created perf domain
10622 09:27:06.874526 <6>[ 1.819207] sdhci: Secure Digital Host Controller Interface driver
10623 09:27:06.881130 <6>[ 1.825637] sdhci: Copyright(c) Pierre Ossman
10624 09:27:06.887639 <6>[ 1.830596] Synopsys Designware Multimedia Card Interface Driver
10625 09:27:06.893896 <6>[ 1.837245] sdhci-pltfm: SDHCI platform and OF driver helper
10626 09:27:06.897688 <6>[ 1.837447] mmc0: CQHCI version 5.10
10627 09:27:06.904346 <6>[ 1.847519] ledtrig-cpu: registered to indicate activity on CPUs
10628 09:27:06.911050 <6>[ 1.854597] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10629 09:27:06.917853 <6>[ 1.861651] usbcore: registered new interface driver usbhid
10630 09:27:06.920889 <6>[ 1.867473] usbhid: USB HID core driver
10631 09:27:06.927741 <6>[ 1.871667] spi_master spi0: will run message pump with realtime priority
10632 09:27:06.973018 <6>[ 1.910438] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10633 09:27:06.990516 <6>[ 1.925524] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10634 09:27:06.993954 <6>[ 1.939035] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15814
10635 09:27:07.001798 <6>[ 1.946328] cros-ec-spi spi0.0: Chrome EC device registered
10636 09:27:07.008312 <6>[ 1.952354] mmc0: Command Queue Engine enabled
10637 09:27:07.014799 <6>[ 1.957108] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10638 09:27:07.017982 <6>[ 1.964713] mmcblk0: mmc0:0001 DA4128 116 GiB
10639 09:27:07.028934 <6>[ 1.974234] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10640 09:27:07.037167 <6>[ 1.981926] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10641 09:27:07.046951 <6>[ 1.987363] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10642 09:27:07.053849 <6>[ 1.987944] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10643 09:27:07.056964 <6>[ 1.997931] NET: Registered PF_PACKET protocol family
10644 09:27:07.063570 <6>[ 2.002592] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10645 09:27:07.066792 <6>[ 2.007320] 9pnet: Installing 9P2000 support
10646 09:27:07.073389 <5>[ 2.018313] Key type dns_resolver registered
10647 09:27:07.076851 <6>[ 2.023391] registered taskstats version 1
10648 09:27:07.083175 <5>[ 2.027773] Loading compiled-in X.509 certificates
10649 09:27:07.112991 <4>[ 2.051231] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10650 09:27:07.122793 <4>[ 2.062170] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10651 09:27:07.139599 <6>[ 2.084615] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10652 09:27:07.146541 <6>[ 2.091541] xhci-mtk 11200000.usb: xHCI Host Controller
10653 09:27:07.153323 <6>[ 2.097036] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10654 09:27:07.163246 <6>[ 2.104890] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10655 09:27:07.170450 <6>[ 2.114322] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10656 09:27:07.176677 <6>[ 2.120396] xhci-mtk 11200000.usb: xHCI Host Controller
10657 09:27:07.183539 <6>[ 2.125879] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10658 09:27:07.189910 <6>[ 2.133525] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10659 09:27:07.196477 <6>[ 2.141172] hub 1-0:1.0: USB hub found
10660 09:27:07.200410 <6>[ 2.145197] hub 1-0:1.0: 1 port detected
10661 09:27:07.206759 <6>[ 2.149490] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10662 09:27:07.213436 <6>[ 2.158029] hub 2-0:1.0: USB hub found
10663 09:27:07.216575 <6>[ 2.162047] hub 2-0:1.0: 1 port detected
10664 09:27:07.224460 <6>[ 2.168907] mtk-msdc 11f70000.mmc: Got CD GPIO
10665 09:27:07.240163 <6>[ 2.181563] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10666 09:27:07.247075 <6>[ 2.189943] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10667 09:27:07.256820 <6>[ 2.198288] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10668 09:27:07.263187 <6>[ 2.206628] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10669 09:27:07.273374 <6>[ 2.214967] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10670 09:27:07.283015 <6>[ 2.223306] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10671 09:27:07.289590 <6>[ 2.231645] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10672 09:27:07.299241 <6>[ 2.239983] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10673 09:27:07.306017 <6>[ 2.248322] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10674 09:27:07.315969 <6>[ 2.256661] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10675 09:27:07.323188 <6>[ 2.264998] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10676 09:27:07.333040 <6>[ 2.273345] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10677 09:27:07.340211 <6>[ 2.281683] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10678 09:27:07.349898 <6>[ 2.290021] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10679 09:27:07.356240 <6>[ 2.298358] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10680 09:27:07.363411 <6>[ 2.307070] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10681 09:27:07.369626 <6>[ 2.314237] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10682 09:27:07.376429 <6>[ 2.321024] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10683 09:27:07.386086 <6>[ 2.327797] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10684 09:27:07.392613 <6>[ 2.334738] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10685 09:27:07.399571 <6>[ 2.341604] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10686 09:27:07.409359 <6>[ 2.350735] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10687 09:27:07.419260 <6>[ 2.359854] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10688 09:27:07.429201 <6>[ 2.369153] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10689 09:27:07.439177 <6>[ 2.378621] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10690 09:27:07.446065 <6>[ 2.388088] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10691 09:27:07.455777 <6>[ 2.397208] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10692 09:27:07.465210 <6>[ 2.406674] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10693 09:27:07.475605 <6>[ 2.415793] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10694 09:27:07.485747 <6>[ 2.425102] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10695 09:27:07.495992 <6>[ 2.435261] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10696 09:27:07.505222 <6>[ 2.446785] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10697 09:27:07.512897 <6>[ 2.458000] Trying to probe devices needed for running init ...
10698 09:27:07.523924 <3>[ 2.465325] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10699 09:27:07.627415 <6>[ 2.568910] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10700 09:27:07.780990 <6>[ 2.726017] hub 1-1:1.0: USB hub found
10701 09:27:07.784371 <6>[ 2.730484] hub 1-1:1.0: 4 ports detected
10702 09:27:07.795382 <6>[ 2.740334] hub 1-1:1.0: USB hub found
10703 09:27:07.798599 <6>[ 2.744639] hub 1-1:1.0: 4 ports detected
10704 09:27:07.907315 <6>[ 2.849303] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10705 09:27:07.934695 <6>[ 2.879970] hub 2-1:1.0: USB hub found
10706 09:27:07.937979 <6>[ 2.884564] hub 2-1:1.0: 3 ports detected
10707 09:27:07.951453 <6>[ 2.896601] hub 2-1:1.0: USB hub found
10708 09:27:07.954578 <6>[ 2.901175] hub 2-1:1.0: 3 ports detected
10709 09:27:08.118794 <6>[ 3.060957] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10710 09:27:08.251278 <6>[ 3.196690] hub 1-1.4:1.0: USB hub found
10711 09:27:08.254529 <6>[ 3.201351] hub 1-1.4:1.0: 2 ports detected
10712 09:27:08.269543 <6>[ 3.214693] hub 1-1.4:1.0: USB hub found
10713 09:27:08.272831 <6>[ 3.219298] hub 1-1.4:1.0: 2 ports detected
10714 09:27:08.330857 <6>[ 3.273171] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10715 09:27:08.439498 <6>[ 3.381594] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10716 09:27:08.474986 <4>[ 3.417019] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10717 09:27:08.484814 <4>[ 3.426133] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10718 09:27:08.528874 <6>[ 3.474482] r8152 2-1.3:1.0 eth0: v1.12.13
10719 09:27:08.570523 <6>[ 3.512737] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10720 09:27:08.763334 <6>[ 3.704977] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10721 09:27:10.160220 <6>[ 5.105495] r8152 2-1.3:1.0 eth0: carrier on
10722 09:27:12.787287 <5>[ 5.132724] Sending DHCP requests .., OK
10723 09:27:12.793955 <6>[ 7.737106] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10724 09:27:12.797270 <6>[ 7.745395] IP-Config: Complete:
10725 09:27:12.810534 <6>[ 7.748894] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10726 09:27:12.817617 <6>[ 7.759600] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10727 09:27:12.823986 <6>[ 7.768217] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10728 09:27:12.831170 <6>[ 7.768227] nameserver0=192.168.201.1
10729 09:27:12.833981 <6>[ 7.780377] clk: Disabling unused clocks
10730 09:27:12.837392 <6>[ 7.786130] ALSA device list:
10731 09:27:12.843962 <6>[ 7.789375] No soundcards found.
10732 09:27:12.851244 <6>[ 7.796912] Freeing unused kernel memory: 8512K
10733 09:27:12.854929 <6>[ 7.801896] Run /init as init process
10734 09:27:12.864581 Loading, please wait...
10735 09:27:12.890291 Starting systemd-udevd version 252.22-1~deb12u1
10736 09:27:13.179926 <6>[ 8.121951] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10737 09:27:13.186149 <6>[ 8.123397] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10738 09:27:13.198919 <6>[ 8.141211] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10739 09:27:13.208795 <6>[ 8.144454] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10740 09:27:13.215666 <6>[ 8.146124] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10741 09:27:13.222201 <6>[ 8.149660] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10742 09:27:13.232521 <6>[ 8.158965] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10743 09:27:13.242330 <4>[ 8.166038] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10744 09:27:13.245391 <6>[ 8.166074] mc: Linux media interface: v0.10
10745 09:27:13.252076 <6>[ 8.168947] remoteproc remoteproc0: scp is available
10746 09:27:13.255473 <6>[ 8.169003] remoteproc remoteproc0: powering up scp
10747 09:27:13.265323 <6>[ 8.169007] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10748 09:27:13.268644 <6>[ 8.169023] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10749 09:27:13.278879 <6>[ 8.221218] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10750 09:27:13.285655 <3>[ 8.221873] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 09:27:13.295367 <6>[ 8.229913] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10752 09:27:13.302367 <4>[ 8.231012] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10753 09:27:13.308981 <6>[ 8.232222] videodev: Linux video capture interface: v2.00
10754 09:27:13.315613 <4>[ 8.235746] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10755 09:27:13.321958 <3>[ 8.237899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 09:27:13.332176 <6>[ 8.240609] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10757 09:27:13.338676 <6>[ 8.246224] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10758 09:27:13.348313 <3>[ 8.252943] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 09:27:13.354819 <6>[ 8.258721] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10760 09:27:13.362009 <3>[ 8.266305] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10761 09:27:13.371776 <4>[ 8.269806] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10762 09:27:13.378063 <4>[ 8.269806] Fallback method does not support PEC.
10763 09:27:13.384714 <6>[ 8.274086] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10764 09:27:13.394789 <6>[ 8.274091] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10765 09:27:13.401332 <6>[ 8.293979] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10766 09:27:13.408111 <6>[ 8.294187] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10767 09:27:13.414728 <6>[ 8.294276] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10768 09:27:13.421706 <6>[ 8.294288] remoteproc remoteproc0: remote processor scp is now up
10769 09:27:13.431286 <6>[ 8.297723] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10770 09:27:13.441276 <3>[ 8.297884] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 09:27:13.451285 <6>[ 8.298136] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10772 09:27:13.454828 <6>[ 8.305611] pci_bus 0000:00: root bus resource [bus 00-ff]
10773 09:27:13.464242 <6>[ 8.305619] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10774 09:27:13.474134 <6>[ 8.305622] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10775 09:27:13.481259 <3>[ 8.314018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10776 09:27:13.487442 <6>[ 8.327453] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10777 09:27:13.494443 <3>[ 8.335190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10778 09:27:13.504102 <3>[ 8.335196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10779 09:27:13.510418 <3>[ 8.335231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10780 09:27:13.517406 <6>[ 8.344468] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10781 09:27:13.526918 <6>[ 8.345093] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10782 09:27:13.537274 <3>[ 8.351241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 09:27:13.540317 <6>[ 8.358321] pci 0000:00:00.0: supports D1 D2
10784 09:27:13.546756 <3>[ 8.366847] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 09:27:13.556568 <6>[ 8.368714] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10786 09:27:13.563589 <6>[ 8.370112] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10787 09:27:13.573386 <6>[ 8.373233] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10788 09:27:13.579944 <3>[ 8.383306] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 09:27:13.583110 <6>[ 8.384287] Bluetooth: Core ver 2.22
10790 09:27:13.589429 <6>[ 8.384360] NET: Registered PF_BLUETOOTH protocol family
10791 09:27:13.596395 <6>[ 8.384364] Bluetooth: HCI device and connection manager initialized
10792 09:27:13.599607 <6>[ 8.384383] Bluetooth: HCI socket layer initialized
10793 09:27:13.606081 <6>[ 8.384391] Bluetooth: L2CAP socket layer initialized
10794 09:27:13.609820 <6>[ 8.384405] Bluetooth: SCO socket layer initialized
10795 09:27:13.619705 <6>[ 8.393142] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10796 09:27:13.626234 <3>[ 8.400468] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 09:27:13.632694 <6>[ 8.406276] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10798 09:27:13.639561 <6>[ 8.407592] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10799 09:27:13.652717 <6>[ 8.408583] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10800 09:27:13.659892 <6>[ 8.408735] usbcore: registered new interface driver uvcvideo
10801 09:27:13.666097 <3>[ 8.413285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10802 09:27:13.676489 <6>[ 8.423209] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10803 09:27:13.683215 <3>[ 8.431274] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10804 09:27:13.689696 <6>[ 8.437544] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10805 09:27:13.696292 <6>[ 8.438069] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10806 09:27:13.706485 <3>[ 8.445614] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10807 09:27:13.713220 <6>[ 8.453702] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10808 09:27:13.719820 <3>[ 8.461766] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10809 09:27:13.726624 <6>[ 8.462183] usbcore: registered new interface driver btusb
10810 09:27:13.736519 <4>[ 8.463189] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10811 09:27:13.742742 <3>[ 8.463201] Bluetooth: hci0: Failed to load firmware file (-2)
10812 09:27:13.749152 <3>[ 8.463204] Bluetooth: hci0: Failed to set up firmware (-2)
10813 09:27:13.759437 <4>[ 8.463208] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10814 09:27:13.763126 <6>[ 8.469338] pci 0000:01:00.0: supports D1 D2
10815 09:27:13.772639 <3>[ 8.478540] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10816 09:27:13.779634 <6>[ 8.486606] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10817 09:27:13.786000 <6>[ 8.496676] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10818 09:27:13.792297 <6>[ 8.736282] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10819 09:27:13.802730 <6>[ 8.744369] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10820 09:27:13.808963 <6>[ 8.752366] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10821 09:27:13.818692 <6>[ 8.760367] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10822 09:27:13.825139 <6>[ 8.768367] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10823 09:27:13.831740 <6>[ 8.776366] pci 0000:00:00.0: PCI bridge to [bus 01]
10824 09:27:13.838508 <6>[ 8.781583] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10825 09:27:13.845145 <6>[ 8.789702] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10826 09:27:13.851757 <6>[ 8.796538] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10827 09:27:13.858257 <6>[ 8.803129] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10828 09:27:13.879572 <5>[ 8.822173] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10829 09:27:13.901794 <5>[ 8.844495] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10830 09:27:13.908456 <5>[ 8.852093] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10831 09:27:13.918502 <4>[ 8.860557] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10832 09:27:13.925074 <6>[ 8.869468] cfg80211: failed to load regulatory.db
10833 09:27:13.978860 <6>[ 8.921795] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10834 09:27:13.985351 <6>[ 8.929487] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10835 09:27:14.010405 <6>[ 8.956254] mt7921e 0000:01:00.0: ASIC revision: 79610010
10836 09:27:14.116207 <6>[ 9.058777] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10837 09:27:14.119364 <6>[ 9.058777]
10838 09:27:14.127404 Begin: Loading essential drivers ... done.
10839 09:27:14.130663 Begin: Running /scripts/init-premount ... done.
10840 09:27:14.137087 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10841 09:27:14.147409 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10842 09:27:14.150673 Device /sys/class/net/eth0 found
10843 09:27:14.150758 done.
10844 09:27:14.157019 Begin: Waiting up to 180 secs for any network device to become available ... done.
10845 09:27:14.194812 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10846 09:27:14.201317 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10847 09:27:14.208303 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10848 09:27:14.214668 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10849 09:27:14.221476 host : mt8192-asurada-spherion-r0-cbg-1
10850 09:27:14.227828 domain : lava-rack
10851 09:27:14.231110 rootserver: 192.168.201.1 rootpath:
10852 09:27:14.231221 filename :
10853 09:27:14.337352 done.
10854 09:27:14.340502 Begin: Running /scripts/nfs-bottom ... done.
10855 09:27:14.358270 Begin: Running /scripts/init-bottom ... done.
10856 09:27:14.383692 <6>[ 9.326245] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10857 09:27:15.654096 <6>[ 10.600571] NET: Registered PF_INET6 protocol family
10858 09:27:15.661705 <6>[ 10.608034] Segment Routing with IPv6
10859 09:27:15.664922 <6>[ 10.612046] In-situ OAM (IOAM) with IPv6
10860 09:27:15.825708 <30>[ 10.745627] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10861 09:27:15.832704 <30>[ 10.778803] systemd[1]: Detected architecture arm64.
10862 09:27:15.839582
10863 09:27:15.842817 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10864 09:27:15.842901
10865 09:27:15.867114 <30>[ 10.813658] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10866 09:27:16.777774 <30>[ 11.720413] systemd[1]: Queued start job for default target graphical.target.
10867 09:27:16.807193 <30>[ 11.749934] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10868 09:27:16.813898 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10869 09:27:16.835718 <30>[ 11.778773] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10870 09:27:16.845404 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10871 09:27:16.863586 <30>[ 11.806662] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10872 09:27:16.873223 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10873 09:27:16.892067 <30>[ 11.835124] systemd[1]: Created slice user.slice - User and Session Slice.
10874 09:27:16.898578 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10875 09:27:16.922031 <30>[ 11.861812] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10876 09:27:16.931600 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10877 09:27:16.949346 <30>[ 11.889185] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10878 09:27:16.955974 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10879 09:27:16.984377 <30>[ 11.917573] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10880 09:27:16.994295 <30>[ 11.937515] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10881 09:27:17.000774 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10882 09:27:17.018152 <30>[ 11.961312] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10883 09:27:17.027826 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10884 09:27:17.046251 <30>[ 11.989439] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10885 09:27:17.056109 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10886 09:27:17.070768 <30>[ 12.017378] systemd[1]: Reached target paths.target - Path Units.
10887 09:27:17.081187 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10888 09:27:17.098530 <30>[ 12.041399] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10889 09:27:17.105025 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10890 09:27:17.118395 <30>[ 12.064931] systemd[1]: Reached target slices.target - Slice Units.
10891 09:27:17.128538 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10892 09:27:17.143142 <30>[ 12.089429] systemd[1]: Reached target swap.target - Swaps.
10893 09:27:17.149888 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10894 09:27:17.169806 <30>[ 12.113021] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10895 09:27:17.179973 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10896 09:27:17.198098 <30>[ 12.141389] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10897 09:27:17.207906 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10898 09:27:17.228864 <30>[ 12.171718] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10899 09:27:17.238605 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10900 09:27:17.255065 <30>[ 12.198273] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10901 09:27:17.265178 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10902 09:27:17.282399 <30>[ 12.225624] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10903 09:27:17.288977 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10904 09:27:17.307009 <30>[ 12.250257] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10905 09:27:17.316804 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10906 09:27:17.335995 <30>[ 12.279362] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10907 09:27:17.346207 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10908 09:27:17.362363 <30>[ 12.305412] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10909 09:27:17.372277 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10910 09:27:17.426017 <30>[ 12.369281] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10911 09:27:17.432902 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10912 09:27:17.452160 <30>[ 12.395413] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10913 09:27:17.458708 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10914 09:27:17.481475 <30>[ 12.424572] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10915 09:27:17.487874 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10916 09:27:17.512653 <30>[ 12.449420] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10917 09:27:17.527702 <30>[ 12.471208] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10918 09:27:17.537909 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10919 09:27:17.586485 <30>[ 12.529703] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10920 09:27:17.592881 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10921 09:27:17.619093 <30>[ 12.562577] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10922 09:27:17.625809 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10923 09:27:17.651671 <30>[ 12.594551] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10924 09:27:17.661359 Startin<6>[ 12.603955] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10925 09:27:17.667774 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10926 09:27:17.691507 <30>[ 12.634769] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10927 09:27:17.701256 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10928 09:27:17.750331 <30>[ 12.693613] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10929 09:27:17.756827 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10930 09:27:17.783835 <30>[ 12.726907] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10931 09:27:17.790544 Startin<6>[ 12.735663] fuse: init (API version 7.37)
10932 09:27:17.796927 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10933 09:27:17.823868 <30>[ 12.766772] systemd[1]: Starting systemd-journald.service - Journal Service...
10934 09:27:17.830263 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10935 09:27:17.860539 <30>[ 12.804047] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10936 09:27:17.867662 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10937 09:27:17.895579 <30>[ 12.835254] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10938 09:27:17.901964 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10939 09:27:17.927399 <30>[ 12.870457] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10940 09:27:17.937067 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10941 09:27:17.959621 <30>[ 12.902731] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10942 09:27:17.965894 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10943 09:27:17.994088 <30>[ 12.937194] systemd[1]: Started systemd-journald.service - Journal Service.
10944 09:27:18.000450 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10945 09:27:18.022933 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10946 09:27:18.038388 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10947 09:27:18.058647 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10948 09:27:18.079144 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10949 09:27:18.100059 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10950 09:27:18.120367 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10951 09:27:18.139401 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10952 09:27:18.159731 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10953 09:27:18.178864 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10954 09:27:18.200311 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10955 09:27:18.219365 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10956 09:27:18.239393 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10957 09:27:18.259829 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10958 09:27:18.278691 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10959 09:27:18.326486 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10960 09:27:18.354770 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10961 09:27:18.383761 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10962 09:27:18.405964 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10963 09:27:18.429778 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10964 09:27:18.455224 <46>[ 13.398917] systemd-journald[310]: Received client request to flush runtime journal.
10965 09:27:18.495402 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10966 09:27:18.766228 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10967 09:27:18.782947 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10968 09:27:18.802460 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10969 09:27:18.818817 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10970 09:27:19.222562 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10971 09:27:19.790869 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10972 09:27:19.838519 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10973 09:27:19.904095 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10974 09:27:19.998340 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10975 09:27:20.014345 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10976 09:27:20.029890 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10977 09:27:20.094280 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10978 09:27:20.115852 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10979 09:27:20.351266 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10980 09:27:20.420024 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10981 09:27:20.486102 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10982 09:27:20.600115 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10983 09:27:20.757953 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10984 09:27:20.776252 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10985 09:27:20.795008 <6>[ 15.741457] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10986 09:27:20.863276 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10987 09:27:20.882372 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10988 09:27:20.931630 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10989 09:27:20.977819 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10990 09:27:21.023251 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10991 09:27:21.043712 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10992 09:27:21.062435 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10993 09:27:21.085924 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10994 09:27:21.103138 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10995 09:27:21.122790 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10996 09:27:21.153186 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10997 09:27:21.173827 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10998 09:27:21.189642 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10999 09:27:21.205960 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11000 09:27:21.229319 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11001 09:27:21.249947 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11002 09:27:21.266372 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11003 09:27:21.286057 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11004 09:27:21.305621 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11005 09:27:21.320839 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11006 09:27:21.338117 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11007 09:27:21.354917 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11008 09:27:21.371161 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11009 09:27:21.414644 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11010 09:27:21.453558 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11011 09:27:21.533502 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11012 09:27:21.558118 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11013 09:27:21.609012 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11014 09:27:21.657255 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11015 09:27:21.674955 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11016 09:27:21.690693 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11017 09:27:21.720399 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11018 09:27:21.749952 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11019 09:27:21.972251 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11020 09:27:21.994013 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11021 09:27:22.015484 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11022 09:27:22.065874 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11023 09:27:22.109379 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11024 09:27:22.211437
11025 09:27:22.214518 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11026 09:27:22.214615
11027 09:27:22.217670 debian-bookworm-arm64 login: root (automatic login)
11028 09:27:22.217755
11029 09:27:22.484087 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
11030 09:27:22.484242
11031 09:27:22.491080 The programs included with the Debian GNU/Linux system are free software;
11032 09:27:22.497525 the exact distribution terms for each program are described in the
11033 09:27:22.500743 individual files in /usr/share/doc/*/copyright.
11034 09:27:22.500829
11035 09:27:22.507678 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11036 09:27:22.510842 permitted by applicable law.
11037 09:27:23.345681 Matched prompt #10: / #
11039 09:27:23.345983 Setting prompt string to ['/ #']
11040 09:27:23.346079 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11042 09:27:23.346270 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11043 09:27:23.346357 start: 2.2.6 expect-shell-connection (timeout 00:03:40) [common]
11044 09:27:23.346428 Setting prompt string to ['/ #']
11045 09:27:23.346488 Forcing a shell prompt, looking for ['/ #']
11047 09:27:23.396684 / #
11048 09:27:23.396820 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11049 09:27:23.396917 Waiting using forced prompt support (timeout 00:02:30)
11050 09:27:23.401263
11051 09:27:23.401539 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11052 09:27:23.401633 start: 2.2.7 export-device-env (timeout 00:03:40) [common]
11054 09:27:23.501985 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407618/extract-nfsrootfs-voawszzn'
11055 09:27:23.506918 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407618/extract-nfsrootfs-voawszzn'
11057 09:27:23.607471 / # export NFS_SERVER_IP='192.168.201.1'
11058 09:27:23.612706 export NFS_SERVER_IP='192.168.201.1'
11059 09:27:23.612994 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11060 09:27:23.613098 end: 2.2 depthcharge-retry (duration 00:01:21) [common]
11061 09:27:23.613192 end: 2 depthcharge-action (duration 00:01:21) [common]
11062 09:27:23.613289 start: 3 lava-test-retry (timeout 00:08:00) [common]
11063 09:27:23.613384 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
11064 09:27:23.613461 Using namespace: common
11066 09:27:23.713812 / # #
11067 09:27:23.713980 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11068 09:27:23.718736 #
11069 09:27:23.719005 Using /lava-14407618
11071 09:27:23.819323 / # export SHELL=/bin/bash
11072 09:27:23.825119 export SHELL=/bin/bash
11074 09:27:23.925661 / # . /lava-14407618/environment
11075 09:27:23.930833 . /lava-14407618/environment
11077 09:27:24.035984 / # /lava-14407618/bin/lava-test-runner /lava-14407618/0
11078 09:27:24.036148 Test shell timeout: 10s (minimum of the action and connection timeout)
11079 09:27:24.041161 /lava-14407618/bin/lava-test-runner /lava-14407618/0
11080 09:27:24.235142 + export TESTRUN_ID=0_timesync-off
11081 09:27:24.238263 + TESTRUN_ID=0_timesync-off
11082 09:27:24.241484 + cd /lava-14407618/0/tests/0_timesync-off
11083 09:27:24.244802 ++ cat uuid
11084 09:27:24.244888 + UUID=14407618_1.6.2.3.1
11085 09:27:24.248141 + set +x
11086 09:27:24.251282 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14407618_1.6.2.3.1>
11087 09:27:24.251548 Received signal: <STARTRUN> 0_timesync-off 14407618_1.6.2.3.1
11088 09:27:24.251625 Starting test lava.0_timesync-off (14407618_1.6.2.3.1)
11089 09:27:24.251714 Skipping test definition patterns.
11090 09:27:24.254864 + systemctl stop systemd-timesyncd
11091 09:27:24.334020 + set +x
11092 09:27:24.337191 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14407618_1.6.2.3.1>
11093 09:27:24.337463 Received signal: <ENDRUN> 0_timesync-off 14407618_1.6.2.3.1
11094 09:27:24.337557 Ending use of test pattern.
11095 09:27:24.337660 Ending test lava.0_timesync-off (14407618_1.6.2.3.1), duration 0.09
11097 09:27:24.389611 + export TESTRUN_ID=1_kselftest-dt
11098 09:27:24.393373 + TESTRUN_ID=1_kselftest-dt
11099 09:27:24.396762 + cd /lava-14407618/0/tests/1_kselftest-dt
11100 09:27:24.399812 ++ cat uuid
11101 09:27:24.399898 + UUID=14407618_1.6.2.3.5
11102 09:27:24.403056 + set +x
11103 09:27:24.406415 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 14407618_1.6.2.3.5>
11104 09:27:24.406674 Received signal: <STARTRUN> 1_kselftest-dt 14407618_1.6.2.3.5
11105 09:27:24.406747 Starting test lava.1_kselftest-dt (14407618_1.6.2.3.5)
11106 09:27:24.406830 Skipping test definition patterns.
11107 09:27:24.409755 + cd ./automated/linux/kselftest/
11108 09:27:24.436159 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11109 09:27:24.457621 INFO: install_deps skipped
11110 09:27:24.945430 --2024-06-18 09:25:59-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11111 09:27:24.952542 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11112 09:27:25.084847 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11113 09:27:25.217684 HTTP request sent, awaiting response... 200 OK
11114 09:27:25.221284 Length: 1642672 (1.6M) [application/octet-stream]
11115 09:27:25.224592 Saving to: 'kselftest_armhf.tar.gz'
11116 09:27:25.225264
11117 09:27:25.225893
11118 09:27:25.483246 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11119 09:27:25.878643 kselftest_armhf.tar 2%[ ] 46.39K 171KB/s
11120 09:27:26.143049 kselftest_armhf.tar 12%[=> ] 199.11K 295KB/s
11121 09:27:26.405834 kselftest_armhf.tar 42%[=======> ] 688.38K 728KB/s
11122 09:27:26.669147 kselftest_armhf.tar 62%[===========> ] 1001K 825KB/s
11123 09:27:26.811551 kselftest_armhf.tar 82%[===============> ] 1.30M 898KB/s
11124 09:27:26.818158 kselftest_armhf.tar 100%[===================>] 1.57M 986KB/s in 1.6s
11125 09:27:26.818254
11126 09:27:26.962356 2024-06-18 09:26:01 (986 KB/s) - 'kselftest_armhf.tar.gz' saved [1642672/1642672]
11127 09:27:26.962547
11128 09:27:30.349551 skiplist:
11129 09:27:30.352670 ========================================
11130 09:27:30.356251 ========================================
11131 09:27:30.409662 ============== Tests to run ===============
11132 09:27:30.412697 ===========End Tests to run ===============
11133 09:27:30.416223 shardfile-dt fail
11134 09:27:30.436498 ./kselftest.sh: 131: cannot open /lava-14407618/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11135 09:27:30.439611 + ../../utils/send-to-lava.sh ./output/result.txt
11136 09:27:30.485878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11137 09:27:30.486035 + set +x
11138 09:27:30.486288 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11140 09:27:30.492591 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 14407618_1.6.2.3.5>
11141 09:27:30.492848 Received signal: <ENDRUN> 1_kselftest-dt 14407618_1.6.2.3.5
11142 09:27:30.492927 Ending use of test pattern.
11143 09:27:30.492992 Ending test lava.1_kselftest-dt (14407618_1.6.2.3.5), duration 6.09
11145 09:27:30.493211 ok: lava_test_shell seems to have completed
11146 09:27:30.493305 shardfile-dt: fail
11147 09:27:30.493393 end: 3.1 lava-test-shell (duration 00:00:07) [common]
11148 09:27:30.493477 end: 3 lava-test-retry (duration 00:00:07) [common]
11149 09:27:30.493566 start: 4 finalize (timeout 00:07:53) [common]
11150 09:27:30.493659 start: 4.1 power-off (timeout 00:00:30) [common]
11151 09:27:30.493808 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11152 09:27:30.689556 >> Command sent successfully.
11153 09:27:30.691900 Returned 0 in 0 seconds
11154 09:27:30.792281 end: 4.1 power-off (duration 00:00:00) [common]
11156 09:27:30.792652 start: 4.2 read-feedback (timeout 00:07:53) [common]
11158 09:27:30.793197 Listened to connection for namespace 'common' for up to 1s
11159 09:27:31.793846 Finalising connection for namespace 'common'
11160 09:27:31.794025 Disconnecting from shell: Finalise
11161 09:27:31.794103 / #
11162 09:27:31.894406 end: 4.2 read-feedback (duration 00:00:01) [common]
11163 09:27:31.894597 end: 4 finalize (duration 00:00:01) [common]
11164 09:27:31.894754 Cleaning after the job
11165 09:27:31.894882 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/ramdisk
11166 09:27:31.897078 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/kernel
11167 09:27:31.907324 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/dtb
11168 09:27:31.907492 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/nfsrootfs
11169 09:27:31.968329 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407618/tftp-deploy-hb8xxyhl/modules
11170 09:27:31.973832 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407618
11171 09:27:32.493363 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407618
11172 09:27:32.493561 Job finished correctly