Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 09:23:42.425420 lava-dispatcher, installed at version: 2024.03
2 09:23:42.425730 start: 0 validate
3 09:23:42.425857 Start time: 2024-06-18 09:23:42.425849+00:00 (UTC)
4 09:23:42.426028 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:23:42.426212 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:23:42.691349 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:23:42.691515 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:24:00.954486 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:24:00.955049 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:24:01.205126 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:24:01.205262 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:24:01.699915 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:24:01.700057 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:24:03.703231 validate duration: 21.28
16 09:24:03.703597 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:24:03.703742 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:24:03.703875 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:24:03.704085 Not decompressing ramdisk as can be used compressed.
20 09:24:03.704217 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 09:24:03.704315 saving as /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/ramdisk/initrd.cpio.gz
22 09:24:03.704415 total size: 5628151 (5 MB)
23 09:24:03.968358 progress 0 % (0 MB)
24 09:24:03.970339 progress 5 % (0 MB)
25 09:24:03.972332 progress 10 % (0 MB)
26 09:24:03.974210 progress 15 % (0 MB)
27 09:24:03.976033 progress 20 % (1 MB)
28 09:24:03.977536 progress 25 % (1 MB)
29 09:24:03.979328 progress 30 % (1 MB)
30 09:24:03.981008 progress 35 % (1 MB)
31 09:24:03.982544 progress 40 % (2 MB)
32 09:24:03.984198 progress 45 % (2 MB)
33 09:24:03.985645 progress 50 % (2 MB)
34 09:24:03.987274 progress 55 % (2 MB)
35 09:24:03.989004 progress 60 % (3 MB)
36 09:24:03.990576 progress 65 % (3 MB)
37 09:24:03.992197 progress 70 % (3 MB)
38 09:24:03.993669 progress 75 % (4 MB)
39 09:24:03.995256 progress 80 % (4 MB)
40 09:24:03.996815 progress 85 % (4 MB)
41 09:24:03.998461 progress 90 % (4 MB)
42 09:24:04.000194 progress 95 % (5 MB)
43 09:24:04.001646 progress 100 % (5 MB)
44 09:24:04.001869 5 MB downloaded in 0.30 s (18.05 MB/s)
45 09:24:04.002039 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:24:04.002292 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:24:04.002388 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:24:04.002480 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:24:04.002630 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:24:04.002721 saving as /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/kernel/Image
52 09:24:04.002811 total size: 54813184 (52 MB)
53 09:24:04.002902 No compression specified
54 09:24:04.004360 progress 0 % (0 MB)
55 09:24:04.018557 progress 5 % (2 MB)
56 09:24:04.032804 progress 10 % (5 MB)
57 09:24:04.046877 progress 15 % (7 MB)
58 09:24:04.061485 progress 20 % (10 MB)
59 09:24:04.077108 progress 25 % (13 MB)
60 09:24:04.092339 progress 30 % (15 MB)
61 09:24:04.107512 progress 35 % (18 MB)
62 09:24:04.122618 progress 40 % (20 MB)
63 09:24:04.137381 progress 45 % (23 MB)
64 09:24:04.152215 progress 50 % (26 MB)
65 09:24:04.167024 progress 55 % (28 MB)
66 09:24:04.181777 progress 60 % (31 MB)
67 09:24:04.196653 progress 65 % (34 MB)
68 09:24:04.211123 progress 70 % (36 MB)
69 09:24:04.225609 progress 75 % (39 MB)
70 09:24:04.240401 progress 80 % (41 MB)
71 09:24:04.255190 progress 85 % (44 MB)
72 09:24:04.269874 progress 90 % (47 MB)
73 09:24:04.284341 progress 95 % (49 MB)
74 09:24:04.298771 progress 100 % (52 MB)
75 09:24:04.299049 52 MB downloaded in 0.30 s (176.46 MB/s)
76 09:24:04.299252 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:24:04.299508 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:24:04.299591 start: 1.3 download-retry (timeout 00:09:59) [common]
80 09:24:04.299669 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 09:24:04.299802 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:24:04.299874 saving as /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/dtb/mt8192-asurada-spherion-r0.dtb
83 09:24:04.299960 total size: 47258 (0 MB)
84 09:24:04.300038 No compression specified
85 09:24:04.301412 progress 69 % (0 MB)
86 09:24:04.301712 progress 100 % (0 MB)
87 09:24:04.301894 0 MB downloaded in 0.00 s (23.34 MB/s)
88 09:24:04.302054 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:24:04.302261 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:24:04.302339 start: 1.4 download-retry (timeout 00:09:59) [common]
92 09:24:04.302423 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 09:24:04.302533 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 09:24:04.302595 saving as /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/nfsrootfs/full.rootfs.tar
95 09:24:04.302649 total size: 69067788 (65 MB)
96 09:24:04.302705 Using unxz to decompress xz
97 09:24:04.303835 progress 0 % (0 MB)
98 09:24:04.497204 progress 5 % (3 MB)
99 09:24:04.708397 progress 10 % (6 MB)
100 09:24:04.951211 progress 15 % (9 MB)
101 09:24:05.119734 progress 20 % (13 MB)
102 09:24:05.310446 progress 25 % (16 MB)
103 09:24:05.506862 progress 30 % (19 MB)
104 09:24:05.631711 progress 35 % (23 MB)
105 09:24:05.737863 progress 40 % (26 MB)
106 09:24:05.940313 progress 45 % (29 MB)
107 09:24:06.157249 progress 50 % (32 MB)
108 09:24:06.370307 progress 55 % (36 MB)
109 09:24:06.594757 progress 60 % (39 MB)
110 09:24:06.809838 progress 65 % (42 MB)
111 09:24:07.012190 progress 70 % (46 MB)
112 09:24:07.215515 progress 75 % (49 MB)
113 09:24:07.423080 progress 80 % (52 MB)
114 09:24:07.613541 progress 85 % (56 MB)
115 09:24:07.813058 progress 90 % (59 MB)
116 09:24:08.023772 progress 95 % (62 MB)
117 09:24:08.232109 progress 100 % (65 MB)
118 09:24:08.238599 65 MB downloaded in 3.94 s (16.74 MB/s)
119 09:24:08.238855 end: 1.4.1 http-download (duration 00:00:04) [common]
121 09:24:08.239214 end: 1.4 download-retry (duration 00:00:04) [common]
122 09:24:08.239328 start: 1.5 download-retry (timeout 00:09:55) [common]
123 09:24:08.239442 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 09:24:08.239610 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:24:08.239701 saving as /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/modules/modules.tar
126 09:24:08.239790 total size: 8619356 (8 MB)
127 09:24:08.239884 Using unxz to decompress xz
128 09:24:08.241512 progress 0 % (0 MB)
129 09:24:08.263101 progress 5 % (0 MB)
130 09:24:08.289126 progress 10 % (0 MB)
131 09:24:08.314943 progress 15 % (1 MB)
132 09:24:08.340538 progress 20 % (1 MB)
133 09:24:08.366545 progress 25 % (2 MB)
134 09:24:08.392510 progress 30 % (2 MB)
135 09:24:08.419067 progress 35 % (2 MB)
136 09:24:08.445888 progress 40 % (3 MB)
137 09:24:08.471771 progress 45 % (3 MB)
138 09:24:08.497101 progress 50 % (4 MB)
139 09:24:08.523008 progress 55 % (4 MB)
140 09:24:08.548718 progress 60 % (4 MB)
141 09:24:08.573596 progress 65 % (5 MB)
142 09:24:08.603093 progress 70 % (5 MB)
143 09:24:08.629307 progress 75 % (6 MB)
144 09:24:08.654791 progress 80 % (6 MB)
145 09:24:08.678815 progress 85 % (7 MB)
146 09:24:08.702912 progress 90 % (7 MB)
147 09:24:08.730406 progress 95 % (7 MB)
148 09:24:08.759768 progress 100 % (8 MB)
149 09:24:08.764398 8 MB downloaded in 0.52 s (15.67 MB/s)
150 09:24:08.764655 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:24:08.765025 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:24:08.765148 start: 1.6 prepare-tftp-overlay (timeout 00:09:55) [common]
154 09:24:08.765267 start: 1.6.1 extract-nfsrootfs (timeout 00:09:55) [common]
155 09:24:10.640440 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14407629/extract-nfsrootfs-ggqeh951
156 09:24:10.640630 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 09:24:10.640732 start: 1.6.2 lava-overlay (timeout 00:09:53) [common]
158 09:24:10.640900 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8
159 09:24:10.641021 makedir: /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin
160 09:24:10.641135 makedir: /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/tests
161 09:24:10.641227 makedir: /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/results
162 09:24:10.641314 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-add-keys
163 09:24:10.641447 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-add-sources
164 09:24:10.641811 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-background-process-start
165 09:24:10.641939 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-background-process-stop
166 09:24:10.642069 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-common-functions
167 09:24:10.642191 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-echo-ipv4
168 09:24:10.642309 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-install-packages
169 09:24:10.642425 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-installed-packages
170 09:24:10.642540 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-os-build
171 09:24:10.642655 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-probe-channel
172 09:24:10.642770 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-probe-ip
173 09:24:10.642886 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-target-ip
174 09:24:10.643000 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-target-mac
175 09:24:10.643122 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-target-storage
176 09:24:10.643238 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-test-case
177 09:24:10.643352 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-test-event
178 09:24:10.643466 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-test-feedback
179 09:24:10.643579 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-test-raise
180 09:24:10.643692 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-test-reference
181 09:24:10.643823 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-test-runner
182 09:24:10.643946 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-test-set
183 09:24:10.644061 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-test-shell
184 09:24:10.644178 Updating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-install-packages (oe)
185 09:24:10.644330 Updating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/bin/lava-installed-packages (oe)
186 09:24:10.644448 Creating /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/environment
187 09:24:10.644563 LAVA metadata
188 09:24:10.644667 - LAVA_JOB_ID=14407629
189 09:24:10.644755 - LAVA_DISPATCHER_IP=192.168.201.1
190 09:24:10.644860 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:53) [common]
191 09:24:10.644918 skipped lava-vland-overlay
192 09:24:10.644988 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 09:24:10.645062 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
194 09:24:10.645115 skipped lava-multinode-overlay
195 09:24:10.645182 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 09:24:10.645252 start: 1.6.2.3 test-definition (timeout 00:09:53) [common]
197 09:24:10.645316 Loading test definitions
198 09:24:10.645392 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:53) [common]
199 09:24:10.645451 Using /lava-14407629 at stage 0
200 09:24:10.645752 uuid=14407629_1.6.2.3.1 testdef=None
201 09:24:10.645835 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 09:24:10.645911 start: 1.6.2.3.2 test-overlay (timeout 00:09:53) [common]
203 09:24:10.646349 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 09:24:10.646555 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:53) [common]
206 09:24:10.647130 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 09:24:10.647377 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
209 09:24:10.647951 runner path: /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/0/tests/0_lc-compliance test_uuid 14407629_1.6.2.3.1
210 09:24:10.648104 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 09:24:10.648292 Creating lava-test-runner.conf files
213 09:24:10.648348 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407629/lava-overlay-sxci1ps8/lava-14407629/0 for stage 0
214 09:24:10.648429 - 0_lc-compliance
215 09:24:10.648521 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 09:24:10.648600 start: 1.6.2.4 compress-overlay (timeout 00:09:53) [common]
217 09:24:10.655586 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 09:24:10.655741 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
219 09:24:10.655853 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 09:24:10.655964 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 09:24:10.656071 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
222 09:24:10.824105 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 09:24:10.824252 start: 1.6.4 extract-modules (timeout 00:09:53) [common]
224 09:24:10.824331 extracting modules file /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407629/extract-nfsrootfs-ggqeh951
225 09:24:11.046183 extracting modules file /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407629/extract-overlay-ramdisk-y2pr8212/ramdisk
226 09:24:11.275466 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 09:24:11.275613 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 09:24:11.275703 [common] Applying overlay to NFS
229 09:24:11.275764 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407629/compress-overlay-ldfjdzpy/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407629/extract-nfsrootfs-ggqeh951
230 09:24:11.281986 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 09:24:11.282115 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 09:24:11.282201 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 09:24:11.282281 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 09:24:11.282350 Building ramdisk /var/lib/lava/dispatcher/tmp/14407629/extract-overlay-ramdisk-y2pr8212/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407629/extract-overlay-ramdisk-y2pr8212/ramdisk
235 09:24:11.651560 >> 130466 blocks
236 09:24:13.797690 rename /var/lib/lava/dispatcher/tmp/14407629/extract-overlay-ramdisk-y2pr8212/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/ramdisk/ramdisk.cpio.gz
237 09:24:13.797870 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
238 09:24:13.797999 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 09:24:13.798116 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 09:24:13.798236 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/kernel/Image']
241 09:24:28.421534 Returned 0 in 14 seconds
242 09:24:28.522095 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/kernel/image.itb
243 09:24:28.926216 output: FIT description: Kernel Image image with one or more FDT blobs
244 09:24:28.926351 output: Created: Tue Jun 18 10:24:28 2024
245 09:24:28.926441 output: Image 0 (kernel-1)
246 09:24:28.926517 output: Description:
247 09:24:28.926591 output: Created: Tue Jun 18 10:24:28 2024
248 09:24:28.926665 output: Type: Kernel Image
249 09:24:28.926740 output: Compression: lzma compressed
250 09:24:28.926839 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
251 09:24:28.926938 output: Architecture: AArch64
252 09:24:28.927023 output: OS: Linux
253 09:24:28.927108 output: Load Address: 0x00000000
254 09:24:28.927192 output: Entry Point: 0x00000000
255 09:24:28.927273 output: Hash algo: crc32
256 09:24:28.927358 output: Hash value: 4137a6e7
257 09:24:28.927437 output: Image 1 (fdt-1)
258 09:24:28.927516 output: Description: mt8192-asurada-spherion-r0
259 09:24:28.927595 output: Created: Tue Jun 18 10:24:28 2024
260 09:24:28.927673 output: Type: Flat Device Tree
261 09:24:28.927761 output: Compression: uncompressed
262 09:24:28.927836 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 09:24:28.927912 output: Architecture: AArch64
264 09:24:28.927988 output: Hash algo: crc32
265 09:24:28.928063 output: Hash value: 0f8e4d2e
266 09:24:28.928137 output: Image 2 (ramdisk-1)
267 09:24:28.928212 output: Description: unavailable
268 09:24:28.928289 output: Created: Tue Jun 18 10:24:28 2024
269 09:24:28.928372 output: Type: RAMDisk Image
270 09:24:28.928447 output: Compression: uncompressed
271 09:24:28.928522 output: Data Size: 18745209 Bytes = 18305.87 KiB = 17.88 MiB
272 09:24:28.928598 output: Architecture: AArch64
273 09:24:28.928672 output: OS: Linux
274 09:24:28.928747 output: Load Address: unavailable
275 09:24:28.928822 output: Entry Point: unavailable
276 09:24:28.928896 output: Hash algo: crc32
277 09:24:28.928970 output: Hash value: 5cf5cff9
278 09:24:28.929045 output: Default Configuration: 'conf-1'
279 09:24:28.929120 output: Configuration 0 (conf-1)
280 09:24:28.929194 output: Description: mt8192-asurada-spherion-r0
281 09:24:28.929269 output: Kernel: kernel-1
282 09:24:28.929343 output: Init Ramdisk: ramdisk-1
283 09:24:28.929418 output: FDT: fdt-1
284 09:24:28.929492 output: Loadables: kernel-1
285 09:24:28.929592 output:
286 09:24:28.929743 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
287 09:24:28.929828 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
288 09:24:28.929916 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
289 09:24:28.929995 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
290 09:24:28.930060 No LXC device requested
291 09:24:28.930128 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 09:24:28.930203 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
293 09:24:28.930270 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 09:24:28.930332 Checking files for TFTP limit of 4294967296 bytes.
295 09:24:28.930779 end: 1 tftp-deploy (duration 00:00:25) [common]
296 09:24:28.930875 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 09:24:28.930956 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 09:24:28.931069 substitutions:
299 09:24:28.931131 - {DTB}: 14407629/tftp-deploy-x56ds326/dtb/mt8192-asurada-spherion-r0.dtb
300 09:24:28.931190 - {INITRD}: 14407629/tftp-deploy-x56ds326/ramdisk/ramdisk.cpio.gz
301 09:24:28.931244 - {KERNEL}: 14407629/tftp-deploy-x56ds326/kernel/Image
302 09:24:28.931297 - {LAVA_MAC}: None
303 09:24:28.931349 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14407629/extract-nfsrootfs-ggqeh951
304 09:24:28.931401 - {NFS_SERVER_IP}: 192.168.201.1
305 09:24:28.931450 - {PRESEED_CONFIG}: None
306 09:24:28.931509 - {PRESEED_LOCAL}: None
307 09:24:28.931558 - {RAMDISK}: 14407629/tftp-deploy-x56ds326/ramdisk/ramdisk.cpio.gz
308 09:24:28.931607 - {ROOT_PART}: None
309 09:24:28.931656 - {ROOT}: None
310 09:24:28.931715 - {SERVER_IP}: 192.168.201.1
311 09:24:28.931790 - {TEE}: None
312 09:24:28.931862 Parsed boot commands:
313 09:24:28.931911 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 09:24:28.932066 Parsed boot commands: tftpboot 192.168.201.1 14407629/tftp-deploy-x56ds326/kernel/image.itb 14407629/tftp-deploy-x56ds326/kernel/cmdline
315 09:24:28.932147 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 09:24:28.932221 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 09:24:28.932302 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 09:24:28.932377 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 09:24:28.932439 Not connected, no need to disconnect.
320 09:24:28.932505 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 09:24:28.932576 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 09:24:28.932636 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
323 09:24:28.936091 Setting prompt string to ['lava-test: # ']
324 09:24:28.936459 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 09:24:28.936569 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 09:24:28.936661 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 09:24:28.936797 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 09:24:28.937050 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
329 09:24:38.082475 >> Command sent successfully.
330 09:24:38.085463 Returned 0 in 9 seconds
331 09:24:38.185804 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
333 09:24:38.186088 end: 2.2.2 reset-device (duration 00:00:09) [common]
334 09:24:38.186198 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
335 09:24:38.186310 Setting prompt string to 'Starting depthcharge on Spherion...'
336 09:24:38.186396 Changing prompt to 'Starting depthcharge on Spherion...'
337 09:24:38.186485 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 09:24:38.187016 [Enter `^Ec?' for help]
339 09:24:39.700160
340 09:24:39.700300
341 09:24:39.700398 F0: 102B 0000
342 09:24:39.700486
343 09:24:39.700571 F3: 1001 0000 [0200]
344 09:24:39.704487
345 09:24:39.704590 F3: 1001 0000
346 09:24:39.704679
347 09:24:39.704774 F7: 102D 0000
348 09:24:39.704861
349 09:24:39.704957 F1: 0000 0000
350 09:24:39.705046
351 09:24:39.708029 V0: 0000 0000 [0001]
352 09:24:39.708128
353 09:24:39.708212 00: 0007 8000
354 09:24:39.708294
355 09:24:39.711472 01: 0000 0000
356 09:24:39.711579
357 09:24:39.711642 BP: 0C00 0209 [0000]
358 09:24:39.711698
359 09:24:39.715163 G0: 1182 0000
360 09:24:39.715259
361 09:24:39.715344 EC: 0000 0021 [4000]
362 09:24:39.715435
363 09:24:39.719423 S7: 0000 0000 [0000]
364 09:24:39.719518
365 09:24:39.719600 CC: 0000 0000 [0001]
366 09:24:39.719688
367 09:24:39.722265 T0: 0000 0040 [010F]
368 09:24:39.722359
369 09:24:39.722419 Jump to BL
370 09:24:39.722472
371 09:24:39.748098
372 09:24:39.748210
373 09:24:39.755119 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 09:24:39.759114 ARM64: Exception handlers installed.
375 09:24:39.762041 ARM64: Testing exception
376 09:24:39.766792 ARM64: Done test exception
377 09:24:39.770269 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 09:24:39.781092 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 09:24:39.787528 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 09:24:39.798411 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 09:24:39.804848 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 09:24:39.815090 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 09:24:39.825496 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 09:24:39.831892 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 09:24:39.849973 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 09:24:39.853566 WDT: Last reset was cold boot
387 09:24:39.857210 SPI1(PAD0) initialized at 2873684 Hz
388 09:24:39.859998 SPI5(PAD0) initialized at 992727 Hz
389 09:24:39.863437 VBOOT: Loading verstage.
390 09:24:39.869799 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 09:24:39.873407 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 09:24:39.876914 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 09:24:39.880269 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 09:24:39.887765 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 09:24:39.894098 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 09:24:39.905343 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
397 09:24:39.905451
398 09:24:39.905513
399 09:24:39.915386 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 09:24:39.919087 ARM64: Exception handlers installed.
401 09:24:39.922081 ARM64: Testing exception
402 09:24:39.922162 ARM64: Done test exception
403 09:24:39.928589 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 09:24:39.932216 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 09:24:39.946636 Probing TPM: . done!
406 09:24:39.946733 TPM ready after 0 ms
407 09:24:39.953029 Connected to device vid:did:rid of 1ae0:0028:00
408 09:24:39.963105 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
409 09:24:40.000175 Initialized TPM device CR50 revision 0
410 09:24:40.011726 tlcl_send_startup: Startup return code is 0
411 09:24:40.011817 TPM: setup succeeded
412 09:24:40.023190 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 09:24:40.032475 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 09:24:40.042116 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 09:24:40.051569 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 09:24:40.054899 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 09:24:40.057744 in-header: 03 07 00 00 08 00 00 00
418 09:24:40.061235 in-data: aa e4 47 04 13 02 00 00
419 09:24:40.064673 Chrome EC: UHEPI supported
420 09:24:40.071187 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 09:24:40.074580 in-header: 03 a9 00 00 08 00 00 00
422 09:24:40.078094 in-data: 84 60 60 08 00 00 00 00
423 09:24:40.078167 Phase 1
424 09:24:40.081415 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 09:24:40.088006 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 09:24:40.094494 VB2:vb2_check_recovery() Recovery was requested manually
427 09:24:40.097914 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
428 09:24:40.101438 Recovery requested (1009000e)
429 09:24:40.109649 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 09:24:40.114686 tlcl_extend: response is 0
431 09:24:40.123180 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 09:24:40.128223 tlcl_extend: response is 0
433 09:24:40.135188 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 09:24:40.156927 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 09:24:40.163870 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 09:24:40.163962
437 09:24:40.164023
438 09:24:40.174129 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 09:24:40.174218 ARM64: Exception handlers installed.
440 09:24:40.177554 ARM64: Testing exception
441 09:24:40.181000 ARM64: Done test exception
442 09:24:40.201262 pmic_efuse_setting: Set efuses in 11 msecs
443 09:24:40.204844 pmwrap_interface_init: Select PMIF_VLD_RDY
444 09:24:40.211320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 09:24:40.214925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 09:24:40.221377 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 09:24:40.224851 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 09:24:40.231800 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 09:24:40.234645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 09:24:40.238213 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 09:24:40.244740 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 09:24:40.248366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 09:24:40.254685 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 09:24:40.258316 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 09:24:40.261894 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 09:24:40.268051 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 09:24:40.275087 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 09:24:40.278602 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 09:24:40.285009 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 09:24:40.291733 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 09:24:40.295068 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 09:24:40.301327 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 09:24:40.308368 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 09:24:40.311825 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 09:24:40.318185 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 09:24:40.325447 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 09:24:40.328338 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 09:24:40.335157 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 09:24:40.341992 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 09:24:40.344879 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 09:24:40.351478 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 09:24:40.355074 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 09:24:40.362076 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 09:24:40.364888 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 09:24:40.371457 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 09:24:40.375041 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 09:24:40.381999 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 09:24:40.385424 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 09:24:40.392002 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 09:24:40.395433 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 09:24:40.402401 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 09:24:40.405145 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 09:24:40.408806 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 09:24:40.412511 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 09:24:40.418863 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 09:24:40.422212 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 09:24:40.425565 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 09:24:40.432303 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 09:24:40.435809 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 09:24:40.439526 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 09:24:40.442323 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 09:24:40.448840 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 09:24:40.452288 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 09:24:40.455703 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 09:24:40.465336 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
496 09:24:40.472531 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 09:24:40.479015 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 09:24:40.485862 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 09:24:40.495811 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 09:24:40.498688 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 09:24:40.502305 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 09:24:40.508744 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 09:24:40.515499 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x28
504 09:24:40.518983 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 09:24:40.525963 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 09:24:40.529491 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 09:24:40.538754 [RTC]rtc_get_frequency_meter,154: input=15, output=760
508 09:24:40.548275 [RTC]rtc_get_frequency_meter,154: input=23, output=943
509 09:24:40.557525 [RTC]rtc_get_frequency_meter,154: input=19, output=851
510 09:24:40.567236 [RTC]rtc_get_frequency_meter,154: input=17, output=803
511 09:24:40.576606 [RTC]rtc_get_frequency_meter,154: input=16, output=782
512 09:24:40.586082 [RTC]rtc_get_frequency_meter,154: input=16, output=782
513 09:24:40.595749 [RTC]rtc_get_frequency_meter,154: input=17, output=804
514 09:24:40.599317 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
515 09:24:40.606531 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
516 09:24:40.609409 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 09:24:40.613070 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 09:24:40.619527 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 09:24:40.622840 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 09:24:40.626164 ADC[4]: Raw value=906203 ID=7
521 09:24:40.626248 ADC[3]: Raw value=213441 ID=1
522 09:24:40.629740 RAM Code: 0x71
523 09:24:40.632702 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 09:24:40.639930 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 09:24:40.646112 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 09:24:40.653068 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 09:24:40.655935 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 09:24:40.659506 in-header: 03 07 00 00 08 00 00 00
529 09:24:40.662997 in-data: aa e4 47 04 13 02 00 00
530 09:24:40.666035 Chrome EC: UHEPI supported
531 09:24:40.673202 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 09:24:40.676030 in-header: 03 a9 00 00 08 00 00 00
533 09:24:40.679693 in-data: 84 60 60 08 00 00 00 00
534 09:24:40.682954 MRC: failed to locate region type 0.
535 09:24:40.689299 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 09:24:40.692952 DRAM-K: Running full calibration
537 09:24:40.699156 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 09:24:40.699243 header.status = 0x0
539 09:24:40.702606 header.version = 0x6 (expected: 0x6)
540 09:24:40.705764 header.size = 0xd00 (expected: 0xd00)
541 09:24:40.709384 header.flags = 0x0
542 09:24:40.716079 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 09:24:40.733017 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
544 09:24:40.739645 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 09:24:40.743267 dram_init: ddr_geometry: 2
546 09:24:40.743338 [EMI] MDL number = 2
547 09:24:40.746089 [EMI] Get MDL freq = 0
548 09:24:40.749592 dram_init: ddr_type: 0
549 09:24:40.749663 is_discrete_lpddr4: 1
550 09:24:40.753259 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 09:24:40.753355
552 09:24:40.753440
553 09:24:40.756061 [Bian_co] ETT version 0.0.0.1
554 09:24:40.762784 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 09:24:40.762888
556 09:24:40.766309 dramc_set_vcore_voltage set vcore to 650000
557 09:24:40.766404 Read voltage for 800, 4
558 09:24:40.769774 Vio18 = 0
559 09:24:40.769867 Vcore = 650000
560 09:24:40.769964 Vdram = 0
561 09:24:40.773391 Vddq = 0
562 09:24:40.773481 Vmddr = 0
563 09:24:40.776290 dram_init: config_dvfs: 1
564 09:24:40.779137 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 09:24:40.786217 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 09:24:40.789463 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
567 09:24:40.792896 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
568 09:24:40.796632 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
569 09:24:40.799430 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
570 09:24:40.802752 MEM_TYPE=3, freq_sel=18
571 09:24:40.806446 sv_algorithm_assistance_LP4_1600
572 09:24:40.810049 ============ PULL DRAM RESETB DOWN ============
573 09:24:40.813308 ========== PULL DRAM RESETB DOWN end =========
574 09:24:40.820468 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 09:24:40.824792 ===================================
576 09:24:40.824898 LPDDR4 DRAM CONFIGURATION
577 09:24:40.827829 ===================================
578 09:24:40.831559 EX_ROW_EN[0] = 0x0
579 09:24:40.831662 EX_ROW_EN[1] = 0x0
580 09:24:40.835773 LP4Y_EN = 0x0
581 09:24:40.835911 WORK_FSP = 0x0
582 09:24:40.836005 WL = 0x2
583 09:24:40.839288 RL = 0x2
584 09:24:40.839423 BL = 0x2
585 09:24:40.842872 RPST = 0x0
586 09:24:40.842982 RD_PRE = 0x0
587 09:24:40.847336 WR_PRE = 0x1
588 09:24:40.847480 WR_PST = 0x0
589 09:24:40.850850 DBI_WR = 0x0
590 09:24:40.850977 DBI_RD = 0x0
591 09:24:40.853858 OTF = 0x1
592 09:24:40.857492 ===================================
593 09:24:40.860912 ===================================
594 09:24:40.861052 ANA top config
595 09:24:40.864562 ===================================
596 09:24:40.867529 DLL_ASYNC_EN = 0
597 09:24:40.867623 ALL_SLAVE_EN = 1
598 09:24:40.870953 NEW_RANK_MODE = 1
599 09:24:40.874508 DLL_IDLE_MODE = 1
600 09:24:40.877202 LP45_APHY_COMB_EN = 1
601 09:24:40.880738 TX_ODT_DIS = 1
602 09:24:40.880845 NEW_8X_MODE = 1
603 09:24:40.884362 ===================================
604 09:24:40.887255 ===================================
605 09:24:40.890840 data_rate = 1600
606 09:24:40.893742 CKR = 1
607 09:24:40.897207 DQ_P2S_RATIO = 8
608 09:24:40.900674 ===================================
609 09:24:40.904105 CA_P2S_RATIO = 8
610 09:24:40.907801 DQ_CA_OPEN = 0
611 09:24:40.907894 DQ_SEMI_OPEN = 0
612 09:24:40.910748 CA_SEMI_OPEN = 0
613 09:24:40.914427 CA_FULL_RATE = 0
614 09:24:40.917332 DQ_CKDIV4_EN = 1
615 09:24:40.920856 CA_CKDIV4_EN = 1
616 09:24:40.920925 CA_PREDIV_EN = 0
617 09:24:40.924135 PH8_DLY = 0
618 09:24:40.927630 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 09:24:40.931183 DQ_AAMCK_DIV = 4
620 09:24:40.934381 CA_AAMCK_DIV = 4
621 09:24:40.937831 CA_ADMCK_DIV = 4
622 09:24:40.937930 DQ_TRACK_CA_EN = 0
623 09:24:40.940718 CA_PICK = 800
624 09:24:40.944077 CA_MCKIO = 800
625 09:24:40.947501 MCKIO_SEMI = 0
626 09:24:40.951180 PLL_FREQ = 3068
627 09:24:40.954072 DQ_UI_PI_RATIO = 32
628 09:24:40.957717 CA_UI_PI_RATIO = 0
629 09:24:40.960631 ===================================
630 09:24:40.964285 ===================================
631 09:24:40.964388 memory_type:LPDDR4
632 09:24:40.967911 GP_NUM : 10
633 09:24:40.967986 SRAM_EN : 1
634 09:24:40.970837 MD32_EN : 0
635 09:24:40.974479 ===================================
636 09:24:40.977422 [ANA_INIT] >>>>>>>>>>>>>>
637 09:24:40.980989 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 09:24:40.984690 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 09:24:40.987499 ===================================
640 09:24:40.987602 data_rate = 1600,PCW = 0X7600
641 09:24:40.991053 ===================================
642 09:24:40.994492 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 09:24:41.001507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 09:24:41.007809 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 09:24:41.011259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 09:24:41.014718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 09:24:41.018256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 09:24:41.021201 [ANA_INIT] flow start
649 09:24:41.021298 [ANA_INIT] PLL >>>>>>>>
650 09:24:41.024997 [ANA_INIT] PLL <<<<<<<<
651 09:24:41.027885 [ANA_INIT] MIDPI >>>>>>>>
652 09:24:41.031381 [ANA_INIT] MIDPI <<<<<<<<
653 09:24:41.031461 [ANA_INIT] DLL >>>>>>>>
654 09:24:41.034766 [ANA_INIT] flow end
655 09:24:41.038135 ============ LP4 DIFF to SE enter ============
656 09:24:41.041755 ============ LP4 DIFF to SE exit ============
657 09:24:41.044863 [ANA_INIT] <<<<<<<<<<<<<
658 09:24:41.048354 [Flow] Enable top DCM control >>>>>
659 09:24:41.051520 [Flow] Enable top DCM control <<<<<
660 09:24:41.055126 Enable DLL master slave shuffle
661 09:24:41.058651 ==============================================================
662 09:24:41.061436 Gating Mode config
663 09:24:41.068602 ==============================================================
664 09:24:41.068709 Config description:
665 09:24:41.078534 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 09:24:41.085052 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 09:24:41.088603 SELPH_MODE 0: By rank 1: By Phase
668 09:24:41.094877 ==============================================================
669 09:24:41.098343 GAT_TRACK_EN = 1
670 09:24:41.101744 RX_GATING_MODE = 2
671 09:24:41.105140 RX_GATING_TRACK_MODE = 2
672 09:24:41.108057 SELPH_MODE = 1
673 09:24:41.111765 PICG_EARLY_EN = 1
674 09:24:41.115240 VALID_LAT_VALUE = 1
675 09:24:41.118066 ==============================================================
676 09:24:41.121506 Enter into Gating configuration >>>>
677 09:24:41.125300 Exit from Gating configuration <<<<
678 09:24:41.128146 Enter into DVFS_PRE_config >>>>>
679 09:24:41.138288 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 09:24:41.141697 Exit from DVFS_PRE_config <<<<<
681 09:24:41.144965 Enter into PICG configuration >>>>
682 09:24:41.148264 Exit from PICG configuration <<<<
683 09:24:41.151684 [RX_INPUT] configuration >>>>>
684 09:24:41.154940 [RX_INPUT] configuration <<<<<
685 09:24:41.161836 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 09:24:41.172561 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 09:24:41.172700 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 09:24:41.178051 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 09:24:41.185076 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 09:24:41.191592 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 09:24:41.195163 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 09:24:41.198660 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 09:24:41.201677 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 09:24:41.204994 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 09:24:41.212069 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 09:24:41.215528 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 09:24:41.218376 ===================================
698 09:24:41.221865 LPDDR4 DRAM CONFIGURATION
699 09:24:41.225335 ===================================
700 09:24:41.225415 EX_ROW_EN[0] = 0x0
701 09:24:41.228780 EX_ROW_EN[1] = 0x0
702 09:24:41.228859 LP4Y_EN = 0x0
703 09:24:41.231660 WORK_FSP = 0x0
704 09:24:41.231738 WL = 0x2
705 09:24:41.235231 RL = 0x2
706 09:24:41.235308 BL = 0x2
707 09:24:41.238818 RPST = 0x0
708 09:24:41.238896 RD_PRE = 0x0
709 09:24:41.241692 WR_PRE = 0x1
710 09:24:41.241768 WR_PST = 0x0
711 09:24:41.245281 DBI_WR = 0x0
712 09:24:41.248276 DBI_RD = 0x0
713 09:24:41.248354 OTF = 0x1
714 09:24:41.251667 ===================================
715 09:24:41.254976 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 09:24:41.258547 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 09:24:41.265310 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 09:24:41.268682 ===================================
719 09:24:41.272015 LPDDR4 DRAM CONFIGURATION
720 09:24:41.272095 ===================================
721 09:24:41.274959 EX_ROW_EN[0] = 0x10
722 09:24:41.278487 EX_ROW_EN[1] = 0x0
723 09:24:41.278569 LP4Y_EN = 0x0
724 09:24:41.281767 WORK_FSP = 0x0
725 09:24:41.281863 WL = 0x2
726 09:24:41.285388 RL = 0x2
727 09:24:41.285510 BL = 0x2
728 09:24:41.288205 RPST = 0x0
729 09:24:41.288310 RD_PRE = 0x0
730 09:24:41.291736 WR_PRE = 0x1
731 09:24:41.291843 WR_PST = 0x0
732 09:24:41.295399 DBI_WR = 0x0
733 09:24:41.295507 DBI_RD = 0x0
734 09:24:41.298256 OTF = 0x1
735 09:24:41.301848 ===================================
736 09:24:41.308317 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 09:24:41.311588 nWR fixed to 40
738 09:24:41.311720 [ModeRegInit_LP4] CH0 RK0
739 09:24:41.314991 [ModeRegInit_LP4] CH0 RK1
740 09:24:41.318335 [ModeRegInit_LP4] CH1 RK0
741 09:24:41.321931 [ModeRegInit_LP4] CH1 RK1
742 09:24:41.322077 match AC timing 13
743 09:24:41.328772 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 09:24:41.332200 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 09:24:41.335530 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 09:24:41.338439 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 09:24:41.345631 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 09:24:41.345740 [EMI DOE] emi_dcm 0
749 09:24:41.351902 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 09:24:41.352032 ==
751 09:24:41.355407 Dram Type= 6, Freq= 0, CH_0, rank 0
752 09:24:41.358774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 09:24:41.358902 ==
754 09:24:41.365503 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 09:24:41.368817 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 09:24:41.379154 [CA 0] Center 36 (6~67) winsize 62
757 09:24:41.381792 [CA 1] Center 36 (6~67) winsize 62
758 09:24:41.385324 [CA 2] Center 34 (4~65) winsize 62
759 09:24:41.388914 [CA 3] Center 33 (3~64) winsize 62
760 09:24:41.391836 [CA 4] Center 33 (3~64) winsize 62
761 09:24:41.395423 [CA 5] Center 32 (3~62) winsize 60
762 09:24:41.395561
763 09:24:41.399693 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 09:24:41.399814
765 09:24:41.403256 [CATrainingPosCal] consider 1 rank data
766 09:24:41.406900 u2DelayCellTimex100 = 270/100 ps
767 09:24:41.409739 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
768 09:24:41.413209 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
769 09:24:41.416716 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
770 09:24:41.420073 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
771 09:24:41.423520 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
772 09:24:41.427096 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
773 09:24:41.427218
774 09:24:41.433516 CA PerBit enable=1, Macro0, CA PI delay=32
775 09:24:41.433641
776 09:24:41.436978 [CBTSetCACLKResult] CA Dly = 32
777 09:24:41.437068 CS Dly: 5 (0~36)
778 09:24:41.437127 ==
779 09:24:41.440251 Dram Type= 6, Freq= 0, CH_0, rank 1
780 09:24:41.443075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 09:24:41.443212 ==
782 09:24:41.450241 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 09:24:41.456579 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 09:24:41.464919 [CA 0] Center 36 (6~67) winsize 62
785 09:24:41.468345 [CA 1] Center 36 (6~67) winsize 62
786 09:24:41.471885 [CA 2] Center 34 (4~65) winsize 62
787 09:24:41.475246 [CA 3] Center 33 (3~64) winsize 62
788 09:24:41.478236 [CA 4] Center 32 (2~63) winsize 62
789 09:24:41.481729 [CA 5] Center 32 (2~63) winsize 62
790 09:24:41.481837
791 09:24:41.485200 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 09:24:41.485303
793 09:24:41.487907 [CATrainingPosCal] consider 2 rank data
794 09:24:41.491267 u2DelayCellTimex100 = 270/100 ps
795 09:24:41.494600 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
796 09:24:41.498279 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
797 09:24:41.504906 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
798 09:24:41.508532 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
799 09:24:41.511288 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
800 09:24:41.514695 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
801 09:24:41.514831
802 09:24:41.518172 CA PerBit enable=1, Macro0, CA PI delay=32
803 09:24:41.518272
804 09:24:41.521707 [CBTSetCACLKResult] CA Dly = 32
805 09:24:41.521807 CS Dly: 5 (0~36)
806 09:24:41.521895
807 09:24:41.525193 ----->DramcWriteLeveling(PI) begin...
808 09:24:41.528512 ==
809 09:24:41.531961 Dram Type= 6, Freq= 0, CH_0, rank 0
810 09:24:41.534950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 09:24:41.535069 ==
812 09:24:41.538525 Write leveling (Byte 0): 33 => 33
813 09:24:41.541900 Write leveling (Byte 1): 29 => 29
814 09:24:41.544717 DramcWriteLeveling(PI) end<-----
815 09:24:41.544822
816 09:24:41.544909 ==
817 09:24:41.548211 Dram Type= 6, Freq= 0, CH_0, rank 0
818 09:24:41.551824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 09:24:41.551941 ==
820 09:24:41.555280 [Gating] SW mode calibration
821 09:24:41.561585 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 09:24:41.565162 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 09:24:41.571591 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 09:24:41.574981 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 09:24:41.578473 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 09:24:41.585532 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 09:24:41.588427 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 09:24:41.591891 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 09:24:41.598592 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 09:24:41.601984 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 09:24:41.605529 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 09:24:41.612094 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 09:24:41.615619 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 09:24:41.618426 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 09:24:41.621903 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 09:24:41.628888 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 09:24:41.631692 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 09:24:41.635079 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 09:24:41.642135 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 09:24:41.645659 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 09:24:41.648768 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
842 09:24:41.655650 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 09:24:41.659273 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 09:24:41.662230 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 09:24:41.668606 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 09:24:41.672188 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 09:24:41.675732 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 09:24:41.681878 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 09:24:41.685230 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
850 09:24:41.688579 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
851 09:24:41.695555 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 09:24:41.699160 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 09:24:41.702489 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 09:24:41.705261 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 09:24:41.712111 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 09:24:41.715656 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
857 09:24:41.719189 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
858 09:24:41.725425 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 09:24:41.728934 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 09:24:41.732617 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 09:24:41.738944 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 09:24:41.742400 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 09:24:41.745786 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 09:24:41.752850 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 09:24:41.755770 0 11 8 | B1->B0 | 2e2e 3e3e | 0 0 | (0 0) (0 0)
866 09:24:41.759382 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
867 09:24:41.762868 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 09:24:41.769113 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 09:24:41.772540 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 09:24:41.776183 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 09:24:41.782820 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 09:24:41.786390 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 09:24:41.789196 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
874 09:24:41.795871 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 09:24:41.799176 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 09:24:41.802940 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 09:24:41.809495 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 09:24:41.812980 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 09:24:41.815773 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 09:24:41.822639 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 09:24:41.826177 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 09:24:41.829662 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 09:24:41.835876 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 09:24:41.839305 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 09:24:41.842782 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 09:24:41.846379 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 09:24:41.853139 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 09:24:41.856747 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
889 09:24:41.859510 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
890 09:24:41.863104 Total UI for P1: 0, mck2ui 16
891 09:24:41.866590 best dqsien dly found for B0: ( 0, 14, 4)
892 09:24:41.872820 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
893 09:24:41.876491 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 09:24:41.879884 Total UI for P1: 0, mck2ui 16
895 09:24:41.882842 best dqsien dly found for B1: ( 0, 14, 10)
896 09:24:41.886521 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
897 09:24:41.889900 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
898 09:24:41.889994
899 09:24:41.893492 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
900 09:24:41.896258 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
901 09:24:41.900051 [Gating] SW calibration Done
902 09:24:41.900163 ==
903 09:24:41.902903 Dram Type= 6, Freq= 0, CH_0, rank 0
904 09:24:41.906345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
905 09:24:41.906435 ==
906 09:24:41.909616 RX Vref Scan: 0
907 09:24:41.909699
908 09:24:41.912951 RX Vref 0 -> 0, step: 1
909 09:24:41.913067
910 09:24:41.913157 RX Delay -130 -> 252, step: 16
911 09:24:41.920125 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
912 09:24:41.923235 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
913 09:24:41.926321 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
914 09:24:41.930349 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
915 09:24:41.933229 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
916 09:24:41.939825 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
917 09:24:41.943230 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
918 09:24:41.946661 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
919 09:24:41.950266 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
920 09:24:41.953112 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
921 09:24:41.959987 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
922 09:24:41.963201 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
923 09:24:41.966736 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
924 09:24:41.970123 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
925 09:24:41.973657 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
926 09:24:41.980573 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
927 09:24:41.980717 ==
928 09:24:41.983415 Dram Type= 6, Freq= 0, CH_0, rank 0
929 09:24:41.987154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 09:24:41.987276 ==
931 09:24:41.987374 DQS Delay:
932 09:24:41.990578 DQS0 = 0, DQS1 = 0
933 09:24:41.990664 DQM Delay:
934 09:24:41.993408 DQM0 = 90, DQM1 = 83
935 09:24:41.993518 DQ Delay:
936 09:24:41.997026 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
937 09:24:42.000599 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
938 09:24:42.003539 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
939 09:24:42.007036 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
940 09:24:42.007157
941 09:24:42.007248
942 09:24:42.007333 ==
943 09:24:42.010587 Dram Type= 6, Freq= 0, CH_0, rank 0
944 09:24:42.013422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 09:24:42.013532 ==
946 09:24:42.013617
947 09:24:42.013673
948 09:24:42.016878 TX Vref Scan disable
949 09:24:42.020506 == TX Byte 0 ==
950 09:24:42.024061 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
951 09:24:42.027045 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
952 09:24:42.030649 == TX Byte 1 ==
953 09:24:42.033983 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
954 09:24:42.037391 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
955 09:24:42.037492 ==
956 09:24:42.040619 Dram Type= 6, Freq= 0, CH_0, rank 0
957 09:24:42.043788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 09:24:42.047336 ==
959 09:24:42.058752 TX Vref=22, minBit 8, minWin=27, winSum=450
960 09:24:42.062202 TX Vref=24, minBit 8, minWin=27, winSum=452
961 09:24:42.065479 TX Vref=26, minBit 9, minWin=27, winSum=455
962 09:24:42.068903 TX Vref=28, minBit 5, minWin=28, winSum=458
963 09:24:42.072135 TX Vref=30, minBit 0, minWin=28, winSum=456
964 09:24:42.075404 TX Vref=32, minBit 5, minWin=28, winSum=456
965 09:24:42.082283 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 28
966 09:24:42.082417
967 09:24:42.085707 Final TX Range 1 Vref 28
968 09:24:42.085814
969 09:24:42.085878 ==
970 09:24:42.089151 Dram Type= 6, Freq= 0, CH_0, rank 0
971 09:24:42.092071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
972 09:24:42.092157 ==
973 09:24:42.092218
974 09:24:42.092273
975 09:24:42.095561 TX Vref Scan disable
976 09:24:42.099197 == TX Byte 0 ==
977 09:24:42.102208 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
978 09:24:42.105717 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
979 09:24:42.109279 == TX Byte 1 ==
980 09:24:42.112149 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
981 09:24:42.115806 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
982 09:24:42.115899
983 09:24:42.119415 [DATLAT]
984 09:24:42.119501 Freq=800, CH0 RK0
985 09:24:42.119559
986 09:24:42.122270 DATLAT Default: 0xa
987 09:24:42.122340 0, 0xFFFF, sum = 0
988 09:24:42.125710 1, 0xFFFF, sum = 0
989 09:24:42.125817 2, 0xFFFF, sum = 0
990 09:24:42.129059 3, 0xFFFF, sum = 0
991 09:24:42.129142 4, 0xFFFF, sum = 0
992 09:24:42.132676 5, 0xFFFF, sum = 0
993 09:24:42.132765 6, 0xFFFF, sum = 0
994 09:24:42.135447 7, 0xFFFF, sum = 0
995 09:24:42.135532 8, 0xFFFF, sum = 0
996 09:24:42.139121 9, 0x0, sum = 1
997 09:24:42.139214 10, 0x0, sum = 2
998 09:24:42.142632 11, 0x0, sum = 3
999 09:24:42.142724 12, 0x0, sum = 4
1000 09:24:42.145508 best_step = 10
1001 09:24:42.145615
1002 09:24:42.145695 ==
1003 09:24:42.149106 Dram Type= 6, Freq= 0, CH_0, rank 0
1004 09:24:42.152415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1005 09:24:42.152507 ==
1006 09:24:42.155880 RX Vref Scan: 1
1007 09:24:42.155972
1008 09:24:42.156035 Set Vref Range= 32 -> 127
1009 09:24:42.156093
1010 09:24:42.159196 RX Vref 32 -> 127, step: 1
1011 09:24:42.159287
1012 09:24:42.162655 RX Delay -95 -> 252, step: 8
1013 09:24:42.162745
1014 09:24:42.166008 Set Vref, RX VrefLevel [Byte0]: 32
1015 09:24:42.169274 [Byte1]: 32
1016 09:24:42.169367
1017 09:24:42.172704 Set Vref, RX VrefLevel [Byte0]: 33
1018 09:24:42.176194 [Byte1]: 33
1019 09:24:42.178756
1020 09:24:42.178876 Set Vref, RX VrefLevel [Byte0]: 34
1021 09:24:42.182217 [Byte1]: 34
1022 09:24:42.186748
1023 09:24:42.186867 Set Vref, RX VrefLevel [Byte0]: 35
1024 09:24:42.190251 [Byte1]: 35
1025 09:24:42.194344
1026 09:24:42.194448 Set Vref, RX VrefLevel [Byte0]: 36
1027 09:24:42.197532 [Byte1]: 36
1028 09:24:42.202107
1029 09:24:42.202216 Set Vref, RX VrefLevel [Byte0]: 37
1030 09:24:42.205645 [Byte1]: 37
1031 09:24:42.209234
1032 09:24:42.209329 Set Vref, RX VrefLevel [Byte0]: 38
1033 09:24:42.212762 [Byte1]: 38
1034 09:24:42.217121
1035 09:24:42.217222 Set Vref, RX VrefLevel [Byte0]: 39
1036 09:24:42.220704 [Byte1]: 39
1037 09:24:42.225150
1038 09:24:42.225249 Set Vref, RX VrefLevel [Byte0]: 40
1039 09:24:42.227985 [Byte1]: 40
1040 09:24:42.232215
1041 09:24:42.232329 Set Vref, RX VrefLevel [Byte0]: 41
1042 09:24:42.235607 [Byte1]: 41
1043 09:24:42.239813
1044 09:24:42.239923 Set Vref, RX VrefLevel [Byte0]: 42
1045 09:24:42.243466 [Byte1]: 42
1046 09:24:42.247657
1047 09:24:42.247766 Set Vref, RX VrefLevel [Byte0]: 43
1048 09:24:42.250665 [Byte1]: 43
1049 09:24:42.254915
1050 09:24:42.255011 Set Vref, RX VrefLevel [Byte0]: 44
1051 09:24:42.258317 [Byte1]: 44
1052 09:24:42.262407
1053 09:24:42.262537 Set Vref, RX VrefLevel [Byte0]: 45
1054 09:24:42.265911 [Byte1]: 45
1055 09:24:42.270138
1056 09:24:42.270245 Set Vref, RX VrefLevel [Byte0]: 46
1057 09:24:42.273441 [Byte1]: 46
1058 09:24:42.278194
1059 09:24:42.278296 Set Vref, RX VrefLevel [Byte0]: 47
1060 09:24:42.281285 [Byte1]: 47
1061 09:24:42.285646
1062 09:24:42.285751 Set Vref, RX VrefLevel [Byte0]: 48
1063 09:24:42.289049 [Byte1]: 48
1064 09:24:42.293038
1065 09:24:42.293149 Set Vref, RX VrefLevel [Byte0]: 49
1066 09:24:42.296217 [Byte1]: 49
1067 09:24:42.300961
1068 09:24:42.301065 Set Vref, RX VrefLevel [Byte0]: 50
1069 09:24:42.303774 [Byte1]: 50
1070 09:24:42.308470
1071 09:24:42.311682 Set Vref, RX VrefLevel [Byte0]: 51
1072 09:24:42.311803 [Byte1]: 51
1073 09:24:42.315624
1074 09:24:42.315715 Set Vref, RX VrefLevel [Byte0]: 52
1075 09:24:42.319044 [Byte1]: 52
1076 09:24:42.323255
1077 09:24:42.323360 Set Vref, RX VrefLevel [Byte0]: 53
1078 09:24:42.326863 [Byte1]: 53
1079 09:24:42.331269
1080 09:24:42.331377 Set Vref, RX VrefLevel [Byte0]: 54
1081 09:24:42.334126 [Byte1]: 54
1082 09:24:42.338432
1083 09:24:42.338523 Set Vref, RX VrefLevel [Byte0]: 55
1084 09:24:42.341825 [Byte1]: 55
1085 09:24:42.346150
1086 09:24:42.346251 Set Vref, RX VrefLevel [Byte0]: 56
1087 09:24:42.349641 [Byte1]: 56
1088 09:24:42.353949
1089 09:24:42.354048 Set Vref, RX VrefLevel [Byte0]: 57
1090 09:24:42.357452 [Byte1]: 57
1091 09:24:42.361754
1092 09:24:42.361848 Set Vref, RX VrefLevel [Byte0]: 58
1093 09:24:42.364569 [Byte1]: 58
1094 09:24:42.369256
1095 09:24:42.369353 Set Vref, RX VrefLevel [Byte0]: 59
1096 09:24:42.372084 [Byte1]: 59
1097 09:24:42.376368
1098 09:24:42.376475 Set Vref, RX VrefLevel [Byte0]: 60
1099 09:24:42.379826 [Byte1]: 60
1100 09:24:42.384540
1101 09:24:42.384645 Set Vref, RX VrefLevel [Byte0]: 61
1102 09:24:42.387903 [Byte1]: 61
1103 09:24:42.392096
1104 09:24:42.392191 Set Vref, RX VrefLevel [Byte0]: 62
1105 09:24:42.395047 [Byte1]: 62
1106 09:24:42.399235
1107 09:24:42.399327 Set Vref, RX VrefLevel [Byte0]: 63
1108 09:24:42.402595 [Byte1]: 63
1109 09:24:42.407278
1110 09:24:42.410484 Set Vref, RX VrefLevel [Byte0]: 64
1111 09:24:42.410599 [Byte1]: 64
1112 09:24:42.414735
1113 09:24:42.414867 Set Vref, RX VrefLevel [Byte0]: 65
1114 09:24:42.418230 [Byte1]: 65
1115 09:24:42.422265
1116 09:24:42.422382 Set Vref, RX VrefLevel [Byte0]: 66
1117 09:24:42.425772 [Byte1]: 66
1118 09:24:42.429669
1119 09:24:42.429792 Set Vref, RX VrefLevel [Byte0]: 67
1120 09:24:42.433566 [Byte1]: 67
1121 09:24:42.437622
1122 09:24:42.437720 Set Vref, RX VrefLevel [Byte0]: 68
1123 09:24:42.440512 [Byte1]: 68
1124 09:24:42.445354
1125 09:24:42.445441 Set Vref, RX VrefLevel [Byte0]: 69
1126 09:24:42.448281 [Byte1]: 69
1127 09:24:42.452386
1128 09:24:42.452492 Set Vref, RX VrefLevel [Byte0]: 70
1129 09:24:42.455934 [Byte1]: 70
1130 09:24:42.460285
1131 09:24:42.460378 Set Vref, RX VrefLevel [Byte0]: 71
1132 09:24:42.463757 [Byte1]: 71
1133 09:24:42.467874
1134 09:24:42.467964 Set Vref, RX VrefLevel [Byte0]: 72
1135 09:24:42.471473 [Byte1]: 72
1136 09:24:42.475682
1137 09:24:42.475775 Set Vref, RX VrefLevel [Byte0]: 73
1138 09:24:42.478534 [Byte1]: 73
1139 09:24:42.482872
1140 09:24:42.482962 Set Vref, RX VrefLevel [Byte0]: 74
1141 09:24:42.486547 [Byte1]: 74
1142 09:24:42.490513
1143 09:24:42.490608 Set Vref, RX VrefLevel [Byte0]: 75
1144 09:24:42.494014 [Byte1]: 75
1145 09:24:42.498169
1146 09:24:42.498256 Set Vref, RX VrefLevel [Byte0]: 76
1147 09:24:42.501785 [Byte1]: 76
1148 09:24:42.506092
1149 09:24:42.506210 Set Vref, RX VrefLevel [Byte0]: 77
1150 09:24:42.508964 [Byte1]: 77
1151 09:24:42.513843
1152 09:24:42.513945 Final RX Vref Byte 0 = 57 to rank0
1153 09:24:42.517191 Final RX Vref Byte 1 = 56 to rank0
1154 09:24:42.520491 Final RX Vref Byte 0 = 57 to rank1
1155 09:24:42.523407 Final RX Vref Byte 1 = 56 to rank1==
1156 09:24:42.526772 Dram Type= 6, Freq= 0, CH_0, rank 0
1157 09:24:42.530309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 09:24:42.534003 ==
1159 09:24:42.534087 DQS Delay:
1160 09:24:42.534148 DQS0 = 0, DQS1 = 0
1161 09:24:42.536830 DQM Delay:
1162 09:24:42.536937 DQM0 = 92, DQM1 = 85
1163 09:24:42.540349 DQ Delay:
1164 09:24:42.540442 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1165 09:24:42.543727 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1166 09:24:42.547103 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1167 09:24:42.550360 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1168 09:24:42.553589
1169 09:24:42.553672
1170 09:24:42.560187 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1171 09:24:42.563738 CH0 RK0: MR19=606, MR18=4E43
1172 09:24:42.570625 CH0_RK0: MR19=0x606, MR18=0x4E43, DQSOSC=390, MR23=63, INC=97, DEC=64
1173 09:24:42.570763
1174 09:24:42.573458 ----->DramcWriteLeveling(PI) begin...
1175 09:24:42.573579 ==
1176 09:24:42.576803 Dram Type= 6, Freq= 0, CH_0, rank 1
1177 09:24:42.580408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 09:24:42.580542 ==
1179 09:24:42.584063 Write leveling (Byte 0): 33 => 33
1180 09:24:42.586997 Write leveling (Byte 1): 29 => 29
1181 09:24:42.590597 DramcWriteLeveling(PI) end<-----
1182 09:24:42.590713
1183 09:24:42.590798 ==
1184 09:24:42.594060 Dram Type= 6, Freq= 0, CH_0, rank 1
1185 09:24:42.597556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1186 09:24:42.597656 ==
1187 09:24:42.600517 [Gating] SW mode calibration
1188 09:24:42.607662 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1189 09:24:42.614075 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1190 09:24:42.657801 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1191 09:24:42.658101 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1192 09:24:42.658172 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1193 09:24:42.658237 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 09:24:42.658305 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 09:24:42.658361 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 09:24:42.658424 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 09:24:42.658485 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 09:24:42.658552 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 09:24:42.658616 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 09:24:42.693981 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 09:24:42.694099 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 09:24:42.694161 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 09:24:42.694218 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 09:24:42.694465 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 09:24:42.694523 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 09:24:42.694575 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 09:24:42.694626 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1208 09:24:42.698105 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1209 09:24:42.701456 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1210 09:24:42.704374 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 09:24:42.707695 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 09:24:42.714742 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 09:24:42.717586 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 09:24:42.721268 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 09:24:42.727581 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 09:24:42.730898 0 9 8 | B1->B0 | 2d2d 2b2a | 1 1 | (0 0) (0 0)
1217 09:24:42.734518 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 09:24:42.741411 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 09:24:42.744201 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 09:24:42.747722 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 09:24:42.754730 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 09:24:42.757555 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 09:24:42.761154 0 10 4 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
1224 09:24:42.768134 0 10 8 | B1->B0 | 2a2a 2626 | 0 1 | (0 0) (1 0)
1225 09:24:42.771094 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 09:24:42.774789 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 09:24:42.777649 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 09:24:42.784744 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 09:24:42.788115 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 09:24:42.791488 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 09:24:42.797705 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 09:24:42.801454 0 11 8 | B1->B0 | 4343 3a3a | 0 0 | (0 0) (0 0)
1233 09:24:42.804496 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 09:24:42.811495 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 09:24:42.814805 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 09:24:42.818107 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 09:24:42.824502 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 09:24:42.828115 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 09:24:42.831017 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 09:24:42.838054 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1241 09:24:42.841442 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 09:24:42.844802 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 09:24:42.851048 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 09:24:42.854499 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 09:24:42.857885 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 09:24:42.861405 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 09:24:42.868492 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 09:24:42.871348 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 09:24:42.874916 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 09:24:42.881478 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 09:24:42.885102 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 09:24:42.888057 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 09:24:42.895175 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 09:24:42.897990 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 09:24:42.901443 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 09:24:42.908590 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1257 09:24:42.911323 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 09:24:42.914663 Total UI for P1: 0, mck2ui 16
1259 09:24:42.918364 best dqsien dly found for B0: ( 0, 14, 8)
1260 09:24:42.921655 Total UI for P1: 0, mck2ui 16
1261 09:24:42.924843 best dqsien dly found for B1: ( 0, 14, 10)
1262 09:24:42.928498 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1263 09:24:42.931750 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1264 09:24:42.931881
1265 09:24:42.935333 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1266 09:24:42.938167 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1267 09:24:42.941633 [Gating] SW calibration Done
1268 09:24:42.941740 ==
1269 09:24:42.945064 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 09:24:42.948552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 09:24:42.948669 ==
1272 09:24:42.951332 RX Vref Scan: 0
1273 09:24:42.951410
1274 09:24:42.954855 RX Vref 0 -> 0, step: 1
1275 09:24:42.954966
1276 09:24:42.955055 RX Delay -130 -> 252, step: 16
1277 09:24:42.961803 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1278 09:24:42.965292 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1279 09:24:42.968232 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1280 09:24:42.971617 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1281 09:24:42.975354 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1282 09:24:42.981802 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1283 09:24:42.985402 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1284 09:24:42.988183 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1285 09:24:42.991715 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1286 09:24:42.995423 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1287 09:24:43.001913 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1288 09:24:43.005464 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1289 09:24:43.008309 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1290 09:24:43.011699 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1291 09:24:43.015049 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1292 09:24:43.022143 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1293 09:24:43.022262 ==
1294 09:24:43.025574 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 09:24:43.028454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 09:24:43.028554 ==
1297 09:24:43.028617 DQS Delay:
1298 09:24:43.031876 DQS0 = 0, DQS1 = 0
1299 09:24:43.031982 DQM Delay:
1300 09:24:43.035399 DQM0 = 92, DQM1 = 81
1301 09:24:43.035499 DQ Delay:
1302 09:24:43.038837 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1303 09:24:43.042198 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =109
1304 09:24:43.045498 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1305 09:24:43.048678 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1306 09:24:43.048768
1307 09:24:43.048846
1308 09:24:43.048920 ==
1309 09:24:43.051899 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 09:24:43.055281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 09:24:43.055391 ==
1312 09:24:43.055471
1313 09:24:43.055543
1314 09:24:43.058730 TX Vref Scan disable
1315 09:24:43.062327 == TX Byte 0 ==
1316 09:24:43.065134 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1317 09:24:43.068619 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1318 09:24:43.072151 == TX Byte 1 ==
1319 09:24:43.075663 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1320 09:24:43.079197 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1321 09:24:43.079291 ==
1322 09:24:43.082168 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 09:24:43.085797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 09:24:43.088699 ==
1325 09:24:43.100674 TX Vref=22, minBit 9, minWin=27, winSum=451
1326 09:24:43.103697 TX Vref=24, minBit 1, minWin=28, winSum=454
1327 09:24:43.107178 TX Vref=26, minBit 1, minWin=28, winSum=454
1328 09:24:43.110895 TX Vref=28, minBit 4, minWin=28, winSum=459
1329 09:24:43.113766 TX Vref=30, minBit 8, minWin=27, winSum=456
1330 09:24:43.117242 TX Vref=32, minBit 2, minWin=28, winSum=452
1331 09:24:43.123849 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 28
1332 09:24:43.123989
1333 09:24:43.127218 Final TX Range 1 Vref 28
1334 09:24:43.127308
1335 09:24:43.127389 ==
1336 09:24:43.130621 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 09:24:43.134273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 09:24:43.134386 ==
1339 09:24:43.134478
1340 09:24:43.134572
1341 09:24:43.137692 TX Vref Scan disable
1342 09:24:43.140573 == TX Byte 0 ==
1343 09:24:43.144186 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1344 09:24:43.147669 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1345 09:24:43.150686 == TX Byte 1 ==
1346 09:24:43.154161 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1347 09:24:43.157379 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1348 09:24:43.157482
1349 09:24:43.160564 [DATLAT]
1350 09:24:43.160657 Freq=800, CH0 RK1
1351 09:24:43.160719
1352 09:24:43.164186 DATLAT Default: 0xa
1353 09:24:43.164283 0, 0xFFFF, sum = 0
1354 09:24:43.167893 1, 0xFFFF, sum = 0
1355 09:24:43.167985 2, 0xFFFF, sum = 0
1356 09:24:43.170846 3, 0xFFFF, sum = 0
1357 09:24:43.170935 4, 0xFFFF, sum = 0
1358 09:24:43.174449 5, 0xFFFF, sum = 0
1359 09:24:43.174545 6, 0xFFFF, sum = 0
1360 09:24:43.177453 7, 0xFFFF, sum = 0
1361 09:24:43.177574 8, 0xFFFF, sum = 0
1362 09:24:43.180593 9, 0x0, sum = 1
1363 09:24:43.180682 10, 0x0, sum = 2
1364 09:24:43.184012 11, 0x0, sum = 3
1365 09:24:43.184125 12, 0x0, sum = 4
1366 09:24:43.187886 best_step = 10
1367 09:24:43.188001
1368 09:24:43.188098 ==
1369 09:24:43.191497 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 09:24:43.194207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 09:24:43.194318 ==
1372 09:24:43.197675 RX Vref Scan: 0
1373 09:24:43.197787
1374 09:24:43.197849 RX Vref 0 -> 0, step: 1
1375 09:24:43.197904
1376 09:24:43.201149 RX Delay -95 -> 252, step: 8
1377 09:24:43.204604 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1378 09:24:43.211003 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1379 09:24:43.214641 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1380 09:24:43.218241 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1381 09:24:43.221029 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1382 09:24:43.224697 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1383 09:24:43.231338 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1384 09:24:43.234260 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1385 09:24:43.238033 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1386 09:24:43.241474 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1387 09:24:43.244885 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1388 09:24:43.251149 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1389 09:24:43.254782 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1390 09:24:43.258309 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1391 09:24:43.261131 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1392 09:24:43.264583 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1393 09:24:43.264678 ==
1394 09:24:43.268310 Dram Type= 6, Freq= 0, CH_0, rank 1
1395 09:24:43.274603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 09:24:43.274736 ==
1397 09:24:43.274825 DQS Delay:
1398 09:24:43.278061 DQS0 = 0, DQS1 = 0
1399 09:24:43.278147 DQM Delay:
1400 09:24:43.278207 DQM0 = 93, DQM1 = 83
1401 09:24:43.281399 DQ Delay:
1402 09:24:43.284601 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1403 09:24:43.287773 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1404 09:24:43.291379 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1405 09:24:43.294599 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1406 09:24:43.294723
1407 09:24:43.294811
1408 09:24:43.301070 [DQSOSCAuto] RK1, (LSB)MR18= 0x4618, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
1409 09:24:43.304797 CH0 RK1: MR19=606, MR18=4618
1410 09:24:43.311511 CH0_RK1: MR19=0x606, MR18=0x4618, DQSOSC=392, MR23=63, INC=96, DEC=64
1411 09:24:43.314936 [RxdqsGatingPostProcess] freq 800
1412 09:24:43.318434 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1413 09:24:43.321282 Pre-setting of DQS Precalculation
1414 09:24:43.328429 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1415 09:24:43.328537 ==
1416 09:24:43.331342 Dram Type= 6, Freq= 0, CH_1, rank 0
1417 09:24:43.334864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 09:24:43.334955 ==
1419 09:24:43.341235 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1420 09:24:43.348229 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1421 09:24:43.355768 [CA 0] Center 36 (6~67) winsize 62
1422 09:24:43.359039 [CA 1] Center 36 (6~67) winsize 62
1423 09:24:43.362631 [CA 2] Center 34 (4~65) winsize 62
1424 09:24:43.365466 [CA 3] Center 34 (4~65) winsize 62
1425 09:24:43.369108 [CA 4] Center 34 (4~65) winsize 62
1426 09:24:43.372646 [CA 5] Center 34 (4~65) winsize 62
1427 09:24:43.372737
1428 09:24:43.375495 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1429 09:24:43.375583
1430 09:24:43.379104 [CATrainingPosCal] consider 1 rank data
1431 09:24:43.381940 u2DelayCellTimex100 = 270/100 ps
1432 09:24:43.385459 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1433 09:24:43.388907 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1434 09:24:43.395749 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 09:24:43.398628 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1436 09:24:43.402109 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1437 09:24:43.405526 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 09:24:43.405647
1439 09:24:43.409178 CA PerBit enable=1, Macro0, CA PI delay=34
1440 09:24:43.409259
1441 09:24:43.411905 [CBTSetCACLKResult] CA Dly = 34
1442 09:24:43.411981 CS Dly: 6 (0~37)
1443 09:24:43.415296 ==
1444 09:24:43.415410 Dram Type= 6, Freq= 0, CH_1, rank 1
1445 09:24:43.421865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 09:24:43.421994 ==
1447 09:24:43.425622 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1448 09:24:43.432117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1449 09:24:43.441577 [CA 0] Center 36 (6~67) winsize 62
1450 09:24:43.445016 [CA 1] Center 37 (6~68) winsize 63
1451 09:24:43.448509 [CA 2] Center 35 (5~66) winsize 62
1452 09:24:43.451301 [CA 3] Center 34 (4~65) winsize 62
1453 09:24:43.454702 [CA 4] Center 35 (4~66) winsize 63
1454 09:24:43.458088 [CA 5] Center 34 (4~65) winsize 62
1455 09:24:43.458208
1456 09:24:43.461536 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1457 09:24:43.461652
1458 09:24:43.464849 [CATrainingPosCal] consider 2 rank data
1459 09:24:43.468519 u2DelayCellTimex100 = 270/100 ps
1460 09:24:43.471655 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1461 09:24:43.475128 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1462 09:24:43.482099 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1463 09:24:43.484922 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 09:24:43.488420 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 09:24:43.491952 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 09:24:43.492044
1467 09:24:43.495352 CA PerBit enable=1, Macro0, CA PI delay=34
1468 09:24:43.495470
1469 09:24:43.498798 [CBTSetCACLKResult] CA Dly = 34
1470 09:24:43.498907 CS Dly: 6 (0~38)
1471 09:24:43.498995
1472 09:24:43.502337 ----->DramcWriteLeveling(PI) begin...
1473 09:24:43.502422 ==
1474 09:24:43.505569 Dram Type= 6, Freq= 0, CH_1, rank 0
1475 09:24:43.511975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 09:24:43.512091 ==
1477 09:24:43.515548 Write leveling (Byte 0): 25 => 25
1478 09:24:43.518988 Write leveling (Byte 1): 26 => 26
1479 09:24:43.519087 DramcWriteLeveling(PI) end<-----
1480 09:24:43.519149
1481 09:24:43.522492 ==
1482 09:24:43.525396 Dram Type= 6, Freq= 0, CH_1, rank 0
1483 09:24:43.528880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1484 09:24:43.528972 ==
1485 09:24:43.532478 [Gating] SW mode calibration
1486 09:24:43.539031 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1487 09:24:43.542091 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1488 09:24:43.549154 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1489 09:24:43.552364 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1490 09:24:43.555654 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 09:24:43.562283 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 09:24:43.565844 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 09:24:43.568731 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 09:24:43.575591 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 09:24:43.578904 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 09:24:43.582151 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 09:24:43.585315 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 09:24:43.592106 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 09:24:43.595655 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 09:24:43.598465 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 09:24:43.605517 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 09:24:43.609110 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 09:24:43.612488 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1504 09:24:43.618725 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 09:24:43.622358 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1506 09:24:43.625856 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1507 09:24:43.632214 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 09:24:43.635714 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 09:24:43.639191 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 09:24:43.645438 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 09:24:43.648807 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 09:24:43.652088 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 09:24:43.659051 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1514 09:24:43.662338 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1515 09:24:43.665700 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 09:24:43.668897 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 09:24:43.675713 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 09:24:43.679107 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 09:24:43.682564 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 09:24:43.688986 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1521 09:24:43.692345 0 10 4 | B1->B0 | 3333 2d2d | 1 1 | (0 0) (1 1)
1522 09:24:43.695652 0 10 8 | B1->B0 | 2424 2323 | 1 0 | (0 0) (1 0)
1523 09:24:43.702377 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 09:24:43.705850 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 09:24:43.709250 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 09:24:43.715634 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 09:24:43.719078 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 09:24:43.722591 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1529 09:24:43.729556 0 11 4 | B1->B0 | 2828 3838 | 0 1 | (0 0) (0 0)
1530 09:24:43.732300 0 11 8 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
1531 09:24:43.735756 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 09:24:43.739293 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 09:24:43.745798 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 09:24:43.749350 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 09:24:43.752187 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 09:24:43.759498 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1537 09:24:43.762895 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1538 09:24:43.765629 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 09:24:43.772773 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 09:24:43.775621 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 09:24:43.779475 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 09:24:43.786104 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 09:24:43.789337 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 09:24:43.792542 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 09:24:43.799155 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 09:24:43.802393 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 09:24:43.805750 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 09:24:43.812249 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 09:24:43.816275 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 09:24:43.819363 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 09:24:43.826161 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 09:24:43.829463 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1553 09:24:43.832800 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1554 09:24:43.835635 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 09:24:43.839254 Total UI for P1: 0, mck2ui 16
1556 09:24:43.842819 best dqsien dly found for B0: ( 0, 14, 4)
1557 09:24:43.845789 Total UI for P1: 0, mck2ui 16
1558 09:24:43.849252 best dqsien dly found for B1: ( 0, 14, 2)
1559 09:24:43.852843 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1560 09:24:43.855848 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1561 09:24:43.859322
1562 09:24:43.862902 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1563 09:24:43.865691 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1564 09:24:43.869636 [Gating] SW calibration Done
1565 09:24:43.869737 ==
1566 09:24:43.873092 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 09:24:43.875920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 09:24:43.876012 ==
1569 09:24:43.876093 RX Vref Scan: 0
1570 09:24:43.876186
1571 09:24:43.879536 RX Vref 0 -> 0, step: 1
1572 09:24:43.879625
1573 09:24:43.882493 RX Delay -130 -> 252, step: 16
1574 09:24:43.885931 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1575 09:24:43.889322 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1576 09:24:43.896053 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1577 09:24:43.899533 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1578 09:24:43.903050 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1579 09:24:43.905708 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1580 09:24:43.909266 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1581 09:24:43.912597 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1582 09:24:43.919580 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1583 09:24:43.922943 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1584 09:24:43.926412 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1585 09:24:43.929147 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1586 09:24:43.932620 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1587 09:24:43.939672 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1588 09:24:43.942642 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1589 09:24:43.946390 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1590 09:24:43.946523 ==
1591 09:24:43.949852 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 09:24:43.952771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 09:24:43.952881 ==
1594 09:24:43.956363 DQS Delay:
1595 09:24:43.956478 DQS0 = 0, DQS1 = 0
1596 09:24:43.959223 DQM Delay:
1597 09:24:43.959329 DQM0 = 92, DQM1 = 87
1598 09:24:43.959391 DQ Delay:
1599 09:24:43.962766 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1600 09:24:43.966449 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1601 09:24:43.969201 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1602 09:24:43.972734 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1603 09:24:43.972838
1604 09:24:43.972899
1605 09:24:43.975906 ==
1606 09:24:43.979826 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 09:24:43.983288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 09:24:43.983385 ==
1609 09:24:43.983446
1610 09:24:43.983501
1611 09:24:43.986244 TX Vref Scan disable
1612 09:24:43.986348 == TX Byte 0 ==
1613 09:24:43.989738 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1614 09:24:43.996788 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1615 09:24:43.996929 == TX Byte 1 ==
1616 09:24:43.999521 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1617 09:24:44.006425 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1618 09:24:44.006554 ==
1619 09:24:44.009779 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 09:24:44.013094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 09:24:44.013204 ==
1622 09:24:44.025888 TX Vref=22, minBit 1, minWin=26, winSum=437
1623 09:24:44.029110 TX Vref=24, minBit 1, minWin=26, winSum=438
1624 09:24:44.032640 TX Vref=26, minBit 1, minWin=26, winSum=444
1625 09:24:44.036103 TX Vref=28, minBit 1, minWin=26, winSum=446
1626 09:24:44.039647 TX Vref=30, minBit 2, minWin=27, winSum=451
1627 09:24:44.042468 TX Vref=32, minBit 1, minWin=27, winSum=444
1628 09:24:44.049542 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
1629 09:24:44.049674
1630 09:24:44.053051 Final TX Range 1 Vref 30
1631 09:24:44.053166
1632 09:24:44.053263 ==
1633 09:24:44.056414 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 09:24:44.059185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 09:24:44.059315 ==
1636 09:24:44.059407
1637 09:24:44.059517
1638 09:24:44.062611 TX Vref Scan disable
1639 09:24:44.066179 == TX Byte 0 ==
1640 09:24:44.069797 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1641 09:24:44.072612 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1642 09:24:44.076307 == TX Byte 1 ==
1643 09:24:44.079682 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1644 09:24:44.083179 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1645 09:24:44.083279
1646 09:24:44.086523 [DATLAT]
1647 09:24:44.086614 Freq=800, CH1 RK0
1648 09:24:44.086676
1649 09:24:44.089808 DATLAT Default: 0xa
1650 09:24:44.089919 0, 0xFFFF, sum = 0
1651 09:24:44.092658 1, 0xFFFF, sum = 0
1652 09:24:44.092785 2, 0xFFFF, sum = 0
1653 09:24:44.096330 3, 0xFFFF, sum = 0
1654 09:24:44.096450 4, 0xFFFF, sum = 0
1655 09:24:44.099761 5, 0xFFFF, sum = 0
1656 09:24:44.099858 6, 0xFFFF, sum = 0
1657 09:24:44.102570 7, 0xFFFF, sum = 0
1658 09:24:44.102668 8, 0xFFFF, sum = 0
1659 09:24:44.106133 9, 0x0, sum = 1
1660 09:24:44.106219 10, 0x0, sum = 2
1661 09:24:44.109512 11, 0x0, sum = 3
1662 09:24:44.109622 12, 0x0, sum = 4
1663 09:24:44.113132 best_step = 10
1664 09:24:44.113246
1665 09:24:44.113333 ==
1666 09:24:44.115903 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 09:24:44.119437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 09:24:44.119528 ==
1669 09:24:44.122895 RX Vref Scan: 1
1670 09:24:44.122980
1671 09:24:44.123038 Set Vref Range= 32 -> 127
1672 09:24:44.123092
1673 09:24:44.126312 RX Vref 32 -> 127, step: 1
1674 09:24:44.126389
1675 09:24:44.129818 RX Delay -79 -> 252, step: 8
1676 09:24:44.129935
1677 09:24:44.133183 Set Vref, RX VrefLevel [Byte0]: 32
1678 09:24:44.136539 [Byte1]: 32
1679 09:24:44.136634
1680 09:24:44.139641 Set Vref, RX VrefLevel [Byte0]: 33
1681 09:24:44.142830 [Byte1]: 33
1682 09:24:44.142944
1683 09:24:44.146700 Set Vref, RX VrefLevel [Byte0]: 34
1684 09:24:44.149427 [Byte1]: 34
1685 09:24:44.153498
1686 09:24:44.153612 Set Vref, RX VrefLevel [Byte0]: 35
1687 09:24:44.156845 [Byte1]: 35
1688 09:24:44.161140
1689 09:24:44.161237 Set Vref, RX VrefLevel [Byte0]: 36
1690 09:24:44.164452 [Byte1]: 36
1691 09:24:44.168623
1692 09:24:44.168721 Set Vref, RX VrefLevel [Byte0]: 37
1693 09:24:44.172110 [Byte1]: 37
1694 09:24:44.176186
1695 09:24:44.176266 Set Vref, RX VrefLevel [Byte0]: 38
1696 09:24:44.179621 [Byte1]: 38
1697 09:24:44.183965
1698 09:24:44.184072 Set Vref, RX VrefLevel [Byte0]: 39
1699 09:24:44.187436 [Byte1]: 39
1700 09:24:44.191015
1701 09:24:44.191140 Set Vref, RX VrefLevel [Byte0]: 40
1702 09:24:44.194404 [Byte1]: 40
1703 09:24:44.198966
1704 09:24:44.199100 Set Vref, RX VrefLevel [Byte0]: 41
1705 09:24:44.202166 [Byte1]: 41
1706 09:24:44.206539
1707 09:24:44.206669 Set Vref, RX VrefLevel [Byte0]: 42
1708 09:24:44.210124 [Byte1]: 42
1709 09:24:44.214171
1710 09:24:44.214286 Set Vref, RX VrefLevel [Byte0]: 43
1711 09:24:44.217769 [Byte1]: 43
1712 09:24:44.221308
1713 09:24:44.221415 Set Vref, RX VrefLevel [Byte0]: 44
1714 09:24:44.224947 [Byte1]: 44
1715 09:24:44.229192
1716 09:24:44.229293 Set Vref, RX VrefLevel [Byte0]: 45
1717 09:24:44.232744 [Byte1]: 45
1718 09:24:44.236332
1719 09:24:44.236481 Set Vref, RX VrefLevel [Byte0]: 46
1720 09:24:44.239848 [Byte1]: 46
1721 09:24:44.243899
1722 09:24:44.244024 Set Vref, RX VrefLevel [Byte0]: 47
1723 09:24:44.247516 [Byte1]: 47
1724 09:24:44.251709
1725 09:24:44.251866 Set Vref, RX VrefLevel [Byte0]: 48
1726 09:24:44.255035 [Byte1]: 48
1727 09:24:44.259197
1728 09:24:44.259399 Set Vref, RX VrefLevel [Byte0]: 49
1729 09:24:44.262628 [Byte1]: 49
1730 09:24:44.266602
1731 09:24:44.266779 Set Vref, RX VrefLevel [Byte0]: 50
1732 09:24:44.269827 [Byte1]: 50
1733 09:24:44.274433
1734 09:24:44.274623 Set Vref, RX VrefLevel [Byte0]: 51
1735 09:24:44.278026 [Byte1]: 51
1736 09:24:44.281667
1737 09:24:44.281813 Set Vref, RX VrefLevel [Byte0]: 52
1738 09:24:44.285188 [Byte1]: 52
1739 09:24:44.289479
1740 09:24:44.289612 Set Vref, RX VrefLevel [Byte0]: 53
1741 09:24:44.293092 [Byte1]: 53
1742 09:24:44.297228
1743 09:24:44.297357 Set Vref, RX VrefLevel [Byte0]: 54
1744 09:24:44.300058 [Byte1]: 54
1745 09:24:44.304275
1746 09:24:44.304401 Set Vref, RX VrefLevel [Byte0]: 55
1747 09:24:44.307933 [Byte1]: 55
1748 09:24:44.312328
1749 09:24:44.312438 Set Vref, RX VrefLevel [Byte0]: 56
1750 09:24:44.315148 [Byte1]: 56
1751 09:24:44.319478
1752 09:24:44.319601 Set Vref, RX VrefLevel [Byte0]: 57
1753 09:24:44.323040 [Byte1]: 57
1754 09:24:44.327329
1755 09:24:44.327436 Set Vref, RX VrefLevel [Byte0]: 58
1756 09:24:44.330186 [Byte1]: 58
1757 09:24:44.334529
1758 09:24:44.334631 Set Vref, RX VrefLevel [Byte0]: 59
1759 09:24:44.338034 [Byte1]: 59
1760 09:24:44.342302
1761 09:24:44.342403 Set Vref, RX VrefLevel [Byte0]: 60
1762 09:24:44.345891 [Byte1]: 60
1763 09:24:44.350124
1764 09:24:44.350243 Set Vref, RX VrefLevel [Byte0]: 61
1765 09:24:44.352824 [Byte1]: 61
1766 09:24:44.357642
1767 09:24:44.357778 Set Vref, RX VrefLevel [Byte0]: 62
1768 09:24:44.360274 [Byte1]: 62
1769 09:24:44.365050
1770 09:24:44.365177 Set Vref, RX VrefLevel [Byte0]: 63
1771 09:24:44.367851 [Byte1]: 63
1772 09:24:44.372208
1773 09:24:44.372329 Set Vref, RX VrefLevel [Byte0]: 64
1774 09:24:44.375588 [Byte1]: 64
1775 09:24:44.380194
1776 09:24:44.380323 Set Vref, RX VrefLevel [Byte0]: 65
1777 09:24:44.383476 [Byte1]: 65
1778 09:24:44.387313
1779 09:24:44.387433 Set Vref, RX VrefLevel [Byte0]: 66
1780 09:24:44.390849 [Byte1]: 66
1781 09:24:44.395119
1782 09:24:44.395249 Set Vref, RX VrefLevel [Byte0]: 67
1783 09:24:44.398063 [Byte1]: 67
1784 09:24:44.402325
1785 09:24:44.402438 Set Vref, RX VrefLevel [Byte0]: 68
1786 09:24:44.405824 [Byte1]: 68
1787 09:24:44.410082
1788 09:24:44.410219 Set Vref, RX VrefLevel [Byte0]: 69
1789 09:24:44.413647 [Byte1]: 69
1790 09:24:44.417996
1791 09:24:44.418126 Set Vref, RX VrefLevel [Byte0]: 70
1792 09:24:44.420864 [Byte1]: 70
1793 09:24:44.425114
1794 09:24:44.425237 Set Vref, RX VrefLevel [Byte0]: 71
1795 09:24:44.428513 [Byte1]: 71
1796 09:24:44.433086
1797 09:24:44.433218 Set Vref, RX VrefLevel [Byte0]: 72
1798 09:24:44.436224 [Byte1]: 72
1799 09:24:44.440744
1800 09:24:44.440873 Set Vref, RX VrefLevel [Byte0]: 73
1801 09:24:44.443679 [Byte1]: 73
1802 09:24:44.448047
1803 09:24:44.448164 Set Vref, RX VrefLevel [Byte0]: 74
1804 09:24:44.451252 [Byte1]: 74
1805 09:24:44.455688
1806 09:24:44.455814 Final RX Vref Byte 0 = 59 to rank0
1807 09:24:44.458445 Final RX Vref Byte 1 = 53 to rank0
1808 09:24:44.461894 Final RX Vref Byte 0 = 59 to rank1
1809 09:24:44.465256 Final RX Vref Byte 1 = 53 to rank1==
1810 09:24:44.468833 Dram Type= 6, Freq= 0, CH_1, rank 0
1811 09:24:44.472266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 09:24:44.475559 ==
1813 09:24:44.475681 DQS Delay:
1814 09:24:44.475775 DQS0 = 0, DQS1 = 0
1815 09:24:44.479133 DQM Delay:
1816 09:24:44.479242 DQM0 = 95, DQM1 = 89
1817 09:24:44.482067 DQ Delay:
1818 09:24:44.485498 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1819 09:24:44.488851 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1820 09:24:44.492418 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =84
1821 09:24:44.495745 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1822 09:24:44.495900
1823 09:24:44.495976
1824 09:24:44.502450 [DQSOSCAuto] RK0, (LSB)MR18= 0x3450, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1825 09:24:44.505389 CH1 RK0: MR19=606, MR18=3450
1826 09:24:44.512644 CH1_RK0: MR19=0x606, MR18=0x3450, DQSOSC=389, MR23=63, INC=97, DEC=65
1827 09:24:44.512802
1828 09:24:44.515531 ----->DramcWriteLeveling(PI) begin...
1829 09:24:44.515645 ==
1830 09:24:44.519112 Dram Type= 6, Freq= 0, CH_1, rank 1
1831 09:24:44.522656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1832 09:24:44.522803 ==
1833 09:24:44.525390 Write leveling (Byte 0): 26 => 26
1834 09:24:44.528945 Write leveling (Byte 1): 30 => 30
1835 09:24:44.532463 DramcWriteLeveling(PI) end<-----
1836 09:24:44.532601
1837 09:24:44.532692 ==
1838 09:24:44.536043 Dram Type= 6, Freq= 0, CH_1, rank 1
1839 09:24:44.538846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 09:24:44.538954 ==
1841 09:24:44.542349 [Gating] SW mode calibration
1842 09:24:44.549336 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1843 09:24:44.555819 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1844 09:24:44.559205 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1845 09:24:44.562197 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1846 09:24:44.569328 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 09:24:44.572278 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 09:24:44.575511 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 09:24:44.582122 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 09:24:44.586082 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 09:24:44.588731 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 09:24:44.595799 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 09:24:44.599491 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 09:24:44.602368 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 09:24:44.609195 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 09:24:44.612064 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 09:24:44.615567 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 09:24:44.619131 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 09:24:44.625738 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 09:24:44.629432 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 09:24:44.632336 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1862 09:24:44.639388 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 09:24:44.642134 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 09:24:44.645636 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 09:24:44.652625 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 09:24:44.656049 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 09:24:44.659622 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 09:24:44.666030 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 09:24:44.669408 0 9 4 | B1->B0 | 2626 2322 | 0 1 | (0 0) (0 0)
1870 09:24:44.672879 0 9 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1871 09:24:44.679031 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 09:24:44.682478 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 09:24:44.685675 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 09:24:44.689485 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 09:24:44.695618 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 09:24:44.699548 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 09:24:44.702677 0 10 4 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (1 0)
1878 09:24:44.709468 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 09:24:44.712406 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 09:24:44.715997 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 09:24:44.722583 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 09:24:44.726265 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 09:24:44.729516 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 09:24:44.735990 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 09:24:44.739612 0 11 4 | B1->B0 | 3c3c 3030 | 0 0 | (0 0) (0 0)
1886 09:24:44.742512 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1887 09:24:44.749436 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 09:24:44.752982 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 09:24:44.755862 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 09:24:44.762821 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 09:24:44.766382 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 09:24:44.769284 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 09:24:44.772856 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1894 09:24:44.779364 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 09:24:44.782927 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 09:24:44.786427 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 09:24:44.792898 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 09:24:44.796238 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 09:24:44.799738 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 09:24:44.806382 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 09:24:44.809700 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 09:24:44.813218 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 09:24:44.819849 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 09:24:44.823146 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 09:24:44.826390 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 09:24:44.833217 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 09:24:44.836515 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 09:24:44.839683 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1909 09:24:44.842842 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1910 09:24:44.849711 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 09:24:44.853195 Total UI for P1: 0, mck2ui 16
1912 09:24:44.856693 best dqsien dly found for B0: ( 0, 14, 4)
1913 09:24:44.860240 Total UI for P1: 0, mck2ui 16
1914 09:24:44.862983 best dqsien dly found for B1: ( 0, 14, 2)
1915 09:24:44.866424 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1916 09:24:44.870025 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1917 09:24:44.870161
1918 09:24:44.873642 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1919 09:24:44.876459 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1920 09:24:44.879904 [Gating] SW calibration Done
1921 09:24:44.880018 ==
1922 09:24:44.883450 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 09:24:44.886354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 09:24:44.886477 ==
1925 09:24:44.890045 RX Vref Scan: 0
1926 09:24:44.890162
1927 09:24:44.890260 RX Vref 0 -> 0, step: 1
1928 09:24:44.890345
1929 09:24:44.893650 RX Delay -130 -> 252, step: 16
1930 09:24:44.896549 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1931 09:24:44.903650 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1932 09:24:44.906614 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1933 09:24:44.910061 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1934 09:24:44.913409 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1935 09:24:44.916553 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1936 09:24:44.920386 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1937 09:24:44.926702 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1938 09:24:44.930189 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1939 09:24:44.933492 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1940 09:24:44.936865 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1941 09:24:44.940365 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1942 09:24:44.946762 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1943 09:24:44.950223 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1944 09:24:44.953502 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1945 09:24:44.956849 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1946 09:24:44.956940 ==
1947 09:24:44.960072 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 09:24:44.967053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 09:24:44.967208 ==
1950 09:24:44.967299 DQS Delay:
1951 09:24:44.970350 DQS0 = 0, DQS1 = 0
1952 09:24:44.970459 DQM Delay:
1953 09:24:44.970537 DQM0 = 92, DQM1 = 89
1954 09:24:44.973201 DQ Delay:
1955 09:24:44.976800 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1956 09:24:44.980194 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1957 09:24:44.983784 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1958 09:24:44.986574 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1959 09:24:44.986697
1960 09:24:44.986785
1961 09:24:44.986869 ==
1962 09:24:44.990192 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 09:24:44.993751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 09:24:44.993853 ==
1965 09:24:44.993918
1966 09:24:44.993974
1967 09:24:44.996539 TX Vref Scan disable
1968 09:24:45.000085 == TX Byte 0 ==
1969 09:24:45.003589 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1970 09:24:45.007242 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1971 09:24:45.010060 == TX Byte 1 ==
1972 09:24:45.013659 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1973 09:24:45.017171 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1974 09:24:45.017295 ==
1975 09:24:45.020030 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 09:24:45.023390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 09:24:45.023508 ==
1978 09:24:45.038187 TX Vref=22, minBit 2, minWin=26, winSum=442
1979 09:24:45.041498 TX Vref=24, minBit 0, minWin=27, winSum=446
1980 09:24:45.045005 TX Vref=26, minBit 0, minWin=27, winSum=446
1981 09:24:45.048626 TX Vref=28, minBit 0, minWin=27, winSum=449
1982 09:24:45.051506 TX Vref=30, minBit 2, minWin=27, winSum=451
1983 09:24:45.055148 TX Vref=32, minBit 2, minWin=27, winSum=449
1984 09:24:45.061350 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
1985 09:24:45.061488
1986 09:24:45.064779 Final TX Range 1 Vref 30
1987 09:24:45.064931
1988 09:24:45.065033 ==
1989 09:24:45.068252 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 09:24:45.071774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 09:24:45.071897 ==
1992 09:24:45.071985
1993 09:24:45.072068
1994 09:24:45.075121 TX Vref Scan disable
1995 09:24:45.078200 == TX Byte 0 ==
1996 09:24:45.081581 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1997 09:24:45.084731 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1998 09:24:45.088291 == TX Byte 1 ==
1999 09:24:45.091510 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2000 09:24:45.094685 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2001 09:24:45.094784
2002 09:24:45.098295 [DATLAT]
2003 09:24:45.098392 Freq=800, CH1 RK1
2004 09:24:45.098454
2005 09:24:45.101737 DATLAT Default: 0xa
2006 09:24:45.101851 0, 0xFFFF, sum = 0
2007 09:24:45.104625 1, 0xFFFF, sum = 0
2008 09:24:45.104714 2, 0xFFFF, sum = 0
2009 09:24:45.108160 3, 0xFFFF, sum = 0
2010 09:24:45.108273 4, 0xFFFF, sum = 0
2011 09:24:45.111632 5, 0xFFFF, sum = 0
2012 09:24:45.111737 6, 0xFFFF, sum = 0
2013 09:24:45.115206 7, 0xFFFF, sum = 0
2014 09:24:45.115285 8, 0xFFFF, sum = 0
2015 09:24:45.118151 9, 0x0, sum = 1
2016 09:24:45.118274 10, 0x0, sum = 2
2017 09:24:45.121654 11, 0x0, sum = 3
2018 09:24:45.121764 12, 0x0, sum = 4
2019 09:24:45.125192 best_step = 10
2020 09:24:45.125288
2021 09:24:45.125376 ==
2022 09:24:45.128748 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 09:24:45.131565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 09:24:45.131667 ==
2025 09:24:45.135112 RX Vref Scan: 0
2026 09:24:45.135205
2027 09:24:45.135266 RX Vref 0 -> 0, step: 1
2028 09:24:45.135322
2029 09:24:45.138477 RX Delay -79 -> 252, step: 8
2030 09:24:45.145136 iDelay=209, Bit 0, Center 100 (1 ~ 200) 200
2031 09:24:45.148413 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2032 09:24:45.152300 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2033 09:24:45.155572 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2034 09:24:45.158344 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2035 09:24:45.161913 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2036 09:24:45.168850 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2037 09:24:45.171733 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2038 09:24:45.175190 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2039 09:24:45.178744 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2040 09:24:45.181534 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2041 09:24:45.185097 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2042 09:24:45.192013 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2043 09:24:45.195362 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2044 09:24:45.198840 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2045 09:24:45.201605 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2046 09:24:45.201721 ==
2047 09:24:45.205062 Dram Type= 6, Freq= 0, CH_1, rank 1
2048 09:24:45.211737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2049 09:24:45.211886 ==
2050 09:24:45.211981 DQS Delay:
2051 09:24:45.212065 DQS0 = 0, DQS1 = 0
2052 09:24:45.214959 DQM Delay:
2053 09:24:45.215058 DQM0 = 97, DQM1 = 91
2054 09:24:45.218989 DQ Delay:
2055 09:24:45.221735 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
2056 09:24:45.225322 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2057 09:24:45.228813 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2058 09:24:45.231590 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2059 09:24:45.231701
2060 09:24:45.231788
2061 09:24:45.238537 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
2062 09:24:45.242047 CH1 RK1: MR19=606, MR18=4E17
2063 09:24:45.248982 CH1_RK1: MR19=0x606, MR18=0x4E17, DQSOSC=390, MR23=63, INC=97, DEC=64
2064 09:24:45.251681 [RxdqsGatingPostProcess] freq 800
2065 09:24:45.255203 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2066 09:24:45.258628 Pre-setting of DQS Precalculation
2067 09:24:45.265441 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2068 09:24:45.272358 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2069 09:24:45.278781 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2070 09:24:45.278919
2071 09:24:45.279016
2072 09:24:45.282332 [Calibration Summary] 1600 Mbps
2073 09:24:45.282435 CH 0, Rank 0
2074 09:24:45.285273 SW Impedance : PASS
2075 09:24:45.288747 DUTY Scan : NO K
2076 09:24:45.288856 ZQ Calibration : PASS
2077 09:24:45.292251 Jitter Meter : NO K
2078 09:24:45.295678 CBT Training : PASS
2079 09:24:45.295795 Write leveling : PASS
2080 09:24:45.299111 RX DQS gating : PASS
2081 09:24:45.299224 RX DQ/DQS(RDDQC) : PASS
2082 09:24:45.302512 TX DQ/DQS : PASS
2083 09:24:45.305354 RX DATLAT : PASS
2084 09:24:45.305437 RX DQ/DQS(Engine): PASS
2085 09:24:45.309067 TX OE : NO K
2086 09:24:45.309172 All Pass.
2087 09:24:45.309256
2088 09:24:45.312553 CH 0, Rank 1
2089 09:24:45.312656 SW Impedance : PASS
2090 09:24:45.315374 DUTY Scan : NO K
2091 09:24:45.318837 ZQ Calibration : PASS
2092 09:24:45.318959 Jitter Meter : NO K
2093 09:24:45.322463 CBT Training : PASS
2094 09:24:45.325841 Write leveling : PASS
2095 09:24:45.325971 RX DQS gating : PASS
2096 09:24:45.329083 RX DQ/DQS(RDDQC) : PASS
2097 09:24:45.332472 TX DQ/DQS : PASS
2098 09:24:45.332602 RX DATLAT : PASS
2099 09:24:45.335670 RX DQ/DQS(Engine): PASS
2100 09:24:45.335778 TX OE : NO K
2101 09:24:45.339261 All Pass.
2102 09:24:45.339386
2103 09:24:45.339481 CH 1, Rank 0
2104 09:24:45.342029 SW Impedance : PASS
2105 09:24:45.342107 DUTY Scan : NO K
2106 09:24:45.345455 ZQ Calibration : PASS
2107 09:24:45.349006 Jitter Meter : NO K
2108 09:24:45.349120 CBT Training : PASS
2109 09:24:45.352451 Write leveling : PASS
2110 09:24:45.355675 RX DQS gating : PASS
2111 09:24:45.355786 RX DQ/DQS(RDDQC) : PASS
2112 09:24:45.359226 TX DQ/DQS : PASS
2113 09:24:45.362069 RX DATLAT : PASS
2114 09:24:45.362195 RX DQ/DQS(Engine): PASS
2115 09:24:45.365610 TX OE : NO K
2116 09:24:45.365700 All Pass.
2117 09:24:45.365762
2118 09:24:45.368875 CH 1, Rank 1
2119 09:24:45.368959 SW Impedance : PASS
2120 09:24:45.372087 DUTY Scan : NO K
2121 09:24:45.375944 ZQ Calibration : PASS
2122 09:24:45.376075 Jitter Meter : NO K
2123 09:24:45.378746 CBT Training : PASS
2124 09:24:45.378851 Write leveling : PASS
2125 09:24:45.382233 RX DQS gating : PASS
2126 09:24:45.385725 RX DQ/DQS(RDDQC) : PASS
2127 09:24:45.385840 TX DQ/DQS : PASS
2128 09:24:45.389309 RX DATLAT : PASS
2129 09:24:45.392150 RX DQ/DQS(Engine): PASS
2130 09:24:45.392298 TX OE : NO K
2131 09:24:45.395627 All Pass.
2132 09:24:45.395762
2133 09:24:45.395854 DramC Write-DBI off
2134 09:24:45.399013 PER_BANK_REFRESH: Hybrid Mode
2135 09:24:45.399140 TX_TRACKING: ON
2136 09:24:45.405689 [GetDramInforAfterCalByMRR] Vendor 6.
2137 09:24:45.409209 [GetDramInforAfterCalByMRR] Revision 606.
2138 09:24:45.412055 [GetDramInforAfterCalByMRR] Revision 2 0.
2139 09:24:45.412176 MR0 0x3b3b
2140 09:24:45.412262 MR8 0x5151
2141 09:24:45.415588 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2142 09:24:45.415707
2143 09:24:45.419214 MR0 0x3b3b
2144 09:24:45.419334 MR8 0x5151
2145 09:24:45.422837 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2146 09:24:45.422946
2147 09:24:45.432806 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2148 09:24:45.435711 [FAST_K] Save calibration result to emmc
2149 09:24:45.439123 [FAST_K] Save calibration result to emmc
2150 09:24:45.442516 dram_init: config_dvfs: 1
2151 09:24:45.445855 dramc_set_vcore_voltage set vcore to 662500
2152 09:24:45.449187 Read voltage for 1200, 2
2153 09:24:45.449312 Vio18 = 0
2154 09:24:45.449414 Vcore = 662500
2155 09:24:45.452342 Vdram = 0
2156 09:24:45.452444 Vddq = 0
2157 09:24:45.452536 Vmddr = 0
2158 09:24:45.458948 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2159 09:24:45.462194 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2160 09:24:45.465456 MEM_TYPE=3, freq_sel=15
2161 09:24:45.468948 sv_algorithm_assistance_LP4_1600
2162 09:24:45.472472 ============ PULL DRAM RESETB DOWN ============
2163 09:24:45.476004 ========== PULL DRAM RESETB DOWN end =========
2164 09:24:45.482704 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2165 09:24:45.486037 ===================================
2166 09:24:45.486161 LPDDR4 DRAM CONFIGURATION
2167 09:24:45.488772 ===================================
2168 09:24:45.492241 EX_ROW_EN[0] = 0x0
2169 09:24:45.495800 EX_ROW_EN[1] = 0x0
2170 09:24:45.495942 LP4Y_EN = 0x0
2171 09:24:45.499446 WORK_FSP = 0x0
2172 09:24:45.499621 WL = 0x4
2173 09:24:45.502219 RL = 0x4
2174 09:24:45.502341 BL = 0x2
2175 09:24:45.505629 RPST = 0x0
2176 09:24:45.505714 RD_PRE = 0x0
2177 09:24:45.509212 WR_PRE = 0x1
2178 09:24:45.509324 WR_PST = 0x0
2179 09:24:45.512580 DBI_WR = 0x0
2180 09:24:45.512691 DBI_RD = 0x0
2181 09:24:45.515518 OTF = 0x1
2182 09:24:45.519051 ===================================
2183 09:24:45.522548 ===================================
2184 09:24:45.522670 ANA top config
2185 09:24:45.526071 ===================================
2186 09:24:45.528825 DLL_ASYNC_EN = 0
2187 09:24:45.532416 ALL_SLAVE_EN = 0
2188 09:24:45.532529 NEW_RANK_MODE = 1
2189 09:24:45.536041 DLL_IDLE_MODE = 1
2190 09:24:45.539539 LP45_APHY_COMB_EN = 1
2191 09:24:45.542379 TX_ODT_DIS = 1
2192 09:24:45.545948 NEW_8X_MODE = 1
2193 09:24:45.549418 ===================================
2194 09:24:45.552907 ===================================
2195 09:24:45.553022 data_rate = 2400
2196 09:24:45.555744 CKR = 1
2197 09:24:45.559195 DQ_P2S_RATIO = 8
2198 09:24:45.562653 ===================================
2199 09:24:45.565988 CA_P2S_RATIO = 8
2200 09:24:45.569256 DQ_CA_OPEN = 0
2201 09:24:45.572352 DQ_SEMI_OPEN = 0
2202 09:24:45.572468 CA_SEMI_OPEN = 0
2203 09:24:45.575880 CA_FULL_RATE = 0
2204 09:24:45.579005 DQ_CKDIV4_EN = 0
2205 09:24:45.582903 CA_CKDIV4_EN = 0
2206 09:24:45.586258 CA_PREDIV_EN = 0
2207 09:24:45.586392 PH8_DLY = 17
2208 09:24:45.589649 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2209 09:24:45.592875 DQ_AAMCK_DIV = 4
2210 09:24:45.596223 CA_AAMCK_DIV = 4
2211 09:24:45.599039 CA_ADMCK_DIV = 4
2212 09:24:45.602561 DQ_TRACK_CA_EN = 0
2213 09:24:45.605889 CA_PICK = 1200
2214 09:24:45.606029 CA_MCKIO = 1200
2215 09:24:45.609475 MCKIO_SEMI = 0
2216 09:24:45.612955 PLL_FREQ = 2366
2217 09:24:45.616392 DQ_UI_PI_RATIO = 32
2218 09:24:45.619712 CA_UI_PI_RATIO = 0
2219 09:24:45.622555 ===================================
2220 09:24:45.626085 ===================================
2221 09:24:45.629538 memory_type:LPDDR4
2222 09:24:45.629669 GP_NUM : 10
2223 09:24:45.632456 SRAM_EN : 1
2224 09:24:45.632559 MD32_EN : 0
2225 09:24:45.636036 ===================================
2226 09:24:45.639620 [ANA_INIT] >>>>>>>>>>>>>>
2227 09:24:45.643048 <<<<<< [CONFIGURE PHASE]: ANA_TX
2228 09:24:45.645767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2229 09:24:45.649371 ===================================
2230 09:24:45.652955 data_rate = 2400,PCW = 0X5b00
2231 09:24:45.655727 ===================================
2232 09:24:45.659183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2233 09:24:45.662713 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2234 09:24:45.669159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2235 09:24:45.672682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2236 09:24:45.676145 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2237 09:24:45.682513 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2238 09:24:45.682621 [ANA_INIT] flow start
2239 09:24:45.685838 [ANA_INIT] PLL >>>>>>>>
2240 09:24:45.685932 [ANA_INIT] PLL <<<<<<<<
2241 09:24:45.689282 [ANA_INIT] MIDPI >>>>>>>>
2242 09:24:45.692472 [ANA_INIT] MIDPI <<<<<<<<
2243 09:24:45.696377 [ANA_INIT] DLL >>>>>>>>
2244 09:24:45.696540 [ANA_INIT] DLL <<<<<<<<
2245 09:24:45.699406 [ANA_INIT] flow end
2246 09:24:45.702481 ============ LP4 DIFF to SE enter ============
2247 09:24:45.705948 ============ LP4 DIFF to SE exit ============
2248 09:24:45.709712 [ANA_INIT] <<<<<<<<<<<<<
2249 09:24:45.712962 [Flow] Enable top DCM control >>>>>
2250 09:24:45.716186 [Flow] Enable top DCM control <<<<<
2251 09:24:45.719345 Enable DLL master slave shuffle
2252 09:24:45.722561 ==============================================================
2253 09:24:45.725982 Gating Mode config
2254 09:24:45.732876 ==============================================================
2255 09:24:45.733028 Config description:
2256 09:24:45.743159 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2257 09:24:45.749528 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2258 09:24:45.755950 SELPH_MODE 0: By rank 1: By Phase
2259 09:24:45.759447 ==============================================================
2260 09:24:45.762862 GAT_TRACK_EN = 1
2261 09:24:45.766454 RX_GATING_MODE = 2
2262 09:24:45.769360 RX_GATING_TRACK_MODE = 2
2263 09:24:45.772968 SELPH_MODE = 1
2264 09:24:45.775870 PICG_EARLY_EN = 1
2265 09:24:45.779333 VALID_LAT_VALUE = 1
2266 09:24:45.783017 ==============================================================
2267 09:24:45.786478 Enter into Gating configuration >>>>
2268 09:24:45.789310 Exit from Gating configuration <<<<
2269 09:24:45.792715 Enter into DVFS_PRE_config >>>>>
2270 09:24:45.806138 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2271 09:24:45.806274 Exit from DVFS_PRE_config <<<<<
2272 09:24:45.809712 Enter into PICG configuration >>>>
2273 09:24:45.813215 Exit from PICG configuration <<<<
2274 09:24:45.816028 [RX_INPUT] configuration >>>>>
2275 09:24:45.819459 [RX_INPUT] configuration <<<<<
2276 09:24:45.826148 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2277 09:24:45.829662 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2278 09:24:45.835974 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2279 09:24:45.842704 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2280 09:24:45.849611 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2281 09:24:45.856209 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2282 09:24:45.859650 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2283 09:24:45.863250 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2284 09:24:45.866557 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2285 09:24:45.873091 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2286 09:24:45.876697 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2287 09:24:45.879469 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2288 09:24:45.883079 ===================================
2289 09:24:45.886716 LPDDR4 DRAM CONFIGURATION
2290 09:24:45.889491 ===================================
2291 09:24:45.889612 EX_ROW_EN[0] = 0x0
2292 09:24:45.893187 EX_ROW_EN[1] = 0x0
2293 09:24:45.893301 LP4Y_EN = 0x0
2294 09:24:45.896782 WORK_FSP = 0x0
2295 09:24:45.896953 WL = 0x4
2296 09:24:45.899498 RL = 0x4
2297 09:24:45.902958 BL = 0x2
2298 09:24:45.903080 RPST = 0x0
2299 09:24:45.906535 RD_PRE = 0x0
2300 09:24:45.906681 WR_PRE = 0x1
2301 09:24:45.910035 WR_PST = 0x0
2302 09:24:45.910142 DBI_WR = 0x0
2303 09:24:45.912822 DBI_RD = 0x0
2304 09:24:45.912937 OTF = 0x1
2305 09:24:45.916434 ===================================
2306 09:24:45.919917 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2307 09:24:45.922728 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2308 09:24:45.929815 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2309 09:24:45.933414 ===================================
2310 09:24:45.936386 LPDDR4 DRAM CONFIGURATION
2311 09:24:45.939898 ===================================
2312 09:24:45.940036 EX_ROW_EN[0] = 0x10
2313 09:24:45.943311 EX_ROW_EN[1] = 0x0
2314 09:24:45.943443 LP4Y_EN = 0x0
2315 09:24:45.946817 WORK_FSP = 0x0
2316 09:24:45.946964 WL = 0x4
2317 09:24:45.949518 RL = 0x4
2318 09:24:45.949686 BL = 0x2
2319 09:24:45.953059 RPST = 0x0
2320 09:24:45.953218 RD_PRE = 0x0
2321 09:24:45.956497 WR_PRE = 0x1
2322 09:24:45.956616 WR_PST = 0x0
2323 09:24:45.959914 DBI_WR = 0x0
2324 09:24:45.960055 DBI_RD = 0x0
2325 09:24:45.963498 OTF = 0x1
2326 09:24:45.966972 ===================================
2327 09:24:45.973094 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2328 09:24:45.973244 ==
2329 09:24:45.976942 Dram Type= 6, Freq= 0, CH_0, rank 0
2330 09:24:45.980103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2331 09:24:45.980226 ==
2332 09:24:45.983155 [Duty_Offset_Calibration]
2333 09:24:45.983276 B0:2 B1:1 CA:1
2334 09:24:45.983362
2335 09:24:45.986707 [DutyScan_Calibration_Flow] k_type=0
2336 09:24:45.997339
2337 09:24:45.997482 ==CLK 0==
2338 09:24:46.000129 Final CLK duty delay cell = 0
2339 09:24:46.003514 [0] MAX Duty = 5218%(X100), DQS PI = 24
2340 09:24:46.006963 [0] MIN Duty = 4875%(X100), DQS PI = 0
2341 09:24:46.007122 [0] AVG Duty = 5046%(X100)
2342 09:24:46.007214
2343 09:24:46.010305 CH0 CLK Duty spec in!! Max-Min= 343%
2344 09:24:46.017306 [DutyScan_Calibration_Flow] ====Done====
2345 09:24:46.017489
2346 09:24:46.020165 [DutyScan_Calibration_Flow] k_type=1
2347 09:24:46.035603
2348 09:24:46.035776 ==DQS 0 ==
2349 09:24:46.039123 Final DQS duty delay cell = -4
2350 09:24:46.042007 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2351 09:24:46.045400 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2352 09:24:46.048773 [-4] AVG Duty = 4937%(X100)
2353 09:24:46.048874
2354 09:24:46.048936 ==DQS 1 ==
2355 09:24:46.052163 Final DQS duty delay cell = 0
2356 09:24:46.055598 [0] MAX Duty = 5156%(X100), DQS PI = 0
2357 09:24:46.058996 [0] MIN Duty = 5000%(X100), DQS PI = 32
2358 09:24:46.062433 [0] AVG Duty = 5078%(X100)
2359 09:24:46.062543
2360 09:24:46.065872 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2361 09:24:46.066001
2362 09:24:46.069287 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2363 09:24:46.072152 [DutyScan_Calibration_Flow] ====Done====
2364 09:24:46.072243
2365 09:24:46.075735 [DutyScan_Calibration_Flow] k_type=3
2366 09:24:46.092613
2367 09:24:46.092759 ==DQM 0 ==
2368 09:24:46.095873 Final DQM duty delay cell = 0
2369 09:24:46.099271 [0] MAX Duty = 5156%(X100), DQS PI = 30
2370 09:24:46.102433 [0] MIN Duty = 4875%(X100), DQS PI = 58
2371 09:24:46.102561 [0] AVG Duty = 5015%(X100)
2372 09:24:46.105536
2373 09:24:46.105650 ==DQM 1 ==
2374 09:24:46.109238 Final DQM duty delay cell = 0
2375 09:24:46.112342 [0] MAX Duty = 5093%(X100), DQS PI = 0
2376 09:24:46.115562 [0] MIN Duty = 5031%(X100), DQS PI = 14
2377 09:24:46.115694 [0] AVG Duty = 5062%(X100)
2378 09:24:46.118912
2379 09:24:46.122031 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2380 09:24:46.122143
2381 09:24:46.125782 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2382 09:24:46.128658 [DutyScan_Calibration_Flow] ====Done====
2383 09:24:46.128800
2384 09:24:46.132383 [DutyScan_Calibration_Flow] k_type=2
2385 09:24:46.148654
2386 09:24:46.148809 ==DQ 0 ==
2387 09:24:46.152202 Final DQ duty delay cell = 0
2388 09:24:46.155697 [0] MAX Duty = 5062%(X100), DQS PI = 32
2389 09:24:46.158483 [0] MIN Duty = 4844%(X100), DQS PI = 0
2390 09:24:46.158575 [0] AVG Duty = 4953%(X100)
2391 09:24:46.158636
2392 09:24:46.161818 ==DQ 1 ==
2393 09:24:46.165163 Final DQ duty delay cell = 0
2394 09:24:46.168520 [0] MAX Duty = 5093%(X100), DQS PI = 24
2395 09:24:46.172393 [0] MIN Duty = 4907%(X100), DQS PI = 36
2396 09:24:46.172498 [0] AVG Duty = 5000%(X100)
2397 09:24:46.172559
2398 09:24:46.175200 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2399 09:24:46.175316
2400 09:24:46.178799 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2401 09:24:46.185307 [DutyScan_Calibration_Flow] ====Done====
2402 09:24:46.185426 ==
2403 09:24:46.188779 Dram Type= 6, Freq= 0, CH_1, rank 0
2404 09:24:46.192137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2405 09:24:46.192230 ==
2406 09:24:46.195591 [Duty_Offset_Calibration]
2407 09:24:46.195681 B0:1 B1:0 CA:1
2408 09:24:46.195740
2409 09:24:46.198572 [DutyScan_Calibration_Flow] k_type=0
2410 09:24:46.207742
2411 09:24:46.207908 ==CLK 0==
2412 09:24:46.211191 Final CLK duty delay cell = -4
2413 09:24:46.214643 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2414 09:24:46.218110 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2415 09:24:46.221604 [-4] AVG Duty = 4969%(X100)
2416 09:24:46.221743
2417 09:24:46.224471 CH1 CLK Duty spec in!! Max-Min= 124%
2418 09:24:46.227947 [DutyScan_Calibration_Flow] ====Done====
2419 09:24:46.228071
2420 09:24:46.231452 [DutyScan_Calibration_Flow] k_type=1
2421 09:24:46.247142
2422 09:24:46.247286 ==DQS 0 ==
2423 09:24:46.250847 Final DQS duty delay cell = 0
2424 09:24:46.254410 [0] MAX Duty = 5062%(X100), DQS PI = 20
2425 09:24:46.257295 [0] MIN Duty = 4875%(X100), DQS PI = 0
2426 09:24:46.257436 [0] AVG Duty = 4968%(X100)
2427 09:24:46.257527
2428 09:24:46.260842 ==DQS 1 ==
2429 09:24:46.264370 Final DQS duty delay cell = 0
2430 09:24:46.267711 [0] MAX Duty = 5187%(X100), DQS PI = 18
2431 09:24:46.271270 [0] MIN Duty = 4938%(X100), DQS PI = 10
2432 09:24:46.271430 [0] AVG Duty = 5062%(X100)
2433 09:24:46.271525
2434 09:24:46.277388 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2435 09:24:46.277564
2436 09:24:46.281301 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2437 09:24:46.284682 [DutyScan_Calibration_Flow] ====Done====
2438 09:24:46.284796
2439 09:24:46.287572 [DutyScan_Calibration_Flow] k_type=3
2440 09:24:46.304186
2441 09:24:46.304337 ==DQM 0 ==
2442 09:24:46.307146 Final DQM duty delay cell = 0
2443 09:24:46.310631 [0] MAX Duty = 5156%(X100), DQS PI = 6
2444 09:24:46.314191 [0] MIN Duty = 5031%(X100), DQS PI = 0
2445 09:24:46.314328 [0] AVG Duty = 5093%(X100)
2446 09:24:46.314416
2447 09:24:46.317649 ==DQM 1 ==
2448 09:24:46.320921 Final DQM duty delay cell = 0
2449 09:24:46.324319 [0] MAX Duty = 5031%(X100), DQS PI = 26
2450 09:24:46.327156 [0] MIN Duty = 4875%(X100), DQS PI = 36
2451 09:24:46.327288 [0] AVG Duty = 4953%(X100)
2452 09:24:46.327402
2453 09:24:46.334252 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2454 09:24:46.334439
2455 09:24:46.337719 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2456 09:24:46.340530 [DutyScan_Calibration_Flow] ====Done====
2457 09:24:46.340692
2458 09:24:46.344146 [DutyScan_Calibration_Flow] k_type=2
2459 09:24:46.359953
2460 09:24:46.360142 ==DQ 0 ==
2461 09:24:46.363228 Final DQ duty delay cell = -4
2462 09:24:46.366536 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2463 09:24:46.369773 [-4] MIN Duty = 4906%(X100), DQS PI = 38
2464 09:24:46.373106 [-4] AVG Duty = 4984%(X100)
2465 09:24:46.373243
2466 09:24:46.373343 ==DQ 1 ==
2467 09:24:46.376194 Final DQ duty delay cell = 0
2468 09:24:46.379661 [0] MAX Duty = 5125%(X100), DQS PI = 20
2469 09:24:46.383129 [0] MIN Duty = 4969%(X100), DQS PI = 10
2470 09:24:46.383269 [0] AVG Duty = 5047%(X100)
2471 09:24:46.386441
2472 09:24:46.389917 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2473 09:24:46.390037
2474 09:24:46.393070 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2475 09:24:46.396182 [DutyScan_Calibration_Flow] ====Done====
2476 09:24:46.399975 nWR fixed to 30
2477 09:24:46.400125 [ModeRegInit_LP4] CH0 RK0
2478 09:24:46.403291 [ModeRegInit_LP4] CH0 RK1
2479 09:24:46.406765 [ModeRegInit_LP4] CH1 RK0
2480 09:24:46.406900 [ModeRegInit_LP4] CH1 RK1
2481 09:24:46.409584 match AC timing 7
2482 09:24:46.413034 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2483 09:24:46.416542 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2484 09:24:46.423622 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2485 09:24:46.426540 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2486 09:24:46.433307 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2487 09:24:46.433469 ==
2488 09:24:46.436766 Dram Type= 6, Freq= 0, CH_0, rank 0
2489 09:24:46.440133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2490 09:24:46.440270 ==
2491 09:24:46.446503 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2492 09:24:46.450217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2493 09:24:46.460164 [CA 0] Center 39 (8~70) winsize 63
2494 09:24:46.463580 [CA 1] Center 39 (8~70) winsize 63
2495 09:24:46.466353 [CA 2] Center 35 (5~66) winsize 62
2496 09:24:46.469878 [CA 3] Center 34 (4~65) winsize 62
2497 09:24:46.473415 [CA 4] Center 33 (3~64) winsize 62
2498 09:24:46.476860 [CA 5] Center 32 (3~62) winsize 60
2499 09:24:46.477054
2500 09:24:46.479633 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2501 09:24:46.479815
2502 09:24:46.483260 [CATrainingPosCal] consider 1 rank data
2503 09:24:46.486746 u2DelayCellTimex100 = 270/100 ps
2504 09:24:46.490203 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2505 09:24:46.492983 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2506 09:24:46.499652 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2507 09:24:46.503496 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2508 09:24:46.506673 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2509 09:24:46.509750 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2510 09:24:46.509864
2511 09:24:46.513426 CA PerBit enable=1, Macro0, CA PI delay=32
2512 09:24:46.513531
2513 09:24:46.516829 [CBTSetCACLKResult] CA Dly = 32
2514 09:24:46.516938 CS Dly: 6 (0~37)
2515 09:24:46.517023 ==
2516 09:24:46.520156 Dram Type= 6, Freq= 0, CH_0, rank 1
2517 09:24:46.526663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 09:24:46.526811 ==
2519 09:24:46.530312 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2520 09:24:46.536914 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2521 09:24:46.545683 [CA 0] Center 38 (8~69) winsize 62
2522 09:24:46.549101 [CA 1] Center 38 (8~69) winsize 62
2523 09:24:46.552618 [CA 2] Center 35 (4~66) winsize 63
2524 09:24:46.555482 [CA 3] Center 34 (4~65) winsize 62
2525 09:24:46.559536 [CA 4] Center 33 (3~63) winsize 61
2526 09:24:46.562282 [CA 5] Center 32 (3~62) winsize 60
2527 09:24:46.562375
2528 09:24:46.565876 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2529 09:24:46.565989
2530 09:24:46.568746 [CATrainingPosCal] consider 2 rank data
2531 09:24:46.572175 u2DelayCellTimex100 = 270/100 ps
2532 09:24:46.575757 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2533 09:24:46.579426 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2534 09:24:46.585715 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2535 09:24:46.589240 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2536 09:24:46.592065 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2537 09:24:46.595600 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2538 09:24:46.595738
2539 09:24:46.599267 CA PerBit enable=1, Macro0, CA PI delay=32
2540 09:24:46.599412
2541 09:24:46.602061 [CBTSetCACLKResult] CA Dly = 32
2542 09:24:46.602200 CS Dly: 6 (0~38)
2543 09:24:46.602291
2544 09:24:46.605471 ----->DramcWriteLeveling(PI) begin...
2545 09:24:46.609082 ==
2546 09:24:46.609215 Dram Type= 6, Freq= 0, CH_0, rank 0
2547 09:24:46.616043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2548 09:24:46.616193 ==
2549 09:24:46.618800 Write leveling (Byte 0): 32 => 32
2550 09:24:46.622273 Write leveling (Byte 1): 30 => 30
2551 09:24:46.622390 DramcWriteLeveling(PI) end<-----
2552 09:24:46.625711
2553 09:24:46.625839 ==
2554 09:24:46.629261 Dram Type= 6, Freq= 0, CH_0, rank 0
2555 09:24:46.632719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2556 09:24:46.632827 ==
2557 09:24:46.636069 [Gating] SW mode calibration
2558 09:24:46.642356 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2559 09:24:46.646050 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2560 09:24:46.652373 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2561 09:24:46.655543 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2562 09:24:46.659120 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2563 09:24:46.665944 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 09:24:46.669220 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 09:24:46.672227 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 09:24:46.678817 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2567 09:24:46.682570 0 15 28 | B1->B0 | 3333 2323 | 1 0 | (1 1) (1 0)
2568 09:24:46.686149 1 0 0 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
2569 09:24:46.692541 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 09:24:46.696033 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 09:24:46.698832 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 09:24:46.705770 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 09:24:46.709325 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 09:24:46.712268 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2575 09:24:46.719294 1 0 28 | B1->B0 | 2727 4646 | 1 0 | (0 0) (0 0)
2576 09:24:46.722225 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2577 09:24:46.725683 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 09:24:46.729201 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 09:24:46.735574 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 09:24:46.739138 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 09:24:46.742704 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 09:24:46.749235 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 09:24:46.752163 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2584 09:24:46.755817 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2585 09:24:46.762221 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 09:24:46.765535 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 09:24:46.769018 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 09:24:46.775809 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 09:24:46.779065 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 09:24:46.782329 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 09:24:46.788854 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 09:24:46.792269 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 09:24:46.795750 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 09:24:46.802543 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 09:24:46.805836 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 09:24:46.809067 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 09:24:46.815676 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 09:24:46.819019 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2599 09:24:46.822247 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2600 09:24:46.826132 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2601 09:24:46.828993 Total UI for P1: 0, mck2ui 16
2602 09:24:46.832441 best dqsien dly found for B0: ( 1, 3, 26)
2603 09:24:46.839231 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2604 09:24:46.842650 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 09:24:46.846198 Total UI for P1: 0, mck2ui 16
2606 09:24:46.849119 best dqsien dly found for B1: ( 1, 4, 2)
2607 09:24:46.852667 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2608 09:24:46.856232 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2609 09:24:46.856303
2610 09:24:46.859093 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2611 09:24:46.862546 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2612 09:24:46.866079 [Gating] SW calibration Done
2613 09:24:46.866157 ==
2614 09:24:46.868991 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 09:24:46.872397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 09:24:46.872475 ==
2617 09:24:46.875887 RX Vref Scan: 0
2618 09:24:46.875965
2619 09:24:46.879451 RX Vref 0 -> 0, step: 1
2620 09:24:46.879529
2621 09:24:46.879589 RX Delay -40 -> 252, step: 8
2622 09:24:46.886422 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2623 09:24:46.889301 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2624 09:24:46.892709 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2625 09:24:46.896248 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2626 09:24:46.899781 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2627 09:24:46.906039 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2628 09:24:46.909512 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2629 09:24:46.913309 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2630 09:24:46.916664 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2631 09:24:46.919664 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2632 09:24:46.923213 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2633 09:24:46.929795 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2634 09:24:46.932851 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2635 09:24:46.936524 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2636 09:24:46.939801 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2637 09:24:46.946252 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2638 09:24:46.946328 ==
2639 09:24:46.950028 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 09:24:46.953095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 09:24:46.953192 ==
2642 09:24:46.953277 DQS Delay:
2643 09:24:46.956675 DQS0 = 0, DQS1 = 0
2644 09:24:46.956770 DQM Delay:
2645 09:24:46.959875 DQM0 = 121, DQM1 = 113
2646 09:24:46.959958 DQ Delay:
2647 09:24:46.963108 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2648 09:24:46.966355 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2649 09:24:46.969809 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2650 09:24:46.973363 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2651 09:24:46.973466
2652 09:24:46.973561
2653 09:24:46.973622 ==
2654 09:24:46.976849 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 09:24:46.983153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 09:24:46.983237 ==
2657 09:24:46.983298
2658 09:24:46.983353
2659 09:24:46.983405 TX Vref Scan disable
2660 09:24:46.986683 == TX Byte 0 ==
2661 09:24:46.990220 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2662 09:24:46.993831 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2663 09:24:46.996704 == TX Byte 1 ==
2664 09:24:47.000304 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2665 09:24:47.003761 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2666 09:24:47.006651 ==
2667 09:24:47.010261 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 09:24:47.013650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 09:24:47.013725 ==
2670 09:24:47.024560 TX Vref=22, minBit 12, minWin=24, winSum=405
2671 09:24:47.028055 TX Vref=24, minBit 0, minWin=25, winSum=409
2672 09:24:47.031692 TX Vref=26, minBit 4, minWin=25, winSum=416
2673 09:24:47.034929 TX Vref=28, minBit 10, minWin=26, winSum=426
2674 09:24:47.038364 TX Vref=30, minBit 0, minWin=26, winSum=425
2675 09:24:47.044408 TX Vref=32, minBit 10, minWin=25, winSum=419
2676 09:24:47.048292 [TxChooseVref] Worse bit 10, Min win 26, Win sum 426, Final Vref 28
2677 09:24:47.048396
2678 09:24:47.051166 Final TX Range 1 Vref 28
2679 09:24:47.051259
2680 09:24:47.051342 ==
2681 09:24:47.054720 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 09:24:47.058296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 09:24:47.061030 ==
2684 09:24:47.061095
2685 09:24:47.061149
2686 09:24:47.061207 TX Vref Scan disable
2687 09:24:47.065044 == TX Byte 0 ==
2688 09:24:47.068185 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2689 09:24:47.071541 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2690 09:24:47.074923 == TX Byte 1 ==
2691 09:24:47.078011 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2692 09:24:47.081774 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2693 09:24:47.081868
2694 09:24:47.084893 [DATLAT]
2695 09:24:47.084983 Freq=1200, CH0 RK0
2696 09:24:47.085043
2697 09:24:47.088063 DATLAT Default: 0xd
2698 09:24:47.088130 0, 0xFFFF, sum = 0
2699 09:24:47.091757 1, 0xFFFF, sum = 0
2700 09:24:47.091859 2, 0xFFFF, sum = 0
2701 09:24:47.094745 3, 0xFFFF, sum = 0
2702 09:24:47.094839 4, 0xFFFF, sum = 0
2703 09:24:47.098182 5, 0xFFFF, sum = 0
2704 09:24:47.098252 6, 0xFFFF, sum = 0
2705 09:24:47.101310 7, 0xFFFF, sum = 0
2706 09:24:47.101408 8, 0xFFFF, sum = 0
2707 09:24:47.104704 9, 0xFFFF, sum = 0
2708 09:24:47.108332 10, 0xFFFF, sum = 0
2709 09:24:47.108405 11, 0xFFFF, sum = 0
2710 09:24:47.111923 12, 0x0, sum = 1
2711 09:24:47.112000 13, 0x0, sum = 2
2712 09:24:47.112060 14, 0x0, sum = 3
2713 09:24:47.114673 15, 0x0, sum = 4
2714 09:24:47.114780 best_step = 13
2715 09:24:47.114863
2716 09:24:47.118197 ==
2717 09:24:47.118263 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 09:24:47.124627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 09:24:47.124726 ==
2720 09:24:47.124811 RX Vref Scan: 1
2721 09:24:47.124892
2722 09:24:47.128241 Set Vref Range= 32 -> 127
2723 09:24:47.128328
2724 09:24:47.131631 RX Vref 32 -> 127, step: 1
2725 09:24:47.131703
2726 09:24:47.135267 RX Delay -13 -> 252, step: 4
2727 09:24:47.135348
2728 09:24:47.138114 Set Vref, RX VrefLevel [Byte0]: 32
2729 09:24:47.141558 [Byte1]: 32
2730 09:24:47.141627
2731 09:24:47.145084 Set Vref, RX VrefLevel [Byte0]: 33
2732 09:24:47.148613 [Byte1]: 33
2733 09:24:47.148703
2734 09:24:47.152120 Set Vref, RX VrefLevel [Byte0]: 34
2735 09:24:47.154781 [Byte1]: 34
2736 09:24:47.158869
2737 09:24:47.158965 Set Vref, RX VrefLevel [Byte0]: 35
2738 09:24:47.162046 [Byte1]: 35
2739 09:24:47.166615
2740 09:24:47.166717 Set Vref, RX VrefLevel [Byte0]: 36
2741 09:24:47.170017 [Byte1]: 36
2742 09:24:47.174982
2743 09:24:47.175093 Set Vref, RX VrefLevel [Byte0]: 37
2744 09:24:47.177812 [Byte1]: 37
2745 09:24:47.182850
2746 09:24:47.182944 Set Vref, RX VrefLevel [Byte0]: 38
2747 09:24:47.185691 [Byte1]: 38
2748 09:24:47.190294
2749 09:24:47.190359 Set Vref, RX VrefLevel [Byte0]: 39
2750 09:24:47.193507 [Byte1]: 39
2751 09:24:47.198227
2752 09:24:47.198329 Set Vref, RX VrefLevel [Byte0]: 40
2753 09:24:47.201699 [Byte1]: 40
2754 09:24:47.206513
2755 09:24:47.206581 Set Vref, RX VrefLevel [Byte0]: 41
2756 09:24:47.210003 [Byte1]: 41
2757 09:24:47.214528
2758 09:24:47.214606 Set Vref, RX VrefLevel [Byte0]: 42
2759 09:24:47.217745 [Byte1]: 42
2760 09:24:47.221936
2761 09:24:47.222008 Set Vref, RX VrefLevel [Byte0]: 43
2762 09:24:47.225542 [Byte1]: 43
2763 09:24:47.229677
2764 09:24:47.229762 Set Vref, RX VrefLevel [Byte0]: 44
2765 09:24:47.233066 [Byte1]: 44
2766 09:24:47.237850
2767 09:24:47.237928 Set Vref, RX VrefLevel [Byte0]: 45
2768 09:24:47.241318 [Byte1]: 45
2769 09:24:47.245490
2770 09:24:47.245579 Set Vref, RX VrefLevel [Byte0]: 46
2771 09:24:47.248801 [Byte1]: 46
2772 09:24:47.253989
2773 09:24:47.254056 Set Vref, RX VrefLevel [Byte0]: 47
2774 09:24:47.256820 [Byte1]: 47
2775 09:24:47.261868
2776 09:24:47.261937 Set Vref, RX VrefLevel [Byte0]: 48
2777 09:24:47.264498 [Byte1]: 48
2778 09:24:47.269249
2779 09:24:47.269317 Set Vref, RX VrefLevel [Byte0]: 49
2780 09:24:47.272613 [Byte1]: 49
2781 09:24:47.277457
2782 09:24:47.277536 Set Vref, RX VrefLevel [Byte0]: 50
2783 09:24:47.280709 [Byte1]: 50
2784 09:24:47.285155
2785 09:24:47.285232 Set Vref, RX VrefLevel [Byte0]: 51
2786 09:24:47.288584 [Byte1]: 51
2787 09:24:47.292807
2788 09:24:47.292883 Set Vref, RX VrefLevel [Byte0]: 52
2789 09:24:47.296363 [Byte1]: 52
2790 09:24:47.300972
2791 09:24:47.301048 Set Vref, RX VrefLevel [Byte0]: 53
2792 09:24:47.304320 [Byte1]: 53
2793 09:24:47.308573
2794 09:24:47.308650 Set Vref, RX VrefLevel [Byte0]: 54
2795 09:24:47.312123 [Byte1]: 54
2796 09:24:47.316999
2797 09:24:47.317078 Set Vref, RX VrefLevel [Byte0]: 55
2798 09:24:47.319853 [Byte1]: 55
2799 09:24:47.324530
2800 09:24:47.324608 Set Vref, RX VrefLevel [Byte0]: 56
2801 09:24:47.327966 [Byte1]: 56
2802 09:24:47.332216
2803 09:24:47.332292 Set Vref, RX VrefLevel [Byte0]: 57
2804 09:24:47.335673 [Byte1]: 57
2805 09:24:47.340593
2806 09:24:47.340659 Set Vref, RX VrefLevel [Byte0]: 58
2807 09:24:47.343839 [Byte1]: 58
2808 09:24:47.348264
2809 09:24:47.348335 Set Vref, RX VrefLevel [Byte0]: 59
2810 09:24:47.351694 [Byte1]: 59
2811 09:24:47.356130
2812 09:24:47.356201 Set Vref, RX VrefLevel [Byte0]: 60
2813 09:24:47.359340 [Byte1]: 60
2814 09:24:47.364224
2815 09:24:47.364324 Set Vref, RX VrefLevel [Byte0]: 61
2816 09:24:47.367120 [Byte1]: 61
2817 09:24:47.371987
2818 09:24:47.372084 Set Vref, RX VrefLevel [Byte0]: 62
2819 09:24:47.375568 [Byte1]: 62
2820 09:24:47.379815
2821 09:24:47.379908 Set Vref, RX VrefLevel [Byte0]: 63
2822 09:24:47.383465 [Byte1]: 63
2823 09:24:47.387721
2824 09:24:47.387795 Set Vref, RX VrefLevel [Byte0]: 64
2825 09:24:47.391193 [Byte1]: 64
2826 09:24:47.395818
2827 09:24:47.395885 Set Vref, RX VrefLevel [Byte0]: 65
2828 09:24:47.399022 [Byte1]: 65
2829 09:24:47.403444
2830 09:24:47.403540 Set Vref, RX VrefLevel [Byte0]: 66
2831 09:24:47.406597 [Byte1]: 66
2832 09:24:47.411070
2833 09:24:47.411169 Set Vref, RX VrefLevel [Byte0]: 67
2834 09:24:47.414427 [Byte1]: 67
2835 09:24:47.419438
2836 09:24:47.419511 Set Vref, RX VrefLevel [Byte0]: 68
2837 09:24:47.422366 [Byte1]: 68
2838 09:24:47.427287
2839 09:24:47.427359 Set Vref, RX VrefLevel [Byte0]: 69
2840 09:24:47.430738 [Byte1]: 69
2841 09:24:47.434917
2842 09:24:47.434994 Final RX Vref Byte 0 = 55 to rank0
2843 09:24:47.438545 Final RX Vref Byte 1 = 54 to rank0
2844 09:24:47.442163 Final RX Vref Byte 0 = 55 to rank1
2845 09:24:47.445037 Final RX Vref Byte 1 = 54 to rank1==
2846 09:24:47.448417 Dram Type= 6, Freq= 0, CH_0, rank 0
2847 09:24:47.454894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 09:24:47.454966 ==
2849 09:24:47.455029 DQS Delay:
2850 09:24:47.455085 DQS0 = 0, DQS1 = 0
2851 09:24:47.458492 DQM Delay:
2852 09:24:47.458557 DQM0 = 120, DQM1 = 113
2853 09:24:47.461856 DQ Delay:
2854 09:24:47.465168 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2855 09:24:47.468472 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2856 09:24:47.471883 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2857 09:24:47.475086 DQ12 =120, DQ13 =118, DQ14 =124, DQ15 =122
2858 09:24:47.475165
2859 09:24:47.475258
2860 09:24:47.481820 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
2861 09:24:47.485197 CH0 RK0: MR19=404, MR18=1A13
2862 09:24:47.491720 CH0_RK0: MR19=0x404, MR18=0x1A13, DQSOSC=400, MR23=63, INC=40, DEC=27
2863 09:24:47.491818
2864 09:24:47.495086 ----->DramcWriteLeveling(PI) begin...
2865 09:24:47.495190 ==
2866 09:24:47.498585 Dram Type= 6, Freq= 0, CH_0, rank 1
2867 09:24:47.502081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2868 09:24:47.505484 ==
2869 09:24:47.505584 Write leveling (Byte 0): 34 => 34
2870 09:24:47.508170 Write leveling (Byte 1): 28 => 28
2871 09:24:47.511642 DramcWriteLeveling(PI) end<-----
2872 09:24:47.511737
2873 09:24:47.511820 ==
2874 09:24:47.515002 Dram Type= 6, Freq= 0, CH_0, rank 1
2875 09:24:47.521417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2876 09:24:47.521488 ==
2877 09:24:47.521552 [Gating] SW mode calibration
2878 09:24:47.532111 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2879 09:24:47.534872 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2880 09:24:47.538412 0 15 0 | B1->B0 | 3333 302f | 1 1 | (1 1) (0 0)
2881 09:24:47.544766 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2882 09:24:47.548197 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 09:24:47.551656 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 09:24:47.558631 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 09:24:47.561448 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 09:24:47.564869 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 09:24:47.571824 0 15 28 | B1->B0 | 2c2c 2828 | 0 0 | (1 0) (1 0)
2888 09:24:47.575418 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2889 09:24:47.578241 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 09:24:47.585465 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 09:24:47.588882 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 09:24:47.591795 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 09:24:47.598555 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 09:24:47.602045 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2895 09:24:47.605250 1 0 28 | B1->B0 | 3f3f 3c3c | 0 1 | (0 0) (0 0)
2896 09:24:47.611997 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 09:24:47.615196 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 09:24:47.618650 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 09:24:47.621847 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 09:24:47.628884 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 09:24:47.632256 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 09:24:47.635597 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 09:24:47.641906 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2904 09:24:47.645688 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2905 09:24:47.648709 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 09:24:47.655436 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 09:24:47.658711 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 09:24:47.662217 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 09:24:47.668690 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 09:24:47.672253 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 09:24:47.675665 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 09:24:47.682054 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 09:24:47.685640 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 09:24:47.689202 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 09:24:47.692019 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 09:24:47.698988 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 09:24:47.701815 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 09:24:47.705385 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 09:24:47.711950 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2920 09:24:47.715381 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 09:24:47.718841 Total UI for P1: 0, mck2ui 16
2922 09:24:47.722373 best dqsien dly found for B0: ( 1, 3, 28)
2923 09:24:47.725216 Total UI for P1: 0, mck2ui 16
2924 09:24:47.728531 best dqsien dly found for B1: ( 1, 3, 28)
2925 09:24:47.731934 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2926 09:24:47.735153 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2927 09:24:47.735218
2928 09:24:47.738926 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2929 09:24:47.741871 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2930 09:24:47.745413 [Gating] SW calibration Done
2931 09:24:47.745486 ==
2932 09:24:47.748647 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 09:24:47.755511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 09:24:47.755593 ==
2935 09:24:47.755661 RX Vref Scan: 0
2936 09:24:47.755722
2937 09:24:47.758478 RX Vref 0 -> 0, step: 1
2938 09:24:47.758544
2939 09:24:47.761960 RX Delay -40 -> 252, step: 8
2940 09:24:47.765088 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2941 09:24:47.768240 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2942 09:24:47.772011 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2943 09:24:47.775049 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2944 09:24:47.781878 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2945 09:24:47.785103 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2946 09:24:47.788119 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2947 09:24:47.791553 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2948 09:24:47.795180 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2949 09:24:47.801639 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2950 09:24:47.805246 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2951 09:24:47.808707 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2952 09:24:47.811565 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2953 09:24:47.818636 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2954 09:24:47.821498 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2955 09:24:47.825017 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2956 09:24:47.825111 ==
2957 09:24:47.828606 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 09:24:47.831364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 09:24:47.831442 ==
2960 09:24:47.835006 DQS Delay:
2961 09:24:47.835085 DQS0 = 0, DQS1 = 0
2962 09:24:47.835146 DQM Delay:
2963 09:24:47.838566 DQM0 = 122, DQM1 = 113
2964 09:24:47.838672 DQ Delay:
2965 09:24:47.841449 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2966 09:24:47.844998 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2967 09:24:47.851333 DQ8 =103, DQ9 =103, DQ10 =111, DQ11 =107
2968 09:24:47.854790 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2969 09:24:47.854858
2970 09:24:47.854914
2971 09:24:47.854968 ==
2972 09:24:47.858255 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 09:24:47.861638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 09:24:47.861730 ==
2975 09:24:47.861792
2976 09:24:47.861847
2977 09:24:47.864892 TX Vref Scan disable
2978 09:24:47.868036 == TX Byte 0 ==
2979 09:24:47.871128 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2980 09:24:47.874658 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2981 09:24:47.878467 == TX Byte 1 ==
2982 09:24:47.881380 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2983 09:24:47.884669 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2984 09:24:47.884735 ==
2985 09:24:47.888046 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 09:24:47.891523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 09:24:47.894500 ==
2988 09:24:47.905102 TX Vref=22, minBit 2, minWin=25, winSum=418
2989 09:24:47.908607 TX Vref=24, minBit 1, minWin=25, winSum=421
2990 09:24:47.911529 TX Vref=26, minBit 0, minWin=26, winSum=424
2991 09:24:47.915191 TX Vref=28, minBit 0, minWin=26, winSum=429
2992 09:24:47.918466 TX Vref=30, minBit 0, minWin=26, winSum=430
2993 09:24:47.921849 TX Vref=32, minBit 1, minWin=26, winSum=429
2994 09:24:47.928755 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 30
2995 09:24:47.928857
2996 09:24:47.932156 Final TX Range 1 Vref 30
2997 09:24:47.932251
2998 09:24:47.932339 ==
2999 09:24:47.935100 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 09:24:47.938605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 09:24:47.938681 ==
3002 09:24:47.938741
3003 09:24:47.942020
3004 09:24:47.942088 TX Vref Scan disable
3005 09:24:47.945522 == TX Byte 0 ==
3006 09:24:47.948371 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3007 09:24:47.952022 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3008 09:24:47.955539 == TX Byte 1 ==
3009 09:24:47.958521 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3010 09:24:47.962106 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3011 09:24:47.962172
3012 09:24:47.965012 [DATLAT]
3013 09:24:47.965079 Freq=1200, CH0 RK1
3014 09:24:47.965139
3015 09:24:47.968590 DATLAT Default: 0xd
3016 09:24:47.968658 0, 0xFFFF, sum = 0
3017 09:24:47.971542 1, 0xFFFF, sum = 0
3018 09:24:47.971645 2, 0xFFFF, sum = 0
3019 09:24:47.975031 3, 0xFFFF, sum = 0
3020 09:24:47.975097 4, 0xFFFF, sum = 0
3021 09:24:47.978490 5, 0xFFFF, sum = 0
3022 09:24:47.978584 6, 0xFFFF, sum = 0
3023 09:24:47.981749 7, 0xFFFF, sum = 0
3024 09:24:47.985262 8, 0xFFFF, sum = 0
3025 09:24:47.985369 9, 0xFFFF, sum = 0
3026 09:24:47.988746 10, 0xFFFF, sum = 0
3027 09:24:47.988844 11, 0xFFFF, sum = 0
3028 09:24:47.992071 12, 0x0, sum = 1
3029 09:24:47.992169 13, 0x0, sum = 2
3030 09:24:47.995325 14, 0x0, sum = 3
3031 09:24:47.995429 15, 0x0, sum = 4
3032 09:24:47.995525 best_step = 13
3033 09:24:47.995611
3034 09:24:47.998582 ==
3035 09:24:48.001791 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 09:24:48.005205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 09:24:48.005311 ==
3038 09:24:48.005419 RX Vref Scan: 0
3039 09:24:48.005509
3040 09:24:48.008717 RX Vref 0 -> 0, step: 1
3041 09:24:48.008819
3042 09:24:48.011530 RX Delay -13 -> 252, step: 4
3043 09:24:48.014780 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3044 09:24:48.021674 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3045 09:24:48.024671 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3046 09:24:48.028176 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3047 09:24:48.031547 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3048 09:24:48.034853 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3049 09:24:48.041617 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3050 09:24:48.045204 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3051 09:24:48.048432 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3052 09:24:48.051861 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3053 09:24:48.055289 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3054 09:24:48.058132 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3055 09:24:48.065304 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3056 09:24:48.068179 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3057 09:24:48.071756 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3058 09:24:48.075294 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3059 09:24:48.075388 ==
3060 09:24:48.078256 Dram Type= 6, Freq= 0, CH_0, rank 1
3061 09:24:48.085306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 09:24:48.085407 ==
3063 09:24:48.085494 DQS Delay:
3064 09:24:48.088157 DQS0 = 0, DQS1 = 0
3065 09:24:48.088250 DQM Delay:
3066 09:24:48.091671 DQM0 = 121, DQM1 = 111
3067 09:24:48.091761 DQ Delay:
3068 09:24:48.095224 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3069 09:24:48.098043 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3070 09:24:48.101346 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =104
3071 09:24:48.104750 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3072 09:24:48.104842
3073 09:24:48.104936
3074 09:24:48.115170 [DQSOSCAuto] RK1, (LSB)MR18= 0xff0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps
3075 09:24:48.115246 CH0 RK1: MR19=403, MR18=FF0
3076 09:24:48.121561 CH0_RK1: MR19=0x403, MR18=0xFF0, DQSOSC=404, MR23=63, INC=40, DEC=26
3077 09:24:48.125123 [RxdqsGatingPostProcess] freq 1200
3078 09:24:48.131460 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3079 09:24:48.134896 best DQS0 dly(2T, 0.5T) = (0, 11)
3080 09:24:48.138304 best DQS1 dly(2T, 0.5T) = (0, 12)
3081 09:24:48.141519 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3082 09:24:48.144800 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3083 09:24:48.144905 best DQS0 dly(2T, 0.5T) = (0, 11)
3084 09:24:48.147994 best DQS1 dly(2T, 0.5T) = (0, 11)
3085 09:24:48.151257 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3086 09:24:48.154555 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3087 09:24:48.158303 Pre-setting of DQS Precalculation
3088 09:24:48.164933 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3089 09:24:48.165041 ==
3090 09:24:48.167844 Dram Type= 6, Freq= 0, CH_1, rank 0
3091 09:24:48.171376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3092 09:24:48.171444 ==
3093 09:24:48.178060 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3094 09:24:48.184971 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3095 09:24:48.191200 [CA 0] Center 37 (7~68) winsize 62
3096 09:24:48.194531 [CA 1] Center 37 (7~68) winsize 62
3097 09:24:48.198129 [CA 2] Center 35 (5~65) winsize 61
3098 09:24:48.201634 [CA 3] Center 34 (4~64) winsize 61
3099 09:24:48.204581 [CA 4] Center 34 (4~64) winsize 61
3100 09:24:48.208128 [CA 5] Center 33 (3~63) winsize 61
3101 09:24:48.208195
3102 09:24:48.211626 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3103 09:24:48.211691
3104 09:24:48.214375 [CATrainingPosCal] consider 1 rank data
3105 09:24:48.217826 u2DelayCellTimex100 = 270/100 ps
3106 09:24:48.221296 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3107 09:24:48.227869 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3108 09:24:48.230802 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3109 09:24:48.234350 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3110 09:24:48.237928 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3111 09:24:48.241431 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3112 09:24:48.241500
3113 09:24:48.244214 CA PerBit enable=1, Macro0, CA PI delay=33
3114 09:24:48.244281
3115 09:24:48.247670 [CBTSetCACLKResult] CA Dly = 33
3116 09:24:48.247760 CS Dly: 8 (0~39)
3117 09:24:48.251175 ==
3118 09:24:48.254639 Dram Type= 6, Freq= 0, CH_1, rank 1
3119 09:24:48.257528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 09:24:48.257606 ==
3121 09:24:48.263953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3122 09:24:48.267550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3123 09:24:48.276739 [CA 0] Center 37 (7~68) winsize 62
3124 09:24:48.280255 [CA 1] Center 37 (7~68) winsize 62
3125 09:24:48.283647 [CA 2] Center 35 (5~65) winsize 61
3126 09:24:48.287498 [CA 3] Center 34 (4~65) winsize 62
3127 09:24:48.290548 [CA 4] Center 34 (4~65) winsize 62
3128 09:24:48.293573 [CA 5] Center 34 (4~64) winsize 61
3129 09:24:48.293642
3130 09:24:48.297349 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3131 09:24:48.297456
3132 09:24:48.300698 [CATrainingPosCal] consider 2 rank data
3133 09:24:48.304026 u2DelayCellTimex100 = 270/100 ps
3134 09:24:48.307313 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3135 09:24:48.310130 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3136 09:24:48.317378 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3137 09:24:48.320119 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3138 09:24:48.323671 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3139 09:24:48.327080 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3140 09:24:48.327181
3141 09:24:48.329965 CA PerBit enable=1, Macro0, CA PI delay=33
3142 09:24:48.330052
3143 09:24:48.333912 [CBTSetCACLKResult] CA Dly = 33
3144 09:24:48.333980 CS Dly: 8 (0~40)
3145 09:24:48.334038
3146 09:24:48.336685 ----->DramcWriteLeveling(PI) begin...
3147 09:24:48.340007 ==
3148 09:24:48.343603 Dram Type= 6, Freq= 0, CH_1, rank 0
3149 09:24:48.347218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3150 09:24:48.347287 ==
3151 09:24:48.350051 Write leveling (Byte 0): 24 => 24
3152 09:24:48.353486 Write leveling (Byte 1): 27 => 27
3153 09:24:48.356788 DramcWriteLeveling(PI) end<-----
3154 09:24:48.356860
3155 09:24:48.356917 ==
3156 09:24:48.360253 Dram Type= 6, Freq= 0, CH_1, rank 0
3157 09:24:48.363631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3158 09:24:48.363728 ==
3159 09:24:48.367258 [Gating] SW mode calibration
3160 09:24:48.373442 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3161 09:24:48.380382 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3162 09:24:48.383214 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 09:24:48.386772 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 09:24:48.390176 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 09:24:48.396547 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 09:24:48.400005 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 09:24:48.403262 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 09:24:48.410493 0 15 24 | B1->B0 | 3434 2e2e | 1 0 | (0 1) (0 1)
3169 09:24:48.413574 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3170 09:24:48.416518 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 09:24:48.423466 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 09:24:48.426901 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 09:24:48.429697 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 09:24:48.436582 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 09:24:48.440260 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3176 09:24:48.443045 1 0 24 | B1->B0 | 3636 4242 | 1 0 | (0 0) (0 0)
3177 09:24:48.449780 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 09:24:48.452990 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 09:24:48.456794 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 09:24:48.463457 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 09:24:48.466308 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 09:24:48.469871 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 09:24:48.476304 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 09:24:48.479621 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3185 09:24:48.483251 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3186 09:24:48.489545 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 09:24:48.492891 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 09:24:48.496293 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 09:24:48.503415 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 09:24:48.506209 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 09:24:48.509719 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 09:24:48.516104 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 09:24:48.519672 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 09:24:48.523173 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 09:24:48.526393 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 09:24:48.532697 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 09:24:48.536438 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 09:24:48.539743 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 09:24:48.545943 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 09:24:48.549983 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3201 09:24:48.552839 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3202 09:24:48.559866 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 09:24:48.563147 Total UI for P1: 0, mck2ui 16
3204 09:24:48.566263 best dqsien dly found for B0: ( 1, 3, 26)
3205 09:24:48.566359 Total UI for P1: 0, mck2ui 16
3206 09:24:48.572742 best dqsien dly found for B1: ( 1, 3, 26)
3207 09:24:48.576366 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3208 09:24:48.579353 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3209 09:24:48.579451
3210 09:24:48.582583 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3211 09:24:48.586112 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3212 09:24:48.589500 [Gating] SW calibration Done
3213 09:24:48.589574 ==
3214 09:24:48.592469 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 09:24:48.595981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 09:24:48.596052 ==
3217 09:24:48.599316 RX Vref Scan: 0
3218 09:24:48.599405
3219 09:24:48.599499 RX Vref 0 -> 0, step: 1
3220 09:24:48.599582
3221 09:24:48.602744 RX Delay -40 -> 252, step: 8
3222 09:24:48.609216 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3223 09:24:48.612838 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3224 09:24:48.615719 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3225 09:24:48.619474 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3226 09:24:48.623002 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3227 09:24:48.625835 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3228 09:24:48.632895 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3229 09:24:48.635774 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3230 09:24:48.639327 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3231 09:24:48.642749 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3232 09:24:48.646159 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3233 09:24:48.652837 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3234 09:24:48.656001 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3235 09:24:48.659060 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3236 09:24:48.662212 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3237 09:24:48.668845 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3238 09:24:48.668940 ==
3239 09:24:48.672638 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 09:24:48.676023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 09:24:48.676121 ==
3242 09:24:48.676220 DQS Delay:
3243 09:24:48.679268 DQS0 = 0, DQS1 = 0
3244 09:24:48.679360 DQM Delay:
3245 09:24:48.682602 DQM0 = 120, DQM1 = 116
3246 09:24:48.682673 DQ Delay:
3247 09:24:48.685335 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3248 09:24:48.689305 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3249 09:24:48.692521 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3250 09:24:48.695485 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3251 09:24:48.695580
3252 09:24:48.695677
3253 09:24:48.698918 ==
3254 09:24:48.702314 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 09:24:48.705642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 09:24:48.705740 ==
3257 09:24:48.705825
3258 09:24:48.705907
3259 09:24:48.709170 TX Vref Scan disable
3260 09:24:48.709269 == TX Byte 0 ==
3261 09:24:48.712675 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3262 09:24:48.719259 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3263 09:24:48.719352 == TX Byte 1 ==
3264 09:24:48.722163 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3265 09:24:48.728476 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3266 09:24:48.728579 ==
3267 09:24:48.732066 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 09:24:48.735543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 09:24:48.735634 ==
3270 09:24:48.747408 TX Vref=22, minBit 11, minWin=24, winSum=411
3271 09:24:48.750858 TX Vref=24, minBit 11, minWin=24, winSum=418
3272 09:24:48.753756 TX Vref=26, minBit 1, minWin=26, winSum=425
3273 09:24:48.757384 TX Vref=28, minBit 9, minWin=25, winSum=426
3274 09:24:48.761012 TX Vref=30, minBit 1, minWin=26, winSum=425
3275 09:24:48.767352 TX Vref=32, minBit 2, minWin=26, winSum=426
3276 09:24:48.770771 [TxChooseVref] Worse bit 2, Min win 26, Win sum 426, Final Vref 32
3277 09:24:48.770868
3278 09:24:48.774228 Final TX Range 1 Vref 32
3279 09:24:48.774299
3280 09:24:48.774356 ==
3281 09:24:48.777665 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 09:24:48.780979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 09:24:48.781069 ==
3284 09:24:48.784108
3285 09:24:48.784176
3286 09:24:48.784232 TX Vref Scan disable
3287 09:24:48.787098 == TX Byte 0 ==
3288 09:24:48.790694 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3289 09:24:48.797431 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3290 09:24:48.797530 == TX Byte 1 ==
3291 09:24:48.800728 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3292 09:24:48.806939 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3293 09:24:48.807034
3294 09:24:48.807124 [DATLAT]
3295 09:24:48.807207 Freq=1200, CH1 RK0
3296 09:24:48.807294
3297 09:24:48.810395 DATLAT Default: 0xd
3298 09:24:48.810463 0, 0xFFFF, sum = 0
3299 09:24:48.813517 1, 0xFFFF, sum = 0
3300 09:24:48.816768 2, 0xFFFF, sum = 0
3301 09:24:48.816840 3, 0xFFFF, sum = 0
3302 09:24:48.820434 4, 0xFFFF, sum = 0
3303 09:24:48.820507 5, 0xFFFF, sum = 0
3304 09:24:48.823424 6, 0xFFFF, sum = 0
3305 09:24:48.823495 7, 0xFFFF, sum = 0
3306 09:24:48.827091 8, 0xFFFF, sum = 0
3307 09:24:48.827159 9, 0xFFFF, sum = 0
3308 09:24:48.830655 10, 0xFFFF, sum = 0
3309 09:24:48.830757 11, 0xFFFF, sum = 0
3310 09:24:48.833951 12, 0x0, sum = 1
3311 09:24:48.834052 13, 0x0, sum = 2
3312 09:24:48.836768 14, 0x0, sum = 3
3313 09:24:48.836837 15, 0x0, sum = 4
3314 09:24:48.836895 best_step = 13
3315 09:24:48.840279
3316 09:24:48.840372 ==
3317 09:24:48.843751 Dram Type= 6, Freq= 0, CH_1, rank 0
3318 09:24:48.847318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3319 09:24:48.847384 ==
3320 09:24:48.847439 RX Vref Scan: 1
3321 09:24:48.847498
3322 09:24:48.850005 Set Vref Range= 32 -> 127
3323 09:24:48.850068
3324 09:24:48.853494 RX Vref 32 -> 127, step: 1
3325 09:24:48.853607
3326 09:24:48.857028 RX Delay -5 -> 252, step: 4
3327 09:24:48.857119
3328 09:24:48.860618 Set Vref, RX VrefLevel [Byte0]: 32
3329 09:24:48.863407 [Byte1]: 32
3330 09:24:48.863503
3331 09:24:48.866972 Set Vref, RX VrefLevel [Byte0]: 33
3332 09:24:48.869790 [Byte1]: 33
3333 09:24:48.873325
3334 09:24:48.873401 Set Vref, RX VrefLevel [Byte0]: 34
3335 09:24:48.876964 [Byte1]: 34
3336 09:24:48.881171
3337 09:24:48.881247 Set Vref, RX VrefLevel [Byte0]: 35
3338 09:24:48.884579 [Byte1]: 35
3339 09:24:48.889595
3340 09:24:48.889675 Set Vref, RX VrefLevel [Byte0]: 36
3341 09:24:48.892454 [Byte1]: 36
3342 09:24:48.897260
3343 09:24:48.897337 Set Vref, RX VrefLevel [Byte0]: 37
3344 09:24:48.900571 [Byte1]: 37
3345 09:24:48.905054
3346 09:24:48.905147 Set Vref, RX VrefLevel [Byte0]: 38
3347 09:24:48.908042 [Byte1]: 38
3348 09:24:48.912649
3349 09:24:48.912754 Set Vref, RX VrefLevel [Byte0]: 39
3350 09:24:48.915906 [Byte1]: 39
3351 09:24:48.920661
3352 09:24:48.920761 Set Vref, RX VrefLevel [Byte0]: 40
3353 09:24:48.923857 [Byte1]: 40
3354 09:24:48.928510
3355 09:24:48.928605 Set Vref, RX VrefLevel [Byte0]: 41
3356 09:24:48.932025 [Byte1]: 41
3357 09:24:48.936084
3358 09:24:48.936166 Set Vref, RX VrefLevel [Byte0]: 42
3359 09:24:48.939867 [Byte1]: 42
3360 09:24:48.944450
3361 09:24:48.944558 Set Vref, RX VrefLevel [Byte0]: 43
3362 09:24:48.947596 [Byte1]: 43
3363 09:24:48.951983
3364 09:24:48.952079 Set Vref, RX VrefLevel [Byte0]: 44
3365 09:24:48.955402 [Byte1]: 44
3366 09:24:48.959553
3367 09:24:48.959659 Set Vref, RX VrefLevel [Byte0]: 45
3368 09:24:48.963160 [Byte1]: 45
3369 09:24:48.967538
3370 09:24:48.967633 Set Vref, RX VrefLevel [Byte0]: 46
3371 09:24:48.971150 [Byte1]: 46
3372 09:24:48.975328
3373 09:24:48.975422 Set Vref, RX VrefLevel [Byte0]: 47
3374 09:24:48.978941 [Byte1]: 47
3375 09:24:48.983243
3376 09:24:48.983337 Set Vref, RX VrefLevel [Byte0]: 48
3377 09:24:48.986815 [Byte1]: 48
3378 09:24:48.991184
3379 09:24:48.991287 Set Vref, RX VrefLevel [Byte0]: 49
3380 09:24:48.994682 [Byte1]: 49
3381 09:24:48.998852
3382 09:24:48.998950 Set Vref, RX VrefLevel [Byte0]: 50
3383 09:24:49.002461 [Byte1]: 50
3384 09:24:49.006690
3385 09:24:49.006828 Set Vref, RX VrefLevel [Byte0]: 51
3386 09:24:49.010354 [Byte1]: 51
3387 09:24:49.014605
3388 09:24:49.014738 Set Vref, RX VrefLevel [Byte0]: 52
3389 09:24:49.018008 [Byte1]: 52
3390 09:24:49.022749
3391 09:24:49.022895 Set Vref, RX VrefLevel [Byte0]: 53
3392 09:24:49.026025 [Byte1]: 53
3393 09:24:49.030293
3394 09:24:49.030383 Set Vref, RX VrefLevel [Byte0]: 54
3395 09:24:49.033953 [Byte1]: 54
3396 09:24:49.038488
3397 09:24:49.038570 Set Vref, RX VrefLevel [Byte0]: 55
3398 09:24:49.041771 [Byte1]: 55
3399 09:24:49.046129
3400 09:24:49.046208 Set Vref, RX VrefLevel [Byte0]: 56
3401 09:24:49.049421 [Byte1]: 56
3402 09:24:49.054029
3403 09:24:49.054108 Set Vref, RX VrefLevel [Byte0]: 57
3404 09:24:49.057199 [Byte1]: 57
3405 09:24:49.062352
3406 09:24:49.062430 Set Vref, RX VrefLevel [Byte0]: 58
3407 09:24:49.065475 [Byte1]: 58
3408 09:24:49.069634
3409 09:24:49.069711 Set Vref, RX VrefLevel [Byte0]: 59
3410 09:24:49.072846 [Byte1]: 59
3411 09:24:49.077947
3412 09:24:49.078026 Set Vref, RX VrefLevel [Byte0]: 60
3413 09:24:49.081187 [Byte1]: 60
3414 09:24:49.085787
3415 09:24:49.085861 Set Vref, RX VrefLevel [Byte0]: 61
3416 09:24:49.088639 [Byte1]: 61
3417 09:24:49.093009
3418 09:24:49.093082 Set Vref, RX VrefLevel [Byte0]: 62
3419 09:24:49.096479 [Byte1]: 62
3420 09:24:49.101444
3421 09:24:49.101511 Set Vref, RX VrefLevel [Byte0]: 63
3422 09:24:49.104312 [Byte1]: 63
3423 09:24:49.109311
3424 09:24:49.109383 Set Vref, RX VrefLevel [Byte0]: 64
3425 09:24:49.112183 [Byte1]: 64
3426 09:24:49.116549
3427 09:24:49.116614 Set Vref, RX VrefLevel [Byte0]: 65
3428 09:24:49.120112 [Byte1]: 65
3429 09:24:49.124373
3430 09:24:49.124445 Set Vref, RX VrefLevel [Byte0]: 66
3431 09:24:49.128003 [Byte1]: 66
3432 09:24:49.132984
3433 09:24:49.133049 Set Vref, RX VrefLevel [Byte0]: 67
3434 09:24:49.135834 [Byte1]: 67
3435 09:24:49.140179
3436 09:24:49.140243 Set Vref, RX VrefLevel [Byte0]: 68
3437 09:24:49.143597 [Byte1]: 68
3438 09:24:49.148008
3439 09:24:49.148083 Set Vref, RX VrefLevel [Byte0]: 69
3440 09:24:49.151247 [Byte1]: 69
3441 09:24:49.156336
3442 09:24:49.156421 Final RX Vref Byte 0 = 53 to rank0
3443 09:24:49.159416 Final RX Vref Byte 1 = 50 to rank0
3444 09:24:49.162787 Final RX Vref Byte 0 = 53 to rank1
3445 09:24:49.166134 Final RX Vref Byte 1 = 50 to rank1==
3446 09:24:49.169334 Dram Type= 6, Freq= 0, CH_1, rank 0
3447 09:24:49.175817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 09:24:49.175890 ==
3449 09:24:49.175957 DQS Delay:
3450 09:24:49.179002 DQS0 = 0, DQS1 = 0
3451 09:24:49.179083 DQM Delay:
3452 09:24:49.179139 DQM0 = 119, DQM1 = 116
3453 09:24:49.182766 DQ Delay:
3454 09:24:49.185808 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =116
3455 09:24:49.189417 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3456 09:24:49.192347 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3457 09:24:49.195861 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3458 09:24:49.195929
3459 09:24:49.195986
3460 09:24:49.206000 [DQSOSCAuto] RK0, (LSB)MR18= 0x619, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 407 ps
3461 09:24:49.206076 CH1 RK0: MR19=404, MR18=619
3462 09:24:49.212435 CH1_RK0: MR19=0x404, MR18=0x619, DQSOSC=400, MR23=63, INC=40, DEC=27
3463 09:24:49.212510
3464 09:24:49.216049 ----->DramcWriteLeveling(PI) begin...
3465 09:24:49.216135 ==
3466 09:24:49.219566 Dram Type= 6, Freq= 0, CH_1, rank 1
3467 09:24:49.226000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 09:24:49.226079 ==
3469 09:24:49.229326 Write leveling (Byte 0): 26 => 26
3470 09:24:49.229427 Write leveling (Byte 1): 27 => 27
3471 09:24:49.232213 DramcWriteLeveling(PI) end<-----
3472 09:24:49.232278
3473 09:24:49.232339 ==
3474 09:24:49.235755 Dram Type= 6, Freq= 0, CH_1, rank 1
3475 09:24:49.242784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3476 09:24:49.242853 ==
3477 09:24:49.245536 [Gating] SW mode calibration
3478 09:24:49.252465 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3479 09:24:49.255958 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3480 09:24:49.262388 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 09:24:49.265774 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 09:24:49.268881 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 09:24:49.275796 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 09:24:49.279242 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 09:24:49.282671 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3486 09:24:49.285390 0 15 24 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 0)
3487 09:24:49.292558 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3488 09:24:49.295460 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 09:24:49.298852 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 09:24:49.305318 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 09:24:49.309159 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 09:24:49.312385 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 09:24:49.319081 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3494 09:24:49.322128 1 0 24 | B1->B0 | 4343 2727 | 0 1 | (0 0) (0 0)
3495 09:24:49.325691 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3496 09:24:49.332416 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 09:24:49.335733 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 09:24:49.339248 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 09:24:49.345680 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 09:24:49.349184 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 09:24:49.352055 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 09:24:49.358962 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3503 09:24:49.362469 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3504 09:24:49.365339 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 09:24:49.372512 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 09:24:49.375796 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 09:24:49.379008 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 09:24:49.385445 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 09:24:49.388908 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 09:24:49.392274 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 09:24:49.395687 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 09:24:49.402045 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 09:24:49.405583 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 09:24:49.409156 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 09:24:49.415407 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 09:24:49.418819 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 09:24:49.422263 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3518 09:24:49.428937 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3519 09:24:49.432287 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3520 09:24:49.435429 Total UI for P1: 0, mck2ui 16
3521 09:24:49.438713 best dqsien dly found for B1: ( 1, 3, 22)
3522 09:24:49.441713 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 09:24:49.445607 Total UI for P1: 0, mck2ui 16
3524 09:24:49.448831 best dqsien dly found for B0: ( 1, 3, 26)
3525 09:24:49.452074 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3526 09:24:49.455392 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3527 09:24:49.455466
3528 09:24:49.462155 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3529 09:24:49.465767 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3530 09:24:49.465865 [Gating] SW calibration Done
3531 09:24:49.468632 ==
3532 09:24:49.472119 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 09:24:49.475016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 09:24:49.475086 ==
3535 09:24:49.475144 RX Vref Scan: 0
3536 09:24:49.475205
3537 09:24:49.478471 RX Vref 0 -> 0, step: 1
3538 09:24:49.478545
3539 09:24:49.482221 RX Delay -40 -> 252, step: 8
3540 09:24:49.485421 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3541 09:24:49.488791 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3542 09:24:49.492079 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3543 09:24:49.498586 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3544 09:24:49.501863 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3545 09:24:49.505083 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3546 09:24:49.508543 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3547 09:24:49.511983 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3548 09:24:49.518526 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3549 09:24:49.521884 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3550 09:24:49.525115 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3551 09:24:49.528731 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3552 09:24:49.532254 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3553 09:24:49.538677 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3554 09:24:49.542247 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3555 09:24:49.545541 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3556 09:24:49.545630 ==
3557 09:24:49.548828 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 09:24:49.552394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 09:24:49.552506 ==
3560 09:24:49.555083 DQS Delay:
3561 09:24:49.555148 DQS0 = 0, DQS1 = 0
3562 09:24:49.558866 DQM Delay:
3563 09:24:49.558928 DQM0 = 119, DQM1 = 118
3564 09:24:49.562030 DQ Delay:
3565 09:24:49.565393 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3566 09:24:49.568728 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3567 09:24:49.571820 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3568 09:24:49.575102 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3569 09:24:49.575164
3570 09:24:49.575218
3571 09:24:49.575294 ==
3572 09:24:49.578472 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 09:24:49.582002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 09:24:49.582069 ==
3575 09:24:49.582125
3576 09:24:49.582177
3577 09:24:49.584926 TX Vref Scan disable
3578 09:24:49.588406 == TX Byte 0 ==
3579 09:24:49.591987 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3580 09:24:49.594767 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3581 09:24:49.598096 == TX Byte 1 ==
3582 09:24:49.601487 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3583 09:24:49.604972 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3584 09:24:49.605042 ==
3585 09:24:49.608417 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 09:24:49.615080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 09:24:49.615165 ==
3588 09:24:49.625197 TX Vref=22, minBit 0, minWin=26, winSum=420
3589 09:24:49.628712 TX Vref=24, minBit 1, minWin=26, winSum=423
3590 09:24:49.631928 TX Vref=26, minBit 4, minWin=26, winSum=430
3591 09:24:49.635375 TX Vref=28, minBit 9, minWin=26, winSum=432
3592 09:24:49.638100 TX Vref=30, minBit 9, minWin=26, winSum=434
3593 09:24:49.645078 TX Vref=32, minBit 9, minWin=26, winSum=435
3594 09:24:49.648582 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 32
3595 09:24:49.648708
3596 09:24:49.651594 Final TX Range 1 Vref 32
3597 09:24:49.651684
3598 09:24:49.651742 ==
3599 09:24:49.655051 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 09:24:49.658605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 09:24:49.661455 ==
3602 09:24:49.661533
3603 09:24:49.661647
3604 09:24:49.661730 TX Vref Scan disable
3605 09:24:49.664967 == TX Byte 0 ==
3606 09:24:49.668326 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3607 09:24:49.674981 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3608 09:24:49.675054 == TX Byte 1 ==
3609 09:24:49.677762 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3610 09:24:49.684504 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3611 09:24:49.684579
3612 09:24:49.684692 [DATLAT]
3613 09:24:49.684751 Freq=1200, CH1 RK1
3614 09:24:49.684807
3615 09:24:49.688338 DATLAT Default: 0xd
3616 09:24:49.688413 0, 0xFFFF, sum = 0
3617 09:24:49.691531 1, 0xFFFF, sum = 0
3618 09:24:49.691600 2, 0xFFFF, sum = 0
3619 09:24:49.694890 3, 0xFFFF, sum = 0
3620 09:24:49.697821 4, 0xFFFF, sum = 0
3621 09:24:49.697888 5, 0xFFFF, sum = 0
3622 09:24:49.701425 6, 0xFFFF, sum = 0
3623 09:24:49.701498 7, 0xFFFF, sum = 0
3624 09:24:49.704609 8, 0xFFFF, sum = 0
3625 09:24:49.704692 9, 0xFFFF, sum = 0
3626 09:24:49.708091 10, 0xFFFF, sum = 0
3627 09:24:49.708161 11, 0xFFFF, sum = 0
3628 09:24:49.711772 12, 0x0, sum = 1
3629 09:24:49.711842 13, 0x0, sum = 2
3630 09:24:49.714586 14, 0x0, sum = 3
3631 09:24:49.714656 15, 0x0, sum = 4
3632 09:24:49.714721 best_step = 13
3633 09:24:49.718141
3634 09:24:49.718216 ==
3635 09:24:49.721490 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 09:24:49.724787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 09:24:49.724859 ==
3638 09:24:49.724924 RX Vref Scan: 0
3639 09:24:49.724994
3640 09:24:49.728082 RX Vref 0 -> 0, step: 1
3641 09:24:49.728154
3642 09:24:49.731183 RX Delay -5 -> 252, step: 4
3643 09:24:49.734515 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3644 09:24:49.741156 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3645 09:24:49.745208 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3646 09:24:49.748017 iDelay=195, Bit 3, Center 114 (55 ~ 174) 120
3647 09:24:49.751550 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3648 09:24:49.755072 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3649 09:24:49.757828 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3650 09:24:49.764975 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3651 09:24:49.767722 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3652 09:24:49.771240 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3653 09:24:49.774685 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3654 09:24:49.781583 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3655 09:24:49.784425 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3656 09:24:49.787976 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3657 09:24:49.791531 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3658 09:24:49.794386 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3659 09:24:49.797826 ==
3660 09:24:49.797895 Dram Type= 6, Freq= 0, CH_1, rank 1
3661 09:24:49.805031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3662 09:24:49.805129 ==
3663 09:24:49.805225 DQS Delay:
3664 09:24:49.807706 DQS0 = 0, DQS1 = 0
3665 09:24:49.807795 DQM Delay:
3666 09:24:49.811051 DQM0 = 120, DQM1 = 117
3667 09:24:49.811118 DQ Delay:
3668 09:24:49.814369 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =114
3669 09:24:49.817832 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3670 09:24:49.821393 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =112
3671 09:24:49.824243 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3672 09:24:49.824316
3673 09:24:49.824372
3674 09:24:49.834509 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3675 09:24:49.834611 CH1 RK1: MR19=403, MR18=12EF
3676 09:24:49.841123 CH1_RK1: MR19=0x403, MR18=0x12EF, DQSOSC=403, MR23=63, INC=40, DEC=26
3677 09:24:49.844462 [RxdqsGatingPostProcess] freq 1200
3678 09:24:49.850864 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3679 09:24:49.854159 best DQS0 dly(2T, 0.5T) = (0, 11)
3680 09:24:49.857573 best DQS1 dly(2T, 0.5T) = (0, 11)
3681 09:24:49.860863 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3682 09:24:49.864319 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3683 09:24:49.867833 best DQS0 dly(2T, 0.5T) = (0, 11)
3684 09:24:49.871330 best DQS1 dly(2T, 0.5T) = (0, 11)
3685 09:24:49.874127 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3686 09:24:49.877590 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3687 09:24:49.877705 Pre-setting of DQS Precalculation
3688 09:24:49.884559 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3689 09:24:49.891228 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3690 09:24:49.897568 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3691 09:24:49.897711
3692 09:24:49.897771
3693 09:24:49.901037 [Calibration Summary] 2400 Mbps
3694 09:24:49.903906 CH 0, Rank 0
3695 09:24:49.903976 SW Impedance : PASS
3696 09:24:49.907503 DUTY Scan : NO K
3697 09:24:49.910996 ZQ Calibration : PASS
3698 09:24:49.911071 Jitter Meter : NO K
3699 09:24:49.914212 CBT Training : PASS
3700 09:24:49.917309 Write leveling : PASS
3701 09:24:49.917376 RX DQS gating : PASS
3702 09:24:49.921041 RX DQ/DQS(RDDQC) : PASS
3703 09:24:49.921110 TX DQ/DQS : PASS
3704 09:24:49.924195 RX DATLAT : PASS
3705 09:24:49.927502 RX DQ/DQS(Engine): PASS
3706 09:24:49.927600 TX OE : NO K
3707 09:24:49.931058 All Pass.
3708 09:24:49.931127
3709 09:24:49.931193 CH 0, Rank 1
3710 09:24:49.934011 SW Impedance : PASS
3711 09:24:49.934077 DUTY Scan : NO K
3712 09:24:49.937271 ZQ Calibration : PASS
3713 09:24:49.940716 Jitter Meter : NO K
3714 09:24:49.940809 CBT Training : PASS
3715 09:24:49.944157 Write leveling : PASS
3716 09:24:49.947658 RX DQS gating : PASS
3717 09:24:49.947729 RX DQ/DQS(RDDQC) : PASS
3718 09:24:49.950892 TX DQ/DQS : PASS
3719 09:24:49.954494 RX DATLAT : PASS
3720 09:24:49.954591 RX DQ/DQS(Engine): PASS
3721 09:24:49.957324 TX OE : NO K
3722 09:24:49.957391 All Pass.
3723 09:24:49.957448
3724 09:24:49.960747 CH 1, Rank 0
3725 09:24:49.960821 SW Impedance : PASS
3726 09:24:49.964010 DUTY Scan : NO K
3727 09:24:49.964102 ZQ Calibration : PASS
3728 09:24:49.967132 Jitter Meter : NO K
3729 09:24:49.971110 CBT Training : PASS
3730 09:24:49.971179 Write leveling : PASS
3731 09:24:49.974322 RX DQS gating : PASS
3732 09:24:49.977180 RX DQ/DQS(RDDQC) : PASS
3733 09:24:49.977278 TX DQ/DQS : PASS
3734 09:24:49.980539 RX DATLAT : PASS
3735 09:24:49.984076 RX DQ/DQS(Engine): PASS
3736 09:24:49.984171 TX OE : NO K
3737 09:24:49.987582 All Pass.
3738 09:24:49.987648
3739 09:24:49.987713 CH 1, Rank 1
3740 09:24:49.990425 SW Impedance : PASS
3741 09:24:49.990490 DUTY Scan : NO K
3742 09:24:49.994343 ZQ Calibration : PASS
3743 09:24:49.997388 Jitter Meter : NO K
3744 09:24:49.997493 CBT Training : PASS
3745 09:24:50.000525 Write leveling : PASS
3746 09:24:50.003983 RX DQS gating : PASS
3747 09:24:50.004053 RX DQ/DQS(RDDQC) : PASS
3748 09:24:50.006851 TX DQ/DQS : PASS
3749 09:24:50.010457 RX DATLAT : PASS
3750 09:24:50.010521 RX DQ/DQS(Engine): PASS
3751 09:24:50.013284 TX OE : NO K
3752 09:24:50.013352 All Pass.
3753 09:24:50.013444
3754 09:24:50.016861 DramC Write-DBI off
3755 09:24:50.020486 PER_BANK_REFRESH: Hybrid Mode
3756 09:24:50.020583 TX_TRACKING: ON
3757 09:24:50.029926 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3758 09:24:50.033690 [FAST_K] Save calibration result to emmc
3759 09:24:50.036843 dramc_set_vcore_voltage set vcore to 650000
3760 09:24:50.040103 Read voltage for 600, 5
3761 09:24:50.040180 Vio18 = 0
3762 09:24:50.040239 Vcore = 650000
3763 09:24:50.043131 Vdram = 0
3764 09:24:50.043207 Vddq = 0
3765 09:24:50.043266 Vmddr = 0
3766 09:24:50.050125 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3767 09:24:50.053519 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3768 09:24:50.056831 MEM_TYPE=3, freq_sel=19
3769 09:24:50.060185 sv_algorithm_assistance_LP4_1600
3770 09:24:50.063032 ============ PULL DRAM RESETB DOWN ============
3771 09:24:50.066547 ========== PULL DRAM RESETB DOWN end =========
3772 09:24:50.073391 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3773 09:24:50.076175 ===================================
3774 09:24:50.079486 LPDDR4 DRAM CONFIGURATION
3775 09:24:50.079565 ===================================
3776 09:24:50.083295 EX_ROW_EN[0] = 0x0
3777 09:24:50.086516 EX_ROW_EN[1] = 0x0
3778 09:24:50.086599 LP4Y_EN = 0x0
3779 09:24:50.090020 WORK_FSP = 0x0
3780 09:24:50.090125 WL = 0x2
3781 09:24:50.092867 RL = 0x2
3782 09:24:50.092969 BL = 0x2
3783 09:24:50.096101 RPST = 0x0
3784 09:24:50.096178 RD_PRE = 0x0
3785 09:24:50.099759 WR_PRE = 0x1
3786 09:24:50.099836 WR_PST = 0x0
3787 09:24:50.103345 DBI_WR = 0x0
3788 09:24:50.103429 DBI_RD = 0x0
3789 09:24:50.106126 OTF = 0x1
3790 09:24:50.109411 ===================================
3791 09:24:50.113319 ===================================
3792 09:24:50.113424 ANA top config
3793 09:24:50.116216 ===================================
3794 09:24:50.119790 DLL_ASYNC_EN = 0
3795 09:24:50.123330 ALL_SLAVE_EN = 1
3796 09:24:50.126064 NEW_RANK_MODE = 1
3797 09:24:50.126140 DLL_IDLE_MODE = 1
3798 09:24:50.129531 LP45_APHY_COMB_EN = 1
3799 09:24:50.133191 TX_ODT_DIS = 1
3800 09:24:50.135993 NEW_8X_MODE = 1
3801 09:24:50.139511 ===================================
3802 09:24:50.142886 ===================================
3803 09:24:50.146393 data_rate = 1200
3804 09:24:50.146467 CKR = 1
3805 09:24:50.149716 DQ_P2S_RATIO = 8
3806 09:24:50.152970 ===================================
3807 09:24:50.156102 CA_P2S_RATIO = 8
3808 09:24:50.159146 DQ_CA_OPEN = 0
3809 09:24:50.162961 DQ_SEMI_OPEN = 0
3810 09:24:50.166039 CA_SEMI_OPEN = 0
3811 09:24:50.166113 CA_FULL_RATE = 0
3812 09:24:50.169351 DQ_CKDIV4_EN = 1
3813 09:24:50.172837 CA_CKDIV4_EN = 1
3814 09:24:50.176266 CA_PREDIV_EN = 0
3815 09:24:50.179581 PH8_DLY = 0
3816 09:24:50.182529 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3817 09:24:50.182597 DQ_AAMCK_DIV = 4
3818 09:24:50.185930 CA_AAMCK_DIV = 4
3819 09:24:50.189383 CA_ADMCK_DIV = 4
3820 09:24:50.192716 DQ_TRACK_CA_EN = 0
3821 09:24:50.196061 CA_PICK = 600
3822 09:24:50.199417 CA_MCKIO = 600
3823 09:24:50.199483 MCKIO_SEMI = 0
3824 09:24:50.202839 PLL_FREQ = 2288
3825 09:24:50.206368 DQ_UI_PI_RATIO = 32
3826 09:24:50.209181 CA_UI_PI_RATIO = 0
3827 09:24:50.212812 ===================================
3828 09:24:50.216276 ===================================
3829 09:24:50.219066 memory_type:LPDDR4
3830 09:24:50.219158 GP_NUM : 10
3831 09:24:50.222879 SRAM_EN : 1
3832 09:24:50.226334 MD32_EN : 0
3833 09:24:50.229060 ===================================
3834 09:24:50.229157 [ANA_INIT] >>>>>>>>>>>>>>
3835 09:24:50.232683 <<<<<< [CONFIGURE PHASE]: ANA_TX
3836 09:24:50.236196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3837 09:24:50.239021 ===================================
3838 09:24:50.242566 data_rate = 1200,PCW = 0X5800
3839 09:24:50.245915 ===================================
3840 09:24:50.249248 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3841 09:24:50.255749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3842 09:24:50.259307 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3843 09:24:50.266039 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3844 09:24:50.269234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3845 09:24:50.272645 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3846 09:24:50.272751 [ANA_INIT] flow start
3847 09:24:50.275957 [ANA_INIT] PLL >>>>>>>>
3848 09:24:50.279405 [ANA_INIT] PLL <<<<<<<<
3849 09:24:50.282570 [ANA_INIT] MIDPI >>>>>>>>
3850 09:24:50.282677 [ANA_INIT] MIDPI <<<<<<<<
3851 09:24:50.285733 [ANA_INIT] DLL >>>>>>>>
3852 09:24:50.288987 [ANA_INIT] flow end
3853 09:24:50.292583 ============ LP4 DIFF to SE enter ============
3854 09:24:50.295370 ============ LP4 DIFF to SE exit ============
3855 09:24:50.298693 [ANA_INIT] <<<<<<<<<<<<<
3856 09:24:50.302149 [Flow] Enable top DCM control >>>>>
3857 09:24:50.305700 [Flow] Enable top DCM control <<<<<
3858 09:24:50.309192 Enable DLL master slave shuffle
3859 09:24:50.311991 ==============================================================
3860 09:24:50.315330 Gating Mode config
3861 09:24:50.318699 ==============================================================
3862 09:24:50.322180 Config description:
3863 09:24:50.332267 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3864 09:24:50.339235 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3865 09:24:50.342712 SELPH_MODE 0: By rank 1: By Phase
3866 09:24:50.348995 ==============================================================
3867 09:24:50.352408 GAT_TRACK_EN = 1
3868 09:24:50.355777 RX_GATING_MODE = 2
3869 09:24:50.359354 RX_GATING_TRACK_MODE = 2
3870 09:24:50.362116 SELPH_MODE = 1
3871 09:24:50.362250 PICG_EARLY_EN = 1
3872 09:24:50.365649 VALID_LAT_VALUE = 1
3873 09:24:50.372709 ==============================================================
3874 09:24:50.375559 Enter into Gating configuration >>>>
3875 09:24:50.379216 Exit from Gating configuration <<<<
3876 09:24:50.382580 Enter into DVFS_PRE_config >>>>>
3877 09:24:50.392726 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3878 09:24:50.396194 Exit from DVFS_PRE_config <<<<<
3879 09:24:50.399358 Enter into PICG configuration >>>>
3880 09:24:50.402613 Exit from PICG configuration <<<<
3881 09:24:50.406012 [RX_INPUT] configuration >>>>>
3882 09:24:50.409358 [RX_INPUT] configuration <<<<<
3883 09:24:50.412157 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3884 09:24:50.419062 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3885 09:24:50.425772 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3886 09:24:50.432559 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3887 09:24:50.435958 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3888 09:24:50.442061 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3889 09:24:50.448976 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3890 09:24:50.452486 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3891 09:24:50.455294 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3892 09:24:50.458766 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3893 09:24:50.462293 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3894 09:24:50.468738 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3895 09:24:50.472252 ===================================
3896 09:24:50.474994 LPDDR4 DRAM CONFIGURATION
3897 09:24:50.478396 ===================================
3898 09:24:50.478473 EX_ROW_EN[0] = 0x0
3899 09:24:50.481890 EX_ROW_EN[1] = 0x0
3900 09:24:50.481960 LP4Y_EN = 0x0
3901 09:24:50.485364 WORK_FSP = 0x0
3902 09:24:50.485457 WL = 0x2
3903 09:24:50.488772 RL = 0x2
3904 09:24:50.488840 BL = 0x2
3905 09:24:50.492209 RPST = 0x0
3906 09:24:50.492302 RD_PRE = 0x0
3907 09:24:50.495692 WR_PRE = 0x1
3908 09:24:50.495766 WR_PST = 0x0
3909 09:24:50.498421 DBI_WR = 0x0
3910 09:24:50.498516 DBI_RD = 0x0
3911 09:24:50.501958 OTF = 0x1
3912 09:24:50.505336 ===================================
3913 09:24:50.508616 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3914 09:24:50.511720 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3915 09:24:50.518520 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3916 09:24:50.522264 ===================================
3917 09:24:50.522346 LPDDR4 DRAM CONFIGURATION
3918 09:24:50.525458 ===================================
3919 09:24:50.528761 EX_ROW_EN[0] = 0x10
3920 09:24:50.532192 EX_ROW_EN[1] = 0x0
3921 09:24:50.532268 LP4Y_EN = 0x0
3922 09:24:50.535668 WORK_FSP = 0x0
3923 09:24:50.535744 WL = 0x2
3924 09:24:50.538409 RL = 0x2
3925 09:24:50.538485 BL = 0x2
3926 09:24:50.542316 RPST = 0x0
3927 09:24:50.542392 RD_PRE = 0x0
3928 09:24:50.545420 WR_PRE = 0x1
3929 09:24:50.545520 WR_PST = 0x0
3930 09:24:50.548599 DBI_WR = 0x0
3931 09:24:50.548676 DBI_RD = 0x0
3932 09:24:50.551767 OTF = 0x1
3933 09:24:50.555042 ===================================
3934 09:24:50.562084 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3935 09:24:50.565634 nWR fixed to 30
3936 09:24:50.568443 [ModeRegInit_LP4] CH0 RK0
3937 09:24:50.568520 [ModeRegInit_LP4] CH0 RK1
3938 09:24:50.572089 [ModeRegInit_LP4] CH1 RK0
3939 09:24:50.575038 [ModeRegInit_LP4] CH1 RK1
3940 09:24:50.575114 match AC timing 17
3941 09:24:50.582011 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3942 09:24:50.585516 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3943 09:24:50.588380 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3944 09:24:50.595268 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3945 09:24:50.598729 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3946 09:24:50.598803 ==
3947 09:24:50.601571 Dram Type= 6, Freq= 0, CH_0, rank 0
3948 09:24:50.605043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3949 09:24:50.605150 ==
3950 09:24:50.611883 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3951 09:24:50.618325 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3952 09:24:50.621735 [CA 0] Center 35 (5~66) winsize 62
3953 09:24:50.625093 [CA 1] Center 35 (5~66) winsize 62
3954 09:24:50.628429 [CA 2] Center 34 (3~65) winsize 63
3955 09:24:50.631712 [CA 3] Center 33 (2~64) winsize 63
3956 09:24:50.634712 [CA 4] Center 33 (2~64) winsize 63
3957 09:24:50.638341 [CA 5] Center 32 (2~63) winsize 62
3958 09:24:50.638413
3959 09:24:50.641538 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3960 09:24:50.641614
3961 09:24:50.645013 [CATrainingPosCal] consider 1 rank data
3962 09:24:50.647908 u2DelayCellTimex100 = 270/100 ps
3963 09:24:50.651425 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3964 09:24:50.654812 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3965 09:24:50.658162 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3966 09:24:50.661288 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3967 09:24:50.664388 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3968 09:24:50.667710 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3969 09:24:50.671005
3970 09:24:50.674452 CA PerBit enable=1, Macro0, CA PI delay=32
3971 09:24:50.674543
3972 09:24:50.677946 [CBTSetCACLKResult] CA Dly = 32
3973 09:24:50.678011 CS Dly: 4 (0~35)
3974 09:24:50.678066 ==
3975 09:24:50.681257 Dram Type= 6, Freq= 0, CH_0, rank 1
3976 09:24:50.684649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 09:24:50.684738 ==
3978 09:24:50.691165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3979 09:24:50.697491 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3980 09:24:50.701014 [CA 0] Center 35 (5~66) winsize 62
3981 09:24:50.704422 [CA 1] Center 35 (5~66) winsize 62
3982 09:24:50.708003 [CA 2] Center 34 (3~65) winsize 63
3983 09:24:50.710704 [CA 3] Center 33 (3~64) winsize 62
3984 09:24:50.714269 [CA 4] Center 32 (2~63) winsize 62
3985 09:24:50.717880 [CA 5] Center 32 (2~63) winsize 62
3986 09:24:50.717947
3987 09:24:50.721262 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3988 09:24:50.721352
3989 09:24:50.724235 [CATrainingPosCal] consider 2 rank data
3990 09:24:50.727782 u2DelayCellTimex100 = 270/100 ps
3991 09:24:50.731257 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3992 09:24:50.734096 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3993 09:24:50.737734 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3994 09:24:50.741077 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3995 09:24:50.747371 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3996 09:24:50.751053 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3997 09:24:50.751142
3998 09:24:50.754094 CA PerBit enable=1, Macro0, CA PI delay=32
3999 09:24:50.754181
4000 09:24:50.757448 [CBTSetCACLKResult] CA Dly = 32
4001 09:24:50.757536 CS Dly: 4 (0~35)
4002 09:24:50.757607
4003 09:24:50.760986 ----->DramcWriteLeveling(PI) begin...
4004 09:24:50.761072 ==
4005 09:24:50.763820 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 09:24:50.770833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 09:24:50.770932 ==
4008 09:24:50.774292 Write leveling (Byte 0): 32 => 32
4009 09:24:50.777231 Write leveling (Byte 1): 30 => 30
4010 09:24:50.777321 DramcWriteLeveling(PI) end<-----
4011 09:24:50.777403
4012 09:24:50.780563 ==
4013 09:24:50.783856 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 09:24:50.787641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 09:24:50.787733 ==
4016 09:24:50.790754 [Gating] SW mode calibration
4017 09:24:50.797553 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4018 09:24:50.800694 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4019 09:24:50.807487 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4020 09:24:50.810226 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 09:24:50.814201 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4022 09:24:50.820680 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
4023 09:24:50.824336 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4024 09:24:50.827154 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 09:24:50.834213 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 09:24:50.837109 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 09:24:50.840685 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 09:24:50.847154 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 09:24:50.850621 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 09:24:50.853944 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4031 09:24:50.857469 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4032 09:24:50.863964 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 09:24:50.867216 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 09:24:50.870579 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 09:24:50.877467 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 09:24:50.880234 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 09:24:50.883768 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 09:24:50.890762 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4039 09:24:50.893668 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4040 09:24:50.896985 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 09:24:50.903769 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 09:24:50.907240 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 09:24:50.910573 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 09:24:50.917202 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 09:24:50.920002 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 09:24:50.923968 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 09:24:50.929922 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 09:24:50.933451 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 09:24:50.937025 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 09:24:50.943466 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 09:24:50.947137 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 09:24:50.950010 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 09:24:50.956430 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 09:24:50.960045 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4055 09:24:50.963360 Total UI for P1: 0, mck2ui 16
4056 09:24:50.966182 best dqsien dly found for B0: ( 0, 13, 10)
4057 09:24:50.969765 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4058 09:24:50.976581 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 09:24:50.976672 Total UI for P1: 0, mck2ui 16
4060 09:24:50.982956 best dqsien dly found for B1: ( 0, 13, 18)
4061 09:24:50.986454 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4062 09:24:50.989967 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4063 09:24:50.990037
4064 09:24:50.993491 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4065 09:24:50.996967 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4066 09:24:50.999860 [Gating] SW calibration Done
4067 09:24:50.999945 ==
4068 09:24:51.003107 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 09:24:51.006515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 09:24:51.006577 ==
4071 09:24:51.010031 RX Vref Scan: 0
4072 09:24:51.010093
4073 09:24:51.010173 RX Vref 0 -> 0, step: 1
4074 09:24:51.010251
4075 09:24:51.013609 RX Delay -230 -> 252, step: 16
4076 09:24:51.016470 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4077 09:24:51.023238 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4078 09:24:51.026741 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4079 09:24:51.030177 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4080 09:24:51.033019 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4081 09:24:51.040256 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4082 09:24:51.043034 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4083 09:24:51.046552 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4084 09:24:51.050039 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4085 09:24:51.053621 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4086 09:24:51.059886 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4087 09:24:51.063211 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4088 09:24:51.066600 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4089 09:24:51.070079 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4090 09:24:51.076385 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4091 09:24:51.079839 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4092 09:24:51.079918 ==
4093 09:24:51.083322 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 09:24:51.086672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 09:24:51.086750 ==
4096 09:24:51.089870 DQS Delay:
4097 09:24:51.089946 DQS0 = 0, DQS1 = 0
4098 09:24:51.090005 DQM Delay:
4099 09:24:51.093089 DQM0 = 48, DQM1 = 44
4100 09:24:51.093166 DQ Delay:
4101 09:24:51.096147 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4102 09:24:51.099656 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4103 09:24:51.103131 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4104 09:24:51.106536 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =57
4105 09:24:51.106627
4106 09:24:51.106717
4107 09:24:51.106799 ==
4108 09:24:51.109365 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 09:24:51.116082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 09:24:51.116155 ==
4111 09:24:51.116214
4112 09:24:51.116274
4113 09:24:51.116328 TX Vref Scan disable
4114 09:24:51.120376 == TX Byte 0 ==
4115 09:24:51.123243 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4116 09:24:51.126777 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4117 09:24:51.130016 == TX Byte 1 ==
4118 09:24:51.133403 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4119 09:24:51.139761 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4120 09:24:51.139860 ==
4121 09:24:51.143260 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 09:24:51.146860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 09:24:51.146961 ==
4124 09:24:51.147057
4125 09:24:51.147141
4126 09:24:51.150278 TX Vref Scan disable
4127 09:24:51.150344 == TX Byte 0 ==
4128 09:24:51.156865 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4129 09:24:51.159698 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4130 09:24:51.159795 == TX Byte 1 ==
4131 09:24:51.166679 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4132 09:24:51.170065 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4133 09:24:51.170151
4134 09:24:51.170210 [DATLAT]
4135 09:24:51.172761 Freq=600, CH0 RK0
4136 09:24:51.172849
4137 09:24:51.172938 DATLAT Default: 0x9
4138 09:24:51.176167 0, 0xFFFF, sum = 0
4139 09:24:51.176266 1, 0xFFFF, sum = 0
4140 09:24:51.179697 2, 0xFFFF, sum = 0
4141 09:24:51.179791 3, 0xFFFF, sum = 0
4142 09:24:51.183270 4, 0xFFFF, sum = 0
4143 09:24:51.186682 5, 0xFFFF, sum = 0
4144 09:24:51.186767 6, 0xFFFF, sum = 0
4145 09:24:51.189460 7, 0xFFFF, sum = 0
4146 09:24:51.189563 8, 0x0, sum = 1
4147 09:24:51.189622 9, 0x0, sum = 2
4148 09:24:51.193113 10, 0x0, sum = 3
4149 09:24:51.193203 11, 0x0, sum = 4
4150 09:24:51.196536 best_step = 9
4151 09:24:51.196617
4152 09:24:51.196672 ==
4153 09:24:51.199992 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 09:24:51.202712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 09:24:51.202811 ==
4156 09:24:51.206574 RX Vref Scan: 1
4157 09:24:51.206671
4158 09:24:51.206755 RX Vref 0 -> 0, step: 1
4159 09:24:51.206844
4160 09:24:51.209713 RX Delay -163 -> 252, step: 8
4161 09:24:51.209804
4162 09:24:51.212790 Set Vref, RX VrefLevel [Byte0]: 55
4163 09:24:51.216392 [Byte1]: 54
4164 09:24:51.220312
4165 09:24:51.220403 Final RX Vref Byte 0 = 55 to rank0
4166 09:24:51.223612 Final RX Vref Byte 1 = 54 to rank0
4167 09:24:51.227113 Final RX Vref Byte 0 = 55 to rank1
4168 09:24:51.230553 Final RX Vref Byte 1 = 54 to rank1==
4169 09:24:51.233334 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 09:24:51.240117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 09:24:51.240213 ==
4172 09:24:51.240301 DQS Delay:
4173 09:24:51.240383 DQS0 = 0, DQS1 = 0
4174 09:24:51.243671 DQM Delay:
4175 09:24:51.243736 DQM0 = 53, DQM1 = 45
4176 09:24:51.247242 DQ Delay:
4177 09:24:51.250110 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4178 09:24:51.250180 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4179 09:24:51.253696 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4180 09:24:51.260074 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4181 09:24:51.260174
4182 09:24:51.260262
4183 09:24:51.266835 [DQSOSCAuto] RK0, (LSB)MR18= 0x776a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 387 ps
4184 09:24:51.270323 CH0 RK0: MR19=808, MR18=776A
4185 09:24:51.277027 CH0_RK0: MR19=0x808, MR18=0x776A, DQSOSC=387, MR23=63, INC=175, DEC=116
4186 09:24:51.277126
4187 09:24:51.280383 ----->DramcWriteLeveling(PI) begin...
4188 09:24:51.280477 ==
4189 09:24:51.283948 Dram Type= 6, Freq= 0, CH_0, rank 1
4190 09:24:51.286797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 09:24:51.286887 ==
4192 09:24:51.290269 Write leveling (Byte 0): 34 => 34
4193 09:24:51.293954 Write leveling (Byte 1): 34 => 34
4194 09:24:51.296631 DramcWriteLeveling(PI) end<-----
4195 09:24:51.296716
4196 09:24:51.296801 ==
4197 09:24:51.300199 Dram Type= 6, Freq= 0, CH_0, rank 1
4198 09:24:51.303689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 09:24:51.303754 ==
4200 09:24:51.306525 [Gating] SW mode calibration
4201 09:24:51.313692 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4202 09:24:51.320517 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4203 09:24:51.323681 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4204 09:24:51.327076 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4205 09:24:51.333677 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4206 09:24:51.336852 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4207 09:24:51.340143 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4208 09:24:51.346916 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 09:24:51.350033 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 09:24:51.353371 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 09:24:51.360086 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 09:24:51.363642 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 09:24:51.366437 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 09:24:51.373373 0 10 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4215 09:24:51.376577 0 10 16 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)
4216 09:24:51.380029 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 09:24:51.386517 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 09:24:51.389791 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 09:24:51.393322 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 09:24:51.399743 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 09:24:51.403178 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 09:24:51.406732 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4223 09:24:51.413141 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4224 09:24:51.416636 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 09:24:51.420169 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 09:24:51.426640 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 09:24:51.430032 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 09:24:51.433232 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 09:24:51.436637 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 09:24:51.442889 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 09:24:51.446306 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 09:24:51.449776 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 09:24:51.456332 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 09:24:51.459335 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 09:24:51.463339 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 09:24:51.469280 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 09:24:51.473203 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 09:24:51.476596 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4239 09:24:51.479334 Total UI for P1: 0, mck2ui 16
4240 09:24:51.482724 best dqsien dly found for B0: ( 0, 13, 10)
4241 09:24:51.489528 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4242 09:24:51.492920 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 09:24:51.496320 Total UI for P1: 0, mck2ui 16
4244 09:24:51.499652 best dqsien dly found for B1: ( 0, 13, 14)
4245 09:24:51.503202 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4246 09:24:51.506038 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4247 09:24:51.506115
4248 09:24:51.509526 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4249 09:24:51.512995 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4250 09:24:51.516625 [Gating] SW calibration Done
4251 09:24:51.516724 ==
4252 09:24:51.519459 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 09:24:51.522980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 09:24:51.526516 ==
4255 09:24:51.526589 RX Vref Scan: 0
4256 09:24:51.526647
4257 09:24:51.529962 RX Vref 0 -> 0, step: 1
4258 09:24:51.530032
4259 09:24:51.532852 RX Delay -230 -> 252, step: 16
4260 09:24:51.536299 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4261 09:24:51.539668 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4262 09:24:51.542844 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4263 09:24:51.549459 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4264 09:24:51.552946 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4265 09:24:51.556300 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4266 09:24:51.559270 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4267 09:24:51.562761 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4268 09:24:51.569468 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4269 09:24:51.572308 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4270 09:24:51.575698 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4271 09:24:51.579175 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4272 09:24:51.585898 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4273 09:24:51.589206 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4274 09:24:51.592411 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4275 09:24:51.595557 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4276 09:24:51.599198 ==
4277 09:24:51.602175 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 09:24:51.605453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 09:24:51.605529 ==
4280 09:24:51.605604 DQS Delay:
4281 09:24:51.608797 DQS0 = 0, DQS1 = 0
4282 09:24:51.608866 DQM Delay:
4283 09:24:51.612105 DQM0 = 51, DQM1 = 42
4284 09:24:51.612194 DQ Delay:
4285 09:24:51.615421 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4286 09:24:51.619032 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4287 09:24:51.621865 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4288 09:24:51.625665 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4289 09:24:51.625779
4290 09:24:51.625843
4291 09:24:51.625900 ==
4292 09:24:51.629028 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 09:24:51.631964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 09:24:51.632064 ==
4295 09:24:51.632126
4296 09:24:51.632182
4297 09:24:51.635420 TX Vref Scan disable
4298 09:24:51.638938 == TX Byte 0 ==
4299 09:24:51.642531 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4300 09:24:51.645248 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4301 09:24:51.648682 == TX Byte 1 ==
4302 09:24:51.652143 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4303 09:24:51.655487 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4304 09:24:51.655565 ==
4305 09:24:51.658469 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 09:24:51.665158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 09:24:51.665238 ==
4308 09:24:51.665298
4309 09:24:51.665354
4310 09:24:51.665406 TX Vref Scan disable
4311 09:24:51.669446 == TX Byte 0 ==
4312 09:24:51.672962 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4313 09:24:51.679161 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4314 09:24:51.679241 == TX Byte 1 ==
4315 09:24:51.682671 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4316 09:24:51.689494 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4317 09:24:51.689579
4318 09:24:51.689641 [DATLAT]
4319 09:24:51.689696 Freq=600, CH0 RK1
4320 09:24:51.689751
4321 09:24:51.692322 DATLAT Default: 0x9
4322 09:24:51.692399 0, 0xFFFF, sum = 0
4323 09:24:51.695847 1, 0xFFFF, sum = 0
4324 09:24:51.695927 2, 0xFFFF, sum = 0
4325 09:24:51.699270 3, 0xFFFF, sum = 0
4326 09:24:51.702092 4, 0xFFFF, sum = 0
4327 09:24:51.702188 5, 0xFFFF, sum = 0
4328 09:24:51.705617 6, 0xFFFF, sum = 0
4329 09:24:51.705699 7, 0xFFFF, sum = 0
4330 09:24:51.708801 8, 0x0, sum = 1
4331 09:24:51.708869 9, 0x0, sum = 2
4332 09:24:51.708926 10, 0x0, sum = 3
4333 09:24:51.712606 11, 0x0, sum = 4
4334 09:24:51.712705 best_step = 9
4335 09:24:51.712790
4336 09:24:51.712870 ==
4337 09:24:51.715891 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 09:24:51.722205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 09:24:51.722317 ==
4340 09:24:51.722405 RX Vref Scan: 0
4341 09:24:51.722496
4342 09:24:51.725714 RX Vref 0 -> 0, step: 1
4343 09:24:51.725793
4344 09:24:51.728722 RX Delay -179 -> 252, step: 8
4345 09:24:51.732360 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4346 09:24:51.739305 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4347 09:24:51.742069 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4348 09:24:51.745561 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4349 09:24:51.749140 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4350 09:24:51.752070 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4351 09:24:51.759159 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4352 09:24:51.762627 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4353 09:24:51.765386 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4354 09:24:51.769274 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4355 09:24:51.772610 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4356 09:24:51.779294 iDelay=197, Bit 11, Center 36 (-107 ~ 180) 288
4357 09:24:51.782593 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4358 09:24:51.785880 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4359 09:24:51.788675 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4360 09:24:51.792062 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4361 09:24:51.795549 ==
4362 09:24:51.799177 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 09:24:51.801961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 09:24:51.802029 ==
4365 09:24:51.802085 DQS Delay:
4366 09:24:51.805617 DQS0 = 0, DQS1 = 0
4367 09:24:51.805684 DQM Delay:
4368 09:24:51.809190 DQM0 = 54, DQM1 = 46
4369 09:24:51.809276 DQ Delay:
4370 09:24:51.812639 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4371 09:24:51.815477 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4372 09:24:51.818863 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4373 09:24:51.822214 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4374 09:24:51.822283
4375 09:24:51.822339
4376 09:24:51.829289 [DQSOSCAuto] RK1, (LSB)MR18= 0x6627, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4377 09:24:51.831976 CH0 RK1: MR19=808, MR18=6627
4378 09:24:51.838643 CH0_RK1: MR19=0x808, MR18=0x6627, DQSOSC=390, MR23=63, INC=172, DEC=114
4379 09:24:51.841856 [RxdqsGatingPostProcess] freq 600
4380 09:24:51.848571 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4381 09:24:51.848667 Pre-setting of DQS Precalculation
4382 09:24:51.855352 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4383 09:24:51.855452 ==
4384 09:24:51.859076 Dram Type= 6, Freq= 0, CH_1, rank 0
4385 09:24:51.861838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 09:24:51.861915 ==
4387 09:24:51.868660 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4388 09:24:51.875708 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4389 09:24:51.878471 [CA 0] Center 35 (5~66) winsize 62
4390 09:24:51.881794 [CA 1] Center 35 (5~66) winsize 62
4391 09:24:51.884957 [CA 2] Center 34 (4~65) winsize 62
4392 09:24:51.888970 [CA 3] Center 34 (3~65) winsize 63
4393 09:24:51.892297 [CA 4] Center 34 (4~65) winsize 62
4394 09:24:51.895289 [CA 5] Center 33 (3~64) winsize 62
4395 09:24:51.895388
4396 09:24:51.898535 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4397 09:24:51.898600
4398 09:24:51.902057 [CATrainingPosCal] consider 1 rank data
4399 09:24:51.905494 u2DelayCellTimex100 = 270/100 ps
4400 09:24:51.909028 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4401 09:24:51.912027 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4402 09:24:51.915422 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 09:24:51.918872 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4404 09:24:51.922408 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 09:24:51.925854 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 09:24:51.925937
4407 09:24:51.928673 CA PerBit enable=1, Macro0, CA PI delay=33
4408 09:24:51.932215
4409 09:24:51.932299 [CBTSetCACLKResult] CA Dly = 33
4410 09:24:51.935686 CS Dly: 6 (0~37)
4411 09:24:51.935764 ==
4412 09:24:51.938567 Dram Type= 6, Freq= 0, CH_1, rank 1
4413 09:24:51.942210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 09:24:51.942290 ==
4415 09:24:51.948707 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4416 09:24:51.955157 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4417 09:24:51.958642 [CA 0] Center 36 (5~67) winsize 63
4418 09:24:51.962162 [CA 1] Center 36 (5~67) winsize 63
4419 09:24:51.965438 [CA 2] Center 34 (4~65) winsize 62
4420 09:24:51.968719 [CA 3] Center 34 (4~65) winsize 62
4421 09:24:51.972267 [CA 4] Center 34 (4~65) winsize 62
4422 09:24:51.975143 [CA 5] Center 34 (3~65) winsize 63
4423 09:24:51.975221
4424 09:24:51.978697 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4425 09:24:51.978776
4426 09:24:51.982334 [CATrainingPosCal] consider 2 rank data
4427 09:24:51.985247 u2DelayCellTimex100 = 270/100 ps
4428 09:24:51.988837 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4429 09:24:51.991678 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4430 09:24:51.995096 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4431 09:24:51.998604 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4432 09:24:52.001991 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 09:24:52.005509 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 09:24:52.005597
4435 09:24:52.011745 CA PerBit enable=1, Macro0, CA PI delay=33
4436 09:24:52.011841
4437 09:24:52.014872 [CBTSetCACLKResult] CA Dly = 33
4438 09:24:52.014951 CS Dly: 6 (0~38)
4439 09:24:52.015012
4440 09:24:52.018261 ----->DramcWriteLeveling(PI) begin...
4441 09:24:52.018341 ==
4442 09:24:52.021675 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 09:24:52.025263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 09:24:52.025343 ==
4445 09:24:52.028156 Write leveling (Byte 0): 28 => 28
4446 09:24:52.031664 Write leveling (Byte 1): 31 => 31
4447 09:24:52.035221 DramcWriteLeveling(PI) end<-----
4448 09:24:52.035299
4449 09:24:52.035360 ==
4450 09:24:52.038644 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 09:24:52.044723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 09:24:52.044803 ==
4453 09:24:52.044865 [Gating] SW mode calibration
4454 09:24:52.055000 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4455 09:24:52.058436 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4456 09:24:52.061741 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4457 09:24:52.068115 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 09:24:52.071585 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4459 09:24:52.075052 0 9 12 | B1->B0 | 3030 2e2e | 1 1 | (1 1) (1 0)
4460 09:24:52.081617 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 09:24:52.084543 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 09:24:52.088220 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 09:24:52.094598 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 09:24:52.098088 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 09:24:52.101596 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 09:24:52.108110 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 09:24:52.111647 0 10 12 | B1->B0 | 3232 3737 | 0 0 | (1 1) (0 0)
4468 09:24:52.115224 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 09:24:52.121132 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 09:24:52.124809 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 09:24:52.128124 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 09:24:52.135102 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 09:24:52.138026 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 09:24:52.141492 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 09:24:52.148120 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4476 09:24:52.151726 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 09:24:52.154500 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 09:24:52.161356 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 09:24:52.164700 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 09:24:52.168138 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 09:24:52.171544 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 09:24:52.177928 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 09:24:52.181493 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 09:24:52.184315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 09:24:52.191071 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 09:24:52.194373 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 09:24:52.197898 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 09:24:52.204247 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 09:24:52.207648 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 09:24:52.211040 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 09:24:52.217442 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4492 09:24:52.221000 Total UI for P1: 0, mck2ui 16
4493 09:24:52.224451 best dqsien dly found for B0: ( 0, 13, 10)
4494 09:24:52.227369 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 09:24:52.230770 Total UI for P1: 0, mck2ui 16
4496 09:24:52.233928 best dqsien dly found for B1: ( 0, 13, 12)
4497 09:24:52.237662 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4498 09:24:52.240956 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4499 09:24:52.241029
4500 09:24:52.244179 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4501 09:24:52.247561 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4502 09:24:52.251139 [Gating] SW calibration Done
4503 09:24:52.251240 ==
4504 09:24:52.254630 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 09:24:52.261107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 09:24:52.261218 ==
4507 09:24:52.261324 RX Vref Scan: 0
4508 09:24:52.261409
4509 09:24:52.264553 RX Vref 0 -> 0, step: 1
4510 09:24:52.264656
4511 09:24:52.267353 RX Delay -230 -> 252, step: 16
4512 09:24:52.270734 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4513 09:24:52.274090 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4514 09:24:52.277340 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4515 09:24:52.284375 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4516 09:24:52.287321 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4517 09:24:52.290708 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4518 09:24:52.294214 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4519 09:24:52.297013 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4520 09:24:52.303954 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4521 09:24:52.307274 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4522 09:24:52.310531 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4523 09:24:52.314051 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4524 09:24:52.320742 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4525 09:24:52.324197 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4526 09:24:52.327081 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4527 09:24:52.330656 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4528 09:24:52.330754 ==
4529 09:24:52.333551 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 09:24:52.337051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 09:24:52.340581 ==
4532 09:24:52.340653 DQS Delay:
4533 09:24:52.340711 DQS0 = 0, DQS1 = 0
4534 09:24:52.343988 DQM Delay:
4535 09:24:52.344090 DQM0 = 53, DQM1 = 51
4536 09:24:52.347158 DQ Delay:
4537 09:24:52.350318 DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =49
4538 09:24:52.350397 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4539 09:24:52.353988 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =41
4540 09:24:52.357340 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4541 09:24:52.360459
4542 09:24:52.360536
4543 09:24:52.360602 ==
4544 09:24:52.363608 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 09:24:52.366956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 09:24:52.367036 ==
4547 09:24:52.367097
4548 09:24:52.367152
4549 09:24:52.370349 TX Vref Scan disable
4550 09:24:52.370452 == TX Byte 0 ==
4551 09:24:52.377428 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4552 09:24:52.380148 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4553 09:24:52.380249 == TX Byte 1 ==
4554 09:24:52.386832 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4555 09:24:52.390396 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4556 09:24:52.390473 ==
4557 09:24:52.393938 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 09:24:52.396782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 09:24:52.396881 ==
4560 09:24:52.396968
4561 09:24:52.397050
4562 09:24:52.400351 TX Vref Scan disable
4563 09:24:52.403958 == TX Byte 0 ==
4564 09:24:52.406913 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4565 09:24:52.410548 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4566 09:24:52.413339 == TX Byte 1 ==
4567 09:24:52.416866 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4568 09:24:52.420219 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4569 09:24:52.423605
4570 09:24:52.423682 [DATLAT]
4571 09:24:52.423740 Freq=600, CH1 RK0
4572 09:24:52.423794
4573 09:24:52.426965 DATLAT Default: 0x9
4574 09:24:52.427028 0, 0xFFFF, sum = 0
4575 09:24:52.430164 1, 0xFFFF, sum = 0
4576 09:24:52.430243 2, 0xFFFF, sum = 0
4577 09:24:52.433347 3, 0xFFFF, sum = 0
4578 09:24:52.433448 4, 0xFFFF, sum = 0
4579 09:24:52.437270 5, 0xFFFF, sum = 0
4580 09:24:52.437342 6, 0xFFFF, sum = 0
4581 09:24:52.439954 7, 0xFFFF, sum = 0
4582 09:24:52.440029 8, 0x0, sum = 1
4583 09:24:52.443490 9, 0x0, sum = 2
4584 09:24:52.443566 10, 0x0, sum = 3
4585 09:24:52.447076 11, 0x0, sum = 4
4586 09:24:52.447171 best_step = 9
4587 09:24:52.447255
4588 09:24:52.447335 ==
4589 09:24:52.449924 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 09:24:52.456851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 09:24:52.456947 ==
4592 09:24:52.457044 RX Vref Scan: 1
4593 09:24:52.457127
4594 09:24:52.460047 RX Vref 0 -> 0, step: 1
4595 09:24:52.460120
4596 09:24:52.463495 RX Delay -163 -> 252, step: 8
4597 09:24:52.463565
4598 09:24:52.467081 Set Vref, RX VrefLevel [Byte0]: 53
4599 09:24:52.470407 [Byte1]: 50
4600 09:24:52.470501
4601 09:24:52.473753 Final RX Vref Byte 0 = 53 to rank0
4602 09:24:52.476991 Final RX Vref Byte 1 = 50 to rank0
4603 09:24:52.480028 Final RX Vref Byte 0 = 53 to rank1
4604 09:24:52.483690 Final RX Vref Byte 1 = 50 to rank1==
4605 09:24:52.486551 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 09:24:52.490034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 09:24:52.490116 ==
4608 09:24:52.493107 DQS Delay:
4609 09:24:52.493185 DQS0 = 0, DQS1 = 0
4610 09:24:52.493246 DQM Delay:
4611 09:24:52.497083 DQM0 = 48, DQM1 = 46
4612 09:24:52.497163 DQ Delay:
4613 09:24:52.499813 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4614 09:24:52.503331 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4615 09:24:52.506310 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =40
4616 09:24:52.509896 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =60
4617 09:24:52.509990
4618 09:24:52.510079
4619 09:24:52.519663 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a6f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
4620 09:24:52.519768 CH1 RK0: MR19=808, MR18=4A6F
4621 09:24:52.526700 CH1_RK0: MR19=0x808, MR18=0x4A6F, DQSOSC=389, MR23=63, INC=173, DEC=115
4622 09:24:52.526802
4623 09:24:52.530207 ----->DramcWriteLeveling(PI) begin...
4624 09:24:52.533072 ==
4625 09:24:52.533168 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 09:24:52.540108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 09:24:52.540206 ==
4628 09:24:52.543552 Write leveling (Byte 0): 29 => 29
4629 09:24:52.546759 Write leveling (Byte 1): 30 => 30
4630 09:24:52.550120 DramcWriteLeveling(PI) end<-----
4631 09:24:52.550215
4632 09:24:52.550301 ==
4633 09:24:52.553383 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 09:24:52.556563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 09:24:52.556654 ==
4636 09:24:52.559733 [Gating] SW mode calibration
4637 09:24:52.566400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4638 09:24:52.569679 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4639 09:24:52.576755 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4640 09:24:52.579746 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 09:24:52.583189 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 09:24:52.589855 0 9 12 | B1->B0 | 3030 2f2f | 0 1 | (0 0) (0 0)
4643 09:24:52.593131 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 09:24:52.596327 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 09:24:52.603190 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 09:24:52.606232 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 09:24:52.609446 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 09:24:52.616597 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 09:24:52.619503 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 09:24:52.623024 0 10 12 | B1->B0 | 3b3b 3535 | 0 1 | (0 0) (1 1)
4651 09:24:52.629442 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 09:24:52.633049 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 09:24:52.635969 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 09:24:52.643058 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 09:24:52.646597 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 09:24:52.649500 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 09:24:52.656236 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 09:24:52.659887 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4659 09:24:52.663146 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 09:24:52.669743 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 09:24:52.672990 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 09:24:52.676207 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 09:24:52.679688 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 09:24:52.686348 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 09:24:52.689619 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 09:24:52.693061 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 09:24:52.699451 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 09:24:52.702786 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 09:24:52.706308 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 09:24:52.712497 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 09:24:52.715865 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 09:24:52.719003 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 09:24:52.725874 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4674 09:24:52.729235 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4675 09:24:52.732833 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 09:24:52.735779 Total UI for P1: 0, mck2ui 16
4677 09:24:52.739301 best dqsien dly found for B0: ( 0, 13, 14)
4678 09:24:52.742806 Total UI for P1: 0, mck2ui 16
4679 09:24:52.745704 best dqsien dly found for B1: ( 0, 13, 10)
4680 09:24:52.749150 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4681 09:24:52.752603 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4682 09:24:52.756171
4683 09:24:52.759004 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4684 09:24:52.762571 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4685 09:24:52.765453 [Gating] SW calibration Done
4686 09:24:52.765532 ==
4687 09:24:52.768870 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 09:24:52.772491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 09:24:52.772572 ==
4690 09:24:52.772633 RX Vref Scan: 0
4691 09:24:52.772690
4692 09:24:52.775952 RX Vref 0 -> 0, step: 1
4693 09:24:52.776061
4694 09:24:52.778970 RX Delay -230 -> 252, step: 16
4695 09:24:52.781966 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4696 09:24:52.788565 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4697 09:24:52.792004 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4698 09:24:52.795364 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4699 09:24:52.798613 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4700 09:24:52.802195 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4701 09:24:52.808704 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4702 09:24:52.812064 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4703 09:24:52.815854 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4704 09:24:52.818736 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4705 09:24:52.822275 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4706 09:24:52.829092 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4707 09:24:52.832130 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4708 09:24:52.835233 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4709 09:24:52.838942 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4710 09:24:52.845539 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4711 09:24:52.845641 ==
4712 09:24:52.849107 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 09:24:52.851945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 09:24:52.852067 ==
4715 09:24:52.852160 DQS Delay:
4716 09:24:52.855697 DQS0 = 0, DQS1 = 0
4717 09:24:52.855808 DQM Delay:
4718 09:24:52.858700 DQM0 = 52, DQM1 = 50
4719 09:24:52.858801 DQ Delay:
4720 09:24:52.862382 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4721 09:24:52.865531 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4722 09:24:52.869202 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4723 09:24:52.872105 DQ12 =57, DQ13 =65, DQ14 =49, DQ15 =65
4724 09:24:52.872207
4725 09:24:52.872301
4726 09:24:52.872384 ==
4727 09:24:52.875840 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 09:24:52.878787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 09:24:52.878882 ==
4730 09:24:52.878945
4731 09:24:52.879002
4732 09:24:52.882577 TX Vref Scan disable
4733 09:24:52.885503 == TX Byte 0 ==
4734 09:24:52.889046 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4735 09:24:52.892137 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4736 09:24:52.895822 == TX Byte 1 ==
4737 09:24:52.898796 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4738 09:24:52.902288 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4739 09:24:52.902385 ==
4740 09:24:52.905257 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 09:24:52.912133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 09:24:52.912242 ==
4743 09:24:52.912331
4744 09:24:52.912417
4745 09:24:52.912507 TX Vref Scan disable
4746 09:24:52.916574 == TX Byte 0 ==
4747 09:24:52.919443 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4748 09:24:52.926608 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4749 09:24:52.926689 == TX Byte 1 ==
4750 09:24:52.929946 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4751 09:24:52.933119 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4752 09:24:52.936577
4753 09:24:52.936661 [DATLAT]
4754 09:24:52.936727 Freq=600, CH1 RK1
4755 09:24:52.936820
4756 09:24:52.939971 DATLAT Default: 0x9
4757 09:24:52.940073 0, 0xFFFF, sum = 0
4758 09:24:52.942744 1, 0xFFFF, sum = 0
4759 09:24:52.942844 2, 0xFFFF, sum = 0
4760 09:24:52.946344 3, 0xFFFF, sum = 0
4761 09:24:52.946444 4, 0xFFFF, sum = 0
4762 09:24:52.949738 5, 0xFFFF, sum = 0
4763 09:24:52.949830 6, 0xFFFF, sum = 0
4764 09:24:52.953086 7, 0xFFFF, sum = 0
4765 09:24:52.953183 8, 0x0, sum = 1
4766 09:24:52.956244 9, 0x0, sum = 2
4767 09:24:52.956335 10, 0x0, sum = 3
4768 09:24:52.959397 11, 0x0, sum = 4
4769 09:24:52.959499 best_step = 9
4770 09:24:52.959585
4771 09:24:52.959667 ==
4772 09:24:52.963099 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 09:24:52.969517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 09:24:52.969624 ==
4775 09:24:52.969710 RX Vref Scan: 0
4776 09:24:52.969795
4777 09:24:52.973143 RX Vref 0 -> 0, step: 1
4778 09:24:52.973236
4779 09:24:52.976151 RX Delay -163 -> 252, step: 8
4780 09:24:52.979693 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4781 09:24:52.983169 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4782 09:24:52.989499 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4783 09:24:52.993151 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4784 09:24:52.995941 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4785 09:24:52.999430 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4786 09:24:53.003184 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4787 09:24:53.009768 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4788 09:24:53.012612 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4789 09:24:53.016221 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4790 09:24:53.019794 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4791 09:24:53.026134 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4792 09:24:53.029613 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4793 09:24:53.032950 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4794 09:24:53.036154 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4795 09:24:53.039305 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4796 09:24:53.042588 ==
4797 09:24:53.046010 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 09:24:53.048982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 09:24:53.049065 ==
4800 09:24:53.049126 DQS Delay:
4801 09:24:53.052696 DQS0 = 0, DQS1 = 0
4802 09:24:53.052773 DQM Delay:
4803 09:24:53.056057 DQM0 = 48, DQM1 = 44
4804 09:24:53.056129 DQ Delay:
4805 09:24:53.059400 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4806 09:24:53.062773 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4807 09:24:53.066078 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4808 09:24:53.069378 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4809 09:24:53.069477
4810 09:24:53.069609
4811 09:24:53.075666 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4812 09:24:53.078917 CH1 RK1: MR19=808, MR18=6F24
4813 09:24:53.086032 CH1_RK1: MR19=0x808, MR18=0x6F24, DQSOSC=389, MR23=63, INC=173, DEC=115
4814 09:24:53.088783 [RxdqsGatingPostProcess] freq 600
4815 09:24:53.095850 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4816 09:24:53.095947 Pre-setting of DQS Precalculation
4817 09:24:53.102314 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4818 09:24:53.108951 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4819 09:24:53.115885 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4820 09:24:53.115958
4821 09:24:53.116021
4822 09:24:53.119369 [Calibration Summary] 1200 Mbps
4823 09:24:53.122113 CH 0, Rank 0
4824 09:24:53.122185 SW Impedance : PASS
4825 09:24:53.125664 DUTY Scan : NO K
4826 09:24:53.125735 ZQ Calibration : PASS
4827 09:24:53.129300 Jitter Meter : NO K
4828 09:24:53.132130 CBT Training : PASS
4829 09:24:53.132209 Write leveling : PASS
4830 09:24:53.135554 RX DQS gating : PASS
4831 09:24:53.139194 RX DQ/DQS(RDDQC) : PASS
4832 09:24:53.139274 TX DQ/DQS : PASS
4833 09:24:53.142547 RX DATLAT : PASS
4834 09:24:53.145880 RX DQ/DQS(Engine): PASS
4835 09:24:53.145959 TX OE : NO K
4836 09:24:53.149115 All Pass.
4837 09:24:53.149192
4838 09:24:53.149253 CH 0, Rank 1
4839 09:24:53.152414 SW Impedance : PASS
4840 09:24:53.152494 DUTY Scan : NO K
4841 09:24:53.155828 ZQ Calibration : PASS
4842 09:24:53.159313 Jitter Meter : NO K
4843 09:24:53.159392 CBT Training : PASS
4844 09:24:53.162048 Write leveling : PASS
4845 09:24:53.165824 RX DQS gating : PASS
4846 09:24:53.165904 RX DQ/DQS(RDDQC) : PASS
4847 09:24:53.169069 TX DQ/DQS : PASS
4848 09:24:53.169147 RX DATLAT : PASS
4849 09:24:53.172226 RX DQ/DQS(Engine): PASS
4850 09:24:53.175588 TX OE : NO K
4851 09:24:53.175669 All Pass.
4852 09:24:53.175730
4853 09:24:53.175787 CH 1, Rank 0
4854 09:24:53.178970 SW Impedance : PASS
4855 09:24:53.182417 DUTY Scan : NO K
4856 09:24:53.182525 ZQ Calibration : PASS
4857 09:24:53.185804 Jitter Meter : NO K
4858 09:24:53.189118 CBT Training : PASS
4859 09:24:53.189197 Write leveling : PASS
4860 09:24:53.192384 RX DQS gating : PASS
4861 09:24:53.195710 RX DQ/DQS(RDDQC) : PASS
4862 09:24:53.195790 TX DQ/DQS : PASS
4863 09:24:53.198976 RX DATLAT : PASS
4864 09:24:53.202158 RX DQ/DQS(Engine): PASS
4865 09:24:53.202239 TX OE : NO K
4866 09:24:53.205663 All Pass.
4867 09:24:53.205742
4868 09:24:53.205816 CH 1, Rank 1
4869 09:24:53.208526 SW Impedance : PASS
4870 09:24:53.208605 DUTY Scan : NO K
4871 09:24:53.212092 ZQ Calibration : PASS
4872 09:24:53.215598 Jitter Meter : NO K
4873 09:24:53.215708 CBT Training : PASS
4874 09:24:53.218391 Write leveling : PASS
4875 09:24:53.221843 RX DQS gating : PASS
4876 09:24:53.221950 RX DQ/DQS(RDDQC) : PASS
4877 09:24:53.225430 TX DQ/DQS : PASS
4878 09:24:53.225526 RX DATLAT : PASS
4879 09:24:53.228925 RX DQ/DQS(Engine): PASS
4880 09:24:53.231868 TX OE : NO K
4881 09:24:53.231965 All Pass.
4882 09:24:53.232057
4883 09:24:53.235396 DramC Write-DBI off
4884 09:24:53.235486 PER_BANK_REFRESH: Hybrid Mode
4885 09:24:53.238941 TX_TRACKING: ON
4886 09:24:53.248293 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4887 09:24:53.251831 [FAST_K] Save calibration result to emmc
4888 09:24:53.255277 dramc_set_vcore_voltage set vcore to 662500
4889 09:24:53.255357 Read voltage for 933, 3
4890 09:24:53.258798 Vio18 = 0
4891 09:24:53.258877 Vcore = 662500
4892 09:24:53.258962 Vdram = 0
4893 09:24:53.262201 Vddq = 0
4894 09:24:53.262286 Vmddr = 0
4895 09:24:53.265010 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4896 09:24:53.272195 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4897 09:24:53.274998 MEM_TYPE=3, freq_sel=17
4898 09:24:53.278376 sv_algorithm_assistance_LP4_1600
4899 09:24:53.282244 ============ PULL DRAM RESETB DOWN ============
4900 09:24:53.285003 ========== PULL DRAM RESETB DOWN end =========
4901 09:24:53.291813 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4902 09:24:53.295109 ===================================
4903 09:24:53.295190 LPDDR4 DRAM CONFIGURATION
4904 09:24:53.298588 ===================================
4905 09:24:53.302100 EX_ROW_EN[0] = 0x0
4906 09:24:53.302179 EX_ROW_EN[1] = 0x0
4907 09:24:53.305028 LP4Y_EN = 0x0
4908 09:24:53.305108 WORK_FSP = 0x0
4909 09:24:53.308407 WL = 0x3
4910 09:24:53.308485 RL = 0x3
4911 09:24:53.311703 BL = 0x2
4912 09:24:53.314961 RPST = 0x0
4913 09:24:53.315040 RD_PRE = 0x0
4914 09:24:53.318691 WR_PRE = 0x1
4915 09:24:53.318770 WR_PST = 0x0
4916 09:24:53.322058 DBI_WR = 0x0
4917 09:24:53.322138 DBI_RD = 0x0
4918 09:24:53.324833 OTF = 0x1
4919 09:24:53.328505 ===================================
4920 09:24:53.331949 ===================================
4921 09:24:53.332052 ANA top config
4922 09:24:53.334897 ===================================
4923 09:24:53.338473 DLL_ASYNC_EN = 0
4924 09:24:53.342002 ALL_SLAVE_EN = 1
4925 09:24:53.342075 NEW_RANK_MODE = 1
4926 09:24:53.344877 DLL_IDLE_MODE = 1
4927 09:24:53.348410 LP45_APHY_COMB_EN = 1
4928 09:24:53.351333 TX_ODT_DIS = 1
4929 09:24:53.351426 NEW_8X_MODE = 1
4930 09:24:53.355010 ===================================
4931 09:24:53.357908 ===================================
4932 09:24:53.361418 data_rate = 1866
4933 09:24:53.364967 CKR = 1
4934 09:24:53.368325 DQ_P2S_RATIO = 8
4935 09:24:53.371742 ===================================
4936 09:24:53.375039 CA_P2S_RATIO = 8
4937 09:24:53.377826 DQ_CA_OPEN = 0
4938 09:24:53.377929 DQ_SEMI_OPEN = 0
4939 09:24:53.381429 CA_SEMI_OPEN = 0
4940 09:24:53.384522 CA_FULL_RATE = 0
4941 09:24:53.387829 DQ_CKDIV4_EN = 1
4942 09:24:53.391131 CA_CKDIV4_EN = 1
4943 09:24:53.394529 CA_PREDIV_EN = 0
4944 09:24:53.394603 PH8_DLY = 0
4945 09:24:53.397979 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4946 09:24:53.401410 DQ_AAMCK_DIV = 4
4947 09:24:53.404923 CA_AAMCK_DIV = 4
4948 09:24:53.407637 CA_ADMCK_DIV = 4
4949 09:24:53.411069 DQ_TRACK_CA_EN = 0
4950 09:24:53.414595 CA_PICK = 933
4951 09:24:53.414666 CA_MCKIO = 933
4952 09:24:53.418143 MCKIO_SEMI = 0
4953 09:24:53.421543 PLL_FREQ = 3732
4954 09:24:53.424346 DQ_UI_PI_RATIO = 32
4955 09:24:53.427681 CA_UI_PI_RATIO = 0
4956 09:24:53.431034 ===================================
4957 09:24:53.434220 ===================================
4958 09:24:53.438013 memory_type:LPDDR4
4959 09:24:53.438084 GP_NUM : 10
4960 09:24:53.441229 SRAM_EN : 1
4961 09:24:53.441296 MD32_EN : 0
4962 09:24:53.444517 ===================================
4963 09:24:53.447911 [ANA_INIT] >>>>>>>>>>>>>>
4964 09:24:53.451453 <<<<<< [CONFIGURE PHASE]: ANA_TX
4965 09:24:53.454267 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4966 09:24:53.457791 ===================================
4967 09:24:53.461271 data_rate = 1866,PCW = 0X8f00
4968 09:24:53.464188 ===================================
4969 09:24:53.467797 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4970 09:24:53.470754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4971 09:24:53.477817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4972 09:24:53.484497 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4973 09:24:53.487382 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4974 09:24:53.491064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4975 09:24:53.491160 [ANA_INIT] flow start
4976 09:24:53.494574 [ANA_INIT] PLL >>>>>>>>
4977 09:24:53.497862 [ANA_INIT] PLL <<<<<<<<
4978 09:24:53.497943 [ANA_INIT] MIDPI >>>>>>>>
4979 09:24:53.501208 [ANA_INIT] MIDPI <<<<<<<<
4980 09:24:53.504003 [ANA_INIT] DLL >>>>>>>>
4981 09:24:53.504102 [ANA_INIT] flow end
4982 09:24:53.510704 ============ LP4 DIFF to SE enter ============
4983 09:24:53.514179 ============ LP4 DIFF to SE exit ============
4984 09:24:53.514261 [ANA_INIT] <<<<<<<<<<<<<
4985 09:24:53.517520 [Flow] Enable top DCM control >>>>>
4986 09:24:53.520854 [Flow] Enable top DCM control <<<<<
4987 09:24:53.524405 Enable DLL master slave shuffle
4988 09:24:53.530704 ==============================================================
4989 09:24:53.534337 Gating Mode config
4990 09:24:53.537175 ==============================================================
4991 09:24:53.540788 Config description:
4992 09:24:53.550544 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4993 09:24:53.557404 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4994 09:24:53.560516 SELPH_MODE 0: By rank 1: By Phase
4995 09:24:53.567643 ==============================================================
4996 09:24:53.570529 GAT_TRACK_EN = 1
4997 09:24:53.573454 RX_GATING_MODE = 2
4998 09:24:53.577066 RX_GATING_TRACK_MODE = 2
4999 09:24:53.577191 SELPH_MODE = 1
5000 09:24:53.580607 PICG_EARLY_EN = 1
5001 09:24:53.583399 VALID_LAT_VALUE = 1
5002 09:24:53.590199 ==============================================================
5003 09:24:53.593478 Enter into Gating configuration >>>>
5004 09:24:53.597035 Exit from Gating configuration <<<<
5005 09:24:53.600665 Enter into DVFS_PRE_config >>>>>
5006 09:24:53.610142 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5007 09:24:53.613481 Exit from DVFS_PRE_config <<<<<
5008 09:24:53.616947 Enter into PICG configuration >>>>
5009 09:24:53.620245 Exit from PICG configuration <<<<
5010 09:24:53.623772 [RX_INPUT] configuration >>>>>
5011 09:24:53.626579 [RX_INPUT] configuration <<<<<
5012 09:24:53.630064 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5013 09:24:53.636437 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5014 09:24:53.643068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5015 09:24:53.650275 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5016 09:24:53.656889 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 09:24:53.659746 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 09:24:53.666273 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5019 09:24:53.669723 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5020 09:24:53.673048 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5021 09:24:53.676479 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5022 09:24:53.683088 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5023 09:24:53.686295 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 09:24:53.690265 ===================================
5025 09:24:53.693068 LPDDR4 DRAM CONFIGURATION
5026 09:24:53.696723 ===================================
5027 09:24:53.696803 EX_ROW_EN[0] = 0x0
5028 09:24:53.700139 EX_ROW_EN[1] = 0x0
5029 09:24:53.700219 LP4Y_EN = 0x0
5030 09:24:53.703495 WORK_FSP = 0x0
5031 09:24:53.703573 WL = 0x3
5032 09:24:53.706259 RL = 0x3
5033 09:24:53.706366 BL = 0x2
5034 09:24:53.709892 RPST = 0x0
5035 09:24:53.709967 RD_PRE = 0x0
5036 09:24:53.713495 WR_PRE = 0x1
5037 09:24:53.713600 WR_PST = 0x0
5038 09:24:53.716420 DBI_WR = 0x0
5039 09:24:53.716493 DBI_RD = 0x0
5040 09:24:53.719754 OTF = 0x1
5041 09:24:53.723023 ===================================
5042 09:24:53.726328 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5043 09:24:53.729705 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5044 09:24:53.736513 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 09:24:53.739732 ===================================
5046 09:24:53.739835 LPDDR4 DRAM CONFIGURATION
5047 09:24:53.743310 ===================================
5048 09:24:53.746087 EX_ROW_EN[0] = 0x10
5049 09:24:53.749719 EX_ROW_EN[1] = 0x0
5050 09:24:53.749793 LP4Y_EN = 0x0
5051 09:24:53.753435 WORK_FSP = 0x0
5052 09:24:53.753530 WL = 0x3
5053 09:24:53.756219 RL = 0x3
5054 09:24:53.756289 BL = 0x2
5055 09:24:53.759802 RPST = 0x0
5056 09:24:53.759874 RD_PRE = 0x0
5057 09:24:53.763373 WR_PRE = 0x1
5058 09:24:53.763444 WR_PST = 0x0
5059 09:24:53.766325 DBI_WR = 0x0
5060 09:24:53.766401 DBI_RD = 0x0
5061 09:24:53.769946 OTF = 0x1
5062 09:24:53.772764 ===================================
5063 09:24:53.779426 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5064 09:24:53.782923 nWR fixed to 30
5065 09:24:53.786527 [ModeRegInit_LP4] CH0 RK0
5066 09:24:53.786606 [ModeRegInit_LP4] CH0 RK1
5067 09:24:53.789363 [ModeRegInit_LP4] CH1 RK0
5068 09:24:53.792952 [ModeRegInit_LP4] CH1 RK1
5069 09:24:53.793047 match AC timing 9
5070 09:24:53.799602 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5071 09:24:53.802944 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5072 09:24:53.806202 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5073 09:24:53.812704 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5074 09:24:53.816395 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5075 09:24:53.816493 ==
5076 09:24:53.819668 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 09:24:53.823033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 09:24:53.823109 ==
5079 09:24:53.829306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5080 09:24:53.836227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5081 09:24:53.839497 [CA 0] Center 37 (6~68) winsize 63
5082 09:24:53.842810 [CA 1] Center 37 (6~68) winsize 63
5083 09:24:53.846029 [CA 2] Center 34 (4~65) winsize 62
5084 09:24:53.849531 [CA 3] Center 34 (3~65) winsize 63
5085 09:24:53.852779 [CA 4] Center 33 (2~64) winsize 63
5086 09:24:53.855776 [CA 5] Center 32 (2~62) winsize 61
5087 09:24:53.855875
5088 09:24:53.859412 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5089 09:24:53.859485
5090 09:24:53.862297 [CATrainingPosCal] consider 1 rank data
5091 09:24:53.866019 u2DelayCellTimex100 = 270/100 ps
5092 09:24:53.868982 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5093 09:24:53.872601 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5094 09:24:53.876143 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5095 09:24:53.878975 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5096 09:24:53.882539 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5097 09:24:53.885557 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5098 09:24:53.885645
5099 09:24:53.892741 CA PerBit enable=1, Macro0, CA PI delay=32
5100 09:24:53.892826
5101 09:24:53.895636 [CBTSetCACLKResult] CA Dly = 32
5102 09:24:53.895737 CS Dly: 5 (0~36)
5103 09:24:53.895832 ==
5104 09:24:53.899281 Dram Type= 6, Freq= 0, CH_0, rank 1
5105 09:24:53.902145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 09:24:53.902225 ==
5107 09:24:53.908645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5108 09:24:53.915721 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5109 09:24:53.919193 [CA 0] Center 37 (6~68) winsize 63
5110 09:24:53.922510 [CA 1] Center 37 (6~68) winsize 63
5111 09:24:53.925729 [CA 2] Center 34 (4~65) winsize 62
5112 09:24:53.928824 [CA 3] Center 34 (3~65) winsize 63
5113 09:24:53.931991 [CA 4] Center 32 (2~63) winsize 62
5114 09:24:53.935457 [CA 5] Center 32 (2~62) winsize 61
5115 09:24:53.935547
5116 09:24:53.939178 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5117 09:24:53.939278
5118 09:24:53.942303 [CATrainingPosCal] consider 2 rank data
5119 09:24:53.945879 u2DelayCellTimex100 = 270/100 ps
5120 09:24:53.949048 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5121 09:24:53.952328 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5122 09:24:53.955559 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5123 09:24:53.958621 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5124 09:24:53.962283 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5125 09:24:53.969044 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5126 09:24:53.969163
5127 09:24:53.972354 CA PerBit enable=1, Macro0, CA PI delay=32
5128 09:24:53.972438
5129 09:24:53.975614 [CBTSetCACLKResult] CA Dly = 32
5130 09:24:53.975698 CS Dly: 5 (0~37)
5131 09:24:53.975760
5132 09:24:53.979185 ----->DramcWriteLeveling(PI) begin...
5133 09:24:53.979266 ==
5134 09:24:53.982154 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 09:24:53.985696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 09:24:53.988744 ==
5137 09:24:53.988821 Write leveling (Byte 0): 31 => 31
5138 09:24:53.992223 Write leveling (Byte 1): 27 => 27
5139 09:24:53.995733 DramcWriteLeveling(PI) end<-----
5140 09:24:53.995807
5141 09:24:53.995865 ==
5142 09:24:53.998597 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 09:24:54.005080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 09:24:54.005164 ==
5145 09:24:54.008681 [Gating] SW mode calibration
5146 09:24:54.015233 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5147 09:24:54.018855 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5148 09:24:54.025463 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
5149 09:24:54.028496 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 09:24:54.032181 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 09:24:54.035631 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 09:24:54.041844 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 09:24:54.045414 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 09:24:54.048719 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5155 09:24:54.055231 0 14 28 | B1->B0 | 3434 2626 | 0 0 | (0 0) (1 0)
5156 09:24:54.058723 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5157 09:24:54.062187 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 09:24:54.068847 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 09:24:54.072074 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 09:24:54.075507 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 09:24:54.082027 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 09:24:54.085189 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 09:24:54.089046 0 15 28 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
5164 09:24:54.095553 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5165 09:24:54.098953 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 09:24:54.102053 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 09:24:54.108353 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 09:24:54.112042 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 09:24:54.114994 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 09:24:54.122133 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5171 09:24:54.124986 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5172 09:24:54.128488 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5173 09:24:54.135633 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 09:24:54.138567 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 09:24:54.142153 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 09:24:54.148183 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 09:24:54.151782 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 09:24:54.155305 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 09:24:54.158090 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 09:24:54.165172 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 09:24:54.168728 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 09:24:54.171457 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 09:24:54.178475 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 09:24:54.181746 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 09:24:54.185196 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 09:24:54.191642 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5187 09:24:54.195024 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5188 09:24:54.198256 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5189 09:24:54.201442 Total UI for P1: 0, mck2ui 16
5190 09:24:54.205128 best dqsien dly found for B0: ( 1, 2, 26)
5191 09:24:54.211603 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 09:24:54.211717 Total UI for P1: 0, mck2ui 16
5193 09:24:54.218294 best dqsien dly found for B1: ( 1, 2, 30)
5194 09:24:54.221948 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5195 09:24:54.224782 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5196 09:24:54.224921
5197 09:24:54.228385 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5198 09:24:54.231307 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5199 09:24:54.234981 [Gating] SW calibration Done
5200 09:24:54.235118 ==
5201 09:24:54.238582 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 09:24:54.241440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 09:24:54.241556 ==
5204 09:24:54.245121 RX Vref Scan: 0
5205 09:24:54.245276
5206 09:24:54.245450 RX Vref 0 -> 0, step: 1
5207 09:24:54.245566
5208 09:24:54.248000 RX Delay -80 -> 252, step: 8
5209 09:24:54.251435 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5210 09:24:54.258123 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5211 09:24:54.261514 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5212 09:24:54.264295 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5213 09:24:54.268191 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5214 09:24:54.271009 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5215 09:24:54.278105 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5216 09:24:54.281014 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5217 09:24:54.284424 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5218 09:24:54.288014 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5219 09:24:54.291437 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5220 09:24:54.294793 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5221 09:24:54.298169 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5222 09:24:54.304230 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5223 09:24:54.307870 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5224 09:24:54.311198 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5225 09:24:54.311319 ==
5226 09:24:54.314490 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 09:24:54.317946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 09:24:54.321193 ==
5229 09:24:54.321321 DQS Delay:
5230 09:24:54.321412 DQS0 = 0, DQS1 = 0
5231 09:24:54.324582 DQM Delay:
5232 09:24:54.324659 DQM0 = 104, DQM1 = 95
5233 09:24:54.327840 DQ Delay:
5234 09:24:54.327943 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5235 09:24:54.331246 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5236 09:24:54.334747 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5237 09:24:54.340642 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5238 09:24:54.340739
5239 09:24:54.340834
5240 09:24:54.340921 ==
5241 09:24:54.344255 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 09:24:54.347797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 09:24:54.347883 ==
5244 09:24:54.347962
5245 09:24:54.348047
5246 09:24:54.350668 TX Vref Scan disable
5247 09:24:54.350772 == TX Byte 0 ==
5248 09:24:54.357836 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5249 09:24:54.361303 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5250 09:24:54.361420 == TX Byte 1 ==
5251 09:24:54.367787 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5252 09:24:54.371146 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5253 09:24:54.371266 ==
5254 09:24:54.374598 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 09:24:54.377470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 09:24:54.377587 ==
5257 09:24:54.377649
5258 09:24:54.377704
5259 09:24:54.381052 TX Vref Scan disable
5260 09:24:54.384518 == TX Byte 0 ==
5261 09:24:54.387413 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5262 09:24:54.390831 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5263 09:24:54.394340 == TX Byte 1 ==
5264 09:24:54.397119 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5265 09:24:54.400677 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5266 09:24:54.404287
5267 09:24:54.404451 [DATLAT]
5268 09:24:54.404556 Freq=933, CH0 RK0
5269 09:24:54.404650
5270 09:24:54.407263 DATLAT Default: 0xd
5271 09:24:54.407487 0, 0xFFFF, sum = 0
5272 09:24:54.410354 1, 0xFFFF, sum = 0
5273 09:24:54.410498 2, 0xFFFF, sum = 0
5274 09:24:54.413583 3, 0xFFFF, sum = 0
5275 09:24:54.417138 4, 0xFFFF, sum = 0
5276 09:24:54.417300 5, 0xFFFF, sum = 0
5277 09:24:54.420606 6, 0xFFFF, sum = 0
5278 09:24:54.420721 7, 0xFFFF, sum = 0
5279 09:24:54.423976 8, 0xFFFF, sum = 0
5280 09:24:54.424088 9, 0xFFFF, sum = 0
5281 09:24:54.427148 10, 0x0, sum = 1
5282 09:24:54.427256 11, 0x0, sum = 2
5283 09:24:54.430680 12, 0x0, sum = 3
5284 09:24:54.430790 13, 0x0, sum = 4
5285 09:24:54.430881 best_step = 11
5286 09:24:54.430970
5287 09:24:54.433588 ==
5288 09:24:54.437022 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 09:24:54.440395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 09:24:54.440499 ==
5291 09:24:54.440591 RX Vref Scan: 1
5292 09:24:54.440676
5293 09:24:54.443765 RX Vref 0 -> 0, step: 1
5294 09:24:54.443865
5295 09:24:54.447276 RX Delay -45 -> 252, step: 4
5296 09:24:54.447375
5297 09:24:54.450268 Set Vref, RX VrefLevel [Byte0]: 55
5298 09:24:54.453900 [Byte1]: 54
5299 09:24:54.454007
5300 09:24:54.456683 Final RX Vref Byte 0 = 55 to rank0
5301 09:24:54.460188 Final RX Vref Byte 1 = 54 to rank0
5302 09:24:54.463732 Final RX Vref Byte 0 = 55 to rank1
5303 09:24:54.466609 Final RX Vref Byte 1 = 54 to rank1==
5304 09:24:54.470222 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 09:24:54.473351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 09:24:54.476481 ==
5307 09:24:54.476606 DQS Delay:
5308 09:24:54.476680 DQS0 = 0, DQS1 = 0
5309 09:24:54.480463 DQM Delay:
5310 09:24:54.480601 DQM0 = 104, DQM1 = 96
5311 09:24:54.483704 DQ Delay:
5312 09:24:54.486569 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =104
5313 09:24:54.490216 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5314 09:24:54.493733 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =92
5315 09:24:54.496412 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5316 09:24:54.496526
5317 09:24:54.496605
5318 09:24:54.503580 [DQSOSCAuto] RK0, (LSB)MR18= 0x362e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 404 ps
5319 09:24:54.507077 CH0 RK0: MR19=505, MR18=362E
5320 09:24:54.513446 CH0_RK0: MR19=0x505, MR18=0x362E, DQSOSC=404, MR23=63, INC=66, DEC=44
5321 09:24:54.513609
5322 09:24:54.517137 ----->DramcWriteLeveling(PI) begin...
5323 09:24:54.517261 ==
5324 09:24:54.519930 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 09:24:54.523484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 09:24:54.523602 ==
5327 09:24:54.526970 Write leveling (Byte 0): 31 => 31
5328 09:24:54.530153 Write leveling (Byte 1): 28 => 28
5329 09:24:54.533523 DramcWriteLeveling(PI) end<-----
5330 09:24:54.533663
5331 09:24:54.533776 ==
5332 09:24:54.536725 Dram Type= 6, Freq= 0, CH_0, rank 1
5333 09:24:54.540269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 09:24:54.540355 ==
5335 09:24:54.543256 [Gating] SW mode calibration
5336 09:24:54.549649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5337 09:24:54.556473 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5338 09:24:54.559871 0 14 0 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
5339 09:24:54.566303 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 09:24:54.570002 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 09:24:54.572922 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 09:24:54.580053 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 09:24:54.583487 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 09:24:54.586216 0 14 24 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 1)
5345 09:24:54.592906 0 14 28 | B1->B0 | 2727 2c2c | 1 0 | (1 1) (0 0)
5346 09:24:54.596396 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 09:24:54.600084 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 09:24:54.606464 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 09:24:54.610116 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 09:24:54.612858 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 09:24:54.619388 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 09:24:54.623004 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5353 09:24:54.626584 0 15 28 | B1->B0 | 3f3f 3939 | 0 0 | (1 1) (0 0)
5354 09:24:54.629434 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5355 09:24:54.636429 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 09:24:54.639184 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 09:24:54.643276 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 09:24:54.649644 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 09:24:54.652602 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 09:24:54.656156 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 09:24:54.663151 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5362 09:24:54.666064 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 09:24:54.669582 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 09:24:54.676362 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 09:24:54.679326 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 09:24:54.682912 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 09:24:54.689206 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 09:24:54.692740 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 09:24:54.696191 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 09:24:54.702927 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 09:24:54.706247 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 09:24:54.709355 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 09:24:54.715806 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 09:24:54.719422 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 09:24:54.722428 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 09:24:54.729705 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 09:24:54.732556 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5378 09:24:54.736127 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 09:24:54.739057 Total UI for P1: 0, mck2ui 16
5380 09:24:54.742752 best dqsien dly found for B0: ( 1, 2, 28)
5381 09:24:54.746142 Total UI for P1: 0, mck2ui 16
5382 09:24:54.749523 best dqsien dly found for B1: ( 1, 2, 28)
5383 09:24:54.752913 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5384 09:24:54.755783 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5385 09:24:54.755902
5386 09:24:54.759187 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5387 09:24:54.766252 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5388 09:24:54.766404 [Gating] SW calibration Done
5389 09:24:54.766495 ==
5390 09:24:54.769138 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 09:24:54.775716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 09:24:54.775859 ==
5393 09:24:54.775967 RX Vref Scan: 0
5394 09:24:54.776056
5395 09:24:54.779257 RX Vref 0 -> 0, step: 1
5396 09:24:54.779371
5397 09:24:54.782736 RX Delay -80 -> 252, step: 8
5398 09:24:54.786140 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5399 09:24:54.789468 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5400 09:24:54.792829 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5401 09:24:54.795787 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5402 09:24:54.802369 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5403 09:24:54.806059 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5404 09:24:54.809490 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5405 09:24:54.812346 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5406 09:24:54.815794 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5407 09:24:54.819222 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5408 09:24:54.826173 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5409 09:24:54.829104 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5410 09:24:54.832613 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5411 09:24:54.835643 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5412 09:24:54.839268 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5413 09:24:54.845757 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5414 09:24:54.845870 ==
5415 09:24:54.849285 Dram Type= 6, Freq= 0, CH_0, rank 1
5416 09:24:54.851997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5417 09:24:54.852093 ==
5418 09:24:54.852178 DQS Delay:
5419 09:24:54.855430 DQS0 = 0, DQS1 = 0
5420 09:24:54.855525 DQM Delay:
5421 09:24:54.858791 DQM0 = 105, DQM1 = 94
5422 09:24:54.858883 DQ Delay:
5423 09:24:54.862394 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5424 09:24:54.865229 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5425 09:24:54.868743 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5426 09:24:54.872074 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5427 09:24:54.872184
5428 09:24:54.872278
5429 09:24:54.872367 ==
5430 09:24:54.875541 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 09:24:54.879072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 09:24:54.881973 ==
5433 09:24:54.882071
5434 09:24:54.882163
5435 09:24:54.882250 TX Vref Scan disable
5436 09:24:54.885564 == TX Byte 0 ==
5437 09:24:54.888541 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5438 09:24:54.892051 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5439 09:24:54.895559 == TX Byte 1 ==
5440 09:24:54.899053 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5441 09:24:54.902292 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5442 09:24:54.905817 ==
5443 09:24:54.908662 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 09:24:54.912159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 09:24:54.912246 ==
5446 09:24:54.912308
5447 09:24:54.912363
5448 09:24:54.915039 TX Vref Scan disable
5449 09:24:54.915143 == TX Byte 0 ==
5450 09:24:54.922157 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5451 09:24:54.925612 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5452 09:24:54.925688 == TX Byte 1 ==
5453 09:24:54.931785 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5454 09:24:54.935431 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5455 09:24:54.935543
5456 09:24:54.935631 [DATLAT]
5457 09:24:54.938360 Freq=933, CH0 RK1
5458 09:24:54.938434
5459 09:24:54.938521 DATLAT Default: 0xb
5460 09:24:54.942049 0, 0xFFFF, sum = 0
5461 09:24:54.942153 1, 0xFFFF, sum = 0
5462 09:24:54.945534 2, 0xFFFF, sum = 0
5463 09:24:54.945627 3, 0xFFFF, sum = 0
5464 09:24:54.948458 4, 0xFFFF, sum = 0
5465 09:24:54.948556 5, 0xFFFF, sum = 0
5466 09:24:54.952058 6, 0xFFFF, sum = 0
5467 09:24:54.954811 7, 0xFFFF, sum = 0
5468 09:24:54.954920 8, 0xFFFF, sum = 0
5469 09:24:54.958229 9, 0xFFFF, sum = 0
5470 09:24:54.958322 10, 0x0, sum = 1
5471 09:24:54.961686 11, 0x0, sum = 2
5472 09:24:54.961765 12, 0x0, sum = 3
5473 09:24:54.961839 13, 0x0, sum = 4
5474 09:24:54.964963 best_step = 11
5475 09:24:54.965034
5476 09:24:54.965111 ==
5477 09:24:54.968335 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 09:24:54.971982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 09:24:54.972081 ==
5480 09:24:54.974664 RX Vref Scan: 0
5481 09:24:54.974766
5482 09:24:54.974865 RX Vref 0 -> 0, step: 1
5483 09:24:54.978226
5484 09:24:54.978330 RX Delay -45 -> 252, step: 4
5485 09:24:54.986112 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5486 09:24:54.988676 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5487 09:24:54.992074 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5488 09:24:54.995672 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5489 09:24:54.999237 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5490 09:24:55.005664 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5491 09:24:55.009231 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5492 09:24:55.012497 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5493 09:24:55.015220 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5494 09:24:55.019187 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5495 09:24:55.022494 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5496 09:24:55.028835 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5497 09:24:55.032333 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5498 09:24:55.035671 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5499 09:24:55.039115 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5500 09:24:55.041918 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5501 09:24:55.045453 ==
5502 09:24:55.049055 Dram Type= 6, Freq= 0, CH_0, rank 1
5503 09:24:55.051960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 09:24:55.052059 ==
5505 09:24:55.052127 DQS Delay:
5506 09:24:55.055540 DQS0 = 0, DQS1 = 0
5507 09:24:55.055641 DQM Delay:
5508 09:24:55.059110 DQM0 = 103, DQM1 = 95
5509 09:24:55.059185 DQ Delay:
5510 09:24:55.061985 DQ0 =100, DQ1 =104, DQ2 =102, DQ3 =102
5511 09:24:55.065605 DQ4 =106, DQ5 =96, DQ6 =108, DQ7 =112
5512 09:24:55.069100 DQ8 =88, DQ9 =86, DQ10 =94, DQ11 =88
5513 09:24:55.071851 DQ12 =98, DQ13 =100, DQ14 =104, DQ15 =102
5514 09:24:55.071961
5515 09:24:55.072050
5516 09:24:55.082096 [DQSOSCAuto] RK1, (LSB)MR18= 0x3008, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 406 ps
5517 09:24:55.082233 CH0 RK1: MR19=505, MR18=3008
5518 09:24:55.088912 CH0_RK1: MR19=0x505, MR18=0x3008, DQSOSC=406, MR23=63, INC=65, DEC=43
5519 09:24:55.091744 [RxdqsGatingPostProcess] freq 933
5520 09:24:55.099276 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5521 09:24:55.102130 best DQS0 dly(2T, 0.5T) = (0, 10)
5522 09:24:55.104929 best DQS1 dly(2T, 0.5T) = (0, 10)
5523 09:24:55.108501 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5524 09:24:55.111979 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5525 09:24:55.112096 best DQS0 dly(2T, 0.5T) = (0, 10)
5526 09:24:55.115513 best DQS1 dly(2T, 0.5T) = (0, 10)
5527 09:24:55.118373 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5528 09:24:55.121805 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5529 09:24:55.125233 Pre-setting of DQS Precalculation
5530 09:24:55.131751 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5531 09:24:55.131878 ==
5532 09:24:55.135303 Dram Type= 6, Freq= 0, CH_1, rank 0
5533 09:24:55.138879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 09:24:55.139000 ==
5535 09:24:55.145183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5536 09:24:55.151718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5537 09:24:55.155388 [CA 0] Center 36 (6~67) winsize 62
5538 09:24:55.158280 [CA 1] Center 36 (6~67) winsize 62
5539 09:24:55.161763 [CA 2] Center 34 (4~65) winsize 62
5540 09:24:55.165330 [CA 3] Center 34 (4~65) winsize 62
5541 09:24:55.168183 [CA 4] Center 34 (4~64) winsize 61
5542 09:24:55.168282 [CA 5] Center 33 (3~64) winsize 62
5543 09:24:55.171655
5544 09:24:55.175148 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5545 09:24:55.175248
5546 09:24:55.178007 [CATrainingPosCal] consider 1 rank data
5547 09:24:55.181726 u2DelayCellTimex100 = 270/100 ps
5548 09:24:55.185092 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5549 09:24:55.188329 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5550 09:24:55.191762 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5551 09:24:55.195090 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5552 09:24:55.198589 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5553 09:24:55.201964 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5554 09:24:55.202047
5555 09:24:55.205295 CA PerBit enable=1, Macro0, CA PI delay=33
5556 09:24:55.205395
5557 09:24:55.208191 [CBTSetCACLKResult] CA Dly = 33
5558 09:24:55.211574 CS Dly: 7 (0~38)
5559 09:24:55.211646 ==
5560 09:24:55.215163 Dram Type= 6, Freq= 0, CH_1, rank 1
5561 09:24:55.218073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 09:24:55.218155 ==
5563 09:24:55.224881 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5564 09:24:55.231774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5565 09:24:55.235088 [CA 0] Center 37 (7~67) winsize 61
5566 09:24:55.238366 [CA 1] Center 37 (7~68) winsize 62
5567 09:24:55.241710 [CA 2] Center 35 (5~65) winsize 61
5568 09:24:55.245107 [CA 3] Center 34 (4~65) winsize 62
5569 09:24:55.248464 [CA 4] Center 34 (4~65) winsize 62
5570 09:24:55.248569 [CA 5] Center 33 (3~64) winsize 62
5571 09:24:55.251226
5572 09:24:55.254758 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5573 09:24:55.254881
5574 09:24:55.258434 [CATrainingPosCal] consider 2 rank data
5575 09:24:55.261245 u2DelayCellTimex100 = 270/100 ps
5576 09:24:55.264820 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5577 09:24:55.268392 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5578 09:24:55.271074 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5579 09:24:55.274726 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5580 09:24:55.278225 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5581 09:24:55.281149 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5582 09:24:55.281243
5583 09:24:55.287648 CA PerBit enable=1, Macro0, CA PI delay=33
5584 09:24:55.287758
5585 09:24:55.287823 [CBTSetCACLKResult] CA Dly = 33
5586 09:24:55.291159 CS Dly: 8 (0~40)
5587 09:24:55.291288
5588 09:24:55.294111 ----->DramcWriteLeveling(PI) begin...
5589 09:24:55.294225 ==
5590 09:24:55.297640 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 09:24:55.301078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 09:24:55.301200 ==
5593 09:24:55.304396 Write leveling (Byte 0): 28 => 28
5594 09:24:55.307740 Write leveling (Byte 1): 28 => 28
5595 09:24:55.311171 DramcWriteLeveling(PI) end<-----
5596 09:24:55.311298
5597 09:24:55.311389 ==
5598 09:24:55.314023 Dram Type= 6, Freq= 0, CH_1, rank 0
5599 09:24:55.320898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5600 09:24:55.321010 ==
5601 09:24:55.321112 [Gating] SW mode calibration
5602 09:24:55.331206 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5603 09:24:55.334551 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5604 09:24:55.337917 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 09:24:55.344236 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 09:24:55.347732 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 09:24:55.350542 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 09:24:55.357125 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 09:24:55.361027 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 09:24:55.363995 0 14 24 | B1->B0 | 3333 2d2d | 1 1 | (1 0) (1 0)
5611 09:24:55.370485 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
5612 09:24:55.374019 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 09:24:55.377026 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 09:24:55.384060 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 09:24:55.387565 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 09:24:55.390327 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 09:24:55.397622 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 09:24:55.400499 0 15 24 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
5619 09:24:55.404144 0 15 28 | B1->B0 | 3e3d 4646 | 1 0 | (0 0) (0 0)
5620 09:24:55.410514 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 09:24:55.414010 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 09:24:55.417505 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 09:24:55.423836 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 09:24:55.427370 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 09:24:55.430901 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 09:24:55.437117 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5627 09:24:55.440533 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 09:24:55.444008 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 09:24:55.450632 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 09:24:55.454008 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 09:24:55.456756 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 09:24:55.460066 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 09:24:55.467324 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 09:24:55.470658 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 09:24:55.473661 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 09:24:55.480230 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 09:24:55.483792 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 09:24:55.487380 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 09:24:55.493869 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 09:24:55.497460 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 09:24:55.500181 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 09:24:55.507334 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5643 09:24:55.510164 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5644 09:24:55.513701 Total UI for P1: 0, mck2ui 16
5645 09:24:55.517114 best dqsien dly found for B1: ( 1, 2, 24)
5646 09:24:55.520494 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 09:24:55.523496 Total UI for P1: 0, mck2ui 16
5648 09:24:55.527045 best dqsien dly found for B0: ( 1, 2, 26)
5649 09:24:55.530583 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5650 09:24:55.533483 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5651 09:24:55.533597
5652 09:24:55.537027 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5653 09:24:55.543418 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5654 09:24:55.543513 [Gating] SW calibration Done
5655 09:24:55.543575 ==
5656 09:24:55.546861 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 09:24:55.553636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 09:24:55.553748 ==
5659 09:24:55.553813 RX Vref Scan: 0
5660 09:24:55.553872
5661 09:24:55.556939 RX Vref 0 -> 0, step: 1
5662 09:24:55.557017
5663 09:24:55.560168 RX Delay -80 -> 252, step: 8
5664 09:24:55.563519 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5665 09:24:55.566829 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5666 09:24:55.570422 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5667 09:24:55.573678 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5668 09:24:55.580428 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5669 09:24:55.583794 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5670 09:24:55.586537 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5671 09:24:55.590166 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5672 09:24:55.593638 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5673 09:24:55.596634 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5674 09:24:55.603629 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5675 09:24:55.606512 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5676 09:24:55.610152 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5677 09:24:55.613021 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5678 09:24:55.616623 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5679 09:24:55.623124 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5680 09:24:55.623245 ==
5681 09:24:55.626536 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 09:24:55.630173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 09:24:55.630288 ==
5684 09:24:55.630377 DQS Delay:
5685 09:24:55.633045 DQS0 = 0, DQS1 = 0
5686 09:24:55.633161 DQM Delay:
5687 09:24:55.636427 DQM0 = 102, DQM1 = 98
5688 09:24:55.636540 DQ Delay:
5689 09:24:55.640050 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5690 09:24:55.643614 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5691 09:24:55.646395 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5692 09:24:55.650080 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5693 09:24:55.650192
5694 09:24:55.650256
5695 09:24:55.650313 ==
5696 09:24:55.652968 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 09:24:55.660132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 09:24:55.660254 ==
5699 09:24:55.660354
5700 09:24:55.660448
5701 09:24:55.660543 TX Vref Scan disable
5702 09:24:55.663636 == TX Byte 0 ==
5703 09:24:55.666841 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5704 09:24:55.673461 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5705 09:24:55.673605 == TX Byte 1 ==
5706 09:24:55.676826 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5707 09:24:55.683062 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5708 09:24:55.683184 ==
5709 09:24:55.686419 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 09:24:55.689733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 09:24:55.689830 ==
5712 09:24:55.689890
5713 09:24:55.689951
5714 09:24:55.693099 TX Vref Scan disable
5715 09:24:55.693198 == TX Byte 0 ==
5716 09:24:55.699735 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5717 09:24:55.703427 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5718 09:24:55.703548 == TX Byte 1 ==
5719 09:24:55.709763 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5720 09:24:55.713379 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5721 09:24:55.713501
5722 09:24:55.713596 [DATLAT]
5723 09:24:55.717006 Freq=933, CH1 RK0
5724 09:24:55.717104
5725 09:24:55.717189 DATLAT Default: 0xd
5726 09:24:55.719920 0, 0xFFFF, sum = 0
5727 09:24:55.720010 1, 0xFFFF, sum = 0
5728 09:24:55.722921 2, 0xFFFF, sum = 0
5729 09:24:55.723008 3, 0xFFFF, sum = 0
5730 09:24:55.726434 4, 0xFFFF, sum = 0
5731 09:24:55.726552 5, 0xFFFF, sum = 0
5732 09:24:55.729969 6, 0xFFFF, sum = 0
5733 09:24:55.733397 7, 0xFFFF, sum = 0
5734 09:24:55.733509 8, 0xFFFF, sum = 0
5735 09:24:55.736255 9, 0xFFFF, sum = 0
5736 09:24:55.736368 10, 0x0, sum = 1
5737 09:24:55.736462 11, 0x0, sum = 2
5738 09:24:55.739732 12, 0x0, sum = 3
5739 09:24:55.739815 13, 0x0, sum = 4
5740 09:24:55.743164 best_step = 11
5741 09:24:55.743279
5742 09:24:55.743366 ==
5743 09:24:55.746792 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 09:24:55.749591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 09:24:55.749690 ==
5746 09:24:55.753085 RX Vref Scan: 1
5747 09:24:55.753157
5748 09:24:55.753231 RX Vref 0 -> 0, step: 1
5749 09:24:55.755981
5750 09:24:55.756093 RX Delay -45 -> 252, step: 4
5751 09:24:55.756186
5752 09:24:55.759599 Set Vref, RX VrefLevel [Byte0]: 53
5753 09:24:55.763138 [Byte1]: 50
5754 09:24:55.767422
5755 09:24:55.767517 Final RX Vref Byte 0 = 53 to rank0
5756 09:24:55.770956 Final RX Vref Byte 1 = 50 to rank0
5757 09:24:55.773688 Final RX Vref Byte 0 = 53 to rank1
5758 09:24:55.777210 Final RX Vref Byte 1 = 50 to rank1==
5759 09:24:55.780691 Dram Type= 6, Freq= 0, CH_1, rank 0
5760 09:24:55.787036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 09:24:55.787178 ==
5762 09:24:55.787270 DQS Delay:
5763 09:24:55.787357 DQS0 = 0, DQS1 = 0
5764 09:24:55.790614 DQM Delay:
5765 09:24:55.790704 DQM0 = 103, DQM1 = 99
5766 09:24:55.793796 DQ Delay:
5767 09:24:55.797310 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5768 09:24:55.800138 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5769 09:24:55.803561 DQ8 =88, DQ9 =92, DQ10 =98, DQ11 =94
5770 09:24:55.806801 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =108
5771 09:24:55.806888
5772 09:24:55.806959
5773 09:24:55.813618 [DQSOSCAuto] RK0, (LSB)MR18= 0x1930, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5774 09:24:55.816945 CH1 RK0: MR19=505, MR18=1930
5775 09:24:55.823424 CH1_RK0: MR19=0x505, MR18=0x1930, DQSOSC=406, MR23=63, INC=65, DEC=43
5776 09:24:55.823534
5777 09:24:55.827088 ----->DramcWriteLeveling(PI) begin...
5778 09:24:55.827171 ==
5779 09:24:55.830629 Dram Type= 6, Freq= 0, CH_1, rank 1
5780 09:24:55.833351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 09:24:55.833459 ==
5782 09:24:55.836816 Write leveling (Byte 0): 29 => 29
5783 09:24:55.840581 Write leveling (Byte 1): 28 => 28
5784 09:24:55.843254 DramcWriteLeveling(PI) end<-----
5785 09:24:55.843336
5786 09:24:55.843395 ==
5787 09:24:55.846765 Dram Type= 6, Freq= 0, CH_1, rank 1
5788 09:24:55.853274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 09:24:55.853410 ==
5790 09:24:55.853501 [Gating] SW mode calibration
5791 09:24:55.863210 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5792 09:24:55.866865 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5793 09:24:55.869714 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 09:24:55.877070 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 09:24:55.880508 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 09:24:55.883399 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 09:24:55.890427 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 09:24:55.893223 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 09:24:55.896600 0 14 24 | B1->B0 | 2e2e 3131 | 0 0 | (0 1) (0 1)
5800 09:24:55.903674 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
5801 09:24:55.907047 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 09:24:55.909855 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 09:24:55.916776 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 09:24:55.920133 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 09:24:55.923470 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 09:24:55.929687 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 09:24:55.933009 0 15 24 | B1->B0 | 4141 2525 | 0 0 | (0 0) (0 0)
5808 09:24:55.936352 0 15 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
5809 09:24:55.943229 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 09:24:55.946962 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 09:24:55.949676 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 09:24:55.956752 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 09:24:55.959688 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 09:24:55.963236 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 09:24:55.966754 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5816 09:24:55.973155 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 09:24:55.976726 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 09:24:55.980396 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 09:24:55.986792 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 09:24:55.989700 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 09:24:55.993269 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 09:24:56.000275 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 09:24:56.003701 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 09:24:56.006455 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 09:24:56.013463 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 09:24:56.016698 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 09:24:56.020061 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 09:24:56.026961 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 09:24:56.029592 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 09:24:56.033114 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 09:24:56.039498 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5832 09:24:56.043297 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 09:24:56.046421 Total UI for P1: 0, mck2ui 16
5834 09:24:56.049624 best dqsien dly found for B0: ( 1, 2, 24)
5835 09:24:56.053214 Total UI for P1: 0, mck2ui 16
5836 09:24:56.056205 best dqsien dly found for B1: ( 1, 2, 24)
5837 09:24:56.060211 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5838 09:24:56.063024 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5839 09:24:56.063116
5840 09:24:56.066659 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5841 09:24:56.069608 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5842 09:24:56.073267 [Gating] SW calibration Done
5843 09:24:56.073364 ==
5844 09:24:56.076175 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 09:24:56.079696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 09:24:56.079799 ==
5847 09:24:56.083306 RX Vref Scan: 0
5848 09:24:56.083414
5849 09:24:56.086150 RX Vref 0 -> 0, step: 1
5850 09:24:56.086236
5851 09:24:56.086305 RX Delay -80 -> 252, step: 8
5852 09:24:56.093434 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5853 09:24:56.096266 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5854 09:24:56.099957 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5855 09:24:56.102819 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5856 09:24:56.106578 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5857 09:24:56.110030 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5858 09:24:56.116403 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5859 09:24:56.119829 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5860 09:24:56.123154 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5861 09:24:56.126457 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5862 09:24:56.129964 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5863 09:24:56.132715 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5864 09:24:56.139628 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5865 09:24:56.143040 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5866 09:24:56.146418 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5867 09:24:56.149875 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5868 09:24:56.149994 ==
5869 09:24:56.152732 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 09:24:56.159750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 09:24:56.159886 ==
5872 09:24:56.159995 DQS Delay:
5873 09:24:56.162471 DQS0 = 0, DQS1 = 0
5874 09:24:56.162568 DQM Delay:
5875 09:24:56.162629 DQM0 = 102, DQM1 = 99
5876 09:24:56.166421 DQ Delay:
5877 09:24:56.169490 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5878 09:24:56.172400 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5879 09:24:56.175837 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5880 09:24:56.179105 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5881 09:24:56.179217
5882 09:24:56.179307
5883 09:24:56.179390 ==
5884 09:24:56.182981 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 09:24:56.186081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 09:24:56.186177 ==
5887 09:24:56.186261
5888 09:24:56.186341
5889 09:24:56.189566 TX Vref Scan disable
5890 09:24:56.192359 == TX Byte 0 ==
5891 09:24:56.196029 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5892 09:24:56.199502 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5893 09:24:56.202361 == TX Byte 1 ==
5894 09:24:56.206044 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5895 09:24:56.208956 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5896 09:24:56.209032 ==
5897 09:24:56.212492 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 09:24:56.219018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 09:24:56.219106 ==
5900 09:24:56.219180
5901 09:24:56.219235
5902 09:24:56.219288 TX Vref Scan disable
5903 09:24:56.222677 == TX Byte 0 ==
5904 09:24:56.226039 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5905 09:24:56.232724 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5906 09:24:56.232842 == TX Byte 1 ==
5907 09:24:56.236305 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5908 09:24:56.242786 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5909 09:24:56.242919
5910 09:24:56.243010 [DATLAT]
5911 09:24:56.243094 Freq=933, CH1 RK1
5912 09:24:56.243183
5913 09:24:56.246463 DATLAT Default: 0xb
5914 09:24:56.246545 0, 0xFFFF, sum = 0
5915 09:24:56.249355 1, 0xFFFF, sum = 0
5916 09:24:56.249450 2, 0xFFFF, sum = 0
5917 09:24:56.252873 3, 0xFFFF, sum = 0
5918 09:24:56.252959 4, 0xFFFF, sum = 0
5919 09:24:56.256264 5, 0xFFFF, sum = 0
5920 09:24:56.259393 6, 0xFFFF, sum = 0
5921 09:24:56.259477 7, 0xFFFF, sum = 0
5922 09:24:56.262682 8, 0xFFFF, sum = 0
5923 09:24:56.262767 9, 0xFFFF, sum = 0
5924 09:24:56.265961 10, 0x0, sum = 1
5925 09:24:56.266077 11, 0x0, sum = 2
5926 09:24:56.266171 12, 0x0, sum = 3
5927 09:24:56.269490 13, 0x0, sum = 4
5928 09:24:56.269583 best_step = 11
5929 09:24:56.269646
5930 09:24:56.273033 ==
5931 09:24:56.275805 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 09:24:56.279243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 09:24:56.279331 ==
5934 09:24:56.279393 RX Vref Scan: 0
5935 09:24:56.279450
5936 09:24:56.282679 RX Vref 0 -> 0, step: 1
5937 09:24:56.282761
5938 09:24:56.286056 RX Delay -45 -> 252, step: 4
5939 09:24:56.289321 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5940 09:24:56.295840 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5941 09:24:56.299070 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5942 09:24:56.302270 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5943 09:24:56.305640 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5944 09:24:56.309272 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5945 09:24:56.315632 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5946 09:24:56.319231 iDelay=203, Bit 7, Center 102 (15 ~ 190) 176
5947 09:24:56.322724 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5948 09:24:56.325607 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5949 09:24:56.329102 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5950 09:24:56.332630 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5951 09:24:56.338969 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5952 09:24:56.342524 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5953 09:24:56.345351 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5954 09:24:56.348795 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5955 09:24:56.348888 ==
5956 09:24:56.352249 Dram Type= 6, Freq= 0, CH_1, rank 1
5957 09:24:56.358715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 09:24:56.358835 ==
5959 09:24:56.358900 DQS Delay:
5960 09:24:56.362382 DQS0 = 0, DQS1 = 0
5961 09:24:56.362497 DQM Delay:
5962 09:24:56.362586 DQM0 = 103, DQM1 = 99
5963 09:24:56.365874 DQ Delay:
5964 09:24:56.368812 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =98
5965 09:24:56.372237 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =102
5966 09:24:56.375711 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5967 09:24:56.378987 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5968 09:24:56.379079
5969 09:24:56.379175
5970 09:24:56.385605 [DQSOSCAuto] RK1, (LSB)MR18= 0x3103, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
5971 09:24:56.388406 CH1 RK1: MR19=505, MR18=3103
5972 09:24:56.395194 CH1_RK1: MR19=0x505, MR18=0x3103, DQSOSC=406, MR23=63, INC=65, DEC=43
5973 09:24:56.398825 [RxdqsGatingPostProcess] freq 933
5974 09:24:56.405212 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5975 09:24:56.408600 best DQS0 dly(2T, 0.5T) = (0, 10)
5976 09:24:56.408765 best DQS1 dly(2T, 0.5T) = (0, 10)
5977 09:24:56.411982 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5978 09:24:56.415130 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5979 09:24:56.418397 best DQS0 dly(2T, 0.5T) = (0, 10)
5980 09:24:56.421754 best DQS1 dly(2T, 0.5T) = (0, 10)
5981 09:24:56.425440 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5982 09:24:56.428349 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5983 09:24:56.431980 Pre-setting of DQS Precalculation
5984 09:24:56.438184 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5985 09:24:56.445215 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5986 09:24:56.451728 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5987 09:24:56.451898
5988 09:24:56.452027
5989 09:24:56.455260 [Calibration Summary] 1866 Mbps
5990 09:24:56.455402 CH 0, Rank 0
5991 09:24:56.458107 SW Impedance : PASS
5992 09:24:56.461776 DUTY Scan : NO K
5993 09:24:56.461929 ZQ Calibration : PASS
5994 09:24:56.465115 Jitter Meter : NO K
5995 09:24:56.468783 CBT Training : PASS
5996 09:24:56.468954 Write leveling : PASS
5997 09:24:56.471631 RX DQS gating : PASS
5998 09:24:56.475211 RX DQ/DQS(RDDQC) : PASS
5999 09:24:56.475381 TX DQ/DQS : PASS
6000 09:24:56.478185 RX DATLAT : PASS
6001 09:24:56.478314 RX DQ/DQS(Engine): PASS
6002 09:24:56.481680 TX OE : NO K
6003 09:24:56.481836 All Pass.
6004 09:24:56.481954
6005 09:24:56.485163 CH 0, Rank 1
6006 09:24:56.485313 SW Impedance : PASS
6007 09:24:56.488581 DUTY Scan : NO K
6008 09:24:56.491957 ZQ Calibration : PASS
6009 09:24:56.492140 Jitter Meter : NO K
6010 09:24:56.495819 CBT Training : PASS
6011 09:24:56.498441 Write leveling : PASS
6012 09:24:56.498603 RX DQS gating : PASS
6013 09:24:56.502070 RX DQ/DQS(RDDQC) : PASS
6014 09:24:56.505173 TX DQ/DQS : PASS
6015 09:24:56.505314 RX DATLAT : PASS
6016 09:24:56.508536 RX DQ/DQS(Engine): PASS
6017 09:24:56.511489 TX OE : NO K
6018 09:24:56.511645 All Pass.
6019 09:24:56.511770
6020 09:24:56.511881 CH 1, Rank 0
6021 09:24:56.515184 SW Impedance : PASS
6022 09:24:56.518196 DUTY Scan : NO K
6023 09:24:56.518373 ZQ Calibration : PASS
6024 09:24:56.521646 Jitter Meter : NO K
6025 09:24:56.525096 CBT Training : PASS
6026 09:24:56.525268 Write leveling : PASS
6027 09:24:56.528348 RX DQS gating : PASS
6028 09:24:56.531523 RX DQ/DQS(RDDQC) : PASS
6029 09:24:56.531664 TX DQ/DQS : PASS
6030 09:24:56.534646 RX DATLAT : PASS
6031 09:24:56.534789 RX DQ/DQS(Engine): PASS
6032 09:24:56.537808 TX OE : NO K
6033 09:24:56.537951 All Pass.
6034 09:24:56.538073
6035 09:24:56.541780 CH 1, Rank 1
6036 09:24:56.541929 SW Impedance : PASS
6037 09:24:56.544542 DUTY Scan : NO K
6038 09:24:56.547983 ZQ Calibration : PASS
6039 09:24:56.548141 Jitter Meter : NO K
6040 09:24:56.551637 CBT Training : PASS
6041 09:24:56.554692 Write leveling : PASS
6042 09:24:56.554832 RX DQS gating : PASS
6043 09:24:56.558186 RX DQ/DQS(RDDQC) : PASS
6044 09:24:56.561712 TX DQ/DQS : PASS
6045 09:24:56.561868 RX DATLAT : PASS
6046 09:24:56.564602 RX DQ/DQS(Engine): PASS
6047 09:24:56.568030 TX OE : NO K
6048 09:24:56.568183 All Pass.
6049 09:24:56.568308
6050 09:24:56.568426 DramC Write-DBI off
6051 09:24:56.571586 PER_BANK_REFRESH: Hybrid Mode
6052 09:24:56.575154 TX_TRACKING: ON
6053 09:24:56.581606 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6054 09:24:56.584533 [FAST_K] Save calibration result to emmc
6055 09:24:56.591563 dramc_set_vcore_voltage set vcore to 650000
6056 09:24:56.591759 Read voltage for 400, 6
6057 09:24:56.595122 Vio18 = 0
6058 09:24:56.595292 Vcore = 650000
6059 09:24:56.595418 Vdram = 0
6060 09:24:56.595535 Vddq = 0
6061 09:24:56.597980 Vmddr = 0
6062 09:24:56.601602 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6063 09:24:56.607663 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6064 09:24:56.611572 MEM_TYPE=3, freq_sel=20
6065 09:24:56.611756 sv_algorithm_assistance_LP4_800
6066 09:24:56.617925 ============ PULL DRAM RESETB DOWN ============
6067 09:24:56.621128 ========== PULL DRAM RESETB DOWN end =========
6068 09:24:56.624698 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6069 09:24:56.628264 ===================================
6070 09:24:56.631112 LPDDR4 DRAM CONFIGURATION
6071 09:24:56.634679 ===================================
6072 09:24:56.638248 EX_ROW_EN[0] = 0x0
6073 09:24:56.638366 EX_ROW_EN[1] = 0x0
6074 09:24:56.641693 LP4Y_EN = 0x0
6075 09:24:56.641794 WORK_FSP = 0x0
6076 09:24:56.644813 WL = 0x2
6077 09:24:56.644941 RL = 0x2
6078 09:24:56.647956 BL = 0x2
6079 09:24:56.648079 RPST = 0x0
6080 09:24:56.651401 RD_PRE = 0x0
6081 09:24:56.651533 WR_PRE = 0x1
6082 09:24:56.654966 WR_PST = 0x0
6083 09:24:56.655103 DBI_WR = 0x0
6084 09:24:56.658221 DBI_RD = 0x0
6085 09:24:56.658349 OTF = 0x1
6086 09:24:56.661702 ===================================
6087 09:24:56.664613 ===================================
6088 09:24:56.668271 ANA top config
6089 09:24:56.671755 ===================================
6090 09:24:56.671907 DLL_ASYNC_EN = 0
6091 09:24:56.674568 ALL_SLAVE_EN = 1
6092 09:24:56.678085 NEW_RANK_MODE = 1
6093 09:24:56.681588 DLL_IDLE_MODE = 1
6094 09:24:56.684436 LP45_APHY_COMB_EN = 1
6095 09:24:56.684574 TX_ODT_DIS = 1
6096 09:24:56.688055 NEW_8X_MODE = 1
6097 09:24:56.691665 ===================================
6098 09:24:56.694578 ===================================
6099 09:24:56.697907 data_rate = 800
6100 09:24:56.701393 CKR = 1
6101 09:24:56.704331 DQ_P2S_RATIO = 4
6102 09:24:56.707726 ===================================
6103 09:24:56.711196 CA_P2S_RATIO = 4
6104 09:24:56.711348 DQ_CA_OPEN = 0
6105 09:24:56.714977 DQ_SEMI_OPEN = 1
6106 09:24:56.717748 CA_SEMI_OPEN = 1
6107 09:24:56.721158 CA_FULL_RATE = 0
6108 09:24:56.724424 DQ_CKDIV4_EN = 0
6109 09:24:56.727616 CA_CKDIV4_EN = 1
6110 09:24:56.727740 CA_PREDIV_EN = 0
6111 09:24:56.730849 PH8_DLY = 0
6112 09:24:56.734245 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6113 09:24:56.737764 DQ_AAMCK_DIV = 0
6114 09:24:56.741129 CA_AAMCK_DIV = 0
6115 09:24:56.741253 CA_ADMCK_DIV = 4
6116 09:24:56.744483 DQ_TRACK_CA_EN = 0
6117 09:24:56.748169 CA_PICK = 800
6118 09:24:56.751109 CA_MCKIO = 400
6119 09:24:56.754764 MCKIO_SEMI = 400
6120 09:24:56.757637 PLL_FREQ = 3016
6121 09:24:56.761020 DQ_UI_PI_RATIO = 32
6122 09:24:56.764331 CA_UI_PI_RATIO = 32
6123 09:24:56.767353 ===================================
6124 09:24:56.770940 ===================================
6125 09:24:56.771091 memory_type:LPDDR4
6126 09:24:56.774384 GP_NUM : 10
6127 09:24:56.777399 SRAM_EN : 1
6128 09:24:56.777562 MD32_EN : 0
6129 09:24:56.780604 ===================================
6130 09:24:56.784427 [ANA_INIT] >>>>>>>>>>>>>>
6131 09:24:56.787850 <<<<<< [CONFIGURE PHASE]: ANA_TX
6132 09:24:56.790669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6133 09:24:56.794172 ===================================
6134 09:24:56.797737 data_rate = 800,PCW = 0X7400
6135 09:24:56.800544 ===================================
6136 09:24:56.804143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6137 09:24:56.807822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6138 09:24:56.820706 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6139 09:24:56.824232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6140 09:24:56.827086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6141 09:24:56.830568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6142 09:24:56.833902 [ANA_INIT] flow start
6143 09:24:56.834087 [ANA_INIT] PLL >>>>>>>>
6144 09:24:56.837088 [ANA_INIT] PLL <<<<<<<<
6145 09:24:56.840294 [ANA_INIT] MIDPI >>>>>>>>
6146 09:24:56.843839 [ANA_INIT] MIDPI <<<<<<<<
6147 09:24:56.844028 [ANA_INIT] DLL >>>>>>>>
6148 09:24:56.847222 [ANA_INIT] flow end
6149 09:24:56.850681 ============ LP4 DIFF to SE enter ============
6150 09:24:56.854203 ============ LP4 DIFF to SE exit ============
6151 09:24:56.856979 [ANA_INIT] <<<<<<<<<<<<<
6152 09:24:56.860473 [Flow] Enable top DCM control >>>>>
6153 09:24:56.864047 [Flow] Enable top DCM control <<<<<
6154 09:24:56.866991 Enable DLL master slave shuffle
6155 09:24:56.873930 ==============================================================
6156 09:24:56.874044 Gating Mode config
6157 09:24:56.880190 ==============================================================
6158 09:24:56.880302 Config description:
6159 09:24:56.890365 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6160 09:24:56.897340 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6161 09:24:56.903518 SELPH_MODE 0: By rank 1: By Phase
6162 09:24:56.907198 ==============================================================
6163 09:24:56.910396 GAT_TRACK_EN = 0
6164 09:24:56.913616 RX_GATING_MODE = 2
6165 09:24:56.916951 RX_GATING_TRACK_MODE = 2
6166 09:24:56.920474 SELPH_MODE = 1
6167 09:24:56.923343 PICG_EARLY_EN = 1
6168 09:24:56.926887 VALID_LAT_VALUE = 1
6169 09:24:56.930407 ==============================================================
6170 09:24:56.933928 Enter into Gating configuration >>>>
6171 09:24:56.936794 Exit from Gating configuration <<<<
6172 09:24:56.940271 Enter into DVFS_PRE_config >>>>>
6173 09:24:56.953536 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6174 09:24:56.956839 Exit from DVFS_PRE_config <<<<<
6175 09:24:56.960298 Enter into PICG configuration >>>>
6176 09:24:56.963732 Exit from PICG configuration <<<<
6177 09:24:56.963895 [RX_INPUT] configuration >>>>>
6178 09:24:56.966513 [RX_INPUT] configuration <<<<<
6179 09:24:56.973563 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6180 09:24:56.976561 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6181 09:24:56.983688 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6182 09:24:56.990102 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6183 09:24:56.996722 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6184 09:24:57.003682 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6185 09:24:57.006526 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6186 09:24:57.009846 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6187 09:24:57.013342 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6188 09:24:57.019964 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6189 09:24:57.023129 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6190 09:24:57.026407 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6191 09:24:57.030177 ===================================
6192 09:24:57.033589 LPDDR4 DRAM CONFIGURATION
6193 09:24:57.036509 ===================================
6194 09:24:57.040218 EX_ROW_EN[0] = 0x0
6195 09:24:57.040379 EX_ROW_EN[1] = 0x0
6196 09:24:57.043153 LP4Y_EN = 0x0
6197 09:24:57.043286 WORK_FSP = 0x0
6198 09:24:57.046693 WL = 0x2
6199 09:24:57.046830 RL = 0x2
6200 09:24:57.050148 BL = 0x2
6201 09:24:57.050312 RPST = 0x0
6202 09:24:57.052889 RD_PRE = 0x0
6203 09:24:57.053028 WR_PRE = 0x1
6204 09:24:57.056417 WR_PST = 0x0
6205 09:24:57.056560 DBI_WR = 0x0
6206 09:24:57.059945 DBI_RD = 0x0
6207 09:24:57.060083 OTF = 0x1
6208 09:24:57.063365 ===================================
6209 09:24:57.069995 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6210 09:24:57.073470 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6211 09:24:57.076248 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6212 09:24:57.079790 ===================================
6213 09:24:57.083207 LPDDR4 DRAM CONFIGURATION
6214 09:24:57.086752 ===================================
6215 09:24:57.089637 EX_ROW_EN[0] = 0x10
6216 09:24:57.089746 EX_ROW_EN[1] = 0x0
6217 09:24:57.093147 LP4Y_EN = 0x0
6218 09:24:57.093224 WORK_FSP = 0x0
6219 09:24:57.096753 WL = 0x2
6220 09:24:57.096831 RL = 0x2
6221 09:24:57.099588 BL = 0x2
6222 09:24:57.099701 RPST = 0x0
6223 09:24:57.103067 RD_PRE = 0x0
6224 09:24:57.103186 WR_PRE = 0x1
6225 09:24:57.106196 WR_PST = 0x0
6226 09:24:57.106317 DBI_WR = 0x0
6227 09:24:57.109555 DBI_RD = 0x0
6228 09:24:57.109681 OTF = 0x1
6229 09:24:57.113073 ===================================
6230 09:24:57.119522 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6231 09:24:57.123828 nWR fixed to 30
6232 09:24:57.127334 [ModeRegInit_LP4] CH0 RK0
6233 09:24:57.127463 [ModeRegInit_LP4] CH0 RK1
6234 09:24:57.130879 [ModeRegInit_LP4] CH1 RK0
6235 09:24:57.134384 [ModeRegInit_LP4] CH1 RK1
6236 09:24:57.134509 match AC timing 19
6237 09:24:57.140813 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6238 09:24:57.144073 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6239 09:24:57.147487 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6240 09:24:57.154104 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6241 09:24:57.157499 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6242 09:24:57.157655 ==
6243 09:24:57.161005 Dram Type= 6, Freq= 0, CH_0, rank 0
6244 09:24:57.163793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 09:24:57.163930 ==
6246 09:24:57.170906 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6247 09:24:57.177190 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6248 09:24:57.180722 [CA 0] Center 36 (8~64) winsize 57
6249 09:24:57.183956 [CA 1] Center 36 (8~64) winsize 57
6250 09:24:57.187335 [CA 2] Center 36 (8~64) winsize 57
6251 09:24:57.187499 [CA 3] Center 36 (8~64) winsize 57
6252 09:24:57.190715 [CA 4] Center 36 (8~64) winsize 57
6253 09:24:57.194296 [CA 5] Center 36 (8~64) winsize 57
6254 09:24:57.194402
6255 09:24:57.197038 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6256 09:24:57.200581
6257 09:24:57.204214 [CATrainingPosCal] consider 1 rank data
6258 09:24:57.207001 u2DelayCellTimex100 = 270/100 ps
6259 09:24:57.210475 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 09:24:57.213700 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 09:24:57.217099 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 09:24:57.220552 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 09:24:57.223975 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 09:24:57.227542 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 09:24:57.227669
6266 09:24:57.230415 CA PerBit enable=1, Macro0, CA PI delay=36
6267 09:24:57.230492
6268 09:24:57.234019 [CBTSetCACLKResult] CA Dly = 36
6269 09:24:57.237489 CS Dly: 1 (0~32)
6270 09:24:57.237587 ==
6271 09:24:57.240310 Dram Type= 6, Freq= 0, CH_0, rank 1
6272 09:24:57.243860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 09:24:57.243942 ==
6274 09:24:57.250566 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6275 09:24:57.253952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6276 09:24:57.257162 [CA 0] Center 36 (8~64) winsize 57
6277 09:24:57.260598 [CA 1] Center 36 (8~64) winsize 57
6278 09:24:57.263818 [CA 2] Center 36 (8~64) winsize 57
6279 09:24:57.266736 [CA 3] Center 36 (8~64) winsize 57
6280 09:24:57.270281 [CA 4] Center 36 (8~64) winsize 57
6281 09:24:57.273820 [CA 5] Center 36 (8~64) winsize 57
6282 09:24:57.273887
6283 09:24:57.277234 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6284 09:24:57.277333
6285 09:24:57.280109 [CATrainingPosCal] consider 2 rank data
6286 09:24:57.283648 u2DelayCellTimex100 = 270/100 ps
6287 09:24:57.287134 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 09:24:57.289909 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 09:24:57.296666 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 09:24:57.299957 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 09:24:57.303280 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 09:24:57.306738 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 09:24:57.306838
6294 09:24:57.310332 CA PerBit enable=1, Macro0, CA PI delay=36
6295 09:24:57.310403
6296 09:24:57.313931 [CBTSetCACLKResult] CA Dly = 36
6297 09:24:57.314001 CS Dly: 1 (0~32)
6298 09:24:57.314059
6299 09:24:57.317006 ----->DramcWriteLeveling(PI) begin...
6300 09:24:57.317100 ==
6301 09:24:57.320354 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 09:24:57.326641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 09:24:57.326741 ==
6304 09:24:57.330086 Write leveling (Byte 0): 40 => 8
6305 09:24:57.333594 Write leveling (Byte 1): 40 => 8
6306 09:24:57.333684 DramcWriteLeveling(PI) end<-----
6307 09:24:57.333745
6308 09:24:57.337030 ==
6309 09:24:57.339903 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 09:24:57.343437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 09:24:57.343530 ==
6312 09:24:57.346944 [Gating] SW mode calibration
6313 09:24:57.353727 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6314 09:24:57.356560 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6315 09:24:57.363535 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6316 09:24:57.366633 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6317 09:24:57.369789 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 09:24:57.377072 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6319 09:24:57.379919 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 09:24:57.383333 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 09:24:57.390481 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 09:24:57.393195 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 09:24:57.396736 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 09:24:57.400537 Total UI for P1: 0, mck2ui 16
6325 09:24:57.403428 best dqsien dly found for B0: ( 0, 14, 24)
6326 09:24:57.407005 Total UI for P1: 0, mck2ui 16
6327 09:24:57.409843 best dqsien dly found for B1: ( 0, 14, 24)
6328 09:24:57.413299 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6329 09:24:57.416831 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6330 09:24:57.416963
6331 09:24:57.420168 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6332 09:24:57.426810 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6333 09:24:57.426943 [Gating] SW calibration Done
6334 09:24:57.430184 ==
6335 09:24:57.430308 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 09:24:57.436808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 09:24:57.436926 ==
6338 09:24:57.436988 RX Vref Scan: 0
6339 09:24:57.437050
6340 09:24:57.440241 RX Vref 0 -> 0, step: 1
6341 09:24:57.440328
6342 09:24:57.443087 RX Delay -410 -> 252, step: 16
6343 09:24:57.446709 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6344 09:24:57.450185 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6345 09:24:57.456713 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6346 09:24:57.459538 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6347 09:24:57.463204 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6348 09:24:57.466070 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6349 09:24:57.473343 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6350 09:24:57.476084 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6351 09:24:57.479932 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6352 09:24:57.483079 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6353 09:24:57.489900 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6354 09:24:57.492608 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6355 09:24:57.495976 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6356 09:24:57.503141 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6357 09:24:57.505947 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6358 09:24:57.509398 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6359 09:24:57.509496 ==
6360 09:24:57.512846 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 09:24:57.515745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 09:24:57.515846 ==
6363 09:24:57.519703 DQS Delay:
6364 09:24:57.519805 DQS0 = 27, DQS1 = 35
6365 09:24:57.522583 DQM Delay:
6366 09:24:57.522659 DQM0 = 10, DQM1 = 11
6367 09:24:57.526144 DQ Delay:
6368 09:24:57.526247 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6369 09:24:57.529505 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6370 09:24:57.532793 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6371 09:24:57.536168 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6372 09:24:57.536277
6373 09:24:57.536367
6374 09:24:57.536450 ==
6375 09:24:57.539375 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 09:24:57.545842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 09:24:57.545948 ==
6378 09:24:57.546009
6379 09:24:57.546070
6380 09:24:57.546123 TX Vref Scan disable
6381 09:24:57.549631 == TX Byte 0 ==
6382 09:24:57.552918 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6383 09:24:57.556266 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6384 09:24:57.559089 == TX Byte 1 ==
6385 09:24:57.562535 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 09:24:57.566005 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 09:24:57.566104 ==
6388 09:24:57.573399 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 09:24:57.575968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 09:24:57.576072 ==
6391 09:24:57.576170
6392 09:24:57.576256
6393 09:24:57.576338 TX Vref Scan disable
6394 09:24:57.579493 == TX Byte 0 ==
6395 09:24:57.582384 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6396 09:24:57.585771 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6397 09:24:57.588989 == TX Byte 1 ==
6398 09:24:57.592355 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 09:24:57.595520 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 09:24:57.595632
6401 09:24:57.598911 [DATLAT]
6402 09:24:57.599014 Freq=400, CH0 RK0
6403 09:24:57.599102
6404 09:24:57.602913 DATLAT Default: 0xf
6405 09:24:57.603013 0, 0xFFFF, sum = 0
6406 09:24:57.605505 1, 0xFFFF, sum = 0
6407 09:24:57.605620 2, 0xFFFF, sum = 0
6408 09:24:57.609039 3, 0xFFFF, sum = 0
6409 09:24:57.609143 4, 0xFFFF, sum = 0
6410 09:24:57.612632 5, 0xFFFF, sum = 0
6411 09:24:57.612728 6, 0xFFFF, sum = 0
6412 09:24:57.616071 7, 0xFFFF, sum = 0
6413 09:24:57.616184 8, 0xFFFF, sum = 0
6414 09:24:57.618933 9, 0xFFFF, sum = 0
6415 09:24:57.622503 10, 0xFFFF, sum = 0
6416 09:24:57.622615 11, 0xFFFF, sum = 0
6417 09:24:57.626093 12, 0xFFFF, sum = 0
6418 09:24:57.626201 13, 0x0, sum = 1
6419 09:24:57.628824 14, 0x0, sum = 2
6420 09:24:57.628923 15, 0x0, sum = 3
6421 09:24:57.632471 16, 0x0, sum = 4
6422 09:24:57.632579 best_step = 14
6423 09:24:57.632649
6424 09:24:57.632735 ==
6425 09:24:57.635862 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 09:24:57.639104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 09:24:57.639200 ==
6428 09:24:57.642480 RX Vref Scan: 1
6429 09:24:57.642586
6430 09:24:57.645934 RX Vref 0 -> 0, step: 1
6431 09:24:57.646037
6432 09:24:57.646119 RX Delay -311 -> 252, step: 8
6433 09:24:57.646197
6434 09:24:57.648523 Set Vref, RX VrefLevel [Byte0]: 55
6435 09:24:57.651874 [Byte1]: 54
6436 09:24:57.657184
6437 09:24:57.660336 Final RX Vref Byte 0 = 55 to rank0
6438 09:24:57.660442 Final RX Vref Byte 1 = 54 to rank0
6439 09:24:57.663718 Final RX Vref Byte 0 = 55 to rank1
6440 09:24:57.667105 Final RX Vref Byte 1 = 54 to rank1==
6441 09:24:57.670487 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 09:24:57.677043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 09:24:57.677174 ==
6444 09:24:57.677271 DQS Delay:
6445 09:24:57.680534 DQS0 = 28, DQS1 = 36
6446 09:24:57.680651 DQM Delay:
6447 09:24:57.680723 DQM0 = 11, DQM1 = 13
6448 09:24:57.684140 DQ Delay:
6449 09:24:57.686917 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6450 09:24:57.690453 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6451 09:24:57.690570 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6452 09:24:57.697010 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6453 09:24:57.697144
6454 09:24:57.697237
6455 09:24:57.703706 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1bd, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6456 09:24:57.706948 CH0 RK0: MR19=C0C, MR18=D1BD
6457 09:24:57.713767 CH0_RK0: MR19=0xC0C, MR18=0xD1BD, DQSOSC=384, MR23=63, INC=400, DEC=267
6458 09:24:57.713899 ==
6459 09:24:57.717074 Dram Type= 6, Freq= 0, CH_0, rank 1
6460 09:24:57.720400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 09:24:57.720517 ==
6462 09:24:57.723096 [Gating] SW mode calibration
6463 09:24:57.730099 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6464 09:24:57.737008 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6465 09:24:57.739972 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6466 09:24:57.743346 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6467 09:24:57.749852 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 09:24:57.753790 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6469 09:24:57.756637 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 09:24:57.763452 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 09:24:57.766735 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 09:24:57.770308 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 09:24:57.773594 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 09:24:57.776818 Total UI for P1: 0, mck2ui 16
6475 09:24:57.779969 best dqsien dly found for B0: ( 0, 14, 24)
6476 09:24:57.783683 Total UI for P1: 0, mck2ui 16
6477 09:24:57.786495 best dqsien dly found for B1: ( 0, 14, 24)
6478 09:24:57.790136 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6479 09:24:57.796686 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6480 09:24:57.796808
6481 09:24:57.799567 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6482 09:24:57.803412 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6483 09:24:57.806304 [Gating] SW calibration Done
6484 09:24:57.806462 ==
6485 09:24:57.809757 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 09:24:57.813182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 09:24:57.813352 ==
6488 09:24:57.816530 RX Vref Scan: 0
6489 09:24:57.816688
6490 09:24:57.816806 RX Vref 0 -> 0, step: 1
6491 09:24:57.816917
6492 09:24:57.820231 RX Delay -410 -> 252, step: 16
6493 09:24:57.823570 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6494 09:24:57.829722 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6495 09:24:57.833085 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6496 09:24:57.836416 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6497 09:24:57.839841 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6498 09:24:57.846631 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6499 09:24:57.849479 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6500 09:24:57.853206 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6501 09:24:57.856475 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6502 09:24:57.863248 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6503 09:24:57.866680 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6504 09:24:57.869636 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6505 09:24:57.873361 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6506 09:24:57.879717 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6507 09:24:57.883389 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6508 09:24:57.886760 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6509 09:24:57.886898 ==
6510 09:24:57.890218 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 09:24:57.893057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 09:24:57.896773 ==
6513 09:24:57.896912 DQS Delay:
6514 09:24:57.897007 DQS0 = 19, DQS1 = 35
6515 09:24:57.899824 DQM Delay:
6516 09:24:57.899930 DQM0 = 5, DQM1 = 10
6517 09:24:57.903392 DQ Delay:
6518 09:24:57.903520 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6519 09:24:57.906429 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6520 09:24:57.909800 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6521 09:24:57.913495 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6522 09:24:57.913628
6523 09:24:57.913721
6524 09:24:57.913806 ==
6525 09:24:57.916491 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 09:24:57.923149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 09:24:57.923281 ==
6528 09:24:57.923372
6529 09:24:57.923458
6530 09:24:57.923544 TX Vref Scan disable
6531 09:24:57.926576 == TX Byte 0 ==
6532 09:24:57.930125 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6533 09:24:57.932723 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6534 09:24:57.936692 == TX Byte 1 ==
6535 09:24:57.939439 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6536 09:24:57.942869 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6537 09:24:57.946143 ==
6538 09:24:57.946240 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 09:24:57.952932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 09:24:57.953062 ==
6541 09:24:57.953128
6542 09:24:57.953184
6543 09:24:57.956615 TX Vref Scan disable
6544 09:24:57.956729 == TX Byte 0 ==
6545 09:24:57.959380 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6546 09:24:57.966036 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6547 09:24:57.966145 == TX Byte 1 ==
6548 09:24:57.969295 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6549 09:24:57.973059 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6550 09:24:57.973143
6551 09:24:57.976193 [DATLAT]
6552 09:24:57.976276 Freq=400, CH0 RK1
6553 09:24:57.976337
6554 09:24:57.979776 DATLAT Default: 0xe
6555 09:24:57.979868 0, 0xFFFF, sum = 0
6556 09:24:57.982564 1, 0xFFFF, sum = 0
6557 09:24:57.982642 2, 0xFFFF, sum = 0
6558 09:24:57.985988 3, 0xFFFF, sum = 0
6559 09:24:57.986066 4, 0xFFFF, sum = 0
6560 09:24:57.989425 5, 0xFFFF, sum = 0
6561 09:24:57.989530 6, 0xFFFF, sum = 0
6562 09:24:57.992772 7, 0xFFFF, sum = 0
6563 09:24:57.996114 8, 0xFFFF, sum = 0
6564 09:24:57.996230 9, 0xFFFF, sum = 0
6565 09:24:57.999543 10, 0xFFFF, sum = 0
6566 09:24:57.999638 11, 0xFFFF, sum = 0
6567 09:24:58.003054 12, 0xFFFF, sum = 0
6568 09:24:58.003134 13, 0x0, sum = 1
6569 09:24:58.005793 14, 0x0, sum = 2
6570 09:24:58.005865 15, 0x0, sum = 3
6571 09:24:58.009485 16, 0x0, sum = 4
6572 09:24:58.009587 best_step = 14
6573 09:24:58.009679
6574 09:24:58.009763 ==
6575 09:24:58.012886 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 09:24:58.016329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 09:24:58.016427 ==
6578 09:24:58.019224 RX Vref Scan: 0
6579 09:24:58.019303
6580 09:24:58.022687 RX Vref 0 -> 0, step: 1
6581 09:24:58.022765
6582 09:24:58.022824 RX Delay -311 -> 252, step: 8
6583 09:24:58.031142 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6584 09:24:58.034685 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6585 09:24:58.038095 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6586 09:24:58.041425 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6587 09:24:58.047607 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6588 09:24:58.051206 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6589 09:24:58.054578 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6590 09:24:58.057966 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6591 09:24:58.064448 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6592 09:24:58.067997 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6593 09:24:58.071505 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6594 09:24:58.074967 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6595 09:24:58.081001 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6596 09:24:58.084915 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6597 09:24:58.087954 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6598 09:24:58.091227 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6599 09:24:58.094716 ==
6600 09:24:58.098188 Dram Type= 6, Freq= 0, CH_0, rank 1
6601 09:24:58.100938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 09:24:58.101015 ==
6603 09:24:58.101080 DQS Delay:
6604 09:24:58.104281 DQS0 = 24, DQS1 = 32
6605 09:24:58.104353 DQM Delay:
6606 09:24:58.107740 DQM0 = 8, DQM1 = 9
6607 09:24:58.107811 DQ Delay:
6608 09:24:58.111279 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6609 09:24:58.114104 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6610 09:24:58.117627 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6611 09:24:58.121158 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6612 09:24:58.121235
6613 09:24:58.121303
6614 09:24:58.128156 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6615 09:24:58.130997 CH0 RK1: MR19=C0C, MR18=BD5D
6616 09:24:58.137935 CH0_RK1: MR19=0xC0C, MR18=0xBD5D, DQSOSC=386, MR23=63, INC=396, DEC=264
6617 09:24:58.141480 [RxdqsGatingPostProcess] freq 400
6618 09:24:58.144384 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6619 09:24:58.147801 best DQS0 dly(2T, 0.5T) = (0, 10)
6620 09:24:58.151248 best DQS1 dly(2T, 0.5T) = (0, 10)
6621 09:24:58.154761 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6622 09:24:58.157723 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6623 09:24:58.161195 best DQS0 dly(2T, 0.5T) = (0, 10)
6624 09:24:58.164556 best DQS1 dly(2T, 0.5T) = (0, 10)
6625 09:24:58.167252 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6626 09:24:58.171294 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6627 09:24:58.174555 Pre-setting of DQS Precalculation
6628 09:24:58.177841 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6629 09:24:58.177934 ==
6630 09:24:58.181034 Dram Type= 6, Freq= 0, CH_1, rank 0
6631 09:24:58.187305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 09:24:58.187407 ==
6633 09:24:58.190703 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6634 09:24:58.197346 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6635 09:24:58.200593 [CA 0] Center 36 (8~64) winsize 57
6636 09:24:58.204454 [CA 1] Center 36 (8~64) winsize 57
6637 09:24:58.207807 [CA 2] Center 36 (8~64) winsize 57
6638 09:24:58.211050 [CA 3] Center 36 (8~64) winsize 57
6639 09:24:58.214390 [CA 4] Center 36 (8~64) winsize 57
6640 09:24:58.217852 [CA 5] Center 36 (8~64) winsize 57
6641 09:24:58.217977
6642 09:24:58.220504 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6643 09:24:58.220582
6644 09:24:58.223928 [CATrainingPosCal] consider 1 rank data
6645 09:24:58.227493 u2DelayCellTimex100 = 270/100 ps
6646 09:24:58.230987 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 09:24:58.234540 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 09:24:58.237393 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 09:24:58.240918 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 09:24:58.244327 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 09:24:58.247905 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 09:24:58.247976
6653 09:24:58.254108 CA PerBit enable=1, Macro0, CA PI delay=36
6654 09:24:58.254185
6655 09:24:58.257415 [CBTSetCACLKResult] CA Dly = 36
6656 09:24:58.257530 CS Dly: 1 (0~32)
6657 09:24:58.257641 ==
6658 09:24:58.261112 Dram Type= 6, Freq= 0, CH_1, rank 1
6659 09:24:58.263999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 09:24:58.264090 ==
6661 09:24:58.270546 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6662 09:24:58.277679 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6663 09:24:58.280868 [CA 0] Center 36 (8~64) winsize 57
6664 09:24:58.284380 [CA 1] Center 36 (8~64) winsize 57
6665 09:24:58.287713 [CA 2] Center 36 (8~64) winsize 57
6666 09:24:58.290367 [CA 3] Center 36 (8~64) winsize 57
6667 09:24:58.290436 [CA 4] Center 36 (8~64) winsize 57
6668 09:24:58.293764 [CA 5] Center 36 (8~64) winsize 57
6669 09:24:58.293842
6670 09:24:58.300532 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6671 09:24:58.300639
6672 09:24:58.304053 [CATrainingPosCal] consider 2 rank data
6673 09:24:58.307484 u2DelayCellTimex100 = 270/100 ps
6674 09:24:58.310819 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 09:24:58.314344 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 09:24:58.317069 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 09:24:58.320329 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 09:24:58.323760 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 09:24:58.327125 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 09:24:58.327200
6681 09:24:58.330225 CA PerBit enable=1, Macro0, CA PI delay=36
6682 09:24:58.330299
6683 09:24:58.334099 [CBTSetCACLKResult] CA Dly = 36
6684 09:24:58.337618 CS Dly: 1 (0~32)
6685 09:24:58.337694
6686 09:24:58.340477 ----->DramcWriteLeveling(PI) begin...
6687 09:24:58.340544 ==
6688 09:24:58.343964 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 09:24:58.347403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 09:24:58.347509 ==
6691 09:24:58.350929 Write leveling (Byte 0): 40 => 8
6692 09:24:58.353711 Write leveling (Byte 1): 40 => 8
6693 09:24:58.357304 DramcWriteLeveling(PI) end<-----
6694 09:24:58.357402
6695 09:24:58.357486 ==
6696 09:24:58.360799 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 09:24:58.364319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 09:24:58.364419 ==
6699 09:24:58.367124 [Gating] SW mode calibration
6700 09:24:58.374205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6701 09:24:58.380600 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6702 09:24:58.384324 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6703 09:24:58.387092 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6704 09:24:58.394160 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 09:24:58.396991 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6706 09:24:58.400391 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 09:24:58.407317 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 09:24:58.410464 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 09:24:58.413845 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 09:24:58.420490 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 09:24:58.420615 Total UI for P1: 0, mck2ui 16
6712 09:24:58.426786 best dqsien dly found for B0: ( 0, 14, 24)
6713 09:24:58.426885 Total UI for P1: 0, mck2ui 16
6714 09:24:58.430202 best dqsien dly found for B1: ( 0, 14, 24)
6715 09:24:58.437138 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6716 09:24:58.440408 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6717 09:24:58.440483
6718 09:24:58.444112 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6719 09:24:58.446762 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6720 09:24:58.450087 [Gating] SW calibration Done
6721 09:24:58.450166 ==
6722 09:24:58.453598 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 09:24:58.457052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 09:24:58.457130 ==
6725 09:24:58.460556 RX Vref Scan: 0
6726 09:24:58.460624
6727 09:24:58.460681 RX Vref 0 -> 0, step: 1
6728 09:24:58.460735
6729 09:24:58.463490 RX Delay -410 -> 252, step: 16
6730 09:24:58.466815 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6731 09:24:58.474019 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6732 09:24:58.477454 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6733 09:24:58.480401 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6734 09:24:58.483820 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6735 09:24:58.490202 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6736 09:24:58.493732 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6737 09:24:58.497249 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6738 09:24:58.499961 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6739 09:24:58.507015 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6740 09:24:58.510313 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6741 09:24:58.513726 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6742 09:24:58.517050 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6743 09:24:58.523579 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6744 09:24:58.526907 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6745 09:24:58.530136 iDelay=230, Bit 15, Center -11 (-234 ~ 213) 448
6746 09:24:58.530204 ==
6747 09:24:58.533260 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 09:24:58.539910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 09:24:58.540017 ==
6750 09:24:58.540106 DQS Delay:
6751 09:24:58.543335 DQS0 = 35, DQS1 = 35
6752 09:24:58.543405 DQM Delay:
6753 09:24:58.543461 DQM0 = 18, DQM1 = 14
6754 09:24:58.546846 DQ Delay:
6755 09:24:58.550258 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6756 09:24:58.553427 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6757 09:24:58.556626 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6758 09:24:58.559756 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6759 09:24:58.559852
6760 09:24:58.559934
6761 09:24:58.560013 ==
6762 09:24:58.563371 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 09:24:58.566591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 09:24:58.566724 ==
6765 09:24:58.566820
6766 09:24:58.566907
6767 09:24:58.569929 TX Vref Scan disable
6768 09:24:58.570015 == TX Byte 0 ==
6769 09:24:58.576302 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6770 09:24:58.579671 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6771 09:24:58.579759 == TX Byte 1 ==
6772 09:24:58.586642 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 09:24:58.589414 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 09:24:58.589583 ==
6775 09:24:58.593065 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 09:24:58.595991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 09:24:58.596144 ==
6778 09:24:58.596250
6779 09:24:58.596340
6780 09:24:58.599681 TX Vref Scan disable
6781 09:24:58.599803 == TX Byte 0 ==
6782 09:24:58.606311 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6783 09:24:58.609906 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6784 09:24:58.610006 == TX Byte 1 ==
6785 09:24:58.616311 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 09:24:58.619840 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 09:24:58.619936
6788 09:24:58.620022 [DATLAT]
6789 09:24:58.622539 Freq=400, CH1 RK0
6790 09:24:58.622630
6791 09:24:58.622711 DATLAT Default: 0xf
6792 09:24:58.626106 0, 0xFFFF, sum = 0
6793 09:24:58.626173 1, 0xFFFF, sum = 0
6794 09:24:58.629435 2, 0xFFFF, sum = 0
6795 09:24:58.629522 3, 0xFFFF, sum = 0
6796 09:24:58.633076 4, 0xFFFF, sum = 0
6797 09:24:58.633166 5, 0xFFFF, sum = 0
6798 09:24:58.635818 6, 0xFFFF, sum = 0
6799 09:24:58.635907 7, 0xFFFF, sum = 0
6800 09:24:58.639413 8, 0xFFFF, sum = 0
6801 09:24:58.642861 9, 0xFFFF, sum = 0
6802 09:24:58.642927 10, 0xFFFF, sum = 0
6803 09:24:58.646091 11, 0xFFFF, sum = 0
6804 09:24:58.646190 12, 0xFFFF, sum = 0
6805 09:24:58.649331 13, 0x0, sum = 1
6806 09:24:58.649458 14, 0x0, sum = 2
6807 09:24:58.652458 15, 0x0, sum = 3
6808 09:24:58.652558 16, 0x0, sum = 4
6809 09:24:58.652644 best_step = 14
6810 09:24:58.652725
6811 09:24:58.655876 ==
6812 09:24:58.659464 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 09:24:58.663069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 09:24:58.663165 ==
6815 09:24:58.663249 RX Vref Scan: 1
6816 09:24:58.663333
6817 09:24:58.665858 RX Vref 0 -> 0, step: 1
6818 09:24:58.665926
6819 09:24:58.669303 RX Delay -311 -> 252, step: 8
6820 09:24:58.669394
6821 09:24:58.672700 Set Vref, RX VrefLevel [Byte0]: 53
6822 09:24:58.675951 [Byte1]: 50
6823 09:24:58.679327
6824 09:24:58.679418 Final RX Vref Byte 0 = 53 to rank0
6825 09:24:58.682595 Final RX Vref Byte 1 = 50 to rank0
6826 09:24:58.685656 Final RX Vref Byte 0 = 53 to rank1
6827 09:24:58.688991 Final RX Vref Byte 1 = 50 to rank1==
6828 09:24:58.692686 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 09:24:58.699242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 09:24:58.699364 ==
6831 09:24:58.699455 DQS Delay:
6832 09:24:58.702941 DQS0 = 28, DQS1 = 32
6833 09:24:58.703037 DQM Delay:
6834 09:24:58.703124 DQM0 = 10, DQM1 = 11
6835 09:24:58.705841 DQ Delay:
6836 09:24:58.709342 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6837 09:24:58.709439 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6838 09:24:58.712201 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6839 09:24:58.715720 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6840 09:24:58.715796
6841 09:24:58.719333
6842 09:24:58.725870 [DQSOSCAuto] RK0, (LSB)MR18= 0x97cf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 390 ps
6843 09:24:58.729345 CH1 RK0: MR19=C0C, MR18=97CF
6844 09:24:58.735490 CH1_RK0: MR19=0xC0C, MR18=0x97CF, DQSOSC=384, MR23=63, INC=400, DEC=267
6845 09:24:58.735584 ==
6846 09:24:58.738982 Dram Type= 6, Freq= 0, CH_1, rank 1
6847 09:24:58.742652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 09:24:58.742752 ==
6849 09:24:58.745490 [Gating] SW mode calibration
6850 09:24:58.752596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6851 09:24:58.758816 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6852 09:24:58.761964 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6853 09:24:58.765279 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6854 09:24:58.772251 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 09:24:58.775905 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6856 09:24:58.778703 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 09:24:58.782252 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 09:24:58.788613 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 09:24:58.792044 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 09:24:58.795499 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 09:24:58.798941 Total UI for P1: 0, mck2ui 16
6862 09:24:58.801704 best dqsien dly found for B0: ( 0, 14, 24)
6863 09:24:58.805049 Total UI for P1: 0, mck2ui 16
6864 09:24:58.808364 best dqsien dly found for B1: ( 0, 14, 24)
6865 09:24:58.812097 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6866 09:24:58.818696 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6867 09:24:58.818797
6868 09:24:58.821635 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6869 09:24:58.825126 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6870 09:24:58.828669 [Gating] SW calibration Done
6871 09:24:58.828760 ==
6872 09:24:58.831528 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 09:24:58.834974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 09:24:58.835065 ==
6875 09:24:58.838399 RX Vref Scan: 0
6876 09:24:58.838474
6877 09:24:58.838543 RX Vref 0 -> 0, step: 1
6878 09:24:58.838614
6879 09:24:58.841862 RX Delay -410 -> 252, step: 16
6880 09:24:58.845479 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6881 09:24:58.851864 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6882 09:24:58.854776 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6883 09:24:58.858323 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6884 09:24:58.862050 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6885 09:24:58.868439 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6886 09:24:58.871775 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6887 09:24:58.875362 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6888 09:24:58.878076 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6889 09:24:58.884643 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6890 09:24:58.888286 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6891 09:24:58.891139 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6892 09:24:58.894809 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6893 09:24:58.901352 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6894 09:24:58.904815 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6895 09:24:58.907744 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6896 09:24:58.907837 ==
6897 09:24:58.911372 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 09:24:58.917798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 09:24:58.917872 ==
6900 09:24:58.917935 DQS Delay:
6901 09:24:58.921150 DQS0 = 35, DQS1 = 35
6902 09:24:58.921240 DQM Delay:
6903 09:24:58.921322 DQM0 = 17, DQM1 = 13
6904 09:24:58.924501 DQ Delay:
6905 09:24:58.927775 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6906 09:24:58.931726 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6907 09:24:58.934859 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6908 09:24:58.937779 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6909 09:24:58.937906
6910 09:24:58.937972
6911 09:24:58.938027 ==
6912 09:24:58.941428 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 09:24:58.944697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 09:24:58.944808 ==
6915 09:24:58.944872
6916 09:24:58.944928
6917 09:24:58.947793 TX Vref Scan disable
6918 09:24:58.947915 == TX Byte 0 ==
6919 09:24:58.954674 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6920 09:24:58.957674 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6921 09:24:58.957770 == TX Byte 1 ==
6922 09:24:58.961253 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6923 09:24:58.967749 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6924 09:24:58.967855 ==
6925 09:24:58.971345 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 09:24:58.974224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 09:24:58.974292 ==
6928 09:24:58.974390
6929 09:24:58.974472
6930 09:24:58.977573 TX Vref Scan disable
6931 09:24:58.977647 == TX Byte 0 ==
6932 09:24:58.984043 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6933 09:24:58.987450 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6934 09:24:58.987523 == TX Byte 1 ==
6935 09:24:58.994134 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6936 09:24:58.997651 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6937 09:24:58.997752
6938 09:24:58.997833 [DATLAT]
6939 09:24:59.001373 Freq=400, CH1 RK1
6940 09:24:59.001451
6941 09:24:59.001511 DATLAT Default: 0xe
6942 09:24:59.004166 0, 0xFFFF, sum = 0
6943 09:24:59.004244 1, 0xFFFF, sum = 0
6944 09:24:59.007767 2, 0xFFFF, sum = 0
6945 09:24:59.007845 3, 0xFFFF, sum = 0
6946 09:24:59.010678 4, 0xFFFF, sum = 0
6947 09:24:59.010759 5, 0xFFFF, sum = 0
6948 09:24:59.014306 6, 0xFFFF, sum = 0
6949 09:24:59.014385 7, 0xFFFF, sum = 0
6950 09:24:59.017827 8, 0xFFFF, sum = 0
6951 09:24:59.017905 9, 0xFFFF, sum = 0
6952 09:24:59.020739 10, 0xFFFF, sum = 0
6953 09:24:59.020817 11, 0xFFFF, sum = 0
6954 09:24:59.024492 12, 0xFFFF, sum = 0
6955 09:24:59.024571 13, 0x0, sum = 1
6956 09:24:59.027231 14, 0x0, sum = 2
6957 09:24:59.027310 15, 0x0, sum = 3
6958 09:24:59.030805 16, 0x0, sum = 4
6959 09:24:59.030877 best_step = 14
6960 09:24:59.030970
6961 09:24:59.031061 ==
6962 09:24:59.034426 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 09:24:59.040805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 09:24:59.040880 ==
6965 09:24:59.040975 RX Vref Scan: 0
6966 09:24:59.041066
6967 09:24:59.044352 RX Vref 0 -> 0, step: 1
6968 09:24:59.044446
6969 09:24:59.047653 RX Delay -311 -> 252, step: 8
6970 09:24:59.054130 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6971 09:24:59.057169 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6972 09:24:59.060304 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6973 09:24:59.063768 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6974 09:24:59.070549 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6975 09:24:59.073973 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6976 09:24:59.077518 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6977 09:24:59.081033 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6978 09:24:59.087557 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6979 09:24:59.090378 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6980 09:24:59.093833 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6981 09:24:59.097247 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6982 09:24:59.103618 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6983 09:24:59.106804 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6984 09:24:59.110331 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6985 09:24:59.113850 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6986 09:24:59.117326 ==
6987 09:24:59.120297 Dram Type= 6, Freq= 0, CH_1, rank 1
6988 09:24:59.123727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6989 09:24:59.123827 ==
6990 09:24:59.123928 DQS Delay:
6991 09:24:59.126781 DQS0 = 28, DQS1 = 36
6992 09:24:59.126851 DQM Delay:
6993 09:24:59.130291 DQM0 = 10, DQM1 = 14
6994 09:24:59.130359 DQ Delay:
6995 09:24:59.133891 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6996 09:24:59.136797 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6997 09:24:59.140359 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6998 09:24:59.143282 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6999 09:24:59.143388
7000 09:24:59.143477
7001 09:24:59.150339 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf60, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 384 ps
7002 09:24:59.153849 CH1 RK1: MR19=C0C, MR18=CF60
7003 09:24:59.160532 CH1_RK1: MR19=0xC0C, MR18=0xCF60, DQSOSC=384, MR23=63, INC=400, DEC=267
7004 09:24:59.163346 [RxdqsGatingPostProcess] freq 400
7005 09:24:59.166964 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7006 09:24:59.170401 best DQS0 dly(2T, 0.5T) = (0, 10)
7007 09:24:59.173495 best DQS1 dly(2T, 0.5T) = (0, 10)
7008 09:24:59.176799 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7009 09:24:59.180520 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7010 09:24:59.183521 best DQS0 dly(2T, 0.5T) = (0, 10)
7011 09:24:59.187180 best DQS1 dly(2T, 0.5T) = (0, 10)
7012 09:24:59.189952 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7013 09:24:59.193706 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7014 09:24:59.196999 Pre-setting of DQS Precalculation
7015 09:24:59.200112 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7016 09:24:59.209996 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7017 09:24:59.216785 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7018 09:24:59.216881
7019 09:24:59.216974
7020 09:24:59.220011 [Calibration Summary] 800 Mbps
7021 09:24:59.220103 CH 0, Rank 0
7022 09:24:59.223180 SW Impedance : PASS
7023 09:24:59.223271 DUTY Scan : NO K
7024 09:24:59.226800 ZQ Calibration : PASS
7025 09:24:59.229783 Jitter Meter : NO K
7026 09:24:59.229850 CBT Training : PASS
7027 09:24:59.233255 Write leveling : PASS
7028 09:24:59.236783 RX DQS gating : PASS
7029 09:24:59.236872 RX DQ/DQS(RDDQC) : PASS
7030 09:24:59.240392 TX DQ/DQS : PASS
7031 09:24:59.243169 RX DATLAT : PASS
7032 09:24:59.243261 RX DQ/DQS(Engine): PASS
7033 09:24:59.246829 TX OE : NO K
7034 09:24:59.246920 All Pass.
7035 09:24:59.247003
7036 09:24:59.249638 CH 0, Rank 1
7037 09:24:59.249728 SW Impedance : PASS
7038 09:24:59.253225 DUTY Scan : NO K
7039 09:24:59.253317 ZQ Calibration : PASS
7040 09:24:59.256736 Jitter Meter : NO K
7041 09:24:59.260148 CBT Training : PASS
7042 09:24:59.260239 Write leveling : NO K
7043 09:24:59.263113 RX DQS gating : PASS
7044 09:24:59.266619 RX DQ/DQS(RDDQC) : PASS
7045 09:24:59.266686 TX DQ/DQS : PASS
7046 09:24:59.269455 RX DATLAT : PASS
7047 09:24:59.273017 RX DQ/DQS(Engine): PASS
7048 09:24:59.273108 TX OE : NO K
7049 09:24:59.276493 All Pass.
7050 09:24:59.276560
7051 09:24:59.276615 CH 1, Rank 0
7052 09:24:59.279375 SW Impedance : PASS
7053 09:24:59.279444 DUTY Scan : NO K
7054 09:24:59.283018 ZQ Calibration : PASS
7055 09:24:59.286599 Jitter Meter : NO K
7056 09:24:59.286693 CBT Training : PASS
7057 09:24:59.289374 Write leveling : PASS
7058 09:24:59.292907 RX DQS gating : PASS
7059 09:24:59.292975 RX DQ/DQS(RDDQC) : PASS
7060 09:24:59.296510 TX DQ/DQS : PASS
7061 09:24:59.299297 RX DATLAT : PASS
7062 09:24:59.299388 RX DQ/DQS(Engine): PASS
7063 09:24:59.302601 TX OE : NO K
7064 09:24:59.302669 All Pass.
7065 09:24:59.302725
7066 09:24:59.306500 CH 1, Rank 1
7067 09:24:59.306592 SW Impedance : PASS
7068 09:24:59.309600 DUTY Scan : NO K
7069 09:24:59.309709 ZQ Calibration : PASS
7070 09:24:59.312644 Jitter Meter : NO K
7071 09:24:59.316330 CBT Training : PASS
7072 09:24:59.316399 Write leveling : NO K
7073 09:24:59.319393 RX DQS gating : PASS
7074 09:24:59.322825 RX DQ/DQS(RDDQC) : PASS
7075 09:24:59.322892 TX DQ/DQS : PASS
7076 09:24:59.325834 RX DATLAT : PASS
7077 09:24:59.329534 RX DQ/DQS(Engine): PASS
7078 09:24:59.329676 TX OE : NO K
7079 09:24:59.332629 All Pass.
7080 09:24:59.332727
7081 09:24:59.332817 DramC Write-DBI off
7082 09:24:59.336261 PER_BANK_REFRESH: Hybrid Mode
7083 09:24:59.336330 TX_TRACKING: ON
7084 09:24:59.346065 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7085 09:24:59.349194 [FAST_K] Save calibration result to emmc
7086 09:24:59.352938 dramc_set_vcore_voltage set vcore to 725000
7087 09:24:59.356200 Read voltage for 1600, 0
7088 09:24:59.356272 Vio18 = 0
7089 09:24:59.359758 Vcore = 725000
7090 09:24:59.359823 Vdram = 0
7091 09:24:59.359878 Vddq = 0
7092 09:24:59.362633 Vmddr = 0
7093 09:24:59.366192 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7094 09:24:59.372660 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7095 09:24:59.372758 MEM_TYPE=3, freq_sel=13
7096 09:24:59.376195 sv_algorithm_assistance_LP4_3733
7097 09:24:59.382684 ============ PULL DRAM RESETB DOWN ============
7098 09:24:59.386330 ========== PULL DRAM RESETB DOWN end =========
7099 09:24:59.389032 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7100 09:24:59.392561 ===================================
7101 09:24:59.396257 LPDDR4 DRAM CONFIGURATION
7102 09:24:59.399268 ===================================
7103 09:24:59.399337 EX_ROW_EN[0] = 0x0
7104 09:24:59.402811 EX_ROW_EN[1] = 0x0
7105 09:24:59.405569 LP4Y_EN = 0x0
7106 09:24:59.405689 WORK_FSP = 0x1
7107 09:24:59.409252 WL = 0x5
7108 09:24:59.409320 RL = 0x5
7109 09:24:59.412774 BL = 0x2
7110 09:24:59.412841 RPST = 0x0
7111 09:24:59.415552 RD_PRE = 0x0
7112 09:24:59.415647 WR_PRE = 0x1
7113 09:24:59.418970 WR_PST = 0x1
7114 09:24:59.419039 DBI_WR = 0x0
7115 09:24:59.422375 DBI_RD = 0x0
7116 09:24:59.422441 OTF = 0x1
7117 09:24:59.425882 ===================================
7118 09:24:59.429419 ===================================
7119 09:24:59.432062 ANA top config
7120 09:24:59.435411 ===================================
7121 09:24:59.435480 DLL_ASYNC_EN = 0
7122 09:24:59.439227 ALL_SLAVE_EN = 0
7123 09:24:59.442677 NEW_RANK_MODE = 1
7124 09:24:59.445421 DLL_IDLE_MODE = 1
7125 09:24:59.448875 LP45_APHY_COMB_EN = 1
7126 09:24:59.448946 TX_ODT_DIS = 0
7127 09:24:59.452080 NEW_8X_MODE = 1
7128 09:24:59.455792 ===================================
7129 09:24:59.459055 ===================================
7130 09:24:59.462328 data_rate = 3200
7131 09:24:59.465415 CKR = 1
7132 09:24:59.469076 DQ_P2S_RATIO = 8
7133 09:24:59.472259 ===================================
7134 09:24:59.472361 CA_P2S_RATIO = 8
7135 09:24:59.475341 DQ_CA_OPEN = 0
7136 09:24:59.478536 DQ_SEMI_OPEN = 0
7137 09:24:59.481846 CA_SEMI_OPEN = 0
7138 09:24:59.485348 CA_FULL_RATE = 0
7139 09:24:59.488317 DQ_CKDIV4_EN = 0
7140 09:24:59.491722 CA_CKDIV4_EN = 0
7141 09:24:59.491814 CA_PREDIV_EN = 0
7142 09:24:59.495328 PH8_DLY = 12
7143 09:24:59.498769 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7144 09:24:59.501651 DQ_AAMCK_DIV = 4
7145 09:24:59.505212 CA_AAMCK_DIV = 4
7146 09:24:59.508627 CA_ADMCK_DIV = 4
7147 09:24:59.508720 DQ_TRACK_CA_EN = 0
7148 09:24:59.512165 CA_PICK = 1600
7149 09:24:59.514993 CA_MCKIO = 1600
7150 09:24:59.518665 MCKIO_SEMI = 0
7151 09:24:59.522093 PLL_FREQ = 3068
7152 09:24:59.524871 DQ_UI_PI_RATIO = 32
7153 09:24:59.528546 CA_UI_PI_RATIO = 0
7154 09:24:59.532172 ===================================
7155 09:24:59.534962 ===================================
7156 09:24:59.535049 memory_type:LPDDR4
7157 09:24:59.538522 GP_NUM : 10
7158 09:24:59.541999 SRAM_EN : 1
7159 09:24:59.542071 MD32_EN : 0
7160 09:24:59.545300 ===================================
7161 09:24:59.548650 [ANA_INIT] >>>>>>>>>>>>>>
7162 09:24:59.551509 <<<<<< [CONFIGURE PHASE]: ANA_TX
7163 09:24:59.555205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7164 09:24:59.557931 ===================================
7165 09:24:59.561304 data_rate = 3200,PCW = 0X7600
7166 09:24:59.564588 ===================================
7167 09:24:59.568108 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7168 09:24:59.571582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7169 09:24:59.578522 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7170 09:24:59.581297 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7171 09:24:59.584627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7172 09:24:59.587930 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7173 09:24:59.591723 [ANA_INIT] flow start
7174 09:24:59.594859 [ANA_INIT] PLL >>>>>>>>
7175 09:24:59.594975 [ANA_INIT] PLL <<<<<<<<
7176 09:24:59.598220 [ANA_INIT] MIDPI >>>>>>>>
7177 09:24:59.601609 [ANA_INIT] MIDPI <<<<<<<<
7178 09:24:59.601681 [ANA_INIT] DLL >>>>>>>>
7179 09:24:59.605126 [ANA_INIT] DLL <<<<<<<<
7180 09:24:59.608012 [ANA_INIT] flow end
7181 09:24:59.611565 ============ LP4 DIFF to SE enter ============
7182 09:24:59.615040 ============ LP4 DIFF to SE exit ============
7183 09:24:59.618537 [ANA_INIT] <<<<<<<<<<<<<
7184 09:24:59.621491 [Flow] Enable top DCM control >>>>>
7185 09:24:59.624953 [Flow] Enable top DCM control <<<<<
7186 09:24:59.628442 Enable DLL master slave shuffle
7187 09:24:59.631368 ==============================================================
7188 09:24:59.634900 Gating Mode config
7189 09:24:59.641564 ==============================================================
7190 09:24:59.641648 Config description:
7191 09:24:59.651047 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7192 09:24:59.658006 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7193 09:24:59.664337 SELPH_MODE 0: By rank 1: By Phase
7194 09:24:59.667338 ==============================================================
7195 09:24:59.670688 GAT_TRACK_EN = 1
7196 09:24:59.674270 RX_GATING_MODE = 2
7197 09:24:59.677191 RX_GATING_TRACK_MODE = 2
7198 09:24:59.680568 SELPH_MODE = 1
7199 09:24:59.683983 PICG_EARLY_EN = 1
7200 09:24:59.687406 VALID_LAT_VALUE = 1
7201 09:24:59.691029 ==============================================================
7202 09:24:59.693887 Enter into Gating configuration >>>>
7203 09:24:59.697375 Exit from Gating configuration <<<<
7204 09:24:59.700772 Enter into DVFS_PRE_config >>>>>
7205 09:24:59.714088 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7206 09:24:59.717299 Exit from DVFS_PRE_config <<<<<
7207 09:24:59.720572 Enter into PICG configuration >>>>
7208 09:24:59.724128 Exit from PICG configuration <<<<
7209 09:24:59.724224 [RX_INPUT] configuration >>>>>
7210 09:24:59.726994 [RX_INPUT] configuration <<<<<
7211 09:24:59.733758 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7212 09:24:59.737332 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7213 09:24:59.743630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7214 09:24:59.750172 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7215 09:24:59.757364 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7216 09:24:59.763862 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7217 09:24:59.767087 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7218 09:24:59.770419 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7219 09:24:59.777138 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7220 09:24:59.780459 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7221 09:24:59.783828 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7222 09:24:59.786569 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7223 09:24:59.790137 ===================================
7224 09:24:59.793515 LPDDR4 DRAM CONFIGURATION
7225 09:24:59.796982 ===================================
7226 09:24:59.800571 EX_ROW_EN[0] = 0x0
7227 09:24:59.800641 EX_ROW_EN[1] = 0x0
7228 09:24:59.803275 LP4Y_EN = 0x0
7229 09:24:59.803366 WORK_FSP = 0x1
7230 09:24:59.806799 WL = 0x5
7231 09:24:59.806890 RL = 0x5
7232 09:24:59.810289 BL = 0x2
7233 09:24:59.810358 RPST = 0x0
7234 09:24:59.813848 RD_PRE = 0x0
7235 09:24:59.813916 WR_PRE = 0x1
7236 09:24:59.817158 WR_PST = 0x1
7237 09:24:59.817248 DBI_WR = 0x0
7238 09:24:59.820636 DBI_RD = 0x0
7239 09:24:59.820728 OTF = 0x1
7240 09:24:59.824092 ===================================
7241 09:24:59.830499 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7242 09:24:59.833741 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7243 09:24:59.836780 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7244 09:24:59.840056 ===================================
7245 09:24:59.843717 LPDDR4 DRAM CONFIGURATION
7246 09:24:59.846854 ===================================
7247 09:24:59.846925 EX_ROW_EN[0] = 0x10
7248 09:24:59.850540 EX_ROW_EN[1] = 0x0
7249 09:24:59.853297 LP4Y_EN = 0x0
7250 09:24:59.853367 WORK_FSP = 0x1
7251 09:24:59.856923 WL = 0x5
7252 09:24:59.856990 RL = 0x5
7253 09:24:59.860431 BL = 0x2
7254 09:24:59.860521 RPST = 0x0
7255 09:24:59.863297 RD_PRE = 0x0
7256 09:24:59.863390 WR_PRE = 0x1
7257 09:24:59.866989 WR_PST = 0x1
7258 09:24:59.867079 DBI_WR = 0x0
7259 09:24:59.870403 DBI_RD = 0x0
7260 09:24:59.870492 OTF = 0x1
7261 09:24:59.873457 ===================================
7262 09:24:59.880457 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7263 09:24:59.880554 ==
7264 09:24:59.883713 Dram Type= 6, Freq= 0, CH_0, rank 0
7265 09:24:59.887044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7266 09:24:59.890337 ==
7267 09:24:59.890409 [Duty_Offset_Calibration]
7268 09:24:59.893771 B0:2 B1:1 CA:1
7269 09:24:59.893863
7270 09:24:59.896961 [DutyScan_Calibration_Flow] k_type=0
7271 09:24:59.905434
7272 09:24:59.905529 ==CLK 0==
7273 09:24:59.908993 Final CLK duty delay cell = 0
7274 09:24:59.912704 [0] MAX Duty = 5156%(X100), DQS PI = 22
7275 09:24:59.915502 [0] MIN Duty = 4907%(X100), DQS PI = 0
7276 09:24:59.915596 [0] AVG Duty = 5031%(X100)
7277 09:24:59.919099
7278 09:24:59.922035 CH0 CLK Duty spec in!! Max-Min= 249%
7279 09:24:59.925505 [DutyScan_Calibration_Flow] ====Done====
7280 09:24:59.925619
7281 09:24:59.929114 [DutyScan_Calibration_Flow] k_type=1
7282 09:24:59.944709
7283 09:24:59.944783 ==DQS 0 ==
7284 09:24:59.948033 Final DQS duty delay cell = -4
7285 09:24:59.951282 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7286 09:24:59.955119 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7287 09:24:59.958163 [-4] AVG Duty = 4891%(X100)
7288 09:24:59.958254
7289 09:24:59.958339 ==DQS 1 ==
7290 09:24:59.961788 Final DQS duty delay cell = 0
7291 09:24:59.964933 [0] MAX Duty = 5187%(X100), DQS PI = 4
7292 09:24:59.968279 [0] MIN Duty = 5031%(X100), DQS PI = 32
7293 09:24:59.971821 [0] AVG Duty = 5109%(X100)
7294 09:24:59.971915
7295 09:24:59.974615 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7296 09:24:59.974682
7297 09:24:59.978123 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7298 09:24:59.981679 [DutyScan_Calibration_Flow] ====Done====
7299 09:24:59.981771
7300 09:24:59.984465 [DutyScan_Calibration_Flow] k_type=3
7301 09:25:00.002169
7302 09:25:00.002242 ==DQM 0 ==
7303 09:25:00.005502 Final DQM duty delay cell = 0
7304 09:25:00.008746 [0] MAX Duty = 5218%(X100), DQS PI = 34
7305 09:25:00.011953 [0] MIN Duty = 4875%(X100), DQS PI = 60
7306 09:25:00.015639 [0] AVG Duty = 5046%(X100)
7307 09:25:00.015734
7308 09:25:00.015819 ==DQM 1 ==
7309 09:25:00.018540 Final DQM duty delay cell = 0
7310 09:25:00.022143 [0] MAX Duty = 5187%(X100), DQS PI = 2
7311 09:25:00.025697 [0] MIN Duty = 5062%(X100), DQS PI = 14
7312 09:25:00.028602 [0] AVG Duty = 5124%(X100)
7313 09:25:00.028690
7314 09:25:00.032224 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7315 09:25:00.032314
7316 09:25:00.035101 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7317 09:25:00.038598 [DutyScan_Calibration_Flow] ====Done====
7318 09:25:00.038667
7319 09:25:00.042033 [DutyScan_Calibration_Flow] k_type=2
7320 09:25:00.059632
7321 09:25:00.059727 ==DQ 0 ==
7322 09:25:00.062439 Final DQ duty delay cell = 0
7323 09:25:00.065745 [0] MAX Duty = 5062%(X100), DQS PI = 24
7324 09:25:00.069732 [0] MIN Duty = 4907%(X100), DQS PI = 0
7325 09:25:00.069799 [0] AVG Duty = 4984%(X100)
7326 09:25:00.069855
7327 09:25:00.072889 ==DQ 1 ==
7328 09:25:00.076096 Final DQ duty delay cell = 0
7329 09:25:00.079138 [0] MAX Duty = 5125%(X100), DQS PI = 6
7330 09:25:00.082972 [0] MIN Duty = 4907%(X100), DQS PI = 34
7331 09:25:00.083042 [0] AVG Duty = 5016%(X100)
7332 09:25:00.083098
7333 09:25:00.085863 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7334 09:25:00.085966
7335 09:25:00.089740 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7336 09:25:00.095853 [DutyScan_Calibration_Flow] ====Done====
7337 09:25:00.095947 ==
7338 09:25:00.099355 Dram Type= 6, Freq= 0, CH_1, rank 0
7339 09:25:00.102623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7340 09:25:00.102713 ==
7341 09:25:00.105926 [Duty_Offset_Calibration]
7342 09:25:00.106015 B0:1 B1:0 CA:0
7343 09:25:00.106095
7344 09:25:00.109413 [DutyScan_Calibration_Flow] k_type=0
7345 09:25:00.118447
7346 09:25:00.118514 ==CLK 0==
7347 09:25:00.121606 Final CLK duty delay cell = -4
7348 09:25:00.125631 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7349 09:25:00.128516 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7350 09:25:00.132101 [-4] AVG Duty = 4906%(X100)
7351 09:25:00.132192
7352 09:25:00.135103 CH1 CLK Duty spec in!! Max-Min= 125%
7353 09:25:00.138573 [DutyScan_Calibration_Flow] ====Done====
7354 09:25:00.138667
7355 09:25:00.142238 [DutyScan_Calibration_Flow] k_type=1
7356 09:25:00.158839
7357 09:25:00.158911 ==DQS 0 ==
7358 09:25:00.161762 Final DQS duty delay cell = 0
7359 09:25:00.165306 [0] MAX Duty = 5062%(X100), DQS PI = 8
7360 09:25:00.168871 [0] MIN Duty = 4844%(X100), DQS PI = 0
7361 09:25:00.168938 [0] AVG Duty = 4953%(X100)
7362 09:25:00.171791
7363 09:25:00.171855 ==DQS 1 ==
7364 09:25:00.175395 Final DQS duty delay cell = 0
7365 09:25:00.178338 [0] MAX Duty = 5249%(X100), DQS PI = 18
7366 09:25:00.181818 [0] MIN Duty = 4938%(X100), DQS PI = 8
7367 09:25:00.181896 [0] AVG Duty = 5093%(X100)
7368 09:25:00.185370
7369 09:25:00.188114 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7370 09:25:00.188186
7371 09:25:00.191537 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7372 09:25:00.194823 [DutyScan_Calibration_Flow] ====Done====
7373 09:25:00.194894
7374 09:25:00.198270 [DutyScan_Calibration_Flow] k_type=3
7375 09:25:00.215317
7376 09:25:00.215396 ==DQM 0 ==
7377 09:25:00.218584 Final DQM duty delay cell = 0
7378 09:25:00.221728 [0] MAX Duty = 5187%(X100), DQS PI = 10
7379 09:25:00.225035 [0] MIN Duty = 4969%(X100), DQS PI = 46
7380 09:25:00.228480 [0] AVG Duty = 5078%(X100)
7381 09:25:00.228552
7382 09:25:00.228606 ==DQM 1 ==
7383 09:25:00.232035 Final DQM duty delay cell = 0
7384 09:25:00.235146 [0] MAX Duty = 5062%(X100), DQS PI = 16
7385 09:25:00.238478 [0] MIN Duty = 4907%(X100), DQS PI = 32
7386 09:25:00.241520 [0] AVG Duty = 4984%(X100)
7387 09:25:00.241633
7388 09:25:00.244910 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7389 09:25:00.244977
7390 09:25:00.248634 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7391 09:25:00.251790 [DutyScan_Calibration_Flow] ====Done====
7392 09:25:00.251861
7393 09:25:00.255434 [DutyScan_Calibration_Flow] k_type=2
7394 09:25:00.271360
7395 09:25:00.271429 ==DQ 0 ==
7396 09:25:00.275055 Final DQ duty delay cell = -4
7397 09:25:00.277962 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7398 09:25:00.281532 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7399 09:25:00.284938 [-4] AVG Duty = 4937%(X100)
7400 09:25:00.285010
7401 09:25:00.285067 ==DQ 1 ==
7402 09:25:00.288430 Final DQ duty delay cell = 0
7403 09:25:00.291411 [0] MAX Duty = 5124%(X100), DQS PI = 16
7404 09:25:00.295011 [0] MIN Duty = 4938%(X100), DQS PI = 10
7405 09:25:00.297749 [0] AVG Duty = 5031%(X100)
7406 09:25:00.297827
7407 09:25:00.301278 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7408 09:25:00.301347
7409 09:25:00.304997 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7410 09:25:00.307766 [DutyScan_Calibration_Flow] ====Done====
7411 09:25:00.311451 nWR fixed to 30
7412 09:25:00.311526 [ModeRegInit_LP4] CH0 RK0
7413 09:25:00.314879 [ModeRegInit_LP4] CH0 RK1
7414 09:25:00.317813 [ModeRegInit_LP4] CH1 RK0
7415 09:25:00.321398 [ModeRegInit_LP4] CH1 RK1
7416 09:25:00.321466 match AC timing 5
7417 09:25:00.327805 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7418 09:25:00.331431 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7419 09:25:00.334359 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7420 09:25:00.341398 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7421 09:25:00.344723 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7422 09:25:00.344792 [MiockJmeterHQA]
7423 09:25:00.344849
7424 09:25:00.348033 [DramcMiockJmeter] u1RxGatingPI = 0
7425 09:25:00.351285 0 : 4253, 4026
7426 09:25:00.351354 4 : 4255, 4029
7427 09:25:00.354776 8 : 4253, 4026
7428 09:25:00.354845 12 : 4253, 4026
7429 09:25:00.354916 16 : 4253, 4027
7430 09:25:00.358006 20 : 4363, 4137
7431 09:25:00.358072 24 : 4252, 4027
7432 09:25:00.360983 28 : 4363, 4137
7433 09:25:00.361047 32 : 4252, 4027
7434 09:25:00.364807 36 : 4252, 4027
7435 09:25:00.364885 40 : 4253, 4026
7436 09:25:00.368010 44 : 4255, 4029
7437 09:25:00.368091 48 : 4363, 4137
7438 09:25:00.368151 52 : 4250, 4027
7439 09:25:00.371324 56 : 4361, 4138
7440 09:25:00.371404 60 : 4253, 4026
7441 09:25:00.374437 64 : 4250, 4027
7442 09:25:00.374503 68 : 4250, 4026
7443 09:25:00.377920 72 : 4361, 4137
7444 09:25:00.377986 76 : 4250, 4027
7445 09:25:00.378041 80 : 4361, 4137
7446 09:25:00.381449 84 : 4252, 4027
7447 09:25:00.381518 88 : 4250, 198
7448 09:25:00.384429 92 : 4361, 0
7449 09:25:00.384492 96 : 4250, 0
7450 09:25:00.384548 100 : 4360, 0
7451 09:25:00.388025 104 : 4360, 0
7452 09:25:00.388089 108 : 4250, 0
7453 09:25:00.390753 112 : 4250, 0
7454 09:25:00.390821 116 : 4250, 0
7455 09:25:00.390876 120 : 4252, 0
7456 09:25:00.394367 124 : 4250, 0
7457 09:25:00.394438 128 : 4250, 0
7458 09:25:00.398050 132 : 4252, 0
7459 09:25:00.398177 136 : 4361, 0
7460 09:25:00.398319 140 : 4250, 0
7461 09:25:00.400866 144 : 4250, 0
7462 09:25:00.400936 148 : 4250, 0
7463 09:25:00.404308 152 : 4360, 0
7464 09:25:00.404383 156 : 4361, 0
7465 09:25:00.404440 160 : 4250, 0
7466 09:25:00.407663 164 : 4250, 0
7467 09:25:00.407727 168 : 4250, 0
7468 09:25:00.407790 172 : 4252, 0
7469 09:25:00.411248 176 : 4250, 0
7470 09:25:00.411316 180 : 4249, 0
7471 09:25:00.414787 184 : 4252, 0
7472 09:25:00.414860 188 : 4250, 0
7473 09:25:00.414918 192 : 4250, 0
7474 09:25:00.417585 196 : 4252, 0
7475 09:25:00.417671 200 : 4250, 0
7476 09:25:00.421249 204 : 4361, 1186
7477 09:25:00.421314 208 : 4363, 4058
7478 09:25:00.424760 212 : 4247, 4025
7479 09:25:00.424825 216 : 4360, 4138
7480 09:25:00.424881 220 : 4252, 4030
7481 09:25:00.427544 224 : 4250, 4026
7482 09:25:00.427625 228 : 4250, 4027
7483 09:25:00.431213 232 : 4252, 4030
7484 09:25:00.431278 236 : 4250, 4027
7485 09:25:00.434789 240 : 4250, 4026
7486 09:25:00.434854 244 : 4250, 4027
7487 09:25:00.437702 248 : 4252, 4030
7488 09:25:00.437768 252 : 4250, 4027
7489 09:25:00.441330 256 : 4361, 4137
7490 09:25:00.441393 260 : 4361, 4137
7491 09:25:00.444197 264 : 4250, 4027
7492 09:25:00.444274 268 : 4363, 4140
7493 09:25:00.447711 272 : 4361, 4137
7494 09:25:00.447775 276 : 4250, 4026
7495 09:25:00.447829 280 : 4250, 4027
7496 09:25:00.451299 284 : 4252, 4030
7497 09:25:00.451370 288 : 4250, 4027
7498 09:25:00.454147 292 : 4250, 4026
7499 09:25:00.454221 296 : 4250, 4027
7500 09:25:00.457659 300 : 4252, 4030
7501 09:25:00.457724 304 : 4250, 4027
7502 09:25:00.461211 308 : 4361, 4104
7503 09:25:00.461276 312 : 4361, 2203
7504 09:25:00.464705 316 : 4250, 11
7505 09:25:00.464769
7506 09:25:00.464821 MIOCK jitter meter ch=0
7507 09:25:00.464879
7508 09:25:00.467538 1T = (316-88) = 228 dly cells
7509 09:25:00.474589 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7510 09:25:00.474666 ==
7511 09:25:00.478121 Dram Type= 6, Freq= 0, CH_0, rank 0
7512 09:25:00.481213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7513 09:25:00.481433 ==
7514 09:25:00.487926 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7515 09:25:00.491124 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7516 09:25:00.494460 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7517 09:25:00.501387 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7518 09:25:00.510632 [CA 0] Center 43 (12~74) winsize 63
7519 09:25:00.514123 [CA 1] Center 43 (12~74) winsize 63
7520 09:25:00.517405 [CA 2] Center 38 (9~68) winsize 60
7521 09:25:00.520217 [CA 3] Center 38 (8~68) winsize 61
7522 09:25:00.523695 [CA 4] Center 37 (7~67) winsize 61
7523 09:25:00.527366 [CA 5] Center 35 (6~65) winsize 60
7524 09:25:00.527465
7525 09:25:00.530379 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7526 09:25:00.530471
7527 09:25:00.533975 [CATrainingPosCal] consider 1 rank data
7528 09:25:00.536736 u2DelayCellTimex100 = 285/100 ps
7529 09:25:00.540210 CA0 delay=43 (12~74),Diff = 8 PI (27 cell)
7530 09:25:00.547401 CA1 delay=43 (12~74),Diff = 8 PI (27 cell)
7531 09:25:00.550188 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7532 09:25:00.553777 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7533 09:25:00.557378 CA4 delay=37 (7~67),Diff = 2 PI (6 cell)
7534 09:25:00.560152 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7535 09:25:00.560221
7536 09:25:00.563794 CA PerBit enable=1, Macro0, CA PI delay=35
7537 09:25:00.563870
7538 09:25:00.567342 [CBTSetCACLKResult] CA Dly = 35
7539 09:25:00.570733 CS Dly: 9 (0~40)
7540 09:25:00.573437 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7541 09:25:00.576818 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7542 09:25:00.576888 ==
7543 09:25:00.580360 Dram Type= 6, Freq= 0, CH_0, rank 1
7544 09:25:00.583921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 09:25:00.584041 ==
7546 09:25:00.590171 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7547 09:25:00.593727 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7548 09:25:00.600367 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7549 09:25:00.603420 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7550 09:25:00.614013 [CA 0] Center 42 (12~73) winsize 62
7551 09:25:00.617786 [CA 1] Center 42 (12~73) winsize 62
7552 09:25:00.620457 [CA 2] Center 38 (8~68) winsize 61
7553 09:25:00.623906 [CA 3] Center 37 (7~67) winsize 61
7554 09:25:00.627199 [CA 4] Center 35 (5~65) winsize 61
7555 09:25:00.630480 [CA 5] Center 35 (5~65) winsize 61
7556 09:25:00.630550
7557 09:25:00.633691 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7558 09:25:00.633785
7559 09:25:00.637151 [CATrainingPosCal] consider 2 rank data
7560 09:25:00.640128 u2DelayCellTimex100 = 285/100 ps
7561 09:25:00.643517 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7562 09:25:00.650677 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7563 09:25:00.653680 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7564 09:25:00.657300 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7565 09:25:00.660124 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7566 09:25:00.663744 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7567 09:25:00.663813
7568 09:25:00.667269 CA PerBit enable=1, Macro0, CA PI delay=35
7569 09:25:00.667338
7570 09:25:00.670291 [CBTSetCACLKResult] CA Dly = 35
7571 09:25:00.673986 CS Dly: 10 (0~42)
7572 09:25:00.676839 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7573 09:25:00.680307 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7574 09:25:00.680377
7575 09:25:00.683864 ----->DramcWriteLeveling(PI) begin...
7576 09:25:00.683946 ==
7577 09:25:00.687238 Dram Type= 6, Freq= 0, CH_0, rank 0
7578 09:25:00.690102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 09:25:00.693628 ==
7580 09:25:00.693697 Write leveling (Byte 0): 33 => 33
7581 09:25:00.696937 Write leveling (Byte 1): 26 => 26
7582 09:25:00.700589 DramcWriteLeveling(PI) end<-----
7583 09:25:00.700688
7584 09:25:00.700783 ==
7585 09:25:00.703358 Dram Type= 6, Freq= 0, CH_0, rank 0
7586 09:25:00.710526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7587 09:25:00.710600 ==
7588 09:25:00.713980 [Gating] SW mode calibration
7589 09:25:00.720443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7590 09:25:00.723526 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7591 09:25:00.730578 1 4 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7592 09:25:00.733655 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7593 09:25:00.736785 1 4 8 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7594 09:25:00.743639 1 4 12 | B1->B0 | 2323 3838 | 0 1 | (0 0) (1 1)
7595 09:25:00.746864 1 4 16 | B1->B0 | 2323 3837 | 0 1 | (0 0) (1 1)
7596 09:25:00.750265 1 4 20 | B1->B0 | 3333 3737 | 1 1 | (1 1) (1 1)
7597 09:25:00.753404 1 4 24 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
7598 09:25:00.759778 1 4 28 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)
7599 09:25:00.763390 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7600 09:25:00.767037 1 5 4 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7601 09:25:00.773219 1 5 8 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 0)
7602 09:25:00.776844 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
7603 09:25:00.779777 1 5 16 | B1->B0 | 3434 2c2b | 1 1 | (1 0) (0 0)
7604 09:25:00.786814 1 5 20 | B1->B0 | 2424 2827 | 0 1 | (0 0) (1 1)
7605 09:25:00.790223 1 5 24 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7606 09:25:00.792960 1 5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7607 09:25:00.800015 1 6 0 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (1 1)
7608 09:25:00.803522 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7609 09:25:00.806526 1 6 8 | B1->B0 | 2323 3736 | 0 1 | (0 0) (0 0)
7610 09:25:00.813043 1 6 12 | B1->B0 | 2323 4544 | 0 1 | (0 0) (0 0)
7611 09:25:00.816604 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7612 09:25:00.820234 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7613 09:25:00.826608 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 09:25:00.830154 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 09:25:00.833058 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 09:25:00.839518 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 09:25:00.842828 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 09:25:00.846188 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7619 09:25:00.853421 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7620 09:25:00.856534 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7621 09:25:00.859780 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 09:25:00.866403 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 09:25:00.869616 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 09:25:00.872783 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 09:25:00.879958 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 09:25:00.882860 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 09:25:00.886330 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 09:25:00.889987 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 09:25:00.896348 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 09:25:00.899838 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 09:25:00.903291 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 09:25:00.909746 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 09:25:00.913310 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7634 09:25:00.916274 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7635 09:25:00.922762 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7636 09:25:00.922841 Total UI for P1: 0, mck2ui 16
7637 09:25:00.929970 best dqsien dly found for B0: ( 1, 9, 10)
7638 09:25:00.932776 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 09:25:00.936277 Total UI for P1: 0, mck2ui 16
7640 09:25:00.939904 best dqsien dly found for B1: ( 1, 9, 16)
7641 09:25:00.942808 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7642 09:25:00.946321 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7643 09:25:00.946483
7644 09:25:00.949917 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7645 09:25:00.952861 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7646 09:25:00.956436 [Gating] SW calibration Done
7647 09:25:00.956538 ==
7648 09:25:00.959354 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 09:25:00.966086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 09:25:00.966191 ==
7651 09:25:00.966277 RX Vref Scan: 0
7652 09:25:00.966364
7653 09:25:00.969330 RX Vref 0 -> 0, step: 1
7654 09:25:00.969446
7655 09:25:00.972823 RX Delay 0 -> 252, step: 8
7656 09:25:00.976246 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7657 09:25:00.979424 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7658 09:25:00.982722 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7659 09:25:00.986108 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7660 09:25:00.992769 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7661 09:25:00.995650 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7662 09:25:00.999196 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7663 09:25:01.002755 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7664 09:25:01.005457 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7665 09:25:01.012585 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7666 09:25:01.016130 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7667 09:25:01.019012 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7668 09:25:01.022727 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7669 09:25:01.026152 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7670 09:25:01.032604 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7671 09:25:01.036115 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7672 09:25:01.036218 ==
7673 09:25:01.039376 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 09:25:01.042689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 09:25:01.042774 ==
7676 09:25:01.046079 DQS Delay:
7677 09:25:01.046175 DQS0 = 0, DQS1 = 0
7678 09:25:01.046260 DQM Delay:
7679 09:25:01.049650 DQM0 = 137, DQM1 = 130
7680 09:25:01.049719 DQ Delay:
7681 09:25:01.052480 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7682 09:25:01.056206 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7683 09:25:01.059079 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7684 09:25:01.066009 DQ12 =131, DQ13 =139, DQ14 =139, DQ15 =135
7685 09:25:01.066109
7686 09:25:01.066195
7687 09:25:01.066277 ==
7688 09:25:01.068728 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 09:25:01.072117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 09:25:01.072211 ==
7691 09:25:01.072294
7692 09:25:01.072374
7693 09:25:01.075573 TX Vref Scan disable
7694 09:25:01.075660 == TX Byte 0 ==
7695 09:25:01.082043 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7696 09:25:01.085558 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7697 09:25:01.085630 == TX Byte 1 ==
7698 09:25:01.092410 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7699 09:25:01.095632 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7700 09:25:01.095730 ==
7701 09:25:01.098980 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 09:25:01.102276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 09:25:01.102396 ==
7704 09:25:01.116937
7705 09:25:01.119754 TX Vref early break, caculate TX vref
7706 09:25:01.123258 TX Vref=16, minBit 0, minWin=22, winSum=381
7707 09:25:01.126935 TX Vref=18, minBit 0, minWin=24, winSum=394
7708 09:25:01.129677 TX Vref=20, minBit 7, minWin=24, winSum=408
7709 09:25:01.133214 TX Vref=22, minBit 4, minWin=24, winSum=412
7710 09:25:01.136833 TX Vref=24, minBit 0, minWin=26, winSum=422
7711 09:25:01.143495 TX Vref=26, minBit 6, minWin=25, winSum=425
7712 09:25:01.146337 TX Vref=28, minBit 2, minWin=25, winSum=425
7713 09:25:01.149723 TX Vref=30, minBit 2, minWin=25, winSum=415
7714 09:25:01.153206 TX Vref=32, minBit 6, minWin=24, winSum=409
7715 09:25:01.156189 TX Vref=34, minBit 1, minWin=23, winSum=396
7716 09:25:01.163404 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 24
7717 09:25:01.163518
7718 09:25:01.166217 Final TX Range 0 Vref 24
7719 09:25:01.166317
7720 09:25:01.166402 ==
7721 09:25:01.169653 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 09:25:01.173206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 09:25:01.173308 ==
7724 09:25:01.173402
7725 09:25:01.173496
7726 09:25:01.176761 TX Vref Scan disable
7727 09:25:01.183191 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7728 09:25:01.183291 == TX Byte 0 ==
7729 09:25:01.186649 u2DelayCellOfst[0]=13 cells (4 PI)
7730 09:25:01.189479 u2DelayCellOfst[1]=17 cells (5 PI)
7731 09:25:01.193382 u2DelayCellOfst[2]=13 cells (4 PI)
7732 09:25:01.196640 u2DelayCellOfst[3]=13 cells (4 PI)
7733 09:25:01.199896 u2DelayCellOfst[4]=10 cells (3 PI)
7734 09:25:01.203164 u2DelayCellOfst[5]=0 cells (0 PI)
7735 09:25:01.206454 u2DelayCellOfst[6]=17 cells (5 PI)
7736 09:25:01.209695 u2DelayCellOfst[7]=17 cells (5 PI)
7737 09:25:01.213106 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7738 09:25:01.216483 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7739 09:25:01.219333 == TX Byte 1 ==
7740 09:25:01.219429 u2DelayCellOfst[8]=0 cells (0 PI)
7741 09:25:01.222663 u2DelayCellOfst[9]=0 cells (0 PI)
7742 09:25:01.226332 u2DelayCellOfst[10]=6 cells (2 PI)
7743 09:25:01.229755 u2DelayCellOfst[11]=3 cells (1 PI)
7744 09:25:01.232545 u2DelayCellOfst[12]=10 cells (3 PI)
7745 09:25:01.235921 u2DelayCellOfst[13]=10 cells (3 PI)
7746 09:25:01.239497 u2DelayCellOfst[14]=17 cells (5 PI)
7747 09:25:01.243072 u2DelayCellOfst[15]=10 cells (3 PI)
7748 09:25:01.245929 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7749 09:25:01.252403 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7750 09:25:01.252505 DramC Write-DBI on
7751 09:25:01.252599 ==
7752 09:25:01.255853 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 09:25:01.259330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 09:25:01.262833 ==
7755 09:25:01.262937
7756 09:25:01.263027
7757 09:25:01.263121 TX Vref Scan disable
7758 09:25:01.266558 == TX Byte 0 ==
7759 09:25:01.269506 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7760 09:25:01.273152 == TX Byte 1 ==
7761 09:25:01.276600 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7762 09:25:01.276703 DramC Write-DBI off
7763 09:25:01.279510
7764 09:25:01.279611 [DATLAT]
7765 09:25:01.279707 Freq=1600, CH0 RK0
7766 09:25:01.279790
7767 09:25:01.283184 DATLAT Default: 0xf
7768 09:25:01.283279 0, 0xFFFF, sum = 0
7769 09:25:01.286175 1, 0xFFFF, sum = 0
7770 09:25:01.286250 2, 0xFFFF, sum = 0
7771 09:25:01.289726 3, 0xFFFF, sum = 0
7772 09:25:01.289804 4, 0xFFFF, sum = 0
7773 09:25:01.293283 5, 0xFFFF, sum = 0
7774 09:25:01.296010 6, 0xFFFF, sum = 0
7775 09:25:01.296089 7, 0xFFFF, sum = 0
7776 09:25:01.299770 8, 0xFFFF, sum = 0
7777 09:25:01.299849 9, 0xFFFF, sum = 0
7778 09:25:01.303223 10, 0xFFFF, sum = 0
7779 09:25:01.303302 11, 0xFFFF, sum = 0
7780 09:25:01.306575 12, 0xFFFF, sum = 0
7781 09:25:01.306653 13, 0xFFFF, sum = 0
7782 09:25:01.309957 14, 0x0, sum = 1
7783 09:25:01.310035 15, 0x0, sum = 2
7784 09:25:01.313210 16, 0x0, sum = 3
7785 09:25:01.313288 17, 0x0, sum = 4
7786 09:25:01.313348 best_step = 15
7787 09:25:01.316478
7788 09:25:01.316556 ==
7789 09:25:01.319919 Dram Type= 6, Freq= 0, CH_0, rank 0
7790 09:25:01.323313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7791 09:25:01.323391 ==
7792 09:25:01.323450 RX Vref Scan: 1
7793 09:25:01.323505
7794 09:25:01.326107 Set Vref Range= 24 -> 127
7795 09:25:01.326184
7796 09:25:01.329594 RX Vref 24 -> 127, step: 1
7797 09:25:01.329671
7798 09:25:01.332998 RX Delay 27 -> 252, step: 4
7799 09:25:01.333074
7800 09:25:01.336351 Set Vref, RX VrefLevel [Byte0]: 24
7801 09:25:01.339546 [Byte1]: 24
7802 09:25:01.339623
7803 09:25:01.342785 Set Vref, RX VrefLevel [Byte0]: 25
7804 09:25:01.346092 [Byte1]: 25
7805 09:25:01.346169
7806 09:25:01.349446 Set Vref, RX VrefLevel [Byte0]: 26
7807 09:25:01.353060 [Byte1]: 26
7808 09:25:01.356796
7809 09:25:01.356873 Set Vref, RX VrefLevel [Byte0]: 27
7810 09:25:01.359646 [Byte1]: 27
7811 09:25:01.363967
7812 09:25:01.364043 Set Vref, RX VrefLevel [Byte0]: 28
7813 09:25:01.367403 [Byte1]: 28
7814 09:25:01.371701
7815 09:25:01.371778 Set Vref, RX VrefLevel [Byte0]: 29
7816 09:25:01.374636 [Byte1]: 29
7817 09:25:01.378999
7818 09:25:01.379077 Set Vref, RX VrefLevel [Byte0]: 30
7819 09:25:01.382546 [Byte1]: 30
7820 09:25:01.386805
7821 09:25:01.386883 Set Vref, RX VrefLevel [Byte0]: 31
7822 09:25:01.389658 [Byte1]: 31
7823 09:25:01.394131
7824 09:25:01.394207 Set Vref, RX VrefLevel [Byte0]: 32
7825 09:25:01.397679 [Byte1]: 32
7826 09:25:01.401740
7827 09:25:01.401819 Set Vref, RX VrefLevel [Byte0]: 33
7828 09:25:01.404743 [Byte1]: 33
7829 09:25:01.409007
7830 09:25:01.409084 Set Vref, RX VrefLevel [Byte0]: 34
7831 09:25:01.412562 [Byte1]: 34
7832 09:25:01.416711
7833 09:25:01.416787 Set Vref, RX VrefLevel [Byte0]: 35
7834 09:25:01.420207 [Byte1]: 35
7835 09:25:01.424154
7836 09:25:01.424229 Set Vref, RX VrefLevel [Byte0]: 36
7837 09:25:01.427377 [Byte1]: 36
7838 09:25:01.431511
7839 09:25:01.431587 Set Vref, RX VrefLevel [Byte0]: 37
7840 09:25:01.434827 [Byte1]: 37
7841 09:25:01.439113
7842 09:25:01.439189 Set Vref, RX VrefLevel [Byte0]: 38
7843 09:25:01.442864 [Byte1]: 38
7844 09:25:01.447172
7845 09:25:01.447263 Set Vref, RX VrefLevel [Byte0]: 39
7846 09:25:01.450607 [Byte1]: 39
7847 09:25:01.454685
7848 09:25:01.454760 Set Vref, RX VrefLevel [Byte0]: 40
7849 09:25:01.457328 [Byte1]: 40
7850 09:25:01.461946
7851 09:25:01.462037 Set Vref, RX VrefLevel [Byte0]: 41
7852 09:25:01.465298 [Byte1]: 41
7853 09:25:01.469216
7854 09:25:01.469310 Set Vref, RX VrefLevel [Byte0]: 42
7855 09:25:01.472829 [Byte1]: 42
7856 09:25:01.477008
7857 09:25:01.477135 Set Vref, RX VrefLevel [Byte0]: 43
7858 09:25:01.480498 [Byte1]: 43
7859 09:25:01.484224
7860 09:25:01.484333 Set Vref, RX VrefLevel [Byte0]: 44
7861 09:25:01.487685 [Byte1]: 44
7862 09:25:01.492013
7863 09:25:01.492140 Set Vref, RX VrefLevel [Byte0]: 45
7864 09:25:01.495015 [Byte1]: 45
7865 09:25:01.499413
7866 09:25:01.499506 Set Vref, RX VrefLevel [Byte0]: 46
7867 09:25:01.503129 [Byte1]: 46
7868 09:25:01.507240
7869 09:25:01.507384 Set Vref, RX VrefLevel [Byte0]: 47
7870 09:25:01.510187 [Byte1]: 47
7871 09:25:01.514692
7872 09:25:01.514766 Set Vref, RX VrefLevel [Byte0]: 48
7873 09:25:01.517699 [Byte1]: 48
7874 09:25:01.522020
7875 09:25:01.522189 Set Vref, RX VrefLevel [Byte0]: 49
7876 09:25:01.525671 [Byte1]: 49
7877 09:25:01.530001
7878 09:25:01.530075 Set Vref, RX VrefLevel [Byte0]: 50
7879 09:25:01.532917 [Byte1]: 50
7880 09:25:01.537021
7881 09:25:01.537100 Set Vref, RX VrefLevel [Byte0]: 51
7882 09:25:01.540200 [Byte1]: 51
7883 09:25:01.545078
7884 09:25:01.545167 Set Vref, RX VrefLevel [Byte0]: 52
7885 09:25:01.547985 [Byte1]: 52
7886 09:25:01.552306
7887 09:25:01.552380 Set Vref, RX VrefLevel [Byte0]: 53
7888 09:25:01.555911 [Byte1]: 53
7889 09:25:01.559600
7890 09:25:01.559678 Set Vref, RX VrefLevel [Byte0]: 54
7891 09:25:01.563237 [Byte1]: 54
7892 09:25:01.567591
7893 09:25:01.567669 Set Vref, RX VrefLevel [Byte0]: 55
7894 09:25:01.570998 [Byte1]: 55
7895 09:25:01.575123
7896 09:25:01.575200 Set Vref, RX VrefLevel [Byte0]: 56
7897 09:25:01.577840 [Byte1]: 56
7898 09:25:01.582506
7899 09:25:01.582584 Set Vref, RX VrefLevel [Byte0]: 57
7900 09:25:01.585623 [Byte1]: 57
7901 09:25:01.589870
7902 09:25:01.589980 Set Vref, RX VrefLevel [Byte0]: 58
7903 09:25:01.593413 [Byte1]: 58
7904 09:25:01.597808
7905 09:25:01.597889 Set Vref, RX VrefLevel [Byte0]: 59
7906 09:25:01.600500 [Byte1]: 59
7907 09:25:01.604762
7908 09:25:01.604856 Set Vref, RX VrefLevel [Byte0]: 60
7909 09:25:01.607954 [Byte1]: 60
7910 09:25:01.612146
7911 09:25:01.612240 Set Vref, RX VrefLevel [Byte0]: 61
7912 09:25:01.615504 [Byte1]: 61
7913 09:25:01.619897
7914 09:25:01.619990 Set Vref, RX VrefLevel [Byte0]: 62
7915 09:25:01.623569 [Byte1]: 62
7916 09:25:01.627250
7917 09:25:01.627329 Set Vref, RX VrefLevel [Byte0]: 63
7918 09:25:01.630921 [Byte1]: 63
7919 09:25:01.635358
7920 09:25:01.635432 Set Vref, RX VrefLevel [Byte0]: 64
7921 09:25:01.638192 [Byte1]: 64
7922 09:25:01.642665
7923 09:25:01.642744 Set Vref, RX VrefLevel [Byte0]: 65
7924 09:25:01.646254 [Byte1]: 65
7925 09:25:01.650174
7926 09:25:01.650252 Set Vref, RX VrefLevel [Byte0]: 66
7927 09:25:01.653272 [Byte1]: 66
7928 09:25:01.657432
7929 09:25:01.657529 Set Vref, RX VrefLevel [Byte0]: 67
7930 09:25:01.660953 [Byte1]: 67
7931 09:25:01.665333
7932 09:25:01.665406 Set Vref, RX VrefLevel [Byte0]: 68
7933 09:25:01.668246 [Byte1]: 68
7934 09:25:01.672667
7935 09:25:01.672750 Set Vref, RX VrefLevel [Byte0]: 69
7936 09:25:01.676187 [Byte1]: 69
7937 09:25:01.680433
7938 09:25:01.680520 Set Vref, RX VrefLevel [Byte0]: 70
7939 09:25:01.683281 [Byte1]: 70
7940 09:25:01.687761
7941 09:25:01.687833 Set Vref, RX VrefLevel [Byte0]: 71
7942 09:25:01.691316 [Byte1]: 71
7943 09:25:01.695191
7944 09:25:01.695263 Set Vref, RX VrefLevel [Byte0]: 72
7945 09:25:01.698550 [Byte1]: 72
7946 09:25:01.702834
7947 09:25:01.702913 Set Vref, RX VrefLevel [Byte0]: 73
7948 09:25:01.706064 [Byte1]: 73
7949 09:25:01.710673
7950 09:25:01.710756 Set Vref, RX VrefLevel [Byte0]: 74
7951 09:25:01.714031 [Byte1]: 74
7952 09:25:01.718345
7953 09:25:01.718431 Set Vref, RX VrefLevel [Byte0]: 75
7954 09:25:01.721201 [Byte1]: 75
7955 09:25:01.725470
7956 09:25:01.725543 Final RX Vref Byte 0 = 56 to rank0
7957 09:25:01.729027 Final RX Vref Byte 1 = 65 to rank0
7958 09:25:01.731885 Final RX Vref Byte 0 = 56 to rank1
7959 09:25:01.735510 Final RX Vref Byte 1 = 65 to rank1==
7960 09:25:01.738527 Dram Type= 6, Freq= 0, CH_0, rank 0
7961 09:25:01.745229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 09:25:01.745320 ==
7963 09:25:01.745383 DQS Delay:
7964 09:25:01.745438 DQS0 = 0, DQS1 = 0
7965 09:25:01.748855 DQM Delay:
7966 09:25:01.748922 DQM0 = 134, DQM1 = 127
7967 09:25:01.751679 DQ Delay:
7968 09:25:01.755422 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7969 09:25:01.758887 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7970 09:25:01.761559 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7971 09:25:01.764998 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7972 09:25:01.765078
7973 09:25:01.765170
7974 09:25:01.765256
7975 09:25:01.768702 [DramC_TX_OE_Calibration] TA2
7976 09:25:01.772007 Original DQ_B0 (3 6) =30, OEN = 27
7977 09:25:01.775047 Original DQ_B1 (3 6) =30, OEN = 27
7978 09:25:01.778509 24, 0x0, End_B0=24 End_B1=24
7979 09:25:01.778589 25, 0x0, End_B0=25 End_B1=25
7980 09:25:01.782196 26, 0x0, End_B0=26 End_B1=26
7981 09:25:01.784922 27, 0x0, End_B0=27 End_B1=27
7982 09:25:01.788752 28, 0x0, End_B0=28 End_B1=28
7983 09:25:01.791725 29, 0x0, End_B0=29 End_B1=29
7984 09:25:01.791819 30, 0x0, End_B0=30 End_B1=30
7985 09:25:01.795453 31, 0x5151, End_B0=30 End_B1=30
7986 09:25:01.798328 Byte0 end_step=30 best_step=27
7987 09:25:01.802052 Byte1 end_step=30 best_step=27
7988 09:25:01.804920 Byte0 TX OE(2T, 0.5T) = (3, 3)
7989 09:25:01.808298 Byte1 TX OE(2T, 0.5T) = (3, 3)
7990 09:25:01.808385
7991 09:25:01.808463
7992 09:25:01.815439 [DQSOSCAuto] RK0, (LSB)MR18= 0x2823, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
7993 09:25:01.818923 CH0 RK0: MR19=303, MR18=2823
7994 09:25:01.824934 CH0_RK0: MR19=0x303, MR18=0x2823, DQSOSC=389, MR23=63, INC=24, DEC=16
7995 09:25:01.825036
7996 09:25:01.828307 ----->DramcWriteLeveling(PI) begin...
7997 09:25:01.828378 ==
7998 09:25:01.832148 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 09:25:01.835125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 09:25:01.835199 ==
8001 09:25:01.838424 Write leveling (Byte 0): 37 => 37
8002 09:25:01.841942 Write leveling (Byte 1): 27 => 27
8003 09:25:01.845405 DramcWriteLeveling(PI) end<-----
8004 09:25:01.845484
8005 09:25:01.845553 ==
8006 09:25:01.848449 Dram Type= 6, Freq= 0, CH_0, rank 1
8007 09:25:01.852098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 09:25:01.852177 ==
8009 09:25:01.855013 [Gating] SW mode calibration
8010 09:25:01.861494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8011 09:25:01.868280 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8012 09:25:01.871726 1 4 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
8013 09:25:01.875056 1 4 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8014 09:25:01.882186 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8015 09:25:01.885443 1 4 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8016 09:25:01.888674 1 4 16 | B1->B0 | 3131 3635 | 1 1 | (1 1) (0 0)
8017 09:25:01.895497 1 4 20 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
8018 09:25:01.898261 1 4 24 | B1->B0 | 3434 3939 | 1 0 | (1 1) (1 1)
8019 09:25:01.902083 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8020 09:25:01.908421 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
8021 09:25:01.912015 1 5 4 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
8022 09:25:01.915565 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
8023 09:25:01.922134 1 5 12 | B1->B0 | 3434 3838 | 1 1 | (1 0) (0 1)
8024 09:25:01.924984 1 5 16 | B1->B0 | 2929 2c2c | 1 0 | (1 0) (1 0)
8025 09:25:01.928779 1 5 20 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (1 1)
8026 09:25:01.935216 1 5 24 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
8027 09:25:01.938469 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8028 09:25:01.942131 1 6 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
8029 09:25:01.948619 1 6 4 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (1 1)
8030 09:25:01.951879 1 6 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
8031 09:25:01.954841 1 6 12 | B1->B0 | 2525 3939 | 0 1 | (0 0) (0 0)
8032 09:25:01.958437 1 6 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8033 09:25:01.965131 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8034 09:25:01.968082 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8035 09:25:01.971680 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 09:25:01.978253 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 09:25:01.981266 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 09:25:01.984654 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 09:25:01.991679 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8040 09:25:01.995063 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8041 09:25:01.997996 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 09:25:02.005099 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 09:25:02.008300 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 09:25:02.011387 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 09:25:02.018209 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 09:25:02.021593 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 09:25:02.024473 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 09:25:02.031089 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 09:25:02.034733 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 09:25:02.037695 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 09:25:02.045004 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 09:25:02.047962 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 09:25:02.051502 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 09:25:02.058275 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 09:25:02.061187 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8056 09:25:02.064771 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 09:25:02.068303 Total UI for P1: 0, mck2ui 16
8058 09:25:02.071583 best dqsien dly found for B0: ( 1, 9, 12)
8059 09:25:02.074882 Total UI for P1: 0, mck2ui 16
8060 09:25:02.077970 best dqsien dly found for B1: ( 1, 9, 12)
8061 09:25:02.081063 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8062 09:25:02.084797 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8063 09:25:02.084865
8064 09:25:02.087930 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8065 09:25:02.094791 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8066 09:25:02.094863 [Gating] SW calibration Done
8067 09:25:02.094922 ==
8068 09:25:02.098384 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 09:25:02.104868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 09:25:02.104969 ==
8071 09:25:02.105063 RX Vref Scan: 0
8072 09:25:02.105132
8073 09:25:02.107952 RX Vref 0 -> 0, step: 1
8074 09:25:02.108046
8075 09:25:02.111582 RX Delay 0 -> 252, step: 8
8076 09:25:02.114344 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8077 09:25:02.117632 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8078 09:25:02.120945 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8079 09:25:02.127869 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8080 09:25:02.131073 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8081 09:25:02.134463 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8082 09:25:02.138045 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8083 09:25:02.140894 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8084 09:25:02.144567 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8085 09:25:02.151253 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8086 09:25:02.154303 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8087 09:25:02.158128 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8088 09:25:02.161046 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8089 09:25:02.164680 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8090 09:25:02.171266 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8091 09:25:02.174878 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8092 09:25:02.174956 ==
8093 09:25:02.177821 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 09:25:02.181325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 09:25:02.181427 ==
8096 09:25:02.184685 DQS Delay:
8097 09:25:02.184765 DQS0 = 0, DQS1 = 0
8098 09:25:02.184838 DQM Delay:
8099 09:25:02.187549 DQM0 = 137, DQM1 = 131
8100 09:25:02.187660 DQ Delay:
8101 09:25:02.190982 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8102 09:25:02.194560 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8103 09:25:02.201147 DQ8 =123, DQ9 =123, DQ10 =131, DQ11 =123
8104 09:25:02.204362 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8105 09:25:02.204464
8106 09:25:02.204557
8107 09:25:02.204642 ==
8108 09:25:02.207531 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 09:25:02.211017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 09:25:02.211116 ==
8111 09:25:02.211213
8112 09:25:02.211298
8113 09:25:02.214469 TX Vref Scan disable
8114 09:25:02.217795 == TX Byte 0 ==
8115 09:25:02.221314 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8116 09:25:02.224156 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8117 09:25:02.227639 == TX Byte 1 ==
8118 09:25:02.231045 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8119 09:25:02.234476 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8120 09:25:02.234566 ==
8121 09:25:02.237856 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 09:25:02.241137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 09:25:02.241247 ==
8124 09:25:02.256137
8125 09:25:02.259854 TX Vref early break, caculate TX vref
8126 09:25:02.262761 TX Vref=16, minBit 3, minWin=22, winSum=386
8127 09:25:02.266561 TX Vref=18, minBit 1, minWin=23, winSum=395
8128 09:25:02.269497 TX Vref=20, minBit 1, minWin=24, winSum=405
8129 09:25:02.273166 TX Vref=22, minBit 3, minWin=24, winSum=410
8130 09:25:02.276106 TX Vref=24, minBit 1, minWin=25, winSum=421
8131 09:25:02.283326 TX Vref=26, minBit 3, minWin=25, winSum=425
8132 09:25:02.286132 TX Vref=28, minBit 1, minWin=25, winSum=422
8133 09:25:02.289682 TX Vref=30, minBit 0, minWin=25, winSum=416
8134 09:25:02.293317 TX Vref=32, minBit 1, minWin=24, winSum=407
8135 09:25:02.296254 TX Vref=34, minBit 0, minWin=24, winSum=401
8136 09:25:02.303255 [TxChooseVref] Worse bit 3, Min win 25, Win sum 425, Final Vref 26
8137 09:25:02.303338
8138 09:25:02.306305 Final TX Range 0 Vref 26
8139 09:25:02.306375
8140 09:25:02.306432 ==
8141 09:25:02.309830 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 09:25:02.312762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 09:25:02.312831 ==
8144 09:25:02.312888
8145 09:25:02.312945
8146 09:25:02.316256 TX Vref Scan disable
8147 09:25:02.323085 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8148 09:25:02.323163 == TX Byte 0 ==
8149 09:25:02.326225 u2DelayCellOfst[0]=13 cells (4 PI)
8150 09:25:02.329617 u2DelayCellOfst[1]=17 cells (5 PI)
8151 09:25:02.333360 u2DelayCellOfst[2]=13 cells (4 PI)
8152 09:25:02.336415 u2DelayCellOfst[3]=10 cells (3 PI)
8153 09:25:02.340090 u2DelayCellOfst[4]=6 cells (2 PI)
8154 09:25:02.340161 u2DelayCellOfst[5]=0 cells (0 PI)
8155 09:25:02.343111 u2DelayCellOfst[6]=17 cells (5 PI)
8156 09:25:02.346175 u2DelayCellOfst[7]=17 cells (5 PI)
8157 09:25:02.353067 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8158 09:25:02.356425 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8159 09:25:02.356507 == TX Byte 1 ==
8160 09:25:02.359765 u2DelayCellOfst[8]=3 cells (1 PI)
8161 09:25:02.363195 u2DelayCellOfst[9]=0 cells (0 PI)
8162 09:25:02.366262 u2DelayCellOfst[10]=6 cells (2 PI)
8163 09:25:02.369608 u2DelayCellOfst[11]=6 cells (2 PI)
8164 09:25:02.373117 u2DelayCellOfst[12]=10 cells (3 PI)
8165 09:25:02.375983 u2DelayCellOfst[13]=10 cells (3 PI)
8166 09:25:02.379641 u2DelayCellOfst[14]=13 cells (4 PI)
8167 09:25:02.382669 u2DelayCellOfst[15]=10 cells (3 PI)
8168 09:25:02.386353 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8169 09:25:02.389160 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8170 09:25:02.392858 DramC Write-DBI on
8171 09:25:02.392958 ==
8172 09:25:02.396565 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 09:25:02.399306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 09:25:02.399396 ==
8175 09:25:02.399494
8176 09:25:02.402843
8177 09:25:02.402941 TX Vref Scan disable
8178 09:25:02.406473 == TX Byte 0 ==
8179 09:25:02.409438 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8180 09:25:02.412411 == TX Byte 1 ==
8181 09:25:02.416129 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8182 09:25:02.416199 DramC Write-DBI off
8183 09:25:02.419663
8184 09:25:02.419728 [DATLAT]
8185 09:25:02.419783 Freq=1600, CH0 RK1
8186 09:25:02.419837
8187 09:25:02.422608 DATLAT Default: 0xf
8188 09:25:02.422669 0, 0xFFFF, sum = 0
8189 09:25:02.426198 1, 0xFFFF, sum = 0
8190 09:25:02.426304 2, 0xFFFF, sum = 0
8191 09:25:02.429294 3, 0xFFFF, sum = 0
8192 09:25:02.433004 4, 0xFFFF, sum = 0
8193 09:25:02.433088 5, 0xFFFF, sum = 0
8194 09:25:02.435767 6, 0xFFFF, sum = 0
8195 09:25:02.435853 7, 0xFFFF, sum = 0
8196 09:25:02.439430 8, 0xFFFF, sum = 0
8197 09:25:02.439542 9, 0xFFFF, sum = 0
8198 09:25:02.442312 10, 0xFFFF, sum = 0
8199 09:25:02.442389 11, 0xFFFF, sum = 0
8200 09:25:02.445834 12, 0xFFFF, sum = 0
8201 09:25:02.445958 13, 0xFFFF, sum = 0
8202 09:25:02.449421 14, 0x0, sum = 1
8203 09:25:02.449532 15, 0x0, sum = 2
8204 09:25:02.452734 16, 0x0, sum = 3
8205 09:25:02.452847 17, 0x0, sum = 4
8206 09:25:02.456092 best_step = 15
8207 09:25:02.456207
8208 09:25:02.456300 ==
8209 09:25:02.458841 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 09:25:02.462664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 09:25:02.462809 ==
8212 09:25:02.462925 RX Vref Scan: 0
8213 09:25:02.465992
8214 09:25:02.466120 RX Vref 0 -> 0, step: 1
8215 09:25:02.466209
8216 09:25:02.469135 RX Delay 27 -> 252, step: 4
8217 09:25:02.472341 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8218 09:25:02.479193 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8219 09:25:02.482856 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8220 09:25:02.485715 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8221 09:25:02.489076 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8222 09:25:02.492294 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8223 09:25:02.499366 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8224 09:25:02.502287 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8225 09:25:02.505888 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8226 09:25:02.509366 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8227 09:25:02.512119 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8228 09:25:02.518833 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8229 09:25:02.522490 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8230 09:25:02.525342 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8231 09:25:02.528952 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8232 09:25:02.532460 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8233 09:25:02.532597 ==
8234 09:25:02.535547 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 09:25:02.542120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 09:25:02.542230 ==
8237 09:25:02.542304 DQS Delay:
8238 09:25:02.545506 DQS0 = 0, DQS1 = 0
8239 09:25:02.545625 DQM Delay:
8240 09:25:02.549081 DQM0 = 133, DQM1 = 126
8241 09:25:02.549195 DQ Delay:
8242 09:25:02.552047 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8243 09:25:02.555792 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =140
8244 09:25:02.558717 DQ8 =120, DQ9 =116, DQ10 =126, DQ11 =118
8245 09:25:02.562265 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8246 09:25:02.562378
8247 09:25:02.562464
8248 09:25:02.562556
8249 09:25:02.565860 [DramC_TX_OE_Calibration] TA2
8250 09:25:02.569341 Original DQ_B0 (3 6) =30, OEN = 27
8251 09:25:02.572214 Original DQ_B1 (3 6) =30, OEN = 27
8252 09:25:02.575543 24, 0x0, End_B0=24 End_B1=24
8253 09:25:02.575626 25, 0x0, End_B0=25 End_B1=25
8254 09:25:02.578961 26, 0x0, End_B0=26 End_B1=26
8255 09:25:02.581874 27, 0x0, End_B0=27 End_B1=27
8256 09:25:02.585676 28, 0x0, End_B0=28 End_B1=28
8257 09:25:02.588765 29, 0x0, End_B0=29 End_B1=29
8258 09:25:02.588904 30, 0x0, End_B0=30 End_B1=30
8259 09:25:02.591939 31, 0x4545, End_B0=30 End_B1=30
8260 09:25:02.595285 Byte0 end_step=30 best_step=27
8261 09:25:02.598374 Byte1 end_step=30 best_step=27
8262 09:25:02.602176 Byte0 TX OE(2T, 0.5T) = (3, 3)
8263 09:25:02.605373 Byte1 TX OE(2T, 0.5T) = (3, 3)
8264 09:25:02.605446
8265 09:25:02.605525
8266 09:25:02.611697 [DQSOSCAuto] RK1, (LSB)MR18= 0x220b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8267 09:25:02.615242 CH0 RK1: MR19=303, MR18=220B
8268 09:25:02.622223 CH0_RK1: MR19=0x303, MR18=0x220B, DQSOSC=392, MR23=63, INC=24, DEC=16
8269 09:25:02.625013 [RxdqsGatingPostProcess] freq 1600
8270 09:25:02.628576 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8271 09:25:02.632180 best DQS0 dly(2T, 0.5T) = (1, 1)
8272 09:25:02.635096 best DQS1 dly(2T, 0.5T) = (1, 1)
8273 09:25:02.638761 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8274 09:25:02.641703 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8275 09:25:02.645197 best DQS0 dly(2T, 0.5T) = (1, 1)
8276 09:25:02.648833 best DQS1 dly(2T, 0.5T) = (1, 1)
8277 09:25:02.651592 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8278 09:25:02.655288 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8279 09:25:02.658178 Pre-setting of DQS Precalculation
8280 09:25:02.661699 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8281 09:25:02.661807 ==
8282 09:25:02.665266 Dram Type= 6, Freq= 0, CH_1, rank 0
8283 09:25:02.671612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 09:25:02.671735 ==
8285 09:25:02.675139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8286 09:25:02.678642 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8287 09:25:02.684882 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8288 09:25:02.691230 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8289 09:25:02.698712 [CA 0] Center 41 (12~71) winsize 60
8290 09:25:02.702304 [CA 1] Center 41 (11~71) winsize 61
8291 09:25:02.705699 [CA 2] Center 39 (10~68) winsize 59
8292 09:25:02.709049 [CA 3] Center 37 (9~66) winsize 58
8293 09:25:02.712535 [CA 4] Center 37 (8~67) winsize 60
8294 09:25:02.715286 [CA 5] Center 36 (7~66) winsize 60
8295 09:25:02.715375
8296 09:25:02.718937 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8297 09:25:02.719011
8298 09:25:02.722415 [CATrainingPosCal] consider 1 rank data
8299 09:25:02.725807 u2DelayCellTimex100 = 285/100 ps
8300 09:25:02.729025 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8301 09:25:02.735974 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8302 09:25:02.739047 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
8303 09:25:02.742218 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8304 09:25:02.745887 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8305 09:25:02.748813 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8306 09:25:02.748893
8307 09:25:02.752382 CA PerBit enable=1, Macro0, CA PI delay=36
8308 09:25:02.752480
8309 09:25:02.755813 [CBTSetCACLKResult] CA Dly = 36
8310 09:25:02.758749 CS Dly: 10 (0~41)
8311 09:25:02.762418 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8312 09:25:02.765367 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8313 09:25:02.765462 ==
8314 09:25:02.773431 Dram Type= 6, Freq= 0, CH_1, rank 1
8315 09:25:02.773695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 09:25:02.773800 ==
8317 09:25:02.779659 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8318 09:25:02.782428 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8319 09:25:02.789046 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8320 09:25:02.792439 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8321 09:25:02.802341 [CA 0] Center 42 (12~72) winsize 61
8322 09:25:02.805722 [CA 1] Center 42 (13~72) winsize 60
8323 09:25:02.809179 [CA 2] Center 38 (9~68) winsize 60
8324 09:25:02.811933 [CA 3] Center 38 (9~68) winsize 60
8325 09:25:02.815239 [CA 4] Center 39 (9~69) winsize 61
8326 09:25:02.818735 [CA 5] Center 37 (8~67) winsize 60
8327 09:25:02.818849
8328 09:25:02.822162 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8329 09:25:02.822272
8330 09:25:02.825785 [CATrainingPosCal] consider 2 rank data
8331 09:25:02.828740 u2DelayCellTimex100 = 285/100 ps
8332 09:25:02.832283 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8333 09:25:02.838593 CA1 delay=42 (13~71),Diff = 5 PI (17 cell)
8334 09:25:02.842238 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8335 09:25:02.845711 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8336 09:25:02.848442 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8337 09:25:02.852412 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8338 09:25:02.852509
8339 09:25:02.855521 CA PerBit enable=1, Macro0, CA PI delay=37
8340 09:25:02.855616
8341 09:25:02.858605 [CBTSetCACLKResult] CA Dly = 37
8342 09:25:02.861765 CS Dly: 12 (0~45)
8343 09:25:02.865077 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8344 09:25:02.868628 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8345 09:25:02.868736
8346 09:25:02.872257 ----->DramcWriteLeveling(PI) begin...
8347 09:25:02.872356 ==
8348 09:25:02.875078 Dram Type= 6, Freq= 0, CH_1, rank 0
8349 09:25:02.882103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 09:25:02.882195 ==
8351 09:25:02.882272 Write leveling (Byte 0): 26 => 26
8352 09:25:02.885070 Write leveling (Byte 1): 28 => 28
8353 09:25:02.888775 DramcWriteLeveling(PI) end<-----
8354 09:25:02.888937
8355 09:25:02.889040 ==
8356 09:25:02.892421 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 09:25:02.898646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 09:25:02.898799 ==
8359 09:25:02.901638 [Gating] SW mode calibration
8360 09:25:02.908550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8361 09:25:02.911863 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8362 09:25:02.918297 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 09:25:02.921823 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 09:25:02.925430 1 4 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
8365 09:25:02.931807 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8366 09:25:02.935546 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 09:25:02.938407 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 09:25:02.941989 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 09:25:02.948276 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 09:25:02.951983 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 09:25:02.954861 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 09:25:02.962030 1 5 8 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
8373 09:25:02.965562 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 1) (1 0)
8374 09:25:02.968169 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 09:25:02.975062 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 09:25:02.978520 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 09:25:02.981623 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 09:25:02.988644 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 09:25:02.992174 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 09:25:02.995832 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8381 09:25:03.002318 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8382 09:25:03.005035 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 09:25:03.008474 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 09:25:03.015305 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 09:25:03.018643 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 09:25:03.021902 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 09:25:03.025027 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 09:25:03.031809 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8389 09:25:03.035309 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8390 09:25:03.038931 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 09:25:03.045203 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 09:25:03.048719 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 09:25:03.052306 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 09:25:03.058836 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 09:25:03.061762 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 09:25:03.065237 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 09:25:03.071696 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 09:25:03.075247 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 09:25:03.078132 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 09:25:03.085026 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 09:25:03.088389 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 09:25:03.091555 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 09:25:03.098419 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 09:25:03.101802 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8405 09:25:03.105241 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8406 09:25:03.108262 Total UI for P1: 0, mck2ui 16
8407 09:25:03.111635 best dqsien dly found for B1: ( 1, 9, 8)
8408 09:25:03.117992 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 09:25:03.118090 Total UI for P1: 0, mck2ui 16
8410 09:25:03.125065 best dqsien dly found for B0: ( 1, 9, 10)
8411 09:25:03.128567 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8412 09:25:03.131302 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8413 09:25:03.131395
8414 09:25:03.134584 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8415 09:25:03.138212 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8416 09:25:03.141565 [Gating] SW calibration Done
8417 09:25:03.141673 ==
8418 09:25:03.145140 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 09:25:03.147965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 09:25:03.148062 ==
8421 09:25:03.151441 RX Vref Scan: 0
8422 09:25:03.151532
8423 09:25:03.151617 RX Vref 0 -> 0, step: 1
8424 09:25:03.151698
8425 09:25:03.154914 RX Delay 0 -> 252, step: 8
8426 09:25:03.158465 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8427 09:25:03.161484 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8428 09:25:03.168205 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8429 09:25:03.171777 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8430 09:25:03.174672 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8431 09:25:03.178269 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8432 09:25:03.181160 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8433 09:25:03.188374 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8434 09:25:03.191246 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8435 09:25:03.194716 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8436 09:25:03.198401 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8437 09:25:03.201134 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8438 09:25:03.207857 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8439 09:25:03.210994 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8440 09:25:03.214736 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8441 09:25:03.217687 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8442 09:25:03.217770 ==
8443 09:25:03.221261 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 09:25:03.228164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 09:25:03.228263 ==
8446 09:25:03.228352 DQS Delay:
8447 09:25:03.231355 DQS0 = 0, DQS1 = 0
8448 09:25:03.231426 DQM Delay:
8449 09:25:03.231497 DQM0 = 136, DQM1 = 132
8450 09:25:03.234567 DQ Delay:
8451 09:25:03.238142 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8452 09:25:03.241081 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8453 09:25:03.244519 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8454 09:25:03.247823 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8455 09:25:03.247943
8456 09:25:03.248041
8457 09:25:03.248125 ==
8458 09:25:03.251059 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 09:25:03.254327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 09:25:03.257678 ==
8461 09:25:03.257796
8462 09:25:03.257868
8463 09:25:03.257958 TX Vref Scan disable
8464 09:25:03.260987 == TX Byte 0 ==
8465 09:25:03.264188 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8466 09:25:03.267693 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8467 09:25:03.271275 == TX Byte 1 ==
8468 09:25:03.274231 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8469 09:25:03.277883 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8470 09:25:03.280785 ==
8471 09:25:03.280878 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 09:25:03.287281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 09:25:03.287395 ==
8474 09:25:03.299473
8475 09:25:03.302421 TX Vref early break, caculate TX vref
8476 09:25:03.305974 TX Vref=16, minBit 9, minWin=22, winSum=377
8477 09:25:03.309662 TX Vref=18, minBit 0, minWin=23, winSum=387
8478 09:25:03.312546 TX Vref=20, minBit 6, minWin=23, winSum=395
8479 09:25:03.316185 TX Vref=22, minBit 0, minWin=24, winSum=404
8480 09:25:03.319766 TX Vref=24, minBit 0, minWin=25, winSum=418
8481 09:25:03.325754 TX Vref=26, minBit 0, minWin=25, winSum=428
8482 09:25:03.329225 TX Vref=28, minBit 0, minWin=25, winSum=424
8483 09:25:03.332653 TX Vref=30, minBit 0, minWin=25, winSum=418
8484 09:25:03.336110 TX Vref=32, minBit 6, minWin=24, winSum=411
8485 09:25:03.338912 TX Vref=34, minBit 0, minWin=23, winSum=399
8486 09:25:03.345722 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 26
8487 09:25:03.345827
8488 09:25:03.349351 Final TX Range 0 Vref 26
8489 09:25:03.349448
8490 09:25:03.349540 ==
8491 09:25:03.352288 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 09:25:03.356037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 09:25:03.356137 ==
8494 09:25:03.356225
8495 09:25:03.356310
8496 09:25:03.359274 TX Vref Scan disable
8497 09:25:03.365804 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8498 09:25:03.365903 == TX Byte 0 ==
8499 09:25:03.368817 u2DelayCellOfst[0]=17 cells (5 PI)
8500 09:25:03.372651 u2DelayCellOfst[1]=10 cells (3 PI)
8501 09:25:03.376155 u2DelayCellOfst[2]=0 cells (0 PI)
8502 09:25:03.379205 u2DelayCellOfst[3]=6 cells (2 PI)
8503 09:25:03.382293 u2DelayCellOfst[4]=10 cells (3 PI)
8504 09:25:03.385478 u2DelayCellOfst[5]=17 cells (5 PI)
8505 09:25:03.388929 u2DelayCellOfst[6]=20 cells (6 PI)
8506 09:25:03.389031 u2DelayCellOfst[7]=6 cells (2 PI)
8507 09:25:03.395473 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8508 09:25:03.399196 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8509 09:25:03.399297 == TX Byte 1 ==
8510 09:25:03.402209 u2DelayCellOfst[8]=0 cells (0 PI)
8511 09:25:03.405699 u2DelayCellOfst[9]=3 cells (1 PI)
8512 09:25:03.409294 u2DelayCellOfst[10]=13 cells (4 PI)
8513 09:25:03.412313 u2DelayCellOfst[11]=6 cells (2 PI)
8514 09:25:03.416071 u2DelayCellOfst[12]=13 cells (4 PI)
8515 09:25:03.418859 u2DelayCellOfst[13]=17 cells (5 PI)
8516 09:25:03.422492 u2DelayCellOfst[14]=17 cells (5 PI)
8517 09:25:03.425431 u2DelayCellOfst[15]=13 cells (4 PI)
8518 09:25:03.428907 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8519 09:25:03.435229 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8520 09:25:03.435327 DramC Write-DBI on
8521 09:25:03.435417 ==
8522 09:25:03.438753 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 09:25:03.442291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 09:25:03.445194 ==
8525 09:25:03.445292
8526 09:25:03.445378
8527 09:25:03.445460 TX Vref Scan disable
8528 09:25:03.448600 == TX Byte 0 ==
8529 09:25:03.452112 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8530 09:25:03.455673 == TX Byte 1 ==
8531 09:25:03.458503 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8532 09:25:03.461780 DramC Write-DBI off
8533 09:25:03.461872
8534 09:25:03.461960 [DATLAT]
8535 09:25:03.462044 Freq=1600, CH1 RK0
8536 09:25:03.462130
8537 09:25:03.465809 DATLAT Default: 0xf
8538 09:25:03.465903 0, 0xFFFF, sum = 0
8539 09:25:03.468597 1, 0xFFFF, sum = 0
8540 09:25:03.468693 2, 0xFFFF, sum = 0
8541 09:25:03.472135 3, 0xFFFF, sum = 0
8542 09:25:03.475775 4, 0xFFFF, sum = 0
8543 09:25:03.475875 5, 0xFFFF, sum = 0
8544 09:25:03.478526 6, 0xFFFF, sum = 0
8545 09:25:03.478622 7, 0xFFFF, sum = 0
8546 09:25:03.481894 8, 0xFFFF, sum = 0
8547 09:25:03.482007 9, 0xFFFF, sum = 0
8548 09:25:03.485056 10, 0xFFFF, sum = 0
8549 09:25:03.485158 11, 0xFFFF, sum = 0
8550 09:25:03.488666 12, 0xFFFF, sum = 0
8551 09:25:03.488747 13, 0xFFFF, sum = 0
8552 09:25:03.491709 14, 0x0, sum = 1
8553 09:25:03.491810 15, 0x0, sum = 2
8554 09:25:03.494950 16, 0x0, sum = 3
8555 09:25:03.495023 17, 0x0, sum = 4
8556 09:25:03.498841 best_step = 15
8557 09:25:03.498939
8558 09:25:03.499035 ==
8559 09:25:03.501969 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 09:25:03.504838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 09:25:03.504964 ==
8562 09:25:03.508200 RX Vref Scan: 1
8563 09:25:03.508322
8564 09:25:03.508433 Set Vref Range= 24 -> 127
8565 09:25:03.508542
8566 09:25:03.511651 RX Vref 24 -> 127, step: 1
8567 09:25:03.511775
8568 09:25:03.515376 RX Delay 27 -> 252, step: 4
8569 09:25:03.515501
8570 09:25:03.518202 Set Vref, RX VrefLevel [Byte0]: 24
8571 09:25:03.521921 [Byte1]: 24
8572 09:25:03.522046
8573 09:25:03.524731 Set Vref, RX VrefLevel [Byte0]: 25
8574 09:25:03.528472 [Byte1]: 25
8575 09:25:03.528566
8576 09:25:03.531474 Set Vref, RX VrefLevel [Byte0]: 26
8577 09:25:03.534988 [Byte1]: 26
8578 09:25:03.539273
8579 09:25:03.539376 Set Vref, RX VrefLevel [Byte0]: 27
8580 09:25:03.542047 [Byte1]: 27
8581 09:25:03.546252
8582 09:25:03.546357 Set Vref, RX VrefLevel [Byte0]: 28
8583 09:25:03.549784 [Byte1]: 28
8584 09:25:03.554145
8585 09:25:03.554225 Set Vref, RX VrefLevel [Byte0]: 29
8586 09:25:03.556974 [Byte1]: 29
8587 09:25:03.561455
8588 09:25:03.561568 Set Vref, RX VrefLevel [Byte0]: 30
8589 09:25:03.565004 [Byte1]: 30
8590 09:25:03.569315
8591 09:25:03.569394 Set Vref, RX VrefLevel [Byte0]: 31
8592 09:25:03.572694 [Byte1]: 31
8593 09:25:03.576847
8594 09:25:03.576925 Set Vref, RX VrefLevel [Byte0]: 32
8595 09:25:03.579772 [Byte1]: 32
8596 09:25:03.583942
8597 09:25:03.584036 Set Vref, RX VrefLevel [Byte0]: 33
8598 09:25:03.587636 [Byte1]: 33
8599 09:25:03.592009
8600 09:25:03.592089 Set Vref, RX VrefLevel [Byte0]: 34
8601 09:25:03.594663 [Byte1]: 34
8602 09:25:03.599358
8603 09:25:03.599444 Set Vref, RX VrefLevel [Byte0]: 35
8604 09:25:03.602637 [Byte1]: 35
8605 09:25:03.606636
8606 09:25:03.606716 Set Vref, RX VrefLevel [Byte0]: 36
8607 09:25:03.610001 [Byte1]: 36
8608 09:25:03.613999
8609 09:25:03.614078 Set Vref, RX VrefLevel [Byte0]: 37
8610 09:25:03.617966 [Byte1]: 37
8611 09:25:03.621816
8612 09:25:03.621895 Set Vref, RX VrefLevel [Byte0]: 38
8613 09:25:03.624861 [Byte1]: 38
8614 09:25:03.629101
8615 09:25:03.629179 Set Vref, RX VrefLevel [Byte0]: 39
8616 09:25:03.632519 [Byte1]: 39
8617 09:25:03.636710
8618 09:25:03.636805 Set Vref, RX VrefLevel [Byte0]: 40
8619 09:25:03.640207 [Byte1]: 40
8620 09:25:03.644464
8621 09:25:03.644541 Set Vref, RX VrefLevel [Byte0]: 41
8622 09:25:03.648193 [Byte1]: 41
8623 09:25:03.651807
8624 09:25:03.651882 Set Vref, RX VrefLevel [Byte0]: 42
8625 09:25:03.655531 [Byte1]: 42
8626 09:25:03.659785
8627 09:25:03.659860 Set Vref, RX VrefLevel [Byte0]: 43
8628 09:25:03.662488 [Byte1]: 43
8629 09:25:03.666708
8630 09:25:03.666811 Set Vref, RX VrefLevel [Byte0]: 44
8631 09:25:03.670285 [Byte1]: 44
8632 09:25:03.674766
8633 09:25:03.674842 Set Vref, RX VrefLevel [Byte0]: 45
8634 09:25:03.677615 [Byte1]: 45
8635 09:25:03.682282
8636 09:25:03.682359 Set Vref, RX VrefLevel [Byte0]: 46
8637 09:25:03.685167 [Byte1]: 46
8638 09:25:03.689342
8639 09:25:03.689420 Set Vref, RX VrefLevel [Byte0]: 47
8640 09:25:03.692953 [Byte1]: 47
8641 09:25:03.697414
8642 09:25:03.697517 Set Vref, RX VrefLevel [Byte0]: 48
8643 09:25:03.700400 [Byte1]: 48
8644 09:25:03.704671
8645 09:25:03.704786 Set Vref, RX VrefLevel [Byte0]: 49
8646 09:25:03.708258 [Byte1]: 49
8647 09:25:03.712367
8648 09:25:03.712444 Set Vref, RX VrefLevel [Byte0]: 50
8649 09:25:03.715799 [Byte1]: 50
8650 09:25:03.719421
8651 09:25:03.719518 Set Vref, RX VrefLevel [Byte0]: 51
8652 09:25:03.722828 [Byte1]: 51
8653 09:25:03.727051
8654 09:25:03.727146 Set Vref, RX VrefLevel [Byte0]: 52
8655 09:25:03.730686 [Byte1]: 52
8656 09:25:03.734683
8657 09:25:03.734782 Set Vref, RX VrefLevel [Byte0]: 53
8658 09:25:03.738134 [Byte1]: 53
8659 09:25:03.742081
8660 09:25:03.742176 Set Vref, RX VrefLevel [Byte0]: 54
8661 09:25:03.745728 [Byte1]: 54
8662 09:25:03.749947
8663 09:25:03.750025 Set Vref, RX VrefLevel [Byte0]: 55
8664 09:25:03.753345 [Byte1]: 55
8665 09:25:03.757470
8666 09:25:03.757571 Set Vref, RX VrefLevel [Byte0]: 56
8667 09:25:03.760397 [Byte1]: 56
8668 09:25:03.765370
8669 09:25:03.765452 Set Vref, RX VrefLevel [Byte0]: 57
8670 09:25:03.768023 [Byte1]: 57
8671 09:25:03.772251
8672 09:25:03.772324 Set Vref, RX VrefLevel [Byte0]: 58
8673 09:25:03.775910 [Byte1]: 58
8674 09:25:03.780255
8675 09:25:03.780335 Set Vref, RX VrefLevel [Byte0]: 59
8676 09:25:03.783121 [Byte1]: 59
8677 09:25:03.787835
8678 09:25:03.787917 Set Vref, RX VrefLevel [Byte0]: 60
8679 09:25:03.790448 [Byte1]: 60
8680 09:25:03.794779
8681 09:25:03.794849 Set Vref, RX VrefLevel [Byte0]: 61
8682 09:25:03.798327 [Byte1]: 61
8683 09:25:03.802676
8684 09:25:03.802745 Set Vref, RX VrefLevel [Byte0]: 62
8685 09:25:03.805479 [Byte1]: 62
8686 09:25:03.809877
8687 09:25:03.809957 Set Vref, RX VrefLevel [Byte0]: 63
8688 09:25:03.813386 [Byte1]: 63
8689 09:25:03.817613
8690 09:25:03.817698 Set Vref, RX VrefLevel [Byte0]: 64
8691 09:25:03.821104 [Byte1]: 64
8692 09:25:03.825041
8693 09:25:03.825129 Set Vref, RX VrefLevel [Byte0]: 65
8694 09:25:03.828620 [Byte1]: 65
8695 09:25:03.832877
8696 09:25:03.832958 Set Vref, RX VrefLevel [Byte0]: 66
8697 09:25:03.835645 [Byte1]: 66
8698 09:25:03.840035
8699 09:25:03.840128 Set Vref, RX VrefLevel [Byte0]: 67
8700 09:25:03.843724 [Byte1]: 67
8701 09:25:03.847945
8702 09:25:03.848028 Set Vref, RX VrefLevel [Byte0]: 68
8703 09:25:03.850817 [Byte1]: 68
8704 09:25:03.855255
8705 09:25:03.855326 Set Vref, RX VrefLevel [Byte0]: 69
8706 09:25:03.858694 [Byte1]: 69
8707 09:25:03.862586
8708 09:25:03.862654 Set Vref, RX VrefLevel [Byte0]: 70
8709 09:25:03.866453 [Byte1]: 70
8710 09:25:03.870454
8711 09:25:03.870528 Set Vref, RX VrefLevel [Byte0]: 71
8712 09:25:03.873896 [Byte1]: 71
8713 09:25:03.877956
8714 09:25:03.878034 Set Vref, RX VrefLevel [Byte0]: 72
8715 09:25:03.881321 [Byte1]: 72
8716 09:25:03.885482
8717 09:25:03.885604 Set Vref, RX VrefLevel [Byte0]: 73
8718 09:25:03.888445 [Byte1]: 73
8719 09:25:03.892642
8720 09:25:03.892727 Set Vref, RX VrefLevel [Byte0]: 74
8721 09:25:03.896631 [Byte1]: 74
8722 09:25:03.900227
8723 09:25:03.900303 Set Vref, RX VrefLevel [Byte0]: 75
8724 09:25:03.903482 [Byte1]: 75
8725 09:25:03.908304
8726 09:25:03.908391 Set Vref, RX VrefLevel [Byte0]: 76
8727 09:25:03.911233 [Byte1]: 76
8728 09:25:03.915470
8729 09:25:03.915572 Set Vref, RX VrefLevel [Byte0]: 77
8730 09:25:03.919040 [Byte1]: 77
8731 09:25:03.922940
8732 09:25:03.923044 Final RX Vref Byte 0 = 61 to rank0
8733 09:25:03.926308 Final RX Vref Byte 1 = 55 to rank0
8734 09:25:03.929696 Final RX Vref Byte 0 = 61 to rank1
8735 09:25:03.933177 Final RX Vref Byte 1 = 55 to rank1==
8736 09:25:03.936678 Dram Type= 6, Freq= 0, CH_1, rank 0
8737 09:25:03.943177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 09:25:03.943256 ==
8739 09:25:03.943316 DQS Delay:
8740 09:25:03.943371 DQS0 = 0, DQS1 = 0
8741 09:25:03.946752 DQM Delay:
8742 09:25:03.946829 DQM0 = 134, DQM1 = 131
8743 09:25:03.949478 DQ Delay:
8744 09:25:03.953225 DQ0 =140, DQ1 =128, DQ2 =120, DQ3 =130
8745 09:25:03.956242 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8746 09:25:03.959905 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8747 09:25:03.963132 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8748 09:25:03.963259
8749 09:25:03.963344
8750 09:25:03.963426
8751 09:25:03.966133 [DramC_TX_OE_Calibration] TA2
8752 09:25:03.970063 Original DQ_B0 (3 6) =30, OEN = 27
8753 09:25:03.973128 Original DQ_B1 (3 6) =30, OEN = 27
8754 09:25:03.976786 24, 0x0, End_B0=24 End_B1=24
8755 09:25:03.976888 25, 0x0, End_B0=25 End_B1=25
8756 09:25:03.979863 26, 0x0, End_B0=26 End_B1=26
8757 09:25:03.982775 27, 0x0, End_B0=27 End_B1=27
8758 09:25:03.986252 28, 0x0, End_B0=28 End_B1=28
8759 09:25:03.986339 29, 0x0, End_B0=29 End_B1=29
8760 09:25:03.989493 30, 0x0, End_B0=30 End_B1=30
8761 09:25:03.993134 31, 0x4141, End_B0=30 End_B1=30
8762 09:25:03.996313 Byte0 end_step=30 best_step=27
8763 09:25:03.999969 Byte1 end_step=30 best_step=27
8764 09:25:04.002824 Byte0 TX OE(2T, 0.5T) = (3, 3)
8765 09:25:04.002901 Byte1 TX OE(2T, 0.5T) = (3, 3)
8766 09:25:04.002961
8767 09:25:04.006586
8768 09:25:04.012877 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b29, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8769 09:25:04.016139 CH1 RK0: MR19=303, MR18=1B29
8770 09:25:04.023139 CH1_RK0: MR19=0x303, MR18=0x1B29, DQSOSC=389, MR23=63, INC=24, DEC=16
8771 09:25:04.023221
8772 09:25:04.026370 ----->DramcWriteLeveling(PI) begin...
8773 09:25:04.026449 ==
8774 09:25:04.029717 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 09:25:04.032991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 09:25:04.033088 ==
8777 09:25:04.036398 Write leveling (Byte 0): 25 => 25
8778 09:25:04.039650 Write leveling (Byte 1): 29 => 29
8779 09:25:04.042935 DramcWriteLeveling(PI) end<-----
8780 09:25:04.043015
8781 09:25:04.043075 ==
8782 09:25:04.046612 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 09:25:04.049384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 09:25:04.049486 ==
8785 09:25:04.053181 [Gating] SW mode calibration
8786 09:25:04.059772 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8787 09:25:04.066623 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8788 09:25:04.069955 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 09:25:04.073001 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 09:25:04.079795 1 4 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8791 09:25:04.082768 1 4 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 0)
8792 09:25:04.085847 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 09:25:04.092685 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 09:25:04.095620 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 09:25:04.099477 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 09:25:04.106300 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 09:25:04.109087 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 09:25:04.113001 1 5 8 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 0)
8799 09:25:04.119419 1 5 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8800 09:25:04.122242 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8801 09:25:04.125780 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 09:25:04.132158 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 09:25:04.135700 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 09:25:04.139490 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 09:25:04.145601 1 6 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
8806 09:25:04.149015 1 6 8 | B1->B0 | 3f3f 2323 | 0 0 | (0 0) (0 0)
8807 09:25:04.152381 1 6 12 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
8808 09:25:04.158933 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 09:25:04.162463 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 09:25:04.165481 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 09:25:04.168978 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 09:25:04.176135 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 09:25:04.179019 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 09:25:04.182598 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8815 09:25:04.189027 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8816 09:25:04.192628 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 09:25:04.195484 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 09:25:04.202479 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 09:25:04.206004 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 09:25:04.208983 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 09:25:04.215532 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 09:25:04.219065 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 09:25:04.222527 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 09:25:04.229045 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 09:25:04.232717 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 09:25:04.235700 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 09:25:04.242091 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 09:25:04.245646 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 09:25:04.249258 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8830 09:25:04.255741 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8831 09:25:04.259386 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8832 09:25:04.262079 Total UI for P1: 0, mck2ui 16
8833 09:25:04.265394 best dqsien dly found for B1: ( 1, 9, 6)
8834 09:25:04.268738 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 09:25:04.272251 Total UI for P1: 0, mck2ui 16
8836 09:25:04.275425 best dqsien dly found for B0: ( 1, 9, 12)
8837 09:25:04.279140 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8838 09:25:04.282197 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8839 09:25:04.282283
8840 09:25:04.285279 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8841 09:25:04.292246 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8842 09:25:04.292352 [Gating] SW calibration Done
8843 09:25:04.292442 ==
8844 09:25:04.295684 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 09:25:04.302001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 09:25:04.302084 ==
8847 09:25:04.302148 RX Vref Scan: 0
8848 09:25:04.302204
8849 09:25:04.305390 RX Vref 0 -> 0, step: 1
8850 09:25:04.305494
8851 09:25:04.308940 RX Delay 0 -> 252, step: 8
8852 09:25:04.312031 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8853 09:25:04.315387 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8854 09:25:04.318853 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8855 09:25:04.321735 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8856 09:25:04.329043 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8857 09:25:04.331841 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8858 09:25:04.335518 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8859 09:25:04.339062 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8860 09:25:04.341985 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8861 09:25:04.349018 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8862 09:25:04.351801 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8863 09:25:04.355444 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8864 09:25:04.358287 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8865 09:25:04.364760 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8866 09:25:04.368418 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8867 09:25:04.372048 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8868 09:25:04.372126 ==
8869 09:25:04.375066 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 09:25:04.378701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 09:25:04.378803 ==
8872 09:25:04.381516 DQS Delay:
8873 09:25:04.381596 DQS0 = 0, DQS1 = 0
8874 09:25:04.385312 DQM Delay:
8875 09:25:04.385389 DQM0 = 136, DQM1 = 133
8876 09:25:04.385449 DQ Delay:
8877 09:25:04.388174 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8878 09:25:04.394793 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8879 09:25:04.398414 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8880 09:25:04.401871 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8881 09:25:04.401949
8882 09:25:04.402010
8883 09:25:04.402066 ==
8884 09:25:04.405191 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 09:25:04.408301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 09:25:04.408379 ==
8887 09:25:04.408440
8888 09:25:04.408495
8889 09:25:04.411818 TX Vref Scan disable
8890 09:25:04.415262 == TX Byte 0 ==
8891 09:25:04.418042 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8892 09:25:04.421376 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8893 09:25:04.424649 == TX Byte 1 ==
8894 09:25:04.428076 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8895 09:25:04.431214 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8896 09:25:04.431317 ==
8897 09:25:04.434916 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 09:25:04.437944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 09:25:04.441598 ==
8900 09:25:04.452589
8901 09:25:04.456048 TX Vref early break, caculate TX vref
8902 09:25:04.459410 TX Vref=16, minBit 0, minWin=23, winSum=383
8903 09:25:04.462221 TX Vref=18, minBit 0, minWin=23, winSum=391
8904 09:25:04.465758 TX Vref=20, minBit 0, minWin=24, winSum=401
8905 09:25:04.468821 TX Vref=22, minBit 0, minWin=25, winSum=413
8906 09:25:04.472548 TX Vref=24, minBit 2, minWin=25, winSum=417
8907 09:25:04.479079 TX Vref=26, minBit 0, minWin=25, winSum=425
8908 09:25:04.482202 TX Vref=28, minBit 6, minWin=25, winSum=429
8909 09:25:04.485824 TX Vref=30, minBit 6, minWin=25, winSum=418
8910 09:25:04.488824 TX Vref=32, minBit 0, minWin=24, winSum=409
8911 09:25:04.492579 TX Vref=34, minBit 0, minWin=24, winSum=403
8912 09:25:04.499218 [TxChooseVref] Worse bit 6, Min win 25, Win sum 429, Final Vref 28
8913 09:25:04.499289
8914 09:25:04.502746 Final TX Range 0 Vref 28
8915 09:25:04.502819
8916 09:25:04.502887 ==
8917 09:25:04.505595 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 09:25:04.509252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 09:25:04.509322 ==
8920 09:25:04.509379
8921 09:25:04.509443
8922 09:25:04.512724 TX Vref Scan disable
8923 09:25:04.518757 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8924 09:25:04.518832 == TX Byte 0 ==
8925 09:25:04.522614 u2DelayCellOfst[0]=17 cells (5 PI)
8926 09:25:04.525400 u2DelayCellOfst[1]=10 cells (3 PI)
8927 09:25:04.528626 u2DelayCellOfst[2]=0 cells (0 PI)
8928 09:25:04.532235 u2DelayCellOfst[3]=6 cells (2 PI)
8929 09:25:04.535885 u2DelayCellOfst[4]=10 cells (3 PI)
8930 09:25:04.538702 u2DelayCellOfst[5]=17 cells (5 PI)
8931 09:25:04.542172 u2DelayCellOfst[6]=17 cells (5 PI)
8932 09:25:04.542242 u2DelayCellOfst[7]=6 cells (2 PI)
8933 09:25:04.548625 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8934 09:25:04.552244 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8935 09:25:04.552347 == TX Byte 1 ==
8936 09:25:04.555672 u2DelayCellOfst[8]=0 cells (0 PI)
8937 09:25:04.559041 u2DelayCellOfst[9]=3 cells (1 PI)
8938 09:25:04.562141 u2DelayCellOfst[10]=10 cells (3 PI)
8939 09:25:04.565224 u2DelayCellOfst[11]=3 cells (1 PI)
8940 09:25:04.569151 u2DelayCellOfst[12]=13 cells (4 PI)
8941 09:25:04.572221 u2DelayCellOfst[13]=17 cells (5 PI)
8942 09:25:04.575410 u2DelayCellOfst[14]=17 cells (5 PI)
8943 09:25:04.578987 u2DelayCellOfst[15]=17 cells (5 PI)
8944 09:25:04.581851 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8945 09:25:04.588486 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8946 09:25:04.588566 DramC Write-DBI on
8947 09:25:04.588626 ==
8948 09:25:04.592059 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 09:25:04.595382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 09:25:04.595485 ==
8951 09:25:04.598979
8952 09:25:04.599076
8953 09:25:04.599163 TX Vref Scan disable
8954 09:25:04.601762 == TX Byte 0 ==
8955 09:25:04.605598 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8956 09:25:04.608469 == TX Byte 1 ==
8957 09:25:04.612012 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8958 09:25:04.615576 DramC Write-DBI off
8959 09:25:04.615666
8960 09:25:04.615748 [DATLAT]
8961 09:25:04.615832 Freq=1600, CH1 RK1
8962 09:25:04.615912
8963 09:25:04.618475 DATLAT Default: 0xf
8964 09:25:04.618539 0, 0xFFFF, sum = 0
8965 09:25:04.622140 1, 0xFFFF, sum = 0
8966 09:25:04.622218 2, 0xFFFF, sum = 0
8967 09:25:04.624946 3, 0xFFFF, sum = 0
8968 09:25:04.628377 4, 0xFFFF, sum = 0
8969 09:25:04.628468 5, 0xFFFF, sum = 0
8970 09:25:04.631677 6, 0xFFFF, sum = 0
8971 09:25:04.631742 7, 0xFFFF, sum = 0
8972 09:25:04.635166 8, 0xFFFF, sum = 0
8973 09:25:04.635279 9, 0xFFFF, sum = 0
8974 09:25:04.638776 10, 0xFFFF, sum = 0
8975 09:25:04.638926 11, 0xFFFF, sum = 0
8976 09:25:04.642110 12, 0xFFFF, sum = 0
8977 09:25:04.642212 13, 0xFFFF, sum = 0
8978 09:25:04.644893 14, 0x0, sum = 1
8979 09:25:04.644993 15, 0x0, sum = 2
8980 09:25:04.648506 16, 0x0, sum = 3
8981 09:25:04.648625 17, 0x0, sum = 4
8982 09:25:04.651366 best_step = 15
8983 09:25:04.651466
8984 09:25:04.651553 ==
8985 09:25:04.654956 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 09:25:04.658670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 09:25:04.658748 ==
8988 09:25:04.661561 RX Vref Scan: 0
8989 09:25:04.661651
8990 09:25:04.661811 RX Vref 0 -> 0, step: 1
8991 09:25:04.661912
8992 09:25:04.665097 RX Delay 19 -> 252, step: 4
8993 09:25:04.668063 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8994 09:25:04.675002 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8995 09:25:04.678534 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8996 09:25:04.681377 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8997 09:25:04.684989 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8998 09:25:04.687852 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8999 09:25:04.691302 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9000 09:25:04.697930 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9001 09:25:04.701724 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9002 09:25:04.704844 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
9003 09:25:04.708480 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9004 09:25:04.711491 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9005 09:25:04.718509 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9006 09:25:04.721945 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
9007 09:25:04.724935 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9008 09:25:04.728591 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9009 09:25:04.728669 ==
9010 09:25:04.731590 Dram Type= 6, Freq= 0, CH_1, rank 1
9011 09:25:04.738291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9012 09:25:04.738390 ==
9013 09:25:04.738477 DQS Delay:
9014 09:25:04.741931 DQS0 = 0, DQS1 = 0
9015 09:25:04.742033 DQM Delay:
9016 09:25:04.742120 DQM0 = 134, DQM1 = 130
9017 09:25:04.744942 DQ Delay:
9018 09:25:04.748491 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
9019 09:25:04.751358 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9020 09:25:04.754788 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
9021 09:25:04.758249 DQ12 =140, DQ13 =136, DQ14 =136, DQ15 =138
9022 09:25:04.758328
9023 09:25:04.758387
9024 09:25:04.758442
9025 09:25:04.761104 [DramC_TX_OE_Calibration] TA2
9026 09:25:04.764968 Original DQ_B0 (3 6) =30, OEN = 27
9027 09:25:04.768527 Original DQ_B1 (3 6) =30, OEN = 27
9028 09:25:04.771493 24, 0x0, End_B0=24 End_B1=24
9029 09:25:04.771573 25, 0x0, End_B0=25 End_B1=25
9030 09:25:04.774322 26, 0x0, End_B0=26 End_B1=26
9031 09:25:04.777959 27, 0x0, End_B0=27 End_B1=27
9032 09:25:04.780968 28, 0x0, End_B0=28 End_B1=28
9033 09:25:04.784580 29, 0x0, End_B0=29 End_B1=29
9034 09:25:04.784660 30, 0x0, End_B0=30 End_B1=30
9035 09:25:04.788058 31, 0x5151, End_B0=30 End_B1=30
9036 09:25:04.791062 Byte0 end_step=30 best_step=27
9037 09:25:04.794782 Byte1 end_step=30 best_step=27
9038 09:25:04.797765 Byte0 TX OE(2T, 0.5T) = (3, 3)
9039 09:25:04.801445 Byte1 TX OE(2T, 0.5T) = (3, 3)
9040 09:25:04.801553
9041 09:25:04.801618
9042 09:25:04.807971 [DQSOSCAuto] RK1, (LSB)MR18= 0x2309, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9043 09:25:04.810787 CH1 RK1: MR19=303, MR18=2309
9044 09:25:04.817916 CH1_RK1: MR19=0x303, MR18=0x2309, DQSOSC=392, MR23=63, INC=24, DEC=16
9045 09:25:04.821316 [RxdqsGatingPostProcess] freq 1600
9046 09:25:04.824016 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9047 09:25:04.827914 best DQS0 dly(2T, 0.5T) = (1, 1)
9048 09:25:04.831019 best DQS1 dly(2T, 0.5T) = (1, 1)
9049 09:25:04.834111 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9050 09:25:04.837817 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9051 09:25:04.840790 best DQS0 dly(2T, 0.5T) = (1, 1)
9052 09:25:04.844378 best DQS1 dly(2T, 0.5T) = (1, 1)
9053 09:25:04.847839 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9054 09:25:04.850800 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9055 09:25:04.854173 Pre-setting of DQS Precalculation
9056 09:25:04.857540 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9057 09:25:04.864588 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9058 09:25:04.874192 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9059 09:25:04.874297
9060 09:25:04.874375
9061 09:25:04.874454 [Calibration Summary] 3200 Mbps
9062 09:25:04.877808 CH 0, Rank 0
9063 09:25:04.877877 SW Impedance : PASS
9064 09:25:04.880749 DUTY Scan : NO K
9065 09:25:04.884453 ZQ Calibration : PASS
9066 09:25:04.884552 Jitter Meter : NO K
9067 09:25:04.888023 CBT Training : PASS
9068 09:25:04.890965 Write leveling : PASS
9069 09:25:04.891069 RX DQS gating : PASS
9070 09:25:04.894038 RX DQ/DQS(RDDQC) : PASS
9071 09:25:04.897924 TX DQ/DQS : PASS
9072 09:25:04.898027 RX DATLAT : PASS
9073 09:25:04.900891 RX DQ/DQS(Engine): PASS
9074 09:25:04.903902 TX OE : PASS
9075 09:25:04.903992 All Pass.
9076 09:25:04.904077
9077 09:25:04.904162 CH 0, Rank 1
9078 09:25:04.907657 SW Impedance : PASS
9079 09:25:04.910614 DUTY Scan : NO K
9080 09:25:04.910718 ZQ Calibration : PASS
9081 09:25:04.914328 Jitter Meter : NO K
9082 09:25:04.917244 CBT Training : PASS
9083 09:25:04.917340 Write leveling : PASS
9084 09:25:04.921020 RX DQS gating : PASS
9085 09:25:04.924107 RX DQ/DQS(RDDQC) : PASS
9086 09:25:04.924211 TX DQ/DQS : PASS
9087 09:25:04.927150 RX DATLAT : PASS
9088 09:25:04.930835 RX DQ/DQS(Engine): PASS
9089 09:25:04.930939 TX OE : PASS
9090 09:25:04.931035 All Pass.
9091 09:25:04.933845
9092 09:25:04.933953 CH 1, Rank 0
9093 09:25:04.937408 SW Impedance : PASS
9094 09:25:04.937511 DUTY Scan : NO K
9095 09:25:04.940368 ZQ Calibration : PASS
9096 09:25:04.940466 Jitter Meter : NO K
9097 09:25:04.944158 CBT Training : PASS
9098 09:25:04.947001 Write leveling : PASS
9099 09:25:04.947098 RX DQS gating : PASS
9100 09:25:04.950473 RX DQ/DQS(RDDQC) : PASS
9101 09:25:04.953938 TX DQ/DQS : PASS
9102 09:25:04.954033 RX DATLAT : PASS
9103 09:25:04.957542 RX DQ/DQS(Engine): PASS
9104 09:25:04.960377 TX OE : PASS
9105 09:25:04.960471 All Pass.
9106 09:25:04.960556
9107 09:25:04.960642 CH 1, Rank 1
9108 09:25:04.963616 SW Impedance : PASS
9109 09:25:04.967059 DUTY Scan : NO K
9110 09:25:04.967158 ZQ Calibration : PASS
9111 09:25:04.970368 Jitter Meter : NO K
9112 09:25:04.974127 CBT Training : PASS
9113 09:25:04.974222 Write leveling : PASS
9114 09:25:04.977116 RX DQS gating : PASS
9115 09:25:04.977195 RX DQ/DQS(RDDQC) : PASS
9116 09:25:04.980516 TX DQ/DQS : PASS
9117 09:25:04.983639 RX DATLAT : PASS
9118 09:25:04.983738 RX DQ/DQS(Engine): PASS
9119 09:25:04.986977 TX OE : PASS
9120 09:25:04.987076 All Pass.
9121 09:25:04.987164
9122 09:25:04.990588 DramC Write-DBI on
9123 09:25:04.993703 PER_BANK_REFRESH: Hybrid Mode
9124 09:25:04.993779 TX_TRACKING: ON
9125 09:25:05.004235 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9126 09:25:05.010252 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9127 09:25:05.016940 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9128 09:25:05.023472 [FAST_K] Save calibration result to emmc
9129 09:25:05.023574 sync common calibartion params.
9130 09:25:05.027092 sync cbt_mode0:1, 1:1
9131 09:25:05.030071 dram_init: ddr_geometry: 2
9132 09:25:05.030149 dram_init: ddr_geometry: 2
9133 09:25:05.033842 dram_init: ddr_geometry: 2
9134 09:25:05.036909 0:dram_rank_size:100000000
9135 09:25:05.040439 1:dram_rank_size:100000000
9136 09:25:05.044102 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9137 09:25:05.047138 DFS_SHUFFLE_HW_MODE: ON
9138 09:25:05.050027 dramc_set_vcore_voltage set vcore to 725000
9139 09:25:05.053667 Read voltage for 1600, 0
9140 09:25:05.053765 Vio18 = 0
9141 09:25:05.056637 Vcore = 725000
9142 09:25:05.056731 Vdram = 0
9143 09:25:05.056816 Vddq = 0
9144 09:25:05.056898 Vmddr = 0
9145 09:25:05.060262 switch to 3200 Mbps bootup
9146 09:25:05.063300 [DramcRunTimeConfig]
9147 09:25:05.063393 PHYPLL
9148 09:25:05.066886 DPM_CONTROL_AFTERK: ON
9149 09:25:05.066964 PER_BANK_REFRESH: ON
9150 09:25:05.070487 REFRESH_OVERHEAD_REDUCTION: ON
9151 09:25:05.073431 CMD_PICG_NEW_MODE: OFF
9152 09:25:05.073531 XRTWTW_NEW_MODE: ON
9153 09:25:05.077114 XRTRTR_NEW_MODE: ON
9154 09:25:05.077216 TX_TRACKING: ON
9155 09:25:05.080129 RDSEL_TRACKING: OFF
9156 09:25:05.080225 DQS Precalculation for DVFS: ON
9157 09:25:05.083199 RX_TRACKING: OFF
9158 09:25:05.083279 HW_GATING DBG: ON
9159 09:25:05.086803 ZQCS_ENABLE_LP4: ON
9160 09:25:05.090376 RX_PICG_NEW_MODE: ON
9161 09:25:05.090454 TX_PICG_NEW_MODE: ON
9162 09:25:05.093825 ENABLE_RX_DCM_DPHY: ON
9163 09:25:05.097018 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9164 09:25:05.097096 DUMMY_READ_FOR_TRACKING: OFF
9165 09:25:05.100002 !!! SPM_CONTROL_AFTERK: OFF
9166 09:25:05.103167 !!! SPM could not control APHY
9167 09:25:05.106963 IMPEDANCE_TRACKING: ON
9168 09:25:05.107042 TEMP_SENSOR: ON
9169 09:25:05.109899 HW_SAVE_FOR_SR: OFF
9170 09:25:05.109977 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9171 09:25:05.116771 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9172 09:25:05.116850 Read ODT Tracking: ON
9173 09:25:05.120245 Refresh Rate DeBounce: ON
9174 09:25:05.122938 DFS_NO_QUEUE_FLUSH: ON
9175 09:25:05.126479 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9176 09:25:05.126559 ENABLE_DFS_RUNTIME_MRW: OFF
9177 09:25:05.129750 DDR_RESERVE_NEW_MODE: ON
9178 09:25:05.133419 MR_CBT_SWITCH_FREQ: ON
9179 09:25:05.133497 =========================
9180 09:25:05.153133 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9181 09:25:05.155939 dram_init: ddr_geometry: 2
9182 09:25:05.174786 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9183 09:25:05.177596 dram_init: dram init end (result: 0)
9184 09:25:05.184771 DRAM-K: Full calibration passed in 24479 msecs
9185 09:25:05.187655 MRC: failed to locate region type 0.
9186 09:25:05.187726 DRAM rank0 size:0x100000000,
9187 09:25:05.191289 DRAM rank1 size=0x100000000
9188 09:25:05.200788 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9189 09:25:05.207929 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9190 09:25:05.214468 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9191 09:25:05.220750 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9192 09:25:05.224258 DRAM rank0 size:0x100000000,
9193 09:25:05.227786 DRAM rank1 size=0x100000000
9194 09:25:05.227857 CBMEM:
9195 09:25:05.230861 IMD: root @ 0xfffff000 254 entries.
9196 09:25:05.234686 IMD: root @ 0xffffec00 62 entries.
9197 09:25:05.237808 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9198 09:25:05.240993 WARNING: RO_VPD is uninitialized or empty.
9199 09:25:05.247672 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9200 09:25:05.254358 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9201 09:25:05.267079 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
9202 09:25:05.279031 BS: romstage times (exec / console): total (unknown) / 24007 ms
9203 09:25:05.279127
9204 09:25:05.279190
9205 09:25:05.288410 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9206 09:25:05.292122 ARM64: Exception handlers installed.
9207 09:25:05.295041 ARM64: Testing exception
9208 09:25:05.298622 ARM64: Done test exception
9209 09:25:05.298693 Enumerating buses...
9210 09:25:05.302390 Show all devs... Before device enumeration.
9211 09:25:05.305204 Root Device: enabled 1
9212 09:25:05.308971 CPU_CLUSTER: 0: enabled 1
9213 09:25:05.309056 CPU: 00: enabled 1
9214 09:25:05.312005 Compare with tree...
9215 09:25:05.312095 Root Device: enabled 1
9216 09:25:05.315533 CPU_CLUSTER: 0: enabled 1
9217 09:25:05.318488 CPU: 00: enabled 1
9218 09:25:05.318563 Root Device scanning...
9219 09:25:05.321993 scan_static_bus for Root Device
9220 09:25:05.325441 CPU_CLUSTER: 0 enabled
9221 09:25:05.328403 scan_static_bus for Root Device done
9222 09:25:05.331907 scan_bus: bus Root Device finished in 8 msecs
9223 09:25:05.332138 done
9224 09:25:05.338486 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9225 09:25:05.342039 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9226 09:25:05.348490 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9227 09:25:05.351491 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9228 09:25:05.354976 Allocating resources...
9229 09:25:05.358631 Reading resources...
9230 09:25:05.361428 Root Device read_resources bus 0 link: 0
9231 09:25:05.361542 DRAM rank0 size:0x100000000,
9232 09:25:05.364968 DRAM rank1 size=0x100000000
9233 09:25:05.368381 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9234 09:25:05.371190 CPU: 00 missing read_resources
9235 09:25:05.377865 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9236 09:25:05.381380 Root Device read_resources bus 0 link: 0 done
9237 09:25:05.381473 Done reading resources.
9238 09:25:05.387791 Show resources in subtree (Root Device)...After reading.
9239 09:25:05.391749 Root Device child on link 0 CPU_CLUSTER: 0
9240 09:25:05.394712 CPU_CLUSTER: 0 child on link 0 CPU: 00
9241 09:25:05.404416 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9242 09:25:05.404528 CPU: 00
9243 09:25:05.407745 Root Device assign_resources, bus 0 link: 0
9244 09:25:05.411464 CPU_CLUSTER: 0 missing set_resources
9245 09:25:05.418258 Root Device assign_resources, bus 0 link: 0 done
9246 09:25:05.418333 Done setting resources.
9247 09:25:05.424772 Show resources in subtree (Root Device)...After assigning values.
9248 09:25:05.428407 Root Device child on link 0 CPU_CLUSTER: 0
9249 09:25:05.431293 CPU_CLUSTER: 0 child on link 0 CPU: 00
9250 09:25:05.441436 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9251 09:25:05.441516 CPU: 00
9252 09:25:05.445057 Done allocating resources.
9253 09:25:05.448023 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9254 09:25:05.451693 Enabling resources...
9255 09:25:05.451769 done.
9256 09:25:05.458317 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9257 09:25:05.458394 Initializing devices...
9258 09:25:05.461189 Root Device init
9259 09:25:05.461283 init hardware done!
9260 09:25:05.464860 0x00000018: ctrlr->caps
9261 09:25:05.467812 52.000 MHz: ctrlr->f_max
9262 09:25:05.467895 0.400 MHz: ctrlr->f_min
9263 09:25:05.471426 0x40ff8080: ctrlr->voltages
9264 09:25:05.471504 sclk: 390625
9265 09:25:05.475067 Bus Width = 1
9266 09:25:05.475134 sclk: 390625
9267 09:25:05.477840 Bus Width = 1
9268 09:25:05.477916 Early init status = 3
9269 09:25:05.484313 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9270 09:25:05.488036 in-header: 03 fc 00 00 01 00 00 00
9271 09:25:05.490955 in-data: 00
9272 09:25:05.494613 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9273 09:25:05.499136 in-header: 03 fd 00 00 00 00 00 00
9274 09:25:05.502186 in-data:
9275 09:25:05.505711 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9276 09:25:05.510177 in-header: 03 fc 00 00 01 00 00 00
9277 09:25:05.513776 in-data: 00
9278 09:25:05.516690 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9279 09:25:05.522585 in-header: 03 fd 00 00 00 00 00 00
9280 09:25:05.525620 in-data:
9281 09:25:05.529006 [SSUSB] Setting up USB HOST controller...
9282 09:25:05.532427 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9283 09:25:05.535545 [SSUSB] phy power-on done.
9284 09:25:05.539298 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9285 09:25:05.545714 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9286 09:25:05.549219 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9287 09:25:05.555869 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9288 09:25:05.562443 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9289 09:25:05.569089 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9290 09:25:05.575433 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9291 09:25:05.582095 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9292 09:25:05.585588 SPM: binary array size = 0x9dc
9293 09:25:05.588402 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9294 09:25:05.594987 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9295 09:25:05.602192 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9296 09:25:05.608553 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9297 09:25:05.611423 configure_display: Starting display init
9298 09:25:05.645304 anx7625_power_on_init: Init interface.
9299 09:25:05.648727 anx7625_disable_pd_protocol: Disabled PD feature.
9300 09:25:05.652203 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9301 09:25:05.680008 anx7625_start_dp_work: Secure OCM version=00
9302 09:25:05.683352 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9303 09:25:05.698241 sp_tx_get_edid_block: EDID Block = 1
9304 09:25:05.800531 Extracted contents:
9305 09:25:05.804121 header: 00 ff ff ff ff ff ff 00
9306 09:25:05.807560 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9307 09:25:05.810706 version: 01 04
9308 09:25:05.813850 basic params: 95 1f 11 78 0a
9309 09:25:05.817283 chroma info: 76 90 94 55 54 90 27 21 50 54
9310 09:25:05.820479 established: 00 00 00
9311 09:25:05.824111 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9312 09:25:05.831028 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9313 09:25:05.837681 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9314 09:25:05.843742 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9315 09:25:05.850692 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9316 09:25:05.853677 extensions: 00
9317 09:25:05.853790 checksum: fb
9318 09:25:05.853877
9319 09:25:05.857298 Manufacturer: IVO Model 57d Serial Number 0
9320 09:25:05.860263 Made week 0 of 2020
9321 09:25:05.860375 EDID version: 1.4
9322 09:25:05.863888 Digital display
9323 09:25:05.867513 6 bits per primary color channel
9324 09:25:05.867616 DisplayPort interface
9325 09:25:05.870311 Maximum image size: 31 cm x 17 cm
9326 09:25:05.873774 Gamma: 220%
9327 09:25:05.873844 Check DPMS levels
9328 09:25:05.877469 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9329 09:25:05.880333 First detailed timing is preferred timing
9330 09:25:05.883729 Established timings supported:
9331 09:25:05.887372 Standard timings supported:
9332 09:25:05.887454 Detailed timings
9333 09:25:05.893897 Hex of detail: 383680a07038204018303c0035ae10000019
9334 09:25:05.896839 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9335 09:25:05.903585 0780 0798 07c8 0820 hborder 0
9336 09:25:05.907480 0438 043b 0447 0458 vborder 0
9337 09:25:05.910180 -hsync -vsync
9338 09:25:05.910251 Did detailed timing
9339 09:25:05.913884 Hex of detail: 000000000000000000000000000000000000
9340 09:25:05.916612 Manufacturer-specified data, tag 0
9341 09:25:05.923600 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9342 09:25:05.923685 ASCII string: InfoVision
9343 09:25:05.930197 Hex of detail: 000000fe00523134304e574635205248200a
9344 09:25:05.933411 ASCII string: R140NWF5 RH
9345 09:25:05.933513 Checksum
9346 09:25:05.933616 Checksum: 0xfb (valid)
9347 09:25:05.940327 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9348 09:25:05.943820 DSI data_rate: 832800000 bps
9349 09:25:05.946969 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9350 09:25:05.950167 anx7625_parse_edid: pixelclock(138800).
9351 09:25:05.956721 hactive(1920), hsync(48), hfp(24), hbp(88)
9352 09:25:05.960518 vactive(1080), vsync(12), vfp(3), vbp(17)
9353 09:25:05.963854 anx7625_dsi_config: config dsi.
9354 09:25:05.970525 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9355 09:25:05.982467 anx7625_dsi_config: success to config DSI
9356 09:25:05.985983 anx7625_dp_start: MIPI phy setup OK.
9357 09:25:05.989208 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9358 09:25:05.992656 mtk_ddp_mode_set invalid vrefresh 60
9359 09:25:05.996078 main_disp_path_setup
9360 09:25:05.996154 ovl_layer_smi_id_en
9361 09:25:05.999512 ovl_layer_smi_id_en
9362 09:25:05.999588 ccorr_config
9363 09:25:05.999649 aal_config
9364 09:25:06.002554 gamma_config
9365 09:25:06.002630 postmask_config
9366 09:25:06.005957 dither_config
9367 09:25:06.009682 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9368 09:25:06.016090 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9369 09:25:06.019009 Root Device init finished in 555 msecs
9370 09:25:06.019087 CPU_CLUSTER: 0 init
9371 09:25:06.029322 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9372 09:25:06.032811 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9373 09:25:06.035615 APU_MBOX 0x190000b0 = 0x10001
9374 09:25:06.039517 APU_MBOX 0x190001b0 = 0x10001
9375 09:25:06.042463 APU_MBOX 0x190005b0 = 0x10001
9376 09:25:06.046072 APU_MBOX 0x190006b0 = 0x10001
9377 09:25:06.048981 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9378 09:25:06.062030 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9379 09:25:06.074233 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9380 09:25:06.080878 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9381 09:25:06.092586 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9382 09:25:06.101383 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9383 09:25:06.104975 CPU_CLUSTER: 0 init finished in 81 msecs
9384 09:25:06.108252 Devices initialized
9385 09:25:06.111591 Show all devs... After init.
9386 09:25:06.111660 Root Device: enabled 1
9387 09:25:06.115111 CPU_CLUSTER: 0: enabled 1
9388 09:25:06.118407 CPU: 00: enabled 1
9389 09:25:06.121708 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9390 09:25:06.124731 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9391 09:25:06.128212 ELOG: NV offset 0x57f000 size 0x1000
9392 09:25:06.134874 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9393 09:25:06.141391 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9394 09:25:06.145072 ELOG: Event(17) added with size 13 at 2024-06-18 09:25:06 UTC
9395 09:25:06.147847 out: cmd=0x121: 03 db 21 01 00 00 00 00
9396 09:25:06.152021 in-header: 03 5f 00 00 2c 00 00 00
9397 09:25:06.165153 in-data: de 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9398 09:25:06.171359 ELOG: Event(A1) added with size 10 at 2024-06-18 09:25:06 UTC
9399 09:25:06.178406 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9400 09:25:06.184967 ELOG: Event(A0) added with size 9 at 2024-06-18 09:25:06 UTC
9401 09:25:06.188633 elog_add_boot_reason: Logged dev mode boot
9402 09:25:06.191390 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9403 09:25:06.194788 Finalize devices...
9404 09:25:06.194886 Devices finalized
9405 09:25:06.201608 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9406 09:25:06.204766 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9407 09:25:06.207954 in-header: 03 07 00 00 08 00 00 00
9408 09:25:06.211204 in-data: aa e4 47 04 13 02 00 00
9409 09:25:06.214215 Chrome EC: UHEPI supported
9410 09:25:06.221429 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9411 09:25:06.224222 in-header: 03 a9 00 00 08 00 00 00
9412 09:25:06.227684 in-data: 84 60 60 08 00 00 00 00
9413 09:25:06.231041 ELOG: Event(91) added with size 10 at 2024-06-18 09:25:06 UTC
9414 09:25:06.237534 Chrome EC: clear events_b mask to 0x0000000020004000
9415 09:25:06.244850 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9416 09:25:06.248551 in-header: 03 fd 00 00 00 00 00 00
9417 09:25:06.248631 in-data:
9418 09:25:06.255033 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9419 09:25:06.258065 Writing coreboot table at 0xffe64000
9420 09:25:06.261822 0. 000000000010a000-0000000000113fff: RAMSTAGE
9421 09:25:06.264704 1. 0000000040000000-00000000400fffff: RAM
9422 09:25:06.268034 2. 0000000040100000-000000004032afff: RAMSTAGE
9423 09:25:06.275198 3. 000000004032b000-00000000545fffff: RAM
9424 09:25:06.277976 4. 0000000054600000-000000005465ffff: BL31
9425 09:25:06.281479 5. 0000000054660000-00000000ffe63fff: RAM
9426 09:25:06.285113 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9427 09:25:06.291520 7. 0000000100000000-000000023fffffff: RAM
9428 09:25:06.291602 Passing 5 GPIOs to payload:
9429 09:25:06.298615 NAME | PORT | POLARITY | VALUE
9430 09:25:06.301450 EC in RW | 0x000000aa | low | undefined
9431 09:25:06.307886 EC interrupt | 0x00000005 | low | undefined
9432 09:25:06.311329 TPM interrupt | 0x000000ab | high | undefined
9433 09:25:06.314965 SD card detect | 0x00000011 | high | undefined
9434 09:25:06.321331 speaker enable | 0x00000093 | high | undefined
9435 09:25:06.324833 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9436 09:25:06.328303 in-header: 03 f9 00 00 02 00 00 00
9437 09:25:06.328397 in-data: 02 00
9438 09:25:06.331734 ADC[4]: Raw value=904726 ID=7
9439 09:25:06.334566 ADC[3]: Raw value=213441 ID=1
9440 09:25:06.334643 RAM Code: 0x71
9441 09:25:06.338110 ADC[6]: Raw value=75332 ID=0
9442 09:25:06.341504 ADC[5]: Raw value=212703 ID=1
9443 09:25:06.341592 SKU Code: 0x1
9444 09:25:06.347864 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d743
9445 09:25:06.351502 coreboot table: 964 bytes.
9446 09:25:06.354727 IMD ROOT 0. 0xfffff000 0x00001000
9447 09:25:06.357952 IMD SMALL 1. 0xffffe000 0x00001000
9448 09:25:06.361613 RO MCACHE 2. 0xffffc000 0x00001104
9449 09:25:06.364597 CONSOLE 3. 0xfff7c000 0x00080000
9450 09:25:06.368236 FMAP 4. 0xfff7b000 0x00000452
9451 09:25:06.371806 TIME STAMP 5. 0xfff7a000 0x00000910
9452 09:25:06.374566 VBOOT WORK 6. 0xfff66000 0x00014000
9453 09:25:06.378177 RAMOOPS 7. 0xffe66000 0x00100000
9454 09:25:06.381753 COREBOOT 8. 0xffe64000 0x00002000
9455 09:25:06.381863 IMD small region:
9456 09:25:06.384546 IMD ROOT 0. 0xffffec00 0x00000400
9457 09:25:06.388191 VPD 1. 0xffffeb80 0x0000006c
9458 09:25:06.391212 MMC STATUS 2. 0xffffeb60 0x00000004
9459 09:25:06.398253 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9460 09:25:06.404802 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9461 09:25:06.443872 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9462 09:25:06.447331 Checking segment from ROM address 0x40100000
9463 09:25:06.450733 Checking segment from ROM address 0x4010001c
9464 09:25:06.457417 Loading segment from ROM address 0x40100000
9465 09:25:06.457519 code (compression=0)
9466 09:25:06.467358 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9467 09:25:06.474012 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9468 09:25:06.474119 it's not compressed!
9469 09:25:06.480720 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9470 09:25:06.483831 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9471 09:25:06.504460 Loading segment from ROM address 0x4010001c
9472 09:25:06.504568 Entry Point 0x80000000
9473 09:25:06.507680 Loaded segments
9474 09:25:06.510560 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9475 09:25:06.517581 Jumping to boot code at 0x80000000(0xffe64000)
9476 09:25:06.523970 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9477 09:25:06.530402 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9478 09:25:06.538680 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9479 09:25:06.542167 Checking segment from ROM address 0x40100000
9480 09:25:06.545066 Checking segment from ROM address 0x4010001c
9481 09:25:06.552143 Loading segment from ROM address 0x40100000
9482 09:25:06.552242 code (compression=1)
9483 09:25:06.558394 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9484 09:25:06.568570 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9485 09:25:06.568669 using LZMA
9486 09:25:06.577164 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9487 09:25:06.583615 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9488 09:25:06.587135 Loading segment from ROM address 0x4010001c
9489 09:25:06.587232 Entry Point 0x54601000
9490 09:25:06.589992 Loaded segments
9491 09:25:06.593461 NOTICE: MT8192 bl31_setup
9492 09:25:06.600591 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9493 09:25:06.604038 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9494 09:25:06.607340 WARNING: region 0:
9495 09:25:06.610428 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 09:25:06.610506 WARNING: region 1:
9497 09:25:06.617160 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9498 09:25:06.620092 WARNING: region 2:
9499 09:25:06.623742 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9500 09:25:06.626856 WARNING: region 3:
9501 09:25:06.630006 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9502 09:25:06.633814 WARNING: region 4:
9503 09:25:06.640418 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9504 09:25:06.640522 WARNING: region 5:
9505 09:25:06.643220 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 09:25:06.646836 WARNING: region 6:
9507 09:25:06.650490 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 09:25:06.653367 WARNING: region 7:
9509 09:25:06.656766 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 09:25:06.663249 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9511 09:25:06.666881 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9512 09:25:06.673438 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9513 09:25:06.676441 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9514 09:25:06.680023 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9515 09:25:06.686565 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9516 09:25:06.690185 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9517 09:25:06.693012 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9518 09:25:06.700115 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9519 09:25:06.703011 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9520 09:25:06.706693 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9521 09:25:06.713208 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9522 09:25:06.716669 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9523 09:25:06.722937 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9524 09:25:06.726326 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9525 09:25:06.729589 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9526 09:25:06.736463 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9527 09:25:06.739778 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9528 09:25:06.743235 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9529 09:25:06.749844 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9530 09:25:06.752890 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9531 09:25:06.759980 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9532 09:25:06.762970 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9533 09:25:06.766307 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9534 09:25:06.773320 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9535 09:25:06.776746 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9536 09:25:06.783521 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9537 09:25:06.786424 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9538 09:25:06.790077 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9539 09:25:06.796374 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9540 09:25:06.799804 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9541 09:25:06.806314 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9542 09:25:06.809965 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9543 09:25:06.813484 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9544 09:25:06.816379 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9545 09:25:06.823420 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9546 09:25:06.826271 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9547 09:25:06.829995 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9548 09:25:06.832854 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9549 09:25:06.836108 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9550 09:25:06.842855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9551 09:25:06.846468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9552 09:25:06.849352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9553 09:25:06.856327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9554 09:25:06.859793 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9555 09:25:06.863087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9556 09:25:06.866505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9557 09:25:06.872563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9558 09:25:06.875810 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9559 09:25:06.882529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9560 09:25:06.886172 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9561 09:25:06.889496 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9562 09:25:06.895963 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9563 09:25:06.898980 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9564 09:25:06.906071 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9565 09:25:06.909529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9566 09:25:06.912546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9567 09:25:06.919130 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9568 09:25:06.922693 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9569 09:25:06.929076 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9570 09:25:06.932660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9571 09:25:06.939058 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9572 09:25:06.942414 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9573 09:25:06.949544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9574 09:25:06.952994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9575 09:25:06.955928 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9576 09:25:06.962489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9577 09:25:06.966162 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9578 09:25:06.972473 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9579 09:25:06.976160 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9580 09:25:06.982737 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9581 09:25:06.985685 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9582 09:25:06.988999 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9583 09:25:06.995650 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9584 09:25:06.999508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9585 09:25:07.005702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9586 09:25:07.008849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9587 09:25:07.016000 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9588 09:25:07.019179 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9589 09:25:07.025695 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9590 09:25:07.029212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9591 09:25:07.032692 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9592 09:25:07.039191 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9593 09:25:07.042708 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9594 09:25:07.049083 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9595 09:25:07.052516 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9596 09:25:07.058982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9597 09:25:07.062208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9598 09:25:07.065543 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9599 09:25:07.072554 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9600 09:25:07.076033 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9601 09:25:07.082580 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9602 09:25:07.085458 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9603 09:25:07.092443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9604 09:25:07.095369 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9605 09:25:07.098996 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9606 09:25:07.105379 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9607 09:25:07.108806 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9608 09:25:07.112242 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9609 09:25:07.115597 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9610 09:25:07.122340 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9611 09:25:07.125568 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9612 09:25:07.132348 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9613 09:25:07.135738 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9614 09:25:07.138902 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9615 09:25:07.145760 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9616 09:25:07.148660 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9617 09:25:07.155222 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9618 09:25:07.158758 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9619 09:25:07.162235 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9620 09:25:07.168827 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9621 09:25:07.172026 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9622 09:25:07.178337 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9623 09:25:07.182471 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9624 09:25:07.185199 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9625 09:25:07.192450 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9626 09:25:07.195263 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9627 09:25:07.198920 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9628 09:25:07.205274 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9629 09:25:07.208817 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9630 09:25:07.212348 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9631 09:25:07.215087 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9632 09:25:07.221973 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9633 09:25:07.225556 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9634 09:25:07.228474 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9635 09:25:07.235158 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9636 09:25:07.238539 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9637 09:25:07.242114 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9638 09:25:07.248465 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9639 09:25:07.251741 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9640 09:25:07.258929 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9641 09:25:07.262176 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9642 09:25:07.265686 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9643 09:25:07.272222 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9644 09:25:07.275050 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9645 09:25:07.281771 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9646 09:25:07.285041 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9647 09:25:07.288808 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9648 09:25:07.295198 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9649 09:25:07.298861 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9650 09:25:07.301695 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9651 09:25:07.308227 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9652 09:25:07.311808 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9653 09:25:07.318306 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9654 09:25:07.321754 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9655 09:25:07.325179 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9656 09:25:07.331771 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9657 09:25:07.334702 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9658 09:25:07.341359 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9659 09:25:07.344763 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9660 09:25:07.348245 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9661 09:25:07.355093 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9662 09:25:07.357983 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9663 09:25:07.364913 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9664 09:25:07.368235 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9665 09:25:07.371512 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9666 09:25:07.378418 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9667 09:25:07.381423 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9668 09:25:07.384988 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9669 09:25:07.391197 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9670 09:25:07.394550 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9671 09:25:07.401148 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9672 09:25:07.404481 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9673 09:25:07.408045 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9674 09:25:07.414547 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9675 09:25:07.418151 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9676 09:25:07.424736 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9677 09:25:07.428275 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9678 09:25:07.431360 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9679 09:25:07.437951 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9680 09:25:07.441541 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9681 09:25:07.447852 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9682 09:25:07.451527 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9683 09:25:07.454498 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9684 09:25:07.461395 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9685 09:25:07.464919 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9686 09:25:07.468464 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9687 09:25:07.474882 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9688 09:25:07.478513 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9689 09:25:07.484847 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9690 09:25:07.488097 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9691 09:25:07.491737 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9692 09:25:07.497815 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9693 09:25:07.501371 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9694 09:25:07.508272 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9695 09:25:07.511467 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9696 09:25:07.514870 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9697 09:25:07.521082 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9698 09:25:07.524597 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9699 09:25:07.531057 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9700 09:25:07.534581 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9701 09:25:07.538133 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9702 09:25:07.544655 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9703 09:25:07.547527 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9704 09:25:07.554640 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9705 09:25:07.557528 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9706 09:25:07.560962 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9707 09:25:07.567454 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9708 09:25:07.570874 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9709 09:25:07.577801 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9710 09:25:07.581079 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9711 09:25:07.587520 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9712 09:25:07.590965 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9713 09:25:07.594349 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9714 09:25:07.601088 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9715 09:25:07.603996 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9716 09:25:07.611001 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9717 09:25:07.614535 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9718 09:25:07.618010 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9719 09:25:07.624079 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9720 09:25:07.627734 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9721 09:25:07.634537 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9722 09:25:07.637370 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9723 09:25:07.643912 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9724 09:25:07.647542 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9725 09:25:07.651273 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9726 09:25:07.657748 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9727 09:25:07.660580 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9728 09:25:07.667729 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9729 09:25:07.670600 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9730 09:25:07.674212 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9731 09:25:07.680504 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9732 09:25:07.684023 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9733 09:25:07.691046 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9734 09:25:07.694044 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9735 09:25:07.697590 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9736 09:25:07.704201 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9737 09:25:07.707627 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9738 09:25:07.713749 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9739 09:25:07.717146 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9740 09:25:07.720799 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9741 09:25:07.724231 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9742 09:25:07.730516 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9743 09:25:07.734016 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9744 09:25:07.737212 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9745 09:25:07.744011 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9746 09:25:07.747348 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9747 09:25:07.750336 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9748 09:25:07.757419 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9749 09:25:07.761045 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9750 09:25:07.763799 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9751 09:25:07.770911 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9752 09:25:07.823020 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9753 09:25:07.823158 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9754 09:25:07.823233 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9755 09:25:07.823312 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9756 09:25:07.823372 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9757 09:25:07.823425 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9758 09:25:07.823485 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9759 09:25:07.823537 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9760 09:25:07.823589 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9761 09:25:07.823649 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9762 09:25:07.823700 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9763 09:25:07.823940 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9764 09:25:07.827433 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9765 09:25:07.833844 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9766 09:25:07.837347 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9767 09:25:07.843995 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9768 09:25:07.847272 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9769 09:25:07.850308 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9770 09:25:07.857194 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9771 09:25:07.860285 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9772 09:25:07.863744 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9773 09:25:07.870262 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9774 09:25:07.873993 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9775 09:25:07.877539 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9776 09:25:07.883721 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9777 09:25:07.887333 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9778 09:25:07.890717 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9779 09:25:07.897233 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9780 09:25:07.900654 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9781 09:25:07.904164 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9782 09:25:07.906997 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9783 09:25:07.910618 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9784 09:25:07.917081 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9785 09:25:07.920545 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9786 09:25:07.924004 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9787 09:25:07.926918 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9788 09:25:07.934102 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9789 09:25:07.936973 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9790 09:25:07.940494 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9791 09:25:07.947212 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9792 09:25:07.950762 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9793 09:25:07.953573 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9794 09:25:07.960451 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9795 09:25:07.963867 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9796 09:25:07.970612 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9797 09:25:07.973432 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9798 09:25:07.980269 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9799 09:25:07.983990 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9800 09:25:07.987258 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9801 09:25:07.993509 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9802 09:25:07.996938 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9803 09:25:08.000664 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9804 09:25:08.006790 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9805 09:25:08.010424 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9806 09:25:08.017392 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9807 09:25:08.020234 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9808 09:25:08.023898 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9809 09:25:08.030228 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9810 09:25:08.033811 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9811 09:25:08.040980 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9812 09:25:08.043925 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9813 09:25:08.050271 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9814 09:25:08.053756 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9815 09:25:08.057366 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9816 09:25:08.063714 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9817 09:25:08.079465 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9818 09:25:08.079760 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9819 09:25:08.079835 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9820 09:25:08.080497 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9821 09:25:08.087192 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9822 09:25:08.090065 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9823 09:25:08.093544 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9824 09:25:08.100284 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9825 09:25:08.103795 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9826 09:25:08.110392 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9827 09:25:08.113396 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9828 09:25:08.120187 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9829 09:25:08.123654 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9830 09:25:08.126822 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9831 09:25:08.140112 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9832 09:25:08.140201 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9833 09:25:08.143924 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9834 09:25:08.146787 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9835 09:25:08.150398 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9836 09:25:08.156965 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9837 09:25:08.160474 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9838 09:25:08.167106 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9839 09:25:08.170115 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9840 09:25:08.173564 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9841 09:25:08.180231 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9842 09:25:08.183871 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9843 09:25:08.190030 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9844 09:25:08.193291 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9845 09:25:08.197212 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9846 09:25:08.203828 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9847 09:25:08.206436 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9848 09:25:08.213525 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9849 09:25:08.216426 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9850 09:25:08.220089 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9851 09:25:08.226961 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9852 09:25:08.230348 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9853 09:25:08.236660 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9854 09:25:08.240466 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9855 09:25:08.243643 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9856 09:25:08.250336 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9857 09:25:08.253889 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9858 09:25:08.260373 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9859 09:25:08.263893 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9860 09:25:08.267458 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9861 09:25:08.273752 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9862 09:25:08.277324 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9863 09:25:08.283842 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9864 09:25:08.287212 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9865 09:25:08.290069 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9866 09:25:08.297258 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9867 09:25:08.300031 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9868 09:25:08.306843 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9869 09:25:08.310310 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9870 09:25:08.317172 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9871 09:25:08.320374 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9872 09:25:08.323758 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9873 09:25:08.330257 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9874 09:25:08.333812 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9875 09:25:08.340224 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9876 09:25:08.343734 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9877 09:25:08.350153 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9878 09:25:08.353563 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9879 09:25:08.356896 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9880 09:25:08.363424 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9881 09:25:08.366997 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9882 09:25:08.373270 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9883 09:25:08.376975 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9884 09:25:08.383297 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9885 09:25:08.386929 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9886 09:25:08.393496 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9887 09:25:08.397148 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9888 09:25:08.399968 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9889 09:25:08.407064 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9890 09:25:08.409720 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9891 09:25:08.416711 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9892 09:25:08.419639 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9893 09:25:08.426644 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9894 09:25:08.430014 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9895 09:25:08.433277 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9896 09:25:08.440214 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9897 09:25:08.442931 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9898 09:25:08.450059 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9899 09:25:08.453458 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9900 09:25:08.460331 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9901 09:25:08.463286 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9902 09:25:08.469706 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9903 09:25:08.473065 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9904 09:25:08.476346 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9905 09:25:08.483201 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9906 09:25:08.486564 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9907 09:25:08.492971 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9908 09:25:08.496277 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9909 09:25:08.503197 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9910 09:25:08.506099 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9911 09:25:08.509517 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9912 09:25:08.516178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9913 09:25:08.519489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9914 09:25:08.526508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9915 09:25:08.529228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9916 09:25:08.536402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9917 09:25:08.540015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9918 09:25:08.542779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9919 09:25:08.549337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9920 09:25:08.552930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9921 09:25:08.559220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9922 09:25:08.562675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9923 09:25:08.569635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9924 09:25:08.572560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9925 09:25:08.579633 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9926 09:25:08.583122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9927 09:25:08.589497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9928 09:25:08.593085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9929 09:25:08.599211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9930 09:25:08.602847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9931 09:25:08.609104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9932 09:25:08.612591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9933 09:25:08.619815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9934 09:25:08.622629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9935 09:25:08.629679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9936 09:25:08.633232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9937 09:25:08.639690 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9938 09:25:08.642598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9939 09:25:08.649599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9940 09:25:08.653043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9941 09:25:08.659863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9942 09:25:08.663102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9943 09:25:08.669381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9944 09:25:08.672700 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9945 09:25:08.672795 INFO: [APUAPC] vio 0
9946 09:25:08.680292 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9947 09:25:08.683826 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9948 09:25:08.687375 INFO: [APUAPC] D0_APC_0: 0x400510
9949 09:25:08.690241 INFO: [APUAPC] D0_APC_1: 0x0
9950 09:25:08.693745 INFO: [APUAPC] D0_APC_2: 0x1540
9951 09:25:08.697087 INFO: [APUAPC] D0_APC_3: 0x0
9952 09:25:08.700428 INFO: [APUAPC] D1_APC_0: 0xffffffff
9953 09:25:08.703839 INFO: [APUAPC] D1_APC_1: 0xffffffff
9954 09:25:08.707388 INFO: [APUAPC] D1_APC_2: 0x3fffff
9955 09:25:08.710165 INFO: [APUAPC] D1_APC_3: 0x0
9956 09:25:08.713937 INFO: [APUAPC] D2_APC_0: 0xffffffff
9957 09:25:08.717475 INFO: [APUAPC] D2_APC_1: 0xffffffff
9958 09:25:08.720301 INFO: [APUAPC] D2_APC_2: 0x3fffff
9959 09:25:08.723891 INFO: [APUAPC] D2_APC_3: 0x0
9960 09:25:08.727247 INFO: [APUAPC] D3_APC_0: 0xffffffff
9961 09:25:08.730678 INFO: [APUAPC] D3_APC_1: 0xffffffff
9962 09:25:08.733649 INFO: [APUAPC] D3_APC_2: 0x3fffff
9963 09:25:08.733724 INFO: [APUAPC] D3_APC_3: 0x0
9964 09:25:08.737231 INFO: [APUAPC] D4_APC_0: 0xffffffff
9965 09:25:08.743646 INFO: [APUAPC] D4_APC_1: 0xffffffff
9966 09:25:08.747222 INFO: [APUAPC] D4_APC_2: 0x3fffff
9967 09:25:08.747322 INFO: [APUAPC] D4_APC_3: 0x0
9968 09:25:08.750140 INFO: [APUAPC] D5_APC_0: 0xffffffff
9969 09:25:08.753680 INFO: [APUAPC] D5_APC_1: 0xffffffff
9970 09:25:08.757258 INFO: [APUAPC] D5_APC_2: 0x3fffff
9971 09:25:08.760218 INFO: [APUAPC] D5_APC_3: 0x0
9972 09:25:08.763730 INFO: [APUAPC] D6_APC_0: 0xffffffff
9973 09:25:08.767229 INFO: [APUAPC] D6_APC_1: 0xffffffff
9974 09:25:08.770100 INFO: [APUAPC] D6_APC_2: 0x3fffff
9975 09:25:08.773957 INFO: [APUAPC] D6_APC_3: 0x0
9976 09:25:08.777266 INFO: [APUAPC] D7_APC_0: 0xffffffff
9977 09:25:08.780518 INFO: [APUAPC] D7_APC_1: 0xffffffff
9978 09:25:08.783764 INFO: [APUAPC] D7_APC_2: 0x3fffff
9979 09:25:08.787154 INFO: [APUAPC] D7_APC_3: 0x0
9980 09:25:08.790393 INFO: [APUAPC] D8_APC_0: 0xffffffff
9981 09:25:08.793298 INFO: [APUAPC] D8_APC_1: 0xffffffff
9982 09:25:08.796851 INFO: [APUAPC] D8_APC_2: 0x3fffff
9983 09:25:08.800348 INFO: [APUAPC] D8_APC_3: 0x0
9984 09:25:08.803689 INFO: [APUAPC] D9_APC_0: 0xffffffff
9985 09:25:08.806914 INFO: [APUAPC] D9_APC_1: 0xffffffff
9986 09:25:08.810203 INFO: [APUAPC] D9_APC_2: 0x3fffff
9987 09:25:08.813394 INFO: [APUAPC] D9_APC_3: 0x0
9988 09:25:08.816814 INFO: [APUAPC] D10_APC_0: 0xffffffff
9989 09:25:08.820523 INFO: [APUAPC] D10_APC_1: 0xffffffff
9990 09:25:08.823394 INFO: [APUAPC] D10_APC_2: 0x3fffff
9991 09:25:08.826999 INFO: [APUAPC] D10_APC_3: 0x0
9992 09:25:08.829987 INFO: [APUAPC] D11_APC_0: 0xffffffff
9993 09:25:08.833493 INFO: [APUAPC] D11_APC_1: 0xffffffff
9994 09:25:08.837053 INFO: [APUAPC] D11_APC_2: 0x3fffff
9995 09:25:08.839907 INFO: [APUAPC] D11_APC_3: 0x0
9996 09:25:08.843380 INFO: [APUAPC] D12_APC_0: 0xffffffff
9997 09:25:08.846662 INFO: [APUAPC] D12_APC_1: 0xffffffff
9998 09:25:08.849973 INFO: [APUAPC] D12_APC_2: 0x3fffff
9999 09:25:08.853330 INFO: [APUAPC] D12_APC_3: 0x0
10000 09:25:08.857230 INFO: [APUAPC] D13_APC_0: 0xffffffff
10001 09:25:08.860262 INFO: [APUAPC] D13_APC_1: 0xffffffff
10002 09:25:08.863898 INFO: [APUAPC] D13_APC_2: 0x3fffff
10003 09:25:08.866947 INFO: [APUAPC] D13_APC_3: 0x0
10004 09:25:08.870583 INFO: [APUAPC] D14_APC_0: 0xffffffff
10005 09:25:08.873414 INFO: [APUAPC] D14_APC_1: 0xffffffff
10006 09:25:08.876768 INFO: [APUAPC] D14_APC_2: 0x3fffff
10007 09:25:08.880340 INFO: [APUAPC] D14_APC_3: 0x0
10008 09:25:08.883618 INFO: [APUAPC] D15_APC_0: 0xffffffff
10009 09:25:08.887176 INFO: [APUAPC] D15_APC_1: 0xffffffff
10010 09:25:08.890639 INFO: [APUAPC] D15_APC_2: 0x3fffff
10011 09:25:08.893324 INFO: [APUAPC] D15_APC_3: 0x0
10012 09:25:08.896646 INFO: [APUAPC] APC_CON: 0x4
10013 09:25:08.900232 INFO: [NOCDAPC] D0_APC_0: 0x0
10014 09:25:08.903403 INFO: [NOCDAPC] D0_APC_1: 0x0
10015 09:25:08.903479 INFO: [NOCDAPC] D1_APC_0: 0x0
10016 09:25:08.907203 INFO: [NOCDAPC] D1_APC_1: 0xfff
10017 09:25:08.910139 INFO: [NOCDAPC] D2_APC_0: 0x0
10018 09:25:08.913453 INFO: [NOCDAPC] D2_APC_1: 0xfff
10019 09:25:08.916708 INFO: [NOCDAPC] D3_APC_0: 0x0
10020 09:25:08.920004 INFO: [NOCDAPC] D3_APC_1: 0xfff
10021 09:25:08.923661 INFO: [NOCDAPC] D4_APC_0: 0x0
10022 09:25:08.927189 INFO: [NOCDAPC] D4_APC_1: 0xfff
10023 09:25:08.929982 INFO: [NOCDAPC] D5_APC_0: 0x0
10024 09:25:08.933708 INFO: [NOCDAPC] D5_APC_1: 0xfff
10025 09:25:08.933778 INFO: [NOCDAPC] D6_APC_0: 0x0
10026 09:25:08.936690 INFO: [NOCDAPC] D6_APC_1: 0xfff
10027 09:25:08.940175 INFO: [NOCDAPC] D7_APC_0: 0x0
10028 09:25:08.943858 INFO: [NOCDAPC] D7_APC_1: 0xfff
10029 09:25:08.946618 INFO: [NOCDAPC] D8_APC_0: 0x0
10030 09:25:08.950343 INFO: [NOCDAPC] D8_APC_1: 0xfff
10031 09:25:08.953128 INFO: [NOCDAPC] D9_APC_0: 0x0
10032 09:25:08.956825 INFO: [NOCDAPC] D9_APC_1: 0xfff
10033 09:25:08.960286 INFO: [NOCDAPC] D10_APC_0: 0x0
10034 09:25:08.963106 INFO: [NOCDAPC] D10_APC_1: 0xfff
10035 09:25:08.966516 INFO: [NOCDAPC] D11_APC_0: 0x0
10036 09:25:08.969877 INFO: [NOCDAPC] D11_APC_1: 0xfff
10037 09:25:08.973809 INFO: [NOCDAPC] D12_APC_0: 0x0
10038 09:25:08.973888 INFO: [NOCDAPC] D12_APC_1: 0xfff
10039 09:25:08.976747 INFO: [NOCDAPC] D13_APC_0: 0x0
10040 09:25:08.979812 INFO: [NOCDAPC] D13_APC_1: 0xfff
10041 09:25:08.983283 INFO: [NOCDAPC] D14_APC_0: 0x0
10042 09:25:08.986934 INFO: [NOCDAPC] D14_APC_1: 0xfff
10043 09:25:08.990314 INFO: [NOCDAPC] D15_APC_0: 0x0
10044 09:25:08.993143 INFO: [NOCDAPC] D15_APC_1: 0xfff
10045 09:25:08.996651 INFO: [NOCDAPC] APC_CON: 0x4
10046 09:25:08.999560 INFO: [APUAPC] set_apusys_apc done
10047 09:25:09.003299 INFO: [DEVAPC] devapc_init done
10048 09:25:09.006279 INFO: GICv3 without legacy support detected.
10049 09:25:09.009736 INFO: ARM GICv3 driver initialized in EL3
10050 09:25:09.013092 INFO: Maximum SPI INTID supported: 639
10051 09:25:09.019970 INFO: BL31: Initializing runtime services
10052 09:25:09.022907 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10053 09:25:09.026351 INFO: SPM: enable CPC mode
10054 09:25:09.033054 INFO: mcdi ready for mcusys-off-idle and system suspend
10055 09:25:09.036695 INFO: BL31: Preparing for EL3 exit to normal world
10056 09:25:09.039826 INFO: Entry point address = 0x80000000
10057 09:25:09.043487 INFO: SPSR = 0x8
10058 09:25:09.048481
10059 09:25:09.048561
10060 09:25:09.048620
10061 09:25:09.051970 Starting depthcharge on Spherion...
10062 09:25:09.052047
10063 09:25:09.052114 Wipe memory regions:
10064 09:25:09.052170
10065 09:25:09.052804 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10066 09:25:09.052920 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10067 09:25:09.053000 Setting prompt string to ['asurada:']
10068 09:25:09.053089 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10069 09:25:09.054717 [0x00000040000000, 0x00000054600000)
10070 09:25:09.177593
10071 09:25:09.177737 [0x00000054660000, 0x00000080000000)
10072 09:25:09.437946
10073 09:25:09.438057 [0x000000821a7280, 0x000000ffe64000)
10074 09:25:10.183002
10075 09:25:10.183437 [0x00000100000000, 0x00000240000000)
10076 09:25:12.072345
10077 09:25:12.075437 Initializing XHCI USB controller at 0x11200000.
10078 09:25:13.113528
10079 09:25:13.117229 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10080 09:25:13.117344
10081 09:25:13.117431
10082 09:25:13.117741 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10084 09:25:13.218089 asurada: tftpboot 192.168.201.1 14407629/tftp-deploy-x56ds326/kernel/image.itb 14407629/tftp-deploy-x56ds326/kernel/cmdline
10085 09:25:13.218291 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 09:25:13.218372 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10087 09:25:13.222180 tftpboot 192.168.201.1 14407629/tftp-deploy-x56ds326/kernel/image.itbtp-deploy-x56ds326/kernel/cmdline
10088 09:25:13.222260
10089 09:25:13.222321 Waiting for link
10090 09:25:13.380276
10091 09:25:13.380394 R8152: Initializing
10092 09:25:13.380458
10093 09:25:13.383971 Version 9 (ocp_data = 6010)
10094 09:25:13.384038
10095 09:25:13.387422 R8152: Done initializing
10096 09:25:13.387489
10097 09:25:13.387546 Adding net device
10098 09:25:15.335240
10099 09:25:15.335359 done.
10100 09:25:15.335424
10101 09:25:15.335488 MAC: 00:e0:4c:78:7a:aa
10102 09:25:15.335564
10103 09:25:15.338336 Sending DHCP discover... done.
10104 09:25:15.338446
10105 09:25:15.473884 Waiting for reply... done.
10106 09:25:15.474001
10107 09:25:15.474064 Sending DHCP request... done.
10108 09:25:15.477386
10109 09:25:16.229676 Waiting for reply... done.
10110 09:25:16.229820
10111 09:25:16.229903 My ip is 192.168.201.12
10112 09:25:16.229963
10113 09:25:16.233137 The DHCP server ip is 192.168.201.1
10114 09:25:16.233237
10115 09:25:16.239575 TFTP server IP predefined by user: 192.168.201.1
10116 09:25:16.239655
10117 09:25:16.246424 Bootfile predefined by user: 14407629/tftp-deploy-x56ds326/kernel/image.itb
10118 09:25:16.246521
10119 09:25:16.246609 Sending tftp read request... done.
10120 09:25:16.249905
10121 09:25:16.253168 Waiting for the transfer...
10122 09:25:16.253247
10123 09:25:16.514641 00000000 ################################################################
10124 09:25:16.514783
10125 09:25:16.767641 00080000 ################################################################
10126 09:25:16.767753
10127 09:25:17.029929 00100000 ################################################################
10128 09:25:17.030047
10129 09:25:17.279188 00180000 ################################################################
10130 09:25:17.279324
10131 09:25:17.531706 00200000 ################################################################
10132 09:25:17.531821
10133 09:25:17.785145 00280000 ################################################################
10134 09:25:17.785263
10135 09:25:18.042073 00300000 ################################################################
10136 09:25:18.042203
10137 09:25:18.305324 00380000 ################################################################
10138 09:25:18.305479
10139 09:25:18.557815 00400000 ################################################################
10140 09:25:18.557950
10141 09:25:18.813292 00480000 ################################################################
10142 09:25:18.813429
10143 09:25:19.079899 00500000 ################################################################
10144 09:25:19.080077
10145 09:25:19.350935 00580000 ################################################################
10146 09:25:19.351077
10147 09:25:19.609342 00600000 ################################################################
10148 09:25:19.609500
10149 09:25:19.866664 00680000 ################################################################
10150 09:25:19.866807
10151 09:25:20.127669 00700000 ################################################################
10152 09:25:20.127798
10153 09:25:20.402264 00780000 ################################################################
10154 09:25:20.402386
10155 09:25:20.666454 00800000 ################################################################
10156 09:25:20.666571
10157 09:25:20.928635 00880000 ################################################################
10158 09:25:20.928776
10159 09:25:21.182887 00900000 ################################################################
10160 09:25:21.183023
10161 09:25:21.520243 00980000 ################################################################
10162 09:25:21.520381
10163 09:25:21.806084 00a00000 ################################################################
10164 09:25:21.806211
10165 09:25:22.073540 00a80000 ################################################################
10166 09:25:22.073670
10167 09:25:22.334477 00b00000 ################################################################
10168 09:25:22.334596
10169 09:25:22.605210 00b80000 ################################################################
10170 09:25:22.605330
10171 09:25:22.880584 00c00000 ################################################################
10172 09:25:22.880695
10173 09:25:23.168169 00c80000 ################################################################
10174 09:25:23.168282
10175 09:25:23.449421 00d00000 ################################################################
10176 09:25:23.449575
10177 09:25:23.730107 00d80000 ################################################################
10178 09:25:23.730223
10179 09:25:23.992928 00e00000 ################################################################
10180 09:25:23.993043
10181 09:25:24.264253 00e80000 ################################################################
10182 09:25:24.264381
10183 09:25:24.548727 00f00000 ################################################################
10184 09:25:24.548852
10185 09:25:24.828408 00f80000 ################################################################
10186 09:25:24.828543
10187 09:25:25.103547 01000000 ################################################################
10188 09:25:25.103701
10189 09:25:25.379792 01080000 ################################################################
10190 09:25:25.379929
10191 09:25:25.676305 01100000 ################################################################
10192 09:25:25.676418
10193 09:25:25.957773 01180000 ################################################################
10194 09:25:25.957888
10195 09:25:26.219782 01200000 ################################################################
10196 09:25:26.219901
10197 09:25:26.518397 01280000 ################################################################
10198 09:25:26.518574
10199 09:25:26.868679 01300000 ################################################################
10200 09:25:26.868804
10201 09:25:27.220678 01380000 ################################################################
10202 09:25:27.220797
10203 09:25:27.574082 01400000 ################################################################
10204 09:25:27.574205
10205 09:25:27.931336 01480000 ################################################################
10206 09:25:27.931483
10207 09:25:28.292246 01500000 ################################################################
10208 09:25:28.292374
10209 09:25:28.649799 01580000 ################################################################
10210 09:25:28.649914
10211 09:25:29.010678 01600000 ################################################################
10212 09:25:29.010872
10213 09:25:29.338903 01680000 ################################################################
10214 09:25:29.339054
10215 09:25:29.651131 01700000 ################################################################
10216 09:25:29.651271
10217 09:25:29.978692 01780000 ################################################################
10218 09:25:29.978837
10219 09:25:30.239777 01800000 ################################################################
10220 09:25:30.239933
10221 09:25:30.508982 01880000 ################################################################
10222 09:25:30.509128
10223 09:25:30.767603 01900000 ################################################################
10224 09:25:30.767747
10225 09:25:31.025302 01980000 ################################################################
10226 09:25:31.025414
10227 09:25:31.282946 01a00000 ################################################################
10228 09:25:31.283091
10229 09:25:31.557667 01a80000 ################################################################
10230 09:25:31.557816
10231 09:25:31.830741 01b00000 ################################################################
10232 09:25:31.830878
10233 09:25:32.119824 01b80000 ################################################################
10234 09:25:32.119975
10235 09:25:32.390124 01c00000 ################################################################
10236 09:25:32.390240
10237 09:25:32.667614 01c80000 ################################################################
10238 09:25:32.667738
10239 09:25:32.941407 01d00000 ################################################################
10240 09:25:32.941552
10241 09:25:33.200340 01d80000 ################################################################
10242 09:25:33.200470
10243 09:25:33.428666 01e00000 ######################################################### done.
10244 09:25:33.428804
10245 09:25:33.432173 The bootfile was 31921222 bytes long.
10246 09:25:33.432255
10247 09:25:33.435704 Sending tftp read request... done.
10248 09:25:33.435790
10249 09:25:33.438580 Waiting for the transfer...
10250 09:25:33.438668
10251 09:25:33.442152 00000000 # done.
10252 09:25:33.442239
10253 09:25:33.448812 Command line loaded dynamically from TFTP file: 14407629/tftp-deploy-x56ds326/kernel/cmdline
10254 09:25:33.448901
10255 09:25:33.472016 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407629/extract-nfsrootfs-ggqeh951,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10256 09:25:33.472131
10257 09:25:33.472228 Loading FIT.
10258 09:25:33.472322
10259 09:25:33.475786 Image ramdisk-1 has 18745209 bytes.
10260 09:25:33.475868
10261 09:25:33.478668 Image fdt-1 has 47258 bytes.
10262 09:25:33.478750
10263 09:25:33.482224 Image kernel-1 has 13126726 bytes.
10264 09:25:33.482305
10265 09:25:33.488588 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10266 09:25:33.488670
10267 09:25:33.508729 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10268 09:25:33.508832
10269 09:25:33.511940 Choosing best match conf-1 for compat google,spherion-rev2.
10270 09:25:33.517160
10271 09:25:33.521885 Connected to device vid:did:rid of 1ae0:0028:00
10272 09:25:33.529263
10273 09:25:33.532189 tpm_get_response: command 0x17b, return code 0x0
10274 09:25:33.532270
10275 09:25:33.535787 ec_init: CrosEC protocol v3 supported (256, 248)
10276 09:25:33.540729
10277 09:25:33.543697 tpm_cleanup: add release locality here.
10278 09:25:33.543779
10279 09:25:33.543840 Shutting down all USB controllers.
10280 09:25:33.547457
10281 09:25:33.547541 Removing current net device
10282 09:25:33.547620
10283 09:25:33.554078 Exiting depthcharge with code 4 at timestamp: 53802488
10284 09:25:33.554162
10285 09:25:33.556877 LZMA decompressing kernel-1 to 0x821a6718
10286 09:25:33.556949
10287 09:25:33.560430 LZMA decompressing kernel-1 to 0x40000000
10288 09:25:35.178616
10289 09:25:35.178779 jumping to kernel
10290 09:25:35.179340 end: 2.2.4 bootloader-commands (duration 00:00:26) [common]
10291 09:25:35.179461 start: 2.2.5 auto-login-action (timeout 00:03:54) [common]
10292 09:25:35.179565 Setting prompt string to ['Linux version [0-9]']
10293 09:25:35.179674 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10294 09:25:35.179776 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10295 09:25:35.260672
10296 09:25:35.264020 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10297 09:25:35.267750 start: 2.2.5.1 login-action (timeout 00:03:54) [common]
10298 09:25:35.267849 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10299 09:25:35.267925 Setting prompt string to []
10300 09:25:35.268003 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10301 09:25:35.268072 Using line separator: #'\n'#
10302 09:25:35.268133 No login prompt set.
10303 09:25:35.268198 Parsing kernel messages
10304 09:25:35.268250 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10305 09:25:35.268351 [login-action] Waiting for messages, (timeout 00:03:54)
10306 09:25:35.268423 Waiting using forced prompt support (timeout 00:01:57)
10307 09:25:35.287243 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
10308 09:25:35.290731 [ 0.000000] random: crng init done
10309 09:25:35.294191 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10310 09:25:35.297050 [ 0.000000] efi: UEFI not found.
10311 09:25:35.306904 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10312 09:25:35.313979 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10313 09:25:35.323659 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10314 09:25:35.333346 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10315 09:25:35.340259 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10316 09:25:35.343648 [ 0.000000] printk: bootconsole [mtk8250] enabled
10317 09:25:35.352791 [ 0.000000] NUMA: No NUMA configuration found
10318 09:25:35.359325 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10319 09:25:35.365444 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10320 09:25:35.365594 [ 0.000000] Zone ranges:
10321 09:25:35.372480 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10322 09:25:35.375673 [ 0.000000] DMA32 empty
10323 09:25:35.382583 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10324 09:25:35.386136 [ 0.000000] Movable zone start for each node
10325 09:25:35.388796 [ 0.000000] Early memory node ranges
10326 09:25:35.395769 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10327 09:25:35.402218 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10328 09:25:35.408657 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10329 09:25:35.415110 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10330 09:25:35.422192 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10331 09:25:35.428316 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10332 09:25:35.485350 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10333 09:25:35.491904 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10334 09:25:35.499014 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10335 09:25:35.501654 [ 0.000000] psci: probing for conduit method from DT.
10336 09:25:35.508740 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10337 09:25:35.512181 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10338 09:25:35.518341 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10339 09:25:35.522052 [ 0.000000] psci: SMC Calling Convention v1.2
10340 09:25:35.528432 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10341 09:25:35.531956 [ 0.000000] Detected VIPT I-cache on CPU0
10342 09:25:35.538129 [ 0.000000] CPU features: detected: GIC system register CPU interface
10343 09:25:35.544893 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10344 09:25:35.551710 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10345 09:25:35.558074 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10346 09:25:35.565092 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10347 09:25:35.571567 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10348 09:25:35.577928 [ 0.000000] alternatives: applying boot alternatives
10349 09:25:35.581162 [ 0.000000] Fallback order for Node 0: 0
10350 09:25:35.591672 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10351 09:25:35.591823 [ 0.000000] Policy zone: Normal
10352 09:25:35.617560 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407629/extract-nfsrootfs-ggqeh951,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10353 09:25:35.627530 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10354 09:25:35.638257 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10355 09:25:35.648543 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10356 09:25:35.654867 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10357 09:25:35.658612 <6>[ 0.000000] software IO TLB: area num 8.
10358 09:25:35.715027 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10359 09:25:35.864496 <6>[ 0.000000] Memory: 7945756K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407012K reserved, 32768K cma-reserved)
10360 09:25:35.870784 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10361 09:25:35.877319 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10362 09:25:35.880696 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10363 09:25:35.887743 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10364 09:25:35.894073 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10365 09:25:35.897568 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10366 09:25:35.907324 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10367 09:25:35.914108 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10368 09:25:35.917781 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10369 09:25:35.925775 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10370 09:25:35.928480 <6>[ 0.000000] GICv3: 608 SPIs implemented
10371 09:25:35.935032 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10372 09:25:35.938527 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10373 09:25:35.942042 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10374 09:25:35.951866 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10375 09:25:35.961817 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10376 09:25:35.975080 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10377 09:25:35.981626 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10378 09:25:35.991035 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10379 09:25:36.004031 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10380 09:25:36.010594 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10381 09:25:36.017651 <6>[ 0.009181] Console: colour dummy device 80x25
10382 09:25:36.027403 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10383 09:25:36.033924 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10384 09:25:36.037495 <6>[ 0.029221] LSM: Security Framework initializing
10385 09:25:36.043930 <6>[ 0.034160] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10386 09:25:36.053971 <6>[ 0.041974] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10387 09:25:36.061058 <6>[ 0.051396] cblist_init_generic: Setting adjustable number of callback queues.
10388 09:25:36.067634 <6>[ 0.058842] cblist_init_generic: Setting shift to 3 and lim to 1.
10389 09:25:36.077555 <6>[ 0.065181] cblist_init_generic: Setting adjustable number of callback queues.
10390 09:25:36.080389 <6>[ 0.072608] cblist_init_generic: Setting shift to 3 and lim to 1.
10391 09:25:36.087347 <6>[ 0.079007] rcu: Hierarchical SRCU implementation.
10392 09:25:36.093633 <6>[ 0.084022] rcu: Max phase no-delay instances is 1000.
10393 09:25:36.100586 <6>[ 0.091060] EFI services will not be available.
10394 09:25:36.103897 <6>[ 0.096015] smp: Bringing up secondary CPUs ...
10395 09:25:36.111890 <6>[ 0.101064] Detected VIPT I-cache on CPU1
10396 09:25:36.117996 <6>[ 0.101137] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10397 09:25:36.125286 <6>[ 0.101169] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10398 09:25:36.128230 <6>[ 0.101510] Detected VIPT I-cache on CPU2
10399 09:25:36.134860 <6>[ 0.101565] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10400 09:25:36.144557 <6>[ 0.101583] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10401 09:25:36.148005 <6>[ 0.101843] Detected VIPT I-cache on CPU3
10402 09:25:36.154604 <6>[ 0.101891] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10403 09:25:36.161529 <6>[ 0.101906] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10404 09:25:36.164982 <6>[ 0.102213] CPU features: detected: Spectre-v4
10405 09:25:36.171472 <6>[ 0.102219] CPU features: detected: Spectre-BHB
10406 09:25:36.174363 <6>[ 0.102224] Detected PIPT I-cache on CPU4
10407 09:25:36.181513 <6>[ 0.102279] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10408 09:25:36.187883 <6>[ 0.102295] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10409 09:25:36.194257 <6>[ 0.102574] Detected PIPT I-cache on CPU5
10410 09:25:36.200709 <6>[ 0.102630] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10411 09:25:36.207927 <6>[ 0.102646] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10412 09:25:36.210905 <6>[ 0.102922] Detected PIPT I-cache on CPU6
10413 09:25:36.217723 <6>[ 0.102988] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10414 09:25:36.224585 <6>[ 0.103004] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10415 09:25:36.230882 <6>[ 0.103300] Detected PIPT I-cache on CPU7
10416 09:25:36.237263 <6>[ 0.103366] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10417 09:25:36.244091 <6>[ 0.103382] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10418 09:25:36.247439 <6>[ 0.103429] smp: Brought up 1 node, 8 CPUs
10419 09:25:36.254252 <6>[ 0.244756] SMP: Total of 8 processors activated.
10420 09:25:36.257406 <6>[ 0.249708] CPU features: detected: 32-bit EL0 Support
10421 09:25:36.267164 <6>[ 0.255072] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10422 09:25:36.274353 <6>[ 0.263872] CPU features: detected: Common not Private translations
10423 09:25:36.277327 <6>[ 0.270348] CPU features: detected: CRC32 instructions
10424 09:25:36.283985 <6>[ 0.275699] CPU features: detected: RCpc load-acquire (LDAPR)
10425 09:25:36.290556 <6>[ 0.281660] CPU features: detected: LSE atomic instructions
10426 09:25:36.297431 <6>[ 0.287441] CPU features: detected: Privileged Access Never
10427 09:25:36.300361 <6>[ 0.293221] CPU features: detected: RAS Extension Support
10428 09:25:36.310583 <6>[ 0.298864] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10429 09:25:36.314167 <6>[ 0.306084] CPU: All CPU(s) started at EL2
10430 09:25:36.320406 <6>[ 0.310401] alternatives: applying system-wide alternatives
10431 09:25:36.329514 <6>[ 0.321258] devtmpfs: initialized
10432 09:25:36.344908 <6>[ 0.330128] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10433 09:25:36.351955 <6>[ 0.340089] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10434 09:25:36.358244 <6>[ 0.348108] pinctrl core: initialized pinctrl subsystem
10435 09:25:36.361722 <6>[ 0.354776] DMI not present or invalid.
10436 09:25:36.367875 <6>[ 0.359194] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10437 09:25:36.378177 <6>[ 0.366066] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10438 09:25:36.384474 <6>[ 0.373656] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10439 09:25:36.394573 <6>[ 0.381876] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10440 09:25:36.397824 <6>[ 0.390117] audit: initializing netlink subsys (disabled)
10441 09:25:36.407667 <5>[ 0.395810] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10442 09:25:36.414118 <6>[ 0.396534] thermal_sys: Registered thermal governor 'step_wise'
10443 09:25:36.421053 <6>[ 0.403777] thermal_sys: Registered thermal governor 'power_allocator'
10444 09:25:36.424091 <6>[ 0.410030] cpuidle: using governor menu
10445 09:25:36.431074 <6>[ 0.420985] NET: Registered PF_QIPCRTR protocol family
10446 09:25:36.437417 <6>[ 0.426471] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10447 09:25:36.440631 <6>[ 0.433573] ASID allocator initialised with 32768 entries
10448 09:25:36.448698 <6>[ 0.440155] Serial: AMBA PL011 UART driver
10449 09:25:36.457274 <4>[ 0.449000] Trying to register duplicate clock ID: 134
10450 09:25:36.763998 <6>[ 0.510622] KASLR enabled
10451 09:25:36.764172 <6>[ 0.518352] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10452 09:25:36.764297 <6>[ 0.525366] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10453 09:25:36.764436 <6>[ 0.531856] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10454 09:25:36.764536 <6>[ 0.538861] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10455 09:25:36.764648 <6>[ 0.545347] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10456 09:25:36.764704 <6>[ 0.552352] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10457 09:25:36.764766 <6>[ 0.558840] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10458 09:25:36.764828 <6>[ 0.565842] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10459 09:25:36.764912 <6>[ 0.573368] ACPI: Interpreter disabled.
10460 09:25:36.764993 <6>[ 0.579803] iommu: Default domain type: Translated
10461 09:25:36.765074 <6>[ 0.584915] iommu: DMA domain TLB invalidation policy: strict mode
10462 09:25:36.765161 <5>[ 0.591577] SCSI subsystem initialized
10463 09:25:36.765241 <6>[ 0.595744] usbcore: registered new interface driver usbfs
10464 09:25:36.765319 <6>[ 0.601477] usbcore: registered new interface driver hub
10465 09:25:36.765400 <6>[ 0.607031] usbcore: registered new device driver usb
10466 09:25:36.765505 <6>[ 0.613134] pps_core: LinuxPPS API ver. 1 registered
10467 09:25:36.765597 <6>[ 0.618328] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10468 09:25:36.765650 <6>[ 0.627674] PTP clock support registered
10469 09:25:36.765700 <6>[ 0.631919] EDAC MC: Ver: 3.0.0
10470 09:25:36.765771 <6>[ 0.637073] FPGA manager framework
10471 09:25:36.765849 <6>[ 0.640759] Advanced Linux Sound Architecture Driver Initialized.
10472 09:25:36.765926 <6>[ 0.647538] vgaarb: loaded
10473 09:25:36.766005 <6>[ 0.650698] clocksource: Switched to clocksource arch_sys_counter
10474 09:25:36.766083 <5>[ 0.657142] VFS: Disk quotas dquot_6.6.0
10475 09:25:36.766150 <6>[ 0.661329] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10476 09:25:36.766201 <6>[ 0.668519] pnp: PnP ACPI: disabled
10477 09:25:36.766266 <6>[ 0.675225] NET: Registered PF_INET protocol family
10478 09:25:36.766344 <6>[ 0.680819] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10479 09:25:36.766422 <6>[ 0.693168] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10480 09:25:36.766530 <6>[ 0.701987] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10481 09:25:36.766709 <6>[ 0.709957] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10482 09:25:36.766791 <6>[ 0.718659] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10483 09:25:36.766871 <6>[ 0.728415] TCP: Hash tables configured (established 65536 bind 65536)
10484 09:25:36.766958 <6>[ 0.735283] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10485 09:25:36.767037 <6>[ 0.742482] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10486 09:25:36.767117 <6>[ 0.750183] NET: Registered PF_UNIX/PF_LOCAL protocol family
10487 09:25:36.767651 <6>[ 0.756285] RPC: Registered named UNIX socket transport module.
10488 09:25:36.770223 <6>[ 0.762439] RPC: Registered udp transport module.
10489 09:25:36.776298 <6>[ 0.767373] RPC: Registered tcp transport module.
10490 09:25:36.783153 <6>[ 0.772305] RPC: Registered tcp NFSv4.1 backchannel transport module.
10491 09:25:36.786277 <6>[ 0.778970] PCI: CLS 0 bytes, default 64
10492 09:25:36.789418 <6>[ 0.783298] Unpacking initramfs...
10493 09:25:36.814443 <6>[ 0.802791] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10494 09:25:36.824552 <6>[ 0.811446] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10495 09:25:36.827812 <6>[ 0.820289] kvm [1]: IPA Size Limit: 40 bits
10496 09:25:36.834502 <6>[ 0.824817] kvm [1]: GICv3: no GICV resource entry
10497 09:25:36.838001 <6>[ 0.829836] kvm [1]: disabling GICv2 emulation
10498 09:25:36.844203 <6>[ 0.834525] kvm [1]: GIC system register CPU interface enabled
10499 09:25:36.847843 <6>[ 0.840683] kvm [1]: vgic interrupt IRQ18
10500 09:25:36.854328 <6>[ 0.845040] kvm [1]: VHE mode initialized successfully
10501 09:25:36.860846 <5>[ 0.851474] Initialise system trusted keyrings
10502 09:25:36.867181 <6>[ 0.856323] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10503 09:25:36.874265 <6>[ 0.866411] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10504 09:25:36.881166 <5>[ 0.872816] NFS: Registering the id_resolver key type
10505 09:25:36.884698 <5>[ 0.878113] Key type id_resolver registered
10506 09:25:36.890866 <5>[ 0.882527] Key type id_legacy registered
10507 09:25:36.897441 <6>[ 0.886805] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10508 09:25:36.904611 <6>[ 0.893724] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10509 09:25:36.919020 <6>[ 0.901472] 9p: Installing v9fs 9p2000 file system support
10510 09:25:36.947064 <5>[ 0.938956] Key type asymmetric registered
10511 09:25:36.950419 <5>[ 0.943285] Asymmetric key parser 'x509' registered
10512 09:25:36.960389 <6>[ 0.948428] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10513 09:25:36.963875 <6>[ 0.956045] io scheduler mq-deadline registered
10514 09:25:36.966812 <6>[ 0.960823] io scheduler kyber registered
10515 09:25:36.985944 <6>[ 0.977702] EINJ: ACPI disabled.
10516 09:25:37.018556 <4>[ 1.003867] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10517 09:25:37.028346 <4>[ 1.014523] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10518 09:25:37.044506 <6>[ 1.036260] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10519 09:25:37.052009 <6>[ 1.044359] printk: console [ttyS0] disabled
10520 09:25:37.080628 <6>[ 1.068997] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10521 09:25:37.087109 <6>[ 1.078482] printk: console [ttyS0] enabled
10522 09:25:37.090450 <6>[ 1.078482] printk: console [ttyS0] enabled
10523 09:25:37.097170 <6>[ 1.087380] printk: bootconsole [mtk8250] disabled
10524 09:25:37.100586 <6>[ 1.087380] printk: bootconsole [mtk8250] disabled
10525 09:25:37.106871 <6>[ 1.098630] SuperH (H)SCI(F) driver initialized
10526 09:25:37.110222 <6>[ 1.103904] msm_serial: driver initialized
10527 09:25:37.124688 <6>[ 1.112938] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10528 09:25:37.134226 <6>[ 1.121486] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10529 09:25:37.140956 <6>[ 1.130031] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10530 09:25:37.150640 <6>[ 1.138657] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10531 09:25:37.160993 <6>[ 1.147370] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10532 09:25:37.167447 <6>[ 1.156085] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10533 09:25:37.177225 <6>[ 1.164632] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10534 09:25:37.184227 <6>[ 1.173433] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10535 09:25:37.194140 <6>[ 1.181977] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10536 09:25:37.206132 <6>[ 1.197781] loop: module loaded
10537 09:25:37.212756 <6>[ 1.203769] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10538 09:25:37.235729 <4>[ 1.227407] mtk-pmic-keys: Failed to locate of_node [id: -1]
10539 09:25:37.242494 <6>[ 1.234491] megasas: 07.719.03.00-rc1
10540 09:25:37.257935 <6>[ 1.243996] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10541 09:25:37.259130 <6>[ 1.250080] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10542 09:25:37.275177 <6>[ 1.266831] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10543 09:25:37.331925 <6>[ 1.317091] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10544 09:25:37.583811 <6>[ 1.575902] Freeing initrd memory: 18300K
10545 09:25:37.595368 <6>[ 1.587575] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10546 09:25:37.606649 <6>[ 1.598259] tun: Universal TUN/TAP device driver, 1.6
10547 09:25:37.609723 <6>[ 1.604310] thunder_xcv, ver 1.0
10548 09:25:37.613487 <6>[ 1.607813] thunder_bgx, ver 1.0
10549 09:25:37.616128 <6>[ 1.611323] nicpf, ver 1.0
10550 09:25:37.626891 <6>[ 1.615333] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10551 09:25:37.630224 <6>[ 1.622810] hns3: Copyright (c) 2017 Huawei Corporation.
10552 09:25:37.633626 <6>[ 1.628396] hclge is initializing
10553 09:25:37.640024 <6>[ 1.631971] e1000: Intel(R) PRO/1000 Network Driver
10554 09:25:37.646971 <6>[ 1.637101] e1000: Copyright (c) 1999-2006 Intel Corporation.
10555 09:25:37.650599 <6>[ 1.643113] e1000e: Intel(R) PRO/1000 Network Driver
10556 09:25:37.656500 <6>[ 1.648329] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10557 09:25:37.663654 <6>[ 1.654519] igb: Intel(R) Gigabit Ethernet Network Driver
10558 09:25:37.670172 <6>[ 1.660170] igb: Copyright (c) 2007-2014 Intel Corporation.
10559 09:25:37.677249 <6>[ 1.666005] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10560 09:25:37.680300 <6>[ 1.672523] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10561 09:25:37.687364 <6>[ 1.678980] sky2: driver version 1.30
10562 09:25:37.693525 <6>[ 1.683906] usbcore: registered new device driver r8152-cfgselector
10563 09:25:37.700483 <6>[ 1.690439] usbcore: registered new interface driver r8152
10564 09:25:37.704016 <6>[ 1.696254] VFIO - User Level meta-driver version: 0.3
10565 09:25:37.712413 <6>[ 1.704469] usbcore: registered new interface driver usb-storage
10566 09:25:37.719127 <6>[ 1.710910] usbcore: registered new device driver onboard-usb-hub
10567 09:25:37.728118 <6>[ 1.720064] mt6397-rtc mt6359-rtc: registered as rtc0
10568 09:25:37.738423 <6>[ 1.725538] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-18T09:25:37 UTC (1718702737)
10569 09:25:37.741169 <6>[ 1.735136] i2c_dev: i2c /dev entries driver
10570 09:25:37.755440 <4>[ 1.747192] cpu cpu0: supply cpu not found, using dummy regulator
10571 09:25:37.761713 <4>[ 1.753620] cpu cpu1: supply cpu not found, using dummy regulator
10572 09:25:37.768673 <4>[ 1.760027] cpu cpu2: supply cpu not found, using dummy regulator
10573 09:25:37.775000 <4>[ 1.766427] cpu cpu3: supply cpu not found, using dummy regulator
10574 09:25:37.781950 <4>[ 1.772844] cpu cpu4: supply cpu not found, using dummy regulator
10575 09:25:37.788726 <4>[ 1.779243] cpu cpu5: supply cpu not found, using dummy regulator
10576 09:25:37.795183 <4>[ 1.785642] cpu cpu6: supply cpu not found, using dummy regulator
10577 09:25:37.801904 <4>[ 1.792040] cpu cpu7: supply cpu not found, using dummy regulator
10578 09:25:37.821203 <6>[ 1.812697] cpu cpu0: EM: created perf domain
10579 09:25:37.823918 <6>[ 1.817638] cpu cpu4: EM: created perf domain
10580 09:25:37.831607 <6>[ 1.823181] sdhci: Secure Digital Host Controller Interface driver
10581 09:25:37.838287 <6>[ 1.829610] sdhci: Copyright(c) Pierre Ossman
10582 09:25:37.844509 <6>[ 1.834566] Synopsys Designware Multimedia Card Interface Driver
10583 09:25:37.851484 <6>[ 1.841221] sdhci-pltfm: SDHCI platform and OF driver helper
10584 09:25:37.855145 <6>[ 1.841346] mmc0: CQHCI version 5.10
10585 09:25:37.861529 <6>[ 1.851305] ledtrig-cpu: registered to indicate activity on CPUs
10586 09:25:37.867830 <6>[ 1.858279] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10587 09:25:37.874691 <6>[ 1.865348] usbcore: registered new interface driver usbhid
10588 09:25:37.878184 <6>[ 1.871181] usbhid: USB HID core driver
10589 09:25:37.884491 <6>[ 1.875372] spi_master spi0: will run message pump with realtime priority
10590 09:25:37.931198 <6>[ 1.916508] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10591 09:25:37.949924 <6>[ 1.931875] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10592 09:25:37.953436 <6>[ 1.940261] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10593 09:25:37.961216 <6>[ 1.953212] cros-ec-spi spi0.0: Chrome EC device registered
10594 09:25:37.967700 <6>[ 1.959242] mmc0: Command Queue Engine enabled
10595 09:25:37.974631 <6>[ 1.963990] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10596 09:25:37.980802 <6>[ 1.971867] mmcblk0: mmc0:0001 DA4128 116 GiB
10597 09:25:37.990483 <6>[ 1.982650] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10598 09:25:37.998669 <6>[ 1.990400] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10599 09:25:38.008486 <6>[ 1.994296] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10600 09:25:38.011980 <6>[ 1.996341] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10601 09:25:38.018254 <6>[ 2.006468] NET: Registered PF_PACKET protocol family
10602 09:25:38.025110 <6>[ 2.010993] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10603 09:25:38.028416 <6>[ 2.015544] 9pnet: Installing 9P2000 support
10604 09:25:38.034931 <5>[ 2.026584] Key type dns_resolver registered
10605 09:25:38.038594 <6>[ 2.031666] registered taskstats version 1
10606 09:25:38.045226 <5>[ 2.036063] Loading compiled-in X.509 certificates
10607 09:25:38.074186 <4>[ 2.059140] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10608 09:25:38.083686 <4>[ 2.069913] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10609 09:25:38.097991 <6>[ 2.090058] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10610 09:25:38.104754 <6>[ 2.097014] xhci-mtk 11200000.usb: xHCI Host Controller
10611 09:25:38.111557 <6>[ 2.102519] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10612 09:25:38.121466 <6>[ 2.110393] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10613 09:25:38.128673 <6>[ 2.119830] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10614 09:25:38.134923 <6>[ 2.126022] xhci-mtk 11200000.usb: xHCI Host Controller
10615 09:25:38.141719 <6>[ 2.131525] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10616 09:25:38.148906 <6>[ 2.139178] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10617 09:25:38.155147 <6>[ 2.146950] hub 1-0:1.0: USB hub found
10618 09:25:38.158204 <6>[ 2.150971] hub 1-0:1.0: 1 port detected
10619 09:25:38.164985 <6>[ 2.155251] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10620 09:25:38.171853 <6>[ 2.163913] hub 2-0:1.0: USB hub found
10621 09:25:38.175224 <6>[ 2.167933] hub 2-0:1.0: 1 port detected
10622 09:25:38.182891 <6>[ 2.175008] mtk-msdc 11f70000.mmc: Got CD GPIO
10623 09:25:38.196725 <6>[ 2.184859] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10624 09:25:38.202994 <6>[ 2.193231] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10625 09:25:38.212704 <6>[ 2.201570] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10626 09:25:38.219617 <6>[ 2.209914] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10627 09:25:38.229866 <6>[ 2.218252] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10628 09:25:38.236264 <6>[ 2.226591] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10629 09:25:38.246220 <6>[ 2.234930] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10630 09:25:38.253103 <6>[ 2.243268] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10631 09:25:38.262765 <6>[ 2.251611] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10632 09:25:38.269841 <6>[ 2.259950] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10633 09:25:38.279907 <6>[ 2.268288] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10634 09:25:38.289472 <6>[ 2.276631] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10635 09:25:38.296478 <6>[ 2.284969] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10636 09:25:38.306410 <6>[ 2.293307] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10637 09:25:38.312733 <6>[ 2.301645] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10638 09:25:38.319517 <6>[ 2.310363] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10639 09:25:38.325808 <6>[ 2.317566] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10640 09:25:38.332546 <6>[ 2.324345] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10641 09:25:38.339407 <6>[ 2.331146] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10642 09:25:38.349396 <6>[ 2.338078] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10643 09:25:38.355944 <6>[ 2.344974] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10644 09:25:38.366438 <6>[ 2.354109] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10645 09:25:38.376207 <6>[ 2.363231] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10646 09:25:38.386045 <6>[ 2.372525] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10647 09:25:38.396055 <6>[ 2.381992] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10648 09:25:38.402199 <6>[ 2.391459] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10649 09:25:38.412216 <6>[ 2.400579] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10650 09:25:38.422343 <6>[ 2.410045] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10651 09:25:38.432766 <6>[ 2.419164] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10652 09:25:38.442413 <6>[ 2.428460] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10653 09:25:38.452167 <6>[ 2.438622] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10654 09:25:38.462273 <6>[ 2.450498] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10655 09:25:38.469270 <6>[ 2.461642] Trying to probe devices needed for running init ...
10656 09:25:38.480480 <3>[ 2.468923] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10657 09:25:38.589627 <6>[ 2.578844] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10658 09:25:38.745042 <6>[ 2.736840] hub 1-1:1.0: USB hub found
10659 09:25:38.748186 <6>[ 2.741396] hub 1-1:1.0: 4 ports detected
10660 09:25:38.760306 <6>[ 2.752462] hub 1-1:1.0: USB hub found
10661 09:25:38.763627 <6>[ 2.756752] hub 1-1:1.0: 4 ports detected
10662 09:25:38.870464 <6>[ 2.859199] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10663 09:25:38.897016 <6>[ 2.889220] hub 2-1:1.0: USB hub found
10664 09:25:38.900463 <6>[ 2.893723] hub 2-1:1.0: 3 ports detected
10665 09:25:38.912922 <6>[ 2.904833] hub 2-1:1.0: USB hub found
10666 09:25:38.915710 <6>[ 2.909330] hub 2-1:1.0: 3 ports detected
10667 09:25:39.086357 <6>[ 3.075015] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10668 09:25:39.218671 <6>[ 3.210798] hub 1-1.4:1.0: USB hub found
10669 09:25:39.221861 <6>[ 3.215460] hub 1-1.4:1.0: 2 ports detected
10670 09:25:39.236378 <6>[ 3.228320] hub 1-1.4:1.0: USB hub found
10671 09:25:39.239863 <6>[ 3.232886] hub 1-1.4:1.0: 2 ports detected
10672 09:25:39.298648 <6>[ 3.287206] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10673 09:25:39.406704 <6>[ 3.395648] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10674 09:25:39.442491 <4>[ 3.431282] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10675 09:25:39.452138 <4>[ 3.440405] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10676 09:25:39.492052 <6>[ 3.484498] r8152 2-1.3:1.0 eth0: v1.12.13
10677 09:25:39.546263 <6>[ 3.526809] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10678 09:25:39.730098 <6>[ 3.718846] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10679 09:25:41.246871 <6>[ 5.239396] r8152 2-1.3:1.0 eth0: carrier on
10680 09:25:43.478564 <5>[ 5.270809] Sending DHCP requests .., OK
10681 09:25:43.484897 <6>[ 7.475079] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10682 09:25:43.488461 <6>[ 7.483369] IP-Config: Complete:
10683 09:25:43.498289 <6>[ 7.486863] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10684 09:25:43.508568 <6>[ 7.497572] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10685 09:25:43.515195 <6>[ 7.506191] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10686 09:25:43.521685 <6>[ 7.506200] nameserver0=192.168.201.1
10687 09:25:43.525023 <6>[ 7.518333] clk: Disabling unused clocks
10688 09:25:43.528490 <6>[ 7.523855] ALSA device list:
10689 09:25:43.531843 <6>[ 7.527131] No soundcards found.
10690 09:25:43.542437 <6>[ 7.534950] Freeing unused kernel memory: 8512K
10691 09:25:43.545597 <6>[ 7.539911] Run /init as init process
10692 09:25:43.554774 Loading, please wait...
10693 09:25:43.581651 Starting systemd-udevd version 252.22-1~deb12u1
10694 09:25:43.808936 <6>[ 7.798556] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10695 09:25:43.833602 <6>[ 7.822988] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10696 09:25:43.840375 <6>[ 7.828419] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10697 09:25:43.850616 <6>[ 7.831127] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10698 09:25:43.856826 <6>[ 7.838891] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10699 09:25:43.866813 <4>[ 7.847599] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10700 09:25:43.876578 <6>[ 7.855669] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10701 09:25:43.883774 <6>[ 7.857089] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10702 09:25:43.890154 <4>[ 7.857882] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10703 09:25:43.896676 <4>[ 7.858052] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10704 09:25:43.906576 <3>[ 7.861022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 09:25:43.913489 <3>[ 7.862111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 09:25:43.923081 <3>[ 7.862119] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 09:25:43.930115 <6>[ 7.865484] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10708 09:25:43.940227 <3>[ 7.875405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 09:25:43.942883 <6>[ 7.879071] remoteproc remoteproc0: scp is available
10710 09:25:43.949976 <6>[ 7.879226] remoteproc remoteproc0: powering up scp
10711 09:25:43.956202 <6>[ 7.879238] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10712 09:25:43.962980 <6>[ 7.879274] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10713 09:25:43.969999 <6>[ 7.880714] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10714 09:25:43.979849 <3>[ 7.888017] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 09:25:43.985934 <3>[ 7.888024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 09:25:43.996816 <3>[ 7.888031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 09:25:44.003576 <3>[ 7.888035] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 09:25:44.010239 <3>[ 7.907758] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 09:25:44.021328 <6>[ 7.913575] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10720 09:25:44.024775 <6>[ 7.918808] mc: Linux media interface: v0.10
10721 09:25:44.031107 <3>[ 7.932384] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 09:25:44.040867 <6>[ 7.936109] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10723 09:25:44.047490 <3>[ 7.941285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 09:25:44.050865 <6>[ 7.945023] Bluetooth: Core ver 2.22
10725 09:25:44.057872 <6>[ 7.945657] NET: Registered PF_BLUETOOTH protocol family
10726 09:25:44.064191 <6>[ 7.945660] Bluetooth: HCI device and connection manager initialized
10727 09:25:44.067472 <6>[ 7.945676] Bluetooth: HCI socket layer initialized
10728 09:25:44.074456 <6>[ 7.945684] Bluetooth: L2CAP socket layer initialized
10729 09:25:44.077911 <6>[ 7.945697] Bluetooth: SCO socket layer initialized
10730 09:25:44.087576 <6>[ 7.946359] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10731 09:25:44.097322 <6>[ 7.946376] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10732 09:25:44.104111 <6>[ 7.954108] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10733 09:25:44.111100 <3>[ 7.954891] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 09:25:44.120717 <6>[ 7.973991] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10735 09:25:44.127944 <3>[ 7.976632] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 09:25:44.137724 <4>[ 7.980025] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10737 09:25:44.144594 <4>[ 7.980025] Fallback method does not support PEC.
10738 09:25:44.150977 <6>[ 7.992023] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10739 09:25:44.157430 <3>[ 7.992710] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 09:25:44.167795 <3>[ 7.997589] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10741 09:25:44.171097 <6>[ 8.000799] pci_bus 0000:00: root bus resource [bus 00-ff]
10742 09:25:44.180897 <6>[ 8.004938] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10743 09:25:44.187282 <6>[ 8.005050] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10744 09:25:44.194231 <6>[ 8.005056] remoteproc remoteproc0: remote processor scp is now up
10745 09:25:44.203818 <3>[ 8.008862] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 09:25:44.210623 <3>[ 8.008868] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 09:25:44.217601 <3>[ 8.008871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 09:25:44.227361 <6>[ 8.016777] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10749 09:25:44.233956 <3>[ 8.019881] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10750 09:25:44.243693 <3>[ 8.021316] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 09:25:44.253578 <6>[ 8.029376] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10752 09:25:44.263601 <6>[ 8.055012] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10753 09:25:44.270089 <6>[ 8.078947] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10754 09:25:44.277402 <6>[ 8.085166] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10755 09:25:44.283774 <6>[ 8.093833] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10756 09:25:44.290070 <6>[ 8.119536] videodev: Linux video capture interface: v2.00
10757 09:25:44.300364 <6>[ 8.120905] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10758 09:25:44.307228 <6>[ 8.123434] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10759 09:25:44.310665 <6>[ 8.126993] pci 0000:00:00.0: supports D1 D2
10760 09:25:44.316812 <6>[ 8.170827] usbcore: registered new interface driver btusb
10761 09:25:44.327310 <4>[ 8.171645] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10762 09:25:44.333538 <3>[ 8.171657] Bluetooth: hci0: Failed to load firmware file (-2)
10763 09:25:44.340837 <3>[ 8.171662] Bluetooth: hci0: Failed to set up firmware (-2)
10764 09:25:44.350350 <4>[ 8.171667] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10765 09:25:44.357127 <6>[ 8.177041] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10766 09:25:44.366873 <6>[ 8.178236] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10767 09:25:44.373239 <6>[ 8.201090] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10768 09:25:44.380235 <6>[ 8.208330] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10769 09:25:44.389817 <6>[ 8.218055] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10770 09:25:44.399669 <6>[ 8.223399] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10771 09:25:44.406719 <6>[ 8.223857] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10772 09:25:44.410258 <6>[ 8.232328] usbcore: registered new interface driver uvcvideo
10773 09:25:44.419886 <6>[ 8.240246] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10774 09:25:44.426187 <6>[ 8.416511] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10775 09:25:44.429748 <6>[ 8.424087] pci 0000:01:00.0: supports D1 D2
10776 09:25:44.436503 <6>[ 8.428606] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10777 09:25:44.457275 <6>[ 8.446865] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10778 09:25:44.463999 <6>[ 8.453777] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10779 09:25:44.470667 <6>[ 8.461857] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10780 09:25:44.481030 <6>[ 8.469856] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10781 09:25:44.487090 <6>[ 8.477857] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10782 09:25:44.496886 <6>[ 8.485857] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10783 09:25:44.500753 <6>[ 8.493858] pci 0000:00:00.0: PCI bridge to [bus 01]
10784 09:25:44.510253 <6>[ 8.499075] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10785 09:25:44.516966 <6>[ 8.507195] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10786 09:25:44.523887 <6>[ 8.514042] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10787 09:25:44.530122 <6>[ 8.520808] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10788 09:25:44.545250 <5>[ 8.534671] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10789 09:25:44.564404 <5>[ 8.553509] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10790 09:25:44.570399 <5>[ 8.560547] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10791 09:25:44.580524 <4>[ 8.569017] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10792 09:25:44.583654 <6>[ 8.577889] cfg80211: failed to load regulatory.db
10793 09:25:44.626687 <6>[ 8.615858] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10794 09:25:44.632780 <6>[ 8.623356] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10795 09:25:44.654200 <6>[ 8.646842] mt7921e 0000:01:00.0: ASIC revision: 79610010
10796 09:25:44.757263 <6>[ 8.746635] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10797 09:25:44.760622 <6>[ 8.746635]
10798 09:25:44.770890 Begin: Loading essential drivers ... done.
10799 09:25:44.774311 Begin: Running /scripts/init-premount ... done.
10800 09:25:44.781274 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10801 09:25:44.791017 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10802 09:25:44.793815 Device /sys/class/net/eth0 found
10803 09:25:44.793922 done.
10804 09:25:44.810470 Begin: Waiting up to 180 secs for any network device to become available ... done.
10805 09:25:44.841952 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10806 09:25:44.850104 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10807 09:25:44.856911 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10808 09:25:44.863105 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10809 09:25:44.870159 host : mt8192-asurada-spherion-r0-cbg-0
10810 09:25:44.876335 domain : lava-rack
10811 09:25:44.879603 rootserver: 192.168.201.1 rootpath:
10812 09:25:44.882851 filename :
10813 09:25:44.888963 done.
10814 09:25:44.892407 Begin: Running /scripts/nfs-bottom ... done.
10815 09:25:44.908558 Begin: Running /scripts/init-bottom ... done.
10816 09:25:45.027143 <6>[ 9.016803] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10817 09:25:46.214510 <6>[ 10.207404] NET: Registered PF_INET6 protocol family
10818 09:25:46.222453 <6>[ 10.214904] Segment Routing with IPv6
10819 09:25:46.225716 <6>[ 10.218852] In-situ OAM (IOAM) with IPv6
10820 09:25:46.380511 <30>[ 10.346364] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10821 09:25:46.386980 <30>[ 10.379528] systemd[1]: Detected architecture arm64.
10822 09:25:46.393485
10823 09:25:46.396727 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10824 09:25:46.396834
10825 09:25:46.422991 <30>[ 10.415887] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10826 09:25:47.393868 <30>[ 11.383487] systemd[1]: Queued start job for default target graphical.target.
10827 09:25:47.430311 <30>[ 11.420056] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10828 09:25:47.436538 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10829 09:25:47.458996 <30>[ 11.448773] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10830 09:25:47.469133 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10831 09:25:47.487198 <30>[ 11.476742] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10832 09:25:47.496983 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10833 09:25:47.514649 <30>[ 11.504371] systemd[1]: Created slice user.slice - User and Session Slice.
10834 09:25:47.521088 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10835 09:25:47.545413 <30>[ 11.531858] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10836 09:25:47.555147 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10837 09:25:47.572525 <30>[ 11.559235] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10838 09:25:47.579640 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10839 09:25:47.607644 <30>[ 11.587677] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10840 09:25:47.617937 <30>[ 11.607587] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10841 09:25:47.624362 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10842 09:25:47.641724 <30>[ 11.631376] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10843 09:25:47.651366 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10844 09:25:47.669835 <30>[ 11.659500] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10845 09:25:47.679940 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10846 09:25:47.694221 <30>[ 11.687498] systemd[1]: Reached target paths.target - Path Units.
10847 09:25:47.704414 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10848 09:25:47.721905 <30>[ 11.711481] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10849 09:25:47.728370 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10850 09:25:47.742316 <30>[ 11.734987] systemd[1]: Reached target slices.target - Slice Units.
10851 09:25:47.752160 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10852 09:25:47.766306 <30>[ 11.759492] systemd[1]: Reached target swap.target - Swaps.
10853 09:25:47.772739 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10854 09:25:47.793723 <30>[ 11.783498] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10855 09:25:47.803924 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10856 09:25:47.822553 <30>[ 11.811962] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10857 09:25:47.832562 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10858 09:25:47.852177 <30>[ 11.841735] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10859 09:25:47.861905 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10860 09:25:47.878426 <30>[ 11.868308] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10861 09:25:47.888101 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10862 09:25:47.906090 <30>[ 11.895626] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10863 09:25:47.912371 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10864 09:25:47.930769 <30>[ 11.920878] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10865 09:25:47.940886 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10866 09:25:47.960666 <30>[ 11.950268] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10867 09:25:47.970072 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10868 09:25:47.986089 <30>[ 11.975486] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10869 09:25:47.995945 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10870 09:25:48.049172 <30>[ 12.039240] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10871 09:25:48.056280 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10872 09:25:48.077902 <30>[ 12.067672] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10873 09:25:48.084339 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10874 09:25:48.161648 <30>[ 12.151452] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10875 09:25:48.168225 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10876 09:25:48.196042 <30>[ 12.179591] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10877 09:25:48.211634 <30>[ 12.201464] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10878 09:25:48.221339 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10879 09:25:48.243295 <30>[ 12.232740] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10880 09:25:48.249096 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10881 09:25:48.274993 <30>[ 12.264852] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10882 09:25:48.282111 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10883 09:25:48.307178 <30>[ 12.296839] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10884 09:25:48.316846 Startin<6>[ 12.306078] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10885 09:25:48.323428 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10886 09:25:48.347590 <30>[ 12.336992] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10887 09:25:48.356813 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10888 09:25:48.418331 <30>[ 12.407821] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10889 09:25:48.424492 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10890 09:25:48.448871 <30>[ 12.438838] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10891 09:25:48.455930 Startin<6>[ 12.448683] fuse: init (API version 7.37)
10892 09:25:48.462424 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10893 09:25:48.513754 <30>[ 12.503735] systemd[1]: Starting systemd-journald.service - Journal Service...
10894 09:25:48.520331 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10895 09:25:48.553767 <30>[ 12.543777] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10896 09:25:48.560186 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10897 09:25:48.601444 <30>[ 12.587830] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10898 09:25:48.607719 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10899 09:25:48.631952 <30>[ 12.621725] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10900 09:25:48.641949 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10901 09:25:48.662578 <30>[ 12.652108] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10902 09:25:48.672082 <3>[ 12.653702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 09:25:48.678646 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10904 09:25:48.703012 <30>[ 12.692339] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10905 09:25:48.709260 <3>[ 12.694628] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 09:25:48.719444 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10907 09:25:48.737583 <30>[ 12.727418] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10908 09:25:48.747690 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10909 09:25:48.762101 <3>[ 12.751714] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 09:25:48.771675 <30>[ 12.761810] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10911 09:25:48.778886 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10912 09:25:48.792739 <3>[ 12.782639] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 09:25:48.803147 <30>[ 12.793014] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10914 09:25:48.813075 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10915 09:25:48.824485 <3>[ 12.814503] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 09:25:48.835532 <30>[ 12.825550] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10917 09:25:48.842657 <30>[ 12.833734] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10918 09:25:48.855895 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 12.845339] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 09:25:48.862660 onfigfs…[0m - Load Kernel Module configfs.
10920 09:25:48.878568 <30>[ 12.867799] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10921 09:25:48.885066 <30>[ 12.875483] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10922 09:25:48.894901 <3>[ 12.876069] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 09:25:48.901475 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10924 09:25:48.923364 <30>[ 12.912855] systemd[1]: modprobe@drm.service: Deactivated successfully.
10925 09:25:48.929496 <3>[ 12.914664] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 09:25:48.939385 <30>[ 12.920735] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10927 09:25:48.946347 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10928 09:25:48.966726 <30>[ 12.956812] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10929 09:25:48.974536 <30>[ 12.965568] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10930 09:25:48.984935 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10931 09:25:49.001682 <30>[ 12.991721] systemd[1]: Started systemd-journald.service - Journal Service.
10932 09:25:49.008153 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10933 09:25:49.030583 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10934 09:25:49.052253 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10935 09:25:49.071412 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10936 09:25:49.091408 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10937 09:25:49.098842 <4>[ 13.091606] power_supply_show_property: 2 callbacks suppressed
10938 09:25:49.108274 <3>[ 13.091622] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 09:25:49.122580 <4>[ 13.106506] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10940 09:25:49.132334 <3>[ 13.118467] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 09:25:49.138815 <3>[ 13.122133] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10942 09:25:49.149316 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10943 09:25:49.168351 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10944 09:25:49.174808 <3>[ 13.165377] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 09:25:49.187985 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10946 09:25:49.214896 <3>[ 13.204927] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 09:25:49.239262 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10948 09:25:49.249844 <3>[ 13.239487] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 09:25:49.267098 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10950 09:25:49.282158 <3>[ 13.271578] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 09:25:49.296669 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10952 09:25:49.314065 <3>[ 13.303973] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 09:25:49.324141 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10954 09:25:49.348239 <3>[ 13.337952] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 09:25:49.383307 <3>[ 13.373330] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 09:25:49.393945 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10957 09:25:49.416238 <3>[ 13.406038] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 09:25:49.422603 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10959 09:25:49.450249 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10960 09:25:49.473882 [[0;32m OK [0m] Mounted [0;<46>[ 13.462235] systemd-journald[309]: Received client request to flush runtime journal.
10961 09:25:49.476571 1;39msys-kernel-config.… Kernel Configuration File System.
10962 09:25:49.498867 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10963 09:25:49.518791 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10964 09:25:49.538378 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10965 09:25:49.590441 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10966 09:25:50.881787 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10967 09:25:50.914843 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10968 09:25:50.933398 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10969 09:25:50.957053 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10970 09:25:51.010873 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10971 09:25:51.037141 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10972 09:25:51.260228 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10973 09:25:51.322364 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10974 09:25:51.346005 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10975 09:25:51.374154 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10976 09:25:51.443557 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10977 09:25:51.510796 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10978 09:25:51.709851 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10979 09:25:51.759971 <6>[ 15.753317] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10980 09:25:51.783289 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10981 09:25:51.842237 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10982 09:25:51.867016 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10983 09:25:51.932715 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10984 09:25:51.949968 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10985 09:25:51.988036 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10986 09:25:52.008440 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10987 09:25:52.021832 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10988 09:25:52.040776 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10989 09:25:52.069645 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10990 09:25:52.095244 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10991 09:25:52.113396 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10992 09:25:52.166169 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10993 09:25:52.187497 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10994 09:25:52.204790 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10995 09:25:52.220590 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10996 09:25:52.238616 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10997 09:25:52.256591 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10998 09:25:52.272195 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10999 09:25:52.288220 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11000 09:25:52.332547 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11001 09:25:52.364173 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11002 09:25:52.450759 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11003 09:25:52.472604 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11004 09:25:52.500545 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11005 09:25:52.537316 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11006 09:25:52.585308 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11007 09:25:52.605148 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11008 09:25:52.627708 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11009 09:25:52.643562 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11010 09:25:52.662529 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11011 09:25:52.704221 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11012 09:25:52.911550 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11013 09:25:52.934018 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11014 09:25:52.951654 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11015 09:25:52.990838 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11016 09:25:53.036032 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11017 09:25:53.112243
11018 09:25:53.115684 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11019 09:25:53.115755
11020 09:25:53.119121 debian-bookworm-arm64 login: root (automatic login)
11021 09:25:53.119198
11022 09:25:53.330321 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
11023 09:25:53.330427
11024 09:25:53.337286 The programs included with the Debian GNU/Linux system are free software;
11025 09:25:53.344043 the exact distribution terms for each program are described in the
11026 09:25:53.346930 individual files in /usr/share/doc/*/copyright.
11027 09:25:53.347002
11028 09:25:53.353510 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11029 09:25:53.356852 permitted by applicable law.
11030 09:25:53.406868 Matched prompt #10: / #
11032 09:25:53.407111 Setting prompt string to ['/ #']
11033 09:25:53.407201 end: 2.2.5.1 login-action (duration 00:00:18) [common]
11035 09:25:53.407396 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
11036 09:25:53.407487 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11037 09:25:53.407554 Setting prompt string to ['/ #']
11038 09:25:53.407610 Forcing a shell prompt, looking for ['/ #']
11040 09:25:53.457806 / #
11041 09:25:53.457968 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11042 09:25:53.458113 Waiting using forced prompt support (timeout 00:02:30)
11043 09:25:53.462445
11044 09:25:53.462705 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11045 09:25:53.462803 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11047 09:25:53.563110 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407629/extract-nfsrootfs-ggqeh951'
11048 09:25:53.568056 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407629/extract-nfsrootfs-ggqeh951'
11050 09:25:53.668541 / # export NFS_SERVER_IP='192.168.201.1'
11051 09:25:53.673264 export NFS_SERVER_IP='192.168.201.1'
11052 09:25:53.673540 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11053 09:25:53.673650 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11054 09:25:53.673754 end: 2 depthcharge-action (duration 00:01:25) [common]
11055 09:25:53.673848 start: 3 lava-test-retry (timeout 00:30:00) [common]
11056 09:25:53.673933 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11057 09:25:53.674009 Using namespace: common
11059 09:25:53.774293 / # #
11060 09:25:53.774485 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11061 09:25:53.779587 #
11062 09:25:53.779872 Using /lava-14407629
11064 09:25:53.880203 / # export SHELL=/bin/sh
11065 09:25:53.884660 export SHELL=/bin/sh
11067 09:25:53.985144 / # . /lava-14407629/environment
11068 09:25:53.990126 . /lava-14407629/environment
11070 09:25:54.095519 / # /lava-14407629/bin/lava-test-runner /lava-14407629/0
11071 09:25:54.095703 Test shell timeout: 10s (minimum of the action and connection timeout)
11072 09:25:54.101407 /lava-14407629/bin/lava-test-runner /lava-14407629/0
11073 09:25:54.273295 + export TESTRUN_ID=0_lc-compliance
11074 09:25:54.280258 + cd /lava-14407629/0/tests/0_lc-compliance
11075 09:25:54.280378 + cat uuid
11076 09:25:54.283623 + UUID=14407629_1.6.2.3.1
11077 09:25:54.283697 + set +x
11078 09:25:54.290313 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14407629_1.6.2.3.1>
11079 09:25:54.290567 Received signal: <STARTRUN> 0_lc-compliance 14407629_1.6.2.3.1
11080 09:25:54.290648 Starting test lava.0_lc-compliance (14407629_1.6.2.3.1)
11081 09:25:54.290751 Skipping test definition patterns.
11082 09:25:54.293436 + /usr/bin/lc-compliance-parser.sh
11083 09:25:56.091508 [0:00:20.043803731] [414] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11084 09:25:56.094807 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11085 09:25:56.110481 [0:00:20.062892668] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11086 09:25:56.148568 [==========] Running 120 tests from 1 test suite.
11087 09:25:56.166626 [0:00:20.119969151] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11088 09:25:56.199466 [----------] Global test environment set-up.
11089 09:25:56.220953 [0:00:20.175122437] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11090 09:25:56.255227 [----------] 120 tests from CaptureTests/SingleStream
11091 09:25:56.276189 [0:00:20.231324518] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11092 09:25:56.312121 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11093 09:25:56.352942 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11094 09:25:56.353218 Received signal: <TESTSET> START CaptureTests/SingleStream
11095 09:25:56.353292 Starting test_set CaptureTests/SingleStream
11096 09:25:56.356162 Camera needs 4 requests, can't test only 1
11097 09:25:56.412588 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11098 09:25:56.468180
11099 09:25:56.530259 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (57 ms)
11100 09:25:56.599542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11101 09:25:56.599829 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11103 09:25:56.610478 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11104 09:25:56.650453 Camera needs 4 requests, can't test only 2
11105 09:25:56.702873 [0:00:20.664441745] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11106 09:25:56.714569 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11107 09:25:56.772664
11108 09:25:56.830167 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (54 ms)
11109 09:25:56.891319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11110 09:25:56.891615 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11112 09:25:56.903890 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11113 09:25:56.945276 Camera needs 4 requests, can't test only 3
11114 09:25:57.007070 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11115 09:25:57.065240
11116 09:25:57.127650 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (55 ms)
11117 09:25:57.192290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11118 09:25:57.192607 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11120 09:25:57.204802 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11121 09:25:57.244550 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (434 ms)
11122 09:25:57.309170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11123 09:25:57.309439 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11125 09:25:57.319205 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11126 09:25:57.388004 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (703 ms)
11127 09:25:57.397880 [0:00:21.367717303] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11128 09:25:57.460858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11129 09:25:57.461162 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11131 09:25:57.472103 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11132 09:25:58.644639 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1271 ms)
11133 09:25:58.654034 [0:00:22.639382477] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11134 09:25:58.705826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11135 09:25:58.706123 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11137 09:25:58.716821 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11138 09:26:00.460031 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1833 ms)
11139 09:26:00.469437 [0:00:24.473790033] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11140 09:26:00.526622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11141 09:26:00.526949 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11143 09:26:00.537457 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11144 09:26:03.186902 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2747 ms)
11145 09:26:03.196956 [0:00:27.221166950] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11146 09:26:03.258303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11147 09:26:03.258597 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11149 09:26:03.271786 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11150 09:26:07.503591 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4217 ms)
11151 09:26:07.503755 [0:00:31.439321861] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11152 09:26:07.504043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11153 09:26:07.504351 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11155 09:26:07.513033 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11156 09:26:13.781688 <6>[ 37.781076] vpu: disabling
11157 09:26:13.785412 <6>[ 37.784174] vproc2: disabling
11158 09:26:13.788123 <6>[ 37.787488] vproc1: disabling
11159 09:26:13.791364 <6>[ 37.790796] vaud18: disabling
11160 09:26:13.798551 <6>[ 37.794299] vsram_others: disabling
11161 09:26:13.801830 <6>[ 37.798261] va09: disabling
11162 09:26:13.804487 <6>[ 37.801424] vsram_md: disabling
11163 09:26:13.807890 <6>[ 37.804990] Vgpu: disabling
11164 09:26:13.961846 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6592 ms)
11165 09:26:13.971624 [0:00:38.032268169] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11166 09:26:14.027058 [0:00:38.087708407] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11167 09:26:14.029931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11168 09:26:14.030181 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11170 09:26:14.037154 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11171 09:26:14.071777 Camera needs 4 requests, can't test only 1
11172 09:26:14.086118 [0:00:38.147074796] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11173 09:26:14.123814 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11174 09:26:14.140766 [0:00:38.202128018] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11175 09:26:14.174269
11176 09:26:14.228917 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (56 ms)
11177 09:26:14.290890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11178 09:26:14.291177 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11180 09:26:14.308566 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11181 09:26:14.345847 Camera needs 4 requests, can't test only 2
11182 09:26:14.401270 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11183 09:26:14.450725
11184 09:26:14.504564 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (59 ms)
11185 09:26:14.561764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11186 09:26:14.562077 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11188 09:26:14.575053 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11189 09:26:14.614928 Camera needs 4 requests, can't test only 3
11190 09:26:14.669235 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11191 09:26:14.729109
11192 09:26:14.790988 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (55 ms)
11193 09:26:14.839187 [0:00:38.901439452] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11194 09:26:14.862700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11195 09:26:14.862979 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11197 09:26:14.875303 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11198 09:26:14.914530 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (697 ms)
11199 09:26:14.982534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11200 09:26:14.982840 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11202 09:26:14.994362 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11203 09:26:15.738867 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (909 ms)
11204 09:26:15.751952 [0:00:39.811609372] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11205 09:26:15.805187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11206 09:26:15.805469 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11208 09:26:15.816793 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11209 09:26:16.996980 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1259 ms)
11210 09:26:17.010339 [0:00:41.071548917] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11211 09:26:17.064171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11212 09:26:17.064474 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11214 09:26:17.076504 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11215 09:26:18.815015 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1819 ms)
11216 09:26:18.828408 [0:00:42.891245788] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11217 09:26:18.881992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11218 09:26:18.882277 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11220 09:26:18.892859 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11221 09:26:21.544822 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2731 ms)
11222 09:26:21.557476 [0:00:45.622950467] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11223 09:26:21.615109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11224 09:26:21.615412 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11226 09:26:21.624570 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11227 09:26:25.742629 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4199 ms)
11228 09:26:25.755650 [0:00:49.824661079] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11229 09:26:25.808324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11230 09:26:25.808630 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11232 09:26:25.819999 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11233 09:26:32.323359 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6582 ms)
11234 09:26:32.336170 [0:00:56.406721682] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11235 09:26:32.390583 [0:00:56.463607241] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11236 09:26:32.397541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11237 09:26:32.397845 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11239 09:26:32.407588 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11240 09:26:32.446844 [0:00:56.519311428] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11241 09:26:32.450046 Camera needs 4 requests, can't test only 1
11242 09:26:32.503167 [0:00:56.575867948] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11243 09:26:32.506724 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11244 09:26:32.558244
11245 09:26:32.614464 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (58 ms)
11246 09:26:32.678726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11247 09:26:32.679017 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11249 09:26:32.690749 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11250 09:26:32.726051 Camera needs 4 requests, can't test only 2
11251 09:26:32.781164 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11252 09:26:32.839996
11253 09:26:32.905479 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (56 ms)
11254 09:26:32.975773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11255 09:26:32.976089 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11257 09:26:32.987931 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11258 09:26:33.027481 Camera needs 4 requests, can't test only 3
11259 09:26:33.074116 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11260 09:26:33.125895
11261 09:26:33.180324 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (55 ms)
11262 09:26:33.200636 [0:00:57.273230686] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11263 09:26:33.246763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11264 09:26:33.247069 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11266 09:26:33.259911 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11267 09:26:33.299548 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (697 ms)
11268 09:26:33.359151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11269 09:26:33.359442 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11271 09:26:33.371031 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11272 09:26:34.100643 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (909 ms)
11273 09:26:34.114074 [0:00:58.182892170] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11274 09:26:34.181623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11275 09:26:34.181969 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11277 09:26:34.196795 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11278 09:26:35.358223 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1257 ms)
11279 09:26:35.371156 [0:00:59.440377492] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11280 09:26:35.442423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11281 09:26:35.442701 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11283 09:26:35.454336 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11284 09:26:37.175991 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1818 ms)
11285 09:26:37.189620 [0:01:01.258687699] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11286 09:26:37.252374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11287 09:26:37.252653 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11289 09:26:37.265034 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11290 09:26:39.905033 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2729 ms)
11291 09:26:39.918359 [0:01:03.987982039] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11292 09:26:39.984834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11293 09:26:39.985122 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11295 09:26:39.998582 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11296 09:26:44.103072 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4197 ms)
11297 09:26:44.115942 [0:01:08.186444522] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11298 09:26:44.184251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11299 09:26:44.184578 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11301 09:26:44.197121 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11302 09:26:50.681049 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6579 ms)
11303 09:26:50.694322 [0:01:14.765980047] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11304 09:26:50.746756 [0:01:14.822517888] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11305 09:26:50.753294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11306 09:26:50.753577 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11308 09:26:50.763387 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11309 09:26:50.801528 [0:01:14.876967706] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11310 09:26:50.804821 Camera needs 4 requests, can't test only 1
11311 09:26:50.855854 [0:01:14.931370370] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11312 09:26:50.863696 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11313 09:26:50.915089
11314 09:26:50.970522 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (57 ms)
11315 09:26:51.025462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11316 09:26:51.025806 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11318 09:26:51.036375 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11319 09:26:51.076885 Camera needs 4 requests, can't test only 2
11320 09:26:51.130986 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11321 09:26:51.185424
11322 09:26:51.250546 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (55 ms)
11323 09:26:51.316937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11324 09:26:51.317286 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11326 09:26:51.327836 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11327 09:26:51.360463 Camera needs 4 requests, can't test only 3
11328 09:26:51.414268 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11329 09:26:51.467440
11330 09:26:51.523860 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (54 ms)
11331 09:26:51.548698 [0:01:15.624651314] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11332 09:26:51.589295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11333 09:26:51.589573 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11335 09:26:51.601222 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11336 09:26:51.641679 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (693 ms)
11337 09:26:51.706738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11338 09:26:51.707038 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11340 09:26:51.717111 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11341 09:26:52.445389 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (903 ms)
11342 09:26:52.458600 [0:01:16.530010217] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11343 09:26:52.523605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11344 09:26:52.523909 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11346 09:26:52.536697 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11347 09:26:53.702907 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1257 ms)
11348 09:26:53.716304 [0:01:17.787830222] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11349 09:26:53.785805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11350 09:26:53.786181 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11352 09:26:53.799230 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11353 09:26:55.521311 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1818 ms)
11354 09:26:55.534358 [0:01:19.606537553] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11355 09:26:55.597493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11356 09:26:55.597848 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11358 09:26:55.609162 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11359 09:26:58.250209 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2728 ms)
11360 09:26:58.263689 [0:01:22.335595798] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11361 09:26:58.325499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11362 09:26:58.325808 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11364 09:26:58.338029 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11365 09:27:02.448418 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4198 ms)
11366 09:27:02.461505 [0:01:26.534390471] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11367 09:27:02.529365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11368 09:27:02.529648 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11370 09:27:02.542025 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11371 09:27:09.026526 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6578 ms)
11372 09:27:09.039801 [0:01:33.113457192] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11373 09:27:09.093431 [0:01:33.171014702] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11374 09:27:09.100084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11375 09:27:09.100354 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11377 09:27:09.112330 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11378 09:27:09.146506 [0:01:33.224281901] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11379 09:27:09.149955 Camera needs 4 requests, can't test only 1
11380 09:27:09.201190 [0:01:33.278626332] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11381 09:27:09.207889 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11382 09:27:09.253897
11383 09:27:09.299601 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (57 ms)
11384 09:27:09.362863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11385 09:27:09.363162 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11387 09:27:09.375479 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11388 09:27:09.413364 Camera needs 4 requests, can't test only 2
11389 09:27:09.473504 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11390 09:27:09.530638
11391 09:27:09.589115 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (54 ms)
11392 09:27:09.660189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11393 09:27:09.660512 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11395 09:27:09.673065 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11396 09:27:09.708829 Camera needs 4 requests, can't test only 3
11397 09:27:09.763431 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11398 09:27:09.820528
11399 09:27:09.882432 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (52 ms)
11400 09:27:09.943115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11401 09:27:09.943415 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11403 09:27:09.953880 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11404 09:27:11.272862 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2080 ms)
11405 09:27:11.285448 [0:01:35.359602414] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11406 09:27:11.353025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11407 09:27:11.353312 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11409 09:27:11.365210 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11410 09:27:13.990347 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2717 ms)
11411 09:27:14.003351 [0:01:38.079490039] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11412 09:27:14.065656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11413 09:27:14.065958 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11415 09:27:14.076661 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11416 09:27:17.754389 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3764 ms)
11417 09:27:17.767153 [0:01:41.843998657] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11418 09:27:17.828983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11419 09:27:17.829257 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11421 09:27:17.839787 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11422 09:27:23.197863 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5444 ms)
11423 09:27:23.210749 [0:01:47.288075144] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11424 09:27:23.272827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11425 09:27:23.273102 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11427 09:27:23.285505 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11428 09:27:31.373476 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8176 ms)
11429 09:27:31.386614 [0:01:55.465338290] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11430 09:27:31.457126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11431 09:27:31.457411 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11433 09:27:31.469978 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11434 09:27:43.958571 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12586 ms)
11435 09:27:43.971785 [0:02:08.051491033] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11436 09:27:44.035287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11437 09:27:44.035572 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11439 09:27:44.048742 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11440 09:28:03.683672 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19727 ms)
11441 09:28:03.697279 [0:02:27.778853402] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11442 09:28:03.752483 [0:02:27.836438018] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11443 09:28:03.772179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11444 09:28:03.772453 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11446 09:28:03.785515 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11447 09:28:03.808761 [0:02:27.892676941] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11448 09:28:03.832797 Camera needs 4 requests, can't test only 1
11449 09:28:03.863885 [0:02:27.947364633] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11450 09:28:03.902008 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11451 09:28:03.961428
11452 09:28:04.027880 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (58 ms)
11453 09:28:04.100609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11454 09:28:04.100913 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11456 09:28:04.110345 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11457 09:28:04.152492 Camera needs 4 requests, can't test only 2
11458 09:28:04.209313 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11459 09:28:04.276695
11460 09:28:04.346570 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (57 ms)
11461 09:28:04.424248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11462 09:28:04.424541 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11464 09:28:04.434954 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11465 09:28:04.480685 Camera needs 4 requests, can't test only 3
11466 09:28:04.544486 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11467 09:28:04.610527
11468 09:28:04.682969 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (54 ms)
11469 09:28:04.761047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11470 09:28:04.761364 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11472 09:28:04.770834 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11473 09:28:05.940131 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2081 ms)
11474 09:28:05.949733 [0:02:30.029612250] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11475 09:28:06.020106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11476 09:28:06.020402 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11478 09:28:06.030891 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11479 09:28:08.651984 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2712 ms)
11480 09:28:08.662302 [0:02:32.744894251] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11481 09:28:08.743686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11482 09:28:08.743997 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11484 09:28:08.757930 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11485 09:28:12.417046 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3765 ms)
11486 09:28:12.427289 [0:02:36.509861406] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11487 09:28:12.501779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11488 09:28:12.502121 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11490 09:28:12.512903 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11491 09:28:17.860731 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5443 ms)
11492 09:28:17.870491 [0:02:41.954074253] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11493 09:28:17.953440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11494 09:28:17.953792 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11496 09:28:17.965687 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11497 09:28:26.036796 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8176 ms)
11498 09:28:26.047094 [0:02:50.131102562] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11499 09:28:26.129527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11500 09:28:26.129854 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11502 09:28:26.139689 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11503 09:28:38.620631 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12585 ms)
11504 09:28:38.630440 [0:03:02.716349332] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11505 09:28:38.699415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11506 09:28:38.699693 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11508 09:28:38.708342 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11509 09:28:58.346485 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19727 ms)
11510 09:28:58.356662 [0:03:22.444071333] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11511 09:28:58.411028 [0:03:22.500719872] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11512 09:28:58.444731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11513 09:28:58.445399 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11515 09:28:58.458143 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11516 09:28:58.471600 [0:03:22.558998487] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11517 09:28:58.511584 Camera needs 4 requests, can't test only 1
11518 09:28:58.524518 [0:03:22.613696179] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11519 09:28:58.589591 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11520 09:28:58.668775
11521 09:28:58.761344 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (59 ms)
11522 09:28:58.850537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11523 09:28:58.851186 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11525 09:28:58.862810 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11526 09:28:58.914132 Camera needs 4 requests, can't test only 2
11527 09:28:58.975751 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11528 09:28:59.045232
11529 09:28:59.119655 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (55 ms)
11530 09:28:59.205950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11531 09:28:59.206763 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11533 09:28:59.219808 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11534 09:28:59.270613 Camera needs 4 requests, can't test only 3
11535 09:28:59.338740 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11536 09:28:59.402678
11537 09:28:59.482663 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (58 ms)
11538 09:28:59.567541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11539 09:28:59.567818 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11541 09:28:59.578290 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11542 09:29:00.595667 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2075 ms)
11543 09:29:00.604947 [0:03:24.690871487] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11544 09:29:00.691409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11545 09:29:00.692128 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11547 09:29:00.701930 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11548 09:29:03.307086 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2712 ms)
11549 09:29:03.316725 [0:03:27.405274641] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11550 09:29:03.397033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11551 09:29:03.397683 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11553 09:29:03.411130 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11554 09:29:07.070793 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3763 ms)
11555 09:29:07.080558 [0:03:31.169248718] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11556 09:29:07.148932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11557 09:29:07.149299 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11559 09:29:07.159551 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11560 09:29:12.513836 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5444 ms)
11561 09:29:12.524235 [0:03:36.613656565] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11562 09:29:12.598833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11563 09:29:12.599192 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11565 09:29:12.608405 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11566 09:29:20.691085 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8177 ms)
11567 09:29:20.700574 [0:03:44.791239950] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11568 09:29:20.775442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11569 09:29:20.775737 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11571 09:29:20.784514 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11572 09:29:33.273412 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12584 ms)
11573 09:29:33.283542 [0:03:57.375131335] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11574 09:29:33.345471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11575 09:29:33.345829 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11577 09:29:33.354586 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11578 09:29:52.998012 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19726 ms)
11579 09:29:53.007773 [0:04:17.102078798] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11580 09:29:53.063266 [0:04:17.158950490] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11581 09:29:53.069377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11582 09:29:53.069654 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11584 09:29:53.083166 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11585 09:29:53.119454 [0:04:17.215601798] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11586 09:29:53.127303 Camera needs 4 requests, can't test only 1
11587 09:29:53.174730 [0:04:17.270994567] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11588 09:29:53.186013 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11589 09:29:53.240321
11590 09:29:53.300343 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (59 ms)
11591 09:29:53.364275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11592 09:29:53.364549 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11594 09:29:53.370410 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11595 09:29:53.403804 Camera needs 4 requests, can't test only 2
11596 09:29:53.460675 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11597 09:29:53.511486
11598 09:29:53.576024 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (55 ms)
11599 09:29:53.636729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11600 09:29:53.637009 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11602 09:29:53.645334 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11603 09:29:53.686798 Camera needs 4 requests, can't test only 3
11604 09:29:53.743888 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11605 09:29:53.797967
11606 09:29:53.865312 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (57 ms)
11607 09:29:53.930733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11608 09:29:53.931005 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11610 09:29:53.941719 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11611 09:29:55.250122 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2080 ms)
11612 09:29:55.259856 [0:04:19.352252490] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11613 09:29:55.343829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11614 09:29:55.344103 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11616 09:29:55.356741 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11617 09:29:57.962500 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2712 ms)
11618 09:29:57.972446 [0:04:22.066931798] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11619 09:29:58.034060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11620 09:29:58.034340 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11622 09:29:58.043218 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11623 09:30:01.726144 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3763 ms)
11624 09:30:01.735784 [0:04:25.831114029] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11625 09:30:01.790812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11626 09:30:01.791118 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11628 09:30:01.799999 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11629 09:30:07.169933 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5444 ms)
11630 09:30:07.179694 [0:04:31.275541722] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11631 09:30:07.250266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11632 09:30:07.250550 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11634 09:30:07.257868 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11635 09:30:15.345501 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8176 ms)
11636 09:30:15.355545 [0:04:39.452879722] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11637 09:30:15.415045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11638 09:30:15.415325 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11640 09:30:15.421068 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11641 09:30:27.930404 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12586 ms)
11642 09:30:27.940253 [0:04:52.038786261] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11643 09:30:28.003265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11644 09:30:28.003660 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11646 09:30:28.013252 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11647 09:30:47.654199 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19723 ms)
11648 09:30:47.663619 [0:05:11.764938647] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11649 09:30:47.720513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11650 09:30:47.720811 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11652 09:30:47.727644 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11653 09:30:48.070853 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (417 ms)
11654 09:30:48.084208 [0:05:12.184596955] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11655 09:30:48.147411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11656 09:30:48.147706 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11658 09:30:48.159964 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11659 09:30:48.562579 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (490 ms)
11660 09:30:48.575596 [0:05:12.673550032] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11661 09:30:48.637107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11662 09:30:48.637397 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11664 09:30:48.649789 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11665 09:30:49.119925 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (557 ms)
11666 09:30:49.133611 [0:05:13.231606801] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11667 09:30:49.199930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11668 09:30:49.200222 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11670 09:30:49.211940 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11671 09:30:49.818306 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (698 ms)
11672 09:30:49.828262 [0:05:13.929942570] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11673 09:30:49.901380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11674 09:30:49.901666 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11676 09:30:49.913696 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11677 09:30:50.726836 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (907 ms)
11678 09:30:50.736447 [0:05:14.838091109] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11679 09:30:50.803998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11680 09:30:50.804256 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11682 09:30:50.816108 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11683 09:30:51.984507 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1258 ms)
11684 09:30:51.997490 [0:05:16.096393340] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11685 09:30:52.064906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11686 09:30:52.065171 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11688 09:30:52.077687 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11689 09:30:53.803481 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1818 ms)
11690 09:30:53.816780 [0:05:17.914972186] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11691 09:30:53.908254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11692 09:30:53.908985 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11694 09:30:53.923566 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11695 09:30:56.531245 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2728 ms)
11696 09:30:56.544803 [0:05:20.643329725] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11697 09:30:56.626177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11698 09:30:56.626859 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11700 09:30:56.640813 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11701 09:31:00.729721 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4198 ms)
11702 09:31:00.743044 [0:05:24.842157879] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11703 09:31:00.823817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11704 09:31:00.824456 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11706 09:31:00.839302 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11707 09:31:07.308157 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6579 ms)
11708 09:31:07.320946 [0:05:31.421558495] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11709 09:31:07.390057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11710 09:31:07.390319 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11712 09:31:07.402845 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11713 09:31:07.729646 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (417 ms)
11714 09:31:07.739677 [0:05:31.839486648] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11715 09:31:07.817270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11716 09:31:07.817561 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11718 09:31:07.827242 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11719 09:31:08.217699 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (488 ms)
11720 09:31:08.227823 [0:05:32.327936725] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11721 09:31:08.289357 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11723 09:31:08.292552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11724 09:31:08.302192 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11725 09:31:08.776254 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (558 ms)
11726 09:31:08.785755 [0:05:32.886297956] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11727 09:31:08.859839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11728 09:31:08.860107 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11730 09:31:08.867373 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11731 09:31:09.474058 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (697 ms)
11732 09:31:09.484032 [0:05:33.584287802] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11733 09:31:09.560944 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11735 09:31:09.563552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11736 09:31:09.575353 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11737 09:31:10.383619 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (909 ms)
11738 09:31:10.393863 [0:05:34.494195802] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11739 09:31:10.460219 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11741 09:31:10.463470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11742 09:31:10.471830 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11743 09:31:11.642645 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1258 ms)
11744 09:31:11.652041 [0:05:35.752068495] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11745 09:31:11.737869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11746 09:31:11.738697 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11748 09:31:11.749752 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11749 09:31:13.459598 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1817 ms)
11750 09:31:13.469379 [0:05:37.570019418] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11751 09:31:13.538259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11752 09:31:13.538553 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11754 09:31:13.548419 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11755 09:31:16.189024 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2729 ms)
11756 09:31:16.198799 [0:05:40.299488649] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11757 09:31:16.258975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11758 09:31:16.259241 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11760 09:31:16.268165 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11761 09:31:20.386960 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4197 ms)
11762 09:31:20.396799 [0:05:44.498176034] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11763 09:31:20.482454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11764 09:31:20.483106 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11766 09:31:20.493804 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11767 09:31:26.965460 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6579 ms)
11768 09:31:26.974844 [0:05:51.077271419] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11769 09:31:27.058422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11770 09:31:27.059048 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11772 09:31:27.070169 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11773 09:31:27.383521 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (417 ms)
11774 09:31:27.393159 [0:05:51.495307650] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11775 09:31:27.470527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11776 09:31:27.470898 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11778 09:31:27.480713 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11779 09:31:27.871677 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (488 ms)
11780 09:31:27.881346 [0:05:51.983594727] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11781 09:31:27.955826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11782 09:31:27.956106 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11784 09:31:27.964829 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11785 09:31:28.429621 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (558 ms)
11786 09:31:28.439256 [0:05:52.541863496] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11787 09:31:28.524436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11788 09:31:28.525077 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11790 09:31:28.538017 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11791 09:31:29.127792 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (698 ms)
11792 09:31:29.137497 [0:05:53.240048419] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11793 09:31:29.215027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11794 09:31:29.215773 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11796 09:31:29.226491 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11797 09:31:30.037498 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (910 ms)
11798 09:31:30.047525 [0:05:54.150194957] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11799 09:31:30.128236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11800 09:31:30.128511 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11802 09:31:30.136868 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11803 09:31:31.295975 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1258 ms)
11804 09:31:31.305353 [0:05:55.408306496] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11805 09:31:31.391996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11806 09:31:31.392846 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11808 09:31:31.403779 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11809 09:31:33.113951 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1818 ms)
11810 09:31:33.124084 [0:05:57.226793650] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11811 09:31:33.207865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11812 09:31:33.208671 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11814 09:31:33.218675 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11815 09:31:35.842558 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2728 ms)
11816 09:31:35.852050 [0:05:59.955360881] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11817 09:31:35.942533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11818 09:31:35.943312 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11820 09:31:35.955615 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11821 09:31:40.039807 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4198 ms)
11822 09:31:40.050071 [0:06:04.153643573] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11823 09:31:40.134106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11824 09:31:40.134839 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11826 09:31:40.146318 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11827 09:31:46.618491 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6579 ms)
11828 09:31:46.628710 [0:06:10.732264882] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11829 09:31:46.710142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11830 09:31:46.710853 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11832 09:31:46.720792 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11833 09:31:47.036410 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (417 ms)
11834 09:31:47.046338 [0:06:11.150683574] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11835 09:31:47.125248 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11837 09:31:47.128273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11838 09:31:47.139516 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11839 09:31:47.523871 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (487 ms)
11840 09:31:47.533719 [0:06:11.638456651] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11841 09:31:47.596913 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11843 09:31:47.600241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11844 09:31:47.610761 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11845 09:31:48.081012 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (557 ms)
11846 09:31:48.091340 [0:06:12.196225882] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11847 09:31:48.157167 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11849 09:31:48.160481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11850 09:31:48.169715 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11851 09:31:48.779868 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (697 ms)
11852 09:31:48.789455 [0:06:12.894215497] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11853 09:31:48.869352 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11855 09:31:48.872243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11856 09:31:48.884620 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11857 09:31:49.688040 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (908 ms)
11858 09:31:49.697725 [0:06:13.802582497] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11859 09:31:49.777078 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11861 09:31:49.780110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11862 09:31:49.792340 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11863 09:31:50.946110 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1257 ms)
11864 09:31:50.955965 [0:06:15.060675497] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11865 09:31:51.031052 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11867 09:31:51.034142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11868 09:31:51.044722 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11869 09:31:52.764752 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1818 ms)
11870 09:31:52.774382 [0:06:16.879359343] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11871 09:31:52.849516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11872 09:31:52.849816 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11874 09:31:52.862962 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11875 09:31:55.492147 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2728 ms)
11876 09:31:55.502215 [0:06:19.607701959] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11877 09:31:55.596668 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11879 09:31:55.599643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11880 09:31:55.611295 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11881 09:31:59.691102 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4198 ms)
11882 09:31:59.700507 [0:06:23.806710267] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11883 09:31:59.786666 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11885 09:31:59.789633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11886 09:31:59.802511 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11887 09:32:06.269130 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6579 ms)
11888 09:32:06.347644 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11890 09:32:06.350579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11891 09:32:06.360848 [----------] 120 tests from CaptureTests/SingleStream (370322 ms total)
11892 09:32:06.414770
11893 09:32:06.477525 [----------] Global test environment tear-down
11894 09:32:06.540411 [==========] 120 tests from 1 test suite ran. (370323 ms total)
11895 09:32:06.594790 <LAVA_SIGNAL_TESTSET STOP>
11896 09:32:06.594918 + set +x
11897 09:32:06.595152 Received signal: <TESTSET> STOP
11898 09:32:06.595210 Closing test_set CaptureTests/SingleStream
11899 09:32:06.601051 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14407629_1.6.2.3.1>
11900 09:32:06.601296 Received signal: <ENDRUN> 0_lc-compliance 14407629_1.6.2.3.1
11901 09:32:06.601370 Ending use of test pattern.
11902 09:32:06.601425 Ending test lava.0_lc-compliance (14407629_1.6.2.3.1), duration 372.31
11904 09:32:06.604412 <LAVA_TEST_RUNNER EXIT>
11905 09:32:06.604664 ok: lava_test_shell seems to have completed
11906 09:32:06.606313 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11907 09:32:06.606499 end: 3.1 lava-test-shell (duration 00:06:13) [common]
11908 09:32:06.606580 end: 3 lava-test-retry (duration 00:06:13) [common]
11909 09:32:06.606658 start: 4 finalize (timeout 00:10:00) [common]
11910 09:32:06.606734 start: 4.1 power-off (timeout 00:00:30) [common]
11911 09:32:06.606857 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11912 09:32:08.690879 >> Command sent successfully.
11913 09:32:08.693993 Returned 0 in 2 seconds
11914 09:32:08.794387 end: 4.1 power-off (duration 00:00:02) [common]
11916 09:32:08.794693 start: 4.2 read-feedback (timeout 00:09:58) [common]
11917 09:32:08.794982 Listened to connection for namespace 'common' for up to 1s
11918 09:32:09.795883 Finalising connection for namespace 'common'
11919 09:32:09.796053 Disconnecting from shell: Finalise
11920 09:32:09.796141 / #
11921 09:32:09.896395 end: 4.2 read-feedback (duration 00:00:01) [common]
11922 09:32:09.896558 end: 4 finalize (duration 00:00:03) [common]
11923 09:32:09.896689 Cleaning after the job
11924 09:32:09.896793 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/ramdisk
11925 09:32:09.898911 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/kernel
11926 09:32:09.909263 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/dtb
11927 09:32:09.909467 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/nfsrootfs
11928 09:32:09.948214 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407629/tftp-deploy-x56ds326/modules
11929 09:32:09.953752 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407629
11930 09:32:10.211863 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407629
11931 09:32:10.212038 Job finished correctly