Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 20
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 09:27:58.440579 lava-dispatcher, installed at version: 2024.03
2 09:27:58.440821 start: 0 validate
3 09:27:58.440953 Start time: 2024-06-18 09:27:58.440945+00:00 (UTC)
4 09:27:58.441072 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:27:58.441207 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 09:27:58.726094 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:27:58.726270 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:27:58.992851 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:27:58.993035 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:27:59.255692 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:27:59.255878 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:27:59.507441 validate duration: 1.07
14 09:27:59.507736 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:27:59.507852 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:27:59.507943 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:27:59.508065 Not decompressing ramdisk as can be used compressed.
18 09:27:59.508153 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 09:27:59.508218 saving as /var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/ramdisk/rootfs.cpio.gz
20 09:27:59.508282 total size: 28105535 (26 MB)
21 09:27:59.509418 progress 0 % (0 MB)
22 09:27:59.516660 progress 5 % (1 MB)
23 09:27:59.523822 progress 10 % (2 MB)
24 09:27:59.531152 progress 15 % (4 MB)
25 09:27:59.538445 progress 20 % (5 MB)
26 09:27:59.545731 progress 25 % (6 MB)
27 09:27:59.553402 progress 30 % (8 MB)
28 09:27:59.561908 progress 35 % (9 MB)
29 09:27:59.569397 progress 40 % (10 MB)
30 09:27:59.576632 progress 45 % (12 MB)
31 09:27:59.585415 progress 50 % (13 MB)
32 09:27:59.593808 progress 55 % (14 MB)
33 09:27:59.602137 progress 60 % (16 MB)
34 09:27:59.609387 progress 65 % (17 MB)
35 09:27:59.616679 progress 70 % (18 MB)
36 09:27:59.623888 progress 75 % (20 MB)
37 09:27:59.631119 progress 80 % (21 MB)
38 09:27:59.638381 progress 85 % (22 MB)
39 09:27:59.645411 progress 90 % (24 MB)
40 09:27:59.652572 progress 95 % (25 MB)
41 09:27:59.659750 progress 100 % (26 MB)
42 09:27:59.659960 26 MB downloaded in 0.15 s (176.72 MB/s)
43 09:27:59.660122 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:27:59.660372 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:27:59.660463 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:27:59.660558 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:27:59.660696 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:27:59.660771 saving as /var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/kernel/Image
50 09:27:59.660834 total size: 54813184 (52 MB)
51 09:27:59.660897 No compression specified
52 09:27:59.662015 progress 0 % (0 MB)
53 09:27:59.675996 progress 5 % (2 MB)
54 09:27:59.690117 progress 10 % (5 MB)
55 09:27:59.704030 progress 15 % (7 MB)
56 09:27:59.718077 progress 20 % (10 MB)
57 09:27:59.732147 progress 25 % (13 MB)
58 09:27:59.745954 progress 30 % (15 MB)
59 09:27:59.759850 progress 35 % (18 MB)
60 09:27:59.773685 progress 40 % (20 MB)
61 09:27:59.787317 progress 45 % (23 MB)
62 09:27:59.801058 progress 50 % (26 MB)
63 09:27:59.814812 progress 55 % (28 MB)
64 09:27:59.828518 progress 60 % (31 MB)
65 09:27:59.842569 progress 65 % (34 MB)
66 09:27:59.856467 progress 70 % (36 MB)
67 09:27:59.870354 progress 75 % (39 MB)
68 09:27:59.884082 progress 80 % (41 MB)
69 09:27:59.897684 progress 85 % (44 MB)
70 09:27:59.911408 progress 90 % (47 MB)
71 09:27:59.925248 progress 95 % (49 MB)
72 09:27:59.938737 progress 100 % (52 MB)
73 09:27:59.938980 52 MB downloaded in 0.28 s (187.94 MB/s)
74 09:27:59.939132 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:27:59.939371 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:27:59.939458 start: 1.3 download-retry (timeout 00:10:00) [common]
78 09:27:59.939544 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 09:27:59.939675 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:27:59.939750 saving as /var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/dtb/mt8192-asurada-spherion-r0.dtb
81 09:27:59.939813 total size: 47258 (0 MB)
82 09:27:59.939876 No compression specified
83 09:27:59.941030 progress 69 % (0 MB)
84 09:27:59.941313 progress 100 % (0 MB)
85 09:27:59.941469 0 MB downloaded in 0.00 s (27.26 MB/s)
86 09:27:59.941593 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:27:59.941818 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:27:59.941940 start: 1.4 download-retry (timeout 00:10:00) [common]
90 09:27:59.942024 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 09:27:59.942134 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:27:59.942232 saving as /var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/modules/modules.tar
93 09:27:59.942293 total size: 8619356 (8 MB)
94 09:27:59.942355 Using unxz to decompress xz
95 09:27:59.946244 progress 0 % (0 MB)
96 09:27:59.966984 progress 5 % (0 MB)
97 09:27:59.992346 progress 10 % (0 MB)
98 09:28:00.018715 progress 15 % (1 MB)
99 09:28:00.044708 progress 20 % (1 MB)
100 09:28:00.071188 progress 25 % (2 MB)
101 09:28:00.096805 progress 30 % (2 MB)
102 09:28:00.122895 progress 35 % (2 MB)
103 09:28:00.148435 progress 40 % (3 MB)
104 09:28:00.174115 progress 45 % (3 MB)
105 09:28:00.198900 progress 50 % (4 MB)
106 09:28:00.224364 progress 55 % (4 MB)
107 09:28:00.250456 progress 60 % (4 MB)
108 09:28:00.275166 progress 65 % (5 MB)
109 09:28:00.304225 progress 70 % (5 MB)
110 09:28:00.329980 progress 75 % (6 MB)
111 09:28:00.354002 progress 80 % (6 MB)
112 09:28:00.378582 progress 85 % (7 MB)
113 09:28:00.402644 progress 90 % (7 MB)
114 09:28:00.431367 progress 95 % (7 MB)
115 09:28:00.462195 progress 100 % (8 MB)
116 09:28:00.467025 8 MB downloaded in 0.52 s (15.67 MB/s)
117 09:28:00.467276 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:28:00.467561 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:28:00.467670 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 09:28:00.467775 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 09:28:00.467871 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:28:00.467977 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 09:28:00.468239 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6
125 09:28:00.468410 makedir: /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin
126 09:28:00.468580 makedir: /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/tests
127 09:28:00.468734 makedir: /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/results
128 09:28:00.468865 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-add-keys
129 09:28:00.469025 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-add-sources
130 09:28:00.469169 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-background-process-start
131 09:28:00.469315 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-background-process-stop
132 09:28:00.469481 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-common-functions
133 09:28:00.469619 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-echo-ipv4
134 09:28:00.469761 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-install-packages
135 09:28:00.469928 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-installed-packages
136 09:28:00.470091 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-os-build
137 09:28:00.470230 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-probe-channel
138 09:28:00.470367 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-probe-ip
139 09:28:00.470505 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-target-ip
140 09:28:00.470644 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-target-mac
141 09:28:00.470807 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-target-storage
142 09:28:00.470948 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-test-case
143 09:28:00.471089 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-test-event
144 09:28:00.471254 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-test-feedback
145 09:28:00.471417 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-test-raise
146 09:28:00.471553 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-test-reference
147 09:28:00.471691 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-test-runner
148 09:28:00.471828 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-test-set
149 09:28:00.471970 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-test-shell
150 09:28:00.472139 Updating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-install-packages (oe)
151 09:28:00.472294 Updating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/bin/lava-installed-packages (oe)
152 09:28:00.472433 Creating /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/environment
153 09:28:00.472616 LAVA metadata
154 09:28:00.472725 - LAVA_JOB_ID=14407641
155 09:28:00.472830 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:28:00.472977 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 09:28:00.473079 skipped lava-vland-overlay
158 09:28:00.473196 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:28:00.473321 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 09:28:00.473421 skipped lava-multinode-overlay
161 09:28:00.473537 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:28:00.473670 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 09:28:00.473782 Loading test definitions
164 09:28:00.473920 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 09:28:00.474030 Using /lava-14407641 at stage 0
166 09:28:00.474442 uuid=14407641_1.5.2.3.1 testdef=None
167 09:28:00.474570 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:28:00.474696 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 09:28:00.475399 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:28:00.475755 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 09:28:00.476669 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:28:00.476955 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 09:28:00.477558 runner path: /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 14407641_1.5.2.3.1
176 09:28:00.477724 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:28:00.477953 Creating lava-test-runner.conf files
179 09:28:00.478033 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407641/lava-overlay-58qwawv6/lava-14407641/0 for stage 0
180 09:28:00.478148 - 0_v4l2-compliance-mtk-vcodec-enc
181 09:28:00.478287 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 09:28:00.478410 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 09:28:00.485526 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 09:28:00.485711 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 09:28:00.485813 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 09:28:00.485914 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 09:28:00.486043 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 09:28:01.382941 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 09:28:01.383384 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 09:28:01.383537 extracting modules file /var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407641/extract-overlay-ramdisk-3_lseiia/ramdisk
191 09:28:01.613382 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 09:28:01.613554 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 09:28:01.613649 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407641/compress-overlay-crq1rkk9/overlay-1.5.2.4.tar.gz to ramdisk
194 09:28:01.613721 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407641/compress-overlay-crq1rkk9/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407641/extract-overlay-ramdisk-3_lseiia/ramdisk
195 09:28:01.620335 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 09:28:01.620476 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 09:28:01.620634 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 09:28:01.620799 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 09:28:01.620912 Building ramdisk /var/lib/lava/dispatcher/tmp/14407641/extract-overlay-ramdisk-3_lseiia/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407641/extract-overlay-ramdisk-3_lseiia/ramdisk
200 09:28:02.243181 >> 276012 blocks
201 09:28:06.420172 rename /var/lib/lava/dispatcher/tmp/14407641/extract-overlay-ramdisk-3_lseiia/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/ramdisk/ramdisk.cpio.gz
202 09:28:06.420698 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 09:28:06.420863 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 09:28:06.420995 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 09:28:06.421147 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/kernel/Image']
206 09:28:19.860077 Returned 0 in 13 seconds
207 09:28:19.961102 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/kernel/image.itb
208 09:28:20.619794 output: FIT description: Kernel Image image with one or more FDT blobs
209 09:28:20.620160 output: Created: Tue Jun 18 10:28:20 2024
210 09:28:20.620239 output: Image 0 (kernel-1)
211 09:28:20.620307 output: Description:
212 09:28:20.620374 output: Created: Tue Jun 18 10:28:20 2024
213 09:28:20.620436 output: Type: Kernel Image
214 09:28:20.620496 output: Compression: lzma compressed
215 09:28:20.620559 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
216 09:28:20.620655 output: Architecture: AArch64
217 09:28:20.620714 output: OS: Linux
218 09:28:20.620772 output: Load Address: 0x00000000
219 09:28:20.620833 output: Entry Point: 0x00000000
220 09:28:20.620892 output: Hash algo: crc32
221 09:28:20.620953 output: Hash value: 4137a6e7
222 09:28:20.621017 output: Image 1 (fdt-1)
223 09:28:20.621079 output: Description: mt8192-asurada-spherion-r0
224 09:28:20.621141 output: Created: Tue Jun 18 10:28:20 2024
225 09:28:20.621200 output: Type: Flat Device Tree
226 09:28:20.621255 output: Compression: uncompressed
227 09:28:20.621310 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 09:28:20.621365 output: Architecture: AArch64
229 09:28:20.621420 output: Hash algo: crc32
230 09:28:20.621475 output: Hash value: 0f8e4d2e
231 09:28:20.621530 output: Image 2 (ramdisk-1)
232 09:28:20.621585 output: Description: unavailable
233 09:28:20.621640 output: Created: Tue Jun 18 10:28:20 2024
234 09:28:20.621695 output: Type: RAMDisk Image
235 09:28:20.621750 output: Compression: Unknown Compression
236 09:28:20.621805 output: Data Size: 41223829 Bytes = 40257.65 KiB = 39.31 MiB
237 09:28:20.621861 output: Architecture: AArch64
238 09:28:20.621916 output: OS: Linux
239 09:28:20.621971 output: Load Address: unavailable
240 09:28:20.622026 output: Entry Point: unavailable
241 09:28:20.622080 output: Hash algo: crc32
242 09:28:20.622135 output: Hash value: a082e5ec
243 09:28:20.622189 output: Default Configuration: 'conf-1'
244 09:28:20.622244 output: Configuration 0 (conf-1)
245 09:28:20.622299 output: Description: mt8192-asurada-spherion-r0
246 09:28:20.622354 output: Kernel: kernel-1
247 09:28:20.622409 output: Init Ramdisk: ramdisk-1
248 09:28:20.622464 output: FDT: fdt-1
249 09:28:20.622518 output: Loadables: kernel-1
250 09:28:20.622573 output:
251 09:28:20.622772 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 09:28:20.622874 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 09:28:20.622984 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 09:28:20.623081 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 09:28:20.623164 No LXC device requested
256 09:28:20.623245 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 09:28:20.623329 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 09:28:20.623408 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 09:28:20.623481 Checking files for TFTP limit of 4294967296 bytes.
260 09:28:20.623967 end: 1 tftp-deploy (duration 00:00:21) [common]
261 09:28:20.624072 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 09:28:20.624167 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 09:28:20.624291 substitutions:
264 09:28:20.624359 - {DTB}: 14407641/tftp-deploy-kc612fpy/dtb/mt8192-asurada-spherion-r0.dtb
265 09:28:20.624425 - {INITRD}: 14407641/tftp-deploy-kc612fpy/ramdisk/ramdisk.cpio.gz
266 09:28:20.624487 - {KERNEL}: 14407641/tftp-deploy-kc612fpy/kernel/Image
267 09:28:20.624550 - {LAVA_MAC}: None
268 09:28:20.624646 - {PRESEED_CONFIG}: None
269 09:28:20.624705 - {PRESEED_LOCAL}: None
270 09:28:20.624762 - {RAMDISK}: 14407641/tftp-deploy-kc612fpy/ramdisk/ramdisk.cpio.gz
271 09:28:20.624820 - {ROOT_PART}: None
272 09:28:20.624876 - {ROOT}: None
273 09:28:20.624934 - {SERVER_IP}: 192.168.201.1
274 09:28:20.624990 - {TEE}: None
275 09:28:20.625049 Parsed boot commands:
276 09:28:20.625104 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 09:28:20.625274 Parsed boot commands: tftpboot 192.168.201.1 14407641/tftp-deploy-kc612fpy/kernel/image.itb 14407641/tftp-deploy-kc612fpy/kernel/cmdline
278 09:28:20.625368 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 09:28:20.625456 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 09:28:20.625550 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 09:28:20.625638 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 09:28:20.625712 Not connected, no need to disconnect.
283 09:28:20.625788 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 09:28:20.625869 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 09:28:20.625940 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 09:28:20.629173 Setting prompt string to ['lava-test: # ']
287 09:28:20.629501 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 09:28:20.629616 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 09:28:20.629725 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 09:28:20.629817 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 09:28:20.629987 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
292 09:28:34.261857 Returned 0 in 13 seconds
293 09:28:34.362759 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 09:28:34.363072 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 09:28:34.363175 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 09:28:34.363263 Setting prompt string to 'Starting depthcharge on Spherion...'
298 09:28:34.363332 Changing prompt to 'Starting depthcharge on Spherion...'
299 09:28:34.363402 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 09:28:34.363860 [Enter `^Ec?' for help]
301 09:28:34.363943
302 09:28:34.364009
303 09:28:34.364073 F0: 102B 0000
304 09:28:34.364135
305 09:28:34.364194 F3: 1001 0000 [0200]
306 09:28:34.364305
307 09:28:34.364377 F3: 1001 0000
308 09:28:34.364455
309 09:28:34.364512 F7: 102D 0000
310 09:28:34.364595
311 09:28:34.364652 F1: 0000 0000
312 09:28:34.364709
313 09:28:34.364765 V0: 0000 0000 [0001]
314 09:28:34.364821
315 09:28:34.364877 00: 0007 8000
316 09:28:34.364935
317 09:28:34.364991 01: 0000 0000
318 09:28:34.365048
319 09:28:34.365104 BP: 0C00 0209 [0000]
320 09:28:34.365160
321 09:28:34.365215 G0: 1182 0000
322 09:28:34.365271
323 09:28:34.365326 EC: 0000 0021 [4000]
324 09:28:34.365382
325 09:28:34.365437 S7: 0000 0000 [0000]
326 09:28:34.365493
327 09:28:34.365549 CC: 0000 0000 [0001]
328 09:28:34.365604
329 09:28:34.365659 T0: 0000 0040 [010F]
330 09:28:34.365714
331 09:28:34.365770 Jump to BL
332 09:28:34.365827
333 09:28:34.365882
334 09:28:34.365937
335 09:28:34.365993 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 09:28:34.366052 ARM64: Exception handlers installed.
337 09:28:34.366108 ARM64: Testing exception
338 09:28:34.366164 ARM64: Done test exception
339 09:28:34.366236 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 09:28:34.366337 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 09:28:34.366394 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 09:28:34.366450 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 09:28:34.366507 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 09:28:34.366563 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 09:28:34.366619 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 09:28:34.366675 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 09:28:34.366732 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 09:28:34.366789 WDT: Last reset was cold boot
349 09:28:34.366845 SPI1(PAD0) initialized at 2873684 Hz
350 09:28:34.366901 SPI5(PAD0) initialized at 992727 Hz
351 09:28:34.366957 VBOOT: Loading verstage.
352 09:28:34.367013 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 09:28:34.367070 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 09:28:34.367127 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 09:28:34.367183 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 09:28:34.367239 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 09:28:34.367296 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 09:28:34.367353 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 09:28:34.367409
360 09:28:34.367465
361 09:28:34.367520 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 09:28:34.367576 ARM64: Exception handlers installed.
363 09:28:34.367633 ARM64: Testing exception
364 09:28:34.367688 ARM64: Done test exception
365 09:28:34.367743 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 09:28:34.367800 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 09:28:34.367856 Probing TPM: . done!
368 09:28:34.367912 TPM ready after 0 ms
369 09:28:34.367968 Connected to device vid:did:rid of 1ae0:0028:00
370 09:28:34.368024 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
371 09:28:34.368080 Initialized TPM device CR50 revision 0
372 09:28:34.368136 tlcl_send_startup: Startup return code is 0
373 09:28:34.368192 TPM: setup succeeded
374 09:28:34.368248 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 09:28:34.368304 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 09:28:34.368361 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 09:28:34.368417 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 09:28:34.368473 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 09:28:34.368530 in-header: 03 07 00 00 08 00 00 00
380 09:28:34.368629 in-data: aa e4 47 04 13 02 00 00
381 09:28:34.368686 Chrome EC: UHEPI supported
382 09:28:34.368742 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 09:28:34.368799 in-header: 03 a9 00 00 08 00 00 00
384 09:28:34.368855 in-data: 84 60 60 08 00 00 00 00
385 09:28:34.368910 Phase 1
386 09:28:34.368966 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 09:28:34.369023 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 09:28:34.369079 VB2:vb2_check_recovery() Recovery was requested manually
389 09:28:34.369136 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 09:28:34.369191 Recovery requested (1009000e)
391 09:28:34.369247 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 09:28:34.369304 tlcl_extend: response is 0
393 09:28:34.369360 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 09:28:34.369417 tlcl_extend: response is 0
395 09:28:34.369473 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 09:28:34.369530 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 09:28:34.369586 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 09:28:34.369642
399 09:28:34.369697
400 09:28:34.369752 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 09:28:34.369809 ARM64: Exception handlers installed.
402 09:28:34.369865 ARM64: Testing exception
403 09:28:34.369925 ARM64: Done test exception
404 09:28:34.369980 pmic_efuse_setting: Set efuses in 11 msecs
405 09:28:34.370037 pmwrap_interface_init: Select PMIF_VLD_RDY
406 09:28:34.370092 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 09:28:34.370149 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 09:28:34.370394 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 09:28:34.370460 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 09:28:34.370518 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 09:28:34.370574 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 09:28:34.370630 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 09:28:34.370686 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 09:28:34.370741 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 09:28:34.370797 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 09:28:34.370851 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 09:28:34.370906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 09:28:34.370961 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 09:28:34.371016 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 09:28:34.371071 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 09:28:34.371126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 09:28:34.371181 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 09:28:34.371237 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 09:28:34.371294 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 09:28:34.371350 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 09:28:34.371407 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 09:28:34.371463 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 09:28:34.371519 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 09:28:34.371575 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 09:28:34.371631 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 09:28:34.371687 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 09:28:34.371743 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 09:28:34.371799 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 09:28:34.371867 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 09:28:34.371931 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 09:28:34.371988 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 09:28:34.372044 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 09:28:34.372101 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 09:28:34.372157 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 09:28:34.372229 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 09:28:34.372300 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 09:28:34.372356 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 09:28:34.372413 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 09:28:34.372469 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 09:28:34.372525 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 09:28:34.372622 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 09:28:34.372680 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 09:28:34.372736 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 09:28:34.372792 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 09:28:34.372848 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 09:28:34.372903 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 09:28:34.372959 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 09:28:34.373015 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 09:28:34.373071 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 09:28:34.373126 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 09:28:34.373182 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 09:28:34.373238 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 09:28:34.373295 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 09:28:34.373351 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 09:28:34.373407 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 09:28:34.373464 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 09:28:34.373520 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 09:28:34.373577 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 09:28:34.373632 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 09:28:34.373689 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2d
466 09:28:34.373745 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 09:28:34.373801 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 09:28:34.373857 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 09:28:34.373913 [RTC]rtc_get_frequency_meter,154: input=15, output=771
470 09:28:34.373968 [RTC]rtc_get_frequency_meter,154: input=23, output=958
471 09:28:34.374024 [RTC]rtc_get_frequency_meter,154: input=19, output=865
472 09:28:34.374080 [RTC]rtc_get_frequency_meter,154: input=17, output=818
473 09:28:34.374135 [RTC]rtc_get_frequency_meter,154: input=16, output=796
474 09:28:34.374191 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
475 09:28:34.374247 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
476 09:28:34.374315 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
477 09:28:34.374371 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
478 09:28:34.374617 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
479 09:28:34.374684 ADC[4]: Raw value=902507 ID=7
480 09:28:34.374742 ADC[3]: Raw value=212810 ID=1
481 09:28:34.374798 RAM Code: 0x71
482 09:28:34.374855 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
483 09:28:34.374912 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
484 09:28:34.374968 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
485 09:28:34.375026 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
486 09:28:34.375083 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
487 09:28:34.375140 in-header: 03 07 00 00 08 00 00 00
488 09:28:34.375196 in-data: aa e4 47 04 13 02 00 00
489 09:28:34.375252 Chrome EC: UHEPI supported
490 09:28:34.375308 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
491 09:28:34.375364 in-header: 03 a9 00 00 08 00 00 00
492 09:28:34.375420 in-data: 84 60 60 08 00 00 00 00
493 09:28:34.375476 MRC: failed to locate region type 0.
494 09:28:34.375532 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
495 09:28:34.375588 DRAM-K: Running full calibration
496 09:28:34.375644 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
497 09:28:34.375700 header.status = 0x0
498 09:28:34.375756 header.version = 0x6 (expected: 0x6)
499 09:28:34.375812 header.size = 0xd00 (expected: 0xd00)
500 09:28:34.375868 header.flags = 0x0
501 09:28:34.375924 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
502 09:28:34.375980 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
503 09:28:34.376036 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
504 09:28:34.376092 dram_init: ddr_geometry: 2
505 09:28:34.376148 [EMI] MDL number = 2
506 09:28:34.376204 [EMI] Get MDL freq = 0
507 09:28:34.376275 dram_init: ddr_type: 0
508 09:28:34.376344 is_discrete_lpddr4: 1
509 09:28:34.376400 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
510 09:28:34.376455
511 09:28:34.376510
512 09:28:34.376594 [Bian_co] ETT version 0.0.0.1
513 09:28:34.376665 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
514 09:28:34.376721
515 09:28:34.376776 dramc_set_vcore_voltage set vcore to 650000
516 09:28:34.376833 Read voltage for 800, 4
517 09:28:34.376889 Vio18 = 0
518 09:28:34.376944 Vcore = 650000
519 09:28:34.377000 Vdram = 0
520 09:28:34.377055 Vddq = 0
521 09:28:34.377111 Vmddr = 0
522 09:28:34.377166 dram_init: config_dvfs: 1
523 09:28:34.377222 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
524 09:28:34.377278 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
525 09:28:34.377334 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
526 09:28:34.377405 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
527 09:28:34.377466 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
528 09:28:34.377522 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
529 09:28:34.377579 MEM_TYPE=3, freq_sel=18
530 09:28:34.377635 sv_algorithm_assistance_LP4_1600
531 09:28:34.377691 ============ PULL DRAM RESETB DOWN ============
532 09:28:34.377747 ========== PULL DRAM RESETB DOWN end =========
533 09:28:34.377804 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
534 09:28:34.377860 ===================================
535 09:28:34.377916 LPDDR4 DRAM CONFIGURATION
536 09:28:34.377972 ===================================
537 09:28:34.378028 EX_ROW_EN[0] = 0x0
538 09:28:34.378084 EX_ROW_EN[1] = 0x0
539 09:28:34.378140 LP4Y_EN = 0x0
540 09:28:34.378195 WORK_FSP = 0x0
541 09:28:34.378251 WL = 0x2
542 09:28:34.378314 RL = 0x2
543 09:28:34.378370 BL = 0x2
544 09:28:34.378425 RPST = 0x0
545 09:28:34.378481 RD_PRE = 0x0
546 09:28:34.378537 WR_PRE = 0x1
547 09:28:34.378592 WR_PST = 0x0
548 09:28:34.378647 DBI_WR = 0x0
549 09:28:34.378703 DBI_RD = 0x0
550 09:28:34.378758 OTF = 0x1
551 09:28:34.378814 ===================================
552 09:28:34.378870 ===================================
553 09:28:34.378926 ANA top config
554 09:28:34.378982 ===================================
555 09:28:34.379038 DLL_ASYNC_EN = 0
556 09:28:34.379093 ALL_SLAVE_EN = 1
557 09:28:34.379149 NEW_RANK_MODE = 1
558 09:28:34.379207 DLL_IDLE_MODE = 1
559 09:28:34.379263 LP45_APHY_COMB_EN = 1
560 09:28:34.379318 TX_ODT_DIS = 1
561 09:28:34.379374 NEW_8X_MODE = 1
562 09:28:34.379431 ===================================
563 09:28:34.379487 ===================================
564 09:28:34.379543 data_rate = 1600
565 09:28:34.379599 CKR = 1
566 09:28:34.379655 DQ_P2S_RATIO = 8
567 09:28:34.379710 ===================================
568 09:28:34.379766 CA_P2S_RATIO = 8
569 09:28:34.379822 DQ_CA_OPEN = 0
570 09:28:34.379877 DQ_SEMI_OPEN = 0
571 09:28:34.379933 CA_SEMI_OPEN = 0
572 09:28:34.379989 CA_FULL_RATE = 0
573 09:28:34.380045 DQ_CKDIV4_EN = 1
574 09:28:34.380100 CA_CKDIV4_EN = 1
575 09:28:34.380156 CA_PREDIV_EN = 0
576 09:28:34.380212 PH8_DLY = 0
577 09:28:34.380273 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
578 09:28:34.380369 DQ_AAMCK_DIV = 4
579 09:28:34.380466 CA_AAMCK_DIV = 4
580 09:28:34.380578 CA_ADMCK_DIV = 4
581 09:28:34.380658 DQ_TRACK_CA_EN = 0
582 09:28:34.380715 CA_PICK = 800
583 09:28:34.380772 CA_MCKIO = 800
584 09:28:34.380828 MCKIO_SEMI = 0
585 09:28:34.380884 PLL_FREQ = 3068
586 09:28:34.380940 DQ_UI_PI_RATIO = 32
587 09:28:34.380996 CA_UI_PI_RATIO = 0
588 09:28:34.381051 ===================================
589 09:28:34.381107 ===================================
590 09:28:34.381163 memory_type:LPDDR4
591 09:28:34.381219 GP_NUM : 10
592 09:28:34.381275 SRAM_EN : 1
593 09:28:34.381331 MD32_EN : 0
594 09:28:34.381386 ===================================
595 09:28:34.381442 [ANA_INIT] >>>>>>>>>>>>>>
596 09:28:34.381497 <<<<<< [CONFIGURE PHASE]: ANA_TX
597 09:28:34.381555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
598 09:28:34.381611 ===================================
599 09:28:34.381867 data_rate = 1600,PCW = 0X7600
600 09:28:34.381928 ===================================
601 09:28:34.381986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
602 09:28:34.382042 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
603 09:28:34.382099 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 09:28:34.382170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
605 09:28:34.382230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
606 09:28:34.382287 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
607 09:28:34.382343 [ANA_INIT] flow start
608 09:28:34.382399 [ANA_INIT] PLL >>>>>>>>
609 09:28:34.382455 [ANA_INIT] PLL <<<<<<<<
610 09:28:34.382511 [ANA_INIT] MIDPI >>>>>>>>
611 09:28:34.382567 [ANA_INIT] MIDPI <<<<<<<<
612 09:28:34.382623 [ANA_INIT] DLL >>>>>>>>
613 09:28:34.382678 [ANA_INIT] flow end
614 09:28:34.382734 ============ LP4 DIFF to SE enter ============
615 09:28:34.382791 ============ LP4 DIFF to SE exit ============
616 09:28:34.382847 [ANA_INIT] <<<<<<<<<<<<<
617 09:28:34.382903 [Flow] Enable top DCM control >>>>>
618 09:28:34.382958 [Flow] Enable top DCM control <<<<<
619 09:28:34.383014 Enable DLL master slave shuffle
620 09:28:34.383070 ==============================================================
621 09:28:34.383126 Gating Mode config
622 09:28:34.383181 ==============================================================
623 09:28:34.383237 Config description:
624 09:28:34.383293 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
625 09:28:34.383351 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
626 09:28:34.383407 SELPH_MODE 0: By rank 1: By Phase
627 09:28:34.383464 ==============================================================
628 09:28:34.383520 GAT_TRACK_EN = 1
629 09:28:34.383576 RX_GATING_MODE = 2
630 09:28:34.383631 RX_GATING_TRACK_MODE = 2
631 09:28:34.383687 SELPH_MODE = 1
632 09:28:34.383743 PICG_EARLY_EN = 1
633 09:28:34.383799 VALID_LAT_VALUE = 1
634 09:28:34.383855 ==============================================================
635 09:28:34.383911 Enter into Gating configuration >>>>
636 09:28:34.383967 Exit from Gating configuration <<<<
637 09:28:34.384023 Enter into DVFS_PRE_config >>>>>
638 09:28:34.384079 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
639 09:28:34.384138 Exit from DVFS_PRE_config <<<<<
640 09:28:34.384194 Enter into PICG configuration >>>>
641 09:28:34.384249 Exit from PICG configuration <<<<
642 09:28:34.384305 [RX_INPUT] configuration >>>>>
643 09:28:34.384360 [RX_INPUT] configuration <<<<<
644 09:28:34.384416 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
645 09:28:34.384472 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
646 09:28:34.384528 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
647 09:28:34.384628 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
648 09:28:34.384684 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
649 09:28:34.384740 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
650 09:28:34.384797 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
651 09:28:34.384852 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
652 09:28:34.384908 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
653 09:28:34.384991 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
654 09:28:34.385069 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
655 09:28:34.385139 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
656 09:28:34.385196 ===================================
657 09:28:34.385252 LPDDR4 DRAM CONFIGURATION
658 09:28:34.385308 ===================================
659 09:28:34.385364 EX_ROW_EN[0] = 0x0
660 09:28:34.385428 EX_ROW_EN[1] = 0x0
661 09:28:34.385492 LP4Y_EN = 0x0
662 09:28:34.385550 WORK_FSP = 0x0
663 09:28:34.385609 WL = 0x2
664 09:28:34.385704 RL = 0x2
665 09:28:34.385764 BL = 0x2
666 09:28:34.385821 RPST = 0x0
667 09:28:34.385877 RD_PRE = 0x0
668 09:28:34.385932 WR_PRE = 0x1
669 09:28:34.385988 WR_PST = 0x0
670 09:28:34.386044 DBI_WR = 0x0
671 09:28:34.386099 DBI_RD = 0x0
672 09:28:34.386155 OTF = 0x1
673 09:28:34.386211 ===================================
674 09:28:34.386268 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
675 09:28:34.386324 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
676 09:28:34.386380 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
677 09:28:34.386437 ===================================
678 09:28:34.386493 LPDDR4 DRAM CONFIGURATION
679 09:28:34.386549 ===================================
680 09:28:34.386604 EX_ROW_EN[0] = 0x10
681 09:28:34.386660 EX_ROW_EN[1] = 0x0
682 09:28:34.386716 LP4Y_EN = 0x0
683 09:28:34.386771 WORK_FSP = 0x0
684 09:28:34.386827 WL = 0x2
685 09:28:34.386882 RL = 0x2
686 09:28:34.386939 BL = 0x2
687 09:28:34.386994 RPST = 0x0
688 09:28:34.387050 RD_PRE = 0x0
689 09:28:34.387105 WR_PRE = 0x1
690 09:28:34.387161 WR_PST = 0x0
691 09:28:34.387217 DBI_WR = 0x0
692 09:28:34.387272 DBI_RD = 0x0
693 09:28:34.387328 OTF = 0x1
694 09:28:34.387384 ===================================
695 09:28:34.387441 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
696 09:28:34.387497 nWR fixed to 40
697 09:28:34.387553 [ModeRegInit_LP4] CH0 RK0
698 09:28:34.387609 [ModeRegInit_LP4] CH0 RK1
699 09:28:34.387664 [ModeRegInit_LP4] CH1 RK0
700 09:28:34.387720 [ModeRegInit_LP4] CH1 RK1
701 09:28:34.387775 match AC timing 13
702 09:28:34.387831 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
703 09:28:34.387887 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
704 09:28:34.387943 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
705 09:28:34.387999 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
706 09:28:34.388249 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
707 09:28:34.388311 [EMI DOE] emi_dcm 0
708 09:28:34.388368 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
709 09:28:34.388425 ==
710 09:28:34.388481 Dram Type= 6, Freq= 0, CH_0, rank 0
711 09:28:34.388537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
712 09:28:34.388635 ==
713 09:28:34.388691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
714 09:28:34.388747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
715 09:28:34.388804 [CA 0] Center 38 (7~69) winsize 63
716 09:28:34.388860 [CA 1] Center 38 (7~69) winsize 63
717 09:28:34.388916 [CA 2] Center 35 (5~66) winsize 62
718 09:28:34.388971 [CA 3] Center 35 (4~66) winsize 63
719 09:28:34.389026 [CA 4] Center 34 (4~65) winsize 62
720 09:28:34.389082 [CA 5] Center 33 (3~64) winsize 62
721 09:28:34.389137
722 09:28:34.389193 [CmdBusTrainingLP45] Vref(ca) range 1: 34
723 09:28:34.389249
724 09:28:34.389304 [CATrainingPosCal] consider 1 rank data
725 09:28:34.389360 u2DelayCellTimex100 = 270/100 ps
726 09:28:34.389415 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
727 09:28:34.389471 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
728 09:28:34.389527 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
729 09:28:34.389583 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
730 09:28:34.389639 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
731 09:28:34.389694 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
732 09:28:34.389750
733 09:28:34.389806 CA PerBit enable=1, Macro0, CA PI delay=33
734 09:28:34.389862
735 09:28:34.389917 [CBTSetCACLKResult] CA Dly = 33
736 09:28:34.389973 CS Dly: 5 (0~36)
737 09:28:34.390028 ==
738 09:28:34.390084 Dram Type= 6, Freq= 0, CH_0, rank 1
739 09:28:34.390140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
740 09:28:34.390196 ==
741 09:28:34.390252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
742 09:28:34.390308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
743 09:28:34.390363 [CA 0] Center 38 (7~69) winsize 63
744 09:28:34.390419 [CA 1] Center 38 (7~69) winsize 63
745 09:28:34.390475 [CA 2] Center 36 (6~67) winsize 62
746 09:28:34.390531 [CA 3] Center 35 (5~66) winsize 62
747 09:28:34.390586 [CA 4] Center 35 (4~66) winsize 63
748 09:28:34.390642 [CA 5] Center 34 (4~65) winsize 62
749 09:28:34.390698
750 09:28:34.390753 [CmdBusTrainingLP45] Vref(ca) range 1: 32
751 09:28:34.390809
752 09:28:34.390865 [CATrainingPosCal] consider 2 rank data
753 09:28:34.390921 u2DelayCellTimex100 = 270/100 ps
754 09:28:34.390976 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
755 09:28:34.391032 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
756 09:28:34.391088 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
757 09:28:34.391144 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
758 09:28:34.391200 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
759 09:28:34.391256 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
760 09:28:34.391312
761 09:28:34.391367 CA PerBit enable=1, Macro0, CA PI delay=34
762 09:28:34.391423
763 09:28:34.391479 [CBTSetCACLKResult] CA Dly = 34
764 09:28:34.391534 CS Dly: 6 (0~38)
765 09:28:34.391590
766 09:28:34.391645 ----->DramcWriteLeveling(PI) begin...
767 09:28:34.391702 ==
768 09:28:34.391759 Dram Type= 6, Freq= 0, CH_0, rank 0
769 09:28:34.391815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
770 09:28:34.391871 ==
771 09:28:34.391927 Write leveling (Byte 0): 30 => 30
772 09:28:34.391983 Write leveling (Byte 1): 28 => 28
773 09:28:34.392039 DramcWriteLeveling(PI) end<-----
774 09:28:34.392095
775 09:28:34.392150 ==
776 09:28:34.392205 Dram Type= 6, Freq= 0, CH_0, rank 0
777 09:28:34.392261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
778 09:28:34.392317 ==
779 09:28:34.392372 [Gating] SW mode calibration
780 09:28:34.392428 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
781 09:28:34.392484 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
782 09:28:34.392540 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
783 09:28:34.392644 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
784 09:28:34.392700 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
785 09:28:34.392865 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 09:28:34.392961 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 09:28:34.393024 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 09:28:34.393093 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 09:28:34.393182 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 09:28:34.393268 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 09:28:34.393355 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 09:28:34.393442 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 09:28:34.393528 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 09:28:34.393616 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 09:28:34.393699 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 09:28:34.393771 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 09:28:34.393828 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 09:28:34.393884 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
799 09:28:34.393940 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 09:28:34.393996 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 09:28:34.394052 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 09:28:34.394108 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 09:28:34.394164 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 09:28:34.394220 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 09:28:34.394276 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 09:28:34.394344 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 09:28:34.394449 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
808 09:28:34.394511 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
809 09:28:34.394569 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
810 09:28:34.394626 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 09:28:34.394683 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 09:28:34.394740 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 09:28:34.394796 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 09:28:34.395049 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
815 09:28:34.395114 0 10 4 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
816 09:28:34.395177 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (1 1) (0 0)
817 09:28:34.395233 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
818 09:28:34.395290 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 09:28:34.395346 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 09:28:34.395402 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 09:28:34.395458 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 09:28:34.395514 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 09:28:34.395570 0 11 4 | B1->B0 | 2323 3636 | 0 1 | (0 0) (1 1)
824 09:28:34.395626 0 11 8 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
825 09:28:34.395682 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
826 09:28:34.395739 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 09:28:34.395794 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 09:28:34.395856 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 09:28:34.395954 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 09:28:34.396016 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 09:28:34.396073 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 09:28:34.396130 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
833 09:28:34.396185 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 09:28:34.396241 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 09:28:34.396297 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 09:28:34.396353 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 09:28:34.396409 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 09:28:34.396465 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 09:28:34.396521 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 09:28:34.396619 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 09:28:34.396675 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 09:28:34.396732 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 09:28:34.396788 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:28:34.396844 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 09:28:34.396899 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 09:28:34.396956 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 09:28:34.397012 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
848 09:28:34.397068 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
849 09:28:34.397124 Total UI for P1: 0, mck2ui 16
850 09:28:34.397180 best dqsien dly found for B0: ( 0, 14, 4)
851 09:28:34.397236 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 09:28:34.397292 Total UI for P1: 0, mck2ui 16
853 09:28:34.397348 best dqsien dly found for B1: ( 0, 14, 8)
854 09:28:34.397404 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
855 09:28:34.397460 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
856 09:28:34.397516
857 09:28:34.397572 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
858 09:28:34.397628 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
859 09:28:34.397684 [Gating] SW calibration Done
860 09:28:34.397740 ==
861 09:28:34.397796 Dram Type= 6, Freq= 0, CH_0, rank 0
862 09:28:34.397852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 09:28:34.397909 ==
864 09:28:34.397964 RX Vref Scan: 0
865 09:28:34.398020
866 09:28:34.398100 RX Vref 0 -> 0, step: 1
867 09:28:34.398160
868 09:28:34.398229 RX Delay -130 -> 252, step: 16
869 09:28:34.398285 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
870 09:28:34.398341 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
871 09:28:34.398398 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
872 09:28:34.398453 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
873 09:28:34.398509 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
874 09:28:34.398564 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
875 09:28:34.398620 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
876 09:28:34.398676 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
877 09:28:34.398732 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
878 09:28:34.398787 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
879 09:28:34.398843 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
880 09:28:34.398899 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
881 09:28:34.398956 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
882 09:28:34.399020 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
883 09:28:34.399084 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 09:28:34.399148 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
885 09:28:34.399211 ==
886 09:28:34.399275 Dram Type= 6, Freq= 0, CH_0, rank 0
887 09:28:34.399338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 09:28:34.399402 ==
889 09:28:34.399465 DQS Delay:
890 09:28:34.399528 DQS0 = 0, DQS1 = 0
891 09:28:34.399589 DQM Delay:
892 09:28:34.399652 DQM0 = 89, DQM1 = 80
893 09:28:34.399714 DQ Delay:
894 09:28:34.399777 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
895 09:28:34.399840 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
896 09:28:34.399903 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
897 09:28:34.399966 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
898 09:28:34.400027
899 09:28:34.400089
900 09:28:34.400150 ==
901 09:28:34.400213 Dram Type= 6, Freq= 0, CH_0, rank 0
902 09:28:34.400275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 09:28:34.400338 ==
904 09:28:34.400399
905 09:28:34.400461
906 09:28:34.400521 TX Vref Scan disable
907 09:28:34.400628 == TX Byte 0 ==
908 09:28:34.400688 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
909 09:28:34.400747 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
910 09:28:34.400805 == TX Byte 1 ==
911 09:28:34.400862 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
912 09:28:34.400919 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
913 09:28:34.400976 ==
914 09:28:34.401033 Dram Type= 6, Freq= 0, CH_0, rank 0
915 09:28:34.401090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 09:28:34.401146 ==
917 09:28:34.401203 TX Vref=22, minBit 11, minWin=26, winSum=442
918 09:28:34.401260 TX Vref=24, minBit 8, minWin=27, winSum=447
919 09:28:34.401316 TX Vref=26, minBit 6, minWin=27, winSum=450
920 09:28:34.401372 TX Vref=28, minBit 9, minWin=27, winSum=453
921 09:28:34.401429 TX Vref=30, minBit 9, minWin=27, winSum=456
922 09:28:34.401679 TX Vref=32, minBit 8, minWin=28, winSum=459
923 09:28:34.401742 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 32
924 09:28:34.401800
925 09:28:34.401857 Final TX Range 1 Vref 32
926 09:28:34.401914
927 09:28:34.401970 ==
928 09:28:34.402026 Dram Type= 6, Freq= 0, CH_0, rank 0
929 09:28:34.402082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 09:28:34.402138 ==
931 09:28:34.402194
932 09:28:34.402249
933 09:28:34.402304 TX Vref Scan disable
934 09:28:34.402360 == TX Byte 0 ==
935 09:28:34.402416 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
936 09:28:34.402472 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
937 09:28:34.402528 == TX Byte 1 ==
938 09:28:34.402583 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
939 09:28:34.402639 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
940 09:28:34.402694
941 09:28:34.402750 [DATLAT]
942 09:28:34.402805 Freq=800, CH0 RK0
943 09:28:34.402866
944 09:28:34.402921 DATLAT Default: 0xa
945 09:28:34.402976 0, 0xFFFF, sum = 0
946 09:28:34.403034 1, 0xFFFF, sum = 0
947 09:28:34.403090 2, 0xFFFF, sum = 0
948 09:28:34.403146 3, 0xFFFF, sum = 0
949 09:28:34.403202 4, 0xFFFF, sum = 0
950 09:28:34.403258 5, 0xFFFF, sum = 0
951 09:28:34.403314 6, 0xFFFF, sum = 0
952 09:28:34.403370 7, 0xFFFF, sum = 0
953 09:28:34.403426 8, 0xFFFF, sum = 0
954 09:28:34.403482 9, 0x0, sum = 1
955 09:28:34.403538 10, 0x0, sum = 2
956 09:28:34.403595 11, 0x0, sum = 3
957 09:28:34.403651 12, 0x0, sum = 4
958 09:28:34.403707 best_step = 10
959 09:28:34.403762
960 09:28:34.403817 ==
961 09:28:34.403872 Dram Type= 6, Freq= 0, CH_0, rank 0
962 09:28:34.403928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 09:28:34.403984 ==
964 09:28:34.404040 RX Vref Scan: 1
965 09:28:34.404095
966 09:28:34.404151 Set Vref Range= 32 -> 127
967 09:28:34.404207
968 09:28:34.404262 RX Vref 32 -> 127, step: 1
969 09:28:34.404317
970 09:28:34.404373 RX Delay -95 -> 252, step: 8
971 09:28:34.404428
972 09:28:34.404484 Set Vref, RX VrefLevel [Byte0]: 32
973 09:28:34.404539 [Byte1]: 32
974 09:28:34.404640
975 09:28:34.404696 Set Vref, RX VrefLevel [Byte0]: 33
976 09:28:34.404752 [Byte1]: 33
977 09:28:34.404808
978 09:28:34.404863 Set Vref, RX VrefLevel [Byte0]: 34
979 09:28:34.404918 [Byte1]: 34
980 09:28:34.404973
981 09:28:34.405029 Set Vref, RX VrefLevel [Byte0]: 35
982 09:28:34.405085 [Byte1]: 35
983 09:28:34.405140
984 09:28:34.405196 Set Vref, RX VrefLevel [Byte0]: 36
985 09:28:34.405252 [Byte1]: 36
986 09:28:34.405307
987 09:28:34.405363 Set Vref, RX VrefLevel [Byte0]: 37
988 09:28:34.405418 [Byte1]: 37
989 09:28:34.405474
990 09:28:34.405529 Set Vref, RX VrefLevel [Byte0]: 38
991 09:28:34.405585 [Byte1]: 38
992 09:28:34.405640
993 09:28:34.405696 Set Vref, RX VrefLevel [Byte0]: 39
994 09:28:34.405751 [Byte1]: 39
995 09:28:34.405807
996 09:28:34.405862 Set Vref, RX VrefLevel [Byte0]: 40
997 09:28:34.405918 [Byte1]: 40
998 09:28:34.405973
999 09:28:34.406028 Set Vref, RX VrefLevel [Byte0]: 41
1000 09:28:34.406084 [Byte1]: 41
1001 09:28:34.406139
1002 09:28:34.406195 Set Vref, RX VrefLevel [Byte0]: 42
1003 09:28:34.406251 [Byte1]: 42
1004 09:28:34.406305
1005 09:28:34.406361 Set Vref, RX VrefLevel [Byte0]: 43
1006 09:28:34.406417 [Byte1]: 43
1007 09:28:34.406472
1008 09:28:34.406526 Set Vref, RX VrefLevel [Byte0]: 44
1009 09:28:34.406582 [Byte1]: 44
1010 09:28:34.406637
1011 09:28:34.406692 Set Vref, RX VrefLevel [Byte0]: 45
1012 09:28:34.406748 [Byte1]: 45
1013 09:28:34.406803
1014 09:28:34.406859 Set Vref, RX VrefLevel [Byte0]: 46
1015 09:28:34.406915 [Byte1]: 46
1016 09:28:34.406971
1017 09:28:34.407027 Set Vref, RX VrefLevel [Byte0]: 47
1018 09:28:34.407084 [Byte1]: 47
1019 09:28:34.407140
1020 09:28:34.407195 Set Vref, RX VrefLevel [Byte0]: 48
1021 09:28:34.407251 [Byte1]: 48
1022 09:28:34.407306
1023 09:28:34.407361 Set Vref, RX VrefLevel [Byte0]: 49
1024 09:28:34.407417 [Byte1]: 49
1025 09:28:34.407478
1026 09:28:34.407537 Set Vref, RX VrefLevel [Byte0]: 50
1027 09:28:34.407593 [Byte1]: 50
1028 09:28:34.407649
1029 09:28:34.407703 Set Vref, RX VrefLevel [Byte0]: 51
1030 09:28:34.407759 [Byte1]: 51
1031 09:28:34.407815
1032 09:28:34.407870 Set Vref, RX VrefLevel [Byte0]: 52
1033 09:28:34.407924 [Byte1]: 52
1034 09:28:34.407980
1035 09:28:34.408034 Set Vref, RX VrefLevel [Byte0]: 53
1036 09:28:34.408089 [Byte1]: 53
1037 09:28:34.408144
1038 09:28:34.408198 Set Vref, RX VrefLevel [Byte0]: 54
1039 09:28:34.408253 [Byte1]: 54
1040 09:28:34.408308
1041 09:28:34.408363 Set Vref, RX VrefLevel [Byte0]: 55
1042 09:28:34.408418 [Byte1]: 55
1043 09:28:34.408472
1044 09:28:34.408527 Set Vref, RX VrefLevel [Byte0]: 56
1045 09:28:34.408619 [Byte1]: 56
1046 09:28:34.408675
1047 09:28:34.408729 Set Vref, RX VrefLevel [Byte0]: 57
1048 09:28:34.408784 [Byte1]: 57
1049 09:28:34.408839
1050 09:28:34.408894 Set Vref, RX VrefLevel [Byte0]: 58
1051 09:28:34.408948 [Byte1]: 58
1052 09:28:34.409003
1053 09:28:34.409058 Set Vref, RX VrefLevel [Byte0]: 59
1054 09:28:34.409112 [Byte1]: 59
1055 09:28:34.409167
1056 09:28:34.409221 Set Vref, RX VrefLevel [Byte0]: 60
1057 09:28:34.409276 [Byte1]: 60
1058 09:28:34.409332
1059 09:28:34.409386 Set Vref, RX VrefLevel [Byte0]: 61
1060 09:28:34.409441 [Byte1]: 61
1061 09:28:34.409497
1062 09:28:34.409552 Set Vref, RX VrefLevel [Byte0]: 62
1063 09:28:34.409607 [Byte1]: 62
1064 09:28:34.409661
1065 09:28:34.409715 Set Vref, RX VrefLevel [Byte0]: 63
1066 09:28:34.409770 [Byte1]: 63
1067 09:28:34.409825
1068 09:28:34.409880 Set Vref, RX VrefLevel [Byte0]: 64
1069 09:28:34.409935 [Byte1]: 64
1070 09:28:34.409990
1071 09:28:34.410044 Set Vref, RX VrefLevel [Byte0]: 65
1072 09:28:34.410099 [Byte1]: 65
1073 09:28:34.410154
1074 09:28:34.410208 Set Vref, RX VrefLevel [Byte0]: 66
1075 09:28:34.410263 [Byte1]: 66
1076 09:28:34.410318
1077 09:28:34.410372 Set Vref, RX VrefLevel [Byte0]: 67
1078 09:28:34.410427 [Byte1]: 67
1079 09:28:34.410481
1080 09:28:34.410536 Set Vref, RX VrefLevel [Byte0]: 68
1081 09:28:34.410590 [Byte1]: 68
1082 09:28:34.410645
1083 09:28:34.410699 Set Vref, RX VrefLevel [Byte0]: 69
1084 09:28:34.410754 [Byte1]: 69
1085 09:28:34.410809
1086 09:28:34.410863 Set Vref, RX VrefLevel [Byte0]: 70
1087 09:28:34.410919 [Byte1]: 70
1088 09:28:34.410973
1089 09:28:34.411027 Set Vref, RX VrefLevel [Byte0]: 71
1090 09:28:34.411082 [Byte1]: 71
1091 09:28:34.411137
1092 09:28:34.411192 Set Vref, RX VrefLevel [Byte0]: 72
1093 09:28:34.411440 [Byte1]: 72
1094 09:28:34.411502
1095 09:28:34.411558 Set Vref, RX VrefLevel [Byte0]: 73
1096 09:28:34.411614 [Byte1]: 73
1097 09:28:34.411669
1098 09:28:34.411723 Set Vref, RX VrefLevel [Byte0]: 74
1099 09:28:34.411778 [Byte1]: 74
1100 09:28:34.411849
1101 09:28:34.411919 Set Vref, RX VrefLevel [Byte0]: 75
1102 09:28:34.411974 [Byte1]: 75
1103 09:28:34.412029
1104 09:28:34.412084 Set Vref, RX VrefLevel [Byte0]: 76
1105 09:28:34.412139 [Byte1]: 76
1106 09:28:34.412193
1107 09:28:34.412247 Set Vref, RX VrefLevel [Byte0]: 77
1108 09:28:34.412302 [Byte1]: 77
1109 09:28:34.412356
1110 09:28:34.412410 Final RX Vref Byte 0 = 62 to rank0
1111 09:28:34.412465 Final RX Vref Byte 1 = 60 to rank0
1112 09:28:34.412521 Final RX Vref Byte 0 = 62 to rank1
1113 09:28:34.412622 Final RX Vref Byte 1 = 60 to rank1==
1114 09:28:34.412678 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 09:28:34.412734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 09:28:34.412790 ==
1117 09:28:34.412845 DQS Delay:
1118 09:28:34.412900 DQS0 = 0, DQS1 = 0
1119 09:28:34.412954 DQM Delay:
1120 09:28:34.413009 DQM0 = 93, DQM1 = 82
1121 09:28:34.413064 DQ Delay:
1122 09:28:34.413120 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1123 09:28:34.413175 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1124 09:28:34.413230 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1125 09:28:34.413285 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1126 09:28:34.413340
1127 09:28:34.413394
1128 09:28:34.413449 [DQSOSCAuto] RK0, (LSB)MR18= 0x403b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
1129 09:28:34.413505 CH0 RK0: MR19=606, MR18=403B
1130 09:28:34.413561 CH0_RK0: MR19=0x606, MR18=0x403B, DQSOSC=393, MR23=63, INC=95, DEC=63
1131 09:28:34.413616
1132 09:28:34.413671 ----->DramcWriteLeveling(PI) begin...
1133 09:28:34.413727 ==
1134 09:28:34.413782 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 09:28:34.413837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 09:28:34.413893 ==
1137 09:28:34.413948 Write leveling (Byte 0): 32 => 32
1138 09:28:34.414002 Write leveling (Byte 1): 28 => 28
1139 09:28:34.414058 DramcWriteLeveling(PI) end<-----
1140 09:28:34.414113
1141 09:28:34.414167 ==
1142 09:28:34.414222 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 09:28:34.414277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 09:28:34.414333 ==
1145 09:28:34.414387 [Gating] SW mode calibration
1146 09:28:34.414443 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 09:28:34.414498 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 09:28:34.414554 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 09:28:34.414609 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1150 09:28:34.414664 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1151 09:28:34.414719 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 09:28:34.414775 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 09:28:34.414829 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 09:28:34.414885 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 09:28:34.414940 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 09:28:34.414995 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 09:28:34.415049 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 09:28:34.415104 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 09:28:34.415160 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 09:28:34.415215 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 09:28:34.415269 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 09:28:34.415324 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 09:28:34.415379 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 09:28:34.415434 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1165 09:28:34.415489 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1166 09:28:34.415544 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 09:28:34.415599 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 09:28:34.415654 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 09:28:34.415709 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 09:28:34.415763 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 09:28:34.415818 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 09:28:34.415873 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 09:28:34.415928 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1174 09:28:34.415983 0 9 8 | B1->B0 | 2e2e 3333 | 0 0 | (0 0) (0 0)
1175 09:28:34.416038 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 09:28:34.416092 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 09:28:34.416147 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 09:28:34.416202 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 09:28:34.416256 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 09:28:34.416311 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 09:28:34.416398 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1182 09:28:34.416453 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
1183 09:28:34.416508 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 09:28:34.416600 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 09:28:34.416657 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 09:28:34.416713 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 09:28:34.416768 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 09:28:34.416823 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 09:28:34.416878 0 11 4 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
1190 09:28:34.416933 0 11 8 | B1->B0 | 3a39 4646 | 1 0 | (0 0) (0 0)
1191 09:28:34.416988 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 09:28:34.417043 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 09:28:34.417099 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 09:28:34.417154 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 09:28:34.417209 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 09:28:34.417264 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 09:28:34.417514 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1198 09:28:34.417578 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1199 09:28:34.417635 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 09:28:34.417691 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 09:28:34.417748 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 09:28:34.417803 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 09:28:34.417859 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 09:28:34.417915 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 09:28:34.417970 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 09:28:34.418026 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 09:28:34.418082 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 09:28:34.418137 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 09:28:34.418192 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 09:28:34.418247 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 09:28:34.418302 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 09:28:34.418357 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 09:28:34.418443 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1214 09:28:34.418497 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1215 09:28:34.418552 Total UI for P1: 0, mck2ui 16
1216 09:28:34.418608 best dqsien dly found for B0: ( 0, 14, 4)
1217 09:28:34.418663 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 09:28:34.418718 Total UI for P1: 0, mck2ui 16
1219 09:28:34.418773 best dqsien dly found for B1: ( 0, 14, 8)
1220 09:28:34.418829 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1221 09:28:34.418884 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1222 09:28:34.418939
1223 09:28:34.418994 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1224 09:28:34.419049 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 09:28:34.419104 [Gating] SW calibration Done
1226 09:28:34.419159 ==
1227 09:28:34.419214 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 09:28:34.419270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 09:28:34.419325 ==
1230 09:28:34.419380 RX Vref Scan: 0
1231 09:28:34.419435
1232 09:28:34.419489 RX Vref 0 -> 0, step: 1
1233 09:28:34.419544
1234 09:28:34.419598 RX Delay -130 -> 252, step: 16
1235 09:28:34.419653 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1236 09:28:34.419708 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1237 09:28:34.419763 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1238 09:28:34.419818 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1239 09:28:34.419873 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1240 09:28:34.419927 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1241 09:28:34.419982 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1242 09:28:34.420037 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1243 09:28:34.420092 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1244 09:28:34.420147 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1245 09:28:34.420202 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1246 09:28:34.420257 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1247 09:28:34.420312 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1248 09:28:34.420367 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1249 09:28:34.420422 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1250 09:28:34.420476 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1251 09:28:34.420531 ==
1252 09:28:34.420631 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 09:28:34.420688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 09:28:34.420744 ==
1255 09:28:34.420799 DQS Delay:
1256 09:28:34.420854 DQS0 = 0, DQS1 = 0
1257 09:28:34.420909 DQM Delay:
1258 09:28:34.420964 DQM0 = 90, DQM1 = 79
1259 09:28:34.421018 DQ Delay:
1260 09:28:34.421073 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1261 09:28:34.421128 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =101
1262 09:28:34.421183 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1263 09:28:34.421238 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =85
1264 09:28:34.421293
1265 09:28:34.421347
1266 09:28:34.421402 ==
1267 09:28:34.421457 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 09:28:34.421512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 09:28:34.421568 ==
1270 09:28:34.421622
1271 09:28:34.421677
1272 09:28:34.421731 TX Vref Scan disable
1273 09:28:34.421786 == TX Byte 0 ==
1274 09:28:34.421841 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1275 09:28:34.421897 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1276 09:28:34.421953 == TX Byte 1 ==
1277 09:28:34.422008 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1278 09:28:34.422063 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1279 09:28:34.422118 ==
1280 09:28:34.422173 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 09:28:34.422228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 09:28:34.422284 ==
1283 09:28:34.422338 TX Vref=22, minBit 1, minWin=27, winSum=445
1284 09:28:34.422395 TX Vref=24, minBit 8, minWin=27, winSum=453
1285 09:28:34.422450 TX Vref=26, minBit 8, minWin=27, winSum=452
1286 09:28:34.422506 TX Vref=28, minBit 4, minWin=28, winSum=456
1287 09:28:34.422561 TX Vref=30, minBit 8, minWin=28, winSum=459
1288 09:28:34.422616 TX Vref=32, minBit 10, minWin=27, winSum=457
1289 09:28:34.422672 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1290 09:28:34.422727
1291 09:28:34.422782 Final TX Range 1 Vref 30
1292 09:28:34.422837
1293 09:28:34.422892 ==
1294 09:28:34.422945 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 09:28:34.422999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 09:28:34.423053 ==
1297 09:28:34.423106
1298 09:28:34.423159
1299 09:28:34.423212 TX Vref Scan disable
1300 09:28:34.423266 == TX Byte 0 ==
1301 09:28:34.423319 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1302 09:28:34.423373 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1303 09:28:34.423427 == TX Byte 1 ==
1304 09:28:34.423480 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1305 09:28:34.423534 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1306 09:28:34.423587
1307 09:28:34.423641 [DATLAT]
1308 09:28:34.423693 Freq=800, CH0 RK1
1309 09:28:34.423747
1310 09:28:34.423799 DATLAT Default: 0xa
1311 09:28:34.423852 0, 0xFFFF, sum = 0
1312 09:28:34.423907 1, 0xFFFF, sum = 0
1313 09:28:34.423961 2, 0xFFFF, sum = 0
1314 09:28:34.424016 3, 0xFFFF, sum = 0
1315 09:28:34.424070 4, 0xFFFF, sum = 0
1316 09:28:34.424124 5, 0xFFFF, sum = 0
1317 09:28:34.424177 6, 0xFFFF, sum = 0
1318 09:28:34.424231 7, 0xFFFF, sum = 0
1319 09:28:34.424285 8, 0xFFFF, sum = 0
1320 09:28:34.424340 9, 0x0, sum = 1
1321 09:28:34.424394 10, 0x0, sum = 2
1322 09:28:34.424449 11, 0x0, sum = 3
1323 09:28:34.424503 12, 0x0, sum = 4
1324 09:28:34.424581 best_step = 10
1325 09:28:34.424650
1326 09:28:34.424703 ==
1327 09:28:34.424756 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 09:28:34.425003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 09:28:34.425064 ==
1330 09:28:34.425119 RX Vref Scan: 0
1331 09:28:34.425173
1332 09:28:34.425226 RX Vref 0 -> 0, step: 1
1333 09:28:34.425279
1334 09:28:34.425333 RX Delay -79 -> 252, step: 8
1335 09:28:34.425386 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1336 09:28:34.425440 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1337 09:28:34.425494 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1338 09:28:34.425549 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1339 09:28:34.425602 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1340 09:28:34.425655 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1341 09:28:34.425709 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1342 09:28:34.425762 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1343 09:28:34.425815 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1344 09:28:34.425869 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1345 09:28:34.425922 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1346 09:28:34.425976 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1347 09:28:34.426029 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1348 09:28:34.426083 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1349 09:28:34.426136 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1350 09:28:34.426189 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1351 09:28:34.426242 ==
1352 09:28:34.426296 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 09:28:34.426350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 09:28:34.426403 ==
1355 09:28:34.426456 DQS Delay:
1356 09:28:34.426509 DQS0 = 0, DQS1 = 0
1357 09:28:34.426563 DQM Delay:
1358 09:28:34.426615 DQM0 = 90, DQM1 = 81
1359 09:28:34.426668 DQ Delay:
1360 09:28:34.426721 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1361 09:28:34.426785 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1362 09:28:34.426842 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1363 09:28:34.426896 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1364 09:28:34.426949
1365 09:28:34.427002
1366 09:28:34.427056 [DQSOSCAuto] RK1, (LSB)MR18= 0x451e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1367 09:28:34.427111 CH0 RK1: MR19=606, MR18=451E
1368 09:28:34.427164 CH0_RK1: MR19=0x606, MR18=0x451E, DQSOSC=392, MR23=63, INC=96, DEC=64
1369 09:28:34.427218 [RxdqsGatingPostProcess] freq 800
1370 09:28:34.427271 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 09:28:34.427325 Pre-setting of DQS Precalculation
1372 09:28:34.427379 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 09:28:34.427433 ==
1374 09:28:34.427487 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 09:28:34.427540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 09:28:34.427595 ==
1377 09:28:34.427649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 09:28:34.427702 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 09:28:34.427756 [CA 0] Center 36 (6~67) winsize 62
1380 09:28:34.427809 [CA 1] Center 37 (6~68) winsize 63
1381 09:28:34.427863 [CA 2] Center 34 (4~65) winsize 62
1382 09:28:34.427916 [CA 3] Center 34 (3~65) winsize 63
1383 09:28:34.427970 [CA 4] Center 34 (4~65) winsize 62
1384 09:28:34.428023 [CA 5] Center 33 (3~64) winsize 62
1385 09:28:34.428076
1386 09:28:34.428129 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1387 09:28:34.428183
1388 09:28:34.428236 [CATrainingPosCal] consider 1 rank data
1389 09:28:34.428289 u2DelayCellTimex100 = 270/100 ps
1390 09:28:34.428342 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1391 09:28:34.428396 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1392 09:28:34.428450 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1393 09:28:34.428503 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1394 09:28:34.428582 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 09:28:34.428650 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1396 09:28:34.428704
1397 09:28:34.428757 CA PerBit enable=1, Macro0, CA PI delay=33
1398 09:28:34.428810
1399 09:28:34.428863 [CBTSetCACLKResult] CA Dly = 33
1400 09:28:34.428916 CS Dly: 5 (0~36)
1401 09:28:34.428970 ==
1402 09:28:34.429023 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 09:28:34.429077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 09:28:34.429131 ==
1405 09:28:34.429184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 09:28:34.429238 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 09:28:34.429292 [CA 0] Center 36 (6~67) winsize 62
1408 09:28:34.429345 [CA 1] Center 37 (6~68) winsize 63
1409 09:28:34.429399 [CA 2] Center 35 (5~66) winsize 62
1410 09:28:34.429452 [CA 3] Center 34 (4~65) winsize 62
1411 09:28:34.429505 [CA 4] Center 34 (4~65) winsize 62
1412 09:28:34.429559 [CA 5] Center 34 (4~65) winsize 62
1413 09:28:34.429612
1414 09:28:34.429665 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1415 09:28:34.429719
1416 09:28:34.429772 [CATrainingPosCal] consider 2 rank data
1417 09:28:34.429825 u2DelayCellTimex100 = 270/100 ps
1418 09:28:34.429878 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1419 09:28:34.429932 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1420 09:28:34.429985 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1421 09:28:34.430039 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 09:28:34.430092 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 09:28:34.430145 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1424 09:28:34.430198
1425 09:28:34.430252 CA PerBit enable=1, Macro0, CA PI delay=34
1426 09:28:34.430305
1427 09:28:34.430358 [CBTSetCACLKResult] CA Dly = 34
1428 09:28:34.430442 CS Dly: 6 (0~38)
1429 09:28:34.430500
1430 09:28:34.430554 ----->DramcWriteLeveling(PI) begin...
1431 09:28:34.430608 ==
1432 09:28:34.430662 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 09:28:34.430715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 09:28:34.430770 ==
1435 09:28:34.430823 Write leveling (Byte 0): 27 => 27
1436 09:28:34.430877 Write leveling (Byte 1): 31 => 31
1437 09:28:34.430930 DramcWriteLeveling(PI) end<-----
1438 09:28:34.430983
1439 09:28:34.431036 ==
1440 09:28:34.431089 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 09:28:34.431142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 09:28:34.431196 ==
1443 09:28:34.431250 [Gating] SW mode calibration
1444 09:28:34.431303 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 09:28:34.431358 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 09:28:34.431412 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1447 09:28:34.431466 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 09:28:34.431519 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 09:28:34.431573 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 09:28:34.431820 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 09:28:34.431881 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 09:28:34.431936 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 09:28:34.431990 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 09:28:34.432045 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 09:28:34.432099 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 09:28:34.432153 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 09:28:34.432206 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 09:28:34.432277 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 09:28:34.432332 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 09:28:34.432387 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 09:28:34.432442 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 09:28:34.432497 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1463 09:28:34.432563 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 09:28:34.432633 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 09:28:34.432686 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 09:28:34.432740 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 09:28:34.432794 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 09:28:34.432847 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 09:28:34.432900 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 09:28:34.432954 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 09:28:34.433008 0 9 4 | B1->B0 | 2323 2525 | 1 1 | (1 1) (1 1)
1472 09:28:34.433061 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1473 09:28:34.433115 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 09:28:34.433168 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 09:28:34.433221 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 09:28:34.433274 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 09:28:34.433328 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 09:28:34.433382 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 09:28:34.433435 0 10 4 | B1->B0 | 3030 2c2c | 0 0 | (0 1) (1 0)
1480 09:28:34.433489 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1481 09:28:34.433543 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 09:28:34.433596 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 09:28:34.433650 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 09:28:34.433703 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 09:28:34.433757 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 09:28:34.433810 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 09:28:34.433865 0 11 4 | B1->B0 | 3030 3b3b | 0 1 | (0 0) (0 0)
1488 09:28:34.433919 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 09:28:34.433972 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 09:28:34.434025 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 09:28:34.434079 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 09:28:34.434133 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 09:28:34.434187 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 09:28:34.434241 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 09:28:34.434294 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1496 09:28:34.434347 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 09:28:34.434400 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 09:28:34.434454 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 09:28:34.434507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 09:28:34.434560 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 09:28:34.434614 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 09:28:34.434677 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 09:28:34.434730 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 09:28:34.434784 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 09:28:34.434837 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 09:28:34.434891 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 09:28:34.434944 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 09:28:34.434997 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 09:28:34.435050 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 09:28:34.435104 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 09:28:34.435157 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1512 09:28:34.435211 Total UI for P1: 0, mck2ui 16
1513 09:28:34.435265 best dqsien dly found for B0: ( 0, 14, 2)
1514 09:28:34.435320 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 09:28:34.435373 Total UI for P1: 0, mck2ui 16
1516 09:28:34.435427 best dqsien dly found for B1: ( 0, 14, 4)
1517 09:28:34.435480 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1518 09:28:34.435534 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1519 09:28:34.435587
1520 09:28:34.435640 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1521 09:28:34.435695 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1522 09:28:34.435748 [Gating] SW calibration Done
1523 09:28:34.435801 ==
1524 09:28:34.435854 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 09:28:34.435908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 09:28:34.435962 ==
1527 09:28:34.436015 RX Vref Scan: 0
1528 09:28:34.436068
1529 09:28:34.436121 RX Vref 0 -> 0, step: 1
1530 09:28:34.436174
1531 09:28:34.436227 RX Delay -130 -> 252, step: 16
1532 09:28:34.436281 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1533 09:28:34.436334 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1534 09:28:34.436388 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1535 09:28:34.436442 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1536 09:28:34.436495 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1537 09:28:34.436555 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1538 09:28:34.436610 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1539 09:28:34.436860 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1540 09:28:34.436924 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1541 09:28:34.436980 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1542 09:28:34.437034 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1543 09:28:34.437088 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1544 09:28:34.437142 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1545 09:28:34.437196 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1546 09:28:34.437251 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1547 09:28:34.437304 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1548 09:28:34.437358 ==
1549 09:28:34.437411 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 09:28:34.437465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 09:28:34.437519 ==
1552 09:28:34.437572 DQS Delay:
1553 09:28:34.437625 DQS0 = 0, DQS1 = 0
1554 09:28:34.437678 DQM Delay:
1555 09:28:34.437732 DQM0 = 90, DQM1 = 80
1556 09:28:34.437785 DQ Delay:
1557 09:28:34.437838 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1558 09:28:34.437891 DQ4 =93, DQ5 =93, DQ6 =101, DQ7 =85
1559 09:28:34.437945 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1560 09:28:34.437999 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1561 09:28:34.438053
1562 09:28:34.438105
1563 09:28:34.438158 ==
1564 09:28:34.438211 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 09:28:34.438265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 09:28:34.438319 ==
1567 09:28:34.438372
1568 09:28:34.438424
1569 09:28:34.438477 TX Vref Scan disable
1570 09:28:34.438530 == TX Byte 0 ==
1571 09:28:34.438583 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1572 09:28:34.438636 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1573 09:28:34.438689 == TX Byte 1 ==
1574 09:28:34.438742 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1575 09:28:34.438796 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1576 09:28:34.438849 ==
1577 09:28:34.438902 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 09:28:34.438956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 09:28:34.439010 ==
1580 09:28:34.439063 TX Vref=22, minBit 8, minWin=27, winSum=449
1581 09:28:34.439117 TX Vref=24, minBit 13, minWin=27, winSum=452
1582 09:28:34.439171 TX Vref=26, minBit 15, minWin=27, winSum=455
1583 09:28:34.439225 TX Vref=28, minBit 1, minWin=28, winSum=457
1584 09:28:34.439278 TX Vref=30, minBit 1, minWin=28, winSum=457
1585 09:28:34.439332 TX Vref=32, minBit 12, minWin=27, winSum=456
1586 09:28:34.439386 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 28
1587 09:28:34.439440
1588 09:28:34.439493 Final TX Range 1 Vref 28
1589 09:28:34.439547
1590 09:28:34.439600 ==
1591 09:28:34.439653 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 09:28:34.439706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 09:28:34.439760 ==
1594 09:28:34.439814
1595 09:28:34.439866
1596 09:28:34.439918 TX Vref Scan disable
1597 09:28:34.439972 == TX Byte 0 ==
1598 09:28:34.440025 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1599 09:28:34.440079 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1600 09:28:34.440132 == TX Byte 1 ==
1601 09:28:34.440186 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1602 09:28:34.440240 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1603 09:28:34.440294
1604 09:28:34.440347 [DATLAT]
1605 09:28:34.440400 Freq=800, CH1 RK0
1606 09:28:34.440454
1607 09:28:34.440506 DATLAT Default: 0xa
1608 09:28:34.440590 0, 0xFFFF, sum = 0
1609 09:28:34.440661 1, 0xFFFF, sum = 0
1610 09:28:34.440716 2, 0xFFFF, sum = 0
1611 09:28:34.440769 3, 0xFFFF, sum = 0
1612 09:28:34.440824 4, 0xFFFF, sum = 0
1613 09:28:34.440878 5, 0xFFFF, sum = 0
1614 09:28:34.440932 6, 0xFFFF, sum = 0
1615 09:28:34.440986 7, 0xFFFF, sum = 0
1616 09:28:34.441040 8, 0xFFFF, sum = 0
1617 09:28:34.441093 9, 0x0, sum = 1
1618 09:28:34.441147 10, 0x0, sum = 2
1619 09:28:34.441201 11, 0x0, sum = 3
1620 09:28:34.441255 12, 0x0, sum = 4
1621 09:28:34.441309 best_step = 10
1622 09:28:34.441362
1623 09:28:34.441415 ==
1624 09:28:34.441469 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 09:28:34.441523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 09:28:34.441576 ==
1627 09:28:34.441629 RX Vref Scan: 1
1628 09:28:34.441682
1629 09:28:34.441735 Set Vref Range= 32 -> 127
1630 09:28:34.441788
1631 09:28:34.441841 RX Vref 32 -> 127, step: 1
1632 09:28:34.441894
1633 09:28:34.441947 RX Delay -95 -> 252, step: 8
1634 09:28:34.442001
1635 09:28:34.442054 Set Vref, RX VrefLevel [Byte0]: 32
1636 09:28:34.442108 [Byte1]: 32
1637 09:28:34.442161
1638 09:28:34.442214 Set Vref, RX VrefLevel [Byte0]: 33
1639 09:28:34.442267 [Byte1]: 33
1640 09:28:34.442321
1641 09:28:34.442374 Set Vref, RX VrefLevel [Byte0]: 34
1642 09:28:34.442428 [Byte1]: 34
1643 09:28:34.442481
1644 09:28:34.442535 Set Vref, RX VrefLevel [Byte0]: 35
1645 09:28:34.442588 [Byte1]: 35
1646 09:28:34.442641
1647 09:28:34.442695 Set Vref, RX VrefLevel [Byte0]: 36
1648 09:28:34.442749 [Byte1]: 36
1649 09:28:34.442801
1650 09:28:34.442855 Set Vref, RX VrefLevel [Byte0]: 37
1651 09:28:34.442908 [Byte1]: 37
1652 09:28:34.442962
1653 09:28:34.443015 Set Vref, RX VrefLevel [Byte0]: 38
1654 09:28:34.443068 [Byte1]: 38
1655 09:28:34.443121
1656 09:28:34.443174 Set Vref, RX VrefLevel [Byte0]: 39
1657 09:28:34.443227 [Byte1]: 39
1658 09:28:34.443280
1659 09:28:34.443332 Set Vref, RX VrefLevel [Byte0]: 40
1660 09:28:34.443385 [Byte1]: 40
1661 09:28:34.443439
1662 09:28:34.443492 Set Vref, RX VrefLevel [Byte0]: 41
1663 09:28:34.443545 [Byte1]: 41
1664 09:28:34.443598
1665 09:28:34.443651 Set Vref, RX VrefLevel [Byte0]: 42
1666 09:28:34.443704 [Byte1]: 42
1667 09:28:34.443775
1668 09:28:34.443850 Set Vref, RX VrefLevel [Byte0]: 43
1669 09:28:34.443906 [Byte1]: 43
1670 09:28:34.443960
1671 09:28:34.444019 Set Vref, RX VrefLevel [Byte0]: 44
1672 09:28:34.444095 [Byte1]: 44
1673 09:28:34.444155
1674 09:28:34.444211 Set Vref, RX VrefLevel [Byte0]: 45
1675 09:28:34.444286 [Byte1]: 45
1676 09:28:34.444358
1677 09:28:34.444476 Set Vref, RX VrefLevel [Byte0]: 46
1678 09:28:34.444592 [Byte1]: 46
1679 09:28:34.444690
1680 09:28:34.444782 Set Vref, RX VrefLevel [Byte0]: 47
1681 09:28:34.444905 [Byte1]: 47
1682 09:28:34.445003
1683 09:28:34.445098 Set Vref, RX VrefLevel [Byte0]: 48
1684 09:28:34.445222 [Byte1]: 48
1685 09:28:34.445313
1686 09:28:34.445420 Set Vref, RX VrefLevel [Byte0]: 49
1687 09:28:34.445520 [Byte1]: 49
1688 09:28:34.445602
1689 09:28:34.445685 Set Vref, RX VrefLevel [Byte0]: 50
1690 09:28:34.445798 [Byte1]: 50
1691 09:28:34.445881
1692 09:28:34.445961 Set Vref, RX VrefLevel [Byte0]: 51
1693 09:28:34.446019 [Byte1]: 51
1694 09:28:34.446074
1695 09:28:34.446150 Set Vref, RX VrefLevel [Byte0]: 52
1696 09:28:34.446212 [Byte1]: 52
1697 09:28:34.446311
1698 09:28:34.446417 Set Vref, RX VrefLevel [Byte0]: 53
1699 09:28:34.446518 [Byte1]: 53
1700 09:28:34.446646
1701 09:28:34.446945 Set Vref, RX VrefLevel [Byte0]: 54
1702 09:28:34.447038 [Byte1]: 54
1703 09:28:34.447152
1704 09:28:34.447236 Set Vref, RX VrefLevel [Byte0]: 55
1705 09:28:34.447320 [Byte1]: 55
1706 09:28:34.447430
1707 09:28:34.447513 Set Vref, RX VrefLevel [Byte0]: 56
1708 09:28:34.447596 [Byte1]: 56
1709 09:28:34.447694
1710 09:28:34.447789 Set Vref, RX VrefLevel [Byte0]: 57
1711 09:28:34.447872 [Byte1]: 57
1712 09:28:34.447969
1713 09:28:34.448065 Set Vref, RX VrefLevel [Byte0]: 58
1714 09:28:34.448147 [Byte1]: 58
1715 09:28:34.448229
1716 09:28:34.448312 Set Vref, RX VrefLevel [Byte0]: 59
1717 09:28:34.448433 [Byte1]: 59
1718 09:28:34.448523
1719 09:28:34.448631 Set Vref, RX VrefLevel [Byte0]: 60
1720 09:28:34.448687 [Byte1]: 60
1721 09:28:34.448742
1722 09:28:34.448796 Set Vref, RX VrefLevel [Byte0]: 61
1723 09:28:34.448849 [Byte1]: 61
1724 09:28:34.448903
1725 09:28:34.448956 Set Vref, RX VrefLevel [Byte0]: 62
1726 09:28:34.449010 [Byte1]: 62
1727 09:28:34.449064
1728 09:28:34.449117 Set Vref, RX VrefLevel [Byte0]: 63
1729 09:28:34.449171 [Byte1]: 63
1730 09:28:34.449224
1731 09:28:34.449277 Set Vref, RX VrefLevel [Byte0]: 64
1732 09:28:34.449332 [Byte1]: 64
1733 09:28:34.449385
1734 09:28:34.449438 Set Vref, RX VrefLevel [Byte0]: 65
1735 09:28:34.449492 [Byte1]: 65
1736 09:28:34.449546
1737 09:28:34.449599 Set Vref, RX VrefLevel [Byte0]: 66
1738 09:28:34.449653 [Byte1]: 66
1739 09:28:34.449706
1740 09:28:34.449760 Set Vref, RX VrefLevel [Byte0]: 67
1741 09:28:34.449813 [Byte1]: 67
1742 09:28:34.449867
1743 09:28:34.449919 Set Vref, RX VrefLevel [Byte0]: 68
1744 09:28:34.449973 [Byte1]: 68
1745 09:28:34.450026
1746 09:28:34.450079 Set Vref, RX VrefLevel [Byte0]: 69
1747 09:28:34.450132 [Byte1]: 69
1748 09:28:34.450185
1749 09:28:34.450238 Set Vref, RX VrefLevel [Byte0]: 70
1750 09:28:34.450291 [Byte1]: 70
1751 09:28:34.450345
1752 09:28:34.450398 Set Vref, RX VrefLevel [Byte0]: 71
1753 09:28:34.450451 [Byte1]: 71
1754 09:28:34.450504
1755 09:28:34.450557 Set Vref, RX VrefLevel [Byte0]: 72
1756 09:28:34.450611 [Byte1]: 72
1757 09:28:34.450665
1758 09:28:34.450718 Set Vref, RX VrefLevel [Byte0]: 73
1759 09:28:34.450771 [Byte1]: 73
1760 09:28:34.450824
1761 09:28:34.450877 Set Vref, RX VrefLevel [Byte0]: 74
1762 09:28:34.450931 [Byte1]: 74
1763 09:28:34.450983
1764 09:28:34.451037 Set Vref, RX VrefLevel [Byte0]: 75
1765 09:28:34.451090 [Byte1]: 75
1766 09:28:34.451144
1767 09:28:34.451197 Set Vref, RX VrefLevel [Byte0]: 76
1768 09:28:34.451250 [Byte1]: 76
1769 09:28:34.451303
1770 09:28:34.451356 Set Vref, RX VrefLevel [Byte0]: 77
1771 09:28:34.451409 [Byte1]: 77
1772 09:28:34.451462
1773 09:28:34.451515 Set Vref, RX VrefLevel [Byte0]: 78
1774 09:28:34.451570 [Byte1]: 78
1775 09:28:34.451623
1776 09:28:34.451676 Final RX Vref Byte 0 = 53 to rank0
1777 09:28:34.451730 Final RX Vref Byte 1 = 59 to rank0
1778 09:28:34.451784 Final RX Vref Byte 0 = 53 to rank1
1779 09:28:34.451837 Final RX Vref Byte 1 = 59 to rank1==
1780 09:28:34.451891 Dram Type= 6, Freq= 0, CH_1, rank 0
1781 09:28:34.451945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 09:28:34.451999 ==
1783 09:28:34.452052 DQS Delay:
1784 09:28:34.452105 DQS0 = 0, DQS1 = 0
1785 09:28:34.452158 DQM Delay:
1786 09:28:34.452211 DQM0 = 91, DQM1 = 81
1787 09:28:34.452264 DQ Delay:
1788 09:28:34.452317 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1789 09:28:34.452371 DQ4 =88, DQ5 =104, DQ6 =100, DQ7 =84
1790 09:28:34.452424 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1791 09:28:34.452478 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1792 09:28:34.452531
1793 09:28:34.452623
1794 09:28:34.452678 [DQSOSCAuto] RK0, (LSB)MR18= 0x304e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1795 09:28:34.452733 CH1 RK0: MR19=606, MR18=304E
1796 09:28:34.452787 CH1_RK0: MR19=0x606, MR18=0x304E, DQSOSC=390, MR23=63, INC=97, DEC=64
1797 09:28:34.452841
1798 09:28:34.452894 ----->DramcWriteLeveling(PI) begin...
1799 09:28:34.452949 ==
1800 09:28:34.453002 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 09:28:34.453056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 09:28:34.453110 ==
1803 09:28:34.453164 Write leveling (Byte 0): 27 => 27
1804 09:28:34.453219 Write leveling (Byte 1): 32 => 32
1805 09:28:34.453272 DramcWriteLeveling(PI) end<-----
1806 09:28:34.453326
1807 09:28:34.453379 ==
1808 09:28:34.453432 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 09:28:34.453485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 09:28:34.453539 ==
1811 09:28:34.453592 [Gating] SW mode calibration
1812 09:28:34.453646 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1813 09:28:34.453701 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1814 09:28:34.453756 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1815 09:28:34.453810 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1816 09:28:34.453864 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 09:28:34.453919 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 09:28:34.453972 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 09:28:34.454026 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 09:28:34.454079 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 09:28:34.454133 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 09:28:34.454187 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 09:28:34.454241 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 09:28:34.454294 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 09:28:34.454348 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 09:28:34.454401 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 09:28:34.454455 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 09:28:34.454508 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 09:28:34.454562 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 09:28:34.454615 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 09:28:34.454669 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1832 09:28:34.454722 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1833 09:28:34.454775 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 09:28:34.455023 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 09:28:34.455083 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 09:28:34.455138 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 09:28:34.455192 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 09:28:34.455245 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 09:28:34.455299 0 9 4 | B1->B0 | 2626 2423 | 0 1 | (0 0) (0 0)
1840 09:28:34.455352 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1841 09:28:34.455406 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 09:28:34.455460 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 09:28:34.455514 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 09:28:34.455567 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 09:28:34.455620 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 09:28:34.455674 0 10 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1847 09:28:34.455728 0 10 4 | B1->B0 | 2c2c 2a2a | 0 0 | (0 0) (0 1)
1848 09:28:34.455781 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 09:28:34.455835 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 09:28:34.455888 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 09:28:34.455942 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 09:28:34.455996 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 09:28:34.456049 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 09:28:34.456103 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 09:28:34.456156 0 11 4 | B1->B0 | 3636 3434 | 0 0 | (0 0) (0 0)
1856 09:28:34.456210 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1857 09:28:34.456263 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 09:28:34.456317 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 09:28:34.456370 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 09:28:34.456423 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 09:28:34.456476 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 09:28:34.456530 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 09:28:34.456619 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1864 09:28:34.456673 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 09:28:34.456726 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 09:28:34.456779 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 09:28:34.456833 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 09:28:34.456886 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 09:28:34.456940 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 09:28:34.456993 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 09:28:34.457047 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 09:28:34.457101 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 09:28:34.457155 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 09:28:34.457217 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 09:28:34.457279 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 09:28:34.457339 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 09:28:34.457400 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 09:28:34.457459 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 09:28:34.457519 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1880 09:28:34.457581 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 09:28:34.457642 Total UI for P1: 0, mck2ui 16
1882 09:28:34.457702 best dqsien dly found for B0: ( 0, 14, 4)
1883 09:28:34.457762 Total UI for P1: 0, mck2ui 16
1884 09:28:34.457821 best dqsien dly found for B1: ( 0, 14, 4)
1885 09:28:34.457880 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1886 09:28:34.457940 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1887 09:28:34.457999
1888 09:28:34.458057 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1889 09:28:34.458116 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1890 09:28:34.458174 [Gating] SW calibration Done
1891 09:28:34.458234 ==
1892 09:28:34.458293 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 09:28:34.458353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 09:28:34.458412 ==
1895 09:28:34.458472 RX Vref Scan: 0
1896 09:28:34.458531
1897 09:28:34.458589 RX Vref 0 -> 0, step: 1
1898 09:28:34.458648
1899 09:28:34.458706 RX Delay -130 -> 252, step: 16
1900 09:28:34.458764 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1901 09:28:34.458823 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1902 09:28:34.458882 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1903 09:28:34.458941 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1904 09:28:34.458999 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1905 09:28:34.459058 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1906 09:28:34.459117 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1907 09:28:34.459176 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1908 09:28:34.459234 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1909 09:28:34.459293 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1910 09:28:34.459352 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1911 09:28:34.459410 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1912 09:28:34.459469 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1913 09:28:34.459528 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1914 09:28:34.459587 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1915 09:28:34.459646 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1916 09:28:34.459704 ==
1917 09:28:34.459762 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 09:28:34.684617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 09:28:34.684736 ==
1920 09:28:34.684833 DQS Delay:
1921 09:28:34.684894 DQS0 = 0, DQS1 = 0
1922 09:28:34.684953 DQM Delay:
1923 09:28:34.685011 DQM0 = 92, DQM1 = 81
1924 09:28:34.685066 DQ Delay:
1925 09:28:34.685122 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1926 09:28:34.685178 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85
1927 09:28:34.685233 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1928 09:28:34.685288 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =93
1929 09:28:34.685343
1930 09:28:34.685410
1931 09:28:34.685469 ==
1932 09:28:34.685523 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 09:28:34.685579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 09:28:34.685634 ==
1935 09:28:34.685688
1936 09:28:34.685742
1937 09:28:34.685796 TX Vref Scan disable
1938 09:28:34.686057 == TX Byte 0 ==
1939 09:28:34.686118 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1940 09:28:34.686174 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1941 09:28:34.686230 == TX Byte 1 ==
1942 09:28:34.686284 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1943 09:28:34.686339 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1944 09:28:34.686393 ==
1945 09:28:34.686447 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 09:28:34.686501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 09:28:34.686555 ==
1948 09:28:34.686609 TX Vref=22, minBit 12, minWin=27, winSum=450
1949 09:28:34.686663 TX Vref=24, minBit 12, minWin=27, winSum=451
1950 09:28:34.686718 TX Vref=26, minBit 13, minWin=27, winSum=458
1951 09:28:34.686772 TX Vref=28, minBit 13, minWin=27, winSum=455
1952 09:28:34.686826 TX Vref=30, minBit 8, minWin=28, winSum=460
1953 09:28:34.686880 TX Vref=32, minBit 8, minWin=27, winSum=454
1954 09:28:34.686934 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1955 09:28:34.686988
1956 09:28:34.687041 Final TX Range 1 Vref 30
1957 09:28:34.687095
1958 09:28:34.687147 ==
1959 09:28:34.687200 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 09:28:34.687254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 09:28:34.687309 ==
1962 09:28:34.687362
1963 09:28:34.687415
1964 09:28:34.687467 TX Vref Scan disable
1965 09:28:34.687520 == TX Byte 0 ==
1966 09:28:34.687573 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1967 09:28:34.687627 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1968 09:28:34.687680 == TX Byte 1 ==
1969 09:28:34.687734 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1970 09:28:34.687787 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1971 09:28:34.687841
1972 09:28:34.687894 [DATLAT]
1973 09:28:34.687947 Freq=800, CH1 RK1
1974 09:28:34.688000
1975 09:28:34.688053 DATLAT Default: 0xa
1976 09:28:34.688106 0, 0xFFFF, sum = 0
1977 09:28:34.688161 1, 0xFFFF, sum = 0
1978 09:28:34.688216 2, 0xFFFF, sum = 0
1979 09:28:34.688302 3, 0xFFFF, sum = 0
1980 09:28:34.688359 4, 0xFFFF, sum = 0
1981 09:28:34.688414 5, 0xFFFF, sum = 0
1982 09:28:34.688469 6, 0xFFFF, sum = 0
1983 09:28:34.688523 7, 0xFFFF, sum = 0
1984 09:28:34.688622 8, 0xFFFF, sum = 0
1985 09:28:34.688678 9, 0x0, sum = 1
1986 09:28:34.688732 10, 0x0, sum = 2
1987 09:28:34.688786 11, 0x0, sum = 3
1988 09:28:34.688841 12, 0x0, sum = 4
1989 09:28:34.688896 best_step = 10
1990 09:28:34.688967
1991 09:28:34.689024 ==
1992 09:28:34.689079 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 09:28:34.689134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 09:28:34.689189 ==
1995 09:28:34.689242 RX Vref Scan: 0
1996 09:28:34.689296
1997 09:28:34.689349 RX Vref 0 -> 0, step: 1
1998 09:28:34.689403
1999 09:28:34.689456 RX Delay -95 -> 252, step: 8
2000 09:28:34.689509 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2001 09:28:34.689564 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2002 09:28:34.689618 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2003 09:28:34.689672 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2004 09:28:34.689725 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2005 09:28:34.689779 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2006 09:28:34.689833 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
2007 09:28:34.689887 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2008 09:28:34.689940 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2009 09:28:34.689994 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2010 09:28:34.690047 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2011 09:28:34.690101 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2012 09:28:34.690155 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2013 09:28:34.690209 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2014 09:28:34.690262 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2015 09:28:34.690315 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2016 09:28:34.690369 ==
2017 09:28:34.690422 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 09:28:34.690476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 09:28:34.690531 ==
2020 09:28:34.690584 DQS Delay:
2021 09:28:34.690637 DQS0 = 0, DQS1 = 0
2022 09:28:34.690690 DQM Delay:
2023 09:28:34.690743 DQM0 = 91, DQM1 = 83
2024 09:28:34.690804 DQ Delay:
2025 09:28:34.690858 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2026 09:28:34.690912 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
2027 09:28:34.690965 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2028 09:28:34.691019 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =96
2029 09:28:34.691073
2030 09:28:34.691125
2031 09:28:34.691178 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 395 ps
2032 09:28:34.691233 CH1 RK1: MR19=606, MR18=3A11
2033 09:28:34.691287 CH1_RK1: MR19=0x606, MR18=0x3A11, DQSOSC=395, MR23=63, INC=94, DEC=63
2034 09:28:34.691341 [RxdqsGatingPostProcess] freq 800
2035 09:28:34.691394 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2036 09:28:34.691448 Pre-setting of DQS Precalculation
2037 09:28:34.691502 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2038 09:28:34.691555 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2039 09:28:34.691609 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2040 09:28:34.691663
2041 09:28:34.691716
2042 09:28:34.691772 [Calibration Summary] 1600 Mbps
2043 09:28:34.691827 CH 0, Rank 0
2044 09:28:34.691881 SW Impedance : PASS
2045 09:28:34.691936 DUTY Scan : NO K
2046 09:28:34.692015 ZQ Calibration : PASS
2047 09:28:34.692073 Jitter Meter : NO K
2048 09:28:34.692129 CBT Training : PASS
2049 09:28:34.692203 Write leveling : PASS
2050 09:28:34.692259 RX DQS gating : PASS
2051 09:28:34.692314 RX DQ/DQS(RDDQC) : PASS
2052 09:28:34.692370 TX DQ/DQS : PASS
2053 09:28:34.692425 RX DATLAT : PASS
2054 09:28:34.692481 RX DQ/DQS(Engine): PASS
2055 09:28:34.692535 TX OE : NO K
2056 09:28:34.692631 All Pass.
2057 09:28:34.692687
2058 09:28:34.692742 CH 0, Rank 1
2059 09:28:34.692816 SW Impedance : PASS
2060 09:28:34.692903 DUTY Scan : NO K
2061 09:28:34.692962 ZQ Calibration : PASS
2062 09:28:34.693018 Jitter Meter : NO K
2063 09:28:34.693074 CBT Training : PASS
2064 09:28:34.693130 Write leveling : PASS
2065 09:28:34.693201 RX DQS gating : PASS
2066 09:28:34.693275 RX DQ/DQS(RDDQC) : PASS
2067 09:28:34.693341 TX DQ/DQS : PASS
2068 09:28:34.693401 RX DATLAT : PASS
2069 09:28:34.693498 RX DQ/DQS(Engine): PASS
2070 09:28:34.693617 TX OE : NO K
2071 09:28:34.693711 All Pass.
2072 09:28:34.693803
2073 09:28:34.693901 CH 1, Rank 0
2074 09:28:34.693981 SW Impedance : PASS
2075 09:28:34.694047 DUTY Scan : NO K
2076 09:28:34.694142 ZQ Calibration : PASS
2077 09:28:34.694249 Jitter Meter : NO K
2078 09:28:34.694345 CBT Training : PASS
2079 09:28:34.694455 Write leveling : PASS
2080 09:28:34.694561 RX DQS gating : PASS
2081 09:28:34.694656 RX DQ/DQS(RDDQC) : PASS
2082 09:28:34.694764 TX DQ/DQS : PASS
2083 09:28:34.695090 RX DATLAT : PASS
2084 09:28:34.695185 RX DQ/DQS(Engine): PASS
2085 09:28:34.695274 TX OE : NO K
2086 09:28:34.695392 All Pass.
2087 09:28:34.695493
2088 09:28:34.695579 CH 1, Rank 1
2089 09:28:34.695678 SW Impedance : PASS
2090 09:28:34.695821 DUTY Scan : NO K
2091 09:28:34.695945 ZQ Calibration : PASS
2092 09:28:34.696047 Jitter Meter : NO K
2093 09:28:34.696232 CBT Training : PASS
2094 09:28:34.696356 Write leveling : PASS
2095 09:28:34.696452 RX DQS gating : PASS
2096 09:28:34.696540 RX DQ/DQS(RDDQC) : PASS
2097 09:28:34.696611 TX DQ/DQS : PASS
2098 09:28:34.696669 RX DATLAT : PASS
2099 09:28:34.696725 RX DQ/DQS(Engine): PASS
2100 09:28:34.696782 TX OE : NO K
2101 09:28:34.696839 All Pass.
2102 09:28:34.696895
2103 09:28:34.696951 DramC Write-DBI off
2104 09:28:34.697021 PER_BANK_REFRESH: Hybrid Mode
2105 09:28:34.697076 TX_TRACKING: ON
2106 09:28:34.697132 [GetDramInforAfterCalByMRR] Vendor 6.
2107 09:28:34.697202 [GetDramInforAfterCalByMRR] Revision 606.
2108 09:28:34.697286 [GetDramInforAfterCalByMRR] Revision 2 0.
2109 09:28:34.697355 MR0 0x3b3b
2110 09:28:34.697425 MR8 0x5151
2111 09:28:34.697493 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 09:28:34.697549
2113 09:28:34.697604 MR0 0x3b3b
2114 09:28:34.697658 MR8 0x5151
2115 09:28:34.697713 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 09:28:34.697769
2117 09:28:34.697824 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2118 09:28:34.697880 [FAST_K] Save calibration result to emmc
2119 09:28:34.697935 [FAST_K] Save calibration result to emmc
2120 09:28:34.697990 dram_init: config_dvfs: 1
2121 09:28:34.698046 dramc_set_vcore_voltage set vcore to 662500
2122 09:28:34.698101 Read voltage for 1200, 2
2123 09:28:34.698156 Vio18 = 0
2124 09:28:34.698211 Vcore = 662500
2125 09:28:34.698266 Vdram = 0
2126 09:28:34.698320 Vddq = 0
2127 09:28:34.698375 Vmddr = 0
2128 09:28:34.698459 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2129 09:28:34.698514 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2130 09:28:34.698570 MEM_TYPE=3, freq_sel=15
2131 09:28:34.698626 sv_algorithm_assistance_LP4_1600
2132 09:28:34.698681 ============ PULL DRAM RESETB DOWN ============
2133 09:28:34.698736 ========== PULL DRAM RESETB DOWN end =========
2134 09:28:34.698792 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 09:28:34.698847 ===================================
2136 09:28:34.698903 LPDDR4 DRAM CONFIGURATION
2137 09:28:34.698958 ===================================
2138 09:28:34.699013 EX_ROW_EN[0] = 0x0
2139 09:28:34.699068 EX_ROW_EN[1] = 0x0
2140 09:28:34.699123 LP4Y_EN = 0x0
2141 09:28:34.699178 WORK_FSP = 0x0
2142 09:28:34.699232 WL = 0x4
2143 09:28:34.699287 RL = 0x4
2144 09:28:34.699342 BL = 0x2
2145 09:28:34.699397 RPST = 0x0
2146 09:28:34.699452 RD_PRE = 0x0
2147 09:28:34.699507 WR_PRE = 0x1
2148 09:28:34.699562 WR_PST = 0x0
2149 09:28:34.699616 DBI_WR = 0x0
2150 09:28:34.699670 DBI_RD = 0x0
2151 09:28:34.699726 OTF = 0x1
2152 09:28:34.699781 ===================================
2153 09:28:34.699836 ===================================
2154 09:28:34.699891 ANA top config
2155 09:28:34.699946 ===================================
2156 09:28:34.700002 DLL_ASYNC_EN = 0
2157 09:28:34.700057 ALL_SLAVE_EN = 0
2158 09:28:34.700111 NEW_RANK_MODE = 1
2159 09:28:34.700167 DLL_IDLE_MODE = 1
2160 09:28:34.700222 LP45_APHY_COMB_EN = 1
2161 09:28:34.700277 TX_ODT_DIS = 1
2162 09:28:34.700332 NEW_8X_MODE = 1
2163 09:28:34.700388 ===================================
2164 09:28:34.700443 ===================================
2165 09:28:34.700498 data_rate = 2400
2166 09:28:34.700595 CKR = 1
2167 09:28:34.700666 DQ_P2S_RATIO = 8
2168 09:28:34.700722 ===================================
2169 09:28:34.700778 CA_P2S_RATIO = 8
2170 09:28:34.700833 DQ_CA_OPEN = 0
2171 09:28:34.700889 DQ_SEMI_OPEN = 0
2172 09:28:34.700944 CA_SEMI_OPEN = 0
2173 09:28:34.701000 CA_FULL_RATE = 0
2174 09:28:34.701055 DQ_CKDIV4_EN = 0
2175 09:28:34.701111 CA_CKDIV4_EN = 0
2176 09:28:34.701167 CA_PREDIV_EN = 0
2177 09:28:34.701222 PH8_DLY = 17
2178 09:28:34.701277 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2179 09:28:34.701332 DQ_AAMCK_DIV = 4
2180 09:28:34.701387 CA_AAMCK_DIV = 4
2181 09:28:34.701442 CA_ADMCK_DIV = 4
2182 09:28:34.701497 DQ_TRACK_CA_EN = 0
2183 09:28:34.701552 CA_PICK = 1200
2184 09:28:34.701607 CA_MCKIO = 1200
2185 09:28:34.701663 MCKIO_SEMI = 0
2186 09:28:34.701718 PLL_FREQ = 2366
2187 09:28:34.701773 DQ_UI_PI_RATIO = 32
2188 09:28:34.701828 CA_UI_PI_RATIO = 0
2189 09:28:34.701883 ===================================
2190 09:28:34.701938 ===================================
2191 09:28:34.701994 memory_type:LPDDR4
2192 09:28:34.702048 GP_NUM : 10
2193 09:28:34.702103 SRAM_EN : 1
2194 09:28:34.702158 MD32_EN : 0
2195 09:28:34.702217 ===================================
2196 09:28:34.702272 [ANA_INIT] >>>>>>>>>>>>>>
2197 09:28:34.702327 <<<<<< [CONFIGURE PHASE]: ANA_TX
2198 09:28:34.702383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2199 09:28:34.702438 ===================================
2200 09:28:34.702493 data_rate = 2400,PCW = 0X5b00
2201 09:28:34.702548 ===================================
2202 09:28:34.702604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2203 09:28:34.702659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 09:28:34.702715 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 09:28:34.702770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2206 09:28:34.702826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2207 09:28:34.702881 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2208 09:28:34.702937 [ANA_INIT] flow start
2209 09:28:34.702992 [ANA_INIT] PLL >>>>>>>>
2210 09:28:34.703047 [ANA_INIT] PLL <<<<<<<<
2211 09:28:34.703103 [ANA_INIT] MIDPI >>>>>>>>
2212 09:28:34.703158 [ANA_INIT] MIDPI <<<<<<<<
2213 09:28:34.703212 [ANA_INIT] DLL >>>>>>>>
2214 09:28:34.703267 [ANA_INIT] DLL <<<<<<<<
2215 09:28:34.703322 [ANA_INIT] flow end
2216 09:28:34.703377 ============ LP4 DIFF to SE enter ============
2217 09:28:34.703432 ============ LP4 DIFF to SE exit ============
2218 09:28:34.703487 [ANA_INIT] <<<<<<<<<<<<<
2219 09:28:34.703742 [Flow] Enable top DCM control >>>>>
2220 09:28:34.703806 [Flow] Enable top DCM control <<<<<
2221 09:28:34.703922 Enable DLL master slave shuffle
2222 09:28:34.703978 ==============================================================
2223 09:28:34.704034 Gating Mode config
2224 09:28:34.704090 ==============================================================
2225 09:28:34.704145 Config description:
2226 09:28:34.704200 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2227 09:28:34.704257 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2228 09:28:34.704313 SELPH_MODE 0: By rank 1: By Phase
2229 09:28:34.704369 ==============================================================
2230 09:28:34.704424 GAT_TRACK_EN = 1
2231 09:28:34.704479 RX_GATING_MODE = 2
2232 09:28:34.704535 RX_GATING_TRACK_MODE = 2
2233 09:28:34.704635 SELPH_MODE = 1
2234 09:28:34.704691 PICG_EARLY_EN = 1
2235 09:28:34.704749 VALID_LAT_VALUE = 1
2236 09:28:34.704830 ==============================================================
2237 09:28:34.704888 Enter into Gating configuration >>>>
2238 09:28:34.704945 Exit from Gating configuration <<<<
2239 09:28:34.704999 Enter into DVFS_PRE_config >>>>>
2240 09:28:34.705055 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2241 09:28:34.705112 Exit from DVFS_PRE_config <<<<<
2242 09:28:34.705168 Enter into PICG configuration >>>>
2243 09:28:34.705223 Exit from PICG configuration <<<<
2244 09:28:34.705279 [RX_INPUT] configuration >>>>>
2245 09:28:34.705334 [RX_INPUT] configuration <<<<<
2246 09:28:34.705389 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2247 09:28:34.705444 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2248 09:28:34.705500 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 09:28:34.705555 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 09:28:34.705610 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 09:28:34.705665 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 09:28:34.705721 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2253 09:28:34.705776 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2254 09:28:34.705832 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2255 09:28:34.705887 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2256 09:28:34.705942 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2257 09:28:34.705997 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 09:28:34.706052 ===================================
2259 09:28:34.706107 LPDDR4 DRAM CONFIGURATION
2260 09:28:34.706162 ===================================
2261 09:28:34.706217 EX_ROW_EN[0] = 0x0
2262 09:28:34.706272 EX_ROW_EN[1] = 0x0
2263 09:28:34.706327 LP4Y_EN = 0x0
2264 09:28:34.706382 WORK_FSP = 0x0
2265 09:28:34.706436 WL = 0x4
2266 09:28:34.706490 RL = 0x4
2267 09:28:34.706545 BL = 0x2
2268 09:28:34.706600 RPST = 0x0
2269 09:28:34.706654 RD_PRE = 0x0
2270 09:28:34.706708 WR_PRE = 0x1
2271 09:28:34.706763 WR_PST = 0x0
2272 09:28:34.706817 DBI_WR = 0x0
2273 09:28:34.706871 DBI_RD = 0x0
2274 09:28:34.706925 OTF = 0x1
2275 09:28:34.706980 ===================================
2276 09:28:34.707035 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2277 09:28:34.707091 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2278 09:28:34.707146 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 09:28:34.707201 ===================================
2280 09:28:34.707256 LPDDR4 DRAM CONFIGURATION
2281 09:28:34.707311 ===================================
2282 09:28:34.707366 EX_ROW_EN[0] = 0x10
2283 09:28:34.707421 EX_ROW_EN[1] = 0x0
2284 09:28:34.707475 LP4Y_EN = 0x0
2285 09:28:34.707530 WORK_FSP = 0x0
2286 09:28:34.707585 WL = 0x4
2287 09:28:34.707639 RL = 0x4
2288 09:28:34.707693 BL = 0x2
2289 09:28:34.707748 RPST = 0x0
2290 09:28:34.707803 RD_PRE = 0x0
2291 09:28:34.707857 WR_PRE = 0x1
2292 09:28:34.707912 WR_PST = 0x0
2293 09:28:34.707966 DBI_WR = 0x0
2294 09:28:34.708019 DBI_RD = 0x0
2295 09:28:34.708073 OTF = 0x1
2296 09:28:34.708126 ===================================
2297 09:28:34.708180 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2298 09:28:34.708234 ==
2299 09:28:34.708288 Dram Type= 6, Freq= 0, CH_0, rank 0
2300 09:28:34.708342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2301 09:28:34.708396 ==
2302 09:28:34.708449 [Duty_Offset_Calibration]
2303 09:28:34.708503 B0:2 B1:0 CA:1
2304 09:28:34.708581
2305 09:28:34.708650 [DutyScan_Calibration_Flow] k_type=0
2306 09:28:34.708741
2307 09:28:34.708824 ==CLK 0==
2308 09:28:34.708878 Final CLK duty delay cell = -4
2309 09:28:34.708932 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2310 09:28:34.708986 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2311 09:28:34.709040 [-4] AVG Duty = 4953%(X100)
2312 09:28:34.709093
2313 09:28:34.709146 CH0 CLK Duty spec in!! Max-Min= 156%
2314 09:28:34.709199 [DutyScan_Calibration_Flow] ====Done====
2315 09:28:34.709253
2316 09:28:34.709306 [DutyScan_Calibration_Flow] k_type=1
2317 09:28:34.709359
2318 09:28:34.709412 ==DQS 0 ==
2319 09:28:34.709466 Final DQS duty delay cell = 0
2320 09:28:34.709520 [0] MAX Duty = 5187%(X100), DQS PI = 30
2321 09:28:34.709573 [0] MIN Duty = 4938%(X100), DQS PI = 0
2322 09:28:34.709626 [0] AVG Duty = 5062%(X100)
2323 09:28:34.709679
2324 09:28:34.709732 ==DQS 1 ==
2325 09:28:34.709785 Final DQS duty delay cell = -4
2326 09:28:34.709838 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2327 09:28:34.709891 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2328 09:28:34.709944 [-4] AVG Duty = 5015%(X100)
2329 09:28:34.709997
2330 09:28:34.710050 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2331 09:28:34.710103
2332 09:28:34.710156 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2333 09:28:34.710209 [DutyScan_Calibration_Flow] ====Done====
2334 09:28:34.710263
2335 09:28:34.710315 [DutyScan_Calibration_Flow] k_type=3
2336 09:28:34.710370
2337 09:28:34.710424 ==DQM 0 ==
2338 09:28:34.710478 Final DQM duty delay cell = 0
2339 09:28:34.710532 [0] MAX Duty = 5062%(X100), DQS PI = 24
2340 09:28:34.710585 [0] MIN Duty = 4813%(X100), DQS PI = 2
2341 09:28:34.710834 [0] AVG Duty = 4937%(X100)
2342 09:28:34.710895
2343 09:28:34.710965 ==DQM 1 ==
2344 09:28:34.711033 Final DQM duty delay cell = 0
2345 09:28:34.711087 [0] MAX Duty = 5187%(X100), DQS PI = 48
2346 09:28:34.711141 [0] MIN Duty = 5000%(X100), DQS PI = 12
2347 09:28:34.711195 [0] AVG Duty = 5093%(X100)
2348 09:28:34.711262
2349 09:28:34.711329 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2350 09:28:34.711383
2351 09:28:34.711436 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2352 09:28:34.711490 [DutyScan_Calibration_Flow] ====Done====
2353 09:28:34.711543
2354 09:28:34.711596 [DutyScan_Calibration_Flow] k_type=2
2355 09:28:34.711650
2356 09:28:34.711703 ==DQ 0 ==
2357 09:28:34.711756 Final DQ duty delay cell = -4
2358 09:28:34.711810 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2359 09:28:34.711864 [-4] MIN Duty = 4844%(X100), DQS PI = 14
2360 09:28:34.711917 [-4] AVG Duty = 4937%(X100)
2361 09:28:34.711970
2362 09:28:34.712023 ==DQ 1 ==
2363 09:28:34.712103 Final DQ duty delay cell = 4
2364 09:28:34.712158 [4] MAX Duty = 5093%(X100), DQS PI = 4
2365 09:28:34.712211 [4] MIN Duty = 5031%(X100), DQS PI = 0
2366 09:28:34.712264 [4] AVG Duty = 5062%(X100)
2367 09:28:34.712317
2368 09:28:34.712370 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2369 09:28:34.712439
2370 09:28:34.712493 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2371 09:28:34.712555 [DutyScan_Calibration_Flow] ====Done====
2372 09:28:34.712625 ==
2373 09:28:34.712678 Dram Type= 6, Freq= 0, CH_1, rank 0
2374 09:28:34.712732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 09:28:34.712786 ==
2376 09:28:34.712840 [Duty_Offset_Calibration]
2377 09:28:34.712893 B0:0 B1:-1 CA:2
2378 09:28:34.712945
2379 09:28:34.712999 [DutyScan_Calibration_Flow] k_type=0
2380 09:28:34.713052
2381 09:28:34.713105 ==CLK 0==
2382 09:28:34.713159 Final CLK duty delay cell = 0
2383 09:28:34.713211 [0] MAX Duty = 5156%(X100), DQS PI = 16
2384 09:28:34.713265 [0] MIN Duty = 4938%(X100), DQS PI = 44
2385 09:28:34.713319 [0] AVG Duty = 5047%(X100)
2386 09:28:34.713372
2387 09:28:34.713424 CH1 CLK Duty spec in!! Max-Min= 218%
2388 09:28:34.713478 [DutyScan_Calibration_Flow] ====Done====
2389 09:28:34.713532
2390 09:28:34.713584 [DutyScan_Calibration_Flow] k_type=1
2391 09:28:34.713638
2392 09:28:34.713691 ==DQS 0 ==
2393 09:28:34.713745 Final DQS duty delay cell = 0
2394 09:28:34.713799 [0] MAX Duty = 5093%(X100), DQS PI = 24
2395 09:28:34.713852 [0] MIN Duty = 4969%(X100), DQS PI = 0
2396 09:28:34.713905 [0] AVG Duty = 5031%(X100)
2397 09:28:34.713959
2398 09:28:34.714011 ==DQS 1 ==
2399 09:28:34.714065 Final DQS duty delay cell = 0
2400 09:28:34.714119 [0] MAX Duty = 5156%(X100), DQS PI = 0
2401 09:28:34.714173 [0] MIN Duty = 4813%(X100), DQS PI = 36
2402 09:28:34.714227 [0] AVG Duty = 4984%(X100)
2403 09:28:34.714280
2404 09:28:34.714333 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2405 09:28:34.714387
2406 09:28:34.714439 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2407 09:28:34.714492 [DutyScan_Calibration_Flow] ====Done====
2408 09:28:34.714546
2409 09:28:34.714598 [DutyScan_Calibration_Flow] k_type=3
2410 09:28:34.714651
2411 09:28:34.714704 ==DQM 0 ==
2412 09:28:34.714757 Final DQM duty delay cell = 4
2413 09:28:34.714811 [4] MAX Duty = 5093%(X100), DQS PI = 22
2414 09:28:34.714864 [4] MIN Duty = 4938%(X100), DQS PI = 30
2415 09:28:34.714917 [4] AVG Duty = 5015%(X100)
2416 09:28:34.714970
2417 09:28:34.715023 ==DQM 1 ==
2418 09:28:34.715075 Final DQM duty delay cell = 0
2419 09:28:34.715129 [0] MAX Duty = 5249%(X100), DQS PI = 60
2420 09:28:34.715182 [0] MIN Duty = 4907%(X100), DQS PI = 36
2421 09:28:34.715236 [0] AVG Duty = 5078%(X100)
2422 09:28:34.715290
2423 09:28:34.715343 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2424 09:28:34.715396
2425 09:28:34.715449 CH1 DQM 1 Duty spec in!! Max-Min= 342%
2426 09:28:34.715502 [DutyScan_Calibration_Flow] ====Done====
2427 09:28:34.715555
2428 09:28:34.715608 [DutyScan_Calibration_Flow] k_type=2
2429 09:28:34.715661
2430 09:28:34.715714 ==DQ 0 ==
2431 09:28:34.715767 Final DQ duty delay cell = 0
2432 09:28:34.715820 [0] MAX Duty = 5031%(X100), DQS PI = 16
2433 09:28:34.715874 [0] MIN Duty = 4938%(X100), DQS PI = 0
2434 09:28:34.715928 [0] AVG Duty = 4984%(X100)
2435 09:28:34.715980
2436 09:28:34.716033 ==DQ 1 ==
2437 09:28:34.716086 Final DQ duty delay cell = 0
2438 09:28:34.716140 [0] MAX Duty = 5031%(X100), DQS PI = 2
2439 09:28:34.716194 [0] MIN Duty = 4813%(X100), DQS PI = 34
2440 09:28:34.716247 [0] AVG Duty = 4922%(X100)
2441 09:28:34.716300
2442 09:28:34.716353 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2443 09:28:34.716406
2444 09:28:34.716459 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2445 09:28:34.716512 [DutyScan_Calibration_Flow] ====Done====
2446 09:28:34.716607 nWR fixed to 30
2447 09:28:34.716663 [ModeRegInit_LP4] CH0 RK0
2448 09:28:34.716716 [ModeRegInit_LP4] CH0 RK1
2449 09:28:34.716769 [ModeRegInit_LP4] CH1 RK0
2450 09:28:34.716822 [ModeRegInit_LP4] CH1 RK1
2451 09:28:34.716875 match AC timing 7
2452 09:28:34.716929 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2453 09:28:34.716983 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2454 09:28:34.717036 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2455 09:28:34.717090 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2456 09:28:34.717144 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2457 09:28:34.717197 ==
2458 09:28:34.717251 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 09:28:34.717304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 09:28:34.717358 ==
2461 09:28:34.717411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2462 09:28:34.717466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2463 09:28:34.717520 [CA 0] Center 38 (8~69) winsize 62
2464 09:28:34.717574 [CA 1] Center 38 (7~69) winsize 63
2465 09:28:34.717628 [CA 2] Center 35 (5~66) winsize 62
2466 09:28:34.717681 [CA 3] Center 35 (4~66) winsize 63
2467 09:28:34.717734 [CA 4] Center 34 (4~65) winsize 62
2468 09:28:34.717788 [CA 5] Center 33 (3~63) winsize 61
2469 09:28:34.717841
2470 09:28:34.717894 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2471 09:28:34.717947
2472 09:28:34.718001 [CATrainingPosCal] consider 1 rank data
2473 09:28:34.718054 u2DelayCellTimex100 = 270/100 ps
2474 09:28:34.718108 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2475 09:28:34.718161 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2476 09:28:34.718215 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 09:28:34.718269 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2478 09:28:34.718323 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2479 09:28:34.718376 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2480 09:28:34.718429
2481 09:28:34.718482 CA PerBit enable=1, Macro0, CA PI delay=33
2482 09:28:34.718535
2483 09:28:34.718588 [CBTSetCACLKResult] CA Dly = 33
2484 09:28:34.718641 CS Dly: 6 (0~37)
2485 09:28:34.718694 ==
2486 09:28:34.718747 Dram Type= 6, Freq= 0, CH_0, rank 1
2487 09:28:34.718801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2488 09:28:34.718855 ==
2489 09:28:34.718908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2490 09:28:34.719156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2491 09:28:34.719217 [CA 0] Center 39 (8~70) winsize 63
2492 09:28:34.719271 [CA 1] Center 38 (8~69) winsize 62
2493 09:28:34.719339 [CA 2] Center 35 (5~66) winsize 62
2494 09:28:34.719407 [CA 3] Center 35 (5~66) winsize 62
2495 09:28:34.719460 [CA 4] Center 34 (4~65) winsize 62
2496 09:28:34.719513 [CA 5] Center 34 (4~64) winsize 61
2497 09:28:34.719566
2498 09:28:34.719633 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2499 09:28:34.719701
2500 09:28:34.719754 [CATrainingPosCal] consider 2 rank data
2501 09:28:34.719807 u2DelayCellTimex100 = 270/100 ps
2502 09:28:34.719862 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2503 09:28:34.719916 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2504 09:28:34.719969 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 09:28:34.720023 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 09:28:34.720077 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2507 09:28:34.720130 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2508 09:28:34.720183
2509 09:28:34.720236 CA PerBit enable=1, Macro0, CA PI delay=33
2510 09:28:34.720290
2511 09:28:34.720342 [CBTSetCACLKResult] CA Dly = 33
2512 09:28:34.720396 CS Dly: 7 (0~39)
2513 09:28:34.720449
2514 09:28:34.720502 ----->DramcWriteLeveling(PI) begin...
2515 09:28:34.720585 ==
2516 09:28:34.720654 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 09:28:34.720707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 09:28:34.720761 ==
2519 09:28:34.720815 Write leveling (Byte 0): 32 => 32
2520 09:28:34.720869 Write leveling (Byte 1): 32 => 32
2521 09:28:34.720923 DramcWriteLeveling(PI) end<-----
2522 09:28:34.720976
2523 09:28:34.721029 ==
2524 09:28:34.721082 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 09:28:34.721136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 09:28:34.721189 ==
2527 09:28:34.721242 [Gating] SW mode calibration
2528 09:28:34.721296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2529 09:28:34.721350 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2530 09:28:34.721403 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2531 09:28:34.721458 0 15 4 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
2532 09:28:34.721511 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 09:28:34.721565 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 09:28:34.721639 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 09:28:34.721706 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 09:28:34.721759 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2537 09:28:34.721812 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2538 09:28:34.721866 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2539 09:28:34.721919 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 09:28:34.721973 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 09:28:34.722027 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 09:28:34.722080 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 09:28:34.722134 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 09:28:34.722187 1 0 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2545 09:28:34.722240 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2546 09:28:34.722293 1 1 0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
2547 09:28:34.722346 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 09:28:34.722400 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 09:28:34.722453 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 09:28:34.722507 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 09:28:34.722560 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 09:28:34.722613 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 09:28:34.722666 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2554 09:28:34.722719 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 09:28:34.722772 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 09:28:34.722826 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 09:28:34.722880 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 09:28:34.722933 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 09:28:34.722986 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 09:28:34.723039 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 09:28:34.723093 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 09:28:34.723146 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 09:28:34.723200 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 09:28:34.723252 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 09:28:34.723306 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 09:28:34.723359 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 09:28:34.723412 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 09:28:34.723465 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 09:28:34.723518 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2570 09:28:34.723571 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 09:28:34.723625 Total UI for P1: 0, mck2ui 16
2572 09:28:34.723679 best dqsien dly found for B0: ( 1, 3, 28)
2573 09:28:34.723733 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 09:28:34.723787 Total UI for P1: 0, mck2ui 16
2575 09:28:34.723841 best dqsien dly found for B1: ( 1, 4, 0)
2576 09:28:34.723895 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2577 09:28:34.723948 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2578 09:28:34.724002
2579 09:28:34.724055 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2580 09:28:34.724109 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2581 09:28:34.724162 [Gating] SW calibration Done
2582 09:28:34.724216 ==
2583 09:28:34.724270 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 09:28:34.724324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 09:28:34.724378 ==
2586 09:28:34.724431 RX Vref Scan: 0
2587 09:28:34.724484
2588 09:28:34.724537 RX Vref 0 -> 0, step: 1
2589 09:28:34.724631
2590 09:28:34.724685 RX Delay -40 -> 252, step: 8
2591 09:28:34.724739 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2592 09:28:34.724793 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2593 09:28:34.724846 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2594 09:28:34.724899 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2595 09:28:34.725149 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2596 09:28:34.725212 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2597 09:28:34.725267 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2598 09:28:34.725322 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2599 09:28:34.725375 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
2600 09:28:34.725459 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2601 09:28:34.725545 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2602 09:28:34.725600 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2603 09:28:34.725653 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2604 09:28:34.725707 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2605 09:28:34.725761 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2606 09:28:34.725815 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2607 09:28:34.725868 ==
2608 09:28:34.725922 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 09:28:34.725975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 09:28:34.726028 ==
2611 09:28:34.726082 DQS Delay:
2612 09:28:34.726135 DQS0 = 0, DQS1 = 0
2613 09:28:34.726188 DQM Delay:
2614 09:28:34.726242 DQM0 = 122, DQM1 = 110
2615 09:28:34.726295 DQ Delay:
2616 09:28:34.726347 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2617 09:28:34.726401 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2618 09:28:34.726455 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2619 09:28:34.726508 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2620 09:28:34.726561
2621 09:28:34.726615
2622 09:28:34.726667 ==
2623 09:28:34.726720 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 09:28:34.726774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 09:28:34.726828 ==
2626 09:28:34.726882
2627 09:28:34.726935
2628 09:28:34.726987 TX Vref Scan disable
2629 09:28:34.727040 == TX Byte 0 ==
2630 09:28:34.727093 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2631 09:28:34.727147 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2632 09:28:34.727201 == TX Byte 1 ==
2633 09:28:34.727254 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2634 09:28:34.727308 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2635 09:28:34.727362 ==
2636 09:28:34.727415 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 09:28:34.727468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 09:28:34.727522 ==
2639 09:28:34.727575 TX Vref=22, minBit 2, minWin=24, winSum=406
2640 09:28:34.727629 TX Vref=24, minBit 0, minWin=25, winSum=416
2641 09:28:34.727683 TX Vref=26, minBit 0, minWin=25, winSum=419
2642 09:28:34.727737 TX Vref=28, minBit 7, minWin=25, winSum=421
2643 09:28:34.727791 TX Vref=30, minBit 7, minWin=25, winSum=421
2644 09:28:34.727845 TX Vref=32, minBit 7, minWin=25, winSum=421
2645 09:28:34.727898 [TxChooseVref] Worse bit 7, Min win 25, Win sum 421, Final Vref 28
2646 09:28:34.727952
2647 09:28:34.728005 Final TX Range 1 Vref 28
2648 09:28:34.728058
2649 09:28:34.728111 ==
2650 09:28:34.728164 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 09:28:34.728218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 09:28:34.728272 ==
2653 09:28:34.728325
2654 09:28:34.728377
2655 09:28:34.728431 TX Vref Scan disable
2656 09:28:34.728485 == TX Byte 0 ==
2657 09:28:34.728538 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2658 09:28:34.728630 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2659 09:28:34.728684 == TX Byte 1 ==
2660 09:28:34.728737 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2661 09:28:34.728792 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2662 09:28:34.728846
2663 09:28:34.728898 [DATLAT]
2664 09:28:34.728952 Freq=1200, CH0 RK0
2665 09:28:34.729005
2666 09:28:34.729058 DATLAT Default: 0xd
2667 09:28:34.729111 0, 0xFFFF, sum = 0
2668 09:28:34.729166 1, 0xFFFF, sum = 0
2669 09:28:34.729221 2, 0xFFFF, sum = 0
2670 09:28:34.729275 3, 0xFFFF, sum = 0
2671 09:28:34.729329 4, 0xFFFF, sum = 0
2672 09:28:34.729384 5, 0xFFFF, sum = 0
2673 09:28:34.729438 6, 0xFFFF, sum = 0
2674 09:28:34.729492 7, 0xFFFF, sum = 0
2675 09:28:34.729546 8, 0xFFFF, sum = 0
2676 09:28:34.729600 9, 0xFFFF, sum = 0
2677 09:28:34.729654 10, 0xFFFF, sum = 0
2678 09:28:34.729708 11, 0xFFFF, sum = 0
2679 09:28:34.729761 12, 0x0, sum = 1
2680 09:28:34.729816 13, 0x0, sum = 2
2681 09:28:34.729869 14, 0x0, sum = 3
2682 09:28:34.729924 15, 0x0, sum = 4
2683 09:28:34.729978 best_step = 13
2684 09:28:34.730031
2685 09:28:34.730084 ==
2686 09:28:34.730137 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 09:28:34.730191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 09:28:34.730245 ==
2689 09:28:34.730298 RX Vref Scan: 1
2690 09:28:34.730351
2691 09:28:34.730404 Set Vref Range= 32 -> 127
2692 09:28:34.730457
2693 09:28:34.730510 RX Vref 32 -> 127, step: 1
2694 09:28:34.730562
2695 09:28:34.730615 RX Delay -13 -> 252, step: 4
2696 09:28:34.730668
2697 09:28:34.730721 Set Vref, RX VrefLevel [Byte0]: 32
2698 09:28:34.730775 [Byte1]: 32
2699 09:28:34.730828
2700 09:28:34.730881 Set Vref, RX VrefLevel [Byte0]: 33
2701 09:28:34.730935 [Byte1]: 33
2702 09:28:34.730989
2703 09:28:34.731041 Set Vref, RX VrefLevel [Byte0]: 34
2704 09:28:34.731094 [Byte1]: 34
2705 09:28:34.731147
2706 09:28:34.731200 Set Vref, RX VrefLevel [Byte0]: 35
2707 09:28:34.731254 [Byte1]: 35
2708 09:28:34.731307
2709 09:28:34.731360 Set Vref, RX VrefLevel [Byte0]: 36
2710 09:28:34.731414 [Byte1]: 36
2711 09:28:34.731467
2712 09:28:34.731521 Set Vref, RX VrefLevel [Byte0]: 37
2713 09:28:34.731574 [Byte1]: 37
2714 09:28:34.731627
2715 09:28:34.731681 Set Vref, RX VrefLevel [Byte0]: 38
2716 09:28:34.731734 [Byte1]: 38
2717 09:28:34.731787
2718 09:28:34.731840 Set Vref, RX VrefLevel [Byte0]: 39
2719 09:28:34.731894 [Byte1]: 39
2720 09:28:34.731947
2721 09:28:34.732000 Set Vref, RX VrefLevel [Byte0]: 40
2722 09:28:34.732054 [Byte1]: 40
2723 09:28:34.732106
2724 09:28:34.732159 Set Vref, RX VrefLevel [Byte0]: 41
2725 09:28:34.732212 [Byte1]: 41
2726 09:28:34.732265
2727 09:28:34.732318 Set Vref, RX VrefLevel [Byte0]: 42
2728 09:28:34.732371 [Byte1]: 42
2729 09:28:34.732425
2730 09:28:34.732477 Set Vref, RX VrefLevel [Byte0]: 43
2731 09:28:34.732531 [Byte1]: 43
2732 09:28:34.732623
2733 09:28:34.732676 Set Vref, RX VrefLevel [Byte0]: 44
2734 09:28:34.732730 [Byte1]: 44
2735 09:28:34.732783
2736 09:28:34.732836 Set Vref, RX VrefLevel [Byte0]: 45
2737 09:28:34.732889 [Byte1]: 45
2738 09:28:34.732942
2739 09:28:34.732995 Set Vref, RX VrefLevel [Byte0]: 46
2740 09:28:34.733048 [Byte1]: 46
2741 09:28:34.733101
2742 09:28:34.733154 Set Vref, RX VrefLevel [Byte0]: 47
2743 09:28:34.733208 [Byte1]: 47
2744 09:28:34.733262
2745 09:28:34.733314 Set Vref, RX VrefLevel [Byte0]: 48
2746 09:28:34.733367 [Byte1]: 48
2747 09:28:34.733421
2748 09:28:34.733474 Set Vref, RX VrefLevel [Byte0]: 49
2749 09:28:34.733527 [Byte1]: 49
2750 09:28:34.733580
2751 09:28:34.733634 Set Vref, RX VrefLevel [Byte0]: 50
2752 09:28:34.733687 [Byte1]: 50
2753 09:28:34.733740
2754 09:28:34.733986 Set Vref, RX VrefLevel [Byte0]: 51
2755 09:28:34.734047 [Byte1]: 51
2756 09:28:34.734102
2757 09:28:34.734156 Set Vref, RX VrefLevel [Byte0]: 52
2758 09:28:34.734210 [Byte1]: 52
2759 09:28:34.734263
2760 09:28:34.734317 Set Vref, RX VrefLevel [Byte0]: 53
2761 09:28:34.734370 [Byte1]: 53
2762 09:28:34.734424
2763 09:28:34.734477 Set Vref, RX VrefLevel [Byte0]: 54
2764 09:28:34.734530 [Byte1]: 54
2765 09:28:34.734584
2766 09:28:34.734637 Set Vref, RX VrefLevel [Byte0]: 55
2767 09:28:34.734690 [Byte1]: 55
2768 09:28:34.734743
2769 09:28:34.734796 Set Vref, RX VrefLevel [Byte0]: 56
2770 09:28:34.734850 [Byte1]: 56
2771 09:28:34.734903
2772 09:28:34.734956 Set Vref, RX VrefLevel [Byte0]: 57
2773 09:28:34.735010 [Byte1]: 57
2774 09:28:34.735064
2775 09:28:34.735117 Set Vref, RX VrefLevel [Byte0]: 58
2776 09:28:34.735171 [Byte1]: 58
2777 09:28:34.735224
2778 09:28:34.735278 Set Vref, RX VrefLevel [Byte0]: 59
2779 09:28:34.735331 [Byte1]: 59
2780 09:28:34.735385
2781 09:28:34.735438 Set Vref, RX VrefLevel [Byte0]: 60
2782 09:28:34.735492 [Byte1]: 60
2783 09:28:34.735545
2784 09:28:34.735598 Set Vref, RX VrefLevel [Byte0]: 61
2785 09:28:34.735652 [Byte1]: 61
2786 09:28:34.735706
2787 09:28:34.735759 Set Vref, RX VrefLevel [Byte0]: 62
2788 09:28:34.735812 [Byte1]: 62
2789 09:28:34.735866
2790 09:28:34.735953 Set Vref, RX VrefLevel [Byte0]: 63
2791 09:28:34.736036 [Byte1]: 63
2792 09:28:34.736126
2793 09:28:34.736179 Set Vref, RX VrefLevel [Byte0]: 64
2794 09:28:34.736233 [Byte1]: 64
2795 09:28:34.736287
2796 09:28:34.736340 Set Vref, RX VrefLevel [Byte0]: 65
2797 09:28:34.736393 [Byte1]: 65
2798 09:28:34.736446
2799 09:28:34.736499 Set Vref, RX VrefLevel [Byte0]: 66
2800 09:28:34.736557 [Byte1]: 66
2801 09:28:34.736676
2802 09:28:34.736730 Set Vref, RX VrefLevel [Byte0]: 67
2803 09:28:34.736783 [Byte1]: 67
2804 09:28:34.736868
2805 09:28:34.736921 Set Vref, RX VrefLevel [Byte0]: 68
2806 09:28:34.736975 [Byte1]: 68
2807 09:28:34.737029
2808 09:28:34.737082 Set Vref, RX VrefLevel [Byte0]: 69
2809 09:28:34.737135 [Byte1]: 69
2810 09:28:34.737189
2811 09:28:34.737242 Final RX Vref Byte 0 = 58 to rank0
2812 09:28:34.737296 Final RX Vref Byte 1 = 50 to rank0
2813 09:28:34.737350 Final RX Vref Byte 0 = 58 to rank1
2814 09:28:34.737404 Final RX Vref Byte 1 = 50 to rank1==
2815 09:28:34.737458 Dram Type= 6, Freq= 0, CH_0, rank 0
2816 09:28:34.737512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2817 09:28:34.737566 ==
2818 09:28:34.737619 DQS Delay:
2819 09:28:34.737672 DQS0 = 0, DQS1 = 0
2820 09:28:34.737726 DQM Delay:
2821 09:28:34.737779 DQM0 = 122, DQM1 = 109
2822 09:28:34.737832 DQ Delay:
2823 09:28:34.737885 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2824 09:28:34.737939 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2825 09:28:34.737993 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2826 09:28:34.738046 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =116
2827 09:28:34.738101
2828 09:28:34.738154
2829 09:28:34.738207 [DQSOSCAuto] RK0, (LSB)MR18= 0x905, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2830 09:28:34.738261 CH0 RK0: MR19=404, MR18=905
2831 09:28:34.738315 CH0_RK0: MR19=0x404, MR18=0x905, DQSOSC=406, MR23=63, INC=39, DEC=26
2832 09:28:34.738369
2833 09:28:34.738422 ----->DramcWriteLeveling(PI) begin...
2834 09:28:34.738476 ==
2835 09:28:34.738530 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 09:28:34.738584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 09:28:34.738638 ==
2838 09:28:34.738691 Write leveling (Byte 0): 33 => 33
2839 09:28:34.738745 Write leveling (Byte 1): 29 => 29
2840 09:28:34.738797 DramcWriteLeveling(PI) end<-----
2841 09:28:34.738852
2842 09:28:34.738904 ==
2843 09:28:34.738957 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 09:28:34.739011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 09:28:34.739064 ==
2846 09:28:34.739118 [Gating] SW mode calibration
2847 09:28:34.739171 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2848 09:28:34.739225 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2849 09:28:34.739278 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2850 09:28:34.739333 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 09:28:34.739386 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 09:28:34.739468 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 09:28:34.739521 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 09:28:34.739575 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 09:28:34.739628 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2856 09:28:34.739681 0 15 28 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 0)
2857 09:28:34.739734 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 09:28:34.739787 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 09:28:34.739841 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 09:28:34.739894 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 09:28:34.739948 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 09:28:34.740002 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 09:28:34.740055 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2864 09:28:34.740109 1 0 28 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (0 0)
2865 09:28:34.740163 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 09:28:34.740216 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 09:28:34.740269 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 09:28:34.740323 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 09:28:34.740376 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 09:28:34.740429 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 09:28:34.740483 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 09:28:34.740536 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2873 09:28:34.740631 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2874 09:28:34.740684 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 09:28:34.740738 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 09:28:34.740792 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 09:28:34.741038 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 09:28:34.741098 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 09:28:34.741152 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 09:28:34.741237 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 09:28:34.741291 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 09:28:34.741345 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 09:28:34.741398 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 09:28:34.741452 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 09:28:34.741506 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 09:28:34.741559 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 09:28:34.741613 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 09:28:34.741666 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2889 09:28:34.741720 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2890 09:28:34.741773 Total UI for P1: 0, mck2ui 16
2891 09:28:34.741827 best dqsien dly found for B1: ( 1, 3, 28)
2892 09:28:34.741881 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 09:28:34.741935 Total UI for P1: 0, mck2ui 16
2894 09:28:34.741988 best dqsien dly found for B0: ( 1, 3, 30)
2895 09:28:34.742042 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2896 09:28:34.742096 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2897 09:28:34.742149
2898 09:28:34.742202 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2899 09:28:34.742256 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2900 09:28:34.742310 [Gating] SW calibration Done
2901 09:28:34.742364 ==
2902 09:28:34.742417 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 09:28:34.742470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 09:28:34.742525 ==
2905 09:28:34.742578 RX Vref Scan: 0
2906 09:28:34.742631
2907 09:28:34.742683 RX Vref 0 -> 0, step: 1
2908 09:28:34.742737
2909 09:28:34.742789 RX Delay -40 -> 252, step: 8
2910 09:28:34.742843 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2911 09:28:34.742897 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2912 09:28:34.742951 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2913 09:28:34.743004 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2914 09:28:34.743058 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2915 09:28:34.743111 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2916 09:28:34.743165 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2917 09:28:34.743218 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2918 09:28:34.743271 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2919 09:28:34.743325 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2920 09:28:34.743378 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2921 09:28:34.743431 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2922 09:28:34.743485 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2923 09:28:34.743539 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2924 09:28:34.743592 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2925 09:28:34.743646 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2926 09:28:34.743698 ==
2927 09:28:34.743752 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 09:28:34.743806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 09:28:34.743859 ==
2930 09:28:34.743912 DQS Delay:
2931 09:28:34.743965 DQS0 = 0, DQS1 = 0
2932 09:28:34.744019 DQM Delay:
2933 09:28:34.744072 DQM0 = 120, DQM1 = 108
2934 09:28:34.744125 DQ Delay:
2935 09:28:34.744178 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2936 09:28:34.744231 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2937 09:28:34.744285 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2938 09:28:34.870934 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2939 09:28:34.871044
2940 09:28:34.871109
2941 09:28:34.871168 ==
2942 09:28:34.871227 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 09:28:34.871285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 09:28:34.871342 ==
2945 09:28:34.871398
2946 09:28:34.871452
2947 09:28:34.871506 TX Vref Scan disable
2948 09:28:34.871560 == TX Byte 0 ==
2949 09:28:34.871621 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2950 09:28:34.871676 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2951 09:28:34.871731 == TX Byte 1 ==
2952 09:28:34.871787 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2953 09:28:34.871842 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2954 09:28:34.871896 ==
2955 09:28:34.871950 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 09:28:34.872005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 09:28:34.872059 ==
2958 09:28:34.872114 TX Vref=22, minBit 7, minWin=24, winSum=412
2959 09:28:34.872168 TX Vref=24, minBit 7, minWin=24, winSum=420
2960 09:28:34.872224 TX Vref=26, minBit 4, minWin=25, winSum=423
2961 09:28:34.872278 TX Vref=28, minBit 1, minWin=25, winSum=427
2962 09:28:34.872333 TX Vref=30, minBit 1, minWin=25, winSum=426
2963 09:28:34.872387 TX Vref=32, minBit 1, minWin=25, winSum=422
2964 09:28:34.872441 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 28
2965 09:28:34.872503
2966 09:28:34.872605 Final TX Range 1 Vref 28
2967 09:28:34.872676
2968 09:28:34.872730 ==
2969 09:28:34.872784 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 09:28:34.872839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 09:28:34.872893 ==
2972 09:28:34.872952
2973 09:28:34.873011
2974 09:28:34.873066 TX Vref Scan disable
2975 09:28:34.873120 == TX Byte 0 ==
2976 09:28:34.873173 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2977 09:28:34.873227 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2978 09:28:34.873281 == TX Byte 1 ==
2979 09:28:34.873335 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2980 09:28:34.873389 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2981 09:28:34.873443
2982 09:28:34.873496 [DATLAT]
2983 09:28:34.873549 Freq=1200, CH0 RK1
2984 09:28:34.873604
2985 09:28:34.873657 DATLAT Default: 0xd
2986 09:28:34.873710 0, 0xFFFF, sum = 0
2987 09:28:34.873765 1, 0xFFFF, sum = 0
2988 09:28:34.873821 2, 0xFFFF, sum = 0
2989 09:28:34.873874 3, 0xFFFF, sum = 0
2990 09:28:34.873929 4, 0xFFFF, sum = 0
2991 09:28:34.873983 5, 0xFFFF, sum = 0
2992 09:28:34.874038 6, 0xFFFF, sum = 0
2993 09:28:34.874092 7, 0xFFFF, sum = 0
2994 09:28:34.874147 8, 0xFFFF, sum = 0
2995 09:28:34.874201 9, 0xFFFF, sum = 0
2996 09:28:34.874255 10, 0xFFFF, sum = 0
2997 09:28:34.874309 11, 0xFFFF, sum = 0
2998 09:28:34.874364 12, 0x0, sum = 1
2999 09:28:34.874418 13, 0x0, sum = 2
3000 09:28:34.874471 14, 0x0, sum = 3
3001 09:28:34.874526 15, 0x0, sum = 4
3002 09:28:34.874581 best_step = 13
3003 09:28:34.874638
3004 09:28:34.874692 ==
3005 09:28:34.874746 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 09:28:34.874800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 09:28:34.874854 ==
3008 09:28:34.874907 RX Vref Scan: 0
3009 09:28:34.874961
3010 09:28:34.875014 RX Vref 0 -> 0, step: 1
3011 09:28:34.875067
3012 09:28:34.875120 RX Delay -21 -> 252, step: 4
3013 09:28:34.875174 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3014 09:28:34.875228 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3015 09:28:34.875490 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3016 09:28:34.875574 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3017 09:28:34.875679 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3018 09:28:34.875782 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3019 09:28:34.875885 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3020 09:28:34.875979 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3021 09:28:34.876063 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3022 09:28:34.876147 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3023 09:28:34.876230 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3024 09:28:34.876313 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3025 09:28:34.876396 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3026 09:28:34.876479 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3027 09:28:34.876591 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3028 09:28:34.876688 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3029 09:28:34.876770 ==
3030 09:28:34.876853 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 09:28:34.876937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 09:28:34.877019 ==
3033 09:28:34.877103 DQS Delay:
3034 09:28:34.877164 DQS0 = 0, DQS1 = 0
3035 09:28:34.877219 DQM Delay:
3036 09:28:34.877273 DQM0 = 119, DQM1 = 107
3037 09:28:34.877326 DQ Delay:
3038 09:28:34.877380 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3039 09:28:34.877434 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3040 09:28:34.877488 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =104
3041 09:28:34.877542 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3042 09:28:34.877596
3043 09:28:34.877649
3044 09:28:34.877703 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3045 09:28:34.877757 CH0 RK1: MR19=403, MR18=11F9
3046 09:28:34.877811 CH0_RK1: MR19=0x403, MR18=0x11F9, DQSOSC=403, MR23=63, INC=40, DEC=26
3047 09:28:34.877865 [RxdqsGatingPostProcess] freq 1200
3048 09:28:34.877919 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3049 09:28:34.877973 best DQS0 dly(2T, 0.5T) = (0, 11)
3050 09:28:34.878027 best DQS1 dly(2T, 0.5T) = (0, 12)
3051 09:28:34.878099 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3052 09:28:34.878155 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3053 09:28:34.878213 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 09:28:34.878268 best DQS1 dly(2T, 0.5T) = (0, 11)
3055 09:28:34.878327 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 09:28:34.878381 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3057 09:28:34.878435 Pre-setting of DQS Precalculation
3058 09:28:34.878490 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3059 09:28:34.878544 ==
3060 09:28:34.878598 Dram Type= 6, Freq= 0, CH_1, rank 0
3061 09:28:34.878652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 09:28:34.878706 ==
3063 09:28:34.878761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3064 09:28:34.878816 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3065 09:28:34.878870 [CA 0] Center 37 (7~68) winsize 62
3066 09:28:34.878924 [CA 1] Center 37 (7~68) winsize 62
3067 09:28:34.878978 [CA 2] Center 35 (5~65) winsize 61
3068 09:28:34.879031 [CA 3] Center 34 (4~65) winsize 62
3069 09:28:34.879085 [CA 4] Center 34 (4~65) winsize 62
3070 09:28:34.879138 [CA 5] Center 33 (3~64) winsize 62
3071 09:28:34.879192
3072 09:28:34.879246 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3073 09:28:34.879300
3074 09:28:34.879353 [CATrainingPosCal] consider 1 rank data
3075 09:28:34.879406 u2DelayCellTimex100 = 270/100 ps
3076 09:28:34.879460 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3077 09:28:34.879513 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3078 09:28:34.879567 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3079 09:28:34.879620 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3080 09:28:34.879674 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3081 09:28:34.879728 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3082 09:28:34.879781
3083 09:28:34.879835 CA PerBit enable=1, Macro0, CA PI delay=33
3084 09:28:34.879888
3085 09:28:34.879941 [CBTSetCACLKResult] CA Dly = 33
3086 09:28:34.879994 CS Dly: 5 (0~36)
3087 09:28:34.880048 ==
3088 09:28:34.880101 Dram Type= 6, Freq= 0, CH_1, rank 1
3089 09:28:34.880155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 09:28:34.880209 ==
3091 09:28:34.880265 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3092 09:28:34.880322 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3093 09:28:34.880375 [CA 0] Center 38 (8~69) winsize 62
3094 09:28:34.880431 [CA 1] Center 38 (7~69) winsize 63
3095 09:28:34.880486 [CA 2] Center 35 (5~66) winsize 62
3096 09:28:34.880541 [CA 3] Center 35 (5~65) winsize 61
3097 09:28:34.880603 [CA 4] Center 34 (4~64) winsize 61
3098 09:28:34.880659 [CA 5] Center 34 (4~64) winsize 61
3099 09:28:34.880714
3100 09:28:34.880768 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3101 09:28:34.880824
3102 09:28:34.880879 [CATrainingPosCal] consider 2 rank data
3103 09:28:34.880934 u2DelayCellTimex100 = 270/100 ps
3104 09:28:34.880990 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3105 09:28:34.881050 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3106 09:28:34.881106 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3107 09:28:34.881162 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3108 09:28:34.881222 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3109 09:28:34.881279 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3110 09:28:34.881342
3111 09:28:34.881398 CA PerBit enable=1, Macro0, CA PI delay=34
3112 09:28:34.881454
3113 09:28:34.881509 [CBTSetCACLKResult] CA Dly = 34
3114 09:28:34.881564 CS Dly: 6 (0~39)
3115 09:28:34.881619
3116 09:28:34.881674 ----->DramcWriteLeveling(PI) begin...
3117 09:28:34.881730 ==
3118 09:28:34.881785 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 09:28:34.881840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 09:28:34.881897 ==
3121 09:28:34.881952 Write leveling (Byte 0): 25 => 25
3122 09:28:34.882009 Write leveling (Byte 1): 28 => 28
3123 09:28:34.882064 DramcWriteLeveling(PI) end<-----
3124 09:28:34.882119
3125 09:28:34.882174 ==
3126 09:28:34.882229 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 09:28:34.882284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 09:28:34.882340 ==
3129 09:28:34.882395 [Gating] SW mode calibration
3130 09:28:34.882450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3131 09:28:34.882506 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3132 09:28:34.882562 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 09:28:34.882817 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 09:28:34.882892 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 09:28:34.882951 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 09:28:34.883008 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 09:28:34.883064 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 09:28:34.883119 0 15 24 | B1->B0 | 2828 2626 | 0 1 | (0 0) (1 0)
3139 09:28:34.883175 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 09:28:34.883230 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 09:28:34.883285 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 09:28:34.883340 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 09:28:34.883395 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 09:28:34.883451 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 09:28:34.883506 1 0 20 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
3146 09:28:34.883561 1 0 24 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)
3147 09:28:34.883616 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 09:28:34.883671 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 09:28:34.883726 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 09:28:34.883781 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 09:28:34.883836 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 09:28:34.883892 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 09:28:34.883947 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3154 09:28:34.884002 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3155 09:28:34.884057 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3156 09:28:34.884113 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 09:28:34.884168 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 09:28:34.884223 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 09:28:34.884277 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 09:28:34.884333 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 09:28:34.884388 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 09:28:34.884443 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 09:28:34.884498 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 09:28:34.884561 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 09:28:34.884619 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 09:28:34.884674 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 09:28:34.884729 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 09:28:34.884784 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 09:28:34.884839 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 09:28:34.884894 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3171 09:28:34.884949 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 09:28:34.885061 Total UI for P1: 0, mck2ui 16
3173 09:28:34.885147 best dqsien dly found for B0: ( 1, 3, 24)
3174 09:28:34.885217 Total UI for P1: 0, mck2ui 16
3175 09:28:34.885273 best dqsien dly found for B1: ( 1, 3, 24)
3176 09:28:34.885328 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3177 09:28:34.885383 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3178 09:28:34.885438
3179 09:28:34.885493 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3180 09:28:34.885549 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3181 09:28:34.885605 [Gating] SW calibration Done
3182 09:28:34.885660 ==
3183 09:28:34.885715 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 09:28:34.885770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 09:28:34.885825 ==
3186 09:28:34.885880 RX Vref Scan: 0
3187 09:28:34.885934
3188 09:28:34.885989 RX Vref 0 -> 0, step: 1
3189 09:28:34.886044
3190 09:28:34.886099 RX Delay -40 -> 252, step: 8
3191 09:28:34.886154 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3192 09:28:34.886209 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3193 09:28:34.886265 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3194 09:28:34.886320 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3195 09:28:34.886376 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3196 09:28:34.886431 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3197 09:28:34.886486 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3198 09:28:34.886541 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3199 09:28:34.886595 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3200 09:28:34.886651 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3201 09:28:34.886706 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3202 09:28:34.886761 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3203 09:28:34.886816 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3204 09:28:34.886872 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3205 09:28:34.886927 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3206 09:28:34.886982 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3207 09:28:34.887036 ==
3208 09:28:34.887091 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 09:28:34.887145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 09:28:34.887201 ==
3211 09:28:34.887256 DQS Delay:
3212 09:28:34.887312 DQS0 = 0, DQS1 = 0
3213 09:28:34.887367 DQM Delay:
3214 09:28:34.887422 DQM0 = 119, DQM1 = 112
3215 09:28:34.887477 DQ Delay:
3216 09:28:34.887532 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3217 09:28:34.887587 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3218 09:28:34.887642 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3219 09:28:34.887697 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3220 09:28:34.887752
3221 09:28:34.887807
3222 09:28:34.887861 ==
3223 09:28:34.887916 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 09:28:34.887971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 09:28:34.888026 ==
3226 09:28:34.888081
3227 09:28:34.888135
3228 09:28:34.888189 TX Vref Scan disable
3229 09:28:34.888244 == TX Byte 0 ==
3230 09:28:34.888299 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3231 09:28:34.888354 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3232 09:28:34.888409 == TX Byte 1 ==
3233 09:28:34.888464 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3234 09:28:34.888519 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3235 09:28:34.888604 ==
3236 09:28:34.888673 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 09:28:34.888729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 09:28:34.888785 ==
3239 09:28:34.888840 TX Vref=22, minBit 10, minWin=24, winSum=404
3240 09:28:34.888896 TX Vref=24, minBit 11, minWin=24, winSum=408
3241 09:28:34.889145 TX Vref=26, minBit 3, minWin=25, winSum=416
3242 09:28:34.889206 TX Vref=28, minBit 9, minWin=25, winSum=421
3243 09:28:34.889263 TX Vref=30, minBit 10, minWin=25, winSum=421
3244 09:28:34.889319 TX Vref=32, minBit 10, minWin=25, winSum=422
3245 09:28:34.889375 [TxChooseVref] Worse bit 10, Min win 25, Win sum 422, Final Vref 32
3246 09:28:34.889431
3247 09:28:34.889486 Final TX Range 1 Vref 32
3248 09:28:34.889542
3249 09:28:34.889596 ==
3250 09:28:34.889651 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 09:28:34.889706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 09:28:34.889763 ==
3253 09:28:34.889817
3254 09:28:34.889871
3255 09:28:34.889926 TX Vref Scan disable
3256 09:28:34.889981 == TX Byte 0 ==
3257 09:28:34.890037 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3258 09:28:34.890092 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3259 09:28:34.890148 == TX Byte 1 ==
3260 09:28:34.890203 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3261 09:28:34.890259 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3262 09:28:34.890315
3263 09:28:34.890369 [DATLAT]
3264 09:28:34.890424 Freq=1200, CH1 RK0
3265 09:28:34.890479
3266 09:28:34.890534 DATLAT Default: 0xd
3267 09:28:34.890589 0, 0xFFFF, sum = 0
3268 09:28:34.890645 1, 0xFFFF, sum = 0
3269 09:28:34.890702 2, 0xFFFF, sum = 0
3270 09:28:34.890757 3, 0xFFFF, sum = 0
3271 09:28:34.890813 4, 0xFFFF, sum = 0
3272 09:28:34.890869 5, 0xFFFF, sum = 0
3273 09:28:34.890925 6, 0xFFFF, sum = 0
3274 09:28:34.890981 7, 0xFFFF, sum = 0
3275 09:28:34.891038 8, 0xFFFF, sum = 0
3276 09:28:34.891094 9, 0xFFFF, sum = 0
3277 09:28:34.891150 10, 0xFFFF, sum = 0
3278 09:28:34.891206 11, 0xFFFF, sum = 0
3279 09:28:34.891262 12, 0x0, sum = 1
3280 09:28:34.891317 13, 0x0, sum = 2
3281 09:28:34.891373 14, 0x0, sum = 3
3282 09:28:34.891429 15, 0x0, sum = 4
3283 09:28:34.891484 best_step = 13
3284 09:28:34.891538
3285 09:28:34.891593 ==
3286 09:28:34.891648 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 09:28:34.891703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 09:28:34.891759 ==
3289 09:28:34.891813 RX Vref Scan: 1
3290 09:28:34.891868
3291 09:28:34.891922 Set Vref Range= 32 -> 127
3292 09:28:34.891977
3293 09:28:34.892031 RX Vref 32 -> 127, step: 1
3294 09:28:34.892084
3295 09:28:34.892137 RX Delay -13 -> 252, step: 4
3296 09:28:34.892191
3297 09:28:34.892243 Set Vref, RX VrefLevel [Byte0]: 32
3298 09:28:34.892296 [Byte1]: 32
3299 09:28:34.892350
3300 09:28:34.892404 Set Vref, RX VrefLevel [Byte0]: 33
3301 09:28:34.892457 [Byte1]: 33
3302 09:28:34.892510
3303 09:28:34.892588 Set Vref, RX VrefLevel [Byte0]: 34
3304 09:28:34.892656 [Byte1]: 34
3305 09:28:34.892710
3306 09:28:34.892763 Set Vref, RX VrefLevel [Byte0]: 35
3307 09:28:34.892817 [Byte1]: 35
3308 09:28:34.892870
3309 09:28:34.892923 Set Vref, RX VrefLevel [Byte0]: 36
3310 09:28:34.892976 [Byte1]: 36
3311 09:28:34.893031
3312 09:28:34.893084 Set Vref, RX VrefLevel [Byte0]: 37
3313 09:28:34.893137 [Byte1]: 37
3314 09:28:34.893190
3315 09:28:34.893243 Set Vref, RX VrefLevel [Byte0]: 38
3316 09:28:34.893296 [Byte1]: 38
3317 09:28:34.893349
3318 09:28:34.893402 Set Vref, RX VrefLevel [Byte0]: 39
3319 09:28:34.893455 [Byte1]: 39
3320 09:28:34.893509
3321 09:28:34.893562 Set Vref, RX VrefLevel [Byte0]: 40
3322 09:28:34.893616 [Byte1]: 40
3323 09:28:34.893683
3324 09:28:34.893737 Set Vref, RX VrefLevel [Byte0]: 41
3325 09:28:34.893791 [Byte1]: 41
3326 09:28:34.893845
3327 09:28:34.893898 Set Vref, RX VrefLevel [Byte0]: 42
3328 09:28:34.893952 [Byte1]: 42
3329 09:28:34.894005
3330 09:28:34.894058 Set Vref, RX VrefLevel [Byte0]: 43
3331 09:28:34.894112 [Byte1]: 43
3332 09:28:34.894165
3333 09:28:34.894218 Set Vref, RX VrefLevel [Byte0]: 44
3334 09:28:34.894271 [Byte1]: 44
3335 09:28:34.894325
3336 09:28:34.894377 Set Vref, RX VrefLevel [Byte0]: 45
3337 09:28:34.894432 [Byte1]: 45
3338 09:28:34.894485
3339 09:28:34.894538 Set Vref, RX VrefLevel [Byte0]: 46
3340 09:28:34.894591 [Byte1]: 46
3341 09:28:34.894644
3342 09:28:34.894698 Set Vref, RX VrefLevel [Byte0]: 47
3343 09:28:34.894751 [Byte1]: 47
3344 09:28:34.894804
3345 09:28:34.894856 Set Vref, RX VrefLevel [Byte0]: 48
3346 09:28:34.894910 [Byte1]: 48
3347 09:28:34.894963
3348 09:28:34.895016 Set Vref, RX VrefLevel [Byte0]: 49
3349 09:28:34.895069 [Byte1]: 49
3350 09:28:34.895161
3351 09:28:34.895231 Set Vref, RX VrefLevel [Byte0]: 50
3352 09:28:34.895287 [Byte1]: 50
3353 09:28:34.895341
3354 09:28:34.895394 Set Vref, RX VrefLevel [Byte0]: 51
3355 09:28:34.895447 [Byte1]: 51
3356 09:28:34.895500
3357 09:28:34.895553 Set Vref, RX VrefLevel [Byte0]: 52
3358 09:28:34.895606 [Byte1]: 52
3359 09:28:34.895660
3360 09:28:34.895713 Set Vref, RX VrefLevel [Byte0]: 53
3361 09:28:34.895766 [Byte1]: 53
3362 09:28:34.895819
3363 09:28:34.895872 Set Vref, RX VrefLevel [Byte0]: 54
3364 09:28:34.895925 [Byte1]: 54
3365 09:28:34.895979
3366 09:28:34.896031 Set Vref, RX VrefLevel [Byte0]: 55
3367 09:28:34.896084 [Byte1]: 55
3368 09:28:34.896137
3369 09:28:34.896191 Set Vref, RX VrefLevel [Byte0]: 56
3370 09:28:34.896244 [Byte1]: 56
3371 09:28:34.896297
3372 09:28:34.896350 Set Vref, RX VrefLevel [Byte0]: 57
3373 09:28:34.896403 [Byte1]: 57
3374 09:28:34.896456
3375 09:28:34.896509 Set Vref, RX VrefLevel [Byte0]: 58
3376 09:28:34.896605 [Byte1]: 58
3377 09:28:34.896694
3378 09:28:34.896778 Set Vref, RX VrefLevel [Byte0]: 59
3379 09:28:34.896836 [Byte1]: 59
3380 09:28:34.896890
3381 09:28:34.896945 Set Vref, RX VrefLevel [Byte0]: 60
3382 09:28:34.896999 [Byte1]: 60
3383 09:28:34.897053
3384 09:28:34.897106 Set Vref, RX VrefLevel [Byte0]: 61
3385 09:28:34.897160 [Byte1]: 61
3386 09:28:34.897214
3387 09:28:34.897266 Set Vref, RX VrefLevel [Byte0]: 62
3388 09:28:34.897320 [Byte1]: 62
3389 09:28:34.897373
3390 09:28:34.897426 Set Vref, RX VrefLevel [Byte0]: 63
3391 09:28:34.897479 [Byte1]: 63
3392 09:28:34.897532
3393 09:28:34.897585 Set Vref, RX VrefLevel [Byte0]: 64
3394 09:28:34.897638 [Byte1]: 64
3395 09:28:34.897692
3396 09:28:34.897744 Set Vref, RX VrefLevel [Byte0]: 65
3397 09:28:34.897798 [Byte1]: 65
3398 09:28:34.897851
3399 09:28:34.897903 Set Vref, RX VrefLevel [Byte0]: 66
3400 09:28:34.897957 [Byte1]: 66
3401 09:28:34.898010
3402 09:28:34.898063 Set Vref, RX VrefLevel [Byte0]: 67
3403 09:28:34.898117 [Byte1]: 67
3404 09:28:34.898169
3405 09:28:34.898222 Final RX Vref Byte 0 = 52 to rank0
3406 09:28:34.898276 Final RX Vref Byte 1 = 52 to rank0
3407 09:28:34.898330 Final RX Vref Byte 0 = 52 to rank1
3408 09:28:34.898578 Final RX Vref Byte 1 = 52 to rank1==
3409 09:28:34.898639 Dram Type= 6, Freq= 0, CH_1, rank 0
3410 09:28:34.898693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3411 09:28:34.898748 ==
3412 09:28:34.898801 DQS Delay:
3413 09:28:34.898854 DQS0 = 0, DQS1 = 0
3414 09:28:34.898907 DQM Delay:
3415 09:28:34.898960 DQM0 = 119, DQM1 = 112
3416 09:28:34.899014 DQ Delay:
3417 09:28:34.899077 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3418 09:28:34.899131 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3419 09:28:34.899185 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3420 09:28:34.899239 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3421 09:28:34.899294
3422 09:28:34.899347
3423 09:28:34.899400 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3424 09:28:34.899454 CH1 RK0: MR19=404, MR18=114
3425 09:28:34.899508 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3426 09:28:34.899562
3427 09:28:34.899615 ----->DramcWriteLeveling(PI) begin...
3428 09:28:34.899669 ==
3429 09:28:34.899722 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 09:28:34.899776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 09:28:34.899830 ==
3432 09:28:34.899884 Write leveling (Byte 0): 25 => 25
3433 09:28:34.899938 Write leveling (Byte 1): 29 => 29
3434 09:28:34.899991 DramcWriteLeveling(PI) end<-----
3435 09:28:34.900044
3436 09:28:34.900097 ==
3437 09:28:34.900150 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 09:28:34.900204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 09:28:34.900257 ==
3440 09:28:34.900310 [Gating] SW mode calibration
3441 09:28:34.900364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3442 09:28:34.900418 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3443 09:28:34.900472 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 09:28:34.900526 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 09:28:34.900607 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 09:28:34.900677 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 09:28:34.900730 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 09:28:34.900784 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3449 09:28:34.900838 0 15 24 | B1->B0 | 2b2b 3333 | 0 1 | (0 0) (1 0)
3450 09:28:34.900892 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3451 09:28:34.900946 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 09:28:34.900999 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 09:28:34.901070 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 09:28:34.901155 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 09:28:34.901214 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 09:28:34.901269 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 09:28:34.901323 1 0 24 | B1->B0 | 3c3c 2b2b | 0 0 | (0 0) (0 0)
3458 09:28:34.901377 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3459 09:28:34.901431 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 09:28:34.901485 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 09:28:34.901539 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 09:28:34.901592 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 09:28:34.901646 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 09:28:34.901700 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 09:28:34.901753 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3466 09:28:34.901806 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3467 09:28:34.901859 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 09:28:34.901913 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 09:28:34.901967 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 09:28:34.902020 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 09:28:34.902073 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 09:28:34.902127 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 09:28:34.902180 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 09:28:34.902234 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 09:28:34.902288 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 09:28:34.902341 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 09:28:34.902404 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 09:28:34.902465 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 09:28:34.902526 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 09:28:34.902587 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3481 09:28:34.902648 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3482 09:28:34.902709 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 09:28:34.902769 Total UI for P1: 0, mck2ui 16
3484 09:28:34.902829 best dqsien dly found for B0: ( 1, 3, 24)
3485 09:28:34.902889 Total UI for P1: 0, mck2ui 16
3486 09:28:34.902950 best dqsien dly found for B1: ( 1, 3, 22)
3487 09:28:34.903010 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3488 09:28:34.903071 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3489 09:28:34.903130
3490 09:28:34.903190 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3491 09:28:34.903250 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3492 09:28:34.903310 [Gating] SW calibration Done
3493 09:28:34.903369 ==
3494 09:28:34.903429 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 09:28:34.903488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 09:28:34.903548 ==
3497 09:28:34.903606 RX Vref Scan: 0
3498 09:28:34.903665
3499 09:28:34.903723 RX Vref 0 -> 0, step: 1
3500 09:28:34.903782
3501 09:28:34.903840 RX Delay -40 -> 252, step: 8
3502 09:28:34.903898 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3503 09:28:34.903957 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3504 09:28:34.904016 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3505 09:28:34.904075 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3506 09:28:34.904135 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3507 09:28:34.904194 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3508 09:28:34.904252 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3509 09:28:34.904312 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3510 09:28:34.904370 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3511 09:28:34.904430 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3512 09:28:34.904683 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3513 09:28:34.904749 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3514 09:28:34.904807 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3515 09:28:34.904863 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3516 09:28:34.904918 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3517 09:28:34.904973 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3518 09:28:34.905027 ==
3519 09:28:34.905081 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 09:28:34.905135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 09:28:34.905190 ==
3522 09:28:34.905243 DQS Delay:
3523 09:28:34.905297 DQS0 = 0, DQS1 = 0
3524 09:28:34.905350 DQM Delay:
3525 09:28:34.905404 DQM0 = 119, DQM1 = 113
3526 09:28:34.905457 DQ Delay:
3527 09:28:34.905511 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3528 09:28:34.905564 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3529 09:28:34.905618 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3530 09:28:34.905672 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3531 09:28:34.905727
3532 09:28:34.905780
3533 09:28:34.905833 ==
3534 09:28:34.905886 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 09:28:34.905939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 09:28:34.905994 ==
3537 09:28:34.906047
3538 09:28:34.906100
3539 09:28:34.906152 TX Vref Scan disable
3540 09:28:34.906205 == TX Byte 0 ==
3541 09:28:34.906258 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3542 09:28:34.906312 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3543 09:28:34.906366 == TX Byte 1 ==
3544 09:28:34.906419 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3545 09:28:34.906473 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3546 09:28:34.906526 ==
3547 09:28:34.906579 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 09:28:34.906633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 09:28:34.906687 ==
3550 09:28:34.906740 TX Vref=22, minBit 1, minWin=25, winSum=417
3551 09:28:34.906794 TX Vref=24, minBit 1, minWin=25, winSum=422
3552 09:28:34.906848 TX Vref=26, minBit 3, minWin=25, winSum=424
3553 09:28:34.906902 TX Vref=28, minBit 3, minWin=26, winSum=429
3554 09:28:34.906955 TX Vref=30, minBit 3, minWin=26, winSum=428
3555 09:28:34.907009 TX Vref=32, minBit 9, minWin=25, winSum=424
3556 09:28:34.907063 [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 28
3557 09:28:34.907116
3558 09:28:34.907169 Final TX Range 1 Vref 28
3559 09:28:34.907222
3560 09:28:34.907275 ==
3561 09:28:34.907328 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 09:28:34.907382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 09:28:34.907435 ==
3564 09:28:34.907488
3565 09:28:34.907541
3566 09:28:34.907593 TX Vref Scan disable
3567 09:28:34.907646 == TX Byte 0 ==
3568 09:28:34.907699 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3569 09:28:34.907753 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3570 09:28:34.907806 == TX Byte 1 ==
3571 09:28:34.907860 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3572 09:28:34.907914 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3573 09:28:34.907967
3574 09:28:34.908020 [DATLAT]
3575 09:28:34.908074 Freq=1200, CH1 RK1
3576 09:28:34.908127
3577 09:28:34.908180 DATLAT Default: 0xd
3578 09:28:34.908233 0, 0xFFFF, sum = 0
3579 09:28:34.908288 1, 0xFFFF, sum = 0
3580 09:28:34.908342 2, 0xFFFF, sum = 0
3581 09:28:34.908396 3, 0xFFFF, sum = 0
3582 09:28:34.908451 4, 0xFFFF, sum = 0
3583 09:28:34.908505 5, 0xFFFF, sum = 0
3584 09:28:34.908587 6, 0xFFFF, sum = 0
3585 09:28:34.908656 7, 0xFFFF, sum = 0
3586 09:28:34.908711 8, 0xFFFF, sum = 0
3587 09:28:34.908765 9, 0xFFFF, sum = 0
3588 09:28:34.908819 10, 0xFFFF, sum = 0
3589 09:28:34.908873 11, 0xFFFF, sum = 0
3590 09:28:34.908927 12, 0x0, sum = 1
3591 09:28:34.908981 13, 0x0, sum = 2
3592 09:28:34.909034 14, 0x0, sum = 3
3593 09:28:34.909088 15, 0x0, sum = 4
3594 09:28:34.909141 best_step = 13
3595 09:28:34.909195
3596 09:28:34.909248 ==
3597 09:28:34.909301 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 09:28:34.909354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 09:28:34.909408 ==
3600 09:28:34.909461 RX Vref Scan: 0
3601 09:28:34.909514
3602 09:28:34.909568 RX Vref 0 -> 0, step: 1
3603 09:28:34.909621
3604 09:28:34.909673 RX Delay -13 -> 252, step: 4
3605 09:28:34.909727 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3606 09:28:34.909781 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3607 09:28:34.909834 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3608 09:28:34.909887 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3609 09:28:34.909940 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3610 09:28:34.909993 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3611 09:28:34.910047 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3612 09:28:34.910101 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3613 09:28:34.910154 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3614 09:28:34.910208 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3615 09:28:34.910262 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3616 09:28:34.910316 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3617 09:28:34.910369 iDelay=195, Bit 12, Center 120 (55 ~ 186) 132
3618 09:28:34.910422 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3619 09:28:34.910475 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3620 09:28:34.910529 iDelay=195, Bit 15, Center 122 (55 ~ 190) 136
3621 09:28:34.910582 ==
3622 09:28:34.910635 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 09:28:34.910688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 09:28:34.910742 ==
3625 09:28:34.910795 DQS Delay:
3626 09:28:34.910847 DQS0 = 0, DQS1 = 0
3627 09:28:34.910900 DQM Delay:
3628 09:28:34.910953 DQM0 = 119, DQM1 = 112
3629 09:28:34.911007 DQ Delay:
3630 09:28:34.911060 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3631 09:28:34.911114 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3632 09:28:34.911168 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3633 09:28:34.911221 DQ12 =120, DQ13 =118, DQ14 =122, DQ15 =122
3634 09:28:34.911276
3635 09:28:34.911329
3636 09:28:34.911382 [DQSOSCAuto] RK1, (LSB)MR18= 0x9ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3637 09:28:34.911436 CH1 RK1: MR19=403, MR18=9EE
3638 09:28:34.911490 CH1_RK1: MR19=0x403, MR18=0x9EE, DQSOSC=406, MR23=63, INC=39, DEC=26
3639 09:28:34.911543 [RxdqsGatingPostProcess] freq 1200
3640 09:28:34.911597 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3641 09:28:34.911651 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 09:28:34.911705 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 09:28:34.911758 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 09:28:34.911811 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 09:28:34.911865 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 09:28:34.911919 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 09:28:34.911972 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 09:28:34.912025 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 09:28:34.912078 Pre-setting of DQS Precalculation
3650 09:28:34.912132 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3651 09:28:34.912382 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3652 09:28:34.912445 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3653 09:28:34.912501
3654 09:28:34.912580
3655 09:28:34.912683 [Calibration Summary] 2400 Mbps
3656 09:28:34.912736 CH 0, Rank 0
3657 09:28:34.912790 SW Impedance : PASS
3658 09:28:34.912844 DUTY Scan : NO K
3659 09:28:34.912898 ZQ Calibration : PASS
3660 09:28:34.912951 Jitter Meter : NO K
3661 09:28:34.913005 CBT Training : PASS
3662 09:28:34.913059 Write leveling : PASS
3663 09:28:34.913112 RX DQS gating : PASS
3664 09:28:34.913165 RX DQ/DQS(RDDQC) : PASS
3665 09:28:34.913219 TX DQ/DQS : PASS
3666 09:28:34.913273 RX DATLAT : PASS
3667 09:28:34.913326 RX DQ/DQS(Engine): PASS
3668 09:28:34.913380 TX OE : NO K
3669 09:28:34.913433 All Pass.
3670 09:28:34.913486
3671 09:28:34.913539 CH 0, Rank 1
3672 09:28:34.913592 SW Impedance : PASS
3673 09:28:34.913645 DUTY Scan : NO K
3674 09:28:34.913697 ZQ Calibration : PASS
3675 09:28:34.913751 Jitter Meter : NO K
3676 09:28:34.913805 CBT Training : PASS
3677 09:28:34.913858 Write leveling : PASS
3678 09:28:34.913911 RX DQS gating : PASS
3679 09:28:34.913964 RX DQ/DQS(RDDQC) : PASS
3680 09:28:34.914017 TX DQ/DQS : PASS
3681 09:28:34.914071 RX DATLAT : PASS
3682 09:28:34.914123 RX DQ/DQS(Engine): PASS
3683 09:28:34.914176 TX OE : NO K
3684 09:28:34.914230 All Pass.
3685 09:28:34.914283
3686 09:28:34.914335 CH 1, Rank 0
3687 09:28:34.914388 SW Impedance : PASS
3688 09:28:34.914442 DUTY Scan : NO K
3689 09:28:34.914494 ZQ Calibration : PASS
3690 09:28:34.914547 Jitter Meter : NO K
3691 09:28:34.914600 CBT Training : PASS
3692 09:28:34.914654 Write leveling : PASS
3693 09:28:34.914706 RX DQS gating : PASS
3694 09:28:34.914759 RX DQ/DQS(RDDQC) : PASS
3695 09:28:34.914812 TX DQ/DQS : PASS
3696 09:28:34.914866 RX DATLAT : PASS
3697 09:28:34.914920 RX DQ/DQS(Engine): PASS
3698 09:28:34.914974 TX OE : NO K
3699 09:28:34.915032 All Pass.
3700 09:28:34.915085
3701 09:28:34.915138 CH 1, Rank 1
3702 09:28:34.915191 SW Impedance : PASS
3703 09:28:34.915245 DUTY Scan : NO K
3704 09:28:34.915298 ZQ Calibration : PASS
3705 09:28:34.915350 Jitter Meter : NO K
3706 09:28:34.915403 CBT Training : PASS
3707 09:28:34.915456 Write leveling : PASS
3708 09:28:34.915509 RX DQS gating : PASS
3709 09:28:34.915561 RX DQ/DQS(RDDQC) : PASS
3710 09:28:34.915615 TX DQ/DQS : PASS
3711 09:28:34.915668 RX DATLAT : PASS
3712 09:28:34.915721 RX DQ/DQS(Engine): PASS
3713 09:28:34.915774 TX OE : NO K
3714 09:28:34.915828 All Pass.
3715 09:28:34.915880
3716 09:28:34.915932 DramC Write-DBI off
3717 09:28:34.915985 PER_BANK_REFRESH: Hybrid Mode
3718 09:28:34.916038 TX_TRACKING: ON
3719 09:28:34.916092 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3720 09:28:34.916147 [FAST_K] Save calibration result to emmc
3721 09:28:34.916200 dramc_set_vcore_voltage set vcore to 650000
3722 09:28:34.916254 Read voltage for 600, 5
3723 09:28:34.916307 Vio18 = 0
3724 09:28:34.916360 Vcore = 650000
3725 09:28:34.916413 Vdram = 0
3726 09:28:34.916467 Vddq = 0
3727 09:28:34.916519 Vmddr = 0
3728 09:28:34.916603 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3729 09:28:34.916671 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3730 09:28:34.916725 MEM_TYPE=3, freq_sel=19
3731 09:28:34.916778 sv_algorithm_assistance_LP4_1600
3732 09:28:34.916832 ============ PULL DRAM RESETB DOWN ============
3733 09:28:34.916886 ========== PULL DRAM RESETB DOWN end =========
3734 09:28:34.916941 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3735 09:28:34.916994 ===================================
3736 09:28:34.917048 LPDDR4 DRAM CONFIGURATION
3737 09:28:34.917101 ===================================
3738 09:28:34.917156 EX_ROW_EN[0] = 0x0
3739 09:28:34.917209 EX_ROW_EN[1] = 0x0
3740 09:28:34.917262 LP4Y_EN = 0x0
3741 09:28:34.917316 WORK_FSP = 0x0
3742 09:28:34.917369 WL = 0x2
3743 09:28:34.917422 RL = 0x2
3744 09:28:34.917475 BL = 0x2
3745 09:28:34.917527 RPST = 0x0
3746 09:28:34.917581 RD_PRE = 0x0
3747 09:28:34.917633 WR_PRE = 0x1
3748 09:28:34.917686 WR_PST = 0x0
3749 09:28:34.917738 DBI_WR = 0x0
3750 09:28:34.917791 DBI_RD = 0x0
3751 09:28:34.917844 OTF = 0x1
3752 09:28:34.917898 ===================================
3753 09:28:34.917951 ===================================
3754 09:28:34.918005 ANA top config
3755 09:28:34.918058 ===================================
3756 09:28:34.918112 DLL_ASYNC_EN = 0
3757 09:28:34.918165 ALL_SLAVE_EN = 1
3758 09:28:34.918218 NEW_RANK_MODE = 1
3759 09:28:34.918279 DLL_IDLE_MODE = 1
3760 09:28:34.918339 LP45_APHY_COMB_EN = 1
3761 09:28:34.918399 TX_ODT_DIS = 1
3762 09:28:34.918459 NEW_8X_MODE = 1
3763 09:28:34.918520 ===================================
3764 09:28:34.918579 ===================================
3765 09:28:34.918639 data_rate = 1200
3766 09:28:34.918698 CKR = 1
3767 09:28:34.918757 DQ_P2S_RATIO = 8
3768 09:28:34.918817 ===================================
3769 09:28:34.918876 CA_P2S_RATIO = 8
3770 09:28:34.918935 DQ_CA_OPEN = 0
3771 09:28:34.918995 DQ_SEMI_OPEN = 0
3772 09:28:34.919055 CA_SEMI_OPEN = 0
3773 09:28:34.919114 CA_FULL_RATE = 0
3774 09:28:34.919173 DQ_CKDIV4_EN = 1
3775 09:28:34.919233 CA_CKDIV4_EN = 1
3776 09:28:34.919293 CA_PREDIV_EN = 0
3777 09:28:34.919352 PH8_DLY = 0
3778 09:28:34.919411 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3779 09:28:34.919471 DQ_AAMCK_DIV = 4
3780 09:28:34.919530 CA_AAMCK_DIV = 4
3781 09:28:34.919589 CA_ADMCK_DIV = 4
3782 09:28:34.919649 DQ_TRACK_CA_EN = 0
3783 09:28:34.919708 CA_PICK = 600
3784 09:28:34.919767 CA_MCKIO = 600
3785 09:28:34.919826 MCKIO_SEMI = 0
3786 09:28:34.919885 PLL_FREQ = 2288
3787 09:28:34.919944 DQ_UI_PI_RATIO = 32
3788 09:28:34.920002 CA_UI_PI_RATIO = 0
3789 09:28:34.920061 ===================================
3790 09:28:34.920120 ===================================
3791 09:28:34.920183 memory_type:LPDDR4
3792 09:28:34.920285 GP_NUM : 10
3793 09:28:34.920379 SRAM_EN : 1
3794 09:28:34.920471 MD32_EN : 0
3795 09:28:34.920584 ===================================
3796 09:28:34.920657 [ANA_INIT] >>>>>>>>>>>>>>
3797 09:28:34.920712 <<<<<< [CONFIGURE PHASE]: ANA_TX
3798 09:28:34.920767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3799 09:28:34.921010 ===================================
3800 09:28:34.921072 data_rate = 1200,PCW = 0X5800
3801 09:28:34.921128 ===================================
3802 09:28:34.921183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3803 09:28:34.921238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 09:28:34.921293 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 09:28:34.921348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3806 09:28:34.921403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3807 09:28:34.921473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3808 09:28:34.921541 [ANA_INIT] flow start
3809 09:28:34.921594 [ANA_INIT] PLL >>>>>>>>
3810 09:28:34.921648 [ANA_INIT] PLL <<<<<<<<
3811 09:28:34.921702 [ANA_INIT] MIDPI >>>>>>>>
3812 09:28:34.921767 [ANA_INIT] MIDPI <<<<<<<<
3813 09:28:34.924827 [ANA_INIT] DLL >>>>>>>>
3814 09:28:34.924909 [ANA_INIT] flow end
3815 09:28:34.928084 ============ LP4 DIFF to SE enter ============
3816 09:28:34.934562 ============ LP4 DIFF to SE exit ============
3817 09:28:34.934644 [ANA_INIT] <<<<<<<<<<<<<
3818 09:28:34.937827 [Flow] Enable top DCM control >>>>>
3819 09:28:34.941238 [Flow] Enable top DCM control <<<<<
3820 09:28:34.944533 Enable DLL master slave shuffle
3821 09:28:34.951158 ==============================================================
3822 09:28:34.951240 Gating Mode config
3823 09:28:34.957850 ==============================================================
3824 09:28:34.961123 Config description:
3825 09:28:34.971097 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3826 09:28:34.977544 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3827 09:28:34.981245 SELPH_MODE 0: By rank 1: By Phase
3828 09:28:34.987513 ==============================================================
3829 09:28:34.991143 GAT_TRACK_EN = 1
3830 09:28:34.994149 RX_GATING_MODE = 2
3831 09:28:34.994231 RX_GATING_TRACK_MODE = 2
3832 09:28:34.997754 SELPH_MODE = 1
3833 09:28:35.000896 PICG_EARLY_EN = 1
3834 09:28:35.004496 VALID_LAT_VALUE = 1
3835 09:28:35.010840 ==============================================================
3836 09:28:35.014078 Enter into Gating configuration >>>>
3837 09:28:35.017413 Exit from Gating configuration <<<<
3838 09:28:35.021145 Enter into DVFS_PRE_config >>>>>
3839 09:28:35.030822 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3840 09:28:35.034041 Exit from DVFS_PRE_config <<<<<
3841 09:28:35.037325 Enter into PICG configuration >>>>
3842 09:28:35.040534 Exit from PICG configuration <<<<
3843 09:28:35.043865 [RX_INPUT] configuration >>>>>
3844 09:28:35.047675 [RX_INPUT] configuration <<<<<
3845 09:28:35.050926 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3846 09:28:35.057475 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3847 09:28:35.064066 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 09:28:35.067289 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 09:28:35.074156 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 09:28:35.080817 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 09:28:35.083969 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3852 09:28:35.090570 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3853 09:28:35.093919 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3854 09:28:35.097681 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3855 09:28:35.100786 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3856 09:28:35.107426 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3857 09:28:35.110537 ===================================
3858 09:28:35.110620 LPDDR4 DRAM CONFIGURATION
3859 09:28:35.114102 ===================================
3860 09:28:35.117537 EX_ROW_EN[0] = 0x0
3861 09:28:35.120839 EX_ROW_EN[1] = 0x0
3862 09:28:35.120949 LP4Y_EN = 0x0
3863 09:28:35.124057 WORK_FSP = 0x0
3864 09:28:35.124178 WL = 0x2
3865 09:28:35.127334 RL = 0x2
3866 09:28:35.127464 BL = 0x2
3867 09:28:35.130487 RPST = 0x0
3868 09:28:35.130599 RD_PRE = 0x0
3869 09:28:35.133793 WR_PRE = 0x1
3870 09:28:35.133892 WR_PST = 0x0
3871 09:28:35.137533 DBI_WR = 0x0
3872 09:28:35.137634 DBI_RD = 0x0
3873 09:28:35.140328 OTF = 0x1
3874 09:28:35.144178 ===================================
3875 09:28:35.147375 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3876 09:28:35.150471 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3877 09:28:35.157079 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 09:28:35.160353 ===================================
3879 09:28:35.160449 LPDDR4 DRAM CONFIGURATION
3880 09:28:35.164013 ===================================
3881 09:28:35.167254 EX_ROW_EN[0] = 0x10
3882 09:28:35.167353 EX_ROW_EN[1] = 0x0
3883 09:28:35.170441 LP4Y_EN = 0x0
3884 09:28:35.173613 WORK_FSP = 0x0
3885 09:28:35.173706 WL = 0x2
3886 09:28:35.176956 RL = 0x2
3887 09:28:35.177022 BL = 0x2
3888 09:28:35.180705 RPST = 0x0
3889 09:28:35.180770 RD_PRE = 0x0
3890 09:28:35.183967 WR_PRE = 0x1
3891 09:28:35.184059 WR_PST = 0x0
3892 09:28:35.187255 DBI_WR = 0x0
3893 09:28:35.187356 DBI_RD = 0x0
3894 09:28:35.190266 OTF = 0x1
3895 09:28:35.193842 ===================================
3896 09:28:35.200182 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3897 09:28:35.203935 nWR fixed to 30
3898 09:28:35.204026 [ModeRegInit_LP4] CH0 RK0
3899 09:28:35.206912 [ModeRegInit_LP4] CH0 RK1
3900 09:28:35.210543 [ModeRegInit_LP4] CH1 RK0
3901 09:28:35.210638 [ModeRegInit_LP4] CH1 RK1
3902 09:28:35.213694 match AC timing 17
3903 09:28:35.216754 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3904 09:28:35.220374 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3905 09:28:35.226832 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3906 09:28:35.230580 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3907 09:28:35.237029 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3908 09:28:35.237113 ==
3909 09:28:35.240254 Dram Type= 6, Freq= 0, CH_0, rank 0
3910 09:28:35.243568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3911 09:28:35.243653 ==
3912 09:28:35.250029 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3913 09:28:35.253720 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3914 09:28:35.258122 [CA 0] Center 36 (6~67) winsize 62
3915 09:28:35.261560 [CA 1] Center 36 (6~67) winsize 62
3916 09:28:35.264413 [CA 2] Center 34 (4~65) winsize 62
3917 09:28:35.268081 [CA 3] Center 34 (4~65) winsize 62
3918 09:28:35.271335 [CA 4] Center 34 (3~65) winsize 63
3919 09:28:35.274651 [CA 5] Center 33 (3~64) winsize 62
3920 09:28:35.274734
3921 09:28:35.277845 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3922 09:28:35.277929
3923 09:28:35.281137 [CATrainingPosCal] consider 1 rank data
3924 09:28:35.284949 u2DelayCellTimex100 = 270/100 ps
3925 09:28:35.288248 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3926 09:28:35.291389 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3927 09:28:35.298173 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3928 09:28:35.301216 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3929 09:28:35.304376 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3930 09:28:35.308080 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3931 09:28:35.308165
3932 09:28:35.311093 CA PerBit enable=1, Macro0, CA PI delay=33
3933 09:28:35.311178
3934 09:28:35.314795 [CBTSetCACLKResult] CA Dly = 33
3935 09:28:35.314879 CS Dly: 5 (0~36)
3936 09:28:35.314946 ==
3937 09:28:35.317857 Dram Type= 6, Freq= 0, CH_0, rank 1
3938 09:28:35.324582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 09:28:35.324671 ==
3940 09:28:35.327884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3941 09:28:35.334454 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3942 09:28:35.338218 [CA 0] Center 36 (6~67) winsize 62
3943 09:28:35.341413 [CA 1] Center 36 (6~67) winsize 62
3944 09:28:35.344607 [CA 2] Center 35 (5~66) winsize 62
3945 09:28:35.347877 [CA 3] Center 34 (4~65) winsize 62
3946 09:28:35.351548 [CA 4] Center 34 (3~65) winsize 63
3947 09:28:35.354801 [CA 5] Center 34 (3~65) winsize 63
3948 09:28:35.354879
3949 09:28:35.357896 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3950 09:28:35.357982
3951 09:28:35.361193 [CATrainingPosCal] consider 2 rank data
3952 09:28:35.365077 u2DelayCellTimex100 = 270/100 ps
3953 09:28:35.368234 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3954 09:28:35.371469 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3955 09:28:35.377938 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3956 09:28:35.381246 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3957 09:28:35.384464 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3958 09:28:35.387910 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3959 09:28:35.387995
3960 09:28:35.391233 CA PerBit enable=1, Macro0, CA PI delay=33
3961 09:28:35.391318
3962 09:28:35.394403 [CBTSetCACLKResult] CA Dly = 33
3963 09:28:35.394483 CS Dly: 5 (0~37)
3964 09:28:35.394555
3965 09:28:35.398119 ----->DramcWriteLeveling(PI) begin...
3966 09:28:35.401259 ==
3967 09:28:35.404695 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 09:28:35.407802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 09:28:35.407883 ==
3970 09:28:35.411069 Write leveling (Byte 0): 34 => 34
3971 09:28:35.414603 Write leveling (Byte 1): 34 => 34
3972 09:28:35.417779 DramcWriteLeveling(PI) end<-----
3973 09:28:35.417860
3974 09:28:35.417937 ==
3975 09:28:35.421429 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 09:28:35.424464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 09:28:35.424537 ==
3978 09:28:35.428123 [Gating] SW mode calibration
3979 09:28:35.434744 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3980 09:28:35.438146 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3981 09:28:35.444595 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 09:28:35.447837 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 09:28:35.451018 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3984 09:28:35.458125 0 9 12 | B1->B0 | 3333 2b2b | 1 0 | (0 1) (1 1)
3985 09:28:35.461351 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3986 09:28:35.464542 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 09:28:35.470994 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 09:28:35.474415 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 09:28:35.477678 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 09:28:35.484733 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 09:28:35.488057 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 09:28:35.491332 0 10 12 | B1->B0 | 2828 4141 | 0 0 | (0 0) (0 0)
3993 09:28:35.497887 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
3994 09:28:35.500918 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 09:28:35.504461 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 09:28:35.511306 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 09:28:35.514363 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 09:28:35.517958 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 09:28:35.524384 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4000 09:28:35.527575 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4001 09:28:35.531149 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 09:28:35.537637 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 09:28:35.540927 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 09:28:35.544229 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 09:28:35.551242 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 09:28:35.554554 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 09:28:35.557905 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 09:28:35.561025 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 09:28:35.567587 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 09:28:35.570944 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 09:28:35.574175 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 09:28:35.580502 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 09:28:35.584293 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 09:28:35.587502 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 09:28:35.594024 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 09:28:35.597333 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4017 09:28:35.600456 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 09:28:35.604230 Total UI for P1: 0, mck2ui 16
4019 09:28:35.607351 best dqsien dly found for B0: ( 0, 13, 12)
4020 09:28:35.610534 Total UI for P1: 0, mck2ui 16
4021 09:28:35.614024 best dqsien dly found for B1: ( 0, 13, 14)
4022 09:28:35.617252 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4023 09:28:35.623534 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4024 09:28:35.623614
4025 09:28:35.626825 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4026 09:28:35.630381 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4027 09:28:35.633919 [Gating] SW calibration Done
4028 09:28:35.634018 ==
4029 09:28:35.637205 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 09:28:35.640386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 09:28:35.640464 ==
4032 09:28:35.643501 RX Vref Scan: 0
4033 09:28:35.643576
4034 09:28:35.643691 RX Vref 0 -> 0, step: 1
4035 09:28:35.643794
4036 09:28:35.646736 RX Delay -230 -> 252, step: 16
4037 09:28:35.650401 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4038 09:28:35.656891 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4039 09:28:35.660221 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4040 09:28:35.663323 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4041 09:28:35.666655 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4042 09:28:35.670438 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4043 09:28:35.676436 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4044 09:28:35.680253 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4045 09:28:35.683357 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4046 09:28:35.686608 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4047 09:28:35.693366 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4048 09:28:35.696799 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4049 09:28:35.699983 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4050 09:28:35.703348 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4051 09:28:35.709671 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4052 09:28:35.713264 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4053 09:28:35.713346 ==
4054 09:28:35.716323 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 09:28:35.719847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 09:28:35.719931 ==
4057 09:28:35.723081 DQS Delay:
4058 09:28:35.723165 DQS0 = 0, DQS1 = 0
4059 09:28:35.723240 DQM Delay:
4060 09:28:35.726721 DQM0 = 51, DQM1 = 39
4061 09:28:35.726804 DQ Delay:
4062 09:28:35.729887 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4063 09:28:35.733126 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4064 09:28:35.736724 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4065 09:28:35.739894 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41
4066 09:28:35.739978
4067 09:28:35.740075
4068 09:28:35.740135 ==
4069 09:28:35.743100 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 09:28:35.749692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 09:28:35.749803 ==
4072 09:28:35.749903
4073 09:28:35.750016
4074 09:28:35.750122 TX Vref Scan disable
4075 09:28:35.753542 == TX Byte 0 ==
4076 09:28:35.756334 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4077 09:28:35.760212 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4078 09:28:35.763370 == TX Byte 1 ==
4079 09:28:35.766550 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4080 09:28:35.769917 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4081 09:28:35.773268 ==
4082 09:28:35.776462 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 09:28:35.779735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 09:28:35.779848 ==
4085 09:28:35.779943
4086 09:28:35.780018
4087 09:28:35.783099 TX Vref Scan disable
4088 09:28:35.783182 == TX Byte 0 ==
4089 09:28:35.790062 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4090 09:28:35.793324 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4091 09:28:35.793409 == TX Byte 1 ==
4092 09:28:35.800254 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4093 09:28:35.803447 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4094 09:28:35.803531
4095 09:28:35.803597 [DATLAT]
4096 09:28:35.806758 Freq=600, CH0 RK0
4097 09:28:35.806841
4098 09:28:35.806907 DATLAT Default: 0x9
4099 09:28:35.810019 0, 0xFFFF, sum = 0
4100 09:28:35.810104 1, 0xFFFF, sum = 0
4101 09:28:35.813038 2, 0xFFFF, sum = 0
4102 09:28:35.813122 3, 0xFFFF, sum = 0
4103 09:28:35.816768 4, 0xFFFF, sum = 0
4104 09:28:35.819788 5, 0xFFFF, sum = 0
4105 09:28:35.819867 6, 0xFFFF, sum = 0
4106 09:28:35.823353 7, 0xFFFF, sum = 0
4107 09:28:35.823428 8, 0x0, sum = 1
4108 09:28:35.823492 9, 0x0, sum = 2
4109 09:28:35.826387 10, 0x0, sum = 3
4110 09:28:35.826471 11, 0x0, sum = 4
4111 09:28:35.829971 best_step = 9
4112 09:28:35.830047
4113 09:28:35.830110 ==
4114 09:28:35.833125 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 09:28:35.836283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 09:28:35.836456 ==
4117 09:28:35.840000 RX Vref Scan: 1
4118 09:28:35.840090
4119 09:28:35.840168 RX Vref 0 -> 0, step: 1
4120 09:28:35.840266
4121 09:28:35.843071 RX Delay -179 -> 252, step: 8
4122 09:28:35.843160
4123 09:28:35.846445 Set Vref, RX VrefLevel [Byte0]: 58
4124 09:28:35.849684 [Byte1]: 50
4125 09:28:35.853928
4126 09:28:35.854034 Final RX Vref Byte 0 = 58 to rank0
4127 09:28:35.857333 Final RX Vref Byte 1 = 50 to rank0
4128 09:28:35.860529 Final RX Vref Byte 0 = 58 to rank1
4129 09:28:35.863713 Final RX Vref Byte 1 = 50 to rank1==
4130 09:28:35.866907 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 09:28:35.873462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 09:28:35.873542 ==
4133 09:28:35.873608 DQS Delay:
4134 09:28:35.873670 DQS0 = 0, DQS1 = 0
4135 09:28:35.876760 DQM Delay:
4136 09:28:35.876833 DQM0 = 47, DQM1 = 39
4137 09:28:35.880021 DQ Delay:
4138 09:28:35.883769 DQ0 =44, DQ1 =44, DQ2 =44, DQ3 =44
4139 09:28:35.886932 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4140 09:28:35.890282 DQ8 =36, DQ9 =28, DQ10 =36, DQ11 =36
4141 09:28:35.893536 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =44
4142 09:28:35.893623
4143 09:28:35.893725
4144 09:28:35.900457 [DQSOSCAuto] RK0, (LSB)MR18= 0x5953, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4145 09:28:35.903693 CH0 RK0: MR19=808, MR18=5953
4146 09:28:35.910250 CH0_RK0: MR19=0x808, MR18=0x5953, DQSOSC=393, MR23=63, INC=169, DEC=113
4147 09:28:35.910352
4148 09:28:35.913478 ----->DramcWriteLeveling(PI) begin...
4149 09:28:35.913565 ==
4150 09:28:35.916730 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 09:28:35.919980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 09:28:35.920067 ==
4153 09:28:35.923560 Write leveling (Byte 0): 34 => 34
4154 09:28:35.927062 Write leveling (Byte 1): 30 => 30
4155 09:28:35.930120 DramcWriteLeveling(PI) end<-----
4156 09:28:35.930207
4157 09:28:35.930292 ==
4158 09:28:35.933304 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 09:28:35.936898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 09:28:35.936985 ==
4161 09:28:35.940043 [Gating] SW mode calibration
4162 09:28:35.946725 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4163 09:28:35.953626 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4164 09:28:35.956836 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 09:28:35.960177 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 09:28:35.966556 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 09:28:35.970402 0 9 12 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 0)
4168 09:28:35.973710 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4169 09:28:35.980223 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 09:28:35.983547 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 09:28:35.986810 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 09:28:35.993266 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 09:28:35.996382 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 09:28:36.000286 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 09:28:36.006754 0 10 12 | B1->B0 | 2f2f 3535 | 0 0 | (0 0) (0 0)
4176 09:28:36.009978 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4177 09:28:36.013228 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 09:28:36.020228 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 09:28:36.023523 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 09:28:36.026657 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 09:28:36.033702 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 09:28:36.036457 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 09:28:36.040128 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 09:28:36.046763 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 09:28:36.049851 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 09:28:36.053417 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 09:28:36.059844 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 09:28:36.063236 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 09:28:36.066413 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 09:28:36.069558 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 09:28:36.076597 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 09:28:36.079883 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 09:28:36.083086 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 09:28:36.089622 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 09:28:36.093230 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 09:28:36.096529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 09:28:36.102919 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 09:28:36.106183 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 09:28:36.109464 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4200 09:28:36.116577 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 09:28:36.119753 Total UI for P1: 0, mck2ui 16
4202 09:28:36.122962 best dqsien dly found for B0: ( 0, 13, 12)
4203 09:28:36.123074 Total UI for P1: 0, mck2ui 16
4204 09:28:36.129883 best dqsien dly found for B1: ( 0, 13, 14)
4205 09:28:36.133015 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4206 09:28:36.136486 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4207 09:28:36.136587
4208 09:28:36.139540 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4209 09:28:36.142858 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4210 09:28:36.146582 [Gating] SW calibration Done
4211 09:28:36.146665 ==
4212 09:28:36.149815 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 09:28:36.152915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 09:28:36.152998 ==
4215 09:28:36.156470 RX Vref Scan: 0
4216 09:28:36.156575
4217 09:28:36.156673 RX Vref 0 -> 0, step: 1
4218 09:28:36.156757
4219 09:28:36.159554 RX Delay -230 -> 252, step: 16
4220 09:28:36.166134 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4221 09:28:36.169915 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4222 09:28:36.173070 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4223 09:28:36.176327 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4224 09:28:36.179688 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4225 09:28:36.186182 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4226 09:28:36.189768 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4227 09:28:36.193172 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4228 09:28:36.196335 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4229 09:28:36.202784 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4230 09:28:36.205947 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4231 09:28:36.209334 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4232 09:28:36.212747 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4233 09:28:36.219332 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4234 09:28:36.222495 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4235 09:28:36.225829 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4236 09:28:36.225916 ==
4237 09:28:36.229126 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 09:28:36.232398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 09:28:36.232500 ==
4240 09:28:36.236063 DQS Delay:
4241 09:28:36.236172 DQS0 = 0, DQS1 = 0
4242 09:28:36.239291 DQM Delay:
4243 09:28:36.239374 DQM0 = 49, DQM1 = 42
4244 09:28:36.239442 DQ Delay:
4245 09:28:36.242404 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =41
4246 09:28:36.246167 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4247 09:28:36.249137 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4248 09:28:36.252433 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4249 09:28:36.252533
4250 09:28:36.252625
4251 09:28:36.255640 ==
4252 09:28:36.255724 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 09:28:36.262462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 09:28:36.262548 ==
4255 09:28:36.262615
4256 09:28:36.262675
4257 09:28:36.265679 TX Vref Scan disable
4258 09:28:36.265763 == TX Byte 0 ==
4259 09:28:36.272123 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4260 09:28:36.275794 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4261 09:28:36.275905 == TX Byte 1 ==
4262 09:28:36.282355 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4263 09:28:36.285590 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4264 09:28:36.285702 ==
4265 09:28:36.288870 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 09:28:36.292151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 09:28:36.292259 ==
4268 09:28:36.292353
4269 09:28:36.292447
4270 09:28:36.295342 TX Vref Scan disable
4271 09:28:36.299187 == TX Byte 0 ==
4272 09:28:36.301970 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4273 09:28:36.305695 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4274 09:28:36.309006 == TX Byte 1 ==
4275 09:28:36.312266 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4276 09:28:36.315563 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4277 09:28:36.315665
4278 09:28:36.318806 [DATLAT]
4279 09:28:36.318907 Freq=600, CH0 RK1
4280 09:28:36.319006
4281 09:28:36.321962 DATLAT Default: 0x9
4282 09:28:36.322062 0, 0xFFFF, sum = 0
4283 09:28:36.325287 1, 0xFFFF, sum = 0
4284 09:28:36.325393 2, 0xFFFF, sum = 0
4285 09:28:36.329017 3, 0xFFFF, sum = 0
4286 09:28:36.329121 4, 0xFFFF, sum = 0
4287 09:28:36.332307 5, 0xFFFF, sum = 0
4288 09:28:36.332409 6, 0xFFFF, sum = 0
4289 09:28:36.335118 7, 0xFFFF, sum = 0
4290 09:28:36.335225 8, 0x0, sum = 1
4291 09:28:36.338839 9, 0x0, sum = 2
4292 09:28:36.338946 10, 0x0, sum = 3
4293 09:28:36.342120 11, 0x0, sum = 4
4294 09:28:36.342225 best_step = 9
4295 09:28:36.342352
4296 09:28:36.342443 ==
4297 09:28:36.345310 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 09:28:36.348856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 09:28:36.352026 ==
4300 09:28:36.352097 RX Vref Scan: 0
4301 09:28:36.352159
4302 09:28:36.355061 RX Vref 0 -> 0, step: 1
4303 09:28:36.355182
4304 09:28:36.358855 RX Delay -179 -> 252, step: 8
4305 09:28:36.361751 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4306 09:28:36.365308 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4307 09:28:36.371623 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4308 09:28:36.375300 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4309 09:28:36.378549 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4310 09:28:36.381889 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4311 09:28:36.385194 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4312 09:28:36.391782 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4313 09:28:36.395564 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4314 09:28:36.398352 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4315 09:28:36.402151 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4316 09:28:36.405367 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4317 09:28:36.411859 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4318 09:28:36.415063 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4319 09:28:36.418828 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4320 09:28:36.422146 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4321 09:28:36.422229 ==
4322 09:28:36.425388 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 09:28:36.431841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 09:28:36.431925 ==
4325 09:28:36.431991 DQS Delay:
4326 09:28:36.435523 DQS0 = 0, DQS1 = 0
4327 09:28:36.435605 DQM Delay:
4328 09:28:36.435670 DQM0 = 48, DQM1 = 40
4329 09:28:36.438799 DQ Delay:
4330 09:28:36.442024 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4331 09:28:36.445392 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =52
4332 09:28:36.448422 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4333 09:28:36.451833 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4334 09:28:36.451917
4335 09:28:36.451981
4336 09:28:36.458764 [DQSOSCAuto] RK1, (LSB)MR18= 0x6733, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4337 09:28:36.461946 CH0 RK1: MR19=808, MR18=6733
4338 09:28:36.468248 CH0_RK1: MR19=0x808, MR18=0x6733, DQSOSC=390, MR23=63, INC=172, DEC=114
4339 09:28:36.471869 [RxdqsGatingPostProcess] freq 600
4340 09:28:36.475103 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4341 09:28:36.478317 Pre-setting of DQS Precalculation
4342 09:28:36.484801 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4343 09:28:36.484885 ==
4344 09:28:36.488144 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 09:28:36.491470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 09:28:36.491550 ==
4347 09:28:36.498439 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4348 09:28:36.504912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4349 09:28:36.508168 [CA 0] Center 35 (5~66) winsize 62
4350 09:28:36.511387 [CA 1] Center 35 (5~66) winsize 62
4351 09:28:36.514743 [CA 2] Center 34 (4~65) winsize 62
4352 09:28:36.518141 [CA 3] Center 33 (3~64) winsize 62
4353 09:28:36.521409 [CA 4] Center 33 (3~64) winsize 62
4354 09:28:36.524534 [CA 5] Center 33 (3~64) winsize 62
4355 09:28:36.524641
4356 09:28:36.528276 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4357 09:28:36.528374
4358 09:28:36.531392 [CATrainingPosCal] consider 1 rank data
4359 09:28:36.534674 u2DelayCellTimex100 = 270/100 ps
4360 09:28:36.537906 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4361 09:28:36.541287 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4362 09:28:36.544494 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4363 09:28:36.547865 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4364 09:28:36.551443 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4365 09:28:36.554466 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4366 09:28:36.554537
4367 09:28:36.561406 CA PerBit enable=1, Macro0, CA PI delay=33
4368 09:28:36.561478
4369 09:28:36.561538 [CBTSetCACLKResult] CA Dly = 33
4370 09:28:36.564473 CS Dly: 4 (0~35)
4371 09:28:36.564542 ==
4372 09:28:36.567794 Dram Type= 6, Freq= 0, CH_1, rank 1
4373 09:28:36.571294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 09:28:36.571367 ==
4375 09:28:36.578135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 09:28:36.584451 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4377 09:28:36.588293 [CA 0] Center 35 (5~66) winsize 62
4378 09:28:36.591497 [CA 1] Center 35 (5~66) winsize 62
4379 09:28:36.594873 [CA 2] Center 34 (4~65) winsize 62
4380 09:28:36.598025 [CA 3] Center 34 (4~64) winsize 61
4381 09:28:36.601366 [CA 4] Center 34 (4~65) winsize 62
4382 09:28:36.604614 [CA 5] Center 33 (3~64) winsize 62
4383 09:28:36.604691
4384 09:28:36.607932 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4385 09:28:36.608008
4386 09:28:36.611202 [CATrainingPosCal] consider 2 rank data
4387 09:28:36.614563 u2DelayCellTimex100 = 270/100 ps
4388 09:28:36.617889 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4389 09:28:36.621297 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4390 09:28:36.624595 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4391 09:28:36.627889 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4392 09:28:36.631544 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4393 09:28:36.634856 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4394 09:28:36.634944
4395 09:28:36.641388 CA PerBit enable=1, Macro0, CA PI delay=33
4396 09:28:36.641480
4397 09:28:36.641546 [CBTSetCACLKResult] CA Dly = 33
4398 09:28:36.644539 CS Dly: 5 (0~37)
4399 09:28:36.644663
4400 09:28:36.647853 ----->DramcWriteLeveling(PI) begin...
4401 09:28:36.647929 ==
4402 09:28:36.651050 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 09:28:36.654298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 09:28:36.654373 ==
4405 09:28:36.657845 Write leveling (Byte 0): 28 => 28
4406 09:28:36.661457 Write leveling (Byte 1): 31 => 31
4407 09:28:36.664466 DramcWriteLeveling(PI) end<-----
4408 09:28:36.664621
4409 09:28:36.664687 ==
4410 09:28:36.667603 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 09:28:36.671248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 09:28:36.674286 ==
4413 09:28:36.674360 [Gating] SW mode calibration
4414 09:28:36.684543 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4415 09:28:36.687644 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4416 09:28:36.690973 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 09:28:36.697586 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 09:28:36.700891 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 09:28:36.704281 0 9 12 | B1->B0 | 2f2f 2e2e | 1 0 | (1 0) (0 0)
4420 09:28:36.711197 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 09:28:36.714480 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 09:28:36.717804 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 09:28:36.724284 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 09:28:36.728017 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 09:28:36.731205 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 09:28:36.737741 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4427 09:28:36.741027 0 10 12 | B1->B0 | 3636 4040 | 0 0 | (0 0) (0 0)
4428 09:28:36.744265 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 09:28:36.750751 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 09:28:36.754148 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 09:28:36.757370 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 09:28:36.760979 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 09:28:36.767411 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 09:28:36.770694 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 09:28:36.774324 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4436 09:28:36.780705 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 09:28:36.783925 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 09:28:36.787680 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 09:28:36.794060 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 09:28:36.797619 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 09:28:36.800702 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 09:28:36.807310 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 09:28:36.810493 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 09:28:36.813832 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 09:28:36.820880 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 09:28:36.824209 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 09:28:36.827583 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 09:28:36.833885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 09:28:36.837121 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 09:28:36.840287 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4451 09:28:36.846966 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 09:28:36.847046 Total UI for P1: 0, mck2ui 16
4453 09:28:36.854135 best dqsien dly found for B0: ( 0, 13, 8)
4454 09:28:36.854249 Total UI for P1: 0, mck2ui 16
4455 09:28:36.860609 best dqsien dly found for B1: ( 0, 13, 10)
4456 09:28:36.863861 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4457 09:28:36.867109 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4458 09:28:36.867186
4459 09:28:36.870297 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4460 09:28:36.873916 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4461 09:28:36.877226 [Gating] SW calibration Done
4462 09:28:36.877303 ==
4463 09:28:36.880276 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 09:28:36.883805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 09:28:36.883883 ==
4466 09:28:36.887470 RX Vref Scan: 0
4467 09:28:36.887546
4468 09:28:36.887609 RX Vref 0 -> 0, step: 1
4469 09:28:36.887678
4470 09:28:36.890459 RX Delay -230 -> 252, step: 16
4471 09:28:36.893987 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4472 09:28:36.900468 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4473 09:28:36.903750 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4474 09:28:36.906960 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4475 09:28:36.910636 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4476 09:28:36.917188 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4477 09:28:36.920376 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4478 09:28:36.923663 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4479 09:28:36.926860 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4480 09:28:36.930210 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4481 09:28:36.937221 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4482 09:28:36.940394 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4483 09:28:36.943456 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4484 09:28:36.946778 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4485 09:28:36.953856 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4486 09:28:36.957029 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4487 09:28:36.957128 ==
4488 09:28:36.960319 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 09:28:36.963940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 09:28:36.964038 ==
4491 09:28:36.967278 DQS Delay:
4492 09:28:36.967375 DQS0 = 0, DQS1 = 0
4493 09:28:36.967455 DQM Delay:
4494 09:28:36.970535 DQM0 = 51, DQM1 = 43
4495 09:28:36.970617 DQ Delay:
4496 09:28:36.973874 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4497 09:28:36.977036 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4498 09:28:36.980553 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4499 09:28:36.983635 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4500 09:28:36.983718
4501 09:28:36.983783
4502 09:28:36.983845 ==
4503 09:28:36.986791 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 09:28:36.993370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 09:28:36.993455 ==
4506 09:28:36.993521
4507 09:28:36.993583
4508 09:28:36.993642 TX Vref Scan disable
4509 09:28:36.997271 == TX Byte 0 ==
4510 09:28:37.000459 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4511 09:28:37.006946 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4512 09:28:37.007032 == TX Byte 1 ==
4513 09:28:37.010314 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4514 09:28:37.017219 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4515 09:28:37.017307 ==
4516 09:28:37.020505 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 09:28:37.023892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 09:28:37.023977 ==
4519 09:28:37.024044
4520 09:28:37.024105
4521 09:28:37.027122 TX Vref Scan disable
4522 09:28:37.030382 == TX Byte 0 ==
4523 09:28:37.033743 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4524 09:28:37.036948 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4525 09:28:37.037032 == TX Byte 1 ==
4526 09:28:37.043891 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4527 09:28:37.047137 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4528 09:28:37.047221
4529 09:28:37.047305 [DATLAT]
4530 09:28:37.050472 Freq=600, CH1 RK0
4531 09:28:37.050556
4532 09:28:37.050622 DATLAT Default: 0x9
4533 09:28:37.053685 0, 0xFFFF, sum = 0
4534 09:28:37.053770 1, 0xFFFF, sum = 0
4535 09:28:37.056891 2, 0xFFFF, sum = 0
4536 09:28:37.060191 3, 0xFFFF, sum = 0
4537 09:28:37.060276 4, 0xFFFF, sum = 0
4538 09:28:37.063881 5, 0xFFFF, sum = 0
4539 09:28:37.063966 6, 0xFFFF, sum = 0
4540 09:28:37.067068 7, 0xFFFF, sum = 0
4541 09:28:37.067154 8, 0x0, sum = 1
4542 09:28:37.067242 9, 0x0, sum = 2
4543 09:28:37.070303 10, 0x0, sum = 3
4544 09:28:37.070389 11, 0x0, sum = 4
4545 09:28:37.073604 best_step = 9
4546 09:28:37.073688
4547 09:28:37.073755 ==
4548 09:28:37.076789 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 09:28:37.080171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 09:28:37.080256 ==
4551 09:28:37.083758 RX Vref Scan: 1
4552 09:28:37.083842
4553 09:28:37.083908 RX Vref 0 -> 0, step: 1
4554 09:28:37.083970
4555 09:28:37.086916 RX Delay -179 -> 252, step: 8
4556 09:28:37.087000
4557 09:28:37.090535 Set Vref, RX VrefLevel [Byte0]: 52
4558 09:28:37.093763 [Byte1]: 52
4559 09:28:37.097386
4560 09:28:37.097470 Final RX Vref Byte 0 = 52 to rank0
4561 09:28:37.101075 Final RX Vref Byte 1 = 52 to rank0
4562 09:28:37.104182 Final RX Vref Byte 0 = 52 to rank1
4563 09:28:37.107597 Final RX Vref Byte 1 = 52 to rank1==
4564 09:28:37.110812 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 09:28:37.117692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 09:28:37.117792 ==
4567 09:28:37.117860 DQS Delay:
4568 09:28:37.117923 DQS0 = 0, DQS1 = 0
4569 09:28:37.120924 DQM Delay:
4570 09:28:37.121007 DQM0 = 48, DQM1 = 41
4571 09:28:37.124264 DQ Delay:
4572 09:28:37.127445 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4573 09:28:37.127562 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4574 09:28:37.130752 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4575 09:28:37.137413 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4576 09:28:37.137491
4577 09:28:37.137555
4578 09:28:37.143839 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4579 09:28:37.147551 CH1 RK0: MR19=808, MR18=4A71
4580 09:28:37.153927 CH1_RK0: MR19=0x808, MR18=0x4A71, DQSOSC=388, MR23=63, INC=174, DEC=116
4581 09:28:37.154017
4582 09:28:37.157201 ----->DramcWriteLeveling(PI) begin...
4583 09:28:37.157274 ==
4584 09:28:37.160368 Dram Type= 6, Freq= 0, CH_1, rank 1
4585 09:28:37.163744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 09:28:37.163818 ==
4587 09:28:37.167398 Write leveling (Byte 0): 28 => 28
4588 09:28:37.170536 Write leveling (Byte 1): 30 => 30
4589 09:28:37.173683 DramcWriteLeveling(PI) end<-----
4590 09:28:37.173755
4591 09:28:37.173834 ==
4592 09:28:37.177497 Dram Type= 6, Freq= 0, CH_1, rank 1
4593 09:28:37.180750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 09:28:37.180827 ==
4595 09:28:37.183854 [Gating] SW mode calibration
4596 09:28:37.190579 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4597 09:28:37.197157 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4598 09:28:37.200303 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4599 09:28:37.203823 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4600 09:28:37.210490 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 09:28:37.213907 0 9 12 | B1->B0 | 2727 3030 | 1 1 | (1 0) (1 0)
4602 09:28:37.217108 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 09:28:37.223630 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 09:28:37.226925 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 09:28:37.230176 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 09:28:37.237155 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 09:28:37.240344 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 09:28:37.243657 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 09:28:37.250529 0 10 12 | B1->B0 | 3f3f 2f2f | 0 0 | (0 0) (0 0)
4610 09:28:37.253835 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 09:28:37.257039 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 09:28:37.263435 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 09:28:37.266723 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 09:28:37.270300 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 09:28:37.276809 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 09:28:37.280015 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4617 09:28:37.283264 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4618 09:28:37.290273 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 09:28:37.293494 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 09:28:37.296966 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 09:28:37.303321 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 09:28:37.306571 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 09:28:37.310211 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 09:28:37.316868 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 09:28:37.320399 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 09:28:37.323736 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 09:28:37.327018 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 09:28:37.333669 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 09:28:37.336919 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 09:28:37.340251 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 09:28:37.346698 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 09:28:37.350400 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 09:28:37.353660 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 09:28:37.356970 Total UI for P1: 0, mck2ui 16
4635 09:28:37.360198 best dqsien dly found for B0: ( 0, 13, 10)
4636 09:28:37.363471 Total UI for P1: 0, mck2ui 16
4637 09:28:37.366688 best dqsien dly found for B1: ( 0, 13, 10)
4638 09:28:37.369860 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4639 09:28:37.373094 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4640 09:28:37.376937
4641 09:28:37.380192 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4642 09:28:37.383277 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4643 09:28:37.386520 [Gating] SW calibration Done
4644 09:28:37.386633 ==
4645 09:28:37.389843 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 09:28:37.393529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 09:28:37.393667 ==
4648 09:28:37.393760 RX Vref Scan: 0
4649 09:28:37.396609
4650 09:28:37.396712 RX Vref 0 -> 0, step: 1
4651 09:28:37.396802
4652 09:28:37.400156 RX Delay -230 -> 252, step: 16
4653 09:28:37.403248 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4654 09:28:37.409539 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4655 09:28:37.413131 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4656 09:28:37.416331 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4657 09:28:37.420069 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4658 09:28:37.423224 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4659 09:28:37.429583 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4660 09:28:37.433326 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4661 09:28:37.436632 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4662 09:28:37.439816 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4663 09:28:37.443197 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4664 09:28:37.449601 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4665 09:28:37.452893 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4666 09:28:37.456658 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4667 09:28:37.459893 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4668 09:28:37.466398 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4669 09:28:37.466488 ==
4670 09:28:37.469725 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 09:28:37.472999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 09:28:37.473076 ==
4673 09:28:37.473151 DQS Delay:
4674 09:28:37.476235 DQS0 = 0, DQS1 = 0
4675 09:28:37.476308 DQM Delay:
4676 09:28:37.479994 DQM0 = 51, DQM1 = 46
4677 09:28:37.480076 DQ Delay:
4678 09:28:37.483259 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4679 09:28:37.486414 DQ4 =49, DQ5 =65, DQ6 =49, DQ7 =49
4680 09:28:37.489581 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4681 09:28:37.492868 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4682 09:28:37.492943
4683 09:28:37.493016
4684 09:28:37.493076 ==
4685 09:28:37.496207 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 09:28:37.499871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 09:28:37.499949 ==
4688 09:28:37.503075
4689 09:28:37.503163
4690 09:28:37.503228 TX Vref Scan disable
4691 09:28:37.506206 == TX Byte 0 ==
4692 09:28:37.509491 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4693 09:28:37.513058 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4694 09:28:37.516175 == TX Byte 1 ==
4695 09:28:37.519448 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4696 09:28:37.523181 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4697 09:28:37.523256 ==
4698 09:28:37.526256 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 09:28:37.533155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 09:28:37.533234 ==
4701 09:28:37.533310
4702 09:28:37.533372
4703 09:28:37.533430 TX Vref Scan disable
4704 09:28:37.537541 == TX Byte 0 ==
4705 09:28:37.540866 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4706 09:28:37.544095 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4707 09:28:37.547363 == TX Byte 1 ==
4708 09:28:37.551096 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4709 09:28:37.557476 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4710 09:28:37.557553
4711 09:28:37.557629 [DATLAT]
4712 09:28:37.557690 Freq=600, CH1 RK1
4713 09:28:37.557749
4714 09:28:37.560848 DATLAT Default: 0x9
4715 09:28:37.560918 0, 0xFFFF, sum = 0
4716 09:28:37.564110 1, 0xFFFF, sum = 0
4717 09:28:37.564195 2, 0xFFFF, sum = 0
4718 09:28:37.567397 3, 0xFFFF, sum = 0
4719 09:28:37.567470 4, 0xFFFF, sum = 0
4720 09:28:37.570762 5, 0xFFFF, sum = 0
4721 09:28:37.573923 6, 0xFFFF, sum = 0
4722 09:28:37.573998 7, 0xFFFF, sum = 0
4723 09:28:37.574069 8, 0x0, sum = 1
4724 09:28:37.577646 9, 0x0, sum = 2
4725 09:28:37.577733 10, 0x0, sum = 3
4726 09:28:37.580559 11, 0x0, sum = 4
4727 09:28:37.580665 best_step = 9
4728 09:28:37.580735
4729 09:28:37.580794 ==
4730 09:28:37.583850 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 09:28:37.590872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 09:28:37.590961 ==
4733 09:28:37.591026 RX Vref Scan: 0
4734 09:28:37.591085
4735 09:28:37.594189 RX Vref 0 -> 0, step: 1
4736 09:28:37.594264
4737 09:28:37.597438 RX Delay -179 -> 252, step: 8
4738 09:28:37.600688 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4739 09:28:37.607253 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4740 09:28:37.610769 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4741 09:28:37.613935 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4742 09:28:37.617567 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4743 09:28:37.620731 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4744 09:28:37.627628 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4745 09:28:37.630700 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4746 09:28:37.634312 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4747 09:28:37.637522 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4748 09:28:37.640872 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4749 09:28:37.647492 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4750 09:28:37.650704 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4751 09:28:37.653880 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4752 09:28:37.657066 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4753 09:28:37.660868 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4754 09:28:37.664144 ==
4755 09:28:37.667389 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 09:28:37.670681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 09:28:37.670770 ==
4758 09:28:37.670841 DQS Delay:
4759 09:28:37.673920 DQS0 = 0, DQS1 = 0
4760 09:28:37.674002 DQM Delay:
4761 09:28:37.677171 DQM0 = 49, DQM1 = 44
4762 09:28:37.677246 DQ Delay:
4763 09:28:37.680353 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =48
4764 09:28:37.684086 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4765 09:28:37.687343 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4766 09:28:37.690590 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4767 09:28:37.690725
4768 09:28:37.690805
4769 09:28:37.697254 [DQSOSCAuto] RK1, (LSB)MR18= 0x571e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4770 09:28:37.700503 CH1 RK1: MR19=808, MR18=571E
4771 09:28:37.707163 CH1_RK1: MR19=0x808, MR18=0x571E, DQSOSC=393, MR23=63, INC=169, DEC=113
4772 09:28:37.710402 [RxdqsGatingPostProcess] freq 600
4773 09:28:37.716863 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4774 09:28:37.716948 Pre-setting of DQS Precalculation
4775 09:28:37.723684 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4776 09:28:37.730497 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4777 09:28:37.736867 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4778 09:28:37.736977
4779 09:28:37.737071
4780 09:28:37.740436 [Calibration Summary] 1200 Mbps
4781 09:28:37.743753 CH 0, Rank 0
4782 09:28:37.743836 SW Impedance : PASS
4783 09:28:37.747111 DUTY Scan : NO K
4784 09:28:37.750399 ZQ Calibration : PASS
4785 09:28:37.750482 Jitter Meter : NO K
4786 09:28:37.753614 CBT Training : PASS
4787 09:28:37.753697 Write leveling : PASS
4788 09:28:37.756844 RX DQS gating : PASS
4789 09:28:37.760504 RX DQ/DQS(RDDQC) : PASS
4790 09:28:37.760636 TX DQ/DQS : PASS
4791 09:28:37.763792 RX DATLAT : PASS
4792 09:28:37.767104 RX DQ/DQS(Engine): PASS
4793 09:28:37.767187 TX OE : NO K
4794 09:28:37.770432 All Pass.
4795 09:28:37.770514
4796 09:28:37.770580 CH 0, Rank 1
4797 09:28:37.773620 SW Impedance : PASS
4798 09:28:37.773703 DUTY Scan : NO K
4799 09:28:37.776980 ZQ Calibration : PASS
4800 09:28:37.780169 Jitter Meter : NO K
4801 09:28:37.780278 CBT Training : PASS
4802 09:28:37.783919 Write leveling : PASS
4803 09:28:37.787203 RX DQS gating : PASS
4804 09:28:37.787286 RX DQ/DQS(RDDQC) : PASS
4805 09:28:37.790578 TX DQ/DQS : PASS
4806 09:28:37.790660 RX DATLAT : PASS
4807 09:28:37.793829 RX DQ/DQS(Engine): PASS
4808 09:28:37.797044 TX OE : NO K
4809 09:28:37.797127 All Pass.
4810 09:28:37.797192
4811 09:28:37.797253 CH 1, Rank 0
4812 09:28:37.800367 SW Impedance : PASS
4813 09:28:37.803622 DUTY Scan : NO K
4814 09:28:37.803704 ZQ Calibration : PASS
4815 09:28:37.806909 Jitter Meter : NO K
4816 09:28:37.810192 CBT Training : PASS
4817 09:28:37.810274 Write leveling : PASS
4818 09:28:37.813379 RX DQS gating : PASS
4819 09:28:37.816929 RX DQ/DQS(RDDQC) : PASS
4820 09:28:37.817013 TX DQ/DQS : PASS
4821 09:28:37.820276 RX DATLAT : PASS
4822 09:28:37.823438 RX DQ/DQS(Engine): PASS
4823 09:28:37.823520 TX OE : NO K
4824 09:28:37.826944 All Pass.
4825 09:28:37.827106
4826 09:28:37.827265 CH 1, Rank 1
4827 09:28:37.830115 SW Impedance : PASS
4828 09:28:37.830201 DUTY Scan : NO K
4829 09:28:37.833788 ZQ Calibration : PASS
4830 09:28:37.836951 Jitter Meter : NO K
4831 09:28:37.837034 CBT Training : PASS
4832 09:28:37.840044 Write leveling : PASS
4833 09:28:37.840126 RX DQS gating : PASS
4834 09:28:37.843332 RX DQ/DQS(RDDQC) : PASS
4835 09:28:37.847087 TX DQ/DQS : PASS
4836 09:28:37.847171 RX DATLAT : PASS
4837 09:28:37.850293 RX DQ/DQS(Engine): PASS
4838 09:28:37.853483 TX OE : NO K
4839 09:28:37.853569 All Pass.
4840 09:28:37.853638
4841 09:28:37.856782 DramC Write-DBI off
4842 09:28:37.856864 PER_BANK_REFRESH: Hybrid Mode
4843 09:28:37.859972 TX_TRACKING: ON
4844 09:28:37.866591 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4845 09:28:37.873606 [FAST_K] Save calibration result to emmc
4846 09:28:37.876796 dramc_set_vcore_voltage set vcore to 662500
4847 09:28:37.876904 Read voltage for 933, 3
4848 09:28:37.880101 Vio18 = 0
4849 09:28:37.880193 Vcore = 662500
4850 09:28:37.880280 Vdram = 0
4851 09:28:37.883378 Vddq = 0
4852 09:28:37.883461 Vmddr = 0
4853 09:28:37.886578 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4854 09:28:37.893187 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4855 09:28:37.896408 MEM_TYPE=3, freq_sel=17
4856 09:28:37.899660 sv_algorithm_assistance_LP4_1600
4857 09:28:37.903496 ============ PULL DRAM RESETB DOWN ============
4858 09:28:37.906670 ========== PULL DRAM RESETB DOWN end =========
4859 09:28:37.913197 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4860 09:28:37.916367 ===================================
4861 09:28:37.916478 LPDDR4 DRAM CONFIGURATION
4862 09:28:37.920077 ===================================
4863 09:28:37.923027 EX_ROW_EN[0] = 0x0
4864 09:28:37.923110 EX_ROW_EN[1] = 0x0
4865 09:28:37.926764 LP4Y_EN = 0x0
4866 09:28:37.926847 WORK_FSP = 0x0
4867 09:28:37.929964 WL = 0x3
4868 09:28:37.930047 RL = 0x3
4869 09:28:37.933200 BL = 0x2
4870 09:28:37.936353 RPST = 0x0
4871 09:28:37.936474 RD_PRE = 0x0
4872 09:28:37.939834 WR_PRE = 0x1
4873 09:28:37.939917 WR_PST = 0x0
4874 09:28:37.943078 DBI_WR = 0x0
4875 09:28:37.943161 DBI_RD = 0x0
4876 09:28:37.946603 OTF = 0x1
4877 09:28:37.949931 ===================================
4878 09:28:37.953341 ===================================
4879 09:28:37.953424 ANA top config
4880 09:28:37.956436 ===================================
4881 09:28:37.959766 DLL_ASYNC_EN = 0
4882 09:28:37.963037 ALL_SLAVE_EN = 1
4883 09:28:37.963120 NEW_RANK_MODE = 1
4884 09:28:37.966235 DLL_IDLE_MODE = 1
4885 09:28:37.969547 LP45_APHY_COMB_EN = 1
4886 09:28:37.972806 TX_ODT_DIS = 1
4887 09:28:37.972890 NEW_8X_MODE = 1
4888 09:28:37.976047 ===================================
4889 09:28:37.979380 ===================================
4890 09:28:37.983069 data_rate = 1866
4891 09:28:37.986299 CKR = 1
4892 09:28:37.989464 DQ_P2S_RATIO = 8
4893 09:28:37.992728 ===================================
4894 09:28:37.995887 CA_P2S_RATIO = 8
4895 09:28:37.999593 DQ_CA_OPEN = 0
4896 09:28:38.002896 DQ_SEMI_OPEN = 0
4897 09:28:38.002979 CA_SEMI_OPEN = 0
4898 09:28:38.006242 CA_FULL_RATE = 0
4899 09:28:38.009349 DQ_CKDIV4_EN = 1
4900 09:28:38.012533 CA_CKDIV4_EN = 1
4901 09:28:38.015971 CA_PREDIV_EN = 0
4902 09:28:38.019049 PH8_DLY = 0
4903 09:28:38.019132 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4904 09:28:38.022344 DQ_AAMCK_DIV = 4
4905 09:28:38.025920 CA_AAMCK_DIV = 4
4906 09:28:38.029734 CA_ADMCK_DIV = 4
4907 09:28:38.032855 DQ_TRACK_CA_EN = 0
4908 09:28:38.035803 CA_PICK = 933
4909 09:28:38.035885 CA_MCKIO = 933
4910 09:28:38.038997 MCKIO_SEMI = 0
4911 09:28:38.042626 PLL_FREQ = 3732
4912 09:28:38.045758 DQ_UI_PI_RATIO = 32
4913 09:28:38.049500 CA_UI_PI_RATIO = 0
4914 09:28:38.052684 ===================================
4915 09:28:38.055922 ===================================
4916 09:28:38.059066 memory_type:LPDDR4
4917 09:28:38.059149 GP_NUM : 10
4918 09:28:38.062962 SRAM_EN : 1
4919 09:28:38.063045 MD32_EN : 0
4920 09:28:38.066214 ===================================
4921 09:28:38.069444 [ANA_INIT] >>>>>>>>>>>>>>
4922 09:28:38.072742 <<<<<< [CONFIGURE PHASE]: ANA_TX
4923 09:28:38.075980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4924 09:28:38.079257 ===================================
4925 09:28:38.082538 data_rate = 1866,PCW = 0X8f00
4926 09:28:38.086035 ===================================
4927 09:28:38.089462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4928 09:28:38.092680 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4929 09:28:38.099355 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4930 09:28:38.105871 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4931 09:28:38.109139 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4932 09:28:38.112362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4933 09:28:38.112483 [ANA_INIT] flow start
4934 09:28:38.115635 [ANA_INIT] PLL >>>>>>>>
4935 09:28:38.118945 [ANA_INIT] PLL <<<<<<<<
4936 09:28:38.119028 [ANA_INIT] MIDPI >>>>>>>>
4937 09:28:38.122127 [ANA_INIT] MIDPI <<<<<<<<
4938 09:28:38.125421 [ANA_INIT] DLL >>>>>>>>
4939 09:28:38.125504 [ANA_INIT] flow end
4940 09:28:38.131925 ============ LP4 DIFF to SE enter ============
4941 09:28:38.135547 ============ LP4 DIFF to SE exit ============
4942 09:28:38.135631 [ANA_INIT] <<<<<<<<<<<<<
4943 09:28:38.138670 [Flow] Enable top DCM control >>>>>
4944 09:28:38.142207 [Flow] Enable top DCM control <<<<<
4945 09:28:38.145317 Enable DLL master slave shuffle
4946 09:28:38.152135 ==============================================================
4947 09:28:38.155281 Gating Mode config
4948 09:28:38.159075 ==============================================================
4949 09:28:38.162318 Config description:
4950 09:28:38.172035 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4951 09:28:38.178588 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4952 09:28:38.181881 SELPH_MODE 0: By rank 1: By Phase
4953 09:28:38.188770 ==============================================================
4954 09:28:38.191999 GAT_TRACK_EN = 1
4955 09:28:38.195354 RX_GATING_MODE = 2
4956 09:28:38.198626 RX_GATING_TRACK_MODE = 2
4957 09:28:38.198710 SELPH_MODE = 1
4958 09:28:38.201828 PICG_EARLY_EN = 1
4959 09:28:38.204980 VALID_LAT_VALUE = 1
4960 09:28:38.211985 ==============================================================
4961 09:28:38.215355 Enter into Gating configuration >>>>
4962 09:28:38.218625 Exit from Gating configuration <<<<
4963 09:28:38.221905 Enter into DVFS_PRE_config >>>>>
4964 09:28:38.231508 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4965 09:28:38.235298 Exit from DVFS_PRE_config <<<<<
4966 09:28:38.238432 Enter into PICG configuration >>>>
4967 09:28:38.242182 Exit from PICG configuration <<<<
4968 09:28:38.245366 [RX_INPUT] configuration >>>>>
4969 09:28:38.248464 [RX_INPUT] configuration <<<<<
4970 09:28:38.251975 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4971 09:28:38.258339 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4972 09:28:38.265261 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 09:28:38.271662 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 09:28:38.274954 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 09:28:38.282097 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 09:28:38.285399 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4977 09:28:38.291671 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4978 09:28:38.295395 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4979 09:28:38.298710 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4980 09:28:38.301857 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4981 09:28:38.308274 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4982 09:28:38.311541 ===================================
4983 09:28:38.311617 LPDDR4 DRAM CONFIGURATION
4984 09:28:38.315313 ===================================
4985 09:28:38.318543 EX_ROW_EN[0] = 0x0
4986 09:28:38.321835 EX_ROW_EN[1] = 0x0
4987 09:28:38.321906 LP4Y_EN = 0x0
4988 09:28:38.325019 WORK_FSP = 0x0
4989 09:28:38.325096 WL = 0x3
4990 09:28:38.328352 RL = 0x3
4991 09:28:38.328418 BL = 0x2
4992 09:28:38.331547 RPST = 0x0
4993 09:28:38.331615 RD_PRE = 0x0
4994 09:28:38.334835 WR_PRE = 0x1
4995 09:28:38.334907 WR_PST = 0x0
4996 09:28:38.338694 DBI_WR = 0x0
4997 09:28:38.338761 DBI_RD = 0x0
4998 09:28:38.341864 OTF = 0x1
4999 09:28:38.345058 ===================================
5000 09:28:38.348280 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5001 09:28:38.351307 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5002 09:28:38.358237 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5003 09:28:38.361880 ===================================
5004 09:28:38.361951 LPDDR4 DRAM CONFIGURATION
5005 09:28:38.365022 ===================================
5006 09:28:38.368237 EX_ROW_EN[0] = 0x10
5007 09:28:38.368304 EX_ROW_EN[1] = 0x0
5008 09:28:38.371526 LP4Y_EN = 0x0
5009 09:28:38.374760 WORK_FSP = 0x0
5010 09:28:38.374828 WL = 0x3
5011 09:28:38.378563 RL = 0x3
5012 09:28:38.378633 BL = 0x2
5013 09:28:38.381849 RPST = 0x0
5014 09:28:38.381928 RD_PRE = 0x0
5015 09:28:38.385220 WR_PRE = 0x1
5016 09:28:38.385300 WR_PST = 0x0
5017 09:28:38.388459 DBI_WR = 0x0
5018 09:28:38.388583 DBI_RD = 0x0
5019 09:28:38.391667 OTF = 0x1
5020 09:28:38.394892 ===================================
5021 09:28:38.401806 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5022 09:28:38.405001 nWR fixed to 30
5023 09:28:38.405086 [ModeRegInit_LP4] CH0 RK0
5024 09:28:38.408257 [ModeRegInit_LP4] CH0 RK1
5025 09:28:38.411496 [ModeRegInit_LP4] CH1 RK0
5026 09:28:38.411567 [ModeRegInit_LP4] CH1 RK1
5027 09:28:38.414851 match AC timing 9
5028 09:28:38.418151 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5029 09:28:38.421298 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5030 09:28:38.428356 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5031 09:28:38.431650 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5032 09:28:38.437946 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5033 09:28:38.438019 ==
5034 09:28:38.441309 Dram Type= 6, Freq= 0, CH_0, rank 0
5035 09:28:38.444657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5036 09:28:38.444746 ==
5037 09:28:38.451483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5038 09:28:38.457672 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5039 09:28:38.461205 [CA 0] Center 37 (7~68) winsize 62
5040 09:28:38.464421 [CA 1] Center 38 (8~69) winsize 62
5041 09:28:38.467493 [CA 2] Center 35 (5~66) winsize 62
5042 09:28:38.471187 [CA 3] Center 35 (5~66) winsize 62
5043 09:28:38.474327 [CA 4] Center 34 (4~65) winsize 62
5044 09:28:38.474399 [CA 5] Center 33 (3~64) winsize 62
5045 09:28:38.477526
5046 09:28:38.480831 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5047 09:28:38.480902
5048 09:28:38.484520 [CATrainingPosCal] consider 1 rank data
5049 09:28:38.487885 u2DelayCellTimex100 = 270/100 ps
5050 09:28:38.491228 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5051 09:28:38.494386 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5052 09:28:38.497642 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5053 09:28:38.500891 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5054 09:28:38.504228 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5055 09:28:38.507904 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5056 09:28:38.507977
5057 09:28:38.511214 CA PerBit enable=1, Macro0, CA PI delay=33
5058 09:28:38.514530
5059 09:28:38.514608 [CBTSetCACLKResult] CA Dly = 33
5060 09:28:38.517805 CS Dly: 6 (0~37)
5061 09:28:38.517875 ==
5062 09:28:38.520937 Dram Type= 6, Freq= 0, CH_0, rank 1
5063 09:28:38.524381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 09:28:38.524479 ==
5065 09:28:38.530901 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 09:28:38.537525 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5067 09:28:38.540786 [CA 0] Center 38 (7~69) winsize 63
5068 09:28:38.544042 [CA 1] Center 38 (8~69) winsize 62
5069 09:28:38.547882 [CA 2] Center 36 (6~66) winsize 61
5070 09:28:38.551133 [CA 3] Center 35 (5~66) winsize 62
5071 09:28:38.554219 [CA 4] Center 34 (4~65) winsize 62
5072 09:28:38.558133 [CA 5] Center 34 (4~65) winsize 62
5073 09:28:38.558307
5074 09:28:38.561492 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5075 09:28:38.561715
5076 09:28:38.564456 [CATrainingPosCal] consider 2 rank data
5077 09:28:38.567753 u2DelayCellTimex100 = 270/100 ps
5078 09:28:38.571261 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5079 09:28:38.574159 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5080 09:28:38.577844 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5081 09:28:38.581319 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5082 09:28:38.584820 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5083 09:28:38.587924 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5084 09:28:38.588181
5085 09:28:38.594372 CA PerBit enable=1, Macro0, CA PI delay=34
5086 09:28:38.594644
5087 09:28:38.594866 [CBTSetCACLKResult] CA Dly = 34
5088 09:28:38.597661 CS Dly: 7 (0~39)
5089 09:28:38.597912
5090 09:28:38.600890 ----->DramcWriteLeveling(PI) begin...
5091 09:28:38.601322 ==
5092 09:28:38.604130 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 09:28:38.607998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 09:28:38.608453 ==
5095 09:28:38.610994 Write leveling (Byte 0): 32 => 32
5096 09:28:38.614126 Write leveling (Byte 1): 30 => 30
5097 09:28:38.617356 DramcWriteLeveling(PI) end<-----
5098 09:28:38.618002
5099 09:28:38.618516 ==
5100 09:28:38.620664 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 09:28:38.627163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 09:28:38.627742 ==
5103 09:28:38.628110 [Gating] SW mode calibration
5104 09:28:38.637658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5105 09:28:38.641012 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5106 09:28:38.644263 0 14 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5107 09:28:38.650778 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 09:28:38.653944 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 09:28:38.657903 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 09:28:38.664240 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 09:28:38.667527 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 09:28:38.671062 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 1)
5113 09:28:38.677487 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5114 09:28:38.680683 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5115 09:28:38.683789 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 09:28:38.690170 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 09:28:38.693911 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 09:28:38.697293 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 09:28:38.703550 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 09:28:38.707271 0 15 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5121 09:28:38.710921 0 15 28 | B1->B0 | 2c2c 4343 | 0 0 | (0 0) (0 0)
5122 09:28:38.717122 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
5123 09:28:38.720626 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 09:28:38.724165 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 09:28:38.730027 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 09:28:38.733338 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 09:28:38.736706 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 09:28:38.743840 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5129 09:28:38.746660 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5130 09:28:38.750090 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5131 09:28:38.757197 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 09:28:38.760272 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 09:28:38.763188 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 09:28:38.770424 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 09:28:38.773385 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 09:28:38.776438 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 09:28:38.783010 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 09:28:38.786896 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 09:28:38.789686 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 09:28:38.797131 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 09:28:38.799759 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 09:28:38.803157 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 09:28:38.809941 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 09:28:38.812957 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 09:28:38.816207 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5146 09:28:38.819722 Total UI for P1: 0, mck2ui 16
5147 09:28:38.823514 best dqsien dly found for B0: ( 1, 2, 26)
5148 09:28:38.826386 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5149 09:28:38.832882 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 09:28:38.836221 Total UI for P1: 0, mck2ui 16
5151 09:28:38.839426 best dqsien dly found for B1: ( 1, 2, 30)
5152 09:28:38.842713 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5153 09:28:38.846015 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5154 09:28:38.846502
5155 09:28:38.849368 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5156 09:28:38.852597 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5157 09:28:38.855733 [Gating] SW calibration Done
5158 09:28:38.856192 ==
5159 09:28:38.859211 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 09:28:38.862481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 09:28:38.862959 ==
5162 09:28:38.865738 RX Vref Scan: 0
5163 09:28:38.866266
5164 09:28:38.868937 RX Vref 0 -> 0, step: 1
5165 09:28:38.869398
5166 09:28:38.869766 RX Delay -80 -> 252, step: 8
5167 09:28:38.876372 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5168 09:28:38.879337 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5169 09:28:38.882336 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5170 09:28:38.886040 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5171 09:28:38.889157 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5172 09:28:38.895458 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5173 09:28:38.899128 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5174 09:28:38.902703 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5175 09:28:38.905690 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5176 09:28:38.908888 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5177 09:28:38.912498 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5178 09:28:38.919365 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5179 09:28:38.922430 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5180 09:28:38.925724 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5181 09:28:38.928976 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5182 09:28:38.932616 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5183 09:28:38.933241 ==
5184 09:28:38.935718 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 09:28:38.942519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 09:28:38.943079 ==
5187 09:28:38.943453 DQS Delay:
5188 09:28:38.943796 DQS0 = 0, DQS1 = 0
5189 09:28:38.945897 DQM Delay:
5190 09:28:38.946463 DQM0 = 105, DQM1 = 90
5191 09:28:38.949398 DQ Delay:
5192 09:28:38.952699 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5193 09:28:38.955636 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5194 09:28:38.959231 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5195 09:28:38.962282 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5196 09:28:38.962856
5197 09:28:38.963227
5198 09:28:38.963570 ==
5199 09:28:38.965209 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 09:28:38.969516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 09:28:38.970235 ==
5202 09:28:38.970769
5203 09:28:38.971275
5204 09:28:38.972326 TX Vref Scan disable
5205 09:28:38.975588 == TX Byte 0 ==
5206 09:28:38.978868 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5207 09:28:38.982353 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5208 09:28:38.982911 == TX Byte 1 ==
5209 09:28:38.989272 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5210 09:28:38.992126 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5211 09:28:38.992776 ==
5212 09:28:38.995436 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 09:28:38.998755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 09:28:38.999229 ==
5215 09:28:38.999631
5216 09:28:39.002450
5217 09:28:39.002917 TX Vref Scan disable
5218 09:28:39.005719 == TX Byte 0 ==
5219 09:28:39.008999 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5220 09:28:39.012254 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5221 09:28:39.015736 == TX Byte 1 ==
5222 09:28:39.019110 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5223 09:28:39.025391 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5224 09:28:39.025970
5225 09:28:39.026350 [DATLAT]
5226 09:28:39.026707 Freq=933, CH0 RK0
5227 09:28:39.027051
5228 09:28:39.028690 DATLAT Default: 0xd
5229 09:28:39.029156 0, 0xFFFF, sum = 0
5230 09:28:39.032186 1, 0xFFFF, sum = 0
5231 09:28:39.032788 2, 0xFFFF, sum = 0
5232 09:28:39.035286 3, 0xFFFF, sum = 0
5233 09:28:39.035766 4, 0xFFFF, sum = 0
5234 09:28:39.038531 5, 0xFFFF, sum = 0
5235 09:28:39.042570 6, 0xFFFF, sum = 0
5236 09:28:39.043143 7, 0xFFFF, sum = 0
5237 09:28:39.045643 8, 0xFFFF, sum = 0
5238 09:28:39.046139 9, 0xFFFF, sum = 0
5239 09:28:39.048830 10, 0x0, sum = 1
5240 09:28:39.049306 11, 0x0, sum = 2
5241 09:28:39.049682 12, 0x0, sum = 3
5242 09:28:39.052197 13, 0x0, sum = 4
5243 09:28:39.052701 best_step = 11
5244 09:28:39.053075
5245 09:28:39.053419 ==
5246 09:28:39.055311 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 09:28:39.061849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 09:28:39.062385 ==
5249 09:28:39.062758 RX Vref Scan: 1
5250 09:28:39.063103
5251 09:28:39.065549 RX Vref 0 -> 0, step: 1
5252 09:28:39.066018
5253 09:28:39.068872 RX Delay -53 -> 252, step: 4
5254 09:28:39.069340
5255 09:28:39.072424 Set Vref, RX VrefLevel [Byte0]: 58
5256 09:28:39.075958 [Byte1]: 50
5257 09:28:39.076519
5258 09:28:39.078858 Final RX Vref Byte 0 = 58 to rank0
5259 09:28:39.081872 Final RX Vref Byte 1 = 50 to rank0
5260 09:28:39.085035 Final RX Vref Byte 0 = 58 to rank1
5261 09:28:39.088784 Final RX Vref Byte 1 = 50 to rank1==
5262 09:28:39.091678 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 09:28:39.095263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 09:28:39.095735 ==
5265 09:28:39.098611 DQS Delay:
5266 09:28:39.099178 DQS0 = 0, DQS1 = 0
5267 09:28:39.102151 DQM Delay:
5268 09:28:39.102831 DQM0 = 107, DQM1 = 92
5269 09:28:39.103437 DQ Delay:
5270 09:28:39.105320 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =106
5271 09:28:39.111941 DQ4 =108, DQ5 =100, DQ6 =116, DQ7 =114
5272 09:28:39.112625 DQ8 =88, DQ9 =76, DQ10 =92, DQ11 =92
5273 09:28:39.118739 DQ12 =96, DQ13 =92, DQ14 =102, DQ15 =100
5274 09:28:39.119311
5275 09:28:39.119682
5276 09:28:39.125894 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5277 09:28:39.129007 CH0 RK0: MR19=505, MR18=2622
5278 09:28:39.135622 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5279 09:28:39.136090
5280 09:28:39.139092 ----->DramcWriteLeveling(PI) begin...
5281 09:28:39.139676 ==
5282 09:28:39.141850 Dram Type= 6, Freq= 0, CH_0, rank 1
5283 09:28:39.145270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 09:28:39.145842 ==
5285 09:28:39.149004 Write leveling (Byte 0): 35 => 35
5286 09:28:39.152151 Write leveling (Byte 1): 30 => 30
5287 09:28:39.155318 DramcWriteLeveling(PI) end<-----
5288 09:28:39.155780
5289 09:28:39.156146 ==
5290 09:28:39.159050 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 09:28:39.162303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 09:28:39.163035 ==
5293 09:28:39.165270 [Gating] SW mode calibration
5294 09:28:39.171663 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5295 09:28:39.178225 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5296 09:28:39.181484 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 09:28:39.185115 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 09:28:39.191541 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 09:28:39.195172 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 09:28:39.198499 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 09:28:39.204925 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 09:28:39.208209 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5303 09:28:39.211450 0 14 28 | B1->B0 | 2626 2424 | 0 0 | (0 1) (1 0)
5304 09:28:39.218496 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 09:28:39.221486 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 09:28:39.224691 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 09:28:39.231337 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 09:28:39.234472 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 09:28:39.238213 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 09:28:39.245062 0 15 24 | B1->B0 | 2929 3030 | 1 0 | (0 0) (0 0)
5311 09:28:39.247970 0 15 28 | B1->B0 | 3939 4141 | 0 0 | (0 0) (1 1)
5312 09:28:39.251190 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 09:28:39.257985 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 09:28:39.261265 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 09:28:39.264950 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 09:28:39.271821 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 09:28:39.275196 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 09:28:39.278283 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 09:28:39.284786 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5320 09:28:39.287918 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 09:28:39.291413 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 09:28:39.297707 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 09:28:39.301358 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 09:28:39.304378 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 09:28:39.307950 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 09:28:39.314960 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 09:28:39.318041 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 09:28:39.321322 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 09:28:39.327689 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 09:28:39.330927 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 09:28:39.334448 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 09:28:39.340923 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 09:28:39.344170 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 09:28:39.347385 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5335 09:28:39.354492 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5336 09:28:39.357734 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 09:28:39.361104 Total UI for P1: 0, mck2ui 16
5338 09:28:39.364420 best dqsien dly found for B0: ( 1, 2, 26)
5339 09:28:39.367649 Total UI for P1: 0, mck2ui 16
5340 09:28:39.371035 best dqsien dly found for B1: ( 1, 2, 26)
5341 09:28:39.374398 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5342 09:28:39.377974 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5343 09:28:39.378501
5344 09:28:39.380933 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5345 09:28:39.384359 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5346 09:28:39.387438 [Gating] SW calibration Done
5347 09:28:39.387904 ==
5348 09:28:39.390777 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 09:28:39.397746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 09:28:39.398213 ==
5351 09:28:39.398579 RX Vref Scan: 0
5352 09:28:39.399036
5353 09:28:39.400932 RX Vref 0 -> 0, step: 1
5354 09:28:39.401395
5355 09:28:39.404242 RX Delay -80 -> 252, step: 8
5356 09:28:39.407309 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5357 09:28:39.410939 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5358 09:28:39.414055 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5359 09:28:39.417565 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5360 09:28:39.424457 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5361 09:28:39.427397 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5362 09:28:39.430723 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5363 09:28:39.433922 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5364 09:28:39.437233 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5365 09:28:39.440470 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5366 09:28:39.447140 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5367 09:28:39.450943 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5368 09:28:39.454583 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5369 09:28:39.457955 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5370 09:28:39.461087 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5371 09:28:39.464294 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5372 09:28:39.468014 ==
5373 09:28:39.468540 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 09:28:39.474156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 09:28:39.474674 ==
5376 09:28:39.475012 DQS Delay:
5377 09:28:39.477370 DQS0 = 0, DQS1 = 0
5378 09:28:39.477788 DQM Delay:
5379 09:28:39.480616 DQM0 = 104, DQM1 = 90
5380 09:28:39.481055 DQ Delay:
5381 09:28:39.484185 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5382 09:28:39.487408 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5383 09:28:39.490463 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5384 09:28:39.493627 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5385 09:28:39.494049
5386 09:28:39.494385
5387 09:28:39.494697 ==
5388 09:28:39.497277 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 09:28:39.500470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 09:28:39.500941 ==
5391 09:28:39.501285
5392 09:28:39.503739
5393 09:28:39.504185 TX Vref Scan disable
5394 09:28:39.507219 == TX Byte 0 ==
5395 09:28:39.510346 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5396 09:28:39.513860 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5397 09:28:39.517027 == TX Byte 1 ==
5398 09:28:39.520153 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5399 09:28:39.523728 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5400 09:28:39.524321 ==
5401 09:28:39.526854 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 09:28:39.533386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 09:28:39.533808 ==
5404 09:28:39.534141
5405 09:28:39.534450
5406 09:28:39.534751 TX Vref Scan disable
5407 09:28:39.537894 == TX Byte 0 ==
5408 09:28:39.541219 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5409 09:28:39.544413 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5410 09:28:39.547479 == TX Byte 1 ==
5411 09:28:39.550726 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5412 09:28:39.554131 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5413 09:28:39.557360
5414 09:28:39.557775 [DATLAT]
5415 09:28:39.558111 Freq=933, CH0 RK1
5416 09:28:39.558425
5417 09:28:39.560671 DATLAT Default: 0xb
5418 09:28:39.561089 0, 0xFFFF, sum = 0
5419 09:28:39.564081 1, 0xFFFF, sum = 0
5420 09:28:39.564607 2, 0xFFFF, sum = 0
5421 09:28:39.567320 3, 0xFFFF, sum = 0
5422 09:28:39.567766 4, 0xFFFF, sum = 0
5423 09:28:39.570818 5, 0xFFFF, sum = 0
5424 09:28:39.574006 6, 0xFFFF, sum = 0
5425 09:28:39.574432 7, 0xFFFF, sum = 0
5426 09:28:39.577299 8, 0xFFFF, sum = 0
5427 09:28:39.577816 9, 0xFFFF, sum = 0
5428 09:28:39.580517 10, 0x0, sum = 1
5429 09:28:39.580994 11, 0x0, sum = 2
5430 09:28:39.584391 12, 0x0, sum = 3
5431 09:28:39.584964 13, 0x0, sum = 4
5432 09:28:39.585313 best_step = 11
5433 09:28:39.585629
5434 09:28:39.587620 ==
5435 09:28:39.590918 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 09:28:39.594017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 09:28:39.594439 ==
5438 09:28:39.594775 RX Vref Scan: 0
5439 09:28:39.595091
5440 09:28:39.597382 RX Vref 0 -> 0, step: 1
5441 09:28:39.597811
5442 09:28:39.600611 RX Delay -53 -> 252, step: 4
5443 09:28:39.603805 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5444 09:28:39.610518 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5445 09:28:39.614229 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5446 09:28:39.617443 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5447 09:28:39.620619 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5448 09:28:39.624314 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5449 09:28:39.630792 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5450 09:28:39.633984 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5451 09:28:39.637217 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5452 09:28:39.640645 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5453 09:28:39.643955 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5454 09:28:39.647277 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5455 09:28:39.653874 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5456 09:28:39.657089 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5457 09:28:39.660616 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5458 09:28:39.663914 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5459 09:28:39.664446 ==
5460 09:28:39.667106 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 09:28:39.673892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 09:28:39.674423 ==
5463 09:28:39.674795 DQS Delay:
5464 09:28:39.675135 DQS0 = 0, DQS1 = 0
5465 09:28:39.677108 DQM Delay:
5466 09:28:39.677572 DQM0 = 104, DQM1 = 92
5467 09:28:39.680395 DQ Delay:
5468 09:28:39.683563 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5469 09:28:39.687425 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =112
5470 09:28:39.690618 DQ8 =84, DQ9 =80, DQ10 =96, DQ11 =90
5471 09:28:39.693651 DQ12 =98, DQ13 =96, DQ14 =100, DQ15 =98
5472 09:28:39.694399
5473 09:28:39.695032
5474 09:28:39.700282 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5475 09:28:39.703582 CH0 RK1: MR19=505, MR18=2B0B
5476 09:28:39.710127 CH0_RK1: MR19=0x505, MR18=0x2B0B, DQSOSC=408, MR23=63, INC=65, DEC=43
5477 09:28:39.713337 [RxdqsGatingPostProcess] freq 933
5478 09:28:39.720335 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5479 09:28:39.720439 best DQS0 dly(2T, 0.5T) = (0, 10)
5480 09:28:39.723468 best DQS1 dly(2T, 0.5T) = (0, 10)
5481 09:28:39.726603 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5482 09:28:39.730453 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5483 09:28:39.733161 best DQS0 dly(2T, 0.5T) = (0, 10)
5484 09:28:39.736878 best DQS1 dly(2T, 0.5T) = (0, 10)
5485 09:28:39.740185 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5486 09:28:39.743179 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5487 09:28:39.746531 Pre-setting of DQS Precalculation
5488 09:28:39.749772 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5489 09:28:39.753134 ==
5490 09:28:39.756634 Dram Type= 6, Freq= 0, CH_1, rank 0
5491 09:28:39.760223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 09:28:39.760668 ==
5493 09:28:39.763320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5494 09:28:39.770829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5495 09:28:39.773557 [CA 0] Center 37 (7~68) winsize 62
5496 09:28:39.777416 [CA 1] Center 37 (7~68) winsize 62
5497 09:28:39.780681 [CA 2] Center 36 (6~66) winsize 61
5498 09:28:39.783973 [CA 3] Center 35 (5~65) winsize 61
5499 09:28:39.787399 [CA 4] Center 35 (5~66) winsize 62
5500 09:28:39.790610 [CA 5] Center 34 (4~65) winsize 62
5501 09:28:39.791098
5502 09:28:39.793791 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5503 09:28:39.794254
5504 09:28:39.796951 [CATrainingPosCal] consider 1 rank data
5505 09:28:39.800171 u2DelayCellTimex100 = 270/100 ps
5506 09:28:39.803865 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5507 09:28:39.807183 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5508 09:28:39.813486 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5509 09:28:39.816794 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5510 09:28:39.820514 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5511 09:28:39.823647 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5512 09:28:39.824067
5513 09:28:39.826918 CA PerBit enable=1, Macro0, CA PI delay=34
5514 09:28:39.827339
5515 09:28:39.830430 [CBTSetCACLKResult] CA Dly = 34
5516 09:28:39.830849 CS Dly: 7 (0~38)
5517 09:28:39.833493 ==
5518 09:28:39.833909 Dram Type= 6, Freq= 0, CH_1, rank 1
5519 09:28:39.840372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 09:28:39.840837 ==
5521 09:28:39.843691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5522 09:28:39.850368 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5523 09:28:39.854046 [CA 0] Center 38 (8~68) winsize 61
5524 09:28:39.857217 [CA 1] Center 38 (8~68) winsize 61
5525 09:28:39.860635 [CA 2] Center 36 (6~66) winsize 61
5526 09:28:39.863958 [CA 3] Center 35 (6~65) winsize 60
5527 09:28:39.867173 [CA 4] Center 35 (5~65) winsize 61
5528 09:28:39.870770 [CA 5] Center 34 (5~64) winsize 60
5529 09:28:39.871357
5530 09:28:39.873771 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5531 09:28:39.874187
5532 09:28:39.877054 [CATrainingPosCal] consider 2 rank data
5533 09:28:39.880499 u2DelayCellTimex100 = 270/100 ps
5534 09:28:39.884539 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5535 09:28:39.887569 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5536 09:28:39.894155 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5537 09:28:39.897245 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5538 09:28:39.900722 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5539 09:28:39.904164 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5540 09:28:39.904785
5541 09:28:39.907621 CA PerBit enable=1, Macro0, CA PI delay=34
5542 09:28:39.908093
5543 09:28:39.910416 [CBTSetCACLKResult] CA Dly = 34
5544 09:28:39.910891 CS Dly: 7 (0~39)
5545 09:28:39.911305
5546 09:28:39.914254 ----->DramcWriteLeveling(PI) begin...
5547 09:28:39.917365 ==
5548 09:28:39.920640 Dram Type= 6, Freq= 0, CH_1, rank 0
5549 09:28:39.923896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 09:28:39.924373 ==
5551 09:28:39.927200 Write leveling (Byte 0): 27 => 27
5552 09:28:39.930418 Write leveling (Byte 1): 29 => 29
5553 09:28:39.934314 DramcWriteLeveling(PI) end<-----
5554 09:28:39.934896
5555 09:28:39.935275 ==
5556 09:28:39.937171 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 09:28:39.940292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 09:28:39.940810 ==
5559 09:28:39.943780 [Gating] SW mode calibration
5560 09:28:39.950323 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5561 09:28:39.954164 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5562 09:28:39.960934 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 09:28:39.963941 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 09:28:39.967192 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 09:28:39.973810 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 09:28:39.977094 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 09:28:39.980373 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5568 09:28:39.986894 0 14 24 | B1->B0 | 3030 2f2f | 0 0 | (1 0) (0 0)
5569 09:28:39.990161 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5570 09:28:39.993535 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 09:28:40.000123 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 09:28:40.003438 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 09:28:40.007102 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 09:28:40.013762 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 09:28:40.016739 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 09:28:40.019855 0 15 24 | B1->B0 | 2a2a 2e2e | 0 0 | (0 0) (0 0)
5577 09:28:40.026995 0 15 28 | B1->B0 | 3c3c 4343 | 0 0 | (0 0) (0 0)
5578 09:28:40.030278 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 09:28:40.033463 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 09:28:40.040274 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 09:28:40.043262 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 09:28:40.046945 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 09:28:40.053570 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5584 09:28:40.056694 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5585 09:28:40.060186 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 09:28:40.067037 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 09:28:40.070028 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 09:28:40.073221 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 09:28:40.080071 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 09:28:40.083555 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 09:28:40.086779 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 09:28:40.090057 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 09:28:40.096809 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 09:28:40.100190 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 09:28:40.103451 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 09:28:40.110268 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 09:28:40.113507 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 09:28:40.116717 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 09:28:40.123407 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 09:28:40.126760 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5601 09:28:40.129942 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 09:28:40.133184 Total UI for P1: 0, mck2ui 16
5603 09:28:40.136959 best dqsien dly found for B0: ( 1, 2, 24)
5604 09:28:40.140166 Total UI for P1: 0, mck2ui 16
5605 09:28:40.143261 best dqsien dly found for B1: ( 1, 2, 26)
5606 09:28:40.146810 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5607 09:28:40.149734 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5608 09:28:40.150157
5609 09:28:40.156838 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5610 09:28:40.160130 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5611 09:28:40.160678 [Gating] SW calibration Done
5612 09:28:40.163472 ==
5613 09:28:40.166726 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 09:28:40.169915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 09:28:40.170445 ==
5616 09:28:40.170791 RX Vref Scan: 0
5617 09:28:40.171111
5618 09:28:40.173427 RX Vref 0 -> 0, step: 1
5619 09:28:40.173939
5620 09:28:40.176777 RX Delay -80 -> 252, step: 8
5621 09:28:40.179617 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5622 09:28:40.182859 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5623 09:28:40.185960 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5624 09:28:40.193226 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5625 09:28:40.196599 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5626 09:28:40.199882 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5627 09:28:40.203198 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5628 09:28:40.206206 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5629 09:28:40.212656 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5630 09:28:40.216472 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5631 09:28:40.219646 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5632 09:28:40.222814 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5633 09:28:40.226072 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5634 09:28:40.232699 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5635 09:28:40.235868 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5636 09:28:40.239157 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5637 09:28:40.239581 ==
5638 09:28:40.242950 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 09:28:40.246067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 09:28:40.246489 ==
5641 09:28:40.249063 DQS Delay:
5642 09:28:40.249495 DQS0 = 0, DQS1 = 0
5643 09:28:40.249829 DQM Delay:
5644 09:28:40.252804 DQM0 = 104, DQM1 = 95
5645 09:28:40.253224 DQ Delay:
5646 09:28:40.256457 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5647 09:28:40.259361 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =103
5648 09:28:40.262533 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5649 09:28:40.265955 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5650 09:28:40.269564
5651 09:28:40.269977
5652 09:28:40.270305 ==
5653 09:28:40.272269 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 09:28:40.275722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 09:28:40.276308 ==
5656 09:28:40.276691
5657 09:28:40.277009
5658 09:28:40.278908 TX Vref Scan disable
5659 09:28:40.279326 == TX Byte 0 ==
5660 09:28:40.285542 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5661 09:28:40.289491 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5662 09:28:40.289984 == TX Byte 1 ==
5663 09:28:40.295995 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5664 09:28:40.299206 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5665 09:28:40.299630 ==
5666 09:28:40.302692 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 09:28:40.305834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 09:28:40.306260 ==
5669 09:28:40.306594
5670 09:28:40.306906
5671 09:28:40.309127 TX Vref Scan disable
5672 09:28:40.312346 == TX Byte 0 ==
5673 09:28:40.315693 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5674 09:28:40.319410 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5675 09:28:40.322777 == TX Byte 1 ==
5676 09:28:40.326265 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5677 09:28:40.329151 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5678 09:28:40.329589
5679 09:28:40.332295 [DATLAT]
5680 09:28:40.332754 Freq=933, CH1 RK0
5681 09:28:40.333190
5682 09:28:40.335530 DATLAT Default: 0xd
5683 09:28:40.336100 0, 0xFFFF, sum = 0
5684 09:28:40.339350 1, 0xFFFF, sum = 0
5685 09:28:40.339780 2, 0xFFFF, sum = 0
5686 09:28:40.342652 3, 0xFFFF, sum = 0
5687 09:28:40.343080 4, 0xFFFF, sum = 0
5688 09:28:40.345693 5, 0xFFFF, sum = 0
5689 09:28:40.346158 6, 0xFFFF, sum = 0
5690 09:28:40.349549 7, 0xFFFF, sum = 0
5691 09:28:40.349990 8, 0xFFFF, sum = 0
5692 09:28:40.352649 9, 0xFFFF, sum = 0
5693 09:28:40.353093 10, 0x0, sum = 1
5694 09:28:40.355787 11, 0x0, sum = 2
5695 09:28:40.356228 12, 0x0, sum = 3
5696 09:28:40.359282 13, 0x0, sum = 4
5697 09:28:40.359820 best_step = 11
5698 09:28:40.360363
5699 09:28:40.360743 ==
5700 09:28:40.362388 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 09:28:40.366108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 09:28:40.366790 ==
5703 09:28:40.369308 RX Vref Scan: 1
5704 09:28:40.369817
5705 09:28:40.372861 RX Vref 0 -> 0, step: 1
5706 09:28:40.373318
5707 09:28:40.373690 RX Delay -53 -> 252, step: 4
5708 09:28:40.374098
5709 09:28:40.375730 Set Vref, RX VrefLevel [Byte0]: 52
5710 09:28:40.379047 [Byte1]: 52
5711 09:28:40.384041
5712 09:28:40.384458 Final RX Vref Byte 0 = 52 to rank0
5713 09:28:40.387547 Final RX Vref Byte 1 = 52 to rank0
5714 09:28:40.390826 Final RX Vref Byte 0 = 52 to rank1
5715 09:28:40.394126 Final RX Vref Byte 1 = 52 to rank1==
5716 09:28:40.397334 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 09:28:40.404101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 09:28:40.404541 ==
5719 09:28:40.404912 DQS Delay:
5720 09:28:40.405227 DQS0 = 0, DQS1 = 0
5721 09:28:40.407368 DQM Delay:
5722 09:28:40.407824 DQM0 = 104, DQM1 = 97
5723 09:28:40.410590 DQ Delay:
5724 09:28:40.414379 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5725 09:28:40.417178 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =100
5726 09:28:40.421011 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =92
5727 09:28:40.424248 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =102
5728 09:28:40.424692
5729 09:28:40.425027
5730 09:28:40.430744 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5731 09:28:40.433931 CH1 RK0: MR19=505, MR18=1D35
5732 09:28:40.441018 CH1_RK0: MR19=0x505, MR18=0x1D35, DQSOSC=405, MR23=63, INC=66, DEC=44
5733 09:28:40.441444
5734 09:28:40.444316 ----->DramcWriteLeveling(PI) begin...
5735 09:28:40.444762 ==
5736 09:28:40.447595 Dram Type= 6, Freq= 0, CH_1, rank 1
5737 09:28:40.450846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 09:28:40.451270 ==
5739 09:28:40.454099 Write leveling (Byte 0): 27 => 27
5740 09:28:40.457247 Write leveling (Byte 1): 29 => 29
5741 09:28:40.460612 DramcWriteLeveling(PI) end<-----
5742 09:28:40.461038
5743 09:28:40.461371 ==
5744 09:28:40.464310 Dram Type= 6, Freq= 0, CH_1, rank 1
5745 09:28:40.467437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 09:28:40.470388 ==
5747 09:28:40.470806 [Gating] SW mode calibration
5748 09:28:40.480729 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5749 09:28:40.483977 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5750 09:28:40.487264 0 14 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5751 09:28:40.494030 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 09:28:40.497271 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 09:28:40.500267 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 09:28:40.506805 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 09:28:40.510198 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5756 09:28:40.513937 0 14 24 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 1)
5757 09:28:40.520343 0 14 28 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (1 0)
5758 09:28:40.523559 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5759 09:28:40.526875 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 09:28:40.533515 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 09:28:40.536900 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 09:28:40.540195 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 09:28:40.546675 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 09:28:40.549903 0 15 24 | B1->B0 | 2f2f 2a2a | 0 0 | (0 0) (0 0)
5765 09:28:40.553040 0 15 28 | B1->B0 | 3e3e 3939 | 0 0 | (0 0) (0 0)
5766 09:28:40.559826 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 09:28:40.563229 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 09:28:40.566963 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 09:28:40.573146 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 09:28:40.576672 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 09:28:40.579918 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 09:28:40.586402 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5773 09:28:40.589730 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 09:28:40.593105 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 09:28:40.599858 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 09:28:40.603172 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 09:28:40.606412 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 09:28:40.612861 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 09:28:40.616099 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 09:28:40.619356 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 09:28:40.626957 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 09:28:40.629283 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 09:28:40.633043 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 09:28:40.639803 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 09:28:40.643078 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 09:28:40.646143 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 09:28:40.652611 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 09:28:40.655808 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5789 09:28:40.659651 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5790 09:28:40.663015 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 09:28:40.666129 Total UI for P1: 0, mck2ui 16
5792 09:28:40.669305 best dqsien dly found for B0: ( 1, 2, 26)
5793 09:28:40.672853 Total UI for P1: 0, mck2ui 16
5794 09:28:40.675990 best dqsien dly found for B1: ( 1, 2, 26)
5795 09:28:40.679270 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5796 09:28:40.682874 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5797 09:28:40.686194
5798 09:28:40.689380 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5799 09:28:40.692729 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5800 09:28:40.696022 [Gating] SW calibration Done
5801 09:28:40.696495 ==
5802 09:28:40.699360 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 09:28:40.702658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 09:28:40.703083 ==
5805 09:28:40.703418 RX Vref Scan: 0
5806 09:28:40.706218
5807 09:28:40.706635 RX Vref 0 -> 0, step: 1
5808 09:28:40.707048
5809 09:28:40.709422 RX Delay -80 -> 252, step: 8
5810 09:28:40.712826 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5811 09:28:40.716130 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5812 09:28:40.722669 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5813 09:28:40.725862 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5814 09:28:40.729457 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5815 09:28:40.732853 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5816 09:28:40.736022 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5817 09:28:40.739131 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5818 09:28:40.745813 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5819 09:28:40.749139 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5820 09:28:40.752358 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5821 09:28:40.755601 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5822 09:28:40.758844 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5823 09:28:40.762286 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5824 09:28:40.769246 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5825 09:28:40.772656 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5826 09:28:40.773147 ==
5827 09:28:40.775729 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 09:28:40.779318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 09:28:40.779742 ==
5830 09:28:40.782394 DQS Delay:
5831 09:28:40.782813 DQS0 = 0, DQS1 = 0
5832 09:28:40.783149 DQM Delay:
5833 09:28:40.785889 DQM0 = 101, DQM1 = 96
5834 09:28:40.786306 DQ Delay:
5835 09:28:40.788920 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5836 09:28:40.792260 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5837 09:28:40.795591 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =87
5838 09:28:40.798949 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5839 09:28:40.799459
5840 09:28:40.799793
5841 09:28:40.802077 ==
5842 09:28:40.805396 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 09:28:40.808701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 09:28:40.809123 ==
5845 09:28:40.809458
5846 09:28:40.809768
5847 09:28:40.812513 TX Vref Scan disable
5848 09:28:40.812979 == TX Byte 0 ==
5849 09:28:40.815781 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5850 09:28:40.822285 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5851 09:28:40.822725 == TX Byte 1 ==
5852 09:28:40.825640 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5853 09:28:40.832080 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5854 09:28:40.832608 ==
5855 09:28:40.835532 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 09:28:40.838687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 09:28:40.839109 ==
5858 09:28:40.839442
5859 09:28:40.839765
5860 09:28:40.841932 TX Vref Scan disable
5861 09:28:40.845134 == TX Byte 0 ==
5862 09:28:40.848409 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5863 09:28:40.851736 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5864 09:28:40.855490 == TX Byte 1 ==
5865 09:28:40.858782 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5866 09:28:40.862117 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5867 09:28:40.862547
5868 09:28:40.865228 [DATLAT]
5869 09:28:40.865729 Freq=933, CH1 RK1
5870 09:28:40.866070
5871 09:28:40.868471 DATLAT Default: 0xb
5872 09:28:40.868917 0, 0xFFFF, sum = 0
5873 09:28:40.871935 1, 0xFFFF, sum = 0
5874 09:28:40.872442 2, 0xFFFF, sum = 0
5875 09:28:40.875349 3, 0xFFFF, sum = 0
5876 09:28:40.875839 4, 0xFFFF, sum = 0
5877 09:28:40.878372 5, 0xFFFF, sum = 0
5878 09:28:40.878806 6, 0xFFFF, sum = 0
5879 09:28:40.882140 7, 0xFFFF, sum = 0
5880 09:28:40.882571 8, 0xFFFF, sum = 0
5881 09:28:40.885424 9, 0xFFFF, sum = 0
5882 09:28:40.885904 10, 0x0, sum = 1
5883 09:28:40.888499 11, 0x0, sum = 2
5884 09:28:40.888968 12, 0x0, sum = 3
5885 09:28:40.891617 13, 0x0, sum = 4
5886 09:28:40.892057 best_step = 11
5887 09:28:40.892401
5888 09:28:40.892768 ==
5889 09:28:40.895472 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 09:28:40.898797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 09:28:40.901922 ==
5892 09:28:40.902349 RX Vref Scan: 0
5893 09:28:40.902690
5894 09:28:40.905087 RX Vref 0 -> 0, step: 1
5895 09:28:40.905513
5896 09:28:40.908244 RX Delay -53 -> 252, step: 4
5897 09:28:40.911507 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5898 09:28:40.914762 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5899 09:28:40.921789 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5900 09:28:40.924986 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5901 09:28:40.928301 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5902 09:28:40.931532 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5903 09:28:40.934770 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5904 09:28:40.938421 iDelay=199, Bit 7, Center 100 (19 ~ 182) 164
5905 09:28:40.944980 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5906 09:28:40.948219 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5907 09:28:40.951762 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5908 09:28:40.954718 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5909 09:28:40.958024 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5910 09:28:40.965082 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5911 09:28:40.968283 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5912 09:28:40.971602 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5913 09:28:40.972030 ==
5914 09:28:40.974861 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 09:28:40.978190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 09:28:40.978623 ==
5917 09:28:40.981179 DQS Delay:
5918 09:28:40.981604 DQS0 = 0, DQS1 = 0
5919 09:28:40.984767 DQM Delay:
5920 09:28:40.985195 DQM0 = 104, DQM1 = 97
5921 09:28:40.987845 DQ Delay:
5922 09:28:40.988306 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5923 09:28:40.994616 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =100
5924 09:28:40.998155 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =92
5925 09:28:41.001305 DQ12 =108, DQ13 =102, DQ14 =104, DQ15 =106
5926 09:28:41.001732
5927 09:28:41.002068
5928 09:28:41.008328 [DQSOSCAuto] RK1, (LSB)MR18= 0x2401, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5929 09:28:41.011693 CH1 RK1: MR19=505, MR18=2401
5930 09:28:41.018116 CH1_RK1: MR19=0x505, MR18=0x2401, DQSOSC=410, MR23=63, INC=64, DEC=42
5931 09:28:41.021344 [RxdqsGatingPostProcess] freq 933
5932 09:28:41.024699 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5933 09:28:41.027915 best DQS0 dly(2T, 0.5T) = (0, 10)
5934 09:28:41.031281 best DQS1 dly(2T, 0.5T) = (0, 10)
5935 09:28:41.034382 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5936 09:28:41.038161 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5937 09:28:41.041515 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 09:28:41.045088 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 09:28:41.048234 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 09:28:41.051329 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 09:28:41.054910 Pre-setting of DQS Precalculation
5942 09:28:41.058031 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5943 09:28:41.067866 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5944 09:28:41.075137 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5945 09:28:41.075670
5946 09:28:41.076005
5947 09:28:41.078397 [Calibration Summary] 1866 Mbps
5948 09:28:41.078929 CH 0, Rank 0
5949 09:28:41.081550 SW Impedance : PASS
5950 09:28:41.082075 DUTY Scan : NO K
5951 09:28:41.084659 ZQ Calibration : PASS
5952 09:28:41.088043 Jitter Meter : NO K
5953 09:28:41.088596 CBT Training : PASS
5954 09:28:41.091077 Write leveling : PASS
5955 09:28:41.094800 RX DQS gating : PASS
5956 09:28:41.095220 RX DQ/DQS(RDDQC) : PASS
5957 09:28:41.097722 TX DQ/DQS : PASS
5958 09:28:41.098143 RX DATLAT : PASS
5959 09:28:41.100980 RX DQ/DQS(Engine): PASS
5960 09:28:41.104663 TX OE : NO K
5961 09:28:41.105087 All Pass.
5962 09:28:41.105422
5963 09:28:41.105734 CH 0, Rank 1
5964 09:28:41.107622 SW Impedance : PASS
5965 09:28:41.111433 DUTY Scan : NO K
5966 09:28:41.112100 ZQ Calibration : PASS
5967 09:28:41.114512 Jitter Meter : NO K
5968 09:28:41.117950 CBT Training : PASS
5969 09:28:41.118434 Write leveling : PASS
5970 09:28:41.121216 RX DQS gating : PASS
5971 09:28:41.124623 RX DQ/DQS(RDDQC) : PASS
5972 09:28:41.125042 TX DQ/DQS : PASS
5973 09:28:41.127892 RX DATLAT : PASS
5974 09:28:41.131563 RX DQ/DQS(Engine): PASS
5975 09:28:41.132096 TX OE : NO K
5976 09:28:41.134813 All Pass.
5977 09:28:41.135346
5978 09:28:41.135684 CH 1, Rank 0
5979 09:28:41.137715 SW Impedance : PASS
5980 09:28:41.138136 DUTY Scan : NO K
5981 09:28:41.141630 ZQ Calibration : PASS
5982 09:28:41.142050 Jitter Meter : NO K
5983 09:28:41.144836 CBT Training : PASS
5984 09:28:41.148043 Write leveling : PASS
5985 09:28:41.148540 RX DQS gating : PASS
5986 09:28:41.151065 RX DQ/DQS(RDDQC) : PASS
5987 09:28:41.154613 TX DQ/DQS : PASS
5988 09:28:41.155226 RX DATLAT : PASS
5989 09:28:41.157890 RX DQ/DQS(Engine): PASS
5990 09:28:41.161471 TX OE : NO K
5991 09:28:41.161998 All Pass.
5992 09:28:41.162343
5993 09:28:41.162653 CH 1, Rank 1
5994 09:28:41.164252 SW Impedance : PASS
5995 09:28:41.167858 DUTY Scan : NO K
5996 09:28:41.168384 ZQ Calibration : PASS
5997 09:28:41.171233 Jitter Meter : NO K
5998 09:28:41.174634 CBT Training : PASS
5999 09:28:41.175161 Write leveling : PASS
6000 09:28:41.177916 RX DQS gating : PASS
6001 09:28:41.181089 RX DQ/DQS(RDDQC) : PASS
6002 09:28:41.181513 TX DQ/DQS : PASS
6003 09:28:41.184628 RX DATLAT : PASS
6004 09:28:41.187609 RX DQ/DQS(Engine): PASS
6005 09:28:41.188039 TX OE : NO K
6006 09:28:41.188389 All Pass.
6007 09:28:41.190752
6008 09:28:41.191166 DramC Write-DBI off
6009 09:28:41.194116 PER_BANK_REFRESH: Hybrid Mode
6010 09:28:41.194549 TX_TRACKING: ON
6011 09:28:41.204180 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6012 09:28:41.207685 [FAST_K] Save calibration result to emmc
6013 09:28:41.210549 dramc_set_vcore_voltage set vcore to 650000
6014 09:28:41.214109 Read voltage for 400, 6
6015 09:28:41.214727 Vio18 = 0
6016 09:28:41.217314 Vcore = 650000
6017 09:28:41.217731 Vdram = 0
6018 09:28:41.218060 Vddq = 0
6019 09:28:41.218371 Vmddr = 0
6020 09:28:41.224046 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6021 09:28:41.230711 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6022 09:28:41.231165 MEM_TYPE=3, freq_sel=20
6023 09:28:41.234190 sv_algorithm_assistance_LP4_800
6024 09:28:41.237267 ============ PULL DRAM RESETB DOWN ============
6025 09:28:41.244003 ========== PULL DRAM RESETB DOWN end =========
6026 09:28:41.247214 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6027 09:28:41.250790 ===================================
6028 09:28:41.253966 LPDDR4 DRAM CONFIGURATION
6029 09:28:41.257417 ===================================
6030 09:28:41.257951 EX_ROW_EN[0] = 0x0
6031 09:28:41.260821 EX_ROW_EN[1] = 0x0
6032 09:28:41.263560 LP4Y_EN = 0x0
6033 09:28:41.264095 WORK_FSP = 0x0
6034 09:28:41.267340 WL = 0x2
6035 09:28:41.268032 RL = 0x2
6036 09:28:41.270314 BL = 0x2
6037 09:28:41.270734 RPST = 0x0
6038 09:28:41.273779 RD_PRE = 0x0
6039 09:28:41.274201 WR_PRE = 0x1
6040 09:28:41.277238 WR_PST = 0x0
6041 09:28:41.277764 DBI_WR = 0x0
6042 09:28:41.280506 DBI_RD = 0x0
6043 09:28:41.280971 OTF = 0x1
6044 09:28:41.283862 ===================================
6045 09:28:41.287342 ===================================
6046 09:28:41.290468 ANA top config
6047 09:28:41.293766 ===================================
6048 09:28:41.294269 DLL_ASYNC_EN = 0
6049 09:28:41.297044 ALL_SLAVE_EN = 1
6050 09:28:41.300247 NEW_RANK_MODE = 1
6051 09:28:41.303799 DLL_IDLE_MODE = 1
6052 09:28:41.304218 LP45_APHY_COMB_EN = 1
6053 09:28:41.306949 TX_ODT_DIS = 1
6054 09:28:41.310667 NEW_8X_MODE = 1
6055 09:28:41.313715 ===================================
6056 09:28:41.316764 ===================================
6057 09:28:41.320534 data_rate = 800
6058 09:28:41.323802 CKR = 1
6059 09:28:41.324331 DQ_P2S_RATIO = 4
6060 09:28:41.326800 ===================================
6061 09:28:41.330298 CA_P2S_RATIO = 4
6062 09:28:41.333489 DQ_CA_OPEN = 0
6063 09:28:41.337349 DQ_SEMI_OPEN = 1
6064 09:28:41.340676 CA_SEMI_OPEN = 1
6065 09:28:41.343953 CA_FULL_RATE = 0
6066 09:28:41.344470 DQ_CKDIV4_EN = 0
6067 09:28:41.347195 CA_CKDIV4_EN = 1
6068 09:28:41.350378 CA_PREDIV_EN = 0
6069 09:28:41.353783 PH8_DLY = 0
6070 09:28:41.356886 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6071 09:28:41.360535 DQ_AAMCK_DIV = 0
6072 09:28:41.361089 CA_AAMCK_DIV = 0
6073 09:28:41.363590 CA_ADMCK_DIV = 4
6074 09:28:41.366836 DQ_TRACK_CA_EN = 0
6075 09:28:41.369927 CA_PICK = 800
6076 09:28:41.373882 CA_MCKIO = 400
6077 09:28:41.377180 MCKIO_SEMI = 400
6078 09:28:41.380509 PLL_FREQ = 3016
6079 09:28:41.381060 DQ_UI_PI_RATIO = 32
6080 09:28:41.383793 CA_UI_PI_RATIO = 32
6081 09:28:41.387069 ===================================
6082 09:28:41.390326 ===================================
6083 09:28:41.393498 memory_type:LPDDR4
6084 09:28:41.396765 GP_NUM : 10
6085 09:28:41.397169 SRAM_EN : 1
6086 09:28:41.400638 MD32_EN : 0
6087 09:28:41.403852 ===================================
6088 09:28:41.406849 [ANA_INIT] >>>>>>>>>>>>>>
6089 09:28:41.407452 <<<<<< [CONFIGURE PHASE]: ANA_TX
6090 09:28:41.410152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6091 09:28:41.413633 ===================================
6092 09:28:41.416692 data_rate = 800,PCW = 0X7400
6093 09:28:41.420442 ===================================
6094 09:28:41.423643 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6095 09:28:41.430366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 09:28:41.440157 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6097 09:28:41.446750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6098 09:28:41.450032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6099 09:28:41.453260 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6100 09:28:41.453682 [ANA_INIT] flow start
6101 09:28:41.456615 [ANA_INIT] PLL >>>>>>>>
6102 09:28:41.459911 [ANA_INIT] PLL <<<<<<<<
6103 09:28:41.463198 [ANA_INIT] MIDPI >>>>>>>>
6104 09:28:41.463645 [ANA_INIT] MIDPI <<<<<<<<
6105 09:28:41.466589 [ANA_INIT] DLL >>>>>>>>
6106 09:28:41.469741 [ANA_INIT] flow end
6107 09:28:41.473518 ============ LP4 DIFF to SE enter ============
6108 09:28:41.476830 ============ LP4 DIFF to SE exit ============
6109 09:28:41.479939 [ANA_INIT] <<<<<<<<<<<<<
6110 09:28:41.483112 [Flow] Enable top DCM control >>>>>
6111 09:28:41.486369 [Flow] Enable top DCM control <<<<<
6112 09:28:41.490195 Enable DLL master slave shuffle
6113 09:28:41.493372 ==============================================================
6114 09:28:41.496709 Gating Mode config
6115 09:28:41.500003 ==============================================================
6116 09:28:41.503114 Config description:
6117 09:28:41.513352 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6118 09:28:41.519748 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6119 09:28:41.523167 SELPH_MODE 0: By rank 1: By Phase
6120 09:28:41.529556 ==============================================================
6121 09:28:41.533322 GAT_TRACK_EN = 0
6122 09:28:41.536730 RX_GATING_MODE = 2
6123 09:28:41.539927 RX_GATING_TRACK_MODE = 2
6124 09:28:41.543000 SELPH_MODE = 1
6125 09:28:41.546254 PICG_EARLY_EN = 1
6126 09:28:41.546658 VALID_LAT_VALUE = 1
6127 09:28:41.552894 ==============================================================
6128 09:28:41.556204 Enter into Gating configuration >>>>
6129 09:28:41.559481 Exit from Gating configuration <<<<
6130 09:28:41.563376 Enter into DVFS_PRE_config >>>>>
6131 09:28:41.573259 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6132 09:28:41.576457 Exit from DVFS_PRE_config <<<<<
6133 09:28:41.579736 Enter into PICG configuration >>>>
6134 09:28:41.583322 Exit from PICG configuration <<<<
6135 09:28:41.586339 [RX_INPUT] configuration >>>>>
6136 09:28:41.589761 [RX_INPUT] configuration <<<<<
6137 09:28:41.593093 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6138 09:28:41.599558 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6139 09:28:41.606466 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6140 09:28:41.613234 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6141 09:28:41.619866 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 09:28:41.623136 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 09:28:41.630212 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6144 09:28:41.633010 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6145 09:28:41.636174 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6146 09:28:41.639395 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6147 09:28:41.645925 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6148 09:28:41.649708 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6149 09:28:41.652953 ===================================
6150 09:28:41.656283 LPDDR4 DRAM CONFIGURATION
6151 09:28:41.659537 ===================================
6152 09:28:41.659958 EX_ROW_EN[0] = 0x0
6153 09:28:41.662777 EX_ROW_EN[1] = 0x0
6154 09:28:41.663199 LP4Y_EN = 0x0
6155 09:28:41.666095 WORK_FSP = 0x0
6156 09:28:41.666512 WL = 0x2
6157 09:28:41.669213 RL = 0x2
6158 09:28:41.669630 BL = 0x2
6159 09:28:41.672571 RPST = 0x0
6160 09:28:41.675881 RD_PRE = 0x0
6161 09:28:41.676297 WR_PRE = 0x1
6162 09:28:41.679639 WR_PST = 0x0
6163 09:28:41.680109 DBI_WR = 0x0
6164 09:28:41.682833 DBI_RD = 0x0
6165 09:28:41.683259 OTF = 0x1
6166 09:28:41.686331 ===================================
6167 09:28:41.689306 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6168 09:28:41.695925 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6169 09:28:41.699324 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6170 09:28:41.702896 ===================================
6171 09:28:41.705886 LPDDR4 DRAM CONFIGURATION
6172 09:28:41.708997 ===================================
6173 09:28:41.709421 EX_ROW_EN[0] = 0x10
6174 09:28:41.712294 EX_ROW_EN[1] = 0x0
6175 09:28:41.712754 LP4Y_EN = 0x0
6176 09:28:41.715560 WORK_FSP = 0x0
6177 09:28:41.715987 WL = 0x2
6178 09:28:41.719425 RL = 0x2
6179 09:28:41.719853 BL = 0x2
6180 09:28:41.722518 RPST = 0x0
6181 09:28:41.722947 RD_PRE = 0x0
6182 09:28:41.725754 WR_PRE = 0x1
6183 09:28:41.726238 WR_PST = 0x0
6184 09:28:41.729354 DBI_WR = 0x0
6185 09:28:41.729783 DBI_RD = 0x0
6186 09:28:41.732654 OTF = 0x1
6187 09:28:41.735650 ===================================
6188 09:28:41.742424 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6189 09:28:41.745690 nWR fixed to 30
6190 09:28:41.749435 [ModeRegInit_LP4] CH0 RK0
6191 09:28:41.749889 [ModeRegInit_LP4] CH0 RK1
6192 09:28:41.752447 [ModeRegInit_LP4] CH1 RK0
6193 09:28:41.755851 [ModeRegInit_LP4] CH1 RK1
6194 09:28:41.756279 match AC timing 19
6195 09:28:41.762553 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6196 09:28:41.765498 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6197 09:28:41.769250 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6198 09:28:41.776116 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6199 09:28:41.779309 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6200 09:28:41.779944 ==
6201 09:28:41.782237 Dram Type= 6, Freq= 0, CH_0, rank 0
6202 09:28:41.785886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6203 09:28:41.786318 ==
6204 09:28:41.792754 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6205 09:28:41.799129 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6206 09:28:41.802502 [CA 0] Center 36 (8~64) winsize 57
6207 09:28:41.805767 [CA 1] Center 36 (8~64) winsize 57
6208 09:28:41.808955 [CA 2] Center 36 (8~64) winsize 57
6209 09:28:41.809397 [CA 3] Center 36 (8~64) winsize 57
6210 09:28:41.812530 [CA 4] Center 36 (8~64) winsize 57
6211 09:28:41.815542 [CA 5] Center 36 (8~64) winsize 57
6212 09:28:41.815991
6213 09:28:41.822510 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6214 09:28:41.823068
6215 09:28:41.825638 [CATrainingPosCal] consider 1 rank data
6216 09:28:41.829221 u2DelayCellTimex100 = 270/100 ps
6217 09:28:41.832388 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 09:28:41.835704 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 09:28:41.839212 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 09:28:41.842361 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 09:28:41.845671 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 09:28:41.848676 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 09:28:41.849098
6224 09:28:41.851957 CA PerBit enable=1, Macro0, CA PI delay=36
6225 09:28:41.852482
6226 09:28:41.855493 [CBTSetCACLKResult] CA Dly = 36
6227 09:28:41.858764 CS Dly: 1 (0~32)
6228 09:28:41.859181 ==
6229 09:28:41.862035 Dram Type= 6, Freq= 0, CH_0, rank 1
6230 09:28:41.865319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6231 09:28:41.865743 ==
6232 09:28:41.872469 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6233 09:28:41.876078 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6234 09:28:41.879346 [CA 0] Center 36 (8~64) winsize 57
6235 09:28:41.882394 [CA 1] Center 36 (8~64) winsize 57
6236 09:28:41.885450 [CA 2] Center 36 (8~64) winsize 57
6237 09:28:41.888757 [CA 3] Center 36 (8~64) winsize 57
6238 09:28:41.892036 [CA 4] Center 36 (8~64) winsize 57
6239 09:28:41.895589 [CA 5] Center 36 (8~64) winsize 57
6240 09:28:41.896119
6241 09:28:41.898693 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6242 09:28:41.899113
6243 09:28:41.902088 [CATrainingPosCal] consider 2 rank data
6244 09:28:41.905366 u2DelayCellTimex100 = 270/100 ps
6245 09:28:41.908714 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 09:28:41.912206 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 09:28:41.915351 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 09:28:41.922047 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 09:28:41.925187 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 09:28:41.928618 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 09:28:41.929038
6252 09:28:41.932017 CA PerBit enable=1, Macro0, CA PI delay=36
6253 09:28:41.932605
6254 09:28:41.935370 [CBTSetCACLKResult] CA Dly = 36
6255 09:28:41.935800 CS Dly: 1 (0~32)
6256 09:28:41.936144
6257 09:28:41.938356 ----->DramcWriteLeveling(PI) begin...
6258 09:28:41.938785 ==
6259 09:28:41.941805 Dram Type= 6, Freq= 0, CH_0, rank 0
6260 09:28:41.948654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 09:28:41.949082 ==
6262 09:28:41.951982 Write leveling (Byte 0): 40 => 8
6263 09:28:41.955651 Write leveling (Byte 1): 32 => 0
6264 09:28:41.956181 DramcWriteLeveling(PI) end<-----
6265 09:28:41.956527
6266 09:28:41.958835 ==
6267 09:28:41.961989 Dram Type= 6, Freq= 0, CH_0, rank 0
6268 09:28:41.965428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 09:28:41.965948 ==
6270 09:28:41.968939 [Gating] SW mode calibration
6271 09:28:41.975555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6272 09:28:41.978465 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6273 09:28:41.985221 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 09:28:41.988678 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 09:28:41.991770 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 09:28:41.998695 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 09:28:42.001841 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 09:28:42.005085 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 09:28:42.011563 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 09:28:42.014894 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 09:28:42.018098 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 09:28:42.021405 Total UI for P1: 0, mck2ui 16
6283 09:28:42.024609 best dqsien dly found for B0: ( 0, 14, 24)
6284 09:28:42.028076 Total UI for P1: 0, mck2ui 16
6285 09:28:42.031399 best dqsien dly found for B1: ( 0, 14, 24)
6286 09:28:42.035121 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6287 09:28:42.038589 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6288 09:28:42.039200
6289 09:28:42.045004 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 09:28:42.047935 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6291 09:28:42.048360 [Gating] SW calibration Done
6292 09:28:42.051760 ==
6293 09:28:42.054793 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 09:28:42.058280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 09:28:42.058700 ==
6296 09:28:42.059032 RX Vref Scan: 0
6297 09:28:42.059342
6298 09:28:42.061191 RX Vref 0 -> 0, step: 1
6299 09:28:42.061622
6300 09:28:42.064487 RX Delay -410 -> 252, step: 16
6301 09:28:42.067764 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6302 09:28:42.074783 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6303 09:28:42.078333 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6304 09:28:42.081342 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6305 09:28:42.084781 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6306 09:28:42.088172 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6307 09:28:42.094779 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6308 09:28:42.098028 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6309 09:28:42.101469 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6310 09:28:42.104914 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6311 09:28:42.111054 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6312 09:28:42.114422 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6313 09:28:42.117772 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6314 09:28:42.124367 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6315 09:28:42.127711 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6316 09:28:42.130970 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6317 09:28:42.131381 ==
6318 09:28:42.134483 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 09:28:42.137992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 09:28:42.138409 ==
6321 09:28:42.141363 DQS Delay:
6322 09:28:42.141925 DQS0 = 27, DQS1 = 43
6323 09:28:42.144241 DQM Delay:
6324 09:28:42.144764 DQM0 = 12, DQM1 = 13
6325 09:28:42.147847 DQ Delay:
6326 09:28:42.148255 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6327 09:28:42.151021 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6328 09:28:42.154527 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6329 09:28:42.157652 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6330 09:28:42.158069
6331 09:28:42.158391
6332 09:28:42.158690 ==
6333 09:28:42.161158 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 09:28:42.167711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 09:28:42.168124 ==
6336 09:28:42.168450
6337 09:28:42.168783
6338 09:28:42.169131 TX Vref Scan disable
6339 09:28:42.170754 == TX Byte 0 ==
6340 09:28:42.174171 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 09:28:42.177490 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 09:28:42.180843 == TX Byte 1 ==
6343 09:28:42.184087 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6344 09:28:42.187312 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6345 09:28:42.190970 ==
6346 09:28:42.194211 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 09:28:42.197483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 09:28:42.197898 ==
6349 09:28:42.198258
6350 09:28:42.198741
6351 09:28:42.200777 TX Vref Scan disable
6352 09:28:42.201182 == TX Byte 0 ==
6353 09:28:42.204335 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 09:28:42.210604 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 09:28:42.211075 == TX Byte 1 ==
6356 09:28:42.214631 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6357 09:28:42.220787 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6358 09:28:42.221201
6359 09:28:42.221525 [DATLAT]
6360 09:28:42.221825 Freq=400, CH0 RK0
6361 09:28:42.222116
6362 09:28:42.224051 DATLAT Default: 0xf
6363 09:28:42.224458 0, 0xFFFF, sum = 0
6364 09:28:42.227340 1, 0xFFFF, sum = 0
6365 09:28:42.230972 2, 0xFFFF, sum = 0
6366 09:28:42.231498 3, 0xFFFF, sum = 0
6367 09:28:42.234393 4, 0xFFFF, sum = 0
6368 09:28:42.234923 5, 0xFFFF, sum = 0
6369 09:28:42.237341 6, 0xFFFF, sum = 0
6370 09:28:42.237756 7, 0xFFFF, sum = 0
6371 09:28:42.240725 8, 0xFFFF, sum = 0
6372 09:28:42.241249 9, 0xFFFF, sum = 0
6373 09:28:42.243797 10, 0xFFFF, sum = 0
6374 09:28:42.244212 11, 0xFFFF, sum = 0
6375 09:28:42.247445 12, 0xFFFF, sum = 0
6376 09:28:42.247863 13, 0x0, sum = 1
6377 09:28:42.250514 14, 0x0, sum = 2
6378 09:28:42.250925 15, 0x0, sum = 3
6379 09:28:42.253843 16, 0x0, sum = 4
6380 09:28:42.254256 best_step = 14
6381 09:28:42.254578
6382 09:28:42.254881 ==
6383 09:28:42.257913 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 09:28:42.260614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 09:28:42.263817 ==
6386 09:28:42.264328 RX Vref Scan: 1
6387 09:28:42.264701
6388 09:28:42.267173 RX Vref 0 -> 0, step: 1
6389 09:28:42.267623
6390 09:28:42.270597 RX Delay -327 -> 252, step: 8
6391 09:28:42.271053
6392 09:28:42.274178 Set Vref, RX VrefLevel [Byte0]: 58
6393 09:28:42.276963 [Byte1]: 50
6394 09:28:42.277417
6395 09:28:42.280351 Final RX Vref Byte 0 = 58 to rank0
6396 09:28:42.283781 Final RX Vref Byte 1 = 50 to rank0
6397 09:28:42.287184 Final RX Vref Byte 0 = 58 to rank1
6398 09:28:42.290197 Final RX Vref Byte 1 = 50 to rank1==
6399 09:28:42.293461 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 09:28:42.296673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 09:28:42.297089 ==
6402 09:28:42.300663 DQS Delay:
6403 09:28:42.301117 DQS0 = 28, DQS1 = 48
6404 09:28:42.304165 DQM Delay:
6405 09:28:42.304770 DQM0 = 12, DQM1 = 15
6406 09:28:42.305110 DQ Delay:
6407 09:28:42.307204 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6408 09:28:42.310447 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6409 09:28:42.313766 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6410 09:28:42.316811 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6411 09:28:42.317229
6412 09:28:42.317561
6413 09:28:42.326635 [DQSOSCAuto] RK0, (LSB)MR18= 0xaca4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6414 09:28:42.330007 CH0 RK0: MR19=C0C, MR18=ACA4
6415 09:28:42.333310 CH0_RK0: MR19=0xC0C, MR18=0xACA4, DQSOSC=388, MR23=63, INC=392, DEC=261
6416 09:28:42.336622 ==
6417 09:28:42.337042 Dram Type= 6, Freq= 0, CH_0, rank 1
6418 09:28:42.343737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 09:28:42.344264 ==
6420 09:28:42.347264 [Gating] SW mode calibration
6421 09:28:42.353288 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6422 09:28:42.356826 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6423 09:28:42.363799 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 09:28:42.366865 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 09:28:42.370317 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 09:28:42.376849 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 09:28:42.379992 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 09:28:42.383714 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 09:28:42.390356 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 09:28:42.393061 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 09:28:42.396916 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 09:28:42.400081 Total UI for P1: 0, mck2ui 16
6433 09:28:42.403298 best dqsien dly found for B0: ( 0, 14, 24)
6434 09:28:42.406847 Total UI for P1: 0, mck2ui 16
6435 09:28:42.410002 best dqsien dly found for B1: ( 0, 14, 24)
6436 09:28:42.413455 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6437 09:28:42.416844 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6438 09:28:42.417354
6439 09:28:42.422996 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 09:28:42.426612 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6441 09:28:42.427127 [Gating] SW calibration Done
6442 09:28:42.429502 ==
6443 09:28:42.432887 Dram Type= 6, Freq= 0, CH_0, rank 1
6444 09:28:42.436059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 09:28:42.436665 ==
6446 09:28:42.437161 RX Vref Scan: 0
6447 09:28:42.437484
6448 09:28:42.439277 RX Vref 0 -> 0, step: 1
6449 09:28:42.439688
6450 09:28:42.442585 RX Delay -410 -> 252, step: 16
6451 09:28:42.445857 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6452 09:28:42.452734 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6453 09:28:42.455955 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6454 09:28:42.459203 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6455 09:28:42.462455 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6456 09:28:42.469481 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6457 09:28:42.472719 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6458 09:28:42.476000 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6459 09:28:42.479420 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6460 09:28:42.482900 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6461 09:28:42.489318 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6462 09:28:42.492628 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6463 09:28:42.495649 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6464 09:28:42.502623 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6465 09:28:42.506074 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6466 09:28:42.509116 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6467 09:28:42.509538 ==
6468 09:28:42.512717 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 09:28:42.516068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 09:28:42.519269 ==
6471 09:28:42.519929 DQS Delay:
6472 09:28:42.520327 DQS0 = 27, DQS1 = 43
6473 09:28:42.522300 DQM Delay:
6474 09:28:42.522719 DQM0 = 9, DQM1 = 15
6475 09:28:42.525906 DQ Delay:
6476 09:28:42.526325 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6477 09:28:42.529095 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6478 09:28:42.532689 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6479 09:28:42.535652 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6480 09:28:42.536071
6481 09:28:42.536403
6482 09:28:42.536758 ==
6483 09:28:42.538987 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 09:28:42.545725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 09:28:42.546258 ==
6486 09:28:42.546601
6487 09:28:42.546909
6488 09:28:42.548943 TX Vref Scan disable
6489 09:28:42.549466 == TX Byte 0 ==
6490 09:28:42.552200 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6491 09:28:42.555416 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6492 09:28:42.559076 == TX Byte 1 ==
6493 09:28:42.562487 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6494 09:28:42.565365 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6495 09:28:42.568938 ==
6496 09:28:42.569490 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 09:28:42.575519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 09:28:42.576046 ==
6499 09:28:42.576505
6500 09:28:42.576997
6501 09:28:42.578714 TX Vref Scan disable
6502 09:28:42.579221 == TX Byte 0 ==
6503 09:28:42.582082 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6504 09:28:42.585216 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6505 09:28:42.588384 == TX Byte 1 ==
6506 09:28:42.592238 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6507 09:28:42.595394 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6508 09:28:42.595694
6509 09:28:42.598536 [DATLAT]
6510 09:28:42.598831 Freq=400, CH0 RK1
6511 09:28:42.599068
6512 09:28:42.601986 DATLAT Default: 0xe
6513 09:28:42.602282 0, 0xFFFF, sum = 0
6514 09:28:42.605453 1, 0xFFFF, sum = 0
6515 09:28:42.605758 2, 0xFFFF, sum = 0
6516 09:28:42.608987 3, 0xFFFF, sum = 0
6517 09:28:42.609303 4, 0xFFFF, sum = 0
6518 09:28:42.611991 5, 0xFFFF, sum = 0
6519 09:28:42.612291 6, 0xFFFF, sum = 0
6520 09:28:42.615424 7, 0xFFFF, sum = 0
6521 09:28:42.615748 8, 0xFFFF, sum = 0
6522 09:28:42.618562 9, 0xFFFF, sum = 0
6523 09:28:42.618937 10, 0xFFFF, sum = 0
6524 09:28:42.621811 11, 0xFFFF, sum = 0
6525 09:28:42.625184 12, 0xFFFF, sum = 0
6526 09:28:42.625485 13, 0x0, sum = 1
6527 09:28:42.628473 14, 0x0, sum = 2
6528 09:28:42.628804 15, 0x0, sum = 3
6529 09:28:42.629050 16, 0x0, sum = 4
6530 09:28:42.632161 best_step = 14
6531 09:28:42.632455
6532 09:28:42.632727 ==
6533 09:28:42.635664 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 09:28:42.638820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 09:28:42.639120 ==
6536 09:28:42.642107 RX Vref Scan: 0
6537 09:28:42.642406
6538 09:28:42.642642 RX Vref 0 -> 0, step: 1
6539 09:28:42.645575
6540 09:28:42.645976 RX Delay -327 -> 252, step: 8
6541 09:28:42.653698 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6542 09:28:42.657023 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6543 09:28:42.660290 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6544 09:28:42.664066 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6545 09:28:42.670502 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6546 09:28:42.673847 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6547 09:28:42.677129 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6548 09:28:42.680584 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6549 09:28:42.687123 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6550 09:28:42.690566 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6551 09:28:42.694240 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6552 09:28:42.697466 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6553 09:28:42.703896 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6554 09:28:42.706910 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6555 09:28:42.710564 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6556 09:28:42.717340 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6557 09:28:42.717851 ==
6558 09:28:42.720347 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 09:28:42.723894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 09:28:42.724378 ==
6561 09:28:42.724855 DQS Delay:
6562 09:28:42.727211 DQS0 = 28, DQS1 = 40
6563 09:28:42.727694 DQM Delay:
6564 09:28:42.730407 DQM0 = 9, DQM1 = 12
6565 09:28:42.730841 DQ Delay:
6566 09:28:42.733698 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6567 09:28:42.736844 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6568 09:28:42.740480 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6569 09:28:42.743792 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6570 09:28:42.744222
6571 09:28:42.744591
6572 09:28:42.750569 [DQSOSCAuto] RK1, (LSB)MR18= 0xc074, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6573 09:28:42.753799 CH0 RK1: MR19=C0C, MR18=C074
6574 09:28:42.760389 CH0_RK1: MR19=0xC0C, MR18=0xC074, DQSOSC=386, MR23=63, INC=396, DEC=264
6575 09:28:42.763628 [RxdqsGatingPostProcess] freq 400
6576 09:28:42.766981 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6577 09:28:42.770335 best DQS0 dly(2T, 0.5T) = (0, 10)
6578 09:28:42.773653 best DQS1 dly(2T, 0.5T) = (0, 10)
6579 09:28:42.777076 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6580 09:28:42.780418 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6581 09:28:42.783806 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 09:28:42.787168 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 09:28:42.790301 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 09:28:42.793698 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 09:28:42.797039 Pre-setting of DQS Precalculation
6586 09:28:42.800368 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6587 09:28:42.800871 ==
6588 09:28:42.803752 Dram Type= 6, Freq= 0, CH_1, rank 0
6589 09:28:42.810122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 09:28:42.810558 ==
6591 09:28:42.813840 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6592 09:28:42.820636 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6593 09:28:42.823543 [CA 0] Center 36 (8~64) winsize 57
6594 09:28:42.826933 [CA 1] Center 36 (8~64) winsize 57
6595 09:28:42.830327 [CA 2] Center 36 (8~64) winsize 57
6596 09:28:42.833584 [CA 3] Center 36 (8~64) winsize 57
6597 09:28:42.836918 [CA 4] Center 36 (8~64) winsize 57
6598 09:28:42.840188 [CA 5] Center 36 (8~64) winsize 57
6599 09:28:42.840664
6600 09:28:42.843423 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6601 09:28:42.843852
6602 09:28:42.846951 [CATrainingPosCal] consider 1 rank data
6603 09:28:42.850165 u2DelayCellTimex100 = 270/100 ps
6604 09:28:42.853370 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 09:28:42.857106 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 09:28:42.860160 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 09:28:42.863413 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 09:28:42.866692 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 09:28:42.870331 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 09:28:42.870761
6611 09:28:42.876907 CA PerBit enable=1, Macro0, CA PI delay=36
6612 09:28:42.877339
6613 09:28:42.880638 [CBTSetCACLKResult] CA Dly = 36
6614 09:28:42.881192 CS Dly: 1 (0~32)
6615 09:28:42.881547 ==
6616 09:28:42.883502 Dram Type= 6, Freq= 0, CH_1, rank 1
6617 09:28:42.886850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 09:28:42.887276 ==
6619 09:28:42.893580 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6620 09:28:42.900259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6621 09:28:42.903748 [CA 0] Center 36 (8~64) winsize 57
6622 09:28:42.907147 [CA 1] Center 36 (8~64) winsize 57
6623 09:28:42.910220 [CA 2] Center 36 (8~64) winsize 57
6624 09:28:42.913763 [CA 3] Center 36 (8~64) winsize 57
6625 09:28:42.914320 [CA 4] Center 36 (8~64) winsize 57
6626 09:28:42.916752 [CA 5] Center 36 (8~64) winsize 57
6627 09:28:42.917177
6628 09:28:42.923351 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6629 09:28:42.923829
6630 09:28:42.926488 [CATrainingPosCal] consider 2 rank data
6631 09:28:42.930243 u2DelayCellTimex100 = 270/100 ps
6632 09:28:42.933155 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 09:28:42.936450 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 09:28:42.939890 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 09:28:42.943199 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 09:28:42.947224 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 09:28:42.950222 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 09:28:42.950702
6639 09:28:42.953589 CA PerBit enable=1, Macro0, CA PI delay=36
6640 09:28:42.954027
6641 09:28:42.956765 [CBTSetCACLKResult] CA Dly = 36
6642 09:28:42.960008 CS Dly: 1 (0~32)
6643 09:28:42.960426
6644 09:28:42.963276 ----->DramcWriteLeveling(PI) begin...
6645 09:28:42.963767 ==
6646 09:28:42.966487 Dram Type= 6, Freq= 0, CH_1, rank 0
6647 09:28:42.969794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 09:28:42.970217 ==
6649 09:28:42.973090 Write leveling (Byte 0): 40 => 8
6650 09:28:42.976434 Write leveling (Byte 1): 32 => 0
6651 09:28:42.979757 DramcWriteLeveling(PI) end<-----
6652 09:28:42.980244
6653 09:28:42.980692 ==
6654 09:28:42.983119 Dram Type= 6, Freq= 0, CH_1, rank 0
6655 09:28:42.986843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 09:28:42.987280 ==
6657 09:28:42.990236 [Gating] SW mode calibration
6658 09:28:42.996955 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6659 09:28:43.003215 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6660 09:28:43.006449 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 09:28:43.009845 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6662 09:28:43.016632 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 09:28:43.019856 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 09:28:43.022947 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 09:28:43.029600 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 09:28:43.033075 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 09:28:43.036089 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 09:28:43.042673 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 09:28:43.043245 Total UI for P1: 0, mck2ui 16
6670 09:28:43.049858 best dqsien dly found for B0: ( 0, 14, 24)
6671 09:28:43.050540 Total UI for P1: 0, mck2ui 16
6672 09:28:43.056705 best dqsien dly found for B1: ( 0, 14, 24)
6673 09:28:43.060346 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6674 09:28:43.062823 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6675 09:28:43.063246
6676 09:28:43.066173 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 09:28:43.069505 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6678 09:28:43.072578 [Gating] SW calibration Done
6679 09:28:43.072957 ==
6680 09:28:43.076017 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 09:28:43.079346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 09:28:43.079992 ==
6683 09:28:43.082761 RX Vref Scan: 0
6684 09:28:43.083434
6685 09:28:43.083964 RX Vref 0 -> 0, step: 1
6686 09:28:43.084436
6687 09:28:43.086324 RX Delay -410 -> 252, step: 16
6688 09:28:43.093096 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6689 09:28:43.096243 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6690 09:28:43.099406 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6691 09:28:43.102793 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6692 09:28:43.109920 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6693 09:28:43.113150 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6694 09:28:43.116440 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6695 09:28:43.119685 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6696 09:28:43.126437 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6697 09:28:43.129208 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6698 09:28:43.132953 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6699 09:28:43.136164 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6700 09:28:43.142901 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6701 09:28:43.146080 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6702 09:28:43.149139 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6703 09:28:43.152735 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6704 09:28:43.155886 ==
6705 09:28:43.159352 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 09:28:43.162776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 09:28:43.163225 ==
6708 09:28:43.163569 DQS Delay:
6709 09:28:43.166262 DQS0 = 27, DQS1 = 43
6710 09:28:43.166787 DQM Delay:
6711 09:28:43.169221 DQM0 = 8, DQM1 = 17
6712 09:28:43.169667 DQ Delay:
6713 09:28:43.173097 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6714 09:28:43.176411 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6715 09:28:43.176933 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6716 09:28:43.180108 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6717 09:28:43.183432
6718 09:28:43.183955
6719 09:28:43.184301 ==
6720 09:28:43.186246 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 09:28:43.189534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 09:28:43.189973 ==
6723 09:28:43.190385
6724 09:28:43.190743
6725 09:28:43.192809 TX Vref Scan disable
6726 09:28:43.193249 == TX Byte 0 ==
6727 09:28:43.196116 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 09:28:43.203060 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 09:28:43.203665 == TX Byte 1 ==
6730 09:28:43.206080 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6731 09:28:43.212728 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6732 09:28:43.213318 ==
6733 09:28:43.216039 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 09:28:43.219566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 09:28:43.220125 ==
6736 09:28:43.220473
6737 09:28:43.220828
6738 09:28:43.222630 TX Vref Scan disable
6739 09:28:43.223086 == TX Byte 0 ==
6740 09:28:43.229115 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 09:28:43.232599 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 09:28:43.233180 == TX Byte 1 ==
6743 09:28:43.239027 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6744 09:28:43.242239 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6745 09:28:43.242682
6746 09:28:43.243122 [DATLAT]
6747 09:28:43.245796 Freq=400, CH1 RK0
6748 09:28:43.246237
6749 09:28:43.246672 DATLAT Default: 0xf
6750 09:28:43.249198 0, 0xFFFF, sum = 0
6751 09:28:43.249643 1, 0xFFFF, sum = 0
6752 09:28:43.252314 2, 0xFFFF, sum = 0
6753 09:28:43.252795 3, 0xFFFF, sum = 0
6754 09:28:43.255946 4, 0xFFFF, sum = 0
6755 09:28:43.256392 5, 0xFFFF, sum = 0
6756 09:28:43.258977 6, 0xFFFF, sum = 0
6757 09:28:43.259423 7, 0xFFFF, sum = 0
6758 09:28:43.262369 8, 0xFFFF, sum = 0
6759 09:28:43.262811 9, 0xFFFF, sum = 0
6760 09:28:43.265601 10, 0xFFFF, sum = 0
6761 09:28:43.268991 11, 0xFFFF, sum = 0
6762 09:28:43.269440 12, 0xFFFF, sum = 0
6763 09:28:43.272174 13, 0x0, sum = 1
6764 09:28:43.272633 14, 0x0, sum = 2
6765 09:28:43.272989 15, 0x0, sum = 3
6766 09:28:43.276073 16, 0x0, sum = 4
6767 09:28:43.276669 best_step = 14
6768 09:28:43.277062
6769 09:28:43.279276 ==
6770 09:28:43.279699 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 09:28:43.285764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 09:28:43.286194 ==
6773 09:28:43.286617 RX Vref Scan: 1
6774 09:28:43.286951
6775 09:28:43.289088 RX Vref 0 -> 0, step: 1
6776 09:28:43.289510
6777 09:28:43.292267 RX Delay -327 -> 252, step: 8
6778 09:28:43.292725
6779 09:28:43.295439 Set Vref, RX VrefLevel [Byte0]: 52
6780 09:28:43.298744 [Byte1]: 52
6781 09:28:43.302468
6782 09:28:43.302902 Final RX Vref Byte 0 = 52 to rank0
6783 09:28:43.305279 Final RX Vref Byte 1 = 52 to rank0
6784 09:28:43.308637 Final RX Vref Byte 0 = 52 to rank1
6785 09:28:43.312252 Final RX Vref Byte 1 = 52 to rank1==
6786 09:28:43.315583 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 09:28:43.322051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 09:28:43.322477 ==
6789 09:28:43.322815 DQS Delay:
6790 09:28:43.325399 DQS0 = 32, DQS1 = 40
6791 09:28:43.325822 DQM Delay:
6792 09:28:43.326159 DQM0 = 12, DQM1 = 12
6793 09:28:43.328652 DQ Delay:
6794 09:28:43.332354 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6795 09:28:43.332814 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6796 09:28:43.335623 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6797 09:28:43.338707 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6798 09:28:43.339135
6799 09:28:43.339476
6800 09:28:43.348840 [DQSOSCAuto] RK0, (LSB)MR18= 0x9ad4, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6801 09:28:43.352352 CH1 RK0: MR19=C0C, MR18=9AD4
6802 09:28:43.358829 CH1_RK0: MR19=0xC0C, MR18=0x9AD4, DQSOSC=383, MR23=63, INC=402, DEC=268
6803 09:28:43.359262 ==
6804 09:28:43.362081 Dram Type= 6, Freq= 0, CH_1, rank 1
6805 09:28:43.365265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 09:28:43.365698 ==
6807 09:28:43.368522 [Gating] SW mode calibration
6808 09:28:43.375586 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6809 09:28:43.378532 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6810 09:28:43.385445 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 09:28:43.388610 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6812 09:28:43.391894 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 09:28:43.398224 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 09:28:43.401663 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 09:28:43.404868 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 09:28:43.412270 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 09:28:43.415624 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 09:28:43.418858 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 09:28:43.422036 Total UI for P1: 0, mck2ui 16
6820 09:28:43.425203 best dqsien dly found for B0: ( 0, 14, 24)
6821 09:28:43.428625 Total UI for P1: 0, mck2ui 16
6822 09:28:43.431770 best dqsien dly found for B1: ( 0, 14, 24)
6823 09:28:43.435478 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6824 09:28:43.438789 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6825 09:28:43.439217
6826 09:28:43.445243 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 09:28:43.448373 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6828 09:28:43.451982 [Gating] SW calibration Done
6829 09:28:43.452430 ==
6830 09:28:43.455020 Dram Type= 6, Freq= 0, CH_1, rank 1
6831 09:28:43.458600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 09:28:43.459031 ==
6833 09:28:43.459370 RX Vref Scan: 0
6834 09:28:43.459691
6835 09:28:43.461676 RX Vref 0 -> 0, step: 1
6836 09:28:43.462106
6837 09:28:43.465031 RX Delay -410 -> 252, step: 16
6838 09:28:43.468265 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6839 09:28:43.475304 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6840 09:28:43.478509 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6841 09:28:43.481560 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6842 09:28:43.484958 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6843 09:28:43.491519 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6844 09:28:43.494818 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6845 09:28:43.498226 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6846 09:28:43.501601 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6847 09:28:43.504778 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6848 09:28:43.511917 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6849 09:28:43.515160 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6850 09:28:43.518315 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6851 09:28:43.524899 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6852 09:28:43.528072 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6853 09:28:43.531464 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6854 09:28:43.531770 ==
6855 09:28:43.534690 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 09:28:43.538360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 09:28:43.541609 ==
6858 09:28:43.541912 DQS Delay:
6859 09:28:43.542153 DQS0 = 35, DQS1 = 43
6860 09:28:43.544818 DQM Delay:
6861 09:28:43.545123 DQM0 = 16, DQM1 = 19
6862 09:28:43.547960 DQ Delay:
6863 09:28:43.548264 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6864 09:28:43.551303 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6865 09:28:43.554670 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6866 09:28:43.558274 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6867 09:28:43.558707
6868 09:28:43.561132
6869 09:28:43.561560 ==
6870 09:28:43.564805 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 09:28:43.567842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 09:28:43.568274 ==
6873 09:28:43.568656
6874 09:28:43.568981
6875 09:28:43.571550 TX Vref Scan disable
6876 09:28:43.571977 == TX Byte 0 ==
6877 09:28:43.574711 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6878 09:28:43.581195 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6879 09:28:43.581626 == TX Byte 1 ==
6880 09:28:43.584725 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6881 09:28:43.591162 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6882 09:28:43.591592 ==
6883 09:28:43.594434 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 09:28:43.597688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 09:28:43.598120 ==
6886 09:28:43.598479
6887 09:28:43.598797
6888 09:28:43.601439 TX Vref Scan disable
6889 09:28:43.601870 == TX Byte 0 ==
6890 09:28:43.604675 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6891 09:28:43.611375 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6892 09:28:43.611806 == TX Byte 1 ==
6893 09:28:43.614681 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6894 09:28:43.621104 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6895 09:28:43.621575
6896 09:28:43.621923 [DATLAT]
6897 09:28:43.622241 Freq=400, CH1 RK1
6898 09:28:43.622613
6899 09:28:43.624379 DATLAT Default: 0xe
6900 09:28:43.624959 0, 0xFFFF, sum = 0
6901 09:28:43.627648 1, 0xFFFF, sum = 0
6902 09:28:43.631514 2, 0xFFFF, sum = 0
6903 09:28:43.631946 3, 0xFFFF, sum = 0
6904 09:28:43.634720 4, 0xFFFF, sum = 0
6905 09:28:43.635196 5, 0xFFFF, sum = 0
6906 09:28:43.637865 6, 0xFFFF, sum = 0
6907 09:28:43.638299 7, 0xFFFF, sum = 0
6908 09:28:43.640998 8, 0xFFFF, sum = 0
6909 09:28:43.641435 9, 0xFFFF, sum = 0
6910 09:28:43.644365 10, 0xFFFF, sum = 0
6911 09:28:43.644841 11, 0xFFFF, sum = 0
6912 09:28:43.647724 12, 0xFFFF, sum = 0
6913 09:28:43.648157 13, 0x0, sum = 1
6914 09:28:43.650862 14, 0x0, sum = 2
6915 09:28:43.651170 15, 0x0, sum = 3
6916 09:28:43.654089 16, 0x0, sum = 4
6917 09:28:43.654397 best_step = 14
6918 09:28:43.654638
6919 09:28:43.654863 ==
6920 09:28:43.657919 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 09:28:43.661192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 09:28:43.664191 ==
6923 09:28:43.664495 RX Vref Scan: 0
6924 09:28:43.664775
6925 09:28:43.667611 RX Vref 0 -> 0, step: 1
6926 09:28:43.667976
6927 09:28:43.670758 RX Delay -327 -> 252, step: 8
6928 09:28:43.674293 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6929 09:28:43.680887 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6930 09:28:43.683943 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6931 09:28:43.687199 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6932 09:28:43.690602 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6933 09:28:43.697085 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6934 09:28:43.700411 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6935 09:28:43.704189 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6936 09:28:43.707651 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6937 09:28:43.714165 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6938 09:28:43.717449 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6939 09:28:43.720566 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6940 09:28:43.723929 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6941 09:28:43.730530 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6942 09:28:43.734007 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6943 09:28:43.737290 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6944 09:28:43.737399 ==
6945 09:28:43.740702 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 09:28:43.747039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 09:28:43.747130 ==
6948 09:28:43.747201 DQS Delay:
6949 09:28:43.750763 DQS0 = 32, DQS1 = 36
6950 09:28:43.750860 DQM Delay:
6951 09:28:43.750937 DQM0 = 13, DQM1 = 11
6952 09:28:43.753929 DQ Delay:
6953 09:28:43.757261 DQ0 =20, DQ1 =12, DQ2 =0, DQ3 =12
6954 09:28:43.760660 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
6955 09:28:43.760785 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6956 09:28:43.763929 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =24
6957 09:28:43.764042
6958 09:28:43.767172
6959 09:28:43.774052 [DQSOSCAuto] RK1, (LSB)MR18= 0xab54, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6960 09:28:43.777309 CH1 RK1: MR19=C0C, MR18=AB54
6961 09:28:43.783957 CH1_RK1: MR19=0xC0C, MR18=0xAB54, DQSOSC=388, MR23=63, INC=392, DEC=261
6962 09:28:43.787415 [RxdqsGatingPostProcess] freq 400
6963 09:28:43.790867 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6964 09:28:43.793773 best DQS0 dly(2T, 0.5T) = (0, 10)
6965 09:28:43.797264 best DQS1 dly(2T, 0.5T) = (0, 10)
6966 09:28:43.800570 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6967 09:28:43.803838 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6968 09:28:43.807101 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 09:28:43.810414 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 09:28:43.813525 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 09:28:43.816754 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 09:28:43.820107 Pre-setting of DQS Precalculation
6973 09:28:43.823880 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6974 09:28:43.830240 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6975 09:28:43.840677 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6976 09:28:43.841253
6977 09:28:43.841621
6978 09:28:43.843719 [Calibration Summary] 800 Mbps
6979 09:28:43.844146 CH 0, Rank 0
6980 09:28:43.846842 SW Impedance : PASS
6981 09:28:43.847268 DUTY Scan : NO K
6982 09:28:43.850219 ZQ Calibration : PASS
6983 09:28:43.853690 Jitter Meter : NO K
6984 09:28:43.854119 CBT Training : PASS
6985 09:28:43.856977 Write leveling : PASS
6986 09:28:43.860275 RX DQS gating : PASS
6987 09:28:43.860729 RX DQ/DQS(RDDQC) : PASS
6988 09:28:43.863647 TX DQ/DQS : PASS
6989 09:28:43.864343 RX DATLAT : PASS
6990 09:28:43.867159 RX DQ/DQS(Engine): PASS
6991 09:28:43.870121 TX OE : NO K
6992 09:28:43.870769 All Pass.
6993 09:28:43.871156
6994 09:28:43.871479 CH 0, Rank 1
6995 09:28:43.873362 SW Impedance : PASS
6996 09:28:43.876870 DUTY Scan : NO K
6997 09:28:43.877470 ZQ Calibration : PASS
6998 09:28:43.879838 Jitter Meter : NO K
6999 09:28:43.883120 CBT Training : PASS
7000 09:28:43.883691 Write leveling : NO K
7001 09:28:43.886783 RX DQS gating : PASS
7002 09:28:43.890561 RX DQ/DQS(RDDQC) : PASS
7003 09:28:43.891087 TX DQ/DQS : PASS
7004 09:28:43.893357 RX DATLAT : PASS
7005 09:28:43.896848 RX DQ/DQS(Engine): PASS
7006 09:28:43.897268 TX OE : NO K
7007 09:28:43.899815 All Pass.
7008 09:28:43.900405
7009 09:28:43.900838 CH 1, Rank 0
7010 09:28:43.902821 SW Impedance : PASS
7011 09:28:43.903237 DUTY Scan : NO K
7012 09:28:43.906645 ZQ Calibration : PASS
7013 09:28:43.909863 Jitter Meter : NO K
7014 09:28:43.910281 CBT Training : PASS
7015 09:28:43.913164 Write leveling : PASS
7016 09:28:43.916239 RX DQS gating : PASS
7017 09:28:43.916683 RX DQ/DQS(RDDQC) : PASS
7018 09:28:43.919575 TX DQ/DQS : PASS
7019 09:28:43.922693 RX DATLAT : PASS
7020 09:28:43.922990 RX DQ/DQS(Engine): PASS
7021 09:28:43.925863 TX OE : NO K
7022 09:28:43.926213 All Pass.
7023 09:28:43.926404
7024 09:28:43.929705 CH 1, Rank 1
7025 09:28:43.929931 SW Impedance : PASS
7026 09:28:43.932825 DUTY Scan : NO K
7027 09:28:43.933052 ZQ Calibration : PASS
7028 09:28:43.935970 Jitter Meter : NO K
7029 09:28:43.939353 CBT Training : PASS
7030 09:28:43.939507 Write leveling : NO K
7031 09:28:43.942622 RX DQS gating : PASS
7032 09:28:43.945902 RX DQ/DQS(RDDQC) : PASS
7033 09:28:43.946016 TX DQ/DQS : PASS
7034 09:28:43.948999 RX DATLAT : PASS
7035 09:28:43.952909 RX DQ/DQS(Engine): PASS
7036 09:28:43.953328 TX OE : NO K
7037 09:28:43.956086 All Pass.
7038 09:28:43.956502
7039 09:28:43.956911 DramC Write-DBI off
7040 09:28:43.959287 PER_BANK_REFRESH: Hybrid Mode
7041 09:28:43.959716 TX_TRACKING: ON
7042 09:28:43.969080 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7043 09:28:43.972432 [FAST_K] Save calibration result to emmc
7044 09:28:43.975733 dramc_set_vcore_voltage set vcore to 725000
7045 09:28:43.979785 Read voltage for 1600, 0
7046 09:28:43.980316 Vio18 = 0
7047 09:28:43.982703 Vcore = 725000
7048 09:28:43.983139 Vdram = 0
7049 09:28:43.983478 Vddq = 0
7050 09:28:43.985928 Vmddr = 0
7051 09:28:43.989351 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7052 09:28:43.995967 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7053 09:28:43.996385 MEM_TYPE=3, freq_sel=13
7054 09:28:43.999515 sv_algorithm_assistance_LP4_3733
7055 09:28:44.006032 ============ PULL DRAM RESETB DOWN ============
7056 09:28:44.009146 ========== PULL DRAM RESETB DOWN end =========
7057 09:28:44.012742 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7058 09:28:44.016103 ===================================
7059 09:28:44.019438 LPDDR4 DRAM CONFIGURATION
7060 09:28:44.022657 ===================================
7061 09:28:44.023121 EX_ROW_EN[0] = 0x0
7062 09:28:44.025723 EX_ROW_EN[1] = 0x0
7063 09:28:44.029138 LP4Y_EN = 0x0
7064 09:28:44.029567 WORK_FSP = 0x1
7065 09:28:44.032159 WL = 0x5
7066 09:28:44.032728 RL = 0x5
7067 09:28:44.035510 BL = 0x2
7068 09:28:44.036007 RPST = 0x0
7069 09:28:44.039335 RD_PRE = 0x0
7070 09:28:44.039760 WR_PRE = 0x1
7071 09:28:44.042596 WR_PST = 0x1
7072 09:28:44.043023 DBI_WR = 0x0
7073 09:28:44.045882 DBI_RD = 0x0
7074 09:28:44.046309 OTF = 0x1
7075 09:28:44.049048 ===================================
7076 09:28:44.052306 ===================================
7077 09:28:44.055505 ANA top config
7078 09:28:44.059256 ===================================
7079 09:28:44.059685 DLL_ASYNC_EN = 0
7080 09:28:44.062619 ALL_SLAVE_EN = 0
7081 09:28:44.065869 NEW_RANK_MODE = 1
7082 09:28:44.069002 DLL_IDLE_MODE = 1
7083 09:28:44.072297 LP45_APHY_COMB_EN = 1
7084 09:28:44.072854 TX_ODT_DIS = 0
7085 09:28:44.075510 NEW_8X_MODE = 1
7086 09:28:44.078740 ===================================
7087 09:28:44.081851 ===================================
7088 09:28:44.085642 data_rate = 3200
7089 09:28:44.088679 CKR = 1
7090 09:28:44.091886 DQ_P2S_RATIO = 8
7091 09:28:44.095195 ===================================
7092 09:28:44.095382 CA_P2S_RATIO = 8
7093 09:28:44.098816 DQ_CA_OPEN = 0
7094 09:28:44.101937 DQ_SEMI_OPEN = 0
7095 09:28:44.105131 CA_SEMI_OPEN = 0
7096 09:28:44.108718 CA_FULL_RATE = 0
7097 09:28:44.111917 DQ_CKDIV4_EN = 0
7098 09:28:44.112030 CA_CKDIV4_EN = 0
7099 09:28:44.115174 CA_PREDIV_EN = 0
7100 09:28:44.118405 PH8_DLY = 12
7101 09:28:44.121700 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7102 09:28:44.124972 DQ_AAMCK_DIV = 4
7103 09:28:44.128259 CA_AAMCK_DIV = 4
7104 09:28:44.128371 CA_ADMCK_DIV = 4
7105 09:28:44.132118 DQ_TRACK_CA_EN = 0
7106 09:28:44.135381 CA_PICK = 1600
7107 09:28:44.138454 CA_MCKIO = 1600
7108 09:28:44.141704 MCKIO_SEMI = 0
7109 09:28:44.145310 PLL_FREQ = 3068
7110 09:28:44.148591 DQ_UI_PI_RATIO = 32
7111 09:28:44.152105 CA_UI_PI_RATIO = 0
7112 09:28:44.152609 ===================================
7113 09:28:44.155822 ===================================
7114 09:28:44.159076 memory_type:LPDDR4
7115 09:28:44.162474 GP_NUM : 10
7116 09:28:44.163004 SRAM_EN : 1
7117 09:28:44.165507 MD32_EN : 0
7118 09:28:44.168488 ===================================
7119 09:28:44.171838 [ANA_INIT] >>>>>>>>>>>>>>
7120 09:28:44.175287 <<<<<< [CONFIGURE PHASE]: ANA_TX
7121 09:28:44.179181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7122 09:28:44.182207 ===================================
7123 09:28:44.182911 data_rate = 3200,PCW = 0X7600
7124 09:28:44.185511 ===================================
7125 09:28:44.188956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7126 09:28:44.195318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 09:28:44.202187 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7128 09:28:44.205182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7129 09:28:44.208811 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7130 09:28:44.211875 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7131 09:28:44.215412 [ANA_INIT] flow start
7132 09:28:44.218736 [ANA_INIT] PLL >>>>>>>>
7133 09:28:44.219265 [ANA_INIT] PLL <<<<<<<<
7134 09:28:44.221858 [ANA_INIT] MIDPI >>>>>>>>
7135 09:28:44.225069 [ANA_INIT] MIDPI <<<<<<<<
7136 09:28:44.225497 [ANA_INIT] DLL >>>>>>>>
7137 09:28:44.228828 [ANA_INIT] DLL <<<<<<<<
7138 09:28:44.231866 [ANA_INIT] flow end
7139 09:28:44.235121 ============ LP4 DIFF to SE enter ============
7140 09:28:44.238380 ============ LP4 DIFF to SE exit ============
7141 09:28:44.241742 [ANA_INIT] <<<<<<<<<<<<<
7142 09:28:44.245578 [Flow] Enable top DCM control >>>>>
7143 09:28:44.248803 [Flow] Enable top DCM control <<<<<
7144 09:28:44.251862 Enable DLL master slave shuffle
7145 09:28:44.255289 ==============================================================
7146 09:28:44.258326 Gating Mode config
7147 09:28:44.264856 ==============================================================
7148 09:28:44.265281 Config description:
7149 09:28:44.275318 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7150 09:28:44.281878 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7151 09:28:44.285045 SELPH_MODE 0: By rank 1: By Phase
7152 09:28:44.291519 ==============================================================
7153 09:28:44.294780 GAT_TRACK_EN = 1
7154 09:28:44.298363 RX_GATING_MODE = 2
7155 09:28:44.301694 RX_GATING_TRACK_MODE = 2
7156 09:28:44.305029 SELPH_MODE = 1
7157 09:28:44.308123 PICG_EARLY_EN = 1
7158 09:28:44.311701 VALID_LAT_VALUE = 1
7159 09:28:44.314813 ==============================================================
7160 09:28:44.317854 Enter into Gating configuration >>>>
7161 09:28:44.321485 Exit from Gating configuration <<<<
7162 09:28:44.324838 Enter into DVFS_PRE_config >>>>>
7163 09:28:44.337856 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7164 09:28:44.338070 Exit from DVFS_PRE_config <<<<<
7165 09:28:44.340861 Enter into PICG configuration >>>>
7166 09:28:44.344865 Exit from PICG configuration <<<<
7167 09:28:44.348196 [RX_INPUT] configuration >>>>>
7168 09:28:44.351716 [RX_INPUT] configuration <<<<<
7169 09:28:44.357654 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7170 09:28:44.360880 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7171 09:28:44.367653 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7172 09:28:44.375161 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7173 09:28:44.381492 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 09:28:44.387915 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 09:28:44.391102 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7176 09:28:44.394755 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7177 09:28:44.397942 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7178 09:28:44.404727 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7179 09:28:44.408125 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7180 09:28:44.411036 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7181 09:28:44.414596 ===================================
7182 09:28:44.417993 LPDDR4 DRAM CONFIGURATION
7183 09:28:44.421312 ===================================
7184 09:28:44.421740 EX_ROW_EN[0] = 0x0
7185 09:28:44.424692 EX_ROW_EN[1] = 0x0
7186 09:28:44.427576 LP4Y_EN = 0x0
7187 09:28:44.428214 WORK_FSP = 0x1
7188 09:28:44.431013 WL = 0x5
7189 09:28:44.431435 RL = 0x5
7190 09:28:44.434180 BL = 0x2
7191 09:28:44.434599 RPST = 0x0
7192 09:28:44.437507 RD_PRE = 0x0
7193 09:28:44.437925 WR_PRE = 0x1
7194 09:28:44.440831 WR_PST = 0x1
7195 09:28:44.441255 DBI_WR = 0x0
7196 09:28:44.444652 DBI_RD = 0x0
7197 09:28:44.445096 OTF = 0x1
7198 09:28:44.448035 ===================================
7199 09:28:44.451068 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7200 09:28:44.457398 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7201 09:28:44.460738 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7202 09:28:44.464708 ===================================
7203 09:28:44.468062 LPDDR4 DRAM CONFIGURATION
7204 09:28:44.470918 ===================================
7205 09:28:44.471347 EX_ROW_EN[0] = 0x10
7206 09:28:44.474234 EX_ROW_EN[1] = 0x0
7207 09:28:44.474658 LP4Y_EN = 0x0
7208 09:28:44.477790 WORK_FSP = 0x1
7209 09:28:44.481179 WL = 0x5
7210 09:28:44.481700 RL = 0x5
7211 09:28:44.483993 BL = 0x2
7212 09:28:44.484413 RPST = 0x0
7213 09:28:44.487615 RD_PRE = 0x0
7214 09:28:44.488133 WR_PRE = 0x1
7215 09:28:44.490994 WR_PST = 0x1
7216 09:28:44.491514 DBI_WR = 0x0
7217 09:28:44.494845 DBI_RD = 0x0
7218 09:28:44.495361 OTF = 0x1
7219 09:28:44.498179 ===================================
7220 09:28:44.504623 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7221 09:28:44.505148 ==
7222 09:28:44.508050 Dram Type= 6, Freq= 0, CH_0, rank 0
7223 09:28:44.511064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7224 09:28:44.511585 ==
7225 09:28:44.514254 [Duty_Offset_Calibration]
7226 09:28:44.517634 B0:2 B1:0 CA:1
7227 09:28:44.518154
7228 09:28:44.520649 [DutyScan_Calibration_Flow] k_type=0
7229 09:28:44.529103
7230 09:28:44.529594 ==CLK 0==
7231 09:28:44.532162 Final CLK duty delay cell = 0
7232 09:28:44.535959 [0] MAX Duty = 5187%(X100), DQS PI = 20
7233 09:28:44.539176 [0] MIN Duty = 5000%(X100), DQS PI = 62
7234 09:28:44.539705 [0] AVG Duty = 5093%(X100)
7235 09:28:44.542585
7236 09:28:44.545670 CH0 CLK Duty spec in!! Max-Min= 187%
7237 09:28:44.548857 [DutyScan_Calibration_Flow] ====Done====
7238 09:28:44.549326
7239 09:28:44.552206 [DutyScan_Calibration_Flow] k_type=1
7240 09:28:44.568402
7241 09:28:44.568870 ==DQS 0 ==
7242 09:28:44.571612 Final DQS duty delay cell = 0
7243 09:28:44.574900 [0] MAX Duty = 5218%(X100), DQS PI = 32
7244 09:28:44.578349 [0] MIN Duty = 4938%(X100), DQS PI = 62
7245 09:28:44.581690 [0] AVG Duty = 5078%(X100)
7246 09:28:44.582114
7247 09:28:44.582449 ==DQS 1 ==
7248 09:28:44.584958 Final DQS duty delay cell = -4
7249 09:28:44.588237 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7250 09:28:44.591528 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7251 09:28:44.594760 [-4] AVG Duty = 4984%(X100)
7252 09:28:44.595181
7253 09:28:44.598108 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7254 09:28:44.598531
7255 09:28:44.601455 CH0 DQS 1 Duty spec in!! Max-Min= 219%
7256 09:28:44.604623 [DutyScan_Calibration_Flow] ====Done====
7257 09:28:44.605046
7258 09:28:44.608089 [DutyScan_Calibration_Flow] k_type=3
7259 09:28:44.626032
7260 09:28:44.626493 ==DQM 0 ==
7261 09:28:44.629116 Final DQM duty delay cell = 0
7262 09:28:44.632606 [0] MAX Duty = 5062%(X100), DQS PI = 12
7263 09:28:44.636087 [0] MIN Duty = 4813%(X100), DQS PI = 2
7264 09:28:44.636658 [0] AVG Duty = 4937%(X100)
7265 09:28:44.639003
7266 09:28:44.639425 ==DQM 1 ==
7267 09:28:44.642661 Final DQM duty delay cell = 0
7268 09:28:44.646344 [0] MAX Duty = 5249%(X100), DQS PI = 30
7269 09:28:44.649431 [0] MIN Duty = 5000%(X100), DQS PI = 20
7270 09:28:44.652467 [0] AVG Duty = 5124%(X100)
7271 09:28:44.652919
7272 09:28:44.655735 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7273 09:28:44.656128
7274 09:28:44.659047 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7275 09:28:44.663168 [DutyScan_Calibration_Flow] ====Done====
7276 09:28:44.663694
7277 09:28:44.665962 [DutyScan_Calibration_Flow] k_type=2
7278 09:28:44.682854
7279 09:28:44.683370 ==DQ 0 ==
7280 09:28:44.686075 Final DQ duty delay cell = 0
7281 09:28:44.689888 [0] MAX Duty = 5124%(X100), DQS PI = 34
7282 09:28:44.693144 [0] MIN Duty = 5000%(X100), DQS PI = 0
7283 09:28:44.693669 [0] AVG Duty = 5062%(X100)
7284 09:28:44.694007
7285 09:28:44.696668 ==DQ 1 ==
7286 09:28:44.699933 Final DQ duty delay cell = 0
7287 09:28:44.703185 [0] MAX Duty = 4969%(X100), DQS PI = 52
7288 09:28:44.706597 [0] MIN Duty = 4875%(X100), DQS PI = 10
7289 09:28:44.707294 [0] AVG Duty = 4922%(X100)
7290 09:28:44.707660
7291 09:28:44.709854 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7292 09:28:44.710419
7293 09:28:44.712844 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7294 09:28:44.719661 [DutyScan_Calibration_Flow] ====Done====
7295 09:28:44.720070 ==
7296 09:28:44.723199 Dram Type= 6, Freq= 0, CH_1, rank 0
7297 09:28:44.726463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7298 09:28:44.726874 ==
7299 09:28:44.729870 [Duty_Offset_Calibration]
7300 09:28:44.730417 B0:0 B1:-1 CA:2
7301 09:28:44.730760
7302 09:28:44.732861 [DutyScan_Calibration_Flow] k_type=0
7303 09:28:44.743310
7304 09:28:44.743722 ==CLK 0==
7305 09:28:44.746582 Final CLK duty delay cell = 0
7306 09:28:44.749834 [0] MAX Duty = 5156%(X100), DQS PI = 10
7307 09:28:44.753237 [0] MIN Duty = 4906%(X100), DQS PI = 46
7308 09:28:44.753773 [0] AVG Duty = 5031%(X100)
7309 09:28:44.756365
7310 09:28:44.756826 CH1 CLK Duty spec in!! Max-Min= 250%
7311 09:28:44.763589 [DutyScan_Calibration_Flow] ====Done====
7312 09:28:44.764142
7313 09:28:44.766761 [DutyScan_Calibration_Flow] k_type=1
7314 09:28:44.783070
7315 09:28:44.783589 ==DQS 0 ==
7316 09:28:44.786284 Final DQS duty delay cell = 0
7317 09:28:44.789735 [0] MAX Duty = 5093%(X100), DQS PI = 24
7318 09:28:44.793193 [0] MIN Duty = 4969%(X100), DQS PI = 2
7319 09:28:44.796148 [0] AVG Duty = 5031%(X100)
7320 09:28:44.796591
7321 09:28:44.796930 ==DQS 1 ==
7322 09:28:44.799813 Final DQS duty delay cell = 0
7323 09:28:44.802835 [0] MAX Duty = 5187%(X100), DQS PI = 0
7324 09:28:44.806400 [0] MIN Duty = 4844%(X100), DQS PI = 32
7325 09:28:44.809478 [0] AVG Duty = 5015%(X100)
7326 09:28:44.810005
7327 09:28:44.812947 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7328 09:28:44.813467
7329 09:28:44.815810 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7330 09:28:44.819572 [DutyScan_Calibration_Flow] ====Done====
7331 09:28:44.820118
7332 09:28:44.822310 [DutyScan_Calibration_Flow] k_type=3
7333 09:28:44.840682
7334 09:28:44.841208 ==DQM 0 ==
7335 09:28:44.844131 Final DQM duty delay cell = 4
7336 09:28:44.847280 [4] MAX Duty = 5125%(X100), DQS PI = 22
7337 09:28:44.850493 [4] MIN Duty = 4938%(X100), DQS PI = 46
7338 09:28:44.853912 [4] AVG Duty = 5031%(X100)
7339 09:28:44.854339
7340 09:28:44.854684 ==DQM 1 ==
7341 09:28:44.857176 Final DQM duty delay cell = 0
7342 09:28:44.860349 [0] MAX Duty = 5281%(X100), DQS PI = 60
7343 09:28:44.863878 [0] MIN Duty = 4876%(X100), DQS PI = 34
7344 09:28:44.867072 [0] AVG Duty = 5078%(X100)
7345 09:28:44.867595
7346 09:28:44.871098 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7347 09:28:44.871625
7348 09:28:44.873608 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7349 09:28:44.877156 [DutyScan_Calibration_Flow] ====Done====
7350 09:28:44.877582
7351 09:28:44.880643 [DutyScan_Calibration_Flow] k_type=2
7352 09:28:44.897093
7353 09:28:44.897719 ==DQ 0 ==
7354 09:28:44.900414 Final DQ duty delay cell = 0
7355 09:28:44.903816 [0] MAX Duty = 5062%(X100), DQS PI = 24
7356 09:28:44.907082 [0] MIN Duty = 4969%(X100), DQS PI = 0
7357 09:28:44.907507 [0] AVG Duty = 5015%(X100)
7358 09:28:44.910725
7359 09:28:44.911249 ==DQ 1 ==
7360 09:28:44.913914 Final DQ duty delay cell = 0
7361 09:28:44.917139 [0] MAX Duty = 5031%(X100), DQS PI = 0
7362 09:28:44.920498 [0] MIN Duty = 4813%(X100), DQS PI = 34
7363 09:28:44.921166 [0] AVG Duty = 4922%(X100)
7364 09:28:44.921644
7365 09:28:44.923768 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7366 09:28:44.924289
7367 09:28:44.927123 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7368 09:28:44.933864 [DutyScan_Calibration_Flow] ====Done====
7369 09:28:44.936963 nWR fixed to 30
7370 09:28:44.937394 [ModeRegInit_LP4] CH0 RK0
7371 09:28:44.940283 [ModeRegInit_LP4] CH0 RK1
7372 09:28:44.944021 [ModeRegInit_LP4] CH1 RK0
7373 09:28:44.944445 [ModeRegInit_LP4] CH1 RK1
7374 09:28:44.947305 match AC timing 5
7375 09:28:44.950349 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7376 09:28:44.953822 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7377 09:28:44.960350 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7378 09:28:44.963981 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7379 09:28:44.971083 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7380 09:28:44.971622 [MiockJmeterHQA]
7381 09:28:44.971970
7382 09:28:44.973823 [DramcMiockJmeter] u1RxGatingPI = 0
7383 09:28:44.977422 0 : 4368, 4140
7384 09:28:44.977973 4 : 4253, 4026
7385 09:28:44.978326 8 : 4363, 4137
7386 09:28:44.980612 12 : 4252, 4027
7387 09:28:44.981047 16 : 4363, 4138
7388 09:28:44.983741 20 : 4253, 4026
7389 09:28:44.984272 24 : 4363, 4137
7390 09:28:44.986949 28 : 4252, 4027
7391 09:28:44.987585 32 : 4253, 4027
7392 09:28:44.990215 36 : 4250, 4026
7393 09:28:44.990643 40 : 4360, 4137
7394 09:28:44.990984 44 : 4361, 4137
7395 09:28:44.993648 48 : 4250, 4027
7396 09:28:44.994077 52 : 4253, 4026
7397 09:28:44.997005 56 : 4250, 4027
7398 09:28:44.997434 60 : 4250, 4027
7399 09:28:45.000231 64 : 4253, 4029
7400 09:28:45.000686 68 : 4361, 4138
7401 09:28:45.003530 72 : 4250, 4026
7402 09:28:45.003959 76 : 4250, 4027
7403 09:28:45.004303 80 : 4250, 4027
7404 09:28:45.007196 84 : 4252, 4030
7405 09:28:45.007730 88 : 4249, 3740
7406 09:28:45.010501 92 : 4360, 0
7407 09:28:45.011030 96 : 4250, 0
7408 09:28:45.011374 100 : 4360, 0
7409 09:28:45.013490 104 : 4250, 0
7410 09:28:45.013920 108 : 4361, 0
7411 09:28:45.017082 112 : 4250, 0
7412 09:28:45.017611 116 : 4250, 0
7413 09:28:45.017959 120 : 4253, 0
7414 09:28:45.020072 124 : 4250, 0
7415 09:28:45.020500 128 : 4250, 0
7416 09:28:45.023210 132 : 4253, 0
7417 09:28:45.023641 136 : 4250, 0
7418 09:28:45.023981 140 : 4250, 0
7419 09:28:45.026475 144 : 4253, 0
7420 09:28:45.026971 148 : 4363, 0
7421 09:28:45.027389 152 : 4361, 0
7422 09:28:45.030207 156 : 4362, 0
7423 09:28:45.030659 160 : 4250, 0
7424 09:28:45.033373 164 : 4250, 0
7425 09:28:45.033807 168 : 4250, 0
7426 09:28:45.034154 172 : 4250, 0
7427 09:28:45.036535 176 : 4250, 0
7428 09:28:45.037004 180 : 4250, 0
7429 09:28:45.040206 184 : 4253, 0
7430 09:28:45.040673 188 : 4253, 0
7431 09:28:45.041024 192 : 4250, 0
7432 09:28:45.043100 196 : 4252, 0
7433 09:28:45.043530 200 : 4360, 11
7434 09:28:45.046932 204 : 4250, 2676
7435 09:28:45.047359 208 : 4249, 4027
7436 09:28:45.050426 212 : 4363, 4137
7437 09:28:45.050953 216 : 4250, 4026
7438 09:28:45.051300 220 : 4250, 4027
7439 09:28:45.053277 224 : 4361, 4138
7440 09:28:45.053702 228 : 4250, 4027
7441 09:28:45.056747 232 : 4250, 4026
7442 09:28:45.057175 236 : 4363, 4140
7443 09:28:45.059926 240 : 4250, 4027
7444 09:28:45.060351 244 : 4250, 4027
7445 09:28:45.063426 248 : 4250, 4026
7446 09:28:45.063953 252 : 4253, 4029
7447 09:28:45.066496 256 : 4250, 4027
7448 09:28:45.066919 260 : 4250, 4027
7449 09:28:45.069772 264 : 4360, 4137
7450 09:28:45.070195 268 : 4250, 4027
7451 09:28:45.073067 272 : 4250, 4027
7452 09:28:45.073492 276 : 4361, 4138
7453 09:28:45.076909 280 : 4250, 4027
7454 09:28:45.077332 284 : 4253, 4026
7455 09:28:45.077673 288 : 4363, 4140
7456 09:28:45.079834 292 : 4250, 4027
7457 09:28:45.080372 296 : 4250, 4027
7458 09:28:45.083605 300 : 4250, 4026
7459 09:28:45.084508 304 : 4253, 4029
7460 09:28:45.086416 308 : 4250, 4027
7461 09:28:45.087004 312 : 4250, 3907
7462 09:28:45.089875 316 : 4360, 2093
7463 09:28:45.090303
7464 09:28:45.090637 MIOCK jitter meter ch=0
7465 09:28:45.090949
7466 09:28:45.093097 1T = (316-92) = 224 dly cells
7467 09:28:45.099596 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7468 09:28:45.100146 ==
7469 09:28:45.102707 Dram Type= 6, Freq= 0, CH_0, rank 0
7470 09:28:45.106291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7471 09:28:45.106713 ==
7472 09:28:45.112877 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7473 09:28:45.116048 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7474 09:28:45.122725 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7475 09:28:45.126546 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7476 09:28:45.136372 [CA 0] Center 43 (13~73) winsize 61
7477 09:28:45.139732 [CA 1] Center 43 (13~73) winsize 61
7478 09:28:45.142880 [CA 2] Center 38 (8~68) winsize 61
7479 09:28:45.146321 [CA 3] Center 37 (8~67) winsize 60
7480 09:28:45.149372 [CA 4] Center 36 (7~66) winsize 60
7481 09:28:45.153084 [CA 5] Center 35 (5~66) winsize 62
7482 09:28:45.153532
7483 09:28:45.156360 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7484 09:28:45.156914
7485 09:28:45.159309 [CATrainingPosCal] consider 1 rank data
7486 09:28:45.162868 u2DelayCellTimex100 = 290/100 ps
7487 09:28:45.166040 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7488 09:28:45.172823 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7489 09:28:45.176108 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7490 09:28:45.180025 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7491 09:28:45.183234 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7492 09:28:45.186138 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7493 09:28:45.186570
7494 09:28:45.189272 CA PerBit enable=1, Macro0, CA PI delay=35
7495 09:28:45.189700
7496 09:28:45.192801 [CBTSetCACLKResult] CA Dly = 35
7497 09:28:45.196326 CS Dly: 9 (0~40)
7498 09:28:45.199360 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7499 09:28:45.202834 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7500 09:28:45.203369 ==
7501 09:28:45.205803 Dram Type= 6, Freq= 0, CH_0, rank 1
7502 09:28:45.209455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7503 09:28:45.212726 ==
7504 09:28:45.215870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7505 09:28:45.219795 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7506 09:28:45.226366 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7507 09:28:45.229329 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7508 09:28:45.239543 [CA 0] Center 44 (14~74) winsize 61
7509 09:28:45.242936 [CA 1] Center 44 (14~74) winsize 61
7510 09:28:45.246484 [CA 2] Center 38 (9~68) winsize 60
7511 09:28:45.249769 [CA 3] Center 38 (9~68) winsize 60
7512 09:28:45.252900 [CA 4] Center 37 (7~67) winsize 61
7513 09:28:45.256122 [CA 5] Center 36 (7~66) winsize 60
7514 09:28:45.256603
7515 09:28:45.259774 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7516 09:28:45.260204
7517 09:28:45.262695 [CATrainingPosCal] consider 2 rank data
7518 09:28:45.266483 u2DelayCellTimex100 = 290/100 ps
7519 09:28:45.269338 CA0 delay=43 (14~73),Diff = 7 PI (23 cell)
7520 09:28:45.276408 CA1 delay=43 (14~73),Diff = 7 PI (23 cell)
7521 09:28:45.279600 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7522 09:28:45.283039 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7523 09:28:45.286081 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7524 09:28:45.289280 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7525 09:28:45.289723
7526 09:28:45.292910 CA PerBit enable=1, Macro0, CA PI delay=36
7527 09:28:45.293450
7528 09:28:45.296156 [CBTSetCACLKResult] CA Dly = 36
7529 09:28:45.299504 CS Dly: 10 (0~43)
7530 09:28:45.302484 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7531 09:28:45.306275 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7532 09:28:45.306723
7533 09:28:45.309622 ----->DramcWriteLeveling(PI) begin...
7534 09:28:45.310080 ==
7535 09:28:45.313165 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 09:28:45.315777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 09:28:45.319597 ==
7538 09:28:45.320036 Write leveling (Byte 0): 34 => 34
7539 09:28:45.323091 Write leveling (Byte 1): 30 => 30
7540 09:28:45.325671 DramcWriteLeveling(PI) end<-----
7541 09:28:45.326110
7542 09:28:45.326545 ==
7543 09:28:45.329427 Dram Type= 6, Freq= 0, CH_0, rank 0
7544 09:28:45.336055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 09:28:45.336636 ==
7546 09:28:45.339263 [Gating] SW mode calibration
7547 09:28:45.345964 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7548 09:28:45.349077 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7549 09:28:45.352821 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 09:28:45.359392 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 09:28:45.362625 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
7552 09:28:45.365818 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7553 09:28:45.372406 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7554 09:28:45.376065 1 4 20 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
7555 09:28:45.379079 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 09:28:45.385713 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 09:28:45.389274 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 09:28:45.392482 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 09:28:45.399033 1 5 8 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7560 09:28:45.403176 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7561 09:28:45.405713 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7562 09:28:45.412922 1 5 20 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
7563 09:28:45.415782 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 09:28:45.419484 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 09:28:45.426028 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 09:28:45.429185 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 09:28:45.432406 1 6 8 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7568 09:28:45.439210 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7569 09:28:45.442007 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7570 09:28:45.445097 1 6 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7571 09:28:45.451723 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 09:28:45.455563 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 09:28:45.458916 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 09:28:45.465483 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 09:28:45.469112 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7576 09:28:45.472044 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 09:28:45.478698 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7578 09:28:45.481789 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7579 09:28:45.485214 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 09:28:45.491499 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 09:28:45.495202 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 09:28:45.498354 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 09:28:45.505420 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 09:28:45.509094 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 09:28:45.512367 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 09:28:45.519063 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 09:28:45.522211 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 09:28:45.525443 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 09:28:45.531949 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 09:28:45.535147 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 09:28:45.538900 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7592 09:28:45.541927 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7593 09:28:45.548419 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7594 09:28:45.551892 Total UI for P1: 0, mck2ui 16
7595 09:28:45.554987 best dqsien dly found for B0: ( 1, 9, 10)
7596 09:28:45.558079 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7597 09:28:45.561313 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 09:28:45.564937 Total UI for P1: 0, mck2ui 16
7599 09:28:45.568443 best dqsien dly found for B1: ( 1, 9, 18)
7600 09:28:45.571619 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7601 09:28:45.577930 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7602 09:28:45.578377
7603 09:28:45.581099 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7604 09:28:45.584169 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7605 09:28:45.587763 [Gating] SW calibration Done
7606 09:28:45.588187 ==
7607 09:28:45.591207 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 09:28:45.594227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 09:28:45.594825 ==
7610 09:28:45.597656 RX Vref Scan: 0
7611 09:28:45.598094
7612 09:28:45.598432 RX Vref 0 -> 0, step: 1
7613 09:28:45.598799
7614 09:28:45.601164 RX Delay 0 -> 252, step: 8
7615 09:28:45.604439 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7616 09:28:45.610998 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7617 09:28:45.614238 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7618 09:28:45.617369 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7619 09:28:45.620764 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7620 09:28:45.624104 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7621 09:28:45.627435 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7622 09:28:45.633941 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7623 09:28:45.637402 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
7624 09:28:45.641233 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7625 09:28:45.643845 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
7626 09:28:45.647949 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7627 09:28:45.654279 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7628 09:28:45.657271 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7629 09:28:45.660698 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7630 09:28:45.664054 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7631 09:28:45.664618 ==
7632 09:28:45.667322 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 09:28:45.674007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 09:28:45.674534 ==
7635 09:28:45.674914 DQS Delay:
7636 09:28:45.677602 DQS0 = 0, DQS1 = 0
7637 09:28:45.678128 DQM Delay:
7638 09:28:45.678469 DQM0 = 138, DQM1 = 128
7639 09:28:45.680652 DQ Delay:
7640 09:28:45.683813 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7641 09:28:45.687287 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7642 09:28:45.690464 DQ8 =123, DQ9 =115, DQ10 =127, DQ11 =127
7643 09:28:45.694177 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7644 09:28:45.694623
7645 09:28:45.694961
7646 09:28:45.695278 ==
7647 09:28:45.697341 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 09:28:45.700358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 09:28:45.703756 ==
7650 09:28:45.704180
7651 09:28:45.704515
7652 09:28:45.704882 TX Vref Scan disable
7653 09:28:45.707113 == TX Byte 0 ==
7654 09:28:45.710906 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7655 09:28:45.714042 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7656 09:28:45.717233 == TX Byte 1 ==
7657 09:28:45.720944 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7658 09:28:45.724160 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7659 09:28:45.724709 ==
7660 09:28:45.727510 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 09:28:45.733754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 09:28:45.734471 ==
7663 09:28:45.745821
7664 09:28:45.749131 TX Vref early break, caculate TX vref
7665 09:28:45.753083 TX Vref=16, minBit 12, minWin=22, winSum=378
7666 09:28:45.755738 TX Vref=18, minBit 12, minWin=22, winSum=387
7667 09:28:45.759334 TX Vref=20, minBit 4, minWin=24, winSum=398
7668 09:28:45.762804 TX Vref=22, minBit 6, minWin=24, winSum=404
7669 09:28:45.765891 TX Vref=24, minBit 1, minWin=25, winSum=418
7670 09:28:45.773048 TX Vref=26, minBit 2, minWin=26, winSum=429
7671 09:28:45.775853 TX Vref=28, minBit 12, minWin=25, winSum=430
7672 09:28:45.779220 TX Vref=30, minBit 2, minWin=25, winSum=421
7673 09:28:45.782223 TX Vref=32, minBit 1, minWin=25, winSum=418
7674 09:28:45.785935 TX Vref=34, minBit 1, minWin=24, winSum=404
7675 09:28:45.792602 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 26
7676 09:28:45.793115
7677 09:28:45.795807 Final TX Range 0 Vref 26
7678 09:28:45.796326
7679 09:28:45.796757 ==
7680 09:28:45.798684 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 09:28:45.802560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 09:28:45.803090 ==
7683 09:28:45.803437
7684 09:28:45.803753
7685 09:28:45.805469 TX Vref Scan disable
7686 09:28:45.812229 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7687 09:28:45.812786 == TX Byte 0 ==
7688 09:28:45.815753 u2DelayCellOfst[0]=16 cells (5 PI)
7689 09:28:45.819034 u2DelayCellOfst[1]=20 cells (6 PI)
7690 09:28:45.822586 u2DelayCellOfst[2]=16 cells (5 PI)
7691 09:28:45.825764 u2DelayCellOfst[3]=16 cells (5 PI)
7692 09:28:45.828933 u2DelayCellOfst[4]=10 cells (3 PI)
7693 09:28:45.832635 u2DelayCellOfst[5]=0 cells (0 PI)
7694 09:28:45.835551 u2DelayCellOfst[6]=20 cells (6 PI)
7695 09:28:45.839226 u2DelayCellOfst[7]=20 cells (6 PI)
7696 09:28:45.842571 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7697 09:28:45.845465 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7698 09:28:45.848990 == TX Byte 1 ==
7699 09:28:45.852435 u2DelayCellOfst[8]=0 cells (0 PI)
7700 09:28:45.853039 u2DelayCellOfst[9]=0 cells (0 PI)
7701 09:28:45.855580 u2DelayCellOfst[10]=6 cells (2 PI)
7702 09:28:45.858873 u2DelayCellOfst[11]=3 cells (1 PI)
7703 09:28:45.862031 u2DelayCellOfst[12]=10 cells (3 PI)
7704 09:28:45.865869 u2DelayCellOfst[13]=10 cells (3 PI)
7705 09:28:45.868600 u2DelayCellOfst[14]=16 cells (5 PI)
7706 09:28:45.872492 u2DelayCellOfst[15]=10 cells (3 PI)
7707 09:28:45.875686 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7708 09:28:45.881642 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7709 09:28:45.882178 DramC Write-DBI on
7710 09:28:45.882616 ==
7711 09:28:45.885420 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 09:28:45.892195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 09:28:45.892772 ==
7714 09:28:45.893222
7715 09:28:45.893634
7716 09:28:45.894040 TX Vref Scan disable
7717 09:28:45.895731 == TX Byte 0 ==
7718 09:28:45.898931 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7719 09:28:45.902133 == TX Byte 1 ==
7720 09:28:45.905699 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7721 09:28:45.906276 DramC Write-DBI off
7722 09:28:45.909022
7723 09:28:45.909439 [DATLAT]
7724 09:28:45.909777 Freq=1600, CH0 RK0
7725 09:28:45.910091
7726 09:28:45.912707 DATLAT Default: 0xf
7727 09:28:45.913230 0, 0xFFFF, sum = 0
7728 09:28:45.915989 1, 0xFFFF, sum = 0
7729 09:28:45.916628 2, 0xFFFF, sum = 0
7730 09:28:45.918723 3, 0xFFFF, sum = 0
7731 09:28:45.919146 4, 0xFFFF, sum = 0
7732 09:28:45.922459 5, 0xFFFF, sum = 0
7733 09:28:45.925747 6, 0xFFFF, sum = 0
7734 09:28:45.926380 7, 0xFFFF, sum = 0
7735 09:28:45.929062 8, 0xFFFF, sum = 0
7736 09:28:45.929533 9, 0xFFFF, sum = 0
7737 09:28:45.932252 10, 0xFFFF, sum = 0
7738 09:28:45.932801 11, 0xFFFF, sum = 0
7739 09:28:45.935810 12, 0xFFFF, sum = 0
7740 09:28:45.936244 13, 0xFFFF, sum = 0
7741 09:28:45.938630 14, 0x0, sum = 1
7742 09:28:45.939058 15, 0x0, sum = 2
7743 09:28:45.942067 16, 0x0, sum = 3
7744 09:28:45.942496 17, 0x0, sum = 4
7745 09:28:45.945826 best_step = 15
7746 09:28:45.946248
7747 09:28:45.946586 ==
7748 09:28:45.949136 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 09:28:45.952444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 09:28:45.953010 ==
7751 09:28:45.953355 RX Vref Scan: 1
7752 09:28:45.955639
7753 09:28:45.956062 Set Vref Range= 24 -> 127
7754 09:28:45.956401
7755 09:28:45.958853 RX Vref 24 -> 127, step: 1
7756 09:28:45.959283
7757 09:28:45.962150 RX Delay 19 -> 252, step: 4
7758 09:28:45.962572
7759 09:28:45.965457 Set Vref, RX VrefLevel [Byte0]: 24
7760 09:28:45.969155 [Byte1]: 24
7761 09:28:45.969583
7762 09:28:45.972566 Set Vref, RX VrefLevel [Byte0]: 25
7763 09:28:45.975943 [Byte1]: 25
7764 09:28:45.976467
7765 09:28:45.978946 Set Vref, RX VrefLevel [Byte0]: 26
7766 09:28:45.982122 [Byte1]: 26
7767 09:28:45.986368
7768 09:28:45.986889 Set Vref, RX VrefLevel [Byte0]: 27
7769 09:28:45.989339 [Byte1]: 27
7770 09:28:45.993687
7771 09:28:45.994204 Set Vref, RX VrefLevel [Byte0]: 28
7772 09:28:45.997178 [Byte1]: 28
7773 09:28:46.001263
7774 09:28:46.001786 Set Vref, RX VrefLevel [Byte0]: 29
7775 09:28:46.004405 [Byte1]: 29
7776 09:28:46.008931
7777 09:28:46.009453 Set Vref, RX VrefLevel [Byte0]: 30
7778 09:28:46.011880 [Byte1]: 30
7779 09:28:46.016356
7780 09:28:46.016811 Set Vref, RX VrefLevel [Byte0]: 31
7781 09:28:46.019395 [Byte1]: 31
7782 09:28:46.023706
7783 09:28:46.024225 Set Vref, RX VrefLevel [Byte0]: 32
7784 09:28:46.027143 [Byte1]: 32
7785 09:28:46.031312
7786 09:28:46.031736 Set Vref, RX VrefLevel [Byte0]: 33
7787 09:28:46.034712 [Byte1]: 33
7788 09:28:46.039005
7789 09:28:46.039431 Set Vref, RX VrefLevel [Byte0]: 34
7790 09:28:46.042462 [Byte1]: 34
7791 09:28:46.046834
7792 09:28:46.047255 Set Vref, RX VrefLevel [Byte0]: 35
7793 09:28:46.050039 [Byte1]: 35
7794 09:28:46.053994
7795 09:28:46.054532 Set Vref, RX VrefLevel [Byte0]: 36
7796 09:28:46.057621 [Byte1]: 36
7797 09:28:46.061825
7798 09:28:46.062248 Set Vref, RX VrefLevel [Byte0]: 37
7799 09:28:46.065163 [Byte1]: 37
7800 09:28:46.069464
7801 09:28:46.069961 Set Vref, RX VrefLevel [Byte0]: 38
7802 09:28:46.072747 [Byte1]: 38
7803 09:28:46.077100
7804 09:28:46.077624 Set Vref, RX VrefLevel [Byte0]: 39
7805 09:28:46.080204 [Byte1]: 39
7806 09:28:46.084887
7807 09:28:46.085409 Set Vref, RX VrefLevel [Byte0]: 40
7808 09:28:46.087888 [Byte1]: 40
7809 09:28:46.092039
7810 09:28:46.092479 Set Vref, RX VrefLevel [Byte0]: 41
7811 09:28:46.095663 [Byte1]: 41
7812 09:28:46.099752
7813 09:28:46.100179 Set Vref, RX VrefLevel [Byte0]: 42
7814 09:28:46.102520 [Byte1]: 42
7815 09:28:46.106978
7816 09:28:46.107505 Set Vref, RX VrefLevel [Byte0]: 43
7817 09:28:46.110734 [Byte1]: 43
7818 09:28:46.115032
7819 09:28:46.115579 Set Vref, RX VrefLevel [Byte0]: 44
7820 09:28:46.117803 [Byte1]: 44
7821 09:28:46.122335
7822 09:28:46.122857 Set Vref, RX VrefLevel [Byte0]: 45
7823 09:28:46.125196 [Byte1]: 45
7824 09:28:46.129905
7825 09:28:46.130328 Set Vref, RX VrefLevel [Byte0]: 46
7826 09:28:46.133152 [Byte1]: 46
7827 09:28:46.137162
7828 09:28:46.137585 Set Vref, RX VrefLevel [Byte0]: 47
7829 09:28:46.140528 [Byte1]: 47
7830 09:28:46.145045
7831 09:28:46.145565 Set Vref, RX VrefLevel [Byte0]: 48
7832 09:28:46.148036 [Byte1]: 48
7833 09:28:46.152492
7834 09:28:46.153096 Set Vref, RX VrefLevel [Byte0]: 49
7835 09:28:46.155789 [Byte1]: 49
7836 09:28:46.160177
7837 09:28:46.160750 Set Vref, RX VrefLevel [Byte0]: 50
7838 09:28:46.163185 [Byte1]: 50
7839 09:28:46.167455
7840 09:28:46.167896 Set Vref, RX VrefLevel [Byte0]: 51
7841 09:28:46.171122 [Byte1]: 51
7842 09:28:46.175209
7843 09:28:46.175727 Set Vref, RX VrefLevel [Byte0]: 52
7844 09:28:46.178596 [Byte1]: 52
7845 09:28:46.182921
7846 09:28:46.183447 Set Vref, RX VrefLevel [Byte0]: 53
7847 09:28:46.185899 [Byte1]: 53
7848 09:28:46.190175
7849 09:28:46.190593 Set Vref, RX VrefLevel [Byte0]: 54
7850 09:28:46.193413 [Byte1]: 54
7851 09:28:46.198258
7852 09:28:46.198773 Set Vref, RX VrefLevel [Byte0]: 55
7853 09:28:46.201262 [Byte1]: 55
7854 09:28:46.205737
7855 09:28:46.206183 Set Vref, RX VrefLevel [Byte0]: 56
7856 09:28:46.208853 [Byte1]: 56
7857 09:28:46.213347
7858 09:28:46.213866 Set Vref, RX VrefLevel [Byte0]: 57
7859 09:28:46.216319 [Byte1]: 57
7860 09:28:46.220884
7861 09:28:46.221416 Set Vref, RX VrefLevel [Byte0]: 58
7862 09:28:46.223882 [Byte1]: 58
7863 09:28:46.228180
7864 09:28:46.228634 Set Vref, RX VrefLevel [Byte0]: 59
7865 09:28:46.231299 [Byte1]: 59
7866 09:28:46.235584
7867 09:28:46.236001 Set Vref, RX VrefLevel [Byte0]: 60
7868 09:28:46.239168 [Byte1]: 60
7869 09:28:46.243201
7870 09:28:46.243620 Set Vref, RX VrefLevel [Byte0]: 61
7871 09:28:46.246633 [Byte1]: 61
7872 09:28:46.251127
7873 09:28:46.251680 Set Vref, RX VrefLevel [Byte0]: 62
7874 09:28:46.254172 [Byte1]: 62
7875 09:28:46.258555
7876 09:28:46.258976 Set Vref, RX VrefLevel [Byte0]: 63
7877 09:28:46.261731 [Byte1]: 63
7878 09:28:46.266407
7879 09:28:46.266923 Set Vref, RX VrefLevel [Byte0]: 64
7880 09:28:46.269405 [Byte1]: 64
7881 09:28:46.273707
7882 09:28:46.274212 Set Vref, RX VrefLevel [Byte0]: 65
7883 09:28:46.277102 [Byte1]: 65
7884 09:28:46.281369
7885 09:28:46.281910 Set Vref, RX VrefLevel [Byte0]: 66
7886 09:28:46.284401 [Byte1]: 66
7887 09:28:46.289048
7888 09:28:46.289561 Set Vref, RX VrefLevel [Byte0]: 67
7889 09:28:46.292050 [Byte1]: 67
7890 09:28:46.296632
7891 09:28:46.297166 Set Vref, RX VrefLevel [Byte0]: 68
7892 09:28:46.300168 [Byte1]: 68
7893 09:28:46.304599
7894 09:28:46.305130 Set Vref, RX VrefLevel [Byte0]: 69
7895 09:28:46.307456 [Byte1]: 69
7896 09:28:46.311936
7897 09:28:46.312468 Set Vref, RX VrefLevel [Byte0]: 70
7898 09:28:46.314628 [Byte1]: 70
7899 09:28:46.319386
7900 09:28:46.319913 Set Vref, RX VrefLevel [Byte0]: 71
7901 09:28:46.322886 [Byte1]: 71
7902 09:28:46.327016
7903 09:28:46.327563 Set Vref, RX VrefLevel [Byte0]: 72
7904 09:28:46.330006 [Byte1]: 72
7905 09:28:46.334352
7906 09:28:46.334774 Set Vref, RX VrefLevel [Byte0]: 73
7907 09:28:46.337279 [Byte1]: 73
7908 09:28:46.341877
7909 09:28:46.342322 Set Vref, RX VrefLevel [Byte0]: 74
7910 09:28:46.345028 [Byte1]: 74
7911 09:28:46.349424
7912 09:28:46.349846 Set Vref, RX VrefLevel [Byte0]: 75
7913 09:28:46.352795 [Byte1]: 75
7914 09:28:46.357005
7915 09:28:46.357587 Set Vref, RX VrefLevel [Byte0]: 76
7916 09:28:46.360084 [Byte1]: 76
7917 09:28:46.364517
7918 09:28:46.364979 Set Vref, RX VrefLevel [Byte0]: 77
7919 09:28:46.367730 [Byte1]: 77
7920 09:28:46.372293
7921 09:28:46.372864 Set Vref, RX VrefLevel [Byte0]: 78
7922 09:28:46.375663 [Byte1]: 78
7923 09:28:46.380072
7924 09:28:46.380643 Final RX Vref Byte 0 = 63 to rank0
7925 09:28:46.383509 Final RX Vref Byte 1 = 61 to rank0
7926 09:28:46.386357 Final RX Vref Byte 0 = 63 to rank1
7927 09:28:46.389837 Final RX Vref Byte 1 = 61 to rank1==
7928 09:28:46.393066 Dram Type= 6, Freq= 0, CH_0, rank 0
7929 09:28:46.400329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7930 09:28:46.400913 ==
7931 09:28:46.401266 DQS Delay:
7932 09:28:46.401587 DQS0 = 0, DQS1 = 0
7933 09:28:46.403522 DQM Delay:
7934 09:28:46.404043 DQM0 = 134, DQM1 = 126
7935 09:28:46.406639 DQ Delay:
7936 09:28:46.409990 DQ0 =132, DQ1 =134, DQ2 =130, DQ3 =132
7937 09:28:46.412788 DQ4 =138, DQ5 =124, DQ6 =144, DQ7 =142
7938 09:28:46.417009 DQ8 =116, DQ9 =112, DQ10 =128, DQ11 =120
7939 09:28:46.419715 DQ12 =130, DQ13 =130, DQ14 =138, DQ15 =134
7940 09:28:46.420172
7941 09:28:46.420526
7942 09:28:46.420882
7943 09:28:46.422844 [DramC_TX_OE_Calibration] TA2
7944 09:28:46.426148 Original DQ_B0 (3 6) =30, OEN = 27
7945 09:28:46.429597 Original DQ_B1 (3 6) =30, OEN = 27
7946 09:28:46.432891 24, 0x0, End_B0=24 End_B1=24
7947 09:28:46.433426 25, 0x0, End_B0=25 End_B1=25
7948 09:28:46.436179 26, 0x0, End_B0=26 End_B1=26
7949 09:28:46.439483 27, 0x0, End_B0=27 End_B1=27
7950 09:28:46.442708 28, 0x0, End_B0=28 End_B1=28
7951 09:28:46.443141 29, 0x0, End_B0=29 End_B1=29
7952 09:28:46.446592 30, 0x0, End_B0=30 End_B1=30
7953 09:28:46.449348 31, 0x4141, End_B0=30 End_B1=30
7954 09:28:46.452770 Byte0 end_step=30 best_step=27
7955 09:28:46.456737 Byte1 end_step=30 best_step=27
7956 09:28:46.459982 Byte0 TX OE(2T, 0.5T) = (3, 3)
7957 09:28:46.460521 Byte1 TX OE(2T, 0.5T) = (3, 3)
7958 09:28:46.462902
7959 09:28:46.463328
7960 09:28:46.469496 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7961 09:28:46.473054 CH0 RK0: MR19=303, MR18=1D1B
7962 09:28:46.479231 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
7963 09:28:46.479746
7964 09:28:46.482908 ----->DramcWriteLeveling(PI) begin...
7965 09:28:46.483346 ==
7966 09:28:46.486183 Dram Type= 6, Freq= 0, CH_0, rank 1
7967 09:28:46.489529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 09:28:46.490059 ==
7969 09:28:46.492869 Write leveling (Byte 0): 39 => 39
7970 09:28:46.496227 Write leveling (Byte 1): 28 => 28
7971 09:28:46.499499 DramcWriteLeveling(PI) end<-----
7972 09:28:46.500024
7973 09:28:46.500372 ==
7974 09:28:46.502841 Dram Type= 6, Freq= 0, CH_0, rank 1
7975 09:28:46.505904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7976 09:28:46.506439 ==
7977 09:28:46.509101 [Gating] SW mode calibration
7978 09:28:46.516149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7979 09:28:46.522708 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7980 09:28:46.525938 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7981 09:28:46.529111 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 09:28:46.536149 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 09:28:46.539085 1 4 12 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
7984 09:28:46.542437 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7985 09:28:46.549594 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 09:28:46.552769 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7987 09:28:46.555684 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7988 09:28:46.562072 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7989 09:28:46.566234 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7990 09:28:46.569259 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7991 09:28:46.576113 1 5 12 | B1->B0 | 3434 2727 | 0 0 | (0 1) (1 0)
7992 09:28:46.579374 1 5 16 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7993 09:28:46.582308 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 09:28:46.589115 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 09:28:46.592421 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 09:28:46.596118 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 09:28:46.602783 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 09:28:46.606118 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7999 09:28:46.609436 1 6 12 | B1->B0 | 2a2a 4343 | 1 0 | (1 1) (0 0)
8000 09:28:46.615391 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 09:28:46.618620 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 09:28:46.622395 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 09:28:46.625711 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 09:28:46.632146 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 09:28:46.635481 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 09:28:46.638628 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8007 09:28:46.645463 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8008 09:28:46.648676 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8009 09:28:46.652348 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 09:28:46.658674 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 09:28:46.662271 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 09:28:46.665421 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 09:28:46.671890 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 09:28:46.675168 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 09:28:46.678986 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 09:28:46.685145 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 09:28:46.688337 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 09:28:46.691964 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 09:28:46.698450 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 09:28:46.701745 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 09:28:46.705064 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 09:28:46.711606 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8023 09:28:46.714921 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8024 09:28:46.718242 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8025 09:28:46.721415 Total UI for P1: 0, mck2ui 16
8026 09:28:46.724537 best dqsien dly found for B0: ( 1, 9, 10)
8027 09:28:46.731498 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 09:28:46.731592 Total UI for P1: 0, mck2ui 16
8029 09:28:46.734840 best dqsien dly found for B1: ( 1, 9, 14)
8030 09:28:46.741367 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8031 09:28:46.744510 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8032 09:28:46.744644
8033 09:28:46.747849 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8034 09:28:46.751396 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8035 09:28:46.754679 [Gating] SW calibration Done
8036 09:28:46.754776 ==
8037 09:28:46.757786 Dram Type= 6, Freq= 0, CH_0, rank 1
8038 09:28:46.760951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8039 09:28:46.761041 ==
8040 09:28:46.764812 RX Vref Scan: 0
8041 09:28:46.764898
8042 09:28:46.764966 RX Vref 0 -> 0, step: 1
8043 09:28:46.765028
8044 09:28:46.767899 RX Delay 0 -> 252, step: 8
8045 09:28:46.771352 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8046 09:28:46.777799 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8047 09:28:46.781760 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8048 09:28:46.784790 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8049 09:28:46.787919 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8050 09:28:46.791385 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8051 09:28:46.797805 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8052 09:28:46.801587 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8053 09:28:46.804764 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8054 09:28:46.807996 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8055 09:28:46.811352 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8056 09:28:46.814728 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8057 09:28:46.821328 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8058 09:28:46.824958 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8059 09:28:46.828019 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8060 09:28:46.831127 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8061 09:28:46.831345 ==
8062 09:28:46.834749 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 09:28:46.841512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 09:28:46.841814 ==
8065 09:28:46.842015 DQS Delay:
8066 09:28:46.844324 DQS0 = 0, DQS1 = 0
8067 09:28:46.844589 DQM Delay:
8068 09:28:46.847689 DQM0 = 135, DQM1 = 126
8069 09:28:46.847994 DQ Delay:
8070 09:28:46.851132 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8071 09:28:46.854786 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8072 09:28:46.858026 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8073 09:28:46.861450 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8074 09:28:46.861879
8075 09:28:46.862223
8076 09:28:46.862585 ==
8077 09:28:46.864854 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 09:28:46.871423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 09:28:46.871967 ==
8080 09:28:46.872313
8081 09:28:46.872670
8082 09:28:46.872985 TX Vref Scan disable
8083 09:28:46.874832 == TX Byte 0 ==
8084 09:28:46.878198 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8085 09:28:46.884765 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8086 09:28:46.885193 == TX Byte 1 ==
8087 09:28:46.887979 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8088 09:28:46.894629 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8089 09:28:46.895071 ==
8090 09:28:46.898197 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 09:28:46.901310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 09:28:46.901733 ==
8093 09:28:46.914922
8094 09:28:46.918300 TX Vref early break, caculate TX vref
8095 09:28:46.921592 TX Vref=16, minBit 8, minWin=22, winSum=391
8096 09:28:46.924725 TX Vref=18, minBit 0, minWin=24, winSum=396
8097 09:28:46.928658 TX Vref=20, minBit 8, minWin=24, winSum=402
8098 09:28:46.931663 TX Vref=22, minBit 8, minWin=24, winSum=412
8099 09:28:46.934907 TX Vref=24, minBit 0, minWin=26, winSum=427
8100 09:28:46.941636 TX Vref=26, minBit 8, minWin=25, winSum=434
8101 09:28:46.944973 TX Vref=28, minBit 8, minWin=25, winSum=430
8102 09:28:46.948236 TX Vref=30, minBit 0, minWin=26, winSum=426
8103 09:28:46.951669 TX Vref=32, minBit 8, minWin=25, winSum=415
8104 09:28:46.954731 TX Vref=34, minBit 2, minWin=25, winSum=410
8105 09:28:46.961885 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 24
8106 09:28:46.962319
8107 09:28:46.964920 Final TX Range 0 Vref 24
8108 09:28:46.965351
8109 09:28:46.965692 ==
8110 09:28:46.968467 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 09:28:46.971883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 09:28:46.972407 ==
8113 09:28:46.972814
8114 09:28:46.973138
8115 09:28:46.974685 TX Vref Scan disable
8116 09:28:46.981169 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8117 09:28:46.981666 == TX Byte 0 ==
8118 09:28:46.985292 u2DelayCellOfst[0]=13 cells (4 PI)
8119 09:28:46.987702 u2DelayCellOfst[1]=16 cells (5 PI)
8120 09:28:46.991201 u2DelayCellOfst[2]=10 cells (3 PI)
8121 09:28:46.995152 u2DelayCellOfst[3]=10 cells (3 PI)
8122 09:28:46.998027 u2DelayCellOfst[4]=6 cells (2 PI)
8123 09:28:47.001308 u2DelayCellOfst[5]=0 cells (0 PI)
8124 09:28:47.004589 u2DelayCellOfst[6]=16 cells (5 PI)
8125 09:28:47.007704 u2DelayCellOfst[7]=16 cells (5 PI)
8126 09:28:47.011264 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8127 09:28:47.014291 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8128 09:28:47.017905 == TX Byte 1 ==
8129 09:28:47.020930 u2DelayCellOfst[8]=3 cells (1 PI)
8130 09:28:47.021358 u2DelayCellOfst[9]=0 cells (0 PI)
8131 09:28:47.025075 u2DelayCellOfst[10]=6 cells (2 PI)
8132 09:28:47.028011 u2DelayCellOfst[11]=3 cells (1 PI)
8133 09:28:47.031091 u2DelayCellOfst[12]=13 cells (4 PI)
8134 09:28:47.034484 u2DelayCellOfst[13]=10 cells (3 PI)
8135 09:28:47.037561 u2DelayCellOfst[14]=13 cells (4 PI)
8136 09:28:47.040780 u2DelayCellOfst[15]=10 cells (3 PI)
8137 09:28:47.044273 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8138 09:28:47.050924 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8139 09:28:47.051446 DramC Write-DBI on
8140 09:28:47.051785 ==
8141 09:28:47.054368 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 09:28:47.061286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 09:28:47.061814 ==
8144 09:28:47.062161
8145 09:28:47.062479
8146 09:28:47.062786 TX Vref Scan disable
8147 09:28:47.064717 == TX Byte 0 ==
8148 09:28:47.068180 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8149 09:28:47.071147 == TX Byte 1 ==
8150 09:28:47.074472 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8151 09:28:47.077764 DramC Write-DBI off
8152 09:28:47.078208
8153 09:28:47.078549 [DATLAT]
8154 09:28:47.078863 Freq=1600, CH0 RK1
8155 09:28:47.079171
8156 09:28:47.081274 DATLAT Default: 0xf
8157 09:28:47.081699 0, 0xFFFF, sum = 0
8158 09:28:47.084328 1, 0xFFFF, sum = 0
8159 09:28:47.084780 2, 0xFFFF, sum = 0
8160 09:28:47.088523 3, 0xFFFF, sum = 0
8161 09:28:47.091577 4, 0xFFFF, sum = 0
8162 09:28:47.092104 5, 0xFFFF, sum = 0
8163 09:28:47.094639 6, 0xFFFF, sum = 0
8164 09:28:47.095079 7, 0xFFFF, sum = 0
8165 09:28:47.097746 8, 0xFFFF, sum = 0
8166 09:28:47.098178 9, 0xFFFF, sum = 0
8167 09:28:47.100987 10, 0xFFFF, sum = 0
8168 09:28:47.101420 11, 0xFFFF, sum = 0
8169 09:28:47.104806 12, 0xFFFF, sum = 0
8170 09:28:47.105257 13, 0xFFFF, sum = 0
8171 09:28:47.108074 14, 0x0, sum = 1
8172 09:28:47.108506 15, 0x0, sum = 2
8173 09:28:47.111174 16, 0x0, sum = 3
8174 09:28:47.111606 17, 0x0, sum = 4
8175 09:28:47.114318 best_step = 15
8176 09:28:47.114740
8177 09:28:47.115078 ==
8178 09:28:47.117632 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 09:28:47.120977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 09:28:47.121406 ==
8181 09:28:47.121796 RX Vref Scan: 0
8182 09:28:47.124895
8183 09:28:47.125317 RX Vref 0 -> 0, step: 1
8184 09:28:47.125657
8185 09:28:47.128141 RX Delay 19 -> 252, step: 4
8186 09:28:47.131381 iDelay=191, Bit 0, Center 130 (79 ~ 182) 104
8187 09:28:47.137849 iDelay=191, Bit 1, Center 134 (83 ~ 186) 104
8188 09:28:47.140945 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8189 09:28:47.144468 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8190 09:28:47.148306 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8191 09:28:47.151585 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8192 09:28:47.154810 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8193 09:28:47.161421 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8194 09:28:47.164336 iDelay=191, Bit 8, Center 118 (71 ~ 166) 96
8195 09:28:47.168289 iDelay=191, Bit 9, Center 112 (63 ~ 162) 100
8196 09:28:47.171229 iDelay=191, Bit 10, Center 128 (83 ~ 174) 92
8197 09:28:47.174668 iDelay=191, Bit 11, Center 122 (75 ~ 170) 96
8198 09:28:47.181380 iDelay=191, Bit 12, Center 128 (79 ~ 178) 100
8199 09:28:47.184783 iDelay=191, Bit 13, Center 130 (83 ~ 178) 96
8200 09:28:47.187504 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8201 09:28:47.190818 iDelay=191, Bit 15, Center 132 (83 ~ 182) 100
8202 09:28:47.191247 ==
8203 09:28:47.194693 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 09:28:47.201072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 09:28:47.201599 ==
8206 09:28:47.201945 DQS Delay:
8207 09:28:47.204160 DQS0 = 0, DQS1 = 0
8208 09:28:47.204730 DQM Delay:
8209 09:28:47.205081 DQM0 = 132, DQM1 = 125
8210 09:28:47.207375 DQ Delay:
8211 09:28:47.210669 DQ0 =130, DQ1 =134, DQ2 =130, DQ3 =130
8212 09:28:47.214299 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
8213 09:28:47.217527 DQ8 =118, DQ9 =112, DQ10 =128, DQ11 =122
8214 09:28:47.220919 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =132
8215 09:28:47.221453
8216 09:28:47.221797
8217 09:28:47.222111
8218 09:28:47.224975 [DramC_TX_OE_Calibration] TA2
8219 09:28:47.227701 Original DQ_B0 (3 6) =30, OEN = 27
8220 09:28:47.230831 Original DQ_B1 (3 6) =30, OEN = 27
8221 09:28:47.234674 24, 0x0, End_B0=24 End_B1=24
8222 09:28:47.235106 25, 0x0, End_B0=25 End_B1=25
8223 09:28:47.237904 26, 0x0, End_B0=26 End_B1=26
8224 09:28:47.241044 27, 0x0, End_B0=27 End_B1=27
8225 09:28:47.244639 28, 0x0, End_B0=28 End_B1=28
8226 09:28:47.245165 29, 0x0, End_B0=29 End_B1=29
8227 09:28:47.248092 30, 0x0, End_B0=30 End_B1=30
8228 09:28:47.251398 31, 0x4141, End_B0=30 End_B1=30
8229 09:28:47.254756 Byte0 end_step=30 best_step=27
8230 09:28:47.257664 Byte1 end_step=30 best_step=27
8231 09:28:47.260952 Byte0 TX OE(2T, 0.5T) = (3, 3)
8232 09:28:47.261525 Byte1 TX OE(2T, 0.5T) = (3, 3)
8233 09:28:47.264170
8234 09:28:47.264616
8235 09:28:47.271384 [DQSOSCAuto] RK1, (LSB)MR18= 0x2310, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8236 09:28:47.274843 CH0 RK1: MR19=303, MR18=2310
8237 09:28:47.281232 CH0_RK1: MR19=0x303, MR18=0x2310, DQSOSC=392, MR23=63, INC=24, DEC=16
8238 09:28:47.284437 [RxdqsGatingPostProcess] freq 1600
8239 09:28:47.287903 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8240 09:28:47.291564 best DQS0 dly(2T, 0.5T) = (1, 1)
8241 09:28:47.294410 best DQS1 dly(2T, 0.5T) = (1, 1)
8242 09:28:47.297772 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8243 09:28:47.300741 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8244 09:28:47.304114 best DQS0 dly(2T, 0.5T) = (1, 1)
8245 09:28:47.307302 best DQS1 dly(2T, 0.5T) = (1, 1)
8246 09:28:47.311158 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8247 09:28:47.314487 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8248 09:28:47.317743 Pre-setting of DQS Precalculation
8249 09:28:47.321004 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8250 09:28:47.321428 ==
8251 09:28:47.324385 Dram Type= 6, Freq= 0, CH_1, rank 0
8252 09:28:47.327736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8253 09:28:47.328261 ==
8254 09:28:47.334154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8255 09:28:47.337385 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8256 09:28:47.344145 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8257 09:28:47.347698 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8258 09:28:47.357443 [CA 0] Center 41 (11~71) winsize 61
8259 09:28:47.360620 [CA 1] Center 41 (11~71) winsize 61
8260 09:28:47.363961 [CA 2] Center 37 (8~67) winsize 60
8261 09:28:47.367575 [CA 3] Center 36 (6~66) winsize 61
8262 09:28:47.370827 [CA 4] Center 36 (6~66) winsize 61
8263 09:28:47.374122 [CA 5] Center 36 (6~66) winsize 61
8264 09:28:47.374646
8265 09:28:47.377148 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8266 09:28:47.377570
8267 09:28:47.380591 [CATrainingPosCal] consider 1 rank data
8268 09:28:47.384296 u2DelayCellTimex100 = 290/100 ps
8269 09:28:47.387380 CA0 delay=41 (11~71),Diff = 5 PI (16 cell)
8270 09:28:47.394212 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8271 09:28:47.397390 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8272 09:28:47.400839 CA3 delay=36 (6~66),Diff = 0 PI (0 cell)
8273 09:28:47.404165 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
8274 09:28:47.407398 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8275 09:28:47.407820
8276 09:28:47.410688 CA PerBit enable=1, Macro0, CA PI delay=36
8277 09:28:47.411131
8278 09:28:47.413766 [CBTSetCACLKResult] CA Dly = 36
8279 09:28:47.414188 CS Dly: 9 (0~40)
8280 09:28:47.420999 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8281 09:28:47.424233 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8282 09:28:47.424792 ==
8283 09:28:47.427668 Dram Type= 6, Freq= 0, CH_1, rank 1
8284 09:28:47.430718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 09:28:47.431146 ==
8286 09:28:47.437388 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8287 09:28:47.440745 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8288 09:28:47.447802 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8289 09:28:47.450280 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8290 09:28:47.460844 [CA 0] Center 41 (12~71) winsize 60
8291 09:28:47.463825 [CA 1] Center 41 (12~71) winsize 60
8292 09:28:47.467441 [CA 2] Center 38 (9~68) winsize 60
8293 09:28:47.469827 [CA 3] Center 37 (8~67) winsize 60
8294 09:28:47.473622 [CA 4] Center 37 (8~67) winsize 60
8295 09:28:47.477194 [CA 5] Center 37 (7~67) winsize 61
8296 09:28:47.477606
8297 09:28:47.479807 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8298 09:28:47.480215
8299 09:28:47.483106 [CATrainingPosCal] consider 2 rank data
8300 09:28:47.486734 u2DelayCellTimex100 = 290/100 ps
8301 09:28:47.493591 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8302 09:28:47.496649 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8303 09:28:47.500080 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8304 09:28:47.503765 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8305 09:28:47.506916 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8306 09:28:47.509925 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8307 09:28:47.510341
8308 09:28:47.512973 CA PerBit enable=1, Macro0, CA PI delay=36
8309 09:28:47.513384
8310 09:28:47.516689 [CBTSetCACLKResult] CA Dly = 36
8311 09:28:47.520239 CS Dly: 10 (0~42)
8312 09:28:47.523265 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8313 09:28:47.526537 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8314 09:28:47.526948
8315 09:28:47.529808 ----->DramcWriteLeveling(PI) begin...
8316 09:28:47.530225 ==
8317 09:28:47.533015 Dram Type= 6, Freq= 0, CH_1, rank 0
8318 09:28:47.539518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 09:28:47.539930 ==
8320 09:28:47.542990 Write leveling (Byte 0): 24 => 24
8321 09:28:47.543550 Write leveling (Byte 1): 28 => 28
8322 09:28:47.546029 DramcWriteLeveling(PI) end<-----
8323 09:28:47.546438
8324 09:28:47.546764 ==
8325 09:28:47.549777 Dram Type= 6, Freq= 0, CH_1, rank 0
8326 09:28:47.556312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 09:28:47.556774 ==
8328 09:28:47.559997 [Gating] SW mode calibration
8329 09:28:47.566196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8330 09:28:47.569906 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8331 09:28:47.576363 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 09:28:47.580133 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 09:28:47.583396 1 4 8 | B1->B0 | 2929 2c2c | 0 0 | (0 0) (0 0)
8334 09:28:47.589987 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 09:28:47.592879 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 09:28:47.596689 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 09:28:47.602888 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 09:28:47.606048 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 09:28:47.609617 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 09:28:47.616257 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8341 09:28:47.619486 1 5 8 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (1 0)
8342 09:28:47.622799 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8343 09:28:47.629567 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 09:28:47.632694 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 09:28:47.636341 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 09:28:47.639196 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 09:28:47.645649 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 09:28:47.648974 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8349 09:28:47.652265 1 6 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8350 09:28:47.659224 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 09:28:47.662605 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 09:28:47.665651 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 09:28:47.672718 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 09:28:47.676272 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 09:28:47.679327 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 09:28:47.685695 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8357 09:28:47.689205 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8358 09:28:47.692468 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8359 09:28:47.698760 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 09:28:47.702593 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 09:28:47.705548 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 09:28:47.712348 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 09:28:47.715540 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 09:28:47.719023 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 09:28:47.725599 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 09:28:47.728917 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 09:28:47.732058 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 09:28:47.738578 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 09:28:47.741708 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 09:28:47.745551 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 09:28:47.752135 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 09:28:47.755504 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 09:28:47.759099 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8374 09:28:47.765303 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8375 09:28:47.765727 Total UI for P1: 0, mck2ui 16
8376 09:28:47.772024 best dqsien dly found for B0: ( 1, 9, 8)
8377 09:28:47.775486 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 09:28:47.778721 Total UI for P1: 0, mck2ui 16
8379 09:28:47.781793 best dqsien dly found for B1: ( 1, 9, 10)
8380 09:28:47.785071 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8381 09:28:47.788732 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8382 09:28:47.789153
8383 09:28:47.792331 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8384 09:28:47.795425 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8385 09:28:47.798613 [Gating] SW calibration Done
8386 09:28:47.799035 ==
8387 09:28:47.802104 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 09:28:47.805311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 09:28:47.805737 ==
8390 09:28:47.808695 RX Vref Scan: 0
8391 09:28:47.809289
8392 09:28:47.811795 RX Vref 0 -> 0, step: 1
8393 09:28:47.812216
8394 09:28:47.812594 RX Delay 0 -> 252, step: 8
8395 09:28:47.818760 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8396 09:28:47.821562 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8397 09:28:47.825178 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8398 09:28:47.828776 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8399 09:28:47.831662 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8400 09:28:47.835857 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8401 09:28:47.842450 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8402 09:28:47.844909 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8403 09:28:47.848804 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8404 09:28:47.852076 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8405 09:28:47.855037 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8406 09:28:47.861567 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8407 09:28:47.865365 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8408 09:28:47.868769 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8409 09:28:47.871972 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8410 09:28:47.875477 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8411 09:28:47.878659 ==
8412 09:28:47.881730 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 09:28:47.885362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 09:28:47.885939 ==
8415 09:28:47.886295 DQS Delay:
8416 09:28:47.888302 DQS0 = 0, DQS1 = 0
8417 09:28:47.888776 DQM Delay:
8418 09:28:47.891949 DQM0 = 138, DQM1 = 129
8419 09:28:47.892470 DQ Delay:
8420 09:28:47.895382 DQ0 =139, DQ1 =135, DQ2 =127, DQ3 =139
8421 09:28:47.898385 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8422 09:28:47.901414 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8423 09:28:47.905321 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8424 09:28:47.905847
8425 09:28:47.906190
8426 09:28:47.907807 ==
8427 09:28:47.908238 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 09:28:47.914804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 09:28:47.915326 ==
8430 09:28:47.915740
8431 09:28:47.916070
8432 09:28:47.917994 TX Vref Scan disable
8433 09:28:47.918598 == TX Byte 0 ==
8434 09:28:47.921087 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8435 09:28:47.927697 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8436 09:28:47.928183 == TX Byte 1 ==
8437 09:28:47.931133 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8438 09:28:47.937944 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8439 09:28:47.938370 ==
8440 09:28:47.941156 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 09:28:47.944653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 09:28:47.945457 ==
8443 09:28:47.957814
8444 09:28:47.960820 TX Vref early break, caculate TX vref
8445 09:28:47.964162 TX Vref=16, minBit 10, minWin=21, winSum=368
8446 09:28:47.967660 TX Vref=18, minBit 10, minWin=21, winSum=379
8447 09:28:47.970853 TX Vref=20, minBit 10, minWin=22, winSum=380
8448 09:28:47.974144 TX Vref=22, minBit 10, minWin=23, winSum=399
8449 09:28:47.977278 TX Vref=24, minBit 8, minWin=24, winSum=407
8450 09:28:47.983811 TX Vref=26, minBit 10, minWin=24, winSum=411
8451 09:28:47.987102 TX Vref=28, minBit 10, minWin=24, winSum=418
8452 09:28:47.990751 TX Vref=30, minBit 9, minWin=24, winSum=417
8453 09:28:47.993887 TX Vref=32, minBit 13, minWin=23, winSum=404
8454 09:28:47.997172 TX Vref=34, minBit 10, minWin=23, winSum=394
8455 09:28:48.004140 [TxChooseVref] Worse bit 10, Min win 24, Win sum 418, Final Vref 28
8456 09:28:48.004733
8457 09:28:48.007319 Final TX Range 0 Vref 28
8458 09:28:48.007750
8459 09:28:48.008179 ==
8460 09:28:48.010644 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 09:28:48.013698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 09:28:48.014105 ==
8463 09:28:48.014520
8464 09:28:48.014915
8465 09:28:48.017444 TX Vref Scan disable
8466 09:28:48.023804 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8467 09:28:48.024236 == TX Byte 0 ==
8468 09:28:48.027157 u2DelayCellOfst[0]=13 cells (4 PI)
8469 09:28:48.030515 u2DelayCellOfst[1]=10 cells (3 PI)
8470 09:28:48.033738 u2DelayCellOfst[2]=0 cells (0 PI)
8471 09:28:48.037284 u2DelayCellOfst[3]=3 cells (1 PI)
8472 09:28:48.040338 u2DelayCellOfst[4]=6 cells (2 PI)
8473 09:28:48.043968 u2DelayCellOfst[5]=20 cells (6 PI)
8474 09:28:48.047183 u2DelayCellOfst[6]=16 cells (5 PI)
8475 09:28:48.050363 u2DelayCellOfst[7]=6 cells (2 PI)
8476 09:28:48.053674 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8477 09:28:48.057213 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8478 09:28:48.060925 == TX Byte 1 ==
8479 09:28:48.064101 u2DelayCellOfst[8]=0 cells (0 PI)
8480 09:28:48.064668 u2DelayCellOfst[9]=3 cells (1 PI)
8481 09:28:48.067194 u2DelayCellOfst[10]=13 cells (4 PI)
8482 09:28:48.070914 u2DelayCellOfst[11]=3 cells (1 PI)
8483 09:28:48.073975 u2DelayCellOfst[12]=16 cells (5 PI)
8484 09:28:48.077228 u2DelayCellOfst[13]=20 cells (6 PI)
8485 09:28:48.080719 u2DelayCellOfst[14]=20 cells (6 PI)
8486 09:28:48.083947 u2DelayCellOfst[15]=16 cells (5 PI)
8487 09:28:48.087004 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8488 09:28:48.094064 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8489 09:28:48.094593 DramC Write-DBI on
8490 09:28:48.095029 ==
8491 09:28:48.097205 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 09:28:48.100633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 09:28:48.103740 ==
8494 09:28:48.104174
8495 09:28:48.104641
8496 09:28:48.105050 TX Vref Scan disable
8497 09:28:48.107754 == TX Byte 0 ==
8498 09:28:48.110819 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8499 09:28:48.114118 == TX Byte 1 ==
8500 09:28:48.117343 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8501 09:28:48.120503 DramC Write-DBI off
8502 09:28:48.120976
8503 09:28:48.121406 [DATLAT]
8504 09:28:48.121925 Freq=1600, CH1 RK0
8505 09:28:48.122264
8506 09:28:48.124055 DATLAT Default: 0xf
8507 09:28:48.124491 0, 0xFFFF, sum = 0
8508 09:28:48.127139 1, 0xFFFF, sum = 0
8509 09:28:48.130838 2, 0xFFFF, sum = 0
8510 09:28:48.131395 3, 0xFFFF, sum = 0
8511 09:28:48.133666 4, 0xFFFF, sum = 0
8512 09:28:48.134105 5, 0xFFFF, sum = 0
8513 09:28:48.137392 6, 0xFFFF, sum = 0
8514 09:28:48.137829 7, 0xFFFF, sum = 0
8515 09:28:48.140460 8, 0xFFFF, sum = 0
8516 09:28:48.141065 9, 0xFFFF, sum = 0
8517 09:28:48.143646 10, 0xFFFF, sum = 0
8518 09:28:48.144072 11, 0xFFFF, sum = 0
8519 09:28:48.147290 12, 0xFFFF, sum = 0
8520 09:28:48.147750 13, 0xFFFF, sum = 0
8521 09:28:48.150611 14, 0x0, sum = 1
8522 09:28:48.151036 15, 0x0, sum = 2
8523 09:28:48.153893 16, 0x0, sum = 3
8524 09:28:48.154319 17, 0x0, sum = 4
8525 09:28:48.157003 best_step = 15
8526 09:28:48.157422
8527 09:28:48.157756 ==
8528 09:28:48.160669 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 09:28:48.164175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 09:28:48.164737 ==
8531 09:28:48.165080 RX Vref Scan: 1
8532 09:28:48.167291
8533 09:28:48.167745 Set Vref Range= 24 -> 127
8534 09:28:48.168082
8535 09:28:48.170629 RX Vref 24 -> 127, step: 1
8536 09:28:48.171050
8537 09:28:48.173873 RX Delay 19 -> 252, step: 4
8538 09:28:48.174293
8539 09:28:48.177217 Set Vref, RX VrefLevel [Byte0]: 24
8540 09:28:48.180459 [Byte1]: 24
8541 09:28:48.180903
8542 09:28:48.184170 Set Vref, RX VrefLevel [Byte0]: 25
8543 09:28:48.187246 [Byte1]: 25
8544 09:28:48.187723
8545 09:28:48.190695 Set Vref, RX VrefLevel [Byte0]: 26
8546 09:28:48.193566 [Byte1]: 26
8547 09:28:48.197745
8548 09:28:48.198279 Set Vref, RX VrefLevel [Byte0]: 27
8549 09:28:48.200910 [Byte1]: 27
8550 09:28:48.205178
8551 09:28:48.205616 Set Vref, RX VrefLevel [Byte0]: 28
8552 09:28:48.208510 [Byte1]: 28
8553 09:28:48.212673
8554 09:28:48.213108 Set Vref, RX VrefLevel [Byte0]: 29
8555 09:28:48.215996 [Byte1]: 29
8556 09:28:48.220647
8557 09:28:48.221490 Set Vref, RX VrefLevel [Byte0]: 30
8558 09:28:48.223604 [Byte1]: 30
8559 09:28:48.228278
8560 09:28:48.228838 Set Vref, RX VrefLevel [Byte0]: 31
8561 09:28:48.231312 [Byte1]: 31
8562 09:28:48.235664
8563 09:28:48.236091 Set Vref, RX VrefLevel [Byte0]: 32
8564 09:28:48.238512 [Byte1]: 32
8565 09:28:48.242904
8566 09:28:48.243333 Set Vref, RX VrefLevel [Byte0]: 33
8567 09:28:48.246628 [Byte1]: 33
8568 09:28:48.250825
8569 09:28:48.251263 Set Vref, RX VrefLevel [Byte0]: 34
8570 09:28:48.253830 [Byte1]: 34
8571 09:28:48.258517
8572 09:28:48.259045 Set Vref, RX VrefLevel [Byte0]: 35
8573 09:28:48.261672 [Byte1]: 35
8574 09:28:48.265957
8575 09:28:48.266638 Set Vref, RX VrefLevel [Byte0]: 36
8576 09:28:48.269038 [Byte1]: 36
8577 09:28:48.273563
8578 09:28:48.274109 Set Vref, RX VrefLevel [Byte0]: 37
8579 09:28:48.276762 [Byte1]: 37
8580 09:28:48.280974
8581 09:28:48.281526 Set Vref, RX VrefLevel [Byte0]: 38
8582 09:28:48.284027 [Byte1]: 38
8583 09:28:48.288734
8584 09:28:48.289255 Set Vref, RX VrefLevel [Byte0]: 39
8585 09:28:48.292150 [Byte1]: 39
8586 09:28:48.296401
8587 09:28:48.296986 Set Vref, RX VrefLevel [Byte0]: 40
8588 09:28:48.299667 [Byte1]: 40
8589 09:28:48.304082
8590 09:28:48.304626 Set Vref, RX VrefLevel [Byte0]: 41
8591 09:28:48.307403 [Byte1]: 41
8592 09:28:48.311493
8593 09:28:48.311917 Set Vref, RX VrefLevel [Byte0]: 42
8594 09:28:48.314992 [Byte1]: 42
8595 09:28:48.318885
8596 09:28:48.319416 Set Vref, RX VrefLevel [Byte0]: 43
8597 09:28:48.321751 [Byte1]: 43
8598 09:28:48.326005
8599 09:28:48.329468 Set Vref, RX VrefLevel [Byte0]: 44
8600 09:28:48.329895 [Byte1]: 44
8601 09:28:48.333925
8602 09:28:48.334473 Set Vref, RX VrefLevel [Byte0]: 45
8603 09:28:48.337463 [Byte1]: 45
8604 09:28:48.341818
8605 09:28:48.342415 Set Vref, RX VrefLevel [Byte0]: 46
8606 09:28:48.344662 [Byte1]: 46
8607 09:28:48.349146
8608 09:28:48.349569 Set Vref, RX VrefLevel [Byte0]: 47
8609 09:28:48.352585 [Byte1]: 47
8610 09:28:48.356729
8611 09:28:48.357149 Set Vref, RX VrefLevel [Byte0]: 48
8612 09:28:48.360167 [Byte1]: 48
8613 09:28:48.364610
8614 09:28:48.365157 Set Vref, RX VrefLevel [Byte0]: 49
8615 09:28:48.367484 [Byte1]: 49
8616 09:28:48.372185
8617 09:28:48.372746 Set Vref, RX VrefLevel [Byte0]: 50
8618 09:28:48.375447 [Byte1]: 50
8619 09:28:48.380050
8620 09:28:48.380626 Set Vref, RX VrefLevel [Byte0]: 51
8621 09:28:48.382890 [Byte1]: 51
8622 09:28:48.387182
8623 09:28:48.387641 Set Vref, RX VrefLevel [Byte0]: 52
8624 09:28:48.390393 [Byte1]: 52
8625 09:28:48.394389
8626 09:28:48.394932 Set Vref, RX VrefLevel [Byte0]: 53
8627 09:28:48.397651 [Byte1]: 53
8628 09:28:48.402343
8629 09:28:48.402868 Set Vref, RX VrefLevel [Byte0]: 54
8630 09:28:48.405215 [Byte1]: 54
8631 09:28:48.409532
8632 09:28:48.410024 Set Vref, RX VrefLevel [Byte0]: 55
8633 09:28:48.412726 [Byte1]: 55
8634 09:28:48.417168
8635 09:28:48.417593 Set Vref, RX VrefLevel [Byte0]: 56
8636 09:28:48.420790 [Byte1]: 56
8637 09:28:48.424921
8638 09:28:48.425342 Set Vref, RX VrefLevel [Byte0]: 57
8639 09:28:48.428317 [Byte1]: 57
8640 09:28:48.432604
8641 09:28:48.433130 Set Vref, RX VrefLevel [Byte0]: 58
8642 09:28:48.435691 [Byte1]: 58
8643 09:28:48.440054
8644 09:28:48.440501 Set Vref, RX VrefLevel [Byte0]: 59
8645 09:28:48.442978 [Byte1]: 59
8646 09:28:48.447324
8647 09:28:48.447752 Set Vref, RX VrefLevel [Byte0]: 60
8648 09:28:48.450855 [Byte1]: 60
8649 09:28:48.455471
8650 09:28:48.455996 Set Vref, RX VrefLevel [Byte0]: 61
8651 09:28:48.458681 [Byte1]: 61
8652 09:28:48.462971
8653 09:28:48.463505 Set Vref, RX VrefLevel [Byte0]: 62
8654 09:28:48.465901 [Byte1]: 62
8655 09:28:48.470420
8656 09:28:48.470949 Set Vref, RX VrefLevel [Byte0]: 63
8657 09:28:48.473442 [Byte1]: 63
8658 09:28:48.478147
8659 09:28:48.478673 Set Vref, RX VrefLevel [Byte0]: 64
8660 09:28:48.481143 [Byte1]: 64
8661 09:28:48.485676
8662 09:28:48.486197 Set Vref, RX VrefLevel [Byte0]: 65
8663 09:28:48.488817 [Byte1]: 65
8664 09:28:48.493096
8665 09:28:48.493618 Set Vref, RX VrefLevel [Byte0]: 66
8666 09:28:48.496124 [Byte1]: 66
8667 09:28:48.500754
8668 09:28:48.501277 Set Vref, RX VrefLevel [Byte0]: 67
8669 09:28:48.503740 [Byte1]: 67
8670 09:28:48.508501
8671 09:28:48.509074 Set Vref, RX VrefLevel [Byte0]: 68
8672 09:28:48.511445 [Byte1]: 68
8673 09:28:48.516266
8674 09:28:48.516830 Set Vref, RX VrefLevel [Byte0]: 69
8675 09:28:48.519328 [Byte1]: 69
8676 09:28:48.523054
8677 09:28:48.523479 Set Vref, RX VrefLevel [Byte0]: 70
8678 09:28:48.527149 [Byte1]: 70
8679 09:28:48.530590
8680 09:28:48.531015 Set Vref, RX VrefLevel [Byte0]: 71
8681 09:28:48.534287 [Byte1]: 71
8682 09:28:48.538488
8683 09:28:48.539010 Set Vref, RX VrefLevel [Byte0]: 72
8684 09:28:48.541892 [Byte1]: 72
8685 09:28:48.546151
8686 09:28:48.546670 Set Vref, RX VrefLevel [Byte0]: 73
8687 09:28:48.549018 [Byte1]: 73
8688 09:28:48.553390
8689 09:28:48.553810 Set Vref, RX VrefLevel [Byte0]: 74
8690 09:28:48.557072 [Byte1]: 74
8691 09:28:48.561258
8692 09:28:48.561693 Set Vref, RX VrefLevel [Byte0]: 75
8693 09:28:48.564456 [Byte1]: 75
8694 09:28:48.568932
8695 09:28:48.569467 Final RX Vref Byte 0 = 53 to rank0
8696 09:28:48.572353 Final RX Vref Byte 1 = 61 to rank0
8697 09:28:48.575959 Final RX Vref Byte 0 = 53 to rank1
8698 09:28:48.578797 Final RX Vref Byte 1 = 61 to rank1==
8699 09:28:48.581995 Dram Type= 6, Freq= 0, CH_1, rank 0
8700 09:28:48.588492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8701 09:28:48.589125 ==
8702 09:28:48.589494 DQS Delay:
8703 09:28:48.589835 DQS0 = 0, DQS1 = 0
8704 09:28:48.591948 DQM Delay:
8705 09:28:48.592473 DQM0 = 133, DQM1 = 129
8706 09:28:48.595075 DQ Delay:
8707 09:28:48.598533 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8708 09:28:48.602310 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8709 09:28:48.605222 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8710 09:28:48.608666 DQ12 =140, DQ13 =134, DQ14 =138, DQ15 =134
8711 09:28:48.609091
8712 09:28:48.609434
8713 09:28:48.609749
8714 09:28:48.611980 [DramC_TX_OE_Calibration] TA2
8715 09:28:48.614788 Original DQ_B0 (3 6) =30, OEN = 27
8716 09:28:48.618068 Original DQ_B1 (3 6) =30, OEN = 27
8717 09:28:48.621781 24, 0x0, End_B0=24 End_B1=24
8718 09:28:48.622226 25, 0x0, End_B0=25 End_B1=25
8719 09:28:48.625064 26, 0x0, End_B0=26 End_B1=26
8720 09:28:48.628353 27, 0x0, End_B0=27 End_B1=27
8721 09:28:48.631529 28, 0x0, End_B0=28 End_B1=28
8722 09:28:48.634770 29, 0x0, End_B0=29 End_B1=29
8723 09:28:48.635254 30, 0x0, End_B0=30 End_B1=30
8724 09:28:48.638526 31, 0x4141, End_B0=30 End_B1=30
8725 09:28:48.641807 Byte0 end_step=30 best_step=27
8726 09:28:48.645199 Byte1 end_step=30 best_step=27
8727 09:28:48.648159 Byte0 TX OE(2T, 0.5T) = (3, 3)
8728 09:28:48.651763 Byte1 TX OE(2T, 0.5T) = (3, 3)
8729 09:28:48.652323
8730 09:28:48.652701
8731 09:28:48.657971 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8732 09:28:48.661324 CH1 RK0: MR19=303, MR18=1826
8733 09:28:48.668150 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8734 09:28:48.668720
8735 09:28:48.671607 ----->DramcWriteLeveling(PI) begin...
8736 09:28:48.672226 ==
8737 09:28:48.674802 Dram Type= 6, Freq= 0, CH_1, rank 1
8738 09:28:48.678363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8739 09:28:48.678935 ==
8740 09:28:48.681539 Write leveling (Byte 0): 22 => 22
8741 09:28:48.684909 Write leveling (Byte 1): 29 => 29
8742 09:28:48.688033 DramcWriteLeveling(PI) end<-----
8743 09:28:48.688477
8744 09:28:48.688888 ==
8745 09:28:48.691656 Dram Type= 6, Freq= 0, CH_1, rank 1
8746 09:28:48.694644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8747 09:28:48.695131 ==
8748 09:28:48.698653 [Gating] SW mode calibration
8749 09:28:48.705101 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8750 09:28:48.711809 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8751 09:28:48.714565 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 09:28:48.718438 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 09:28:48.725183 1 4 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8754 09:28:48.728515 1 4 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (0 0)
8755 09:28:48.731698 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 09:28:48.738326 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 09:28:48.741617 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 09:28:48.745123 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 09:28:48.751546 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 09:28:48.754751 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8761 09:28:48.758402 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 0)
8762 09:28:48.765129 1 5 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8763 09:28:48.768076 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 09:28:48.771149 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 09:28:48.778196 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 09:28:48.781298 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 09:28:48.784978 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 09:28:48.791652 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 09:28:48.794626 1 6 8 | B1->B0 | 4545 2626 | 0 0 | (0 0) (0 0)
8770 09:28:48.798261 1 6 12 | B1->B0 | 4646 3a3a | 0 0 | (0 0) (0 0)
8771 09:28:48.805004 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 09:28:48.808276 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 09:28:48.811608 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 09:28:48.818060 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 09:28:48.821407 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 09:28:48.824238 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 09:28:48.831104 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8778 09:28:48.834639 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8779 09:28:48.838031 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 09:28:48.840895 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 09:28:48.847740 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 09:28:48.850790 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 09:28:48.853977 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 09:28:48.860535 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 09:28:48.864432 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 09:28:48.867274 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 09:28:48.874180 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 09:28:48.877213 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 09:28:48.881027 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 09:28:48.887739 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 09:28:48.890621 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 09:28:48.894127 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 09:28:48.900670 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8794 09:28:48.904257 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8795 09:28:48.907628 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 09:28:48.910801 Total UI for P1: 0, mck2ui 16
8797 09:28:48.913753 best dqsien dly found for B0: ( 1, 9, 10)
8798 09:28:48.917770 Total UI for P1: 0, mck2ui 16
8799 09:28:48.920439 best dqsien dly found for B1: ( 1, 9, 10)
8800 09:28:48.923936 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8801 09:28:48.927239 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8802 09:28:48.927689
8803 09:28:48.933613 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8804 09:28:48.936736 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8805 09:28:48.940618 [Gating] SW calibration Done
8806 09:28:48.941046 ==
8807 09:28:48.943397 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 09:28:48.946924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 09:28:48.947454 ==
8810 09:28:48.947806 RX Vref Scan: 0
8811 09:28:48.950521
8812 09:28:48.951141 RX Vref 0 -> 0, step: 1
8813 09:28:48.951533
8814 09:28:48.953687 RX Delay 0 -> 252, step: 8
8815 09:28:48.957024 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8816 09:28:48.960425 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8817 09:28:48.966864 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8818 09:28:48.970189 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8819 09:28:48.973381 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8820 09:28:48.976872 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8821 09:28:48.980340 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8822 09:28:48.983801 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8823 09:28:48.990053 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8824 09:28:48.993593 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8825 09:28:48.996822 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8826 09:28:49.000187 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8827 09:28:49.007260 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8828 09:28:49.010662 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8829 09:28:49.013212 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8830 09:28:49.016843 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8831 09:28:49.017380 ==
8832 09:28:49.020672 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 09:28:49.023895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 09:28:49.027289 ==
8835 09:28:49.027832 DQS Delay:
8836 09:28:49.028182 DQS0 = 0, DQS1 = 0
8837 09:28:49.030623 DQM Delay:
8838 09:28:49.031158 DQM0 = 137, DQM1 = 133
8839 09:28:49.033427 DQ Delay:
8840 09:28:49.036906 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8841 09:28:49.040082 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =139
8842 09:28:49.043526 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8843 09:28:49.047280 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8844 09:28:49.047818
8845 09:28:49.048166
8846 09:28:49.048489 ==
8847 09:28:49.050184 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 09:28:49.053238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 09:28:49.053715 ==
8850 09:28:49.054072
8851 09:28:49.056581
8852 09:28:49.057024 TX Vref Scan disable
8853 09:28:49.060177 == TX Byte 0 ==
8854 09:28:49.063254 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8855 09:28:49.066374 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8856 09:28:49.069674 == TX Byte 1 ==
8857 09:28:49.072894 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8858 09:28:49.076450 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8859 09:28:49.077064 ==
8860 09:28:49.080092 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 09:28:49.086246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 09:28:49.086774 ==
8863 09:28:49.099881
8864 09:28:49.103629 TX Vref early break, caculate TX vref
8865 09:28:49.106944 TX Vref=16, minBit 9, minWin=21, winSum=377
8866 09:28:49.110070 TX Vref=18, minBit 9, minWin=22, winSum=382
8867 09:28:49.113046 TX Vref=20, minBit 9, minWin=23, winSum=394
8868 09:28:49.116281 TX Vref=22, minBit 11, minWin=23, winSum=401
8869 09:28:49.119641 TX Vref=24, minBit 10, minWin=24, winSum=413
8870 09:28:49.126252 TX Vref=26, minBit 8, minWin=25, winSum=418
8871 09:28:49.129612 TX Vref=28, minBit 13, minWin=24, winSum=419
8872 09:28:49.132976 TX Vref=30, minBit 10, minWin=24, winSum=412
8873 09:28:49.136297 TX Vref=32, minBit 8, minWin=24, winSum=405
8874 09:28:49.139581 TX Vref=34, minBit 8, minWin=24, winSum=398
8875 09:28:49.146362 TX Vref=36, minBit 9, minWin=22, winSum=390
8876 09:28:49.149361 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 26
8877 09:28:49.149787
8878 09:28:49.152509 Final TX Range 0 Vref 26
8879 09:28:49.152976
8880 09:28:49.153317 ==
8881 09:28:49.155757 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 09:28:49.159844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 09:28:49.160440 ==
8884 09:28:49.162715
8885 09:28:49.163139
8886 09:28:49.163481 TX Vref Scan disable
8887 09:28:49.169157 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8888 09:28:49.169667 == TX Byte 0 ==
8889 09:28:49.172653 u2DelayCellOfst[0]=13 cells (4 PI)
8890 09:28:49.175770 u2DelayCellOfst[1]=10 cells (3 PI)
8891 09:28:49.179396 u2DelayCellOfst[2]=0 cells (0 PI)
8892 09:28:49.182337 u2DelayCellOfst[3]=3 cells (1 PI)
8893 09:28:49.185924 u2DelayCellOfst[4]=6 cells (2 PI)
8894 09:28:49.189041 u2DelayCellOfst[5]=16 cells (5 PI)
8895 09:28:49.192648 u2DelayCellOfst[6]=13 cells (4 PI)
8896 09:28:49.195956 u2DelayCellOfst[7]=3 cells (1 PI)
8897 09:28:49.199171 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8898 09:28:49.202951 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8899 09:28:49.206141 == TX Byte 1 ==
8900 09:28:49.208930 u2DelayCellOfst[8]=0 cells (0 PI)
8901 09:28:49.212813 u2DelayCellOfst[9]=6 cells (2 PI)
8902 09:28:49.215936 u2DelayCellOfst[10]=13 cells (4 PI)
8903 09:28:49.216363 u2DelayCellOfst[11]=6 cells (2 PI)
8904 09:28:49.219161 u2DelayCellOfst[12]=13 cells (4 PI)
8905 09:28:49.222379 u2DelayCellOfst[13]=16 cells (5 PI)
8906 09:28:49.226002 u2DelayCellOfst[14]=20 cells (6 PI)
8907 09:28:49.229425 u2DelayCellOfst[15]=20 cells (6 PI)
8908 09:28:49.235743 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8909 09:28:49.239411 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8910 09:28:49.239948 DramC Write-DBI on
8911 09:28:49.240298 ==
8912 09:28:49.242531 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 09:28:49.249029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 09:28:49.249568 ==
8915 09:28:49.249919
8916 09:28:49.250264
8917 09:28:49.250577 TX Vref Scan disable
8918 09:28:49.253195 == TX Byte 0 ==
8919 09:28:49.256822 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8920 09:28:49.260062 == TX Byte 1 ==
8921 09:28:49.263778 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8922 09:28:49.266952 DramC Write-DBI off
8923 09:28:49.267797
8924 09:28:49.268325 [DATLAT]
8925 09:28:49.268716 Freq=1600, CH1 RK1
8926 09:28:49.269049
8927 09:28:49.270055 DATLAT Default: 0xf
8928 09:28:49.270484 0, 0xFFFF, sum = 0
8929 09:28:49.273453 1, 0xFFFF, sum = 0
8930 09:28:49.273999 2, 0xFFFF, sum = 0
8931 09:28:49.276618 3, 0xFFFF, sum = 0
8932 09:28:49.280250 4, 0xFFFF, sum = 0
8933 09:28:49.281148 5, 0xFFFF, sum = 0
8934 09:28:49.283284 6, 0xFFFF, sum = 0
8935 09:28:49.284024 7, 0xFFFF, sum = 0
8936 09:28:49.286531 8, 0xFFFF, sum = 0
8937 09:28:49.287076 9, 0xFFFF, sum = 0
8938 09:28:49.289808 10, 0xFFFF, sum = 0
8939 09:28:49.290247 11, 0xFFFF, sum = 0
8940 09:28:49.293360 12, 0xFFFF, sum = 0
8941 09:28:49.294029 13, 0xFFFF, sum = 0
8942 09:28:49.296829 14, 0x0, sum = 1
8943 09:28:49.297265 15, 0x0, sum = 2
8944 09:28:49.300160 16, 0x0, sum = 3
8945 09:28:49.300635 17, 0x0, sum = 4
8946 09:28:49.303271 best_step = 15
8947 09:28:49.303700
8948 09:28:49.304040 ==
8949 09:28:49.306640 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 09:28:49.309712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 09:28:49.310146 ==
8952 09:28:49.310491 RX Vref Scan: 0
8953 09:28:49.310817
8954 09:28:49.313097 RX Vref 0 -> 0, step: 1
8955 09:28:49.313525
8956 09:28:49.316280 RX Delay 19 -> 252, step: 4
8957 09:28:49.319716 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
8958 09:28:49.327004 iDelay=195, Bit 1, Center 128 (83 ~ 174) 92
8959 09:28:49.329921 iDelay=195, Bit 2, Center 118 (71 ~ 166) 96
8960 09:28:49.333107 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8961 09:28:49.336744 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8962 09:28:49.339726 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8963 09:28:49.343026 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
8964 09:28:49.349701 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
8965 09:28:49.352819 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8966 09:28:49.356042 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8967 09:28:49.359988 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8968 09:28:49.362857 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8969 09:28:49.369343 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8970 09:28:49.372641 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8971 09:28:49.375977 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8972 09:28:49.380014 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8973 09:28:49.380620 ==
8974 09:28:49.383317 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 09:28:49.389384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 09:28:49.389827 ==
8977 09:28:49.390166 DQS Delay:
8978 09:28:49.390480 DQS0 = 0, DQS1 = 0
8979 09:28:49.392670 DQM Delay:
8980 09:28:49.393175 DQM0 = 133, DQM1 = 130
8981 09:28:49.395930 DQ Delay:
8982 09:28:49.399623 DQ0 =136, DQ1 =128, DQ2 =118, DQ3 =130
8983 09:28:49.402782 DQ4 =134, DQ5 =146, DQ6 =140, DQ7 =132
8984 09:28:49.405955 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
8985 09:28:49.409103 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8986 09:28:49.409533
8987 09:28:49.409872
8988 09:28:49.410186
8989 09:28:49.412957 [DramC_TX_OE_Calibration] TA2
8990 09:28:49.416186 Original DQ_B0 (3 6) =30, OEN = 27
8991 09:28:49.419493 Original DQ_B1 (3 6) =30, OEN = 27
8992 09:28:49.423292 24, 0x0, End_B0=24 End_B1=24
8993 09:28:49.423850 25, 0x0, End_B0=25 End_B1=25
8994 09:28:49.426173 26, 0x0, End_B0=26 End_B1=26
8995 09:28:49.429521 27, 0x0, End_B0=27 End_B1=27
8996 09:28:49.432699 28, 0x0, End_B0=28 End_B1=28
8997 09:28:49.433140 29, 0x0, End_B0=29 End_B1=29
8998 09:28:49.435922 30, 0x0, End_B0=30 End_B1=30
8999 09:28:49.439232 31, 0x4141, End_B0=30 End_B1=30
9000 09:28:49.442955 Byte0 end_step=30 best_step=27
9001 09:28:49.446235 Byte1 end_step=30 best_step=27
9002 09:28:49.449539 Byte0 TX OE(2T, 0.5T) = (3, 3)
9003 09:28:49.449966 Byte1 TX OE(2T, 0.5T) = (3, 3)
9004 09:28:49.452654
9005 09:28:49.453274
9006 09:28:49.458979 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9007 09:28:49.462471 CH1 RK1: MR19=303, MR18=1F09
9008 09:28:49.469475 CH1_RK1: MR19=0x303, MR18=0x1F09, DQSOSC=394, MR23=63, INC=23, DEC=15
9009 09:28:49.472640 [RxdqsGatingPostProcess] freq 1600
9010 09:28:49.475839 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9011 09:28:49.479042 best DQS0 dly(2T, 0.5T) = (1, 1)
9012 09:28:49.482833 best DQS1 dly(2T, 0.5T) = (1, 1)
9013 09:28:49.486092 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9014 09:28:49.489553 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9015 09:28:49.492851 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 09:28:49.496029 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 09:28:49.499150 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 09:28:49.502765 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 09:28:49.506088 Pre-setting of DQS Precalculation
9020 09:28:49.509616 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9021 09:28:49.515725 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9022 09:28:49.522973 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9023 09:28:49.523531
9024 09:28:49.523912
9025 09:28:49.525969 [Calibration Summary] 3200 Mbps
9026 09:28:49.529406 CH 0, Rank 0
9027 09:28:49.529940 SW Impedance : PASS
9028 09:28:49.532658 DUTY Scan : NO K
9029 09:28:49.536049 ZQ Calibration : PASS
9030 09:28:49.536622 Jitter Meter : NO K
9031 09:28:49.539380 CBT Training : PASS
9032 09:28:49.542510 Write leveling : PASS
9033 09:28:49.543045 RX DQS gating : PASS
9034 09:28:49.545669 RX DQ/DQS(RDDQC) : PASS
9035 09:28:49.549547 TX DQ/DQS : PASS
9036 09:28:49.549975 RX DATLAT : PASS
9037 09:28:49.552282 RX DQ/DQS(Engine): PASS
9038 09:28:49.552751 TX OE : PASS
9039 09:28:49.555630 All Pass.
9040 09:28:49.556163
9041 09:28:49.556722 CH 0, Rank 1
9042 09:28:49.559545 SW Impedance : PASS
9043 09:28:49.560077 DUTY Scan : NO K
9044 09:28:49.562766 ZQ Calibration : PASS
9045 09:28:49.565803 Jitter Meter : NO K
9046 09:28:49.566321 CBT Training : PASS
9047 09:28:49.568909 Write leveling : PASS
9048 09:28:49.572427 RX DQS gating : PASS
9049 09:28:49.573037 RX DQ/DQS(RDDQC) : PASS
9050 09:28:49.575699 TX DQ/DQS : PASS
9051 09:28:49.579155 RX DATLAT : PASS
9052 09:28:49.579682 RX DQ/DQS(Engine): PASS
9053 09:28:49.582175 TX OE : PASS
9054 09:28:49.582711 All Pass.
9055 09:28:49.583055
9056 09:28:49.585415 CH 1, Rank 0
9057 09:28:49.585939 SW Impedance : PASS
9058 09:28:49.589057 DUTY Scan : NO K
9059 09:28:49.592456 ZQ Calibration : PASS
9060 09:28:49.593022 Jitter Meter : NO K
9061 09:28:49.595634 CBT Training : PASS
9062 09:28:49.598669 Write leveling : PASS
9063 09:28:49.598823 RX DQS gating : PASS
9064 09:28:49.601499 RX DQ/DQS(RDDQC) : PASS
9065 09:28:49.604762 TX DQ/DQS : PASS
9066 09:28:49.604847 RX DATLAT : PASS
9067 09:28:49.607989 RX DQ/DQS(Engine): PASS
9068 09:28:49.611715 TX OE : PASS
9069 09:28:49.611801 All Pass.
9070 09:28:49.611868
9071 09:28:49.611928 CH 1, Rank 1
9072 09:28:49.614901 SW Impedance : PASS
9073 09:28:49.614985 DUTY Scan : NO K
9074 09:28:49.618217 ZQ Calibration : PASS
9075 09:28:49.621793 Jitter Meter : NO K
9076 09:28:49.621890 CBT Training : PASS
9077 09:28:49.625553 Write leveling : PASS
9078 09:28:49.628497 RX DQS gating : PASS
9079 09:28:49.628641 RX DQ/DQS(RDDQC) : PASS
9080 09:28:49.632117 TX DQ/DQS : PASS
9081 09:28:49.635481 RX DATLAT : PASS
9082 09:28:49.635934 RX DQ/DQS(Engine): PASS
9083 09:28:49.638695 TX OE : PASS
9084 09:28:49.639151 All Pass.
9085 09:28:49.639528
9086 09:28:49.641935 DramC Write-DBI on
9087 09:28:49.645147 PER_BANK_REFRESH: Hybrid Mode
9088 09:28:49.645581 TX_TRACKING: ON
9089 09:28:49.655368 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9090 09:28:49.662238 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9091 09:28:49.668476 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9092 09:28:49.671614 [FAST_K] Save calibration result to emmc
9093 09:28:49.675508 sync common calibartion params.
9094 09:28:49.678733 sync cbt_mode0:1, 1:1
9095 09:28:49.681991 dram_init: ddr_geometry: 2
9096 09:28:49.682415 dram_init: ddr_geometry: 2
9097 09:28:49.685240 dram_init: ddr_geometry: 2
9098 09:28:49.688603 0:dram_rank_size:100000000
9099 09:28:49.691878 1:dram_rank_size:100000000
9100 09:28:49.695676 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9101 09:28:49.698658 DFS_SHUFFLE_HW_MODE: ON
9102 09:28:49.702212 dramc_set_vcore_voltage set vcore to 725000
9103 09:28:49.705295 Read voltage for 1600, 0
9104 09:28:49.705829 Vio18 = 0
9105 09:28:49.706176 Vcore = 725000
9106 09:28:49.708809 Vdram = 0
9107 09:28:49.709337 Vddq = 0
9108 09:28:49.709683 Vmddr = 0
9109 09:28:49.712102 switch to 3200 Mbps bootup
9110 09:28:49.712675 [DramcRunTimeConfig]
9111 09:28:49.715489 PHYPLL
9112 09:28:49.716016 DPM_CONTROL_AFTERK: ON
9113 09:28:49.718739 PER_BANK_REFRESH: ON
9114 09:28:49.721838 REFRESH_OVERHEAD_REDUCTION: ON
9115 09:28:49.722265 CMD_PICG_NEW_MODE: OFF
9116 09:28:49.725434 XRTWTW_NEW_MODE: ON
9117 09:28:49.725899 XRTRTR_NEW_MODE: ON
9118 09:28:49.728946 TX_TRACKING: ON
9119 09:28:49.729484 RDSEL_TRACKING: OFF
9120 09:28:49.732210 DQS Precalculation for DVFS: ON
9121 09:28:49.735020 RX_TRACKING: OFF
9122 09:28:49.735573 HW_GATING DBG: ON
9123 09:28:49.738076 ZQCS_ENABLE_LP4: ON
9124 09:28:49.738654 RX_PICG_NEW_MODE: ON
9125 09:28:49.741524 TX_PICG_NEW_MODE: ON
9126 09:28:49.745524 ENABLE_RX_DCM_DPHY: ON
9127 09:28:49.746059 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9128 09:28:49.748959 DUMMY_READ_FOR_TRACKING: OFF
9129 09:28:49.751811 !!! SPM_CONTROL_AFTERK: OFF
9130 09:28:49.755065 !!! SPM could not control APHY
9131 09:28:49.755646 IMPEDANCE_TRACKING: ON
9132 09:28:49.758369 TEMP_SENSOR: ON
9133 09:28:49.758801 HW_SAVE_FOR_SR: OFF
9134 09:28:49.761763 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9135 09:28:49.764761 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9136 09:28:49.768332 Read ODT Tracking: ON
9137 09:28:49.771553 Refresh Rate DeBounce: ON
9138 09:28:49.772098 DFS_NO_QUEUE_FLUSH: ON
9139 09:28:49.775002 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9140 09:28:49.778308 ENABLE_DFS_RUNTIME_MRW: OFF
9141 09:28:49.781955 DDR_RESERVE_NEW_MODE: ON
9142 09:28:49.782602 MR_CBT_SWITCH_FREQ: ON
9143 09:28:49.784483 =========================
9144 09:28:49.804036 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9145 09:28:49.807279 dram_init: ddr_geometry: 2
9146 09:28:49.825718 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9147 09:28:49.828943 dram_init: dram init end (result: 0)
9148 09:28:49.835443 DRAM-K: Full calibration passed in 24499 msecs
9149 09:28:49.838428 MRC: failed to locate region type 0.
9150 09:28:49.838863 DRAM rank0 size:0x100000000,
9151 09:28:49.842169 DRAM rank1 size=0x100000000
9152 09:28:49.851764 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9153 09:28:49.858172 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9154 09:28:49.865383 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9155 09:28:49.875306 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9156 09:28:49.875869 DRAM rank0 size:0x100000000,
9157 09:28:49.878493 DRAM rank1 size=0x100000000
9158 09:28:49.879115 CBMEM:
9159 09:28:49.881572 IMD: root @ 0xfffff000 254 entries.
9160 09:28:49.885083 IMD: root @ 0xffffec00 62 entries.
9161 09:28:49.888739 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9162 09:28:49.895297 WARNING: RO_VPD is uninitialized or empty.
9163 09:28:49.898298 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9164 09:28:49.906177 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9165 09:28:49.918863 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9166 09:28:49.929888 BS: romstage times (exec / console): total (unknown) / 23994 ms
9167 09:28:49.930439
9168 09:28:49.930789
9169 09:28:49.939780 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9170 09:28:49.943320 ARM64: Exception handlers installed.
9171 09:28:49.946311 ARM64: Testing exception
9172 09:28:49.949833 ARM64: Done test exception
9173 09:28:49.950359 Enumerating buses...
9174 09:28:49.952885 Show all devs... Before device enumeration.
9175 09:28:49.956581 Root Device: enabled 1
9176 09:28:49.960101 CPU_CLUSTER: 0: enabled 1
9177 09:28:49.960663 CPU: 00: enabled 1
9178 09:28:49.963225 Compare with tree...
9179 09:28:49.963749 Root Device: enabled 1
9180 09:28:49.966518 CPU_CLUSTER: 0: enabled 1
9181 09:28:49.969428 CPU: 00: enabled 1
9182 09:28:49.969914 Root Device scanning...
9183 09:28:49.972751 scan_static_bus for Root Device
9184 09:28:49.976198 CPU_CLUSTER: 0 enabled
9185 09:28:49.979264 scan_static_bus for Root Device done
9186 09:28:49.983346 scan_bus: bus Root Device finished in 8 msecs
9187 09:28:49.983873 done
9188 09:28:49.989700 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9189 09:28:49.992779 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9190 09:28:49.999616 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9191 09:28:50.002900 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9192 09:28:50.006267 Allocating resources...
9193 09:28:50.009392 Reading resources...
9194 09:28:50.012759 Root Device read_resources bus 0 link: 0
9195 09:28:50.013280 DRAM rank0 size:0x100000000,
9196 09:28:50.016360 DRAM rank1 size=0x100000000
9197 09:28:50.020007 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9198 09:28:50.022845 CPU: 00 missing read_resources
9199 09:28:50.029070 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9200 09:28:50.032773 Root Device read_resources bus 0 link: 0 done
9201 09:28:50.033308 Done reading resources.
9202 09:28:50.039246 Show resources in subtree (Root Device)...After reading.
9203 09:28:50.042530 Root Device child on link 0 CPU_CLUSTER: 0
9204 09:28:50.045921 CPU_CLUSTER: 0 child on link 0 CPU: 00
9205 09:28:50.055949 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9206 09:28:50.056532 CPU: 00
9207 09:28:50.059188 Root Device assign_resources, bus 0 link: 0
9208 09:28:50.062689 CPU_CLUSTER: 0 missing set_resources
9209 09:28:50.068953 Root Device assign_resources, bus 0 link: 0 done
9210 09:28:50.069529 Done setting resources.
9211 09:28:50.075375 Show resources in subtree (Root Device)...After assigning values.
9212 09:28:50.078709 Root Device child on link 0 CPU_CLUSTER: 0
9213 09:28:50.082006 CPU_CLUSTER: 0 child on link 0 CPU: 00
9214 09:28:50.092208 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9215 09:28:50.092816 CPU: 00
9216 09:28:50.096016 Done allocating resources.
9217 09:28:50.098788 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9218 09:28:50.102681 Enabling resources...
9219 09:28:50.103215 done.
9220 09:28:50.109140 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9221 09:28:50.109688 Initializing devices...
9222 09:28:50.112200 Root Device init
9223 09:28:50.112682 init hardware done!
9224 09:28:50.115518 0x00000018: ctrlr->caps
9225 09:28:50.119077 52.000 MHz: ctrlr->f_max
9226 09:28:50.119614 0.400 MHz: ctrlr->f_min
9227 09:28:50.122143 0x40ff8080: ctrlr->voltages
9228 09:28:50.122582 sclk: 390625
9229 09:28:50.125497 Bus Width = 1
9230 09:28:50.126025 sclk: 390625
9231 09:28:50.128895 Bus Width = 1
9232 09:28:50.129325 Early init status = 3
9233 09:28:50.135547 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9234 09:28:50.138780 in-header: 03 fc 00 00 01 00 00 00
9235 09:28:50.139235 in-data: 00
9236 09:28:50.145107 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9237 09:28:50.149802 in-header: 03 fd 00 00 00 00 00 00
9238 09:28:50.153070 in-data:
9239 09:28:50.155915 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9240 09:28:50.160900 in-header: 03 fc 00 00 01 00 00 00
9241 09:28:50.164275 in-data: 00
9242 09:28:50.167006 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9243 09:28:50.172993 in-header: 03 fd 00 00 00 00 00 00
9244 09:28:50.176217 in-data:
9245 09:28:50.179632 [SSUSB] Setting up USB HOST controller...
9246 09:28:50.182931 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9247 09:28:50.185670 [SSUSB] phy power-on done.
9248 09:28:50.189575 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9249 09:28:50.196573 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9250 09:28:50.199666 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9251 09:28:50.206290 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9252 09:28:50.213027 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9253 09:28:50.219249 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9254 09:28:50.225765 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9255 09:28:50.232512 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9256 09:28:50.235711 SPM: binary array size = 0x9dc
9257 09:28:50.239083 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9258 09:28:50.246261 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9259 09:28:50.252602 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9260 09:28:50.255877 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9261 09:28:50.262566 configure_display: Starting display init
9262 09:28:50.296195 anx7625_power_on_init: Init interface.
9263 09:28:50.299406 anx7625_disable_pd_protocol: Disabled PD feature.
9264 09:28:50.302424 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9265 09:28:50.330459 anx7625_start_dp_work: Secure OCM version=00
9266 09:28:50.333685 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9267 09:28:50.348627 sp_tx_get_edid_block: EDID Block = 1
9268 09:28:50.451507 Extracted contents:
9269 09:28:50.454792 header: 00 ff ff ff ff ff ff 00
9270 09:28:50.457830 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9271 09:28:50.461154 version: 01 04
9272 09:28:50.464476 basic params: 95 1f 11 78 0a
9273 09:28:50.467876 chroma info: 76 90 94 55 54 90 27 21 50 54
9274 09:28:50.471124 established: 00 00 00
9275 09:28:50.477650 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9276 09:28:50.480904 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9277 09:28:50.487563 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9278 09:28:50.494345 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9279 09:28:50.500943 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9280 09:28:50.504403 extensions: 00
9281 09:28:50.504953 checksum: fb
9282 09:28:50.505297
9283 09:28:50.508074 Manufacturer: IVO Model 57d Serial Number 0
9284 09:28:50.511404 Made week 0 of 2020
9285 09:28:50.511927 EDID version: 1.4
9286 09:28:50.514054 Digital display
9287 09:28:50.517681 6 bits per primary color channel
9288 09:28:50.518117 DisplayPort interface
9289 09:28:50.521244 Maximum image size: 31 cm x 17 cm
9290 09:28:50.524643 Gamma: 220%
9291 09:28:50.525165 Check DPMS levels
9292 09:28:50.527771 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9293 09:28:50.530588 First detailed timing is preferred timing
9294 09:28:50.533795 Established timings supported:
9295 09:28:50.537734 Standard timings supported:
9296 09:28:50.538156 Detailed timings
9297 09:28:50.544178 Hex of detail: 383680a07038204018303c0035ae10000019
9298 09:28:50.547411 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9299 09:28:50.554096 0780 0798 07c8 0820 hborder 0
9300 09:28:50.557269 0438 043b 0447 0458 vborder 0
9301 09:28:50.560594 -hsync -vsync
9302 09:28:50.561032 Did detailed timing
9303 09:28:50.564293 Hex of detail: 000000000000000000000000000000000000
9304 09:28:50.567379 Manufacturer-specified data, tag 0
9305 09:28:50.573622 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9306 09:28:50.574042 ASCII string: InfoVision
9307 09:28:50.580678 Hex of detail: 000000fe00523134304e574635205248200a
9308 09:28:50.583653 ASCII string: R140NWF5 RH
9309 09:28:50.584080 Checksum
9310 09:28:50.584410 Checksum: 0xfb (valid)
9311 09:28:50.590575 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9312 09:28:50.593634 DSI data_rate: 832800000 bps
9313 09:28:50.596869 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9314 09:28:50.603765 anx7625_parse_edid: pixelclock(138800).
9315 09:28:50.607062 hactive(1920), hsync(48), hfp(24), hbp(88)
9316 09:28:50.610333 vactive(1080), vsync(12), vfp(3), vbp(17)
9317 09:28:50.613716 anx7625_dsi_config: config dsi.
9318 09:28:50.620136 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9319 09:28:50.633275 anx7625_dsi_config: success to config DSI
9320 09:28:50.636347 anx7625_dp_start: MIPI phy setup OK.
9321 09:28:50.639659 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9322 09:28:50.643726 mtk_ddp_mode_set invalid vrefresh 60
9323 09:28:50.646725 main_disp_path_setup
9324 09:28:50.647142 ovl_layer_smi_id_en
9325 09:28:50.650134 ovl_layer_smi_id_en
9326 09:28:50.650653 ccorr_config
9327 09:28:50.650988 aal_config
9328 09:28:50.653280 gamma_config
9329 09:28:50.653791 postmask_config
9330 09:28:50.656509 dither_config
9331 09:28:50.659657 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9332 09:28:50.666166 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9333 09:28:50.669571 Root Device init finished in 554 msecs
9334 09:28:50.670011 CPU_CLUSTER: 0 init
9335 09:28:50.679840 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9336 09:28:50.683038 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9337 09:28:50.686264 APU_MBOX 0x190000b0 = 0x10001
9338 09:28:50.689783 APU_MBOX 0x190001b0 = 0x10001
9339 09:28:50.693032 APU_MBOX 0x190005b0 = 0x10001
9340 09:28:50.696332 APU_MBOX 0x190006b0 = 0x10001
9341 09:28:50.699556 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9342 09:28:50.712118 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9343 09:28:50.724839 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9344 09:28:50.731338 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9345 09:28:50.742652 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9346 09:28:50.752134 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9347 09:28:50.755409 CPU_CLUSTER: 0 init finished in 81 msecs
9348 09:28:50.758904 Devices initialized
9349 09:28:50.761985 Show all devs... After init.
9350 09:28:50.762509 Root Device: enabled 1
9351 09:28:50.765591 CPU_CLUSTER: 0: enabled 1
9352 09:28:50.769166 CPU: 00: enabled 1
9353 09:28:50.772407 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9354 09:28:50.775603 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9355 09:28:50.778494 ELOG: NV offset 0x57f000 size 0x1000
9356 09:28:50.785160 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9357 09:28:50.791863 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9358 09:28:50.795053 ELOG: Event(17) added with size 13 at 2024-06-18 09:27:25 UTC
9359 09:28:50.798625 out: cmd=0x121: 03 db 21 01 00 00 00 00
9360 09:28:50.802173 in-header: 03 34 00 00 2c 00 00 00
9361 09:28:50.815327 in-data: 0a 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9362 09:28:50.822391 ELOG: Event(A1) added with size 10 at 2024-06-18 09:27:25 UTC
9363 09:28:50.829140 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9364 09:28:50.835730 ELOG: Event(A0) added with size 9 at 2024-06-18 09:27:25 UTC
9365 09:28:50.839009 elog_add_boot_reason: Logged dev mode boot
9366 09:28:50.842385 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9367 09:28:50.845494 Finalize devices...
9368 09:28:50.845925 Devices finalized
9369 09:28:50.852001 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9370 09:28:50.855004 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9371 09:28:50.858900 in-header: 03 07 00 00 08 00 00 00
9372 09:28:50.861845 in-data: aa e4 47 04 13 02 00 00
9373 09:28:50.865500 Chrome EC: UHEPI supported
9374 09:28:50.872075 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9375 09:28:50.875445 in-header: 03 a9 00 00 08 00 00 00
9376 09:28:50.878302 in-data: 84 60 60 08 00 00 00 00
9377 09:28:50.881641 ELOG: Event(91) added with size 10 at 2024-06-18 09:27:25 UTC
9378 09:28:50.888495 Chrome EC: clear events_b mask to 0x0000000020004000
9379 09:28:50.895395 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9380 09:28:50.899363 in-header: 03 fd 00 00 00 00 00 00
9381 09:28:50.899899 in-data:
9382 09:28:50.905377 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9383 09:28:50.909028 Writing coreboot table at 0xffe64000
9384 09:28:50.912091 0. 000000000010a000-0000000000113fff: RAMSTAGE
9385 09:28:50.915246 1. 0000000040000000-00000000400fffff: RAM
9386 09:28:50.918725 2. 0000000040100000-000000004032afff: RAMSTAGE
9387 09:28:50.922489 3. 000000004032b000-00000000545fffff: RAM
9388 09:28:50.928823 4. 0000000054600000-000000005465ffff: BL31
9389 09:28:50.932273 5. 0000000054660000-00000000ffe63fff: RAM
9390 09:28:50.935899 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9391 09:28:50.939217 7. 0000000100000000-000000023fffffff: RAM
9392 09:28:50.942460 Passing 5 GPIOs to payload:
9393 09:28:50.948982 NAME | PORT | POLARITY | VALUE
9394 09:28:50.952978 EC in RW | 0x000000aa | low | undefined
9395 09:28:50.956136 EC interrupt | 0x00000005 | low | undefined
9396 09:28:50.962886 TPM interrupt | 0x000000ab | high | undefined
9397 09:28:50.965902 SD card detect | 0x00000011 | high | undefined
9398 09:28:50.972645 speaker enable | 0x00000093 | high | undefined
9399 09:28:50.976080 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9400 09:28:50.979039 in-header: 03 f9 00 00 02 00 00 00
9401 09:28:50.979461 in-data: 02 00
9402 09:28:50.982597 ADC[4]: Raw value=901032 ID=7
9403 09:28:50.985993 ADC[3]: Raw value=213179 ID=1
9404 09:28:50.986524 RAM Code: 0x71
9405 09:28:50.989028 ADC[6]: Raw value=74502 ID=0
9406 09:28:50.992473 ADC[5]: Raw value=212441 ID=1
9407 09:28:50.993020 SKU Code: 0x1
9408 09:28:50.998622 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cec6
9409 09:28:51.002488 coreboot table: 964 bytes.
9410 09:28:51.005817 IMD ROOT 0. 0xfffff000 0x00001000
9411 09:28:51.009055 IMD SMALL 1. 0xffffe000 0x00001000
9412 09:28:51.012076 RO MCACHE 2. 0xffffc000 0x00001104
9413 09:28:51.015609 CONSOLE 3. 0xfff7c000 0x00080000
9414 09:28:51.018612 FMAP 4. 0xfff7b000 0x00000452
9415 09:28:51.022246 TIME STAMP 5. 0xfff7a000 0x00000910
9416 09:28:51.025589 VBOOT WORK 6. 0xfff66000 0x00014000
9417 09:28:51.028662 RAMOOPS 7. 0xffe66000 0x00100000
9418 09:28:51.031776 COREBOOT 8. 0xffe64000 0x00002000
9419 09:28:51.032195 IMD small region:
9420 09:28:51.035451 IMD ROOT 0. 0xffffec00 0x00000400
9421 09:28:51.038876 VPD 1. 0xffffeb80 0x0000006c
9422 09:28:51.041922 MMC STATUS 2. 0xffffeb60 0x00000004
9423 09:28:51.048277 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9424 09:28:51.055008 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9425 09:28:51.093540 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9426 09:28:51.097316 Checking segment from ROM address 0x40100000
9427 09:28:51.100428 Checking segment from ROM address 0x4010001c
9428 09:28:51.107048 Loading segment from ROM address 0x40100000
9429 09:28:51.107496 code (compression=0)
9430 09:28:51.117186 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9431 09:28:51.123601 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9432 09:28:51.124041 it's not compressed!
9433 09:28:51.130180 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9434 09:28:51.137065 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9435 09:28:51.154285 Loading segment from ROM address 0x4010001c
9436 09:28:51.154795 Entry Point 0x80000000
9437 09:28:51.157551 Loaded segments
9438 09:28:51.160761 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9439 09:28:51.167774 Jumping to boot code at 0x80000000(0xffe64000)
9440 09:28:51.174692 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9441 09:28:51.181299 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9442 09:28:51.188818 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9443 09:28:51.192476 Checking segment from ROM address 0x40100000
9444 09:28:51.195546 Checking segment from ROM address 0x4010001c
9445 09:28:51.202180 Loading segment from ROM address 0x40100000
9446 09:28:51.202694 code (compression=1)
9447 09:28:51.209201 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9448 09:28:51.218920 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9449 09:28:51.219425 using LZMA
9450 09:28:51.227434 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9451 09:28:51.233825 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9452 09:28:51.237346 Loading segment from ROM address 0x4010001c
9453 09:28:51.237797 Entry Point 0x54601000
9454 09:28:51.240643 Loaded segments
9455 09:28:51.243658 NOTICE: MT8192 bl31_setup
9456 09:28:51.250849 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9457 09:28:51.254335 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9458 09:28:51.257716 WARNING: region 0:
9459 09:28:51.261099 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 09:28:51.261531 WARNING: region 1:
9461 09:28:51.267547 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9462 09:28:51.271280 WARNING: region 2:
9463 09:28:51.274207 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9464 09:28:51.277708 WARNING: region 3:
9465 09:28:51.281239 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9466 09:28:51.284662 WARNING: region 4:
9467 09:28:51.291230 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9468 09:28:51.291757 WARNING: region 5:
9469 09:28:51.294416 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 09:28:51.297820 WARNING: region 6:
9471 09:28:51.301032 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 09:28:51.304497 WARNING: region 7:
9473 09:28:51.307631 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 09:28:51.313966 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9475 09:28:51.317185 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9476 09:28:51.320413 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9477 09:28:51.327547 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9478 09:28:51.330480 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9479 09:28:51.333671 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9480 09:28:51.340475 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9481 09:28:51.343485 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9482 09:28:51.350662 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9483 09:28:51.353851 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9484 09:28:51.357113 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9485 09:28:51.363478 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9486 09:28:51.367102 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9487 09:28:51.374125 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9488 09:28:51.376642 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9489 09:28:51.380261 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9490 09:28:51.386814 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9491 09:28:51.389946 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9492 09:28:51.393260 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9493 09:28:51.399823 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9494 09:28:51.403266 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9495 09:28:51.410462 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9496 09:28:51.413442 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9497 09:28:51.416645 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9498 09:28:51.423355 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9499 09:28:51.426622 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9500 09:28:51.433103 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9501 09:28:51.436291 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9502 09:28:51.439721 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9503 09:28:51.446820 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9504 09:28:51.449924 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9505 09:28:51.456681 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9506 09:28:51.459700 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9507 09:28:51.462981 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9508 09:28:51.466260 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9509 09:28:51.473066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9510 09:28:51.476353 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9511 09:28:51.479476 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9512 09:28:51.482917 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9513 09:28:51.489876 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9514 09:28:51.493098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9515 09:28:51.496315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9516 09:28:51.500189 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9517 09:28:51.507124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9518 09:28:51.509875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9519 09:28:51.513330 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9520 09:28:51.516703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9521 09:28:51.523148 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9522 09:28:51.526912 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9523 09:28:51.529706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9524 09:28:51.536960 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9525 09:28:51.540037 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9526 09:28:51.546373 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9527 09:28:51.549635 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9528 09:28:51.556803 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9529 09:28:51.559771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9530 09:28:51.562837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9531 09:28:51.570020 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9532 09:28:51.573192 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9533 09:28:51.579596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9534 09:28:51.583132 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9535 09:28:51.590253 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9536 09:28:51.593528 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9537 09:28:51.600031 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9538 09:28:51.602964 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9539 09:28:51.606213 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9540 09:28:51.613527 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9541 09:28:51.616704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9542 09:28:51.623366 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9543 09:28:51.626622 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9544 09:28:51.633071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9545 09:28:51.636228 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9546 09:28:51.639357 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9547 09:28:51.646244 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9548 09:28:51.649482 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9549 09:28:51.656013 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9550 09:28:51.659317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9551 09:28:51.665808 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9552 09:28:51.669704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9553 09:28:51.675874 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9554 09:28:51.679675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9555 09:28:51.682876 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9556 09:28:51.689400 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9557 09:28:51.692742 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9558 09:28:51.699628 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9559 09:28:51.702733 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9560 09:28:51.705937 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9561 09:28:51.712644 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9562 09:28:51.715728 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9563 09:28:51.722612 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9564 09:28:51.726029 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9565 09:28:51.732594 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9566 09:28:51.735750 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9567 09:28:51.742280 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9568 09:28:51.745527 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9569 09:28:51.752262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9570 09:28:51.755616 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9571 09:28:51.758864 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9572 09:28:51.762073 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9573 09:28:51.765762 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9574 09:28:51.772312 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9575 09:28:51.775451 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9576 09:28:51.782252 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9577 09:28:51.785625 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9578 09:28:51.788823 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9579 09:28:51.795865 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9580 09:28:51.798803 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9581 09:28:51.806136 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9582 09:28:51.809463 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9583 09:28:51.812394 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9584 09:28:51.819251 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9585 09:28:51.822238 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9586 09:28:51.828706 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9587 09:28:51.832532 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9588 09:28:51.835493 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9589 09:28:51.842435 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9590 09:28:51.845663 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9591 09:28:51.848794 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9592 09:28:51.855476 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9593 09:28:51.858861 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9594 09:28:51.862168 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9595 09:28:51.865354 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9596 09:28:51.872234 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9597 09:28:51.875504 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9598 09:28:51.879056 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9599 09:28:51.885923 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9600 09:28:51.888671 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9601 09:28:51.891806 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9602 09:28:51.899015 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9603 09:28:51.902041 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9604 09:28:51.908968 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9605 09:28:51.912290 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9606 09:28:51.915275 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9607 09:28:51.921809 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9608 09:28:51.925210 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9609 09:28:51.931844 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9610 09:28:51.934933 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9611 09:28:51.938732 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9612 09:28:51.945370 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9613 09:28:51.948425 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9614 09:28:51.952286 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9615 09:28:51.958394 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9616 09:28:51.961867 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9617 09:28:51.968528 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9618 09:28:51.971944 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9619 09:28:51.975295 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9620 09:28:51.981946 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9621 09:28:51.985013 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9622 09:28:51.991844 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9623 09:28:51.995115 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9624 09:28:51.998700 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9625 09:28:52.005338 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9626 09:28:52.008471 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9627 09:28:52.014946 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9628 09:28:52.018035 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9629 09:28:52.021777 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9630 09:28:52.028478 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9631 09:28:52.031466 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9632 09:28:52.035048 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9633 09:28:52.042102 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9634 09:28:52.045300 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9635 09:28:52.051914 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9636 09:28:52.055248 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9637 09:28:52.058084 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9638 09:28:52.064781 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9639 09:28:52.068419 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9640 09:28:52.075045 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9641 09:28:52.078306 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9642 09:28:52.081631 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9643 09:28:52.088226 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9644 09:28:52.091419 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9645 09:28:52.098375 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9646 09:28:52.101614 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9647 09:28:52.104942 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9648 09:28:52.111459 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9649 09:28:52.114894 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9650 09:28:52.121251 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9651 09:28:52.124627 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9652 09:28:52.127778 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9653 09:28:52.134791 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9654 09:28:52.138131 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9655 09:28:52.141540 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9656 09:28:52.147969 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9657 09:28:52.151465 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9658 09:28:52.157959 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9659 09:28:52.161716 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9660 09:28:52.164719 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9661 09:28:52.171765 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9662 09:28:52.174935 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9663 09:28:52.181129 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9664 09:28:52.185019 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9665 09:28:52.187890 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9666 09:28:52.195005 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9667 09:28:52.197961 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9668 09:28:52.204329 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9669 09:28:52.208028 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9670 09:28:52.214672 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9671 09:28:52.217705 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9672 09:28:52.221080 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9673 09:28:52.227995 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9674 09:28:52.230863 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9675 09:28:52.238195 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9676 09:28:52.241178 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9677 09:28:52.244169 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9678 09:28:52.251017 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9679 09:28:52.254761 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9680 09:28:52.261179 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9681 09:28:52.264600 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9682 09:28:52.267479 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9683 09:28:52.274422 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9684 09:28:52.277743 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9685 09:28:52.284225 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9686 09:28:52.287840 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9687 09:28:52.294326 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9688 09:28:52.298020 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9689 09:28:52.301052 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9690 09:28:52.307992 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9691 09:28:52.311257 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9692 09:28:52.317817 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9693 09:28:52.320982 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9694 09:28:52.324537 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9695 09:28:52.331079 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9696 09:28:52.334025 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9697 09:28:52.340783 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9698 09:28:52.344168 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9699 09:28:52.351087 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9700 09:28:52.354120 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9701 09:28:52.357243 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9702 09:28:52.363927 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9703 09:28:52.367655 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9704 09:28:52.371186 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9705 09:28:52.374236 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9706 09:28:52.381107 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9707 09:28:52.384391 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9708 09:28:52.387677 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9709 09:28:52.394307 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9710 09:28:52.397480 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9711 09:28:52.400661 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9712 09:28:52.408045 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9713 09:28:52.411206 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9714 09:28:52.414921 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9715 09:28:52.420840 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9716 09:28:52.423912 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9717 09:28:52.427531 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9718 09:28:52.434118 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9719 09:28:52.437090 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9720 09:28:52.444378 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9721 09:28:52.447946 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9722 09:28:52.451281 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9723 09:28:52.457213 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9724 09:28:52.460307 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9725 09:28:52.464171 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9726 09:28:52.470766 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9727 09:28:52.473853 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9728 09:28:52.477264 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9729 09:28:52.484076 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9730 09:28:52.486989 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9731 09:28:52.493999 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9732 09:28:52.497439 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9733 09:28:52.500631 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9734 09:28:52.507222 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9735 09:28:52.510478 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9736 09:28:52.516853 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9737 09:28:52.520477 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9738 09:28:52.523944 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9739 09:28:52.530346 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9740 09:28:52.533904 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9741 09:28:52.536875 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9742 09:28:52.543549 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9743 09:28:52.546782 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9744 09:28:52.549853 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9745 09:28:52.553198 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9746 09:28:52.556628 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9747 09:28:52.563337 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9748 09:28:52.566837 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9749 09:28:52.569689 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9750 09:28:52.573092 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9751 09:28:52.579923 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9752 09:28:52.583321 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9753 09:28:52.587093 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9754 09:28:52.593107 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9755 09:28:52.596802 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9756 09:28:52.599770 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9757 09:28:52.606641 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9758 09:28:52.609861 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9759 09:28:52.616876 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9760 09:28:52.620151 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9761 09:28:52.623262 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9762 09:28:52.629778 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9763 09:28:52.632998 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9764 09:28:52.636203 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9765 09:28:52.643677 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9766 09:28:52.646661 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9767 09:28:52.653473 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9768 09:28:52.656893 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9769 09:28:52.663203 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9770 09:28:52.666318 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9771 09:28:52.669421 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9772 09:28:52.676319 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9773 09:28:52.679551 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9774 09:28:52.686236 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9775 09:28:52.689485 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9776 09:28:52.692741 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9777 09:28:52.699336 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9778 09:28:52.703067 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9779 09:28:52.709828 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9780 09:28:52.713075 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9781 09:28:52.716609 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9782 09:28:52.722893 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9783 09:28:52.726421 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9784 09:28:52.733008 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9785 09:28:52.736232 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9786 09:28:52.742620 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9787 09:28:52.745768 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9788 09:28:52.749023 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9789 09:28:52.756354 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9790 09:28:52.759642 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9791 09:28:52.765905 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9792 09:28:52.769312 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9793 09:28:52.772449 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9794 09:28:52.779763 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9795 09:28:52.783052 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9796 09:28:52.789106 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9797 09:28:52.792413 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9798 09:28:52.795971 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9799 09:28:52.802593 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9800 09:28:52.805711 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9801 09:28:52.812542 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9802 09:28:52.815949 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9803 09:28:52.819192 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9804 09:28:52.825859 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9805 09:28:52.829095 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9806 09:28:52.835778 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9807 09:28:52.839143 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9808 09:28:52.842405 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9809 09:28:52.848996 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9810 09:28:52.852165 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9811 09:28:52.859248 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9812 09:28:52.862367 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9813 09:28:52.865977 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9814 09:28:52.872366 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9815 09:28:52.876030 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9816 09:28:52.882084 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9817 09:28:52.885365 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9818 09:28:52.892832 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9819 09:28:52.895546 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9820 09:28:52.899165 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9821 09:28:52.905452 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9822 09:28:52.909143 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9823 09:28:52.915742 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9824 09:28:52.919087 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9825 09:28:52.922026 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9826 09:28:52.929040 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9827 09:28:52.932321 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9828 09:28:52.939115 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9829 09:28:52.942021 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9830 09:28:52.945286 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9831 09:28:52.952200 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9832 09:28:52.955805 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9833 09:28:52.962062 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9834 09:28:52.965255 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9835 09:28:52.972361 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9836 09:28:52.975830 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9837 09:28:52.978793 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9838 09:28:52.985392 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9839 09:28:52.989047 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9840 09:28:52.995951 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9841 09:28:52.999347 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9842 09:28:53.005370 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9843 09:28:53.009024 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9844 09:28:53.012472 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9845 09:28:53.019073 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9846 09:28:53.022128 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9847 09:28:53.028811 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9848 09:28:53.032086 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9849 09:28:53.039099 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9850 09:28:53.042311 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9851 09:28:53.045489 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9852 09:28:53.051683 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9853 09:28:53.055418 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9854 09:28:53.061904 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9855 09:28:53.065173 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9856 09:28:53.071616 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9857 09:28:53.075067 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9858 09:28:53.081656 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9859 09:28:53.084987 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9860 09:28:53.088529 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9861 09:28:53.095579 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9862 09:28:53.098997 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9863 09:28:53.105225 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9864 09:28:53.108838 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9865 09:28:53.114909 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9866 09:28:53.118929 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9867 09:28:53.121833 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9868 09:28:53.128715 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9869 09:28:53.131769 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9870 09:28:53.138323 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9871 09:28:53.141743 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9872 09:28:53.148640 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9873 09:28:53.151704 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9874 09:28:53.154764 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9875 09:28:53.161721 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9876 09:28:53.165075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9877 09:28:53.171357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9878 09:28:53.174823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9879 09:28:53.181652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9880 09:28:53.184824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9881 09:28:53.187999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9882 09:28:53.194997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9883 09:28:53.198227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9884 09:28:53.205116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9885 09:28:53.208467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9886 09:28:53.215056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9887 09:28:53.218551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9888 09:28:53.224968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9889 09:28:53.228497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9890 09:28:53.234631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9891 09:28:53.238033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9892 09:28:53.245250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9893 09:28:53.248710 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9894 09:28:53.254827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9895 09:28:53.258175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9896 09:28:53.264465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9897 09:28:53.268362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9898 09:28:53.274685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9899 09:28:53.278021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9900 09:28:53.284525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9901 09:28:53.288006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9902 09:28:53.294821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9903 09:28:53.297683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9904 09:28:53.304744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9905 09:28:53.308232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9906 09:28:53.314342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9907 09:28:53.317612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9908 09:28:53.321514 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9909 09:28:53.324685 INFO: [APUAPC] vio 0
9910 09:28:53.331207 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9911 09:28:53.334394 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9912 09:28:53.337698 INFO: [APUAPC] D0_APC_0: 0x400510
9913 09:28:53.340982 INFO: [APUAPC] D0_APC_1: 0x0
9914 09:28:53.344195 INFO: [APUAPC] D0_APC_2: 0x1540
9915 09:28:53.347831 INFO: [APUAPC] D0_APC_3: 0x0
9916 09:28:53.351197 INFO: [APUAPC] D1_APC_0: 0xffffffff
9917 09:28:53.354687 INFO: [APUAPC] D1_APC_1: 0xffffffff
9918 09:28:53.358075 INFO: [APUAPC] D1_APC_2: 0x3fffff
9919 09:28:53.358632 INFO: [APUAPC] D1_APC_3: 0x0
9920 09:28:53.364125 INFO: [APUAPC] D2_APC_0: 0xffffffff
9921 09:28:53.367936 INFO: [APUAPC] D2_APC_1: 0xffffffff
9922 09:28:53.371244 INFO: [APUAPC] D2_APC_2: 0x3fffff
9923 09:28:53.371795 INFO: [APUAPC] D2_APC_3: 0x0
9924 09:28:53.374368 INFO: [APUAPC] D3_APC_0: 0xffffffff
9925 09:28:53.377587 INFO: [APUAPC] D3_APC_1: 0xffffffff
9926 09:28:53.380998 INFO: [APUAPC] D3_APC_2: 0x3fffff
9927 09:28:53.384286 INFO: [APUAPC] D3_APC_3: 0x0
9928 09:28:53.387405 INFO: [APUAPC] D4_APC_0: 0xffffffff
9929 09:28:53.391553 INFO: [APUAPC] D4_APC_1: 0xffffffff
9930 09:28:53.394724 INFO: [APUAPC] D4_APC_2: 0x3fffff
9931 09:28:53.397747 INFO: [APUAPC] D4_APC_3: 0x0
9932 09:28:53.401130 INFO: [APUAPC] D5_APC_0: 0xffffffff
9933 09:28:53.404568 INFO: [APUAPC] D5_APC_1: 0xffffffff
9934 09:28:53.407576 INFO: [APUAPC] D5_APC_2: 0x3fffff
9935 09:28:53.411013 INFO: [APUAPC] D5_APC_3: 0x0
9936 09:28:53.414483 INFO: [APUAPC] D6_APC_0: 0xffffffff
9937 09:28:53.417808 INFO: [APUAPC] D6_APC_1: 0xffffffff
9938 09:28:53.421507 INFO: [APUAPC] D6_APC_2: 0x3fffff
9939 09:28:53.424750 INFO: [APUAPC] D6_APC_3: 0x0
9940 09:28:53.428123 INFO: [APUAPC] D7_APC_0: 0xffffffff
9941 09:28:53.430938 INFO: [APUAPC] D7_APC_1: 0xffffffff
9942 09:28:53.433951 INFO: [APUAPC] D7_APC_2: 0x3fffff
9943 09:28:53.437757 INFO: [APUAPC] D7_APC_3: 0x0
9944 09:28:53.441071 INFO: [APUAPC] D8_APC_0: 0xffffffff
9945 09:28:53.444261 INFO: [APUAPC] D8_APC_1: 0xffffffff
9946 09:28:53.447883 INFO: [APUAPC] D8_APC_2: 0x3fffff
9947 09:28:53.451176 INFO: [APUAPC] D8_APC_3: 0x0
9948 09:28:53.454520 INFO: [APUAPC] D9_APC_0: 0xffffffff
9949 09:28:53.457739 INFO: [APUAPC] D9_APC_1: 0xffffffff
9950 09:28:53.461119 INFO: [APUAPC] D9_APC_2: 0x3fffff
9951 09:28:53.464122 INFO: [APUAPC] D9_APC_3: 0x0
9952 09:28:53.468101 INFO: [APUAPC] D10_APC_0: 0xffffffff
9953 09:28:53.471047 INFO: [APUAPC] D10_APC_1: 0xffffffff
9954 09:28:53.473987 INFO: [APUAPC] D10_APC_2: 0x3fffff
9955 09:28:53.477298 INFO: [APUAPC] D10_APC_3: 0x0
9956 09:28:53.480776 INFO: [APUAPC] D11_APC_0: 0xffffffff
9957 09:28:53.483964 INFO: [APUAPC] D11_APC_1: 0xffffffff
9958 09:28:53.487199 INFO: [APUAPC] D11_APC_2: 0x3fffff
9959 09:28:53.490460 INFO: [APUAPC] D11_APC_3: 0x0
9960 09:28:53.494352 INFO: [APUAPC] D12_APC_0: 0xffffffff
9961 09:28:53.497516 INFO: [APUAPC] D12_APC_1: 0xffffffff
9962 09:28:53.500927 INFO: [APUAPC] D12_APC_2: 0x3fffff
9963 09:28:53.504490 INFO: [APUAPC] D12_APC_3: 0x0
9964 09:28:53.507313 INFO: [APUAPC] D13_APC_0: 0xffffffff
9965 09:28:53.510726 INFO: [APUAPC] D13_APC_1: 0xffffffff
9966 09:28:53.514353 INFO: [APUAPC] D13_APC_2: 0x3fffff
9967 09:28:53.517517 INFO: [APUAPC] D13_APC_3: 0x0
9968 09:28:53.520911 INFO: [APUAPC] D14_APC_0: 0xffffffff
9969 09:28:53.523997 INFO: [APUAPC] D14_APC_1: 0xffffffff
9970 09:28:53.527478 INFO: [APUAPC] D14_APC_2: 0x3fffff
9971 09:28:53.530680 INFO: [APUAPC] D14_APC_3: 0x0
9972 09:28:53.533848 INFO: [APUAPC] D15_APC_0: 0xffffffff
9973 09:28:53.537571 INFO: [APUAPC] D15_APC_1: 0xffffffff
9974 09:28:53.540651 INFO: [APUAPC] D15_APC_2: 0x3fffff
9975 09:28:53.543784 INFO: [APUAPC] D15_APC_3: 0x0
9976 09:28:53.547499 INFO: [APUAPC] APC_CON: 0x4
9977 09:28:53.550377 INFO: [NOCDAPC] D0_APC_0: 0x0
9978 09:28:53.554361 INFO: [NOCDAPC] D0_APC_1: 0x0
9979 09:28:53.554886 INFO: [NOCDAPC] D1_APC_0: 0x0
9980 09:28:53.557283 INFO: [NOCDAPC] D1_APC_1: 0xfff
9981 09:28:53.560668 INFO: [NOCDAPC] D2_APC_0: 0x0
9982 09:28:53.563855 INFO: [NOCDAPC] D2_APC_1: 0xfff
9983 09:28:53.567478 INFO: [NOCDAPC] D3_APC_0: 0x0
9984 09:28:53.570731 INFO: [NOCDAPC] D3_APC_1: 0xfff
9985 09:28:53.573763 INFO: [NOCDAPC] D4_APC_0: 0x0
9986 09:28:53.576907 INFO: [NOCDAPC] D4_APC_1: 0xfff
9987 09:28:53.580538 INFO: [NOCDAPC] D5_APC_0: 0x0
9988 09:28:53.583718 INFO: [NOCDAPC] D5_APC_1: 0xfff
9989 09:28:53.584355 INFO: [NOCDAPC] D6_APC_0: 0x0
9990 09:28:53.587578 INFO: [NOCDAPC] D6_APC_1: 0xfff
9991 09:28:53.590659 INFO: [NOCDAPC] D7_APC_0: 0x0
9992 09:28:53.593999 INFO: [NOCDAPC] D7_APC_1: 0xfff
9993 09:28:53.597028 INFO: [NOCDAPC] D8_APC_0: 0x0
9994 09:28:53.600619 INFO: [NOCDAPC] D8_APC_1: 0xfff
9995 09:28:53.603919 INFO: [NOCDAPC] D9_APC_0: 0x0
9996 09:28:53.606892 INFO: [NOCDAPC] D9_APC_1: 0xfff
9997 09:28:53.610142 INFO: [NOCDAPC] D10_APC_0: 0x0
9998 09:28:53.613265 INFO: [NOCDAPC] D10_APC_1: 0xfff
9999 09:28:53.616490 INFO: [NOCDAPC] D11_APC_0: 0x0
10000 09:28:53.620217 INFO: [NOCDAPC] D11_APC_1: 0xfff
10001 09:28:53.623529 INFO: [NOCDAPC] D12_APC_0: 0x0
10002 09:28:53.624070 INFO: [NOCDAPC] D12_APC_1: 0xfff
10003 09:28:53.626755 INFO: [NOCDAPC] D13_APC_0: 0x0
10004 09:28:53.629939 INFO: [NOCDAPC] D13_APC_1: 0xfff
10005 09:28:53.633323 INFO: [NOCDAPC] D14_APC_0: 0x0
10006 09:28:53.636663 INFO: [NOCDAPC] D14_APC_1: 0xfff
10007 09:28:53.640047 INFO: [NOCDAPC] D15_APC_0: 0x0
10008 09:28:53.643010 INFO: [NOCDAPC] D15_APC_1: 0xfff
10009 09:28:53.646620 INFO: [NOCDAPC] APC_CON: 0x4
10010 09:28:53.649706 INFO: [APUAPC] set_apusys_apc done
10011 09:28:53.652840 INFO: [DEVAPC] devapc_init done
10012 09:28:53.656419 INFO: GICv3 without legacy support detected.
10013 09:28:53.659805 INFO: ARM GICv3 driver initialized in EL3
10014 09:28:53.662992 INFO: Maximum SPI INTID supported: 639
10015 09:28:53.669529 INFO: BL31: Initializing runtime services
10016 09:28:53.672762 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10017 09:28:53.675873 INFO: SPM: enable CPC mode
10018 09:28:53.682749 INFO: mcdi ready for mcusys-off-idle and system suspend
10019 09:28:53.685724 INFO: BL31: Preparing for EL3 exit to normal world
10020 09:28:53.689614 INFO: Entry point address = 0x80000000
10021 09:28:53.692439 INFO: SPSR = 0x8
10022 09:28:53.698292
10023 09:28:53.698376
10024 09:28:53.698442
10025 09:28:53.701477 Starting depthcharge on Spherion...
10026 09:28:53.701561
10027 09:28:53.701627 Wipe memory regions:
10028 09:28:53.701689
10029 09:28:53.702270 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10030 09:28:53.702371 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10031 09:28:53.702456 Setting prompt string to ['asurada:']
10032 09:28:53.702534 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10033 09:28:53.704732 [0x00000040000000, 0x00000054600000)
10034 09:28:53.828226
10035 09:28:53.828917 [0x00000054660000, 0x00000080000000)
10036 09:28:54.088300
10037 09:28:54.088862 [0x000000821a7280, 0x000000ffe64000)
10038 09:28:54.833081
10039 09:28:54.833259 [0x00000100000000, 0x00000240000000)
10040 09:28:56.723656
10041 09:28:56.726544 Initializing XHCI USB controller at 0x11200000.
10042 09:28:57.766083
10043 09:28:57.769255 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10044 09:28:57.769783
10045 09:28:57.770125
10046 09:28:57.770878 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10048 09:28:57.872099 asurada: tftpboot 192.168.201.1 14407641/tftp-deploy-kc612fpy/kernel/image.itb 14407641/tftp-deploy-kc612fpy/kernel/cmdline
10049 09:28:57.872888 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10050 09:28:57.873314 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10051 09:28:57.877790 tftpboot 192.168.201.1 14407641/tftp-deploy-kc612fpy/kernel/image.ittp-deploy-kc612fpy/kernel/cmdline
10052 09:28:57.878233
10053 09:28:57.878573 Waiting for link
10054 09:28:58.036246
10055 09:28:58.036784 R8152: Initializing
10056 09:28:58.037142
10057 09:28:58.039582 Version 9 (ocp_data = 6010)
10058 09:28:58.040016
10059 09:28:58.042750 R8152: Done initializing
10060 09:28:58.043204
10061 09:28:58.043547 Adding net device
10062 09:28:59.913786
10063 09:28:59.914278 done.
10064 09:28:59.914626
10065 09:28:59.914954 MAC: 00:e0:4c:72:2d:d6
10066 09:28:59.915312
10067 09:28:59.917367 Sending DHCP discover... done.
10068 09:28:59.917884
10069 09:28:59.921389 Waiting for reply... done.
10070 09:28:59.921828
10071 09:28:59.923386 Sending DHCP request... done.
10072 09:28:59.923816
10073 09:28:59.930070 Waiting for reply... done.
10074 09:28:59.930500
10075 09:28:59.930842 My ip is 192.168.201.21
10076 09:28:59.931164
10077 09:28:59.933185 The DHCP server ip is 192.168.201.1
10078 09:28:59.933638
10079 09:28:59.939712 TFTP server IP predefined by user: 192.168.201.1
10080 09:28:59.940144
10081 09:28:59.946412 Bootfile predefined by user: 14407641/tftp-deploy-kc612fpy/kernel/image.itb
10082 09:28:59.946953
10083 09:28:59.949516 Sending tftp read request... done.
10084 09:28:59.949947
10085 09:28:59.954257 Waiting for the transfer...
10086 09:28:59.954688
10087 09:29:00.246168 00000000 ################################################################
10088 09:29:00.246313
10089 09:29:00.519851 00080000 ################################################################
10090 09:29:00.520011
10091 09:29:00.799257 00100000 ################################################################
10092 09:29:00.799397
10093 09:29:01.065764 00180000 ################################################################
10094 09:29:01.065918
10095 09:29:01.352195 00200000 ################################################################
10096 09:29:01.352335
10097 09:29:01.704537 00280000 ################################################################
10098 09:29:01.704700
10099 09:29:02.032243 00300000 ################################################################
10100 09:29:02.032399
10101 09:29:02.383274 00380000 ################################################################
10102 09:29:02.383430
10103 09:29:02.676415 00400000 ################################################################
10104 09:29:02.676585
10105 09:29:03.021797 00480000 ################################################################
10106 09:29:03.021966
10107 09:29:03.293205 00500000 ################################################################
10108 09:29:03.293394
10109 09:29:03.558037 00580000 ################################################################
10110 09:29:03.558182
10111 09:29:03.819686 00600000 ################################################################
10112 09:29:03.819824
10113 09:29:04.069057 00680000 ################################################################
10114 09:29:04.069190
10115 09:29:04.326964 00700000 ################################################################
10116 09:29:04.327105
10117 09:29:04.605644 00780000 ################################################################
10118 09:29:04.605782
10119 09:29:04.885644 00800000 ################################################################
10120 09:29:04.885788
10121 09:29:05.163410 00880000 ################################################################
10122 09:29:05.163559
10123 09:29:05.436890 00900000 ################################################################
10124 09:29:05.437034
10125 09:29:05.690036 00980000 ################################################################
10126 09:29:05.690172
10127 09:29:05.981690 00a00000 ################################################################
10128 09:29:05.981841
10129 09:29:06.232611 00a80000 ################################################################
10130 09:29:06.232751
10131 09:29:06.482057 00b00000 ################################################################
10132 09:29:06.482224
10133 09:29:06.749717 00b80000 ################################################################
10134 09:29:06.749872
10135 09:29:07.019526 00c00000 ################################################################
10136 09:29:07.019697
10137 09:29:07.297980 00c80000 ################################################################
10138 09:29:07.298128
10139 09:29:07.571430 00d00000 ################################################################
10140 09:29:07.571604
10141 09:29:07.848503 00d80000 ################################################################
10142 09:29:07.848703
10143 09:29:08.117381 00e00000 ################################################################
10144 09:29:08.117523
10145 09:29:08.393951 00e80000 ################################################################
10146 09:29:08.394094
10147 09:29:08.656771 00f00000 ################################################################
10148 09:29:08.656926
10149 09:29:08.922793 00f80000 ################################################################
10150 09:29:08.922971
10151 09:29:09.181224 01000000 ################################################################
10152 09:29:09.181361
10153 09:29:09.437991 01080000 ################################################################
10154 09:29:09.438157
10155 09:29:09.700667 01100000 ################################################################
10156 09:29:09.700819
10157 09:29:09.979474 01180000 ################################################################
10158 09:29:09.979612
10159 09:29:10.249739 01200000 ################################################################
10160 09:29:10.249875
10161 09:29:10.510219 01280000 ################################################################
10162 09:29:10.510353
10163 09:29:10.772384 01300000 ################################################################
10164 09:29:10.772519
10165 09:29:11.039374 01380000 ################################################################
10166 09:29:11.039534
10167 09:29:11.312615 01400000 ################################################################
10168 09:29:11.312777
10169 09:29:11.575598 01480000 ################################################################
10170 09:29:11.575764
10171 09:29:11.825977 01500000 ################################################################
10172 09:29:11.826119
10173 09:29:12.079690 01580000 ################################################################
10174 09:29:12.079831
10175 09:29:12.343618 01600000 ################################################################
10176 09:29:12.343798
10177 09:29:12.600494 01680000 ################################################################
10178 09:29:12.600709
10179 09:29:12.843546 01700000 ################################################################
10180 09:29:12.843699
10181 09:29:13.088291 01780000 ################################################################
10182 09:29:13.088478
10183 09:29:13.348103 01800000 ################################################################
10184 09:29:13.348286
10185 09:29:13.603257 01880000 ################################################################
10186 09:29:13.603423
10187 09:29:13.849457 01900000 ################################################################
10188 09:29:13.849636
10189 09:29:14.096097 01980000 ################################################################
10190 09:29:14.096281
10191 09:29:14.350540 01a00000 ################################################################
10192 09:29:14.350722
10193 09:29:14.614184 01a80000 ################################################################
10194 09:29:14.614355
10195 09:29:14.870473 01b00000 ################################################################
10196 09:29:14.870622
10197 09:29:15.118717 01b80000 ################################################################
10198 09:29:15.118848
10199 09:29:15.388510 01c00000 ################################################################
10200 09:29:15.388683
10201 09:29:15.637348 01c80000 ################################################################
10202 09:29:15.637481
10203 09:29:15.924190 01d00000 ################################################################
10204 09:29:15.924370
10205 09:29:16.264015 01d80000 ################################################################
10206 09:29:16.264152
10207 09:29:16.516852 01e00000 ################################################################
10208 09:29:16.517020
10209 09:29:16.790044 01e80000 ################################################################
10210 09:29:16.790183
10211 09:29:17.065575 01f00000 ################################################################
10212 09:29:17.065742
10213 09:29:17.344500 01f80000 ################################################################
10214 09:29:17.344684
10215 09:29:17.629632 02000000 ################################################################
10216 09:29:17.629774
10217 09:29:17.899781 02080000 ################################################################
10218 09:29:17.899951
10219 09:29:18.185212 02100000 ################################################################
10220 09:29:18.185463
10221 09:29:18.459721 02180000 ################################################################
10222 09:29:18.459866
10223 09:29:18.721139 02200000 ################################################################
10224 09:29:18.721277
10225 09:29:18.997949 02280000 ################################################################
10226 09:29:18.998098
10227 09:29:19.252730 02300000 ################################################################
10228 09:29:19.252878
10229 09:29:19.525579 02380000 ################################################################
10230 09:29:19.525760
10231 09:29:19.813587 02400000 ################################################################
10232 09:29:19.813737
10233 09:29:20.099623 02480000 ################################################################
10234 09:29:20.099768
10235 09:29:20.378874 02500000 ################################################################
10236 09:29:20.379011
10237 09:29:20.653783 02580000 ################################################################
10238 09:29:20.653950
10239 09:29:20.946513 02600000 ################################################################
10240 09:29:20.946697
10241 09:29:21.224940 02680000 ################################################################
10242 09:29:21.225089
10243 09:29:21.522696 02700000 ################################################################
10244 09:29:21.522850
10245 09:29:21.814714 02780000 ################################################################
10246 09:29:21.814853
10247 09:29:22.102292 02800000 ################################################################
10248 09:29:22.102436
10249 09:29:22.383248 02880000 ################################################################
10250 09:29:22.383409
10251 09:29:22.675186 02900000 ################################################################
10252 09:29:22.675327
10253 09:29:22.953220 02980000 ################################################################
10254 09:29:22.953356
10255 09:29:23.226808 02a00000 ################################################################
10256 09:29:23.226943
10257 09:29:23.522131 02a80000 ################################################################
10258 09:29:23.522265
10259 09:29:23.777064 02b00000 ################################################################
10260 09:29:23.777202
10261 09:29:24.064229 02b80000 ################################################################
10262 09:29:24.064387
10263 09:29:24.351202 02c00000 ################################################################
10264 09:29:24.351352
10265 09:29:24.627892 02c80000 ################################################################
10266 09:29:24.628033
10267 09:29:24.888502 02d00000 ################################################################
10268 09:29:24.888672
10269 09:29:25.163158 02d80000 ################################################################
10270 09:29:25.163296
10271 09:29:25.434362 02e00000 ################################################################
10272 09:29:25.434501
10273 09:29:25.695310 02e80000 ################################################################
10274 09:29:25.695449
10275 09:29:25.965971 02f00000 ################################################################
10276 09:29:25.966112
10277 09:29:26.249548 02f80000 ################################################################
10278 09:29:26.249684
10279 09:29:26.519293 03000000 ################################################################
10280 09:29:26.519436
10281 09:29:26.812425 03080000 ################################################################
10282 09:29:26.812624
10283 09:29:27.092464 03100000 ################################################################
10284 09:29:27.092648
10285 09:29:27.370253 03180000 ################################################################
10286 09:29:27.370391
10287 09:29:27.651023 03200000 ################################################################
10288 09:29:27.651156
10289 09:29:27.906224 03280000 ################################################################
10290 09:29:27.906401
10291 09:29:28.163383 03300000 ################################################################
10292 09:29:28.163522
10293 09:29:28.357045 03380000 ################################################# done.
10294 09:29:28.357187
10295 09:29:28.360554 The bootfile was 54399850 bytes long.
10296 09:29:28.360669
10297 09:29:28.364299 Sending tftp read request... done.
10298 09:29:28.364845
10299 09:29:28.367480 Waiting for the transfer...
10300 09:29:28.368243
10301 09:29:28.370694 00000000 # done.
10302 09:29:28.371175
10303 09:29:28.377501 Command line loaded dynamically from TFTP file: 14407641/tftp-deploy-kc612fpy/kernel/cmdline
10304 09:29:28.377993
10305 09:29:28.390635 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10306 09:29:28.391222
10307 09:29:28.391595 Loading FIT.
10308 09:29:28.393864
10309 09:29:28.394370 Image ramdisk-1 has 41223829 bytes.
10310 09:29:28.394753
10311 09:29:28.397055 Image fdt-1 has 47258 bytes.
10312 09:29:28.397529
10313 09:29:28.400241 Image kernel-1 has 13126726 bytes.
10314 09:29:28.400872
10315 09:29:28.410413 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10316 09:29:28.410891
10317 09:29:28.427514 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10318 09:29:28.428216
10319 09:29:28.433529 Choosing best match conf-1 for compat google,spherion-rev2.
10320 09:29:28.436868
10321 09:29:28.441619 Connected to device vid:did:rid of 1ae0:0028:00
10322 09:29:28.448242
10323 09:29:28.452015 tpm_get_response: command 0x17b, return code 0x0
10324 09:29:28.452495
10325 09:29:28.455092 ec_init: CrosEC protocol v3 supported (256, 248)
10326 09:29:28.459285
10327 09:29:28.462287 tpm_cleanup: add release locality here.
10328 09:29:28.462764
10329 09:29:28.463143 Shutting down all USB controllers.
10330 09:29:28.466024
10331 09:29:28.466555 Removing current net device
10332 09:29:28.466938
10333 09:29:28.472513 Exiting depthcharge with code 4 at timestamp: 64108455
10334 09:29:28.473031
10335 09:29:28.476844 LZMA decompressing kernel-1 to 0x821a6718
10336 09:29:28.477147
10337 09:29:28.478846 LZMA decompressing kernel-1 to 0x40000000
10338 09:29:30.096959
10339 09:29:30.097498 jumping to kernel
10340 09:29:30.099557 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10341 09:29:30.100079 start: 2.2.5 auto-login-action (timeout 00:03:51) [common]
10342 09:29:30.100474 Setting prompt string to ['Linux version [0-9]']
10343 09:29:30.100893 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10344 09:29:30.101252 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10345 09:29:30.179396
10346 09:29:30.182601 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10347 09:29:30.186287 start: 2.2.5.1 login-action (timeout 00:03:50) [common]
10348 09:29:30.186785 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10349 09:29:30.187229 Setting prompt string to []
10350 09:29:30.187754 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10351 09:29:30.188140 Using line separator: #'\n'#
10352 09:29:30.188457 No login prompt set.
10353 09:29:30.188806 Parsing kernel messages
10354 09:29:30.189142 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10355 09:29:30.189671 [login-action] Waiting for messages, (timeout 00:03:50)
10356 09:29:30.190019 Waiting using forced prompt support (timeout 00:01:55)
10357 09:29:30.205718 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
10358 09:29:30.209039 [ 0.000000] random: crng init done
10359 09:29:30.215891 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10360 09:29:30.218846 [ 0.000000] efi: UEFI not found.
10361 09:29:30.225121 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10362 09:29:30.231840 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10363 09:29:30.242209 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10364 09:29:30.251677 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10365 09:29:30.258764 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10366 09:29:30.265355 [ 0.000000] printk: bootconsole [mtk8250] enabled
10367 09:29:30.271990 [ 0.000000] NUMA: No NUMA configuration found
10368 09:29:30.278325 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10369 09:29:30.281446 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10370 09:29:30.284681 [ 0.000000] Zone ranges:
10371 09:29:30.291885 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10372 09:29:30.295257 [ 0.000000] DMA32 empty
10373 09:29:30.301918 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10374 09:29:30.305104 [ 0.000000] Movable zone start for each node
10375 09:29:30.308721 [ 0.000000] Early memory node ranges
10376 09:29:30.314852 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10377 09:29:30.321196 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10378 09:29:30.328287 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10379 09:29:30.334923 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10380 09:29:30.338260 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10381 09:29:30.347705 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10382 09:29:30.403793 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10383 09:29:30.410349 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10384 09:29:30.417225 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10385 09:29:30.420688 [ 0.000000] psci: probing for conduit method from DT.
10386 09:29:30.427238 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10387 09:29:30.430451 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10388 09:29:30.436888 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10389 09:29:30.440416 [ 0.000000] psci: SMC Calling Convention v1.2
10390 09:29:30.446858 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10391 09:29:30.450161 [ 0.000000] Detected VIPT I-cache on CPU0
10392 09:29:30.456927 [ 0.000000] CPU features: detected: GIC system register CPU interface
10393 09:29:30.463323 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10394 09:29:30.470131 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10395 09:29:30.476885 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10396 09:29:30.483472 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10397 09:29:30.493258 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10398 09:29:30.496325 [ 0.000000] alternatives: applying boot alternatives
10399 09:29:30.503453 [ 0.000000] Fallback order for Node 0: 0
10400 09:29:30.510029 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10401 09:29:30.513474 [ 0.000000] Policy zone: Normal
10402 09:29:30.526364 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10403 09:29:30.536415 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10404 09:29:30.548354 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10405 09:29:30.557944 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10406 09:29:30.564826 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10407 09:29:30.568050 <6>[ 0.000000] software IO TLB: area num 8.
10408 09:29:30.625365 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10409 09:29:30.774529 <6>[ 0.000000] Memory: 7923804K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 428964K reserved, 32768K cma-reserved)
10410 09:29:30.780993 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10411 09:29:30.788169 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10412 09:29:30.791211 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10413 09:29:30.797573 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10414 09:29:30.804216 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10415 09:29:30.807420 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10416 09:29:30.817877 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10417 09:29:30.824267 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10418 09:29:30.830794 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10419 09:29:30.837602 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10420 09:29:30.840916 <6>[ 0.000000] GICv3: 608 SPIs implemented
10421 09:29:30.844400 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10422 09:29:30.850768 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10423 09:29:30.853946 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10424 09:29:30.860430 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10425 09:29:30.873884 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10426 09:29:30.883844 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10427 09:29:30.894026 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10428 09:29:30.901093 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10429 09:29:30.914490 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10430 09:29:30.921093 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10431 09:29:30.927725 <6>[ 0.009182] Console: colour dummy device 80x25
10432 09:29:30.937368 <6>[ 0.013900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10433 09:29:30.944576 <6>[ 0.024406] pid_max: default: 32768 minimum: 301
10434 09:29:30.947378 <6>[ 0.029277] LSM: Security Framework initializing
10435 09:29:30.954211 <6>[ 0.034216] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10436 09:29:30.964046 <6>[ 0.042079] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10437 09:29:30.970810 <6>[ 0.051505] cblist_init_generic: Setting adjustable number of callback queues.
10438 09:29:30.977452 <6>[ 0.058949] cblist_init_generic: Setting shift to 3 and lim to 1.
10439 09:29:30.987587 <6>[ 0.065288] cblist_init_generic: Setting adjustable number of callback queues.
10440 09:29:30.993940 <6>[ 0.072715] cblist_init_generic: Setting shift to 3 and lim to 1.
10441 09:29:30.997182 <6>[ 0.079154] rcu: Hierarchical SRCU implementation.
10442 09:29:31.004096 <6>[ 0.084169] rcu: Max phase no-delay instances is 1000.
10443 09:29:31.010638 <6>[ 0.091194] EFI services will not be available.
10444 09:29:31.013830 <6>[ 0.096154] smp: Bringing up secondary CPUs ...
10445 09:29:31.021958 <6>[ 0.101233] Detected VIPT I-cache on CPU1
10446 09:29:31.028432 <6>[ 0.101304] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10447 09:29:31.035351 <6>[ 0.101335] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10448 09:29:31.038762 <6>[ 0.101675] Detected VIPT I-cache on CPU2
10449 09:29:31.045327 <6>[ 0.101727] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10450 09:29:31.055047 <6>[ 0.101745] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10451 09:29:31.058469 <6>[ 0.102004] Detected VIPT I-cache on CPU3
10452 09:29:31.064944 <6>[ 0.102051] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10453 09:29:31.071986 <6>[ 0.102066] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10454 09:29:31.075381 <6>[ 0.102371] CPU features: detected: Spectre-v4
10455 09:29:31.081532 <6>[ 0.102377] CPU features: detected: Spectre-BHB
10456 09:29:31.085411 <6>[ 0.102382] Detected PIPT I-cache on CPU4
10457 09:29:31.091763 <6>[ 0.102441] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10458 09:29:31.098317 <6>[ 0.102457] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10459 09:29:31.104998 <6>[ 0.102750] Detected PIPT I-cache on CPU5
10460 09:29:31.111614 <6>[ 0.102814] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10461 09:29:31.118006 <6>[ 0.102830] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10462 09:29:31.121280 <6>[ 0.103110] Detected PIPT I-cache on CPU6
10463 09:29:31.127889 <6>[ 0.103175] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10464 09:29:31.135002 <6>[ 0.103191] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10465 09:29:31.141185 <6>[ 0.103487] Detected PIPT I-cache on CPU7
10466 09:29:31.147856 <6>[ 0.103550] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10467 09:29:31.154816 <6>[ 0.103566] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10468 09:29:31.157847 <6>[ 0.103613] smp: Brought up 1 node, 8 CPUs
10469 09:29:31.164205 <6>[ 0.244889] SMP: Total of 8 processors activated.
10470 09:29:31.167411 <6>[ 0.249811] CPU features: detected: 32-bit EL0 Support
10471 09:29:31.177665 <6>[ 0.255174] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10472 09:29:31.184291 <6>[ 0.263975] CPU features: detected: Common not Private translations
10473 09:29:31.187388 <6>[ 0.270491] CPU features: detected: CRC32 instructions
10474 09:29:31.194486 <6>[ 0.275842] CPU features: detected: RCpc load-acquire (LDAPR)
10475 09:29:31.200876 <6>[ 0.281839] CPU features: detected: LSE atomic instructions
10476 09:29:31.207510 <6>[ 0.287656] CPU features: detected: Privileged Access Never
10477 09:29:31.210887 <6>[ 0.293471] CPU features: detected: RAS Extension Support
10478 09:29:31.221317 <6>[ 0.299080] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10479 09:29:31.224614 <6>[ 0.306344] CPU: All CPU(s) started at EL2
10480 09:29:31.230433 <6>[ 0.310661] alternatives: applying system-wide alternatives
10481 09:29:31.239474 <6>[ 0.321499] devtmpfs: initialized
10482 09:29:31.252106 <6>[ 0.330335] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10483 09:29:31.261788 <6>[ 0.340297] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10484 09:29:31.268189 <6>[ 0.348329] pinctrl core: initialized pinctrl subsystem
10485 09:29:31.272025 <6>[ 0.355017] DMI not present or invalid.
10486 09:29:31.278423 <6>[ 0.359430] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10487 09:29:31.288611 <6>[ 0.366192] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10488 09:29:31.295008 <6>[ 0.373786] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10489 09:29:31.304990 <6>[ 0.382010] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10490 09:29:31.308183 <6>[ 0.390251] audit: initializing netlink subsys (disabled)
10491 09:29:31.317971 <5>[ 0.395943] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10492 09:29:31.325202 <6>[ 0.396657] thermal_sys: Registered thermal governor 'step_wise'
10493 09:29:31.331721 <6>[ 0.403911] thermal_sys: Registered thermal governor 'power_allocator'
10494 09:29:31.335313 <6>[ 0.410164] cpuidle: using governor menu
10495 09:29:31.338346 <6>[ 0.421122] NET: Registered PF_QIPCRTR protocol family
10496 09:29:31.348297 <6>[ 0.426603] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10497 09:29:31.351318 <6>[ 0.433704] ASID allocator initialised with 32768 entries
10498 09:29:31.358459 <6>[ 0.440282] Serial: AMBA PL011 UART driver
10499 09:29:31.367604 <4>[ 0.449129] Trying to register duplicate clock ID: 134
10500 09:29:31.425937 <6>[ 0.510773] KASLR enabled
10501 09:29:31.440062 <6>[ 0.518478] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10502 09:29:31.446865 <6>[ 0.525492] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10503 09:29:31.453234 <6>[ 0.531981] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10504 09:29:31.459644 <6>[ 0.538985] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10505 09:29:31.466331 <6>[ 0.545474] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10506 09:29:31.472867 <6>[ 0.552479] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10507 09:29:31.479954 <6>[ 0.558965] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10508 09:29:31.486290 <6>[ 0.565968] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10509 09:29:31.489405 <6>[ 0.573493] ACPI: Interpreter disabled.
10510 09:29:31.498382 <6>[ 0.579924] iommu: Default domain type: Translated
10511 09:29:31.504745 <6>[ 0.585036] iommu: DMA domain TLB invalidation policy: strict mode
10512 09:29:31.508421 <5>[ 0.591697] SCSI subsystem initialized
10513 09:29:31.514848 <6>[ 0.595864] usbcore: registered new interface driver usbfs
10514 09:29:31.521537 <6>[ 0.601597] usbcore: registered new interface driver hub
10515 09:29:31.524791 <6>[ 0.607147] usbcore: registered new device driver usb
10516 09:29:31.531738 <6>[ 0.613243] pps_core: LinuxPPS API ver. 1 registered
10517 09:29:31.541717 <6>[ 0.618437] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10518 09:29:31.544942 <6>[ 0.627781] PTP clock support registered
10519 09:29:31.548468 <6>[ 0.632025] EDAC MC: Ver: 3.0.0
10520 09:29:31.555093 <6>[ 0.637180] FPGA manager framework
10521 09:29:31.561993 <6>[ 0.640866] Advanced Linux Sound Architecture Driver Initialized.
10522 09:29:31.565400 <6>[ 0.647636] vgaarb: loaded
10523 09:29:31.568906 <6>[ 0.650728] clocksource: Switched to clocksource arch_sys_counter
10524 09:29:31.575503 <5>[ 0.657165] VFS: Disk quotas dquot_6.6.0
10525 09:29:31.582750 <6>[ 0.661351] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10526 09:29:31.585678 <6>[ 0.668543] pnp: PnP ACPI: disabled
10527 09:29:31.593555 <6>[ 0.675270] NET: Registered PF_INET protocol family
10528 09:29:31.600998 <6>[ 0.680866] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10529 09:29:31.614884 <6>[ 0.693184] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10530 09:29:31.624667 <6>[ 0.701999] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10531 09:29:31.631583 <6>[ 0.709970] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10532 09:29:31.638119 <6>[ 0.718672] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10533 09:29:31.649942 <6>[ 0.728427] TCP: Hash tables configured (established 65536 bind 65536)
10534 09:29:31.656619 <6>[ 0.735289] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10535 09:29:31.663180 <6>[ 0.742490] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10536 09:29:31.670007 <6>[ 0.750193] NET: Registered PF_UNIX/PF_LOCAL protocol family
10537 09:29:31.676353 <6>[ 0.756352] RPC: Registered named UNIX socket transport module.
10538 09:29:31.679675 <6>[ 0.762506] RPC: Registered udp transport module.
10539 09:29:31.686828 <6>[ 0.767437] RPC: Registered tcp transport module.
10540 09:29:31.693279 <6>[ 0.772370] RPC: Registered tcp NFSv4.1 backchannel transport module.
10541 09:29:31.696540 <6>[ 0.779040] PCI: CLS 0 bytes, default 64
10542 09:29:31.700233 <6>[ 0.783368] Unpacking initramfs...
10543 09:29:31.724221 <6>[ 0.802852] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10544 09:29:31.734292 <6>[ 0.811504] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10545 09:29:31.737803 <6>[ 0.820353] kvm [1]: IPA Size Limit: 40 bits
10546 09:29:31.744278 <6>[ 0.824882] kvm [1]: GICv3: no GICV resource entry
10547 09:29:31.747385 <6>[ 0.829901] kvm [1]: disabling GICv2 emulation
10548 09:29:31.754156 <6>[ 0.834592] kvm [1]: GIC system register CPU interface enabled
10549 09:29:31.757481 <6>[ 0.840759] kvm [1]: vgic interrupt IRQ18
10550 09:29:31.763776 <6>[ 0.845110] kvm [1]: VHE mode initialized successfully
10551 09:29:31.771083 <5>[ 0.851589] Initialise system trusted keyrings
10552 09:29:31.776945 <6>[ 0.856396] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10553 09:29:31.784685 <6>[ 0.866373] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10554 09:29:31.791591 <5>[ 0.872762] NFS: Registering the id_resolver key type
10555 09:29:31.794578 <5>[ 0.878078] Key type id_resolver registered
10556 09:29:31.801295 <5>[ 0.882491] Key type id_legacy registered
10557 09:29:31.807723 <6>[ 0.886769] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10558 09:29:31.814406 <6>[ 0.893692] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10559 09:29:31.820775 <6>[ 0.901392] 9p: Installing v9fs 9p2000 file system support
10560 09:29:31.856800 <5>[ 0.938895] Key type asymmetric registered
10561 09:29:31.860471 <5>[ 0.943226] Asymmetric key parser 'x509' registered
10562 09:29:31.870353 <6>[ 0.948362] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10563 09:29:31.873751 <6>[ 0.955974] io scheduler mq-deadline registered
10564 09:29:31.877113 <6>[ 0.960765] io scheduler kyber registered
10565 09:29:31.895812 <6>[ 0.977579] EINJ: ACPI disabled.
10566 09:29:31.928356 <4>[ 1.003225] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10567 09:29:31.938017 <4>[ 1.013839] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10568 09:29:31.952696 <6>[ 1.034631] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10569 09:29:31.960869 <6>[ 1.042564] printk: console [ttyS0] disabled
10570 09:29:31.989020 <6>[ 1.067196] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10571 09:29:31.996129 <6>[ 1.076665] printk: console [ttyS0] enabled
10572 09:29:31.999120 <6>[ 1.076665] printk: console [ttyS0] enabled
10573 09:29:32.005084 <6>[ 1.085558] printk: bootconsole [mtk8250] disabled
10574 09:29:32.008800 <6>[ 1.085558] printk: bootconsole [mtk8250] disabled
10575 09:29:32.015243 <6>[ 1.096556] SuperH (H)SCI(F) driver initialized
10576 09:29:32.018515 <6>[ 1.101828] msm_serial: driver initialized
10577 09:29:32.032469 <6>[ 1.110676] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10578 09:29:32.042335 <6>[ 1.119222] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10579 09:29:32.049166 <6>[ 1.127767] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10580 09:29:32.058512 <6>[ 1.136394] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10581 09:29:32.068291 <6>[ 1.145099] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10582 09:29:32.075520 <6>[ 1.153813] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10583 09:29:32.085401 <6>[ 1.162352] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10584 09:29:32.091897 <6>[ 1.171145] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10585 09:29:32.101619 <6>[ 1.179688] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10586 09:29:32.113263 <6>[ 1.195134] loop: module loaded
10587 09:29:32.119633 <6>[ 1.201147] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10588 09:29:32.142651 <4>[ 1.224484] mtk-pmic-keys: Failed to locate of_node [id: -1]
10589 09:29:32.149383 <6>[ 1.231294] megasas: 07.719.03.00-rc1
10590 09:29:32.158857 <6>[ 1.240743] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10591 09:29:32.168442 <6>[ 1.250113] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10592 09:29:32.185172 <6>[ 1.266688] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10593 09:29:32.240719 <6>[ 1.316018] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10594 09:29:33.416864 <6>[ 2.498844] Freeing initrd memory: 40252K
10595 09:29:33.428382 <6>[ 2.510612] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10596 09:29:33.439269 <6>[ 2.521520] tun: Universal TUN/TAP device driver, 1.6
10597 09:29:33.442577 <6>[ 2.527582] thunder_xcv, ver 1.0
10598 09:29:33.445720 <6>[ 2.531086] thunder_bgx, ver 1.0
10599 09:29:33.449027 <6>[ 2.534576] nicpf, ver 1.0
10600 09:29:33.459460 <6>[ 2.538583] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10601 09:29:33.463281 <6>[ 2.546059] hns3: Copyright (c) 2017 Huawei Corporation.
10602 09:29:33.466453 <6>[ 2.551647] hclge is initializing
10603 09:29:33.472966 <6>[ 2.555226] e1000: Intel(R) PRO/1000 Network Driver
10604 09:29:33.479446 <6>[ 2.560355] e1000: Copyright (c) 1999-2006 Intel Corporation.
10605 09:29:33.483142 <6>[ 2.566371] e1000e: Intel(R) PRO/1000 Network Driver
10606 09:29:33.489565 <6>[ 2.571587] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10607 09:29:33.495961 <6>[ 2.577771] igb: Intel(R) Gigabit Ethernet Network Driver
10608 09:29:33.502431 <6>[ 2.583421] igb: Copyright (c) 2007-2014 Intel Corporation.
10609 09:29:33.509383 <6>[ 2.589257] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10610 09:29:33.515968 <6>[ 2.595774] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10611 09:29:33.519029 <6>[ 2.602238] sky2: driver version 1.30
10612 09:29:33.525917 <6>[ 2.607165] usbcore: registered new device driver r8152-cfgselector
10613 09:29:33.532558 <6>[ 2.613700] usbcore: registered new interface driver r8152
10614 09:29:33.539206 <6>[ 2.619518] VFIO - User Level meta-driver version: 0.3
10615 09:29:33.545839 <6>[ 2.627730] usbcore: registered new interface driver usb-storage
10616 09:29:33.552277 <6>[ 2.634173] usbcore: registered new device driver onboard-usb-hub
10617 09:29:33.560964 <6>[ 2.643310] mt6397-rtc mt6359-rtc: registered as rtc0
10618 09:29:33.571101 <6>[ 2.648776] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-18T09:28:08 UTC (1718702888)
10619 09:29:33.573896 <6>[ 2.658332] i2c_dev: i2c /dev entries driver
10620 09:29:33.588108 <4>[ 2.670353] cpu cpu0: supply cpu not found, using dummy regulator
10621 09:29:33.594555 <4>[ 2.676779] cpu cpu1: supply cpu not found, using dummy regulator
10622 09:29:33.601268 <4>[ 2.683196] cpu cpu2: supply cpu not found, using dummy regulator
10623 09:29:33.607822 <4>[ 2.689596] cpu cpu3: supply cpu not found, using dummy regulator
10624 09:29:33.614288 <4>[ 2.695996] cpu cpu4: supply cpu not found, using dummy regulator
10625 09:29:33.620854 <4>[ 2.702391] cpu cpu5: supply cpu not found, using dummy regulator
10626 09:29:33.627658 <4>[ 2.708789] cpu cpu6: supply cpu not found, using dummy regulator
10627 09:29:33.634072 <4>[ 2.715201] cpu cpu7: supply cpu not found, using dummy regulator
10628 09:29:33.653711 <6>[ 2.735849] cpu cpu0: EM: created perf domain
10629 09:29:33.656966 <6>[ 2.740786] cpu cpu4: EM: created perf domain
10630 09:29:33.664023 <6>[ 2.746092] sdhci: Secure Digital Host Controller Interface driver
10631 09:29:33.670486 <6>[ 2.752524] sdhci: Copyright(c) Pierre Ossman
10632 09:29:33.676888 <6>[ 2.757477] Synopsys Designware Multimedia Card Interface Driver
10633 09:29:33.683367 <6>[ 2.764118] sdhci-pltfm: SDHCI platform and OF driver helper
10634 09:29:33.686635 <6>[ 2.764159] mmc0: CQHCI version 5.10
10635 09:29:33.693456 <6>[ 2.774214] ledtrig-cpu: registered to indicate activity on CPUs
10636 09:29:33.700279 <6>[ 2.781337] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10637 09:29:33.706556 <6>[ 2.788398] usbcore: registered new interface driver usbhid
10638 09:29:33.710236 <6>[ 2.794218] usbhid: USB HID core driver
10639 09:29:33.716781 <6>[ 2.798403] spi_master spi0: will run message pump with realtime priority
10640 09:29:33.767440 <6>[ 2.843380] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10641 09:29:33.788429 <6>[ 2.860642] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10642 09:29:33.792196 <6>[ 2.870967] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15414
10643 09:29:33.799151 <6>[ 2.877352] cros-ec-spi spi0.0: Chrome EC device registered
10644 09:29:33.802399 <6>[ 2.886053] mmc0: Command Queue Engine enabled
10645 09:29:33.808592 <6>[ 2.890787] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10646 09:29:33.816011 <6>[ 2.898263] mmcblk0: mmc0:0001 DA4128 116 GiB
10647 09:29:33.826015 <6>[ 2.900895] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10648 09:29:33.832493 <6>[ 2.907728] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10649 09:29:33.835584 <6>[ 2.913212] NET: Registered PF_PACKET protocol family
10650 09:29:33.842439 <6>[ 2.919651] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10651 09:29:33.845920 <6>[ 2.923611] 9pnet: Installing 9P2000 support
10652 09:29:33.852262 <6>[ 2.929378] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10653 09:29:33.855455 <5>[ 2.933278] Key type dns_resolver registered
10654 09:29:33.862093 <6>[ 2.939149] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10655 09:29:33.865453 <6>[ 2.943494] registered taskstats version 1
10656 09:29:33.871830 <5>[ 2.953877] Loading compiled-in X.509 certificates
10657 09:29:33.901861 <4>[ 2.977525] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10658 09:29:33.911601 <4>[ 2.988243] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10659 09:29:33.925863 <6>[ 3.008388] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10660 09:29:33.933100 <6>[ 3.015225] xhci-mtk 11200000.usb: xHCI Host Controller
10661 09:29:33.939288 <6>[ 3.020731] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10662 09:29:33.949614 <6>[ 3.028580] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10663 09:29:33.955952 <6>[ 3.038011] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10664 09:29:33.962920 <6>[ 3.044203] xhci-mtk 11200000.usb: xHCI Host Controller
10665 09:29:33.969490 <6>[ 3.049701] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10666 09:29:33.975850 <6>[ 3.057358] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10667 09:29:33.982819 <6>[ 3.065198] hub 1-0:1.0: USB hub found
10668 09:29:33.986072 <6>[ 3.069226] hub 1-0:1.0: 1 port detected
10669 09:29:33.996161 <6>[ 3.073543] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10670 09:29:33.999431 <6>[ 3.082311] hub 2-0:1.0: USB hub found
10671 09:29:34.002503 <6>[ 3.086336] hub 2-0:1.0: 1 port detected
10672 09:29:34.011500 <6>[ 3.094185] mtk-msdc 11f70000.mmc: Got CD GPIO
10673 09:29:34.030952 <6>[ 3.109953] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10674 09:29:34.041171 <6>[ 3.118341] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10675 09:29:34.047446 <6>[ 3.126682] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10676 09:29:34.057678 <6>[ 3.135022] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10677 09:29:34.064240 <6>[ 3.143359] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10678 09:29:34.074057 <6>[ 3.151699] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10679 09:29:34.080379 <6>[ 3.160038] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10680 09:29:34.090422 <6>[ 3.168376] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10681 09:29:34.097126 <6>[ 3.176714] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10682 09:29:34.107259 <6>[ 3.185052] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10683 09:29:34.113706 <6>[ 3.193393] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10684 09:29:34.123844 <6>[ 3.201731] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10685 09:29:34.130296 <6>[ 3.210071] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10686 09:29:34.140129 <6>[ 3.218410] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10687 09:29:34.146846 <6>[ 3.226748] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10688 09:29:34.153620 <6>[ 3.235415] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10689 09:29:34.160152 <6>[ 3.242574] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10690 09:29:34.166691 <6>[ 3.249350] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10691 09:29:34.173831 <6>[ 3.256109] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10692 09:29:34.184005 <6>[ 3.263038] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10693 09:29:34.190886 <6>[ 3.269905] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10694 09:29:34.200502 <6>[ 3.279038] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10695 09:29:34.210603 <6>[ 3.288157] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10696 09:29:34.220373 <6>[ 3.297450] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10697 09:29:34.230636 <6>[ 3.306917] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10698 09:29:34.237079 <6>[ 3.316384] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10699 09:29:34.246810 <6>[ 3.325504] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10700 09:29:34.256865 <6>[ 3.334970] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10701 09:29:34.266856 <6>[ 3.344089] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10702 09:29:34.276665 <6>[ 3.353388] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10703 09:29:34.286827 <6>[ 3.363549] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10704 09:29:34.296572 <6>[ 3.374692] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10705 09:29:34.392295 <6>[ 3.471211] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10706 09:29:34.419605 <6>[ 3.501980] hub 2-1:1.0: USB hub found
10707 09:29:34.422874 <6>[ 3.506417] hub 2-1:1.0: 3 ports detected
10708 09:29:34.432145 <6>[ 3.514605] hub 2-1:1.0: USB hub found
10709 09:29:34.435433 <6>[ 3.519053] hub 2-1:1.0: 3 ports detected
10710 09:29:34.544019 <6>[ 3.623036] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10711 09:29:34.698000 <6>[ 3.780166] hub 1-1:1.0: USB hub found
10712 09:29:34.700652 <6>[ 3.784621] hub 1-1:1.0: 4 ports detected
10713 09:29:34.712988 <6>[ 3.795428] hub 1-1:1.0: USB hub found
10714 09:29:34.716281 <6>[ 3.799925] hub 1-1:1.0: 4 ports detected
10715 09:29:34.783790 <6>[ 3.863128] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10716 09:29:34.892199 <6>[ 3.971478] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10717 09:29:34.924087 <4>[ 4.003181] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10718 09:29:34.933747 <4>[ 4.012344] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10719 09:29:34.973268 <6>[ 4.056001] r8152 2-1.3:1.0 eth0: v1.12.13
10720 09:29:35.047742 <6>[ 4.127046] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10721 09:29:35.179551 <6>[ 4.262305] hub 1-1.4:1.0: USB hub found
10722 09:29:35.182905 <6>[ 4.266841] hub 1-1.4:1.0: 2 ports detected
10723 09:29:35.197176 <6>[ 4.279603] hub 1-1.4:1.0: USB hub found
10724 09:29:35.200416 <6>[ 4.284194] hub 1-1.4:1.0: 2 ports detected
10725 09:29:35.495999 <6>[ 4.575043] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10726 09:29:35.687649 <6>[ 4.767046] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10727 09:29:36.658255 <6>[ 5.741153] r8152 2-1.3:1.0 eth0: carrier on
10728 09:29:39.407922 <5>[ 5.762752] Sending DHCP requests .., OK
10729 09:29:39.414869 <6>[ 8.495190] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10730 09:29:39.418161 <6>[ 8.503481] IP-Config: Complete:
10731 09:29:39.431288 <6>[ 8.506983] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10732 09:29:39.438047 <6>[ 8.517702] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10733 09:29:39.444640 <6>[ 8.526350] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10734 09:29:39.451213 <6>[ 8.526359] nameserver0=192.168.201.1
10735 09:29:39.454287 <6>[ 8.538527] clk: Disabling unused clocks
10736 09:29:39.457511 <6>[ 8.544094] ALSA device list:
10737 09:29:39.464451 <6>[ 8.547372] No soundcards found.
10738 09:29:39.471975 <6>[ 8.555120] Freeing unused kernel memory: 8512K
10739 09:29:39.475228 <6>[ 8.560032] Run /init as init process
10740 09:29:39.505577 <6>[ 8.588627] NET: Registered PF_INET6 protocol family
10741 09:29:39.512316 <6>[ 8.595459] Segment Routing with IPv6
10742 09:29:39.515876 <6>[ 8.599405] In-situ OAM (IOAM) with IPv6
10743 09:29:39.560707 <30>[ 8.617298] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10744 09:29:39.567167 <30>[ 8.650366] systemd[1]: Detected architecture arm64.
10745 09:29:39.567252
10746 09:29:39.574149 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10747 09:29:39.574232
10748 09:29:39.588142 <30>[ 8.671172] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10749 09:29:39.718536 <30>[ 8.798573] systemd[1]: Queued start job for default target graphical.target.
10750 09:29:39.764804 <30>[ 8.844674] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10751 09:29:39.771274 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10752 09:29:39.791952 <30>[ 8.871862] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10753 09:29:39.802079 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10754 09:29:39.820509 <30>[ 8.900083] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10755 09:29:39.830383 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10756 09:29:39.848669 <30>[ 8.928210] systemd[1]: Created slice user.slice - User and Session Slice.
10757 09:29:39.854836 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10758 09:29:39.874678 <30>[ 8.951053] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10759 09:29:39.881370 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10760 09:29:39.903074 <30>[ 8.979593] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10761 09:29:39.910051 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10762 09:29:39.937212 <30>[ 9.007070] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10763 09:29:39.947509 <30>[ 9.026863] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10764 09:29:39.953860 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10765 09:29:39.972081 <30>[ 9.051359] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10766 09:29:39.978394 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10767 09:29:39.995560 <30>[ 9.075031] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10768 09:29:40.004760 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10769 09:29:40.020516 <30>[ 9.103565] systemd[1]: Reached target paths.target - Path Units.
10770 09:29:40.027491 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10771 09:29:40.047522 <30>[ 9.127452] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10772 09:29:40.054134 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10773 09:29:40.070967 <30>[ 9.150971] systemd[1]: Reached target slices.target - Slice Units.
10774 09:29:40.077999 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10775 09:29:40.092453 <30>[ 9.175506] systemd[1]: Reached target swap.target - Swaps.
10776 09:29:40.098942 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10777 09:29:40.119571 <30>[ 9.199523] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10778 09:29:40.129757 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10779 09:29:40.147624 <30>[ 9.227433] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10780 09:29:40.157539 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10781 09:29:40.177117 <30>[ 9.257106] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10782 09:29:40.187313 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10783 09:29:40.204073 <30>[ 9.283798] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10784 09:29:40.214174 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10785 09:29:40.232042 <30>[ 9.311660] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10786 09:29:40.238543 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10787 09:29:40.256010 <30>[ 9.335736] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10788 09:29:40.265572 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10789 09:29:40.284791 <30>[ 9.364454] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10790 09:29:40.294428 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10791 09:29:40.312750 <30>[ 9.392315] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10792 09:29:40.322401 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10793 09:29:40.366911 <30>[ 9.447028] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10794 09:29:40.373871 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10795 09:29:40.393120 <30>[ 9.472922] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10796 09:29:40.399622 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10797 09:29:40.426887 <30>[ 9.506862] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10798 09:29:40.433510 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10799 09:29:40.462153 <30>[ 9.535443] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10800 09:29:40.475323 <30>[ 9.555269] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10801 09:29:40.485313 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10802 09:29:40.512015 <30>[ 9.591872] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10803 09:29:40.518618 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10804 09:29:40.548167 <30>[ 9.627902] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10805 09:29:40.561170 Starting [0;1;39mmodpr<6>[ 9.638704] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10806 09:29:40.564434 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10807 09:29:40.588358 <30>[ 9.668067] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10808 09:29:40.594516 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10809 09:29:40.620442 <30>[ 9.700459] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10810 09:29:40.630369 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10811 09:29:40.652185 <30>[ 9.731833] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10812 09:29:40.658670 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10813 09:29:40.732147 <30>[ 9.811646] systemd[1]: Starting systemd-journald.service - Journal Service...
10814 09:29:40.738272 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10815 09:29:40.758468 <30>[ 9.838477] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10816 09:29:40.765445 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10817 09:29:40.789991 <30>[ 9.866213] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10818 09:29:40.796312 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10819 09:29:40.819223 <30>[ 9.899228] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10820 09:29:40.828996 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10821 09:29:40.850235 <30>[ 9.930021] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10822 09:29:40.856507 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10823 09:29:40.879415 <30>[ 9.959657] systemd[1]: Started systemd-journald.service - Journal Service.
10824 09:29:40.886374 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10825 09:29:40.905752 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10826 09:29:40.924329 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10827 09:29:40.943944 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10828 09:29:40.964931 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10829 09:29:40.990192 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10830 09:29:41.013197 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10831 09:29:41.038562 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10832 09:29:41.061956 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10833 09:29:41.089674 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10834 09:29:41.113563 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10835 09:29:41.132511 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10836 09:29:41.153806 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10837 09:29:41.171872 See 'systemctl status systemd-remount-fs.service' for details.
10838 09:29:41.196559 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10839 09:29:41.221718 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10840 09:29:41.272028 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10841 09:29:41.292668 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10842 09:29:41.311111 <46>[ 10.391135] systemd-journald[189]: Received client request to flush runtime journal.
10843 09:29:41.323266 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10844 09:29:41.343522 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10845 09:29:41.367178 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10846 09:29:41.397978 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10847 09:29:41.417105 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10848 09:29:41.436858 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10849 09:29:41.456750 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10850 09:29:41.475433 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10851 09:29:41.507368 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10852 09:29:41.529999 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10853 09:29:41.546976 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10854 09:29:41.563145 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10855 09:29:41.603426 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10856 09:29:41.624242 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10857 09:29:41.655438 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10858 09:29:41.699827 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10859 09:29:41.721341 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10860 09:29:41.743782 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10861 09:29:41.768439 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10862 09:29:41.812275 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10863 09:29:41.834066 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10864 09:29:41.929212 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10865 09:29:41.952156 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10866 09:29:41.972343 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10867 09:29:41.992277 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10868 09:29:42.012208 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10869 09:29:42.029915 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10870 09:29:42.036306 <6>[ 11.117517] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10871 09:29:42.053807 [[0;32m OK [0m] Reached targ<6>[ 11.132467] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10872 09:29:42.060630 et [0;1;39msock<6>[ 11.142235] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10873 09:29:42.073580 ets.target[0m -<4>[ 11.151288] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10874 09:29:42.073666 Socket Units.
10875 09:29:42.083895 <3>[ 11.161288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 09:29:42.090316 <6>[ 11.161527] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10877 09:29:42.096760 <3>[ 11.170440] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 09:29:42.107017 <6>[ 11.178561] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10879 09:29:42.113593 <3>[ 11.186740] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10880 09:29:42.113671
10881 09:29:42.123437 <6>[ 11.192628] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10882 09:29:42.129981 <6>[ 11.192663] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10883 09:29:42.139834 <6>[ 11.192673] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10884 09:29:42.146978 <6>[ 11.202883] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10885 09:29:42.153615 <6>[ 11.214172] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10886 09:29:42.163270 <6>[ 11.219172] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10887 09:29:42.169744 <3>[ 11.232057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10888 09:29:42.180022 <6>[ 11.235658] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10889 09:29:42.186542 <6>[ 11.235664] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10890 09:29:42.196115 <3>[ 11.242963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10891 09:29:42.199969 <6>[ 11.260931] remoteproc remoteproc0: scp is available
10892 09:29:42.209673 <3>[ 11.266708] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10893 09:29:42.216109 <3>[ 11.266714] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10894 09:29:42.226433 <3>[ 11.266718] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10895 09:29:42.232887 <3>[ 11.280982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10896 09:29:42.239329 <6>[ 11.284086] remoteproc remoteproc0: powering up scp
10897 09:29:42.246342 <3>[ 11.291188] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10898 09:29:42.255969 <6>[ 11.297383] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10899 09:29:42.262960 <3>[ 11.305646] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10900 09:29:42.269443 <6>[ 11.313578] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10901 09:29:42.275752 <3>[ 11.321716] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10902 09:29:42.282467 <6>[ 11.339871] mc: Linux media interface: v0.10
10903 09:29:42.289396 <6>[ 11.345577] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10904 09:29:42.295691 <6>[ 11.347336] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10905 09:29:42.302686 <6>[ 11.347354] pci_bus 0000:00: root bus resource [bus 00-ff]
10906 09:29:42.309241 <6>[ 11.347367] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10907 09:29:42.319358 <6>[ 11.347375] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10908 09:29:42.325882 <6>[ 11.347464] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10909 09:29:42.332269 <6>[ 11.347493] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10910 09:29:42.335511 <6>[ 11.347600] pci 0000:00:00.0: supports D1 D2
10911 09:29:42.341992 <6>[ 11.347606] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10912 09:29:42.352082 <4>[ 11.356736] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10913 09:29:42.358985 <6>[ 11.357026] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10914 09:29:42.368775 <3>[ 11.357577] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 09:29:42.375276 <6>[ 11.357624] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10916 09:29:42.381951 <6>[ 11.357654] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10917 09:29:42.388764 <6>[ 11.357675] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10918 09:29:42.395289 <6>[ 11.357690] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10919 09:29:42.401761 <6>[ 11.357821] pci 0000:01:00.0: supports D1 D2
10920 09:29:42.408310 <6>[ 11.357823] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10921 09:29:42.414884 <4>[ 11.390407] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10922 09:29:42.425045 <4>[ 11.390774] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10923 09:29:42.428329 <4>[ 11.390774] Fallback method does not support PEC.
10924 09:29:42.438510 <3>[ 11.397205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10925 09:29:42.444905 <6>[ 11.429516] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10926 09:29:42.454849 <6>[ 11.432092] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10927 09:29:42.461382 <3>[ 11.432219] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10928 09:29:42.471453 <3>[ 11.432232] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10929 09:29:42.477979 <6>[ 11.439720] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10930 09:29:42.488005 <3>[ 11.447777] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10931 09:29:42.494429 <6>[ 11.452056] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10932 09:29:42.500971 <6>[ 11.455870] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10933 09:29:42.507927 <6>[ 11.455878] remoteproc remoteproc0: remote processor scp is now up
10934 09:29:42.517565 <6>[ 11.456103] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10935 09:29:42.520865 <6>[ 11.457999] videodev: Linux video capture interface: v2.00
10936 09:29:42.531190 <6>[ 11.460590] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10937 09:29:42.537709 <3>[ 11.460850] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10938 09:29:42.547795 <6>[ 11.514818] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10939 09:29:42.557917 <6>[ 11.517142] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10940 09:29:42.563998 <6>[ 11.546155] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10941 09:29:42.574044 <5>[ 11.548055] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10942 09:29:42.581107 <6>[ 11.552014] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10943 09:29:42.584311 <6>[ 11.559471] Bluetooth: Core ver 2.22
10944 09:29:42.594348 <6>[ 11.565136] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10945 09:29:42.600567 <6>[ 11.566661] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10946 09:29:42.607124 <5>[ 11.569815] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10947 09:29:42.617475 <5>[ 11.570320] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10948 09:29:42.623941 <4>[ 11.570452] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10949 09:29:42.630344 <6>[ 11.570462] cfg80211: failed to load regulatory.db
10950 09:29:42.634109 <6>[ 11.574825] NET: Registered PF_BLUETOOTH protocol family
10951 09:29:42.643970 <6>[ 11.575731] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10952 09:29:42.653563 <6>[ 11.577043] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10953 09:29:42.660488 <6>[ 11.577249] usbcore: registered new interface driver uvcvideo
10954 09:29:42.667005 <6>[ 11.581796] pci 0000:00:00.0: PCI bridge to [bus 01]
10955 09:29:42.673445 <6>[ 11.590289] Bluetooth: HCI device and connection manager initialized
10956 09:29:42.676907 <6>[ 11.590312] Bluetooth: HCI socket layer initialized
10957 09:29:42.686662 <6>[ 11.596722] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10958 09:29:42.690464 <6>[ 11.604714] Bluetooth: L2CAP socket layer initialized
10959 09:29:42.696772 <6>[ 11.610699] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10960 09:29:42.703342 <6>[ 11.619490] Bluetooth: SCO socket layer initialized
10961 09:29:42.709778 <6>[ 11.620061] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10962 09:29:42.716847 <6>[ 11.628073] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10963 09:29:42.720108 <6>[ 11.704780] usbcore: registered new interface driver btusb
10964 09:29:42.729884 <4>[ 11.705686] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10965 09:29:42.736335 <3>[ 11.705697] Bluetooth: hci0: Failed to load firmware file (-2)
10966 09:29:42.743333 <3>[ 11.705701] Bluetooth: hci0: Failed to set up firmware (-2)
10967 09:29:42.753016 <4>[ 11.705705] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10968 09:29:42.759457 <6>[ 11.713445] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10969 09:29:42.766471 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10970 09:29:42.792125 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10971 09:29:42.811024 <6>[ 11.891006] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10972 09:29:42.817621 <6>[ 11.898520] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10973 09:29:42.827422 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10974 09:29:42.841428 <6>[ 11.925033] mt7921e 0000:01:00.0: ASIC revision: 79610010
10975 09:29:42.858115 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10976 09:29:42.875425 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10977 09:29:42.895996 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10978 09:29:42.950068 <6>[ 12.030206] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10979 09:29:42.953386 <6>[ 12.030206]
10980 09:29:42.959867 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10981 09:29:42.979939 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10982 09:29:43.001523 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10983 09:29:43.021485 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10984 09:29:43.041483 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10985 09:29:43.101381 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10986 09:29:43.125791 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10987 09:29:43.148510 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10988 09:29:43.169519 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10989 09:29:43.217268 <6>[ 12.297663] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10990 09:29:43.240031 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10991 09:29:43.261534 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10992 09:29:43.278232 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10993 09:29:43.293446 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10994 09:29:43.309970 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10995 09:29:43.370965 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10996 09:29:43.394537 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10997 09:29:43.420330 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10998 09:29:43.456896 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10999 09:29:43.505695
11000 09:29:43.508946 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11001 09:29:43.509551
11002 09:29:43.511789 debian-bookworm-arm64 login: root (automatic login)
11003 09:29:43.512263
11004 09:29:43.526586 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
11005 09:29:43.527153
11006 09:29:43.532927 The programs included with the Debian GNU/Linux system are free software;
11007 09:29:43.539533 the exact distribution terms for each program are described in the
11008 09:29:43.542823 individual files in /usr/share/doc/*/copyright.
11009 09:29:43.543298
11010 09:29:43.549840 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11011 09:29:43.552985 permitted by applicable law.
11012 09:29:43.554417 Matched prompt #10: / #
11014 09:29:43.555555 Setting prompt string to ['/ #']
11015 09:29:43.556031 end: 2.2.5.1 login-action (duration 00:00:13) [common]
11017 09:29:43.557239 end: 2.2.5 auto-login-action (duration 00:00:13) [common]
11018 09:29:43.557754 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
11019 09:29:43.558159 Setting prompt string to ['/ #']
11020 09:29:43.558537 Forcing a shell prompt, looking for ['/ #']
11022 09:29:43.609486 / #
11023 09:29:43.610158 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11024 09:29:43.610617 Waiting using forced prompt support (timeout 00:02:30)
11025 09:29:43.615598
11026 09:29:43.616542 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11027 09:29:43.617126 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
11028 09:29:43.617639 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11029 09:29:43.618132 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
11030 09:29:43.618594 end: 2 depthcharge-action (duration 00:01:23) [common]
11031 09:29:43.619087 start: 3 lava-test-retry (timeout 00:08:16) [common]
11032 09:29:43.619559 start: 3.1 lava-test-shell (timeout 00:08:16) [common]
11033 09:29:43.619978 Using namespace: common
11035 09:29:43.721240 / # #
11036 09:29:43.721890 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11037 09:29:43.727881 #
11038 09:29:43.728761 Using /lava-14407641
11040 09:29:43.829918 / # export SHELL=/bin/sh
11041 09:29:43.836507 export SHELL=/bin/sh
11043 09:29:43.938240 / # . /lava-14407641/environment
11044 09:29:43.944382 . /lava-14407641/environment
11046 09:29:44.046394 / # /lava-14407641/bin/lava-test-runner /lava-14407641/0
11047 09:29:44.047111 Test shell timeout: 10s (minimum of the action and connection timeout)
11048 09:29:44.052287 /lava-14407641/bin/lava-test-runner /lava-14407641/0
11049 09:29:44.077343 + export TESTRUN<6>[ 13.157960] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11050 09:29:44.081057 _ID=0_v4l2-compliance-mtk-vcodec-enc
11051 09:29:44.084114 + cd /lava-14407641/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11052 09:29:44.087592 + cat uuid
11053 09:29:44.088070 + UUID=14407641_1.5.2.3.1
11054 09:29:44.090603 + set +x
11055 09:29:44.097723 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 14407641_1.5.2.3.1>
11056 09:29:44.098630 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 14407641_1.5.2.3.1
11057 09:29:44.099067 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (14407641_1.5.2.3.1)
11058 09:29:44.099512 Skipping test definition patterns.
11059 09:29:44.100361 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11060 09:29:44.103899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11061 09:29:44.104766 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11063 09:29:44.113727 d<4>[ 13.193458] use of bytesused == 0 is deprecated and will be removed in the future,
11064 09:29:44.120395 evice: /dev/vide<4>[ 13.201470] use the actual size instead.
11065 09:29:44.120996 o2
11066 09:29:44.135378 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11067 09:29:44.148130 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11068 09:29:44.155110
11069 09:29:44.167372 Compliance test for mtk-vcodec-enc device /dev/video2:
11070 09:29:44.177138
11071 09:29:44.188246 Driver Info:
11072 09:29:44.198651 Driver name : mtk-vcodec-enc
11073 09:29:44.215425 Card type : MT8192 video encoder
11074 09:29:44.226695 Bus info : platform:17020000.vcodec
11075 09:29:44.235161 Driver version : 6.1.92
11076 09:29:44.246549 Capabilities : 0x84204000
11077 09:29:44.261924 Video Memory-to-Memory Multiplanar
11078 09:29:44.272718 Streaming
11079 09:29:44.284071 Extended Pix Format
11080 09:29:44.292718 Device Capabilities
11081 09:29:44.303752 Device Caps : 0x04204000
11082 09:29:44.315305 Video Memory-to-Memory Multiplanar
11083 09:29:44.325935 Streaming
11084 09:29:44.340389 Extended Pix Format
11085 09:29:44.350747 Detected Stateful Encoder
11086 09:29:44.364577
11087 09:29:44.376113 Required ioctls:
11088 09:29:44.390980 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11089 09:29:44.391547 test VIDIOC_QUERYCAP: OK
11090 09:29:44.392195 Received signal: <TESTSET> START Required-ioctls
11091 09:29:44.392624 Starting test_set Required-ioctls
11092 09:29:44.421363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11093 09:29:44.421923 test invalid ioctls: OK
11094 09:29:44.422553 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11096 09:29:44.442763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11097 09:29:44.443279
11098 09:29:44.443868 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11100 09:29:44.453103 Allow for multiple opens:
11101 09:29:44.458629 <LAVA_SIGNAL_TESTSET STOP>
11102 09:29:44.459346 Received signal: <TESTSET> STOP
11103 09:29:44.459748 Closing test_set Required-ioctls
11104 09:29:44.468793 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11105 09:29:44.469638 Received signal: <TESTSET> START Allow-for-multiple-opens
11106 09:29:44.470033 Starting test_set Allow-for-multiple-opens
11107 09:29:44.471496 test second /dev/video2 open: OK
11108 09:29:44.492126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11109 09:29:44.492489 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11111 09:29:44.494996 test VIDIOC_QUERYCAP: OK
11112 09:29:44.518632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11113 09:29:44.519036 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11115 09:29:44.522183 test VIDIOC_G/S_PRIORITY: OK
11116 09:29:44.540789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11117 09:29:44.541294 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11119 09:29:44.544596 test for unlimited opens: OK
11120 09:29:44.565243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11121 09:29:44.565805
11122 09:29:44.566437 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11124 09:29:44.574015 Debug ioctls:
11125 09:29:44.580986 <LAVA_SIGNAL_TESTSET STOP>
11126 09:29:44.581801 Received signal: <TESTSET> STOP
11127 09:29:44.582161 Closing test_set Allow-for-multiple-opens
11128 09:29:44.591046 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11129 09:29:44.591924 Received signal: <TESTSET> START Debug-ioctls
11130 09:29:44.592460 Starting test_set Debug-ioctls
11131 09:29:44.593397 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11132 09:29:44.620052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11133 09:29:44.620838 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11135 09:29:44.627055 test VIDIOC_LOG_STATUS: OK (Not Supported)
11136 09:29:44.645677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11137 09:29:44.646162
11138 09:29:44.646746 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11140 09:29:44.656067 Input ioctls:
11141 09:29:44.666025 <LAVA_SIGNAL_TESTSET STOP>
11142 09:29:44.666823 Received signal: <TESTSET> STOP
11143 09:29:44.667261 Closing test_set Debug-ioctls
11144 09:29:44.676864 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11145 09:29:44.677606 Received signal: <TESTSET> START Input-ioctls
11146 09:29:44.677968 Starting test_set Input-ioctls
11147 09:29:44.680238 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11148 09:29:44.706465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11149 09:29:44.707332 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11151 09:29:44.710066 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11152 09:29:44.729826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11153 09:29:44.730580 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11155 09:29:44.736466 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11156 09:29:44.753475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11157 09:29:44.754259 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11159 09:29:44.759981 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11160 09:29:44.778277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11161 09:29:44.779082 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11163 09:29:44.781474 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11164 09:29:44.807509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11165 09:29:44.808305 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11167 09:29:44.811394 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11168 09:29:44.837394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11169 09:29:44.838201 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11171 09:29:44.840457 Inputs: 0 Audio Inputs: 0 Tuners: 0
11172 09:29:44.846305
11173 09:29:44.863581 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11174 09:29:44.888981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11175 09:29:44.889723 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11177 09:29:44.895475 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11178 09:29:44.917073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11179 09:29:44.917828 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11181 09:29:44.923748 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11182 09:29:44.941575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11183 09:29:44.942376 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11185 09:29:44.948373 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11186 09:29:44.967252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11187 09:29:44.968032 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11189 09:29:44.974084 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11190 09:29:44.992264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11191 09:29:44.993105 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11193 09:29:44.995647
11194 09:29:45.013565 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11195 09:29:45.039975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11196 09:29:45.040742 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11198 09:29:45.046463 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11199 09:29:45.067788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11200 09:29:45.068580 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11202 09:29:45.070840 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11203 09:29:45.095085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11204 09:29:45.095775 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11206 09:29:45.098325 test VIDIOC_G/S_EDID: OK (Not Supported)
11207 09:29:45.124029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11208 09:29:45.124831
11209 09:29:45.125649 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11211 09:29:45.134427 Control ioctls:
11212 09:29:45.143612 <LAVA_SIGNAL_TESTSET STOP>
11213 09:29:45.144373 Received signal: <TESTSET> STOP
11214 09:29:45.144756 Closing test_set Input-ioctls
11215 09:29:45.155254 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11216 09:29:45.156021 Received signal: <TESTSET> START Control-ioctls
11217 09:29:45.156389 Starting test_set Control-ioctls
11218 09:29:45.158389 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11219 09:29:45.182998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11220 09:29:45.183551 test VIDIOC_QUERYCTRL: OK
11221 09:29:45.184160 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11223 09:29:45.204313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11224 09:29:45.205114 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11226 09:29:45.207839 test VIDIOC_G/S_CTRL: OK
11227 09:29:45.233825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11228 09:29:45.234570 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11230 09:29:45.237233 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11231 09:29:45.257991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11232 09:29:45.258751 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11234 09:29:45.264472 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11235 09:29:45.271770 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11236 09:29:45.296906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11237 09:29:45.297684 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11239 09:29:45.300006 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11240 09:29:45.318276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11241 09:29:45.319040 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11243 09:29:45.322262 Standard Controls: 16 Private Controls: 0
11244 09:29:45.329300
11245 09:29:45.339028 Format ioctls:
11246 09:29:45.346439 <LAVA_SIGNAL_TESTSET STOP>
11247 09:29:45.347274 Received signal: <TESTSET> STOP
11248 09:29:45.347634 Closing test_set Control-ioctls
11249 09:29:45.356003 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11250 09:29:45.356803 Received signal: <TESTSET> START Format-ioctls
11251 09:29:45.357177 Starting test_set Format-ioctls
11252 09:29:45.359026 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11253 09:29:45.385796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11254 09:29:45.386542 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11256 09:29:45.389033 test VIDIOC_G/S_PARM: OK
11257 09:29:45.408408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11258 09:29:45.409199 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11260 09:29:45.411937 test VIDIOC_G_FBUF: OK (Not Supported)
11261 09:29:45.433038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11262 09:29:45.433790 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11264 09:29:45.436114 test VIDIOC_G_FMT: OK
11265 09:29:45.460454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11266 09:29:45.461303 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11268 09:29:45.463375 test VIDIOC_TRY_FMT: OK
11269 09:29:45.484840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11270 09:29:45.485638 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11272 09:29:45.491537 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11273 09:29:45.495905 test VIDIOC_S_FMT: FAIL
11274 09:29:45.523187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11275 09:29:45.524035 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11277 09:29:45.525981 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11278 09:29:45.548809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11279 09:29:45.549730 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11281 09:29:45.552466 test Cropping: OK
11282 09:29:45.573780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11283 09:29:45.574584 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11285 09:29:45.576817 test Composing: OK (Not Supported)
11286 09:29:45.598805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11287 09:29:45.599737 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11289 09:29:45.601975 test Scaling: OK (Not Supported)
11290 09:29:45.622839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11291 09:29:45.623374
11292 09:29:45.623975 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11294 09:29:45.632294 Codec ioctls:
11295 09:29:45.641581 <LAVA_SIGNAL_TESTSET STOP>
11296 09:29:45.642345 Received signal: <TESTSET> STOP
11297 09:29:45.642700 Closing test_set Format-ioctls
11298 09:29:45.652538 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11299 09:29:45.653372 Received signal: <TESTSET> START Codec-ioctls
11300 09:29:45.653740 Starting test_set Codec-ioctls
11301 09:29:45.656027 test VIDIOC_(TRY_)ENCODER_CMD: OK
11302 09:29:45.678070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11303 09:29:45.678803 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11305 09:29:45.684690 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11306 09:29:45.702186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11307 09:29:45.702926 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11309 09:29:45.708833 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11310 09:29:45.726084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11311 09:29:45.726515
11312 09:29:45.727099 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11314 09:29:45.736359 Buffer ioctls:
11315 09:29:45.743598 <LAVA_SIGNAL_TESTSET STOP>
11316 09:29:45.744276 Received signal: <TESTSET> STOP
11317 09:29:45.744687 Closing test_set Codec-ioctls
11318 09:29:45.753374 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11319 09:29:45.754188 Received signal: <TESTSET> START Buffer-ioctls
11320 09:29:45.754563 Starting test_set Buffer-ioctls
11321 09:29:45.756736 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11322 09:29:45.781012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11323 09:29:45.781785 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11325 09:29:45.784343 test CREATE_BUFS maximum buffers: OK
11326 09:29:45.806161 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11328 09:29:45.809097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11329 09:29:45.809525 test VIDIOC_EXPBUF: OK
11330 09:29:45.835766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11331 09:29:45.836590 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11333 09:29:45.838843 test Requests: OK (Not Supported)
11334 09:29:45.859118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11335 09:29:45.859612
11336 09:29:45.860197 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11338 09:29:45.869927 Test input 0:
11339 09:29:45.881066
11340 09:29:45.893057 Streaming ioctls:
11341 09:29:45.899157 <LAVA_SIGNAL_TESTSET STOP>
11342 09:29:45.899923 Received signal: <TESTSET> STOP
11343 09:29:45.900290 Closing test_set Buffer-ioctls
11344 09:29:45.908074 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11345 09:29:45.908991 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11346 09:29:45.909535 Starting test_set Streaming-ioctls_Test-input-0
11347 09:29:45.911568 test read/write: OK (Not Supported)
11348 09:29:45.937985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11349 09:29:45.938793 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11351 09:29:45.944665 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11352 09:29:45.955322 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11353 09:29:45.964776 test blocking wait: FAIL
11354 09:29:45.994260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11355 09:29:45.995234 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11357 09:29:46.001083 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11358 09:29:46.004527 test MMAP (select): FAIL
11359 09:29:46.034961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11360 09:29:46.035725 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11362 09:29:46.041342 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11363 09:29:46.045883 test MMAP (epoll): FAIL
11364 09:29:46.070807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11365 09:29:46.071621 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11367 09:29:46.077126 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11368 09:29:46.083788 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11369 09:29:46.095263 test USERPTR (select): FAIL
11370 09:29:46.120259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11371 09:29:46.121294 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11373 09:29:46.126632 test DMABUF: Cannot test, specify --expbuf-device
11374 09:29:46.132238
11375 09:29:46.151053 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11376 09:29:46.154250 <LAVA_TEST_RUNNER EXIT>
11377 09:29:46.155080 ok: lava_test_shell seems to have completed
11378 09:29:46.155560 Marking unfinished test run as failed
11380 09:29:46.160803 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls
Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11381 09:29:46.161470 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11382 09:29:46.161940 end: 3 lava-test-retry (duration 00:00:03) [common]
11383 09:29:46.162472 start: 4 finalize (timeout 00:08:13) [common]
11384 09:29:46.162946 start: 4.1 power-off (timeout 00:00:30) [common]
11385 09:29:46.163691 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11386 09:29:46.417212 >> Command sent successfully.
11387 09:29:46.427357 Returned 0 in 0 seconds
11388 09:29:46.528738 end: 4.1 power-off (duration 00:00:00) [common]
11390 09:29:46.530262 start: 4.2 read-feedback (timeout 00:08:13) [common]
11391 09:29:46.531445 Listened to connection for namespace 'common' for up to 1s
11392 09:29:47.532264 Finalising connection for namespace 'common'
11393 09:29:47.533002 Disconnecting from shell: Finalise
11394 09:29:47.533434 / #
11395 09:29:47.634368 end: 4.2 read-feedback (duration 00:00:01) [common]
11396 09:29:47.635021 end: 4 finalize (duration 00:00:01) [common]
11397 09:29:47.635655 Cleaning after the job
11398 09:29:47.636129 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/ramdisk
11399 09:29:47.655687 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/kernel
11400 09:29:47.687248 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/dtb
11401 09:29:47.687531 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407641/tftp-deploy-kc612fpy/modules
11402 09:29:47.694991 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407641
11403 09:29:47.752772 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407641
11404 09:29:47.752934 Job finished correctly