Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 43
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 09:23:53.051057 lava-dispatcher, installed at version: 2024.03
2 09:23:53.051275 start: 0 validate
3 09:23:53.051393 Start time: 2024-06-18 09:23:53.051387+00:00 (UTC)
4 09:23:53.051531 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:23:53.051675 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:23:53.318339 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:23:53.318498 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:25:15.168476 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:25:15.168641 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:25:15.432761 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:25:15.432895 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:25:15.955996 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:25:15.956146 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:25:16.206290 validate duration: 83.15
16 09:25:16.206587 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:25:16.206707 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:25:16.206804 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:25:16.206975 Not decompressing ramdisk as can be used compressed.
20 09:25:16.207077 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 09:25:16.207147 saving as /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/ramdisk/initrd.cpio.gz
22 09:25:16.207212 total size: 5628182 (5 MB)
23 09:25:16.464278 progress 0 % (0 MB)
24 09:25:16.465978 progress 5 % (0 MB)
25 09:25:16.467662 progress 10 % (0 MB)
26 09:25:16.469182 progress 15 % (0 MB)
27 09:25:16.470760 progress 20 % (1 MB)
28 09:25:16.472209 progress 25 % (1 MB)
29 09:25:16.473764 progress 30 % (1 MB)
30 09:25:16.475383 progress 35 % (1 MB)
31 09:25:16.477296 progress 40 % (2 MB)
32 09:25:16.478861 progress 45 % (2 MB)
33 09:25:16.480292 progress 50 % (2 MB)
34 09:25:16.481904 progress 55 % (2 MB)
35 09:25:16.483454 progress 60 % (3 MB)
36 09:25:16.484890 progress 65 % (3 MB)
37 09:25:16.486481 progress 70 % (3 MB)
38 09:25:16.487947 progress 75 % (4 MB)
39 09:25:16.489556 progress 80 % (4 MB)
40 09:25:16.490942 progress 85 % (4 MB)
41 09:25:16.492503 progress 90 % (4 MB)
42 09:25:16.494053 progress 95 % (5 MB)
43 09:25:16.495460 progress 100 % (5 MB)
44 09:25:16.495673 5 MB downloaded in 0.29 s (18.61 MB/s)
45 09:25:16.495830 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:25:16.496061 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:25:16.496151 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:25:16.496236 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:25:16.496376 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:25:16.496439 saving as /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/kernel/Image
52 09:25:16.496493 total size: 54813184 (52 MB)
53 09:25:16.496550 No compression specified
54 09:25:16.497577 progress 0 % (0 MB)
55 09:25:16.511739 progress 5 % (2 MB)
56 09:25:16.526163 progress 10 % (5 MB)
57 09:25:16.540416 progress 15 % (7 MB)
58 09:25:16.555427 progress 20 % (10 MB)
59 09:25:16.569966 progress 25 % (13 MB)
60 09:25:16.585027 progress 30 % (15 MB)
61 09:25:16.600679 progress 35 % (18 MB)
62 09:25:16.619623 progress 40 % (20 MB)
63 09:25:16.860898 progress 45 % (23 MB)
64 09:25:16.876803 progress 50 % (26 MB)
65 09:25:16.894068 progress 55 % (28 MB)
66 09:25:16.912904 progress 60 % (31 MB)
67 09:25:16.929403 progress 65 % (34 MB)
68 09:25:16.943344 progress 70 % (36 MB)
69 09:25:16.957763 progress 75 % (39 MB)
70 09:25:16.973343 progress 80 % (41 MB)
71 09:25:16.992749 progress 85 % (44 MB)
72 09:25:17.007979 progress 90 % (47 MB)
73 09:25:17.022328 progress 95 % (49 MB)
74 09:25:17.035823 progress 100 % (52 MB)
75 09:25:17.036067 52 MB downloaded in 0.54 s (96.88 MB/s)
76 09:25:17.036224 end: 1.2.1 http-download (duration 00:00:01) [common]
78 09:25:17.036438 end: 1.2 download-retry (duration 00:00:01) [common]
79 09:25:17.036521 start: 1.3 download-retry (timeout 00:09:59) [common]
80 09:25:17.036598 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 09:25:17.036745 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:25:17.036809 saving as /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/dtb/mt8192-asurada-spherion-r0.dtb
83 09:25:17.036864 total size: 47258 (0 MB)
84 09:25:17.036919 No compression specified
85 09:25:17.038026 progress 69 % (0 MB)
86 09:25:17.038289 progress 100 % (0 MB)
87 09:25:17.038441 0 MB downloaded in 0.00 s (28.63 MB/s)
88 09:25:17.038554 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:25:17.038759 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:25:17.038836 start: 1.4 download-retry (timeout 00:09:59) [common]
92 09:25:17.038913 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 09:25:17.039024 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 09:25:17.039085 saving as /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/nfsrootfs/full.rootfs.tar
95 09:25:17.039139 total size: 107552908 (102 MB)
96 09:25:17.039193 Using unxz to decompress xz
97 09:25:17.040342 progress 0 % (0 MB)
98 09:25:17.321018 progress 5 % (5 MB)
99 09:25:17.638504 progress 10 % (10 MB)
100 09:25:17.946881 progress 15 % (15 MB)
101 09:25:18.258521 progress 20 % (20 MB)
102 09:25:18.528910 progress 25 % (25 MB)
103 09:25:18.824810 progress 30 % (30 MB)
104 09:25:19.145080 progress 35 % (35 MB)
105 09:25:19.323222 progress 40 % (41 MB)
106 09:25:19.523273 progress 45 % (46 MB)
107 09:25:19.833471 progress 50 % (51 MB)
108 09:25:20.132387 progress 55 % (56 MB)
109 09:25:20.459999 progress 60 % (61 MB)
110 09:25:21.007324 progress 65 % (66 MB)
111 09:25:21.318591 progress 70 % (71 MB)
112 09:25:21.628838 progress 75 % (76 MB)
113 09:25:21.925663 progress 80 % (82 MB)
114 09:25:22.307417 progress 85 % (87 MB)
115 09:25:22.617002 progress 90 % (92 MB)
116 09:25:22.925369 progress 95 % (97 MB)
117 09:25:23.244785 progress 100 % (102 MB)
118 09:25:23.249770 102 MB downloaded in 6.21 s (16.52 MB/s)
119 09:25:23.249987 end: 1.4.1 http-download (duration 00:00:06) [common]
121 09:25:23.250327 end: 1.4 download-retry (duration 00:00:06) [common]
122 09:25:23.250446 start: 1.5 download-retry (timeout 00:09:53) [common]
123 09:25:23.250562 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 09:25:23.250749 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:25:23.250845 saving as /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/modules/modules.tar
126 09:25:23.250932 total size: 8619356 (8 MB)
127 09:25:23.251020 Using unxz to decompress xz
128 09:25:23.252634 progress 0 % (0 MB)
129 09:25:23.271697 progress 5 % (0 MB)
130 09:25:23.295347 progress 10 % (0 MB)
131 09:25:23.319834 progress 15 % (1 MB)
132 09:25:23.343693 progress 20 % (1 MB)
133 09:25:23.367808 progress 25 % (2 MB)
134 09:25:23.391691 progress 30 % (2 MB)
135 09:25:23.415984 progress 35 % (2 MB)
136 09:25:23.440149 progress 40 % (3 MB)
137 09:25:23.464016 progress 45 % (3 MB)
138 09:25:23.487591 progress 50 % (4 MB)
139 09:25:23.512893 progress 55 % (4 MB)
140 09:25:23.537835 progress 60 % (4 MB)
141 09:25:23.561300 progress 65 % (5 MB)
142 09:25:23.589958 progress 70 % (5 MB)
143 09:25:23.615892 progress 75 % (6 MB)
144 09:25:23.639976 progress 80 % (6 MB)
145 09:25:23.663494 progress 85 % (7 MB)
146 09:25:23.688429 progress 90 % (7 MB)
147 09:25:23.717204 progress 95 % (7 MB)
148 09:25:23.746933 progress 100 % (8 MB)
149 09:25:23.751431 8 MB downloaded in 0.50 s (16.42 MB/s)
150 09:25:23.751588 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:25:23.751799 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:25:23.751878 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 09:25:23.751955 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 09:25:25.850315 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14407676/extract-nfsrootfs-3y43sa5u
156 09:25:25.850474 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 09:25:25.850569 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 09:25:25.850737 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56
159 09:25:25.850858 makedir: /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin
160 09:25:25.850959 makedir: /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/tests
161 09:25:25.851052 makedir: /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/results
162 09:25:25.851138 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-add-keys
163 09:25:25.851264 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-add-sources
164 09:25:25.851383 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-background-process-start
165 09:25:25.851498 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-background-process-stop
166 09:25:25.851620 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-common-functions
167 09:25:25.851735 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-echo-ipv4
168 09:25:25.851849 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-install-packages
169 09:25:25.851960 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-installed-packages
170 09:25:25.852087 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-os-build
171 09:25:25.852213 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-probe-channel
172 09:25:25.852323 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-probe-ip
173 09:25:25.852432 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-target-ip
174 09:25:25.852541 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-target-mac
175 09:25:25.852655 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-target-storage
176 09:25:25.852801 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-test-case
177 09:25:25.852910 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-test-event
178 09:25:25.853017 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-test-feedback
179 09:25:25.853124 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-test-raise
180 09:25:25.853234 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-test-reference
181 09:25:25.853341 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-test-runner
182 09:25:25.853447 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-test-set
183 09:25:25.853554 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-test-shell
184 09:25:25.853663 Updating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-install-packages (oe)
185 09:25:25.853803 Updating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/bin/lava-installed-packages (oe)
186 09:25:25.853910 Creating /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/environment
187 09:25:25.854078 LAVA metadata
188 09:25:25.854174 - LAVA_JOB_ID=14407676
189 09:25:25.854233 - LAVA_DISPATCHER_IP=192.168.201.1
190 09:25:25.854331 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 09:25:25.854388 skipped lava-vland-overlay
192 09:25:25.854455 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 09:25:25.854527 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 09:25:25.854579 skipped lava-multinode-overlay
195 09:25:25.854642 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 09:25:25.854712 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 09:25:25.854773 Loading test definitions
198 09:25:25.854847 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 09:25:25.854905 Using /lava-14407676 at stage 0
200 09:25:25.855200 uuid=14407676_1.6.2.3.1 testdef=None
201 09:25:25.855279 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 09:25:25.855354 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 09:25:25.855795 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 09:25:25.855995 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 09:25:25.856567 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 09:25:25.856882 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 09:25:25.857494 runner path: /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/0/tests/0_dmesg test_uuid 14407676_1.6.2.3.1
210 09:25:25.857636 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 09:25:25.857816 Creating lava-test-runner.conf files
213 09:25:25.857871 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407676/lava-overlay-yxq4ww56/lava-14407676/0 for stage 0
214 09:25:25.857949 - 0_dmesg
215 09:25:25.858086 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 09:25:25.858210 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
217 09:25:25.863536 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 09:25:25.863640 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
219 09:25:25.863718 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 09:25:25.863796 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 09:25:25.863873 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
222 09:25:26.032804 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 09:25:26.032953 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
224 09:25:26.033035 extracting modules file /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407676/extract-nfsrootfs-3y43sa5u
225 09:25:26.259792 extracting modules file /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407676/extract-overlay-ramdisk-yy28cy4k/ramdisk
226 09:25:26.493324 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 09:25:26.493469 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
228 09:25:26.493556 [common] Applying overlay to NFS
229 09:25:26.493616 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407676/compress-overlay-4eh8hcqh/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407676/extract-nfsrootfs-3y43sa5u
230 09:25:26.499692 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 09:25:26.499809 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
232 09:25:26.499894 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 09:25:26.499974 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
234 09:25:26.500041 Building ramdisk /var/lib/lava/dispatcher/tmp/14407676/extract-overlay-ramdisk-yy28cy4k/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407676/extract-overlay-ramdisk-yy28cy4k/ramdisk
235 09:25:26.927651 >> 130466 blocks
236 09:25:29.030006 rename /var/lib/lava/dispatcher/tmp/14407676/extract-overlay-ramdisk-yy28cy4k/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/ramdisk/ramdisk.cpio.gz
237 09:25:29.030187 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
238 09:25:29.030280 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
239 09:25:29.030378 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
240 09:25:29.030461 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/kernel/Image']
241 09:25:43.374884 Returned 0 in 14 seconds
242 09:25:43.475410 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/kernel/image.itb
243 09:25:44.008579 output: FIT description: Kernel Image image with one or more FDT blobs
244 09:25:44.008760 output: Created: Tue Jun 18 10:25:43 2024
245 09:25:44.008824 output: Image 0 (kernel-1)
246 09:25:44.008882 output: Description:
247 09:25:44.008940 output: Created: Tue Jun 18 10:25:43 2024
248 09:25:44.008999 output: Type: Kernel Image
249 09:25:44.009055 output: Compression: lzma compressed
250 09:25:44.009114 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
251 09:25:44.009171 output: Architecture: AArch64
252 09:25:44.009227 output: OS: Linux
253 09:25:44.009281 output: Load Address: 0x00000000
254 09:25:44.009337 output: Entry Point: 0x00000000
255 09:25:44.009393 output: Hash algo: crc32
256 09:25:44.009448 output: Hash value: 4137a6e7
257 09:25:44.009500 output: Image 1 (fdt-1)
258 09:25:44.009548 output: Description: mt8192-asurada-spherion-r0
259 09:25:44.009601 output: Created: Tue Jun 18 10:25:43 2024
260 09:25:44.009662 output: Type: Flat Device Tree
261 09:25:44.009714 output: Compression: uncompressed
262 09:25:44.009765 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 09:25:44.009814 output: Architecture: AArch64
264 09:25:44.009862 output: Hash algo: crc32
265 09:25:44.009912 output: Hash value: 0f8e4d2e
266 09:25:44.009959 output: Image 2 (ramdisk-1)
267 09:25:44.010006 output: Description: unavailable
268 09:25:44.010054 output: Created: Tue Jun 18 10:25:43 2024
269 09:25:44.010102 output: Type: RAMDisk Image
270 09:25:44.010149 output: Compression: uncompressed
271 09:25:44.010195 output: Data Size: 18743181 Bytes = 18303.89 KiB = 17.87 MiB
272 09:25:44.010243 output: Architecture: AArch64
273 09:25:44.010290 output: OS: Linux
274 09:25:44.010338 output: Load Address: unavailable
275 09:25:44.010386 output: Entry Point: unavailable
276 09:25:44.010433 output: Hash algo: crc32
277 09:25:44.010480 output: Hash value: 7da8fcfa
278 09:25:44.010528 output: Default Configuration: 'conf-1'
279 09:25:44.010576 output: Configuration 0 (conf-1)
280 09:25:44.010623 output: Description: mt8192-asurada-spherion-r0
281 09:25:44.010671 output: Kernel: kernel-1
282 09:25:44.010718 output: Init Ramdisk: ramdisk-1
283 09:25:44.010765 output: FDT: fdt-1
284 09:25:44.010812 output: Loadables: kernel-1
285 09:25:44.010859 output:
286 09:25:44.011001 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
287 09:25:44.011101 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
288 09:25:44.011192 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
289 09:25:44.011273 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:32) [common]
290 09:25:44.011337 No LXC device requested
291 09:25:44.011405 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 09:25:44.011481 start: 1.8 deploy-device-env (timeout 00:09:32) [common]
293 09:25:44.011550 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 09:25:44.011611 Checking files for TFTP limit of 4294967296 bytes.
295 09:25:44.012055 end: 1 tftp-deploy (duration 00:00:28) [common]
296 09:25:44.012153 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 09:25:44.012238 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 09:25:44.012347 substitutions:
299 09:25:44.012414 - {DTB}: 14407676/tftp-deploy-21hyexwe/dtb/mt8192-asurada-spherion-r0.dtb
300 09:25:44.012477 - {INITRD}: 14407676/tftp-deploy-21hyexwe/ramdisk/ramdisk.cpio.gz
301 09:25:44.012531 - {KERNEL}: 14407676/tftp-deploy-21hyexwe/kernel/Image
302 09:25:44.012582 - {LAVA_MAC}: None
303 09:25:44.012632 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14407676/extract-nfsrootfs-3y43sa5u
304 09:25:44.012722 - {NFS_SERVER_IP}: 192.168.201.1
305 09:25:44.012773 - {PRESEED_CONFIG}: None
306 09:25:44.012830 - {PRESEED_LOCAL}: None
307 09:25:44.012881 - {RAMDISK}: 14407676/tftp-deploy-21hyexwe/ramdisk/ramdisk.cpio.gz
308 09:25:44.012930 - {ROOT_PART}: None
309 09:25:44.012978 - {ROOT}: None
310 09:25:44.013026 - {SERVER_IP}: 192.168.201.1
311 09:25:44.013074 - {TEE}: None
312 09:25:44.013122 Parsed boot commands:
313 09:25:44.013169 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 09:25:44.013322 Parsed boot commands: tftpboot 192.168.201.1 14407676/tftp-deploy-21hyexwe/kernel/image.itb 14407676/tftp-deploy-21hyexwe/kernel/cmdline
315 09:25:44.013404 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 09:25:44.013477 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 09:25:44.013556 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 09:25:44.013643 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 09:25:44.013703 Not connected, no need to disconnect.
320 09:25:44.013769 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 09:25:44.013841 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 09:25:44.013900 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
323 09:25:44.017358 Setting prompt string to ['lava-test: # ']
324 09:25:44.017702 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 09:25:44.017806 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 09:25:44.017901 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 09:25:44.018009 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 09:25:44.018215 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-8']
329 09:25:57.803374 Returned 0 in 13 seconds
330 09:25:57.903939 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
332 09:25:57.904234 end: 2.2.2 reset-device (duration 00:00:14) [common]
333 09:25:57.904331 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
334 09:25:57.904417 Setting prompt string to 'Starting depthcharge on Spherion...'
335 09:25:57.904477 Changing prompt to 'Starting depthcharge on Spherion...'
336 09:25:57.904541 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
337 09:25:57.904933 [Enter `^Ec?' for help]
338 09:25:57.905008
339 09:25:57.905066
340 09:25:57.905123 F0: 102B 0000
341 09:25:57.905177
342 09:25:57.905233 F3: 1001 0000 [0200]
343 09:25:57.905287
344 09:25:57.905343 F3: 1001 0000
345 09:25:57.905397
346 09:25:57.905452 F7: 102D 0000
347 09:25:57.905507
348 09:25:57.905561 F1: 0000 0000
349 09:25:57.905615
350 09:25:57.905667 V0: 0000 0000 [0001]
351 09:25:57.905721
352 09:25:57.905770 00: 0007 8000
353 09:25:57.905820
354 09:25:57.905868 01: 0000 0000
355 09:25:57.905917
356 09:25:57.905966 BP: 0C00 0209 [0000]
357 09:25:57.906013
358 09:25:57.906059 G0: 1182 0000
359 09:25:57.906107
360 09:25:57.906155 EC: 0000 0021 [4000]
361 09:25:57.906203
362 09:25:57.906250 S7: 0000 0000 [0000]
363 09:25:57.906298
364 09:25:57.906345 CC: 0000 0000 [0001]
365 09:25:57.906392
366 09:25:57.906440 T0: 0000 0040 [010F]
367 09:25:57.906487
368 09:25:57.906535 Jump to BL
369 09:25:57.906582
370 09:25:57.906629
371 09:25:57.906676
372 09:25:57.906724 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
373 09:25:57.906797 ARM64: Exception handlers installed.
374 09:25:57.906863 ARM64: Testing exception
375 09:25:57.906912 ARM64: Done test exception
376 09:25:57.906965 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
377 09:25:57.907050 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
378 09:25:57.907103 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
379 09:25:57.907152 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
380 09:25:57.907230 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
381 09:25:57.907308 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
382 09:25:57.907385 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
383 09:25:57.907463 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
384 09:25:57.907540 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
385 09:25:57.907620 WDT: Last reset was cold boot
386 09:25:57.907672 SPI1(PAD0) initialized at 2873684 Hz
387 09:25:57.907721 SPI5(PAD0) initialized at 992727 Hz
388 09:25:57.907770 VBOOT: Loading verstage.
389 09:25:57.907819 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
390 09:25:57.907867 FMAP: Found "FLASH" version 1.1 at 0x20000.
391 09:25:57.907915 FMAP: base = 0x0 size = 0x800000 #areas = 25
392 09:25:57.907962 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
393 09:25:57.908010 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
394 09:25:57.908059 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
395 09:25:57.908107 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
396 09:25:57.908155
397 09:25:57.908202
398 09:25:57.908250 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
399 09:25:57.908299 ARM64: Exception handlers installed.
400 09:25:57.908346 ARM64: Testing exception
401 09:25:57.908395 ARM64: Done test exception
402 09:25:57.908442 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
403 09:25:57.908491 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
404 09:25:57.908539 Probing TPM: . done!
405 09:25:57.908586 TPM ready after 0 ms
406 09:25:57.908634 Connected to device vid:did:rid of 1ae0:0028:00
407 09:25:57.908728 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
408 09:25:57.908778 Initialized TPM device CR50 revision 0
409 09:25:57.908826 tlcl_send_startup: Startup return code is 0
410 09:25:57.908873 TPM: setup succeeded
411 09:25:57.908921 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
412 09:25:57.908968 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
413 09:25:57.909016 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
414 09:25:57.909064 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 09:25:57.909111 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
416 09:25:57.909160 in-header: 03 07 00 00 08 00 00 00
417 09:25:57.909208 in-data: aa e4 47 04 13 02 00 00
418 09:25:57.909256 Chrome EC: UHEPI supported
419 09:25:57.909303 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
420 09:25:57.909351 in-header: 03 a9 00 00 08 00 00 00
421 09:25:57.909400 in-data: 84 60 60 08 00 00 00 00
422 09:25:57.909447 Phase 1
423 09:25:57.909494 FMAP: area GBB found @ 3f5000 (12032 bytes)
424 09:25:57.909543 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
425 09:25:57.909590 VB2:vb2_check_recovery() Recovery was requested manually
426 09:25:57.909638 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
427 09:25:57.909685 Recovery requested (1009000e)
428 09:25:57.909732 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 09:25:57.909780 tlcl_extend: response is 0
430 09:25:57.909829 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 09:25:57.909877 tlcl_extend: response is 0
432 09:25:57.909925 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 09:25:57.909972 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
434 09:25:57.910020 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 09:25:57.910067
436 09:25:57.910114
437 09:25:57.910164 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 09:25:57.910213 ARM64: Exception handlers installed.
439 09:25:57.910261 ARM64: Testing exception
440 09:25:57.910308 ARM64: Done test exception
441 09:25:57.910356 pmic_efuse_setting: Set efuses in 11 msecs
442 09:25:57.910403 pmwrap_interface_init: Select PMIF_VLD_RDY
443 09:25:57.910451 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 09:25:57.910498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 09:25:57.910737 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 09:25:57.910792 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 09:25:57.910842 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 09:25:57.910890 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 09:25:57.910941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 09:25:57.911008 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 09:25:57.911071 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 09:25:57.911119 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 09:25:57.911167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 09:25:57.911232 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 09:25:57.911281 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 09:25:57.911362 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 09:25:57.911441 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 09:25:57.911504 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 09:25:57.911569 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 09:25:57.911648 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 09:25:57.911696 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 09:25:57.911776 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 09:25:57.911825 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 09:25:57.911874 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 09:25:57.911923 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 09:25:57.911972 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 09:25:57.912020 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 09:25:57.912070 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 09:25:57.912119 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 09:25:57.912168 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 09:25:57.912217 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 09:25:57.912267 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 09:25:57.912316 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 09:25:57.912365 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 09:25:57.912413 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 09:25:57.912462 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 09:25:57.912510 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 09:25:57.912560 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 09:25:57.912609 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 09:25:57.912667 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 09:25:57.912719 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 09:25:57.912768 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 09:25:57.912860 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 09:25:57.912908 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 09:25:57.912955 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 09:25:57.913002 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 09:25:57.913050 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 09:25:57.913097 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 09:25:57.913163 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 09:25:57.913224 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 09:25:57.913271 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 09:25:57.913319 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 09:25:57.913366 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 09:25:57.913444 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
495 09:25:57.913492 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 09:25:57.913541 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 09:25:57.913619 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 09:25:57.913667 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 09:25:57.913716 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 09:25:57.913765 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 09:25:57.913813 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 09:25:57.913860 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
503 09:25:57.913909 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
504 09:25:57.913958 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
505 09:25:57.914007 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 09:25:57.914064 [RTC]rtc_get_frequency_meter,154: input=15, output=793
507 09:25:57.914114 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
508 09:25:57.914162 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
509 09:25:57.914210 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
510 09:25:57.914273 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
511 09:25:57.914324 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
512 09:25:57.914373 ADC[4]: Raw value=895191 ID=7
513 09:25:57.914421 ADC[3]: Raw value=213070 ID=1
514 09:25:57.914474 RAM Code: 0x71
515 09:25:57.914522 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
516 09:25:57.914571 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
517 09:25:57.914807 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
518 09:25:57.914865 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
519 09:25:57.914915 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
520 09:25:57.914964 in-header: 03 07 00 00 08 00 00 00
521 09:25:57.915012 in-data: aa e4 47 04 13 02 00 00
522 09:25:57.915060 Chrome EC: UHEPI supported
523 09:25:57.915109 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
524 09:25:57.915157 in-header: 03 a9 00 00 08 00 00 00
525 09:25:57.915205 in-data: 84 60 60 08 00 00 00 00
526 09:25:57.915284 MRC: failed to locate region type 0.
527 09:25:57.915332 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
528 09:25:57.915381 DRAM-K: Running full calibration
529 09:25:57.915429 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
530 09:25:57.915477 header.status = 0x0
531 09:25:57.915525 header.version = 0x6 (expected: 0x6)
532 09:25:57.915573 header.size = 0xd00 (expected: 0xd00)
533 09:25:57.915620 header.flags = 0x0
534 09:25:57.915668 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
535 09:25:57.915716 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
536 09:25:57.915765 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
537 09:25:57.915813 dram_init: ddr_geometry: 2
538 09:25:57.915860 [EMI] MDL number = 2
539 09:25:57.915907 [EMI] Get MDL freq = 0
540 09:25:57.915969 dram_init: ddr_type: 0
541 09:25:57.916030 is_discrete_lpddr4: 1
542 09:25:57.916077 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
543 09:25:57.916124
544 09:25:57.916171
545 09:25:57.916218 [Bian_co] ETT version 0.0.0.1
546 09:25:57.916266 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
547 09:25:57.916313
548 09:25:57.916360 dramc_set_vcore_voltage set vcore to 650000
549 09:25:57.916408 Read voltage for 800, 4
550 09:25:57.916456 Vio18 = 0
551 09:25:57.916503 Vcore = 650000
552 09:25:57.916551 Vdram = 0
553 09:25:57.916599 Vddq = 0
554 09:25:57.916668 Vmddr = 0
555 09:25:57.916734 dram_init: config_dvfs: 1
556 09:25:57.916783 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
557 09:25:57.916831 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
558 09:25:57.916879 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
559 09:25:57.916927 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
560 09:25:57.916975 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
561 09:25:57.917023 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
562 09:25:57.917071 MEM_TYPE=3, freq_sel=18
563 09:25:57.917134 sv_algorithm_assistance_LP4_1600
564 09:25:57.917196 ============ PULL DRAM RESETB DOWN ============
565 09:25:57.917246 ========== PULL DRAM RESETB DOWN end =========
566 09:25:57.917294 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
567 09:25:57.917341 ===================================
568 09:25:57.917388 LPDDR4 DRAM CONFIGURATION
569 09:25:57.917435 ===================================
570 09:25:57.917483 EX_ROW_EN[0] = 0x0
571 09:25:57.917530 EX_ROW_EN[1] = 0x0
572 09:25:57.917577 LP4Y_EN = 0x0
573 09:25:57.917623 WORK_FSP = 0x0
574 09:25:57.917670 WL = 0x2
575 09:25:57.917717 RL = 0x2
576 09:25:57.917764 BL = 0x2
577 09:25:57.917812 RPST = 0x0
578 09:25:57.917859 RD_PRE = 0x0
579 09:25:57.917905 WR_PRE = 0x1
580 09:25:57.917952 WR_PST = 0x0
581 09:25:57.917999 DBI_WR = 0x0
582 09:25:57.918045 DBI_RD = 0x0
583 09:25:57.918092 OTF = 0x1
584 09:25:57.918139 ===================================
585 09:25:57.918187 ===================================
586 09:25:57.918234 ANA top config
587 09:25:57.918281 ===================================
588 09:25:57.918329 DLL_ASYNC_EN = 0
589 09:25:57.918377 ALL_SLAVE_EN = 1
590 09:25:57.918424 NEW_RANK_MODE = 1
591 09:25:57.918471 DLL_IDLE_MODE = 1
592 09:25:57.918518 LP45_APHY_COMB_EN = 1
593 09:25:57.918565 TX_ODT_DIS = 1
594 09:25:57.918617 NEW_8X_MODE = 1
595 09:25:57.918680 ===================================
596 09:25:57.918729 ===================================
597 09:25:57.918777 data_rate = 1600
598 09:25:57.918826 CKR = 1
599 09:25:57.918873 DQ_P2S_RATIO = 8
600 09:25:57.918920 ===================================
601 09:25:57.918968 CA_P2S_RATIO = 8
602 09:25:57.919015 DQ_CA_OPEN = 0
603 09:25:57.919062 DQ_SEMI_OPEN = 0
604 09:25:57.919110 CA_SEMI_OPEN = 0
605 09:25:57.919160 CA_FULL_RATE = 0
606 09:25:57.919208 DQ_CKDIV4_EN = 1
607 09:25:57.919255 CA_CKDIV4_EN = 1
608 09:25:57.919302 CA_PREDIV_EN = 0
609 09:25:57.919349 PH8_DLY = 0
610 09:25:57.919396 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
611 09:25:57.919443 DQ_AAMCK_DIV = 4
612 09:25:57.919508 CA_AAMCK_DIV = 4
613 09:25:57.919568 CA_ADMCK_DIV = 4
614 09:25:57.919645 DQ_TRACK_CA_EN = 0
615 09:25:57.919693 CA_PICK = 800
616 09:25:57.919740 CA_MCKIO = 800
617 09:25:57.919787 MCKIO_SEMI = 0
618 09:25:57.919852 PLL_FREQ = 3068
619 09:25:57.919914 DQ_UI_PI_RATIO = 32
620 09:25:57.919961 CA_UI_PI_RATIO = 0
621 09:25:57.920008 ===================================
622 09:25:57.920056 ===================================
623 09:25:57.920103 memory_type:LPDDR4
624 09:25:57.920150 GP_NUM : 10
625 09:25:57.920197 SRAM_EN : 1
626 09:25:57.920245 MD32_EN : 0
627 09:25:57.920292 ===================================
628 09:25:57.920339 [ANA_INIT] >>>>>>>>>>>>>>
629 09:25:57.920387 <<<<<< [CONFIGURE PHASE]: ANA_TX
630 09:25:57.920438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
631 09:25:57.920486 ===================================
632 09:25:57.920533 data_rate = 1600,PCW = 0X7600
633 09:25:57.920581 ===================================
634 09:25:57.920629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
635 09:25:57.920715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
636 09:25:57.920763 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
637 09:25:57.921011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
638 09:25:57.921065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
639 09:25:57.921113 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
640 09:25:57.921162 [ANA_INIT] flow start
641 09:25:57.921227 [ANA_INIT] PLL >>>>>>>>
642 09:25:57.921290 [ANA_INIT] PLL <<<<<<<<
643 09:25:57.921338 [ANA_INIT] MIDPI >>>>>>>>
644 09:25:57.921385 [ANA_INIT] MIDPI <<<<<<<<
645 09:25:57.921432 [ANA_INIT] DLL >>>>>>>>
646 09:25:57.921479 [ANA_INIT] flow end
647 09:25:57.921525 ============ LP4 DIFF to SE enter ============
648 09:25:57.921573 ============ LP4 DIFF to SE exit ============
649 09:25:57.921651 [ANA_INIT] <<<<<<<<<<<<<
650 09:25:57.921698 [Flow] Enable top DCM control >>>>>
651 09:25:57.921745 [Flow] Enable top DCM control <<<<<
652 09:25:57.921792 Enable DLL master slave shuffle
653 09:25:57.921839 ==============================================================
654 09:25:57.921886 Gating Mode config
655 09:25:57.921933 ==============================================================
656 09:25:57.921999 Config description:
657 09:25:57.922061 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
658 09:25:57.922110 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
659 09:25:57.922158 SELPH_MODE 0: By rank 1: By Phase
660 09:25:57.922206 ==============================================================
661 09:25:57.922254 GAT_TRACK_EN = 1
662 09:25:57.922301 RX_GATING_MODE = 2
663 09:25:57.922366 RX_GATING_TRACK_MODE = 2
664 09:25:57.922428 SELPH_MODE = 1
665 09:25:57.922476 PICG_EARLY_EN = 1
666 09:25:57.922523 VALID_LAT_VALUE = 1
667 09:25:57.922570 ==============================================================
668 09:25:57.922618 Enter into Gating configuration >>>>
669 09:25:57.922666 Exit from Gating configuration <<<<
670 09:25:57.922731 Enter into DVFS_PRE_config >>>>>
671 09:25:57.922793 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
672 09:25:57.922845 Exit from DVFS_PRE_config <<<<<
673 09:25:57.922893 Enter into PICG configuration >>>>
674 09:25:57.922941 Exit from PICG configuration <<<<
675 09:25:57.922989 [RX_INPUT] configuration >>>>>
676 09:25:57.923036 [RX_INPUT] configuration <<<<<
677 09:25:57.923100 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
678 09:25:57.923165 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
679 09:25:57.923213 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
680 09:25:57.923261 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
681 09:25:57.923308 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
682 09:25:57.923356 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
683 09:25:57.923404 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
684 09:25:57.923468 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
685 09:25:57.923529 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
686 09:25:57.923577 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
687 09:25:57.923625 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
688 09:25:57.923672 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
689 09:25:57.923720 ===================================
690 09:25:57.923768 LPDDR4 DRAM CONFIGURATION
691 09:25:57.923815 ===================================
692 09:25:57.923880 EX_ROW_EN[0] = 0x0
693 09:25:57.923941 EX_ROW_EN[1] = 0x0
694 09:25:57.923987 LP4Y_EN = 0x0
695 09:25:57.924033 WORK_FSP = 0x0
696 09:25:57.924081 WL = 0x2
697 09:25:57.924128 RL = 0x2
698 09:25:57.924174 BL = 0x2
699 09:25:57.924235 RPST = 0x0
700 09:25:57.924295 RD_PRE = 0x0
701 09:25:57.924342 WR_PRE = 0x1
702 09:25:57.924389 WR_PST = 0x0
703 09:25:57.924436 DBI_WR = 0x0
704 09:25:57.924482 DBI_RD = 0x0
705 09:25:57.924528 OTF = 0x1
706 09:25:57.924575 ===================================
707 09:25:57.924640 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
708 09:25:57.924710 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
709 09:25:57.924759 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
710 09:25:57.924807 ===================================
711 09:25:57.924854 LPDDR4 DRAM CONFIGURATION
712 09:25:57.924902 ===================================
713 09:25:57.924949 EX_ROW_EN[0] = 0x10
714 09:25:57.925027 EX_ROW_EN[1] = 0x0
715 09:25:57.925073 LP4Y_EN = 0x0
716 09:25:57.925120 WORK_FSP = 0x0
717 09:25:57.925167 WL = 0x2
718 09:25:57.925215 RL = 0x2
719 09:25:57.925262 BL = 0x2
720 09:25:57.925341 RPST = 0x0
721 09:25:57.925388 RD_PRE = 0x0
722 09:25:57.925450 WR_PRE = 0x1
723 09:25:57.925499 WR_PST = 0x0
724 09:25:57.925583 DBI_WR = 0x0
725 09:25:57.925681 DBI_RD = 0x0
726 09:25:57.925755 OTF = 0x1
727 09:25:57.925830 ===================================
728 09:25:57.925919 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
729 09:25:57.926008 nWR fixed to 40
730 09:25:57.926087 [ModeRegInit_LP4] CH0 RK0
731 09:25:57.926165 [ModeRegInit_LP4] CH0 RK1
732 09:25:57.926239 [ModeRegInit_LP4] CH1 RK0
733 09:25:57.926299 [ModeRegInit_LP4] CH1 RK1
734 09:25:57.926349 match AC timing 13
735 09:25:57.926398 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
736 09:25:57.926447 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
737 09:25:57.926495 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
738 09:25:57.926544 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
739 09:25:57.926624 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
740 09:25:57.926672 [EMI DOE] emi_dcm 0
741 09:25:57.926719 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
742 09:25:57.926767 ==
743 09:25:57.926815 Dram Type= 6, Freq= 0, CH_0, rank 0
744 09:25:57.926863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
745 09:25:57.926911 ==
746 09:25:57.927150 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
747 09:25:57.927221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
748 09:25:57.927285 [CA 0] Center 38 (7~69) winsize 63
749 09:25:57.927334 [CA 1] Center 38 (7~69) winsize 63
750 09:25:57.927383 [CA 2] Center 36 (6~66) winsize 61
751 09:25:57.927439 [CA 3] Center 35 (5~66) winsize 62
752 09:25:57.927501 [CA 4] Center 34 (4~65) winsize 62
753 09:25:57.927551 [CA 5] Center 34 (4~65) winsize 62
754 09:25:57.927617
755 09:25:57.927682 [CmdBusTrainingLP45] Vref(ca) range 1: 32
756 09:25:57.927746
757 09:25:57.927796 [CATrainingPosCal] consider 1 rank data
758 09:25:57.927845 u2DelayCellTimex100 = 270/100 ps
759 09:25:57.927899 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
760 09:25:57.927968 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
761 09:25:57.928032 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
762 09:25:57.928080 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
763 09:25:57.928127 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
764 09:25:57.928175 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
765 09:25:57.928222
766 09:25:57.928271 CA PerBit enable=1, Macro0, CA PI delay=34
767 09:25:57.928319
768 09:25:57.928383 [CBTSetCACLKResult] CA Dly = 34
769 09:25:57.928446 CS Dly: 6 (0~37)
770 09:25:57.928493 ==
771 09:25:57.928541 Dram Type= 6, Freq= 0, CH_0, rank 1
772 09:25:57.928588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 09:25:57.928663 ==
774 09:25:57.928726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
775 09:25:57.928774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
776 09:25:57.928822 [CA 0] Center 38 (7~69) winsize 63
777 09:25:57.928871 [CA 1] Center 38 (7~69) winsize 63
778 09:25:57.928918 [CA 2] Center 35 (5~66) winsize 62
779 09:25:57.928966 [CA 3] Center 35 (5~66) winsize 62
780 09:25:57.929014 [CA 4] Center 34 (4~65) winsize 62
781 09:25:57.929061 [CA 5] Center 34 (3~65) winsize 63
782 09:25:57.929109
783 09:25:57.929155 [CmdBusTrainingLP45] Vref(ca) range 1: 34
784 09:25:57.929202
785 09:25:57.929249 [CATrainingPosCal] consider 2 rank data
786 09:25:57.929296 u2DelayCellTimex100 = 270/100 ps
787 09:25:57.929344 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
788 09:25:57.929393 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
789 09:25:57.929440 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
790 09:25:57.929487 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
791 09:25:57.929535 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
792 09:25:57.929582 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
793 09:25:57.929628
794 09:25:57.929712 CA PerBit enable=1, Macro0, CA PI delay=34
795 09:25:57.929784
796 09:25:57.929836 [CBTSetCACLKResult] CA Dly = 34
797 09:25:57.929887 CS Dly: 6 (0~38)
798 09:25:57.929935
799 09:25:57.929983 ----->DramcWriteLeveling(PI) begin...
800 09:25:57.930036 ==
801 09:25:57.930085 Dram Type= 6, Freq= 0, CH_0, rank 0
802 09:25:57.930134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
803 09:25:57.930182 ==
804 09:25:57.930232 Write leveling (Byte 0): 31 => 31
805 09:25:57.930280 Write leveling (Byte 1): 31 => 31
806 09:25:57.930329 DramcWriteLeveling(PI) end<-----
807 09:25:57.930376
808 09:25:57.930424 ==
809 09:25:57.930472 Dram Type= 6, Freq= 0, CH_0, rank 0
810 09:25:57.930521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 09:25:57.930569 ==
812 09:25:57.930616 [Gating] SW mode calibration
813 09:25:57.930664 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
814 09:25:57.930714 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
815 09:25:57.930778 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
816 09:25:57.930840 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
817 09:25:57.930888 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
818 09:25:57.930936 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 09:25:57.931013 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 09:25:57.931060 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 09:25:57.931107 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 09:25:57.931154 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 09:25:57.931202 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 09:25:57.931250 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 09:25:57.931297 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 09:25:57.931345 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 09:25:57.931392 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 09:25:57.931439 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 09:25:57.931486 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 09:25:57.931533 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 09:25:57.931581 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 09:25:57.931628 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
833 09:25:57.931675 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
834 09:25:57.931723 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
835 09:25:57.931770 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 09:25:57.931852 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 09:25:57.931899 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 09:25:57.931947 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 09:25:57.931994 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 09:25:57.932041 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 09:25:57.932089 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 09:25:57.932136 0 9 12 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
843 09:25:57.932184 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
844 09:25:57.932232 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
845 09:25:57.932279 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
846 09:25:57.932327 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
847 09:25:57.932375 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
848 09:25:57.932423 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 09:25:57.932471 0 10 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
850 09:25:57.932519 0 10 12 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
851 09:25:57.932566 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 09:25:57.932829 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 09:25:57.932886 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 09:25:57.932937 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 09:25:57.932988 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 09:25:57.933038 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 09:25:57.933087 0 11 8 | B1->B0 | 2b2b 2d2d | 0 0 | (1 1) (0 0)
858 09:25:57.933136 0 11 12 | B1->B0 | 3636 4545 | 0 0 | (1 1) (0 0)
859 09:25:57.933185 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 09:25:57.933235 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
861 09:25:57.933283 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 09:25:57.933331 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 09:25:57.933379 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 09:25:57.933428 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 09:25:57.933490 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
866 09:25:57.933537 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
867 09:25:57.933585 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 09:25:57.933632 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 09:25:57.933680 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 09:25:57.933727 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 09:25:57.933774 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 09:25:57.933822 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 09:25:57.933869 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 09:25:57.933917 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 09:25:57.933964 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 09:25:57.934011 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 09:25:57.934059 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 09:25:57.934107 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 09:25:57.934154 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 09:25:57.934201 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 09:25:57.934248 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
882 09:25:57.934295 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
883 09:25:57.934342 Total UI for P1: 0, mck2ui 16
884 09:25:57.934389 best dqsien dly found for B0: ( 0, 14, 8)
885 09:25:57.934437 Total UI for P1: 0, mck2ui 16
886 09:25:57.934485 best dqsien dly found for B1: ( 0, 14, 10)
887 09:25:57.934532 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
888 09:25:57.934580 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
889 09:25:57.934627
890 09:25:57.934674 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
891 09:25:57.934721 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
892 09:25:57.934769 [Gating] SW calibration Done
893 09:25:57.934817 ==
894 09:25:57.934864 Dram Type= 6, Freq= 0, CH_0, rank 0
895 09:25:57.934912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
896 09:25:57.934960 ==
897 09:25:57.935008 RX Vref Scan: 0
898 09:25:57.935054
899 09:25:57.935100 RX Vref 0 -> 0, step: 1
900 09:25:57.935147
901 09:25:57.935193 RX Delay -130 -> 252, step: 16
902 09:25:57.935272 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
903 09:25:57.935320 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
904 09:25:57.935367 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
905 09:25:57.935414 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
906 09:25:57.935461 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
907 09:25:57.935509 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
908 09:25:57.935556 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
909 09:25:57.935603 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
910 09:25:57.935650 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
911 09:25:57.935697 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
912 09:25:57.935744 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
913 09:25:57.935792 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
914 09:25:57.935839 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
915 09:25:57.935886 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
916 09:25:57.935934 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
917 09:25:57.935980 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
918 09:25:57.936027 ==
919 09:25:57.936073 Dram Type= 6, Freq= 0, CH_0, rank 0
920 09:25:57.936121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 09:25:57.936169 ==
922 09:25:57.936216 DQS Delay:
923 09:25:57.936262 DQS0 = 0, DQS1 = 0
924 09:25:57.936310 DQM Delay:
925 09:25:57.936358 DQM0 = 81, DQM1 = 70
926 09:25:57.936405 DQ Delay:
927 09:25:57.936452 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
928 09:25:57.936499 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
929 09:25:57.936548 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
930 09:25:57.936651 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
931 09:25:57.936740
932 09:25:57.936788
933 09:25:57.936838 ==
934 09:25:57.936888 Dram Type= 6, Freq= 0, CH_0, rank 0
935 09:25:57.936936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 09:25:57.936984 ==
937 09:25:57.937033
938 09:25:57.937081
939 09:25:57.937128 TX Vref Scan disable
940 09:25:57.937176 == TX Byte 0 ==
941 09:25:57.937224 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
942 09:25:57.937283 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
943 09:25:57.937335 == TX Byte 1 ==
944 09:25:57.937383 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
945 09:25:57.937431 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
946 09:25:57.937498 ==
947 09:25:57.937549 Dram Type= 6, Freq= 0, CH_0, rank 0
948 09:25:57.937598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
949 09:25:57.937647 ==
950 09:25:57.937697 TX Vref=22, minBit 11, minWin=26, winSum=433
951 09:25:57.937745 TX Vref=24, minBit 5, minWin=27, winSum=441
952 09:25:57.937793 TX Vref=26, minBit 4, minWin=27, winSum=440
953 09:25:57.937842 TX Vref=28, minBit 9, minWin=27, winSum=443
954 09:25:57.937891 TX Vref=30, minBit 9, minWin=27, winSum=442
955 09:25:57.937938 TX Vref=32, minBit 2, minWin=27, winSum=440
956 09:25:57.937987 [TxChooseVref] Worse bit 9, Min win 27, Win sum 443, Final Vref 28
957 09:25:57.938035
958 09:25:57.938082 Final TX Range 1 Vref 28
959 09:25:57.938129
960 09:25:57.938175 ==
961 09:25:57.938222 Dram Type= 6, Freq= 0, CH_0, rank 0
962 09:25:57.938271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 09:25:57.938319 ==
964 09:25:57.938365
965 09:25:57.938412
966 09:25:57.938459 TX Vref Scan disable
967 09:25:57.938708 == TX Byte 0 ==
968 09:25:57.938794 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
969 09:25:57.938844 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
970 09:25:57.938892 == TX Byte 1 ==
971 09:25:57.938940 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
972 09:25:57.938987 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
973 09:25:57.939035
974 09:25:57.939082 [DATLAT]
975 09:25:57.939129 Freq=800, CH0 RK0
976 09:25:57.939178
977 09:25:57.939225 DATLAT Default: 0xa
978 09:25:57.939272 0, 0xFFFF, sum = 0
979 09:25:57.939321 1, 0xFFFF, sum = 0
980 09:25:57.939369 2, 0xFFFF, sum = 0
981 09:25:57.939417 3, 0xFFFF, sum = 0
982 09:25:57.939497 4, 0xFFFF, sum = 0
983 09:25:57.939545 5, 0xFFFF, sum = 0
984 09:25:57.939593 6, 0xFFFF, sum = 0
985 09:25:57.939641 7, 0xFFFF, sum = 0
986 09:25:57.939689 8, 0xFFFF, sum = 0
987 09:25:57.939737 9, 0x0, sum = 1
988 09:25:57.939785 10, 0x0, sum = 2
989 09:25:57.939833 11, 0x0, sum = 3
990 09:25:57.939881 12, 0x0, sum = 4
991 09:25:57.939928 best_step = 10
992 09:25:57.939976
993 09:25:57.940022 ==
994 09:25:57.940069 Dram Type= 6, Freq= 0, CH_0, rank 0
995 09:25:57.940116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
996 09:25:57.940163 ==
997 09:25:57.940211 RX Vref Scan: 1
998 09:25:57.940258
999 09:25:57.940304 Set Vref Range= 32 -> 127
1000 09:25:57.940351
1001 09:25:57.940397 RX Vref 32 -> 127, step: 1
1002 09:25:57.940444
1003 09:25:57.940492 RX Delay -111 -> 252, step: 8
1004 09:25:57.940539
1005 09:25:57.940586 Set Vref, RX VrefLevel [Byte0]: 32
1006 09:25:57.940634 [Byte1]: 32
1007 09:25:57.940727
1008 09:25:57.940775 Set Vref, RX VrefLevel [Byte0]: 33
1009 09:25:57.940824 [Byte1]: 33
1010 09:25:57.940871
1011 09:25:57.940918 Set Vref, RX VrefLevel [Byte0]: 34
1012 09:25:57.940965 [Byte1]: 34
1013 09:25:57.941013
1014 09:25:57.941060 Set Vref, RX VrefLevel [Byte0]: 35
1015 09:25:57.941108 [Byte1]: 35
1016 09:25:57.941156
1017 09:25:57.941204 Set Vref, RX VrefLevel [Byte0]: 36
1018 09:25:57.941252 [Byte1]: 36
1019 09:25:57.941300
1020 09:25:57.941346 Set Vref, RX VrefLevel [Byte0]: 37
1021 09:25:57.941395 [Byte1]: 37
1022 09:25:57.941444
1023 09:25:57.941491 Set Vref, RX VrefLevel [Byte0]: 38
1024 09:25:57.941539 [Byte1]: 38
1025 09:25:57.941587
1026 09:25:57.941634 Set Vref, RX VrefLevel [Byte0]: 39
1027 09:25:57.941682 [Byte1]: 39
1028 09:25:57.941729
1029 09:25:57.941777 Set Vref, RX VrefLevel [Byte0]: 40
1030 09:25:57.941824 [Byte1]: 40
1031 09:25:57.941871
1032 09:25:57.941946 Set Vref, RX VrefLevel [Byte0]: 41
1033 09:25:57.942010 [Byte1]: 41
1034 09:25:57.942057
1035 09:25:57.942104 Set Vref, RX VrefLevel [Byte0]: 42
1036 09:25:57.942151 [Byte1]: 42
1037 09:25:57.942198
1038 09:25:57.942245 Set Vref, RX VrefLevel [Byte0]: 43
1039 09:25:57.942293 [Byte1]: 43
1040 09:25:57.942358
1041 09:25:57.942435 Set Vref, RX VrefLevel [Byte0]: 44
1042 09:25:57.942511 [Byte1]: 44
1043 09:25:57.942585
1044 09:25:57.942660 Set Vref, RX VrefLevel [Byte0]: 45
1045 09:25:57.942736 [Byte1]: 45
1046 09:25:57.942811
1047 09:25:57.942886 Set Vref, RX VrefLevel [Byte0]: 46
1048 09:25:57.942962 [Byte1]: 46
1049 09:25:57.943036
1050 09:25:57.943112 Set Vref, RX VrefLevel [Byte0]: 47
1051 09:25:57.943187 [Byte1]: 47
1052 09:25:57.943262
1053 09:25:57.943337 Set Vref, RX VrefLevel [Byte0]: 48
1054 09:25:57.943413 [Byte1]: 48
1055 09:25:57.943487
1056 09:25:57.943562 Set Vref, RX VrefLevel [Byte0]: 49
1057 09:25:57.943637 [Byte1]: 49
1058 09:25:57.943712
1059 09:25:57.943786 Set Vref, RX VrefLevel [Byte0]: 50
1060 09:25:57.943863 [Byte1]: 50
1061 09:25:57.943938
1062 09:25:57.944013 Set Vref, RX VrefLevel [Byte0]: 51
1063 09:25:57.944088 [Byte1]: 51
1064 09:25:57.944163
1065 09:25:57.944237 Set Vref, RX VrefLevel [Byte0]: 52
1066 09:25:57.944313 [Byte1]: 52
1067 09:25:57.944387
1068 09:25:57.944462 Set Vref, RX VrefLevel [Byte0]: 53
1069 09:25:57.944538 [Byte1]: 53
1070 09:25:57.944613
1071 09:25:57.944711 Set Vref, RX VrefLevel [Byte0]: 54
1072 09:25:57.944760 [Byte1]: 54
1073 09:25:57.944807
1074 09:25:57.944855 Set Vref, RX VrefLevel [Byte0]: 55
1075 09:25:57.944903 [Byte1]: 55
1076 09:25:57.944950
1077 09:25:57.944997 Set Vref, RX VrefLevel [Byte0]: 56
1078 09:25:57.945045 [Byte1]: 56
1079 09:25:57.945092
1080 09:25:57.945139 Set Vref, RX VrefLevel [Byte0]: 57
1081 09:25:57.945186 [Byte1]: 57
1082 09:25:57.945233
1083 09:25:57.945281 Set Vref, RX VrefLevel [Byte0]: 58
1084 09:25:57.945328 [Byte1]: 58
1085 09:25:57.945376
1086 09:25:57.945423 Set Vref, RX VrefLevel [Byte0]: 59
1087 09:25:57.945471 [Byte1]: 59
1088 09:25:57.945518
1089 09:25:57.945566 Set Vref, RX VrefLevel [Byte0]: 60
1090 09:25:57.945614 [Byte1]: 60
1091 09:25:57.945662
1092 09:25:57.945709 Set Vref, RX VrefLevel [Byte0]: 61
1093 09:25:57.945757 [Byte1]: 61
1094 09:25:57.945805
1095 09:25:57.945852 Set Vref, RX VrefLevel [Byte0]: 62
1096 09:25:57.945900 [Byte1]: 62
1097 09:25:57.945947
1098 09:25:57.946014 Set Vref, RX VrefLevel [Byte0]: 63
1099 09:25:57.946092 [Byte1]: 63
1100 09:25:57.946153
1101 09:25:57.946200 Set Vref, RX VrefLevel [Byte0]: 64
1102 09:25:57.946248 [Byte1]: 64
1103 09:25:57.946295
1104 09:25:57.946342 Set Vref, RX VrefLevel [Byte0]: 65
1105 09:25:57.946389 [Byte1]: 65
1106 09:25:57.946436
1107 09:25:57.946483 Set Vref, RX VrefLevel [Byte0]: 66
1108 09:25:57.946530 [Byte1]: 66
1109 09:25:57.946577
1110 09:25:57.946624 Set Vref, RX VrefLevel [Byte0]: 67
1111 09:25:57.946671 [Byte1]: 67
1112 09:25:57.946718
1113 09:25:57.946764 Set Vref, RX VrefLevel [Byte0]: 68
1114 09:25:57.946812 [Byte1]: 68
1115 09:25:57.946859
1116 09:25:57.946906 Set Vref, RX VrefLevel [Byte0]: 69
1117 09:25:57.946953 [Byte1]: 69
1118 09:25:57.947000
1119 09:25:57.947048 Set Vref, RX VrefLevel [Byte0]: 70
1120 09:25:57.947095 [Byte1]: 70
1121 09:25:57.947142
1122 09:25:57.947189 Set Vref, RX VrefLevel [Byte0]: 71
1123 09:25:57.947236 [Byte1]: 71
1124 09:25:57.947283
1125 09:25:57.947329 Set Vref, RX VrefLevel [Byte0]: 72
1126 09:25:57.947376 [Byte1]: 72
1127 09:25:57.947423
1128 09:25:57.947470 Set Vref, RX VrefLevel [Byte0]: 73
1129 09:25:57.947517 [Byte1]: 73
1130 09:25:57.947572
1131 09:25:57.947620 Set Vref, RX VrefLevel [Byte0]: 74
1132 09:25:57.947668 [Byte1]: 74
1133 09:25:57.947715
1134 09:25:57.947762 Set Vref, RX VrefLevel [Byte0]: 75
1135 09:25:57.948016 [Byte1]: 75
1136 09:25:57.948071
1137 09:25:57.948121 Set Vref, RX VrefLevel [Byte0]: 76
1138 09:25:57.948171 [Byte1]: 76
1139 09:25:57.948228
1140 09:25:57.948318 Set Vref, RX VrefLevel [Byte0]: 77
1141 09:25:57.948377 [Byte1]: 77
1142 09:25:57.948427
1143 09:25:57.948476 Set Vref, RX VrefLevel [Byte0]: 78
1144 09:25:57.948562 [Byte1]: 78
1145 09:25:57.948650
1146 09:25:57.948707 Final RX Vref Byte 0 = 64 to rank0
1147 09:25:57.948759 Final RX Vref Byte 1 = 59 to rank0
1148 09:25:57.948809 Final RX Vref Byte 0 = 64 to rank1
1149 09:25:57.948859 Final RX Vref Byte 1 = 59 to rank1==
1150 09:25:57.948913 Dram Type= 6, Freq= 0, CH_0, rank 0
1151 09:25:57.948976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 09:25:57.949025 ==
1153 09:25:57.949094 DQS Delay:
1154 09:25:57.949143 DQS0 = 0, DQS1 = 0
1155 09:25:57.949191 DQM Delay:
1156 09:25:57.949239 DQM0 = 81, DQM1 = 68
1157 09:25:57.949288 DQ Delay:
1158 09:25:57.949351 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1159 09:25:57.949398 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =92
1160 09:25:57.949445 DQ8 =64, DQ9 =56, DQ10 =68, DQ11 =60
1161 09:25:57.949493 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1162 09:25:57.949540
1163 09:25:57.949587
1164 09:25:57.949635 [DQSOSCAuto] RK0, (LSB)MR18= 0x2727, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1165 09:25:57.949684 CH0 RK0: MR19=606, MR18=2727
1166 09:25:57.949732 CH0_RK0: MR19=0x606, MR18=0x2727, DQSOSC=400, MR23=63, INC=92, DEC=61
1167 09:25:57.949779
1168 09:25:57.949826 ----->DramcWriteLeveling(PI) begin...
1169 09:25:57.949875 ==
1170 09:25:57.949922 Dram Type= 6, Freq= 0, CH_0, rank 1
1171 09:25:57.949969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1172 09:25:57.950017 ==
1173 09:25:57.950065 Write leveling (Byte 0): 31 => 31
1174 09:25:57.950113 Write leveling (Byte 1): 29 => 29
1175 09:25:57.950160 DramcWriteLeveling(PI) end<-----
1176 09:25:57.950207
1177 09:25:57.950255 ==
1178 09:25:57.950302 Dram Type= 6, Freq= 0, CH_0, rank 1
1179 09:25:57.950349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1180 09:25:57.950397 ==
1181 09:25:57.950444 [Gating] SW mode calibration
1182 09:25:57.950491 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1183 09:25:57.950540 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1184 09:25:57.950588 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1185 09:25:57.950636 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1186 09:25:57.950699 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1187 09:25:57.950748 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 09:25:57.950797 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 09:25:57.950859 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 09:25:57.950923 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 09:25:57.950972 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 09:25:57.951052 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 09:25:57.951103 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 09:25:57.951183 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 09:25:57.951246 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 09:25:57.951294 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 09:25:57.951341 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 09:25:57.951388 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 09:25:57.951436 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 09:25:57.951484 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 09:25:57.951532 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1202 09:25:57.951579 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1203 09:25:57.951627 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1204 09:25:57.951674 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 09:25:57.951722 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 09:25:57.951769 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 09:25:57.951816 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 09:25:57.951864 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 09:25:57.951911 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 09:25:57.951959 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1211 09:25:57.952036 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1212 09:25:57.952115 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1213 09:25:57.952180 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1214 09:25:57.952242 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1215 09:25:57.952310 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1216 09:25:57.952375 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 09:25:57.952424 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 09:25:57.952474 0 10 8 | B1->B0 | 2f2f 2828 | 1 1 | (1 1) (1 0)
1219 09:25:57.952523 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 09:25:57.952572 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 09:25:57.952622 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 09:25:57.952690 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 09:25:57.952768 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 09:25:57.952816 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 09:25:57.952864 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1226 09:25:57.952913 0 11 8 | B1->B0 | 3434 3b3b | 0 1 | (0 0) (0 0)
1227 09:25:57.952995 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1228 09:25:57.953049 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 09:25:57.953115 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 09:25:57.953199 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 09:25:57.953249 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 09:25:57.953297 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 09:25:57.953349 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1234 09:25:57.953398 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1235 09:25:57.953462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1236 09:25:57.953743 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 09:25:57.953835 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 09:25:57.953907 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 09:25:57.954003 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 09:25:57.954096 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 09:25:57.954148 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 09:25:57.954228 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 09:25:57.954297 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 09:25:57.954374 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 09:25:57.954451 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 09:25:57.954559 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 09:25:57.954634 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 09:25:57.954710 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 09:25:57.954786 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 09:25:57.954893 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1251 09:25:57.954969 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 09:25:57.955044 Total UI for P1: 0, mck2ui 16
1253 09:25:57.955120 best dqsien dly found for B0: ( 0, 14, 8)
1254 09:25:57.955196 Total UI for P1: 0, mck2ui 16
1255 09:25:57.955304 best dqsien dly found for B1: ( 0, 14, 8)
1256 09:25:57.955381 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1257 09:25:57.955457 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1258 09:25:57.955532
1259 09:25:57.955625 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1260 09:25:57.955715 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1261 09:25:57.955784 [Gating] SW calibration Done
1262 09:25:57.955833 ==
1263 09:25:57.955881 Dram Type= 6, Freq= 0, CH_0, rank 1
1264 09:25:57.955948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1265 09:25:57.956045 ==
1266 09:25:57.956096 RX Vref Scan: 0
1267 09:25:57.956159
1268 09:25:57.956210 RX Vref 0 -> 0, step: 1
1269 09:25:57.956258
1270 09:25:57.956309 RX Delay -130 -> 252, step: 16
1271 09:25:57.956358 iDelay=222, Bit 0, Center 77 (-34 ~ 189) 224
1272 09:25:57.956406 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1273 09:25:57.956454 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1274 09:25:57.956506 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1275 09:25:57.956583 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1276 09:25:57.956681 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1277 09:25:57.956746 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1278 09:25:57.956795 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1279 09:25:57.956843 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1280 09:25:57.956892 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1281 09:25:57.956940 iDelay=222, Bit 10, Center 61 (-66 ~ 189) 256
1282 09:25:57.956988 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1283 09:25:57.957036 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1284 09:25:57.957084 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1285 09:25:57.957132 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1286 09:25:57.957180 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1287 09:25:57.957228 ==
1288 09:25:57.957275 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 09:25:57.957323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 09:25:57.957371 ==
1291 09:25:57.957419 DQS Delay:
1292 09:25:57.957467 DQS0 = 0, DQS1 = 0
1293 09:25:57.957514 DQM Delay:
1294 09:25:57.957562 DQM0 = 78, DQM1 = 68
1295 09:25:57.957609 DQ Delay:
1296 09:25:57.957656 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1297 09:25:57.957703 DQ4 =77, DQ5 =61, DQ6 =93, DQ7 =93
1298 09:25:57.957751 DQ8 =61, DQ9 =53, DQ10 =61, DQ11 =61
1299 09:25:57.957799 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1300 09:25:57.957846
1301 09:25:57.957893
1302 09:25:57.957939 ==
1303 09:25:57.957987 Dram Type= 6, Freq= 0, CH_0, rank 1
1304 09:25:57.958073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1305 09:25:57.958128 ==
1306 09:25:57.958204
1307 09:25:57.958281
1308 09:25:57.958330 TX Vref Scan disable
1309 09:25:57.958379 == TX Byte 0 ==
1310 09:25:57.958427 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1311 09:25:57.958476 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1312 09:25:57.958525 == TX Byte 1 ==
1313 09:25:57.958573 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1314 09:25:57.958621 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1315 09:25:57.958669 ==
1316 09:25:57.958717 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 09:25:57.958765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 09:25:57.958814 ==
1319 09:25:57.958861 TX Vref=22, minBit 9, minWin=26, winSum=435
1320 09:25:57.958909 TX Vref=24, minBit 1, minWin=27, winSum=439
1321 09:25:57.958957 TX Vref=26, minBit 1, minWin=27, winSum=444
1322 09:25:57.959005 TX Vref=28, minBit 1, minWin=27, winSum=443
1323 09:25:57.959053 TX Vref=30, minBit 1, minWin=27, winSum=445
1324 09:25:57.959118 TX Vref=32, minBit 10, minWin=27, winSum=446
1325 09:25:57.959181 [TxChooseVref] Worse bit 10, Min win 27, Win sum 446, Final Vref 32
1326 09:25:57.959229
1327 09:25:57.959277 Final TX Range 1 Vref 32
1328 09:25:57.959325
1329 09:25:57.959371 ==
1330 09:25:57.959419 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 09:25:57.959466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 09:25:57.959514 ==
1333 09:25:57.959560
1334 09:25:57.959607
1335 09:25:57.959653 TX Vref Scan disable
1336 09:25:57.959700 == TX Byte 0 ==
1337 09:25:57.959747 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1338 09:25:57.959794 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1339 09:25:57.959840 == TX Byte 1 ==
1340 09:25:57.959888 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1341 09:25:57.959934 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1342 09:25:57.959980
1343 09:25:57.960026 [DATLAT]
1344 09:25:57.960073 Freq=800, CH0 RK1
1345 09:25:57.960120
1346 09:25:57.960167 DATLAT Default: 0xa
1347 09:25:57.960214 0, 0xFFFF, sum = 0
1348 09:25:57.960262 1, 0xFFFF, sum = 0
1349 09:25:57.960309 2, 0xFFFF, sum = 0
1350 09:25:57.960357 3, 0xFFFF, sum = 0
1351 09:25:57.960404 4, 0xFFFF, sum = 0
1352 09:25:57.960451 5, 0xFFFF, sum = 0
1353 09:25:57.960498 6, 0xFFFF, sum = 0
1354 09:25:57.960547 7, 0xFFFF, sum = 0
1355 09:25:57.960594 8, 0xFFFF, sum = 0
1356 09:25:57.960641 9, 0x0, sum = 1
1357 09:25:57.960728 10, 0x0, sum = 2
1358 09:25:57.960777 11, 0x0, sum = 3
1359 09:25:57.960824 12, 0x0, sum = 4
1360 09:25:57.960871 best_step = 10
1361 09:25:57.960918
1362 09:25:57.960964 ==
1363 09:25:57.961011 Dram Type= 6, Freq= 0, CH_0, rank 1
1364 09:25:57.961059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1365 09:25:57.961106 ==
1366 09:25:57.961153 RX Vref Scan: 0
1367 09:25:57.961199
1368 09:25:57.961246 RX Vref 0 -> 0, step: 1
1369 09:25:57.961292
1370 09:25:57.961338 RX Delay -111 -> 252, step: 8
1371 09:25:57.961384 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1372 09:25:57.961620 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1373 09:25:57.961674 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1374 09:25:57.961723 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1375 09:25:57.961772 iDelay=209, Bit 4, Center 80 (-31 ~ 192) 224
1376 09:25:57.961820 iDelay=209, Bit 5, Center 64 (-47 ~ 176) 224
1377 09:25:57.961868 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1378 09:25:57.961915 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1379 09:25:57.961963 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1380 09:25:57.962010 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1381 09:25:57.962058 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1382 09:25:57.962105 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1383 09:25:57.962152 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1384 09:25:57.962199 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1385 09:25:57.962246 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1386 09:25:57.962293 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1387 09:25:57.962340 ==
1388 09:25:57.962387 Dram Type= 6, Freq= 0, CH_0, rank 1
1389 09:25:57.962435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 09:25:57.962483 ==
1391 09:25:57.962530 DQS Delay:
1392 09:25:57.962577 DQS0 = 0, DQS1 = 0
1393 09:25:57.962624 DQM Delay:
1394 09:25:57.962670 DQM0 = 80, DQM1 = 71
1395 09:25:57.962717 DQ Delay:
1396 09:25:57.962763 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =76
1397 09:25:57.962810 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =92
1398 09:25:57.962857 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1399 09:25:57.962903 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1400 09:25:57.962950
1401 09:25:57.962996
1402 09:25:57.963042 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
1403 09:25:57.963090 CH0 RK1: MR19=606, MR18=4D29
1404 09:25:57.963138 CH0_RK1: MR19=0x606, MR18=0x4D29, DQSOSC=390, MR23=63, INC=97, DEC=64
1405 09:25:57.963186 [RxdqsGatingPostProcess] freq 800
1406 09:25:57.963233 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1407 09:25:57.963280 Pre-setting of DQS Precalculation
1408 09:25:57.963327 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1409 09:25:57.963374 ==
1410 09:25:57.963421 Dram Type= 6, Freq= 0, CH_1, rank 0
1411 09:25:57.963490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 09:25:57.963550 ==
1413 09:25:57.963598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1414 09:25:57.963645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1415 09:25:57.963692 [CA 0] Center 36 (6~66) winsize 61
1416 09:25:57.963739 [CA 1] Center 37 (7~67) winsize 61
1417 09:25:57.963785 [CA 2] Center 34 (4~64) winsize 61
1418 09:25:57.963832 [CA 3] Center 34 (4~64) winsize 61
1419 09:25:57.963879 [CA 4] Center 34 (4~65) winsize 62
1420 09:25:57.963925 [CA 5] Center 34 (4~64) winsize 61
1421 09:25:57.963972
1422 09:25:57.964018 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1423 09:25:57.964064
1424 09:25:57.964111 [CATrainingPosCal] consider 1 rank data
1425 09:25:57.964157 u2DelayCellTimex100 = 270/100 ps
1426 09:25:57.964204 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1427 09:25:57.964251 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1428 09:25:57.964298 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 09:25:57.964346 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1430 09:25:57.964393 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1431 09:25:57.964440 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1432 09:25:57.964503
1433 09:25:57.964551 CA PerBit enable=1, Macro0, CA PI delay=34
1434 09:25:57.964599
1435 09:25:57.964651 [CBTSetCACLKResult] CA Dly = 34
1436 09:25:57.964713 CS Dly: 5 (0~36)
1437 09:25:57.964760 ==
1438 09:25:57.964807 Dram Type= 6, Freq= 0, CH_1, rank 1
1439 09:25:57.964854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 09:25:57.964902 ==
1441 09:25:57.964949 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1442 09:25:57.964997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1443 09:25:57.965044 [CA 0] Center 37 (7~67) winsize 61
1444 09:25:57.965091 [CA 1] Center 36 (6~67) winsize 62
1445 09:25:57.965137 [CA 2] Center 35 (5~65) winsize 61
1446 09:25:57.965184 [CA 3] Center 34 (4~64) winsize 61
1447 09:25:57.965231 [CA 4] Center 34 (4~65) winsize 62
1448 09:25:57.965278 [CA 5] Center 33 (3~64) winsize 62
1449 09:25:57.965325
1450 09:25:57.965371 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1451 09:25:57.965418
1452 09:25:57.965465 [CATrainingPosCal] consider 2 rank data
1453 09:25:57.965512 u2DelayCellTimex100 = 270/100 ps
1454 09:25:57.965559 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1455 09:25:57.965606 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1456 09:25:57.965652 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1457 09:25:57.965699 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1458 09:25:57.965747 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 09:25:57.965794 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1460 09:25:57.965840
1461 09:25:57.965887 CA PerBit enable=1, Macro0, CA PI delay=34
1462 09:25:57.965934
1463 09:25:57.965980 [CBTSetCACLKResult] CA Dly = 34
1464 09:25:57.966026 CS Dly: 5 (0~37)
1465 09:25:57.966072
1466 09:25:57.966119 ----->DramcWriteLeveling(PI) begin...
1467 09:25:57.966167 ==
1468 09:25:57.966213 Dram Type= 6, Freq= 0, CH_1, rank 0
1469 09:25:57.966260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1470 09:25:57.966307 ==
1471 09:25:57.966353 Write leveling (Byte 0): 28 => 28
1472 09:25:57.966401 Write leveling (Byte 1): 28 => 28
1473 09:25:57.966447 DramcWriteLeveling(PI) end<-----
1474 09:25:57.966494
1475 09:25:57.966540 ==
1476 09:25:57.966586 Dram Type= 6, Freq= 0, CH_1, rank 0
1477 09:25:57.966633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1478 09:25:57.966680 ==
1479 09:25:57.966726 [Gating] SW mode calibration
1480 09:25:57.966774 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1481 09:25:57.966821 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1482 09:25:57.966869 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1483 09:25:57.966916 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1484 09:25:57.966962 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1485 09:25:57.967009 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 09:25:57.967056 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 09:25:57.967103 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 09:25:57.967150 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 09:25:57.967383 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 09:25:57.967436 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 09:25:57.967485 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 09:25:57.967533 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 09:25:57.967580 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 09:25:57.967629 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 09:25:57.967677 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 09:25:57.967739 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 09:25:57.967800 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 09:25:57.967848 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 09:25:57.967895 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 09:25:57.967941 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1501 09:25:57.967988 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 09:25:57.968035 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 09:25:57.968082 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 09:25:57.968129 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 09:25:57.968176 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 09:25:57.968223 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 09:25:57.968270 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 09:25:57.968317 0 9 8 | B1->B0 | 2b2b 2e2e | 0 1 | (0 0) (1 1)
1509 09:25:57.968364 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1510 09:25:57.968411 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1511 09:25:57.968474 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1512 09:25:57.968523 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1513 09:25:57.968571 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1514 09:25:57.968619 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 09:25:57.968687 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
1516 09:25:57.968735 0 10 8 | B1->B0 | 2c2c 2828 | 0 0 | (0 0) (1 0)
1517 09:25:57.968781 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 09:25:57.968828 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 09:25:57.968875 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 09:25:57.968922 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 09:25:57.968968 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 09:25:57.969015 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 09:25:57.969062 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1524 09:25:57.969110 0 11 8 | B1->B0 | 3636 3838 | 0 0 | (0 0) (0 0)
1525 09:25:57.969157 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 09:25:57.969203 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 09:25:57.969250 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 09:25:57.969298 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 09:25:57.969345 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 09:25:57.969392 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 09:25:57.969439 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 09:25:57.969516 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 09:25:57.969562 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 09:25:57.969609 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 09:25:57.969655 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 09:25:57.969702 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 09:25:57.969749 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 09:25:57.969796 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 09:25:57.969843 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 09:25:57.969890 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 09:25:57.969937 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 09:25:57.969985 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 09:25:57.970031 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 09:25:57.970078 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 09:25:57.970125 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 09:25:57.970172 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 09:25:57.970219 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 09:25:57.970265 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1549 09:25:57.970312 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 09:25:57.970359 Total UI for P1: 0, mck2ui 16
1551 09:25:57.970406 best dqsien dly found for B0: ( 0, 14, 8)
1552 09:25:57.970453 Total UI for P1: 0, mck2ui 16
1553 09:25:57.970500 best dqsien dly found for B1: ( 0, 14, 8)
1554 09:25:57.970546 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1555 09:25:57.970594 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1556 09:25:57.970641
1557 09:25:57.970687 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1558 09:25:57.970735 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1559 09:25:57.970782 [Gating] SW calibration Done
1560 09:25:57.970829 ==
1561 09:25:57.970876 Dram Type= 6, Freq= 0, CH_1, rank 0
1562 09:25:57.970923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1563 09:25:57.970970 ==
1564 09:25:57.971018 RX Vref Scan: 0
1565 09:25:57.971065
1566 09:25:57.971112 RX Vref 0 -> 0, step: 1
1567 09:25:57.971158
1568 09:25:57.971204 RX Delay -130 -> 252, step: 16
1569 09:25:57.971251 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1570 09:25:57.971298 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1571 09:25:57.971345 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1572 09:25:57.971392 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1573 09:25:57.971439 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1574 09:25:57.971507 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1575 09:25:57.971568 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1576 09:25:57.971614 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1577 09:25:57.971661 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1578 09:25:57.971708 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1579 09:25:57.971942 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1580 09:25:57.971997 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1581 09:25:57.972046 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1582 09:25:57.972094 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1583 09:25:57.972141 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1584 09:25:57.972188 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1585 09:25:57.972263 ==
1586 09:25:57.972310 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 09:25:57.972357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 09:25:57.972404 ==
1589 09:25:57.972450 DQS Delay:
1590 09:25:57.972499 DQS0 = 0, DQS1 = 0
1591 09:25:57.972546 DQM Delay:
1592 09:25:57.972609 DQM0 = 80, DQM1 = 70
1593 09:25:57.972680 DQ Delay:
1594 09:25:57.972728 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1595 09:25:57.972775 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1596 09:25:57.972821 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1597 09:25:57.972870 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1598 09:25:57.972917
1599 09:25:57.972963
1600 09:25:57.973009 ==
1601 09:25:57.973055 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 09:25:57.973102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 09:25:57.973150 ==
1604 09:25:57.973196
1605 09:25:57.973242
1606 09:25:57.973289 TX Vref Scan disable
1607 09:25:57.973336 == TX Byte 0 ==
1608 09:25:57.973382 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1609 09:25:57.973430 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1610 09:25:57.973477 == TX Byte 1 ==
1611 09:25:57.973523 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1612 09:25:57.973570 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1613 09:25:57.973617 ==
1614 09:25:57.973663 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 09:25:57.973710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 09:25:57.973757 ==
1617 09:25:57.973804 TX Vref=22, minBit 1, minWin=26, winSum=438
1618 09:25:57.973852 TX Vref=24, minBit 1, minWin=27, winSum=442
1619 09:25:57.973899 TX Vref=26, minBit 5, minWin=27, winSum=446
1620 09:25:57.973946 TX Vref=28, minBit 4, minWin=27, winSum=451
1621 09:25:57.973993 TX Vref=30, minBit 4, minWin=27, winSum=448
1622 09:25:57.974040 TX Vref=32, minBit 0, minWin=27, winSum=446
1623 09:25:57.974087 [TxChooseVref] Worse bit 4, Min win 27, Win sum 451, Final Vref 28
1624 09:25:57.974134
1625 09:25:57.974180 Final TX Range 1 Vref 28
1626 09:25:57.974228
1627 09:25:57.974274 ==
1628 09:25:57.974319 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 09:25:57.974366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 09:25:57.974413 ==
1631 09:25:57.974459
1632 09:25:57.974505
1633 09:25:57.974552 TX Vref Scan disable
1634 09:25:57.974598 == TX Byte 0 ==
1635 09:25:57.974645 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1636 09:25:57.974691 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1637 09:25:57.974738 == TX Byte 1 ==
1638 09:25:57.974784 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1639 09:25:57.974831 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1640 09:25:57.974878
1641 09:25:57.974923 [DATLAT]
1642 09:25:57.974970 Freq=800, CH1 RK0
1643 09:25:57.975016
1644 09:25:57.975062 DATLAT Default: 0xa
1645 09:25:57.975123 0, 0xFFFF, sum = 0
1646 09:25:57.975185 1, 0xFFFF, sum = 0
1647 09:25:57.975232 2, 0xFFFF, sum = 0
1648 09:25:57.975280 3, 0xFFFF, sum = 0
1649 09:25:57.975328 4, 0xFFFF, sum = 0
1650 09:25:57.975375 5, 0xFFFF, sum = 0
1651 09:25:57.975422 6, 0xFFFF, sum = 0
1652 09:25:57.975469 7, 0xFFFF, sum = 0
1653 09:25:57.975516 8, 0xFFFF, sum = 0
1654 09:25:57.975563 9, 0x0, sum = 1
1655 09:25:57.975610 10, 0x0, sum = 2
1656 09:25:57.975658 11, 0x0, sum = 3
1657 09:25:57.975704 12, 0x0, sum = 4
1658 09:25:57.975751 best_step = 10
1659 09:25:57.975797
1660 09:25:57.975843 ==
1661 09:25:57.975889 Dram Type= 6, Freq= 0, CH_1, rank 0
1662 09:25:57.975936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1663 09:25:57.975983 ==
1664 09:25:57.976029 RX Vref Scan: 1
1665 09:25:57.976075
1666 09:25:57.976121 Set Vref Range= 32 -> 127
1667 09:25:57.976166
1668 09:25:57.976212 RX Vref 32 -> 127, step: 1
1669 09:25:57.976258
1670 09:25:57.976304 RX Delay -111 -> 252, step: 8
1671 09:25:57.976350
1672 09:25:57.976396 Set Vref, RX VrefLevel [Byte0]: 32
1673 09:25:57.976443 [Byte1]: 32
1674 09:25:57.976489
1675 09:25:57.976534 Set Vref, RX VrefLevel [Byte0]: 33
1676 09:25:57.976626 [Byte1]: 33
1677 09:25:57.976731
1678 09:25:57.976780 Set Vref, RX VrefLevel [Byte0]: 34
1679 09:25:57.976833 [Byte1]: 34
1680 09:25:57.976889
1681 09:25:57.976938 Set Vref, RX VrefLevel [Byte0]: 35
1682 09:25:57.976986 [Byte1]: 35
1683 09:25:57.977064
1684 09:25:57.977127 Set Vref, RX VrefLevel [Byte0]: 36
1685 09:25:57.977176 [Byte1]: 36
1686 09:25:57.977224
1687 09:25:57.977271 Set Vref, RX VrefLevel [Byte0]: 37
1688 09:25:57.977329 [Byte1]: 37
1689 09:25:57.977406
1690 09:25:57.977456 Set Vref, RX VrefLevel [Byte0]: 38
1691 09:25:57.977537 [Byte1]: 38
1692 09:25:57.977607
1693 09:25:57.977656 Set Vref, RX VrefLevel [Byte0]: 39
1694 09:25:57.977704 [Byte1]: 39
1695 09:25:57.977792
1696 09:25:57.977844 Set Vref, RX VrefLevel [Byte0]: 40
1697 09:25:57.977893 [Byte1]: 40
1698 09:25:57.977978
1699 09:25:57.978029 Set Vref, RX VrefLevel [Byte0]: 41
1700 09:25:57.978078 [Byte1]: 41
1701 09:25:57.978168
1702 09:25:57.978220 Set Vref, RX VrefLevel [Byte0]: 42
1703 09:25:57.978269 [Byte1]: 42
1704 09:25:57.978344
1705 09:25:57.978420 Set Vref, RX VrefLevel [Byte0]: 43
1706 09:25:57.978497 [Byte1]: 43
1707 09:25:57.978572
1708 09:25:57.978647 Set Vref, RX VrefLevel [Byte0]: 44
1709 09:25:57.978723 [Byte1]: 44
1710 09:25:57.978797
1711 09:25:57.978872 Set Vref, RX VrefLevel [Byte0]: 45
1712 09:25:57.978947 [Byte1]: 45
1713 09:25:57.979021
1714 09:25:57.979095 Set Vref, RX VrefLevel [Byte0]: 46
1715 09:25:57.979170 [Byte1]: 46
1716 09:25:57.979244
1717 09:25:57.979318 Set Vref, RX VrefLevel [Byte0]: 47
1718 09:25:57.979393 [Byte1]: 47
1719 09:25:57.979467
1720 09:25:57.979542 Set Vref, RX VrefLevel [Byte0]: 48
1721 09:25:57.979617 [Byte1]: 48
1722 09:25:57.979690
1723 09:25:57.979764 Set Vref, RX VrefLevel [Byte0]: 49
1724 09:25:57.979839 [Byte1]: 49
1725 09:25:57.979913
1726 09:25:57.979987 Set Vref, RX VrefLevel [Byte0]: 50
1727 09:25:57.980063 [Byte1]: 50
1728 09:25:57.980137
1729 09:25:57.980211 Set Vref, RX VrefLevel [Byte0]: 51
1730 09:25:57.980286 [Byte1]: 51
1731 09:25:57.980359
1732 09:25:57.980434 Set Vref, RX VrefLevel [Byte0]: 52
1733 09:25:57.980509 [Byte1]: 52
1734 09:25:57.980596
1735 09:25:57.980688 Set Vref, RX VrefLevel [Byte0]: 53
1736 09:25:57.980738 [Byte1]: 53
1737 09:25:57.980786
1738 09:25:57.980833 Set Vref, RX VrefLevel [Byte0]: 54
1739 09:25:57.980881 [Byte1]: 54
1740 09:25:57.980927
1741 09:25:57.980974 Set Vref, RX VrefLevel [Byte0]: 55
1742 09:25:57.981208 [Byte1]: 55
1743 09:25:57.981260
1744 09:25:57.981308 Set Vref, RX VrefLevel [Byte0]: 56
1745 09:25:57.981356 [Byte1]: 56
1746 09:25:57.981404
1747 09:25:57.981451 Set Vref, RX VrefLevel [Byte0]: 57
1748 09:25:57.981499 [Byte1]: 57
1749 09:25:57.981546
1750 09:25:57.981593 Set Vref, RX VrefLevel [Byte0]: 58
1751 09:25:57.981640 [Byte1]: 58
1752 09:25:57.981687
1753 09:25:57.981733 Set Vref, RX VrefLevel [Byte0]: 59
1754 09:25:57.981780 [Byte1]: 59
1755 09:25:57.981826
1756 09:25:57.981873 Set Vref, RX VrefLevel [Byte0]: 60
1757 09:25:57.981920 [Byte1]: 60
1758 09:25:57.981966
1759 09:25:57.982012 Set Vref, RX VrefLevel [Byte0]: 61
1760 09:25:57.982059 [Byte1]: 61
1761 09:25:57.982106
1762 09:25:57.982153 Set Vref, RX VrefLevel [Byte0]: 62
1763 09:25:57.982200 [Byte1]: 62
1764 09:25:57.982246
1765 09:25:57.982293 Set Vref, RX VrefLevel [Byte0]: 63
1766 09:25:57.982341 [Byte1]: 63
1767 09:25:57.982388
1768 09:25:57.982435 Set Vref, RX VrefLevel [Byte0]: 64
1769 09:25:57.982483 [Byte1]: 64
1770 09:25:57.982530
1771 09:25:57.982577 Set Vref, RX VrefLevel [Byte0]: 65
1772 09:25:57.982624 [Byte1]: 65
1773 09:25:57.982670
1774 09:25:57.982718 Set Vref, RX VrefLevel [Byte0]: 66
1775 09:25:57.982765 [Byte1]: 66
1776 09:25:57.982811
1777 09:25:57.982858 Set Vref, RX VrefLevel [Byte0]: 67
1778 09:25:57.982906 [Byte1]: 67
1779 09:25:57.982953
1780 09:25:57.982999 Set Vref, RX VrefLevel [Byte0]: 68
1781 09:25:57.983046 [Byte1]: 68
1782 09:25:57.983094
1783 09:25:57.983140 Set Vref, RX VrefLevel [Byte0]: 69
1784 09:25:57.983187 [Byte1]: 69
1785 09:25:57.983234
1786 09:25:57.983280 Set Vref, RX VrefLevel [Byte0]: 70
1787 09:25:57.983327 [Byte1]: 70
1788 09:25:57.983375
1789 09:25:57.983421 Set Vref, RX VrefLevel [Byte0]: 71
1790 09:25:57.983468 [Byte1]: 71
1791 09:25:57.983514
1792 09:25:57.983561 Set Vref, RX VrefLevel [Byte0]: 72
1793 09:25:57.983607 [Byte1]: 72
1794 09:25:57.983654
1795 09:25:57.983700 Set Vref, RX VrefLevel [Byte0]: 73
1796 09:25:57.983747 [Byte1]: 73
1797 09:25:57.983794
1798 09:25:57.983840 Set Vref, RX VrefLevel [Byte0]: 74
1799 09:25:57.983886 [Byte1]: 74
1800 09:25:57.983933
1801 09:25:57.983980 Final RX Vref Byte 0 = 62 to rank0
1802 09:25:57.984028 Final RX Vref Byte 1 = 54 to rank0
1803 09:25:57.984075 Final RX Vref Byte 0 = 62 to rank1
1804 09:25:57.984122 Final RX Vref Byte 1 = 54 to rank1==
1805 09:25:57.984169 Dram Type= 6, Freq= 0, CH_1, rank 0
1806 09:25:57.984215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 09:25:57.984263 ==
1808 09:25:57.984310 DQS Delay:
1809 09:25:57.984356 DQS0 = 0, DQS1 = 0
1810 09:25:57.984402 DQM Delay:
1811 09:25:57.984450 DQM0 = 81, DQM1 = 71
1812 09:25:57.984497 DQ Delay:
1813 09:25:57.984544 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1814 09:25:57.984590 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1815 09:25:57.984637 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1816 09:25:57.984728 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1817 09:25:57.984776
1818 09:25:57.984822
1819 09:25:57.984868 [DQSOSCAuto] RK0, (LSB)MR18= 0x131d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1820 09:25:57.984916 CH1 RK0: MR19=606, MR18=131D
1821 09:25:57.984963 CH1_RK0: MR19=0x606, MR18=0x131D, DQSOSC=402, MR23=63, INC=91, DEC=60
1822 09:25:57.985010
1823 09:25:57.985057 ----->DramcWriteLeveling(PI) begin...
1824 09:25:57.985104 ==
1825 09:25:57.985151 Dram Type= 6, Freq= 0, CH_1, rank 1
1826 09:25:57.985198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1827 09:25:57.985246 ==
1828 09:25:57.985293 Write leveling (Byte 0): 29 => 29
1829 09:25:57.985340 Write leveling (Byte 1): 29 => 29
1830 09:25:57.985387 DramcWriteLeveling(PI) end<-----
1831 09:25:57.985433
1832 09:25:57.985480 ==
1833 09:25:57.985527 Dram Type= 6, Freq= 0, CH_1, rank 1
1834 09:25:57.985574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1835 09:25:57.985620 ==
1836 09:25:57.985667 [Gating] SW mode calibration
1837 09:25:57.985714 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1838 09:25:57.985762 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1839 09:25:57.985810 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1840 09:25:57.985858 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1841 09:25:57.985905 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1842 09:25:57.985952 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 09:25:57.985999 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 09:25:57.986047 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 09:25:57.986093 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 09:25:57.986140 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 09:25:57.986187 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 09:25:57.986234 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 09:25:57.986283 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 09:25:57.986330 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 09:25:57.986377 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 09:25:57.986424 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 09:25:57.986470 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 09:25:57.986516 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 09:25:57.986563 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 09:25:57.986628 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1857 09:25:57.986678 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 09:25:57.986725 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 09:25:57.986773 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 09:25:57.986838 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 09:25:57.986887 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 09:25:57.986933 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 09:25:57.986986 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 09:25:57.987034 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
1865 09:25:57.987082 0 9 8 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
1866 09:25:57.987130 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 09:25:57.987365 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 09:25:57.987418 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1869 09:25:57.987467 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 09:25:57.987515 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 09:25:57.987563 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1872 09:25:57.987611 0 10 4 | B1->B0 | 3131 2e2e | 1 1 | (1 1) (1 0)
1873 09:25:57.987658 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 09:25:57.987706 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 09:25:57.987753 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 09:25:57.987799 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 09:25:57.987847 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 09:25:57.987894 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 09:25:57.987942 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 09:25:57.987989 0 11 4 | B1->B0 | 2d2d 3b3b | 0 0 | (0 0) (0 0)
1881 09:25:57.988036 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1882 09:25:57.988084 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 09:25:57.988131 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 09:25:57.988178 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 09:25:57.988225 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 09:25:57.988272 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 09:25:57.988319 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 09:25:57.988366 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 09:25:57.988413 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1890 09:25:57.988459 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 09:25:57.988506 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 09:25:57.988553 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 09:25:57.988600 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 09:25:57.988657 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 09:25:57.988743 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 09:25:57.988791 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 09:25:57.988838 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 09:25:57.988885 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 09:25:57.988932 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 09:25:57.988979 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 09:25:57.989027 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 09:25:57.989074 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 09:25:57.989120 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 09:25:57.989168 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1905 09:25:57.989215 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1906 09:25:57.989264 Total UI for P1: 0, mck2ui 16
1907 09:25:57.989312 best dqsien dly found for B0: ( 0, 14, 4)
1908 09:25:57.989359 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 09:25:57.989406 Total UI for P1: 0, mck2ui 16
1910 09:25:57.989454 best dqsien dly found for B1: ( 0, 14, 6)
1911 09:25:57.989501 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1912 09:25:57.989548 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1913 09:25:57.989594
1914 09:25:57.989641 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1915 09:25:57.989689 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1916 09:25:57.989735 [Gating] SW calibration Done
1917 09:25:57.989783 ==
1918 09:25:57.989830 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 09:25:57.989878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 09:25:57.989925 ==
1921 09:25:57.989971 RX Vref Scan: 0
1922 09:25:57.990018
1923 09:25:57.990063 RX Vref 0 -> 0, step: 1
1924 09:25:57.990110
1925 09:25:57.990156 RX Delay -130 -> 252, step: 16
1926 09:25:57.990202 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1927 09:25:57.990249 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1928 09:25:57.990297 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1929 09:25:57.990344 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1930 09:25:57.990390 iDelay=206, Bit 4, Center 69 (-50 ~ 189) 240
1931 09:25:57.990437 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1932 09:25:57.990484 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1933 09:25:57.990532 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1934 09:25:57.990579 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1935 09:25:57.990625 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1936 09:25:57.990672 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1937 09:25:57.990719 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1938 09:25:57.990766 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1939 09:25:57.990812 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1940 09:25:57.990859 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1941 09:25:57.990905 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1942 09:25:57.990952 ==
1943 09:25:57.991000 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 09:25:57.991047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 09:25:57.991094 ==
1946 09:25:57.991141 DQS Delay:
1947 09:25:57.991188 DQS0 = 0, DQS1 = 0
1948 09:25:57.991234 DQM Delay:
1949 09:25:57.991320 DQM0 = 75, DQM1 = 71
1950 09:25:57.991366 DQ Delay:
1951 09:25:57.991413 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =69
1952 09:25:57.991460 DQ4 =69, DQ5 =85, DQ6 =85, DQ7 =77
1953 09:25:57.991507 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1954 09:25:57.991554 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1955 09:25:57.991601
1956 09:25:57.991646
1957 09:25:58.167126 ==
1958 09:25:58.167245 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 09:25:58.167306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 09:25:58.167362 ==
1961 09:25:58.167425
1962 09:25:58.167486
1963 09:25:58.167536 TX Vref Scan disable
1964 09:25:58.167588 == TX Byte 0 ==
1965 09:25:58.167637 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1966 09:25:58.167692 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1967 09:25:58.167742 == TX Byte 1 ==
1968 09:25:58.167791 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1969 09:25:58.167841 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1970 09:25:58.167894 ==
1971 09:25:58.167943 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 09:25:58.167992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 09:25:58.168041 ==
1974 09:25:58.168090 TX Vref=22, minBit 3, minWin=27, winSum=449
1975 09:25:58.168335 TX Vref=24, minBit 0, minWin=28, winSum=451
1976 09:25:58.168393 TX Vref=26, minBit 5, minWin=27, winSum=455
1977 09:25:58.168444 TX Vref=28, minBit 5, minWin=27, winSum=456
1978 09:25:58.168495 TX Vref=30, minBit 0, minWin=28, winSum=459
1979 09:25:58.168545 TX Vref=32, minBit 1, minWin=27, winSum=460
1980 09:25:58.168594 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1981 09:25:58.168652
1982 09:25:58.168711 Final TX Range 1 Vref 30
1983 09:25:58.168762
1984 09:25:58.168811 ==
1985 09:25:58.168860 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 09:25:58.168919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 09:25:58.168970 ==
1988 09:25:58.169018
1989 09:25:58.169065
1990 09:25:58.169121 TX Vref Scan disable
1991 09:25:58.169171 == TX Byte 0 ==
1992 09:25:58.169228 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1993 09:25:58.169279 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1994 09:25:58.169328 == TX Byte 1 ==
1995 09:25:58.169376 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1996 09:25:58.169437 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1997 09:25:58.169487
1998 09:25:58.169535 [DATLAT]
1999 09:25:58.169587 Freq=800, CH1 RK1
2000 09:25:58.169665
2001 09:25:58.169741 DATLAT Default: 0xa
2002 09:25:58.169819 0, 0xFFFF, sum = 0
2003 09:25:58.169898 1, 0xFFFF, sum = 0
2004 09:25:58.169976 2, 0xFFFF, sum = 0
2005 09:25:58.170054 3, 0xFFFF, sum = 0
2006 09:25:58.170132 4, 0xFFFF, sum = 0
2007 09:25:58.170209 5, 0xFFFF, sum = 0
2008 09:25:58.170287 6, 0xFFFF, sum = 0
2009 09:25:58.170366 7, 0xFFFF, sum = 0
2010 09:25:58.170443 8, 0xFFFF, sum = 0
2011 09:25:58.170521 9, 0x0, sum = 1
2012 09:25:58.170599 10, 0x0, sum = 2
2013 09:25:58.170680 11, 0x0, sum = 3
2014 09:25:58.170732 12, 0x0, sum = 4
2015 09:25:58.170782 best_step = 10
2016 09:25:58.170831
2017 09:25:58.170879 ==
2018 09:25:58.170927 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 09:25:58.170976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 09:25:58.171025 ==
2021 09:25:58.171073 RX Vref Scan: 0
2022 09:25:58.171121
2023 09:25:58.171169 RX Vref 0 -> 0, step: 1
2024 09:25:58.171216
2025 09:25:58.171264 RX Delay -111 -> 252, step: 8
2026 09:25:58.171313 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2027 09:25:58.171362 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2028 09:25:58.171409 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2029 09:25:58.171458 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2030 09:25:58.171506 iDelay=209, Bit 4, Center 72 (-47 ~ 192) 240
2031 09:25:58.171554 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2032 09:25:58.171602 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2033 09:25:58.171650 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2034 09:25:58.171699 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2035 09:25:58.171747 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2036 09:25:58.171795 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2037 09:25:58.171844 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2038 09:25:58.171892 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2039 09:25:58.171940 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2040 09:25:58.171989 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2041 09:25:58.172038 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2042 09:25:58.172086 ==
2043 09:25:58.172134 Dram Type= 6, Freq= 0, CH_1, rank 1
2044 09:25:58.172184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2045 09:25:58.172235 ==
2046 09:25:58.172284 DQS Delay:
2047 09:25:58.172332 DQS0 = 0, DQS1 = 0
2048 09:25:58.172380 DQM Delay:
2049 09:25:58.172429 DQM0 = 77, DQM1 = 74
2050 09:25:58.172477 DQ Delay:
2051 09:25:58.172525 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2052 09:25:58.172574 DQ4 =72, DQ5 =88, DQ6 =88, DQ7 =76
2053 09:25:58.172622 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =68
2054 09:25:58.172691 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2055 09:25:58.172742
2056 09:25:58.172790
2057 09:25:58.172838 [DQSOSCAuto] RK1, (LSB)MR18= 0x2139, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2058 09:25:58.172889 CH1 RK1: MR19=606, MR18=2139
2059 09:25:58.172938 CH1_RK1: MR19=0x606, MR18=0x2139, DQSOSC=395, MR23=63, INC=94, DEC=63
2060 09:25:58.172988 [RxdqsGatingPostProcess] freq 800
2061 09:25:58.173036 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2062 09:25:58.173086 Pre-setting of DQS Precalculation
2063 09:25:58.173135 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2064 09:25:58.173184 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2065 09:25:58.173234 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2066 09:25:58.173283
2067 09:25:58.173331
2068 09:25:58.173380 [Calibration Summary] 1600 Mbps
2069 09:25:58.173442 CH 0, Rank 0
2070 09:25:58.173498 SW Impedance : PASS
2071 09:25:58.173547 DUTY Scan : NO K
2072 09:25:58.173596 ZQ Calibration : PASS
2073 09:25:58.173644 Jitter Meter : NO K
2074 09:25:58.173692 CBT Training : PASS
2075 09:25:58.173740 Write leveling : PASS
2076 09:25:58.173788 RX DQS gating : PASS
2077 09:25:58.173837 RX DQ/DQS(RDDQC) : PASS
2078 09:25:58.173885 TX DQ/DQS : PASS
2079 09:25:58.173934 RX DATLAT : PASS
2080 09:25:58.173982 RX DQ/DQS(Engine): PASS
2081 09:25:58.174030 TX OE : NO K
2082 09:25:58.174078 All Pass.
2083 09:25:58.174127
2084 09:25:58.174175 CH 0, Rank 1
2085 09:25:58.174223 SW Impedance : PASS
2086 09:25:58.174271 DUTY Scan : NO K
2087 09:25:58.174320 ZQ Calibration : PASS
2088 09:25:58.174368 Jitter Meter : NO K
2089 09:25:58.174416 CBT Training : PASS
2090 09:25:58.174464 Write leveling : PASS
2091 09:25:58.174513 RX DQS gating : PASS
2092 09:25:58.174561 RX DQ/DQS(RDDQC) : PASS
2093 09:25:58.174609 TX DQ/DQS : PASS
2094 09:25:58.174658 RX DATLAT : PASS
2095 09:25:58.174705 RX DQ/DQS(Engine): PASS
2096 09:25:58.174753 TX OE : NO K
2097 09:25:58.174801 All Pass.
2098 09:25:58.174850
2099 09:25:58.174897 CH 1, Rank 0
2100 09:25:58.174946 SW Impedance : PASS
2101 09:25:58.174994 DUTY Scan : NO K
2102 09:25:58.175043 ZQ Calibration : PASS
2103 09:25:58.175091 Jitter Meter : NO K
2104 09:25:58.175139 CBT Training : PASS
2105 09:25:58.175187 Write leveling : PASS
2106 09:25:58.175235 RX DQS gating : PASS
2107 09:25:58.175283 RX DQ/DQS(RDDQC) : PASS
2108 09:25:58.175330 TX DQ/DQS : PASS
2109 09:25:58.175378 RX DATLAT : PASS
2110 09:25:58.175427 RX DQ/DQS(Engine): PASS
2111 09:25:58.175476 TX OE : NO K
2112 09:25:58.175525 All Pass.
2113 09:25:58.175573
2114 09:25:58.175621 CH 1, Rank 1
2115 09:25:58.175670 SW Impedance : PASS
2116 09:25:58.175719 DUTY Scan : NO K
2117 09:25:58.175766 ZQ Calibration : PASS
2118 09:25:58.175814 Jitter Meter : NO K
2119 09:25:58.175862 CBT Training : PASS
2120 09:25:58.175911 Write leveling : PASS
2121 09:25:58.175959 RX DQS gating : PASS
2122 09:25:58.176007 RX DQ/DQS(RDDQC) : PASS
2123 09:25:58.176054 TX DQ/DQS : PASS
2124 09:25:58.176103 RX DATLAT : PASS
2125 09:25:58.176151 RX DQ/DQS(Engine): PASS
2126 09:25:58.176394 TX OE : NO K
2127 09:25:58.176450 All Pass.
2128 09:25:58.176500
2129 09:25:58.176548 DramC Write-DBI off
2130 09:25:58.176598 PER_BANK_REFRESH: Hybrid Mode
2131 09:25:58.176655 TX_TRACKING: ON
2132 09:25:58.176707 [GetDramInforAfterCalByMRR] Vendor 6.
2133 09:25:58.176756 [GetDramInforAfterCalByMRR] Revision 606.
2134 09:25:58.176805 [GetDramInforAfterCalByMRR] Revision 2 0.
2135 09:25:58.176854 MR0 0x3b3b
2136 09:25:58.176902 MR8 0x5151
2137 09:25:58.176950 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2138 09:25:58.176999
2139 09:25:58.177072 MR0 0x3b3b
2140 09:25:58.177122 MR8 0x5151
2141 09:25:58.177171 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2142 09:25:58.177220
2143 09:25:58.177268 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2144 09:25:58.177319 [FAST_K] Save calibration result to emmc
2145 09:25:58.177369 [FAST_K] Save calibration result to emmc
2146 09:25:58.177418 dram_init: config_dvfs: 1
2147 09:25:58.177467 dramc_set_vcore_voltage set vcore to 662500
2148 09:25:58.177515 Read voltage for 1200, 2
2149 09:25:58.177564 Vio18 = 0
2150 09:25:58.177613 Vcore = 662500
2151 09:25:58.177661 Vdram = 0
2152 09:25:58.177710 Vddq = 0
2153 09:25:58.177758 Vmddr = 0
2154 09:25:58.177807 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2155 09:25:58.177856 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2156 09:25:58.177905 MEM_TYPE=3, freq_sel=15
2157 09:25:58.177953 sv_algorithm_assistance_LP4_1600
2158 09:25:58.178002 ============ PULL DRAM RESETB DOWN ============
2159 09:25:58.178052 ========== PULL DRAM RESETB DOWN end =========
2160 09:25:58.178101 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2161 09:25:58.178151 ===================================
2162 09:25:58.178199 LPDDR4 DRAM CONFIGURATION
2163 09:25:58.178247 ===================================
2164 09:25:58.178295 EX_ROW_EN[0] = 0x0
2165 09:25:58.178343 EX_ROW_EN[1] = 0x0
2166 09:25:58.178391 LP4Y_EN = 0x0
2167 09:25:58.178438 WORK_FSP = 0x0
2168 09:25:58.178487 WL = 0x4
2169 09:25:58.178535 RL = 0x4
2170 09:25:58.178583 BL = 0x2
2171 09:25:58.178630 RPST = 0x0
2172 09:25:58.178679 RD_PRE = 0x0
2173 09:25:58.178726 WR_PRE = 0x1
2174 09:25:58.178775 WR_PST = 0x0
2175 09:25:58.178822 DBI_WR = 0x0
2176 09:25:58.178870 DBI_RD = 0x0
2177 09:25:58.178917 OTF = 0x1
2178 09:25:58.178966 ===================================
2179 09:25:58.179015 ===================================
2180 09:25:58.179064 ANA top config
2181 09:25:58.179112 ===================================
2182 09:25:58.179161 DLL_ASYNC_EN = 0
2183 09:25:58.179209 ALL_SLAVE_EN = 0
2184 09:25:58.179257 NEW_RANK_MODE = 1
2185 09:25:58.179307 DLL_IDLE_MODE = 1
2186 09:25:58.179355 LP45_APHY_COMB_EN = 1
2187 09:25:58.179408 TX_ODT_DIS = 1
2188 09:25:58.179463 NEW_8X_MODE = 1
2189 09:25:58.179521 ===================================
2190 09:25:58.179571 ===================================
2191 09:25:58.179620 data_rate = 2400
2192 09:25:58.179669 CKR = 1
2193 09:25:58.179722 DQ_P2S_RATIO = 8
2194 09:25:58.179773 ===================================
2195 09:25:58.179822 CA_P2S_RATIO = 8
2196 09:25:58.179870 DQ_CA_OPEN = 0
2197 09:25:58.179926 DQ_SEMI_OPEN = 0
2198 09:25:58.179975 CA_SEMI_OPEN = 0
2199 09:25:58.180024 CA_FULL_RATE = 0
2200 09:25:58.180073 DQ_CKDIV4_EN = 0
2201 09:25:58.180127 CA_CKDIV4_EN = 0
2202 09:25:58.180176 CA_PREDIV_EN = 0
2203 09:25:58.180225 PH8_DLY = 17
2204 09:25:58.180274 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2205 09:25:58.180333 DQ_AAMCK_DIV = 4
2206 09:25:58.180393 CA_AAMCK_DIV = 4
2207 09:25:58.180443 CA_ADMCK_DIV = 4
2208 09:25:58.180492 DQ_TRACK_CA_EN = 0
2209 09:25:58.180541 CA_PICK = 1200
2210 09:25:58.180590 CA_MCKIO = 1200
2211 09:25:58.180639 MCKIO_SEMI = 0
2212 09:25:58.180696 PLL_FREQ = 2366
2213 09:25:58.180745 DQ_UI_PI_RATIO = 32
2214 09:25:58.180794 CA_UI_PI_RATIO = 0
2215 09:25:58.180843 ===================================
2216 09:25:58.180892 ===================================
2217 09:25:58.180941 memory_type:LPDDR4
2218 09:25:58.180990 GP_NUM : 10
2219 09:25:58.181038 SRAM_EN : 1
2220 09:25:58.181086 MD32_EN : 0
2221 09:25:58.181135 ===================================
2222 09:25:58.181185 [ANA_INIT] >>>>>>>>>>>>>>
2223 09:25:58.181233 <<<<<< [CONFIGURE PHASE]: ANA_TX
2224 09:25:58.181282 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2225 09:25:58.181331 ===================================
2226 09:25:58.181380 data_rate = 2400,PCW = 0X5b00
2227 09:25:58.181429 ===================================
2228 09:25:58.181478 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2229 09:25:58.181527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2230 09:25:58.181576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2231 09:25:58.181625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2232 09:25:58.181674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2233 09:25:58.181723 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2234 09:25:58.181771 [ANA_INIT] flow start
2235 09:25:58.181819 [ANA_INIT] PLL >>>>>>>>
2236 09:25:58.181869 [ANA_INIT] PLL <<<<<<<<
2237 09:25:58.181918 [ANA_INIT] MIDPI >>>>>>>>
2238 09:25:58.181966 [ANA_INIT] MIDPI <<<<<<<<
2239 09:25:58.182014 [ANA_INIT] DLL >>>>>>>>
2240 09:25:58.182063 [ANA_INIT] DLL <<<<<<<<
2241 09:25:58.182111 [ANA_INIT] flow end
2242 09:25:58.182159 ============ LP4 DIFF to SE enter ============
2243 09:25:58.182208 ============ LP4 DIFF to SE exit ============
2244 09:25:58.182257 [ANA_INIT] <<<<<<<<<<<<<
2245 09:25:58.182316 [Flow] Enable top DCM control >>>>>
2246 09:25:58.182370 [Flow] Enable top DCM control <<<<<
2247 09:25:58.182460 Enable DLL master slave shuffle
2248 09:25:58.182515 ==============================================================
2249 09:25:58.182564 Gating Mode config
2250 09:25:58.182614 ==============================================================
2251 09:25:58.182663 Config description:
2252 09:25:58.182712 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2253 09:25:58.182960 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2254 09:25:58.183017 SELPH_MODE 0: By rank 1: By Phase
2255 09:25:58.183068 ==============================================================
2256 09:25:58.183118 GAT_TRACK_EN = 1
2257 09:25:58.183167 RX_GATING_MODE = 2
2258 09:25:58.183216 RX_GATING_TRACK_MODE = 2
2259 09:25:58.183265 SELPH_MODE = 1
2260 09:25:58.183313 PICG_EARLY_EN = 1
2261 09:25:58.183362 VALID_LAT_VALUE = 1
2262 09:25:58.183437 ==============================================================
2263 09:25:58.183489 Enter into Gating configuration >>>>
2264 09:25:58.183539 Exit from Gating configuration <<<<
2265 09:25:58.183588 Enter into DVFS_PRE_config >>>>>
2266 09:25:58.183638 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2267 09:25:58.183689 Exit from DVFS_PRE_config <<<<<
2268 09:25:58.183738 Enter into PICG configuration >>>>
2269 09:25:58.183788 Exit from PICG configuration <<<<
2270 09:25:58.183837 [RX_INPUT] configuration >>>>>
2271 09:25:58.183885 [RX_INPUT] configuration <<<<<
2272 09:25:58.183934 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2273 09:25:58.183983 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2274 09:25:58.184032 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2275 09:25:58.184081 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2276 09:25:58.184131 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2277 09:25:58.184180 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2278 09:25:58.184229 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2279 09:25:58.184279 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2280 09:25:58.184328 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2281 09:25:58.184377 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2282 09:25:58.184427 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2283 09:25:58.184475 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2284 09:25:58.184524 ===================================
2285 09:25:58.184574 LPDDR4 DRAM CONFIGURATION
2286 09:25:58.184623 ===================================
2287 09:25:58.184683 EX_ROW_EN[0] = 0x0
2288 09:25:58.184733 EX_ROW_EN[1] = 0x0
2289 09:25:58.184782 LP4Y_EN = 0x0
2290 09:25:58.184830 WORK_FSP = 0x0
2291 09:25:58.184878 WL = 0x4
2292 09:25:58.184926 RL = 0x4
2293 09:25:58.184974 BL = 0x2
2294 09:25:58.185023 RPST = 0x0
2295 09:25:58.185071 RD_PRE = 0x0
2296 09:25:58.185119 WR_PRE = 0x1
2297 09:25:58.185167 WR_PST = 0x0
2298 09:25:58.185216 DBI_WR = 0x0
2299 09:25:58.185264 DBI_RD = 0x0
2300 09:25:58.185312 OTF = 0x1
2301 09:25:58.185361 ===================================
2302 09:25:58.185410 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2303 09:25:58.185459 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2304 09:25:58.185508 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2305 09:25:58.185557 ===================================
2306 09:25:58.185606 LPDDR4 DRAM CONFIGURATION
2307 09:25:58.185655 ===================================
2308 09:25:58.185704 EX_ROW_EN[0] = 0x10
2309 09:25:58.185753 EX_ROW_EN[1] = 0x0
2310 09:25:58.185801 LP4Y_EN = 0x0
2311 09:25:58.185849 WORK_FSP = 0x0
2312 09:25:58.185897 WL = 0x4
2313 09:25:58.185946 RL = 0x4
2314 09:25:58.185995 BL = 0x2
2315 09:25:58.186043 RPST = 0x0
2316 09:25:58.186091 RD_PRE = 0x0
2317 09:25:58.186139 WR_PRE = 0x1
2318 09:25:58.186186 WR_PST = 0x0
2319 09:25:58.186234 DBI_WR = 0x0
2320 09:25:58.186283 DBI_RD = 0x0
2321 09:25:58.186331 OTF = 0x1
2322 09:25:58.186379 ===================================
2323 09:25:58.186428 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2324 09:25:58.186477 ==
2325 09:25:58.186525 Dram Type= 6, Freq= 0, CH_0, rank 0
2326 09:25:58.186574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2327 09:25:58.186623 ==
2328 09:25:58.186672 [Duty_Offset_Calibration]
2329 09:25:58.186720 B0:2 B1:0 CA:3
2330 09:25:58.186768
2331 09:25:58.186816 [DutyScan_Calibration_Flow] k_type=0
2332 09:25:58.186865
2333 09:25:58.186913 ==CLK 0==
2334 09:25:58.186961 Final CLK duty delay cell = 0
2335 09:25:58.187011 [0] MAX Duty = 5062%(X100), DQS PI = 12
2336 09:25:58.187063 [0] MIN Duty = 4906%(X100), DQS PI = 54
2337 09:25:58.187131 [0] AVG Duty = 4984%(X100)
2338 09:25:58.187180
2339 09:25:58.187228 CH0 CLK Duty spec in!! Max-Min= 156%
2340 09:25:58.187277 [DutyScan_Calibration_Flow] ====Done====
2341 09:25:58.187325
2342 09:25:58.187372 [DutyScan_Calibration_Flow] k_type=1
2343 09:25:58.187420
2344 09:25:58.187468 ==DQS 0 ==
2345 09:25:58.187516 Final DQS duty delay cell = 0
2346 09:25:58.187565 [0] MAX Duty = 5062%(X100), DQS PI = 12
2347 09:25:58.187614 [0] MIN Duty = 4907%(X100), DQS PI = 44
2348 09:25:58.187662 [0] AVG Duty = 4984%(X100)
2349 09:25:58.187710
2350 09:25:58.187758 ==DQS 1 ==
2351 09:25:58.187806 Final DQS duty delay cell = -4
2352 09:25:58.187854 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2353 09:25:58.187903 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2354 09:25:58.187951 [-4] AVG Duty = 4922%(X100)
2355 09:25:58.188000
2356 09:25:58.188047 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2357 09:25:58.188095
2358 09:25:58.188143 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2359 09:25:58.188197 [DutyScan_Calibration_Flow] ====Done====
2360 09:25:58.188247
2361 09:25:58.188294 [DutyScan_Calibration_Flow] k_type=3
2362 09:25:58.188342
2363 09:25:58.188402 ==DQM 0 ==
2364 09:25:58.188453 Final DQM duty delay cell = 0
2365 09:25:58.188502 [0] MAX Duty = 5124%(X100), DQS PI = 28
2366 09:25:58.188551 [0] MIN Duty = 4876%(X100), DQS PI = 0
2367 09:25:58.188639 [0] AVG Duty = 5000%(X100)
2368 09:25:58.188704
2369 09:25:58.188754 ==DQM 1 ==
2370 09:25:58.188811 Final DQM duty delay cell = 4
2371 09:25:58.188879 [4] MAX Duty = 5093%(X100), DQS PI = 48
2372 09:25:58.188930 [4] MIN Duty = 5000%(X100), DQS PI = 14
2373 09:25:58.188986 [4] AVG Duty = 5046%(X100)
2374 09:25:58.189037
2375 09:25:58.189086 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2376 09:25:58.189155
2377 09:25:58.189204 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2378 09:25:58.189253 [DutyScan_Calibration_Flow] ====Done====
2379 09:25:58.189301
2380 09:25:58.189373 [DutyScan_Calibration_Flow] k_type=2
2381 09:25:58.189425
2382 09:25:58.189474 ==DQ 0 ==
2383 09:25:58.189528 Final DQ duty delay cell = -4
2384 09:25:58.189774 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2385 09:25:58.189830 [-4] MIN Duty = 4907%(X100), DQS PI = 42
2386 09:25:58.189883 [-4] AVG Duty = 4969%(X100)
2387 09:25:58.189932
2388 09:25:58.189998 ==DQ 1 ==
2389 09:25:58.190049 Final DQ duty delay cell = -4
2390 09:25:58.190099 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2391 09:25:58.190158 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2392 09:25:58.190229 [-4] AVG Duty = 4938%(X100)
2393 09:25:58.190308
2394 09:25:58.190385 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2395 09:25:58.190462
2396 09:25:58.190548 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2397 09:25:58.190625 [DutyScan_Calibration_Flow] ====Done====
2398 09:25:58.190702 ==
2399 09:25:58.190787 Dram Type= 6, Freq= 0, CH_1, rank 0
2400 09:25:58.190865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2401 09:25:58.190942 ==
2402 09:25:58.191027 [Duty_Offset_Calibration]
2403 09:25:58.191104 B0:1 B1:-2 CA:0
2404 09:25:58.191181
2405 09:25:58.191258 [DutyScan_Calibration_Flow] k_type=0
2406 09:25:58.191340
2407 09:25:58.191418 ==CLK 0==
2408 09:25:58.191495 Final CLK duty delay cell = 0
2409 09:25:58.191572 [0] MAX Duty = 5031%(X100), DQS PI = 18
2410 09:25:58.191658 [0] MIN Duty = 4844%(X100), DQS PI = 58
2411 09:25:58.191735 [0] AVG Duty = 4937%(X100)
2412 09:25:58.191811
2413 09:25:58.191896 CH1 CLK Duty spec in!! Max-Min= 187%
2414 09:25:58.191974 [DutyScan_Calibration_Flow] ====Done====
2415 09:25:58.192050
2416 09:25:58.192125 [DutyScan_Calibration_Flow] k_type=1
2417 09:25:58.192202
2418 09:25:58.192284 ==DQS 0 ==
2419 09:25:58.192337 Final DQS duty delay cell = -4
2420 09:25:58.192386 [-4] MAX Duty = 4969%(X100), DQS PI = 8
2421 09:25:58.192436 [-4] MIN Duty = 4876%(X100), DQS PI = 48
2422 09:25:58.192483 [-4] AVG Duty = 4922%(X100)
2423 09:25:58.192531
2424 09:25:58.192578 ==DQS 1 ==
2425 09:25:58.192626 Final DQS duty delay cell = 0
2426 09:25:58.192709 [0] MAX Duty = 5062%(X100), DQS PI = 0
2427 09:25:58.192789 [0] MIN Duty = 4875%(X100), DQS PI = 26
2428 09:25:58.192865 [0] AVG Duty = 4968%(X100)
2429 09:25:58.192946
2430 09:25:58.193031 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2431 09:25:58.193117
2432 09:25:58.193175 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2433 09:25:58.193225 [DutyScan_Calibration_Flow] ====Done====
2434 09:25:58.193282
2435 09:25:58.193352 [DutyScan_Calibration_Flow] k_type=3
2436 09:25:58.193419
2437 09:25:58.193478 ==DQM 0 ==
2438 09:25:58.193529 Final DQM duty delay cell = 0
2439 09:25:58.193579 [0] MAX Duty = 5000%(X100), DQS PI = 24
2440 09:25:58.193628 [0] MIN Duty = 4844%(X100), DQS PI = 56
2441 09:25:58.193682 [0] AVG Duty = 4922%(X100)
2442 09:25:58.193732
2443 09:25:58.193798 ==DQM 1 ==
2444 09:25:58.193852 Final DQM duty delay cell = 0
2445 09:25:58.193930 [0] MAX Duty = 5031%(X100), DQS PI = 36
2446 09:25:58.194007 [0] MIN Duty = 4907%(X100), DQS PI = 2
2447 09:25:58.194093 [0] AVG Duty = 4969%(X100)
2448 09:25:58.194170
2449 09:25:58.194247 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2450 09:25:58.194323
2451 09:25:58.194389 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2452 09:25:58.194440 [DutyScan_Calibration_Flow] ====Done====
2453 09:25:58.194488
2454 09:25:58.194536 [DutyScan_Calibration_Flow] k_type=2
2455 09:25:58.194586
2456 09:25:58.194647 ==DQ 0 ==
2457 09:25:58.194697 Final DQ duty delay cell = 0
2458 09:25:58.194746 [0] MAX Duty = 5093%(X100), DQS PI = 28
2459 09:25:58.194794 [0] MIN Duty = 4938%(X100), DQS PI = 54
2460 09:25:58.194847 [0] AVG Duty = 5015%(X100)
2461 09:25:58.194905
2462 09:25:58.194953 ==DQ 1 ==
2463 09:25:58.195000 Final DQ duty delay cell = 0
2464 09:25:58.195048 [0] MAX Duty = 5125%(X100), DQS PI = 36
2465 09:25:58.195102 [0] MIN Duty = 4969%(X100), DQS PI = 26
2466 09:25:58.195160 [0] AVG Duty = 5047%(X100)
2467 09:25:58.195208
2468 09:25:58.195255 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2469 09:25:58.195304
2470 09:25:58.195351 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2471 09:25:58.195399 [DutyScan_Calibration_Flow] ====Done====
2472 09:25:58.195450 nWR fixed to 30
2473 09:25:58.195516 [ModeRegInit_LP4] CH0 RK0
2474 09:25:58.195566 [ModeRegInit_LP4] CH0 RK1
2475 09:25:58.195615 [ModeRegInit_LP4] CH1 RK0
2476 09:25:58.195663 [ModeRegInit_LP4] CH1 RK1
2477 09:25:58.195735 match AC timing 7
2478 09:25:58.195785 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2479 09:25:58.195835 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2480 09:25:58.195890 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2481 09:25:58.195945 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2482 09:25:58.196006 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2483 09:25:58.196054 ==
2484 09:25:58.196106 Dram Type= 6, Freq= 0, CH_0, rank 0
2485 09:25:58.196156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2486 09:25:58.196206 ==
2487 09:25:58.196293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2488 09:25:58.196373 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2489 09:25:58.196453 [CA 0] Center 40 (10~71) winsize 62
2490 09:25:58.196538 [CA 1] Center 39 (9~70) winsize 62
2491 09:25:58.196615 [CA 2] Center 36 (6~66) winsize 61
2492 09:25:58.196685 [CA 3] Center 35 (5~66) winsize 62
2493 09:25:58.196751 [CA 4] Center 34 (4~65) winsize 62
2494 09:25:58.196803 [CA 5] Center 33 (3~63) winsize 61
2495 09:25:58.196851
2496 09:25:58.196899 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2497 09:25:58.196947
2498 09:25:58.197011 [CATrainingPosCal] consider 1 rank data
2499 09:25:58.197065 u2DelayCellTimex100 = 270/100 ps
2500 09:25:58.197132 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2501 09:25:58.197183 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2502 09:25:58.197231 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2503 09:25:58.197280 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2504 09:25:58.197337 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2505 09:25:58.197391 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2506 09:25:58.197438
2507 09:25:58.197486 CA PerBit enable=1, Macro0, CA PI delay=33
2508 09:25:58.197534
2509 09:25:58.197585 [CBTSetCACLKResult] CA Dly = 33
2510 09:25:58.197645 CS Dly: 7 (0~38)
2511 09:25:58.197693 ==
2512 09:25:58.197741 Dram Type= 6, Freq= 0, CH_0, rank 1
2513 09:25:58.197789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 09:25:58.197842 ==
2515 09:25:58.197900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 09:25:58.197949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2517 09:25:58.197998 [CA 0] Center 40 (10~70) winsize 61
2518 09:25:58.198047 [CA 1] Center 40 (10~70) winsize 61
2519 09:25:58.198100 [CA 2] Center 35 (5~66) winsize 62
2520 09:25:58.198158 [CA 3] Center 35 (5~66) winsize 62
2521 09:25:58.198207 [CA 4] Center 34 (4~65) winsize 62
2522 09:25:58.198256 [CA 5] Center 33 (3~64) winsize 62
2523 09:25:58.198304
2524 09:25:58.198351 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2525 09:25:58.198399
2526 09:25:58.198449 [CATrainingPosCal] consider 2 rank data
2527 09:25:58.198709 u2DelayCellTimex100 = 270/100 ps
2528 09:25:58.198774 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2529 09:25:58.198825 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2530 09:25:58.198875 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2531 09:25:58.198924 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2532 09:25:58.198991 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2533 09:25:58.199071 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2534 09:25:58.199152
2535 09:25:58.199231 CA PerBit enable=1, Macro0, CA PI delay=33
2536 09:25:58.199310
2537 09:25:58.199387 [CBTSetCACLKResult] CA Dly = 33
2538 09:25:58.199464 CS Dly: 7 (0~39)
2539 09:25:58.199541
2540 09:25:58.199618 ----->DramcWriteLeveling(PI) begin...
2541 09:25:58.199696 ==
2542 09:25:58.199773 Dram Type= 6, Freq= 0, CH_0, rank 0
2543 09:25:58.199849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2544 09:25:58.199926 ==
2545 09:25:58.200003 Write leveling (Byte 0): 32 => 32
2546 09:25:58.200079 Write leveling (Byte 1): 29 => 29
2547 09:25:58.200155 DramcWriteLeveling(PI) end<-----
2548 09:25:58.200237
2549 09:25:58.200318 ==
2550 09:25:58.200395 Dram Type= 6, Freq= 0, CH_0, rank 0
2551 09:25:58.200472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2552 09:25:58.200549 ==
2553 09:25:58.200624 [Gating] SW mode calibration
2554 09:25:58.200719 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2555 09:25:58.200798 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2556 09:25:58.200875 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 09:25:58.200952 0 15 4 | B1->B0 | 2a2a 3333 | 1 1 | (0 0) (1 1)
2558 09:25:58.201030 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2559 09:25:58.201107 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2560 09:25:58.201184 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2561 09:25:58.201261 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2562 09:25:58.201338 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2563 09:25:58.201415 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2564 09:25:58.201492 1 0 0 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 1)
2565 09:25:58.201569 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 09:25:58.201646 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2567 09:25:58.201723 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2568 09:25:58.201800 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 09:25:58.201877 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 09:25:58.201954 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 09:25:58.202030 1 0 28 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
2572 09:25:58.202108 1 1 0 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
2573 09:25:58.202185 1 1 4 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
2574 09:25:58.202262 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 09:25:58.202339 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 09:25:58.202417 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 09:25:58.202494 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 09:25:58.202570 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 09:25:58.202647 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 09:25:58.202724 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2581 09:25:58.202800 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2582 09:25:58.202877 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 09:25:58.202953 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 09:25:58.203030 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 09:25:58.203106 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 09:25:58.203183 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 09:25:58.203259 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 09:25:58.203347 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 09:25:58.203431 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 09:25:58.203509 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 09:25:58.203587 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 09:25:58.203648 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 09:25:58.203698 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 09:25:58.203748 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 09:25:58.203795 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2596 09:25:58.203843 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2597 09:25:58.203891 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 09:25:58.203939 Total UI for P1: 0, mck2ui 16
2599 09:25:58.203988 best dqsien dly found for B0: ( 1, 3, 30)
2600 09:25:58.204037 Total UI for P1: 0, mck2ui 16
2601 09:25:58.204086 best dqsien dly found for B1: ( 1, 4, 2)
2602 09:25:58.204134 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2603 09:25:58.204182 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2604 09:25:58.204230
2605 09:25:58.204278 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2606 09:25:58.204326 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2607 09:25:58.204374 [Gating] SW calibration Done
2608 09:25:58.204423 ==
2609 09:25:58.204471 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 09:25:58.204519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 09:25:58.204568 ==
2612 09:25:58.204616 RX Vref Scan: 0
2613 09:25:58.204865
2614 09:25:58.204915 RX Vref 0 -> 0, step: 1
2615 09:25:58.204963
2616 09:25:58.205010 RX Delay -40 -> 252, step: 8
2617 09:25:58.205058 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2618 09:25:58.205106 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2619 09:25:58.205154 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2620 09:25:58.205205 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2621 09:25:58.205253 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2622 09:25:58.205301 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2623 09:25:58.205349 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2624 09:25:58.205397 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2625 09:25:58.205445 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2626 09:25:58.205493 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2627 09:25:58.205544 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2628 09:25:58.205786 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2629 09:25:58.205841 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2630 09:25:58.205891 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2631 09:25:58.205940 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2632 09:25:58.205988 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2633 09:25:58.206036 ==
2634 09:25:58.206085 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 09:25:58.206134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 09:25:58.206183 ==
2637 09:25:58.206232 DQS Delay:
2638 09:25:58.206280 DQS0 = 0, DQS1 = 0
2639 09:25:58.206327 DQM Delay:
2640 09:25:58.206374 DQM0 = 112, DQM1 = 102
2641 09:25:58.206422 DQ Delay:
2642 09:25:58.206470 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2643 09:25:58.206518 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2644 09:25:58.206565 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2645 09:25:58.206613 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2646 09:25:58.206661
2647 09:25:58.206709
2648 09:25:58.206756 ==
2649 09:25:58.206804 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 09:25:58.206851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 09:25:58.206901 ==
2652 09:25:58.206949
2653 09:25:58.206996
2654 09:25:58.207042 TX Vref Scan disable
2655 09:25:58.207090 == TX Byte 0 ==
2656 09:25:58.207162 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2657 09:25:58.207213 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2658 09:25:58.207263 == TX Byte 1 ==
2659 09:25:58.207311 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2660 09:25:58.207359 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2661 09:25:58.207408 ==
2662 09:25:58.207455 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 09:25:58.207503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 09:25:58.207551 ==
2665 09:25:58.207602 TX Vref=22, minBit 0, minWin=26, winSum=419
2666 09:25:58.207676 TX Vref=24, minBit 1, minWin=26, winSum=421
2667 09:25:58.207759 TX Vref=26, minBit 8, minWin=26, winSum=430
2668 09:25:58.207838 TX Vref=28, minBit 10, minWin=26, winSum=437
2669 09:25:58.207918 TX Vref=30, minBit 8, minWin=26, winSum=438
2670 09:25:58.207995 TX Vref=32, minBit 8, minWin=26, winSum=431
2671 09:25:58.208046 [TxChooseVref] Worse bit 8, Min win 26, Win sum 438, Final Vref 30
2672 09:25:58.208096
2673 09:25:58.208145 Final TX Range 1 Vref 30
2674 09:25:58.208193
2675 09:25:58.208241 ==
2676 09:25:58.208288 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 09:25:58.208338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 09:25:58.208387 ==
2679 09:25:58.208434
2680 09:25:58.208480
2681 09:25:58.208527 TX Vref Scan disable
2682 09:25:58.208575 == TX Byte 0 ==
2683 09:25:58.208623 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2684 09:25:58.208684 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2685 09:25:58.208734 == TX Byte 1 ==
2686 09:25:58.208782 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2687 09:25:58.208831 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2688 09:25:58.208879
2689 09:25:58.208927 [DATLAT]
2690 09:25:58.208974 Freq=1200, CH0 RK0
2691 09:25:58.209022
2692 09:25:58.209070 DATLAT Default: 0xd
2693 09:25:58.209119 0, 0xFFFF, sum = 0
2694 09:25:58.209168 1, 0xFFFF, sum = 0
2695 09:25:58.209217 2, 0xFFFF, sum = 0
2696 09:25:58.209266 3, 0xFFFF, sum = 0
2697 09:25:58.209315 4, 0xFFFF, sum = 0
2698 09:25:58.209364 5, 0xFFFF, sum = 0
2699 09:25:58.209412 6, 0xFFFF, sum = 0
2700 09:25:58.209461 7, 0xFFFF, sum = 0
2701 09:25:58.209509 8, 0xFFFF, sum = 0
2702 09:25:58.209558 9, 0xFFFF, sum = 0
2703 09:25:58.209607 10, 0xFFFF, sum = 0
2704 09:25:58.209655 11, 0xFFFF, sum = 0
2705 09:25:58.209704 12, 0x0, sum = 1
2706 09:25:58.209753 13, 0x0, sum = 2
2707 09:25:58.209801 14, 0x0, sum = 3
2708 09:25:58.209849 15, 0x0, sum = 4
2709 09:25:58.209898 best_step = 13
2710 09:25:58.209946
2711 09:25:58.209993 ==
2712 09:25:58.210042 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 09:25:58.210091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 09:25:58.210140 ==
2715 09:25:58.210198 RX Vref Scan: 1
2716 09:25:58.210254
2717 09:25:58.210302 Set Vref Range= 32 -> 127
2718 09:25:58.210351
2719 09:25:58.210399 RX Vref 32 -> 127, step: 1
2720 09:25:58.210447
2721 09:25:58.210495 RX Delay -37 -> 252, step: 4
2722 09:25:58.210543
2723 09:25:58.210591 Set Vref, RX VrefLevel [Byte0]: 32
2724 09:25:58.210639 [Byte1]: 32
2725 09:25:58.210687
2726 09:25:58.210735 Set Vref, RX VrefLevel [Byte0]: 33
2727 09:25:58.210783 [Byte1]: 33
2728 09:25:58.210831
2729 09:25:58.210879 Set Vref, RX VrefLevel [Byte0]: 34
2730 09:25:58.210927 [Byte1]: 34
2731 09:25:58.210975
2732 09:25:58.211022 Set Vref, RX VrefLevel [Byte0]: 35
2733 09:25:58.211070 [Byte1]: 35
2734 09:25:58.211118
2735 09:25:58.211166 Set Vref, RX VrefLevel [Byte0]: 36
2736 09:25:58.211213 [Byte1]: 36
2737 09:25:58.211262
2738 09:25:58.211309 Set Vref, RX VrefLevel [Byte0]: 37
2739 09:25:58.211357 [Byte1]: 37
2740 09:25:58.211405
2741 09:25:58.211460 Set Vref, RX VrefLevel [Byte0]: 38
2742 09:25:58.211542 [Byte1]: 38
2743 09:25:58.211619
2744 09:25:58.211697 Set Vref, RX VrefLevel [Byte0]: 39
2745 09:25:58.211754 [Byte1]: 39
2746 09:25:58.211802
2747 09:25:58.211850 Set Vref, RX VrefLevel [Byte0]: 40
2748 09:25:58.211899 [Byte1]: 40
2749 09:25:58.211947
2750 09:25:58.211995 Set Vref, RX VrefLevel [Byte0]: 41
2751 09:25:58.212043 [Byte1]: 41
2752 09:25:58.212091
2753 09:25:58.212138 Set Vref, RX VrefLevel [Byte0]: 42
2754 09:25:58.212186 [Byte1]: 42
2755 09:25:58.212233
2756 09:25:58.212280 Set Vref, RX VrefLevel [Byte0]: 43
2757 09:25:58.212327 [Byte1]: 43
2758 09:25:58.212375
2759 09:25:58.212422 Set Vref, RX VrefLevel [Byte0]: 44
2760 09:25:58.212470 [Byte1]: 44
2761 09:25:58.212518
2762 09:25:58.212566 Set Vref, RX VrefLevel [Byte0]: 45
2763 09:25:58.212614 [Byte1]: 45
2764 09:25:58.212669
2765 09:25:58.212718 Set Vref, RX VrefLevel [Byte0]: 46
2766 09:25:58.212766 [Byte1]: 46
2767 09:25:58.212812
2768 09:25:58.212860 Set Vref, RX VrefLevel [Byte0]: 47
2769 09:25:58.212908 [Byte1]: 47
2770 09:25:58.212956
2771 09:25:58.213003 Set Vref, RX VrefLevel [Byte0]: 48
2772 09:25:58.213051 [Byte1]: 48
2773 09:25:58.213100
2774 09:25:58.213148 Set Vref, RX VrefLevel [Byte0]: 49
2775 09:25:58.213197 [Byte1]: 49
2776 09:25:58.213245
2777 09:25:58.213315 Set Vref, RX VrefLevel [Byte0]: 50
2778 09:25:58.213366 [Byte1]: 50
2779 09:25:58.213416
2780 09:25:58.213464 Set Vref, RX VrefLevel [Byte0]: 51
2781 09:25:58.213513 [Byte1]: 51
2782 09:25:58.213561
2783 09:25:58.213609 Set Vref, RX VrefLevel [Byte0]: 52
2784 09:25:58.213657 [Byte1]: 52
2785 09:25:58.213705
2786 09:25:58.213752 Set Vref, RX VrefLevel [Byte0]: 53
2787 09:25:58.213800 [Byte1]: 53
2788 09:25:58.213847
2789 09:25:58.213894 Set Vref, RX VrefLevel [Byte0]: 54
2790 09:25:58.213943 [Byte1]: 54
2791 09:25:58.213991
2792 09:25:58.214038 Set Vref, RX VrefLevel [Byte0]: 55
2793 09:25:58.214279 [Byte1]: 55
2794 09:25:58.214333
2795 09:25:58.214383 Set Vref, RX VrefLevel [Byte0]: 56
2796 09:25:58.214432 [Byte1]: 56
2797 09:25:58.214481
2798 09:25:58.214529 Set Vref, RX VrefLevel [Byte0]: 57
2799 09:25:58.214578 [Byte1]: 57
2800 09:25:58.214626
2801 09:25:58.214673 Set Vref, RX VrefLevel [Byte0]: 58
2802 09:25:58.214722 [Byte1]: 58
2803 09:25:58.214771
2804 09:25:58.214819 Set Vref, RX VrefLevel [Byte0]: 59
2805 09:25:58.214867 [Byte1]: 59
2806 09:25:58.214915
2807 09:25:58.214962 Set Vref, RX VrefLevel [Byte0]: 60
2808 09:25:58.215010 [Byte1]: 60
2809 09:25:58.215057
2810 09:25:58.215106 Set Vref, RX VrefLevel [Byte0]: 61
2811 09:25:58.215154 [Byte1]: 61
2812 09:25:58.215201
2813 09:25:58.215249 Set Vref, RX VrefLevel [Byte0]: 62
2814 09:25:58.215297 [Byte1]: 62
2815 09:25:58.215346
2816 09:25:58.215393 Set Vref, RX VrefLevel [Byte0]: 63
2817 09:25:58.215440 [Byte1]: 63
2818 09:25:58.215488
2819 09:25:58.215535 Set Vref, RX VrefLevel [Byte0]: 64
2820 09:25:58.215583 [Byte1]: 64
2821 09:25:58.215633
2822 09:25:58.215680 Set Vref, RX VrefLevel [Byte0]: 65
2823 09:25:58.215728 [Byte1]: 65
2824 09:25:58.215777
2825 09:25:58.215825 Set Vref, RX VrefLevel [Byte0]: 66
2826 09:25:58.215872 [Byte1]: 66
2827 09:25:58.215924
2828 09:25:58.216005 Set Vref, RX VrefLevel [Byte0]: 67
2829 09:25:58.216082 [Byte1]: 67
2830 09:25:58.216160
2831 09:25:58.216220 Set Vref, RX VrefLevel [Byte0]: 68
2832 09:25:58.216269 [Byte1]: 68
2833 09:25:58.216319
2834 09:25:58.216367 Set Vref, RX VrefLevel [Byte0]: 69
2835 09:25:58.216414 [Byte1]: 69
2836 09:25:58.216462
2837 09:25:58.216509 Set Vref, RX VrefLevel [Byte0]: 70
2838 09:25:58.216557 [Byte1]: 70
2839 09:25:58.216604
2840 09:25:58.216666 Set Vref, RX VrefLevel [Byte0]: 71
2841 09:25:58.216724 [Byte1]: 71
2842 09:25:58.216774
2843 09:25:58.216822 Set Vref, RX VrefLevel [Byte0]: 72
2844 09:25:58.216870 [Byte1]: 72
2845 09:25:58.216928
2846 09:25:58.216979 Set Vref, RX VrefLevel [Byte0]: 73
2847 09:25:58.217027 [Byte1]: 73
2848 09:25:58.217076
2849 09:25:58.217128 Set Vref, RX VrefLevel [Byte0]: 74
2850 09:25:58.217199 [Byte1]: 74
2851 09:25:58.217249
2852 09:25:58.217302 Set Vref, RX VrefLevel [Byte0]: 75
2853 09:25:58.217352 [Byte1]: 75
2854 09:25:58.217400
2855 09:25:58.217447 Final RX Vref Byte 0 = 62 to rank0
2856 09:25:58.217502 Final RX Vref Byte 1 = 47 to rank0
2857 09:25:58.217553 Final RX Vref Byte 0 = 62 to rank1
2858 09:25:58.217603 Final RX Vref Byte 1 = 47 to rank1==
2859 09:25:58.217651 Dram Type= 6, Freq= 0, CH_0, rank 0
2860 09:25:58.217699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2861 09:25:58.217748 ==
2862 09:25:58.217797 DQS Delay:
2863 09:25:58.217846 DQS0 = 0, DQS1 = 0
2864 09:25:58.217894 DQM Delay:
2865 09:25:58.217941 DQM0 = 111, DQM1 = 98
2866 09:25:58.217990 DQ Delay:
2867 09:25:58.218037 DQ0 =110, DQ1 =110, DQ2 =112, DQ3 =108
2868 09:25:58.218086 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2869 09:25:58.218138 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2870 09:25:58.218189 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2871 09:25:58.218238
2872 09:25:58.218285
2873 09:25:58.218341 [DQSOSCAuto] RK0, (LSB)MR18= 0xff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2874 09:25:58.218393 CH0 RK0: MR19=403, MR18=FF
2875 09:25:58.218442 CH0_RK0: MR19=0x403, MR18=0xFF, DQSOSC=410, MR23=63, INC=39, DEC=26
2876 09:25:58.218491
2877 09:25:58.218556 ----->DramcWriteLeveling(PI) begin...
2878 09:25:58.218608 ==
2879 09:25:58.218656 Dram Type= 6, Freq= 0, CH_0, rank 1
2880 09:25:58.218714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2881 09:25:58.218796 ==
2882 09:25:58.218873 Write leveling (Byte 0): 32 => 32
2883 09:25:58.218959 Write leveling (Byte 1): 30 => 30
2884 09:25:58.219037 DramcWriteLeveling(PI) end<-----
2885 09:25:58.219123
2886 09:25:58.219201 ==
2887 09:25:58.219286 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 09:25:58.219366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 09:25:58.219443 ==
2890 09:25:58.219522 [Gating] SW mode calibration
2891 09:25:58.219601 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2892 09:25:58.219682 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2893 09:25:58.219763 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2894 09:25:58.219844 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 09:25:58.219922 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 09:25:58.219988 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 09:25:58.220039 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 09:25:58.220088 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 09:25:58.220137 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
2900 09:25:58.220186 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2901 09:25:58.220234 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 09:25:58.220283 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 09:25:58.220351 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 09:25:58.220402 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 09:25:58.220451 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 09:25:58.220499 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 09:25:58.220548 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
2908 09:25:58.220597 1 0 28 | B1->B0 | 2524 4646 | 1 0 | (0 0) (0 0)
2909 09:25:58.220654 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
2910 09:25:58.220705 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 09:25:58.220754 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 09:25:58.220802 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 09:25:58.220851 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 09:25:58.220899 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 09:25:58.220947 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 09:25:58.220996 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2917 09:25:58.221044 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2918 09:25:58.221091 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 09:25:58.221139 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 09:25:58.221383 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 09:25:58.221441 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 09:25:58.221491 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 09:25:58.221539 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 09:25:58.221587 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 09:25:58.221635 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 09:25:58.221683 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 09:25:58.221730 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 09:25:58.221778 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 09:25:58.221827 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 09:25:58.221875 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 09:25:58.221923 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2932 09:25:58.221970 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2933 09:25:58.222018 Total UI for P1: 0, mck2ui 16
2934 09:25:58.222066 best dqsien dly found for B0: ( 1, 3, 24)
2935 09:25:58.222114 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 09:25:58.222163 Total UI for P1: 0, mck2ui 16
2937 09:25:58.222212 best dqsien dly found for B1: ( 1, 3, 30)
2938 09:25:58.222261 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2939 09:25:58.222309 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2940 09:25:58.222356
2941 09:25:58.222405 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2942 09:25:58.222454 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2943 09:25:58.222502 [Gating] SW calibration Done
2944 09:25:58.222549 ==
2945 09:25:58.222597 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 09:25:58.222645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 09:25:58.222694 ==
2948 09:25:58.222741 RX Vref Scan: 0
2949 09:25:58.222789
2950 09:25:58.222837 RX Vref 0 -> 0, step: 1
2951 09:25:58.222885
2952 09:25:58.222932 RX Delay -40 -> 252, step: 8
2953 09:25:58.222980 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2954 09:25:58.223027 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2955 09:25:58.223075 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2956 09:25:58.223123 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2957 09:25:58.223171 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2958 09:25:58.223219 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2959 09:25:58.223268 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2960 09:25:58.223316 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2961 09:25:58.223364 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2962 09:25:58.223415 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2963 09:25:58.223485 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2964 09:25:58.223535 iDelay=200, Bit 11, Center 91 (16 ~ 167) 152
2965 09:25:58.223584 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2966 09:25:58.223633 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2967 09:25:58.223681 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2968 09:25:58.223729 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2969 09:25:58.223777 ==
2970 09:25:58.223825 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 09:25:58.223873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 09:25:58.223922 ==
2973 09:25:58.223977 DQS Delay:
2974 09:25:58.224057 DQS0 = 0, DQS1 = 0
2975 09:25:58.460462 DQM Delay:
2976 09:25:58.460604 DQM0 = 111, DQM1 = 100
2977 09:25:58.460688 DQ Delay:
2978 09:25:58.460747 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2979 09:25:58.460802 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2980 09:25:58.460854 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =91
2981 09:25:58.460905 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2982 09:25:58.460955
2983 09:25:58.461005
2984 09:25:58.461054 ==
2985 09:25:58.461104 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 09:25:58.461154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 09:25:58.461205 ==
2988 09:25:58.461263
2989 09:25:58.461312
2990 09:25:58.461360 TX Vref Scan disable
2991 09:25:58.461409 == TX Byte 0 ==
2992 09:25:58.461459 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2993 09:25:58.461513 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2994 09:25:58.461570 == TX Byte 1 ==
2995 09:25:58.461621 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2996 09:25:58.461670 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2997 09:25:58.461730 ==
2998 09:25:58.461796 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 09:25:58.461874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 09:25:58.461951 ==
3001 09:25:58.462028 TX Vref=22, minBit 2, minWin=26, winSum=426
3002 09:25:58.462106 TX Vref=24, minBit 5, minWin=26, winSum=429
3003 09:25:58.462183 TX Vref=26, minBit 1, minWin=26, winSum=434
3004 09:25:58.462260 TX Vref=28, minBit 13, minWin=26, winSum=438
3005 09:25:58.462338 TX Vref=30, minBit 8, minWin=26, winSum=441
3006 09:25:58.462393 TX Vref=32, minBit 13, minWin=26, winSum=441
3007 09:25:58.462443 [TxChooseVref] Worse bit 8, Min win 26, Win sum 441, Final Vref 30
3008 09:25:58.462492
3009 09:25:58.462540 Final TX Range 1 Vref 30
3010 09:25:58.462588
3011 09:25:58.462636 ==
3012 09:25:58.462684 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 09:25:58.462733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 09:25:58.462782 ==
3015 09:25:58.462829
3016 09:25:58.462877
3017 09:25:58.462924 TX Vref Scan disable
3018 09:25:58.462972 == TX Byte 0 ==
3019 09:25:58.463020 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3020 09:25:58.463069 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3021 09:25:58.463117 == TX Byte 1 ==
3022 09:25:58.463166 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3023 09:25:58.463214 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3024 09:25:58.463262
3025 09:25:58.463311 [DATLAT]
3026 09:25:58.463358 Freq=1200, CH0 RK1
3027 09:25:58.463406
3028 09:25:58.463453 DATLAT Default: 0xd
3029 09:25:58.463501 0, 0xFFFF, sum = 0
3030 09:25:58.463550 1, 0xFFFF, sum = 0
3031 09:25:58.463599 2, 0xFFFF, sum = 0
3032 09:25:58.463648 3, 0xFFFF, sum = 0
3033 09:25:58.463697 4, 0xFFFF, sum = 0
3034 09:25:58.463746 5, 0xFFFF, sum = 0
3035 09:25:58.463794 6, 0xFFFF, sum = 0
3036 09:25:58.463842 7, 0xFFFF, sum = 0
3037 09:25:58.463891 8, 0xFFFF, sum = 0
3038 09:25:58.463939 9, 0xFFFF, sum = 0
3039 09:25:58.463988 10, 0xFFFF, sum = 0
3040 09:25:58.464036 11, 0xFFFF, sum = 0
3041 09:25:58.464085 12, 0x0, sum = 1
3042 09:25:58.464134 13, 0x0, sum = 2
3043 09:25:58.464183 14, 0x0, sum = 3
3044 09:25:58.464231 15, 0x0, sum = 4
3045 09:25:58.464280 best_step = 13
3046 09:25:58.464328
3047 09:25:58.464375 ==
3048 09:25:58.464423 Dram Type= 6, Freq= 0, CH_0, rank 1
3049 09:25:58.464471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 09:25:58.464520 ==
3051 09:25:58.464567 RX Vref Scan: 0
3052 09:25:58.464615
3053 09:25:58.464674 RX Vref 0 -> 0, step: 1
3054 09:25:58.464724
3055 09:25:58.464772 RX Delay -37 -> 252, step: 4
3056 09:25:58.464821 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3057 09:25:58.465070 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3058 09:25:58.465125 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3059 09:25:58.465175 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3060 09:25:58.465224 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3061 09:25:58.465273 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3062 09:25:58.465323 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3063 09:25:58.465372 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3064 09:25:58.465420 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3065 09:25:58.465469 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3066 09:25:58.465517 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3067 09:25:58.465567 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3068 09:25:58.465616 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3069 09:25:58.465664 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3070 09:25:58.465719 iDelay=195, Bit 14, Center 110 (43 ~ 178) 136
3071 09:25:58.465798 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3072 09:25:58.465868 ==
3073 09:25:58.465920 Dram Type= 6, Freq= 0, CH_0, rank 1
3074 09:25:58.465969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 09:25:58.466019 ==
3076 09:25:58.466068 DQS Delay:
3077 09:25:58.466117 DQS0 = 0, DQS1 = 0
3078 09:25:58.466165 DQM Delay:
3079 09:25:58.466214 DQM0 = 110, DQM1 = 98
3080 09:25:58.466262 DQ Delay:
3081 09:25:58.466311 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3082 09:25:58.466360 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3083 09:25:58.466408 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3084 09:25:58.466457 DQ12 =108, DQ13 =106, DQ14 =110, DQ15 =108
3085 09:25:58.466506
3086 09:25:58.466555
3087 09:25:58.466604 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3088 09:25:58.466653 CH0 RK1: MR19=403, MR18=14FC
3089 09:25:58.466703 CH0_RK1: MR19=0x403, MR18=0x14FC, DQSOSC=402, MR23=63, INC=40, DEC=27
3090 09:25:58.466752 [RxdqsGatingPostProcess] freq 1200
3091 09:25:58.466801 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3092 09:25:58.466851 best DQS0 dly(2T, 0.5T) = (0, 11)
3093 09:25:58.466899 best DQS1 dly(2T, 0.5T) = (0, 12)
3094 09:25:58.466947 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3095 09:25:58.466995 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3096 09:25:58.467043 best DQS0 dly(2T, 0.5T) = (0, 11)
3097 09:25:58.467091 best DQS1 dly(2T, 0.5T) = (0, 11)
3098 09:25:58.467140 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3099 09:25:58.467188 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3100 09:25:58.467236 Pre-setting of DQS Precalculation
3101 09:25:58.467284 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3102 09:25:58.467333 ==
3103 09:25:58.467381 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 09:25:58.467429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 09:25:58.467478 ==
3106 09:25:58.467526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3107 09:25:58.467575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3108 09:25:58.467624 [CA 0] Center 37 (7~67) winsize 61
3109 09:25:58.467673 [CA 1] Center 37 (7~68) winsize 62
3110 09:25:58.467722 [CA 2] Center 34 (4~64) winsize 61
3111 09:25:58.467771 [CA 3] Center 34 (4~64) winsize 61
3112 09:25:58.467819 [CA 4] Center 34 (4~64) winsize 61
3113 09:25:58.467867 [CA 5] Center 33 (3~63) winsize 61
3114 09:25:58.467914
3115 09:25:58.467963 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3116 09:25:58.468011
3117 09:25:58.468059 [CATrainingPosCal] consider 1 rank data
3118 09:25:58.468107 u2DelayCellTimex100 = 270/100 ps
3119 09:25:58.468156 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3120 09:25:58.468204 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3121 09:25:58.468253 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 09:25:58.468301 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 09:25:58.468349 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3124 09:25:58.468398 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3125 09:25:58.468446
3126 09:25:58.468494 CA PerBit enable=1, Macro0, CA PI delay=33
3127 09:25:58.468543
3128 09:25:58.468591 [CBTSetCACLKResult] CA Dly = 33
3129 09:25:58.468640 CS Dly: 5 (0~36)
3130 09:25:58.468698 ==
3131 09:25:58.468750 Dram Type= 6, Freq= 0, CH_1, rank 1
3132 09:25:58.468799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 09:25:58.468848 ==
3134 09:25:58.468896 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3135 09:25:58.468945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3136 09:25:58.468994 [CA 0] Center 37 (8~67) winsize 60
3137 09:25:58.469043 [CA 1] Center 37 (7~68) winsize 62
3138 09:25:58.469100 [CA 2] Center 34 (4~65) winsize 62
3139 09:25:58.469173 [CA 3] Center 33 (3~64) winsize 62
3140 09:25:58.469247 [CA 4] Center 34 (4~65) winsize 62
3141 09:25:58.469323 [CA 5] Center 33 (3~63) winsize 61
3142 09:25:58.469404
3143 09:25:58.469483 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3144 09:25:58.469568
3145 09:25:58.469654 [CATrainingPosCal] consider 2 rank data
3146 09:25:58.469746 u2DelayCellTimex100 = 270/100 ps
3147 09:25:58.469833 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3148 09:25:58.469923 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3149 09:25:58.470017 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 09:25:58.470105 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 09:25:58.470191 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 09:25:58.470275 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3153 09:25:58.470356
3154 09:25:58.470436 CA PerBit enable=1, Macro0, CA PI delay=33
3155 09:25:58.470517
3156 09:25:58.470596 [CBTSetCACLKResult] CA Dly = 33
3157 09:25:58.470675 CS Dly: 6 (0~39)
3158 09:25:58.470752
3159 09:25:58.470830 ----->DramcWriteLeveling(PI) begin...
3160 09:25:58.470911 ==
3161 09:25:58.470989 Dram Type= 6, Freq= 0, CH_1, rank 0
3162 09:25:58.471070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 09:25:58.471154 ==
3164 09:25:58.471261 Write leveling (Byte 0): 25 => 25
3165 09:25:58.471365 Write leveling (Byte 1): 28 => 28
3166 09:25:58.471474 DramcWriteLeveling(PI) end<-----
3167 09:25:58.471585
3168 09:25:58.471671 ==
3169 09:25:58.471766 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 09:25:58.471855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 09:25:58.471944 ==
3172 09:25:58.472032 [Gating] SW mode calibration
3173 09:25:58.472119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3174 09:25:58.472211 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3175 09:25:58.472301 0 15 0 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (1 1)
3176 09:25:58.472590 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 09:25:58.472690 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 09:25:58.472780 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 09:25:58.472867 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 09:25:58.472953 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 09:25:58.473040 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3182 09:25:58.473126 0 15 28 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (0 1)
3183 09:25:58.473212 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 09:25:58.473298 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 09:25:58.473383 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 09:25:58.473468 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 09:25:58.473552 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 09:25:58.473638 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 09:25:58.473722 1 0 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3190 09:25:58.473807 1 0 28 | B1->B0 | 3d3d 3b3b | 0 1 | (0 0) (0 0)
3191 09:25:58.473892 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3192 09:25:58.473978 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 09:25:58.474064 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 09:25:58.474149 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 09:25:58.474235 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 09:25:58.474320 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 09:25:58.474406 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 09:25:58.474491 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3199 09:25:58.474576 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3200 09:25:58.474660 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 09:25:58.474745 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 09:25:58.474830 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 09:25:58.474914 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 09:25:58.474999 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 09:25:58.475085 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 09:25:58.475171 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 09:25:58.475256 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 09:25:58.475341 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 09:25:58.475426 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 09:25:58.475511 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 09:25:58.475596 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 09:25:58.475680 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 09:25:58.475765 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 09:25:58.475849 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3215 09:25:58.475934 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3216 09:25:58.476019 Total UI for P1: 0, mck2ui 16
3217 09:25:58.476104 best dqsien dly found for B1: ( 1, 3, 28)
3218 09:25:58.476190 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 09:25:58.476274 Total UI for P1: 0, mck2ui 16
3220 09:25:58.476359 best dqsien dly found for B0: ( 1, 3, 30)
3221 09:25:58.476444 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3222 09:25:58.476530 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3223 09:25:58.476614
3224 09:25:58.476706 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3225 09:25:58.476791 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3226 09:25:58.476876 [Gating] SW calibration Done
3227 09:25:58.476960 ==
3228 09:25:58.477044 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 09:25:58.477129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 09:25:58.477215 ==
3231 09:25:58.477299 RX Vref Scan: 0
3232 09:25:58.477384
3233 09:25:58.477468 RX Vref 0 -> 0, step: 1
3234 09:25:58.477552
3235 09:25:58.477637 RX Delay -40 -> 252, step: 8
3236 09:25:58.477721 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3237 09:25:58.477806 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3238 09:25:58.477891 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3239 09:25:58.477976 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3240 09:25:58.478060 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3241 09:25:58.478145 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3242 09:25:58.478230 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3243 09:25:58.478315 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3244 09:25:58.478400 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3245 09:25:58.478485 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3246 09:25:58.478571 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3247 09:25:58.478655 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3248 09:25:58.478740 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3249 09:25:58.478824 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3250 09:25:58.478908 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3251 09:25:58.478993 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3252 09:25:58.479078 ==
3253 09:25:58.479163 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 09:25:58.479248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 09:25:58.479333 ==
3256 09:25:58.479417 DQS Delay:
3257 09:25:58.479501 DQS0 = 0, DQS1 = 0
3258 09:25:58.479586 DQM Delay:
3259 09:25:58.479670 DQM0 = 113, DQM1 = 105
3260 09:25:58.479754 DQ Delay:
3261 09:25:58.479838 DQ0 =115, DQ1 =107, DQ2 =103, DQ3 =111
3262 09:25:58.479923 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3263 09:25:58.480007 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3264 09:25:58.480092 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3265 09:25:58.480177
3266 09:25:58.480260
3267 09:25:58.480345 ==
3268 09:25:58.480429 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 09:25:58.480514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 09:25:58.480598 ==
3271 09:25:58.480703
3272 09:25:58.480788
3273 09:25:58.480872 TX Vref Scan disable
3274 09:25:58.480956 == TX Byte 0 ==
3275 09:25:58.481041 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3276 09:25:58.481126 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3277 09:25:58.481212 == TX Byte 1 ==
3278 09:25:58.481297 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3279 09:25:58.481382 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3280 09:25:58.481467 ==
3281 09:25:58.481551 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 09:25:58.481834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 09:25:58.481919 ==
3284 09:25:58.482004 TX Vref=22, minBit 8, minWin=24, winSum=407
3285 09:25:58.482091 TX Vref=24, minBit 11, minWin=24, winSum=411
3286 09:25:58.482177 TX Vref=26, minBit 8, minWin=25, winSum=416
3287 09:25:58.482263 TX Vref=28, minBit 9, minWin=25, winSum=425
3288 09:25:58.482348 TX Vref=30, minBit 9, minWin=25, winSum=424
3289 09:25:58.482435 TX Vref=32, minBit 9, minWin=24, winSum=422
3290 09:25:58.482520 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 28
3291 09:25:58.482617
3292 09:25:58.482702 Final TX Range 1 Vref 28
3293 09:25:58.482787
3294 09:25:58.482872 ==
3295 09:25:58.482967 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 09:25:58.483053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 09:25:58.483139 ==
3298 09:25:58.483236
3299 09:25:58.483320
3300 09:25:58.483404 TX Vref Scan disable
3301 09:25:58.483489 == TX Byte 0 ==
3302 09:25:58.483574 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3303 09:25:58.483659 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3304 09:25:58.483744 == TX Byte 1 ==
3305 09:25:58.483829 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3306 09:25:58.483915 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3307 09:25:58.483999
3308 09:25:58.484093 [DATLAT]
3309 09:25:58.484181 Freq=1200, CH1 RK0
3310 09:25:58.484266
3311 09:25:58.484350 DATLAT Default: 0xd
3312 09:25:58.484435 0, 0xFFFF, sum = 0
3313 09:25:58.484523 1, 0xFFFF, sum = 0
3314 09:25:58.484615 2, 0xFFFF, sum = 0
3315 09:25:58.484714 3, 0xFFFF, sum = 0
3316 09:25:58.484802 4, 0xFFFF, sum = 0
3317 09:25:58.484888 5, 0xFFFF, sum = 0
3318 09:25:58.484975 6, 0xFFFF, sum = 0
3319 09:25:58.485061 7, 0xFFFF, sum = 0
3320 09:25:58.485148 8, 0xFFFF, sum = 0
3321 09:25:58.485235 9, 0xFFFF, sum = 0
3322 09:25:58.485322 10, 0xFFFF, sum = 0
3323 09:25:58.485409 11, 0xFFFF, sum = 0
3324 09:25:58.485495 12, 0x0, sum = 1
3325 09:25:58.485583 13, 0x0, sum = 2
3326 09:25:58.485669 14, 0x0, sum = 3
3327 09:25:58.485755 15, 0x0, sum = 4
3328 09:25:58.485843 best_step = 13
3329 09:25:58.485927
3330 09:25:58.486011 ==
3331 09:25:58.486093 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 09:25:58.486176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 09:25:58.486255 ==
3334 09:25:58.486338 RX Vref Scan: 1
3335 09:25:58.486417
3336 09:25:58.486493 Set Vref Range= 32 -> 127
3337 09:25:58.486569
3338 09:25:58.486643 RX Vref 32 -> 127, step: 1
3339 09:25:58.486718
3340 09:25:58.486792 RX Delay -21 -> 252, step: 4
3341 09:25:58.486866
3342 09:25:58.486942 Set Vref, RX VrefLevel [Byte0]: 32
3343 09:25:58.487018 [Byte1]: 32
3344 09:25:58.487093
3345 09:25:58.487167 Set Vref, RX VrefLevel [Byte0]: 33
3346 09:25:58.487244 [Byte1]: 33
3347 09:25:58.487318
3348 09:25:58.487392 Set Vref, RX VrefLevel [Byte0]: 34
3349 09:25:58.487467 [Byte1]: 34
3350 09:25:58.487542
3351 09:25:58.487615 Set Vref, RX VrefLevel [Byte0]: 35
3352 09:25:58.487690 [Byte1]: 35
3353 09:25:58.487764
3354 09:25:58.487838 Set Vref, RX VrefLevel [Byte0]: 36
3355 09:25:58.487913 [Byte1]: 36
3356 09:25:58.487988
3357 09:25:58.488061 Set Vref, RX VrefLevel [Byte0]: 37
3358 09:25:58.488137 [Byte1]: 37
3359 09:25:58.488211
3360 09:25:58.488285 Set Vref, RX VrefLevel [Byte0]: 38
3361 09:25:58.488361 [Byte1]: 38
3362 09:25:58.488436
3363 09:25:58.488510 Set Vref, RX VrefLevel [Byte0]: 39
3364 09:25:58.488585 [Byte1]: 39
3365 09:25:58.488685
3366 09:25:58.488761 Set Vref, RX VrefLevel [Byte0]: 40
3367 09:25:58.488856 [Byte1]: 40
3368 09:25:58.488934
3369 09:25:58.489009 Set Vref, RX VrefLevel [Byte0]: 41
3370 09:25:58.489099 [Byte1]: 41
3371 09:25:58.489175
3372 09:25:58.489256 Set Vref, RX VrefLevel [Byte0]: 42
3373 09:25:58.489332 [Byte1]: 42
3374 09:25:58.489409
3375 09:25:58.489485 Set Vref, RX VrefLevel [Byte0]: 43
3376 09:25:58.489560 [Byte1]: 43
3377 09:25:58.489635
3378 09:25:58.489710 Set Vref, RX VrefLevel [Byte0]: 44
3379 09:25:58.489784 [Byte1]: 44
3380 09:25:58.489858
3381 09:25:58.489932 Set Vref, RX VrefLevel [Byte0]: 45
3382 09:25:58.490007 [Byte1]: 45
3383 09:25:58.490081
3384 09:25:58.490155 Set Vref, RX VrefLevel [Byte0]: 46
3385 09:25:58.490230 [Byte1]: 46
3386 09:25:58.490304
3387 09:25:58.490379 Set Vref, RX VrefLevel [Byte0]: 47
3388 09:25:58.490453 [Byte1]: 47
3389 09:25:58.490527
3390 09:25:58.490601 Set Vref, RX VrefLevel [Byte0]: 48
3391 09:25:58.490675 [Byte1]: 48
3392 09:25:58.490750
3393 09:25:58.490824 Set Vref, RX VrefLevel [Byte0]: 49
3394 09:25:58.490899 [Byte1]: 49
3395 09:25:58.490973
3396 09:25:58.491047 Set Vref, RX VrefLevel [Byte0]: 50
3397 09:25:58.491121 [Byte1]: 50
3398 09:25:58.491196
3399 09:25:58.491270 Set Vref, RX VrefLevel [Byte0]: 51
3400 09:25:58.491344 [Byte1]: 51
3401 09:25:58.491418
3402 09:25:58.491491 Set Vref, RX VrefLevel [Byte0]: 52
3403 09:25:58.491565 [Byte1]: 52
3404 09:25:58.491639
3405 09:25:58.491713 Set Vref, RX VrefLevel [Byte0]: 53
3406 09:25:58.491787 [Byte1]: 53
3407 09:25:58.491862
3408 09:25:58.491936 Set Vref, RX VrefLevel [Byte0]: 54
3409 09:25:58.492010 [Byte1]: 54
3410 09:25:58.492084
3411 09:25:58.492158 Set Vref, RX VrefLevel [Byte0]: 55
3412 09:25:58.492234 [Byte1]: 55
3413 09:25:58.492309
3414 09:25:58.492383 Set Vref, RX VrefLevel [Byte0]: 56
3415 09:25:58.492458 [Byte1]: 56
3416 09:25:58.492533
3417 09:25:58.492606 Set Vref, RX VrefLevel [Byte0]: 57
3418 09:25:58.492731 [Byte1]: 57
3419 09:25:58.492810
3420 09:25:58.492885 Set Vref, RX VrefLevel [Byte0]: 58
3421 09:25:58.492960 [Byte1]: 58
3422 09:25:58.493034
3423 09:25:58.493107 Set Vref, RX VrefLevel [Byte0]: 59
3424 09:25:58.493181 [Byte1]: 59
3425 09:25:58.493253
3426 09:25:58.493325 Set Vref, RX VrefLevel [Byte0]: 60
3427 09:25:58.493402 [Byte1]: 60
3428 09:25:58.493480
3429 09:25:58.493576 Set Vref, RX VrefLevel [Byte0]: 61
3430 09:25:58.493656 [Byte1]: 61
3431 09:25:58.493734
3432 09:25:58.493813 Set Vref, RX VrefLevel [Byte0]: 62
3433 09:25:58.493888 [Byte1]: 62
3434 09:25:58.493962
3435 09:25:58.494036 Set Vref, RX VrefLevel [Byte0]: 63
3436 09:25:58.494110 [Byte1]: 63
3437 09:25:58.494185
3438 09:25:58.494259 Set Vref, RX VrefLevel [Byte0]: 64
3439 09:25:58.494340 [Byte1]: 64
3440 09:25:58.494426
3441 09:25:58.494508 Final RX Vref Byte 0 = 58 to rank0
3442 09:25:58.494596 Final RX Vref Byte 1 = 51 to rank0
3443 09:25:58.494682 Final RX Vref Byte 0 = 58 to rank1
3444 09:25:58.494769 Final RX Vref Byte 1 = 51 to rank1==
3445 09:25:58.494869 Dram Type= 6, Freq= 0, CH_1, rank 0
3446 09:25:58.494958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 09:25:58.495043 ==
3448 09:25:58.495324 DQS Delay:
3449 09:25:58.495406 DQS0 = 0, DQS1 = 0
3450 09:25:58.495485 DQM Delay:
3451 09:25:58.495562 DQM0 = 113, DQM1 = 105
3452 09:25:58.495639 DQ Delay:
3453 09:25:58.495716 DQ0 =116, DQ1 =108, DQ2 =104, DQ3 =112
3454 09:25:58.495794 DQ4 =110, DQ5 =124, DQ6 =126, DQ7 =110
3455 09:25:58.495871 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =100
3456 09:25:58.495948 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =112
3457 09:25:58.496029
3458 09:25:58.496108
3459 09:25:58.496187 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3460 09:25:58.496266 CH1 RK0: MR19=303, MR18=F0F7
3461 09:25:58.496344 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3462 09:25:58.496420
3463 09:25:58.496497 ----->DramcWriteLeveling(PI) begin...
3464 09:25:58.496575 ==
3465 09:25:58.496662 Dram Type= 6, Freq= 0, CH_1, rank 1
3466 09:25:58.496741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3467 09:25:58.496818 ==
3468 09:25:58.496895 Write leveling (Byte 0): 25 => 25
3469 09:25:58.496972 Write leveling (Byte 1): 26 => 26
3470 09:25:58.497048 DramcWriteLeveling(PI) end<-----
3471 09:25:58.497124
3472 09:25:58.497200 ==
3473 09:25:58.497277 Dram Type= 6, Freq= 0, CH_1, rank 1
3474 09:25:58.497355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 09:25:58.497431 ==
3476 09:25:58.497508 [Gating] SW mode calibration
3477 09:25:58.497586 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3478 09:25:58.497664 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3479 09:25:58.497742 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3480 09:25:58.497820 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 09:25:58.497897 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 09:25:58.497975 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 09:25:58.498052 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 09:25:58.498130 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 09:25:58.498207 0 15 24 | B1->B0 | 3434 2323 | 0 1 | (0 1) (1 0)
3486 09:25:58.498284 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3487 09:25:58.498361 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 09:25:58.498438 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 09:25:58.498515 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 09:25:58.498593 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 09:25:58.498669 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 09:25:58.498746 1 0 20 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
3493 09:25:58.498823 1 0 24 | B1->B0 | 2d2d 4545 | 0 0 | (0 0) (0 0)
3494 09:25:58.498900 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3495 09:25:58.498978 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 09:25:58.499056 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 09:25:58.499133 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 09:25:58.499210 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 09:25:58.499288 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 09:25:58.499365 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3501 09:25:58.499442 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3502 09:25:58.499519 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3503 09:25:58.499596 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3504 09:25:58.499672 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 09:25:58.499749 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 09:25:58.499826 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 09:25:58.499903 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 09:25:58.499979 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 09:25:58.500055 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 09:25:58.500132 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 09:25:58.500209 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 09:25:58.500286 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 09:25:58.500362 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 09:25:58.500439 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 09:25:58.500516 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 09:25:58.500592 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 09:25:58.500676 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3518 09:25:58.500728 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3519 09:25:58.500777 Total UI for P1: 0, mck2ui 16
3520 09:25:58.500826 best dqsien dly found for B0: ( 1, 3, 24)
3521 09:25:58.500876 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 09:25:58.500924 Total UI for P1: 0, mck2ui 16
3523 09:25:58.500972 best dqsien dly found for B1: ( 1, 3, 26)
3524 09:25:58.501021 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3525 09:25:58.501069 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3526 09:25:58.501117
3527 09:25:58.501165 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3528 09:25:58.501213 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3529 09:25:58.501263 [Gating] SW calibration Done
3530 09:25:58.501311 ==
3531 09:25:58.501359 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 09:25:58.501407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 09:25:58.501456 ==
3534 09:25:58.501503 RX Vref Scan: 0
3535 09:25:58.501550
3536 09:25:58.501598 RX Vref 0 -> 0, step: 1
3537 09:25:58.501645
3538 09:25:58.501693 RX Delay -40 -> 252, step: 8
3539 09:25:58.501741 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3540 09:25:58.501805 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3541 09:25:58.501856 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3542 09:25:58.501904 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3543 09:25:58.501953 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3544 09:25:58.502018 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3545 09:25:58.502067 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3546 09:25:58.502116 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3547 09:25:58.502164 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3548 09:25:58.502215 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3549 09:25:58.502264 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3550 09:25:58.502509 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3551 09:25:58.502565 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3552 09:25:58.502623 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3553 09:25:58.502674 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3554 09:25:58.502723 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3555 09:25:58.502772 ==
3556 09:25:58.502821 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 09:25:58.502869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 09:25:58.502919 ==
3559 09:25:58.502968 DQS Delay:
3560 09:25:58.503017 DQS0 = 0, DQS1 = 0
3561 09:25:58.503065 DQM Delay:
3562 09:25:58.503112 DQM0 = 110, DQM1 = 108
3563 09:25:58.503160 DQ Delay:
3564 09:25:58.503208 DQ0 =115, DQ1 =103, DQ2 =99, DQ3 =107
3565 09:25:58.503256 DQ4 =107, DQ5 =123, DQ6 =119, DQ7 =107
3566 09:25:58.503306 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3567 09:25:58.503354 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3568 09:25:58.503404
3569 09:25:58.503452
3570 09:25:58.503499 ==
3571 09:25:58.503547 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 09:25:58.503595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 09:25:58.503644 ==
3574 09:25:58.503692
3575 09:25:58.503738
3576 09:25:58.503786 TX Vref Scan disable
3577 09:25:58.503834 == TX Byte 0 ==
3578 09:25:58.503891 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3579 09:25:58.503942 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3580 09:25:58.503992 == TX Byte 1 ==
3581 09:25:58.504040 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3582 09:25:58.504087 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3583 09:25:58.504135 ==
3584 09:25:58.504182 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 09:25:58.504230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 09:25:58.504278 ==
3587 09:25:58.504326 TX Vref=22, minBit 9, minWin=25, winSum=418
3588 09:25:58.504375 TX Vref=24, minBit 7, minWin=26, winSum=427
3589 09:25:58.504423 TX Vref=26, minBit 9, minWin=25, winSum=428
3590 09:25:58.504472 TX Vref=28, minBit 7, minWin=26, winSum=433
3591 09:25:58.504520 TX Vref=30, minBit 9, minWin=26, winSum=433
3592 09:25:58.504568 TX Vref=32, minBit 9, minWin=25, winSum=427
3593 09:25:58.504616 [TxChooseVref] Worse bit 7, Min win 26, Win sum 433, Final Vref 28
3594 09:25:58.504676
3595 09:25:58.504726 Final TX Range 1 Vref 28
3596 09:25:58.504774
3597 09:25:58.504821 ==
3598 09:25:58.504869 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 09:25:58.504917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 09:25:58.504966 ==
3601 09:25:58.505014
3602 09:25:58.505061
3603 09:25:58.505108 TX Vref Scan disable
3604 09:25:58.505156 == TX Byte 0 ==
3605 09:25:58.505203 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3606 09:25:58.505252 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3607 09:25:58.505300 == TX Byte 1 ==
3608 09:25:58.505348 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3609 09:25:58.505397 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3610 09:25:58.505445
3611 09:25:58.505493 [DATLAT]
3612 09:25:58.505541 Freq=1200, CH1 RK1
3613 09:25:58.505589
3614 09:25:58.505637 DATLAT Default: 0xd
3615 09:25:58.505684 0, 0xFFFF, sum = 0
3616 09:25:58.505734 1, 0xFFFF, sum = 0
3617 09:25:58.505783 2, 0xFFFF, sum = 0
3618 09:25:58.505831 3, 0xFFFF, sum = 0
3619 09:25:58.505879 4, 0xFFFF, sum = 0
3620 09:25:58.505928 5, 0xFFFF, sum = 0
3621 09:25:58.505975 6, 0xFFFF, sum = 0
3622 09:25:58.506024 7, 0xFFFF, sum = 0
3623 09:25:58.506071 8, 0xFFFF, sum = 0
3624 09:25:58.506121 9, 0xFFFF, sum = 0
3625 09:25:58.506169 10, 0xFFFF, sum = 0
3626 09:25:58.506218 11, 0xFFFF, sum = 0
3627 09:25:58.506266 12, 0x0, sum = 1
3628 09:25:58.506315 13, 0x0, sum = 2
3629 09:25:58.506363 14, 0x0, sum = 3
3630 09:25:58.506411 15, 0x0, sum = 4
3631 09:25:58.506460 best_step = 13
3632 09:25:58.506508
3633 09:25:58.506556 ==
3634 09:25:58.506603 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 09:25:58.506651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 09:25:58.506699 ==
3637 09:25:58.506747 RX Vref Scan: 0
3638 09:25:58.506794
3639 09:25:58.506841 RX Vref 0 -> 0, step: 1
3640 09:25:58.506888
3641 09:25:58.506935 RX Delay -21 -> 252, step: 4
3642 09:25:58.506997 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3643 09:25:58.507047 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3644 09:25:58.507095 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3645 09:25:58.507144 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3646 09:25:58.507191 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3647 09:25:58.507239 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3648 09:25:58.507287 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3649 09:25:58.507334 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3650 09:25:58.507382 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3651 09:25:58.507430 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3652 09:25:58.507478 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3653 09:25:58.507526 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3654 09:25:58.507575 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3655 09:25:58.507622 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3656 09:25:58.507670 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3657 09:25:58.507717 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3658 09:25:58.507765 ==
3659 09:25:58.507813 Dram Type= 6, Freq= 0, CH_1, rank 1
3660 09:25:58.507862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3661 09:25:58.507911 ==
3662 09:25:58.507958 DQS Delay:
3663 09:25:58.508005 DQS0 = 0, DQS1 = 0
3664 09:25:58.508053 DQM Delay:
3665 09:25:58.508101 DQM0 = 111, DQM1 = 109
3666 09:25:58.508148 DQ Delay:
3667 09:25:58.508195 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =110
3668 09:25:58.508243 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3669 09:25:58.508291 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =104
3670 09:25:58.508339 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3671 09:25:58.508387
3672 09:25:58.508434
3673 09:25:58.508482 [DQSOSCAuto] RK1, (LSB)MR18= 0xfe0d, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 410 ps
3674 09:25:58.508531 CH1 RK1: MR19=304, MR18=FE0D
3675 09:25:58.508579 CH1_RK1: MR19=0x304, MR18=0xFE0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3676 09:25:58.508627 [RxdqsGatingPostProcess] freq 1200
3677 09:25:58.508684 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3678 09:25:58.508734 best DQS0 dly(2T, 0.5T) = (0, 11)
3679 09:25:58.508782 best DQS1 dly(2T, 0.5T) = (0, 11)
3680 09:25:58.508830 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3681 09:25:58.508878 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3682 09:25:58.508926 best DQS0 dly(2T, 0.5T) = (0, 11)
3683 09:25:58.508973 best DQS1 dly(2T, 0.5T) = (0, 11)
3684 09:25:58.509021 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3685 09:25:58.509069 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3686 09:25:58.509117 Pre-setting of DQS Precalculation
3687 09:25:58.509164 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3688 09:25:58.509405 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3689 09:25:58.509461 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3690 09:25:58.509512
3691 09:25:58.509560
3692 09:25:58.509608 [Calibration Summary] 2400 Mbps
3693 09:25:58.509657 CH 0, Rank 0
3694 09:25:58.509706 SW Impedance : PASS
3695 09:25:58.509754 DUTY Scan : NO K
3696 09:25:58.509802 ZQ Calibration : PASS
3697 09:25:58.509850 Jitter Meter : NO K
3698 09:25:58.509898 CBT Training : PASS
3699 09:25:58.509946 Write leveling : PASS
3700 09:25:58.509994 RX DQS gating : PASS
3701 09:25:58.510042 RX DQ/DQS(RDDQC) : PASS
3702 09:25:58.510090 TX DQ/DQS : PASS
3703 09:25:58.510138 RX DATLAT : PASS
3704 09:25:58.510186 RX DQ/DQS(Engine): PASS
3705 09:25:58.510233 TX OE : NO K
3706 09:25:58.510281 All Pass.
3707 09:25:58.510329
3708 09:25:58.510377 CH 0, Rank 1
3709 09:25:58.510425 SW Impedance : PASS
3710 09:25:58.510473 DUTY Scan : NO K
3711 09:25:58.510521 ZQ Calibration : PASS
3712 09:25:58.510569 Jitter Meter : NO K
3713 09:25:58.510617 CBT Training : PASS
3714 09:25:58.510665 Write leveling : PASS
3715 09:25:58.510713 RX DQS gating : PASS
3716 09:25:58.510761 RX DQ/DQS(RDDQC) : PASS
3717 09:25:58.510807 TX DQ/DQS : PASS
3718 09:25:58.510855 RX DATLAT : PASS
3719 09:25:58.510903 RX DQ/DQS(Engine): PASS
3720 09:25:58.510951 TX OE : NO K
3721 09:25:58.511025 All Pass.
3722 09:25:58.511076
3723 09:25:58.511124 CH 1, Rank 0
3724 09:25:58.511172 SW Impedance : PASS
3725 09:25:58.511220 DUTY Scan : NO K
3726 09:25:58.511268 ZQ Calibration : PASS
3727 09:25:58.511315 Jitter Meter : NO K
3728 09:25:58.511363 CBT Training : PASS
3729 09:25:58.511410 Write leveling : PASS
3730 09:25:58.511458 RX DQS gating : PASS
3731 09:25:58.511506 RX DQ/DQS(RDDQC) : PASS
3732 09:25:58.511553 TX DQ/DQS : PASS
3733 09:25:58.511601 RX DATLAT : PASS
3734 09:25:58.511651 RX DQ/DQS(Engine): PASS
3735 09:25:58.511699 TX OE : NO K
3736 09:25:58.511747 All Pass.
3737 09:25:58.511795
3738 09:25:58.511842 CH 1, Rank 1
3739 09:25:58.511889 SW Impedance : PASS
3740 09:25:58.511937 DUTY Scan : NO K
3741 09:25:58.511985 ZQ Calibration : PASS
3742 09:25:58.512034 Jitter Meter : NO K
3743 09:25:58.512082 CBT Training : PASS
3744 09:25:58.512129 Write leveling : PASS
3745 09:25:58.512177 RX DQS gating : PASS
3746 09:25:58.512225 RX DQ/DQS(RDDQC) : PASS
3747 09:25:58.512273 TX DQ/DQS : PASS
3748 09:25:58.512322 RX DATLAT : PASS
3749 09:25:58.512370 RX DQ/DQS(Engine): PASS
3750 09:25:58.512417 TX OE : NO K
3751 09:25:58.512465 All Pass.
3752 09:25:58.512513
3753 09:25:58.512560 DramC Write-DBI off
3754 09:25:58.512608 PER_BANK_REFRESH: Hybrid Mode
3755 09:25:58.512665 TX_TRACKING: ON
3756 09:25:58.512716 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3757 09:25:58.512766 [FAST_K] Save calibration result to emmc
3758 09:25:58.512815 dramc_set_vcore_voltage set vcore to 650000
3759 09:25:58.512863 Read voltage for 600, 5
3760 09:25:58.512909 Vio18 = 0
3761 09:25:58.512957 Vcore = 650000
3762 09:25:58.513005 Vdram = 0
3763 09:25:58.513053 Vddq = 0
3764 09:25:58.513101 Vmddr = 0
3765 09:25:58.513149 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3766 09:25:58.513197 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3767 09:25:58.513245 MEM_TYPE=3, freq_sel=19
3768 09:25:58.513293 sv_algorithm_assistance_LP4_1600
3769 09:25:58.513342 ============ PULL DRAM RESETB DOWN ============
3770 09:25:58.513390 ========== PULL DRAM RESETB DOWN end =========
3771 09:25:58.513438 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3772 09:25:58.513486 ===================================
3773 09:25:58.513535 LPDDR4 DRAM CONFIGURATION
3774 09:25:58.513582 ===================================
3775 09:25:58.513631 EX_ROW_EN[0] = 0x0
3776 09:25:58.513679 EX_ROW_EN[1] = 0x0
3777 09:25:58.513728 LP4Y_EN = 0x0
3778 09:25:58.513775 WORK_FSP = 0x0
3779 09:25:58.513823 WL = 0x2
3780 09:25:58.513870 RL = 0x2
3781 09:25:58.513918 BL = 0x2
3782 09:25:58.513966 RPST = 0x0
3783 09:25:58.514014 RD_PRE = 0x0
3784 09:25:58.514061 WR_PRE = 0x1
3785 09:25:58.514109 WR_PST = 0x0
3786 09:25:58.514156 DBI_WR = 0x0
3787 09:25:58.514203 DBI_RD = 0x0
3788 09:25:58.514250 OTF = 0x1
3789 09:25:58.514299 ===================================
3790 09:25:58.514347 ===================================
3791 09:25:58.514395 ANA top config
3792 09:25:58.514442 ===================================
3793 09:25:58.514491 DLL_ASYNC_EN = 0
3794 09:25:58.514539 ALL_SLAVE_EN = 1
3795 09:25:58.514586 NEW_RANK_MODE = 1
3796 09:25:58.514635 DLL_IDLE_MODE = 1
3797 09:25:58.514682 LP45_APHY_COMB_EN = 1
3798 09:25:58.514730 TX_ODT_DIS = 1
3799 09:25:58.514778 NEW_8X_MODE = 1
3800 09:25:58.514826 ===================================
3801 09:25:58.514874 ===================================
3802 09:25:58.514921 data_rate = 1200
3803 09:25:58.514972 CKR = 1
3804 09:25:58.515048 DQ_P2S_RATIO = 8
3805 09:25:58.515122 ===================================
3806 09:25:58.515172 CA_P2S_RATIO = 8
3807 09:25:58.515221 DQ_CA_OPEN = 0
3808 09:25:58.515270 DQ_SEMI_OPEN = 0
3809 09:25:58.515318 CA_SEMI_OPEN = 0
3810 09:25:58.515366 CA_FULL_RATE = 0
3811 09:25:58.515414 DQ_CKDIV4_EN = 1
3812 09:25:58.515462 CA_CKDIV4_EN = 1
3813 09:25:58.515510 CA_PREDIV_EN = 0
3814 09:25:58.515558 PH8_DLY = 0
3815 09:25:58.515605 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3816 09:25:58.515654 DQ_AAMCK_DIV = 4
3817 09:25:58.515701 CA_AAMCK_DIV = 4
3818 09:25:58.515749 CA_ADMCK_DIV = 4
3819 09:25:58.515797 DQ_TRACK_CA_EN = 0
3820 09:25:58.515844 CA_PICK = 600
3821 09:25:58.515892 CA_MCKIO = 600
3822 09:25:58.515940 MCKIO_SEMI = 0
3823 09:25:58.515988 PLL_FREQ = 2288
3824 09:25:58.516036 DQ_UI_PI_RATIO = 32
3825 09:25:58.516084 CA_UI_PI_RATIO = 0
3826 09:25:58.516132 ===================================
3827 09:25:58.516180 ===================================
3828 09:25:58.516228 memory_type:LPDDR4
3829 09:25:58.516276 GP_NUM : 10
3830 09:25:58.516324 SRAM_EN : 1
3831 09:25:58.516372 MD32_EN : 0
3832 09:25:58.516419 ===================================
3833 09:25:58.516468 [ANA_INIT] >>>>>>>>>>>>>>
3834 09:25:58.516516 <<<<<< [CONFIGURE PHASE]: ANA_TX
3835 09:25:58.516564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3836 09:25:58.516611 ===================================
3837 09:25:58.516864 data_rate = 1200,PCW = 0X5800
3838 09:25:58.516921 ===================================
3839 09:25:58.516971 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3840 09:25:58.517021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3841 09:25:58.517070 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3842 09:25:58.517119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3843 09:25:58.517167 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3844 09:25:58.517215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3845 09:25:58.517263 [ANA_INIT] flow start
3846 09:25:58.517312 [ANA_INIT] PLL >>>>>>>>
3847 09:25:58.517360 [ANA_INIT] PLL <<<<<<<<
3848 09:25:58.517408 [ANA_INIT] MIDPI >>>>>>>>
3849 09:25:58.517455 [ANA_INIT] MIDPI <<<<<<<<
3850 09:25:58.517503 [ANA_INIT] DLL >>>>>>>>
3851 09:25:58.517550 [ANA_INIT] flow end
3852 09:25:58.517597 ============ LP4 DIFF to SE enter ============
3853 09:25:58.517645 ============ LP4 DIFF to SE exit ============
3854 09:25:58.517694 [ANA_INIT] <<<<<<<<<<<<<
3855 09:25:58.517742 [Flow] Enable top DCM control >>>>>
3856 09:25:58.517791 [Flow] Enable top DCM control <<<<<
3857 09:25:58.517839 Enable DLL master slave shuffle
3858 09:25:58.517886 ==============================================================
3859 09:25:58.517935 Gating Mode config
3860 09:25:58.517993 ==============================================================
3861 09:25:58.518044 Config description:
3862 09:25:58.518092 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3863 09:25:58.518142 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3864 09:25:58.518206 SELPH_MODE 0: By rank 1: By Phase
3865 09:25:58.518258 ==============================================================
3866 09:25:58.518308 GAT_TRACK_EN = 1
3867 09:25:58.518357 RX_GATING_MODE = 2
3868 09:25:58.518415 RX_GATING_TRACK_MODE = 2
3869 09:25:58.518465 SELPH_MODE = 1
3870 09:25:58.518513 PICG_EARLY_EN = 1
3871 09:25:58.518561 VALID_LAT_VALUE = 1
3872 09:25:58.518619 ==============================================================
3873 09:25:58.518668 Enter into Gating configuration >>>>
3874 09:25:58.518717 Exit from Gating configuration <<<<
3875 09:25:58.518778 Enter into DVFS_PRE_config >>>>>
3876 09:25:58.518828 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3877 09:25:58.518891 Exit from DVFS_PRE_config <<<<<
3878 09:25:58.521647 Enter into PICG configuration >>>>
3879 09:25:58.525465 Exit from PICG configuration <<<<
3880 09:25:58.528593 [RX_INPUT] configuration >>>>>
3881 09:25:58.528683 [RX_INPUT] configuration <<<<<
3882 09:25:58.534972 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3883 09:25:58.541989 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3884 09:25:58.548109 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3885 09:25:58.551397 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3886 09:25:58.558536 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3887 09:25:58.564703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3888 09:25:58.568462 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3889 09:25:58.571477 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3890 09:25:58.578010 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3891 09:25:58.581720 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3892 09:25:58.584814 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3893 09:25:58.591543 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3894 09:25:58.594812 ===================================
3895 09:25:58.594903 LPDDR4 DRAM CONFIGURATION
3896 09:25:58.598259 ===================================
3897 09:25:58.601191 EX_ROW_EN[0] = 0x0
3898 09:25:58.601291 EX_ROW_EN[1] = 0x0
3899 09:25:58.604798 LP4Y_EN = 0x0
3900 09:25:58.607929 WORK_FSP = 0x0
3901 09:25:58.608005 WL = 0x2
3902 09:25:58.611044 RL = 0x2
3903 09:25:58.611122 BL = 0x2
3904 09:25:58.614996 RPST = 0x0
3905 09:25:58.615104 RD_PRE = 0x0
3906 09:25:58.618088 WR_PRE = 0x1
3907 09:25:58.618164 WR_PST = 0x0
3908 09:25:58.621057 DBI_WR = 0x0
3909 09:25:58.621141 DBI_RD = 0x0
3910 09:25:58.624610 OTF = 0x1
3911 09:25:58.627873 ===================================
3912 09:25:58.631158 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3913 09:25:58.634798 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3914 09:25:58.641104 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3915 09:25:58.644739 ===================================
3916 09:25:58.644819 LPDDR4 DRAM CONFIGURATION
3917 09:25:58.647876 ===================================
3918 09:25:58.651093 EX_ROW_EN[0] = 0x10
3919 09:25:58.651168 EX_ROW_EN[1] = 0x0
3920 09:25:58.654686 LP4Y_EN = 0x0
3921 09:25:58.654762 WORK_FSP = 0x0
3922 09:25:58.657834 WL = 0x2
3923 09:25:58.660973 RL = 0x2
3924 09:25:58.661077 BL = 0x2
3925 09:25:58.664460 RPST = 0x0
3926 09:25:58.664559 RD_PRE = 0x0
3927 09:25:58.667947 WR_PRE = 0x1
3928 09:25:58.668057 WR_PST = 0x0
3929 09:25:58.670950 DBI_WR = 0x0
3930 09:25:58.671040 DBI_RD = 0x0
3931 09:25:58.674170 OTF = 0x1
3932 09:25:58.677870 ===================================
3933 09:25:58.684512 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3934 09:25:58.687790 nWR fixed to 30
3935 09:25:58.687892 [ModeRegInit_LP4] CH0 RK0
3936 09:25:58.690975 [ModeRegInit_LP4] CH0 RK1
3937 09:25:58.694108 [ModeRegInit_LP4] CH1 RK0
3938 09:25:58.694197 [ModeRegInit_LP4] CH1 RK1
3939 09:25:58.697864 match AC timing 17
3940 09:25:58.701009 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3941 09:25:58.704046 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3942 09:25:58.710758 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3943 09:25:58.714343 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3944 09:25:58.720839 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3945 09:25:58.720934 ==
3946 09:25:58.723872 Dram Type= 6, Freq= 0, CH_0, rank 0
3947 09:25:58.727516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 09:25:58.727621 ==
3949 09:25:58.733822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 09:25:58.740860 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3951 09:25:58.744031 [CA 0] Center 37 (7~67) winsize 61
3952 09:25:58.747270 [CA 1] Center 37 (7~67) winsize 61
3953 09:25:58.750453 [CA 2] Center 35 (5~65) winsize 61
3954 09:25:58.753564 [CA 3] Center 34 (4~65) winsize 62
3955 09:25:58.757320 [CA 4] Center 34 (4~65) winsize 62
3956 09:25:58.760419 [CA 5] Center 33 (3~64) winsize 62
3957 09:25:58.760521
3958 09:25:58.763688 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3959 09:25:58.763792
3960 09:25:58.766877 [CATrainingPosCal] consider 1 rank data
3961 09:25:58.770174 u2DelayCellTimex100 = 270/100 ps
3962 09:25:58.773857 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3963 09:25:58.776746 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3964 09:25:58.780208 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3965 09:25:58.783653 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3966 09:25:58.786803 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3967 09:25:58.790467 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3968 09:25:58.790547
3969 09:25:58.796568 CA PerBit enable=1, Macro0, CA PI delay=33
3970 09:25:58.796674
3971 09:25:58.796752 [CBTSetCACLKResult] CA Dly = 33
3972 09:25:58.800323 CS Dly: 6 (0~37)
3973 09:25:58.800403 ==
3974 09:25:58.803364 Dram Type= 6, Freq= 0, CH_0, rank 1
3975 09:25:58.807086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 09:25:58.807168 ==
3977 09:25:58.813290 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3978 09:25:58.820307 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3979 09:25:58.823433 [CA 0] Center 37 (7~67) winsize 61
3980 09:25:58.826545 [CA 1] Center 36 (6~67) winsize 62
3981 09:25:58.830041 [CA 2] Center 35 (5~65) winsize 61
3982 09:25:58.833208 [CA 3] Center 35 (5~65) winsize 61
3983 09:25:58.836778 [CA 4] Center 34 (3~65) winsize 63
3984 09:25:58.840253 [CA 5] Center 34 (3~65) winsize 63
3985 09:25:58.840333
3986 09:25:58.843352 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3987 09:25:58.843432
3988 09:25:58.846443 [CATrainingPosCal] consider 2 rank data
3989 09:25:58.850178 u2DelayCellTimex100 = 270/100 ps
3990 09:25:58.853411 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3991 09:25:58.856611 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3992 09:25:58.859861 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3993 09:25:58.862898 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3994 09:25:58.866504 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3995 09:25:58.872858 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3996 09:25:58.872932
3997 09:25:58.876121 CA PerBit enable=1, Macro0, CA PI delay=33
3998 09:25:58.876189
3999 09:25:58.879867 [CBTSetCACLKResult] CA Dly = 33
4000 09:25:58.879964 CS Dly: 6 (0~37)
4001 09:25:58.880036
4002 09:25:58.882953 ----->DramcWriteLeveling(PI) begin...
4003 09:25:58.883021 ==
4004 09:25:58.886016 Dram Type= 6, Freq= 0, CH_0, rank 0
4005 09:25:58.893046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 09:25:58.893124 ==
4007 09:25:58.896093 Write leveling (Byte 0): 33 => 33
4008 09:25:58.896183 Write leveling (Byte 1): 31 => 31
4009 09:25:58.899681 DramcWriteLeveling(PI) end<-----
4010 09:25:58.899748
4011 09:25:58.899817 ==
4012 09:25:58.903072 Dram Type= 6, Freq= 0, CH_0, rank 0
4013 09:25:58.910208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 09:25:58.910286 ==
4015 09:25:58.912612 [Gating] SW mode calibration
4016 09:25:58.919621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4017 09:25:58.922510 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4018 09:25:58.929385 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4019 09:25:58.933058 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4020 09:25:58.936148 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 09:25:58.942492 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4022 09:25:58.946127 0 9 16 | B1->B0 | 3333 2929 | 1 1 | (1 0) (1 0)
4023 09:25:58.949206 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 09:25:58.955869 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 09:25:58.959560 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 09:25:58.962765 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 09:25:58.965982 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 09:25:58.972753 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 09:25:58.975936 0 10 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4030 09:25:58.979098 0 10 16 | B1->B0 | 3535 3b3b | 0 1 | (0 0) (0 0)
4031 09:25:58.985974 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 09:25:58.989102 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 09:25:58.992222 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 09:25:58.998812 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 09:25:59.002352 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 09:25:59.006063 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 09:25:59.012541 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4038 09:25:59.015524 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4039 09:25:59.019356 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 09:25:59.025569 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 09:25:59.029061 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 09:25:59.032114 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 09:25:59.039014 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 09:25:59.042144 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 09:25:59.045385 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 09:25:59.052254 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 09:25:59.055342 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 09:25:59.058287 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 09:25:59.065033 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 09:25:59.068217 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 09:25:59.071954 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 09:25:59.078143 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 09:25:59.081824 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4054 09:25:59.084934 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 09:25:59.088058 Total UI for P1: 0, mck2ui 16
4056 09:25:59.091761 best dqsien dly found for B0: ( 0, 13, 12)
4057 09:25:59.094789 Total UI for P1: 0, mck2ui 16
4058 09:25:59.097892 best dqsien dly found for B1: ( 0, 13, 14)
4059 09:25:59.101696 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4060 09:25:59.104744 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4061 09:25:59.108107
4062 09:25:59.111124 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4063 09:25:59.114767 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4064 09:25:59.117842 [Gating] SW calibration Done
4065 09:25:59.117905 ==
4066 09:25:59.121413 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 09:25:59.124799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 09:25:59.124876 ==
4069 09:25:59.124935 RX Vref Scan: 0
4070 09:25:59.127652
4071 09:25:59.127727 RX Vref 0 -> 0, step: 1
4072 09:25:59.127786
4073 09:25:59.131307 RX Delay -230 -> 252, step: 16
4074 09:25:59.134285 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4075 09:25:59.140961 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4076 09:25:59.144617 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4077 09:25:59.147894 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4078 09:25:59.150996 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4079 09:25:59.154098 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4080 09:25:59.160967 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4081 09:25:59.164089 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4082 09:25:59.167788 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4083 09:25:59.170803 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4084 09:25:59.177694 iDelay=218, Bit 10, Center 25 (-150 ~ 201) 352
4085 09:25:59.180895 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4086 09:25:59.184508 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4087 09:25:59.187603 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4088 09:25:59.193900 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4089 09:25:59.196993 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4090 09:25:59.197072 ==
4091 09:25:59.200652 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 09:25:59.203797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 09:25:59.203868 ==
4094 09:25:59.206965 DQS Delay:
4095 09:25:59.207031 DQS0 = 0, DQS1 = 0
4096 09:25:59.207088 DQM Delay:
4097 09:25:59.210797 DQM0 = 37, DQM1 = 29
4098 09:25:59.210881 DQ Delay:
4099 09:25:59.213840 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4100 09:25:59.217169 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4101 09:25:59.220281 DQ8 =17, DQ9 =17, DQ10 =25, DQ11 =25
4102 09:25:59.224088 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4103 09:25:59.224166
4104 09:25:59.224223
4105 09:25:59.224277 ==
4106 09:25:59.227210 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 09:25:59.233774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 09:25:59.233857 ==
4109 09:25:59.233913
4110 09:25:59.233965
4111 09:25:59.234014 TX Vref Scan disable
4112 09:25:59.237349 == TX Byte 0 ==
4113 09:25:59.240752 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4114 09:25:59.247446 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4115 09:25:59.247522 == TX Byte 1 ==
4116 09:25:59.250772 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4117 09:25:59.257376 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4118 09:25:59.257458 ==
4119 09:25:59.260561 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 09:25:59.263702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 09:25:59.263785 ==
4122 09:25:59.263845
4123 09:25:59.263898
4124 09:25:59.267413 TX Vref Scan disable
4125 09:25:59.270557 == TX Byte 0 ==
4126 09:25:59.274131 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4127 09:25:59.277202 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4128 09:25:59.280234 == TX Byte 1 ==
4129 09:25:59.284014 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4130 09:25:59.287113 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4131 09:25:59.287190
4132 09:25:59.287248 [DATLAT]
4133 09:25:59.290788 Freq=600, CH0 RK0
4134 09:25:59.290864
4135 09:25:59.290927 DATLAT Default: 0x9
4136 09:25:59.293994 0, 0xFFFF, sum = 0
4137 09:25:59.297158 1, 0xFFFF, sum = 0
4138 09:25:59.297239 2, 0xFFFF, sum = 0
4139 09:25:59.300858 3, 0xFFFF, sum = 0
4140 09:25:59.300951 4, 0xFFFF, sum = 0
4141 09:25:59.303938 5, 0xFFFF, sum = 0
4142 09:25:59.304015 6, 0xFFFF, sum = 0
4143 09:25:59.307064 7, 0xFFFF, sum = 0
4144 09:25:59.307142 8, 0x0, sum = 1
4145 09:25:59.310796 9, 0x0, sum = 2
4146 09:25:59.310874 10, 0x0, sum = 3
4147 09:25:59.310934 11, 0x0, sum = 4
4148 09:25:59.313925 best_step = 9
4149 09:25:59.314001
4150 09:25:59.314058 ==
4151 09:25:59.317090 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 09:25:59.320172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 09:25:59.320272 ==
4154 09:25:59.323599 RX Vref Scan: 1
4155 09:25:59.323675
4156 09:25:59.323745 RX Vref 0 -> 0, step: 1
4157 09:25:59.327127
4158 09:25:59.327231 RX Delay -195 -> 252, step: 8
4159 09:25:59.327319
4160 09:25:59.330308 Set Vref, RX VrefLevel [Byte0]: 62
4161 09:25:59.333541 [Byte1]: 47
4162 09:25:59.337867
4163 09:25:59.337951 Final RX Vref Byte 0 = 62 to rank0
4164 09:25:59.340951 Final RX Vref Byte 1 = 47 to rank0
4165 09:25:59.344757 Final RX Vref Byte 0 = 62 to rank1
4166 09:25:59.347645 Final RX Vref Byte 1 = 47 to rank1==
4167 09:25:59.351131 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 09:25:59.357597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 09:25:59.357671 ==
4170 09:25:59.357729 DQS Delay:
4171 09:25:59.357784 DQS0 = 0, DQS1 = 0
4172 09:25:59.361546 DQM Delay:
4173 09:25:59.361622 DQM0 = 35, DQM1 = 28
4174 09:25:59.364432 DQ Delay:
4175 09:25:59.368239 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =32
4176 09:25:59.368337 DQ4 =36, DQ5 =20, DQ6 =40, DQ7 =48
4177 09:25:59.371344 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4178 09:25:59.377626 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4179 09:25:59.377731
4180 09:25:59.377805
4181 09:25:59.384816 [DQSOSCAuto] RK0, (LSB)MR18= 0x4846, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
4182 09:25:59.387953 CH0 RK0: MR19=808, MR18=4846
4183 09:25:59.394732 CH0_RK0: MR19=0x808, MR18=0x4846, DQSOSC=396, MR23=63, INC=167, DEC=111
4184 09:25:59.394803
4185 09:25:59.397861 ----->DramcWriteLeveling(PI) begin...
4186 09:25:59.397931 ==
4187 09:25:59.400909 Dram Type= 6, Freq= 0, CH_0, rank 1
4188 09:25:59.404787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 09:25:59.404867 ==
4190 09:25:59.407928 Write leveling (Byte 0): 31 => 31
4191 09:25:59.411057 Write leveling (Byte 1): 31 => 31
4192 09:25:59.414848 DramcWriteLeveling(PI) end<-----
4193 09:25:59.414919
4194 09:25:59.415001 ==
4195 09:25:59.418005 Dram Type= 6, Freq= 0, CH_0, rank 1
4196 09:25:59.421102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 09:25:59.421170 ==
4198 09:25:59.424253 [Gating] SW mode calibration
4199 09:25:59.431452 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4200 09:25:59.437739 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4201 09:25:59.441360 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4202 09:25:59.444373 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4203 09:25:59.451238 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4204 09:25:59.454339 0 9 12 | B1->B0 | 3434 3030 | 0 0 | (0 1) (1 1)
4205 09:25:59.457864 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
4206 09:25:59.464742 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 09:25:59.467481 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 09:25:59.470867 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 09:25:59.477510 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 09:25:59.480801 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 09:25:59.484536 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 09:25:59.491136 0 10 12 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
4213 09:25:59.494125 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4214 09:25:59.497774 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 09:25:59.504017 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 09:25:59.507190 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 09:25:59.510764 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 09:25:59.517530 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 09:25:59.520765 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 09:25:59.523890 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 09:25:59.530846 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 09:25:59.533970 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 09:25:59.537025 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 09:25:59.544029 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 09:25:59.547149 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 09:25:59.550262 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 09:25:59.557171 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 09:25:59.560369 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 09:25:59.563954 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 09:25:59.570483 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 09:25:59.573532 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 09:25:59.576968 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 09:25:59.583307 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 09:25:59.586330 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 09:25:59.590106 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 09:25:59.596291 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4237 09:25:59.599784 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4238 09:25:59.603317 Total UI for P1: 0, mck2ui 16
4239 09:25:59.606252 best dqsien dly found for B0: ( 0, 13, 12)
4240 09:25:59.609862 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 09:25:59.613045 Total UI for P1: 0, mck2ui 16
4242 09:25:59.616340 best dqsien dly found for B1: ( 0, 13, 16)
4243 09:25:59.619454 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4244 09:25:59.623137 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4245 09:25:59.623213
4246 09:25:59.629409 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4247 09:25:59.632721 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4248 09:25:59.632810 [Gating] SW calibration Done
4249 09:25:59.636460 ==
4250 09:25:59.639561 Dram Type= 6, Freq= 0, CH_0, rank 1
4251 09:25:59.642782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4252 09:25:59.642859 ==
4253 09:25:59.642918 RX Vref Scan: 0
4254 09:25:59.642983
4255 09:25:59.646407 RX Vref 0 -> 0, step: 1
4256 09:25:59.646486
4257 09:25:59.649396 RX Delay -230 -> 252, step: 16
4258 09:25:59.652905 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4259 09:25:59.655922 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4260 09:25:59.662784 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4261 09:25:59.665988 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4262 09:25:59.669205 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4263 09:25:59.672942 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4264 09:25:59.678950 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4265 09:25:59.682458 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4266 09:25:59.685841 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4267 09:25:59.688833 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4268 09:25:59.695579 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4269 09:25:59.698825 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4270 09:25:59.702547 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4271 09:25:59.705693 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4272 09:25:59.709358 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4273 09:25:59.715591 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4274 09:25:59.715667 ==
4275 09:25:59.719195 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 09:25:59.722295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 09:25:59.722372 ==
4278 09:25:59.722431 DQS Delay:
4279 09:25:59.725518 DQS0 = 0, DQS1 = 0
4280 09:25:59.725594 DQM Delay:
4281 09:25:59.728589 DQM0 = 39, DQM1 = 31
4282 09:25:59.728699 DQ Delay:
4283 09:25:59.732248 DQ0 =41, DQ1 =33, DQ2 =41, DQ3 =33
4284 09:25:59.735416 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4285 09:25:59.738517 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4286 09:25:59.742301 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4287 09:25:59.742376
4288 09:25:59.742435
4289 09:25:59.742488 ==
4290 09:25:59.745432 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 09:25:59.748485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 09:25:59.752349 ==
4293 09:25:59.752425
4294 09:25:59.752484
4295 09:25:59.752538 TX Vref Scan disable
4296 09:25:59.755362 == TX Byte 0 ==
4297 09:25:59.758917 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4298 09:25:59.761984 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4299 09:25:59.765420 == TX Byte 1 ==
4300 09:25:59.768772 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4301 09:25:59.771842 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4302 09:25:59.775047 ==
4303 09:25:59.778795 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 09:25:59.781843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 09:25:59.781920 ==
4306 09:25:59.781978
4307 09:25:59.782032
4308 09:25:59.785317 TX Vref Scan disable
4309 09:25:59.785396 == TX Byte 0 ==
4310 09:25:59.791959 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4311 09:25:59.795397 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4312 09:25:59.795468 == TX Byte 1 ==
4313 09:25:59.801639 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4314 09:25:59.804795 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4315 09:25:59.804905
4316 09:25:59.804995 [DATLAT]
4317 09:25:59.808491 Freq=600, CH0 RK1
4318 09:25:59.808580
4319 09:25:59.808700 DATLAT Default: 0x9
4320 09:25:59.811625 0, 0xFFFF, sum = 0
4321 09:25:59.811714 1, 0xFFFF, sum = 0
4322 09:25:59.814744 2, 0xFFFF, sum = 0
4323 09:25:59.818503 3, 0xFFFF, sum = 0
4324 09:25:59.818580 4, 0xFFFF, sum = 0
4325 09:25:59.821391 5, 0xFFFF, sum = 0
4326 09:25:59.821469 6, 0xFFFF, sum = 0
4327 09:25:59.825013 7, 0xFFFF, sum = 0
4328 09:25:59.825098 8, 0x0, sum = 1
4329 09:25:59.825159 9, 0x0, sum = 2
4330 09:25:59.828385 10, 0x0, sum = 3
4331 09:25:59.828461 11, 0x0, sum = 4
4332 09:25:59.831299 best_step = 9
4333 09:25:59.831376
4334 09:25:59.831438 ==
4335 09:25:59.835148 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 09:25:59.838289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 09:25:59.838368 ==
4338 09:25:59.841520 RX Vref Scan: 0
4339 09:25:59.841585
4340 09:25:59.841640 RX Vref 0 -> 0, step: 1
4341 09:25:59.841692
4342 09:25:59.844702 RX Delay -195 -> 252, step: 8
4343 09:25:59.852394 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4344 09:25:59.855511 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4345 09:25:59.858705 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4346 09:25:59.862425 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4347 09:25:59.868541 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4348 09:25:59.872218 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4349 09:25:59.875154 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4350 09:25:59.879063 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4351 09:25:59.885347 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4352 09:25:59.888447 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4353 09:25:59.891907 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4354 09:25:59.894990 iDelay=205, Bit 11, Center 16 (-139 ~ 172) 312
4355 09:25:59.901656 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4356 09:25:59.905123 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4357 09:25:59.908513 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4358 09:25:59.911961 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4359 09:25:59.912057 ==
4360 09:25:59.915092 Dram Type= 6, Freq= 0, CH_0, rank 1
4361 09:25:59.921425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 09:25:59.921495 ==
4363 09:25:59.921555 DQS Delay:
4364 09:25:59.924742 DQS0 = 0, DQS1 = 0
4365 09:25:59.924837 DQM Delay:
4366 09:25:59.924919 DQM0 = 33, DQM1 = 27
4367 09:25:59.928405 DQ Delay:
4368 09:25:59.931435 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4369 09:25:59.935037 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4370 09:25:59.938168 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =16
4371 09:25:59.941259 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4372 09:25:59.941335
4373 09:25:59.941392
4374 09:25:59.948085 [DQSOSCAuto] RK1, (LSB)MR18= 0x7241, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4375 09:25:59.951107 CH0 RK1: MR19=808, MR18=7241
4376 09:25:59.957957 CH0_RK1: MR19=0x808, MR18=0x7241, DQSOSC=388, MR23=63, INC=174, DEC=116
4377 09:25:59.961171 [RxdqsGatingPostProcess] freq 600
4378 09:25:59.965005 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4379 09:25:59.967917 Pre-setting of DQS Precalculation
4380 09:25:59.974803 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4381 09:25:59.974879 ==
4382 09:25:59.977884 Dram Type= 6, Freq= 0, CH_1, rank 0
4383 09:25:59.981369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 09:25:59.981449 ==
4385 09:25:59.988266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4386 09:25:59.994521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4387 09:25:59.998088 [CA 0] Center 36 (6~66) winsize 61
4388 09:26:00.001128 [CA 1] Center 35 (5~66) winsize 62
4389 09:26:00.004608 [CA 2] Center 34 (4~65) winsize 62
4390 09:26:00.007871 [CA 3] Center 34 (3~65) winsize 63
4391 09:26:00.010937 [CA 4] Center 34 (4~65) winsize 62
4392 09:26:00.014636 [CA 5] Center 33 (3~64) winsize 62
4393 09:26:00.014712
4394 09:26:00.017986 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4395 09:26:00.018064
4396 09:26:00.021364 [CATrainingPosCal] consider 1 rank data
4397 09:26:00.024580 u2DelayCellTimex100 = 270/100 ps
4398 09:26:00.027716 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4399 09:26:00.030850 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4400 09:26:00.034669 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4401 09:26:00.037662 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4402 09:26:00.040808 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 09:26:00.044566 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4404 09:26:00.044679
4405 09:26:00.047519 CA PerBit enable=1, Macro0, CA PI delay=33
4406 09:26:00.051013
4407 09:26:00.051120 [CBTSetCACLKResult] CA Dly = 33
4408 09:26:00.054163 CS Dly: 4 (0~35)
4409 09:26:00.054240 ==
4410 09:26:00.057961 Dram Type= 6, Freq= 0, CH_1, rank 1
4411 09:26:00.061106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 09:26:00.061183 ==
4413 09:26:00.067410 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4414 09:26:00.074049 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4415 09:26:00.077279 [CA 0] Center 36 (6~66) winsize 61
4416 09:26:00.080970 [CA 1] Center 35 (5~66) winsize 62
4417 09:26:00.084142 [CA 2] Center 34 (4~65) winsize 62
4418 09:26:00.087233 [CA 3] Center 34 (3~65) winsize 63
4419 09:26:00.090852 [CA 4] Center 34 (4~65) winsize 62
4420 09:26:00.093869 [CA 5] Center 33 (3~64) winsize 62
4421 09:26:00.093947
4422 09:26:00.097318 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4423 09:26:00.097396
4424 09:26:00.100398 [CATrainingPosCal] consider 2 rank data
4425 09:26:00.104121 u2DelayCellTimex100 = 270/100 ps
4426 09:26:00.106941 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4427 09:26:00.110346 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4428 09:26:00.113923 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4429 09:26:00.117113 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4430 09:26:00.120195 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4431 09:26:00.123813 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 09:26:00.126800
4433 09:26:00.130324 CA PerBit enable=1, Macro0, CA PI delay=33
4434 09:26:00.130401
4435 09:26:00.133879 [CBTSetCACLKResult] CA Dly = 33
4436 09:26:00.133956 CS Dly: 5 (0~37)
4437 09:26:00.134015
4438 09:26:00.136923 ----->DramcWriteLeveling(PI) begin...
4439 09:26:00.137032 ==
4440 09:26:00.140576 Dram Type= 6, Freq= 0, CH_1, rank 0
4441 09:26:00.143667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 09:26:00.146754 ==
4443 09:26:00.146836 Write leveling (Byte 0): 29 => 29
4444 09:26:00.150465 Write leveling (Byte 1): 30 => 30
4445 09:26:00.153574 DramcWriteLeveling(PI) end<-----
4446 09:26:00.153652
4447 09:26:00.153730 ==
4448 09:26:00.156792 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 09:26:00.163334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 09:26:00.163414 ==
4451 09:26:00.163492 [Gating] SW mode calibration
4452 09:26:00.173470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4453 09:26:00.176440 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4454 09:26:00.183364 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4455 09:26:00.186477 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4456 09:26:00.190226 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4457 09:26:00.196593 0 9 12 | B1->B0 | 3333 3333 | 0 0 | (0 1) (0 1)
4458 09:26:00.199736 0 9 16 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4459 09:26:00.203381 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 09:26:00.206469 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 09:26:00.213348 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 09:26:00.216225 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 09:26:00.219683 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 09:26:00.226609 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 09:26:00.229622 0 10 12 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (0 0)
4466 09:26:00.233136 0 10 16 | B1->B0 | 3f3f 4444 | 0 0 | (0 0) (0 0)
4467 09:26:00.239739 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 09:26:00.242743 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 09:26:00.246379 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 09:26:00.253125 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 09:26:00.256265 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 09:26:00.259380 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 09:26:00.265991 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4474 09:26:00.269725 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 09:26:00.272764 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 09:26:00.279505 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 09:26:00.282595 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 09:26:00.286446 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 09:26:00.292779 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 09:26:00.295902 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 09:26:00.299721 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 09:26:00.305937 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 09:26:00.309460 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 09:26:00.312558 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 09:26:00.319512 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 09:26:00.322488 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 09:26:00.325996 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 09:26:00.332877 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 09:26:00.336014 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4490 09:26:00.339044 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4491 09:26:00.342629 Total UI for P1: 0, mck2ui 16
4492 09:26:00.345729 best dqsien dly found for B0: ( 0, 13, 12)
4493 09:26:00.349415 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 09:26:00.352370 Total UI for P1: 0, mck2ui 16
4495 09:26:00.355838 best dqsien dly found for B1: ( 0, 13, 14)
4496 09:26:00.359179 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4497 09:26:00.366026 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4498 09:26:00.366103
4499 09:26:00.369174 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4500 09:26:00.372922 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4501 09:26:00.375811 [Gating] SW calibration Done
4502 09:26:00.375888 ==
4503 09:26:00.378953 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 09:26:00.382720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 09:26:00.382797 ==
4506 09:26:00.385874 RX Vref Scan: 0
4507 09:26:00.385949
4508 09:26:00.386012 RX Vref 0 -> 0, step: 1
4509 09:26:00.386067
4510 09:26:00.389011 RX Delay -230 -> 252, step: 16
4511 09:26:00.392143 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4512 09:26:00.399056 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4513 09:26:00.402226 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4514 09:26:00.405456 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4515 09:26:00.408580 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4516 09:26:00.415364 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4517 09:26:00.418431 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4518 09:26:00.422231 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4519 09:26:00.425409 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4520 09:26:00.432013 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4521 09:26:00.435553 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4522 09:26:00.438411 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4523 09:26:00.441982 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4524 09:26:00.448466 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4525 09:26:00.451720 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4526 09:26:00.454872 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4527 09:26:00.454963 ==
4528 09:26:00.458103 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 09:26:00.461948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 09:26:00.462015 ==
4531 09:26:00.464818 DQS Delay:
4532 09:26:00.464894 DQS0 = 0, DQS1 = 0
4533 09:26:00.468350 DQM Delay:
4534 09:26:00.468450 DQM0 = 36, DQM1 = 28
4535 09:26:00.468540 DQ Delay:
4536 09:26:00.471811 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4537 09:26:00.474631 DQ4 =33, DQ5 =49, DQ6 =41, DQ7 =33
4538 09:26:00.478256 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4539 09:26:00.481775 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4540 09:26:00.481856
4541 09:26:00.481915
4542 09:26:00.484750 ==
4543 09:26:00.484828 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 09:26:00.491457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 09:26:00.491535 ==
4546 09:26:00.491596
4547 09:26:00.491650
4548 09:26:00.494607 TX Vref Scan disable
4549 09:26:00.494684 == TX Byte 0 ==
4550 09:26:00.501543 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4551 09:26:00.504619 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4552 09:26:00.504750 == TX Byte 1 ==
4553 09:26:00.511079 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4554 09:26:00.514885 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4555 09:26:00.514962 ==
4556 09:26:00.517978 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 09:26:00.520839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 09:26:00.520925 ==
4559 09:26:00.520984
4560 09:26:00.521038
4561 09:26:00.524420 TX Vref Scan disable
4562 09:26:00.527607 == TX Byte 0 ==
4563 09:26:00.530889 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4564 09:26:00.534565 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4565 09:26:00.537651 == TX Byte 1 ==
4566 09:26:00.540703 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4567 09:26:00.544355 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4568 09:26:00.544433
4569 09:26:00.547359 [DATLAT]
4570 09:26:00.547437 Freq=600, CH1 RK0
4571 09:26:00.547497
4572 09:26:00.550850 DATLAT Default: 0x9
4573 09:26:00.550945 0, 0xFFFF, sum = 0
4574 09:26:00.554251 1, 0xFFFF, sum = 0
4575 09:26:00.554386 2, 0xFFFF, sum = 0
4576 09:26:00.557514 3, 0xFFFF, sum = 0
4577 09:26:00.557595 4, 0xFFFF, sum = 0
4578 09:26:00.561053 5, 0xFFFF, sum = 0
4579 09:26:00.561148 6, 0xFFFF, sum = 0
4580 09:26:00.564216 7, 0xFFFF, sum = 0
4581 09:26:00.564294 8, 0x0, sum = 1
4582 09:26:00.567492 9, 0x0, sum = 2
4583 09:26:00.567571 10, 0x0, sum = 3
4584 09:26:00.570586 11, 0x0, sum = 4
4585 09:26:00.570665 best_step = 9
4586 09:26:00.570725
4587 09:26:00.570781 ==
4588 09:26:00.573630 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 09:26:00.580195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 09:26:00.580274 ==
4591 09:26:00.580335 RX Vref Scan: 1
4592 09:26:00.580392
4593 09:26:00.583835 RX Vref 0 -> 0, step: 1
4594 09:26:00.583912
4595 09:26:00.586834 RX Delay -195 -> 252, step: 8
4596 09:26:00.586912
4597 09:26:00.590366 Set Vref, RX VrefLevel [Byte0]: 58
4598 09:26:00.593804 [Byte1]: 51
4599 09:26:00.593883
4600 09:26:00.597040 Final RX Vref Byte 0 = 58 to rank0
4601 09:26:00.600084 Final RX Vref Byte 1 = 51 to rank0
4602 09:26:00.603857 Final RX Vref Byte 0 = 58 to rank1
4603 09:26:00.607104 Final RX Vref Byte 1 = 51 to rank1==
4604 09:26:00.610327 Dram Type= 6, Freq= 0, CH_1, rank 0
4605 09:26:00.613437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 09:26:00.613515 ==
4607 09:26:00.616559 DQS Delay:
4608 09:26:00.616679 DQS0 = 0, DQS1 = 0
4609 09:26:00.619794 DQM Delay:
4610 09:26:00.619871 DQM0 = 39, DQM1 = 28
4611 09:26:00.619931 DQ Delay:
4612 09:26:00.623694 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4613 09:26:00.626646 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4614 09:26:00.629773 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4615 09:26:00.633479 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4616 09:26:00.633557
4617 09:26:00.633617
4618 09:26:00.642909 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
4619 09:26:00.646755 CH1 RK0: MR19=808, MR18=2B38
4620 09:26:00.652906 CH1_RK0: MR19=0x808, MR18=0x2B38, DQSOSC=399, MR23=63, INC=164, DEC=109
4621 09:26:00.652985
4622 09:26:00.656638 ----->DramcWriteLeveling(PI) begin...
4623 09:26:00.656757 ==
4624 09:26:00.659802 Dram Type= 6, Freq= 0, CH_1, rank 1
4625 09:26:00.663286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 09:26:00.663365 ==
4627 09:26:00.666202 Write leveling (Byte 0): 27 => 27
4628 09:26:00.669877 Write leveling (Byte 1): 31 => 31
4629 09:26:00.672841 DramcWriteLeveling(PI) end<-----
4630 09:26:00.672920
4631 09:26:00.672980 ==
4632 09:26:00.676429 Dram Type= 6, Freq= 0, CH_1, rank 1
4633 09:26:00.679573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 09:26:00.679651 ==
4635 09:26:00.682670 [Gating] SW mode calibration
4636 09:26:00.689624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4637 09:26:00.696459 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4638 09:26:00.699516 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4639 09:26:00.702525 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4640 09:26:00.709522 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4641 09:26:00.712465 0 9 12 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (1 1)
4642 09:26:00.716251 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4643 09:26:00.722441 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 09:26:00.725691 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 09:26:00.729418 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 09:26:00.736002 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 09:26:00.739160 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 09:26:00.742300 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4649 09:26:00.749072 0 10 12 | B1->B0 | 3131 3e3e | 0 0 | (0 0) (0 0)
4650 09:26:00.752159 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4651 09:26:00.755824 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 09:26:00.762036 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 09:26:00.765236 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 09:26:00.768986 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 09:26:00.775104 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 09:26:00.778409 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 09:26:00.781883 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 09:26:00.788298 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 09:26:00.791815 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 09:26:00.795531 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 09:26:00.801847 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 09:26:00.805061 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 09:26:00.808741 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 09:26:00.815118 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 09:26:00.818560 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 09:26:00.821999 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 09:26:00.828350 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 09:26:00.831993 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 09:26:00.835060 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 09:26:00.841625 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 09:26:00.844831 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 09:26:00.848546 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 09:26:00.854865 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 09:26:00.854942 Total UI for P1: 0, mck2ui 16
4675 09:26:00.858505 best dqsien dly found for B0: ( 0, 13, 10)
4676 09:26:00.861514 Total UI for P1: 0, mck2ui 16
4677 09:26:00.864786 best dqsien dly found for B1: ( 0, 13, 10)
4678 09:26:00.871084 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4679 09:26:00.874930 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4680 09:26:00.875007
4681 09:26:00.878011 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4682 09:26:00.881097 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4683 09:26:00.884681 [Gating] SW calibration Done
4684 09:26:00.884772 ==
4685 09:26:00.888194 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 09:26:00.891217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 09:26:00.891295 ==
4688 09:26:00.894341 RX Vref Scan: 0
4689 09:26:00.894417
4690 09:26:00.894475 RX Vref 0 -> 0, step: 1
4691 09:26:00.894531
4692 09:26:00.897900 RX Delay -230 -> 252, step: 16
4693 09:26:00.904141 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4694 09:26:00.907980 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4695 09:26:00.911126 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4696 09:26:00.914370 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4697 09:26:00.917978 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4698 09:26:00.924580 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4699 09:26:00.927391 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4700 09:26:00.930906 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4701 09:26:00.934499 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4702 09:26:00.937731 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4703 09:26:00.944411 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4704 09:26:00.947405 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4705 09:26:00.951245 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4706 09:26:00.954356 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4707 09:26:00.960783 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4708 09:26:00.964264 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4709 09:26:00.964350 ==
4710 09:26:00.967379 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 09:26:00.971170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 09:26:00.971248 ==
4713 09:26:00.974373 DQS Delay:
4714 09:26:00.974450 DQS0 = 0, DQS1 = 0
4715 09:26:00.977463 DQM Delay:
4716 09:26:00.977543 DQM0 = 35, DQM1 = 30
4717 09:26:00.977603 DQ Delay:
4718 09:26:00.980766 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4719 09:26:00.983826 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4720 09:26:00.987581 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4721 09:26:00.990622 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4722 09:26:00.990699
4723 09:26:00.990797
4724 09:26:00.990851 ==
4725 09:26:00.994046 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 09:26:01.000917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 09:26:01.001014 ==
4728 09:26:01.001089
4729 09:26:01.001142
4730 09:26:01.001194 TX Vref Scan disable
4731 09:26:01.004565 == TX Byte 0 ==
4732 09:26:01.008380 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4733 09:26:01.014882 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4734 09:26:01.014960 == TX Byte 1 ==
4735 09:26:01.018242 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4736 09:26:01.024879 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4737 09:26:01.024957 ==
4738 09:26:01.028011 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 09:26:01.031173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 09:26:01.031251 ==
4741 09:26:01.031311
4742 09:26:01.031367
4743 09:26:01.034678 TX Vref Scan disable
4744 09:26:01.037554 == TX Byte 0 ==
4745 09:26:01.041169 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4746 09:26:01.044182 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4747 09:26:01.047822 == TX Byte 1 ==
4748 09:26:01.050971 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4749 09:26:01.054536 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4750 09:26:01.054614
4751 09:26:01.054673 [DATLAT]
4752 09:26:01.057452 Freq=600, CH1 RK1
4753 09:26:01.057530
4754 09:26:01.061101 DATLAT Default: 0x9
4755 09:26:01.061177 0, 0xFFFF, sum = 0
4756 09:26:01.064231 1, 0xFFFF, sum = 0
4757 09:26:01.064309 2, 0xFFFF, sum = 0
4758 09:26:01.067935 3, 0xFFFF, sum = 0
4759 09:26:01.068013 4, 0xFFFF, sum = 0
4760 09:26:01.070887 5, 0xFFFF, sum = 0
4761 09:26:01.070965 6, 0xFFFF, sum = 0
4762 09:26:01.074075 7, 0xFFFF, sum = 0
4763 09:26:01.074152 8, 0x0, sum = 1
4764 09:26:01.077723 9, 0x0, sum = 2
4765 09:26:01.077800 10, 0x0, sum = 3
4766 09:26:01.080962 11, 0x0, sum = 4
4767 09:26:01.081039 best_step = 9
4768 09:26:01.081098
4769 09:26:01.081152 ==
4770 09:26:01.084099 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 09:26:01.087684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 09:26:01.087761 ==
4773 09:26:01.090899 RX Vref Scan: 0
4774 09:26:01.090975
4775 09:26:01.094033 RX Vref 0 -> 0, step: 1
4776 09:26:01.094109
4777 09:26:01.094168 RX Delay -195 -> 252, step: 8
4778 09:26:01.102188 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4779 09:26:01.105332 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4780 09:26:01.108467 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4781 09:26:01.112253 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4782 09:26:01.119026 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4783 09:26:01.121932 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4784 09:26:01.125492 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4785 09:26:01.128441 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4786 09:26:01.132186 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4787 09:26:01.138479 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4788 09:26:01.141561 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4789 09:26:01.145154 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4790 09:26:01.148275 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4791 09:26:01.155340 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4792 09:26:01.158423 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4793 09:26:01.161470 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4794 09:26:01.161547 ==
4795 09:26:01.165114 Dram Type= 6, Freq= 0, CH_1, rank 1
4796 09:26:01.171565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4797 09:26:01.171644 ==
4798 09:26:01.171704 DQS Delay:
4799 09:26:01.171759 DQS0 = 0, DQS1 = 0
4800 09:26:01.174592 DQM Delay:
4801 09:26:01.174669 DQM0 = 36, DQM1 = 30
4802 09:26:01.178395 DQ Delay:
4803 09:26:01.181469 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4804 09:26:01.184823 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =36
4805 09:26:01.184900 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =20
4806 09:26:01.190982 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4807 09:26:01.191059
4808 09:26:01.191118
4809 09:26:01.197783 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4810 09:26:01.200912 CH1 RK1: MR19=808, MR18=3D5C
4811 09:26:01.208068 CH1_RK1: MR19=0x808, MR18=0x3D5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4812 09:26:01.211138 [RxdqsGatingPostProcess] freq 600
4813 09:26:01.214324 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4814 09:26:01.217495 Pre-setting of DQS Precalculation
4815 09:26:01.224192 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4816 09:26:01.231121 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4817 09:26:01.237199 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4818 09:26:01.237277
4819 09:26:01.237336
4820 09:26:01.240939 [Calibration Summary] 1200 Mbps
4821 09:26:01.241022 CH 0, Rank 0
4822 09:26:01.244123 SW Impedance : PASS
4823 09:26:01.247801 DUTY Scan : NO K
4824 09:26:01.247877 ZQ Calibration : PASS
4825 09:26:01.250862 Jitter Meter : NO K
4826 09:26:01.254014 CBT Training : PASS
4827 09:26:01.254091 Write leveling : PASS
4828 09:26:01.257801 RX DQS gating : PASS
4829 09:26:01.260735 RX DQ/DQS(RDDQC) : PASS
4830 09:26:01.260812 TX DQ/DQS : PASS
4831 09:26:01.264206 RX DATLAT : PASS
4832 09:26:01.267066 RX DQ/DQS(Engine): PASS
4833 09:26:01.267146 TX OE : NO K
4834 09:26:01.267207 All Pass.
4835 09:26:01.270740
4836 09:26:01.270817 CH 0, Rank 1
4837 09:26:01.274245 SW Impedance : PASS
4838 09:26:01.274321 DUTY Scan : NO K
4839 09:26:01.277135 ZQ Calibration : PASS
4840 09:26:01.277212 Jitter Meter : NO K
4841 09:26:01.280536 CBT Training : PASS
4842 09:26:01.284214 Write leveling : PASS
4843 09:26:01.284290 RX DQS gating : PASS
4844 09:26:01.287351 RX DQ/DQS(RDDQC) : PASS
4845 09:26:01.290443 TX DQ/DQS : PASS
4846 09:26:01.290520 RX DATLAT : PASS
4847 09:26:01.294257 RX DQ/DQS(Engine): PASS
4848 09:26:01.297496 TX OE : NO K
4849 09:26:01.297573 All Pass.
4850 09:26:01.297632
4851 09:26:01.297687 CH 1, Rank 0
4852 09:26:01.300590 SW Impedance : PASS
4853 09:26:01.303818 DUTY Scan : NO K
4854 09:26:01.303895 ZQ Calibration : PASS
4855 09:26:01.307423 Jitter Meter : NO K
4856 09:26:01.310442 CBT Training : PASS
4857 09:26:01.310519 Write leveling : PASS
4858 09:26:01.314046 RX DQS gating : PASS
4859 09:26:01.317184 RX DQ/DQS(RDDQC) : PASS
4860 09:26:01.317260 TX DQ/DQS : PASS
4861 09:26:01.320274 RX DATLAT : PASS
4862 09:26:01.324014 RX DQ/DQS(Engine): PASS
4863 09:26:01.324114 TX OE : NO K
4864 09:26:01.324178 All Pass.
4865 09:26:01.327001
4866 09:26:01.327077 CH 1, Rank 1
4867 09:26:01.330168 SW Impedance : PASS
4868 09:26:01.330245 DUTY Scan : NO K
4869 09:26:01.333480 ZQ Calibration : PASS
4870 09:26:01.333556 Jitter Meter : NO K
4871 09:26:01.337071 CBT Training : PASS
4872 09:26:01.340115 Write leveling : PASS
4873 09:26:01.340191 RX DQS gating : PASS
4874 09:26:01.343867 RX DQ/DQS(RDDQC) : PASS
4875 09:26:01.346858 TX DQ/DQS : PASS
4876 09:26:01.346935 RX DATLAT : PASS
4877 09:26:01.349992 RX DQ/DQS(Engine): PASS
4878 09:26:01.353693 TX OE : NO K
4879 09:26:01.353770 All Pass.
4880 09:26:01.353829
4881 09:26:01.356890 DramC Write-DBI off
4882 09:26:01.356968 PER_BANK_REFRESH: Hybrid Mode
4883 09:26:01.360057 TX_TRACKING: ON
4884 09:26:01.366911 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4885 09:26:01.373475 [FAST_K] Save calibration result to emmc
4886 09:26:01.376934 dramc_set_vcore_voltage set vcore to 662500
4887 09:26:01.377011 Read voltage for 933, 3
4888 09:26:01.380013 Vio18 = 0
4889 09:26:01.380089 Vcore = 662500
4890 09:26:01.380148 Vdram = 0
4891 09:26:01.383715 Vddq = 0
4892 09:26:01.383792 Vmddr = 0
4893 09:26:01.386630 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4894 09:26:01.393421 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4895 09:26:01.396932 MEM_TYPE=3, freq_sel=17
4896 09:26:01.400085 sv_algorithm_assistance_LP4_1600
4897 09:26:01.403359 ============ PULL DRAM RESETB DOWN ============
4898 09:26:01.406422 ========== PULL DRAM RESETB DOWN end =========
4899 09:26:01.413316 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4900 09:26:01.416300 ===================================
4901 09:26:01.416378 LPDDR4 DRAM CONFIGURATION
4902 09:26:01.419794 ===================================
4903 09:26:01.422965 EX_ROW_EN[0] = 0x0
4904 09:26:01.423043 EX_ROW_EN[1] = 0x0
4905 09:26:01.426132 LP4Y_EN = 0x0
4906 09:26:01.426209 WORK_FSP = 0x0
4907 09:26:01.429850 WL = 0x3
4908 09:26:01.429928 RL = 0x3
4909 09:26:01.432940 BL = 0x2
4910 09:26:01.436121 RPST = 0x0
4911 09:26:01.436198 RD_PRE = 0x0
4912 09:26:01.439872 WR_PRE = 0x1
4913 09:26:01.439950 WR_PST = 0x0
4914 09:26:01.442961 DBI_WR = 0x0
4915 09:26:01.443039 DBI_RD = 0x0
4916 09:26:01.445989 OTF = 0x1
4917 09:26:01.449614 ===================================
4918 09:26:01.452712 ===================================
4919 09:26:01.452790 ANA top config
4920 09:26:01.456307 ===================================
4921 09:26:01.459935 DLL_ASYNC_EN = 0
4922 09:26:01.463053 ALL_SLAVE_EN = 1
4923 09:26:01.463130 NEW_RANK_MODE = 1
4924 09:26:01.466188 DLL_IDLE_MODE = 1
4925 09:26:01.469348 LP45_APHY_COMB_EN = 1
4926 09:26:01.473185 TX_ODT_DIS = 1
4927 09:26:01.473263 NEW_8X_MODE = 1
4928 09:26:01.476324 ===================================
4929 09:26:01.479496 ===================================
4930 09:26:01.482738 data_rate = 1866
4931 09:26:01.485820 CKR = 1
4932 09:26:01.489451 DQ_P2S_RATIO = 8
4933 09:26:01.492996 ===================================
4934 09:26:01.495892 CA_P2S_RATIO = 8
4935 09:26:01.499208 DQ_CA_OPEN = 0
4936 09:26:01.503053 DQ_SEMI_OPEN = 0
4937 09:26:01.503131 CA_SEMI_OPEN = 0
4938 09:26:01.505749 CA_FULL_RATE = 0
4939 09:26:01.508983 DQ_CKDIV4_EN = 1
4940 09:26:01.512404 CA_CKDIV4_EN = 1
4941 09:26:01.516039 CA_PREDIV_EN = 0
4942 09:26:01.519141 PH8_DLY = 0
4943 09:26:01.519218 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4944 09:26:01.522252 DQ_AAMCK_DIV = 4
4945 09:26:01.525749 CA_AAMCK_DIV = 4
4946 09:26:01.529464 CA_ADMCK_DIV = 4
4947 09:26:01.532422 DQ_TRACK_CA_EN = 0
4948 09:26:01.536134 CA_PICK = 933
4949 09:26:01.536212 CA_MCKIO = 933
4950 09:26:01.539296 MCKIO_SEMI = 0
4951 09:26:01.542443 PLL_FREQ = 3732
4952 09:26:01.545593 DQ_UI_PI_RATIO = 32
4953 09:26:01.549360 CA_UI_PI_RATIO = 0
4954 09:26:01.552397 ===================================
4955 09:26:01.555945 ===================================
4956 09:26:01.558948 memory_type:LPDDR4
4957 09:26:01.559026 GP_NUM : 10
4958 09:26:01.562631 SRAM_EN : 1
4959 09:26:01.562709 MD32_EN : 0
4960 09:26:01.565768 ===================================
4961 09:26:01.568946 [ANA_INIT] >>>>>>>>>>>>>>
4962 09:26:01.572629 <<<<<< [CONFIGURE PHASE]: ANA_TX
4963 09:26:01.575870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4964 09:26:01.579009 ===================================
4965 09:26:01.582120 data_rate = 1866,PCW = 0X8f00
4966 09:26:01.585876 ===================================
4967 09:26:01.589010 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4968 09:26:01.595351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4969 09:26:01.599193 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4970 09:26:01.605272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4971 09:26:01.609095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4972 09:26:01.612033 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4973 09:26:01.612111 [ANA_INIT] flow start
4974 09:26:01.615485 [ANA_INIT] PLL >>>>>>>>
4975 09:26:01.618801 [ANA_INIT] PLL <<<<<<<<
4976 09:26:01.618879 [ANA_INIT] MIDPI >>>>>>>>
4977 09:26:01.621897 [ANA_INIT] MIDPI <<<<<<<<
4978 09:26:01.625415 [ANA_INIT] DLL >>>>>>>>
4979 09:26:01.625492 [ANA_INIT] flow end
4980 09:26:01.632027 ============ LP4 DIFF to SE enter ============
4981 09:26:01.635069 ============ LP4 DIFF to SE exit ============
4982 09:26:01.638316 [ANA_INIT] <<<<<<<<<<<<<
4983 09:26:01.641681 [Flow] Enable top DCM control >>>>>
4984 09:26:01.645036 [Flow] Enable top DCM control <<<<<
4985 09:26:01.645136 Enable DLL master slave shuffle
4986 09:26:01.652141 ==============================================================
4987 09:26:01.655299 Gating Mode config
4988 09:26:01.658298 ==============================================================
4989 09:26:01.662014 Config description:
4990 09:26:01.671746 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4991 09:26:01.678727 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4992 09:26:01.681846 SELPH_MODE 0: By rank 1: By Phase
4993 09:26:01.688135 ==============================================================
4994 09:26:01.691971 GAT_TRACK_EN = 1
4995 09:26:01.695029 RX_GATING_MODE = 2
4996 09:26:01.698309 RX_GATING_TRACK_MODE = 2
4997 09:26:01.698388 SELPH_MODE = 1
4998 09:26:01.701415 PICG_EARLY_EN = 1
4999 09:26:01.705322 VALID_LAT_VALUE = 1
5000 09:26:01.711526 ==============================================================
5001 09:26:01.714644 Enter into Gating configuration >>>>
5002 09:26:01.718365 Exit from Gating configuration <<<<
5003 09:26:01.721631 Enter into DVFS_PRE_config >>>>>
5004 09:26:01.731366 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5005 09:26:01.734974 Exit from DVFS_PRE_config <<<<<
5006 09:26:01.738213 Enter into PICG configuration >>>>
5007 09:26:01.741310 Exit from PICG configuration <<<<
5008 09:26:01.744886 [RX_INPUT] configuration >>>>>
5009 09:26:01.748346 [RX_INPUT] configuration <<<<<
5010 09:26:01.751604 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5011 09:26:01.758154 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5012 09:26:01.764424 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5013 09:26:01.771167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5014 09:26:01.777752 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5015 09:26:01.781013 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5016 09:26:01.787673 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5017 09:26:01.791378 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5018 09:26:01.794543 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5019 09:26:01.797759 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5020 09:26:01.804540 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5021 09:26:01.807751 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5022 09:26:01.810879 ===================================
5023 09:26:01.814040 LPDDR4 DRAM CONFIGURATION
5024 09:26:01.817788 ===================================
5025 09:26:01.817866 EX_ROW_EN[0] = 0x0
5026 09:26:01.820997 EX_ROW_EN[1] = 0x0
5027 09:26:01.821074 LP4Y_EN = 0x0
5028 09:26:01.824095 WORK_FSP = 0x0
5029 09:26:01.824172 WL = 0x3
5030 09:26:01.827291 RL = 0x3
5031 09:26:01.827368 BL = 0x2
5032 09:26:01.831015 RPST = 0x0
5033 09:26:01.831116 RD_PRE = 0x0
5034 09:26:01.834118 WR_PRE = 0x1
5035 09:26:01.837299 WR_PST = 0x0
5036 09:26:01.837378 DBI_WR = 0x0
5037 09:26:01.840990 DBI_RD = 0x0
5038 09:26:01.841068 OTF = 0x1
5039 09:26:01.844216 ===================================
5040 09:26:01.847294 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5041 09:26:01.851107 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5042 09:26:01.857287 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5043 09:26:01.860465 ===================================
5044 09:26:01.864134 LPDDR4 DRAM CONFIGURATION
5045 09:26:01.867273 ===================================
5046 09:26:01.867351 EX_ROW_EN[0] = 0x10
5047 09:26:01.870786 EX_ROW_EN[1] = 0x0
5048 09:26:01.870863 LP4Y_EN = 0x0
5049 09:26:01.873709 WORK_FSP = 0x0
5050 09:26:01.873786 WL = 0x3
5051 09:26:01.876971 RL = 0x3
5052 09:26:01.877049 BL = 0x2
5053 09:26:01.880363 RPST = 0x0
5054 09:26:01.880440 RD_PRE = 0x0
5055 09:26:01.883619 WR_PRE = 0x1
5056 09:26:01.883698 WR_PST = 0x0
5057 09:26:01.887227 DBI_WR = 0x0
5058 09:26:01.890319 DBI_RD = 0x0
5059 09:26:01.890397 OTF = 0x1
5060 09:26:01.893435 ===================================
5061 09:26:01.900122 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5062 09:26:01.903655 nWR fixed to 30
5063 09:26:01.907136 [ModeRegInit_LP4] CH0 RK0
5064 09:26:01.907213 [ModeRegInit_LP4] CH0 RK1
5065 09:26:01.910478 [ModeRegInit_LP4] CH1 RK0
5066 09:26:01.913685 [ModeRegInit_LP4] CH1 RK1
5067 09:26:01.913761 match AC timing 9
5068 09:26:01.920610 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5069 09:26:01.923774 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5070 09:26:01.926918 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5071 09:26:01.934043 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5072 09:26:01.937104 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5073 09:26:01.937186 ==
5074 09:26:01.940692 Dram Type= 6, Freq= 0, CH_0, rank 0
5075 09:26:01.943934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5076 09:26:01.944023 ==
5077 09:26:01.950181 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5078 09:26:01.957101 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5079 09:26:01.960148 [CA 0] Center 38 (8~69) winsize 62
5080 09:26:01.963951 [CA 1] Center 38 (8~69) winsize 62
5081 09:26:01.967188 [CA 2] Center 35 (5~66) winsize 62
5082 09:26:01.970231 [CA 3] Center 35 (5~66) winsize 62
5083 09:26:01.973474 [CA 4] Center 34 (4~65) winsize 62
5084 09:26:01.976688 [CA 5] Center 33 (3~64) winsize 62
5085 09:26:01.976803
5086 09:26:01.980295 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5087 09:26:01.980410
5088 09:26:01.983485 [CATrainingPosCal] consider 1 rank data
5089 09:26:01.986761 u2DelayCellTimex100 = 270/100 ps
5090 09:26:01.990311 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5091 09:26:01.993184 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5092 09:26:01.996968 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5093 09:26:02.000230 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5094 09:26:02.006825 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5095 09:26:02.009703 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5096 09:26:02.009798
5097 09:26:02.013086 CA PerBit enable=1, Macro0, CA PI delay=33
5098 09:26:02.013191
5099 09:26:02.016573 [CBTSetCACLKResult] CA Dly = 33
5100 09:26:02.016695 CS Dly: 7 (0~38)
5101 09:26:02.016790 ==
5102 09:26:02.019691 Dram Type= 6, Freq= 0, CH_0, rank 1
5103 09:26:02.023302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 09:26:02.026386 ==
5105 09:26:02.029979 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5106 09:26:02.036665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5107 09:26:02.040014 [CA 0] Center 38 (8~69) winsize 62
5108 09:26:02.043150 [CA 1] Center 38 (8~69) winsize 62
5109 09:26:02.046888 [CA 2] Center 35 (5~66) winsize 62
5110 09:26:02.049857 [CA 3] Center 35 (5~66) winsize 62
5111 09:26:02.053144 [CA 4] Center 34 (4~65) winsize 62
5112 09:26:02.056925 [CA 5] Center 34 (4~64) winsize 61
5113 09:26:02.057322
5114 09:26:02.060129 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5115 09:26:02.060521
5116 09:26:02.063341 [CATrainingPosCal] consider 2 rank data
5117 09:26:02.066510 u2DelayCellTimex100 = 270/100 ps
5118 09:26:02.069741 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5119 09:26:02.073620 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5120 09:26:02.076700 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5121 09:26:02.083407 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5122 09:26:02.086491 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5123 09:26:02.089647 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5124 09:26:02.090040
5125 09:26:02.093357 CA PerBit enable=1, Macro0, CA PI delay=34
5126 09:26:02.093753
5127 09:26:02.096231 [CBTSetCACLKResult] CA Dly = 34
5128 09:26:02.096625 CS Dly: 7 (0~38)
5129 09:26:02.096973
5130 09:26:02.099904 ----->DramcWriteLeveling(PI) begin...
5131 09:26:02.100304 ==
5132 09:26:02.103078 Dram Type= 6, Freq= 0, CH_0, rank 0
5133 09:26:02.109780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5134 09:26:02.110182 ==
5135 09:26:02.113299 Write leveling (Byte 0): 31 => 31
5136 09:26:02.116275 Write leveling (Byte 1): 30 => 30
5137 09:26:02.116689 DramcWriteLeveling(PI) end<-----
5138 09:26:02.117000
5139 09:26:02.120099 ==
5140 09:26:02.123273 Dram Type= 6, Freq= 0, CH_0, rank 0
5141 09:26:02.126328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5142 09:26:02.126742 ==
5143 09:26:02.129538 [Gating] SW mode calibration
5144 09:26:02.136426 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5145 09:26:02.139385 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5146 09:26:02.146487 0 14 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5147 09:26:02.149622 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5148 09:26:02.152695 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 09:26:02.159614 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 09:26:02.162676 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 09:26:02.166147 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 09:26:02.172534 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 09:26:02.176255 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5154 09:26:02.179403 0 15 0 | B1->B0 | 3434 2c2c | 0 1 | (0 1) (0 0)
5155 09:26:02.186204 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5156 09:26:02.189204 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 09:26:02.192930 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 09:26:02.199394 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 09:26:02.202394 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 09:26:02.205959 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 09:26:02.212131 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 09:26:02.216042 1 0 0 | B1->B0 | 2d2d 3838 | 0 0 | (1 1) (0 0)
5163 09:26:02.219149 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
5164 09:26:02.225918 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 09:26:02.229071 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 09:26:02.232275 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 09:26:02.238887 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 09:26:02.242009 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 09:26:02.245822 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5170 09:26:02.252117 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5171 09:26:02.255269 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5172 09:26:02.259166 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 09:26:02.265330 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 09:26:02.268559 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 09:26:02.271807 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 09:26:02.278692 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 09:26:02.281692 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 09:26:02.285146 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 09:26:02.291872 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 09:26:02.295071 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 09:26:02.298457 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 09:26:02.304965 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 09:26:02.308519 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 09:26:02.311605 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 09:26:02.315290 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5186 09:26:02.322074 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5187 09:26:02.325362 Total UI for P1: 0, mck2ui 16
5188 09:26:02.328236 best dqsien dly found for B0: ( 1, 2, 28)
5189 09:26:02.331928 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 09:26:02.335061 Total UI for P1: 0, mck2ui 16
5191 09:26:02.338223 best dqsien dly found for B1: ( 1, 3, 2)
5192 09:26:02.341494 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5193 09:26:02.345286 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5194 09:26:02.345687
5195 09:26:02.348385 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5196 09:26:02.351643 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5197 09:26:02.354795 [Gating] SW calibration Done
5198 09:26:02.355196 ==
5199 09:26:02.357973 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 09:26:02.364968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 09:26:02.365371 ==
5202 09:26:02.365681 RX Vref Scan: 0
5203 09:26:02.365971
5204 09:26:02.368197 RX Vref 0 -> 0, step: 1
5205 09:26:02.368592
5206 09:26:02.371287 RX Delay -80 -> 252, step: 8
5207 09:26:02.374517 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5208 09:26:02.377648 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5209 09:26:02.381245 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5210 09:26:02.384354 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5211 09:26:02.391163 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5212 09:26:02.394800 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5213 09:26:02.397695 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5214 09:26:02.401026 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5215 09:26:02.404485 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5216 09:26:02.407724 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5217 09:26:02.414494 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5218 09:26:02.417915 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5219 09:26:02.421313 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5220 09:26:02.424699 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5221 09:26:02.427689 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5222 09:26:02.434311 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5223 09:26:02.434895 ==
5224 09:26:02.437512 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 09:26:02.440862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 09:26:02.441261 ==
5227 09:26:02.441593 DQS Delay:
5228 09:26:02.444480 DQS0 = 0, DQS1 = 0
5229 09:26:02.444922 DQM Delay:
5230 09:26:02.447406 DQM0 = 93, DQM1 = 83
5231 09:26:02.447836 DQ Delay:
5232 09:26:02.450816 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5233 09:26:02.453959 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =107
5234 09:26:02.457683 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5235 09:26:02.460760 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5236 09:26:02.461281
5237 09:26:02.461801
5238 09:26:02.462266 ==
5239 09:26:02.463944 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 09:26:02.467739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 09:26:02.470887 ==
5242 09:26:02.471444
5243 09:26:02.471766
5244 09:26:02.472068 TX Vref Scan disable
5245 09:26:02.473982 == TX Byte 0 ==
5246 09:26:02.477011 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5247 09:26:02.480741 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5248 09:26:02.483901 == TX Byte 1 ==
5249 09:26:02.487574 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5250 09:26:02.490705 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5251 09:26:02.493877 ==
5252 09:26:02.497142 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 09:26:02.500353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 09:26:02.500817 ==
5255 09:26:02.501130
5256 09:26:02.501427
5257 09:26:02.503399 TX Vref Scan disable
5258 09:26:02.503808 == TX Byte 0 ==
5259 09:26:02.510197 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5260 09:26:02.513359 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5261 09:26:02.513750 == TX Byte 1 ==
5262 09:26:02.520214 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5263 09:26:02.523222 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5264 09:26:02.523649
5265 09:26:02.523972 [DATLAT]
5266 09:26:02.526816 Freq=933, CH0 RK0
5267 09:26:02.527368
5268 09:26:02.527811 DATLAT Default: 0xd
5269 09:26:02.530384 0, 0xFFFF, sum = 0
5270 09:26:02.530798 1, 0xFFFF, sum = 0
5271 09:26:02.533795 2, 0xFFFF, sum = 0
5272 09:26:02.534246 3, 0xFFFF, sum = 0
5273 09:26:02.536549 4, 0xFFFF, sum = 0
5274 09:26:02.540301 5, 0xFFFF, sum = 0
5275 09:26:02.540728 6, 0xFFFF, sum = 0
5276 09:26:02.543603 7, 0xFFFF, sum = 0
5277 09:26:02.544001 8, 0xFFFF, sum = 0
5278 09:26:02.546719 9, 0xFFFF, sum = 0
5279 09:26:02.547119 10, 0x0, sum = 1
5280 09:26:02.550006 11, 0x0, sum = 2
5281 09:26:02.550436 12, 0x0, sum = 3
5282 09:26:02.550754 13, 0x0, sum = 4
5283 09:26:02.553264 best_step = 11
5284 09:26:02.553674
5285 09:26:02.553984 ==
5286 09:26:02.556568 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 09:26:02.559902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 09:26:02.560345 ==
5289 09:26:02.563083 RX Vref Scan: 1
5290 09:26:02.563504
5291 09:26:02.566723 RX Vref 0 -> 0, step: 1
5292 09:26:02.567278
5293 09:26:02.567636 RX Delay -69 -> 252, step: 4
5294 09:26:02.567930
5295 09:26:02.570202 Set Vref, RX VrefLevel [Byte0]: 62
5296 09:26:02.573138 [Byte1]: 47
5297 09:26:02.577571
5298 09:26:02.577964 Final RX Vref Byte 0 = 62 to rank0
5299 09:26:02.581482 Final RX Vref Byte 1 = 47 to rank0
5300 09:26:02.584547 Final RX Vref Byte 0 = 62 to rank1
5301 09:26:02.587660 Final RX Vref Byte 1 = 47 to rank1==
5302 09:26:02.591246 Dram Type= 6, Freq= 0, CH_0, rank 0
5303 09:26:02.597471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 09:26:02.597867 ==
5305 09:26:02.598177 DQS Delay:
5306 09:26:02.600630 DQS0 = 0, DQS1 = 0
5307 09:26:02.601085 DQM Delay:
5308 09:26:02.601429 DQM0 = 95, DQM1 = 83
5309 09:26:02.604396 DQ Delay:
5310 09:26:02.607512 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5311 09:26:02.611147 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =108
5312 09:26:02.614164 DQ8 =74, DQ9 =68, DQ10 =84, DQ11 =76
5313 09:26:02.617471 DQ12 =86, DQ13 =86, DQ14 =98, DQ15 =92
5314 09:26:02.617883
5315 09:26:02.618207
5316 09:26:02.624221 [DQSOSCAuto] RK0, (LSB)MR18= 0x1312, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5317 09:26:02.627220 CH0 RK0: MR19=505, MR18=1312
5318 09:26:02.634145 CH0_RK0: MR19=0x505, MR18=0x1312, DQSOSC=415, MR23=63, INC=62, DEC=41
5319 09:26:02.634572
5320 09:26:02.637225 ----->DramcWriteLeveling(PI) begin...
5321 09:26:02.637644 ==
5322 09:26:02.640924 Dram Type= 6, Freq= 0, CH_0, rank 1
5323 09:26:02.643803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 09:26:02.644205 ==
5325 09:26:02.647235 Write leveling (Byte 0): 31 => 31
5326 09:26:02.650347 Write leveling (Byte 1): 29 => 29
5327 09:26:02.653869 DramcWriteLeveling(PI) end<-----
5328 09:26:02.654455
5329 09:26:02.654869 ==
5330 09:26:02.656891 Dram Type= 6, Freq= 0, CH_0, rank 1
5331 09:26:02.660489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5332 09:26:02.663668 ==
5333 09:26:02.664092 [Gating] SW mode calibration
5334 09:26:02.670482 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5335 09:26:02.676764 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5336 09:26:02.680198 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5337 09:26:02.686766 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 09:26:02.690331 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 09:26:02.693610 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 09:26:02.700367 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 09:26:02.703580 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 09:26:02.706595 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 09:26:02.713535 0 14 28 | B1->B0 | 3434 2929 | 0 0 | (0 0) (0 1)
5344 09:26:02.716710 0 15 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
5345 09:26:02.719914 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 09:26:02.726259 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 09:26:02.730203 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 09:26:02.733360 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 09:26:02.740086 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 09:26:02.743352 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 09:26:02.746530 0 15 28 | B1->B0 | 2626 3939 | 0 1 | (0 0) (0 0)
5352 09:26:02.753153 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5353 09:26:02.756278 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 09:26:02.759805 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 09:26:02.766425 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 09:26:02.770100 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 09:26:02.773272 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 09:26:02.779527 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 09:26:02.783258 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5360 09:26:02.786509 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5361 09:26:02.789478 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5362 09:26:02.796292 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 09:26:02.799862 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 09:26:02.802724 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 09:26:02.809569 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 09:26:02.812922 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 09:26:02.816325 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 09:26:02.823078 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 09:26:02.826321 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 09:26:02.829495 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 09:26:02.836315 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 09:26:02.839559 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 09:26:02.842671 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 09:26:02.849643 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5375 09:26:02.852809 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5376 09:26:02.855708 Total UI for P1: 0, mck2ui 16
5377 09:26:02.859254 best dqsien dly found for B0: ( 1, 2, 24)
5378 09:26:02.862930 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5379 09:26:02.869263 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 09:26:02.869765 Total UI for P1: 0, mck2ui 16
5381 09:26:02.875743 best dqsien dly found for B1: ( 1, 3, 0)
5382 09:26:02.879547 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5383 09:26:02.882634 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5384 09:26:02.883168
5385 09:26:02.885629 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5386 09:26:02.889364 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5387 09:26:02.892729 [Gating] SW calibration Done
5388 09:26:02.893232 ==
5389 09:26:02.895712 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 09:26:02.898854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 09:26:02.899238 ==
5392 09:26:02.902554 RX Vref Scan: 0
5393 09:26:02.902998
5394 09:26:02.903414 RX Vref 0 -> 0, step: 1
5395 09:26:02.903795
5396 09:26:02.905722 RX Delay -80 -> 252, step: 8
5397 09:26:02.909256 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5398 09:26:02.915902 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5399 09:26:02.918837 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5400 09:26:02.922368 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5401 09:26:02.925816 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5402 09:26:02.929027 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5403 09:26:02.932748 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5404 09:26:02.938756 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5405 09:26:02.942418 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5406 09:26:02.945654 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5407 09:26:02.948715 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5408 09:26:02.952519 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5409 09:26:02.958783 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5410 09:26:02.962442 iDelay=208, Bit 13, Center 87 (-8 ~ 183) 192
5411 09:26:02.965758 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5412 09:26:02.968747 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5413 09:26:02.969152 ==
5414 09:26:02.971921 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 09:26:02.975580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 09:26:02.978438 ==
5417 09:26:02.978835 DQS Delay:
5418 09:26:02.979145 DQS0 = 0, DQS1 = 0
5419 09:26:02.981980 DQM Delay:
5420 09:26:02.982376 DQM0 = 92, DQM1 = 81
5421 09:26:02.985241 DQ Delay:
5422 09:26:02.985641 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87
5423 09:26:02.988856 DQ4 =91, DQ5 =75, DQ6 =107, DQ7 =107
5424 09:26:02.991851 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =71
5425 09:26:02.995667 DQ12 =87, DQ13 =87, DQ14 =95, DQ15 =91
5426 09:26:02.998328
5427 09:26:02.998405
5428 09:26:02.998465 ==
5429 09:26:03.001506 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 09:26:03.004770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 09:26:03.004849 ==
5432 09:26:03.004909
5433 09:26:03.004963
5434 09:26:03.008562 TX Vref Scan disable
5435 09:26:03.008639 == TX Byte 0 ==
5436 09:26:03.015208 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5437 09:26:03.018255 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5438 09:26:03.018332 == TX Byte 1 ==
5439 09:26:03.025204 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5440 09:26:03.028365 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5441 09:26:03.028442 ==
5442 09:26:03.031512 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 09:26:03.034578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 09:26:03.034656 ==
5445 09:26:03.034717
5446 09:26:03.034771
5447 09:26:03.037847 TX Vref Scan disable
5448 09:26:03.041177 == TX Byte 0 ==
5449 09:26:03.044609 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5450 09:26:03.047954 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5451 09:26:03.051657 == TX Byte 1 ==
5452 09:26:03.055017 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5453 09:26:03.058036 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5454 09:26:03.058113
5455 09:26:03.061413 [DATLAT]
5456 09:26:03.061490 Freq=933, CH0 RK1
5457 09:26:03.061551
5458 09:26:03.064497 DATLAT Default: 0xb
5459 09:26:03.064574 0, 0xFFFF, sum = 0
5460 09:26:03.068059 1, 0xFFFF, sum = 0
5461 09:26:03.068139 2, 0xFFFF, sum = 0
5462 09:26:03.071557 3, 0xFFFF, sum = 0
5463 09:26:03.071635 4, 0xFFFF, sum = 0
5464 09:26:03.074672 5, 0xFFFF, sum = 0
5465 09:26:03.074751 6, 0xFFFF, sum = 0
5466 09:26:03.077872 7, 0xFFFF, sum = 0
5467 09:26:03.077951 8, 0xFFFF, sum = 0
5468 09:26:03.081575 9, 0xFFFF, sum = 0
5469 09:26:03.081654 10, 0x0, sum = 1
5470 09:26:03.084544 11, 0x0, sum = 2
5471 09:26:03.084627 12, 0x0, sum = 3
5472 09:26:03.088142 13, 0x0, sum = 4
5473 09:26:03.088220 best_step = 11
5474 09:26:03.088281
5475 09:26:03.088336 ==
5476 09:26:03.091450 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 09:26:03.097799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 09:26:03.097877 ==
5479 09:26:03.097938 RX Vref Scan: 0
5480 09:26:03.097993
5481 09:26:03.100851 RX Vref 0 -> 0, step: 1
5482 09:26:03.100929
5483 09:26:03.104438 RX Delay -77 -> 252, step: 4
5484 09:26:03.107614 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5485 09:26:03.114497 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5486 09:26:03.117534 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5487 09:26:03.121222 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5488 09:26:03.124272 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5489 09:26:03.127291 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5490 09:26:03.131085 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5491 09:26:03.137339 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5492 09:26:03.140424 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5493 09:26:03.144310 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5494 09:26:03.147288 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5495 09:26:03.150697 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5496 09:26:03.157346 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5497 09:26:03.160632 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5498 09:26:03.163688 iDelay=199, Bit 14, Center 96 (11 ~ 182) 172
5499 09:26:03.167566 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5500 09:26:03.167644 ==
5501 09:26:03.170731 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 09:26:03.177432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 09:26:03.177512 ==
5504 09:26:03.177572 DQS Delay:
5505 09:26:03.177628 DQS0 = 0, DQS1 = 0
5506 09:26:03.180402 DQM Delay:
5507 09:26:03.180479 DQM0 = 92, DQM1 = 84
5508 09:26:03.183510 DQ Delay:
5509 09:26:03.187244 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5510 09:26:03.190290 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
5511 09:26:03.193783 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =76
5512 09:26:03.196802 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5513 09:26:03.196880
5514 09:26:03.196941
5515 09:26:03.203307 [DQSOSCAuto] RK1, (LSB)MR18= 0x3314, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
5516 09:26:03.206884 CH0 RK1: MR19=505, MR18=3314
5517 09:26:03.213130 CH0_RK1: MR19=0x505, MR18=0x3314, DQSOSC=405, MR23=63, INC=66, DEC=44
5518 09:26:03.216961 [RxdqsGatingPostProcess] freq 933
5519 09:26:03.220031 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5520 09:26:03.223205 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 09:26:03.226923 best DQS1 dly(2T, 0.5T) = (0, 11)
5522 09:26:03.229990 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 09:26:03.233521 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5524 09:26:03.236819 best DQS0 dly(2T, 0.5T) = (0, 10)
5525 09:26:03.239883 best DQS1 dly(2T, 0.5T) = (0, 11)
5526 09:26:03.243109 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5527 09:26:03.246837 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5528 09:26:03.249963 Pre-setting of DQS Precalculation
5529 09:26:03.253113 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5530 09:26:03.253214 ==
5531 09:26:03.256798 Dram Type= 6, Freq= 0, CH_1, rank 0
5532 09:26:03.262766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 09:26:03.262849 ==
5534 09:26:03.266186 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 09:26:03.273091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5536 09:26:03.276786 [CA 0] Center 37 (7~67) winsize 61
5537 09:26:03.279816 [CA 1] Center 37 (7~67) winsize 61
5538 09:26:03.282828 [CA 2] Center 34 (5~64) winsize 60
5539 09:26:03.286385 [CA 3] Center 34 (5~64) winsize 60
5540 09:26:03.289898 [CA 4] Center 34 (5~64) winsize 60
5541 09:26:03.292979 [CA 5] Center 34 (4~64) winsize 61
5542 09:26:03.293063
5543 09:26:03.296053 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5544 09:26:03.296130
5545 09:26:03.299715 [CATrainingPosCal] consider 1 rank data
5546 09:26:03.303115 u2DelayCellTimex100 = 270/100 ps
5547 09:26:03.305986 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5548 09:26:03.313112 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5549 09:26:03.316264 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5550 09:26:03.319422 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5551 09:26:03.322599 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5552 09:26:03.326394 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5553 09:26:03.326472
5554 09:26:03.329567 CA PerBit enable=1, Macro0, CA PI delay=34
5555 09:26:03.329645
5556 09:26:03.332796 [CBTSetCACLKResult] CA Dly = 34
5557 09:26:03.332875 CS Dly: 5 (0~36)
5558 09:26:03.336373 ==
5559 09:26:03.339401 Dram Type= 6, Freq= 0, CH_1, rank 1
5560 09:26:03.343011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 09:26:03.343089 ==
5562 09:26:03.346134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5563 09:26:03.352416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5564 09:26:03.356186 [CA 0] Center 38 (8~68) winsize 61
5565 09:26:03.360015 [CA 1] Center 37 (7~68) winsize 62
5566 09:26:03.362983 [CA 2] Center 35 (5~65) winsize 61
5567 09:26:03.366069 [CA 3] Center 34 (4~64) winsize 61
5568 09:26:03.369331 [CA 4] Center 35 (5~65) winsize 61
5569 09:26:03.373039 [CA 5] Center 34 (4~64) winsize 61
5570 09:26:03.373117
5571 09:26:03.376018 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5572 09:26:03.376095
5573 09:26:03.379546 [CATrainingPosCal] consider 2 rank data
5574 09:26:03.383029 u2DelayCellTimex100 = 270/100 ps
5575 09:26:03.386061 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5576 09:26:03.392958 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5577 09:26:03.396367 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5578 09:26:03.399437 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5579 09:26:03.402530 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5580 09:26:03.406170 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5581 09:26:03.406249
5582 09:26:03.409160 CA PerBit enable=1, Macro0, CA PI delay=34
5583 09:26:03.409238
5584 09:26:03.412581 [CBTSetCACLKResult] CA Dly = 34
5585 09:26:03.412720 CS Dly: 6 (0~38)
5586 09:26:03.412807
5587 09:26:03.419289 ----->DramcWriteLeveling(PI) begin...
5588 09:26:03.419369 ==
5589 09:26:03.422929 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 09:26:03.426073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 09:26:03.426151 ==
5592 09:26:03.429198 Write leveling (Byte 0): 28 => 28
5593 09:26:03.432962 Write leveling (Byte 1): 30 => 30
5594 09:26:03.436132 DramcWriteLeveling(PI) end<-----
5595 09:26:03.436227
5596 09:26:03.436312 ==
5597 09:26:03.439243 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 09:26:03.442344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 09:26:03.442422 ==
5600 09:26:03.445986 [Gating] SW mode calibration
5601 09:26:03.452544 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5602 09:26:03.458847 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5603 09:26:03.462073 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5604 09:26:03.465804 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 09:26:03.471948 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 09:26:03.475820 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 09:26:03.478898 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 09:26:03.485582 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 09:26:03.488770 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 09:26:03.492245 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (1 1) (0 1)
5611 09:26:03.498821 0 15 0 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5612 09:26:03.501780 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 09:26:03.505007 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 09:26:03.512093 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 09:26:03.515047 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 09:26:03.518636 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 09:26:03.524863 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 09:26:03.528349 0 15 28 | B1->B0 | 3333 3636 | 0 0 | (0 0) (0 0)
5619 09:26:03.531453 1 0 0 | B1->B0 | 4242 4343 | 0 0 | (0 0) (0 0)
5620 09:26:03.538282 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 09:26:03.541380 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 09:26:03.545068 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 09:26:03.551331 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 09:26:03.554855 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 09:26:03.557925 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5626 09:26:03.565007 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5627 09:26:03.568163 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5628 09:26:03.571614 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 09:26:03.578011 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 09:26:03.581161 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 09:26:03.584898 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 09:26:03.588006 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 09:26:03.594945 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 09:26:03.597867 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 09:26:03.601460 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 09:26:03.608142 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 09:26:03.611098 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 09:26:03.614501 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 09:26:03.620951 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 09:26:03.624201 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 09:26:03.627632 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 09:26:03.634081 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5643 09:26:03.637754 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 09:26:03.641334 Total UI for P1: 0, mck2ui 16
5645 09:26:03.643908 best dqsien dly found for B0: ( 1, 2, 28)
5646 09:26:03.647644 Total UI for P1: 0, mck2ui 16
5647 09:26:03.650764 best dqsien dly found for B1: ( 1, 2, 28)
5648 09:26:03.653931 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5649 09:26:03.657617 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5650 09:26:03.657696
5651 09:26:03.660716 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5652 09:26:03.664356 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5653 09:26:03.667403 [Gating] SW calibration Done
5654 09:26:03.667481 ==
5655 09:26:03.670655 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 09:26:03.677138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 09:26:03.677218 ==
5658 09:26:03.677279 RX Vref Scan: 0
5659 09:26:03.677335
5660 09:26:03.680887 RX Vref 0 -> 0, step: 1
5661 09:26:03.680965
5662 09:26:03.684001 RX Delay -80 -> 252, step: 8
5663 09:26:03.687170 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5664 09:26:03.690173 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5665 09:26:03.693866 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5666 09:26:03.697065 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5667 09:26:03.703522 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5668 09:26:03.707241 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5669 09:26:03.710247 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5670 09:26:03.713836 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5671 09:26:03.717082 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5672 09:26:03.723337 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5673 09:26:03.726919 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5674 09:26:03.730333 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5675 09:26:03.734164 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5676 09:26:03.736923 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5677 09:26:03.743577 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5678 09:26:03.747043 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5679 09:26:03.747189 ==
5680 09:26:03.750469 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 09:26:03.753930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 09:26:03.754008 ==
5683 09:26:03.754068 DQS Delay:
5684 09:26:03.756972 DQS0 = 0, DQS1 = 0
5685 09:26:03.757069 DQM Delay:
5686 09:26:03.760164 DQM0 = 94, DQM1 = 86
5687 09:26:03.760254 DQ Delay:
5688 09:26:03.763319 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5689 09:26:03.766995 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5690 09:26:03.770097 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5691 09:26:03.773801 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5692 09:26:03.773894
5693 09:26:03.773979
5694 09:26:03.774060 ==
5695 09:26:03.777027 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 09:26:03.780074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 09:26:03.783804 ==
5698 09:26:03.783870
5699 09:26:03.783925
5700 09:26:03.783977 TX Vref Scan disable
5701 09:26:03.786906 == TX Byte 0 ==
5702 09:26:03.790041 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5703 09:26:03.793217 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5704 09:26:03.796802 == TX Byte 1 ==
5705 09:26:03.800003 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5706 09:26:03.803213 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5707 09:26:03.806403 ==
5708 09:26:03.810156 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 09:26:03.813274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 09:26:03.813346 ==
5711 09:26:03.813403
5712 09:26:03.813456
5713 09:26:03.816942 TX Vref Scan disable
5714 09:26:03.817005 == TX Byte 0 ==
5715 09:26:03.823585 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5716 09:26:03.826776 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5717 09:26:03.826846 == TX Byte 1 ==
5718 09:26:03.833029 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5719 09:26:03.836861 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5720 09:26:03.836936
5721 09:26:03.836997 [DATLAT]
5722 09:26:03.840006 Freq=933, CH1 RK0
5723 09:26:03.840086
5724 09:26:03.840144 DATLAT Default: 0xd
5725 09:26:03.843240 0, 0xFFFF, sum = 0
5726 09:26:03.843314 1, 0xFFFF, sum = 0
5727 09:26:03.846085 2, 0xFFFF, sum = 0
5728 09:26:03.846157 3, 0xFFFF, sum = 0
5729 09:26:03.849683 4, 0xFFFF, sum = 0
5730 09:26:03.849762 5, 0xFFFF, sum = 0
5731 09:26:03.853229 6, 0xFFFF, sum = 0
5732 09:26:03.853319 7, 0xFFFF, sum = 0
5733 09:26:03.856668 8, 0xFFFF, sum = 0
5734 09:26:03.859926 9, 0xFFFF, sum = 0
5735 09:26:03.860059 10, 0x0, sum = 1
5736 09:26:03.860182 11, 0x0, sum = 2
5737 09:26:03.863044 12, 0x0, sum = 3
5738 09:26:03.863208 13, 0x0, sum = 4
5739 09:26:03.866289 best_step = 11
5740 09:26:03.866416
5741 09:26:03.866581 ==
5742 09:26:03.869549 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 09:26:03.872896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 09:26:03.873035 ==
5745 09:26:03.876455 RX Vref Scan: 1
5746 09:26:03.876698
5747 09:26:03.876847 RX Vref 0 -> 0, step: 1
5748 09:26:03.876977
5749 09:26:03.879994 RX Delay -69 -> 252, step: 4
5750 09:26:03.880152
5751 09:26:03.883151 Set Vref, RX VrefLevel [Byte0]: 58
5752 09:26:03.886653 [Byte1]: 51
5753 09:26:03.890582
5754 09:26:03.890821 Final RX Vref Byte 0 = 58 to rank0
5755 09:26:03.894355 Final RX Vref Byte 1 = 51 to rank0
5756 09:26:03.897530 Final RX Vref Byte 0 = 58 to rank1
5757 09:26:03.901202 Final RX Vref Byte 1 = 51 to rank1==
5758 09:26:03.904357 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 09:26:03.910726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 09:26:03.911187 ==
5761 09:26:03.911553 DQS Delay:
5762 09:26:03.911880 DQS0 = 0, DQS1 = 0
5763 09:26:03.914321 DQM Delay:
5764 09:26:03.914905 DQM0 = 96, DQM1 = 89
5765 09:26:03.917604 DQ Delay:
5766 09:26:03.920723 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =92
5767 09:26:03.923776 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =94
5768 09:26:03.927388 DQ8 =80, DQ9 =82, DQ10 =88, DQ11 =84
5769 09:26:03.930981 DQ12 =100, DQ13 =94, DQ14 =94, DQ15 =96
5770 09:26:03.931485
5771 09:26:03.931854
5772 09:26:03.937356 [DQSOSCAuto] RK0, (LSB)MR18= 0x9, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5773 09:26:03.940530 CH1 RK0: MR19=505, MR18=9
5774 09:26:03.947427 CH1_RK0: MR19=0x505, MR18=0x9, DQSOSC=419, MR23=63, INC=61, DEC=41
5775 09:26:03.948097
5776 09:26:03.950587 ----->DramcWriteLeveling(PI) begin...
5777 09:26:03.951124 ==
5778 09:26:03.953731 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 09:26:03.957452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 09:26:03.957915 ==
5781 09:26:03.960369 Write leveling (Byte 0): 26 => 26
5782 09:26:03.964176 Write leveling (Byte 1): 29 => 29
5783 09:26:03.967339 DramcWriteLeveling(PI) end<-----
5784 09:26:03.967799
5785 09:26:03.968146 ==
5786 09:26:03.970253 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 09:26:03.973833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 09:26:03.974451 ==
5789 09:26:03.977115 [Gating] SW mode calibration
5790 09:26:03.983824 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5791 09:26:03.990463 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5792 09:26:03.993545 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 09:26:03.997063 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 09:26:04.003728 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 09:26:04.007134 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 09:26:04.010011 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 09:26:04.016967 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 09:26:04.020212 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)
5799 09:26:04.023289 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5800 09:26:04.030297 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 09:26:04.033346 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 09:26:04.036896 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 09:26:04.043165 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 09:26:04.046891 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 09:26:04.050125 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 09:26:04.056510 0 15 24 | B1->B0 | 2929 3434 | 0 0 | (0 0) (0 0)
5807 09:26:04.060161 0 15 28 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
5808 09:26:04.063250 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 09:26:04.069930 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 09:26:04.073033 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 09:26:04.076724 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 09:26:04.083527 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 09:26:04.086720 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 09:26:04.089852 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5815 09:26:04.096292 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5816 09:26:04.099901 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 09:26:04.103446 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 09:26:04.109622 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 09:26:04.113199 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 09:26:04.116052 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 09:26:04.119498 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 09:26:04.126436 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 09:26:04.129825 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 09:26:04.132807 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 09:26:04.139654 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 09:26:04.142656 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 09:26:04.146382 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 09:26:04.152553 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 09:26:04.155690 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 09:26:04.159440 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5831 09:26:04.165709 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5832 09:26:04.169386 Total UI for P1: 0, mck2ui 16
5833 09:26:04.172399 best dqsien dly found for B0: ( 1, 2, 24)
5834 09:26:04.175475 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 09:26:04.179338 Total UI for P1: 0, mck2ui 16
5836 09:26:04.182470 best dqsien dly found for B1: ( 1, 2, 28)
5837 09:26:04.185724 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5838 09:26:04.188826 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5839 09:26:04.189493
5840 09:26:04.192487 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5841 09:26:04.198710 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5842 09:26:04.199325 [Gating] SW calibration Done
5843 09:26:04.199609 ==
5844 09:26:04.201858 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 09:26:04.208248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 09:26:04.208360 ==
5847 09:26:04.208452 RX Vref Scan: 0
5848 09:26:04.208542
5849 09:26:04.211446 RX Vref 0 -> 0, step: 1
5850 09:26:04.211549
5851 09:26:04.215270 RX Delay -80 -> 252, step: 8
5852 09:26:04.218344 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5853 09:26:04.221452 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5854 09:26:04.225065 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5855 09:26:04.231767 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5856 09:26:04.234894 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5857 09:26:04.238329 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5858 09:26:04.241290 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5859 09:26:04.244786 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5860 09:26:04.247830 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5861 09:26:04.254565 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5862 09:26:04.258056 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5863 09:26:04.261505 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5864 09:26:04.264696 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5865 09:26:04.267888 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5866 09:26:04.274716 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5867 09:26:04.277915 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5868 09:26:04.278016 ==
5869 09:26:04.281119 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 09:26:04.284857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 09:26:04.284931 ==
5872 09:26:04.285019 DQS Delay:
5873 09:26:04.287859 DQS0 = 0, DQS1 = 0
5874 09:26:04.287947 DQM Delay:
5875 09:26:04.290965 DQM0 = 93, DQM1 = 88
5876 09:26:04.291054 DQ Delay:
5877 09:26:04.294786 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5878 09:26:04.297923 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5879 09:26:04.301015 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5880 09:26:04.304735 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5881 09:26:04.304811
5882 09:26:04.304894
5883 09:26:04.304975 ==
5884 09:26:04.307842 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 09:26:04.310813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 09:26:04.314338 ==
5887 09:26:04.314435
5888 09:26:04.314519
5889 09:26:04.314601 TX Vref Scan disable
5890 09:26:04.318067 == TX Byte 0 ==
5891 09:26:04.321216 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5892 09:26:04.324282 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5893 09:26:04.327446 == TX Byte 1 ==
5894 09:26:04.331294 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5895 09:26:04.334359 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5896 09:26:04.337442 ==
5897 09:26:04.341162 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 09:26:04.344310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 09:26:04.344405 ==
5900 09:26:04.344493
5901 09:26:04.344576
5902 09:26:04.347276 TX Vref Scan disable
5903 09:26:04.347372 == TX Byte 0 ==
5904 09:26:04.353892 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5905 09:26:04.357386 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5906 09:26:04.357457 == TX Byte 1 ==
5907 09:26:04.363893 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5908 09:26:04.367238 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5909 09:26:04.367337
5910 09:26:04.367423 [DATLAT]
5911 09:26:04.370787 Freq=933, CH1 RK1
5912 09:26:04.370877
5913 09:26:04.370959 DATLAT Default: 0xb
5914 09:26:04.374228 0, 0xFFFF, sum = 0
5915 09:26:04.374322 1, 0xFFFF, sum = 0
5916 09:26:04.377448 2, 0xFFFF, sum = 0
5917 09:26:04.377544 3, 0xFFFF, sum = 0
5918 09:26:04.380632 4, 0xFFFF, sum = 0
5919 09:26:04.383935 5, 0xFFFF, sum = 0
5920 09:26:04.384035 6, 0xFFFF, sum = 0
5921 09:26:04.387517 7, 0xFFFF, sum = 0
5922 09:26:04.387599 8, 0xFFFF, sum = 0
5923 09:26:04.390597 9, 0xFFFF, sum = 0
5924 09:26:04.390676 10, 0x0, sum = 1
5925 09:26:04.393731 11, 0x0, sum = 2
5926 09:26:04.393809 12, 0x0, sum = 3
5927 09:26:04.393870 13, 0x0, sum = 4
5928 09:26:04.397523 best_step = 11
5929 09:26:04.397603
5930 09:26:04.397664 ==
5931 09:26:04.400837 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 09:26:04.403991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 09:26:04.404084 ==
5934 09:26:04.407180 RX Vref Scan: 0
5935 09:26:04.407273
5936 09:26:04.410257 RX Vref 0 -> 0, step: 1
5937 09:26:04.410336
5938 09:26:04.410397 RX Delay -69 -> 252, step: 4
5939 09:26:04.418222 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5940 09:26:04.421253 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5941 09:26:04.424770 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5942 09:26:04.427982 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5943 09:26:04.431112 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5944 09:26:04.438010 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5945 09:26:04.441092 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5946 09:26:04.444931 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5947 09:26:04.447969 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5948 09:26:04.451103 iDelay=203, Bit 9, Center 84 (-9 ~ 178) 188
5949 09:26:04.454871 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5950 09:26:04.461179 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5951 09:26:04.464785 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5952 09:26:04.467773 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5953 09:26:04.471285 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5954 09:26:04.474291 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5955 09:26:04.474371 ==
5956 09:26:04.477961 Dram Type= 6, Freq= 0, CH_1, rank 1
5957 09:26:04.484182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 09:26:04.484263 ==
5959 09:26:04.484325 DQS Delay:
5960 09:26:04.487660 DQS0 = 0, DQS1 = 0
5961 09:26:04.487739 DQM Delay:
5962 09:26:04.487801 DQM0 = 91, DQM1 = 91
5963 09:26:04.491081 DQ Delay:
5964 09:26:04.494321 DQ0 =94, DQ1 =86, DQ2 =82, DQ3 =88
5965 09:26:04.497515 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
5966 09:26:04.500691 DQ8 =78, DQ9 =84, DQ10 =94, DQ11 =84
5967 09:26:04.504387 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
5968 09:26:04.504467
5969 09:26:04.504528
5970 09:26:04.510689 [DQSOSCAuto] RK1, (LSB)MR18= 0x1428, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
5971 09:26:04.514348 CH1 RK1: MR19=505, MR18=1428
5972 09:26:04.520529 CH1_RK1: MR19=0x505, MR18=0x1428, DQSOSC=409, MR23=63, INC=64, DEC=43
5973 09:26:04.524150 [RxdqsGatingPostProcess] freq 933
5974 09:26:04.527166 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5975 09:26:04.530781 best DQS0 dly(2T, 0.5T) = (0, 10)
5976 09:26:04.533999 best DQS1 dly(2T, 0.5T) = (0, 10)
5977 09:26:04.537095 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5978 09:26:04.540985 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5979 09:26:04.544163 best DQS0 dly(2T, 0.5T) = (0, 10)
5980 09:26:04.547348 best DQS1 dly(2T, 0.5T) = (0, 10)
5981 09:26:04.550444 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5982 09:26:04.554221 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5983 09:26:04.557244 Pre-setting of DQS Precalculation
5984 09:26:04.560389 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5985 09:26:04.570494 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5986 09:26:04.577219 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5987 09:26:04.577301
5988 09:26:04.577362
5989 09:26:04.580140 [Calibration Summary] 1866 Mbps
5990 09:26:04.580219 CH 0, Rank 0
5991 09:26:04.583871 SW Impedance : PASS
5992 09:26:04.583950 DUTY Scan : NO K
5993 09:26:04.586932 ZQ Calibration : PASS
5994 09:26:04.590088 Jitter Meter : NO K
5995 09:26:04.590167 CBT Training : PASS
5996 09:26:04.593799 Write leveling : PASS
5997 09:26:04.596959 RX DQS gating : PASS
5998 09:26:04.597038 RX DQ/DQS(RDDQC) : PASS
5999 09:26:04.600133 TX DQ/DQS : PASS
6000 09:26:04.603266 RX DATLAT : PASS
6001 09:26:04.603345 RX DQ/DQS(Engine): PASS
6002 09:26:04.607129 TX OE : NO K
6003 09:26:04.607241 All Pass.
6004 09:26:04.607306
6005 09:26:04.610131 CH 0, Rank 1
6006 09:26:04.610210 SW Impedance : PASS
6007 09:26:04.613529 DUTY Scan : NO K
6008 09:26:04.617035 ZQ Calibration : PASS
6009 09:26:04.617113 Jitter Meter : NO K
6010 09:26:04.620461 CBT Training : PASS
6011 09:26:04.623322 Write leveling : PASS
6012 09:26:04.623401 RX DQS gating : PASS
6013 09:26:04.626585 RX DQ/DQS(RDDQC) : PASS
6014 09:26:04.626664 TX DQ/DQS : PASS
6015 09:26:04.630136 RX DATLAT : PASS
6016 09:26:04.633416 RX DQ/DQS(Engine): PASS
6017 09:26:04.633496 TX OE : NO K
6018 09:26:04.636965 All Pass.
6019 09:26:04.637044
6020 09:26:04.637105 CH 1, Rank 0
6021 09:26:04.640141 SW Impedance : PASS
6022 09:26:04.640220 DUTY Scan : NO K
6023 09:26:04.643232 ZQ Calibration : PASS
6024 09:26:04.646942 Jitter Meter : NO K
6025 09:26:04.647021 CBT Training : PASS
6026 09:26:04.650060 Write leveling : PASS
6027 09:26:04.653229 RX DQS gating : PASS
6028 09:26:04.653308 RX DQ/DQS(RDDQC) : PASS
6029 09:26:04.656942 TX DQ/DQS : PASS
6030 09:26:04.660058 RX DATLAT : PASS
6031 09:26:04.660137 RX DQ/DQS(Engine): PASS
6032 09:26:04.663095 TX OE : NO K
6033 09:26:04.663174 All Pass.
6034 09:26:04.663235
6035 09:26:04.666749 CH 1, Rank 1
6036 09:26:04.666827 SW Impedance : PASS
6037 09:26:04.669986 DUTY Scan : NO K
6038 09:26:04.673596 ZQ Calibration : PASS
6039 09:26:04.673675 Jitter Meter : NO K
6040 09:26:04.676758 CBT Training : PASS
6041 09:26:04.676838 Write leveling : PASS
6042 09:26:04.679823 RX DQS gating : PASS
6043 09:26:04.683416 RX DQ/DQS(RDDQC) : PASS
6044 09:26:04.683520 TX DQ/DQS : PASS
6045 09:26:04.686906 RX DATLAT : PASS
6046 09:26:04.689850 RX DQ/DQS(Engine): PASS
6047 09:26:04.689929 TX OE : NO K
6048 09:26:04.693339 All Pass.
6049 09:26:04.693418
6050 09:26:04.693480 DramC Write-DBI off
6051 09:26:04.696430 PER_BANK_REFRESH: Hybrid Mode
6052 09:26:04.699666 TX_TRACKING: ON
6053 09:26:04.706459 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6054 09:26:04.709502 [FAST_K] Save calibration result to emmc
6055 09:26:04.713119 dramc_set_vcore_voltage set vcore to 650000
6056 09:26:04.716236 Read voltage for 400, 6
6057 09:26:04.716316 Vio18 = 0
6058 09:26:04.719970 Vcore = 650000
6059 09:26:04.720049 Vdram = 0
6060 09:26:04.720111 Vddq = 0
6061 09:26:04.723280 Vmddr = 0
6062 09:26:04.726214 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6063 09:26:04.732822 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6064 09:26:04.732903 MEM_TYPE=3, freq_sel=20
6065 09:26:04.736265 sv_algorithm_assistance_LP4_800
6066 09:26:04.742610 ============ PULL DRAM RESETB DOWN ============
6067 09:26:04.746146 ========== PULL DRAM RESETB DOWN end =========
6068 09:26:04.749743 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6069 09:26:04.752870 ===================================
6070 09:26:04.755982 LPDDR4 DRAM CONFIGURATION
6071 09:26:04.759656 ===================================
6072 09:26:04.762812 EX_ROW_EN[0] = 0x0
6073 09:26:04.762889 EX_ROW_EN[1] = 0x0
6074 09:26:04.765972 LP4Y_EN = 0x0
6075 09:26:04.766085 WORK_FSP = 0x0
6076 09:26:04.769075 WL = 0x2
6077 09:26:04.769153 RL = 0x2
6078 09:26:04.772806 BL = 0x2
6079 09:26:04.772886 RPST = 0x0
6080 09:26:04.776140 RD_PRE = 0x0
6081 09:26:04.776233 WR_PRE = 0x1
6082 09:26:04.779389 WR_PST = 0x0
6083 09:26:04.779492 DBI_WR = 0x0
6084 09:26:04.782525 DBI_RD = 0x0
6085 09:26:04.782603 OTF = 0x1
6086 09:26:04.785818 ===================================
6087 09:26:04.788861 ===================================
6088 09:26:04.792417 ANA top config
6089 09:26:04.795417 ===================================
6090 09:26:04.799025 DLL_ASYNC_EN = 0
6091 09:26:04.799103 ALL_SLAVE_EN = 1
6092 09:26:04.802065 NEW_RANK_MODE = 1
6093 09:26:04.805754 DLL_IDLE_MODE = 1
6094 09:26:04.808960 LP45_APHY_COMB_EN = 1
6095 09:26:04.809062 TX_ODT_DIS = 1
6096 09:26:04.811955 NEW_8X_MODE = 1
6097 09:26:04.815558 ===================================
6098 09:26:04.818710 ===================================
6099 09:26:04.822442 data_rate = 800
6100 09:26:04.825422 CKR = 1
6101 09:26:04.829022 DQ_P2S_RATIO = 4
6102 09:26:04.832178 ===================================
6103 09:26:04.835353 CA_P2S_RATIO = 4
6104 09:26:04.835447 DQ_CA_OPEN = 0
6105 09:26:04.838598 DQ_SEMI_OPEN = 1
6106 09:26:04.841761 CA_SEMI_OPEN = 1
6107 09:26:04.845539 CA_FULL_RATE = 0
6108 09:26:04.848456 DQ_CKDIV4_EN = 0
6109 09:26:04.851960 CA_CKDIV4_EN = 1
6110 09:26:04.852053 CA_PREDIV_EN = 0
6111 09:26:04.855452 PH8_DLY = 0
6112 09:26:04.858786 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6113 09:26:04.862003 DQ_AAMCK_DIV = 0
6114 09:26:04.865253 CA_AAMCK_DIV = 0
6115 09:26:04.868671 CA_ADMCK_DIV = 4
6116 09:26:04.871572 DQ_TRACK_CA_EN = 0
6117 09:26:04.871679 CA_PICK = 800
6118 09:26:04.875024 CA_MCKIO = 400
6119 09:26:04.878069 MCKIO_SEMI = 400
6120 09:26:04.881821 PLL_FREQ = 3016
6121 09:26:04.884978 DQ_UI_PI_RATIO = 32
6122 09:26:04.888137 CA_UI_PI_RATIO = 32
6123 09:26:04.891956 ===================================
6124 09:26:04.895095 ===================================
6125 09:26:04.895201 memory_type:LPDDR4
6126 09:26:04.898279 GP_NUM : 10
6127 09:26:04.901491 SRAM_EN : 1
6128 09:26:04.901591 MD32_EN : 0
6129 09:26:04.905045 ===================================
6130 09:26:04.908250 [ANA_INIT] >>>>>>>>>>>>>>
6131 09:26:04.911396 <<<<<< [CONFIGURE PHASE]: ANA_TX
6132 09:26:04.915259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6133 09:26:04.918265 ===================================
6134 09:26:04.921463 data_rate = 800,PCW = 0X7400
6135 09:26:04.925127 ===================================
6136 09:26:04.928146 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6137 09:26:04.931255 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6138 09:26:04.944764 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6139 09:26:04.948129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6140 09:26:04.951274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6141 09:26:04.955318 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6142 09:26:04.958004 [ANA_INIT] flow start
6143 09:26:04.961805 [ANA_INIT] PLL >>>>>>>>
6144 09:26:04.961887 [ANA_INIT] PLL <<<<<<<<
6145 09:26:04.965035 [ANA_INIT] MIDPI >>>>>>>>
6146 09:26:04.968230 [ANA_INIT] MIDPI <<<<<<<<
6147 09:26:04.968329 [ANA_INIT] DLL >>>>>>>>
6148 09:26:04.971886 [ANA_INIT] flow end
6149 09:26:04.974792 ============ LP4 DIFF to SE enter ============
6150 09:26:04.978242 ============ LP4 DIFF to SE exit ============
6151 09:26:04.981531 [ANA_INIT] <<<<<<<<<<<<<
6152 09:26:04.984624 [Flow] Enable top DCM control >>>>>
6153 09:26:04.988212 [Flow] Enable top DCM control <<<<<
6154 09:26:04.991537 Enable DLL master slave shuffle
6155 09:26:04.997987 ==============================================================
6156 09:26:04.998090 Gating Mode config
6157 09:26:05.004767 ==============================================================
6158 09:26:05.004853 Config description:
6159 09:26:05.014945 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6160 09:26:05.021207 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6161 09:26:05.028184 SELPH_MODE 0: By rank 1: By Phase
6162 09:26:05.031362 ==============================================================
6163 09:26:05.034762 GAT_TRACK_EN = 0
6164 09:26:05.037943 RX_GATING_MODE = 2
6165 09:26:05.041151 RX_GATING_TRACK_MODE = 2
6166 09:26:05.044366 SELPH_MODE = 1
6167 09:26:05.047695 PICG_EARLY_EN = 1
6168 09:26:05.050988 VALID_LAT_VALUE = 1
6169 09:26:05.058119 ==============================================================
6170 09:26:05.061367 Enter into Gating configuration >>>>
6171 09:26:05.064535 Exit from Gating configuration <<<<
6172 09:26:05.064630 Enter into DVFS_PRE_config >>>>>
6173 09:26:05.077902 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6174 09:26:05.081069 Exit from DVFS_PRE_config <<<<<
6175 09:26:05.084206 Enter into PICG configuration >>>>
6176 09:26:05.087978 Exit from PICG configuration <<<<
6177 09:26:05.088073 [RX_INPUT] configuration >>>>>
6178 09:26:05.091172 [RX_INPUT] configuration <<<<<
6179 09:26:05.098126 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6180 09:26:05.100850 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6181 09:26:05.107776 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6182 09:26:05.114642 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6183 09:26:05.120924 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6184 09:26:05.128039 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6185 09:26:05.130992 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6186 09:26:05.134381 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6187 09:26:05.141079 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6188 09:26:05.144037 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6189 09:26:05.147810 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6190 09:26:05.150966 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6191 09:26:05.154019 ===================================
6192 09:26:05.157855 LPDDR4 DRAM CONFIGURATION
6193 09:26:05.161001 ===================================
6194 09:26:05.164168 EX_ROW_EN[0] = 0x0
6195 09:26:05.164258 EX_ROW_EN[1] = 0x0
6196 09:26:05.167440 LP4Y_EN = 0x0
6197 09:26:05.167539 WORK_FSP = 0x0
6198 09:26:05.171178 WL = 0x2
6199 09:26:05.171269 RL = 0x2
6200 09:26:05.174270 BL = 0x2
6201 09:26:05.174366 RPST = 0x0
6202 09:26:05.177350 RD_PRE = 0x0
6203 09:26:05.177442 WR_PRE = 0x1
6204 09:26:05.181086 WR_PST = 0x0
6205 09:26:05.181198 DBI_WR = 0x0
6206 09:26:05.184263 DBI_RD = 0x0
6207 09:26:05.184355 OTF = 0x1
6208 09:26:05.187464 ===================================
6209 09:26:05.193957 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6210 09:26:05.197701 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6211 09:26:05.200866 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6212 09:26:05.204012 ===================================
6213 09:26:05.207686 LPDDR4 DRAM CONFIGURATION
6214 09:26:05.210842 ===================================
6215 09:26:05.213917 EX_ROW_EN[0] = 0x10
6216 09:26:05.214013 EX_ROW_EN[1] = 0x0
6217 09:26:05.217369 LP4Y_EN = 0x0
6218 09:26:05.217466 WORK_FSP = 0x0
6219 09:26:05.220912 WL = 0x2
6220 09:26:05.221006 RL = 0x2
6221 09:26:05.223745 BL = 0x2
6222 09:26:05.223838 RPST = 0x0
6223 09:26:05.227063 RD_PRE = 0x0
6224 09:26:05.227163 WR_PRE = 0x1
6225 09:26:05.230498 WR_PST = 0x0
6226 09:26:05.230592 DBI_WR = 0x0
6227 09:26:05.233841 DBI_RD = 0x0
6228 09:26:05.233941 OTF = 0x1
6229 09:26:05.237121 ===================================
6230 09:26:05.244188 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6231 09:26:05.248553 nWR fixed to 30
6232 09:26:05.251750 [ModeRegInit_LP4] CH0 RK0
6233 09:26:05.251830 [ModeRegInit_LP4] CH0 RK1
6234 09:26:05.255172 [ModeRegInit_LP4] CH1 RK0
6235 09:26:05.258455 [ModeRegInit_LP4] CH1 RK1
6236 09:26:05.258556 match AC timing 19
6237 09:26:05.265224 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6238 09:26:05.268369 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6239 09:26:05.272194 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6240 09:26:05.278363 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6241 09:26:05.281542 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6242 09:26:05.281637 ==
6243 09:26:05.285398 Dram Type= 6, Freq= 0, CH_0, rank 0
6244 09:26:05.288519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 09:26:05.288614 ==
6246 09:26:05.294829 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6247 09:26:05.301818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6248 09:26:05.305021 [CA 0] Center 36 (8~64) winsize 57
6249 09:26:05.308165 [CA 1] Center 36 (8~64) winsize 57
6250 09:26:05.311951 [CA 2] Center 36 (8~64) winsize 57
6251 09:26:05.315150 [CA 3] Center 36 (8~64) winsize 57
6252 09:26:05.315240 [CA 4] Center 36 (8~64) winsize 57
6253 09:26:05.318260 [CA 5] Center 36 (8~64) winsize 57
6254 09:26:05.318328
6255 09:26:05.325061 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6256 09:26:05.325127
6257 09:26:05.328244 [CATrainingPosCal] consider 1 rank data
6258 09:26:05.331736 u2DelayCellTimex100 = 270/100 ps
6259 09:26:05.334780 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 09:26:05.337982 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 09:26:05.341628 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 09:26:05.344870 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 09:26:05.347949 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 09:26:05.351500 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 09:26:05.351570
6266 09:26:05.354982 CA PerBit enable=1, Macro0, CA PI delay=36
6267 09:26:05.355052
6268 09:26:05.357956 [CBTSetCACLKResult] CA Dly = 36
6269 09:26:05.361242 CS Dly: 1 (0~32)
6270 09:26:05.361307 ==
6271 09:26:05.364854 Dram Type= 6, Freq= 0, CH_0, rank 1
6272 09:26:05.367829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 09:26:05.367899 ==
6274 09:26:05.374834 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6275 09:26:05.381192 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6276 09:26:05.381267 [CA 0] Center 36 (8~64) winsize 57
6277 09:26:05.384612 [CA 1] Center 36 (8~64) winsize 57
6278 09:26:05.387773 [CA 2] Center 36 (8~64) winsize 57
6279 09:26:05.391338 [CA 3] Center 36 (8~64) winsize 57
6280 09:26:05.394434 [CA 4] Center 36 (8~64) winsize 57
6281 09:26:05.397818 [CA 5] Center 36 (8~64) winsize 57
6282 09:26:05.397922
6283 09:26:05.401068 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6284 09:26:05.401164
6285 09:26:05.404262 [CATrainingPosCal] consider 2 rank data
6286 09:26:05.408008 u2DelayCellTimex100 = 270/100 ps
6287 09:26:05.411169 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 09:26:05.417457 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 09:26:05.421243 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 09:26:05.424262 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 09:26:05.427361 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 09:26:05.431147 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 09:26:05.431216
6294 09:26:05.434109 CA PerBit enable=1, Macro0, CA PI delay=36
6295 09:26:05.434177
6296 09:26:05.437711 [CBTSetCACLKResult] CA Dly = 36
6297 09:26:05.437785 CS Dly: 1 (0~32)
6298 09:26:05.437844
6299 09:26:05.444069 ----->DramcWriteLeveling(PI) begin...
6300 09:26:05.444176 ==
6301 09:26:05.447872 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 09:26:05.450965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 09:26:05.451060 ==
6304 09:26:05.454139 Write leveling (Byte 0): 40 => 8
6305 09:26:05.457281 Write leveling (Byte 1): 40 => 8
6306 09:26:05.461011 DramcWriteLeveling(PI) end<-----
6307 09:26:05.461107
6308 09:26:05.461192 ==
6309 09:26:05.464369 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 09:26:05.467544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 09:26:05.467641 ==
6312 09:26:05.470713 [Gating] SW mode calibration
6313 09:26:05.477676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6314 09:26:05.480686 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6315 09:26:05.487355 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6316 09:26:05.490548 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6317 09:26:05.494297 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 09:26:05.500651 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6319 09:26:05.504377 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 09:26:05.507307 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 09:26:05.514033 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 09:26:05.517405 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 09:26:05.520918 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 09:26:05.523782 Total UI for P1: 0, mck2ui 16
6325 09:26:05.527474 best dqsien dly found for B0: ( 0, 14, 24)
6326 09:26:05.530522 Total UI for P1: 0, mck2ui 16
6327 09:26:05.533706 best dqsien dly found for B1: ( 0, 14, 24)
6328 09:26:05.537477 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6329 09:26:05.544198 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6330 09:26:05.544275
6331 09:26:05.547353 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6332 09:26:05.550397 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6333 09:26:05.553518 [Gating] SW calibration Done
6334 09:26:05.553607 ==
6335 09:26:05.557322 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 09:26:05.560503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 09:26:05.560594 ==
6338 09:26:05.560706 RX Vref Scan: 0
6339 09:26:05.563605
6340 09:26:05.563693 RX Vref 0 -> 0, step: 1
6341 09:26:05.563775
6342 09:26:05.567267 RX Delay -410 -> 252, step: 16
6343 09:26:05.570241 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6344 09:26:05.576896 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6345 09:26:05.580011 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6346 09:26:05.583835 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6347 09:26:05.586982 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6348 09:26:05.593728 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6349 09:26:05.596879 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6350 09:26:05.599986 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6351 09:26:05.603749 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6352 09:26:05.610138 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6353 09:26:05.613192 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6354 09:26:05.616909 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6355 09:26:05.619952 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6356 09:26:05.626917 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6357 09:26:05.630348 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6358 09:26:05.633696 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6359 09:26:05.633764 ==
6360 09:26:05.636951 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 09:26:05.643718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 09:26:05.643784 ==
6363 09:26:05.643839 DQS Delay:
6364 09:26:05.646932 DQS0 = 59, DQS1 = 67
6365 09:26:05.647018 DQM Delay:
6366 09:26:05.647097 DQM0 = 18, DQM1 = 16
6367 09:26:05.650190 DQ Delay:
6368 09:26:05.653339 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6369 09:26:05.656784 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6370 09:26:05.656878 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6371 09:26:05.659780 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6372 09:26:05.663564
6373 09:26:05.663651
6374 09:26:05.663734 ==
6375 09:26:05.666786 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 09:26:05.669975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 09:26:05.670078 ==
6378 09:26:05.670171
6379 09:26:05.670254
6380 09:26:05.673071 TX Vref Scan disable
6381 09:26:05.673165 == TX Byte 0 ==
6382 09:26:05.676780 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6383 09:26:05.682850 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6384 09:26:05.682932 == TX Byte 1 ==
6385 09:26:05.686651 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 09:26:05.692775 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 09:26:05.692849 ==
6388 09:26:05.696635 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 09:26:05.699707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 09:26:05.699796 ==
6391 09:26:05.699858
6392 09:26:05.699913
6393 09:26:05.702900 TX Vref Scan disable
6394 09:26:05.702993 == TX Byte 0 ==
6395 09:26:05.709857 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6396 09:26:05.712879 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6397 09:26:05.712950 == TX Byte 1 ==
6398 09:26:05.719711 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 09:26:05.722877 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 09:26:05.722973
6401 09:26:05.723072 [DATLAT]
6402 09:26:05.726025 Freq=400, CH0 RK0
6403 09:26:05.726118
6404 09:26:05.726214 DATLAT Default: 0xf
6405 09:26:05.729693 0, 0xFFFF, sum = 0
6406 09:26:05.729787 1, 0xFFFF, sum = 0
6407 09:26:05.732817 2, 0xFFFF, sum = 0
6408 09:26:05.732905 3, 0xFFFF, sum = 0
6409 09:26:05.735938 4, 0xFFFF, sum = 0
6410 09:26:05.736006 5, 0xFFFF, sum = 0
6411 09:26:05.739024 6, 0xFFFF, sum = 0
6412 09:26:05.739125 7, 0xFFFF, sum = 0
6413 09:26:05.742690 8, 0xFFFF, sum = 0
6414 09:26:05.742796 9, 0xFFFF, sum = 0
6415 09:26:05.745758 10, 0xFFFF, sum = 0
6416 09:26:05.749326 11, 0xFFFF, sum = 0
6417 09:26:05.749418 12, 0xFFFF, sum = 0
6418 09:26:05.752386 13, 0x0, sum = 1
6419 09:26:05.752490 14, 0x0, sum = 2
6420 09:26:05.752587 15, 0x0, sum = 3
6421 09:26:05.755518 16, 0x0, sum = 4
6422 09:26:05.755616 best_step = 14
6423 09:26:05.755712
6424 09:26:05.759197 ==
6425 09:26:05.762088 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 09:26:05.765596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 09:26:05.765696 ==
6428 09:26:05.765782 RX Vref Scan: 1
6429 09:26:05.765865
6430 09:26:05.768814 RX Vref 0 -> 0, step: 1
6431 09:26:05.768919
6432 09:26:05.771923 RX Delay -375 -> 252, step: 8
6433 09:26:05.771986
6434 09:26:05.775293 Set Vref, RX VrefLevel [Byte0]: 62
6435 09:26:05.778495 [Byte1]: 47
6436 09:26:05.782948
6437 09:26:05.783041 Final RX Vref Byte 0 = 62 to rank0
6438 09:26:05.785949 Final RX Vref Byte 1 = 47 to rank0
6439 09:26:05.789281 Final RX Vref Byte 0 = 62 to rank1
6440 09:26:05.792292 Final RX Vref Byte 1 = 47 to rank1==
6441 09:26:05.796009 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 09:26:05.802340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 09:26:05.802406 ==
6444 09:26:05.802462 DQS Delay:
6445 09:26:05.806231 DQS0 = 60, DQS1 = 64
6446 09:26:05.806298 DQM Delay:
6447 09:26:05.806354 DQM0 = 14, DQM1 = 9
6448 09:26:05.809447 DQ Delay:
6449 09:26:05.812573 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6450 09:26:05.815744 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6451 09:26:05.815830 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6452 09:26:05.819053 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6453 09:26:05.822282
6454 09:26:05.822364
6455 09:26:05.829178 [DQSOSCAuto] RK0, (LSB)MR18= 0x8e8c, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6456 09:26:05.832216 CH0 RK0: MR19=C0C, MR18=8E8C
6457 09:26:05.839066 CH0_RK0: MR19=0xC0C, MR18=0x8E8C, DQSOSC=392, MR23=63, INC=384, DEC=256
6458 09:26:05.839155 ==
6459 09:26:05.842238 Dram Type= 6, Freq= 0, CH_0, rank 1
6460 09:26:05.845776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 09:26:05.845846 ==
6462 09:26:05.848876 [Gating] SW mode calibration
6463 09:26:05.855678 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6464 09:26:05.862259 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6465 09:26:05.865403 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6466 09:26:05.868596 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6467 09:26:05.875440 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 09:26:05.878585 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6469 09:26:05.881984 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 09:26:05.888675 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 09:26:05.892043 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 09:26:05.895215 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 09:26:05.901500 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 09:26:05.901575 Total UI for P1: 0, mck2ui 16
6475 09:26:05.908729 best dqsien dly found for B0: ( 0, 14, 24)
6476 09:26:05.908824 Total UI for P1: 0, mck2ui 16
6477 09:26:05.911861 best dqsien dly found for B1: ( 0, 14, 24)
6478 09:26:05.918197 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6479 09:26:05.922011 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6480 09:26:05.922103
6481 09:26:05.925239 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6482 09:26:05.928266 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6483 09:26:05.931868 [Gating] SW calibration Done
6484 09:26:05.931960 ==
6485 09:26:05.934840 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 09:26:05.938001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 09:26:05.938089 ==
6488 09:26:05.941767 RX Vref Scan: 0
6489 09:26:05.941829
6490 09:26:05.941886 RX Vref 0 -> 0, step: 1
6491 09:26:05.941939
6492 09:26:05.944999 RX Delay -410 -> 252, step: 16
6493 09:26:05.951228 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6494 09:26:05.954795 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6495 09:26:05.957922 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6496 09:26:05.961511 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6497 09:26:05.968096 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6498 09:26:05.971184 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6499 09:26:05.975045 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6500 09:26:05.978170 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6501 09:26:05.984556 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6502 09:26:05.987724 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6503 09:26:05.991436 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6504 09:26:05.994243 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6505 09:26:06.001034 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6506 09:26:06.004614 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6507 09:26:06.008102 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6508 09:26:06.010917 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6509 09:26:06.014267 ==
6510 09:26:06.018132 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 09:26:06.021169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 09:26:06.021263 ==
6513 09:26:06.021349 DQS Delay:
6514 09:26:06.024715 DQS0 = 59, DQS1 = 59
6515 09:26:06.024787 DQM Delay:
6516 09:26:06.027819 DQM0 = 16, DQM1 = 10
6517 09:26:06.027909 DQ Delay:
6518 09:26:06.030922 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6519 09:26:06.034074 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6520 09:26:06.037775 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6521 09:26:06.040853 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6522 09:26:06.040913
6523 09:26:06.040967
6524 09:26:06.041021 ==
6525 09:26:06.044059 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 09:26:06.047803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 09:26:06.047889 ==
6528 09:26:06.047969
6529 09:26:06.048049
6530 09:26:06.050935 TX Vref Scan disable
6531 09:26:06.051025 == TX Byte 0 ==
6532 09:26:06.057633 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6533 09:26:06.060748 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6534 09:26:06.060810 == TX Byte 1 ==
6535 09:26:06.067480 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6536 09:26:06.070998 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6537 09:26:06.071103 ==
6538 09:26:06.074062 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 09:26:06.077223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 09:26:06.077301 ==
6541 09:26:06.077371
6542 09:26:06.077437
6543 09:26:06.080991 TX Vref Scan disable
6544 09:26:06.081075 == TX Byte 0 ==
6545 09:26:06.087265 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6546 09:26:06.091138 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6547 09:26:06.091265 == TX Byte 1 ==
6548 09:26:06.097429 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6549 09:26:06.100918 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6550 09:26:06.101016
6551 09:26:06.101075 [DATLAT]
6552 09:26:06.103841 Freq=400, CH0 RK1
6553 09:26:06.103926
6554 09:26:06.104010 DATLAT Default: 0xe
6555 09:26:06.107114 0, 0xFFFF, sum = 0
6556 09:26:06.107181 1, 0xFFFF, sum = 0
6557 09:26:06.110949 2, 0xFFFF, sum = 0
6558 09:26:06.111013 3, 0xFFFF, sum = 0
6559 09:26:06.114074 4, 0xFFFF, sum = 0
6560 09:26:06.114205 5, 0xFFFF, sum = 0
6561 09:26:06.117151 6, 0xFFFF, sum = 0
6562 09:26:06.117256 7, 0xFFFF, sum = 0
6563 09:26:06.120309 8, 0xFFFF, sum = 0
6564 09:26:06.120387 9, 0xFFFF, sum = 0
6565 09:26:06.123928 10, 0xFFFF, sum = 0
6566 09:26:06.127519 11, 0xFFFF, sum = 0
6567 09:26:06.127622 12, 0xFFFF, sum = 0
6568 09:26:06.130796 13, 0x0, sum = 1
6569 09:26:06.130899 14, 0x0, sum = 2
6570 09:26:06.133885 15, 0x0, sum = 3
6571 09:26:06.133948 16, 0x0, sum = 4
6572 09:26:06.134001 best_step = 14
6573 09:26:06.134051
6574 09:26:06.137060 ==
6575 09:26:06.140904 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 09:26:06.143822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 09:26:06.143909 ==
6578 09:26:06.143988 RX Vref Scan: 0
6579 09:26:06.144066
6580 09:26:06.147220 RX Vref 0 -> 0, step: 1
6581 09:26:06.147320
6582 09:26:06.150440 RX Delay -359 -> 252, step: 8
6583 09:26:06.157626 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6584 09:26:06.160929 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6585 09:26:06.163952 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6586 09:26:06.167173 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6587 09:26:06.174250 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6588 09:26:06.177099 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6589 09:26:06.180805 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6590 09:26:06.184031 iDelay=217, Bit 7, Center -40 (-295 ~ 216) 512
6591 09:26:06.190358 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6592 09:26:06.194256 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6593 09:26:06.197413 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6594 09:26:06.200699 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6595 09:26:06.207241 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6596 09:26:06.210261 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6597 09:26:06.214052 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6598 09:26:06.220265 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6599 09:26:06.220361 ==
6600 09:26:06.223970 Dram Type= 6, Freq= 0, CH_0, rank 1
6601 09:26:06.227177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 09:26:06.227244 ==
6603 09:26:06.227308 DQS Delay:
6604 09:26:06.230328 DQS0 = 60, DQS1 = 72
6605 09:26:06.230400 DQM Delay:
6606 09:26:06.233460 DQM0 = 11, DQM1 = 16
6607 09:26:06.233530 DQ Delay:
6608 09:26:06.236721 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6609 09:26:06.239978 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6610 09:26:06.243710 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6611 09:26:06.246876 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6612 09:26:06.246965
6613 09:26:06.247032
6614 09:26:06.253359 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf87, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 384 ps
6615 09:26:06.256949 CH0 RK1: MR19=C0C, MR18=CF87
6616 09:26:06.263289 CH0_RK1: MR19=0xC0C, MR18=0xCF87, DQSOSC=384, MR23=63, INC=400, DEC=267
6617 09:26:06.266519 [RxdqsGatingPostProcess] freq 400
6618 09:26:06.273289 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6619 09:26:06.276827 best DQS0 dly(2T, 0.5T) = (0, 10)
6620 09:26:06.276921 best DQS1 dly(2T, 0.5T) = (0, 10)
6621 09:26:06.280067 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6622 09:26:06.283067 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6623 09:26:06.286744 best DQS0 dly(2T, 0.5T) = (0, 10)
6624 09:26:06.289834 best DQS1 dly(2T, 0.5T) = (0, 10)
6625 09:26:06.293080 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6626 09:26:06.296757 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6627 09:26:06.299924 Pre-setting of DQS Precalculation
6628 09:26:06.306758 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6629 09:26:06.306851 ==
6630 09:26:06.309837 Dram Type= 6, Freq= 0, CH_1, rank 0
6631 09:26:06.313027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 09:26:06.313121 ==
6633 09:26:06.320114 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6634 09:26:06.323297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6635 09:26:06.326405 [CA 0] Center 36 (8~64) winsize 57
6636 09:26:06.329556 [CA 1] Center 36 (8~64) winsize 57
6637 09:26:06.333338 [CA 2] Center 36 (8~64) winsize 57
6638 09:26:06.336386 [CA 3] Center 36 (8~64) winsize 57
6639 09:26:06.339628 [CA 4] Center 36 (8~64) winsize 57
6640 09:26:06.342809 [CA 5] Center 36 (8~64) winsize 57
6641 09:26:06.342902
6642 09:26:06.346497 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6643 09:26:06.346632
6644 09:26:06.349646 [CATrainingPosCal] consider 1 rank data
6645 09:26:06.352898 u2DelayCellTimex100 = 270/100 ps
6646 09:26:06.355976 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 09:26:06.359557 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 09:26:06.362786 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 09:26:06.369503 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 09:26:06.372704 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 09:26:06.375848 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 09:26:06.375942
6653 09:26:06.379524 CA PerBit enable=1, Macro0, CA PI delay=36
6654 09:26:06.379621
6655 09:26:06.382617 [CBTSetCACLKResult] CA Dly = 36
6656 09:26:06.382706 CS Dly: 1 (0~32)
6657 09:26:06.382791 ==
6658 09:26:06.386223 Dram Type= 6, Freq= 0, CH_1, rank 1
6659 09:26:06.392634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 09:26:06.392722 ==
6661 09:26:06.396061 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6662 09:26:06.402458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6663 09:26:06.406151 [CA 0] Center 36 (8~64) winsize 57
6664 09:26:06.409354 [CA 1] Center 36 (8~64) winsize 57
6665 09:26:06.412654 [CA 2] Center 36 (8~64) winsize 57
6666 09:26:06.415776 [CA 3] Center 36 (8~64) winsize 57
6667 09:26:06.419075 [CA 4] Center 36 (8~64) winsize 57
6668 09:26:06.422384 [CA 5] Center 36 (8~64) winsize 57
6669 09:26:06.422481
6670 09:26:06.425514 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6671 09:26:06.425608
6672 09:26:06.429046 [CATrainingPosCal] consider 2 rank data
6673 09:26:06.432237 u2DelayCellTimex100 = 270/100 ps
6674 09:26:06.435273 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 09:26:06.439142 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 09:26:06.442303 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 09:26:06.445398 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 09:26:06.448547 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 09:26:06.455556 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 09:26:06.455652
6681 09:26:06.458705 CA PerBit enable=1, Macro0, CA PI delay=36
6682 09:26:06.458773
6683 09:26:06.462418 [CBTSetCACLKResult] CA Dly = 36
6684 09:26:06.462488 CS Dly: 1 (0~32)
6685 09:26:06.462546
6686 09:26:06.465477 ----->DramcWriteLeveling(PI) begin...
6687 09:26:06.465550 ==
6688 09:26:06.468641 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 09:26:06.475429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 09:26:06.475525 ==
6691 09:26:06.478652 Write leveling (Byte 0): 40 => 8
6692 09:26:06.478744 Write leveling (Byte 1): 40 => 8
6693 09:26:06.481700 DramcWriteLeveling(PI) end<-----
6694 09:26:06.481766
6695 09:26:06.481823 ==
6696 09:26:06.485398 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 09:26:06.491619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 09:26:06.491710 ==
6699 09:26:06.495298 [Gating] SW mode calibration
6700 09:26:06.501703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6701 09:26:06.505511 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6702 09:26:06.511675 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6703 09:26:06.515227 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6704 09:26:06.518305 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 09:26:06.524796 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6706 09:26:06.528533 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 09:26:06.531959 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 09:26:06.538316 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 09:26:06.541484 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 09:26:06.544806 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 09:26:06.548243 Total UI for P1: 0, mck2ui 16
6712 09:26:06.551273 best dqsien dly found for B0: ( 0, 14, 24)
6713 09:26:06.554984 Total UI for P1: 0, mck2ui 16
6714 09:26:06.558076 best dqsien dly found for B1: ( 0, 14, 24)
6715 09:26:06.561276 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6716 09:26:06.564373 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6717 09:26:06.564466
6718 09:26:06.571261 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6719 09:26:06.574473 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6720 09:26:06.574568 [Gating] SW calibration Done
6721 09:26:06.578148 ==
6722 09:26:06.581173 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 09:26:06.584398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 09:26:06.584490 ==
6725 09:26:06.584574 RX Vref Scan: 0
6726 09:26:06.584661
6727 09:26:06.587484 RX Vref 0 -> 0, step: 1
6728 09:26:06.587568
6729 09:26:06.591234 RX Delay -410 -> 252, step: 16
6730 09:26:06.594411 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6731 09:26:06.597648 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6732 09:26:06.604300 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6733 09:26:06.607500 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6734 09:26:06.610731 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6735 09:26:06.614508 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6736 09:26:06.620773 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6737 09:26:06.624458 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6738 09:26:06.627652 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6739 09:26:06.630803 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6740 09:26:06.637832 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6741 09:26:06.640963 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6742 09:26:06.644216 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6743 09:26:06.651044 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6744 09:26:06.654199 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6745 09:26:06.657735 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6746 09:26:06.657828 ==
6747 09:26:06.660561 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 09:26:06.663887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 09:26:06.663980 ==
6750 09:26:06.667681 DQS Delay:
6751 09:26:06.667771 DQS0 = 51, DQS1 = 67
6752 09:26:06.670947 DQM Delay:
6753 09:26:06.671044 DQM0 = 13, DQM1 = 19
6754 09:26:06.674221 DQ Delay:
6755 09:26:06.674307 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6756 09:26:06.677554 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6757 09:26:06.680891 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6758 09:26:06.683911 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6759 09:26:06.683986
6760 09:26:06.684045
6761 09:26:06.684108 ==
6762 09:26:06.687647 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 09:26:06.693898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 09:26:06.693971 ==
6765 09:26:06.694038
6766 09:26:06.694121
6767 09:26:06.694204 TX Vref Scan disable
6768 09:26:06.697074 == TX Byte 0 ==
6769 09:26:06.700890 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6770 09:26:06.703905 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6771 09:26:06.707493 == TX Byte 1 ==
6772 09:26:06.710630 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 09:26:06.713783 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 09:26:06.716952 ==
6775 09:26:06.720205 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 09:26:06.723855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 09:26:06.723934 ==
6778 09:26:06.723993
6779 09:26:06.724054
6780 09:26:06.727344 TX Vref Scan disable
6781 09:26:06.727435 == TX Byte 0 ==
6782 09:26:06.730237 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6783 09:26:06.737153 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6784 09:26:06.737250 == TX Byte 1 ==
6785 09:26:06.740275 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 09:26:06.746777 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 09:26:06.746877
6788 09:26:06.746971 [DATLAT]
6789 09:26:06.747055 Freq=400, CH1 RK0
6790 09:26:06.747151
6791 09:26:06.750716 DATLAT Default: 0xf
6792 09:26:06.750808 0, 0xFFFF, sum = 0
6793 09:26:06.753992 1, 0xFFFF, sum = 0
6794 09:26:06.754099 2, 0xFFFF, sum = 0
6795 09:26:06.757194 3, 0xFFFF, sum = 0
6796 09:26:06.757291 4, 0xFFFF, sum = 0
6797 09:26:06.760311 5, 0xFFFF, sum = 0
6798 09:26:06.763535 6, 0xFFFF, sum = 0
6799 09:26:06.763636 7, 0xFFFF, sum = 0
6800 09:26:06.766681 8, 0xFFFF, sum = 0
6801 09:26:06.766774 9, 0xFFFF, sum = 0
6802 09:26:06.770447 10, 0xFFFF, sum = 0
6803 09:26:06.770552 11, 0xFFFF, sum = 0
6804 09:26:06.773437 12, 0xFFFF, sum = 0
6805 09:26:06.773536 13, 0x0, sum = 1
6806 09:26:06.776964 14, 0x0, sum = 2
6807 09:26:06.777059 15, 0x0, sum = 3
6808 09:26:06.780345 16, 0x0, sum = 4
6809 09:26:06.780439 best_step = 14
6810 09:26:06.780524
6811 09:26:06.780606 ==
6812 09:26:06.783283 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 09:26:06.786658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 09:26:06.786752 ==
6815 09:26:06.790185 RX Vref Scan: 1
6816 09:26:06.790277
6817 09:26:06.793453 RX Vref 0 -> 0, step: 1
6818 09:26:06.793543
6819 09:26:06.793626 RX Delay -375 -> 252, step: 8
6820 09:26:06.796852
6821 09:26:06.796919 Set Vref, RX VrefLevel [Byte0]: 58
6822 09:26:06.800215 [Byte1]: 51
6823 09:26:06.805864
6824 09:26:06.805964 Final RX Vref Byte 0 = 58 to rank0
6825 09:26:06.808893 Final RX Vref Byte 1 = 51 to rank0
6826 09:26:06.812619 Final RX Vref Byte 0 = 58 to rank1
6827 09:26:06.815594 Final RX Vref Byte 1 = 51 to rank1==
6828 09:26:06.819360 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 09:26:06.825660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 09:26:06.825731 ==
6831 09:26:06.825790 DQS Delay:
6832 09:26:06.829377 DQS0 = 56, DQS1 = 64
6833 09:26:06.829466 DQM Delay:
6834 09:26:06.829549 DQM0 = 13, DQM1 = 10
6835 09:26:06.832346 DQ Delay:
6836 09:26:06.835806 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6837 09:26:06.835875 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6838 09:26:06.838831 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6839 09:26:06.842557 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6840 09:26:06.842627
6841 09:26:06.845703
6842 09:26:06.852570 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6843 09:26:06.855481 CH1 RK0: MR19=C0C, MR18=5B6E
6844 09:26:06.862513 CH1_RK0: MR19=0xC0C, MR18=0x5B6E, DQSOSC=395, MR23=63, INC=378, DEC=252
6845 09:26:06.862603 ==
6846 09:26:06.865641 Dram Type= 6, Freq= 0, CH_1, rank 1
6847 09:26:06.868742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 09:26:06.868842 ==
6849 09:26:06.872599 [Gating] SW mode calibration
6850 09:26:06.878895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6851 09:26:06.885531 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6852 09:26:06.889000 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6853 09:26:06.892079 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6854 09:26:06.898477 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 09:26:06.902196 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6856 09:26:06.905233 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 09:26:06.908777 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 09:26:06.915560 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 09:26:06.918851 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 09:26:06.922131 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 09:26:06.925354 Total UI for P1: 0, mck2ui 16
6862 09:26:06.928732 best dqsien dly found for B0: ( 0, 14, 24)
6863 09:26:06.931998 Total UI for P1: 0, mck2ui 16
6864 09:26:06.935598 best dqsien dly found for B1: ( 0, 14, 24)
6865 09:26:06.938555 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6866 09:26:06.945042 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6867 09:26:06.945127
6868 09:26:06.948711 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6869 09:26:06.951905 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6870 09:26:06.955084 [Gating] SW calibration Done
6871 09:26:06.955178 ==
6872 09:26:06.958699 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 09:26:06.961986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 09:26:06.962054 ==
6875 09:26:06.962115 RX Vref Scan: 0
6876 09:26:06.965031
6877 09:26:06.965121 RX Vref 0 -> 0, step: 1
6878 09:26:06.965203
6879 09:26:06.968717 RX Delay -410 -> 252, step: 16
6880 09:26:06.971848 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6881 09:26:06.978222 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6882 09:26:06.981941 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6883 09:26:06.985120 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6884 09:26:06.988300 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6885 09:26:06.995121 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6886 09:26:06.998198 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6887 09:26:07.001339 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6888 09:26:07.005006 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6889 09:26:07.011188 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6890 09:26:07.014993 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6891 09:26:07.018051 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6892 09:26:07.024743 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6893 09:26:07.027851 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6894 09:26:07.031414 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6895 09:26:07.034408 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6896 09:26:07.034501 ==
6897 09:26:07.038075 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 09:26:07.044733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 09:26:07.044806 ==
6900 09:26:07.044868 DQS Delay:
6901 09:26:07.047656 DQS0 = 59, DQS1 = 59
6902 09:26:07.047747 DQM Delay:
6903 09:26:07.051318 DQM0 = 19, DQM1 = 14
6904 09:26:07.051389 DQ Delay:
6905 09:26:07.054635 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6906 09:26:07.057935 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6907 09:26:07.061045 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6908 09:26:07.064450 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6909 09:26:07.064544
6910 09:26:07.064630
6911 09:26:07.064698 ==
6912 09:26:07.067979 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 09:26:07.071330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 09:26:07.071425 ==
6915 09:26:07.071512
6916 09:26:07.071595
6917 09:26:07.074720 TX Vref Scan disable
6918 09:26:07.074809 == TX Byte 0 ==
6919 09:26:07.077887 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6920 09:26:07.084299 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6921 09:26:07.084368 == TX Byte 1 ==
6922 09:26:07.088070 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6923 09:26:07.094275 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6924 09:26:07.094343 ==
6925 09:26:07.098033 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 09:26:07.101075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 09:26:07.101147 ==
6928 09:26:07.101203
6929 09:26:07.101256
6930 09:26:07.104510 TX Vref Scan disable
6931 09:26:07.104598 == TX Byte 0 ==
6932 09:26:07.111282 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6933 09:26:07.114445 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6934 09:26:07.114512 == TX Byte 1 ==
6935 09:26:07.120717 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6936 09:26:07.124279 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6937 09:26:07.124370
6938 09:26:07.124455 [DATLAT]
6939 09:26:07.127421 Freq=400, CH1 RK1
6940 09:26:07.127512
6941 09:26:07.127595 DATLAT Default: 0xe
6942 09:26:07.130538 0, 0xFFFF, sum = 0
6943 09:26:07.130628 1, 0xFFFF, sum = 0
6944 09:26:07.134176 2, 0xFFFF, sum = 0
6945 09:26:07.134269 3, 0xFFFF, sum = 0
6946 09:26:07.137354 4, 0xFFFF, sum = 0
6947 09:26:07.137444 5, 0xFFFF, sum = 0
6948 09:26:07.140358 6, 0xFFFF, sum = 0
6949 09:26:07.140450 7, 0xFFFF, sum = 0
6950 09:26:07.143967 8, 0xFFFF, sum = 0
6951 09:26:07.144059 9, 0xFFFF, sum = 0
6952 09:26:07.147040 10, 0xFFFF, sum = 0
6953 09:26:07.147130 11, 0xFFFF, sum = 0
6954 09:26:07.150845 12, 0xFFFF, sum = 0
6955 09:26:07.153976 13, 0x0, sum = 1
6956 09:26:07.154065 14, 0x0, sum = 2
6957 09:26:07.154148 15, 0x0, sum = 3
6958 09:26:07.157622 16, 0x0, sum = 4
6959 09:26:07.157719 best_step = 14
6960 09:26:07.157809
6961 09:26:07.157903 ==
6962 09:26:07.160636 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 09:26:07.167415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 09:26:07.167506 ==
6965 09:26:07.167590 RX Vref Scan: 0
6966 09:26:07.167670
6967 09:26:07.170477 RX Vref 0 -> 0, step: 1
6968 09:26:07.170571
6969 09:26:07.173923 RX Delay -359 -> 252, step: 8
6970 09:26:07.180354 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6971 09:26:07.183606 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6972 09:26:07.187297 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6973 09:26:07.190552 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6974 09:26:07.197313 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6975 09:26:07.200387 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6976 09:26:07.203640 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6977 09:26:07.210443 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6978 09:26:07.213485 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6979 09:26:07.216991 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6980 09:26:07.220141 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6981 09:26:07.226487 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6982 09:26:07.230089 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6983 09:26:07.233190 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6984 09:26:07.236339 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6985 09:26:07.243123 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6986 09:26:07.243192 ==
6987 09:26:07.246789 Dram Type= 6, Freq= 0, CH_1, rank 1
6988 09:26:07.249731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6989 09:26:07.249825 ==
6990 09:26:07.249910 DQS Delay:
6991 09:26:07.253434 DQS0 = 60, DQS1 = 64
6992 09:26:07.253502 DQM Delay:
6993 09:26:07.256473 DQM0 = 12, DQM1 = 10
6994 09:26:07.256566 DQ Delay:
6995 09:26:07.259623 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6996 09:26:07.263328 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6997 09:26:07.266431 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6998 09:26:07.269530 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6999 09:26:07.269625
7000 09:26:07.269687
7001 09:26:07.276559 [DQSOSCAuto] RK1, (LSB)MR18= 0x7aab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7002 09:26:07.279675 CH1 RK1: MR19=C0C, MR18=7AAB
7003 09:26:07.286466 CH1_RK1: MR19=0xC0C, MR18=0x7AAB, DQSOSC=388, MR23=63, INC=392, DEC=261
7004 09:26:07.289527 [RxdqsGatingPostProcess] freq 400
7005 09:26:07.296214 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7006 09:26:07.299763 best DQS0 dly(2T, 0.5T) = (0, 10)
7007 09:26:07.302797 best DQS1 dly(2T, 0.5T) = (0, 10)
7008 09:26:07.306057 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7009 09:26:07.309321 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7010 09:26:07.309391 best DQS0 dly(2T, 0.5T) = (0, 10)
7011 09:26:07.312625 best DQS1 dly(2T, 0.5T) = (0, 10)
7012 09:26:07.316174 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7013 09:26:07.319239 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7014 09:26:07.322806 Pre-setting of DQS Precalculation
7015 09:26:07.329462 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7016 09:26:07.335659 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7017 09:26:07.342535 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7018 09:26:07.342628
7019 09:26:07.342711
7020 09:26:07.345677 [Calibration Summary] 800 Mbps
7021 09:26:07.345741 CH 0, Rank 0
7022 09:26:07.349417 SW Impedance : PASS
7023 09:26:07.352554 DUTY Scan : NO K
7024 09:26:07.352640 ZQ Calibration : PASS
7025 09:26:07.356296 Jitter Meter : NO K
7026 09:26:07.359305 CBT Training : PASS
7027 09:26:07.359394 Write leveling : PASS
7028 09:26:07.362476 RX DQS gating : PASS
7029 09:26:07.366177 RX DQ/DQS(RDDQC) : PASS
7030 09:26:07.366242 TX DQ/DQS : PASS
7031 09:26:07.369226 RX DATLAT : PASS
7032 09:26:07.369313 RX DQ/DQS(Engine): PASS
7033 09:26:07.372654 TX OE : NO K
7034 09:26:07.372760 All Pass.
7035 09:26:07.372817
7036 09:26:07.375808 CH 0, Rank 1
7037 09:26:07.375868 SW Impedance : PASS
7038 09:26:07.378930 DUTY Scan : NO K
7039 09:26:07.382177 ZQ Calibration : PASS
7040 09:26:07.382267 Jitter Meter : NO K
7041 09:26:07.386001 CBT Training : PASS
7042 09:26:07.389002 Write leveling : NO K
7043 09:26:07.389096 RX DQS gating : PASS
7044 09:26:07.392105 RX DQ/DQS(RDDQC) : PASS
7045 09:26:07.395730 TX DQ/DQS : PASS
7046 09:26:07.395821 RX DATLAT : PASS
7047 09:26:07.398839 RX DQ/DQS(Engine): PASS
7048 09:26:07.402035 TX OE : NO K
7049 09:26:07.402104 All Pass.
7050 09:26:07.402160
7051 09:26:07.402212 CH 1, Rank 0
7052 09:26:07.405648 SW Impedance : PASS
7053 09:26:07.408836 DUTY Scan : NO K
7054 09:26:07.408926 ZQ Calibration : PASS
7055 09:26:07.412028 Jitter Meter : NO K
7056 09:26:07.415608 CBT Training : PASS
7057 09:26:07.415696 Write leveling : PASS
7058 09:26:07.418517 RX DQS gating : PASS
7059 09:26:07.421839 RX DQ/DQS(RDDQC) : PASS
7060 09:26:07.421922 TX DQ/DQS : PASS
7061 09:26:07.425135 RX DATLAT : PASS
7062 09:26:07.428754 RX DQ/DQS(Engine): PASS
7063 09:26:07.428847 TX OE : NO K
7064 09:26:07.428931 All Pass.
7065 09:26:07.432133
7066 09:26:07.432222 CH 1, Rank 1
7067 09:26:07.435401 SW Impedance : PASS
7068 09:26:07.435467 DUTY Scan : NO K
7069 09:26:07.438508 ZQ Calibration : PASS
7070 09:26:07.438603 Jitter Meter : NO K
7071 09:26:07.442195 CBT Training : PASS
7072 09:26:07.445093 Write leveling : NO K
7073 09:26:07.445189 RX DQS gating : PASS
7074 09:26:07.448746 RX DQ/DQS(RDDQC) : PASS
7075 09:26:07.451843 TX DQ/DQS : PASS
7076 09:26:07.451933 RX DATLAT : PASS
7077 09:26:07.455132 RX DQ/DQS(Engine): PASS
7078 09:26:07.458856 TX OE : NO K
7079 09:26:07.458945 All Pass.
7080 09:26:07.459027
7081 09:26:07.461952 DramC Write-DBI off
7082 09:26:07.462047 PER_BANK_REFRESH: Hybrid Mode
7083 09:26:07.465121 TX_TRACKING: ON
7084 09:26:07.472080 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7085 09:26:07.478802 [FAST_K] Save calibration result to emmc
7086 09:26:07.481869 dramc_set_vcore_voltage set vcore to 725000
7087 09:26:07.481977 Read voltage for 1600, 0
7088 09:26:07.485051 Vio18 = 0
7089 09:26:07.485144 Vcore = 725000
7090 09:26:07.485226 Vdram = 0
7091 09:26:07.488182 Vddq = 0
7092 09:26:07.488354 Vmddr = 0
7093 09:26:07.491834 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7094 09:26:07.498484 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7095 09:26:07.501770 MEM_TYPE=3, freq_sel=13
7096 09:26:07.504710 sv_algorithm_assistance_LP4_3733
7097 09:26:07.508468 ============ PULL DRAM RESETB DOWN ============
7098 09:26:07.511723 ========== PULL DRAM RESETB DOWN end =========
7099 09:26:07.517926 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7100 09:26:07.521730 ===================================
7101 09:26:07.521823 LPDDR4 DRAM CONFIGURATION
7102 09:26:07.524874 ===================================
7103 09:26:07.528082 EX_ROW_EN[0] = 0x0
7104 09:26:07.528143 EX_ROW_EN[1] = 0x0
7105 09:26:07.531447 LP4Y_EN = 0x0
7106 09:26:07.534961 WORK_FSP = 0x1
7107 09:26:07.535029 WL = 0x5
7108 09:26:07.538112 RL = 0x5
7109 09:26:07.538176 BL = 0x2
7110 09:26:07.541379 RPST = 0x0
7111 09:26:07.541442 RD_PRE = 0x0
7112 09:26:07.544407 WR_PRE = 0x1
7113 09:26:07.544494 WR_PST = 0x1
7114 09:26:07.547899 DBI_WR = 0x0
7115 09:26:07.547983 DBI_RD = 0x0
7116 09:26:07.551273 OTF = 0x1
7117 09:26:07.554580 ===================================
7118 09:26:07.558253 ===================================
7119 09:26:07.558312 ANA top config
7120 09:26:07.561368 ===================================
7121 09:26:07.564667 DLL_ASYNC_EN = 0
7122 09:26:07.567734 ALL_SLAVE_EN = 0
7123 09:26:07.567836 NEW_RANK_MODE = 1
7124 09:26:07.571348 DLL_IDLE_MODE = 1
7125 09:26:07.574275 LP45_APHY_COMB_EN = 1
7126 09:26:07.578032 TX_ODT_DIS = 0
7127 09:26:07.581211 NEW_8X_MODE = 1
7128 09:26:07.584305 ===================================
7129 09:26:07.587862 ===================================
7130 09:26:07.587936 data_rate = 3200
7131 09:26:07.591053 CKR = 1
7132 09:26:07.594278 DQ_P2S_RATIO = 8
7133 09:26:07.597383 ===================================
7134 09:26:07.600941 CA_P2S_RATIO = 8
7135 09:26:07.604437 DQ_CA_OPEN = 0
7136 09:26:07.607613 DQ_SEMI_OPEN = 0
7137 09:26:07.607705 CA_SEMI_OPEN = 0
7138 09:26:07.610725 CA_FULL_RATE = 0
7139 09:26:07.614498 DQ_CKDIV4_EN = 0
7140 09:26:07.617633 CA_CKDIV4_EN = 0
7141 09:26:07.620810 CA_PREDIV_EN = 0
7142 09:26:07.624566 PH8_DLY = 12
7143 09:26:07.624687 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7144 09:26:07.627659 DQ_AAMCK_DIV = 4
7145 09:26:07.630768 CA_AAMCK_DIV = 4
7146 09:26:07.633831 CA_ADMCK_DIV = 4
7147 09:26:07.637580 DQ_TRACK_CA_EN = 0
7148 09:26:07.641054 CA_PICK = 1600
7149 09:26:07.644150 CA_MCKIO = 1600
7150 09:26:07.644218 MCKIO_SEMI = 0
7151 09:26:07.647216 PLL_FREQ = 3068
7152 09:26:07.650974 DQ_UI_PI_RATIO = 32
7153 09:26:07.654155 CA_UI_PI_RATIO = 0
7154 09:26:07.657255 ===================================
7155 09:26:07.661007 ===================================
7156 09:26:07.664160 memory_type:LPDDR4
7157 09:26:07.664222 GP_NUM : 10
7158 09:26:07.667162 SRAM_EN : 1
7159 09:26:07.670753 MD32_EN : 0
7160 09:26:07.673694 ===================================
7161 09:26:07.673787 [ANA_INIT] >>>>>>>>>>>>>>
7162 09:26:07.677168 <<<<<< [CONFIGURE PHASE]: ANA_TX
7163 09:26:07.680528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7164 09:26:07.683881 ===================================
7165 09:26:07.687125 data_rate = 3200,PCW = 0X7600
7166 09:26:07.690339 ===================================
7167 09:26:07.693908 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7168 09:26:07.700542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7169 09:26:07.703679 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7170 09:26:07.710145 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7171 09:26:07.713560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7172 09:26:07.717284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7173 09:26:07.717381 [ANA_INIT] flow start
7174 09:26:07.720454 [ANA_INIT] PLL >>>>>>>>
7175 09:26:07.723714 [ANA_INIT] PLL <<<<<<<<
7176 09:26:07.723802 [ANA_INIT] MIDPI >>>>>>>>
7177 09:26:07.726829 [ANA_INIT] MIDPI <<<<<<<<
7178 09:26:07.730607 [ANA_INIT] DLL >>>>>>>>
7179 09:26:07.733572 [ANA_INIT] DLL <<<<<<<<
7180 09:26:07.733659 [ANA_INIT] flow end
7181 09:26:07.737310 ============ LP4 DIFF to SE enter ============
7182 09:26:07.743472 ============ LP4 DIFF to SE exit ============
7183 09:26:07.743537 [ANA_INIT] <<<<<<<<<<<<<
7184 09:26:07.747146 [Flow] Enable top DCM control >>>>>
7185 09:26:07.750056 [Flow] Enable top DCM control <<<<<
7186 09:26:07.753770 Enable DLL master slave shuffle
7187 09:26:07.760157 ==============================================================
7188 09:26:07.760248 Gating Mode config
7189 09:26:07.766561 ==============================================================
7190 09:26:07.770261 Config description:
7191 09:26:07.780248 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7192 09:26:07.786398 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7193 09:26:07.790112 SELPH_MODE 0: By rank 1: By Phase
7194 09:26:07.796799 ==============================================================
7195 09:26:07.799930 GAT_TRACK_EN = 1
7196 09:26:07.803175 RX_GATING_MODE = 2
7197 09:26:07.803242 RX_GATING_TRACK_MODE = 2
7198 09:26:07.806511 SELPH_MODE = 1
7199 09:26:07.809701 PICG_EARLY_EN = 1
7200 09:26:07.813425 VALID_LAT_VALUE = 1
7201 09:26:07.819701 ==============================================================
7202 09:26:07.822851 Enter into Gating configuration >>>>
7203 09:26:07.826356 Exit from Gating configuration <<<<
7204 09:26:07.829719 Enter into DVFS_PRE_config >>>>>
7205 09:26:07.839735 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7206 09:26:07.842909 Exit from DVFS_PRE_config <<<<<
7207 09:26:07.846051 Enter into PICG configuration >>>>
7208 09:26:07.849788 Exit from PICG configuration <<<<
7209 09:26:07.852842 [RX_INPUT] configuration >>>>>
7210 09:26:07.855996 [RX_INPUT] configuration <<<<<
7211 09:26:07.859370 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7212 09:26:07.866297 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7213 09:26:07.872623 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7214 09:26:07.879394 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7215 09:26:07.882586 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7216 09:26:07.889347 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7217 09:26:07.892555 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7218 09:26:07.899236 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7219 09:26:07.902765 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7220 09:26:07.905967 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7221 09:26:07.909110 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7222 09:26:07.915618 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7223 09:26:07.919281 ===================================
7224 09:26:07.922423 LPDDR4 DRAM CONFIGURATION
7225 09:26:07.925714 ===================================
7226 09:26:07.925781 EX_ROW_EN[0] = 0x0
7227 09:26:07.928778 EX_ROW_EN[1] = 0x0
7228 09:26:07.928841 LP4Y_EN = 0x0
7229 09:26:07.932384 WORK_FSP = 0x1
7230 09:26:07.932471 WL = 0x5
7231 09:26:07.935368 RL = 0x5
7232 09:26:07.935430 BL = 0x2
7233 09:26:07.938711 RPST = 0x0
7234 09:26:07.938771 RD_PRE = 0x0
7235 09:26:07.942326 WR_PRE = 0x1
7236 09:26:07.942390 WR_PST = 0x1
7237 09:26:07.945739 DBI_WR = 0x0
7238 09:26:07.945801 DBI_RD = 0x0
7239 09:26:07.949017 OTF = 0x1
7240 09:26:07.952135 ===================================
7241 09:26:07.955551 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7242 09:26:07.958691 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7243 09:26:07.965340 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7244 09:26:07.969042 ===================================
7245 09:26:07.969123 LPDDR4 DRAM CONFIGURATION
7246 09:26:07.972199 ===================================
7247 09:26:07.975395 EX_ROW_EN[0] = 0x10
7248 09:26:07.978607 EX_ROW_EN[1] = 0x0
7249 09:26:07.978673 LP4Y_EN = 0x0
7250 09:26:07.981802 WORK_FSP = 0x1
7251 09:26:07.981867 WL = 0x5
7252 09:26:07.985471 RL = 0x5
7253 09:26:07.985533 BL = 0x2
7254 09:26:07.988588 RPST = 0x0
7255 09:26:07.988706 RD_PRE = 0x0
7256 09:26:07.992253 WR_PRE = 0x1
7257 09:26:07.992312 WR_PST = 0x1
7258 09:26:07.995479 DBI_WR = 0x0
7259 09:26:07.995538 DBI_RD = 0x0
7260 09:26:07.998692 OTF = 0x1
7261 09:26:08.001739 ===================================
7262 09:26:08.008314 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7263 09:26:08.008381 ==
7264 09:26:08.011951 Dram Type= 6, Freq= 0, CH_0, rank 0
7265 09:26:08.015078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7266 09:26:08.015144 ==
7267 09:26:08.018690 [Duty_Offset_Calibration]
7268 09:26:08.018778 B0:2 B1:0 CA:3
7269 09:26:08.018858
7270 09:26:08.021576 [DutyScan_Calibration_Flow] k_type=0
7271 09:26:08.032809
7272 09:26:08.032872 ==CLK 0==
7273 09:26:08.035951 Final CLK duty delay cell = 0
7274 09:26:08.039090 [0] MAX Duty = 5031%(X100), DQS PI = 12
7275 09:26:08.042853 [0] MIN Duty = 4907%(X100), DQS PI = 6
7276 09:26:08.042914 [0] AVG Duty = 4969%(X100)
7277 09:26:08.046032
7278 09:26:08.049038 CH0 CLK Duty spec in!! Max-Min= 124%
7279 09:26:08.052576 [DutyScan_Calibration_Flow] ====Done====
7280 09:26:08.052697
7281 09:26:08.055598 [DutyScan_Calibration_Flow] k_type=1
7282 09:26:08.072343
7283 09:26:08.072441 ==DQS 0 ==
7284 09:26:08.075620 Final DQS duty delay cell = 0
7285 09:26:08.078824 [0] MAX Duty = 5093%(X100), DQS PI = 30
7286 09:26:08.082510 [0] MIN Duty = 4875%(X100), DQS PI = 50
7287 09:26:08.085431 [0] AVG Duty = 4984%(X100)
7288 09:26:08.085499
7289 09:26:08.085554 ==DQS 1 ==
7290 09:26:08.089197 Final DQS duty delay cell = 0
7291 09:26:08.092389 [0] MAX Duty = 5156%(X100), DQS PI = 30
7292 09:26:08.095397 [0] MIN Duty = 5031%(X100), DQS PI = 14
7293 09:26:08.099082 [0] AVG Duty = 5093%(X100)
7294 09:26:08.099144
7295 09:26:08.102131 CH0 DQS 0 Duty spec in!! Max-Min= 218%
7296 09:26:08.102192
7297 09:26:08.105786 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7298 09:26:08.109004 [DutyScan_Calibration_Flow] ====Done====
7299 09:26:08.109065
7300 09:26:08.111985 [DutyScan_Calibration_Flow] k_type=3
7301 09:26:08.130377
7302 09:26:08.130446 ==DQM 0 ==
7303 09:26:08.133430 Final DQM duty delay cell = 0
7304 09:26:08.136577 [0] MAX Duty = 5156%(X100), DQS PI = 30
7305 09:26:08.140359 [0] MIN Duty = 4875%(X100), DQS PI = 0
7306 09:26:08.140449 [0] AVG Duty = 5015%(X100)
7307 09:26:08.143489
7308 09:26:08.143585 ==DQM 1 ==
7309 09:26:08.146605 Final DQM duty delay cell = 4
7310 09:26:08.149880 [4] MAX Duty = 5187%(X100), DQS PI = 62
7311 09:26:08.153503 [4] MIN Duty = 5000%(X100), DQS PI = 38
7312 09:26:08.156580 [4] AVG Duty = 5093%(X100)
7313 09:26:08.156704
7314 09:26:08.160229 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7315 09:26:08.160294
7316 09:26:08.163447 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7317 09:26:08.166633 [DutyScan_Calibration_Flow] ====Done====
7318 09:26:08.166696
7319 09:26:08.169777 [DutyScan_Calibration_Flow] k_type=2
7320 09:26:08.186151
7321 09:26:08.186249 ==DQ 0 ==
7322 09:26:08.189571 Final DQ duty delay cell = -4
7323 09:26:08.192806 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7324 09:26:08.196343 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7325 09:26:08.199482 [-4] AVG Duty = 4938%(X100)
7326 09:26:08.199569
7327 09:26:08.199652 ==DQ 1 ==
7328 09:26:08.202670 Final DQ duty delay cell = 0
7329 09:26:08.206223 [0] MAX Duty = 5156%(X100), DQS PI = 60
7330 09:26:08.209341 [0] MIN Duty = 5000%(X100), DQS PI = 16
7331 09:26:08.212543 [0] AVG Duty = 5078%(X100)
7332 09:26:08.212636
7333 09:26:08.216280 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7334 09:26:08.216378
7335 09:26:08.219254 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7336 09:26:08.222999 [DutyScan_Calibration_Flow] ====Done====
7337 09:26:08.223069 ==
7338 09:26:08.226118 Dram Type= 6, Freq= 0, CH_1, rank 0
7339 09:26:08.229442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7340 09:26:08.229509 ==
7341 09:26:08.232943 [Duty_Offset_Calibration]
7342 09:26:08.233032 B0:1 B1:-2 CA:0
7343 09:26:08.233112
7344 09:26:08.235924 [DutyScan_Calibration_Flow] k_type=0
7345 09:26:08.247262
7346 09:26:08.247327 ==CLK 0==
7347 09:26:08.250344 Final CLK duty delay cell = 0
7348 09:26:08.253491 [0] MAX Duty = 5093%(X100), DQS PI = 22
7349 09:26:08.257283 [0] MIN Duty = 4844%(X100), DQS PI = 4
7350 09:26:08.257354 [0] AVG Duty = 4968%(X100)
7351 09:26:08.260358
7352 09:26:08.263487 CH1 CLK Duty spec in!! Max-Min= 249%
7353 09:26:08.267000 [DutyScan_Calibration_Flow] ====Done====
7354 09:26:08.267125
7355 09:26:08.270027 [DutyScan_Calibration_Flow] k_type=1
7356 09:26:08.286553
7357 09:26:08.286758 ==DQS 0 ==
7358 09:26:08.289631 Final DQS duty delay cell = 0
7359 09:26:08.292838 [0] MAX Duty = 5187%(X100), DQS PI = 26
7360 09:26:08.296534 [0] MIN Duty = 5062%(X100), DQS PI = 48
7361 09:26:08.299852 [0] AVG Duty = 5124%(X100)
7362 09:26:08.300171
7363 09:26:08.300460 ==DQS 1 ==
7364 09:26:08.303409 Final DQS duty delay cell = 0
7365 09:26:08.306363 [0] MAX Duty = 5093%(X100), DQS PI = 58
7366 09:26:08.309831 [0] MIN Duty = 4844%(X100), DQS PI = 26
7367 09:26:08.313428 [0] AVG Duty = 4968%(X100)
7368 09:26:08.313827
7369 09:26:08.316533 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7370 09:26:08.316970
7371 09:26:08.319836 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7372 09:26:08.323116 [DutyScan_Calibration_Flow] ====Done====
7373 09:26:08.323513
7374 09:26:08.326491 [DutyScan_Calibration_Flow] k_type=3
7375 09:26:08.343628
7376 09:26:08.344061 ==DQM 0 ==
7377 09:26:08.346863 Final DQM duty delay cell = 0
7378 09:26:08.350041 [0] MAX Duty = 5031%(X100), DQS PI = 26
7379 09:26:08.353487 [0] MIN Duty = 4813%(X100), DQS PI = 54
7380 09:26:08.356736 [0] AVG Duty = 4922%(X100)
7381 09:26:08.356809
7382 09:26:08.356865 ==DQM 1 ==
7383 09:26:08.359838 Final DQM duty delay cell = 0
7384 09:26:08.362908 [0] MAX Duty = 5093%(X100), DQS PI = 36
7385 09:26:08.366034 [0] MIN Duty = 4875%(X100), DQS PI = 24
7386 09:26:08.369291 [0] AVG Duty = 4984%(X100)
7387 09:26:08.369355
7388 09:26:08.372929 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7389 09:26:08.372994
7390 09:26:08.375890 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7391 09:26:08.379545 [DutyScan_Calibration_Flow] ====Done====
7392 09:26:08.379610
7393 09:26:08.382707 [DutyScan_Calibration_Flow] k_type=2
7394 09:26:08.399984
7395 09:26:08.400083 ==DQ 0 ==
7396 09:26:08.403343 Final DQ duty delay cell = 0
7397 09:26:08.406473 [0] MAX Duty = 5093%(X100), DQS PI = 22
7398 09:26:08.410259 [0] MIN Duty = 4938%(X100), DQS PI = 0
7399 09:26:08.410324 [0] AVG Duty = 5015%(X100)
7400 09:26:08.413317
7401 09:26:08.413382 ==DQ 1 ==
7402 09:26:08.416381 Final DQ duty delay cell = 0
7403 09:26:08.419984 [0] MAX Duty = 5125%(X100), DQS PI = 34
7404 09:26:08.423506 [0] MIN Duty = 4969%(X100), DQS PI = 24
7405 09:26:08.423621 [0] AVG Duty = 5047%(X100)
7406 09:26:08.423737
7407 09:26:08.430081 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7408 09:26:08.430170
7409 09:26:08.433471 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7410 09:26:08.436396 [DutyScan_Calibration_Flow] ====Done====
7411 09:26:08.439906 nWR fixed to 30
7412 09:26:08.439976 [ModeRegInit_LP4] CH0 RK0
7413 09:26:08.443028 [ModeRegInit_LP4] CH0 RK1
7414 09:26:08.446441 [ModeRegInit_LP4] CH1 RK0
7415 09:26:08.449716 [ModeRegInit_LP4] CH1 RK1
7416 09:26:08.449803 match AC timing 5
7417 09:26:08.453279 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7418 09:26:08.459945 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7419 09:26:08.463096 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7420 09:26:08.469967 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7421 09:26:08.473232 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7422 09:26:08.473300 [MiockJmeterHQA]
7423 09:26:08.473357
7424 09:26:08.476426 [DramcMiockJmeter] u1RxGatingPI = 0
7425 09:26:08.479574 0 : 4254, 4029
7426 09:26:08.479652 4 : 4363, 4137
7427 09:26:08.479730 8 : 4252, 4027
7428 09:26:08.483343 12 : 4255, 4030
7429 09:26:08.483409 16 : 4258, 4030
7430 09:26:08.486177 20 : 4257, 4029
7431 09:26:08.486246 24 : 4255, 4029
7432 09:26:08.489784 28 : 4257, 4029
7433 09:26:08.489851 32 : 4258, 4032
7434 09:26:08.492853 36 : 4255, 4030
7435 09:26:08.492918 40 : 4254, 4029
7436 09:26:08.492973 44 : 4257, 4029
7437 09:26:08.496528 48 : 4258, 4030
7438 09:26:08.496617 52 : 4260, 4032
7439 09:26:08.499724 56 : 4258, 4029
7440 09:26:08.499793 60 : 4257, 4029
7441 09:26:08.502868 64 : 4368, 4142
7442 09:26:08.502958 68 : 4363, 4139
7443 09:26:08.505985 72 : 4252, 4030
7444 09:26:08.506051 76 : 4255, 4030
7445 09:26:08.506114 80 : 4253, 4029
7446 09:26:08.509796 84 : 4258, 4032
7447 09:26:08.509892 88 : 4252, 4030
7448 09:26:08.512933 92 : 4252, 4029
7449 09:26:08.512999 96 : 4258, 4031
7450 09:26:08.516080 100 : 4363, 4139
7451 09:26:08.516173 104 : 4363, 3971
7452 09:26:08.519818 108 : 4250, 0
7453 09:26:08.519907 112 : 4255, 0
7454 09:26:08.519988 116 : 4252, 0
7455 09:26:08.522992 120 : 4253, 0
7456 09:26:08.523064 124 : 4252, 0
7457 09:26:08.523122 128 : 4366, 0
7458 09:26:08.525995 132 : 4252, 0
7459 09:26:08.526056 136 : 4255, 0
7460 09:26:08.529721 140 : 4255, 0
7461 09:26:08.529808 144 : 4253, 0
7462 09:26:08.529891 148 : 4257, 0
7463 09:26:08.532888 152 : 4253, 0
7464 09:26:08.532949 156 : 4363, 0
7465 09:26:08.536471 160 : 4253, 0
7466 09:26:08.536562 164 : 4255, 0
7467 09:26:08.536649 168 : 4255, 0
7468 09:26:08.539581 172 : 4257, 0
7469 09:26:08.539641 176 : 4363, 0
7470 09:26:08.542712 180 : 4363, 0
7471 09:26:08.542797 184 : 4253, 0
7472 09:26:08.542877 188 : 4255, 0
7473 09:26:08.545924 192 : 4252, 0
7474 09:26:08.546002 196 : 4253, 0
7475 09:26:08.546057 200 : 4257, 0
7476 09:26:08.549629 204 : 4253, 0
7477 09:26:08.549688 208 : 4252, 0
7478 09:26:08.552559 212 : 4257, 0
7479 09:26:08.552649 216 : 4250, 0
7480 09:26:08.552705 220 : 4255, 0
7481 09:26:08.556253 224 : 4257, 0
7482 09:26:08.556311 228 : 4252, 0
7483 09:26:08.559162 232 : 4252, 0
7484 09:26:08.559220 236 : 4368, 899
7485 09:26:08.559272 240 : 4252, 4028
7486 09:26:08.562553 244 : 4258, 4032
7487 09:26:08.562645 248 : 4363, 4140
7488 09:26:08.565975 252 : 4255, 4029
7489 09:26:08.566039 256 : 4252, 4030
7490 09:26:08.569591 260 : 4253, 4029
7491 09:26:08.569655 264 : 4253, 4029
7492 09:26:08.572440 268 : 4253, 4029
7493 09:26:08.572538 272 : 4365, 4140
7494 09:26:08.576267 276 : 4253, 4029
7495 09:26:08.576399 280 : 4252, 4030
7496 09:26:08.579391 284 : 4368, 4142
7497 09:26:08.579493 288 : 4255, 4029
7498 09:26:08.582513 292 : 4360, 4137
7499 09:26:08.582639 296 : 4255, 4030
7500 09:26:08.585699 300 : 4255, 4029
7501 09:26:08.585795 304 : 4255, 4029
7502 09:26:08.585855 308 : 4252, 4030
7503 09:26:08.589358 312 : 4361, 4137
7504 09:26:08.589421 316 : 4252, 4029
7505 09:26:08.592358 320 : 4253, 4029
7506 09:26:08.592447 324 : 4252, 4030
7507 09:26:08.595922 328 : 4252, 4029
7508 09:26:08.595990 332 : 4255, 4029
7509 09:26:08.599127 336 : 4253, 4029
7510 09:26:08.599226 340 : 4363, 4140
7511 09:26:08.602733 344 : 4252, 4030
7512 09:26:08.602831 348 : 4365, 4140
7513 09:26:08.605808 352 : 4252, 4027
7514 09:26:08.605900 356 : 4253, 2987
7515 09:26:08.605985 360 : 4252, 0
7516 09:26:08.608902
7517 09:26:08.609010 MIOCK jitter meter ch=0
7518 09:26:08.609088
7519 09:26:08.612558 1T = (360-108) = 252 dly cells
7520 09:26:08.618877 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7521 09:26:08.618965 ==
7522 09:26:08.622652 Dram Type= 6, Freq= 0, CH_0, rank 0
7523 09:26:08.625754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 09:26:08.625821 ==
7525 09:26:08.632399 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7526 09:26:08.635532 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7527 09:26:08.639220 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7528 09:26:08.645480 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7529 09:26:08.654807 [CA 0] Center 44 (14~75) winsize 62
7530 09:26:08.658492 [CA 1] Center 44 (14~74) winsize 61
7531 09:26:08.661657 [CA 2] Center 40 (11~69) winsize 59
7532 09:26:08.664755 [CA 3] Center 39 (10~69) winsize 60
7533 09:26:08.668381 [CA 4] Center 37 (8~67) winsize 60
7534 09:26:08.671367 [CA 5] Center 37 (8~66) winsize 59
7535 09:26:08.671460
7536 09:26:08.674483 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7537 09:26:08.674577
7538 09:26:08.681185 [CATrainingPosCal] consider 1 rank data
7539 09:26:08.681278 u2DelayCellTimex100 = 258/100 ps
7540 09:26:08.688017 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7541 09:26:08.691129 CA1 delay=44 (14~74),Diff = 7 PI (26 cell)
7542 09:26:08.694450 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7543 09:26:08.698184 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7544 09:26:08.701243 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7545 09:26:08.704359 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7546 09:26:08.704446
7547 09:26:08.707848 CA PerBit enable=1, Macro0, CA PI delay=37
7548 09:26:08.707911
7549 09:26:08.711114 [CBTSetCACLKResult] CA Dly = 37
7550 09:26:08.714385 CS Dly: 11 (0~42)
7551 09:26:08.717809 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7552 09:26:08.720988 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7553 09:26:08.721061 ==
7554 09:26:08.724185 Dram Type= 6, Freq= 0, CH_0, rank 1
7555 09:26:08.731021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 09:26:08.731085 ==
7557 09:26:08.734047 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7558 09:26:08.740945 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7559 09:26:08.743891 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7560 09:26:08.750544 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7561 09:26:08.758722 [CA 0] Center 44 (14~75) winsize 62
7562 09:26:08.762318 [CA 1] Center 43 (13~74) winsize 62
7563 09:26:08.765418 [CA 2] Center 39 (10~69) winsize 60
7564 09:26:08.769056 [CA 3] Center 39 (10~69) winsize 60
7565 09:26:08.772104 [CA 4] Center 37 (8~67) winsize 60
7566 09:26:08.775060 [CA 5] Center 37 (7~67) winsize 61
7567 09:26:08.775125
7568 09:26:08.778841 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7569 09:26:08.778908
7570 09:26:08.785315 [CATrainingPosCal] consider 2 rank data
7571 09:26:08.785380 u2DelayCellTimex100 = 258/100 ps
7572 09:26:08.792114 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7573 09:26:08.795056 CA1 delay=44 (14~74),Diff = 7 PI (26 cell)
7574 09:26:08.798506 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7575 09:26:08.801857 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7576 09:26:08.805064 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7577 09:26:08.808886 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7578 09:26:08.808955
7579 09:26:08.811996 CA PerBit enable=1, Macro0, CA PI delay=37
7580 09:26:08.812085
7581 09:26:08.814987 [CBTSetCACLKResult] CA Dly = 37
7582 09:26:08.818547 CS Dly: 11 (0~43)
7583 09:26:08.821507 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7584 09:26:08.824932 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7585 09:26:08.824997
7586 09:26:08.828290 ----->DramcWriteLeveling(PI) begin...
7587 09:26:08.828354 ==
7588 09:26:08.831574 Dram Type= 6, Freq= 0, CH_0, rank 0
7589 09:26:08.838231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 09:26:08.838307 ==
7591 09:26:08.841405 Write leveling (Byte 0): 36 => 36
7592 09:26:08.845084 Write leveling (Byte 1): 29 => 29
7593 09:26:08.848018 DramcWriteLeveling(PI) end<-----
7594 09:26:08.848079
7595 09:26:08.848132 ==
7596 09:26:08.851656 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 09:26:08.854673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 09:26:08.854738 ==
7599 09:26:08.857902 [Gating] SW mode calibration
7600 09:26:08.864768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7601 09:26:08.867871 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7602 09:26:08.874798 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 09:26:08.878339 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 09:26:08.881289 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 09:26:08.888165 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 09:26:08.891237 1 4 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7607 09:26:08.894330 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7608 09:26:08.901301 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
7609 09:26:08.904404 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 09:26:08.907692 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 09:26:08.914575 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 09:26:08.917685 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 09:26:08.920838 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 09:26:08.927723 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
7615 09:26:08.930783 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7616 09:26:08.933866 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
7617 09:26:08.940889 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 09:26:08.944139 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 09:26:08.947257 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 09:26:08.954382 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 09:26:08.957437 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7622 09:26:08.960502 1 6 16 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7623 09:26:08.967351 1 6 20 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
7624 09:26:08.970493 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 09:26:08.973768 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 09:26:08.980515 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 09:26:08.984050 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 09:26:08.987045 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 09:26:08.993891 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 09:26:08.997028 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7631 09:26:09.000149 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7632 09:26:09.006966 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7633 09:26:09.010055 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 09:26:09.013848 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 09:26:09.019845 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 09:26:09.023459 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 09:26:09.026815 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 09:26:09.033499 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 09:26:09.036738 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 09:26:09.039853 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 09:26:09.046834 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 09:26:09.049913 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 09:26:09.053490 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 09:26:09.059734 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 09:26:09.063213 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7646 09:26:09.066268 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7647 09:26:09.073073 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7648 09:26:09.073145 Total UI for P1: 0, mck2ui 16
7649 09:26:09.076232 best dqsien dly found for B0: ( 1, 9, 14)
7650 09:26:09.083266 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7651 09:26:09.086439 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 09:26:09.089437 Total UI for P1: 0, mck2ui 16
7653 09:26:09.093092 best dqsien dly found for B1: ( 1, 9, 22)
7654 09:26:09.096211 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7655 09:26:09.099921 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7656 09:26:09.099985
7657 09:26:09.103049 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7658 09:26:09.110012 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7659 09:26:09.110079 [Gating] SW calibration Done
7660 09:26:09.110135 ==
7661 09:26:09.113283 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 09:26:09.119657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 09:26:09.119724 ==
7664 09:26:09.119780 RX Vref Scan: 0
7665 09:26:09.119833
7666 09:26:09.123308 RX Vref 0 -> 0, step: 1
7667 09:26:09.123396
7668 09:26:09.126408 RX Delay 0 -> 252, step: 8
7669 09:26:09.129550 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7670 09:26:09.132690 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7671 09:26:09.136165 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7672 09:26:09.142779 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7673 09:26:09.146434 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7674 09:26:09.149668 iDelay=192, Bit 5, Center 115 (64 ~ 167) 104
7675 09:26:09.152843 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7676 09:26:09.155887 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7677 09:26:09.162926 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7678 09:26:09.166055 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7679 09:26:09.169178 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7680 09:26:09.172731 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7681 09:26:09.175753 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7682 09:26:09.182454 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7683 09:26:09.185834 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7684 09:26:09.189204 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7685 09:26:09.189279 ==
7686 09:26:09.192483 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 09:26:09.195693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 09:26:09.195760 ==
7689 09:26:09.198860 DQS Delay:
7690 09:26:09.198922 DQS0 = 0, DQS1 = 0
7691 09:26:09.202736 DQM Delay:
7692 09:26:09.202810 DQM0 = 128, DQM1 = 124
7693 09:26:09.206004 DQ Delay:
7694 09:26:09.209088 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7695 09:26:09.212202 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =135
7696 09:26:09.215990 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7697 09:26:09.219236 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7698 09:26:09.219328
7699 09:26:09.219408
7700 09:26:09.219486 ==
7701 09:26:09.222361 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 09:26:09.225544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 09:26:09.225606 ==
7704 09:26:09.225657
7705 09:26:09.225707
7706 09:26:09.229306 TX Vref Scan disable
7707 09:26:09.232485 == TX Byte 0 ==
7708 09:26:09.235579 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7709 09:26:09.238791 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7710 09:26:09.241966 == TX Byte 1 ==
7711 09:26:09.245696 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7712 09:26:09.248707 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7713 09:26:09.248804 ==
7714 09:26:09.252211 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 09:26:09.258905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 09:26:09.258976 ==
7717 09:26:09.272037
7718 09:26:09.275689 TX Vref early break, caculate TX vref
7719 09:26:09.278602 TX Vref=16, minBit 8, minWin=22, winSum=361
7720 09:26:09.281863 TX Vref=18, minBit 8, minWin=22, winSum=370
7721 09:26:09.285613 TX Vref=20, minBit 8, minWin=23, winSum=381
7722 09:26:09.288567 TX Vref=22, minBit 5, minWin=24, winSum=397
7723 09:26:09.292280 TX Vref=24, minBit 4, minWin=24, winSum=404
7724 09:26:09.298423 TX Vref=26, minBit 11, minWin=24, winSum=411
7725 09:26:09.302229 TX Vref=28, minBit 9, minWin=24, winSum=411
7726 09:26:09.305189 TX Vref=30, minBit 8, minWin=24, winSum=403
7727 09:26:09.308476 TX Vref=32, minBit 11, minWin=23, winSum=397
7728 09:26:09.312026 TX Vref=34, minBit 9, minWin=23, winSum=395
7729 09:26:09.315455 TX Vref=36, minBit 9, minWin=22, winSum=379
7730 09:26:09.322195 [TxChooseVref] Worse bit 11, Min win 24, Win sum 411, Final Vref 26
7731 09:26:09.322287
7732 09:26:09.325302 Final TX Range 0 Vref 26
7733 09:26:09.325373
7734 09:26:09.325433 ==
7735 09:26:09.328442 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 09:26:09.331757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 09:26:09.331834 ==
7738 09:26:09.335362
7739 09:26:09.335450
7740 09:26:09.335530 TX Vref Scan disable
7741 09:26:09.341680 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7742 09:26:09.341747 == TX Byte 0 ==
7743 09:26:09.344835 u2DelayCellOfst[0]=11 cells (3 PI)
7744 09:26:09.348558 u2DelayCellOfst[1]=15 cells (4 PI)
7745 09:26:09.351759 u2DelayCellOfst[2]=7 cells (2 PI)
7746 09:26:09.354889 u2DelayCellOfst[3]=7 cells (2 PI)
7747 09:26:09.358721 u2DelayCellOfst[4]=3 cells (1 PI)
7748 09:26:09.361799 u2DelayCellOfst[5]=0 cells (0 PI)
7749 09:26:09.364767 u2DelayCellOfst[6]=18 cells (5 PI)
7750 09:26:09.368357 u2DelayCellOfst[7]=15 cells (4 PI)
7751 09:26:09.371770 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7752 09:26:09.374876 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7753 09:26:09.378589 == TX Byte 1 ==
7754 09:26:09.381692 u2DelayCellOfst[8]=0 cells (0 PI)
7755 09:26:09.384855 u2DelayCellOfst[9]=0 cells (0 PI)
7756 09:26:09.387979 u2DelayCellOfst[10]=7 cells (2 PI)
7757 09:26:09.388056 u2DelayCellOfst[11]=3 cells (1 PI)
7758 09:26:09.391766 u2DelayCellOfst[12]=11 cells (3 PI)
7759 09:26:09.394723 u2DelayCellOfst[13]=11 cells (3 PI)
7760 09:26:09.398457 u2DelayCellOfst[14]=15 cells (4 PI)
7761 09:26:09.401718 u2DelayCellOfst[15]=11 cells (3 PI)
7762 09:26:09.407885 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7763 09:26:09.411696 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7764 09:26:09.411771 DramC Write-DBI on
7765 09:26:09.411863 ==
7766 09:26:09.414586 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 09:26:09.421530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 09:26:09.421602 ==
7769 09:26:09.421681
7770 09:26:09.421750
7771 09:26:09.421837 TX Vref Scan disable
7772 09:26:09.425678 == TX Byte 0 ==
7773 09:26:09.429185 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7774 09:26:09.432478 == TX Byte 1 ==
7775 09:26:09.435856 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7776 09:26:09.439187 DramC Write-DBI off
7777 09:26:09.439262
7778 09:26:09.439332 [DATLAT]
7779 09:26:09.439420 Freq=1600, CH0 RK0
7780 09:26:09.439515
7781 09:26:09.442337 DATLAT Default: 0xf
7782 09:26:09.442402 0, 0xFFFF, sum = 0
7783 09:26:09.445536 1, 0xFFFF, sum = 0
7784 09:26:09.448593 2, 0xFFFF, sum = 0
7785 09:26:09.448711 3, 0xFFFF, sum = 0
7786 09:26:09.452394 4, 0xFFFF, sum = 0
7787 09:26:09.452482 5, 0xFFFF, sum = 0
7788 09:26:09.455506 6, 0xFFFF, sum = 0
7789 09:26:09.455599 7, 0xFFFF, sum = 0
7790 09:26:09.458733 8, 0xFFFF, sum = 0
7791 09:26:09.458805 9, 0xFFFF, sum = 0
7792 09:26:09.462532 10, 0xFFFF, sum = 0
7793 09:26:09.462600 11, 0xFFFF, sum = 0
7794 09:26:09.465650 12, 0xFFFF, sum = 0
7795 09:26:09.465717 13, 0xEFFF, sum = 0
7796 09:26:09.468771 14, 0x0, sum = 1
7797 09:26:09.468838 15, 0x0, sum = 2
7798 09:26:09.472448 16, 0x0, sum = 3
7799 09:26:09.472544 17, 0x0, sum = 4
7800 09:26:09.475676 best_step = 15
7801 09:26:09.475747
7802 09:26:09.475843 ==
7803 09:26:09.478578 Dram Type= 6, Freq= 0, CH_0, rank 0
7804 09:26:09.482196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7805 09:26:09.482264 ==
7806 09:26:09.482361 RX Vref Scan: 1
7807 09:26:09.485544
7808 09:26:09.485611 Set Vref Range= 24 -> 127
7809 09:26:09.485713
7810 09:26:09.488840 RX Vref 24 -> 127, step: 1
7811 09:26:09.488910
7812 09:26:09.491805 RX Delay 11 -> 252, step: 4
7813 09:26:09.491874
7814 09:26:09.495223 Set Vref, RX VrefLevel [Byte0]: 24
7815 09:26:09.498805 [Byte1]: 24
7816 09:26:09.498875
7817 09:26:09.501878 Set Vref, RX VrefLevel [Byte0]: 25
7818 09:26:09.505494 [Byte1]: 25
7819 09:26:09.505571
7820 09:26:09.508585 Set Vref, RX VrefLevel [Byte0]: 26
7821 09:26:09.511606 [Byte1]: 26
7822 09:26:09.515935
7823 09:26:09.516005 Set Vref, RX VrefLevel [Byte0]: 27
7824 09:26:09.519509 [Byte1]: 27
7825 09:26:09.523913
7826 09:26:09.523982 Set Vref, RX VrefLevel [Byte0]: 28
7827 09:26:09.527008 [Byte1]: 28
7828 09:26:09.531407
7829 09:26:09.531473 Set Vref, RX VrefLevel [Byte0]: 29
7830 09:26:09.534576 [Byte1]: 29
7831 09:26:09.538761
7832 09:26:09.538832 Set Vref, RX VrefLevel [Byte0]: 30
7833 09:26:09.542187 [Byte1]: 30
7834 09:26:09.546721
7835 09:26:09.546796 Set Vref, RX VrefLevel [Byte0]: 31
7836 09:26:09.549529 [Byte1]: 31
7837 09:26:09.554230
7838 09:26:09.554303 Set Vref, RX VrefLevel [Byte0]: 32
7839 09:26:09.557388 [Byte1]: 32
7840 09:26:09.561744
7841 09:26:09.561813 Set Vref, RX VrefLevel [Byte0]: 33
7842 09:26:09.564983 [Byte1]: 33
7843 09:26:09.569272
7844 09:26:09.569339 Set Vref, RX VrefLevel [Byte0]: 34
7845 09:26:09.572328 [Byte1]: 34
7846 09:26:09.576831
7847 09:26:09.576910 Set Vref, RX VrefLevel [Byte0]: 35
7848 09:26:09.579957 [Byte1]: 35
7849 09:26:09.584389
7850 09:26:09.587605 Set Vref, RX VrefLevel [Byte0]: 36
7851 09:26:09.587678 [Byte1]: 36
7852 09:26:09.592029
7853 09:26:09.592117 Set Vref, RX VrefLevel [Byte0]: 37
7854 09:26:09.595792 [Byte1]: 37
7855 09:26:09.600034
7856 09:26:09.600101 Set Vref, RX VrefLevel [Byte0]: 38
7857 09:26:09.602878 [Byte1]: 38
7858 09:26:09.607230
7859 09:26:09.607305 Set Vref, RX VrefLevel [Byte0]: 39
7860 09:26:09.610904 [Byte1]: 39
7861 09:26:09.615028
7862 09:26:09.615094 Set Vref, RX VrefLevel [Byte0]: 40
7863 09:26:09.618243 [Byte1]: 40
7864 09:26:09.622608
7865 09:26:09.622709 Set Vref, RX VrefLevel [Byte0]: 41
7866 09:26:09.625844 [Byte1]: 41
7867 09:26:09.630536
7868 09:26:09.630631 Set Vref, RX VrefLevel [Byte0]: 42
7869 09:26:09.633659 [Byte1]: 42
7870 09:26:09.638193
7871 09:26:09.638284 Set Vref, RX VrefLevel [Byte0]: 43
7872 09:26:09.641230 [Byte1]: 43
7873 09:26:09.645614
7874 09:26:09.645679 Set Vref, RX VrefLevel [Byte0]: 44
7875 09:26:09.648675 [Byte1]: 44
7876 09:26:09.652912
7877 09:26:09.652984 Set Vref, RX VrefLevel [Byte0]: 45
7878 09:26:09.656472 [Byte1]: 45
7879 09:26:09.660383
7880 09:26:09.660451 Set Vref, RX VrefLevel [Byte0]: 46
7881 09:26:09.663816 [Byte1]: 46
7882 09:26:09.668151
7883 09:26:09.668219 Set Vref, RX VrefLevel [Byte0]: 47
7884 09:26:09.671469 [Byte1]: 47
7885 09:26:09.675788
7886 09:26:09.675859 Set Vref, RX VrefLevel [Byte0]: 48
7887 09:26:09.679473 [Byte1]: 48
7888 09:26:09.683325
7889 09:26:09.683402 Set Vref, RX VrefLevel [Byte0]: 49
7890 09:26:09.687114 [Byte1]: 49
7891 09:26:09.690887
7892 09:26:09.690956 Set Vref, RX VrefLevel [Byte0]: 50
7893 09:26:09.694665 [Byte1]: 50
7894 09:26:09.698454
7895 09:26:09.698526 Set Vref, RX VrefLevel [Byte0]: 51
7896 09:26:09.702341 [Byte1]: 51
7897 09:26:09.706085
7898 09:26:09.706156 Set Vref, RX VrefLevel [Byte0]: 52
7899 09:26:09.709419 [Byte1]: 52
7900 09:26:09.713849
7901 09:26:09.713926 Set Vref, RX VrefLevel [Byte0]: 53
7902 09:26:09.716968 [Byte1]: 53
7903 09:26:09.721372
7904 09:26:09.721467 Set Vref, RX VrefLevel [Byte0]: 54
7905 09:26:09.725006 [Byte1]: 54
7906 09:26:09.728981
7907 09:26:09.729054 Set Vref, RX VrefLevel [Byte0]: 55
7908 09:26:09.732298 [Byte1]: 55
7909 09:26:09.736553
7910 09:26:09.736626 Set Vref, RX VrefLevel [Byte0]: 56
7911 09:26:09.740147 [Byte1]: 56
7912 09:26:09.744281
7913 09:26:09.744351 Set Vref, RX VrefLevel [Byte0]: 57
7914 09:26:09.747678 [Byte1]: 57
7915 09:26:09.751972
7916 09:26:09.752041 Set Vref, RX VrefLevel [Byte0]: 58
7917 09:26:09.755362 [Byte1]: 58
7918 09:26:09.759570
7919 09:26:09.759648 Set Vref, RX VrefLevel [Byte0]: 59
7920 09:26:09.762821 [Byte1]: 59
7921 09:26:09.767003
7922 09:26:09.767071 Set Vref, RX VrefLevel [Byte0]: 60
7923 09:26:09.770424 [Byte1]: 60
7924 09:26:09.775021
7925 09:26:09.775092 Set Vref, RX VrefLevel [Byte0]: 61
7926 09:26:09.777974 [Byte1]: 61
7927 09:26:09.782881
7928 09:26:09.782952 Set Vref, RX VrefLevel [Byte0]: 62
7929 09:26:09.786084 [Byte1]: 62
7930 09:26:09.789942
7931 09:26:09.790019 Set Vref, RX VrefLevel [Byte0]: 63
7932 09:26:09.793724 [Byte1]: 63
7933 09:26:09.797405
7934 09:26:09.797487 Set Vref, RX VrefLevel [Byte0]: 64
7935 09:26:09.801101 [Byte1]: 64
7936 09:26:09.805508
7937 09:26:09.805580 Set Vref, RX VrefLevel [Byte0]: 65
7938 09:26:09.808715 [Byte1]: 65
7939 09:26:09.813045
7940 09:26:09.813134 Set Vref, RX VrefLevel [Byte0]: 66
7941 09:26:09.816202 [Byte1]: 66
7942 09:26:09.820781
7943 09:26:09.820851 Set Vref, RX VrefLevel [Byte0]: 67
7944 09:26:09.823980 [Byte1]: 67
7945 09:26:09.827826
7946 09:26:09.827892 Set Vref, RX VrefLevel [Byte0]: 68
7947 09:26:09.831588 [Byte1]: 68
7948 09:26:09.835854
7949 09:26:09.835925 Set Vref, RX VrefLevel [Byte0]: 69
7950 09:26:09.838970 [Byte1]: 69
7951 09:26:09.843322
7952 09:26:09.843399 Set Vref, RX VrefLevel [Byte0]: 70
7953 09:26:09.846454 [Byte1]: 70
7954 09:26:09.850746
7955 09:26:09.850813 Set Vref, RX VrefLevel [Byte0]: 71
7956 09:26:09.854433 [Byte1]: 71
7957 09:26:09.858669
7958 09:26:09.858734 Set Vref, RX VrefLevel [Byte0]: 72
7959 09:26:09.861601 [Byte1]: 72
7960 09:26:09.866334
7961 09:26:09.866414 Set Vref, RX VrefLevel [Byte0]: 73
7962 09:26:09.869723 [Byte1]: 73
7963 09:26:09.873991
7964 09:26:09.874066 Set Vref, RX VrefLevel [Byte0]: 74
7965 09:26:09.877347 [Byte1]: 74
7966 09:26:09.881401
7967 09:26:09.881492 Set Vref, RX VrefLevel [Byte0]: 75
7968 09:26:09.884939 [Byte1]: 75
7969 09:26:09.888915
7970 09:26:09.888979 Set Vref, RX VrefLevel [Byte0]: 76
7971 09:26:09.892080 [Byte1]: 76
7972 09:26:09.896400
7973 09:26:09.896502 Final RX Vref Byte 0 = 65 to rank0
7974 09:26:09.899941 Final RX Vref Byte 1 = 60 to rank0
7975 09:26:09.903070 Final RX Vref Byte 0 = 65 to rank1
7976 09:26:09.906493 Final RX Vref Byte 1 = 60 to rank1==
7977 09:26:09.909781 Dram Type= 6, Freq= 0, CH_0, rank 0
7978 09:26:09.916407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 09:26:09.916510 ==
7980 09:26:09.916596 DQS Delay:
7981 09:26:09.916710 DQS0 = 0, DQS1 = 0
7982 09:26:09.919704 DQM Delay:
7983 09:26:09.919806 DQM0 = 126, DQM1 = 119
7984 09:26:09.923115 DQ Delay:
7985 09:26:09.926314 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7986 09:26:09.930068 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7987 09:26:09.933305 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7988 09:26:09.936387 DQ12 =124, DQ13 =124, DQ14 =132, DQ15 =126
7989 09:26:09.936463
7990 09:26:09.936522
7991 09:26:09.936577
7992 09:26:09.940021 [DramC_TX_OE_Calibration] TA2
7993 09:26:09.943235 Original DQ_B0 (3 6) =30, OEN = 27
7994 09:26:09.946233 Original DQ_B1 (3 6) =30, OEN = 27
7995 09:26:09.950014 24, 0x0, End_B0=24 End_B1=24
7996 09:26:09.950102 25, 0x0, End_B0=25 End_B1=25
7997 09:26:09.953479 26, 0x0, End_B0=26 End_B1=26
7998 09:26:09.956557 27, 0x0, End_B0=27 End_B1=27
7999 09:26:09.959903 28, 0x0, End_B0=28 End_B1=28
8000 09:26:09.963101 29, 0x0, End_B0=29 End_B1=29
8001 09:26:09.963203 30, 0x0, End_B0=30 End_B1=30
8002 09:26:09.966396 31, 0x4141, End_B0=30 End_B1=30
8003 09:26:09.969763 Byte0 end_step=30 best_step=27
8004 09:26:09.972992 Byte1 end_step=30 best_step=27
8005 09:26:09.976160 Byte0 TX OE(2T, 0.5T) = (3, 3)
8006 09:26:09.979522 Byte1 TX OE(2T, 0.5T) = (3, 3)
8007 09:26:09.979617
8008 09:26:09.979709
8009 09:26:09.985925 [DQSOSCAuto] RK0, (LSB)MR18= 0x1616, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
8010 09:26:09.989663 CH0 RK0: MR19=303, MR18=1616
8011 09:26:09.996102 CH0_RK0: MR19=0x303, MR18=0x1616, DQSOSC=398, MR23=63, INC=23, DEC=15
8012 09:26:09.996214
8013 09:26:09.999179 ----->DramcWriteLeveling(PI) begin...
8014 09:26:09.999274 ==
8015 09:26:10.002531 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 09:26:10.005970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 09:26:10.006088 ==
8018 09:26:10.009650 Write leveling (Byte 0): 37 => 37
8019 09:26:10.012570 Write leveling (Byte 1): 28 => 28
8020 09:26:10.016019 DramcWriteLeveling(PI) end<-----
8021 09:26:10.016111
8022 09:26:10.016198 ==
8023 09:26:10.019305 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 09:26:10.023021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 09:26:10.023128 ==
8026 09:26:10.026046 [Gating] SW mode calibration
8027 09:26:10.032793 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8028 09:26:10.039342 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8029 09:26:10.042446 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 09:26:10.045725 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 09:26:10.052692 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 09:26:10.055824 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8033 09:26:10.058999 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (1 1) (1 1)
8034 09:26:10.066088 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
8035 09:26:10.069075 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 09:26:10.072368 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 09:26:10.079142 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 09:26:10.082318 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8039 09:26:10.086194 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8040 09:26:10.092478 1 5 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
8041 09:26:10.095634 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8042 09:26:10.098888 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8043 09:26:10.105502 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 09:26:10.109173 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 09:26:10.112295 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 09:26:10.119209 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 09:26:10.122416 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8048 09:26:10.125600 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8049 09:26:10.132083 1 6 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8050 09:26:10.135310 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8051 09:26:10.138638 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 09:26:10.145620 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 09:26:10.148469 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 09:26:10.152283 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 09:26:10.158480 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 09:26:10.161654 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8057 09:26:10.165240 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8058 09:26:10.171538 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8059 09:26:10.175146 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 09:26:10.178259 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 09:26:10.184940 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 09:26:10.188183 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 09:26:10.191920 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 09:26:10.198272 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 09:26:10.201393 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 09:26:10.204637 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 09:26:10.211260 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 09:26:10.214692 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 09:26:10.218215 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 09:26:10.224411 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 09:26:10.228269 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8072 09:26:10.231364 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8073 09:26:10.234465 Total UI for P1: 0, mck2ui 16
8074 09:26:10.238194 best dqsien dly found for B0: ( 1, 9, 8)
8075 09:26:10.244393 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8076 09:26:10.248005 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8077 09:26:10.250887 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 09:26:10.254266 Total UI for P1: 0, mck2ui 16
8079 09:26:10.257595 best dqsien dly found for B1: ( 1, 9, 16)
8080 09:26:10.260890 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8081 09:26:10.264426 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8082 09:26:10.264507
8083 09:26:10.267953 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8084 09:26:10.274185 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8085 09:26:10.274267 [Gating] SW calibration Done
8086 09:26:10.274327 ==
8087 09:26:10.277519 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 09:26:10.284020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 09:26:10.284097 ==
8090 09:26:10.284157 RX Vref Scan: 0
8091 09:26:10.284212
8092 09:26:10.287761 RX Vref 0 -> 0, step: 1
8093 09:26:10.287837
8094 09:26:10.290824 RX Delay 0 -> 252, step: 8
8095 09:26:10.293817 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8096 09:26:10.297480 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8097 09:26:10.300764 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8098 09:26:10.307681 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8099 09:26:10.310259 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8100 09:26:10.314002 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8101 09:26:10.317195 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8102 09:26:10.320205 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8103 09:26:10.327111 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8104 09:26:10.330308 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8105 09:26:10.333441 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8106 09:26:10.337206 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8107 09:26:10.340294 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8108 09:26:10.346588 iDelay=200, Bit 13, Center 123 (64 ~ 183) 120
8109 09:26:10.350382 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8110 09:26:10.353543 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8111 09:26:10.353619 ==
8112 09:26:10.356577 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 09:26:10.360323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 09:26:10.363444 ==
8115 09:26:10.363520 DQS Delay:
8116 09:26:10.363579 DQS0 = 0, DQS1 = 0
8117 09:26:10.366499 DQM Delay:
8118 09:26:10.366577 DQM0 = 127, DQM1 = 120
8119 09:26:10.370074 DQ Delay:
8120 09:26:10.373481 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8121 09:26:10.376922 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8122 09:26:10.380164 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8123 09:26:10.383507 DQ12 =127, DQ13 =123, DQ14 =131, DQ15 =127
8124 09:26:10.383601
8125 09:26:10.383684
8126 09:26:10.383771 ==
8127 09:26:10.386369 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 09:26:10.389793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 09:26:10.393152 ==
8130 09:26:10.393216
8131 09:26:10.393268
8132 09:26:10.393319 TX Vref Scan disable
8133 09:26:10.396186 == TX Byte 0 ==
8134 09:26:10.399972 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8135 09:26:10.403222 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8136 09:26:10.406606 == TX Byte 1 ==
8137 09:26:10.409804 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8138 09:26:10.412885 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8139 09:26:10.416017 ==
8140 09:26:10.416081 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 09:26:10.422795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 09:26:10.422859 ==
8143 09:26:10.437150
8144 09:26:10.440227 TX Vref early break, caculate TX vref
8145 09:26:10.443961 TX Vref=16, minBit 8, minWin=22, winSum=377
8146 09:26:10.447129 TX Vref=18, minBit 8, minWin=22, winSum=386
8147 09:26:10.450253 TX Vref=20, minBit 8, minWin=22, winSum=389
8148 09:26:10.454051 TX Vref=22, minBit 11, minWin=23, winSum=396
8149 09:26:10.457271 TX Vref=24, minBit 8, minWin=24, winSum=406
8150 09:26:10.463560 TX Vref=26, minBit 8, minWin=24, winSum=412
8151 09:26:10.466643 TX Vref=28, minBit 8, minWin=24, winSum=414
8152 09:26:10.470360 TX Vref=30, minBit 8, minWin=24, winSum=409
8153 09:26:10.473566 TX Vref=32, minBit 8, minWin=22, winSum=403
8154 09:26:10.476757 TX Vref=34, minBit 8, minWin=22, winSum=396
8155 09:26:10.479981 TX Vref=36, minBit 8, minWin=22, winSum=389
8156 09:26:10.486519 [TxChooseVref] Worse bit 8, Min win 24, Win sum 414, Final Vref 28
8157 09:26:10.486611
8158 09:26:10.490115 Final TX Range 0 Vref 28
8159 09:26:10.490211
8160 09:26:10.490293 ==
8161 09:26:10.493469 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 09:26:10.496815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 09:26:10.496936 ==
8164 09:26:10.499728
8165 09:26:10.499820
8166 09:26:10.499894 TX Vref Scan disable
8167 09:26:10.506785 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8168 09:26:10.506865 == TX Byte 0 ==
8169 09:26:10.510272 u2DelayCellOfst[0]=11 cells (3 PI)
8170 09:26:10.513599 u2DelayCellOfst[1]=15 cells (4 PI)
8171 09:26:10.516490 u2DelayCellOfst[2]=11 cells (3 PI)
8172 09:26:10.519997 u2DelayCellOfst[3]=11 cells (3 PI)
8173 09:26:10.523484 u2DelayCellOfst[4]=7 cells (2 PI)
8174 09:26:10.526612 u2DelayCellOfst[5]=0 cells (0 PI)
8175 09:26:10.529746 u2DelayCellOfst[6]=15 cells (4 PI)
8176 09:26:10.533480 u2DelayCellOfst[7]=15 cells (4 PI)
8177 09:26:10.536600 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8178 09:26:10.539648 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8179 09:26:10.543180 == TX Byte 1 ==
8180 09:26:10.546605 u2DelayCellOfst[8]=0 cells (0 PI)
8181 09:26:10.549520 u2DelayCellOfst[9]=0 cells (0 PI)
8182 09:26:10.553273 u2DelayCellOfst[10]=11 cells (3 PI)
8183 09:26:10.556448 u2DelayCellOfst[11]=7 cells (2 PI)
8184 09:26:10.559624 u2DelayCellOfst[12]=15 cells (4 PI)
8185 09:26:10.559702 u2DelayCellOfst[13]=11 cells (3 PI)
8186 09:26:10.562787 u2DelayCellOfst[14]=15 cells (4 PI)
8187 09:26:10.566006 u2DelayCellOfst[15]=11 cells (3 PI)
8188 09:26:10.572860 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8189 09:26:10.576065 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8190 09:26:10.576144 DramC Write-DBI on
8191 09:26:10.579834 ==
8192 09:26:10.582933 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 09:26:10.586115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 09:26:10.586194 ==
8195 09:26:10.586257
8196 09:26:10.586312
8197 09:26:10.589206 TX Vref Scan disable
8198 09:26:10.589283 == TX Byte 0 ==
8199 09:26:10.596259 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8200 09:26:10.596337 == TX Byte 1 ==
8201 09:26:10.599285 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8202 09:26:10.603009 DramC Write-DBI off
8203 09:26:10.603086
8204 09:26:10.603146 [DATLAT]
8205 09:26:10.605845 Freq=1600, CH0 RK1
8206 09:26:10.605922
8207 09:26:10.605981 DATLAT Default: 0xf
8208 09:26:10.609188 0, 0xFFFF, sum = 0
8209 09:26:10.609267 1, 0xFFFF, sum = 0
8210 09:26:10.612717 2, 0xFFFF, sum = 0
8211 09:26:10.612797 3, 0xFFFF, sum = 0
8212 09:26:10.615944 4, 0xFFFF, sum = 0
8213 09:26:10.616024 5, 0xFFFF, sum = 0
8214 09:26:10.619324 6, 0xFFFF, sum = 0
8215 09:26:10.622649 7, 0xFFFF, sum = 0
8216 09:26:10.622742 8, 0xFFFF, sum = 0
8217 09:26:10.625983 9, 0xFFFF, sum = 0
8218 09:26:10.626060 10, 0xFFFF, sum = 0
8219 09:26:10.629272 11, 0xFFFF, sum = 0
8220 09:26:10.629350 12, 0xFFFF, sum = 0
8221 09:26:10.632831 13, 0xCFFF, sum = 0
8222 09:26:10.632910 14, 0x0, sum = 1
8223 09:26:10.635747 15, 0x0, sum = 2
8224 09:26:10.635825 16, 0x0, sum = 3
8225 09:26:10.639555 17, 0x0, sum = 4
8226 09:26:10.639633 best_step = 15
8227 09:26:10.639692
8228 09:26:10.639748 ==
8229 09:26:10.642694 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 09:26:10.645754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 09:26:10.645833 ==
8232 09:26:10.648936 RX Vref Scan: 0
8233 09:26:10.649014
8234 09:26:10.652592 RX Vref 0 -> 0, step: 1
8235 09:26:10.652695
8236 09:26:10.652792 RX Delay 3 -> 252, step: 4
8237 09:26:10.659740 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8238 09:26:10.662907 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8239 09:26:10.666074 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8240 09:26:10.669250 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8241 09:26:10.673023 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8242 09:26:10.679202 iDelay=191, Bit 5, Center 110 (59 ~ 162) 104
8243 09:26:10.683005 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8244 09:26:10.686097 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8245 09:26:10.689376 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8246 09:26:10.692541 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8247 09:26:10.699434 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8248 09:26:10.702732 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8249 09:26:10.705847 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8250 09:26:10.709068 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8251 09:26:10.715956 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8252 09:26:10.719485 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8253 09:26:10.719563 ==
8254 09:26:10.722429 Dram Type= 6, Freq= 0, CH_0, rank 1
8255 09:26:10.725544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 09:26:10.725622 ==
8257 09:26:10.729471 DQS Delay:
8258 09:26:10.729548 DQS0 = 0, DQS1 = 0
8259 09:26:10.729608 DQM Delay:
8260 09:26:10.732150 DQM0 = 124, DQM1 = 117
8261 09:26:10.732227 DQ Delay:
8262 09:26:10.735815 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8263 09:26:10.739132 DQ4 =126, DQ5 =110, DQ6 =134, DQ7 =134
8264 09:26:10.742285 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8265 09:26:10.748841 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8266 09:26:10.748918
8267 09:26:10.748976
8268 09:26:10.749030
8269 09:26:10.752480 [DramC_TX_OE_Calibration] TA2
8270 09:26:10.756015 Original DQ_B0 (3 6) =30, OEN = 27
8271 09:26:10.756093 Original DQ_B1 (3 6) =30, OEN = 27
8272 09:26:10.758991 24, 0x0, End_B0=24 End_B1=24
8273 09:26:10.761983 25, 0x0, End_B0=25 End_B1=25
8274 09:26:10.765386 26, 0x0, End_B0=26 End_B1=26
8275 09:26:10.769106 27, 0x0, End_B0=27 End_B1=27
8276 09:26:10.769183 28, 0x0, End_B0=28 End_B1=28
8277 09:26:10.772304 29, 0x0, End_B0=29 End_B1=29
8278 09:26:10.775409 30, 0x0, End_B0=30 End_B1=30
8279 09:26:10.779037 31, 0x4141, End_B0=30 End_B1=30
8280 09:26:10.782279 Byte0 end_step=30 best_step=27
8281 09:26:10.782357 Byte1 end_step=30 best_step=27
8282 09:26:10.785345 Byte0 TX OE(2T, 0.5T) = (3, 3)
8283 09:26:10.788533 Byte1 TX OE(2T, 0.5T) = (3, 3)
8284 09:26:10.788610
8285 09:26:10.788710
8286 09:26:10.798453 [DQSOSCAuto] RK1, (LSB)MR18= 0x2614, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
8287 09:26:10.798531 CH0 RK1: MR19=303, MR18=2614
8288 09:26:10.805342 CH0_RK1: MR19=0x303, MR18=0x2614, DQSOSC=390, MR23=63, INC=24, DEC=16
8289 09:26:10.808467 [RxdqsGatingPostProcess] freq 1600
8290 09:26:10.814860 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8291 09:26:10.818713 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 09:26:10.821806 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 09:26:10.824874 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 09:26:10.828024 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 09:26:10.831640 best DQS0 dly(2T, 0.5T) = (1, 1)
8296 09:26:10.831716 best DQS1 dly(2T, 0.5T) = (1, 1)
8297 09:26:10.835113 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8298 09:26:10.838127 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8299 09:26:10.841830 Pre-setting of DQS Precalculation
8300 09:26:10.848244 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8301 09:26:10.848322 ==
8302 09:26:10.851727 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 09:26:10.854584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 09:26:10.854667 ==
8305 09:26:10.861491 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8306 09:26:10.864975 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8307 09:26:10.867928 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8308 09:26:10.875155 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8309 09:26:10.884030 [CA 0] Center 41 (12~71) winsize 60
8310 09:26:10.887109 [CA 1] Center 42 (12~72) winsize 61
8311 09:26:10.890357 [CA 2] Center 37 (9~66) winsize 58
8312 09:26:10.893626 [CA 3] Center 36 (7~66) winsize 60
8313 09:26:10.897370 [CA 4] Center 37 (8~66) winsize 59
8314 09:26:10.900431 [CA 5] Center 36 (7~66) winsize 60
8315 09:26:10.900524
8316 09:26:10.903996 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8317 09:26:10.904074
8318 09:26:10.907144 [CATrainingPosCal] consider 1 rank data
8319 09:26:10.910294 u2DelayCellTimex100 = 258/100 ps
8320 09:26:10.914047 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8321 09:26:10.920319 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8322 09:26:10.924101 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8323 09:26:10.927305 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8324 09:26:10.930399 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8325 09:26:10.934146 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8326 09:26:10.934224
8327 09:26:10.937325 CA PerBit enable=1, Macro0, CA PI delay=36
8328 09:26:10.937406
8329 09:26:10.940225 [CBTSetCACLKResult] CA Dly = 36
8330 09:26:10.943778 CS Dly: 9 (0~40)
8331 09:26:10.946970 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8332 09:26:10.950565 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8333 09:26:10.950653 ==
8334 09:26:10.953562 Dram Type= 6, Freq= 0, CH_1, rank 1
8335 09:26:10.957197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 09:26:10.957293 ==
8337 09:26:10.963952 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 09:26:10.966978 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 09:26:10.973811 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 09:26:10.977008 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 09:26:10.987399 [CA 0] Center 42 (13~71) winsize 59
8342 09:26:10.990723 [CA 1] Center 42 (12~72) winsize 61
8343 09:26:10.993851 [CA 2] Center 37 (8~66) winsize 59
8344 09:26:10.997172 [CA 3] Center 36 (7~66) winsize 60
8345 09:26:11.000791 [CA 4] Center 37 (7~67) winsize 61
8346 09:26:11.003861 [CA 5] Center 35 (5~66) winsize 62
8347 09:26:11.004220
8348 09:26:11.007000 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8349 09:26:11.007436
8350 09:26:11.010757 [CATrainingPosCal] consider 2 rank data
8351 09:26:11.013937 u2DelayCellTimex100 = 258/100 ps
8352 09:26:11.020335 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8353 09:26:11.023563 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8354 09:26:11.027357 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8355 09:26:11.030531 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8356 09:26:11.033669 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8357 09:26:11.037370 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8358 09:26:11.037933
8359 09:26:11.040704 CA PerBit enable=1, Macro0, CA PI delay=36
8360 09:26:11.041136
8361 09:26:11.043856 [CBTSetCACLKResult] CA Dly = 36
8362 09:26:11.046892 CS Dly: 10 (0~43)
8363 09:26:11.050497 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 09:26:11.053925 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 09:26:11.054356
8366 09:26:11.056979 ----->DramcWriteLeveling(PI) begin...
8367 09:26:11.057418 ==
8368 09:26:11.060361 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 09:26:11.066626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 09:26:11.067070 ==
8371 09:26:11.070200 Write leveling (Byte 0): 25 => 25
8372 09:26:11.073285 Write leveling (Byte 1): 30 => 30
8373 09:26:11.073714 DramcWriteLeveling(PI) end<-----
8374 09:26:11.074048
8375 09:26:11.076764 ==
8376 09:26:11.079692 Dram Type= 6, Freq= 0, CH_1, rank 0
8377 09:26:11.083160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 09:26:11.083594 ==
8379 09:26:11.086726 [Gating] SW mode calibration
8380 09:26:11.093127 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8381 09:26:11.096802 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8382 09:26:11.103383 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 09:26:11.106315 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 09:26:11.109610 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 09:26:11.116407 1 4 12 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
8386 09:26:11.119868 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 09:26:11.122862 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 09:26:11.129470 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 09:26:11.133078 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 09:26:11.136257 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 09:26:11.142634 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 09:26:11.146329 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 09:26:11.149482 1 5 12 | B1->B0 | 3232 3434 | 0 0 | (0 1) (0 1)
8394 09:26:11.156166 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8395 09:26:11.159648 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 09:26:11.162861 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 09:26:11.169445 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 09:26:11.172408 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 09:26:11.175661 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 09:26:11.182396 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 09:26:11.186047 1 6 12 | B1->B0 | 2e2e 2b2b | 0 0 | (0 0) (0 0)
8402 09:26:11.188943 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 09:26:11.195508 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 09:26:11.199035 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 09:26:11.202290 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 09:26:11.209070 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 09:26:11.212122 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 09:26:11.215268 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 09:26:11.222315 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8410 09:26:11.225253 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8411 09:26:11.228842 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 09:26:11.235392 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 09:26:11.238539 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 09:26:11.241731 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 09:26:11.248816 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 09:26:11.252030 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 09:26:11.255190 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 09:26:11.262023 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 09:26:11.265068 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 09:26:11.268047 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 09:26:11.275015 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 09:26:11.278207 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 09:26:11.281668 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 09:26:11.288067 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 09:26:11.291951 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8426 09:26:11.295122 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8427 09:26:11.301621 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 09:26:11.302219 Total UI for P1: 0, mck2ui 16
8429 09:26:11.304579 best dqsien dly found for B0: ( 1, 9, 14)
8430 09:26:11.308300 Total UI for P1: 0, mck2ui 16
8431 09:26:11.311534 best dqsien dly found for B1: ( 1, 9, 16)
8432 09:26:11.314775 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8433 09:26:11.321703 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8434 09:26:11.322311
8435 09:26:11.324698 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8436 09:26:11.328184 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8437 09:26:11.331264 [Gating] SW calibration Done
8438 09:26:11.331699 ==
8439 09:26:11.334900 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 09:26:11.337835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 09:26:11.338276 ==
8442 09:26:11.341519 RX Vref Scan: 0
8443 09:26:11.341955
8444 09:26:11.342291 RX Vref 0 -> 0, step: 1
8445 09:26:11.342602
8446 09:26:11.344600 RX Delay 0 -> 252, step: 8
8447 09:26:11.347690 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8448 09:26:11.354647 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8449 09:26:11.357877 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8450 09:26:11.361172 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8451 09:26:11.364185 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8452 09:26:11.367928 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8453 09:26:11.374131 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8454 09:26:11.377671 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8455 09:26:11.381144 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8456 09:26:11.383964 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8457 09:26:11.387531 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8458 09:26:11.393958 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8459 09:26:11.397287 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8460 09:26:11.400809 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8461 09:26:11.403935 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8462 09:26:11.407485 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8463 09:26:11.410530 ==
8464 09:26:11.414329 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 09:26:11.417304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 09:26:11.417741 ==
8467 09:26:11.418081 DQS Delay:
8468 09:26:11.420565 DQS0 = 0, DQS1 = 0
8469 09:26:11.421040 DQM Delay:
8470 09:26:11.423697 DQM0 = 132, DQM1 = 126
8471 09:26:11.424128 DQ Delay:
8472 09:26:11.427449 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8473 09:26:11.430380 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8474 09:26:11.433930 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8475 09:26:11.437130 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8476 09:26:11.437564
8477 09:26:11.437900
8478 09:26:11.438211 ==
8479 09:26:11.440611 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 09:26:11.447061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 09:26:11.447506 ==
8482 09:26:11.447847
8483 09:26:11.448159
8484 09:26:11.448452 TX Vref Scan disable
8485 09:26:11.450685 == TX Byte 0 ==
8486 09:26:11.453807 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8487 09:26:11.457637 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8488 09:26:11.460810 == TX Byte 1 ==
8489 09:26:11.463880 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8490 09:26:11.470651 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8491 09:26:11.471090 ==
8492 09:26:11.473910 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 09:26:11.477092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 09:26:11.477527 ==
8495 09:26:11.489638
8496 09:26:11.493182 TX Vref early break, caculate TX vref
8497 09:26:11.496541 TX Vref=16, minBit 11, minWin=19, winSum=359
8498 09:26:11.499371 TX Vref=18, minBit 8, minWin=21, winSum=371
8499 09:26:11.502911 TX Vref=20, minBit 8, minWin=22, winSum=385
8500 09:26:11.506193 TX Vref=22, minBit 8, minWin=23, winSum=391
8501 09:26:11.509517 TX Vref=24, minBit 8, minWin=23, winSum=399
8502 09:26:11.516106 TX Vref=26, minBit 11, minWin=24, winSum=409
8503 09:26:11.519545 TX Vref=28, minBit 9, minWin=24, winSum=413
8504 09:26:11.523214 TX Vref=30, minBit 8, minWin=24, winSum=408
8505 09:26:11.526149 TX Vref=32, minBit 9, minWin=23, winSum=401
8506 09:26:11.529870 TX Vref=34, minBit 1, minWin=23, winSum=391
8507 09:26:11.536071 [TxChooseVref] Worse bit 9, Min win 24, Win sum 413, Final Vref 28
8508 09:26:11.536513
8509 09:26:11.539736 Final TX Range 0 Vref 28
8510 09:26:11.540174
8511 09:26:11.540512 ==
8512 09:26:11.542849 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 09:26:11.545933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 09:26:11.546378 ==
8515 09:26:11.546718
8516 09:26:11.547028
8517 09:26:11.549601 TX Vref Scan disable
8518 09:26:11.556330 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8519 09:26:11.556789 == TX Byte 0 ==
8520 09:26:11.559411 u2DelayCellOfst[0]=18 cells (5 PI)
8521 09:26:11.562550 u2DelayCellOfst[1]=15 cells (4 PI)
8522 09:26:11.565707 u2DelayCellOfst[2]=0 cells (0 PI)
8523 09:26:11.568894 u2DelayCellOfst[3]=7 cells (2 PI)
8524 09:26:11.572581 u2DelayCellOfst[4]=7 cells (2 PI)
8525 09:26:11.575788 u2DelayCellOfst[5]=22 cells (6 PI)
8526 09:26:11.578854 u2DelayCellOfst[6]=18 cells (5 PI)
8527 09:26:11.582081 u2DelayCellOfst[7]=7 cells (2 PI)
8528 09:26:11.585776 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8529 09:26:11.588952 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8530 09:26:11.592213 == TX Byte 1 ==
8531 09:26:11.595362 u2DelayCellOfst[8]=0 cells (0 PI)
8532 09:26:11.598946 u2DelayCellOfst[9]=11 cells (3 PI)
8533 09:26:11.599465 u2DelayCellOfst[10]=15 cells (4 PI)
8534 09:26:11.602019 u2DelayCellOfst[11]=11 cells (3 PI)
8535 09:26:11.605601 u2DelayCellOfst[12]=15 cells (4 PI)
8536 09:26:11.608917 u2DelayCellOfst[13]=18 cells (5 PI)
8537 09:26:11.611998 u2DelayCellOfst[14]=18 cells (5 PI)
8538 09:26:11.615193 u2DelayCellOfst[15]=18 cells (5 PI)
8539 09:26:11.622229 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8540 09:26:11.625309 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8541 09:26:11.625745 DramC Write-DBI on
8542 09:26:11.626080 ==
8543 09:26:11.628919 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 09:26:11.635242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 09:26:11.635677 ==
8546 09:26:11.635989
8547 09:26:11.636273
8548 09:26:11.636830 TX Vref Scan disable
8549 09:26:11.639124 == TX Byte 0 ==
8550 09:26:11.642638 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8551 09:26:11.646030 == TX Byte 1 ==
8552 09:26:11.649409 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8553 09:26:11.652989 DramC Write-DBI off
8554 09:26:11.653562
8555 09:26:11.653914 [DATLAT]
8556 09:26:11.654236 Freq=1600, CH1 RK0
8557 09:26:11.654542
8558 09:26:11.655870 DATLAT Default: 0xf
8559 09:26:11.656306 0, 0xFFFF, sum = 0
8560 09:26:11.659566 1, 0xFFFF, sum = 0
8561 09:26:11.662434 2, 0xFFFF, sum = 0
8562 09:26:11.662874 3, 0xFFFF, sum = 0
8563 09:26:11.666258 4, 0xFFFF, sum = 0
8564 09:26:11.666698 5, 0xFFFF, sum = 0
8565 09:26:11.669415 6, 0xFFFF, sum = 0
8566 09:26:11.669857 7, 0xFFFF, sum = 0
8567 09:26:11.672605 8, 0xFFFF, sum = 0
8568 09:26:11.673136 9, 0xFFFF, sum = 0
8569 09:26:11.675702 10, 0xFFFF, sum = 0
8570 09:26:11.676140 11, 0xFFFF, sum = 0
8571 09:26:11.679515 12, 0xFFFF, sum = 0
8572 09:26:11.679990 13, 0x8FFF, sum = 0
8573 09:26:11.682666 14, 0x0, sum = 1
8574 09:26:11.683309 15, 0x0, sum = 2
8575 09:26:11.685848 16, 0x0, sum = 3
8576 09:26:11.686385 17, 0x0, sum = 4
8577 09:26:11.689131 best_step = 15
8578 09:26:11.689515
8579 09:26:11.689828 ==
8580 09:26:11.692254 Dram Type= 6, Freq= 0, CH_1, rank 0
8581 09:26:11.695489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8582 09:26:11.695933 ==
8583 09:26:11.699240 RX Vref Scan: 1
8584 09:26:11.699913
8585 09:26:11.700437 Set Vref Range= 24 -> 127
8586 09:26:11.701031
8587 09:26:11.702426 RX Vref 24 -> 127, step: 1
8588 09:26:11.702884
8589 09:26:11.705497 RX Delay 11 -> 252, step: 4
8590 09:26:11.705907
8591 09:26:11.709194 Set Vref, RX VrefLevel [Byte0]: 24
8592 09:26:11.711963 [Byte1]: 24
8593 09:26:11.712559
8594 09:26:11.715647 Set Vref, RX VrefLevel [Byte0]: 25
8595 09:26:11.718701 [Byte1]: 25
8596 09:26:11.722266
8597 09:26:11.722769 Set Vref, RX VrefLevel [Byte0]: 26
8598 09:26:11.725391 [Byte1]: 26
8599 09:26:11.729856
8600 09:26:11.730354 Set Vref, RX VrefLevel [Byte0]: 27
8601 09:26:11.732884 [Byte1]: 27
8602 09:26:11.737326
8603 09:26:11.737966 Set Vref, RX VrefLevel [Byte0]: 28
8604 09:26:11.740619 [Byte1]: 28
8605 09:26:11.745273
8606 09:26:11.745771 Set Vref, RX VrefLevel [Byte0]: 29
8607 09:26:11.751307 [Byte1]: 29
8608 09:26:11.751818
8609 09:26:11.754768 Set Vref, RX VrefLevel [Byte0]: 30
8610 09:26:11.758241 [Byte1]: 30
8611 09:26:11.758733
8612 09:26:11.761548 Set Vref, RX VrefLevel [Byte0]: 31
8613 09:26:11.764706 [Byte1]: 31
8614 09:26:11.765262
8615 09:26:11.767918 Set Vref, RX VrefLevel [Byte0]: 32
8616 09:26:11.771301 [Byte1]: 32
8617 09:26:11.775289
8618 09:26:11.775833 Set Vref, RX VrefLevel [Byte0]: 33
8619 09:26:11.778879 [Byte1]: 33
8620 09:26:11.783332
8621 09:26:11.783753 Set Vref, RX VrefLevel [Byte0]: 34
8622 09:26:11.786469 [Byte1]: 34
8623 09:26:11.790723
8624 09:26:11.791114 Set Vref, RX VrefLevel [Byte0]: 35
8625 09:26:11.793971 [Byte1]: 35
8626 09:26:11.798429
8627 09:26:11.798822 Set Vref, RX VrefLevel [Byte0]: 36
8628 09:26:11.801569 [Byte1]: 36
8629 09:26:11.805988
8630 09:26:11.806380 Set Vref, RX VrefLevel [Byte0]: 37
8631 09:26:11.809098 [Byte1]: 37
8632 09:26:11.813617
8633 09:26:11.814007 Set Vref, RX VrefLevel [Byte0]: 38
8634 09:26:11.816603 [Byte1]: 38
8635 09:26:11.820865
8636 09:26:11.821365 Set Vref, RX VrefLevel [Byte0]: 39
8637 09:26:11.824502 [Byte1]: 39
8638 09:26:11.828635
8639 09:26:11.829067 Set Vref, RX VrefLevel [Byte0]: 40
8640 09:26:11.831713 [Byte1]: 40
8641 09:26:11.836209
8642 09:26:11.836597 Set Vref, RX VrefLevel [Byte0]: 41
8643 09:26:11.839377 [Byte1]: 41
8644 09:26:11.843751
8645 09:26:11.844144 Set Vref, RX VrefLevel [Byte0]: 42
8646 09:26:11.847156 [Byte1]: 42
8647 09:26:11.851634
8648 09:26:11.852062 Set Vref, RX VrefLevel [Byte0]: 43
8649 09:26:11.855105 [Byte1]: 43
8650 09:26:11.859040
8651 09:26:11.859430 Set Vref, RX VrefLevel [Byte0]: 44
8652 09:26:11.862865 [Byte1]: 44
8653 09:26:11.866477
8654 09:26:11.866914 Set Vref, RX VrefLevel [Byte0]: 45
8655 09:26:11.870232 [Byte1]: 45
8656 09:26:11.874504
8657 09:26:11.874938 Set Vref, RX VrefLevel [Byte0]: 46
8658 09:26:11.877926 [Byte1]: 46
8659 09:26:11.882170
8660 09:26:11.882606 Set Vref, RX VrefLevel [Byte0]: 47
8661 09:26:11.885439 [Byte1]: 47
8662 09:26:11.889773
8663 09:26:11.890211 Set Vref, RX VrefLevel [Byte0]: 48
8664 09:26:11.892823 [Byte1]: 48
8665 09:26:11.897354
8666 09:26:11.897793 Set Vref, RX VrefLevel [Byte0]: 49
8667 09:26:11.900403 [Byte1]: 49
8668 09:26:11.904805
8669 09:26:11.905242 Set Vref, RX VrefLevel [Byte0]: 50
8670 09:26:11.907945 [Byte1]: 50
8671 09:26:11.912290
8672 09:26:11.912882 Set Vref, RX VrefLevel [Byte0]: 51
8673 09:26:11.915611 [Byte1]: 51
8674 09:26:11.920420
8675 09:26:11.920895 Set Vref, RX VrefLevel [Byte0]: 52
8676 09:26:11.923365 [Byte1]: 52
8677 09:26:11.927897
8678 09:26:11.928329 Set Vref, RX VrefLevel [Byte0]: 53
8679 09:26:11.931020 [Byte1]: 53
8680 09:26:11.935255
8681 09:26:11.935747 Set Vref, RX VrefLevel [Byte0]: 54
8682 09:26:11.938880 [Byte1]: 54
8683 09:26:11.942757
8684 09:26:11.943190 Set Vref, RX VrefLevel [Byte0]: 55
8685 09:26:11.946478 [Byte1]: 55
8686 09:26:11.950702
8687 09:26:11.951137 Set Vref, RX VrefLevel [Byte0]: 56
8688 09:26:11.953818 [Byte1]: 56
8689 09:26:11.958033
8690 09:26:11.958467 Set Vref, RX VrefLevel [Byte0]: 57
8691 09:26:11.964323 [Byte1]: 57
8692 09:26:11.964782
8693 09:26:11.967666 Set Vref, RX VrefLevel [Byte0]: 58
8694 09:26:11.971434 [Byte1]: 58
8695 09:26:11.971867
8696 09:26:11.974615 Set Vref, RX VrefLevel [Byte0]: 59
8697 09:26:11.977601 [Byte1]: 59
8698 09:26:11.977996
8699 09:26:11.981536 Set Vref, RX VrefLevel [Byte0]: 60
8700 09:26:11.984727 [Byte1]: 60
8701 09:26:11.988407
8702 09:26:11.989136 Set Vref, RX VrefLevel [Byte0]: 61
8703 09:26:11.992098 [Byte1]: 61
8704 09:26:11.996304
8705 09:26:11.996792 Set Vref, RX VrefLevel [Byte0]: 62
8706 09:26:11.999738 [Byte1]: 62
8707 09:26:12.003831
8708 09:26:12.004271 Set Vref, RX VrefLevel [Byte0]: 63
8709 09:26:12.007201 [Byte1]: 63
8710 09:26:12.011674
8711 09:26:12.012289 Set Vref, RX VrefLevel [Byte0]: 64
8712 09:26:12.014140 [Byte1]: 64
8713 09:26:12.018504
8714 09:26:12.018605 Set Vref, RX VrefLevel [Byte0]: 65
8715 09:26:12.021762 [Byte1]: 65
8716 09:26:12.026116
8717 09:26:12.026208 Set Vref, RX VrefLevel [Byte0]: 66
8718 09:26:12.029754 [Byte1]: 66
8719 09:26:12.033731
8720 09:26:12.033807 Set Vref, RX VrefLevel [Byte0]: 67
8721 09:26:12.036889 [Byte1]: 67
8722 09:26:12.041781
8723 09:26:12.041852 Set Vref, RX VrefLevel [Byte0]: 68
8724 09:26:12.044627 [Byte1]: 68
8725 09:26:12.049143
8726 09:26:12.049237 Set Vref, RX VrefLevel [Byte0]: 69
8727 09:26:12.052273 [Byte1]: 69
8728 09:26:12.056594
8729 09:26:12.056713 Set Vref, RX VrefLevel [Byte0]: 70
8730 09:26:12.060278 [Byte1]: 70
8731 09:26:12.064460
8732 09:26:12.064553 Set Vref, RX VrefLevel [Byte0]: 71
8733 09:26:12.067604 [Byte1]: 71
8734 09:26:12.071763
8735 09:26:12.071888 Set Vref, RX VrefLevel [Byte0]: 72
8736 09:26:12.075145 [Byte1]: 72
8737 09:26:12.079732
8738 09:26:12.079834 Final RX Vref Byte 0 = 58 to rank0
8739 09:26:12.082831 Final RX Vref Byte 1 = 51 to rank0
8740 09:26:12.085966 Final RX Vref Byte 0 = 58 to rank1
8741 09:26:12.089805 Final RX Vref Byte 1 = 51 to rank1==
8742 09:26:12.092874 Dram Type= 6, Freq= 0, CH_1, rank 0
8743 09:26:12.099727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8744 09:26:12.099806 ==
8745 09:26:12.099867 DQS Delay:
8746 09:26:12.102844 DQS0 = 0, DQS1 = 0
8747 09:26:12.102921 DQM Delay:
8748 09:26:12.102981 DQM0 = 131, DQM1 = 123
8749 09:26:12.105925 DQ Delay:
8750 09:26:12.109051 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =126
8751 09:26:12.112802 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =126
8752 09:26:12.115871 DQ8 =110, DQ9 =112, DQ10 =122, DQ11 =118
8753 09:26:12.118893 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =132
8754 09:26:12.118971
8755 09:26:12.119030
8756 09:26:12.119086
8757 09:26:12.122365 [DramC_TX_OE_Calibration] TA2
8758 09:26:12.125738 Original DQ_B0 (3 6) =30, OEN = 27
8759 09:26:12.129196 Original DQ_B1 (3 6) =30, OEN = 27
8760 09:26:12.132394 24, 0x0, End_B0=24 End_B1=24
8761 09:26:12.132543 25, 0x0, End_B0=25 End_B1=25
8762 09:26:12.135818 26, 0x0, End_B0=26 End_B1=26
8763 09:26:12.138829 27, 0x0, End_B0=27 End_B1=27
8764 09:26:12.141958 28, 0x0, End_B0=28 End_B1=28
8765 09:26:12.145686 29, 0x0, End_B0=29 End_B1=29
8766 09:26:12.145765 30, 0x0, End_B0=30 End_B1=30
8767 09:26:12.148816 31, 0x4141, End_B0=30 End_B1=30
8768 09:26:12.152406 Byte0 end_step=30 best_step=27
8769 09:26:12.155555 Byte1 end_step=30 best_step=27
8770 09:26:12.158766 Byte0 TX OE(2T, 0.5T) = (3, 3)
8771 09:26:12.162276 Byte1 TX OE(2T, 0.5T) = (3, 3)
8772 09:26:12.162371
8773 09:26:12.162457
8774 09:26:12.169076 [DQSOSCAuto] RK0, (LSB)MR18= 0x90e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
8775 09:26:12.172242 CH1 RK0: MR19=303, MR18=90E
8776 09:26:12.178417 CH1_RK0: MR19=0x303, MR18=0x90E, DQSOSC=402, MR23=63, INC=22, DEC=15
8777 09:26:12.178508
8778 09:26:12.181944 ----->DramcWriteLeveling(PI) begin...
8779 09:26:12.182017 ==
8780 09:26:12.185432 Dram Type= 6, Freq= 0, CH_1, rank 1
8781 09:26:12.188359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8782 09:26:12.188454 ==
8783 09:26:12.192071 Write leveling (Byte 0): 25 => 25
8784 09:26:12.195260 Write leveling (Byte 1): 27 => 27
8785 09:26:12.198742 DramcWriteLeveling(PI) end<-----
8786 09:26:12.198838
8787 09:26:12.198922 ==
8788 09:26:12.201975 Dram Type= 6, Freq= 0, CH_1, rank 1
8789 09:26:12.205208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8790 09:26:12.205275 ==
8791 09:26:12.208281 [Gating] SW mode calibration
8792 09:26:12.215233 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8793 09:26:12.221407 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8794 09:26:12.224693 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 09:26:12.231328 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 09:26:12.235184 1 4 8 | B1->B0 | 2424 3333 | 1 1 | (1 1) (1 1)
8797 09:26:12.238186 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
8798 09:26:12.245073 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 09:26:12.248271 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 09:26:12.251710 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 09:26:12.257927 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 09:26:12.261445 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 09:26:12.264628 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 09:26:12.271244 1 5 8 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
8805 09:26:12.275071 1 5 12 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
8806 09:26:12.278183 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 09:26:12.281457 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 09:26:12.288292 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 09:26:12.291302 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 09:26:12.294830 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 09:26:12.301395 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8812 09:26:12.304469 1 6 8 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
8813 09:26:12.308217 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8814 09:26:12.314505 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 09:26:12.317649 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 09:26:12.321384 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 09:26:12.327676 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 09:26:12.331449 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 09:26:12.334435 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 09:26:12.341236 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8821 09:26:12.344375 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8822 09:26:12.347568 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 09:26:12.354134 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 09:26:12.357574 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 09:26:12.361075 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 09:26:12.367267 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 09:26:12.371132 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 09:26:12.374353 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 09:26:12.381043 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 09:26:12.383993 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 09:26:12.387794 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 09:26:12.394353 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 09:26:12.397485 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 09:26:12.400539 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 09:26:12.407601 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8836 09:26:12.410594 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8837 09:26:12.413774 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8838 09:26:12.417540 Total UI for P1: 0, mck2ui 16
8839 09:26:12.420635 best dqsien dly found for B0: ( 1, 9, 6)
8840 09:26:12.427018 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 09:26:12.427097 Total UI for P1: 0, mck2ui 16
8842 09:26:12.430747 best dqsien dly found for B1: ( 1, 9, 12)
8843 09:26:12.437042 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8844 09:26:12.440182 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8845 09:26:12.440259
8846 09:26:12.443799 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8847 09:26:12.446887 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8848 09:26:12.450694 [Gating] SW calibration Done
8849 09:26:12.450771 ==
8850 09:26:12.453853 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 09:26:12.457023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 09:26:12.457101 ==
8853 09:26:12.460165 RX Vref Scan: 0
8854 09:26:12.460242
8855 09:26:12.460302 RX Vref 0 -> 0, step: 1
8856 09:26:12.460357
8857 09:26:12.463823 RX Delay 0 -> 252, step: 8
8858 09:26:12.466860 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8859 09:26:12.473798 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8860 09:26:12.476774 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8861 09:26:12.480252 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8862 09:26:12.483307 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8863 09:26:12.486552 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8864 09:26:12.490298 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8865 09:26:12.496709 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8866 09:26:12.500211 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8867 09:26:12.503621 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8868 09:26:12.506745 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8869 09:26:12.509885 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8870 09:26:12.516890 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8871 09:26:12.520322 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8872 09:26:12.523316 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8873 09:26:12.526490 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8874 09:26:12.526568 ==
8875 09:26:12.530219 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 09:26:12.536976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 09:26:12.537054 ==
8878 09:26:12.537114 DQS Delay:
8879 09:26:12.540061 DQS0 = 0, DQS1 = 0
8880 09:26:12.540138 DQM Delay:
8881 09:26:12.543160 DQM0 = 132, DQM1 = 128
8882 09:26:12.543237 DQ Delay:
8883 09:26:12.546945 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8884 09:26:12.549946 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =131
8885 09:26:12.553338 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8886 09:26:12.556511 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8887 09:26:12.556611
8888 09:26:12.556723
8889 09:26:12.556780 ==
8890 09:26:12.559824 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 09:26:12.566518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 09:26:12.566597 ==
8893 09:26:12.566657
8894 09:26:12.566713
8895 09:26:12.566766 TX Vref Scan disable
8896 09:26:12.569724 == TX Byte 0 ==
8897 09:26:12.572868 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8898 09:26:12.579805 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8899 09:26:12.579887 == TX Byte 1 ==
8900 09:26:12.582913 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8901 09:26:12.589773 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8902 09:26:12.589851 ==
8903 09:26:12.593008 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 09:26:12.596097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 09:26:12.596176 ==
8906 09:26:12.609024
8907 09:26:12.611778 TX Vref early break, caculate TX vref
8908 09:26:12.615503 TX Vref=16, minBit 0, minWin=23, winSum=388
8909 09:26:12.618490 TX Vref=18, minBit 0, minWin=24, winSum=396
8910 09:26:12.621995 TX Vref=20, minBit 0, minWin=23, winSum=402
8911 09:26:12.625055 TX Vref=22, minBit 0, minWin=24, winSum=414
8912 09:26:12.628554 TX Vref=24, minBit 0, minWin=25, winSum=423
8913 09:26:12.635231 TX Vref=26, minBit 0, minWin=25, winSum=429
8914 09:26:12.638379 TX Vref=28, minBit 5, minWin=25, winSum=430
8915 09:26:12.641807 TX Vref=30, minBit 0, minWin=25, winSum=423
8916 09:26:12.644928 TX Vref=32, minBit 5, minWin=24, winSum=414
8917 09:26:12.648789 TX Vref=34, minBit 1, minWin=24, winSum=404
8918 09:26:12.654794 [TxChooseVref] Worse bit 5, Min win 25, Win sum 430, Final Vref 28
8919 09:26:12.654872
8920 09:26:12.658542 Final TX Range 0 Vref 28
8921 09:26:12.658619
8922 09:26:12.658680 ==
8923 09:26:12.661339 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 09:26:12.664527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 09:26:12.664605 ==
8926 09:26:12.664693
8927 09:26:12.664765
8928 09:26:12.668310 TX Vref Scan disable
8929 09:26:12.674584 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8930 09:26:12.674661 == TX Byte 0 ==
8931 09:26:12.678329 u2DelayCellOfst[0]=18 cells (5 PI)
8932 09:26:12.681486 u2DelayCellOfst[1]=15 cells (4 PI)
8933 09:26:12.684565 u2DelayCellOfst[2]=0 cells (0 PI)
8934 09:26:12.687782 u2DelayCellOfst[3]=7 cells (2 PI)
8935 09:26:12.691624 u2DelayCellOfst[4]=7 cells (2 PI)
8936 09:26:12.694752 u2DelayCellOfst[5]=18 cells (5 PI)
8937 09:26:12.697849 u2DelayCellOfst[6]=18 cells (5 PI)
8938 09:26:12.700999 u2DelayCellOfst[7]=7 cells (2 PI)
8939 09:26:12.704827 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8940 09:26:12.707813 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8941 09:26:12.711304 == TX Byte 1 ==
8942 09:26:12.711383 u2DelayCellOfst[8]=0 cells (0 PI)
8943 09:26:12.714449 u2DelayCellOfst[9]=7 cells (2 PI)
8944 09:26:12.717698 u2DelayCellOfst[10]=15 cells (4 PI)
8945 09:26:12.721420 u2DelayCellOfst[11]=7 cells (2 PI)
8946 09:26:12.724515 u2DelayCellOfst[12]=15 cells (4 PI)
8947 09:26:12.727510 u2DelayCellOfst[13]=18 cells (5 PI)
8948 09:26:12.730923 u2DelayCellOfst[14]=22 cells (6 PI)
8949 09:26:12.734347 u2DelayCellOfst[15]=18 cells (5 PI)
8950 09:26:12.737727 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8951 09:26:12.744476 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8952 09:26:12.744578 DramC Write-DBI on
8953 09:26:12.744686 ==
8954 09:26:12.747342 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 09:26:12.754212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 09:26:12.754290 ==
8957 09:26:12.754351
8958 09:26:12.754407
8959 09:26:12.754460 TX Vref Scan disable
8960 09:26:12.758152 == TX Byte 0 ==
8961 09:26:12.761244 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8962 09:26:12.764392 == TX Byte 1 ==
8963 09:26:12.767961 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8964 09:26:12.770993 DramC Write-DBI off
8965 09:26:12.771069
8966 09:26:12.771129 [DATLAT]
8967 09:26:12.771185 Freq=1600, CH1 RK1
8968 09:26:12.771239
8969 09:26:12.774668 DATLAT Default: 0xf
8970 09:26:12.777779 0, 0xFFFF, sum = 0
8971 09:26:12.777857 1, 0xFFFF, sum = 0
8972 09:26:12.780846 2, 0xFFFF, sum = 0
8973 09:26:12.780924 3, 0xFFFF, sum = 0
8974 09:26:12.784521 4, 0xFFFF, sum = 0
8975 09:26:12.784624 5, 0xFFFF, sum = 0
8976 09:26:12.787757 6, 0xFFFF, sum = 0
8977 09:26:12.787825 7, 0xFFFF, sum = 0
8978 09:26:12.790902 8, 0xFFFF, sum = 0
8979 09:26:12.790994 9, 0xFFFF, sum = 0
8980 09:26:12.794136 10, 0xFFFF, sum = 0
8981 09:26:12.794201 11, 0xFFFF, sum = 0
8982 09:26:12.797898 12, 0xFFFF, sum = 0
8983 09:26:12.797986 13, 0x8FFF, sum = 0
8984 09:26:12.801171 14, 0x0, sum = 1
8985 09:26:12.801237 15, 0x0, sum = 2
8986 09:26:12.804242 16, 0x0, sum = 3
8987 09:26:12.804332 17, 0x0, sum = 4
8988 09:26:12.807394 best_step = 15
8989 09:26:12.807479
8990 09:26:12.807558 ==
8991 09:26:12.810783 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 09:26:12.814346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 09:26:12.814417 ==
8994 09:26:12.817459 RX Vref Scan: 0
8995 09:26:12.817555
8996 09:26:12.817649 RX Vref 0 -> 0, step: 1
8997 09:26:12.817741
8998 09:26:12.820981 RX Delay 11 -> 252, step: 4
8999 09:26:12.824008 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9000 09:26:12.830949 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9001 09:26:12.833937 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9002 09:26:12.837022 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9003 09:26:12.840649 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9004 09:26:12.847254 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9005 09:26:12.850429 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9006 09:26:12.853507 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9007 09:26:12.857361 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
9008 09:26:12.860465 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
9009 09:26:12.866854 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9010 09:26:12.870181 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9011 09:26:12.873448 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9012 09:26:12.877001 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
9013 09:26:12.880048 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9014 09:26:12.886828 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9015 09:26:12.886927 ==
9016 09:26:12.889986 Dram Type= 6, Freq= 0, CH_1, rank 1
9017 09:26:12.893638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9018 09:26:12.893780 ==
9019 09:26:12.893893 DQS Delay:
9020 09:26:12.896765 DQS0 = 0, DQS1 = 0
9021 09:26:12.896831 DQM Delay:
9022 09:26:12.899958 DQM0 = 130, DQM1 = 125
9023 09:26:12.900024 DQ Delay:
9024 09:26:12.903234 DQ0 =134, DQ1 =128, DQ2 =116, DQ3 =126
9025 09:26:12.906979 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =126
9026 09:26:12.910105 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =120
9027 09:26:12.913304 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
9028 09:26:12.913378
9029 09:26:12.916522
9030 09:26:12.916614
9031 09:26:12.916692 [DramC_TX_OE_Calibration] TA2
9032 09:26:12.919754 Original DQ_B0 (3 6) =30, OEN = 27
9033 09:26:12.923517 Original DQ_B1 (3 6) =30, OEN = 27
9034 09:26:12.926518 24, 0x0, End_B0=24 End_B1=24
9035 09:26:12.929957 25, 0x0, End_B0=25 End_B1=25
9036 09:26:12.933082 26, 0x0, End_B0=26 End_B1=26
9037 09:26:12.933177 27, 0x0, End_B0=27 End_B1=27
9038 09:26:12.936769 28, 0x0, End_B0=28 End_B1=28
9039 09:26:12.939961 29, 0x0, End_B0=29 End_B1=29
9040 09:26:12.942807 30, 0x0, End_B0=30 End_B1=30
9041 09:26:12.946302 31, 0x4141, End_B0=30 End_B1=30
9042 09:26:12.946402 Byte0 end_step=30 best_step=27
9043 09:26:12.949781 Byte1 end_step=30 best_step=27
9044 09:26:12.952773 Byte0 TX OE(2T, 0.5T) = (3, 3)
9045 09:26:12.956610 Byte1 TX OE(2T, 0.5T) = (3, 3)
9046 09:26:12.956725
9047 09:26:12.956781
9048 09:26:12.966067 [DQSOSCAuto] RK1, (LSB)MR18= 0x111d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9049 09:26:12.966137 CH1 RK1: MR19=303, MR18=111D
9050 09:26:12.972944 CH1_RK1: MR19=0x303, MR18=0x111D, DQSOSC=395, MR23=63, INC=23, DEC=15
9051 09:26:12.976197 [RxdqsGatingPostProcess] freq 1600
9052 09:26:12.983067 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9053 09:26:12.986040 best DQS0 dly(2T, 0.5T) = (1, 1)
9054 09:26:12.989681 best DQS1 dly(2T, 0.5T) = (1, 1)
9055 09:26:12.992804 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9056 09:26:12.992890 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9057 09:26:12.996160 best DQS0 dly(2T, 0.5T) = (1, 1)
9058 09:26:12.999673 best DQS1 dly(2T, 0.5T) = (1, 1)
9059 09:26:13.002934 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9060 09:26:13.005866 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9061 09:26:13.009182 Pre-setting of DQS Precalculation
9062 09:26:13.016189 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9063 09:26:13.022882 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9064 09:26:13.029175 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9065 09:26:13.029246
9066 09:26:13.029303
9067 09:26:13.032907 [Calibration Summary] 3200 Mbps
9068 09:26:13.032977 CH 0, Rank 0
9069 09:26:13.035940 SW Impedance : PASS
9070 09:26:13.039590 DUTY Scan : NO K
9071 09:26:13.039684 ZQ Calibration : PASS
9072 09:26:13.042698 Jitter Meter : NO K
9073 09:26:13.045884 CBT Training : PASS
9074 09:26:13.045949 Write leveling : PASS
9075 09:26:13.049391 RX DQS gating : PASS
9076 09:26:13.049480 RX DQ/DQS(RDDQC) : PASS
9077 09:26:13.052207 TX DQ/DQS : PASS
9078 09:26:13.055685 RX DATLAT : PASS
9079 09:26:13.055754 RX DQ/DQS(Engine): PASS
9080 09:26:13.059132 TX OE : PASS
9081 09:26:13.059223 All Pass.
9082 09:26:13.059305
9083 09:26:13.062258 CH 0, Rank 1
9084 09:26:13.062321 SW Impedance : PASS
9085 09:26:13.065485 DUTY Scan : NO K
9086 09:26:13.069250 ZQ Calibration : PASS
9087 09:26:13.069315 Jitter Meter : NO K
9088 09:26:13.072324 CBT Training : PASS
9089 09:26:13.075509 Write leveling : PASS
9090 09:26:13.075596 RX DQS gating : PASS
9091 09:26:13.079207 RX DQ/DQS(RDDQC) : PASS
9092 09:26:13.082335 TX DQ/DQS : PASS
9093 09:26:13.082428 RX DATLAT : PASS
9094 09:26:13.085530 RX DQ/DQS(Engine): PASS
9095 09:26:13.088635 TX OE : PASS
9096 09:26:13.088738 All Pass.
9097 09:26:13.088793
9098 09:26:13.088845 CH 1, Rank 0
9099 09:26:13.092475 SW Impedance : PASS
9100 09:26:13.095534 DUTY Scan : NO K
9101 09:26:13.095619 ZQ Calibration : PASS
9102 09:26:13.098669 Jitter Meter : NO K
9103 09:26:13.102098 CBT Training : PASS
9104 09:26:13.102178 Write leveling : PASS
9105 09:26:13.105722 RX DQS gating : PASS
9106 09:26:13.105798 RX DQ/DQS(RDDQC) : PASS
9107 09:26:13.108846 TX DQ/DQS : PASS
9108 09:26:13.112007 RX DATLAT : PASS
9109 09:26:13.112085 RX DQ/DQS(Engine): PASS
9110 09:26:13.115733 TX OE : PASS
9111 09:26:13.115810 All Pass.
9112 09:26:13.115869
9113 09:26:13.118646 CH 1, Rank 1
9114 09:26:13.118724 SW Impedance : PASS
9115 09:26:13.122280 DUTY Scan : NO K
9116 09:26:13.125718 ZQ Calibration : PASS
9117 09:26:13.125795 Jitter Meter : NO K
9118 09:26:13.128933 CBT Training : PASS
9119 09:26:13.132299 Write leveling : PASS
9120 09:26:13.132376 RX DQS gating : PASS
9121 09:26:13.135228 RX DQ/DQS(RDDQC) : PASS
9122 09:26:13.138591 TX DQ/DQS : PASS
9123 09:26:13.138669 RX DATLAT : PASS
9124 09:26:13.141959 RX DQ/DQS(Engine): PASS
9125 09:26:13.145416 TX OE : PASS
9126 09:26:13.145494 All Pass.
9127 09:26:13.145553
9128 09:26:13.145609 DramC Write-DBI on
9129 09:26:13.148901 PER_BANK_REFRESH: Hybrid Mode
9130 09:26:13.152061 TX_TRACKING: ON
9131 09:26:13.158834 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9132 09:26:13.168787 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9133 09:26:13.175051 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9134 09:26:13.178754 [FAST_K] Save calibration result to emmc
9135 09:26:13.181954 sync common calibartion params.
9136 09:26:13.182031 sync cbt_mode0:1, 1:1
9137 09:26:13.185027 dram_init: ddr_geometry: 2
9138 09:26:13.188994 dram_init: ddr_geometry: 2
9139 09:26:13.192153 dram_init: ddr_geometry: 2
9140 09:26:13.192230 0:dram_rank_size:100000000
9141 09:26:13.195269 1:dram_rank_size:100000000
9142 09:26:13.201665 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9143 09:26:13.201742 DFS_SHUFFLE_HW_MODE: ON
9144 09:26:13.208295 dramc_set_vcore_voltage set vcore to 725000
9145 09:26:13.208424 Read voltage for 1600, 0
9146 09:26:13.211660 Vio18 = 0
9147 09:26:13.211737 Vcore = 725000
9148 09:26:13.211796 Vdram = 0
9149 09:26:13.215255 Vddq = 0
9150 09:26:13.215354 Vmddr = 0
9151 09:26:13.218378 switch to 3200 Mbps bootup
9152 09:26:13.218446 [DramcRunTimeConfig]
9153 09:26:13.218503 PHYPLL
9154 09:26:13.221447 DPM_CONTROL_AFTERK: ON
9155 09:26:13.225223 PER_BANK_REFRESH: ON
9156 09:26:13.225315 REFRESH_OVERHEAD_REDUCTION: ON
9157 09:26:13.228426 CMD_PICG_NEW_MODE: OFF
9158 09:26:13.231517 XRTWTW_NEW_MODE: ON
9159 09:26:13.231605 XRTRTR_NEW_MODE: ON
9160 09:26:13.234701 TX_TRACKING: ON
9161 09:26:13.234795 RDSEL_TRACKING: OFF
9162 09:26:13.238295 DQS Precalculation for DVFS: ON
9163 09:26:13.238390 RX_TRACKING: OFF
9164 09:26:13.241364 HW_GATING DBG: ON
9165 09:26:13.241431 ZQCS_ENABLE_LP4: ON
9166 09:26:13.245010 RX_PICG_NEW_MODE: ON
9167 09:26:13.247988 TX_PICG_NEW_MODE: ON
9168 09:26:13.248078 ENABLE_RX_DCM_DPHY: ON
9169 09:26:13.251627 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9170 09:26:13.254565 DUMMY_READ_FOR_TRACKING: OFF
9171 09:26:13.257928 !!! SPM_CONTROL_AFTERK: OFF
9172 09:26:13.261514 !!! SPM could not control APHY
9173 09:26:13.261612 IMPEDANCE_TRACKING: ON
9174 09:26:13.264851 TEMP_SENSOR: ON
9175 09:26:13.264947 HW_SAVE_FOR_SR: OFF
9176 09:26:13.267794 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9177 09:26:13.271147 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9178 09:26:13.274512 Read ODT Tracking: ON
9179 09:26:13.274603 Refresh Rate DeBounce: ON
9180 09:26:13.277798 DFS_NO_QUEUE_FLUSH: ON
9181 09:26:13.281485 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9182 09:26:13.284627 ENABLE_DFS_RUNTIME_MRW: OFF
9183 09:26:13.287864 DDR_RESERVE_NEW_MODE: ON
9184 09:26:13.287958 MR_CBT_SWITCH_FREQ: ON
9185 09:26:13.291062 =========================
9186 09:26:13.309202 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9187 09:26:13.313055 dram_init: ddr_geometry: 2
9188 09:26:13.330940 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9189 09:26:13.334065 dram_init: dram init end (result: 0)
9190 09:26:13.340859 DRAM-K: Full calibration passed in 24543 msecs
9191 09:26:13.343931 MRC: failed to locate region type 0.
9192 09:26:13.344005 DRAM rank0 size:0x100000000,
9193 09:26:13.347706 DRAM rank1 size=0x100000000
9194 09:26:13.357062 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9195 09:26:13.363755 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9196 09:26:13.370440 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9197 09:26:13.377188 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9198 09:26:13.380811 DRAM rank0 size:0x100000000,
9199 09:26:13.383848 DRAM rank1 size=0x100000000
9200 09:26:13.383946 CBMEM:
9201 09:26:13.386920 IMD: root @ 0xfffff000 254 entries.
9202 09:26:13.390237 IMD: root @ 0xffffec00 62 entries.
9203 09:26:13.393863 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9204 09:26:13.400785 WARNING: RO_VPD is uninitialized or empty.
9205 09:26:13.403984 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9206 09:26:13.410936 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9207 09:26:13.424000 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9208 09:26:13.435457 BS: romstage times (exec / console): total (unknown) / 24011 ms
9209 09:26:13.435536
9210 09:26:13.435597
9211 09:26:13.444986 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9212 09:26:13.448640 ARM64: Exception handlers installed.
9213 09:26:13.451564 ARM64: Testing exception
9214 09:26:13.455252 ARM64: Done test exception
9215 09:26:13.455316 Enumerating buses...
9216 09:26:13.458319 Show all devs... Before device enumeration.
9217 09:26:13.461513 Root Device: enabled 1
9218 09:26:13.465275 CPU_CLUSTER: 0: enabled 1
9219 09:26:13.465339 CPU: 00: enabled 1
9220 09:26:13.468329 Compare with tree...
9221 09:26:13.468391 Root Device: enabled 1
9222 09:26:13.471516 CPU_CLUSTER: 0: enabled 1
9223 09:26:13.474732 CPU: 00: enabled 1
9224 09:26:13.474819 Root Device scanning...
9225 09:26:13.478411 scan_static_bus for Root Device
9226 09:26:13.481333 CPU_CLUSTER: 0 enabled
9227 09:26:13.484930 scan_static_bus for Root Device done
9228 09:26:13.488544 scan_bus: bus Root Device finished in 8 msecs
9229 09:26:13.488636 done
9230 09:26:13.495014 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9231 09:26:13.498268 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9232 09:26:13.505269 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9233 09:26:13.508413 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9234 09:26:13.511667 Allocating resources...
9235 09:26:13.511732 Reading resources...
9236 09:26:13.518042 Root Device read_resources bus 0 link: 0
9237 09:26:13.518109 DRAM rank0 size:0x100000000,
9238 09:26:13.521724 DRAM rank1 size=0x100000000
9239 09:26:13.525020 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9240 09:26:13.528051 CPU: 00 missing read_resources
9241 09:26:13.531326 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9242 09:26:13.538146 Root Device read_resources bus 0 link: 0 done
9243 09:26:13.538214 Done reading resources.
9244 09:26:13.544724 Show resources in subtree (Root Device)...After reading.
9245 09:26:13.547819 Root Device child on link 0 CPU_CLUSTER: 0
9246 09:26:13.551639 CPU_CLUSTER: 0 child on link 0 CPU: 00
9247 09:26:13.561062 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9248 09:26:13.561140 CPU: 00
9249 09:26:13.564631 Root Device assign_resources, bus 0 link: 0
9250 09:26:13.567744 CPU_CLUSTER: 0 missing set_resources
9251 09:26:13.574476 Root Device assign_resources, bus 0 link: 0 done
9252 09:26:13.574545 Done setting resources.
9253 09:26:13.581376 Show resources in subtree (Root Device)...After assigning values.
9254 09:26:13.584572 Root Device child on link 0 CPU_CLUSTER: 0
9255 09:26:13.587704 CPU_CLUSTER: 0 child on link 0 CPU: 00
9256 09:26:13.597984 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9257 09:26:13.598058 CPU: 00
9258 09:26:13.601151 Done allocating resources.
9259 09:26:13.604294 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9260 09:26:13.607621 Enabling resources...
9261 09:26:13.607712 done.
9262 09:26:13.614109 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9263 09:26:13.614202 Initializing devices...
9264 09:26:13.617838 Root Device init
9265 09:26:13.617907 init hardware done!
9266 09:26:13.620983 0x00000018: ctrlr->caps
9267 09:26:13.624206 52.000 MHz: ctrlr->f_max
9268 09:26:13.624299 0.400 MHz: ctrlr->f_min
9269 09:26:13.627373 0x40ff8080: ctrlr->voltages
9270 09:26:13.630521 sclk: 390625
9271 09:26:13.630585 Bus Width = 1
9272 09:26:13.630638 sclk: 390625
9273 09:26:13.633753 Bus Width = 1
9274 09:26:13.633815 Early init status = 3
9275 09:26:13.640556 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9276 09:26:13.643722 in-header: 03 fc 00 00 01 00 00 00
9277 09:26:13.647461 in-data: 00
9278 09:26:13.650378 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9279 09:26:13.655945 in-header: 03 fd 00 00 00 00 00 00
9280 09:26:13.659353 in-data:
9281 09:26:13.662321 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9282 09:26:13.666973 in-header: 03 fc 00 00 01 00 00 00
9283 09:26:13.670067 in-data: 00
9284 09:26:13.673704 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9285 09:26:13.679289 in-header: 03 fd 00 00 00 00 00 00
9286 09:26:13.682462 in-data:
9287 09:26:13.685633 [SSUSB] Setting up USB HOST controller...
9288 09:26:13.688830 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9289 09:26:13.692581 [SSUSB] phy power-on done.
9290 09:26:13.695761 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9291 09:26:13.702453 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9292 09:26:13.705420 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9293 09:26:13.712079 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9294 09:26:13.718666 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9295 09:26:13.725676 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9296 09:26:13.732325 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9297 09:26:13.738668 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9298 09:26:13.741899 SPM: binary array size = 0x9dc
9299 09:26:13.745028 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9300 09:26:13.751941 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9301 09:26:13.758215 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9302 09:26:13.764844 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9303 09:26:13.768559 configure_display: Starting display init
9304 09:26:13.802321 anx7625_power_on_init: Init interface.
9305 09:26:13.805474 anx7625_disable_pd_protocol: Disabled PD feature.
9306 09:26:13.809157 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9307 09:26:13.836952 anx7625_start_dp_work: Secure OCM version=00
9308 09:26:13.839799 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9309 09:26:13.854820 sp_tx_get_edid_block: EDID Block = 1
9310 09:26:13.957594 Extracted contents:
9311 09:26:13.960786 header: 00 ff ff ff ff ff ff 00
9312 09:26:13.963946 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9313 09:26:13.967082 version: 01 04
9314 09:26:13.970746 basic params: 95 1f 11 78 0a
9315 09:26:13.973756 chroma info: 76 90 94 55 54 90 27 21 50 54
9316 09:26:13.977469 established: 00 00 00
9317 09:26:13.983839 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9318 09:26:13.987277 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9319 09:26:13.993367 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9320 09:26:14.000349 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9321 09:26:14.006837 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9322 09:26:14.010254 extensions: 00
9323 09:26:14.010331 checksum: fb
9324 09:26:14.010392
9325 09:26:14.013674 Manufacturer: IVO Model 57d Serial Number 0
9326 09:26:14.016762 Made week 0 of 2020
9327 09:26:14.020345 EDID version: 1.4
9328 09:26:14.020422 Digital display
9329 09:26:14.023531 6 bits per primary color channel
9330 09:26:14.023609 DisplayPort interface
9331 09:26:14.026724 Maximum image size: 31 cm x 17 cm
9332 09:26:14.029933 Gamma: 220%
9333 09:26:14.030010 Check DPMS levels
9334 09:26:14.033623 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9335 09:26:14.040146 First detailed timing is preferred timing
9336 09:26:14.040223 Established timings supported:
9337 09:26:14.043192 Standard timings supported:
9338 09:26:14.046317 Detailed timings
9339 09:26:14.049438 Hex of detail: 383680a07038204018303c0035ae10000019
9340 09:26:14.056352 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9341 09:26:14.059882 0780 0798 07c8 0820 hborder 0
9342 09:26:14.063141 0438 043b 0447 0458 vborder 0
9343 09:26:14.066493 -hsync -vsync
9344 09:26:14.066570 Did detailed timing
9345 09:26:14.072682 Hex of detail: 000000000000000000000000000000000000
9346 09:26:14.076510 Manufacturer-specified data, tag 0
9347 09:26:14.079782 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9348 09:26:14.082904 ASCII string: InfoVision
9349 09:26:14.086019 Hex of detail: 000000fe00523134304e574635205248200a
9350 09:26:14.089880 ASCII string: R140NWF5 RH
9351 09:26:14.089963 Checksum
9352 09:26:14.092750 Checksum: 0xfb (valid)
9353 09:26:14.096342 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9354 09:26:14.099163 DSI data_rate: 832800000 bps
9355 09:26:14.106065 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9356 09:26:14.109085 anx7625_parse_edid: pixelclock(138800).
9357 09:26:14.112719 hactive(1920), hsync(48), hfp(24), hbp(88)
9358 09:26:14.115825 vactive(1080), vsync(12), vfp(3), vbp(17)
9359 09:26:14.118775 anx7625_dsi_config: config dsi.
9360 09:26:14.125422 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9361 09:26:14.139236 anx7625_dsi_config: success to config DSI
9362 09:26:14.142906 anx7625_dp_start: MIPI phy setup OK.
9363 09:26:14.145819 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9364 09:26:14.149152 mtk_ddp_mode_set invalid vrefresh 60
9365 09:26:14.152567 main_disp_path_setup
9366 09:26:14.152667 ovl_layer_smi_id_en
9367 09:26:14.155684 ovl_layer_smi_id_en
9368 09:26:14.155760 ccorr_config
9369 09:26:14.155821 aal_config
9370 09:26:14.159491 gamma_config
9371 09:26:14.159567 postmask_config
9372 09:26:14.162560 dither_config
9373 09:26:14.165666 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9374 09:26:14.172337 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9375 09:26:14.175657 Root Device init finished in 555 msecs
9376 09:26:14.179038 CPU_CLUSTER: 0 init
9377 09:26:14.185472 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9378 09:26:14.192355 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9379 09:26:14.192432 APU_MBOX 0x190000b0 = 0x10001
9380 09:26:14.195594 APU_MBOX 0x190001b0 = 0x10001
9381 09:26:14.198717 APU_MBOX 0x190005b0 = 0x10001
9382 09:26:14.202347 APU_MBOX 0x190006b0 = 0x10001
9383 09:26:14.208996 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9384 09:26:14.218284 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9385 09:26:14.231137 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9386 09:26:14.237167 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9387 09:26:14.249162 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9388 09:26:14.258291 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9389 09:26:14.261189 CPU_CLUSTER: 0 init finished in 81 msecs
9390 09:26:14.264510 Devices initialized
9391 09:26:14.267951 Show all devs... After init.
9392 09:26:14.268044 Root Device: enabled 1
9393 09:26:14.271205 CPU_CLUSTER: 0: enabled 1
9394 09:26:14.274344 CPU: 00: enabled 1
9395 09:26:14.278094 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9396 09:26:14.281161 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9397 09:26:14.284664 ELOG: NV offset 0x57f000 size 0x1000
9398 09:26:14.291588 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9399 09:26:14.297825 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9400 09:26:14.300915 ELOG: Event(17) added with size 13 at 2024-06-18 09:26:14 UTC
9401 09:26:14.307799 out: cmd=0x121: 03 db 21 01 00 00 00 00
9402 09:26:14.311340 in-header: 03 b2 00 00 2c 00 00 00
9403 09:26:14.321045 in-data: 8b 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9404 09:26:14.327800 ELOG: Event(A1) added with size 10 at 2024-06-18 09:26:14 UTC
9405 09:26:14.333882 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9406 09:26:14.340838 ELOG: Event(A0) added with size 9 at 2024-06-18 09:26:14 UTC
9407 09:26:14.343975 elog_add_boot_reason: Logged dev mode boot
9408 09:26:14.350475 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9409 09:26:14.350558 Finalize devices...
9410 09:26:14.354100 Devices finalized
9411 09:26:14.357276 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9412 09:26:14.360420 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9413 09:26:14.364112 in-header: 03 07 00 00 08 00 00 00
9414 09:26:14.367279 in-data: aa e4 47 04 13 02 00 00
9415 09:26:14.370332 Chrome EC: UHEPI supported
9416 09:26:14.376852 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9417 09:26:14.380153 in-header: 03 a9 00 00 08 00 00 00
9418 09:26:14.383823 in-data: 84 60 60 08 00 00 00 00
9419 09:26:14.390140 ELOG: Event(91) added with size 10 at 2024-06-18 09:26:14 UTC
9420 09:26:14.393404 Chrome EC: clear events_b mask to 0x0000000020004000
9421 09:26:14.400536 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9422 09:26:14.404311 in-header: 03 fd 00 00 00 00 00 00
9423 09:26:14.404400 in-data:
9424 09:26:14.411100 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9425 09:26:14.414286 Writing coreboot table at 0xffe64000
9426 09:26:14.417359 0. 000000000010a000-0000000000113fff: RAMSTAGE
9427 09:26:14.420893 1. 0000000040000000-00000000400fffff: RAM
9428 09:26:14.427452 2. 0000000040100000-000000004032afff: RAMSTAGE
9429 09:26:14.430633 3. 000000004032b000-00000000545fffff: RAM
9430 09:26:14.433706 4. 0000000054600000-000000005465ffff: BL31
9431 09:26:14.437643 5. 0000000054660000-00000000ffe63fff: RAM
9432 09:26:14.443923 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9433 09:26:14.447047 7. 0000000100000000-000000023fffffff: RAM
9434 09:26:14.450788 Passing 5 GPIOs to payload:
9435 09:26:14.453934 NAME | PORT | POLARITY | VALUE
9436 09:26:14.456887 EC in RW | 0x000000aa | low | undefined
9437 09:26:14.463459 EC interrupt | 0x00000005 | low | undefined
9438 09:26:14.467253 TPM interrupt | 0x000000ab | high | undefined
9439 09:26:14.473668 SD card detect | 0x00000011 | high | undefined
9440 09:26:14.476843 speaker enable | 0x00000093 | high | undefined
9441 09:26:14.480472 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9442 09:26:14.483526 in-header: 03 f9 00 00 02 00 00 00
9443 09:26:14.487110 in-data: 02 00
9444 09:26:14.487228 ADC[4]: Raw value=895191 ID=7
9445 09:26:14.490516 ADC[3]: Raw value=213440 ID=1
9446 09:26:14.493372 RAM Code: 0x71
9447 09:26:14.493483 ADC[6]: Raw value=74352 ID=0
9448 09:26:14.496561 ADC[5]: Raw value=211960 ID=1
9449 09:26:14.500305 SKU Code: 0x1
9450 09:26:14.503458 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ab69
9451 09:26:14.507071 coreboot table: 964 bytes.
9452 09:26:14.510071 IMD ROOT 0. 0xfffff000 0x00001000
9453 09:26:14.513485 IMD SMALL 1. 0xffffe000 0x00001000
9454 09:26:14.516849 RO MCACHE 2. 0xffffc000 0x00001104
9455 09:26:14.519856 CONSOLE 3. 0xfff7c000 0x00080000
9456 09:26:14.523104 FMAP 4. 0xfff7b000 0x00000452
9457 09:26:14.526664 TIME STAMP 5. 0xfff7a000 0x00000910
9458 09:26:14.529716 VBOOT WORK 6. 0xfff66000 0x00014000
9459 09:26:14.533248 RAMOOPS 7. 0xffe66000 0x00100000
9460 09:26:14.536608 COREBOOT 8. 0xffe64000 0x00002000
9461 09:26:14.536733 IMD small region:
9462 09:26:14.542851 IMD ROOT 0. 0xffffec00 0x00000400
9463 09:26:14.546639 VPD 1. 0xffffeb80 0x0000006c
9464 09:26:14.549769 MMC STATUS 2. 0xffffeb60 0x00000004
9465 09:26:14.552930 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9466 09:26:14.559770 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9467 09:26:14.600181 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9468 09:26:14.603542 Checking segment from ROM address 0x40100000
9469 09:26:14.610327 Checking segment from ROM address 0x4010001c
9470 09:26:14.613507 Loading segment from ROM address 0x40100000
9471 09:26:14.613575 code (compression=0)
9472 09:26:14.623012 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9473 09:26:14.629843 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9474 09:26:14.629935 it's not compressed!
9475 09:26:14.636077 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9476 09:26:14.642647 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9477 09:26:14.660243 Loading segment from ROM address 0x4010001c
9478 09:26:14.660321 Entry Point 0x80000000
9479 09:26:14.664047 Loaded segments
9480 09:26:14.667238 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9481 09:26:14.673475 Jumping to boot code at 0x80000000(0xffe64000)
9482 09:26:14.680612 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9483 09:26:14.687174 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9484 09:26:14.694723 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9485 09:26:14.698623 Checking segment from ROM address 0x40100000
9486 09:26:14.701763 Checking segment from ROM address 0x4010001c
9487 09:26:14.707967 Loading segment from ROM address 0x40100000
9488 09:26:14.708034 code (compression=1)
9489 09:26:14.714662 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9490 09:26:14.724913 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9491 09:26:14.725016 using LZMA
9492 09:26:14.733084 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9493 09:26:14.740125 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9494 09:26:14.743201 Loading segment from ROM address 0x4010001c
9495 09:26:14.743279 Entry Point 0x54601000
9496 09:26:14.746403 Loaded segments
9497 09:26:14.750078 NOTICE: MT8192 bl31_setup
9498 09:26:14.756933 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9499 09:26:14.760447 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9500 09:26:14.763591 WARNING: region 0:
9501 09:26:14.766807 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 09:26:14.766879 WARNING: region 1:
9503 09:26:14.773901 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9504 09:26:14.777010 WARNING: region 2:
9505 09:26:14.780241 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9506 09:26:14.783375 WARNING: region 3:
9507 09:26:14.786932 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9508 09:26:14.790336 WARNING: region 4:
9509 09:26:14.797057 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9510 09:26:14.797134 WARNING: region 5:
9511 09:26:14.800213 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 09:26:14.803328 WARNING: region 6:
9513 09:26:14.807148 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 09:26:14.810279 WARNING: region 7:
9515 09:26:14.813465 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9516 09:26:14.819691 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9517 09:26:14.823167 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9518 09:26:14.826721 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9519 09:26:14.833411 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9520 09:26:14.836650 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9521 09:26:14.842937 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9522 09:26:14.846129 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9523 09:26:14.849991 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9524 09:26:14.856203 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9525 09:26:14.859897 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9526 09:26:14.862904 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9527 09:26:14.869423 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9528 09:26:14.872557 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9529 09:26:14.879293 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9530 09:26:14.883029 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9531 09:26:14.886213 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9532 09:26:14.892517 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9533 09:26:14.896178 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9534 09:26:14.902739 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9535 09:26:14.905848 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9536 09:26:14.908894 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9537 09:26:14.915946 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9538 09:26:14.918984 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9539 09:26:14.925342 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9540 09:26:14.929004 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9541 09:26:14.932143 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9542 09:26:14.939074 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9543 09:26:14.942235 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9544 09:26:14.949095 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9545 09:26:14.952438 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9546 09:26:14.955712 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9547 09:26:14.962196 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9548 09:26:14.965352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9549 09:26:14.969157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9550 09:26:14.972142 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9551 09:26:14.978808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9552 09:26:14.982443 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9553 09:26:14.985598 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9554 09:26:14.989249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9555 09:26:14.995696 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9556 09:26:14.998832 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9557 09:26:15.001905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9558 09:26:15.005695 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9559 09:26:15.011980 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9560 09:26:15.015144 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9561 09:26:15.018378 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9562 09:26:15.025431 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9563 09:26:15.028619 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9564 09:26:15.031759 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9565 09:26:15.038052 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9566 09:26:15.041897 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9567 09:26:15.048068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9568 09:26:15.051215 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9569 09:26:15.055068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9570 09:26:15.061285 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9571 09:26:15.064864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9572 09:26:15.071075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9573 09:26:15.074397 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9574 09:26:15.081106 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9575 09:26:15.084679 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9576 09:26:15.091018 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9577 09:26:15.094295 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9578 09:26:15.101142 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9579 09:26:15.104266 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9580 09:26:15.107417 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9581 09:26:15.114081 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9582 09:26:15.117241 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9583 09:26:15.123846 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9584 09:26:15.127340 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9585 09:26:15.134083 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9586 09:26:15.137220 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9587 09:26:15.144058 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9588 09:26:15.147196 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9589 09:26:15.150285 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9590 09:26:15.157282 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9591 09:26:15.160441 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9592 09:26:15.166642 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9593 09:26:15.170348 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9594 09:26:15.176896 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9595 09:26:15.179908 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9596 09:26:15.186659 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9597 09:26:15.190405 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9598 09:26:15.193323 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9599 09:26:15.199932 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9600 09:26:15.203266 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9601 09:26:15.209791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9602 09:26:15.213297 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9603 09:26:15.219608 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9604 09:26:15.223370 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9605 09:26:15.226534 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9606 09:26:15.233417 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9607 09:26:15.236434 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9608 09:26:15.243054 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9609 09:26:15.246294 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9610 09:26:15.253239 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9611 09:26:15.256375 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9612 09:26:15.259628 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9613 09:26:15.266530 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9614 09:26:15.269527 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9615 09:26:15.272674 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9616 09:26:15.275842 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9617 09:26:15.282672 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9618 09:26:15.286245 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9619 09:26:15.292269 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9620 09:26:15.295519 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9621 09:26:15.302427 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9622 09:26:15.305485 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9623 09:26:15.309051 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9624 09:26:15.315300 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9625 09:26:15.319066 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9626 09:26:15.325189 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9627 09:26:15.328438 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9628 09:26:15.335051 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9629 09:26:15.338550 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9630 09:26:15.341659 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9631 09:26:15.348216 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9632 09:26:15.351971 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9633 09:26:15.355123 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9634 09:26:15.361450 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9635 09:26:15.365267 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9636 09:26:15.368398 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9637 09:26:15.371509 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9638 09:26:15.378389 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9639 09:26:15.381528 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9640 09:26:15.384746 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9641 09:26:15.391340 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9642 09:26:15.394848 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9643 09:26:15.401178 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9644 09:26:15.404252 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9645 09:26:15.407910 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9646 09:26:15.414345 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9647 09:26:15.418112 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9648 09:26:15.424546 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9649 09:26:15.427718 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9650 09:26:15.431390 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9651 09:26:15.437603 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9652 09:26:15.441110 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9653 09:26:15.444229 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9654 09:26:15.450822 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9655 09:26:15.454282 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9656 09:26:15.460747 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9657 09:26:15.464494 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9658 09:26:15.470859 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9659 09:26:15.473950 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9660 09:26:15.477931 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9661 09:26:15.484127 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9662 09:26:15.487263 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9663 09:26:15.490877 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9664 09:26:15.497130 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9665 09:26:15.500792 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9666 09:26:15.507052 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9667 09:26:15.510268 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9668 09:26:15.514001 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9669 09:26:15.520322 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9670 09:26:15.523496 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9671 09:26:15.530505 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9672 09:26:15.533643 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9673 09:26:15.536837 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9674 09:26:15.543704 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9675 09:26:15.547175 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9676 09:26:15.553693 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9677 09:26:15.556780 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9678 09:26:15.560466 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9679 09:26:15.567023 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9680 09:26:15.569976 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9681 09:26:15.573609 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9682 09:26:15.579962 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9683 09:26:15.583553 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9684 09:26:15.589917 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9685 09:26:15.593736 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9686 09:26:15.599722 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9687 09:26:15.603521 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9688 09:26:15.606443 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9689 09:26:15.613454 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9690 09:26:15.616530 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9691 09:26:15.619728 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9692 09:26:15.626761 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9693 09:26:15.629930 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9694 09:26:15.636331 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9695 09:26:15.639973 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9696 09:26:15.643140 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9697 09:26:15.649304 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9698 09:26:15.652932 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9699 09:26:15.659361 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9700 09:26:15.662918 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9701 09:26:15.666005 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9702 09:26:15.672968 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9703 09:26:15.676003 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9704 09:26:15.682438 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9705 09:26:15.685961 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9706 09:26:15.689620 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9707 09:26:15.695708 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9708 09:26:15.699439 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9709 09:26:15.705606 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9710 09:26:15.709389 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9711 09:26:15.716148 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9712 09:26:15.719217 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9713 09:26:15.722422 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9714 09:26:15.728912 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9715 09:26:15.732141 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9716 09:26:15.738886 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9717 09:26:15.742241 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9718 09:26:15.748535 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9719 09:26:15.752325 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9720 09:26:15.755385 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9721 09:26:15.762045 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9722 09:26:15.765516 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9723 09:26:15.772189 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9724 09:26:15.775348 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9725 09:26:15.778602 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9726 09:26:15.785397 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9727 09:26:15.788370 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9728 09:26:15.795419 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9729 09:26:15.798406 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9730 09:26:15.804981 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9731 09:26:15.808620 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9732 09:26:15.811946 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9733 09:26:15.818648 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9734 09:26:15.821524 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9735 09:26:15.828304 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9736 09:26:15.831482 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9737 09:26:15.835161 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9738 09:26:15.841481 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9739 09:26:15.845162 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9740 09:26:15.851704 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9741 09:26:15.854794 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9742 09:26:15.861761 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9743 09:26:15.864678 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9744 09:26:15.867813 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9745 09:26:15.874460 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9746 09:26:15.877927 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9747 09:26:15.881077 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9748 09:26:15.884938 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9749 09:26:15.891204 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9750 09:26:15.894781 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9751 09:26:15.897916 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9752 09:26:15.904228 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9753 09:26:15.907867 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9754 09:26:15.910889 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9755 09:26:15.918115 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9756 09:26:15.921158 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9757 09:26:15.927858 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9758 09:26:15.931342 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9759 09:26:15.934687 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9760 09:26:15.940949 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9761 09:26:15.944011 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9762 09:26:15.947741 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9763 09:26:15.954509 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9764 09:26:15.957509 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9765 09:26:15.961178 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9766 09:26:15.967509 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9767 09:26:15.970494 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9768 09:26:15.977450 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9769 09:26:15.980528 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9770 09:26:15.983990 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9771 09:26:15.990877 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9772 09:26:15.994140 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9773 09:26:16.000329 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9774 09:26:16.003404 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9775 09:26:16.007206 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9776 09:26:16.013417 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9777 09:26:16.017160 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9778 09:26:16.020200 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9779 09:26:16.026926 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9780 09:26:16.030007 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9781 09:26:16.036745 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9782 09:26:16.039946 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9783 09:26:16.042964 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9784 09:26:16.049537 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9785 09:26:16.053324 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9786 09:26:16.056410 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9787 09:26:16.059526 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9788 09:26:16.066434 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9789 09:26:16.069587 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9790 09:26:16.073224 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9791 09:26:16.075930 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9792 09:26:16.079860 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9793 09:26:16.086494 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9794 09:26:16.089621 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9795 09:26:16.092801 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9796 09:26:16.099363 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9797 09:26:16.102573 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9798 09:26:16.105903 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9799 09:26:16.112953 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9800 09:26:16.116108 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9801 09:26:16.122352 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9802 09:26:16.126203 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9803 09:26:16.129250 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9804 09:26:16.136055 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9805 09:26:16.139094 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9806 09:26:16.145879 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9807 09:26:16.148940 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9808 09:26:16.152502 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9809 09:26:16.158798 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9810 09:26:16.162500 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9811 09:26:16.168793 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9812 09:26:16.172284 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9813 09:26:16.175746 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9814 09:26:16.182134 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9815 09:26:16.185237 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9816 09:26:16.191594 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9817 09:26:16.195316 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9818 09:26:16.201525 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9819 09:26:16.205355 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9820 09:26:16.211234 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9821 09:26:16.214598 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9822 09:26:16.218007 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9823 09:26:16.224594 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9824 09:26:16.227818 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9825 09:26:16.234751 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9826 09:26:16.237906 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9827 09:26:16.241009 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9828 09:26:16.247791 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9829 09:26:16.251328 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9830 09:26:16.257652 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9831 09:26:16.261206 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9832 09:26:16.268025 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9833 09:26:16.271227 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9834 09:26:16.274378 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9835 09:26:16.280674 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9836 09:26:16.284248 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9837 09:26:16.290451 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9838 09:26:16.294235 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9839 09:26:16.297608 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9840 09:26:16.303732 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9841 09:26:16.306897 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9842 09:26:16.313707 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9843 09:26:16.317408 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9844 09:26:16.323714 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9845 09:26:16.326786 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9846 09:26:16.330610 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9847 09:26:16.336983 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9848 09:26:16.340054 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9849 09:26:16.346895 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9850 09:26:16.350176 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9851 09:26:16.356515 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9852 09:26:16.360266 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9853 09:26:16.363243 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9854 09:26:16.369785 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9855 09:26:16.373017 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9856 09:26:16.376425 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9857 09:26:16.383217 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9858 09:26:16.386400 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9859 09:26:16.393210 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9860 09:26:16.396202 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9861 09:26:16.402894 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9862 09:26:16.405835 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9863 09:26:16.409364 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9864 09:26:16.415894 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9865 09:26:16.419592 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9866 09:26:16.425739 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9867 09:26:16.429417 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9868 09:26:16.435740 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9869 09:26:16.439078 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9870 09:26:16.442300 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9871 09:26:16.448863 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9872 09:26:16.452775 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9873 09:26:16.459386 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9874 09:26:16.462699 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9875 09:26:16.468997 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9876 09:26:16.472147 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9877 09:26:16.475921 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9878 09:26:16.482008 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9879 09:26:16.485503 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9880 09:26:16.492171 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9881 09:26:16.495400 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9882 09:26:16.501914 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9883 09:26:16.505593 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9884 09:26:16.512058 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9885 09:26:16.515539 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9886 09:26:16.518594 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9887 09:26:16.525554 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9888 09:26:16.528529 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9889 09:26:16.535143 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9890 09:26:16.538356 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9891 09:26:16.545299 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9892 09:26:16.548482 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9893 09:26:16.551773 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9894 09:26:16.558077 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9895 09:26:16.561336 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9896 09:26:16.568334 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9897 09:26:16.571628 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9898 09:26:16.577936 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9899 09:26:16.581155 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9900 09:26:16.587709 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9901 09:26:16.590910 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9902 09:26:16.594630 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9903 09:26:16.601119 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9904 09:26:16.604637 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9905 09:26:16.610750 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9906 09:26:16.614180 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9907 09:26:16.620973 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9908 09:26:16.624408 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9909 09:26:16.630845 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9910 09:26:16.634062 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9911 09:26:16.637280 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9912 09:26:16.644069 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9913 09:26:16.647256 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9914 09:26:16.653818 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9915 09:26:16.657493 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9916 09:26:16.663943 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9917 09:26:16.667134 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9918 09:26:16.670251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9919 09:26:16.676808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9920 09:26:16.680084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9921 09:26:16.687095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9922 09:26:16.690198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9923 09:26:16.697195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9924 09:26:16.700289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9925 09:26:16.707106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9926 09:26:16.710228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9927 09:26:16.716809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9928 09:26:16.719773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9929 09:26:16.726391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9930 09:26:16.730198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9931 09:26:16.736511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9932 09:26:16.739963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9933 09:26:16.746459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9934 09:26:16.749394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9935 09:26:16.756590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9936 09:26:16.759394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9937 09:26:16.765995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9938 09:26:16.769339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9939 09:26:16.776451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9940 09:26:16.779637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9941 09:26:16.786190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9942 09:26:16.789581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9943 09:26:16.796067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9944 09:26:16.799210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9945 09:26:16.805608 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9946 09:26:16.809308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9947 09:26:16.815658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9948 09:26:16.819450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9949 09:26:16.825785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9950 09:26:16.828977 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9951 09:26:16.832495 INFO: [APUAPC] vio 0
9952 09:26:16.836029 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9953 09:26:16.842200 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9954 09:26:16.845764 INFO: [APUAPC] D0_APC_0: 0x400510
9955 09:26:16.845852 INFO: [APUAPC] D0_APC_1: 0x0
9956 09:26:16.848728 INFO: [APUAPC] D0_APC_2: 0x1540
9957 09:26:16.852041 INFO: [APUAPC] D0_APC_3: 0x0
9958 09:26:16.855460 INFO: [APUAPC] D1_APC_0: 0xffffffff
9959 09:26:16.859092 INFO: [APUAPC] D1_APC_1: 0xffffffff
9960 09:26:16.862151 INFO: [APUAPC] D1_APC_2: 0x3fffff
9961 09:26:16.865344 INFO: [APUAPC] D1_APC_3: 0x0
9962 09:26:16.868494 INFO: [APUAPC] D2_APC_0: 0xffffffff
9963 09:26:16.872102 INFO: [APUAPC] D2_APC_1: 0xffffffff
9964 09:26:16.875453 INFO: [APUAPC] D2_APC_2: 0x3fffff
9965 09:26:16.878326 INFO: [APUAPC] D2_APC_3: 0x0
9966 09:26:16.881720 INFO: [APUAPC] D3_APC_0: 0xffffffff
9967 09:26:16.885447 INFO: [APUAPC] D3_APC_1: 0xffffffff
9968 09:26:16.888614 INFO: [APUAPC] D3_APC_2: 0x3fffff
9969 09:26:16.891827 INFO: [APUAPC] D3_APC_3: 0x0
9970 09:26:16.895036 INFO: [APUAPC] D4_APC_0: 0xffffffff
9971 09:26:16.898314 INFO: [APUAPC] D4_APC_1: 0xffffffff
9972 09:26:16.901494 INFO: [APUAPC] D4_APC_2: 0x3fffff
9973 09:26:16.905431 INFO: [APUAPC] D4_APC_3: 0x0
9974 09:26:16.908706 INFO: [APUAPC] D5_APC_0: 0xffffffff
9975 09:26:16.911901 INFO: [APUAPC] D5_APC_1: 0xffffffff
9976 09:26:16.914953 INFO: [APUAPC] D5_APC_2: 0x3fffff
9977 09:26:16.918277 INFO: [APUAPC] D5_APC_3: 0x0
9978 09:26:16.921640 INFO: [APUAPC] D6_APC_0: 0xffffffff
9979 09:26:16.925003 INFO: [APUAPC] D6_APC_1: 0xffffffff
9980 09:26:16.928168 INFO: [APUAPC] D6_APC_2: 0x3fffff
9981 09:26:16.931455 INFO: [APUAPC] D6_APC_3: 0x0
9982 09:26:16.934519 INFO: [APUAPC] D7_APC_0: 0xffffffff
9983 09:26:16.938491 INFO: [APUAPC] D7_APC_1: 0xffffffff
9984 09:26:16.941744 INFO: [APUAPC] D7_APC_2: 0x3fffff
9985 09:26:16.944758 INFO: [APUAPC] D7_APC_3: 0x0
9986 09:26:16.948272 INFO: [APUAPC] D8_APC_0: 0xffffffff
9987 09:26:16.951680 INFO: [APUAPC] D8_APC_1: 0xffffffff
9988 09:26:16.954536 INFO: [APUAPC] D8_APC_2: 0x3fffff
9989 09:26:16.958147 INFO: [APUAPC] D8_APC_3: 0x0
9990 09:26:16.961085 INFO: [APUAPC] D9_APC_0: 0xffffffff
9991 09:26:16.964782 INFO: [APUAPC] D9_APC_1: 0xffffffff
9992 09:26:16.967657 INFO: [APUAPC] D9_APC_2: 0x3fffff
9993 09:26:16.971419 INFO: [APUAPC] D9_APC_3: 0x0
9994 09:26:16.974505 INFO: [APUAPC] D10_APC_0: 0xffffffff
9995 09:26:16.977774 INFO: [APUAPC] D10_APC_1: 0xffffffff
9996 09:26:16.981124 INFO: [APUAPC] D10_APC_2: 0x3fffff
9997 09:26:16.984241 INFO: [APUAPC] D10_APC_3: 0x0
9998 09:26:16.987461 INFO: [APUAPC] D11_APC_0: 0xffffffff
9999 09:26:16.991166 INFO: [APUAPC] D11_APC_1: 0xffffffff
10000 09:26:16.994186 INFO: [APUAPC] D11_APC_2: 0x3fffff
10001 09:26:16.997355 INFO: [APUAPC] D11_APC_3: 0x0
10002 09:26:17.000961 INFO: [APUAPC] D12_APC_0: 0xffffffff
10003 09:26:17.004065 INFO: [APUAPC] D12_APC_1: 0xffffffff
10004 09:26:17.007287 INFO: [APUAPC] D12_APC_2: 0x3fffff
10005 09:26:17.011074 INFO: [APUAPC] D12_APC_3: 0x0
10006 09:26:17.014123 INFO: [APUAPC] D13_APC_0: 0xffffffff
10007 09:26:17.017240 INFO: [APUAPC] D13_APC_1: 0xffffffff
10008 09:26:17.021072 INFO: [APUAPC] D13_APC_2: 0x3fffff
10009 09:26:17.024337 INFO: [APUAPC] D13_APC_3: 0x0
10010 09:26:17.027672 INFO: [APUAPC] D14_APC_0: 0xffffffff
10011 09:26:17.030950 INFO: [APUAPC] D14_APC_1: 0xffffffff
10012 09:26:17.034038 INFO: [APUAPC] D14_APC_2: 0x3fffff
10013 09:26:17.037114 INFO: [APUAPC] D14_APC_3: 0x0
10014 09:26:17.040314 INFO: [APUAPC] D15_APC_0: 0xffffffff
10015 09:26:17.043663 INFO: [APUAPC] D15_APC_1: 0xffffffff
10016 09:26:17.047341 INFO: [APUAPC] D15_APC_2: 0x3fffff
10017 09:26:17.050639 INFO: [APUAPC] D15_APC_3: 0x0
10018 09:26:17.053963 INFO: [APUAPC] APC_CON: 0x4
10019 09:26:17.056921 INFO: [NOCDAPC] D0_APC_0: 0x0
10020 09:26:17.057015 INFO: [NOCDAPC] D0_APC_1: 0x0
10021 09:26:17.060293 INFO: [NOCDAPC] D1_APC_0: 0x0
10022 09:26:17.063692 INFO: [NOCDAPC] D1_APC_1: 0xfff
10023 09:26:17.067445 INFO: [NOCDAPC] D2_APC_0: 0x0
10024 09:26:17.070688 INFO: [NOCDAPC] D2_APC_1: 0xfff
10025 09:26:17.073943 INFO: [NOCDAPC] D3_APC_0: 0x0
10026 09:26:17.076958 INFO: [NOCDAPC] D3_APC_1: 0xfff
10027 09:26:17.079988 INFO: [NOCDAPC] D4_APC_0: 0x0
10028 09:26:17.083371 INFO: [NOCDAPC] D4_APC_1: 0xfff
10029 09:26:17.086992 INFO: [NOCDAPC] D5_APC_0: 0x0
10030 09:26:17.089866 INFO: [NOCDAPC] D5_APC_1: 0xfff
10031 09:26:17.089972 INFO: [NOCDAPC] D6_APC_0: 0x0
10032 09:26:17.093766 INFO: [NOCDAPC] D6_APC_1: 0xfff
10033 09:26:17.096943 INFO: [NOCDAPC] D7_APC_0: 0x0
10034 09:26:17.100285 INFO: [NOCDAPC] D7_APC_1: 0xfff
10035 09:26:17.103383 INFO: [NOCDAPC] D8_APC_0: 0x0
10036 09:26:17.106415 INFO: [NOCDAPC] D8_APC_1: 0xfff
10037 09:26:17.109922 INFO: [NOCDAPC] D9_APC_0: 0x0
10038 09:26:17.113214 INFO: [NOCDAPC] D9_APC_1: 0xfff
10039 09:26:17.116847 INFO: [NOCDAPC] D10_APC_0: 0x0
10040 09:26:17.120144 INFO: [NOCDAPC] D10_APC_1: 0xfff
10041 09:26:17.123271 INFO: [NOCDAPC] D11_APC_0: 0x0
10042 09:26:17.126475 INFO: [NOCDAPC] D11_APC_1: 0xfff
10043 09:26:17.129684 INFO: [NOCDAPC] D12_APC_0: 0x0
10044 09:26:17.132990 INFO: [NOCDAPC] D12_APC_1: 0xfff
10045 09:26:17.133060 INFO: [NOCDAPC] D13_APC_0: 0x0
10046 09:26:17.136264 INFO: [NOCDAPC] D13_APC_1: 0xfff
10047 09:26:17.140158 INFO: [NOCDAPC] D14_APC_0: 0x0
10048 09:26:17.143378 INFO: [NOCDAPC] D14_APC_1: 0xfff
10049 09:26:17.146705 INFO: [NOCDAPC] D15_APC_0: 0x0
10050 09:26:17.149965 INFO: [NOCDAPC] D15_APC_1: 0xfff
10051 09:26:17.153205 INFO: [NOCDAPC] APC_CON: 0x4
10052 09:26:17.156521 INFO: [APUAPC] set_apusys_apc done
10053 09:26:17.159664 INFO: [DEVAPC] devapc_init done
10054 09:26:17.162950 INFO: GICv3 without legacy support detected.
10055 09:26:17.166133 INFO: ARM GICv3 driver initialized in EL3
10056 09:26:17.172876 INFO: Maximum SPI INTID supported: 639
10057 09:26:17.176277 INFO: BL31: Initializing runtime services
10058 09:26:17.179448 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10059 09:26:17.182661 INFO: SPM: enable CPC mode
10060 09:26:17.189233 INFO: mcdi ready for mcusys-off-idle and system suspend
10061 09:26:17.192851 INFO: BL31: Preparing for EL3 exit to normal world
10062 09:26:17.195753 INFO: Entry point address = 0x80000000
10063 09:26:17.199214 INFO: SPSR = 0x8
10064 09:26:17.205172
10065 09:26:17.205268
10066 09:26:17.205353
10067 09:26:17.208425 Starting depthcharge on Spherion...
10068 09:26:17.208538
10069 09:26:17.208626 Wipe memory regions:
10070 09:26:17.208699
10071 09:26:17.209457 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10072 09:26:17.209579 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10073 09:26:17.209683 Setting prompt string to ['asurada:']
10074 09:26:17.209793 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10075 09:26:17.211699 [0x00000040000000, 0x00000054600000)
10076 09:26:17.334375
10077 09:26:17.334526 [0x00000054660000, 0x00000080000000)
10078 09:26:17.595126
10079 09:26:17.595302 [0x000000821a7280, 0x000000ffe64000)
10080 09:26:18.339351
10081 09:26:18.339507 [0x00000100000000, 0x00000240000000)
10082 09:26:20.229975
10083 09:26:20.232953 Initializing XHCI USB controller at 0x11200000.
10084 09:26:21.271172
10085 09:26:21.274178 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10086 09:26:21.274281
10087 09:26:21.274370
10088 09:26:21.274671 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10090 09:26:21.375032 asurada: tftpboot 192.168.201.1 14407676/tftp-deploy-21hyexwe/kernel/image.itb 14407676/tftp-deploy-21hyexwe/kernel/cmdline
10091 09:26:21.375256 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10092 09:26:21.375364 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10093 09:26:21.379379 tftpboot 192.168.201.1 14407676/tftp-deploy-21hyexwe/kernel/image.itp-deploy-21hyexwe/kernel/cmdline
10094 09:26:21.379482
10095 09:26:21.379569 Waiting for link
10096 09:26:21.537664
10097 09:26:21.537799 R8152: Initializing
10098 09:26:21.537864
10099 09:26:21.540468 Version 6 (ocp_data = 5c30)
10100 09:26:21.540559
10101 09:26:21.543794 R8152: Done initializing
10102 09:26:21.543883
10103 09:26:21.543964 Adding net device
10104 09:26:23.403712
10105 09:26:23.403865 done.
10106 09:26:23.403958
10107 09:26:23.404042 MAC: 00:24:32:30:78:ff
10108 09:26:23.404125
10109 09:26:23.406756 Sending DHCP discover... done.
10110 09:26:23.406846
10111 09:26:26.593644 Waiting for reply... done.
10112 09:26:26.593790
10113 09:26:26.593883 Sending DHCP request... done.
10114 09:26:26.596961
10115 09:26:26.597060 Waiting for reply... done.
10116 09:26:26.597149
10117 09:26:26.600177 My ip is 192.168.201.21
10118 09:26:26.600267
10119 09:26:26.603712 The DHCP server ip is 192.168.201.1
10120 09:26:26.603811
10121 09:26:26.606593 TFTP server IP predefined by user: 192.168.201.1
10122 09:26:26.606690
10123 09:26:26.613458 Bootfile predefined by user: 14407676/tftp-deploy-21hyexwe/kernel/image.itb
10124 09:26:26.613556
10125 09:26:26.617058 Sending tftp read request... done.
10126 09:26:26.617161
10127 09:26:26.620001 Waiting for the transfer...
10128 09:26:26.620093
10129 09:26:27.170731 00000000 ################################################################
10130 09:26:27.170882
10131 09:26:27.721259 00080000 ################################################################
10132 09:26:27.721378
10133 09:26:28.274724 00100000 ################################################################
10134 09:26:28.274844
10135 09:26:28.821638 00180000 ################################################################
10136 09:26:28.821752
10137 09:26:29.366234 00200000 ################################################################
10138 09:26:29.366358
10139 09:26:29.920997 00280000 ################################################################
10140 09:26:29.921134
10141 09:26:30.480378 00300000 ################################################################
10142 09:26:30.480527
10143 09:26:31.024561 00380000 ################################################################
10144 09:26:31.024730
10145 09:26:31.569710 00400000 ################################################################
10146 09:26:31.569840
10147 09:26:32.117003 00480000 ################################################################
10148 09:26:32.117134
10149 09:26:32.679413 00500000 ################################################################
10150 09:26:32.679570
10151 09:26:33.246539 00580000 ################################################################
10152 09:26:33.246677
10153 09:26:33.783180 00600000 ################################################################
10154 09:26:33.783311
10155 09:26:34.308668 00680000 ################################################################
10156 09:26:34.308789
10157 09:26:34.836399 00700000 ################################################################
10158 09:26:34.836557
10159 09:26:35.367415 00780000 ################################################################
10160 09:26:35.367583
10161 09:26:35.904446 00800000 ################################################################
10162 09:26:35.904565
10163 09:26:36.434367 00880000 ################################################################
10164 09:26:36.434515
10165 09:26:36.962639 00900000 ################################################################
10166 09:26:36.962763
10167 09:26:37.503640 00980000 ################################################################
10168 09:26:37.503788
10169 09:26:38.048823 00a00000 ################################################################
10170 09:26:38.049012
10171 09:26:38.592362 00a80000 ################################################################
10172 09:26:38.592557
10173 09:26:39.158203 00b00000 ################################################################
10174 09:26:39.158321
10175 09:26:39.739450 00b80000 ################################################################
10176 09:26:39.739579
10177 09:26:40.307176 00c00000 ################################################################
10178 09:26:40.307296
10179 09:26:40.873627 00c80000 ################################################################
10180 09:26:40.873750
10181 09:26:41.429224 00d00000 ################################################################
10182 09:26:41.429361
10183 09:26:41.985672 00d80000 ################################################################
10184 09:26:41.985790
10185 09:26:42.554729 00e00000 ################################################################
10186 09:26:42.554866
10187 09:26:43.112589 00e80000 ################################################################
10188 09:26:43.112731
10189 09:26:43.671163 00f00000 ################################################################
10190 09:26:43.671311
10191 09:26:44.243073 00f80000 ################################################################
10192 09:26:44.243194
10193 09:26:44.814335 01000000 ################################################################
10194 09:26:44.814460
10195 09:26:45.383690 01080000 ################################################################
10196 09:26:45.383830
10197 09:26:45.946249 01100000 ################################################################
10198 09:26:45.946406
10199 09:26:46.491476 01180000 ################################################################
10200 09:26:46.491597
10201 09:26:47.025319 01200000 ################################################################
10202 09:26:47.025436
10203 09:26:47.560956 01280000 ################################################################
10204 09:26:47.561075
10205 09:26:48.094872 01300000 ################################################################
10206 09:26:48.095029
10207 09:26:48.633520 01380000 ################################################################
10208 09:26:48.633673
10209 09:26:49.164136 01400000 ################################################################
10210 09:26:49.164278
10211 09:26:49.701377 01480000 ################################################################
10212 09:26:49.701516
10213 09:26:50.242612 01500000 ################################################################
10214 09:26:50.242753
10215 09:26:50.783323 01580000 ################################################################
10216 09:26:50.783444
10217 09:26:51.356438 01600000 ################################################################
10218 09:26:51.356605
10219 09:26:51.920366 01680000 ################################################################
10220 09:26:51.920503
10221 09:26:52.477951 01700000 ################################################################
10222 09:26:52.478088
10223 09:26:53.018337 01780000 ################################################################
10224 09:26:53.018476
10225 09:26:53.561994 01800000 ################################################################
10226 09:26:53.562141
10227 09:26:54.116017 01880000 ################################################################
10228 09:26:54.116142
10229 09:26:54.676630 01900000 ################################################################
10230 09:26:54.676761
10231 09:26:55.219515 01980000 ################################################################
10232 09:26:55.219644
10233 09:26:55.759386 01a00000 ################################################################
10234 09:26:55.759524
10235 09:26:56.282839 01a80000 ################################################################
10236 09:26:56.282980
10237 09:26:56.836490 01b00000 ################################################################
10238 09:26:56.836656
10239 09:26:57.367180 01b80000 ################################################################
10240 09:26:57.367311
10241 09:26:57.903379 01c00000 ################################################################
10242 09:26:57.903501
10243 09:26:58.451500 01c80000 ################################################################
10244 09:26:58.451636
10245 09:26:59.006906 01d00000 ################################################################
10246 09:26:59.007031
10247 09:26:59.549986 01d80000 ################################################################
10248 09:26:59.550118
10249 09:27:00.034525 01e00000 ######################################################### done.
10250 09:27:00.034678
10251 09:27:00.037819 The bootfile was 31919194 bytes long.
10252 09:27:00.037922
10253 09:27:00.041021 Sending tftp read request... done.
10254 09:27:00.041114
10255 09:27:00.041177 Waiting for the transfer...
10256 09:27:00.041235
10257 09:27:00.044219 00000000 # done.
10258 09:27:00.044308
10259 09:27:00.051033 Command line loaded dynamically from TFTP file: 14407676/tftp-deploy-21hyexwe/kernel/cmdline
10260 09:27:00.051128
10261 09:27:00.074288 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407676/extract-nfsrootfs-3y43sa5u,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10262 09:27:00.074432
10263 09:27:00.074500 Loading FIT.
10264 09:27:00.074559
10265 09:27:00.077583 Image ramdisk-1 has 18743181 bytes.
10266 09:27:00.077668
10267 09:27:00.080847 Image fdt-1 has 47258 bytes.
10268 09:27:00.080933
10269 09:27:00.084094 Image kernel-1 has 13126726 bytes.
10270 09:27:00.084182
10271 09:27:00.094045 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10272 09:27:00.094150
10273 09:27:00.110645 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10274 09:27:00.110775
10275 09:27:00.117300 Choosing best match conf-1 for compat google,spherion-rev2.
10276 09:27:00.117404
10277 09:27:00.125089 Connected to device vid:did:rid of 1ae0:0028:00
10278 09:27:00.132989
10279 09:27:00.136574 tpm_get_response: command 0x17b, return code 0x0
10280 09:27:00.136703
10281 09:27:00.139617 ec_init: CrosEC protocol v3 supported (256, 248)
10282 09:27:00.144087
10283 09:27:00.147194 tpm_cleanup: add release locality here.
10284 09:27:00.147307
10285 09:27:00.147400 Shutting down all USB controllers.
10286 09:27:00.150419
10287 09:27:00.150497 Removing current net device
10288 09:27:00.150559
10289 09:27:00.157330 Exiting depthcharge with code 4 at timestamp: 72260776
10290 09:27:00.157411
10291 09:27:00.160406 LZMA decompressing kernel-1 to 0x821a6718
10292 09:27:00.160510
10293 09:27:00.163411 LZMA decompressing kernel-1 to 0x40000000
10294 09:27:01.781652
10295 09:27:01.781789 jumping to kernel
10296 09:27:01.782250 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10297 09:27:01.782358 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10298 09:27:01.782431 Setting prompt string to ['Linux version [0-9]']
10299 09:27:01.782525 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10300 09:27:01.782594 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10301 09:27:01.863582
10302 09:27:01.866762 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10303 09:27:01.870741 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10304 09:27:01.870839 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10305 09:27:01.870908 Setting prompt string to []
10306 09:27:01.870983 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10307 09:27:01.871053 Using line separator: #'\n'#
10308 09:27:01.871109 No login prompt set.
10309 09:27:01.871168 Parsing kernel messages
10310 09:27:01.871223 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10311 09:27:01.871330 [login-action] Waiting for messages, (timeout 00:03:42)
10312 09:27:01.871395 Waiting using forced prompt support (timeout 00:01:51)
10313 09:27:01.890317 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
10314 09:27:01.893498 [ 0.000000] random: crng init done
10315 09:27:01.899948 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10316 09:27:01.903799 [ 0.000000] efi: UEFI not found.
10317 09:27:01.910172 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10318 09:27:01.916595 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10319 09:27:01.926662 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10320 09:27:01.936775 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10321 09:27:01.942928 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10322 09:27:01.949587 [ 0.000000] printk: bootconsole [mtk8250] enabled
10323 09:27:01.956214 [ 0.000000] NUMA: No NUMA configuration found
10324 09:27:01.963085 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10325 09:27:01.966349 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10326 09:27:01.969476 [ 0.000000] Zone ranges:
10327 09:27:01.975891 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10328 09:27:01.979619 [ 0.000000] DMA32 empty
10329 09:27:01.985963 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10330 09:27:01.989094 [ 0.000000] Movable zone start for each node
10331 09:27:01.992984 [ 0.000000] Early memory node ranges
10332 09:27:01.999338 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10333 09:27:02.006168 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10334 09:27:02.012499 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10335 09:27:02.018942 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10336 09:27:02.025804 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10337 09:27:02.032288 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10338 09:27:02.087954 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10339 09:27:02.095027 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10340 09:27:02.101599 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10341 09:27:02.104809 [ 0.000000] psci: probing for conduit method from DT.
10342 09:27:02.111148 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10343 09:27:02.114396 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10344 09:27:02.121299 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10345 09:27:02.124534 [ 0.000000] psci: SMC Calling Convention v1.2
10346 09:27:02.131543 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10347 09:27:02.134478 [ 0.000000] Detected VIPT I-cache on CPU0
10348 09:27:02.140955 [ 0.000000] CPU features: detected: GIC system register CPU interface
10349 09:27:02.147686 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10350 09:27:02.154478 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10351 09:27:02.160892 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10352 09:27:02.167884 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10353 09:27:02.174773 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10354 09:27:02.181029 [ 0.000000] alternatives: applying boot alternatives
10355 09:27:02.187525 [ 0.000000] Fallback order for Node 0: 0
10356 09:27:02.194480 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10357 09:27:02.197597 [ 0.000000] Policy zone: Normal
10358 09:27:02.220751 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407676/extract-nfsrootfs-3y43sa5u,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10359 09:27:02.230403 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10360 09:27:02.241562 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10361 09:27:02.251247 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10362 09:27:02.258040 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10363 09:27:02.261073 <6>[ 0.000000] software IO TLB: area num 8.
10364 09:27:02.318049 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10365 09:27:02.466944 <6>[ 0.000000] Memory: 7945756K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407012K reserved, 32768K cma-reserved)
10366 09:27:02.473857 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10367 09:27:02.480444 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10368 09:27:02.483430 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10369 09:27:02.490477 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10370 09:27:02.496838 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10371 09:27:02.499946 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10372 09:27:02.510207 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10373 09:27:02.516440 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10374 09:27:02.523561 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10375 09:27:02.529958 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10376 09:27:02.533303 <6>[ 0.000000] GICv3: 608 SPIs implemented
10377 09:27:02.536426 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10378 09:27:02.543302 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10379 09:27:02.546514 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10380 09:27:02.553599 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10381 09:27:02.566542 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10382 09:27:02.576133 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10383 09:27:02.586498 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10384 09:27:02.593753 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10385 09:27:02.606885 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10386 09:27:02.613257 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10387 09:27:02.620082 <6>[ 0.009184] Console: colour dummy device 80x25
10388 09:27:02.629854 <6>[ 0.013912] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10389 09:27:02.636813 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10390 09:27:02.639792 <6>[ 0.029225] LSM: Security Framework initializing
10391 09:27:02.646945 <6>[ 0.034164] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10392 09:27:02.656433 <6>[ 0.041978] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10393 09:27:02.663313 <6>[ 0.051388] cblist_init_generic: Setting adjustable number of callback queues.
10394 09:27:02.669570 <6>[ 0.058878] cblist_init_generic: Setting shift to 3 and lim to 1.
10395 09:27:02.679660 <6>[ 0.065257] cblist_init_generic: Setting adjustable number of callback queues.
10396 09:27:02.686189 <6>[ 0.072684] cblist_init_generic: Setting shift to 3 and lim to 1.
10397 09:27:02.689259 <6>[ 0.079123] rcu: Hierarchical SRCU implementation.
10398 09:27:02.696198 <6>[ 0.084137] rcu: Max phase no-delay instances is 1000.
10399 09:27:02.702958 <6>[ 0.091171] EFI services will not be available.
10400 09:27:02.705801 <6>[ 0.096154] smp: Bringing up secondary CPUs ...
10401 09:27:02.714576 <6>[ 0.101209] Detected VIPT I-cache on CPU1
10402 09:27:02.721108 <6>[ 0.101280] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10403 09:27:02.727362 <6>[ 0.101310] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10404 09:27:02.731129 <6>[ 0.101646] Detected VIPT I-cache on CPU2
10405 09:27:02.737327 <6>[ 0.101697] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10406 09:27:02.744104 <6>[ 0.101714] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10407 09:27:02.750535 <6>[ 0.101974] Detected VIPT I-cache on CPU3
10408 09:27:02.757494 <6>[ 0.102022] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10409 09:27:02.764090 <6>[ 0.102036] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10410 09:27:02.767174 <6>[ 0.102340] CPU features: detected: Spectre-v4
10411 09:27:02.774404 <6>[ 0.102346] CPU features: detected: Spectre-BHB
10412 09:27:02.777264 <6>[ 0.102351] Detected PIPT I-cache on CPU4
10413 09:27:02.784132 <6>[ 0.102412] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10414 09:27:02.790617 <6>[ 0.102428] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10415 09:27:02.796898 <6>[ 0.102717] Detected PIPT I-cache on CPU5
10416 09:27:02.803517 <6>[ 0.102779] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10417 09:27:02.810248 <6>[ 0.102795] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10418 09:27:02.813863 <6>[ 0.103081] Detected PIPT I-cache on CPU6
10419 09:27:02.820202 <6>[ 0.103146] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10420 09:27:02.827204 <6>[ 0.103162] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10421 09:27:02.833664 <6>[ 0.103459] Detected PIPT I-cache on CPU7
10422 09:27:02.840032 <6>[ 0.103523] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10423 09:27:02.846781 <6>[ 0.103539] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10424 09:27:02.849971 <6>[ 0.103586] smp: Brought up 1 node, 8 CPUs
10425 09:27:02.856390 <6>[ 0.244728] SMP: Total of 8 processors activated.
10426 09:27:02.859582 <6>[ 0.249650] CPU features: detected: 32-bit EL0 Support
10427 09:27:02.869470 <6>[ 0.255046] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10428 09:27:02.876447 <6>[ 0.263847] CPU features: detected: Common not Private translations
10429 09:27:02.882905 <6>[ 0.270322] CPU features: detected: CRC32 instructions
10430 09:27:02.885891 <6>[ 0.275673] CPU features: detected: RCpc load-acquire (LDAPR)
10431 09:27:02.892712 <6>[ 0.281634] CPU features: detected: LSE atomic instructions
10432 09:27:02.899163 <6>[ 0.287415] CPU features: detected: Privileged Access Never
10433 09:27:02.906255 <6>[ 0.293230] CPU features: detected: RAS Extension Support
10434 09:27:02.912519 <6>[ 0.298839] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10435 09:27:02.916157 <6>[ 0.306058] CPU: All CPU(s) started at EL2
10436 09:27:02.922358 <6>[ 0.310374] alternatives: applying system-wide alternatives
10437 09:27:02.931593 <6>[ 0.321260] devtmpfs: initialized
10438 09:27:02.947607 <6>[ 0.330215] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10439 09:27:02.954333 <6>[ 0.340177] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10440 09:27:02.960625 <6>[ 0.348194] pinctrl core: initialized pinctrl subsystem
10441 09:27:02.963801 <6>[ 0.354883] DMI not present or invalid.
10442 09:27:02.970855 <6>[ 0.359300] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10443 09:27:02.980564 <6>[ 0.366157] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10444 09:27:02.986962 <6>[ 0.373748] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10445 09:27:02.996992 <6>[ 0.381973] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10446 09:27:03.000081 <6>[ 0.390217] audit: initializing netlink subsys (disabled)
10447 09:27:03.010459 <5>[ 0.395909] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10448 09:27:03.016607 <6>[ 0.396630] thermal_sys: Registered thermal governor 'step_wise'
10449 09:27:03.023704 <6>[ 0.403875] thermal_sys: Registered thermal governor 'power_allocator'
10450 09:27:03.026546 <6>[ 0.410130] cpuidle: using governor menu
10451 09:27:03.033655 <6>[ 0.421093] NET: Registered PF_QIPCRTR protocol family
10452 09:27:03.039984 <6>[ 0.426581] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10453 09:27:03.043123 <6>[ 0.433683] ASID allocator initialised with 32768 entries
10454 09:27:03.050918 <6>[ 0.440268] Serial: AMBA PL011 UART driver
10455 09:27:03.059700 <4>[ 0.449109] Trying to register duplicate clock ID: 134
10456 09:27:03.119745 <6>[ 0.512466] KASLR enabled
10457 09:27:03.134144 <6>[ 0.520177] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10458 09:27:03.140548 <6>[ 0.527189] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10459 09:27:03.147564 <6>[ 0.533676] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10460 09:27:03.153896 <6>[ 0.540681] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10461 09:27:03.160821 <6>[ 0.547170] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10462 09:27:03.166945 <6>[ 0.554176] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10463 09:27:03.174030 <6>[ 0.560664] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10464 09:27:03.180414 <6>[ 0.567668] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10465 09:27:03.183575 <6>[ 0.575127] ACPI: Interpreter disabled.
10466 09:27:03.192100 <6>[ 0.581561] iommu: Default domain type: Translated
10467 09:27:03.199043 <6>[ 0.586707] iommu: DMA domain TLB invalidation policy: strict mode
10468 09:27:03.202265 <5>[ 0.593367] SCSI subsystem initialized
10469 09:27:03.208615 <6>[ 0.597621] usbcore: registered new interface driver usbfs
10470 09:27:03.215702 <6>[ 0.603351] usbcore: registered new interface driver hub
10471 09:27:03.218931 <6>[ 0.608905] usbcore: registered new device driver usb
10472 09:27:03.225682 <6>[ 0.615024] pps_core: LinuxPPS API ver. 1 registered
10473 09:27:03.235839 <6>[ 0.620220] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10474 09:27:03.238803 <6>[ 0.629564] PTP clock support registered
10475 09:27:03.242422 <6>[ 0.633805] EDAC MC: Ver: 3.0.0
10476 09:27:03.249619 <6>[ 0.638992] FPGA manager framework
10477 09:27:03.256292 <6>[ 0.642671] Advanced Linux Sound Architecture Driver Initialized.
10478 09:27:03.259626 <6>[ 0.649450] vgaarb: loaded
10479 09:27:03.266060 <6>[ 0.652604] clocksource: Switched to clocksource arch_sys_counter
10480 09:27:03.269658 <5>[ 0.659031] VFS: Disk quotas dquot_6.6.0
10481 09:27:03.276016 <6>[ 0.663219] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10482 09:27:03.279150 <6>[ 0.670411] pnp: PnP ACPI: disabled
10483 09:27:03.287581 <6>[ 0.677194] NET: Registered PF_INET protocol family
10484 09:27:03.297546 <6>[ 0.682797] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10485 09:27:03.308848 <6>[ 0.695119] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10486 09:27:03.318986 <6>[ 0.703935] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10487 09:27:03.325906 <6>[ 0.711908] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10488 09:27:03.335916 <6>[ 0.720616] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10489 09:27:03.342086 <6>[ 0.730362] TCP: Hash tables configured (established 65536 bind 65536)
10490 09:27:03.348627 <6>[ 0.737226] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10491 09:27:03.358573 <6>[ 0.744425] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10492 09:27:03.365077 <6>[ 0.752131] NET: Registered PF_UNIX/PF_LOCAL protocol family
10493 09:27:03.368588 <6>[ 0.758223] RPC: Registered named UNIX socket transport module.
10494 09:27:03.374979 <6>[ 0.764374] RPC: Registered udp transport module.
10495 09:27:03.378476 <6>[ 0.769305] RPC: Registered tcp transport module.
10496 09:27:03.388125 <6>[ 0.774237] RPC: Registered tcp NFSv4.1 backchannel transport module.
10497 09:27:03.391361 <6>[ 0.780904] PCI: CLS 0 bytes, default 64
10498 09:27:03.395173 <6>[ 0.785336] Unpacking initramfs...
10499 09:27:03.404876 <6>[ 0.789085] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10500 09:27:03.411316 <6>[ 0.797751] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10501 09:27:03.418093 <6>[ 0.806593] kvm [1]: IPA Size Limit: 40 bits
10502 09:27:03.421193 <6>[ 0.811119] kvm [1]: GICv3: no GICV resource entry
10503 09:27:03.427741 <6>[ 0.816143] kvm [1]: disabling GICv2 emulation
10504 09:27:03.430871 <6>[ 0.820832] kvm [1]: GIC system register CPU interface enabled
10505 09:27:03.437812 <6>[ 0.826998] kvm [1]: vgic interrupt IRQ18
10506 09:27:03.444061 <6>[ 0.832655] kvm [1]: VHE mode initialized successfully
10507 09:27:03.450805 <5>[ 0.839092] Initialise system trusted keyrings
10508 09:27:03.457368 <6>[ 0.843899] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10509 09:27:03.464826 <6>[ 0.853927] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10510 09:27:03.470993 <5>[ 0.860274] NFS: Registering the id_resolver key type
10511 09:27:03.474585 <5>[ 0.865572] Key type id_resolver registered
10512 09:27:03.480946 <5>[ 0.869988] Key type id_legacy registered
10513 09:27:03.488020 <6>[ 0.874286] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10514 09:27:03.494468 <6>[ 0.881212] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10515 09:27:03.500722 <6>[ 0.888914] 9p: Installing v9fs 9p2000 file system support
10516 09:27:03.537270 <5>[ 0.926530] Key type asymmetric registered
10517 09:27:03.540421 <5>[ 0.930858] Asymmetric key parser 'x509' registered
10518 09:27:03.550512 <6>[ 0.935992] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10519 09:27:03.553556 <6>[ 0.943608] io scheduler mq-deadline registered
10520 09:27:03.556662 <6>[ 0.948370] io scheduler kyber registered
10521 09:27:03.575904 <6>[ 0.965483] EINJ: ACPI disabled.
10522 09:27:03.609510 <4>[ 0.991913] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10523 09:27:03.618753 <4>[ 1.002645] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10524 09:27:03.634049 <6>[ 1.023569] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10525 09:27:03.642396 <6>[ 1.031564] printk: console [ttyS0] disabled
10526 09:27:03.670469 <6>[ 1.056200] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10527 09:27:03.676668 <6>[ 1.065685] printk: console [ttyS0] enabled
10528 09:27:03.680472 <6>[ 1.065685] printk: console [ttyS0] enabled
10529 09:27:03.686704 <6>[ 1.074582] printk: bootconsole [mtk8250] disabled
10530 09:27:03.689782 <6>[ 1.074582] printk: bootconsole [mtk8250] disabled
10531 09:27:03.696790 <6>[ 1.085632] SuperH (H)SCI(F) driver initialized
10532 09:27:03.699674 <6>[ 1.090929] msm_serial: driver initialized
10533 09:27:03.713805 <6>[ 1.099901] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10534 09:27:03.723567 <6>[ 1.108453] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10535 09:27:03.730510 <6>[ 1.116997] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10536 09:27:03.740600 <6>[ 1.125624] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10537 09:27:03.746850 <6>[ 1.134330] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10538 09:27:03.757010 <6>[ 1.143043] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10539 09:27:03.766648 <6>[ 1.151582] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10540 09:27:03.773398 <6>[ 1.160378] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10541 09:27:03.783503 <6>[ 1.168920] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10542 09:27:03.795491 <6>[ 1.184654] loop: module loaded
10543 09:27:03.802024 <6>[ 1.190597] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10544 09:27:03.824350 <4>[ 1.213784] mtk-pmic-keys: Failed to locate of_node [id: -1]
10545 09:27:03.830963 <6>[ 1.220544] megasas: 07.719.03.00-rc1
10546 09:27:03.841118 <6>[ 1.230154] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10547 09:27:03.847299 <6>[ 1.232005] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10548 09:27:03.862245 <6>[ 1.251733] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10549 09:27:03.917742 <6>[ 1.300452] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10550 09:27:04.181510 <6>[ 1.571091] Freeing initrd memory: 18300K
10551 09:27:04.193584 <6>[ 1.582755] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10552 09:27:04.204184 <6>[ 1.593825] tun: Universal TUN/TAP device driver, 1.6
10553 09:27:04.207935 <6>[ 1.599887] thunder_xcv, ver 1.0
10554 09:27:04.211154 <6>[ 1.603396] thunder_bgx, ver 1.0
10555 09:27:04.214352 <6>[ 1.606895] nicpf, ver 1.0
10556 09:27:04.225113 <6>[ 1.610921] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10557 09:27:04.228496 <6>[ 1.618398] hns3: Copyright (c) 2017 Huawei Corporation.
10558 09:27:04.231571 <6>[ 1.623990] hclge is initializing
10559 09:27:04.238457 <6>[ 1.627565] e1000: Intel(R) PRO/1000 Network Driver
10560 09:27:04.244814 <6>[ 1.632694] e1000: Copyright (c) 1999-2006 Intel Corporation.
10561 09:27:04.248269 <6>[ 1.638710] e1000e: Intel(R) PRO/1000 Network Driver
10562 09:27:04.254916 <6>[ 1.643926] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10563 09:27:04.261591 <6>[ 1.650111] igb: Intel(R) Gigabit Ethernet Network Driver
10564 09:27:04.268388 <6>[ 1.655762] igb: Copyright (c) 2007-2014 Intel Corporation.
10565 09:27:04.274851 <6>[ 1.661599] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10566 09:27:04.281701 <6>[ 1.668117] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10567 09:27:04.284747 <6>[ 1.674582] sky2: driver version 1.30
10568 09:27:04.291639 <6>[ 1.679518] usbcore: registered new device driver r8152-cfgselector
10569 09:27:04.297976 <6>[ 1.686056] usbcore: registered new interface driver r8152
10570 09:27:04.301214 <6>[ 1.691874] VFIO - User Level meta-driver version: 0.3
10571 09:27:04.310638 <6>[ 1.700114] usbcore: registered new interface driver usb-storage
10572 09:27:04.317129 <6>[ 1.706560] usbcore: registered new device driver onboard-usb-hub
10573 09:27:04.326565 <6>[ 1.715714] mt6397-rtc mt6359-rtc: registered as rtc0
10574 09:27:04.336257 <6>[ 1.721184] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-18T09:27:04 UTC (1718702824)
10575 09:27:04.339578 <6>[ 1.730753] i2c_dev: i2c /dev entries driver
10576 09:27:04.353624 <4>[ 1.742918] cpu cpu0: supply cpu not found, using dummy regulator
10577 09:27:04.360115 <4>[ 1.749341] cpu cpu1: supply cpu not found, using dummy regulator
10578 09:27:04.366631 <4>[ 1.755748] cpu cpu2: supply cpu not found, using dummy regulator
10579 09:27:04.373260 <4>[ 1.762150] cpu cpu3: supply cpu not found, using dummy regulator
10580 09:27:04.380456 <4>[ 1.768568] cpu cpu4: supply cpu not found, using dummy regulator
10581 09:27:04.386804 <4>[ 1.774964] cpu cpu5: supply cpu not found, using dummy regulator
10582 09:27:04.393307 <4>[ 1.781358] cpu cpu6: supply cpu not found, using dummy regulator
10583 09:27:04.399822 <4>[ 1.787757] cpu cpu7: supply cpu not found, using dummy regulator
10584 09:27:04.420100 <6>[ 1.809411] cpu cpu0: EM: created perf domain
10585 09:27:04.423364 <6>[ 1.814333] cpu cpu4: EM: created perf domain
10586 09:27:04.430351 <6>[ 1.819941] sdhci: Secure Digital Host Controller Interface driver
10587 09:27:04.437271 <6>[ 1.826374] sdhci: Copyright(c) Pierre Ossman
10588 09:27:04.443579 <6>[ 1.831332] Synopsys Designware Multimedia Card Interface Driver
10589 09:27:04.450518 <6>[ 1.837963] sdhci-pltfm: SDHCI platform and OF driver helper
10590 09:27:04.453707 <6>[ 1.838018] mmc0: CQHCI version 5.10
10591 09:27:04.460592 <6>[ 1.848140] ledtrig-cpu: registered to indicate activity on CPUs
10592 09:27:04.466708 <6>[ 1.855173] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10593 09:27:04.473932 <6>[ 1.862225] usbcore: registered new interface driver usbhid
10594 09:27:04.476807 <6>[ 1.868047] usbhid: USB HID core driver
10595 09:27:04.483605 <6>[ 1.872242] spi_master spi0: will run message pump with realtime priority
10596 09:27:04.530963 <6>[ 1.913752] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10597 09:27:04.549772 <6>[ 1.929424] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10598 09:27:04.553487 <3>[ 1.932766] mtk-msdc 11f60000.mmc: phase error: [map:0]
10599 09:27:04.560463 <3>[ 1.948314] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10600 09:27:04.567035 <3>[ 1.954253] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10601 09:27:04.569973 <3>[ 1.960623] mmc0: error -5 whilst initialising MMC card
10602 09:27:04.576968 <6>[ 1.960761] cros-ec-spi spi0.0: Chrome EC device registered
10603 09:27:04.599249 <6>[ 1.985301] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10604 09:27:04.606782 <6>[ 1.996006] NET: Registered PF_PACKET protocol family
10605 09:27:04.609864 <6>[ 2.001393] 9pnet: Installing 9P2000 support
10606 09:27:04.616870 <5>[ 2.005955] Key type dns_resolver registered
10607 09:27:04.619996 <6>[ 2.010999] registered taskstats version 1
10608 09:27:04.626352 <5>[ 2.015382] Loading compiled-in X.509 certificates
10609 09:27:04.658786 <4>[ 2.041299] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 09:27:04.668386 <4>[ 2.052170] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 09:27:04.683766 <3>[ 2.073257] mtk-msdc 11f60000.mmc: phase error: [map:0]
10612 09:27:04.690604 <3>[ 2.078754] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10613 09:27:04.697308 <6>[ 2.079522] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10614 09:27:04.703877 <3>[ 2.084675] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10615 09:27:04.707167 <6>[ 2.091608] xhci-mtk 11200000.usb: xHCI Host Controller
10616 09:27:04.713823 <3>[ 2.097222] mmc0: error -5 whilst initialising MMC card
10617 09:27:04.720013 <6>[ 2.102683] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10618 09:27:04.730116 <6>[ 2.116009] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10619 09:27:04.737180 <6>[ 2.125440] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10620 09:27:04.743536 <6>[ 2.131517] xhci-mtk 11200000.usb: xHCI Host Controller
10621 09:27:04.750618 <6>[ 2.136998] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10622 09:27:04.757069 <6>[ 2.144646] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10623 09:27:04.760319 <6>[ 2.152297] hub 1-0:1.0: USB hub found
10624 09:27:04.767216 <6>[ 2.156322] hub 1-0:1.0: 1 port detected
10625 09:27:04.773762 <6>[ 2.160602] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10626 09:27:04.780234 <6>[ 2.169152] hub 2-0:1.0: USB hub found
10627 09:27:04.783481 <6>[ 2.173158] hub 2-0:1.0: 1 port detected
10628 09:27:04.790203 <6>[ 2.179869] mtk-msdc 11f70000.mmc: Got CD GPIO
10629 09:27:04.805278 <6>[ 2.191361] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10630 09:27:04.815457 <6>[ 2.199835] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10631 09:27:04.821568 <6>[ 2.208184] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10632 09:27:04.831869 <6>[ 2.216548] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10633 09:27:04.838198 <6>[ 2.224890] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10634 09:27:04.848489 <6>[ 2.233242] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10635 09:27:04.854971 <6>[ 2.241581] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10636 09:27:04.865138 <6>[ 2.249930] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10637 09:27:04.871560 <6>[ 2.258271] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10638 09:27:04.881762 <6>[ 2.266620] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10639 09:27:04.888120 <6>[ 2.274959] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10640 09:27:04.898001 <6>[ 2.283317] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10641 09:27:04.905080 <6>[ 2.291658] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10642 09:27:04.914746 <6>[ 2.300012] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10643 09:27:04.921724 <6>[ 2.308353] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10644 09:27:04.928039 <6>[ 2.317100] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10645 09:27:04.934503 <6>[ 2.324293] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10646 09:27:04.941421 <6>[ 2.331068] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10647 09:27:04.951624 <6>[ 2.337874] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10648 09:27:04.958118 <6>[ 2.344810] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10649 09:27:04.964812 <6>[ 2.351589] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10650 09:27:04.974834 <6>[ 2.360717] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10651 09:27:04.985073 <6>[ 2.369836] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10652 09:27:04.994690 <6>[ 2.379131] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10653 09:27:05.004536 <6>[ 2.388599] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10654 09:27:05.011538 <6>[ 2.398068] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10655 09:27:05.021458 <6>[ 2.407188] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10656 09:27:05.031552 <6>[ 2.416654] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10657 09:27:05.041011 <6>[ 2.425773] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10658 09:27:05.051173 <6>[ 2.435068] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10659 09:27:05.057578 <6>[ 2.442599] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10660 09:27:05.067817 <6>[ 2.445285] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10661 09:27:05.070868 <6>[ 2.461640] mmc0: Command Queue Engine enabled
10662 09:27:05.080703 <6>[ 2.462727] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10663 09:27:05.087737 <6>[ 2.466362] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10664 09:27:05.094067 <6>[ 2.477492] Trying to probe devices needed for running init ...
10665 09:27:05.097817 <6>[ 2.482157] mmcblk0: mmc0:0001 DA4128 116 GiB
10666 09:27:05.107215 <3>[ 2.488546] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10667 09:27:05.111005 <6>[ 2.496662] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10668 09:27:05.118970 <6>[ 2.508173] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10669 09:27:05.125087 <6>[ 2.514028] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10670 09:27:05.132143 <6>[ 2.519825] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10671 09:27:05.206524 <6>[ 2.592764] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10672 09:27:05.361089 <6>[ 2.750800] hub 1-1:1.0: USB hub found
10673 09:27:05.364338 <6>[ 2.755331] hub 1-1:1.0: 4 ports detected
10674 09:27:05.377459 <6>[ 2.766994] hub 1-1:1.0: USB hub found
10675 09:27:05.380476 <6>[ 2.771296] hub 1-1:1.0: 4 ports detected
10676 09:27:05.486942 <6>[ 2.873256] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10677 09:27:05.514699 <6>[ 2.904016] hub 2-1:1.0: USB hub found
10678 09:27:05.517892 <6>[ 2.908575] hub 2-1:1.0: 3 ports detected
10679 09:27:05.530670 <6>[ 2.920430] hub 2-1:1.0: USB hub found
10680 09:27:05.533879 <6>[ 2.924955] hub 2-1:1.0: 3 ports detected
10681 09:27:05.702578 <6>[ 3.088737] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10682 09:27:05.835060 <6>[ 3.224749] hub 1-1.4:1.0: USB hub found
10683 09:27:05.838449 <6>[ 3.229284] hub 1-1.4:1.0: 2 ports detected
10684 09:27:05.850653 <6>[ 3.239843] hub 1-1.4:1.0: USB hub found
10685 09:27:05.853538 <6>[ 3.244368] hub 1-1.4:1.0: 2 ports detected
10686 09:27:05.914946 <6>[ 3.301110] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10687 09:27:06.023207 <6>[ 3.409549] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10688 09:27:06.059754 <4>[ 3.446140] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10689 09:27:06.069722 <4>[ 3.455236] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10690 09:27:06.108697 <6>[ 3.498556] r8152 2-1.3:1.0 eth0: v1.12.13
10691 09:27:06.154075 <6>[ 3.540651] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10692 09:27:06.342599 <6>[ 3.728937] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10693 09:27:07.677053 <6>[ 5.066588] r8152 2-1.3:1.0 eth0: carrier on
10694 09:27:10.310514 <5>[ 5.092715] Sending DHCP requests .., OK
10695 09:27:10.317157 <6>[ 7.704993] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10696 09:27:10.320281 <6>[ 7.713295] IP-Config: Complete:
10697 09:27:10.333496 <6>[ 7.716787] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10698 09:27:10.340375 <6>[ 7.727545] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10699 09:27:10.346734 <6>[ 7.736166] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10700 09:27:10.353724 <6>[ 7.736175] nameserver0=192.168.201.1
10701 09:27:10.356739 <6>[ 7.748342] clk: Disabling unused clocks
10702 09:27:10.360107 <6>[ 7.753740] ALSA device list:
10703 09:27:10.366855 <6>[ 7.757148] No soundcards found.
10704 09:27:10.374859 <6>[ 7.764887] Freeing unused kernel memory: 8512K
10705 09:27:10.378362 <6>[ 7.769832] Run /init as init process
10706 09:27:10.387495 Loading, please wait...
10707 09:27:10.416747 Starting systemd-udevd version 252.22-1~deb12u1
10708 09:27:10.708575 <6>[ 8.095240] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10709 09:27:10.724576 <6>[ 8.111158] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10710 09:27:10.731036 <6>[ 8.113702] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10711 09:27:10.740988 <6>[ 8.119131] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10712 09:27:10.747648 <6>[ 8.123218] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10713 09:27:10.753932 <6>[ 8.123250] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10714 09:27:10.764159 <4>[ 8.123594] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10715 09:27:10.774299 <6>[ 8.124323] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10716 09:27:10.780600 <6>[ 8.124329] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10717 09:27:10.790796 <6>[ 8.124801] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10718 09:27:10.797042 <6>[ 8.124816] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10719 09:27:10.803989 <6>[ 8.124826] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10720 09:27:10.814055 <6>[ 8.124832] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10721 09:27:10.820791 <6>[ 8.139214] remoteproc remoteproc0: scp is available
10722 09:27:10.827304 <6>[ 8.143122] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10723 09:27:10.833694 <6>[ 8.151356] remoteproc remoteproc0: powering up scp
10724 09:27:10.840080 <3>[ 8.161646] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 09:27:10.850554 <6>[ 8.169058] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10726 09:27:10.857177 <3>[ 8.176498] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 09:27:10.863413 <6>[ 8.184665] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10728 09:27:10.870528 <3>[ 8.192024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 09:27:10.876982 <6>[ 8.195144] mc: Linux media interface: v0.10
10730 09:27:10.883968 <4>[ 8.221134] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10731 09:27:10.891038 <3>[ 8.223333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 09:27:10.900526 <6>[ 8.223656] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10733 09:27:10.903703 <6>[ 8.224092] videodev: Linux video capture interface: v2.00
10734 09:27:10.910699 <4>[ 8.228870] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10735 09:27:10.920754 <3>[ 8.236397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 09:27:10.930156 <4>[ 8.255863] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10737 09:27:10.933806 <4>[ 8.255863] Fallback method does not support PEC.
10738 09:27:10.943796 <3>[ 8.258873] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 09:27:10.950019 <3>[ 8.282394] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10740 09:27:10.957057 <6>[ 8.286081] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10741 09:27:10.963527 <6>[ 8.286085] pci_bus 0000:00: root bus resource [bus 00-ff]
10742 09:27:10.969871 <6>[ 8.286090] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10743 09:27:10.980134 <6>[ 8.286092] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10744 09:27:10.987114 <6>[ 8.286118] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10745 09:27:10.993264 <6>[ 8.286131] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10746 09:27:11.000297 <6>[ 8.286200] pci 0000:00:00.0: supports D1 D2
10747 09:27:11.006556 <6>[ 8.286203] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10748 09:27:11.013602 <3>[ 8.286667] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 09:27:11.023832 <6>[ 8.287092] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10750 09:27:11.026881 <6>[ 8.287185] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10751 09:27:11.036942 <6>[ 8.287209] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10752 09:27:11.043485 <6>[ 8.287226] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10753 09:27:11.050502 <6>[ 8.287241] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10754 09:27:11.056854 <6>[ 8.287349] pci 0000:01:00.0: supports D1 D2
10755 09:27:11.063528 <6>[ 8.287351] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10756 09:27:11.073152 <6>[ 8.297108] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10757 09:27:11.080110 <3>[ 8.300007] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 09:27:11.090284 <3>[ 8.300063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 09:27:11.096910 <6>[ 8.300808] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10760 09:27:11.103258 <6>[ 8.300832] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10761 09:27:11.109663 <6>[ 8.300835] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10762 09:27:11.119785 <6>[ 8.300842] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10763 09:27:11.126169 <6>[ 8.300855] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10764 09:27:11.136811 <6>[ 8.300868] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10765 09:27:11.139783 <6>[ 8.300880] pci 0000:00:00.0: PCI bridge to [bus 01]
10766 09:27:11.149636 <6>[ 8.300885] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10767 09:27:11.156597 <6>[ 8.301014] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10768 09:27:11.162977 <6>[ 8.301515] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10769 09:27:11.165999 <6>[ 8.302082] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10770 09:27:11.175965 <6>[ 8.307629] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10771 09:27:11.182951 <3>[ 8.315411] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 09:27:11.192618 <3>[ 8.315414] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 09:27:11.199447 <6>[ 8.329128] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10774 09:27:11.209278 <6>[ 8.329172] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10775 09:27:11.215425 <6>[ 8.329179] remoteproc remoteproc0: remote processor scp is now up
10776 09:27:11.222426 <3>[ 8.337122] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 09:27:11.228872 <3>[ 8.337171] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 09:27:11.238829 <6>[ 8.353013] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10779 09:27:11.248474 <3>[ 8.358547] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 09:27:11.255221 <3>[ 8.358551] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 09:27:11.264783 <3>[ 8.358554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 09:27:11.271730 <3>[ 8.358556] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 09:27:11.281621 <3>[ 8.358570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 09:27:11.288551 <6>[ 8.369341] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10785 09:27:11.295000 <5>[ 8.385167] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10786 09:27:11.304870 <6>[ 8.394336] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10787 09:27:11.308267 <6>[ 8.401639] Bluetooth: Core ver 2.22
10788 09:27:11.314830 <6>[ 8.412705] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10789 09:27:11.324375 <3>[ 8.413553] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10790 09:27:11.331220 <5>[ 8.415585] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10791 09:27:11.337533 <5>[ 8.415827] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10792 09:27:11.347865 <4>[ 8.415879] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10793 09:27:11.353920 <6>[ 8.415884] cfg80211: failed to load regulatory.db
10794 09:27:11.357626 <6>[ 8.417469] NET: Registered PF_BLUETOOTH protocol family
10795 09:27:11.370762 <6>[ 8.425042] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10796 09:27:11.377146 <6>[ 8.431138] Bluetooth: HCI device and connection manager initialized
10797 09:27:11.383985 <6>[ 8.431167] Bluetooth: HCI socket layer initialized
10798 09:27:11.390738 <6>[ 8.432266] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10799 09:27:11.393943 <6>[ 8.438825] usbcore: registered new interface driver uvcvideo
10800 09:27:11.400136 <6>[ 8.446212] Bluetooth: L2CAP socket layer initialized
10801 09:27:11.406852 <6>[ 8.502502] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10802 09:27:11.413581 <6>[ 8.506763] Bluetooth: SCO socket layer initialized
10803 09:27:11.420026 <6>[ 8.514844] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10804 09:27:11.426614 <6>[ 8.562729] usbcore: registered new interface driver btusb
10805 09:27:11.436407 <4>[ 8.563643] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10806 09:27:11.443118 <3>[ 8.563658] Bluetooth: hci0: Failed to load firmware file (-2)
10807 09:27:11.446395 <3>[ 8.563665] Bluetooth: hci0: Failed to set up firmware (-2)
10808 09:27:11.456662 <4>[ 8.563672] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10809 09:27:11.463015 <6>[ 8.588769] mt7921e 0000:01:00.0: ASIC revision: 79610010
10810 09:27:11.565310 <6>[ 8.952524] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10811 09:27:11.568916 <6>[ 8.952524]
10812 09:27:11.572091 Begin: Loading essential drivers ... done.
10813 09:27:11.575319 Begin: Running /scripts/init-premount ... done.
10814 09:27:11.582263 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10815 09:27:11.592154 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10816 09:27:11.595515 Device /sys/class/net/eth0 found
10817 09:27:11.595684 done.
10818 09:27:11.601827 Begin: Waiting up to 180 secs for any network device to become available ... done.
10819 09:27:11.694963 IP-Config: eth0 hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10820 09:27:11.701094 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10821 09:27:11.707878 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10822 09:27:11.714265 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10823 09:27:11.721138 host : mt8192-asurada-spherion-r0-cbg-8
10824 09:27:11.727905 domain : lava-rack
10825 09:27:11.731028 rootserver: 192.168.201.1 rootpath:
10826 09:27:11.731126 filename :
10827 09:27:11.738669 done.
10828 09:27:11.745737 Begin: Running /scripts/nfs-bottom ... done.
10829 09:27:11.762666 Begin: Running /scripts/init-bottom ... done.
10830 09:27:11.834145 <6>[ 9.221163] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10831 09:27:13.171228 <6>[ 10.561752] NET: Registered PF_INET6 protocol family
10832 09:27:13.178598 <6>[ 10.568933] Segment Routing with IPv6
10833 09:27:13.181676 <6>[ 10.572915] In-situ OAM (IOAM) with IPv6
10834 09:27:13.357494 <30>[ 10.721697] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10835 09:27:13.364225 <30>[ 10.754843] systemd[1]: Detected architecture arm64.
10836 09:27:13.373519
10837 09:27:13.376624 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10838 09:27:13.376729
10839 09:27:13.400301 <30>[ 10.790525] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10840 09:27:14.489079 <30>[ 11.876496] systemd[1]: Queued start job for default target graphical.target.
10841 09:27:14.542833 <30>[ 11.930088] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10842 09:27:14.549140 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10843 09:27:14.571401 <30>[ 11.958633] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10844 09:27:14.581022 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10845 09:27:14.599707 <30>[ 11.986586] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10846 09:27:14.609227 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10847 09:27:14.627034 <30>[ 12.014252] systemd[1]: Created slice user.slice - User and Session Slice.
10848 09:27:14.633697 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10849 09:27:14.657123 <30>[ 12.041227] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10850 09:27:14.667175 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10851 09:27:14.685160 <30>[ 12.069125] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10852 09:27:14.691921 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10853 09:27:14.720342 <30>[ 12.097559] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10854 09:27:14.730347 <30>[ 12.117549] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10855 09:27:14.736920 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10856 09:27:14.753985 <30>[ 12.140898] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10857 09:27:14.760116 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10858 09:27:14.777963 <30>[ 12.164936] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10859 09:27:14.787493 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10860 09:27:14.802486 <30>[ 12.193020] systemd[1]: Reached target paths.target - Path Units.
10861 09:27:14.812046 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10862 09:27:14.830216 <30>[ 12.217346] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10863 09:27:14.836662 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10864 09:27:14.850151 <30>[ 12.240897] systemd[1]: Reached target slices.target - Slice Units.
10865 09:27:14.860564 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10866 09:27:14.875152 <30>[ 12.265389] systemd[1]: Reached target swap.target - Swaps.
10867 09:27:14.881221 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10868 09:27:14.901890 <30>[ 12.289399] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10869 09:27:14.911936 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10870 09:27:14.930439 <30>[ 12.317860] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10871 09:27:14.940450 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10872 09:27:14.960890 <30>[ 12.348097] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10873 09:27:14.970982 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10874 09:27:14.987320 <30>[ 12.374434] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10875 09:27:14.997019 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10876 09:27:15.014182 <30>[ 12.401543] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10877 09:27:15.021011 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10878 09:27:15.039203 <30>[ 12.426477] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10879 09:27:15.049274 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10880 09:27:15.068602 <30>[ 12.455885] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10881 09:27:15.078161 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10882 09:27:15.094097 <30>[ 12.481382] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10883 09:27:15.103749 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10884 09:27:15.161733 <30>[ 12.549087] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10885 09:27:15.168357 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10886 09:27:15.190568 <30>[ 12.577820] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10887 09:27:15.196849 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10888 09:27:15.223301 <30>[ 12.610366] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10889 09:27:15.229854 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10890 09:27:15.256797 <30>[ 12.637132] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10891 09:27:15.298367 <30>[ 12.685615] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10892 09:27:15.308375 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10893 09:27:15.330985 <30>[ 12.718564] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10894 09:27:15.337774 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10895 09:27:15.362759 <30>[ 12.750246] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10896 09:27:15.369748 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10897 09:27:15.412845 <6>[ 12.800031] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10898 09:27:15.422557 <30>[ 12.805813] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10899 09:27:15.429078 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10900 09:27:15.451102 <30>[ 12.838514] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10901 09:27:15.461026 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10902 09:27:15.482828 <30>[ 12.870432] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10903 09:27:15.489876 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10904 09:27:15.513673 <30>[ 12.901132] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10905 09:27:15.520456 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10906 09:27:15.530437 <6>[ 12.921224] fuse: init (API version 7.37)
10907 09:27:15.547454 <30>[ 12.934996] systemd[1]: Starting systemd-journald.service - Journal Service...
10908 09:27:15.554300 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10909 09:27:15.614754 <30>[ 13.001995] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10910 09:27:15.621122 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10911 09:27:15.648181 <30>[ 13.032385] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10912 09:27:15.655265 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10913 09:27:15.679793 <30>[ 13.067344] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10914 09:27:15.689780 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10915 09:27:15.710400 <30>[ 13.097872] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10916 09:27:15.720503 <3>[ 13.106983] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 09:27:15.727356 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10918 09:27:15.753225 <30>[ 13.140832] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10919 09:27:15.760144 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10920 09:27:15.773698 <3>[ 13.160682] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 09:27:15.783356 <30>[ 13.170357] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10922 09:27:15.789652 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10923 09:27:15.811079 <30>[ 13.197577] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10924 09:27:15.821013 [[0;32m OK [<3>[ 13.206461] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 09:27:15.827359 0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10926 09:27:15.847300 <30>[ 13.233935] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10927 09:27:15.860111 [[0;32m OK [0m] Finished [0<3>[ 13.245505] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 09:27:15.863444 ;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10929 09:27:15.882753 <30>[ 13.270410] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10930 09:27:15.889702 <30>[ 13.278430] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10931 09:27:15.900000 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10932 09:27:15.910289 <3>[ 13.295546] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 09:27:15.916680 <30>[ 13.306166] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10934 09:27:15.926944 <30>[ 13.313945] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10935 09:27:15.933300 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10936 09:27:15.954181 <3>[ 13.341768] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 09:27:15.961039 <30>[ 13.342066] systemd[1]: modprobe@drm.service: Deactivated successfully.
10938 09:27:15.970938 <30>[ 13.358434] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10939 09:27:15.985008 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Mod<3>[ 13.372021] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 09:27:15.987909 ule drm.
10941 09:27:16.007121 <30>[ 13.393914] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10942 09:27:16.014157 <30>[ 13.401940] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10943 09:27:16.023961 <3>[ 13.404657] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 09:27:16.033872 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10945 09:27:16.048242 <30>[ 13.438620] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10946 09:27:16.058570 <3>[ 13.442213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 09:27:16.068052 <30>[ 13.446549] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10948 09:27:16.075054 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10949 09:27:16.088570 <3>[ 13.476055] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 09:27:16.099481 <30>[ 13.486980] systemd[1]: modprobe@loop.service: Deactivated successfully.
10951 09:27:16.105926 <30>[ 13.494640] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10952 09:27:16.116132 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10953 09:27:16.138298 <30>[ 13.525761] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10954 09:27:16.145294 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10955 09:27:16.157345 <3>[ 13.544836] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 09:27:16.167344 <3>[ 13.545721] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10957 09:27:16.178217 <30>[ 13.554505] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10958 09:27:16.194892 <4>[ 13.562770] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10959 09:27:16.201478 <3>[ 13.562774] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10960 09:27:16.211003 <3>[ 13.573672] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 09:27:16.217490 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10962 09:27:16.239337 <30>[ 13.626258] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10963 09:27:16.249107 <3>[ 13.627294] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 09:27:16.255728 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10965 09:27:16.275658 <30>[ 13.662214] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10966 09:27:16.282047 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10967 09:27:16.302342 <30>[ 13.689374] systemd[1]: Reached target network-pre.target - Preparation for Network.
10968 09:27:16.308453 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10969 09:27:16.361990 <30>[ 13.749374] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10970 09:27:16.368488 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10971 09:27:16.394429 <30>[ 13.782074] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10972 09:27:16.404437 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10973 09:27:16.424937 <30>[ 13.809186] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10974 09:27:16.441837 <30>[ 13.822842] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10975 09:27:16.456318 <30>[ 13.844078] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10976 09:27:16.462780 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10977 09:27:16.489498 <30>[ 13.873763] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10978 09:27:16.533982 <30>[ 13.921723] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10979 09:27:16.540696 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10980 09:27:16.594580 <30>[ 13.982311] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10981 09:27:16.601108 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10982 09:27:16.633030 <30>[ 14.020440] systemd[1]: Started systemd-journald.service - Journal Service.
10983 09:27:16.639417 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10984 09:27:16.666005 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10985 09:27:16.722797 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10986 09:27:16.722963 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10987 09:27:16.727208 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10988 09:27:16.747303 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10989 09:27:16.806983 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10990 09:27:16.830115 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10991 09:27:16.898199 <46>[ 14.285651] systemd-journald[317]: Received client request to flush runtime journal.
10992 09:27:16.945272 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10993 09:27:16.965895 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10994 09:27:16.981481 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10995 09:27:17.682184 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10996 09:27:18.328488 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10997 09:27:18.370254 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10998 09:27:18.473471 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10999 09:27:18.527433 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11000 09:27:18.583665 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11001 09:27:18.893553 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11002 09:27:18.910411 <6>[ 16.301288] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11003 09:27:18.950958 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11004 09:27:18.984556 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11005 09:27:19.076256 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11006 09:27:19.094614 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11007 09:27:19.166760 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11008 09:27:19.206743 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11009 09:27:19.226414 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11010 09:27:19.299126 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11011 09:27:19.318134 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11012 09:27:19.390396 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11013 09:27:19.412116 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11014 09:27:19.465514 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11015 09:27:19.577466 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11016 09:27:19.597805 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11017 09:27:19.621374 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11018 09:27:19.637243 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11019 09:27:19.662400 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11020 09:27:19.684924 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11021 09:27:19.701253 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11022 09:27:19.720986 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11023 09:27:19.740918 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11024 09:27:19.757135 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11025 09:27:19.774373 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11026 09:27:19.793269 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11027 09:27:19.809669 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11028 09:27:19.854635 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11029 09:27:19.892255 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11030 09:27:19.973632 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11031 09:27:19.999809 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11032 09:27:20.167132 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11033 09:27:20.227290 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11034 09:27:20.257133 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11035 09:27:20.279553 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11036 09:27:20.300617 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11037 09:27:20.340048 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11038 09:27:20.363821 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11039 09:27:20.383745 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11040 09:27:20.402525 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11041 09:27:20.454893 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11042 09:27:20.502395 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11043 09:27:20.589445
11044 09:27:20.593110 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11045 09:27:20.593254
11046 09:27:20.596041 debian-bookworm-arm64 login: root (automatic login)
11047 09:27:20.596141
11048 09:27:20.868275 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
11049 09:27:20.868433
11050 09:27:20.875119 The programs included with the Debian GNU/Linux system are free software;
11051 09:27:20.881964 the exact distribution terms for each program are described in the
11052 09:27:20.885162 individual files in /usr/share/doc/*/copyright.
11053 09:27:20.885263
11054 09:27:20.891466 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11055 09:27:20.894537 permitted by applicable law.
11056 09:27:21.001975 Matched prompt #10: / #
11058 09:27:21.002329 Setting prompt string to ['/ #']
11059 09:27:21.002446 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11061 09:27:21.002765 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11062 09:27:21.002875 start: 2.2.6 expect-shell-connection (timeout 00:03:23) [common]
11063 09:27:21.002968 Setting prompt string to ['/ #']
11064 09:27:21.003051 Forcing a shell prompt, looking for ['/ #']
11066 09:27:21.053298 / #
11067 09:27:21.053488 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11068 09:27:21.053585 Waiting using forced prompt support (timeout 00:02:30)
11069 09:27:21.058089
11070 09:27:21.058395 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11071 09:27:21.058627 start: 2.2.7 export-device-env (timeout 00:03:23) [common]
11073 09:27:21.158972 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407676/extract-nfsrootfs-3y43sa5u'
11074 09:27:21.163745 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407676/extract-nfsrootfs-3y43sa5u'
11076 09:27:21.264255 / # export NFS_SERVER_IP='192.168.201.1'
11077 09:27:21.269592 export NFS_SERVER_IP='192.168.201.1'
11078 09:27:21.269893 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11079 09:27:21.269992 end: 2.2 depthcharge-retry (duration 00:01:37) [common]
11080 09:27:21.270109 end: 2 depthcharge-action (duration 00:01:37) [common]
11081 09:27:21.270226 start: 3 lava-test-retry (timeout 00:01:00) [common]
11082 09:27:21.270338 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11083 09:27:21.270444 Using namespace: common
11085 09:27:21.370794 / # #
11086 09:27:21.371024 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11087 09:27:21.375951 #
11088 09:27:21.376213 Using /lava-14407676
11090 09:27:21.476568 / # export SHELL=/bin/sh
11091 09:27:21.481593 export SHELL=/bin/sh
11093 09:27:21.582095 / # . /lava-14407676/environment
11094 09:27:21.587402 . /lava-14407676/environment
11096 09:27:21.694235 / # /lava-14407676/bin/lava-test-runner /lava-14407676/0
11097 09:27:21.694463 Test shell timeout: 10s (minimum of the action and connection timeout)
11098 09:27:21.699425 /lava-14407676/bin/lava-test-runner /lava-14407676/0
11099 09:27:21.951480 + export TESTRUN_ID=0_dmesg
11100 09:27:21.954660 + cd /lava-14407676/0/tests/0_dmesg
11101 09:27:21.957594 + cat uuid
11102 09:27:21.971360 + UUID=14407676_1.<8>[ 19.359774] <LAVA_SIGNAL_STARTRUN 0_dmesg 14407676_1.6.2.3.1>
11103 09:27:21.971459 6.2.3.1
11104 09:27:21.971550 + set +x
11105 09:27:21.971815 Received signal: <STARTRUN> 0_dmesg 14407676_1.6.2.3.1
11106 09:27:21.971906 Starting test lava.0_dmesg (14407676_1.6.2.3.1)
11107 09:27:21.972013 Skipping test definition patterns.
11108 09:27:21.978250 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11109 09:27:22.093895 <8>[ 19.481909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11110 09:27:22.094191 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11112 09:27:22.191715 <8>[ 19.579925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11113 09:27:22.192008 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11115 09:27:22.290736 <8>[ 19.678673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11116 09:27:22.291035 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11118 09:27:22.297190 + <8>[ 19.688414] <LAVA_SIGNAL_ENDRUN 0_dmesg 14407676_1.6.2.3.1>
11119 09:27:22.297274 set +x
11120 09:27:22.297504 Received signal: <ENDRUN> 0_dmesg 14407676_1.6.2.3.1
11121 09:27:22.297589 Ending use of test pattern.
11122 09:27:22.297649 Ending test lava.0_dmesg (14407676_1.6.2.3.1), duration 0.33
11124 09:27:22.306689 <LAVA_TEST_RUNNER EXIT>
11125 09:27:22.306933 ok: lava_test_shell seems to have completed
11126 09:27:22.307031 alert: pass
crit: pass
emerg: pass
11127 09:27:22.307118 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11128 09:27:22.307205 end: 3 lava-test-retry (duration 00:00:01) [common]
11129 09:27:22.307294 start: 4 finalize (timeout 00:07:54) [common]
11130 09:27:22.307378 start: 4.1 power-off (timeout 00:00:30) [common]
11131 09:27:22.307509 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11132 09:27:22.497276 >> Command sent successfully.
11133 09:27:22.500476 Returned 0 in 0 seconds
11134 09:27:22.600768 end: 4.1 power-off (duration 00:00:00) [common]
11136 09:27:22.601077 start: 4.2 read-feedback (timeout 00:07:54) [common]
11137 09:27:22.601326 Listened to connection for namespace 'common' for up to 1s
11138 09:27:23.602262 Finalising connection for namespace 'common'
11139 09:27:23.602429 Disconnecting from shell: Finalise
11140 09:27:23.602512 / #
11141 09:27:23.702770 end: 4.2 read-feedback (duration 00:00:01) [common]
11142 09:27:23.702957 end: 4 finalize (duration 00:00:01) [common]
11143 09:27:23.703103 Cleaning after the job
11144 09:27:23.703262 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/ramdisk
11145 09:27:23.705368 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/kernel
11146 09:27:23.715795 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/dtb
11147 09:27:23.715969 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/nfsrootfs
11148 09:27:23.769922 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407676/tftp-deploy-21hyexwe/modules
11149 09:27:23.775315 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407676
11150 09:27:24.111370 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407676
11151 09:27:24.111542 Job finished correctly