Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 09:23:34.665890 lava-dispatcher, installed at version: 2024.03
2 09:23:34.666192 start: 0 validate
3 09:23:34.666311 Start time: 2024-06-18 09:23:34.666306+00:00 (UTC)
4 09:23:34.666449 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:23:34.666591 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 09:23:34.925879 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:23:34.926074 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:23:35.188947 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:23:35.189131 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:24:35.506695 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:24:35.506856 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:24:36.035660 validate duration: 61.37
14 09:24:36.036901 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:24:36.037477 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:24:36.037970 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:24:36.038700 Not decompressing ramdisk as can be used compressed.
18 09:24:36.039183 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 09:24:36.039572 saving as /var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/ramdisk/rootfs.cpio.gz
20 09:24:36.039985 total size: 39026414 (37 MB)
21 09:24:38.705244 progress 0 % (0 MB)
22 09:24:38.745207 progress 5 % (1 MB)
23 09:24:38.761454 progress 10 % (3 MB)
24 09:24:38.772921 progress 15 % (5 MB)
25 09:24:38.782868 progress 20 % (7 MB)
26 09:24:38.792526 progress 25 % (9 MB)
27 09:24:38.802459 progress 30 % (11 MB)
28 09:24:38.812209 progress 35 % (13 MB)
29 09:24:38.822440 progress 40 % (14 MB)
30 09:24:38.832062 progress 45 % (16 MB)
31 09:24:38.841800 progress 50 % (18 MB)
32 09:24:38.851615 progress 55 % (20 MB)
33 09:24:38.861232 progress 60 % (22 MB)
34 09:24:38.871072 progress 65 % (24 MB)
35 09:24:38.880763 progress 70 % (26 MB)
36 09:24:38.890728 progress 75 % (27 MB)
37 09:24:38.900526 progress 80 % (29 MB)
38 09:24:38.910514 progress 85 % (31 MB)
39 09:24:38.920089 progress 90 % (33 MB)
40 09:24:38.929696 progress 95 % (35 MB)
41 09:24:38.939281 progress 100 % (37 MB)
42 09:24:38.939526 37 MB downloaded in 2.90 s (12.84 MB/s)
43 09:24:38.939680 end: 1.1.1 http-download (duration 00:00:03) [common]
45 09:24:38.939904 end: 1.1 download-retry (duration 00:00:03) [common]
46 09:24:38.939988 start: 1.2 download-retry (timeout 00:09:57) [common]
47 09:24:38.940066 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 09:24:38.940204 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:24:38.940269 saving as /var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/kernel/Image
50 09:24:38.940326 total size: 54813184 (52 MB)
51 09:24:38.940382 No compression specified
52 09:25:25.471349 progress 0 % (0 MB)
53 09:25:25.513358 progress 5 % (2 MB)
54 09:25:25.530858 progress 10 % (5 MB)
55 09:25:25.544549 progress 15 % (7 MB)
56 09:25:25.558254 progress 20 % (10 MB)
57 09:25:25.572011 progress 25 % (13 MB)
58 09:25:25.585650 progress 30 % (15 MB)
59 09:25:25.599684 progress 35 % (18 MB)
60 09:25:25.613578 progress 40 % (20 MB)
61 09:25:25.627400 progress 45 % (23 MB)
62 09:25:25.641205 progress 50 % (26 MB)
63 09:25:25.655001 progress 55 % (28 MB)
64 09:25:25.668545 progress 60 % (31 MB)
65 09:25:25.682372 progress 65 % (34 MB)
66 09:25:25.695954 progress 70 % (36 MB)
67 09:25:25.709563 progress 75 % (39 MB)
68 09:25:25.723318 progress 80 % (41 MB)
69 09:25:25.736750 progress 85 % (44 MB)
70 09:25:25.750318 progress 90 % (47 MB)
71 09:25:25.763834 progress 95 % (49 MB)
72 09:25:25.777115 progress 100 % (52 MB)
73 09:25:25.777330 52 MB downloaded in 46.84 s (1.12 MB/s)
74 09:25:25.777481 end: 1.2.1 http-download (duration 00:00:47) [common]
76 09:25:25.777694 end: 1.2 download-retry (duration 00:00:47) [common]
77 09:25:25.777777 start: 1.3 download-retry (timeout 00:09:10) [common]
78 09:25:25.777854 start: 1.3.1 http-download (timeout 00:09:10) [common]
79 09:25:25.778004 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:25:25.778102 saving as /var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/dtb/mt8192-asurada-spherion-r0.dtb
81 09:25:25.778157 total size: 47258 (0 MB)
82 09:25:25.778212 No compression specified
83 09:25:26.042590 progress 69 % (0 MB)
84 09:25:26.043852 progress 100 % (0 MB)
85 09:25:26.044554 0 MB downloaded in 0.27 s (0.17 MB/s)
86 09:25:26.045117 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:25:26.046095 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:25:26.046493 start: 1.4 download-retry (timeout 00:09:10) [common]
90 09:25:26.046901 start: 1.4.1 http-download (timeout 00:09:10) [common]
91 09:25:26.047429 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:25:26.047729 saving as /var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/modules/modules.tar
93 09:25:26.047986 total size: 8619356 (8 MB)
94 09:25:26.048252 Using unxz to decompress xz
95 09:25:26.054056 progress 0 % (0 MB)
96 09:25:26.106471 progress 5 % (0 MB)
97 09:25:26.133128 progress 10 % (0 MB)
98 09:25:26.158170 progress 15 % (1 MB)
99 09:25:26.181868 progress 20 % (1 MB)
100 09:25:26.206455 progress 25 % (2 MB)
101 09:25:26.230324 progress 30 % (2 MB)
102 09:25:26.254997 progress 35 % (2 MB)
103 09:25:26.278755 progress 40 % (3 MB)
104 09:25:26.302859 progress 45 % (3 MB)
105 09:25:26.327068 progress 50 % (4 MB)
106 09:25:26.352153 progress 55 % (4 MB)
107 09:25:26.376998 progress 60 % (4 MB)
108 09:25:26.401582 progress 65 % (5 MB)
109 09:25:26.429972 progress 70 % (5 MB)
110 09:25:26.455216 progress 75 % (6 MB)
111 09:25:26.479412 progress 80 % (6 MB)
112 09:25:26.503990 progress 85 % (7 MB)
113 09:25:26.528248 progress 90 % (7 MB)
114 09:25:26.554907 progress 95 % (7 MB)
115 09:25:26.582824 progress 100 % (8 MB)
116 09:25:26.587288 8 MB downloaded in 0.54 s (15.24 MB/s)
117 09:25:26.587468 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:25:26.587680 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:25:26.587766 start: 1.5 prepare-tftp-overlay (timeout 00:09:09) [common]
121 09:25:26.587846 start: 1.5.1 extract-nfsrootfs (timeout 00:09:09) [common]
122 09:25:26.587921 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:25:26.588032 start: 1.5.2 lava-overlay (timeout 00:09:09) [common]
124 09:25:26.588231 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig
125 09:25:26.588386 makedir: /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin
126 09:25:26.588490 makedir: /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/tests
127 09:25:26.588579 makedir: /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/results
128 09:25:26.588666 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-add-keys
129 09:25:26.588793 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-add-sources
130 09:25:26.588910 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-background-process-start
131 09:25:26.589029 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-background-process-stop
132 09:25:26.589152 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-common-functions
133 09:25:26.589268 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-echo-ipv4
134 09:25:26.589382 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-install-packages
135 09:25:26.589495 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-installed-packages
136 09:25:26.589607 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-os-build
137 09:25:26.589719 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-probe-channel
138 09:25:26.589831 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-probe-ip
139 09:25:26.589941 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-target-ip
140 09:25:26.590118 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-target-mac
141 09:25:26.590228 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-target-storage
142 09:25:26.590342 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-test-case
143 09:25:26.590452 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-test-event
144 09:25:26.590563 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-test-feedback
145 09:25:26.590673 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-test-raise
146 09:25:26.590784 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-test-reference
147 09:25:26.590895 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-test-runner
148 09:25:26.591006 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-test-set
149 09:25:26.591117 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-test-shell
150 09:25:26.591230 Updating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-install-packages (oe)
151 09:25:26.591368 Updating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/bin/lava-installed-packages (oe)
152 09:25:26.591481 Creating /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/environment
153 09:25:26.591590 LAVA metadata
154 09:25:26.591682 - LAVA_JOB_ID=14407640
155 09:25:26.591769 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:25:26.591900 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:09) [common]
157 09:25:26.591983 skipped lava-vland-overlay
158 09:25:26.592055 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:25:26.592156 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:09) [common]
160 09:25:26.592214 skipped lava-multinode-overlay
161 09:25:26.592281 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:25:26.592352 start: 1.5.2.3 test-definition (timeout 00:09:09) [common]
163 09:25:26.592416 Loading test definitions
164 09:25:26.592491 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:09) [common]
165 09:25:26.592550 Using /lava-14407640 at stage 0
166 09:25:26.592845 uuid=14407640_1.5.2.3.1 testdef=None
167 09:25:26.592925 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:25:26.593000 start: 1.5.2.3.2 test-overlay (timeout 00:09:09) [common]
169 09:25:26.593427 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:25:26.593625 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:09) [common]
172 09:25:26.594218 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:25:26.594436 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:09) [common]
175 09:25:26.595125 runner path: /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/0/tests/0_cros-ec test_uuid 14407640_1.5.2.3.1
176 09:25:26.595271 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:25:26.595462 Creating lava-test-runner.conf files
179 09:25:26.595518 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407640/lava-overlay-laj6_vig/lava-14407640/0 for stage 0
180 09:25:26.595598 - 0_cros-ec
181 09:25:26.595688 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 09:25:26.595765 start: 1.5.2.4 compress-overlay (timeout 00:09:09) [common]
183 09:25:26.602162 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 09:25:26.602258 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:09) [common]
185 09:25:26.602338 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 09:25:26.602414 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 09:25:26.602491 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:09) [common]
188 09:25:27.816699 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 09:25:27.816899 start: 1.5.4 extract-modules (timeout 00:09:08) [common]
190 09:25:27.817011 extracting modules file /var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407640/extract-overlay-ramdisk-hh1vf2w7/ramdisk
191 09:25:28.057694 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 09:25:28.057867 start: 1.5.5 apply-overlay-tftp (timeout 00:09:08) [common]
193 09:25:28.057946 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407640/compress-overlay-mf3o9coo/overlay-1.5.2.4.tar.gz to ramdisk
194 09:25:28.058043 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407640/compress-overlay-mf3o9coo/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407640/extract-overlay-ramdisk-hh1vf2w7/ramdisk
195 09:25:28.064289 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 09:25:28.064389 start: 1.5.6 configure-preseed-file (timeout 00:09:08) [common]
197 09:25:28.064469 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 09:25:28.064548 start: 1.5.7 compress-ramdisk (timeout 00:09:08) [common]
199 09:25:28.064622 Building ramdisk /var/lib/lava/dispatcher/tmp/14407640/extract-overlay-ramdisk-hh1vf2w7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407640/extract-overlay-ramdisk-hh1vf2w7/ramdisk
200 09:25:28.935335 >> 336002 blocks
201 09:25:34.317693 rename /var/lib/lava/dispatcher/tmp/14407640/extract-overlay-ramdisk-hh1vf2w7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/ramdisk/ramdisk.cpio.gz
202 09:25:34.317857 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 09:25:34.317948 start: 1.5.8 prepare-kernel (timeout 00:09:02) [common]
204 09:25:34.318075 start: 1.5.8.1 prepare-fit (timeout 00:09:02) [common]
205 09:25:34.318155 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/kernel/Image']
206 09:25:47.733534 Returned 0 in 13 seconds
207 09:25:47.834092 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/kernel/image.itb
208 09:25:48.661098 output: FIT description: Kernel Image image with one or more FDT blobs
209 09:25:48.661228 output: Created: Tue Jun 18 10:25:48 2024
210 09:25:48.661292 output: Image 0 (kernel-1)
211 09:25:48.661346 output: Description:
212 09:25:48.661403 output: Created: Tue Jun 18 10:25:48 2024
213 09:25:48.661456 output: Type: Kernel Image
214 09:25:48.661507 output: Compression: lzma compressed
215 09:25:48.661561 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
216 09:25:48.661612 output: Architecture: AArch64
217 09:25:48.661661 output: OS: Linux
218 09:25:48.661709 output: Load Address: 0x00000000
219 09:25:48.661757 output: Entry Point: 0x00000000
220 09:25:48.661805 output: Hash algo: crc32
221 09:25:48.661857 output: Hash value: 4137a6e7
222 09:25:48.661907 output: Image 1 (fdt-1)
223 09:25:48.661960 output: Description: mt8192-asurada-spherion-r0
224 09:25:48.662070 output: Created: Tue Jun 18 10:25:48 2024
225 09:25:48.662146 output: Type: Flat Device Tree
226 09:25:48.662202 output: Compression: uncompressed
227 09:25:48.662258 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 09:25:48.662327 output: Architecture: AArch64
229 09:25:48.662382 output: Hash algo: crc32
230 09:25:48.662469 output: Hash value: 0f8e4d2e
231 09:25:48.662524 output: Image 2 (ramdisk-1)
232 09:25:48.662622 output: Description: unavailable
233 09:25:48.662687 output: Created: Tue Jun 18 10:25:48 2024
234 09:25:48.662768 output: Type: RAMDisk Image
235 09:25:48.662816 output: Compression: uncompressed
236 09:25:48.662864 output: Data Size: 52146341 Bytes = 50924.16 KiB = 49.73 MiB
237 09:25:48.662925 output: Architecture: AArch64
238 09:25:48.662974 output: OS: Linux
239 09:25:48.663021 output: Load Address: unavailable
240 09:25:48.663068 output: Entry Point: unavailable
241 09:25:48.663116 output: Hash algo: crc32
242 09:25:48.663164 output: Hash value: efd73404
243 09:25:48.663242 output: Default Configuration: 'conf-1'
244 09:25:48.663309 output: Configuration 0 (conf-1)
245 09:25:48.663371 output: Description: mt8192-asurada-spherion-r0
246 09:25:48.663419 output: Kernel: kernel-1
247 09:25:48.663482 output: Init Ramdisk: ramdisk-1
248 09:25:48.663532 output: FDT: fdt-1
249 09:25:48.663581 output: Loadables: kernel-1
250 09:25:48.663629 output:
251 09:25:48.663765 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 09:25:48.663853 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 09:25:48.663945 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 09:25:48.664027 start: 1.6 lxc-create-udev-rule-action (timeout 00:08:47) [common]
255 09:25:48.664094 No LXC device requested
256 09:25:48.664195 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 09:25:48.664284 start: 1.7 deploy-device-env (timeout 00:08:47) [common]
258 09:25:48.664393 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 09:25:48.664499 Checking files for TFTP limit of 4294967296 bytes.
260 09:25:48.665173 end: 1 tftp-deploy (duration 00:01:13) [common]
261 09:25:48.665275 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 09:25:48.665357 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 09:25:48.665460 substitutions:
264 09:25:48.665517 - {DTB}: 14407640/tftp-deploy-n564n2y3/dtb/mt8192-asurada-spherion-r0.dtb
265 09:25:48.665575 - {INITRD}: 14407640/tftp-deploy-n564n2y3/ramdisk/ramdisk.cpio.gz
266 09:25:48.665627 - {KERNEL}: 14407640/tftp-deploy-n564n2y3/kernel/Image
267 09:25:48.665677 - {LAVA_MAC}: None
268 09:25:48.665727 - {PRESEED_CONFIG}: None
269 09:25:48.665778 - {PRESEED_LOCAL}: None
270 09:25:48.665826 - {RAMDISK}: 14407640/tftp-deploy-n564n2y3/ramdisk/ramdisk.cpio.gz
271 09:25:48.665883 - {ROOT_PART}: None
272 09:25:48.665951 - {ROOT}: None
273 09:25:48.666030 - {SERVER_IP}: 192.168.201.1
274 09:25:48.666081 - {TEE}: None
275 09:25:48.666146 Parsed boot commands:
276 09:25:48.666269 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 09:25:48.666417 Parsed boot commands: tftpboot 192.168.201.1 14407640/tftp-deploy-n564n2y3/kernel/image.itb 14407640/tftp-deploy-n564n2y3/kernel/cmdline
278 09:25:48.666499 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 09:25:48.666577 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 09:25:48.666653 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 09:25:48.666728 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 09:25:48.666788 Not connected, no need to disconnect.
283 09:25:48.666854 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 09:25:48.666925 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 09:25:48.666985 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 09:25:48.670113 Setting prompt string to ['lava-test: # ']
287 09:25:48.670457 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 09:25:48.670555 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 09:25:48.670647 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 09:25:48.670747 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 09:25:48.670936 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 09:25:55.284935 >> Command sent successfully.
293 09:25:55.288989 Returned 0 in 6 seconds
294 09:25:55.389341 end: 2.2.2.1 pdu-reboot (duration 00:00:07) [common]
296 09:25:55.389740 end: 2.2.2 reset-device (duration 00:00:07) [common]
297 09:25:55.389858 start: 2.2.3 depthcharge-start (timeout 00:04:53) [common]
298 09:25:55.389972 Setting prompt string to 'Starting depthcharge on Spherion...'
299 09:25:55.390052 Changing prompt to 'Starting depthcharge on Spherion...'
300 09:25:55.390120 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 09:25:55.390480 [Enter `^Ec?' for help]
302 09:25:55.390554
303 09:25:55.390615
304 09:25:55.390674 F0: 102B 0000
305 09:25:55.390730
306 09:25:55.390785 F3: 1001 0000 [0200]
307 09:25:55.390843
308 09:25:55.390903 F3: 1001 0000
309 09:25:55.390963
310 09:25:55.391022 F7: 102D 0000
311 09:25:55.391080
312 09:25:55.391135 F1: 0000 0000
313 09:25:55.391191
314 09:25:55.391247 V0: 0000 0000 [0001]
315 09:25:55.391305
316 09:25:55.391357 00: 0007 8000
317 09:25:55.391411
318 09:25:55.391464 01: 0000 0000
319 09:25:55.391520
320 09:25:55.391573 BP: 0C00 0209 [0000]
321 09:25:55.391622
322 09:25:55.391671 G0: 1182 0000
323 09:25:55.391721
324 09:25:55.391771 EC: 0000 0021 [4000]
325 09:25:55.391820
326 09:25:55.391869 S7: 0000 0000 [0000]
327 09:25:55.391918
328 09:25:55.391967 CC: 0000 0000 [0001]
329 09:25:55.392018
330 09:25:55.392068 T0: 0000 0040 [010F]
331 09:25:55.392118
332 09:25:55.392168 Jump to BL
333 09:25:55.392218
334 09:25:55.401264
335 09:25:55.401402
336 09:25:55.408292 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 09:25:55.411529 ARM64: Exception handlers installed.
338 09:25:55.414955 ARM64: Testing exception
339 09:25:55.418542 ARM64: Done test exception
340 09:25:55.425043 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 09:25:55.435539 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 09:25:55.442126 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 09:25:55.452342 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 09:25:55.458965 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 09:25:55.469311 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 09:25:55.479469 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 09:25:55.485857 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 09:25:55.504424 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 09:25:55.507461 WDT: Last reset was cold boot
350 09:25:55.511014 SPI1(PAD0) initialized at 2873684 Hz
351 09:25:55.514375 SPI5(PAD0) initialized at 992727 Hz
352 09:25:55.517707 VBOOT: Loading verstage.
353 09:25:55.524629 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 09:25:55.527598 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 09:25:55.531123 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 09:25:55.534720 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 09:25:55.542008 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 09:25:55.548455 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 09:25:55.559520 read SPI 0x96554 0xa1eb: 4596 us, 9018 KB/s, 72.144 Mbps
360 09:25:55.559656
361 09:25:55.559721
362 09:25:55.569679 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 09:25:55.573196 ARM64: Exception handlers installed.
364 09:25:55.576119 ARM64: Testing exception
365 09:25:55.576224 ARM64: Done test exception
366 09:25:55.583089 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 09:25:55.586645 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 09:25:55.600098 Probing TPM: . done!
369 09:25:55.600238 TPM ready after 0 ms
370 09:25:55.607169 Connected to device vid:did:rid of 1ae0:0028:00
371 09:25:55.614038 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 09:25:55.654989 Initialized TPM device CR50 revision 0
373 09:25:55.667049 tlcl_send_startup: Startup return code is 0
374 09:25:55.667188 TPM: setup succeeded
375 09:25:55.678850 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 09:25:55.687205 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 09:25:55.697286 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 09:25:55.706175 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 09:25:55.709732 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 09:25:55.712745 in-header: 03 07 00 00 08 00 00 00
381 09:25:55.716324 in-data: aa e4 47 04 13 02 00 00
382 09:25:55.719352 Chrome EC: UHEPI supported
383 09:25:55.726428 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 09:25:55.730015 in-header: 03 c9 00 00 08 00 00 00
385 09:25:55.732897 in-data: 04 00 20 08 00 00 00 00
386 09:25:55.733059 Phase 1
387 09:25:55.739695 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 09:25:55.746732 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 09:25:55.749799 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 09:25:55.752879 Recovery requested (1009000e)
391 09:25:55.756537 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 09:25:55.765813 tlcl_extend: response is 0
393 09:25:55.774070 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 09:25:55.779306 tlcl_extend: response is 0
395 09:25:55.786373 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 09:25:55.806838 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
397 09:25:55.813379 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 09:25:55.813560
399 09:25:55.813672
400 09:25:55.823860 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 09:25:55.826785 ARM64: Exception handlers installed.
402 09:25:55.830330 ARM64: Testing exception
403 09:25:55.830514 ARM64: Done test exception
404 09:25:55.852083 pmic_efuse_setting: Set efuses in 11 msecs
405 09:25:55.855692 pmwrap_interface_init: Select PMIF_VLD_RDY
406 09:25:55.862191 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 09:25:55.865885 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 09:25:55.872457 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 09:25:55.875945 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 09:25:55.879285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 09:25:55.886137 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 09:25:55.888972 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 09:25:55.895989 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 09:25:55.899440 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 09:25:55.905884 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 09:25:55.909254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 09:25:55.912812 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 09:25:55.919380 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 09:25:55.925939 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 09:25:55.929549 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 09:25:55.935962 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 09:25:55.942461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 09:25:55.946092 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 09:25:55.953067 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 09:25:55.959520 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 09:25:55.962943 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 09:25:55.969858 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 09:25:55.976334 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 09:25:55.979757 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 09:25:55.986252 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 09:25:55.992908 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 09:25:55.996488 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 09:25:55.999900 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 09:25:56.006621 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 09:25:56.009814 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 09:25:56.016864 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 09:25:56.019857 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 09:25:56.027077 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 09:25:56.030247 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 09:25:56.037056 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 09:25:56.040078 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 09:25:56.047241 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 09:25:56.050141 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 09:25:56.057490 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 09:25:56.060985 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 09:25:56.063936 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 09:25:56.067312 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 09:25:56.074312 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 09:25:56.077707 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 09:25:56.081070 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 09:25:56.087654 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 09:25:56.091188 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 09:25:56.094701 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 09:25:56.097667 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 09:25:56.104653 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 09:25:56.108060 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 09:25:56.115026 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 09:25:56.124841 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 09:25:56.127924 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 09:25:56.135124 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 09:25:56.145073 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 09:25:56.148131 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 09:25:56.155289 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 09:25:56.158774 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 09:25:56.165479 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x12
466 09:25:56.172057 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 09:25:56.175341 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 09:25:56.178675 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 09:25:56.189714 [RTC]rtc_get_frequency_meter,154: input=15, output=790
470 09:25:56.199279 [RTC]rtc_get_frequency_meter,154: input=23, output=978
471 09:25:56.208778 [RTC]rtc_get_frequency_meter,154: input=19, output=885
472 09:25:56.218322 [RTC]rtc_get_frequency_meter,154: input=17, output=839
473 09:25:56.227683 [RTC]rtc_get_frequency_meter,154: input=16, output=814
474 09:25:56.237099 [RTC]rtc_get_frequency_meter,154: input=15, output=790
475 09:25:56.246579 [RTC]rtc_get_frequency_meter,154: input=16, output=814
476 09:25:56.249934 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 09:25:56.257279 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 09:25:56.260264 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 09:25:56.263972 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 09:25:56.270466 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 09:25:56.273928 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 09:25:56.277566 ADC[4]: Raw value=901328 ID=7
483 09:25:56.277726 ADC[3]: Raw value=213336 ID=1
484 09:25:56.280234 RAM Code: 0x71
485 09:25:56.283837 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 09:25:56.290974 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 09:25:56.297503 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 09:25:56.304106 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 09:25:56.307227 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 09:25:56.311063 in-header: 03 07 00 00 08 00 00 00
491 09:25:56.313934 in-data: aa e4 47 04 13 02 00 00
492 09:25:56.317470 Chrome EC: UHEPI supported
493 09:25:56.324024 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 09:25:56.327555 in-header: 03 c9 00 00 08 00 00 00
495 09:25:56.331150 in-data: 04 00 20 08 00 00 00 00
496 09:25:56.334048 MRC: failed to locate region type 0.
497 09:25:56.341119 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 09:25:56.344028 DRAM-K: Running full calibration
499 09:25:56.351070 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 09:25:56.351231 header.status = 0x0
501 09:25:56.354549 header.version = 0x6 (expected: 0x6)
502 09:25:56.357575 header.size = 0xd00 (expected: 0xd00)
503 09:25:56.361125 header.flags = 0x0
504 09:25:56.367773 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 09:25:56.384205 read SPI 0x72590 0x1c583: 12504 us, 9284 KB/s, 74.272 Mbps
506 09:25:56.390920 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 09:25:56.394473 dram_init: ddr_geometry: 2
508 09:25:56.394597 [EMI] MDL number = 2
509 09:25:56.398155 [EMI] Get MDL freq = 0
510 09:25:56.401144 dram_init: ddr_type: 0
511 09:25:56.401308 is_discrete_lpddr4: 1
512 09:25:56.404697 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 09:25:56.404831
514 09:25:56.404924
515 09:25:56.407618 [Bian_co] ETT version 0.0.0.1
516 09:25:56.414345 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 09:25:56.414482
518 09:25:56.417862 dramc_set_vcore_voltage set vcore to 650000
519 09:25:56.418000 Read voltage for 800, 4
520 09:25:56.421418 Vio18 = 0
521 09:25:56.421552 Vcore = 650000
522 09:25:56.421641 Vdram = 0
523 09:25:56.424343 Vddq = 0
524 09:25:56.424441 Vmddr = 0
525 09:25:56.428017 dram_init: config_dvfs: 1
526 09:25:56.431610 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 09:25:56.437923 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 09:25:56.441567 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 09:25:56.444522 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 09:25:56.448007 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 09:25:56.451512 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 09:25:56.454913 MEM_TYPE=3, freq_sel=18
533 09:25:56.458049 sv_algorithm_assistance_LP4_1600
534 09:25:56.461705 ============ PULL DRAM RESETB DOWN ============
535 09:25:56.464503 ========== PULL DRAM RESETB DOWN end =========
536 09:25:56.471268 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 09:25:56.474914 ===================================
538 09:25:56.475081 LPDDR4 DRAM CONFIGURATION
539 09:25:56.478297 ===================================
540 09:25:56.481697 EX_ROW_EN[0] = 0x0
541 09:25:56.485177 EX_ROW_EN[1] = 0x0
542 09:25:56.485328 LP4Y_EN = 0x0
543 09:25:56.488147 WORK_FSP = 0x0
544 09:25:56.488269 WL = 0x2
545 09:25:56.491608 RL = 0x2
546 09:25:56.491753 BL = 0x2
547 09:25:56.494985 RPST = 0x0
548 09:25:56.495119 RD_PRE = 0x0
549 09:25:56.498526 WR_PRE = 0x1
550 09:25:56.498667 WR_PST = 0x0
551 09:25:56.501491 DBI_WR = 0x0
552 09:25:56.501613 DBI_RD = 0x0
553 09:25:56.505035 OTF = 0x1
554 09:25:56.508610 ===================================
555 09:25:56.511566 ===================================
556 09:25:56.511679 ANA top config
557 09:25:56.515275 ===================================
558 09:25:56.518762 DLL_ASYNC_EN = 0
559 09:25:56.521721 ALL_SLAVE_EN = 1
560 09:25:56.521827 NEW_RANK_MODE = 1
561 09:25:56.525038 DLL_IDLE_MODE = 1
562 09:25:56.528667 LP45_APHY_COMB_EN = 1
563 09:25:56.532093 TX_ODT_DIS = 1
564 09:25:56.532216 NEW_8X_MODE = 1
565 09:25:56.535508 ===================================
566 09:25:56.538972 ===================================
567 09:25:56.541971 data_rate = 1600
568 09:25:56.545693 CKR = 1
569 09:25:56.549292 DQ_P2S_RATIO = 8
570 09:25:56.552082 ===================================
571 09:25:56.555692 CA_P2S_RATIO = 8
572 09:25:56.555837 DQ_CA_OPEN = 0
573 09:25:56.559177 DQ_SEMI_OPEN = 0
574 09:25:56.562497 CA_SEMI_OPEN = 0
575 09:25:56.565801 CA_FULL_RATE = 0
576 09:25:56.569228 DQ_CKDIV4_EN = 1
577 09:25:56.572160 CA_CKDIV4_EN = 1
578 09:25:56.572300 CA_PREDIV_EN = 0
579 09:25:56.575770 PH8_DLY = 0
580 09:25:56.579112 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 09:25:56.582581 DQ_AAMCK_DIV = 4
582 09:25:56.585497 CA_AAMCK_DIV = 4
583 09:25:56.585634 CA_ADMCK_DIV = 4
584 09:25:56.589145 DQ_TRACK_CA_EN = 0
585 09:25:56.592513 CA_PICK = 800
586 09:25:56.595931 CA_MCKIO = 800
587 09:25:56.599312 MCKIO_SEMI = 0
588 09:25:56.602803 PLL_FREQ = 3068
589 09:25:56.606118 DQ_UI_PI_RATIO = 32
590 09:25:56.606267 CA_UI_PI_RATIO = 0
591 09:25:56.609161 ===================================
592 09:25:56.612859 ===================================
593 09:25:56.615700 memory_type:LPDDR4
594 09:25:56.619222 GP_NUM : 10
595 09:25:56.619369 SRAM_EN : 1
596 09:25:56.622790 MD32_EN : 0
597 09:25:56.625721 ===================================
598 09:25:56.629475 [ANA_INIT] >>>>>>>>>>>>>>
599 09:25:56.632712 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 09:25:56.636116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 09:25:56.639229 ===================================
602 09:25:56.639392 data_rate = 1600,PCW = 0X7600
603 09:25:56.642585 ===================================
604 09:25:56.645900 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 09:25:56.652999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 09:25:56.659672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 09:25:56.662687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 09:25:56.666202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 09:25:56.669646 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 09:25:56.672735 [ANA_INIT] flow start
611 09:25:56.672883 [ANA_INIT] PLL >>>>>>>>
612 09:25:56.676219 [ANA_INIT] PLL <<<<<<<<
613 09:25:56.679875 [ANA_INIT] MIDPI >>>>>>>>
614 09:25:56.680027 [ANA_INIT] MIDPI <<<<<<<<
615 09:25:56.682935 [ANA_INIT] DLL >>>>>>>>
616 09:25:56.686475 [ANA_INIT] flow end
617 09:25:56.689997 ============ LP4 DIFF to SE enter ============
618 09:25:56.692826 ============ LP4 DIFF to SE exit ============
619 09:25:56.696205 [ANA_INIT] <<<<<<<<<<<<<
620 09:25:56.699773 [Flow] Enable top DCM control >>>>>
621 09:25:56.703169 [Flow] Enable top DCM control <<<<<
622 09:25:56.706447 Enable DLL master slave shuffle
623 09:25:56.709705 ==============================================================
624 09:25:56.713409 Gating Mode config
625 09:25:56.719892 ==============================================================
626 09:25:56.720068 Config description:
627 09:25:56.730112 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 09:25:56.736661 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 09:25:56.740250 SELPH_MODE 0: By rank 1: By Phase
630 09:25:56.746947 ==============================================================
631 09:25:56.750101 GAT_TRACK_EN = 1
632 09:25:56.753616 RX_GATING_MODE = 2
633 09:25:56.756952 RX_GATING_TRACK_MODE = 2
634 09:25:56.760466 SELPH_MODE = 1
635 09:25:56.760612 PICG_EARLY_EN = 1
636 09:25:56.763618 VALID_LAT_VALUE = 1
637 09:25:56.770208 ==============================================================
638 09:25:56.773885 Enter into Gating configuration >>>>
639 09:25:56.777117 Exit from Gating configuration <<<<
640 09:25:56.780261 Enter into DVFS_PRE_config >>>>>
641 09:25:56.790207 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 09:25:56.793483 Exit from DVFS_PRE_config <<<<<
643 09:25:56.796992 Enter into PICG configuration >>>>
644 09:25:56.800568 Exit from PICG configuration <<<<
645 09:25:56.803606 [RX_INPUT] configuration >>>>>
646 09:25:56.807170 [RX_INPUT] configuration <<<<<
647 09:25:56.810306 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 09:25:56.817193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 09:25:56.823621 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 09:25:56.830014 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 09:25:56.833908 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 09:25:56.840539 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 09:25:56.843440 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 09:25:56.850691 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 09:25:56.854129 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 09:25:56.857011 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 09:25:56.860702 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 09:25:56.867222 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 09:25:56.870233 ===================================
660 09:25:56.870383 LPDDR4 DRAM CONFIGURATION
661 09:25:56.873687 ===================================
662 09:25:56.877314 EX_ROW_EN[0] = 0x0
663 09:25:56.880245 EX_ROW_EN[1] = 0x0
664 09:25:56.880393 LP4Y_EN = 0x0
665 09:25:56.883756 WORK_FSP = 0x0
666 09:25:56.883890 WL = 0x2
667 09:25:56.887025 RL = 0x2
668 09:25:56.887155 BL = 0x2
669 09:25:56.890365 RPST = 0x0
670 09:25:56.890506 RD_PRE = 0x0
671 09:25:56.893494 WR_PRE = 0x1
672 09:25:56.893630 WR_PST = 0x0
673 09:25:56.896877 DBI_WR = 0x0
674 09:25:56.897006 DBI_RD = 0x0
675 09:25:56.900358 OTF = 0x1
676 09:25:56.904046 ===================================
677 09:25:56.906947 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 09:25:56.910532 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 09:25:56.917062 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 09:25:56.920557 ===================================
681 09:25:56.920702 LPDDR4 DRAM CONFIGURATION
682 09:25:56.923686 ===================================
683 09:25:56.927142 EX_ROW_EN[0] = 0x10
684 09:25:56.930147 EX_ROW_EN[1] = 0x0
685 09:25:56.930256 LP4Y_EN = 0x0
686 09:25:56.933594 WORK_FSP = 0x0
687 09:25:56.933720 WL = 0x2
688 09:25:56.936868 RL = 0x2
689 09:25:56.936993 BL = 0x2
690 09:25:56.940053 RPST = 0x0
691 09:25:56.940185 RD_PRE = 0x0
692 09:25:56.943524 WR_PRE = 0x1
693 09:25:56.943661 WR_PST = 0x0
694 09:25:56.946890 DBI_WR = 0x0
695 09:25:56.947025 DBI_RD = 0x0
696 09:25:56.950524 OTF = 0x1
697 09:25:56.953481 ===================================
698 09:25:56.960339 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 09:25:56.963878 nWR fixed to 40
700 09:25:56.964015 [ModeRegInit_LP4] CH0 RK0
701 09:25:56.967170 [ModeRegInit_LP4] CH0 RK1
702 09:25:56.970580 [ModeRegInit_LP4] CH1 RK0
703 09:25:56.970734 [ModeRegInit_LP4] CH1 RK1
704 09:25:56.973954 match AC timing 13
705 09:25:56.976797 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 09:25:56.980302 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 09:25:56.986913 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 09:25:56.990497 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 09:25:56.997067 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 09:25:56.997236 [EMI DOE] emi_dcm 0
711 09:25:57.000473 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 09:25:57.003935 ==
713 09:25:57.004088 Dram Type= 6, Freq= 0, CH_0, rank 0
714 09:25:57.010516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 09:25:57.010684 ==
716 09:25:57.013572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 09:25:57.020105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 09:25:57.030218 [CA 0] Center 37 (6~68) winsize 63
719 09:25:57.033673 [CA 1] Center 37 (6~68) winsize 63
720 09:25:57.036678 [CA 2] Center 35 (5~66) winsize 62
721 09:25:57.040297 [CA 3] Center 34 (4~65) winsize 62
722 09:25:57.043251 [CA 4] Center 34 (3~65) winsize 63
723 09:25:57.046678 [CA 5] Center 33 (3~64) winsize 62
724 09:25:57.046833
725 09:25:57.050214 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 09:25:57.050352
727 09:25:57.053277 [CATrainingPosCal] consider 1 rank data
728 09:25:57.056872 u2DelayCellTimex100 = 270/100 ps
729 09:25:57.060094 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
730 09:25:57.063581 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 09:25:57.067704 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 09:25:57.071186 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 09:25:57.073964 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
734 09:25:57.080877 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 09:25:57.081048
736 09:25:57.084252 CA PerBit enable=1, Macro0, CA PI delay=33
737 09:25:57.084407
738 09:25:57.087833 [CBTSetCACLKResult] CA Dly = 33
739 09:25:57.087978 CS Dly: 5 (0~36)
740 09:25:57.088069 ==
741 09:25:57.091034 Dram Type= 6, Freq= 0, CH_0, rank 1
742 09:25:57.094688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 09:25:57.097637 ==
744 09:25:57.101079 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 09:25:57.107850 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 09:25:57.116484 [CA 0] Center 37 (6~68) winsize 63
747 09:25:57.119402 [CA 1] Center 37 (6~68) winsize 63
748 09:25:57.123059 [CA 2] Center 35 (4~66) winsize 63
749 09:25:57.126509 [CA 3] Center 35 (4~66) winsize 63
750 09:25:57.129428 [CA 4] Center 33 (3~64) winsize 62
751 09:25:57.132882 [CA 5] Center 33 (3~64) winsize 62
752 09:25:57.133031
753 09:25:57.136187 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 09:25:57.136316
755 09:25:57.139571 [CATrainingPosCal] consider 2 rank data
756 09:25:57.142989 u2DelayCellTimex100 = 270/100 ps
757 09:25:57.146535 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
758 09:25:57.149653 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
759 09:25:57.156614 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 09:25:57.160148 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 09:25:57.162946 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 09:25:57.166298 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 09:25:57.166419
764 09:25:57.169969 CA PerBit enable=1, Macro0, CA PI delay=33
765 09:25:57.170111
766 09:25:57.173267 [CBTSetCACLKResult] CA Dly = 33
767 09:25:57.173392 CS Dly: 6 (0~38)
768 09:25:57.173485
769 09:25:57.176468 ----->DramcWriteLeveling(PI) begin...
770 09:25:57.176597 ==
771 09:25:57.180313 Dram Type= 6, Freq= 0, CH_0, rank 0
772 09:25:57.186844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 09:25:57.186995 ==
774 09:25:57.189901 Write leveling (Byte 0): 28 => 28
775 09:25:57.193299 Write leveling (Byte 1): 28 => 28
776 09:25:57.193446 DramcWriteLeveling(PI) end<-----
777 09:25:57.193539
778 09:25:57.197078 ==
779 09:25:57.199994 Dram Type= 6, Freq= 0, CH_0, rank 0
780 09:25:57.203566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 09:25:57.203718 ==
782 09:25:57.207085 [Gating] SW mode calibration
783 09:25:57.213678 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 09:25:57.216713 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 09:25:57.223471 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 09:25:57.226555 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 09:25:57.230093 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 09:25:57.236584 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 09:25:57.240174 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 09:25:57.243540 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 09:25:57.250251 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 09:25:57.253825 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 09:25:57.256889 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 09:25:57.260441 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 09:25:57.266908 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 09:25:57.270477 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 09:25:57.273591 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 09:25:57.279950 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 09:25:57.283515 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 09:25:57.286822 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 09:25:57.293896 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 09:25:57.296944 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 09:25:57.300009 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 09:25:57.306925 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 09:25:57.310123 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 09:25:57.313554 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 09:25:57.320198 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 09:25:57.323568 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 09:25:57.326538 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 09:25:57.333286 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 09:25:57.336757 0 9 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
812 09:25:57.340448 0 9 12 | B1->B0 | 2a2a 3030 | 0 1 | (0 0) (1 1)
813 09:25:57.346919 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 09:25:57.350217 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 09:25:57.353330 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 09:25:57.356698 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 09:25:57.363309 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 09:25:57.366886 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 09:25:57.370490 0 10 8 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 0)
820 09:25:57.376926 0 10 12 | B1->B0 | 2d2d 2626 | 1 1 | (1 0) (1 0)
821 09:25:57.380391 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 09:25:57.383298 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 09:25:57.389967 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 09:25:57.393598 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 09:25:57.396645 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 09:25:57.403739 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 09:25:57.406650 0 11 8 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
828 09:25:57.409847 0 11 12 | B1->B0 | 3737 4545 | 0 0 | (1 1) (0 0)
829 09:25:57.416782 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 09:25:57.420067 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 09:25:57.423365 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 09:25:57.429891 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 09:25:57.433426 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 09:25:57.436544 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 09:25:57.443290 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 09:25:57.446901 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 09:25:57.450455 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 09:25:57.456865 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 09:25:57.460059 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 09:25:57.463250 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 09:25:57.466779 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 09:25:57.473209 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 09:25:57.476826 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:25:57.480452 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 09:25:57.486974 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 09:25:57.490074 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 09:25:57.493573 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 09:25:57.500119 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 09:25:57.503020 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 09:25:57.506519 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 09:25:57.513515 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 09:25:57.516876 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 09:25:57.519915 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 09:25:57.523472 Total UI for P1: 0, mck2ui 16
855 09:25:57.526453 best dqsien dly found for B0: ( 0, 14, 10)
856 09:25:57.530261 Total UI for P1: 0, mck2ui 16
857 09:25:57.533331 best dqsien dly found for B1: ( 0, 14, 12)
858 09:25:57.537015 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
859 09:25:57.540250 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
860 09:25:57.540376
861 09:25:57.546670 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 09:25:57.550020 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
863 09:25:57.550149 [Gating] SW calibration Done
864 09:25:57.553438 ==
865 09:25:57.553580 Dram Type= 6, Freq= 0, CH_0, rank 0
866 09:25:57.560292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 09:25:57.560452 ==
868 09:25:57.560543 RX Vref Scan: 0
869 09:25:57.560646
870 09:25:57.563252 RX Vref 0 -> 0, step: 1
871 09:25:57.563362
872 09:25:57.566696 RX Delay -130 -> 252, step: 16
873 09:25:57.570276 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 09:25:57.573764 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 09:25:57.576673 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
876 09:25:57.583768 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
877 09:25:57.586863 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 09:25:57.590433 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 09:25:57.593497 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 09:25:57.597117 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 09:25:57.603428 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
882 09:25:57.606986 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 09:25:57.610496 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 09:25:57.613497 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 09:25:57.616988 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
886 09:25:57.623956 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
887 09:25:57.626933 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 09:25:57.630640 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 09:25:57.630763 ==
890 09:25:57.634079 Dram Type= 6, Freq= 0, CH_0, rank 0
891 09:25:57.637108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 09:25:57.637247 ==
893 09:25:57.640536 DQS Delay:
894 09:25:57.640684 DQS0 = 0, DQS1 = 0
895 09:25:57.643838 DQM Delay:
896 09:25:57.643947 DQM0 = 84, DQM1 = 74
897 09:25:57.644012 DQ Delay:
898 09:25:57.647426 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
899 09:25:57.650385 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
900 09:25:57.653798 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
901 09:25:57.656950 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
902 09:25:57.657069
903 09:25:57.657133
904 09:25:57.657190 ==
905 09:25:57.660689 Dram Type= 6, Freq= 0, CH_0, rank 0
906 09:25:57.667294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 09:25:57.667452 ==
908 09:25:57.667553
909 09:25:57.667638
910 09:25:57.667720 TX Vref Scan disable
911 09:25:57.670795 == TX Byte 0 ==
912 09:25:57.674134 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
913 09:25:57.677745 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
914 09:25:57.681169 == TX Byte 1 ==
915 09:25:57.684573 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 09:25:57.691071 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 09:25:57.691232 ==
918 09:25:57.694095 Dram Type= 6, Freq= 0, CH_0, rank 0
919 09:25:57.697740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 09:25:57.697875 ==
921 09:25:57.710216 TX Vref=22, minBit 0, minWin=27, winSum=441
922 09:25:57.713798 TX Vref=24, minBit 0, minWin=27, winSum=443
923 09:25:57.716795 TX Vref=26, minBit 3, minWin=27, winSum=449
924 09:25:57.720416 TX Vref=28, minBit 12, minWin=27, winSum=452
925 09:25:57.723555 TX Vref=30, minBit 2, minWin=28, winSum=455
926 09:25:57.727026 TX Vref=32, minBit 2, minWin=28, winSum=453
927 09:25:57.733508 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 30
928 09:25:57.733669
929 09:25:57.736975 Final TX Range 1 Vref 30
930 09:25:57.737125
931 09:25:57.737218 ==
932 09:25:57.740580 Dram Type= 6, Freq= 0, CH_0, rank 0
933 09:25:57.743509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 09:25:57.743661 ==
935 09:25:57.743757
936 09:25:57.743841
937 09:25:57.746943 TX Vref Scan disable
938 09:25:57.750362 == TX Byte 0 ==
939 09:25:57.753763 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 09:25:57.757265 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 09:25:57.760228 == TX Byte 1 ==
942 09:25:57.763777 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 09:25:57.767099 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 09:25:57.767253
945 09:25:57.770610 [DATLAT]
946 09:25:57.770774 Freq=800, CH0 RK0
947 09:25:57.770872
948 09:25:57.773583 DATLAT Default: 0xa
949 09:25:57.773725 0, 0xFFFF, sum = 0
950 09:25:57.777084 1, 0xFFFF, sum = 0
951 09:25:57.777238 2, 0xFFFF, sum = 0
952 09:25:57.780269 3, 0xFFFF, sum = 0
953 09:25:57.780450 4, 0xFFFF, sum = 0
954 09:25:57.783783 5, 0xFFFF, sum = 0
955 09:25:57.783939 6, 0xFFFF, sum = 0
956 09:25:57.786988 7, 0xFFFF, sum = 0
957 09:25:57.787141 8, 0xFFFF, sum = 0
958 09:25:57.790661 9, 0x0, sum = 1
959 09:25:57.790795 10, 0x0, sum = 2
960 09:25:57.793666 11, 0x0, sum = 3
961 09:25:57.793836 12, 0x0, sum = 4
962 09:25:57.796990 best_step = 10
963 09:25:57.797163
964 09:25:57.797257 ==
965 09:25:57.800486 Dram Type= 6, Freq= 0, CH_0, rank 0
966 09:25:57.804201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 09:25:57.804342 ==
968 09:25:57.807224 RX Vref Scan: 1
969 09:25:57.807352
970 09:25:57.807419 Set Vref Range= 32 -> 127
971 09:25:57.807505
972 09:25:57.810810 RX Vref 32 -> 127, step: 1
973 09:25:57.810944
974 09:25:57.813715 RX Delay -95 -> 252, step: 8
975 09:25:57.813866
976 09:25:57.817066 Set Vref, RX VrefLevel [Byte0]: 32
977 09:25:57.820559 [Byte1]: 32
978 09:25:57.820738
979 09:25:57.824228 Set Vref, RX VrefLevel [Byte0]: 33
980 09:25:57.827421 [Byte1]: 33
981 09:25:57.827578
982 09:25:57.830842 Set Vref, RX VrefLevel [Byte0]: 34
983 09:25:57.834150 [Byte1]: 34
984 09:25:57.837683
985 09:25:57.837849 Set Vref, RX VrefLevel [Byte0]: 35
986 09:25:57.841298 [Byte1]: 35
987 09:25:57.845552
988 09:25:57.845715 Set Vref, RX VrefLevel [Byte0]: 36
989 09:25:57.849085 [Byte1]: 36
990 09:25:57.853277
991 09:25:57.853417 Set Vref, RX VrefLevel [Byte0]: 37
992 09:25:57.856745 [Byte1]: 37
993 09:25:57.860825
994 09:25:57.860986 Set Vref, RX VrefLevel [Byte0]: 38
995 09:25:57.864304 [Byte1]: 38
996 09:25:57.868457
997 09:25:57.868614 Set Vref, RX VrefLevel [Byte0]: 39
998 09:25:57.871773 [Byte1]: 39
999 09:25:57.875794
1000 09:25:57.875953 Set Vref, RX VrefLevel [Byte0]: 40
1001 09:25:57.879326 [Byte1]: 40
1002 09:25:57.883508
1003 09:25:57.883663 Set Vref, RX VrefLevel [Byte0]: 41
1004 09:25:57.886882 [Byte1]: 41
1005 09:25:57.891248
1006 09:25:57.891409 Set Vref, RX VrefLevel [Byte0]: 42
1007 09:25:57.894186 [Byte1]: 42
1008 09:25:57.898850
1009 09:25:57.899007 Set Vref, RX VrefLevel [Byte0]: 43
1010 09:25:57.902074 [Byte1]: 43
1011 09:25:57.906065
1012 09:25:57.906203 Set Vref, RX VrefLevel [Byte0]: 44
1013 09:25:57.909727 [Byte1]: 44
1014 09:25:57.914024
1015 09:25:57.914153 Set Vref, RX VrefLevel [Byte0]: 45
1016 09:25:57.916906 [Byte1]: 45
1017 09:25:57.921564
1018 09:25:57.921718 Set Vref, RX VrefLevel [Byte0]: 46
1019 09:25:57.924612 [Byte1]: 46
1020 09:25:57.929235
1021 09:25:57.929387 Set Vref, RX VrefLevel [Byte0]: 47
1022 09:25:57.932198 [Byte1]: 47
1023 09:25:57.936501
1024 09:25:57.936652 Set Vref, RX VrefLevel [Byte0]: 48
1025 09:25:57.943189 [Byte1]: 48
1026 09:25:57.943348
1027 09:25:57.946725 Set Vref, RX VrefLevel [Byte0]: 49
1028 09:25:57.949737 [Byte1]: 49
1029 09:25:57.949863
1030 09:25:57.953130 Set Vref, RX VrefLevel [Byte0]: 50
1031 09:25:57.956709 [Byte1]: 50
1032 09:25:57.956844
1033 09:25:57.959748 Set Vref, RX VrefLevel [Byte0]: 51
1034 09:25:57.963375 [Byte1]: 51
1035 09:25:57.967268
1036 09:25:57.967408 Set Vref, RX VrefLevel [Byte0]: 52
1037 09:25:57.970399 [Byte1]: 52
1038 09:25:57.974568
1039 09:25:57.974716 Set Vref, RX VrefLevel [Byte0]: 53
1040 09:25:57.978152 [Byte1]: 53
1041 09:25:57.981917
1042 09:25:57.982077 Set Vref, RX VrefLevel [Byte0]: 54
1043 09:25:57.985719 [Byte1]: 54
1044 09:25:57.990078
1045 09:25:57.990200 Set Vref, RX VrefLevel [Byte0]: 55
1046 09:25:57.993362 [Byte1]: 55
1047 09:25:57.997225
1048 09:25:57.997390 Set Vref, RX VrefLevel [Byte0]: 56
1049 09:25:58.000725 [Byte1]: 56
1050 09:25:58.004937
1051 09:25:58.005081 Set Vref, RX VrefLevel [Byte0]: 57
1052 09:25:58.008574 [Byte1]: 57
1053 09:25:58.012526
1054 09:25:58.012684 Set Vref, RX VrefLevel [Byte0]: 58
1055 09:25:58.016024 [Byte1]: 58
1056 09:25:58.020311
1057 09:25:58.020495 Set Vref, RX VrefLevel [Byte0]: 59
1058 09:25:58.023337 [Byte1]: 59
1059 09:25:58.027958
1060 09:25:58.028125 Set Vref, RX VrefLevel [Byte0]: 60
1061 09:25:58.030992 [Byte1]: 60
1062 09:25:58.035669
1063 09:25:58.035831 Set Vref, RX VrefLevel [Byte0]: 61
1064 09:25:58.038566 [Byte1]: 61
1065 09:25:58.042979
1066 09:25:58.043136 Set Vref, RX VrefLevel [Byte0]: 62
1067 09:25:58.046165 [Byte1]: 62
1068 09:25:58.051044
1069 09:25:58.051196 Set Vref, RX VrefLevel [Byte0]: 63
1070 09:25:58.053798 [Byte1]: 63
1071 09:25:58.057974
1072 09:25:58.058123 Set Vref, RX VrefLevel [Byte0]: 64
1073 09:25:58.061561 [Byte1]: 64
1074 09:25:58.065850
1075 09:25:58.065988 Set Vref, RX VrefLevel [Byte0]: 65
1076 09:25:58.069307 [Byte1]: 65
1077 09:25:58.073493
1078 09:25:58.073613 Set Vref, RX VrefLevel [Byte0]: 66
1079 09:25:58.076750 [Byte1]: 66
1080 09:25:58.081186
1081 09:25:58.081305 Set Vref, RX VrefLevel [Byte0]: 67
1082 09:25:58.084229 [Byte1]: 67
1083 09:25:58.088743
1084 09:25:58.088864 Set Vref, RX VrefLevel [Byte0]: 68
1085 09:25:58.092085 [Byte1]: 68
1086 09:25:58.096251
1087 09:25:58.096380 Set Vref, RX VrefLevel [Byte0]: 69
1088 09:25:58.099652 [Byte1]: 69
1089 09:25:58.103763
1090 09:25:58.103872 Set Vref, RX VrefLevel [Byte0]: 70
1091 09:25:58.107279 [Byte1]: 70
1092 09:25:58.111516
1093 09:25:58.111670 Set Vref, RX VrefLevel [Byte0]: 71
1094 09:25:58.114456 [Byte1]: 71
1095 09:25:58.118982
1096 09:25:58.119115 Set Vref, RX VrefLevel [Byte0]: 72
1097 09:25:58.122051 [Byte1]: 72
1098 09:25:58.126767
1099 09:25:58.126884 Set Vref, RX VrefLevel [Byte0]: 73
1100 09:25:58.129546 [Byte1]: 73
1101 09:25:58.133855
1102 09:25:58.134040 Set Vref, RX VrefLevel [Byte0]: 74
1103 09:25:58.137409 [Byte1]: 74
1104 09:25:58.141512
1105 09:25:58.141675 Final RX Vref Byte 0 = 61 to rank0
1106 09:25:58.144990 Final RX Vref Byte 1 = 56 to rank0
1107 09:25:58.148572 Final RX Vref Byte 0 = 61 to rank1
1108 09:25:58.151961 Final RX Vref Byte 1 = 56 to rank1==
1109 09:25:58.155224 Dram Type= 6, Freq= 0, CH_0, rank 0
1110 09:25:58.161738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1111 09:25:58.161901 ==
1112 09:25:58.162030 DQS Delay:
1113 09:25:58.162142 DQS0 = 0, DQS1 = 0
1114 09:25:58.165320 DQM Delay:
1115 09:25:58.165461 DQM0 = 87, DQM1 = 78
1116 09:25:58.168470 DQ Delay:
1117 09:25:58.171952 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1118 09:25:58.172084 DQ4 =92, DQ5 =76, DQ6 =92, DQ7 =92
1119 09:25:58.174949 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1120 09:25:58.178459 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1121 09:25:58.182023
1122 09:25:58.182203
1123 09:25:58.188584 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1124 09:25:58.192133 CH0 RK0: MR19=606, MR18=2C13
1125 09:25:58.198806 CH0_RK0: MR19=0x606, MR18=0x2C13, DQSOSC=398, MR23=63, INC=93, DEC=62
1126 09:25:58.198959
1127 09:25:58.201645 ----->DramcWriteLeveling(PI) begin...
1128 09:25:58.201782 ==
1129 09:25:58.205359 Dram Type= 6, Freq= 0, CH_0, rank 1
1130 09:25:58.208563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1131 09:25:58.208703 ==
1132 09:25:58.211801 Write leveling (Byte 0): 29 => 29
1133 09:25:58.215299 Write leveling (Byte 1): 29 => 29
1134 09:25:58.218739 DramcWriteLeveling(PI) end<-----
1135 09:25:58.218881
1136 09:25:58.218981 ==
1137 09:25:58.221601 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 09:25:58.225241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 09:25:58.225437 ==
1140 09:25:58.228269 [Gating] SW mode calibration
1141 09:25:58.235484 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1142 09:25:58.241945 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1143 09:25:58.245404 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1144 09:25:58.248541 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1145 09:25:58.255539 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1146 09:25:58.258315 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 09:25:58.261706 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 09:25:58.265220 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 09:25:58.272220 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 09:25:58.275122 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 09:25:58.278808 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 09:25:58.326208 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 09:25:58.326350 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 09:25:58.326606 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 09:25:58.326682 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 09:25:58.326769 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 09:25:58.326878 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 09:25:58.326971 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 09:25:58.327055 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1160 09:25:58.327163 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1161 09:25:58.327258 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1162 09:25:58.330545 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 09:25:58.333621 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 09:25:58.337131 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 09:25:58.340599 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 09:25:58.347304 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 09:25:58.350319 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 09:25:58.353809 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 09:25:58.360470 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
1170 09:25:58.363517 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1171 09:25:58.367318 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 09:25:58.373891 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 09:25:58.377520 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 09:25:58.380458 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 09:25:58.387143 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 09:25:58.390782 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
1177 09:25:58.393768 0 10 8 | B1->B0 | 3333 2a2a | 1 0 | (0 1) (0 0)
1178 09:25:58.400555 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1179 09:25:58.403764 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 09:25:58.407110 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 09:25:58.410488 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 09:25:58.417265 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 09:25:58.420381 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 09:25:58.423593 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1185 09:25:58.430241 0 11 8 | B1->B0 | 2a2a 4141 | 0 0 | (0 0) (0 0)
1186 09:25:58.433581 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 09:25:58.437201 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 09:25:58.443607 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 09:25:58.447196 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 09:25:58.450575 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 09:25:58.457255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 09:25:58.460226 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1193 09:25:58.463677 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1194 09:25:58.470847 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 09:25:58.473449 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 09:25:58.477051 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 09:25:58.484124 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 09:25:58.486910 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 09:25:58.490401 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 09:25:58.494099 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 09:25:58.500539 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 09:25:58.504128 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 09:25:58.507613 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 09:25:58.513938 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 09:25:58.517477 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 09:25:58.520827 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 09:25:58.527126 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 09:25:58.530720 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1209 09:25:58.534158 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1210 09:25:58.537358 Total UI for P1: 0, mck2ui 16
1211 09:25:58.540808 best dqsien dly found for B0: ( 0, 14, 4)
1212 09:25:58.547662 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 09:25:58.547832 Total UI for P1: 0, mck2ui 16
1214 09:25:58.550550 best dqsien dly found for B1: ( 0, 14, 8)
1215 09:25:58.557725 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1216 09:25:58.560660 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1217 09:25:58.560795
1218 09:25:58.564209 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1219 09:25:58.567221 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1220 09:25:58.570862 [Gating] SW calibration Done
1221 09:25:58.571010 ==
1222 09:25:58.574435 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 09:25:58.577400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1224 09:25:58.577529 ==
1225 09:25:58.580895 RX Vref Scan: 0
1226 09:25:58.581027
1227 09:25:58.581117 RX Vref 0 -> 0, step: 1
1228 09:25:58.581203
1229 09:25:58.583877 RX Delay -130 -> 252, step: 16
1230 09:25:58.587720 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1231 09:25:58.590707 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1232 09:25:58.597186 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1233 09:25:58.600471 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1234 09:25:58.604131 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1235 09:25:58.607643 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1236 09:25:58.610549 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1237 09:25:58.617568 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1238 09:25:58.620548 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1239 09:25:58.623873 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1240 09:25:58.627263 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1241 09:25:58.630777 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1242 09:25:58.637398 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1243 09:25:58.640989 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1244 09:25:58.643915 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1245 09:25:58.647103 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1246 09:25:58.647266 ==
1247 09:25:58.650681 Dram Type= 6, Freq= 0, CH_0, rank 1
1248 09:25:58.657147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1249 09:25:58.657283 ==
1250 09:25:58.657350 DQS Delay:
1251 09:25:58.660705 DQS0 = 0, DQS1 = 0
1252 09:25:58.660817 DQM Delay:
1253 09:25:58.660880 DQM0 = 86, DQM1 = 76
1254 09:25:58.664397 DQ Delay:
1255 09:25:58.667320 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1256 09:25:58.670420 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1257 09:25:58.673964 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1258 09:25:58.677625 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1259 09:25:58.677772
1260 09:25:58.677863
1261 09:25:58.677947 ==
1262 09:25:58.680644 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 09:25:58.684424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 09:25:58.684574 ==
1265 09:25:58.684670
1266 09:25:58.684768
1267 09:25:58.687357 TX Vref Scan disable
1268 09:25:58.687466 == TX Byte 0 ==
1269 09:25:58.693803 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1270 09:25:58.697281 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1271 09:25:58.697401 == TX Byte 1 ==
1272 09:25:58.703774 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1273 09:25:58.707056 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1274 09:25:58.707181 ==
1275 09:25:58.711171 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 09:25:58.713958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 09:25:58.714105 ==
1278 09:25:58.727831 TX Vref=22, minBit 0, minWin=27, winSum=444
1279 09:25:58.731624 TX Vref=24, minBit 3, minWin=27, winSum=444
1280 09:25:58.734665 TX Vref=26, minBit 3, minWin=27, winSum=447
1281 09:25:58.738038 TX Vref=28, minBit 3, minWin=27, winSum=453
1282 09:25:58.741197 TX Vref=30, minBit 3, minWin=27, winSum=454
1283 09:25:58.744961 TX Vref=32, minBit 0, minWin=28, winSum=454
1284 09:25:58.751351 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1285 09:25:58.751493
1286 09:25:58.754366 Final TX Range 1 Vref 32
1287 09:25:58.754487
1288 09:25:58.754575 ==
1289 09:25:58.757864 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 09:25:58.761087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 09:25:58.761202 ==
1292 09:25:58.764658
1293 09:25:58.764800
1294 09:25:58.764895 TX Vref Scan disable
1295 09:25:58.768141 == TX Byte 0 ==
1296 09:25:58.771546 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1297 09:25:58.774502 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1298 09:25:58.778115 == TX Byte 1 ==
1299 09:25:58.781206 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1300 09:25:58.784714 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1301 09:25:58.787717
1302 09:25:58.787838 [DATLAT]
1303 09:25:58.787902 Freq=800, CH0 RK1
1304 09:25:58.787959
1305 09:25:58.791359 DATLAT Default: 0xa
1306 09:25:58.791470 0, 0xFFFF, sum = 0
1307 09:25:58.794331 1, 0xFFFF, sum = 0
1308 09:25:58.794435 2, 0xFFFF, sum = 0
1309 09:25:58.797794 3, 0xFFFF, sum = 0
1310 09:25:58.797905 4, 0xFFFF, sum = 0
1311 09:25:58.801359 5, 0xFFFF, sum = 0
1312 09:25:58.804316 6, 0xFFFF, sum = 0
1313 09:25:58.804430 7, 0xFFFF, sum = 0
1314 09:25:58.807799 8, 0xFFFF, sum = 0
1315 09:25:58.807916 9, 0x0, sum = 1
1316 09:25:58.807979 10, 0x0, sum = 2
1317 09:25:58.811298 11, 0x0, sum = 3
1318 09:25:58.811402 12, 0x0, sum = 4
1319 09:25:58.814330 best_step = 10
1320 09:25:58.814437
1321 09:25:58.814501 ==
1322 09:25:58.817685 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 09:25:58.820903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 09:25:58.821038 ==
1325 09:25:58.824435 RX Vref Scan: 0
1326 09:25:58.824548
1327 09:25:58.824611 RX Vref 0 -> 0, step: 1
1328 09:25:58.824666
1329 09:25:58.827973 RX Delay -95 -> 252, step: 8
1330 09:25:58.834356 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1331 09:25:58.837816 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1332 09:25:58.841224 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1333 09:25:58.844712 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1334 09:25:58.847859 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1335 09:25:58.854979 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1336 09:25:58.858001 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1337 09:25:58.861586 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1338 09:25:58.864439 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1339 09:25:58.867789 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1340 09:25:58.874612 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1341 09:25:58.878247 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1342 09:25:58.881664 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1343 09:25:58.884610 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1344 09:25:58.888308 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1345 09:25:58.894915 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1346 09:25:58.895050 ==
1347 09:25:58.898376 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 09:25:58.901319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 09:25:58.901441 ==
1350 09:25:58.901510 DQS Delay:
1351 09:25:58.904645 DQS0 = 0, DQS1 = 0
1352 09:25:58.904750 DQM Delay:
1353 09:25:58.908211 DQM0 = 87, DQM1 = 77
1354 09:25:58.908327 DQ Delay:
1355 09:25:58.911281 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1356 09:25:58.914713 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1357 09:25:58.918253 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1358 09:25:58.921607 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1359 09:25:58.921726
1360 09:25:58.921791
1361 09:25:58.927953 [DQSOSCAuto] RK1, (LSB)MR18= 0x301a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1362 09:25:58.931390 CH0 RK1: MR19=606, MR18=301A
1363 09:25:58.938142 CH0_RK1: MR19=0x606, MR18=0x301A, DQSOSC=397, MR23=63, INC=93, DEC=62
1364 09:25:58.941197 [RxdqsGatingPostProcess] freq 800
1365 09:25:58.947935 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1366 09:25:58.951441 Pre-setting of DQS Precalculation
1367 09:25:58.954830 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1368 09:25:58.954943 ==
1369 09:25:58.958179 Dram Type= 6, Freq= 0, CH_1, rank 0
1370 09:25:58.961437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 09:25:58.961582 ==
1372 09:25:58.968140 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1373 09:25:58.974559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1374 09:25:58.982776 [CA 0] Center 36 (6~66) winsize 61
1375 09:25:58.985964 [CA 1] Center 36 (6~66) winsize 61
1376 09:25:58.989452 [CA 2] Center 34 (4~65) winsize 62
1377 09:25:58.992953 [CA 3] Center 34 (3~65) winsize 63
1378 09:25:58.995921 [CA 4] Center 34 (4~65) winsize 62
1379 09:25:58.999526 [CA 5] Center 34 (4~64) winsize 61
1380 09:25:58.999654
1381 09:25:59.003166 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1382 09:25:59.003288
1383 09:25:59.006146 [CATrainingPosCal] consider 1 rank data
1384 09:25:59.009491 u2DelayCellTimex100 = 270/100 ps
1385 09:25:59.013166 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1386 09:25:59.016273 CA1 delay=36 (6~66),Diff = 2 PI (14 cell)
1387 09:25:59.019731 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1388 09:25:59.026327 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1389 09:25:59.029651 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1390 09:25:59.032936 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1391 09:25:59.033055
1392 09:25:59.036493 CA PerBit enable=1, Macro0, CA PI delay=34
1393 09:25:59.036609
1394 09:25:59.039812 [CBTSetCACLKResult] CA Dly = 34
1395 09:25:59.039924 CS Dly: 4 (0~35)
1396 09:25:59.040009 ==
1397 09:25:59.042984 Dram Type= 6, Freq= 0, CH_1, rank 1
1398 09:25:59.049558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 09:25:59.049705 ==
1400 09:25:59.053130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1401 09:25:59.059523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1402 09:25:59.068802 [CA 0] Center 36 (6~66) winsize 61
1403 09:25:59.072067 [CA 1] Center 36 (6~66) winsize 61
1404 09:25:59.075244 [CA 2] Center 34 (4~65) winsize 62
1405 09:25:59.078657 [CA 3] Center 33 (3~64) winsize 62
1406 09:25:59.082072 [CA 4] Center 34 (3~65) winsize 63
1407 09:25:59.085600 [CA 5] Center 33 (3~64) winsize 62
1408 09:25:59.085720
1409 09:25:59.088532 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1410 09:25:59.088627
1411 09:25:59.092021 [CATrainingPosCal] consider 2 rank data
1412 09:25:59.095171 u2DelayCellTimex100 = 270/100 ps
1413 09:25:59.098625 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1414 09:25:59.102256 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1415 09:25:59.105760 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1416 09:25:59.112200 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1417 09:25:59.115743 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1418 09:25:59.118732 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
1419 09:25:59.118853
1420 09:25:59.122298 CA PerBit enable=1, Macro0, CA PI delay=33
1421 09:25:59.122413
1422 09:25:59.125817 [CBTSetCACLKResult] CA Dly = 33
1423 09:25:59.125951 CS Dly: 5 (0~37)
1424 09:25:59.126041
1425 09:25:59.128783 ----->DramcWriteLeveling(PI) begin...
1426 09:25:59.132626 ==
1427 09:25:59.132749 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 09:25:59.141703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 09:25:59.141867 ==
1430 09:25:59.142273 Write leveling (Byte 0): 27 => 27
1431 09:25:59.145619 Write leveling (Byte 1): 32 => 32
1432 09:25:59.145769 DramcWriteLeveling(PI) end<-----
1433 09:25:59.149243
1434 09:25:59.149383 ==
1435 09:25:59.152323 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 09:25:59.155226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 09:25:59.155342 ==
1438 09:25:59.158859 [Gating] SW mode calibration
1439 09:25:59.165127 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1440 09:25:59.168789 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1441 09:25:59.175288 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1442 09:25:59.178731 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1443 09:25:59.182550 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1444 09:25:59.188665 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 09:25:59.192364 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 09:25:59.195515 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 09:25:59.202335 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 09:25:59.205891 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 09:25:59.208802 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 09:25:59.215757 0 7 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1451 09:25:59.219214 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 09:25:59.222322 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1453 09:25:59.225856 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 09:25:59.232432 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1455 09:25:59.236072 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1456 09:25:59.239130 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1457 09:25:59.245657 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 09:25:59.249050 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1459 09:25:59.252340 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 09:25:59.258870 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1461 09:25:59.262229 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 09:25:59.265866 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 09:25:59.272442 0 8 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1464 09:25:59.275611 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 09:25:59.279235 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 09:25:59.285893 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 09:25:59.289178 0 9 8 | B1->B0 | 2323 2424 | 1 0 | (1 1) (0 0)
1468 09:25:59.292131 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1469 09:25:59.299163 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 09:25:59.302181 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 09:25:59.305497 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1472 09:25:59.308880 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 09:25:59.315612 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1474 09:25:59.319155 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1475 09:25:59.322572 0 10 8 | B1->B0 | 2e2e 2f2f | 0 1 | (0 1) (1 0)
1476 09:25:59.329204 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 09:25:59.332253 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 09:25:59.335966 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 09:25:59.342344 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 09:25:59.345997 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 09:25:59.349111 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1482 09:25:59.356094 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 09:25:59.359445 0 11 8 | B1->B0 | 3333 3232 | 1 0 | (0 0) (0 0)
1484 09:25:59.362769 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1485 09:25:59.369085 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 09:25:59.372631 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 09:25:59.376117 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 09:25:59.382697 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 09:25:59.386185 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 09:25:59.389717 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1491 09:25:59.392455 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1492 09:25:59.399448 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 09:25:59.403126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 09:25:59.406299 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 09:25:59.412597 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 09:25:59.415939 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 09:25:59.419522 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 09:25:59.426161 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 09:25:59.429573 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 09:25:59.432497 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 09:25:59.439044 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 09:25:59.442635 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 09:25:59.446115 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 09:25:59.452590 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 09:25:59.456100 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 09:25:59.459656 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 09:25:59.466100 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 09:25:59.466254 Total UI for P1: 0, mck2ui 16
1509 09:25:59.469226 best dqsien dly found for B0: ( 0, 14, 6)
1510 09:25:59.472539 Total UI for P1: 0, mck2ui 16
1511 09:25:59.476039 best dqsien dly found for B1: ( 0, 14, 6)
1512 09:25:59.479427 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1513 09:25:59.486242 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1514 09:25:59.486379
1515 09:25:59.489569 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1516 09:25:59.493195 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1517 09:25:59.496186 [Gating] SW calibration Done
1518 09:25:59.496299 ==
1519 09:25:59.499744 Dram Type= 6, Freq= 0, CH_1, rank 0
1520 09:25:59.503159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1521 09:25:59.503288 ==
1522 09:25:59.503353 RX Vref Scan: 0
1523 09:25:59.503410
1524 09:25:59.506167 RX Vref 0 -> 0, step: 1
1525 09:25:59.506278
1526 09:25:59.509687 RX Delay -130 -> 252, step: 16
1527 09:25:59.513116 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1528 09:25:59.516434 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1529 09:25:59.522952 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1530 09:25:59.526141 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1531 09:25:59.529869 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1532 09:25:59.532997 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1533 09:25:59.536430 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1534 09:25:59.539918 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1535 09:25:59.546538 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1536 09:25:59.549447 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1537 09:25:59.553241 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1538 09:25:59.556165 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1539 09:25:59.563150 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1540 09:25:59.566214 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1541 09:25:59.569699 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1542 09:25:59.573057 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1543 09:25:59.573182 ==
1544 09:25:59.576338 Dram Type= 6, Freq= 0, CH_1, rank 0
1545 09:25:59.579802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1546 09:25:59.583147 ==
1547 09:25:59.583293 DQS Delay:
1548 09:25:59.583390 DQS0 = 0, DQS1 = 0
1549 09:25:59.586088 DQM Delay:
1550 09:25:59.586181 DQM0 = 84, DQM1 = 77
1551 09:25:59.589415 DQ Delay:
1552 09:25:59.589541 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1553 09:25:59.592901 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =85
1554 09:25:59.596355 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1555 09:25:59.599933 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1556 09:25:59.600081
1557 09:25:59.602764
1558 09:25:59.602893 ==
1559 09:25:59.606299 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 09:25:59.609823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 09:25:59.609963 ==
1562 09:25:59.610048
1563 09:25:59.610107
1564 09:25:59.612788 TX Vref Scan disable
1565 09:25:59.612909 == TX Byte 0 ==
1566 09:25:59.619653 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1567 09:25:59.623060 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1568 09:25:59.623200 == TX Byte 1 ==
1569 09:25:59.629509 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1570 09:25:59.632885 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1571 09:25:59.633031 ==
1572 09:25:59.636060 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 09:25:59.639413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 09:25:59.639557 ==
1575 09:25:59.653467 TX Vref=22, minBit 11, minWin=26, winSum=438
1576 09:25:59.656518 TX Vref=24, minBit 8, minWin=27, winSum=445
1577 09:25:59.660143 TX Vref=26, minBit 8, minWin=27, winSum=448
1578 09:25:59.663612 TX Vref=28, minBit 8, minWin=27, winSum=447
1579 09:25:59.666692 TX Vref=30, minBit 11, minWin=27, winSum=452
1580 09:25:59.673844 TX Vref=32, minBit 1, minWin=28, winSum=455
1581 09:25:59.676869 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 32
1582 09:25:59.677005
1583 09:25:59.680303 Final TX Range 1 Vref 32
1584 09:25:59.680428
1585 09:25:59.680522 ==
1586 09:25:59.683719 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 09:25:59.687068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 09:25:59.687201 ==
1589 09:25:59.689757
1590 09:25:59.689876
1591 09:25:59.689966 TX Vref Scan disable
1592 09:25:59.693520 == TX Byte 0 ==
1593 09:25:59.696949 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1594 09:25:59.700248 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1595 09:25:59.703742 == TX Byte 1 ==
1596 09:25:59.707372 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1597 09:25:59.710188 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1598 09:25:59.713742
1599 09:25:59.713879 [DATLAT]
1600 09:25:59.713971 Freq=800, CH1 RK0
1601 09:25:59.714068
1602 09:25:59.717257 DATLAT Default: 0xa
1603 09:25:59.717371 0, 0xFFFF, sum = 0
1604 09:25:59.720265 1, 0xFFFF, sum = 0
1605 09:25:59.720385 2, 0xFFFF, sum = 0
1606 09:25:59.723842 3, 0xFFFF, sum = 0
1607 09:25:59.723968 4, 0xFFFF, sum = 0
1608 09:25:59.727058 5, 0xFFFF, sum = 0
1609 09:25:59.727193 6, 0xFFFF, sum = 0
1610 09:25:59.729957 7, 0xFFFF, sum = 0
1611 09:25:59.733552 8, 0xFFFF, sum = 0
1612 09:25:59.733685 9, 0x0, sum = 1
1613 09:25:59.733783 10, 0x0, sum = 2
1614 09:25:59.736960 11, 0x0, sum = 3
1615 09:25:59.737084 12, 0x0, sum = 4
1616 09:25:59.740574 best_step = 10
1617 09:25:59.740699
1618 09:25:59.740791 ==
1619 09:25:59.743271 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 09:25:59.747177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 09:25:59.747322 ==
1622 09:25:59.750215 RX Vref Scan: 1
1623 09:25:59.750335
1624 09:25:59.750425 Set Vref Range= 32 -> 127
1625 09:25:59.750512
1626 09:25:59.753726 RX Vref 32 -> 127, step: 1
1627 09:25:59.753853
1628 09:25:59.756848 RX Delay -111 -> 252, step: 8
1629 09:25:59.756994
1630 09:25:59.760473 Set Vref, RX VrefLevel [Byte0]: 32
1631 09:25:59.763356 [Byte1]: 32
1632 09:25:59.763487
1633 09:25:59.767054 Set Vref, RX VrefLevel [Byte0]: 33
1634 09:25:59.770067 [Byte1]: 33
1635 09:25:59.774103
1636 09:25:59.774244 Set Vref, RX VrefLevel [Byte0]: 34
1637 09:25:59.777170 [Byte1]: 34
1638 09:25:59.781467
1639 09:25:59.781621 Set Vref, RX VrefLevel [Byte0]: 35
1640 09:25:59.784856 [Byte1]: 35
1641 09:25:59.789599
1642 09:25:59.789754 Set Vref, RX VrefLevel [Byte0]: 36
1643 09:25:59.792620 [Byte1]: 36
1644 09:25:59.797132
1645 09:25:59.797288 Set Vref, RX VrefLevel [Byte0]: 37
1646 09:25:59.800493 [Byte1]: 37
1647 09:25:59.804760
1648 09:25:59.804918 Set Vref, RX VrefLevel [Byte0]: 38
1649 09:25:59.808037 [Byte1]: 38
1650 09:25:59.812056
1651 09:25:59.812210 Set Vref, RX VrefLevel [Byte0]: 39
1652 09:25:59.815761 [Byte1]: 39
1653 09:25:59.819910
1654 09:25:59.820066 Set Vref, RX VrefLevel [Byte0]: 40
1655 09:25:59.823455 [Byte1]: 40
1656 09:25:59.827567
1657 09:25:59.827720 Set Vref, RX VrefLevel [Byte0]: 41
1658 09:25:59.830936 [Byte1]: 41
1659 09:25:59.835278
1660 09:25:59.835417 Set Vref, RX VrefLevel [Byte0]: 42
1661 09:25:59.838198 [Byte1]: 42
1662 09:25:59.843006
1663 09:25:59.843127 Set Vref, RX VrefLevel [Byte0]: 43
1664 09:25:59.845871 [Byte1]: 43
1665 09:25:59.850602
1666 09:25:59.850727 Set Vref, RX VrefLevel [Byte0]: 44
1667 09:25:59.853583 [Byte1]: 44
1668 09:25:59.858178
1669 09:25:59.858299 Set Vref, RX VrefLevel [Byte0]: 45
1670 09:25:59.861361 [Byte1]: 45
1671 09:25:59.865645
1672 09:25:59.865762 Set Vref, RX VrefLevel [Byte0]: 46
1673 09:25:59.869084 [Byte1]: 46
1674 09:25:59.873390
1675 09:25:59.873512 Set Vref, RX VrefLevel [Byte0]: 47
1676 09:25:59.877018 [Byte1]: 47
1677 09:25:59.880708
1678 09:25:59.880824 Set Vref, RX VrefLevel [Byte0]: 48
1679 09:25:59.884227 [Byte1]: 48
1680 09:25:59.888421
1681 09:25:59.888540 Set Vref, RX VrefLevel [Byte0]: 49
1682 09:25:59.892093 [Byte1]: 49
1683 09:25:59.896245
1684 09:25:59.896363 Set Vref, RX VrefLevel [Byte0]: 50
1685 09:25:59.899719 [Byte1]: 50
1686 09:25:59.903981
1687 09:25:59.904077 Set Vref, RX VrefLevel [Byte0]: 51
1688 09:25:59.907442 [Byte1]: 51
1689 09:25:59.911951
1690 09:25:59.912076 Set Vref, RX VrefLevel [Byte0]: 52
1691 09:25:59.914689 [Byte1]: 52
1692 09:25:59.919155
1693 09:25:59.919264 Set Vref, RX VrefLevel [Byte0]: 53
1694 09:25:59.922356 [Byte1]: 53
1695 09:25:59.926956
1696 09:25:59.927048 Set Vref, RX VrefLevel [Byte0]: 54
1697 09:25:59.929987 [Byte1]: 54
1698 09:25:59.934674
1699 09:25:59.934786 Set Vref, RX VrefLevel [Byte0]: 55
1700 09:25:59.938063 [Byte1]: 55
1701 09:25:59.942000
1702 09:25:59.942106 Set Vref, RX VrefLevel [Byte0]: 56
1703 09:25:59.945293 [Byte1]: 56
1704 09:25:59.950146
1705 09:25:59.950277 Set Vref, RX VrefLevel [Byte0]: 57
1706 09:25:59.953006 [Byte1]: 57
1707 09:25:59.957852
1708 09:25:59.957968 Set Vref, RX VrefLevel [Byte0]: 58
1709 09:25:59.960737 [Byte1]: 58
1710 09:25:59.965112
1711 09:25:59.965231 Set Vref, RX VrefLevel [Byte0]: 59
1712 09:25:59.968413 [Byte1]: 59
1713 09:25:59.973145
1714 09:25:59.973270 Set Vref, RX VrefLevel [Byte0]: 60
1715 09:25:59.975928 [Byte1]: 60
1716 09:25:59.980295
1717 09:25:59.980409 Set Vref, RX VrefLevel [Byte0]: 61
1718 09:25:59.983813 [Byte1]: 61
1719 09:25:59.988131
1720 09:25:59.988256 Set Vref, RX VrefLevel [Byte0]: 62
1721 09:25:59.991573 [Byte1]: 62
1722 09:25:59.995567
1723 09:25:59.995690 Set Vref, RX VrefLevel [Byte0]: 63
1724 09:25:59.999162 [Byte1]: 63
1725 09:26:00.003350
1726 09:26:00.003462 Set Vref, RX VrefLevel [Byte0]: 64
1727 09:26:00.006914 [Byte1]: 64
1728 09:26:00.011141
1729 09:26:00.011266 Set Vref, RX VrefLevel [Byte0]: 65
1730 09:26:00.014722 [Byte1]: 65
1731 09:26:00.018436
1732 09:26:00.018556 Set Vref, RX VrefLevel [Byte0]: 66
1733 09:26:00.021971 [Byte1]: 66
1734 09:26:00.026056
1735 09:26:00.026174 Set Vref, RX VrefLevel [Byte0]: 67
1736 09:26:00.029415 [Byte1]: 67
1737 09:26:00.033797
1738 09:26:00.033918 Set Vref, RX VrefLevel [Byte0]: 68
1739 09:26:00.037500 [Byte1]: 68
1740 09:26:00.041594
1741 09:26:00.041711 Set Vref, RX VrefLevel [Byte0]: 69
1742 09:26:00.045199 [Byte1]: 69
1743 09:26:00.049064
1744 09:26:00.049189 Set Vref, RX VrefLevel [Byte0]: 70
1745 09:26:00.052720 [Byte1]: 70
1746 09:26:00.056910
1747 09:26:00.057024 Set Vref, RX VrefLevel [Byte0]: 71
1748 09:26:00.060487 [Byte1]: 71
1749 09:26:00.064598
1750 09:26:00.064706 Set Vref, RX VrefLevel [Byte0]: 72
1751 09:26:00.068057 [Byte1]: 72
1752 09:26:00.072215
1753 09:26:00.072319 Set Vref, RX VrefLevel [Byte0]: 73
1754 09:26:00.075618 [Byte1]: 73
1755 09:26:00.079798
1756 09:26:00.079881 Set Vref, RX VrefLevel [Byte0]: 74
1757 09:26:00.083051 [Byte1]: 74
1758 09:26:00.087717
1759 09:26:00.087799 Set Vref, RX VrefLevel [Byte0]: 75
1760 09:26:00.091175 [Byte1]: 75
1761 09:26:00.095401
1762 09:26:00.095513 Set Vref, RX VrefLevel [Byte0]: 76
1763 09:26:00.098442 [Byte1]: 76
1764 09:26:00.102957
1765 09:26:00.103082 Set Vref, RX VrefLevel [Byte0]: 77
1766 09:26:00.106113 [Byte1]: 77
1767 09:26:00.110505
1768 09:26:00.110620 Set Vref, RX VrefLevel [Byte0]: 78
1769 09:26:00.113561 [Byte1]: 78
1770 09:26:00.118230
1771 09:26:00.118320 Set Vref, RX VrefLevel [Byte0]: 79
1772 09:26:00.121664 [Byte1]: 79
1773 09:26:00.125487
1774 09:26:00.125592 Final RX Vref Byte 0 = 64 to rank0
1775 09:26:00.129029 Final RX Vref Byte 1 = 59 to rank0
1776 09:26:00.132624 Final RX Vref Byte 0 = 64 to rank1
1777 09:26:00.135466 Final RX Vref Byte 1 = 59 to rank1==
1778 09:26:00.138924 Dram Type= 6, Freq= 0, CH_1, rank 0
1779 09:26:00.145924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1780 09:26:00.146074 ==
1781 09:26:00.146166 DQS Delay:
1782 09:26:00.146251 DQS0 = 0, DQS1 = 0
1783 09:26:00.148910 DQM Delay:
1784 09:26:00.149004 DQM0 = 83, DQM1 = 74
1785 09:26:00.152489 DQ Delay:
1786 09:26:00.156073 DQ0 =84, DQ1 =76, DQ2 =76, DQ3 =84
1787 09:26:00.156181 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
1788 09:26:00.159358 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1789 09:26:00.162460 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1790 09:26:00.166094
1791 09:26:00.166197
1792 09:26:00.172697 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f04, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 397 ps
1793 09:26:00.176129 CH1 RK0: MR19=606, MR18=2F04
1794 09:26:00.182513 CH1_RK0: MR19=0x606, MR18=0x2F04, DQSOSC=397, MR23=63, INC=93, DEC=62
1795 09:26:00.182617
1796 09:26:00.186180 ----->DramcWriteLeveling(PI) begin...
1797 09:26:00.186259 ==
1798 09:26:00.189172 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 09:26:00.192732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 09:26:00.192839 ==
1801 09:26:00.196354 Write leveling (Byte 0): 24 => 24
1802 09:26:00.199182 Write leveling (Byte 1): 27 => 27
1803 09:26:00.202686 DramcWriteLeveling(PI) end<-----
1804 09:26:00.202778
1805 09:26:00.202840 ==
1806 09:26:00.206217 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 09:26:00.209429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 09:26:00.209543 ==
1809 09:26:00.212831 [Gating] SW mode calibration
1810 09:26:00.219238 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1811 09:26:00.226173 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1812 09:26:00.229354 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1813 09:26:00.232608 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1814 09:26:00.239643 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 09:26:00.242576 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 09:26:00.246000 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 09:26:00.253075 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 09:26:00.256086 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 09:26:00.259705 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 09:26:00.262586 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 09:26:00.269606 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 09:26:00.272585 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 09:26:00.276234 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1824 09:26:00.283054 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1825 09:26:00.286052 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1826 09:26:00.289653 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 09:26:00.296269 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1828 09:26:00.299671 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1829 09:26:00.302828 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1830 09:26:00.309291 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 09:26:00.312754 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 09:26:00.316095 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 09:26:00.322660 0 8 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1834 09:26:00.326089 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 09:26:00.329337 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 09:26:00.336250 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 09:26:00.339465 0 9 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1838 09:26:00.342826 0 9 8 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
1839 09:26:00.346469 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1840 09:26:00.352877 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 09:26:00.356302 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 09:26:00.359678 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 09:26:00.366327 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 09:26:00.369259 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
1845 09:26:00.372799 0 10 4 | B1->B0 | 3030 2929 | 0 0 | (0 0) (0 0)
1846 09:26:00.379278 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
1847 09:26:00.382837 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 09:26:00.386287 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 09:26:00.392753 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 09:26:00.396301 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 09:26:00.399293 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 09:26:00.406435 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1853 09:26:00.409393 0 11 4 | B1->B0 | 2b2b 3636 | 0 0 | (0 0) (1 1)
1854 09:26:00.413193 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1855 09:26:00.419619 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 09:26:00.422945 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 09:26:00.425913 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 09:26:00.429466 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 09:26:00.436468 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 09:26:00.439274 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1861 09:26:00.442775 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1862 09:26:00.449315 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 09:26:00.452738 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 09:26:00.456502 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 09:26:00.462926 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 09:26:00.466220 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 09:26:00.469513 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 09:26:00.476180 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 09:26:00.479696 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 09:26:00.482908 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 09:26:00.489684 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 09:26:00.492679 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 09:26:00.496317 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 09:26:00.502848 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 09:26:00.506392 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 09:26:00.509949 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1877 09:26:00.516511 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1878 09:26:00.519681 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 09:26:00.523196 Total UI for P1: 0, mck2ui 16
1880 09:26:00.526452 best dqsien dly found for B0: ( 0, 14, 2)
1881 09:26:00.529960 Total UI for P1: 0, mck2ui 16
1882 09:26:00.533017 best dqsien dly found for B1: ( 0, 14, 6)
1883 09:26:00.536517 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1884 09:26:00.539447 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1885 09:26:00.539541
1886 09:26:00.542987 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1887 09:26:00.546305 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1888 09:26:00.549824 [Gating] SW calibration Done
1889 09:26:00.549941 ==
1890 09:26:00.552757 Dram Type= 6, Freq= 0, CH_1, rank 1
1891 09:26:00.556355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1892 09:26:00.556459 ==
1893 09:26:00.560005 RX Vref Scan: 0
1894 09:26:00.560116
1895 09:26:00.560201 RX Vref 0 -> 0, step: 1
1896 09:26:00.560320
1897 09:26:00.562953 RX Delay -130 -> 252, step: 16
1898 09:26:00.566505 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1899 09:26:00.572782 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1900 09:26:00.576815 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1901 09:26:00.579584 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1902 09:26:00.583305 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1903 09:26:00.586371 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1904 09:26:00.593252 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1905 09:26:00.596524 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1906 09:26:00.600089 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1907 09:26:00.603160 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1908 09:26:00.606796 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1909 09:26:00.613315 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1910 09:26:00.616979 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1911 09:26:00.620050 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1912 09:26:00.623643 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1913 09:26:00.626539 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1914 09:26:00.626664 ==
1915 09:26:00.629970 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 09:26:00.636693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 09:26:00.636823 ==
1918 09:26:00.636912 DQS Delay:
1919 09:26:00.640323 DQS0 = 0, DQS1 = 0
1920 09:26:00.640420 DQM Delay:
1921 09:26:00.643374 DQM0 = 80, DQM1 = 77
1922 09:26:00.643531 DQ Delay:
1923 09:26:00.646516 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1924 09:26:00.649962 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1925 09:26:00.653371 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1926 09:26:00.656482 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1927 09:26:00.656588
1928 09:26:00.656682
1929 09:26:00.656765 ==
1930 09:26:00.660138 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 09:26:00.663151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 09:26:00.663252 ==
1933 09:26:00.663344
1934 09:26:00.663433
1935 09:26:00.666772 TX Vref Scan disable
1936 09:26:00.669697 == TX Byte 0 ==
1937 09:26:00.672990 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1938 09:26:00.676458 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1939 09:26:00.680058 == TX Byte 1 ==
1940 09:26:00.682912 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1941 09:26:00.686268 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1942 09:26:00.686360 ==
1943 09:26:00.689893 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 09:26:00.693583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 09:26:00.693694 ==
1946 09:26:00.707681 TX Vref=22, minBit 0, minWin=27, winSum=436
1947 09:26:00.710848 TX Vref=24, minBit 0, minWin=27, winSum=442
1948 09:26:00.714407 TX Vref=26, minBit 3, minWin=27, winSum=445
1949 09:26:00.717849 TX Vref=28, minBit 1, minWin=27, winSum=445
1950 09:26:00.721033 TX Vref=30, minBit 11, minWin=27, winSum=448
1951 09:26:00.724223 TX Vref=32, minBit 9, minWin=27, winSum=450
1952 09:26:00.731287 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 32
1953 09:26:00.731417
1954 09:26:00.734168 Final TX Range 1 Vref 32
1955 09:26:00.734244
1956 09:26:00.734303 ==
1957 09:26:00.737778 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 09:26:00.741294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 09:26:00.741371 ==
1960 09:26:00.741437
1961 09:26:00.744749
1962 09:26:00.744843 TX Vref Scan disable
1963 09:26:00.747781 == TX Byte 0 ==
1964 09:26:00.751133 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1965 09:26:00.754315 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1966 09:26:00.758298 == TX Byte 1 ==
1967 09:26:00.761272 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1968 09:26:00.764806 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1969 09:26:00.764908
1970 09:26:00.767781 [DATLAT]
1971 09:26:00.767880 Freq=800, CH1 RK1
1972 09:26:00.767965
1973 09:26:00.771345 DATLAT Default: 0xa
1974 09:26:00.771439 0, 0xFFFF, sum = 0
1975 09:26:00.774400 1, 0xFFFF, sum = 0
1976 09:26:00.774500 2, 0xFFFF, sum = 0
1977 09:26:00.777708 3, 0xFFFF, sum = 0
1978 09:26:00.777825 4, 0xFFFF, sum = 0
1979 09:26:00.781251 5, 0xFFFF, sum = 0
1980 09:26:00.781331 6, 0xFFFF, sum = 0
1981 09:26:00.784310 7, 0xFFFF, sum = 0
1982 09:26:00.784410 8, 0xFFFF, sum = 0
1983 09:26:00.787918 9, 0x0, sum = 1
1984 09:26:00.788017 10, 0x0, sum = 2
1985 09:26:00.791537 11, 0x0, sum = 3
1986 09:26:00.791649 12, 0x0, sum = 4
1987 09:26:00.794363 best_step = 10
1988 09:26:00.794468
1989 09:26:00.794555 ==
1990 09:26:00.797969 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 09:26:00.800981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 09:26:00.801083 ==
1993 09:26:00.804489 RX Vref Scan: 0
1994 09:26:00.804598
1995 09:26:00.804686 RX Vref 0 -> 0, step: 1
1996 09:26:00.804776
1997 09:26:00.807911 RX Delay -95 -> 252, step: 8
1998 09:26:00.814483 iDelay=201, Bit 0, Center 84 (-31 ~ 200) 232
1999 09:26:00.817996 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2000 09:26:00.821069 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2001 09:26:00.824566 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2002 09:26:00.827908 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2003 09:26:00.834580 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2004 09:26:00.837996 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2005 09:26:00.841146 iDelay=201, Bit 7, Center 72 (-39 ~ 184) 224
2006 09:26:00.844405 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2007 09:26:00.847478 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2008 09:26:00.854587 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2009 09:26:00.857501 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2010 09:26:00.861300 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2011 09:26:00.864125 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2012 09:26:00.867544 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2013 09:26:00.874224 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2014 09:26:00.874349 ==
2015 09:26:00.877716 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 09:26:00.881208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 09:26:00.881322 ==
2018 09:26:00.881409 DQS Delay:
2019 09:26:00.884730 DQS0 = 0, DQS1 = 0
2020 09:26:00.884808 DQM Delay:
2021 09:26:00.887691 DQM0 = 79, DQM1 = 75
2022 09:26:00.887786 DQ Delay:
2023 09:26:00.891227 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2024 09:26:00.894263 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =72
2025 09:26:00.897808 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2026 09:26:00.900727 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2027 09:26:00.900835
2028 09:26:00.900926
2029 09:26:00.908016 [DQSOSCAuto] RK1, (LSB)MR18= 0x222d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2030 09:26:00.910999 CH1 RK1: MR19=606, MR18=222D
2031 09:26:00.917416 CH1_RK1: MR19=0x606, MR18=0x222D, DQSOSC=398, MR23=63, INC=93, DEC=62
2032 09:26:00.921136 [RxdqsGatingPostProcess] freq 800
2033 09:26:00.927856 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2034 09:26:00.927984 Pre-setting of DQS Precalculation
2035 09:26:00.934505 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2036 09:26:00.941076 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2037 09:26:00.947734 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2038 09:26:00.947873
2039 09:26:00.947961
2040 09:26:00.951089 [Calibration Summary] 1600 Mbps
2041 09:26:00.954572 CH 0, Rank 0
2042 09:26:00.954677 SW Impedance : PASS
2043 09:26:00.957824 DUTY Scan : NO K
2044 09:26:00.961209 ZQ Calibration : PASS
2045 09:26:00.961314 Jitter Meter : NO K
2046 09:26:00.964666 CBT Training : PASS
2047 09:26:00.964782 Write leveling : PASS
2048 09:26:00.967874 RX DQS gating : PASS
2049 09:26:00.971407 RX DQ/DQS(RDDQC) : PASS
2050 09:26:00.971512 TX DQ/DQS : PASS
2051 09:26:00.974474 RX DATLAT : PASS
2052 09:26:00.977783 RX DQ/DQS(Engine): PASS
2053 09:26:00.977911 TX OE : NO K
2054 09:26:00.981193 All Pass.
2055 09:26:00.981268
2056 09:26:00.981356 CH 0, Rank 1
2057 09:26:00.984689 SW Impedance : PASS
2058 09:26:00.984820 DUTY Scan : NO K
2059 09:26:00.988160 ZQ Calibration : PASS
2060 09:26:00.991235 Jitter Meter : NO K
2061 09:26:00.991346 CBT Training : PASS
2062 09:26:00.994678 Write leveling : PASS
2063 09:26:00.998031 RX DQS gating : PASS
2064 09:26:00.998120 RX DQ/DQS(RDDQC) : PASS
2065 09:26:01.001596 TX DQ/DQS : PASS
2066 09:26:01.001678 RX DATLAT : PASS
2067 09:26:01.004522 RX DQ/DQS(Engine): PASS
2068 09:26:01.008148 TX OE : NO K
2069 09:26:01.008268 All Pass.
2070 09:26:01.008356
2071 09:26:01.008442 CH 1, Rank 0
2072 09:26:01.011171 SW Impedance : PASS
2073 09:26:01.014816 DUTY Scan : NO K
2074 09:26:01.014929 ZQ Calibration : PASS
2075 09:26:01.017793 Jitter Meter : NO K
2076 09:26:01.021354 CBT Training : PASS
2077 09:26:01.021463 Write leveling : PASS
2078 09:26:01.024504 RX DQS gating : PASS
2079 09:26:01.027818 RX DQ/DQS(RDDQC) : PASS
2080 09:26:01.027966 TX DQ/DQS : PASS
2081 09:26:01.031172 RX DATLAT : PASS
2082 09:26:01.034416 RX DQ/DQS(Engine): PASS
2083 09:26:01.034520 TX OE : NO K
2084 09:26:01.038002 All Pass.
2085 09:26:01.038159
2086 09:26:01.038249 CH 1, Rank 1
2087 09:26:01.041613 SW Impedance : PASS
2088 09:26:01.041697 DUTY Scan : NO K
2089 09:26:01.044460 ZQ Calibration : PASS
2090 09:26:01.048050 Jitter Meter : NO K
2091 09:26:01.048140 CBT Training : PASS
2092 09:26:01.051019 Write leveling : PASS
2093 09:26:01.051100 RX DQS gating : PASS
2094 09:26:01.054482 RX DQ/DQS(RDDQC) : PASS
2095 09:26:01.058154 TX DQ/DQS : PASS
2096 09:26:01.058240 RX DATLAT : PASS
2097 09:26:01.061473 RX DQ/DQS(Engine): PASS
2098 09:26:01.064627 TX OE : NO K
2099 09:26:01.064708 All Pass.
2100 09:26:01.064768
2101 09:26:01.067757 DramC Write-DBI off
2102 09:26:01.067851 PER_BANK_REFRESH: Hybrid Mode
2103 09:26:01.071313 TX_TRACKING: ON
2104 09:26:01.074572 [GetDramInforAfterCalByMRR] Vendor 6.
2105 09:26:01.077910 [GetDramInforAfterCalByMRR] Revision 606.
2106 09:26:01.081092 [GetDramInforAfterCalByMRR] Revision 2 0.
2107 09:26:01.081169 MR0 0x3b3b
2108 09:26:01.084556 MR8 0x5151
2109 09:26:01.087556 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 09:26:01.087634
2111 09:26:01.087693 MR0 0x3b3b
2112 09:26:01.087748 MR8 0x5151
2113 09:26:01.094566 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 09:26:01.094652
2115 09:26:01.101301 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2116 09:26:01.104877 [FAST_K] Save calibration result to emmc
2117 09:26:01.107793 [FAST_K] Save calibration result to emmc
2118 09:26:01.111319 dram_init: config_dvfs: 1
2119 09:26:01.114292 dramc_set_vcore_voltage set vcore to 662500
2120 09:26:01.117886 Read voltage for 1200, 2
2121 09:26:01.117976 Vio18 = 0
2122 09:26:01.120932 Vcore = 662500
2123 09:26:01.121010 Vdram = 0
2124 09:26:01.121071 Vddq = 0
2125 09:26:01.124523 Vmddr = 0
2126 09:26:01.128174 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2127 09:26:01.134544 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2128 09:26:01.134627 MEM_TYPE=3, freq_sel=15
2129 09:26:01.137957 sv_algorithm_assistance_LP4_1600
2130 09:26:01.141301 ============ PULL DRAM RESETB DOWN ============
2131 09:26:01.147888 ========== PULL DRAM RESETB DOWN end =========
2132 09:26:01.151387 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2133 09:26:01.154363 ===================================
2134 09:26:01.158217 LPDDR4 DRAM CONFIGURATION
2135 09:26:01.161612 ===================================
2136 09:26:01.161690 EX_ROW_EN[0] = 0x0
2137 09:26:01.164568 EX_ROW_EN[1] = 0x0
2138 09:26:01.164646 LP4Y_EN = 0x0
2139 09:26:01.168092 WORK_FSP = 0x0
2140 09:26:01.168170 WL = 0x4
2141 09:26:01.171433 RL = 0x4
2142 09:26:01.174799 BL = 0x2
2143 09:26:01.174901 RPST = 0x0
2144 09:26:01.178261 RD_PRE = 0x0
2145 09:26:01.178339 WR_PRE = 0x1
2146 09:26:01.181491 WR_PST = 0x0
2147 09:26:01.181559 DBI_WR = 0x0
2148 09:26:01.184986 DBI_RD = 0x0
2149 09:26:01.185064 OTF = 0x1
2150 09:26:01.187967 ===================================
2151 09:26:01.191526 ===================================
2152 09:26:01.191605 ANA top config
2153 09:26:01.195223 ===================================
2154 09:26:01.198401 DLL_ASYNC_EN = 0
2155 09:26:01.201665 ALL_SLAVE_EN = 0
2156 09:26:01.204699 NEW_RANK_MODE = 1
2157 09:26:01.208319 DLL_IDLE_MODE = 1
2158 09:26:01.208397 LP45_APHY_COMB_EN = 1
2159 09:26:01.211661 TX_ODT_DIS = 1
2160 09:26:01.215323 NEW_8X_MODE = 1
2161 09:26:01.218480 ===================================
2162 09:26:01.221416 ===================================
2163 09:26:01.224950 data_rate = 2400
2164 09:26:01.227940 CKR = 1
2165 09:26:01.228018 DQ_P2S_RATIO = 8
2166 09:26:01.231398 ===================================
2167 09:26:01.235103 CA_P2S_RATIO = 8
2168 09:26:01.238138 DQ_CA_OPEN = 0
2169 09:26:01.241088 DQ_SEMI_OPEN = 0
2170 09:26:01.244772 CA_SEMI_OPEN = 0
2171 09:26:01.248097 CA_FULL_RATE = 0
2172 09:26:01.248228 DQ_CKDIV4_EN = 0
2173 09:26:01.251437 CA_CKDIV4_EN = 0
2174 09:26:01.254747 CA_PREDIV_EN = 0
2175 09:26:01.257819 PH8_DLY = 17
2176 09:26:01.261341 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2177 09:26:01.264392 DQ_AAMCK_DIV = 4
2178 09:26:01.264471 CA_AAMCK_DIV = 4
2179 09:26:01.268113 CA_ADMCK_DIV = 4
2180 09:26:01.271478 DQ_TRACK_CA_EN = 0
2181 09:26:01.274340 CA_PICK = 1200
2182 09:26:01.277763 CA_MCKIO = 1200
2183 09:26:01.281384 MCKIO_SEMI = 0
2184 09:26:01.284663 PLL_FREQ = 2366
2185 09:26:01.284743 DQ_UI_PI_RATIO = 32
2186 09:26:01.288046 CA_UI_PI_RATIO = 0
2187 09:26:01.291485 ===================================
2188 09:26:01.294389 ===================================
2189 09:26:01.298176 memory_type:LPDDR4
2190 09:26:01.300962 GP_NUM : 10
2191 09:26:01.301034 SRAM_EN : 1
2192 09:26:01.304536 MD32_EN : 0
2193 09:26:01.308011 ===================================
2194 09:26:01.308089 [ANA_INIT] >>>>>>>>>>>>>>
2195 09:26:01.311095 <<<<<< [CONFIGURE PHASE]: ANA_TX
2196 09:26:01.314509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2197 09:26:01.317877 ===================================
2198 09:26:01.321178 data_rate = 2400,PCW = 0X5b00
2199 09:26:01.324284 ===================================
2200 09:26:01.328017 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2201 09:26:01.334765 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 09:26:01.341100 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 09:26:01.344545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2204 09:26:01.348121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2205 09:26:01.351112 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2206 09:26:01.354663 [ANA_INIT] flow start
2207 09:26:01.354759 [ANA_INIT] PLL >>>>>>>>
2208 09:26:01.358101 [ANA_INIT] PLL <<<<<<<<
2209 09:26:01.361359 [ANA_INIT] MIDPI >>>>>>>>
2210 09:26:01.361437 [ANA_INIT] MIDPI <<<<<<<<
2211 09:26:01.364689 [ANA_INIT] DLL >>>>>>>>
2212 09:26:01.368161 [ANA_INIT] DLL <<<<<<<<
2213 09:26:01.368240 [ANA_INIT] flow end
2214 09:26:01.374790 ============ LP4 DIFF to SE enter ============
2215 09:26:01.377665 ============ LP4 DIFF to SE exit ============
2216 09:26:01.377744 [ANA_INIT] <<<<<<<<<<<<<
2217 09:26:01.381565 [Flow] Enable top DCM control >>>>>
2218 09:26:01.384383 [Flow] Enable top DCM control <<<<<
2219 09:26:01.387980 Enable DLL master slave shuffle
2220 09:26:01.394799 ==============================================================
2221 09:26:01.394883 Gating Mode config
2222 09:26:01.401235 ==============================================================
2223 09:26:01.404793 Config description:
2224 09:26:01.415034 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2225 09:26:01.421524 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2226 09:26:01.424955 SELPH_MODE 0: By rank 1: By Phase
2227 09:26:01.431553 ==============================================================
2228 09:26:01.434932 GAT_TRACK_EN = 1
2229 09:26:01.435016 RX_GATING_MODE = 2
2230 09:26:01.438037 RX_GATING_TRACK_MODE = 2
2231 09:26:01.441303 SELPH_MODE = 1
2232 09:26:01.444921 PICG_EARLY_EN = 1
2233 09:26:01.447991 VALID_LAT_VALUE = 1
2234 09:26:01.455051 ==============================================================
2235 09:26:01.457841 Enter into Gating configuration >>>>
2236 09:26:01.461439 Exit from Gating configuration <<<<
2237 09:26:01.465034 Enter into DVFS_PRE_config >>>>>
2238 09:26:01.474578 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2239 09:26:01.478104 Exit from DVFS_PRE_config <<<<<
2240 09:26:01.481217 Enter into PICG configuration >>>>
2241 09:26:01.484606 Exit from PICG configuration <<<<
2242 09:26:01.487899 [RX_INPUT] configuration >>>>>
2243 09:26:01.488026 [RX_INPUT] configuration <<<<<
2244 09:26:01.494920 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2245 09:26:01.501405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2246 09:26:01.504962 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 09:26:01.511522 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 09:26:01.518548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 09:26:01.525144 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 09:26:01.528515 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2251 09:26:01.531418 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2252 09:26:01.538094 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2253 09:26:01.541684 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2254 09:26:01.544956 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2255 09:26:01.548482 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2256 09:26:01.551687 ===================================
2257 09:26:01.555055 LPDDR4 DRAM CONFIGURATION
2258 09:26:01.558382 ===================================
2259 09:26:01.561725 EX_ROW_EN[0] = 0x0
2260 09:26:01.561846 EX_ROW_EN[1] = 0x0
2261 09:26:01.565333 LP4Y_EN = 0x0
2262 09:26:01.565483 WORK_FSP = 0x0
2263 09:26:01.568397 WL = 0x4
2264 09:26:01.568513 RL = 0x4
2265 09:26:01.572132 BL = 0x2
2266 09:26:01.572257 RPST = 0x0
2267 09:26:01.574984 RD_PRE = 0x0
2268 09:26:01.575088 WR_PRE = 0x1
2269 09:26:01.578123 WR_PST = 0x0
2270 09:26:01.578206 DBI_WR = 0x0
2271 09:26:01.582243 DBI_RD = 0x0
2272 09:26:01.582330 OTF = 0x1
2273 09:26:01.585055 ===================================
2274 09:26:01.591854 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2275 09:26:01.595164 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2276 09:26:01.598221 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2277 09:26:01.601635 ===================================
2278 09:26:01.605024 LPDDR4 DRAM CONFIGURATION
2279 09:26:01.608397 ===================================
2280 09:26:01.611612 EX_ROW_EN[0] = 0x10
2281 09:26:01.611735 EX_ROW_EN[1] = 0x0
2282 09:26:01.615226 LP4Y_EN = 0x0
2283 09:26:01.615339 WORK_FSP = 0x0
2284 09:26:01.618213 WL = 0x4
2285 09:26:01.618334 RL = 0x4
2286 09:26:01.621637 BL = 0x2
2287 09:26:01.621745 RPST = 0x0
2288 09:26:01.625245 RD_PRE = 0x0
2289 09:26:01.625326 WR_PRE = 0x1
2290 09:26:01.628151 WR_PST = 0x0
2291 09:26:01.628232 DBI_WR = 0x0
2292 09:26:01.631763 DBI_RD = 0x0
2293 09:26:01.631876 OTF = 0x1
2294 09:26:01.635374 ===================================
2295 09:26:01.641761 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2296 09:26:01.641868 ==
2297 09:26:01.645328 Dram Type= 6, Freq= 0, CH_0, rank 0
2298 09:26:01.648206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2299 09:26:01.651770 ==
2300 09:26:01.651856 [Duty_Offset_Calibration]
2301 09:26:01.655057 B0:2 B1:-1 CA:1
2302 09:26:01.655136
2303 09:26:01.658498 [DutyScan_Calibration_Flow] k_type=0
2304 09:26:01.666205
2305 09:26:01.666290 ==CLK 0==
2306 09:26:01.669605 Final CLK duty delay cell = -4
2307 09:26:01.672780 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2308 09:26:01.676102 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2309 09:26:01.679829 [-4] AVG Duty = 4953%(X100)
2310 09:26:01.679940
2311 09:26:01.683143 CH0 CLK Duty spec in!! Max-Min= 156%
2312 09:26:01.686087 [DutyScan_Calibration_Flow] ====Done====
2313 09:26:01.686214
2314 09:26:01.689411 [DutyScan_Calibration_Flow] k_type=1
2315 09:26:01.705005
2316 09:26:01.705104 ==DQS 0 ==
2317 09:26:01.708570 Final DQS duty delay cell = 0
2318 09:26:01.711494 [0] MAX Duty = 5125%(X100), DQS PI = 48
2319 09:26:01.715313 [0] MIN Duty = 5000%(X100), DQS PI = 12
2320 09:26:01.715393 [0] AVG Duty = 5062%(X100)
2321 09:26:01.718573
2322 09:26:01.718651 ==DQS 1 ==
2323 09:26:01.722126 Final DQS duty delay cell = -4
2324 09:26:01.725033 [-4] MAX Duty = 5093%(X100), DQS PI = 14
2325 09:26:01.728807 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2326 09:26:01.731732 [-4] AVG Duty = 5046%(X100)
2327 09:26:01.731841
2328 09:26:01.735147 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2329 09:26:01.735228
2330 09:26:01.738629 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2331 09:26:01.741732 [DutyScan_Calibration_Flow] ====Done====
2332 09:26:01.741810
2333 09:26:01.745259 [DutyScan_Calibration_Flow] k_type=3
2334 09:26:01.761752
2335 09:26:01.761899 ==DQM 0 ==
2336 09:26:01.765190 Final DQM duty delay cell = 0
2337 09:26:01.768803 [0] MAX Duty = 5000%(X100), DQS PI = 54
2338 09:26:01.772056 [0] MIN Duty = 4907%(X100), DQS PI = 2
2339 09:26:01.772168 [0] AVG Duty = 4953%(X100)
2340 09:26:01.775310
2341 09:26:01.775389 ==DQM 1 ==
2342 09:26:01.778494 Final DQM duty delay cell = 0
2343 09:26:01.781899 [0] MAX Duty = 5156%(X100), DQS PI = 62
2344 09:26:01.785349 [0] MIN Duty = 4969%(X100), DQS PI = 10
2345 09:26:01.785439 [0] AVG Duty = 5062%(X100)
2346 09:26:01.788821
2347 09:26:01.792137 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2348 09:26:01.792224
2349 09:26:01.795446 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2350 09:26:01.798477 [DutyScan_Calibration_Flow] ====Done====
2351 09:26:01.798559
2352 09:26:01.801966 [DutyScan_Calibration_Flow] k_type=2
2353 09:26:01.817490
2354 09:26:01.817599 ==DQ 0 ==
2355 09:26:01.820853 Final DQ duty delay cell = -4
2356 09:26:01.824090 [-4] MAX Duty = 5031%(X100), DQS PI = 0
2357 09:26:01.827444 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2358 09:26:01.831064 [-4] AVG Duty = 4953%(X100)
2359 09:26:01.831150
2360 09:26:01.831228 ==DQ 1 ==
2361 09:26:01.834493 Final DQ duty delay cell = 0
2362 09:26:01.837587 [0] MAX Duty = 5031%(X100), DQS PI = 18
2363 09:26:01.841055 [0] MIN Duty = 4907%(X100), DQS PI = 46
2364 09:26:01.841138 [0] AVG Duty = 4969%(X100)
2365 09:26:01.844661
2366 09:26:01.847544 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2367 09:26:01.847625
2368 09:26:01.851253 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2369 09:26:01.854227 [DutyScan_Calibration_Flow] ====Done====
2370 09:26:01.854315 ==
2371 09:26:01.857906 Dram Type= 6, Freq= 0, CH_1, rank 0
2372 09:26:01.860955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 09:26:01.861046 ==
2374 09:26:01.864208 [Duty_Offset_Calibration]
2375 09:26:01.864292 B0:1 B1:1 CA:2
2376 09:26:01.864354
2377 09:26:01.867756 [DutyScan_Calibration_Flow] k_type=0
2378 09:26:01.877918
2379 09:26:01.878062 ==CLK 0==
2380 09:26:01.881353 Final CLK duty delay cell = 0
2381 09:26:01.884300 [0] MAX Duty = 5125%(X100), DQS PI = 24
2382 09:26:01.887738 [0] MIN Duty = 4938%(X100), DQS PI = 40
2383 09:26:01.887821 [0] AVG Duty = 5031%(X100)
2384 09:26:01.891401
2385 09:26:01.894685 CH1 CLK Duty spec in!! Max-Min= 187%
2386 09:26:01.897942 [DutyScan_Calibration_Flow] ====Done====
2387 09:26:01.898061
2388 09:26:01.901258 [DutyScan_Calibration_Flow] k_type=1
2389 09:26:01.917247
2390 09:26:01.917355 ==DQS 0 ==
2391 09:26:01.920883 Final DQS duty delay cell = 0
2392 09:26:01.923821 [0] MAX Duty = 5031%(X100), DQS PI = 18
2393 09:26:01.927370 [0] MIN Duty = 4844%(X100), DQS PI = 48
2394 09:26:01.930755 [0] AVG Duty = 4937%(X100)
2395 09:26:01.930836
2396 09:26:01.930896 ==DQS 1 ==
2397 09:26:01.933948 Final DQS duty delay cell = 0
2398 09:26:01.937072 [0] MAX Duty = 5062%(X100), DQS PI = 36
2399 09:26:01.940460 [0] MIN Duty = 4907%(X100), DQS PI = 16
2400 09:26:01.940541 [0] AVG Duty = 4984%(X100)
2401 09:26:01.944017
2402 09:26:01.947431 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2403 09:26:01.947512
2404 09:26:01.951090 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2405 09:26:01.954018 [DutyScan_Calibration_Flow] ====Done====
2406 09:26:01.954113
2407 09:26:01.957527 [DutyScan_Calibration_Flow] k_type=3
2408 09:26:01.974175
2409 09:26:01.974298 ==DQM 0 ==
2410 09:26:01.977078 Final DQM duty delay cell = 0
2411 09:26:01.980668 [0] MAX Duty = 5093%(X100), DQS PI = 16
2412 09:26:01.983719 [0] MIN Duty = 4875%(X100), DQS PI = 48
2413 09:26:01.987462 [0] AVG Duty = 4984%(X100)
2414 09:26:01.987564
2415 09:26:01.987637 ==DQM 1 ==
2416 09:26:01.990344 Final DQM duty delay cell = 0
2417 09:26:01.993930 [0] MAX Duty = 5125%(X100), DQS PI = 60
2418 09:26:01.997260 [0] MIN Duty = 4969%(X100), DQS PI = 4
2419 09:26:01.997352 [0] AVG Duty = 5047%(X100)
2420 09:26:02.000800
2421 09:26:02.003929 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2422 09:26:02.004023
2423 09:26:02.007739 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2424 09:26:02.010411 [DutyScan_Calibration_Flow] ====Done====
2425 09:26:02.010498
2426 09:26:02.013802 [DutyScan_Calibration_Flow] k_type=2
2427 09:26:02.030257
2428 09:26:02.030382 ==DQ 0 ==
2429 09:26:02.033720 Final DQ duty delay cell = 0
2430 09:26:02.037273 [0] MAX Duty = 5124%(X100), DQS PI = 18
2431 09:26:02.040691 [0] MIN Duty = 4907%(X100), DQS PI = 50
2432 09:26:02.040797 [0] AVG Duty = 5015%(X100)
2433 09:26:02.040859
2434 09:26:02.043891 ==DQ 1 ==
2435 09:26:02.046996 Final DQ duty delay cell = 0
2436 09:26:02.050489 [0] MAX Duty = 5093%(X100), DQS PI = 10
2437 09:26:02.053608 [0] MIN Duty = 5031%(X100), DQS PI = 2
2438 09:26:02.053737 [0] AVG Duty = 5062%(X100)
2439 09:26:02.053824
2440 09:26:02.057185 CH1 DQ 0 Duty spec in!! Max-Min= 217%
2441 09:26:02.057275
2442 09:26:02.060767 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2443 09:26:02.066879 [DutyScan_Calibration_Flow] ====Done====
2444 09:26:02.070319 nWR fixed to 30
2445 09:26:02.070402 [ModeRegInit_LP4] CH0 RK0
2446 09:26:02.073845 [ModeRegInit_LP4] CH0 RK1
2447 09:26:02.076949 [ModeRegInit_LP4] CH1 RK0
2448 09:26:02.077026 [ModeRegInit_LP4] CH1 RK1
2449 09:26:02.080549 match AC timing 7
2450 09:26:02.083422 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2451 09:26:02.087073 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2452 09:26:02.093572 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2453 09:26:02.097140 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2454 09:26:02.103554 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2455 09:26:02.103638 ==
2456 09:26:02.107010 Dram Type= 6, Freq= 0, CH_0, rank 0
2457 09:26:02.110333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2458 09:26:02.110413 ==
2459 09:26:02.117151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2460 09:26:02.120367 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2461 09:26:02.130336 [CA 0] Center 40 (10~71) winsize 62
2462 09:26:02.133536 [CA 1] Center 39 (9~70) winsize 62
2463 09:26:02.137137 [CA 2] Center 36 (6~67) winsize 62
2464 09:26:02.140212 [CA 3] Center 36 (5~67) winsize 63
2465 09:26:02.143615 [CA 4] Center 35 (5~65) winsize 61
2466 09:26:02.146534 [CA 5] Center 34 (4~64) winsize 61
2467 09:26:02.146615
2468 09:26:02.150011 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2469 09:26:02.150135
2470 09:26:02.153601 [CATrainingPosCal] consider 1 rank data
2471 09:26:02.156750 u2DelayCellTimex100 = 270/100 ps
2472 09:26:02.160335 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2473 09:26:02.166626 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2474 09:26:02.170168 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2475 09:26:02.173264 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2476 09:26:02.176633 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2477 09:26:02.180231 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2478 09:26:02.180309
2479 09:26:02.183215 CA PerBit enable=1, Macro0, CA PI delay=34
2480 09:26:02.183294
2481 09:26:02.186710 [CBTSetCACLKResult] CA Dly = 34
2482 09:26:02.186791 CS Dly: 7 (0~38)
2483 09:26:02.189756 ==
2484 09:26:02.193352 Dram Type= 6, Freq= 0, CH_0, rank 1
2485 09:26:02.196366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2486 09:26:02.196446 ==
2487 09:26:02.199888 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2488 09:26:02.206379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2489 09:26:02.216270 [CA 0] Center 39 (9~70) winsize 62
2490 09:26:02.219516 [CA 1] Center 39 (9~70) winsize 62
2491 09:26:02.223091 [CA 2] Center 36 (6~67) winsize 62
2492 09:26:02.226026 [CA 3] Center 35 (5~66) winsize 62
2493 09:26:02.229379 [CA 4] Center 34 (4~65) winsize 62
2494 09:26:02.232838 [CA 5] Center 34 (4~64) winsize 61
2495 09:26:02.232917
2496 09:26:02.236152 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2497 09:26:02.236229
2498 09:26:02.239573 [CATrainingPosCal] consider 2 rank data
2499 09:26:02.242938 u2DelayCellTimex100 = 270/100 ps
2500 09:26:02.245940 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2501 09:26:02.249531 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2502 09:26:02.255972 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2503 09:26:02.259544 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2504 09:26:02.262926 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2505 09:26:02.266362 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2506 09:26:02.266440
2507 09:26:02.269744 CA PerBit enable=1, Macro0, CA PI delay=34
2508 09:26:02.269821
2509 09:26:02.272950 [CBTSetCACLKResult] CA Dly = 34
2510 09:26:02.273029 CS Dly: 8 (0~41)
2511 09:26:02.273089
2512 09:26:02.276302 ----->DramcWriteLeveling(PI) begin...
2513 09:26:02.279290 ==
2514 09:26:02.282734 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 09:26:02.286465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 09:26:02.286545 ==
2517 09:26:02.289322 Write leveling (Byte 0): 31 => 31
2518 09:26:02.292945 Write leveling (Byte 1): 30 => 30
2519 09:26:02.296452 DramcWriteLeveling(PI) end<-----
2520 09:26:02.296531
2521 09:26:02.296593 ==
2522 09:26:02.299341 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 09:26:02.302920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 09:26:02.303000 ==
2525 09:26:02.305851 [Gating] SW mode calibration
2526 09:26:02.312970 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2527 09:26:02.316422 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2528 09:26:02.323065 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2529 09:26:02.325986 0 15 4 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
2530 09:26:02.329645 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 09:26:02.336128 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 09:26:02.339635 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 09:26:02.342514 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 09:26:02.349627 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 09:26:02.352722 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2536 09:26:02.356421 1 0 0 | B1->B0 | 3434 3131 | 0 0 | (0 1) (1 0)
2537 09:26:02.362690 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
2538 09:26:02.366391 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 09:26:02.369662 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 09:26:02.376265 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 09:26:02.379630 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 09:26:02.382584 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 09:26:02.389321 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 09:26:02.392902 1 1 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2545 09:26:02.396336 1 1 4 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
2546 09:26:02.399913 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 09:26:02.406394 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 09:26:02.409900 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 09:26:02.413352 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 09:26:02.419920 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 09:26:02.422910 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 09:26:02.426483 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 09:26:02.433201 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2554 09:26:02.436261 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 09:26:02.439693 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 09:26:02.446695 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 09:26:02.449768 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 09:26:02.453278 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 09:26:02.459589 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 09:26:02.463162 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 09:26:02.465802 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 09:26:02.472890 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 09:26:02.476143 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 09:26:02.479572 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 09:26:02.486327 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 09:26:02.489407 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 09:26:02.492673 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 09:26:02.498950 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2569 09:26:02.502695 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2570 09:26:02.506164 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 09:26:02.509066 Total UI for P1: 0, mck2ui 16
2572 09:26:02.512678 best dqsien dly found for B0: ( 1, 4, 2)
2573 09:26:02.516223 Total UI for P1: 0, mck2ui 16
2574 09:26:02.519217 best dqsien dly found for B1: ( 1, 4, 4)
2575 09:26:02.522780 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2576 09:26:02.525922 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2577 09:26:02.526022
2578 09:26:02.529360 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2579 09:26:02.532930 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2580 09:26:02.536277 [Gating] SW calibration Done
2581 09:26:02.536380 ==
2582 09:26:02.539095 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 09:26:02.545968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 09:26:02.546071 ==
2585 09:26:02.546132 RX Vref Scan: 0
2586 09:26:02.546188
2587 09:26:02.549541 RX Vref 0 -> 0, step: 1
2588 09:26:02.549618
2589 09:26:02.552468 RX Delay -40 -> 252, step: 8
2590 09:26:02.556165 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2591 09:26:02.559060 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2592 09:26:02.562816 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2593 09:26:02.566255 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2594 09:26:02.572933 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2595 09:26:02.575803 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2596 09:26:02.579156 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2597 09:26:02.582534 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2598 09:26:02.586138 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2599 09:26:02.589562 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2600 09:26:02.595854 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2601 09:26:02.599366 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2602 09:26:02.602762 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2603 09:26:02.606331 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2604 09:26:02.609460 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2605 09:26:02.616151 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2606 09:26:02.616241 ==
2607 09:26:02.619747 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 09:26:02.622988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 09:26:02.623068 ==
2610 09:26:02.623129 DQS Delay:
2611 09:26:02.625946 DQS0 = 0, DQS1 = 0
2612 09:26:02.626057 DQM Delay:
2613 09:26:02.629697 DQM0 = 115, DQM1 = 107
2614 09:26:02.629777 DQ Delay:
2615 09:26:02.632738 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2616 09:26:02.636222 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2617 09:26:02.639692 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2618 09:26:02.643049 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2619 09:26:02.643128
2620 09:26:02.643188
2621 09:26:02.646287 ==
2622 09:26:02.646366 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 09:26:02.653148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 09:26:02.653239 ==
2625 09:26:02.653300
2626 09:26:02.653354
2627 09:26:02.656123 TX Vref Scan disable
2628 09:26:02.656200 == TX Byte 0 ==
2629 09:26:02.659724 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2630 09:26:02.666371 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2631 09:26:02.666455 == TX Byte 1 ==
2632 09:26:02.669247 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2633 09:26:02.676179 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2634 09:26:02.676262 ==
2635 09:26:02.679469 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 09:26:02.682913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 09:26:02.682993 ==
2638 09:26:02.694307 TX Vref=22, minBit 1, minWin=24, winSum=415
2639 09:26:02.698311 TX Vref=24, minBit 1, minWin=26, winSum=427
2640 09:26:02.701012 TX Vref=26, minBit 1, minWin=26, winSum=429
2641 09:26:02.704415 TX Vref=28, minBit 1, minWin=26, winSum=435
2642 09:26:02.707799 TX Vref=30, minBit 12, minWin=26, winSum=435
2643 09:26:02.714314 TX Vref=32, minBit 4, minWin=26, winSum=435
2644 09:26:02.717587 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 28
2645 09:26:02.717669
2646 09:26:02.721447 Final TX Range 1 Vref 28
2647 09:26:02.721529
2648 09:26:02.721589 ==
2649 09:26:02.724394 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 09:26:02.727787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 09:26:02.727867 ==
2652 09:26:02.730843
2653 09:26:02.730922
2654 09:26:02.730981 TX Vref Scan disable
2655 09:26:02.734364 == TX Byte 0 ==
2656 09:26:02.738021 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2657 09:26:02.741087 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2658 09:26:02.744600 == TX Byte 1 ==
2659 09:26:02.747654 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2660 09:26:02.750904 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2661 09:26:02.754177
2662 09:26:02.754262 [DATLAT]
2663 09:26:02.754323 Freq=1200, CH0 RK0
2664 09:26:02.754379
2665 09:26:02.757546 DATLAT Default: 0xd
2666 09:26:02.757625 0, 0xFFFF, sum = 0
2667 09:26:02.761089 1, 0xFFFF, sum = 0
2668 09:26:02.761170 2, 0xFFFF, sum = 0
2669 09:26:02.764766 3, 0xFFFF, sum = 0
2670 09:26:02.764846 4, 0xFFFF, sum = 0
2671 09:26:02.767563 5, 0xFFFF, sum = 0
2672 09:26:02.771205 6, 0xFFFF, sum = 0
2673 09:26:02.771287 7, 0xFFFF, sum = 0
2674 09:26:02.774221 8, 0xFFFF, sum = 0
2675 09:26:02.774300 9, 0xFFFF, sum = 0
2676 09:26:02.777824 10, 0xFFFF, sum = 0
2677 09:26:02.777904 11, 0xFFFF, sum = 0
2678 09:26:02.780788 12, 0x0, sum = 1
2679 09:26:02.780874 13, 0x0, sum = 2
2680 09:26:02.784147 14, 0x0, sum = 3
2681 09:26:02.784229 15, 0x0, sum = 4
2682 09:26:02.784290 best_step = 13
2683 09:26:02.787837
2684 09:26:02.787920 ==
2685 09:26:02.790748 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 09:26:02.794207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 09:26:02.794291 ==
2688 09:26:02.794352 RX Vref Scan: 1
2689 09:26:02.794409
2690 09:26:02.797768 Set Vref Range= 32 -> 127
2691 09:26:02.797862
2692 09:26:02.800552 RX Vref 32 -> 127, step: 1
2693 09:26:02.800630
2694 09:26:02.804049 RX Delay -21 -> 252, step: 4
2695 09:26:02.804127
2696 09:26:02.807454 Set Vref, RX VrefLevel [Byte0]: 32
2697 09:26:02.810791 [Byte1]: 32
2698 09:26:02.810871
2699 09:26:02.814180 Set Vref, RX VrefLevel [Byte0]: 33
2700 09:26:02.817680 [Byte1]: 33
2701 09:26:02.820828
2702 09:26:02.820910 Set Vref, RX VrefLevel [Byte0]: 34
2703 09:26:02.824134 [Byte1]: 34
2704 09:26:02.828498
2705 09:26:02.828639 Set Vref, RX VrefLevel [Byte0]: 35
2706 09:26:02.832206 [Byte1]: 35
2707 09:26:02.836817
2708 09:26:02.836902 Set Vref, RX VrefLevel [Byte0]: 36
2709 09:26:02.839738 [Byte1]: 36
2710 09:26:02.844451
2711 09:26:02.844550 Set Vref, RX VrefLevel [Byte0]: 37
2712 09:26:02.848070 [Byte1]: 37
2713 09:26:02.852871
2714 09:26:02.852955 Set Vref, RX VrefLevel [Byte0]: 38
2715 09:26:02.855924 [Byte1]: 38
2716 09:26:02.860775
2717 09:26:02.860867 Set Vref, RX VrefLevel [Byte0]: 39
2718 09:26:02.864003 [Byte1]: 39
2719 09:26:02.868669
2720 09:26:02.868777 Set Vref, RX VrefLevel [Byte0]: 40
2721 09:26:02.871468 [Byte1]: 40
2722 09:26:02.876408
2723 09:26:02.876489 Set Vref, RX VrefLevel [Byte0]: 41
2724 09:26:02.879426 [Byte1]: 41
2725 09:26:02.884207
2726 09:26:02.884288 Set Vref, RX VrefLevel [Byte0]: 42
2727 09:26:02.887826 [Byte1]: 42
2728 09:26:02.892339
2729 09:26:02.892419 Set Vref, RX VrefLevel [Byte0]: 43
2730 09:26:02.895610 [Byte1]: 43
2731 09:26:02.900186
2732 09:26:02.900291 Set Vref, RX VrefLevel [Byte0]: 44
2733 09:26:02.903631 [Byte1]: 44
2734 09:26:02.907739
2735 09:26:02.907824 Set Vref, RX VrefLevel [Byte0]: 45
2736 09:26:02.911309 [Byte1]: 45
2737 09:26:02.916160
2738 09:26:02.916242 Set Vref, RX VrefLevel [Byte0]: 46
2739 09:26:02.919531 [Byte1]: 46
2740 09:26:02.923783
2741 09:26:02.923864 Set Vref, RX VrefLevel [Byte0]: 47
2742 09:26:02.926990 [Byte1]: 47
2743 09:26:02.931653
2744 09:26:02.931735 Set Vref, RX VrefLevel [Byte0]: 48
2745 09:26:02.935081 [Byte1]: 48
2746 09:26:02.940046
2747 09:26:02.940128 Set Vref, RX VrefLevel [Byte0]: 49
2748 09:26:02.942749 [Byte1]: 49
2749 09:26:02.947344
2750 09:26:02.947423 Set Vref, RX VrefLevel [Byte0]: 50
2751 09:26:02.950875 [Byte1]: 50
2752 09:26:02.955679
2753 09:26:02.955759 Set Vref, RX VrefLevel [Byte0]: 51
2754 09:26:02.958672 [Byte1]: 51
2755 09:26:02.963743
2756 09:26:02.963821 Set Vref, RX VrefLevel [Byte0]: 52
2757 09:26:02.966801 [Byte1]: 52
2758 09:26:02.971571
2759 09:26:02.971651 Set Vref, RX VrefLevel [Byte0]: 53
2760 09:26:02.974888 [Byte1]: 53
2761 09:26:02.979751
2762 09:26:02.979830 Set Vref, RX VrefLevel [Byte0]: 54
2763 09:26:02.982673 [Byte1]: 54
2764 09:26:02.987544
2765 09:26:02.987624 Set Vref, RX VrefLevel [Byte0]: 55
2766 09:26:02.990550 [Byte1]: 55
2767 09:26:02.995302
2768 09:26:02.995381 Set Vref, RX VrefLevel [Byte0]: 56
2769 09:26:02.998724 [Byte1]: 56
2770 09:26:03.003125
2771 09:26:03.003205 Set Vref, RX VrefLevel [Byte0]: 57
2772 09:26:03.006314 [Byte1]: 57
2773 09:26:03.011402
2774 09:26:03.011482 Set Vref, RX VrefLevel [Byte0]: 58
2775 09:26:03.014288 [Byte1]: 58
2776 09:26:03.019024
2777 09:26:03.019103 Set Vref, RX VrefLevel [Byte0]: 59
2778 09:26:03.022567 [Byte1]: 59
2779 09:26:03.026744
2780 09:26:03.026823 Set Vref, RX VrefLevel [Byte0]: 60
2781 09:26:03.030009 [Byte1]: 60
2782 09:26:03.034566
2783 09:26:03.034646 Set Vref, RX VrefLevel [Byte0]: 61
2784 09:26:03.038487 [Byte1]: 61
2785 09:26:03.042979
2786 09:26:03.043056 Set Vref, RX VrefLevel [Byte0]: 62
2787 09:26:03.046162 [Byte1]: 62
2788 09:26:03.050590
2789 09:26:03.050667 Set Vref, RX VrefLevel [Byte0]: 63
2790 09:26:03.054099 [Byte1]: 63
2791 09:26:03.058368
2792 09:26:03.058447 Set Vref, RX VrefLevel [Byte0]: 64
2793 09:26:03.061992 [Byte1]: 64
2794 09:26:03.066712
2795 09:26:03.066791 Set Vref, RX VrefLevel [Byte0]: 65
2796 09:26:03.069771 [Byte1]: 65
2797 09:26:03.074828
2798 09:26:03.074909 Set Vref, RX VrefLevel [Byte0]: 66
2799 09:26:03.077929 [Byte1]: 66
2800 09:26:03.082281
2801 09:26:03.082359 Set Vref, RX VrefLevel [Byte0]: 67
2802 09:26:03.085726 [Byte1]: 67
2803 09:26:03.090496
2804 09:26:03.090573 Set Vref, RX VrefLevel [Byte0]: 68
2805 09:26:03.093523 [Byte1]: 68
2806 09:26:03.098113
2807 09:26:03.098223 Set Vref, RX VrefLevel [Byte0]: 69
2808 09:26:03.101735 [Byte1]: 69
2809 09:26:03.106172
2810 09:26:03.106250 Final RX Vref Byte 0 = 54 to rank0
2811 09:26:03.109590 Final RX Vref Byte 1 = 52 to rank0
2812 09:26:03.112889 Final RX Vref Byte 0 = 54 to rank1
2813 09:26:03.116096 Final RX Vref Byte 1 = 52 to rank1==
2814 09:26:03.119247 Dram Type= 6, Freq= 0, CH_0, rank 0
2815 09:26:03.126417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2816 09:26:03.126497 ==
2817 09:26:03.126574 DQS Delay:
2818 09:26:03.126643 DQS0 = 0, DQS1 = 0
2819 09:26:03.129287 DQM Delay:
2820 09:26:03.129364 DQM0 = 115, DQM1 = 104
2821 09:26:03.133013 DQ Delay:
2822 09:26:03.136231 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2823 09:26:03.139184 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2824 09:26:03.142936 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2825 09:26:03.146242 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2826 09:26:03.146320
2827 09:26:03.146380
2828 09:26:03.152699 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 409 ps
2829 09:26:03.156115 CH0 RK0: MR19=403, MR18=2F1
2830 09:26:03.162614 CH0_RK0: MR19=0x403, MR18=0x2F1, DQSOSC=409, MR23=63, INC=39, DEC=26
2831 09:26:03.162694
2832 09:26:03.166347 ----->DramcWriteLeveling(PI) begin...
2833 09:26:03.166426 ==
2834 09:26:03.169300 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 09:26:03.172864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 09:26:03.172942 ==
2837 09:26:03.175971 Write leveling (Byte 0): 33 => 33
2838 09:26:03.179407 Write leveling (Byte 1): 29 => 29
2839 09:26:03.182942 DramcWriteLeveling(PI) end<-----
2840 09:26:03.183020
2841 09:26:03.183080 ==
2842 09:26:03.185737 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 09:26:03.189041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 09:26:03.192916 ==
2845 09:26:03.192993 [Gating] SW mode calibration
2846 09:26:03.202494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2847 09:26:03.206180 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2848 09:26:03.209538 0 15 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
2849 09:26:03.216148 0 15 4 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
2850 09:26:03.219562 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 09:26:03.222669 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 09:26:03.229331 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 09:26:03.232686 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 09:26:03.236194 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2855 09:26:03.242624 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
2856 09:26:03.246160 1 0 0 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (0 0)
2857 09:26:03.249463 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 09:26:03.256191 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 09:26:03.259556 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 09:26:03.262737 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 09:26:03.266265 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 09:26:03.272755 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2863 09:26:03.276206 1 0 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
2864 09:26:03.279230 1 1 0 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0)
2865 09:26:03.286359 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 09:26:03.289241 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 09:26:03.292818 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 09:26:03.299433 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 09:26:03.302556 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 09:26:03.305925 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2871 09:26:03.313052 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2872 09:26:03.315845 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2873 09:26:03.319411 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2874 09:26:03.325907 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 09:26:03.329633 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 09:26:03.332551 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 09:26:03.339738 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 09:26:03.342569 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 09:26:03.346145 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 09:26:03.352652 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 09:26:03.356211 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 09:26:03.359674 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 09:26:03.363012 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 09:26:03.369474 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 09:26:03.373198 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 09:26:03.376396 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2887 09:26:03.383001 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2888 09:26:03.386669 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2889 09:26:03.389448 Total UI for P1: 0, mck2ui 16
2890 09:26:03.392561 best dqsien dly found for B0: ( 1, 3, 26)
2891 09:26:03.396048 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 09:26:03.399387 Total UI for P1: 0, mck2ui 16
2893 09:26:03.402858 best dqsien dly found for B1: ( 1, 4, 0)
2894 09:26:03.406339 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2895 09:26:03.409221 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2896 09:26:03.409311
2897 09:26:03.416413 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2898 09:26:03.419268 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2899 09:26:03.419380 [Gating] SW calibration Done
2900 09:26:03.422769 ==
2901 09:26:03.422847 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 09:26:03.429378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 09:26:03.429460 ==
2904 09:26:03.429520 RX Vref Scan: 0
2905 09:26:03.429576
2906 09:26:03.432717 RX Vref 0 -> 0, step: 1
2907 09:26:03.432795
2908 09:26:03.436223 RX Delay -40 -> 252, step: 8
2909 09:26:03.439703 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2910 09:26:03.442964 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2911 09:26:03.446295 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2912 09:26:03.453108 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2913 09:26:03.456303 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2914 09:26:03.459839 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2915 09:26:03.462794 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2916 09:26:03.466260 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2917 09:26:03.469658 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2918 09:26:03.476149 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2919 09:26:03.479449 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2920 09:26:03.482703 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2921 09:26:03.486473 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2922 09:26:03.489914 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2923 09:26:03.496795 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2924 09:26:03.499744 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2925 09:26:03.499826 ==
2926 09:26:03.503176 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 09:26:03.506751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 09:26:03.506834 ==
2929 09:26:03.510092 DQS Delay:
2930 09:26:03.510171 DQS0 = 0, DQS1 = 0
2931 09:26:03.510231 DQM Delay:
2932 09:26:03.513477 DQM0 = 115, DQM1 = 106
2933 09:26:03.513556 DQ Delay:
2934 09:26:03.516421 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2935 09:26:03.520042 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2936 09:26:03.523002 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2937 09:26:03.529891 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2938 09:26:03.529978
2939 09:26:03.530048
2940 09:26:03.530104 ==
2941 09:26:03.532983 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 09:26:03.536881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 09:26:03.536961 ==
2944 09:26:03.537022
2945 09:26:03.537076
2946 09:26:03.539837 TX Vref Scan disable
2947 09:26:03.539915 == TX Byte 0 ==
2948 09:26:03.546815 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2949 09:26:03.550255 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2950 09:26:03.550336 == TX Byte 1 ==
2951 09:26:03.556356 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2952 09:26:03.560087 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2953 09:26:03.560174 ==
2954 09:26:03.563540 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 09:26:03.566554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 09:26:03.566635 ==
2957 09:26:03.579537 TX Vref=22, minBit 4, minWin=25, winSum=420
2958 09:26:03.582472 TX Vref=24, minBit 0, minWin=26, winSum=429
2959 09:26:03.586122 TX Vref=26, minBit 0, minWin=26, winSum=431
2960 09:26:03.589004 TX Vref=28, minBit 6, minWin=26, winSum=439
2961 09:26:03.592280 TX Vref=30, minBit 0, minWin=27, winSum=439
2962 09:26:03.596010 TX Vref=32, minBit 3, minWin=26, winSum=437
2963 09:26:03.602457 [TxChooseVref] Worse bit 0, Min win 27, Win sum 439, Final Vref 30
2964 09:26:03.602550
2965 09:26:03.606110 Final TX Range 1 Vref 30
2966 09:26:03.606209
2967 09:26:03.606270 ==
2968 09:26:03.609467 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 09:26:03.612549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 09:26:03.612630 ==
2971 09:26:03.612691
2972 09:26:03.612746
2973 09:26:03.615926 TX Vref Scan disable
2974 09:26:03.619267 == TX Byte 0 ==
2975 09:26:03.622803 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2976 09:26:03.625891 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2977 09:26:03.629224 == TX Byte 1 ==
2978 09:26:03.632726 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2979 09:26:03.635665 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2980 09:26:03.635742
2981 09:26:03.639336 [DATLAT]
2982 09:26:03.639415 Freq=1200, CH0 RK1
2983 09:26:03.639476
2984 09:26:03.642753 DATLAT Default: 0xd
2985 09:26:03.642831 0, 0xFFFF, sum = 0
2986 09:26:03.645643 1, 0xFFFF, sum = 0
2987 09:26:03.645722 2, 0xFFFF, sum = 0
2988 09:26:03.649123 3, 0xFFFF, sum = 0
2989 09:26:03.649202 4, 0xFFFF, sum = 0
2990 09:26:03.652604 5, 0xFFFF, sum = 0
2991 09:26:03.652684 6, 0xFFFF, sum = 0
2992 09:26:03.656154 7, 0xFFFF, sum = 0
2993 09:26:03.656236 8, 0xFFFF, sum = 0
2994 09:26:03.658943 9, 0xFFFF, sum = 0
2995 09:26:03.662267 10, 0xFFFF, sum = 0
2996 09:26:03.662348 11, 0xFFFF, sum = 0
2997 09:26:03.665903 12, 0x0, sum = 1
2998 09:26:03.665991 13, 0x0, sum = 2
2999 09:26:03.666086 14, 0x0, sum = 3
3000 09:26:03.669354 15, 0x0, sum = 4
3001 09:26:03.669433 best_step = 13
3002 09:26:03.669493
3003 09:26:03.669548 ==
3004 09:26:03.672366 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 09:26:03.679247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 09:26:03.679330 ==
3007 09:26:03.679391 RX Vref Scan: 0
3008 09:26:03.679447
3009 09:26:03.682766 RX Vref 0 -> 0, step: 1
3010 09:26:03.682845
3011 09:26:03.685898 RX Delay -21 -> 252, step: 4
3012 09:26:03.689341 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3013 09:26:03.692379 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3014 09:26:03.699503 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3015 09:26:03.702800 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3016 09:26:03.706264 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3017 09:26:03.709128 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3018 09:26:03.712246 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3019 09:26:03.719198 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3020 09:26:03.722651 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3021 09:26:03.725839 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3022 09:26:03.729399 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3023 09:26:03.732748 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3024 09:26:03.739581 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3025 09:26:03.742620 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3026 09:26:03.745922 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3027 09:26:03.749587 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3028 09:26:03.749669 ==
3029 09:26:03.752631 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 09:26:03.756067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 09:26:03.759671 ==
3032 09:26:03.759754 DQS Delay:
3033 09:26:03.759833 DQS0 = 0, DQS1 = 0
3034 09:26:03.762497 DQM Delay:
3035 09:26:03.762576 DQM0 = 114, DQM1 = 105
3036 09:26:03.766439 DQ Delay:
3037 09:26:03.769180 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3038 09:26:03.772874 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3039 09:26:03.775869 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3040 09:26:03.779365 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =114
3041 09:26:03.779446
3042 09:26:03.779524
3043 09:26:03.786301 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3044 09:26:03.789312 CH0 RK1: MR19=403, MR18=4F5
3045 09:26:03.795914 CH0_RK1: MR19=0x403, MR18=0x4F5, DQSOSC=408, MR23=63, INC=39, DEC=26
3046 09:26:03.799290 [RxdqsGatingPostProcess] freq 1200
3047 09:26:03.802934 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3048 09:26:03.805878 best DQS0 dly(2T, 0.5T) = (0, 12)
3049 09:26:03.809424 best DQS1 dly(2T, 0.5T) = (0, 12)
3050 09:26:03.812484 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3051 09:26:03.815982 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3052 09:26:03.819516 best DQS0 dly(2T, 0.5T) = (0, 11)
3053 09:26:03.822956 best DQS1 dly(2T, 0.5T) = (0, 12)
3054 09:26:03.826269 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3055 09:26:03.829626 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3056 09:26:03.832822 Pre-setting of DQS Precalculation
3057 09:26:03.836245 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3058 09:26:03.836327 ==
3059 09:26:03.839586 Dram Type= 6, Freq= 0, CH_1, rank 0
3060 09:26:03.845912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 09:26:03.846037 ==
3062 09:26:03.849404 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3063 09:26:03.856187 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3064 09:26:03.864981 [CA 0] Center 38 (9~68) winsize 60
3065 09:26:03.867946 [CA 1] Center 38 (8~68) winsize 61
3066 09:26:03.871335 [CA 2] Center 35 (5~65) winsize 61
3067 09:26:03.874751 [CA 3] Center 34 (4~65) winsize 62
3068 09:26:03.878370 [CA 4] Center 34 (4~65) winsize 62
3069 09:26:03.881304 [CA 5] Center 34 (4~64) winsize 61
3070 09:26:03.881384
3071 09:26:03.884665 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3072 09:26:03.884745
3073 09:26:03.888296 [CATrainingPosCal] consider 1 rank data
3074 09:26:03.891960 u2DelayCellTimex100 = 270/100 ps
3075 09:26:03.894811 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3076 09:26:03.898388 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3077 09:26:03.901461 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3078 09:26:03.908123 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3079 09:26:03.911654 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3080 09:26:03.915232 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3081 09:26:03.915313
3082 09:26:03.918120 CA PerBit enable=1, Macro0, CA PI delay=34
3083 09:26:03.918200
3084 09:26:03.921420 [CBTSetCACLKResult] CA Dly = 34
3085 09:26:03.921498 CS Dly: 6 (0~37)
3086 09:26:03.921559 ==
3087 09:26:03.925355 Dram Type= 6, Freq= 0, CH_1, rank 1
3088 09:26:03.932127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 09:26:03.932217 ==
3090 09:26:03.934919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3091 09:26:03.941878 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3092 09:26:03.950412 [CA 0] Center 38 (8~68) winsize 61
3093 09:26:03.953496 [CA 1] Center 38 (8~68) winsize 61
3094 09:26:03.957241 [CA 2] Center 34 (4~65) winsize 62
3095 09:26:03.960270 [CA 3] Center 34 (4~65) winsize 62
3096 09:26:03.963552 [CA 4] Center 34 (4~65) winsize 62
3097 09:26:03.966975 [CA 5] Center 33 (3~63) winsize 61
3098 09:26:03.967080
3099 09:26:03.970424 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3100 09:26:03.970518
3101 09:26:03.973434 [CATrainingPosCal] consider 2 rank data
3102 09:26:03.976873 u2DelayCellTimex100 = 270/100 ps
3103 09:26:03.980167 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3104 09:26:03.983750 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3105 09:26:03.987349 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3106 09:26:03.993799 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3107 09:26:03.997290 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3108 09:26:04.000417 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3109 09:26:04.000500
3110 09:26:04.004079 CA PerBit enable=1, Macro0, CA PI delay=33
3111 09:26:04.004162
3112 09:26:04.007102 [CBTSetCACLKResult] CA Dly = 33
3113 09:26:04.007182 CS Dly: 7 (0~40)
3114 09:26:04.007261
3115 09:26:04.010660 ----->DramcWriteLeveling(PI) begin...
3116 09:26:04.010742 ==
3117 09:26:04.013733 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 09:26:04.020859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 09:26:04.020948 ==
3120 09:26:04.023832 Write leveling (Byte 0): 25 => 25
3121 09:26:04.027310 Write leveling (Byte 1): 28 => 28
3122 09:26:04.027391 DramcWriteLeveling(PI) end<-----
3123 09:26:04.027469
3124 09:26:04.030795 ==
3125 09:26:04.033937 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 09:26:04.037054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 09:26:04.037162 ==
3128 09:26:04.040394 [Gating] SW mode calibration
3129 09:26:04.047119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3130 09:26:04.050399 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3131 09:26:04.057289 0 15 0 | B1->B0 | 2d2d 2525 | 0 0 | (0 0) (0 0)
3132 09:26:04.060810 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3133 09:26:04.064003 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 09:26:04.070668 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 09:26:04.074263 0 15 16 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
3136 09:26:04.077221 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 09:26:04.084057 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 09:26:04.087667 0 15 28 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 1)
3139 09:26:04.090560 1 0 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3140 09:26:04.093951 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3141 09:26:04.100677 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 09:26:04.104408 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 09:26:04.107282 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 09:26:04.113906 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 09:26:04.117518 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 09:26:04.121034 1 0 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3147 09:26:04.127740 1 1 0 | B1->B0 | 4242 3535 | 0 0 | (0 0) (0 0)
3148 09:26:04.130772 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 09:26:04.134270 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 09:26:04.144087 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 09:26:04.144398 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 09:26:04.147385 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 09:26:04.154374 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 09:26:04.157536 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3155 09:26:04.161176 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 09:26:04.164484 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 09:26:04.171263 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 09:26:04.174214 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 09:26:04.177509 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 09:26:04.184268 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 09:26:04.187510 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 09:26:04.190962 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 09:26:04.197625 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 09:26:04.201261 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 09:26:04.204255 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 09:26:04.211339 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 09:26:04.214961 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 09:26:04.218024 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 09:26:04.224388 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 09:26:04.227975 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3171 09:26:04.230949 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3172 09:26:04.234723 Total UI for P1: 0, mck2ui 16
3173 09:26:04.238167 best dqsien dly found for B1: ( 1, 3, 28)
3174 09:26:04.241139 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 09:26:04.244744 Total UI for P1: 0, mck2ui 16
3176 09:26:04.248176 best dqsien dly found for B0: ( 1, 3, 30)
3177 09:26:04.251234 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3178 09:26:04.254714 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3179 09:26:04.258055
3180 09:26:04.261029 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3181 09:26:04.264534 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3182 09:26:04.267741 [Gating] SW calibration Done
3183 09:26:04.267822 ==
3184 09:26:04.271093 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 09:26:04.274392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 09:26:04.274473 ==
3187 09:26:04.274534 RX Vref Scan: 0
3188 09:26:04.277662
3189 09:26:04.277741 RX Vref 0 -> 0, step: 1
3190 09:26:04.277802
3191 09:26:04.281247 RX Delay -40 -> 252, step: 8
3192 09:26:04.284663 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3193 09:26:04.287883 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3194 09:26:04.294609 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3195 09:26:04.297858 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3196 09:26:04.301466 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3197 09:26:04.304730 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3198 09:26:04.308196 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3199 09:26:04.314716 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3200 09:26:04.317822 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3201 09:26:04.321326 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3202 09:26:04.324831 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3203 09:26:04.327853 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3204 09:26:04.331528 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3205 09:26:04.337938 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3206 09:26:04.341644 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3207 09:26:04.344537 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3208 09:26:04.344618 ==
3209 09:26:04.348184 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 09:26:04.351141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 09:26:04.354514 ==
3212 09:26:04.354632 DQS Delay:
3213 09:26:04.354708 DQS0 = 0, DQS1 = 0
3214 09:26:04.357977 DQM Delay:
3215 09:26:04.358081 DQM0 = 115, DQM1 = 108
3216 09:26:04.361212 DQ Delay:
3217 09:26:04.364705 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3218 09:26:04.368334 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3219 09:26:04.371356 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3220 09:26:04.374812 DQ12 =123, DQ13 =115, DQ14 =111, DQ15 =111
3221 09:26:04.374895
3222 09:26:04.374955
3223 09:26:04.375011 ==
3224 09:26:04.378470 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 09:26:04.381690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 09:26:04.381774 ==
3227 09:26:04.381835
3228 09:26:04.381890
3229 09:26:04.384595 TX Vref Scan disable
3230 09:26:04.387962 == TX Byte 0 ==
3231 09:26:04.391804 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3232 09:26:04.394687 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3233 09:26:04.398311 == TX Byte 1 ==
3234 09:26:04.401833 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3235 09:26:04.404619 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3236 09:26:04.404725 ==
3237 09:26:04.408142 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 09:26:04.411387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 09:26:04.411492 ==
3240 09:26:04.424760 TX Vref=22, minBit 3, minWin=25, winSum=415
3241 09:26:04.428460 TX Vref=24, minBit 1, minWin=25, winSum=417
3242 09:26:04.431407 TX Vref=26, minBit 0, minWin=26, winSum=425
3243 09:26:04.434990 TX Vref=28, minBit 0, minWin=26, winSum=429
3244 09:26:04.437931 TX Vref=30, minBit 0, minWin=26, winSum=431
3245 09:26:04.441510 TX Vref=32, minBit 3, minWin=26, winSum=432
3246 09:26:04.448218 [TxChooseVref] Worse bit 3, Min win 26, Win sum 432, Final Vref 32
3247 09:26:04.448306
3248 09:26:04.451633 Final TX Range 1 Vref 32
3249 09:26:04.451714
3250 09:26:04.451774 ==
3251 09:26:04.454639 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 09:26:04.458153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 09:26:04.458242 ==
3254 09:26:04.458304
3255 09:26:04.461664
3256 09:26:04.461767 TX Vref Scan disable
3257 09:26:04.464656 == TX Byte 0 ==
3258 09:26:04.468319 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3259 09:26:04.471457 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3260 09:26:04.474874 == TX Byte 1 ==
3261 09:26:04.478140 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3262 09:26:04.481124 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3263 09:26:04.481228
3264 09:26:04.484678 [DATLAT]
3265 09:26:04.484758 Freq=1200, CH1 RK0
3266 09:26:04.484818
3267 09:26:04.487960 DATLAT Default: 0xd
3268 09:26:04.488038 0, 0xFFFF, sum = 0
3269 09:26:04.491407 1, 0xFFFF, sum = 0
3270 09:26:04.491498 2, 0xFFFF, sum = 0
3271 09:26:04.494548 3, 0xFFFF, sum = 0
3272 09:26:04.494645 4, 0xFFFF, sum = 0
3273 09:26:04.498201 5, 0xFFFF, sum = 0
3274 09:26:04.498281 6, 0xFFFF, sum = 0
3275 09:26:04.501219 7, 0xFFFF, sum = 0
3276 09:26:04.501297 8, 0xFFFF, sum = 0
3277 09:26:04.504816 9, 0xFFFF, sum = 0
3278 09:26:04.508290 10, 0xFFFF, sum = 0
3279 09:26:04.508369 11, 0xFFFF, sum = 0
3280 09:26:04.511559 12, 0x0, sum = 1
3281 09:26:04.511660 13, 0x0, sum = 2
3282 09:26:04.511749 14, 0x0, sum = 3
3283 09:26:04.514560 15, 0x0, sum = 4
3284 09:26:04.514665 best_step = 13
3285 09:26:04.514755
3286 09:26:04.518094 ==
3287 09:26:04.518179 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 09:26:04.524458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 09:26:04.524542 ==
3290 09:26:04.524603 RX Vref Scan: 1
3291 09:26:04.524659
3292 09:26:04.527801 Set Vref Range= 32 -> 127
3293 09:26:04.527881
3294 09:26:04.531340 RX Vref 32 -> 127, step: 1
3295 09:26:04.531418
3296 09:26:04.534460 RX Delay -21 -> 252, step: 4
3297 09:26:04.534537
3298 09:26:04.537888 Set Vref, RX VrefLevel [Byte0]: 32
3299 09:26:04.541450 [Byte1]: 32
3300 09:26:04.541528
3301 09:26:04.544336 Set Vref, RX VrefLevel [Byte0]: 33
3302 09:26:04.547938 [Byte1]: 33
3303 09:26:04.548017
3304 09:26:04.551612 Set Vref, RX VrefLevel [Byte0]: 34
3305 09:26:04.554680 [Byte1]: 34
3306 09:26:04.558786
3307 09:26:04.558866 Set Vref, RX VrefLevel [Byte0]: 35
3308 09:26:04.562304 [Byte1]: 35
3309 09:26:04.566592
3310 09:26:04.566669 Set Vref, RX VrefLevel [Byte0]: 36
3311 09:26:04.570043 [Byte1]: 36
3312 09:26:04.574831
3313 09:26:04.574909 Set Vref, RX VrefLevel [Byte0]: 37
3314 09:26:04.577840 [Byte1]: 37
3315 09:26:04.582315
3316 09:26:04.582394 Set Vref, RX VrefLevel [Byte0]: 38
3317 09:26:04.585783 [Byte1]: 38
3318 09:26:04.590665
3319 09:26:04.590742 Set Vref, RX VrefLevel [Byte0]: 39
3320 09:26:04.593768 [Byte1]: 39
3321 09:26:04.598664
3322 09:26:04.598743 Set Vref, RX VrefLevel [Byte0]: 40
3323 09:26:04.601603 [Byte1]: 40
3324 09:26:04.606428
3325 09:26:04.606508 Set Vref, RX VrefLevel [Byte0]: 41
3326 09:26:04.609674 [Byte1]: 41
3327 09:26:04.614321
3328 09:26:04.614399 Set Vref, RX VrefLevel [Byte0]: 42
3329 09:26:04.617436 [Byte1]: 42
3330 09:26:04.622207
3331 09:26:04.622290 Set Vref, RX VrefLevel [Byte0]: 43
3332 09:26:04.625611 [Byte1]: 43
3333 09:26:04.629867
3334 09:26:04.629970 Set Vref, RX VrefLevel [Byte0]: 44
3335 09:26:04.633457 [Byte1]: 44
3336 09:26:04.637883
3337 09:26:04.637994 Set Vref, RX VrefLevel [Byte0]: 45
3338 09:26:04.641594 [Byte1]: 45
3339 09:26:04.645639
3340 09:26:04.645711 Set Vref, RX VrefLevel [Byte0]: 46
3341 09:26:04.649266 [Byte1]: 46
3342 09:26:04.653967
3343 09:26:04.654054 Set Vref, RX VrefLevel [Byte0]: 47
3344 09:26:04.657059 [Byte1]: 47
3345 09:26:04.661821
3346 09:26:04.661924 Set Vref, RX VrefLevel [Byte0]: 48
3347 09:26:04.665334 [Byte1]: 48
3348 09:26:04.669548
3349 09:26:04.669626 Set Vref, RX VrefLevel [Byte0]: 49
3350 09:26:04.673087 [Byte1]: 49
3351 09:26:04.677910
3352 09:26:04.678045 Set Vref, RX VrefLevel [Byte0]: 50
3353 09:26:04.680796 [Byte1]: 50
3354 09:26:04.685644
3355 09:26:04.685722 Set Vref, RX VrefLevel [Byte0]: 51
3356 09:26:04.689201 [Byte1]: 51
3357 09:26:04.693758
3358 09:26:04.693837 Set Vref, RX VrefLevel [Byte0]: 52
3359 09:26:04.696646 [Byte1]: 52
3360 09:26:04.701559
3361 09:26:04.701639 Set Vref, RX VrefLevel [Byte0]: 53
3362 09:26:04.704702 [Byte1]: 53
3363 09:26:04.709108
3364 09:26:04.709188 Set Vref, RX VrefLevel [Byte0]: 54
3365 09:26:04.712630 [Byte1]: 54
3366 09:26:04.717387
3367 09:26:04.717470 Set Vref, RX VrefLevel [Byte0]: 55
3368 09:26:04.720362 [Byte1]: 55
3369 09:26:04.724898
3370 09:26:04.724976 Set Vref, RX VrefLevel [Byte0]: 56
3371 09:26:04.728284 [Byte1]: 56
3372 09:26:04.732900
3373 09:26:04.732981 Set Vref, RX VrefLevel [Byte0]: 57
3374 09:26:04.736186 [Byte1]: 57
3375 09:26:04.740965
3376 09:26:04.741044 Set Vref, RX VrefLevel [Byte0]: 58
3377 09:26:04.744415 [Byte1]: 58
3378 09:26:04.749094
3379 09:26:04.749173 Set Vref, RX VrefLevel [Byte0]: 59
3380 09:26:04.751969 [Byte1]: 59
3381 09:26:04.756633
3382 09:26:04.756718 Set Vref, RX VrefLevel [Byte0]: 60
3383 09:26:04.760229 [Byte1]: 60
3384 09:26:04.765015
3385 09:26:04.765094 Set Vref, RX VrefLevel [Byte0]: 61
3386 09:26:04.767950 [Byte1]: 61
3387 09:26:04.772592
3388 09:26:04.772695 Set Vref, RX VrefLevel [Byte0]: 62
3389 09:26:04.776261 [Byte1]: 62
3390 09:26:04.780511
3391 09:26:04.780591 Set Vref, RX VrefLevel [Byte0]: 63
3392 09:26:04.784008 [Byte1]: 63
3393 09:26:04.788781
3394 09:26:04.788862 Set Vref, RX VrefLevel [Byte0]: 64
3395 09:26:04.791797 [Byte1]: 64
3396 09:26:04.796543
3397 09:26:04.796624 Set Vref, RX VrefLevel [Byte0]: 65
3398 09:26:04.800045 [Byte1]: 65
3399 09:26:04.804093
3400 09:26:04.804173 Set Vref, RX VrefLevel [Byte0]: 66
3401 09:26:04.807615 [Byte1]: 66
3402 09:26:04.812304
3403 09:26:04.812383 Set Vref, RX VrefLevel [Byte0]: 67
3404 09:26:04.815350 [Byte1]: 67
3405 09:26:04.820210
3406 09:26:04.820302 Set Vref, RX VrefLevel [Byte0]: 68
3407 09:26:04.823530 [Byte1]: 68
3408 09:26:04.828326
3409 09:26:04.828404 Set Vref, RX VrefLevel [Byte0]: 69
3410 09:26:04.831355 [Byte1]: 69
3411 09:26:04.835996
3412 09:26:04.836074 Final RX Vref Byte 0 = 60 to rank0
3413 09:26:04.839295 Final RX Vref Byte 1 = 53 to rank0
3414 09:26:04.842568 Final RX Vref Byte 0 = 60 to rank1
3415 09:26:04.846181 Final RX Vref Byte 1 = 53 to rank1==
3416 09:26:04.849073 Dram Type= 6, Freq= 0, CH_1, rank 0
3417 09:26:04.856283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 09:26:04.856364 ==
3419 09:26:04.856424 DQS Delay:
3420 09:26:04.856479 DQS0 = 0, DQS1 = 0
3421 09:26:04.859356 DQM Delay:
3422 09:26:04.859434 DQM0 = 115, DQM1 = 110
3423 09:26:04.862963 DQ Delay:
3424 09:26:04.866289 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3425 09:26:04.869228 DQ4 =116, DQ5 =122, DQ6 =126, DQ7 =112
3426 09:26:04.872819 DQ8 =100, DQ9 =98, DQ10 =114, DQ11 =106
3427 09:26:04.875886 DQ12 =116, DQ13 =116, DQ14 =118, DQ15 =114
3428 09:26:04.875965
3429 09:26:04.876025
3430 09:26:04.882365 [DQSOSCAuto] RK0, (LSB)MR18= 0xfee2, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3431 09:26:04.885915 CH1 RK0: MR19=303, MR18=FEE2
3432 09:26:04.892494 CH1_RK0: MR19=0x303, MR18=0xFEE2, DQSOSC=410, MR23=63, INC=39, DEC=26
3433 09:26:04.892573
3434 09:26:04.896278 ----->DramcWriteLeveling(PI) begin...
3435 09:26:04.896357 ==
3436 09:26:04.899245 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 09:26:04.902790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 09:26:04.905835 ==
3439 09:26:04.905912 Write leveling (Byte 0): 26 => 26
3440 09:26:04.909210 Write leveling (Byte 1): 28 => 28
3441 09:26:04.912663 DramcWriteLeveling(PI) end<-----
3442 09:26:04.912740
3443 09:26:04.912800 ==
3444 09:26:04.915644 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 09:26:04.922492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3446 09:26:04.922570 ==
3447 09:26:04.925745 [Gating] SW mode calibration
3448 09:26:04.932610 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3449 09:26:04.935555 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3450 09:26:04.942164 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3451 09:26:04.945732 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 09:26:04.948889 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 09:26:04.952620 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 09:26:04.959235 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 09:26:04.962198 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3456 09:26:04.965765 0 15 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
3457 09:26:04.972579 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
3458 09:26:04.975654 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 09:26:04.979353 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 09:26:04.985682 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 09:26:04.989386 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 09:26:04.992340 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 09:26:04.999424 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3464 09:26:05.002371 1 0 24 | B1->B0 | 2424 3d3d | 0 1 | (0 0) (0 0)
3465 09:26:05.005971 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 09:26:05.012470 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 09:26:05.015995 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 09:26:05.019681 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 09:26:05.026147 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 09:26:05.029541 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 09:26:05.032525 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3472 09:26:05.036057 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3473 09:26:05.042716 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3474 09:26:05.046055 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 09:26:05.049640 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 09:26:05.055964 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 09:26:05.059151 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 09:26:05.062652 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 09:26:05.069253 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 09:26:05.073010 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 09:26:05.075991 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 09:26:05.082959 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 09:26:05.086937 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 09:26:05.089651 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 09:26:05.096268 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 09:26:05.099639 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 09:26:05.102773 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3488 09:26:05.109302 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3489 09:26:05.112916 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3490 09:26:05.115893 Total UI for P1: 0, mck2ui 16
3491 09:26:05.119257 best dqsien dly found for B0: ( 1, 3, 22)
3492 09:26:05.122768 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 09:26:05.126400 Total UI for P1: 0, mck2ui 16
3494 09:26:05.129258 best dqsien dly found for B1: ( 1, 3, 28)
3495 09:26:05.132807 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3496 09:26:05.135831 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3497 09:26:05.135912
3498 09:26:05.139427 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3499 09:26:05.145898 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3500 09:26:05.146005 [Gating] SW calibration Done
3501 09:26:05.146083 ==
3502 09:26:05.149314 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 09:26:05.155999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 09:26:05.156161 ==
3505 09:26:05.156262 RX Vref Scan: 0
3506 09:26:05.156321
3507 09:26:05.159542 RX Vref 0 -> 0, step: 1
3508 09:26:05.159631
3509 09:26:05.162830 RX Delay -40 -> 252, step: 8
3510 09:26:05.166092 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3511 09:26:05.169549 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3512 09:26:05.173054 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3513 09:26:05.176034 iDelay=192, Bit 3, Center 111 (40 ~ 183) 144
3514 09:26:05.182643 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3515 09:26:05.186203 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3516 09:26:05.189876 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3517 09:26:05.192812 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3518 09:26:05.196381 iDelay=192, Bit 8, Center 99 (24 ~ 175) 152
3519 09:26:05.202705 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3520 09:26:05.206400 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3521 09:26:05.209653 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3522 09:26:05.212769 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3523 09:26:05.216160 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3524 09:26:05.222994 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3525 09:26:05.226461 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3526 09:26:05.226563 ==
3527 09:26:05.229541 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 09:26:05.232943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 09:26:05.233069 ==
3530 09:26:05.233162 DQS Delay:
3531 09:26:05.236211 DQS0 = 0, DQS1 = 0
3532 09:26:05.236327 DQM Delay:
3533 09:26:05.239290 DQM0 = 112, DQM1 = 110
3534 09:26:05.239394 DQ Delay:
3535 09:26:05.243033 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =111
3536 09:26:05.246588 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3537 09:26:05.249491 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3538 09:26:05.253142 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3539 09:26:05.253222
3540 09:26:05.256436
3541 09:26:05.256541 ==
3542 09:26:05.259741 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 09:26:05.262949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 09:26:05.263068 ==
3545 09:26:05.263166
3546 09:26:05.263220
3547 09:26:05.266467 TX Vref Scan disable
3548 09:26:05.266545 == TX Byte 0 ==
3549 09:26:05.272852 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3550 09:26:05.276554 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3551 09:26:05.276638 == TX Byte 1 ==
3552 09:26:05.280102 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3553 09:26:05.286776 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3554 09:26:05.286860 ==
3555 09:26:05.289723 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 09:26:05.293227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 09:26:05.293310 ==
3558 09:26:05.305080 TX Vref=22, minBit 0, minWin=25, winSum=419
3559 09:26:05.308540 TX Vref=24, minBit 0, minWin=26, winSum=423
3560 09:26:05.311929 TX Vref=26, minBit 1, minWin=26, winSum=431
3561 09:26:05.314818 TX Vref=28, minBit 1, minWin=26, winSum=431
3562 09:26:05.318388 TX Vref=30, minBit 1, minWin=26, winSum=435
3563 09:26:05.324997 TX Vref=32, minBit 3, minWin=26, winSum=433
3564 09:26:05.328559 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 30
3565 09:26:05.328641
3566 09:26:05.331607 Final TX Range 1 Vref 30
3567 09:26:05.331688
3568 09:26:05.331747 ==
3569 09:26:05.335229 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 09:26:05.338762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 09:26:05.338843 ==
3572 09:26:05.341423
3573 09:26:05.341503
3574 09:26:05.341563 TX Vref Scan disable
3575 09:26:05.345134 == TX Byte 0 ==
3576 09:26:05.348382 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3577 09:26:05.351373 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3578 09:26:05.354982 == TX Byte 1 ==
3579 09:26:05.358585 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3580 09:26:05.361633 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3581 09:26:05.361712
3582 09:26:05.365185 [DATLAT]
3583 09:26:05.365263 Freq=1200, CH1 RK1
3584 09:26:05.365323
3585 09:26:05.368278 DATLAT Default: 0xd
3586 09:26:05.368357 0, 0xFFFF, sum = 0
3587 09:26:05.371793 1, 0xFFFF, sum = 0
3588 09:26:05.371873 2, 0xFFFF, sum = 0
3589 09:26:05.375306 3, 0xFFFF, sum = 0
3590 09:26:05.375386 4, 0xFFFF, sum = 0
3591 09:26:05.378067 5, 0xFFFF, sum = 0
3592 09:26:05.378146 6, 0xFFFF, sum = 0
3593 09:26:05.381547 7, 0xFFFF, sum = 0
3594 09:26:05.384803 8, 0xFFFF, sum = 0
3595 09:26:05.384883 9, 0xFFFF, sum = 0
3596 09:26:05.388317 10, 0xFFFF, sum = 0
3597 09:26:05.388397 11, 0xFFFF, sum = 0
3598 09:26:05.391358 12, 0x0, sum = 1
3599 09:26:05.391438 13, 0x0, sum = 2
3600 09:26:05.395075 14, 0x0, sum = 3
3601 09:26:05.395155 15, 0x0, sum = 4
3602 09:26:05.395216 best_step = 13
3603 09:26:05.395271
3604 09:26:05.398531 ==
3605 09:26:05.398609 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 09:26:05.405109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 09:26:05.405188 ==
3608 09:26:05.405249 RX Vref Scan: 0
3609 09:26:05.405305
3610 09:26:05.408071 RX Vref 0 -> 0, step: 1
3611 09:26:05.408149
3612 09:26:05.411558 RX Delay -21 -> 252, step: 4
3613 09:26:05.415013 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3614 09:26:05.418385 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3615 09:26:05.424882 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3616 09:26:05.428524 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3617 09:26:05.431435 iDelay=191, Bit 4, Center 112 (47 ~ 178) 132
3618 09:26:05.434755 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3619 09:26:05.438137 iDelay=191, Bit 6, Center 118 (51 ~ 186) 136
3620 09:26:05.445147 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3621 09:26:05.448193 iDelay=191, Bit 8, Center 98 (35 ~ 162) 128
3622 09:26:05.452103 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3623 09:26:05.455427 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3624 09:26:05.458173 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3625 09:26:05.465321 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3626 09:26:05.468248 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3627 09:26:05.471598 iDelay=191, Bit 14, Center 116 (51 ~ 182) 132
3628 09:26:05.474894 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3629 09:26:05.474976 ==
3630 09:26:05.478385 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 09:26:05.485096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 09:26:05.485192 ==
3633 09:26:05.485294 DQS Delay:
3634 09:26:05.485349 DQS0 = 0, DQS1 = 0
3635 09:26:05.488361 DQM Delay:
3636 09:26:05.488447 DQM0 = 112, DQM1 = 109
3637 09:26:05.492049 DQ Delay:
3638 09:26:05.495060 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =112
3639 09:26:05.498441 DQ4 =112, DQ5 =124, DQ6 =118, DQ7 =110
3640 09:26:05.502000 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3641 09:26:05.505006 DQ12 =114, DQ13 =120, DQ14 =116, DQ15 =118
3642 09:26:05.505085
3643 09:26:05.505145
3644 09:26:05.511573 [DQSOSCAuto] RK1, (LSB)MR18= 0xf9ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 412 ps
3645 09:26:05.515113 CH1 RK1: MR19=303, MR18=F9FF
3646 09:26:05.521703 CH1_RK1: MR19=0x303, MR18=0xF9FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3647 09:26:05.524983 [RxdqsGatingPostProcess] freq 1200
3648 09:26:05.532059 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3649 09:26:05.535046 best DQS0 dly(2T, 0.5T) = (0, 11)
3650 09:26:05.535125 best DQS1 dly(2T, 0.5T) = (0, 11)
3651 09:26:05.538619 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3652 09:26:05.542117 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3653 09:26:05.545374 best DQS0 dly(2T, 0.5T) = (0, 11)
3654 09:26:05.548636 best DQS1 dly(2T, 0.5T) = (0, 11)
3655 09:26:05.551900 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3656 09:26:05.555483 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3657 09:26:05.558447 Pre-setting of DQS Precalculation
3658 09:26:05.565697 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3659 09:26:05.571901 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3660 09:26:05.578702 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3661 09:26:05.578790
3662 09:26:05.578850
3663 09:26:05.581995 [Calibration Summary] 2400 Mbps
3664 09:26:05.582088 CH 0, Rank 0
3665 09:26:05.585535 SW Impedance : PASS
3666 09:26:05.585613 DUTY Scan : NO K
3667 09:26:05.588544 ZQ Calibration : PASS
3668 09:26:05.592059 Jitter Meter : NO K
3669 09:26:05.592137 CBT Training : PASS
3670 09:26:05.595585 Write leveling : PASS
3671 09:26:05.598529 RX DQS gating : PASS
3672 09:26:05.598608 RX DQ/DQS(RDDQC) : PASS
3673 09:26:05.601886 TX DQ/DQS : PASS
3674 09:26:05.605301 RX DATLAT : PASS
3675 09:26:05.605380 RX DQ/DQS(Engine): PASS
3676 09:26:05.608966 TX OE : NO K
3677 09:26:05.609045 All Pass.
3678 09:26:05.609105
3679 09:26:05.611961 CH 0, Rank 1
3680 09:26:05.612038 SW Impedance : PASS
3681 09:26:05.615460 DUTY Scan : NO K
3682 09:26:05.618579 ZQ Calibration : PASS
3683 09:26:05.618744 Jitter Meter : NO K
3684 09:26:05.621957 CBT Training : PASS
3685 09:26:05.624995 Write leveling : PASS
3686 09:26:05.625091 RX DQS gating : PASS
3687 09:26:05.628563 RX DQ/DQS(RDDQC) : PASS
3688 09:26:05.628643 TX DQ/DQS : PASS
3689 09:26:05.631937 RX DATLAT : PASS
3690 09:26:05.635444 RX DQ/DQS(Engine): PASS
3691 09:26:05.635523 TX OE : NO K
3692 09:26:05.638507 All Pass.
3693 09:26:05.638586
3694 09:26:05.638646 CH 1, Rank 0
3695 09:26:05.642082 SW Impedance : PASS
3696 09:26:05.642184 DUTY Scan : NO K
3697 09:26:05.645578 ZQ Calibration : PASS
3698 09:26:05.648526 Jitter Meter : NO K
3699 09:26:05.648608 CBT Training : PASS
3700 09:26:05.651946 Write leveling : PASS
3701 09:26:05.655314 RX DQS gating : PASS
3702 09:26:05.655396 RX DQ/DQS(RDDQC) : PASS
3703 09:26:05.658576 TX DQ/DQS : PASS
3704 09:26:05.661946 RX DATLAT : PASS
3705 09:26:05.662068 RX DQ/DQS(Engine): PASS
3706 09:26:05.665523 TX OE : NO K
3707 09:26:05.665601 All Pass.
3708 09:26:05.665661
3709 09:26:05.668591 CH 1, Rank 1
3710 09:26:05.668668 SW Impedance : PASS
3711 09:26:05.671922 DUTY Scan : NO K
3712 09:26:05.672000 ZQ Calibration : PASS
3713 09:26:05.675254 Jitter Meter : NO K
3714 09:26:05.678444 CBT Training : PASS
3715 09:26:05.678525 Write leveling : PASS
3716 09:26:05.682254 RX DQS gating : PASS
3717 09:26:05.685404 RX DQ/DQS(RDDQC) : PASS
3718 09:26:05.685484 TX DQ/DQS : PASS
3719 09:26:05.688697 RX DATLAT : PASS
3720 09:26:05.691768 RX DQ/DQS(Engine): PASS
3721 09:26:05.691848 TX OE : NO K
3722 09:26:05.695262 All Pass.
3723 09:26:05.695341
3724 09:26:05.695401 DramC Write-DBI off
3725 09:26:05.698735 PER_BANK_REFRESH: Hybrid Mode
3726 09:26:05.698815 TX_TRACKING: ON
3727 09:26:05.708968 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3728 09:26:05.711762 [FAST_K] Save calibration result to emmc
3729 09:26:05.715052 dramc_set_vcore_voltage set vcore to 650000
3730 09:26:05.718597 Read voltage for 600, 5
3731 09:26:05.718677 Vio18 = 0
3732 09:26:05.722004 Vcore = 650000
3733 09:26:05.722100 Vdram = 0
3734 09:26:05.722160 Vddq = 0
3735 09:26:05.725673 Vmddr = 0
3736 09:26:05.728524 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3737 09:26:05.735554 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3738 09:26:05.735640 MEM_TYPE=3, freq_sel=19
3739 09:26:05.738396 sv_algorithm_assistance_LP4_1600
3740 09:26:05.741914 ============ PULL DRAM RESETB DOWN ============
3741 09:26:05.748579 ========== PULL DRAM RESETB DOWN end =========
3742 09:26:05.751924 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3743 09:26:05.755283 ===================================
3744 09:26:05.758850 LPDDR4 DRAM CONFIGURATION
3745 09:26:05.762338 ===================================
3746 09:26:05.762434 EX_ROW_EN[0] = 0x0
3747 09:26:05.765647 EX_ROW_EN[1] = 0x0
3748 09:26:05.765728 LP4Y_EN = 0x0
3749 09:26:05.768984 WORK_FSP = 0x0
3750 09:26:05.769064 WL = 0x2
3751 09:26:05.771773 RL = 0x2
3752 09:26:05.771850 BL = 0x2
3753 09:26:05.775434 RPST = 0x0
3754 09:26:05.779012 RD_PRE = 0x0
3755 09:26:05.779090 WR_PRE = 0x1
3756 09:26:05.782173 WR_PST = 0x0
3757 09:26:05.782274 DBI_WR = 0x0
3758 09:26:05.785606 DBI_RD = 0x0
3759 09:26:05.785706 OTF = 0x1
3760 09:26:05.789076 ===================================
3761 09:26:05.792127 ===================================
3762 09:26:05.792209 ANA top config
3763 09:26:05.795320 ===================================
3764 09:26:05.798515 DLL_ASYNC_EN = 0
3765 09:26:05.801883 ALL_SLAVE_EN = 1
3766 09:26:05.805522 NEW_RANK_MODE = 1
3767 09:26:05.808558 DLL_IDLE_MODE = 1
3768 09:26:05.808636 LP45_APHY_COMB_EN = 1
3769 09:26:05.812237 TX_ODT_DIS = 1
3770 09:26:05.815147 NEW_8X_MODE = 1
3771 09:26:05.818836 ===================================
3772 09:26:05.822346 ===================================
3773 09:26:05.825662 data_rate = 1200
3774 09:26:05.828843 CKR = 1
3775 09:26:05.828924 DQ_P2S_RATIO = 8
3776 09:26:05.832298 ===================================
3777 09:26:05.835179 CA_P2S_RATIO = 8
3778 09:26:05.838543 DQ_CA_OPEN = 0
3779 09:26:05.841911 DQ_SEMI_OPEN = 0
3780 09:26:05.845434 CA_SEMI_OPEN = 0
3781 09:26:05.848944 CA_FULL_RATE = 0
3782 09:26:05.849025 DQ_CKDIV4_EN = 1
3783 09:26:05.852385 CA_CKDIV4_EN = 1
3784 09:26:05.855345 CA_PREDIV_EN = 0
3785 09:26:05.858719 PH8_DLY = 0
3786 09:26:05.862246 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3787 09:26:05.862331 DQ_AAMCK_DIV = 4
3788 09:26:05.865819 CA_AAMCK_DIV = 4
3789 09:26:05.868856 CA_ADMCK_DIV = 4
3790 09:26:05.872283 DQ_TRACK_CA_EN = 0
3791 09:26:05.875397 CA_PICK = 600
3792 09:26:05.879041 CA_MCKIO = 600
3793 09:26:05.882097 MCKIO_SEMI = 0
3794 09:26:05.882183 PLL_FREQ = 2288
3795 09:26:05.885521 DQ_UI_PI_RATIO = 32
3796 09:26:05.889098 CA_UI_PI_RATIO = 0
3797 09:26:05.892323 ===================================
3798 09:26:05.895372 ===================================
3799 09:26:05.898770 memory_type:LPDDR4
3800 09:26:05.898849 GP_NUM : 10
3801 09:26:05.902173 SRAM_EN : 1
3802 09:26:05.905360 MD32_EN : 0
3803 09:26:05.908811 ===================================
3804 09:26:05.908893 [ANA_INIT] >>>>>>>>>>>>>>
3805 09:26:05.912474 <<<<<< [CONFIGURE PHASE]: ANA_TX
3806 09:26:05.915405 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3807 09:26:05.918951 ===================================
3808 09:26:05.922667 data_rate = 1200,PCW = 0X5800
3809 09:26:05.925524 ===================================
3810 09:26:05.929122 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3811 09:26:05.935544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3812 09:26:05.938936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 09:26:05.945816 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3814 09:26:05.948987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3815 09:26:05.952198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3816 09:26:05.952281 [ANA_INIT] flow start
3817 09:26:05.955679 [ANA_INIT] PLL >>>>>>>>
3818 09:26:05.959154 [ANA_INIT] PLL <<<<<<<<
3819 09:26:05.959245 [ANA_INIT] MIDPI >>>>>>>>
3820 09:26:05.962472 [ANA_INIT] MIDPI <<<<<<<<
3821 09:26:05.965517 [ANA_INIT] DLL >>>>>>>>
3822 09:26:05.965597 [ANA_INIT] flow end
3823 09:26:05.972095 ============ LP4 DIFF to SE enter ============
3824 09:26:05.975606 ============ LP4 DIFF to SE exit ============
3825 09:26:05.979018 [ANA_INIT] <<<<<<<<<<<<<
3826 09:26:05.982277 [Flow] Enable top DCM control >>>>>
3827 09:26:05.985456 [Flow] Enable top DCM control <<<<<
3828 09:26:05.985537 Enable DLL master slave shuffle
3829 09:26:05.992731 ==============================================================
3830 09:26:05.995600 Gating Mode config
3831 09:26:05.999011 ==============================================================
3832 09:26:06.002331 Config description:
3833 09:26:06.012364 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3834 09:26:06.018743 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3835 09:26:06.022257 SELPH_MODE 0: By rank 1: By Phase
3836 09:26:06.028854 ==============================================================
3837 09:26:06.032399 GAT_TRACK_EN = 1
3838 09:26:06.035446 RX_GATING_MODE = 2
3839 09:26:06.039011 RX_GATING_TRACK_MODE = 2
3840 09:26:06.039091 SELPH_MODE = 1
3841 09:26:06.042654 PICG_EARLY_EN = 1
3842 09:26:06.045332 VALID_LAT_VALUE = 1
3843 09:26:06.052242 ==============================================================
3844 09:26:06.055663 Enter into Gating configuration >>>>
3845 09:26:06.059085 Exit from Gating configuration <<<<
3846 09:26:06.061944 Enter into DVFS_PRE_config >>>>>
3847 09:26:06.072259 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3848 09:26:06.075905 Exit from DVFS_PRE_config <<<<<
3849 09:26:06.078983 Enter into PICG configuration >>>>
3850 09:26:06.082143 Exit from PICG configuration <<<<
3851 09:26:06.085725 [RX_INPUT] configuration >>>>>
3852 09:26:06.089074 [RX_INPUT] configuration <<<<<
3853 09:26:06.092229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3854 09:26:06.098880 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3855 09:26:06.105803 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3856 09:26:06.112810 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3857 09:26:06.115854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3858 09:26:06.122162 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3859 09:26:06.125448 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3860 09:26:06.132205 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3861 09:26:06.135724 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3862 09:26:06.139320 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3863 09:26:06.142446 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3864 09:26:06.148868 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3865 09:26:06.152292 ===================================
3866 09:26:06.152375 LPDDR4 DRAM CONFIGURATION
3867 09:26:06.155685 ===================================
3868 09:26:06.159171 EX_ROW_EN[0] = 0x0
3869 09:26:06.162194 EX_ROW_EN[1] = 0x0
3870 09:26:06.162278 LP4Y_EN = 0x0
3871 09:26:06.165796 WORK_FSP = 0x0
3872 09:26:06.165877 WL = 0x2
3873 09:26:06.168961 RL = 0x2
3874 09:26:06.169042 BL = 0x2
3875 09:26:06.172278 RPST = 0x0
3876 09:26:06.172420 RD_PRE = 0x0
3877 09:26:06.175469 WR_PRE = 0x1
3878 09:26:06.175550 WR_PST = 0x0
3879 09:26:06.179141 DBI_WR = 0x0
3880 09:26:06.179221 DBI_RD = 0x0
3881 09:26:06.182367 OTF = 0x1
3882 09:26:06.185824 ===================================
3883 09:26:06.188855 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3884 09:26:06.192399 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3885 09:26:06.199156 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3886 09:26:06.202511 ===================================
3887 09:26:06.202619 LPDDR4 DRAM CONFIGURATION
3888 09:26:06.205989 ===================================
3889 09:26:06.209035 EX_ROW_EN[0] = 0x10
3890 09:26:06.209115 EX_ROW_EN[1] = 0x0
3891 09:26:06.212474 LP4Y_EN = 0x0
3892 09:26:06.212555 WORK_FSP = 0x0
3893 09:26:06.215790 WL = 0x2
3894 09:26:06.215869 RL = 0x2
3895 09:26:06.219243 BL = 0x2
3896 09:26:06.222269 RPST = 0x0
3897 09:26:06.222349 RD_PRE = 0x0
3898 09:26:06.225825 WR_PRE = 0x1
3899 09:26:06.225904 WR_PST = 0x0
3900 09:26:06.229410 DBI_WR = 0x0
3901 09:26:06.229489 DBI_RD = 0x0
3902 09:26:06.232395 OTF = 0x1
3903 09:26:06.235666 ===================================
3904 09:26:06.239284 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3905 09:26:06.244427 nWR fixed to 30
3906 09:26:06.247995 [ModeRegInit_LP4] CH0 RK0
3907 09:26:06.248078 [ModeRegInit_LP4] CH0 RK1
3908 09:26:06.250971 [ModeRegInit_LP4] CH1 RK0
3909 09:26:06.254701 [ModeRegInit_LP4] CH1 RK1
3910 09:26:06.254780 match AC timing 17
3911 09:26:06.261171 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3912 09:26:06.264636 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3913 09:26:06.267793 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3914 09:26:06.274364 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3915 09:26:06.277712 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3916 09:26:06.277815 ==
3917 09:26:06.281209 Dram Type= 6, Freq= 0, CH_0, rank 0
3918 09:26:06.284522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3919 09:26:06.284604 ==
3920 09:26:06.291008 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3921 09:26:06.297774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3922 09:26:06.301330 [CA 0] Center 36 (6~66) winsize 61
3923 09:26:06.304740 [CA 1] Center 35 (5~66) winsize 62
3924 09:26:06.307974 [CA 2] Center 34 (4~65) winsize 62
3925 09:26:06.311336 [CA 3] Center 34 (4~65) winsize 62
3926 09:26:06.314295 [CA 4] Center 33 (3~64) winsize 62
3927 09:26:06.317721 [CA 5] Center 33 (3~64) winsize 62
3928 09:26:06.317800
3929 09:26:06.321280 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3930 09:26:06.321361
3931 09:26:06.324598 [CATrainingPosCal] consider 1 rank data
3932 09:26:06.328342 u2DelayCellTimex100 = 270/100 ps
3933 09:26:06.331161 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3934 09:26:06.334816 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3935 09:26:06.338272 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3936 09:26:06.341273 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 09:26:06.344713 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3938 09:26:06.348005 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3939 09:26:06.348087
3940 09:26:06.354732 CA PerBit enable=1, Macro0, CA PI delay=33
3941 09:26:06.354825
3942 09:26:06.354888 [CBTSetCACLKResult] CA Dly = 33
3943 09:26:06.358130 CS Dly: 3 (0~34)
3944 09:26:06.358261 ==
3945 09:26:06.361257 Dram Type= 6, Freq= 0, CH_0, rank 1
3946 09:26:06.364550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3947 09:26:06.364678 ==
3948 09:26:06.371200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3949 09:26:06.377802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3950 09:26:06.381437 [CA 0] Center 36 (6~66) winsize 61
3951 09:26:06.384759 [CA 1] Center 36 (6~66) winsize 61
3952 09:26:06.388433 [CA 2] Center 34 (4~65) winsize 62
3953 09:26:06.391313 [CA 3] Center 34 (4~65) winsize 62
3954 09:26:06.394617 [CA 4] Center 33 (3~64) winsize 62
3955 09:26:06.397910 [CA 5] Center 33 (3~64) winsize 62
3956 09:26:06.398076
3957 09:26:06.401107 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3958 09:26:06.401234
3959 09:26:06.404469 [CATrainingPosCal] consider 2 rank data
3960 09:26:06.407970 u2DelayCellTimex100 = 270/100 ps
3961 09:26:06.411411 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3962 09:26:06.414784 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3963 09:26:06.418104 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3964 09:26:06.421111 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3965 09:26:06.424612 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3966 09:26:06.428221 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 09:26:06.428342
3968 09:26:06.435013 CA PerBit enable=1, Macro0, CA PI delay=33
3969 09:26:06.435146
3970 09:26:06.435261 [CBTSetCACLKResult] CA Dly = 33
3971 09:26:06.438088 CS Dly: 4 (0~37)
3972 09:26:06.438209
3973 09:26:06.441620 ----->DramcWriteLeveling(PI) begin...
3974 09:26:06.441746 ==
3975 09:26:06.444634 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 09:26:06.448254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 09:26:06.448382 ==
3978 09:26:06.451261 Write leveling (Byte 0): 32 => 32
3979 09:26:06.454600 Write leveling (Byte 1): 32 => 32
3980 09:26:06.457929 DramcWriteLeveling(PI) end<-----
3981 09:26:06.458081
3982 09:26:06.458227 ==
3983 09:26:06.461515 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 09:26:06.464621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 09:26:06.464752 ==
3986 09:26:06.468158 [Gating] SW mode calibration
3987 09:26:06.474768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3988 09:26:06.481242 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3989 09:26:06.484752 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 09:26:06.491627 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 09:26:06.494769 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 09:26:06.498171 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 09:26:06.504541 0 9 16 | B1->B0 | 3232 2b2b | 0 0 | (0 1) (0 0)
3994 09:26:06.507907 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3995 09:26:06.511173 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 09:26:06.514642 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 09:26:06.521547 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 09:26:06.524740 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 09:26:06.528212 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 09:26:06.534763 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4001 09:26:06.538230 0 10 16 | B1->B0 | 2f2f 3c3c | 0 0 | (0 0) (0 0)
4002 09:26:06.541642 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 09:26:06.548170 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 09:26:06.551095 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 09:26:06.554689 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 09:26:06.561430 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 09:26:06.564683 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 09:26:06.567922 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 09:26:06.575062 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4010 09:26:06.578254 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4011 09:26:06.581618 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 09:26:06.588077 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 09:26:06.591573 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 09:26:06.595189 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 09:26:06.598455 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 09:26:06.605030 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 09:26:06.608038 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 09:26:06.611364 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 09:26:06.618100 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 09:26:06.621501 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 09:26:06.625086 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 09:26:06.631465 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 09:26:06.634597 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 09:26:06.638263 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 09:26:06.644712 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4026 09:26:06.648130 Total UI for P1: 0, mck2ui 16
4027 09:26:06.651567 best dqsien dly found for B1: ( 0, 13, 14)
4028 09:26:06.654544 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4029 09:26:06.658187 Total UI for P1: 0, mck2ui 16
4030 09:26:06.661770 best dqsien dly found for B0: ( 0, 13, 16)
4031 09:26:06.664714 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4032 09:26:06.668262 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4033 09:26:06.668343
4034 09:26:06.671697 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4035 09:26:06.674999 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4036 09:26:06.678320 [Gating] SW calibration Done
4037 09:26:06.678425 ==
4038 09:26:06.681316 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 09:26:06.684743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 09:26:06.688045 ==
4041 09:26:06.688126 RX Vref Scan: 0
4042 09:26:06.688187
4043 09:26:06.691657 RX Vref 0 -> 0, step: 1
4044 09:26:06.691737
4045 09:26:06.695019 RX Delay -230 -> 252, step: 16
4046 09:26:06.698311 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4047 09:26:06.701714 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4048 09:26:06.704690 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4049 09:26:06.708297 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4050 09:26:06.714821 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4051 09:26:06.718272 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4052 09:26:06.721612 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4053 09:26:06.725077 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4054 09:26:06.731381 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4055 09:26:06.734948 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4056 09:26:06.738263 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4057 09:26:06.741564 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4058 09:26:06.745134 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4059 09:26:06.751576 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4060 09:26:06.754922 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4061 09:26:06.758299 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4062 09:26:06.758379 ==
4063 09:26:06.761944 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 09:26:06.764826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 09:26:06.768489 ==
4066 09:26:06.768569 DQS Delay:
4067 09:26:06.768629 DQS0 = 0, DQS1 = 0
4068 09:26:06.771381 DQM Delay:
4069 09:26:06.771459 DQM0 = 40, DQM1 = 31
4070 09:26:06.774927 DQ Delay:
4071 09:26:06.778347 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4072 09:26:06.778426 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4073 09:26:06.781549 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4074 09:26:06.785089 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4075 09:26:06.785174
4076 09:26:06.788598
4077 09:26:06.788675 ==
4078 09:26:06.791591 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 09:26:06.795141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 09:26:06.795254 ==
4081 09:26:06.795317
4082 09:26:06.795371
4083 09:26:06.798085 TX Vref Scan disable
4084 09:26:06.798163 == TX Byte 0 ==
4085 09:26:06.805089 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4086 09:26:06.808422 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4087 09:26:06.808502 == TX Byte 1 ==
4088 09:26:06.815274 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4089 09:26:06.818276 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4090 09:26:06.818360 ==
4091 09:26:06.821893 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 09:26:06.824776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 09:26:06.824858 ==
4094 09:26:06.824917
4095 09:26:06.824972
4096 09:26:06.828058 TX Vref Scan disable
4097 09:26:06.831436 == TX Byte 0 ==
4098 09:26:06.834970 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4099 09:26:06.838471 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4100 09:26:06.841895 == TX Byte 1 ==
4101 09:26:06.845409 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4102 09:26:06.848771 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4103 09:26:06.848853
4104 09:26:06.852229 [DATLAT]
4105 09:26:06.852309 Freq=600, CH0 RK0
4106 09:26:06.852369
4107 09:26:06.855060 DATLAT Default: 0x9
4108 09:26:06.855139 0, 0xFFFF, sum = 0
4109 09:26:06.858640 1, 0xFFFF, sum = 0
4110 09:26:06.858720 2, 0xFFFF, sum = 0
4111 09:26:06.861569 3, 0xFFFF, sum = 0
4112 09:26:06.861653 4, 0xFFFF, sum = 0
4113 09:26:06.864964 5, 0xFFFF, sum = 0
4114 09:26:06.865044 6, 0xFFFF, sum = 0
4115 09:26:06.868480 7, 0xFFFF, sum = 0
4116 09:26:06.868561 8, 0x0, sum = 1
4117 09:26:06.872104 9, 0x0, sum = 2
4118 09:26:06.872184 10, 0x0, sum = 3
4119 09:26:06.875003 11, 0x0, sum = 4
4120 09:26:06.875082 best_step = 9
4121 09:26:06.875143
4122 09:26:06.875199 ==
4123 09:26:06.878754 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 09:26:06.881600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 09:26:06.881680 ==
4126 09:26:06.885063 RX Vref Scan: 1
4127 09:26:06.885140
4128 09:26:06.888199 RX Vref 0 -> 0, step: 1
4129 09:26:06.888278
4130 09:26:06.888338 RX Delay -195 -> 252, step: 8
4131 09:26:06.891567
4132 09:26:06.891645 Set Vref, RX VrefLevel [Byte0]: 54
4133 09:26:06.895190 [Byte1]: 52
4134 09:26:06.900082
4135 09:26:06.900166 Final RX Vref Byte 0 = 54 to rank0
4136 09:26:06.903083 Final RX Vref Byte 1 = 52 to rank0
4137 09:26:06.906657 Final RX Vref Byte 0 = 54 to rank1
4138 09:26:06.909661 Final RX Vref Byte 1 = 52 to rank1==
4139 09:26:06.913276 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 09:26:06.920107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 09:26:06.920196 ==
4142 09:26:06.920257 DQS Delay:
4143 09:26:06.920313 DQS0 = 0, DQS1 = 0
4144 09:26:06.922975 DQM Delay:
4145 09:26:06.923055 DQM0 = 41, DQM1 = 33
4146 09:26:06.926657 DQ Delay:
4147 09:26:06.929906 DQ0 =40, DQ1 =40, DQ2 =40, DQ3 =40
4148 09:26:06.930010 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4149 09:26:06.933301 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4150 09:26:06.936668 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4151 09:26:06.939758
4152 09:26:06.939839
4153 09:26:06.946340 [DQSOSCAuto] RK0, (LSB)MR18= 0x4523, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 396 ps
4154 09:26:06.949949 CH0 RK0: MR19=808, MR18=4523
4155 09:26:06.956289 CH0_RK0: MR19=0x808, MR18=0x4523, DQSOSC=396, MR23=63, INC=167, DEC=111
4156 09:26:06.956373
4157 09:26:06.959575 ----->DramcWriteLeveling(PI) begin...
4158 09:26:06.959712 ==
4159 09:26:06.963239 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 09:26:06.966681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 09:26:06.966762 ==
4162 09:26:06.969771 Write leveling (Byte 0): 32 => 32
4163 09:26:06.972953 Write leveling (Byte 1): 30 => 30
4164 09:26:06.976469 DramcWriteLeveling(PI) end<-----
4165 09:26:06.976559
4166 09:26:06.976619 ==
4167 09:26:06.980122 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 09:26:06.983033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 09:26:06.983113 ==
4170 09:26:06.986659 [Gating] SW mode calibration
4171 09:26:06.993514 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4172 09:26:07.000163 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4173 09:26:07.003274 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 09:26:07.006863 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 09:26:07.013495 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4176 09:26:07.016499 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 1)
4177 09:26:07.020115 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
4178 09:26:07.026581 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 09:26:07.030275 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 09:26:07.033174 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 09:26:07.040206 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 09:26:07.043335 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 09:26:07.046905 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 09:26:07.053428 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4185 09:26:07.056929 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4186 09:26:07.060111 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 09:26:07.063247 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 09:26:07.070292 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 09:26:07.073296 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 09:26:07.076761 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 09:26:07.083619 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 09:26:07.086642 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4193 09:26:07.090114 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4194 09:26:07.096811 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4195 09:26:07.100257 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 09:26:07.103474 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 09:26:07.110508 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 09:26:07.113372 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 09:26:07.116950 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 09:26:07.123463 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 09:26:07.126975 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 09:26:07.130475 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 09:26:07.133790 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 09:26:07.140737 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 09:26:07.143724 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 09:26:07.147312 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 09:26:07.153905 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 09:26:07.157316 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 09:26:07.160071 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4210 09:26:07.164010 Total UI for P1: 0, mck2ui 16
4211 09:26:07.166837 best dqsien dly found for B1: ( 0, 13, 14)
4212 09:26:07.173856 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 09:26:07.174087 Total UI for P1: 0, mck2ui 16
4214 09:26:07.180494 best dqsien dly found for B0: ( 0, 13, 16)
4215 09:26:07.183713 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4216 09:26:07.187103 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4217 09:26:07.187269
4218 09:26:07.190394 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4219 09:26:07.193472 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4220 09:26:07.197034 [Gating] SW calibration Done
4221 09:26:07.197158 ==
4222 09:26:07.199979 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 09:26:07.203548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 09:26:07.203704 ==
4225 09:26:07.206986 RX Vref Scan: 0
4226 09:26:07.207136
4227 09:26:07.207269 RX Vref 0 -> 0, step: 1
4228 09:26:07.207393
4229 09:26:07.210385 RX Delay -230 -> 252, step: 16
4230 09:26:07.217241 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4231 09:26:07.220202 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4232 09:26:07.223756 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4233 09:26:07.226825 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4234 09:26:07.230447 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4235 09:26:07.236931 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4236 09:26:07.240345 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4237 09:26:07.243482 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4238 09:26:07.247180 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4239 09:26:07.253583 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4240 09:26:07.256619 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4241 09:26:07.260094 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4242 09:26:07.263734 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4243 09:26:07.270248 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4244 09:26:07.273044 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4245 09:26:07.276529 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4246 09:26:07.276638 ==
4247 09:26:07.280154 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 09:26:07.283686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 09:26:07.283784 ==
4250 09:26:07.286757 DQS Delay:
4251 09:26:07.286894 DQS0 = 0, DQS1 = 0
4252 09:26:07.290174 DQM Delay:
4253 09:26:07.290311 DQM0 = 39, DQM1 = 31
4254 09:26:07.290389 DQ Delay:
4255 09:26:07.293412 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4256 09:26:07.297039 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4257 09:26:07.300053 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4258 09:26:07.303562 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4259 09:26:07.303658
4260 09:26:07.303717
4261 09:26:07.303772 ==
4262 09:26:07.307088 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 09:26:07.313422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 09:26:07.313554 ==
4265 09:26:07.313641
4266 09:26:07.313722
4267 09:26:07.313801 TX Vref Scan disable
4268 09:26:07.317247 == TX Byte 0 ==
4269 09:26:07.320817 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4270 09:26:07.323879 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4271 09:26:07.327398 == TX Byte 1 ==
4272 09:26:07.330357 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4273 09:26:07.334115 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4274 09:26:07.337618 ==
4275 09:26:07.340681 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 09:26:07.344003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 09:26:07.344085 ==
4278 09:26:07.344170
4279 09:26:07.344227
4280 09:26:07.347307 TX Vref Scan disable
4281 09:26:07.347427 == TX Byte 0 ==
4282 09:26:07.354369 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4283 09:26:07.357435 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4284 09:26:07.357524 == TX Byte 1 ==
4285 09:26:07.363908 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4286 09:26:07.367586 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4287 09:26:07.367692
4288 09:26:07.367779 [DATLAT]
4289 09:26:07.370492 Freq=600, CH0 RK1
4290 09:26:07.370579
4291 09:26:07.370640 DATLAT Default: 0x9
4292 09:26:07.373855 0, 0xFFFF, sum = 0
4293 09:26:07.373968 1, 0xFFFF, sum = 0
4294 09:26:07.377351 2, 0xFFFF, sum = 0
4295 09:26:07.377444 3, 0xFFFF, sum = 0
4296 09:26:07.380916 4, 0xFFFF, sum = 0
4297 09:26:07.380998 5, 0xFFFF, sum = 0
4298 09:26:07.384299 6, 0xFFFF, sum = 0
4299 09:26:07.387400 7, 0xFFFF, sum = 0
4300 09:26:07.387482 8, 0x0, sum = 1
4301 09:26:07.387544 9, 0x0, sum = 2
4302 09:26:07.390806 10, 0x0, sum = 3
4303 09:26:07.390889 11, 0x0, sum = 4
4304 09:26:07.394145 best_step = 9
4305 09:26:07.394225
4306 09:26:07.394286 ==
4307 09:26:07.397405 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 09:26:07.400952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 09:26:07.401035 ==
4310 09:26:07.403815 RX Vref Scan: 0
4311 09:26:07.403898
4312 09:26:07.403958 RX Vref 0 -> 0, step: 1
4313 09:26:07.404015
4314 09:26:07.407247 RX Delay -195 -> 252, step: 8
4315 09:26:07.414443 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4316 09:26:07.417534 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4317 09:26:07.421400 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4318 09:26:07.424599 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4319 09:26:07.431376 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4320 09:26:07.434340 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4321 09:26:07.437811 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4322 09:26:07.440821 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4323 09:26:07.444351 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4324 09:26:07.451572 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4325 09:26:07.454725 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4326 09:26:07.458148 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4327 09:26:07.460905 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4328 09:26:07.468048 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4329 09:26:07.471025 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4330 09:26:07.474663 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4331 09:26:07.474755 ==
4332 09:26:07.478109 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 09:26:07.481098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 09:26:07.481181 ==
4335 09:26:07.484741 DQS Delay:
4336 09:26:07.484821 DQS0 = 0, DQS1 = 0
4337 09:26:07.488141 DQM Delay:
4338 09:26:07.488221 DQM0 = 39, DQM1 = 32
4339 09:26:07.488280 DQ Delay:
4340 09:26:07.491591 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4341 09:26:07.494624 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4342 09:26:07.498233 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =20
4343 09:26:07.501554 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =44
4344 09:26:07.501675
4345 09:26:07.501734
4346 09:26:07.511534 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4347 09:26:07.514472 CH0 RK1: MR19=808, MR18=4D30
4348 09:26:07.517995 CH0_RK1: MR19=0x808, MR18=0x4D30, DQSOSC=395, MR23=63, INC=168, DEC=112
4349 09:26:07.521587 [RxdqsGatingPostProcess] freq 600
4350 09:26:07.528264 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4351 09:26:07.531363 Pre-setting of DQS Precalculation
4352 09:26:07.534548 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4353 09:26:07.534646 ==
4354 09:26:07.537951 Dram Type= 6, Freq= 0, CH_1, rank 0
4355 09:26:07.544379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 09:26:07.544477 ==
4357 09:26:07.547950 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4358 09:26:07.554521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4359 09:26:07.557880 [CA 0] Center 35 (5~65) winsize 61
4360 09:26:07.561488 [CA 1] Center 35 (5~66) winsize 62
4361 09:26:07.564741 [CA 2] Center 34 (4~64) winsize 61
4362 09:26:07.568227 [CA 3] Center 33 (3~64) winsize 62
4363 09:26:07.571247 [CA 4] Center 34 (3~65) winsize 63
4364 09:26:07.574873 [CA 5] Center 33 (2~64) winsize 63
4365 09:26:07.574951
4366 09:26:07.577977 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4367 09:26:07.578096
4368 09:26:07.581473 [CATrainingPosCal] consider 1 rank data
4369 09:26:07.584936 u2DelayCellTimex100 = 270/100 ps
4370 09:26:07.587810 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4371 09:26:07.591442 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4372 09:26:07.598201 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4373 09:26:07.601223 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4374 09:26:07.604793 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4375 09:26:07.608241 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4376 09:26:07.608320
4377 09:26:07.611036 CA PerBit enable=1, Macro0, CA PI delay=33
4378 09:26:07.611116
4379 09:26:07.614592 [CBTSetCACLKResult] CA Dly = 33
4380 09:26:07.614674 CS Dly: 4 (0~35)
4381 09:26:07.614735 ==
4382 09:26:07.617669 Dram Type= 6, Freq= 0, CH_1, rank 1
4383 09:26:07.624517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 09:26:07.624611 ==
4385 09:26:07.628058 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4386 09:26:07.634549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4387 09:26:07.637820 [CA 0] Center 35 (5~66) winsize 62
4388 09:26:07.641451 [CA 1] Center 36 (6~66) winsize 61
4389 09:26:07.644730 [CA 2] Center 34 (4~65) winsize 62
4390 09:26:07.647930 [CA 3] Center 33 (3~64) winsize 62
4391 09:26:07.651502 [CA 4] Center 34 (3~65) winsize 63
4392 09:26:07.655145 [CA 5] Center 33 (3~64) winsize 62
4393 09:26:07.655223
4394 09:26:07.657985 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4395 09:26:07.658096
4396 09:26:07.661620 [CATrainingPosCal] consider 2 rank data
4397 09:26:07.665053 u2DelayCellTimex100 = 270/100 ps
4398 09:26:07.667865 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4399 09:26:07.671605 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4400 09:26:07.678309 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4401 09:26:07.681909 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4402 09:26:07.684739 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4403 09:26:07.688138 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4404 09:26:07.688216
4405 09:26:07.691754 CA PerBit enable=1, Macro0, CA PI delay=33
4406 09:26:07.691832
4407 09:26:07.694676 [CBTSetCACLKResult] CA Dly = 33
4408 09:26:07.694753 CS Dly: 4 (0~36)
4409 09:26:07.694812
4410 09:26:07.698259 ----->DramcWriteLeveling(PI) begin...
4411 09:26:07.701508 ==
4412 09:26:07.701586 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 09:26:07.708266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 09:26:07.708345 ==
4415 09:26:07.711746 Write leveling (Byte 0): 28 => 28
4416 09:26:07.714761 Write leveling (Byte 1): 30 => 30
4417 09:26:07.714838 DramcWriteLeveling(PI) end<-----
4418 09:26:07.718249
4419 09:26:07.718326 ==
4420 09:26:07.721742 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 09:26:07.724821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 09:26:07.724899 ==
4423 09:26:07.728070 [Gating] SW mode calibration
4424 09:26:07.735193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4425 09:26:07.738138 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4426 09:26:07.744866 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 09:26:07.748303 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 09:26:07.751870 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4429 09:26:07.758157 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (0 0) (1 0)
4430 09:26:07.761823 0 9 16 | B1->B0 | 2e2e 2424 | 0 0 | (1 1) (0 0)
4431 09:26:07.764901 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 09:26:07.771689 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 09:26:07.775312 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 09:26:07.778552 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 09:26:07.784731 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 09:26:07.788129 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 09:26:07.791653 0 10 12 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
4438 09:26:07.798173 0 10 16 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
4439 09:26:07.801689 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 09:26:07.805171 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 09:26:07.807997 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 09:26:07.814707 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 09:26:07.818178 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 09:26:07.821752 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 09:26:07.828537 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4446 09:26:07.831684 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4447 09:26:07.834895 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 09:26:07.841850 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 09:26:07.845261 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 09:26:07.848143 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 09:26:07.855073 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 09:26:07.858614 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 09:26:07.861537 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 09:26:07.868295 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 09:26:07.871807 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 09:26:07.874870 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 09:26:07.881840 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 09:26:07.885230 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 09:26:07.888649 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 09:26:07.891354 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 09:26:07.898354 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4462 09:26:07.901696 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 09:26:07.905303 Total UI for P1: 0, mck2ui 16
4464 09:26:07.908411 best dqsien dly found for B0: ( 0, 13, 12)
4465 09:26:07.911876 Total UI for P1: 0, mck2ui 16
4466 09:26:07.915286 best dqsien dly found for B1: ( 0, 13, 12)
4467 09:26:07.918234 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4468 09:26:07.921958 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4469 09:26:07.922064
4470 09:26:07.924909 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4471 09:26:07.928492 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4472 09:26:07.931725 [Gating] SW calibration Done
4473 09:26:07.931804 ==
4474 09:26:07.935299 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 09:26:07.941645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 09:26:07.941750 ==
4477 09:26:07.941836 RX Vref Scan: 0
4478 09:26:07.941917
4479 09:26:07.945101 RX Vref 0 -> 0, step: 1
4480 09:26:07.945179
4481 09:26:07.948634 RX Delay -230 -> 252, step: 16
4482 09:26:07.951723 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4483 09:26:07.955428 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4484 09:26:07.958574 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4485 09:26:07.964957 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4486 09:26:07.968617 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4487 09:26:07.971573 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4488 09:26:07.975111 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4489 09:26:07.978571 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4490 09:26:07.985158 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4491 09:26:07.988673 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4492 09:26:07.991664 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4493 09:26:07.995150 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4494 09:26:08.001734 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4495 09:26:08.005535 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4496 09:26:08.008518 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4497 09:26:08.011867 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4498 09:26:08.011944 ==
4499 09:26:08.015260 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 09:26:08.021934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 09:26:08.022066 ==
4502 09:26:08.022127 DQS Delay:
4503 09:26:08.025140 DQS0 = 0, DQS1 = 0
4504 09:26:08.025217 DQM Delay:
4505 09:26:08.025277 DQM0 = 43, DQM1 = 33
4506 09:26:08.028581 DQ Delay:
4507 09:26:08.031800 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4508 09:26:08.035006 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4509 09:26:08.038553 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4510 09:26:08.041925 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =33
4511 09:26:08.042040
4512 09:26:08.042101
4513 09:26:08.042155 ==
4514 09:26:08.045426 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 09:26:08.048285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 09:26:08.048362 ==
4517 09:26:08.048421
4518 09:26:08.048476
4519 09:26:08.051805 TX Vref Scan disable
4520 09:26:08.051882 == TX Byte 0 ==
4521 09:26:08.058443 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4522 09:26:08.061958 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4523 09:26:08.062090 == TX Byte 1 ==
4524 09:26:08.068857 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4525 09:26:08.071800 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4526 09:26:08.071894 ==
4527 09:26:08.075262 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 09:26:08.078614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 09:26:08.078695 ==
4530 09:26:08.078755
4531 09:26:08.078809
4532 09:26:08.082196 TX Vref Scan disable
4533 09:26:08.085012 == TX Byte 0 ==
4534 09:26:08.088461 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4535 09:26:08.091834 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4536 09:26:08.095435 == TX Byte 1 ==
4537 09:26:08.098399 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4538 09:26:08.102064 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4539 09:26:08.102145
4540 09:26:08.105480 [DATLAT]
4541 09:26:08.105558 Freq=600, CH1 RK0
4542 09:26:08.105620
4543 09:26:08.108546 DATLAT Default: 0x9
4544 09:26:08.108624 0, 0xFFFF, sum = 0
4545 09:26:08.111998 1, 0xFFFF, sum = 0
4546 09:26:08.112077 2, 0xFFFF, sum = 0
4547 09:26:08.115469 3, 0xFFFF, sum = 0
4548 09:26:08.115548 4, 0xFFFF, sum = 0
4549 09:26:08.119041 5, 0xFFFF, sum = 0
4550 09:26:08.119119 6, 0xFFFF, sum = 0
4551 09:26:08.122184 7, 0xFFFF, sum = 0
4552 09:26:08.122263 8, 0x0, sum = 1
4553 09:26:08.125207 9, 0x0, sum = 2
4554 09:26:08.125287 10, 0x0, sum = 3
4555 09:26:08.128566 11, 0x0, sum = 4
4556 09:26:08.128647 best_step = 9
4557 09:26:08.128707
4558 09:26:08.128762 ==
4559 09:26:08.131712 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 09:26:08.135405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 09:26:08.138687 ==
4562 09:26:08.138767 RX Vref Scan: 1
4563 09:26:08.138827
4564 09:26:08.141957 RX Vref 0 -> 0, step: 1
4565 09:26:08.142075
4566 09:26:08.145419 RX Delay -179 -> 252, step: 8
4567 09:26:08.145551
4568 09:26:08.149029 Set Vref, RX VrefLevel [Byte0]: 60
4569 09:26:08.151914 [Byte1]: 53
4570 09:26:08.152006
4571 09:26:08.155357 Final RX Vref Byte 0 = 60 to rank0
4572 09:26:08.159006 Final RX Vref Byte 1 = 53 to rank0
4573 09:26:08.161972 Final RX Vref Byte 0 = 60 to rank1
4574 09:26:08.165477 Final RX Vref Byte 1 = 53 to rank1==
4575 09:26:08.168479 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 09:26:08.171861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 09:26:08.171957 ==
4578 09:26:08.172019 DQS Delay:
4579 09:26:08.175346 DQS0 = 0, DQS1 = 0
4580 09:26:08.175424 DQM Delay:
4581 09:26:08.178755 DQM0 = 40, DQM1 = 33
4582 09:26:08.178834 DQ Delay:
4583 09:26:08.182257 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4584 09:26:08.185203 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4585 09:26:08.188733 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4586 09:26:08.191850 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4587 09:26:08.191932
4588 09:26:08.191991
4589 09:26:08.202425 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b0f, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 395 ps
4590 09:26:08.202538 CH1 RK0: MR19=808, MR18=4B0F
4591 09:26:08.209001 CH1_RK0: MR19=0x808, MR18=0x4B0F, DQSOSC=395, MR23=63, INC=168, DEC=112
4592 09:26:08.209097
4593 09:26:08.212175 ----->DramcWriteLeveling(PI) begin...
4594 09:26:08.212260 ==
4595 09:26:08.215101 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 09:26:08.221939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 09:26:08.222097 ==
4598 09:26:08.225659 Write leveling (Byte 0): 29 => 29
4599 09:26:08.228639 Write leveling (Byte 1): 29 => 29
4600 09:26:08.228725 DramcWriteLeveling(PI) end<-----
4601 09:26:08.228785
4602 09:26:08.232304 ==
4603 09:26:08.232399 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 09:26:08.238545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 09:26:08.238650 ==
4606 09:26:08.241662 [Gating] SW mode calibration
4607 09:26:08.248477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4608 09:26:08.252203 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4609 09:26:08.258704 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 09:26:08.262004 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 09:26:08.265348 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4612 09:26:08.272142 0 9 12 | B1->B0 | 2f2f 2a2a | 0 0 | (0 1) (0 0)
4613 09:26:08.275854 0 9 16 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
4614 09:26:08.279006 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4615 09:26:08.282454 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 09:26:08.289028 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 09:26:08.292020 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 09:26:08.295461 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4619 09:26:08.301924 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4620 09:26:08.305494 0 10 12 | B1->B0 | 3030 3e3e | 0 0 | (0 0) (1 1)
4621 09:26:08.308591 0 10 16 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
4622 09:26:08.315821 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 09:26:08.318748 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 09:26:08.321908 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 09:26:08.329269 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 09:26:08.332285 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 09:26:08.335952 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4628 09:26:08.342157 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4629 09:26:08.345773 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4630 09:26:08.348913 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 09:26:08.355911 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 09:26:08.359179 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 09:26:08.362448 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 09:26:08.365573 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 09:26:08.372559 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 09:26:08.375942 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 09:26:08.378878 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 09:26:08.385461 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 09:26:08.388665 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 09:26:08.392121 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 09:26:08.398597 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 09:26:08.402126 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 09:26:08.405690 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4644 09:26:08.412102 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4645 09:26:08.415607 Total UI for P1: 0, mck2ui 16
4646 09:26:08.418812 best dqsien dly found for B0: ( 0, 13, 8)
4647 09:26:08.421864 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 09:26:08.425471 Total UI for P1: 0, mck2ui 16
4649 09:26:08.428672 best dqsien dly found for B1: ( 0, 13, 14)
4650 09:26:08.431668 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4651 09:26:08.435396 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4652 09:26:08.435474
4653 09:26:08.438917 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4654 09:26:08.441931 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4655 09:26:08.445594 [Gating] SW calibration Done
4656 09:26:08.445672 ==
4657 09:26:08.448593 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 09:26:08.452184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 09:26:08.455251 ==
4660 09:26:08.455329 RX Vref Scan: 0
4661 09:26:08.455389
4662 09:26:08.458161 RX Vref 0 -> 0, step: 1
4663 09:26:08.458242
4664 09:26:08.461773 RX Delay -230 -> 252, step: 16
4665 09:26:08.465339 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4666 09:26:08.468529 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4667 09:26:08.471575 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4668 09:26:08.478420 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4669 09:26:08.481499 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4670 09:26:08.485157 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4671 09:26:08.488621 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4672 09:26:08.491798 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4673 09:26:08.498284 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4674 09:26:08.501506 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4675 09:26:08.504776 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4676 09:26:08.508444 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4677 09:26:08.515124 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4678 09:26:08.518140 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4679 09:26:08.521954 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4680 09:26:08.524724 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4681 09:26:08.524813 ==
4682 09:26:08.528446 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 09:26:08.535028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 09:26:08.535137 ==
4685 09:26:08.535198 DQS Delay:
4686 09:26:08.538554 DQS0 = 0, DQS1 = 0
4687 09:26:08.538632 DQM Delay:
4688 09:26:08.538691 DQM0 = 41, DQM1 = 35
4689 09:26:08.541609 DQ Delay:
4690 09:26:08.544685 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4691 09:26:08.548340 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4692 09:26:08.551370 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4693 09:26:08.554940 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4694 09:26:08.555027
4695 09:26:08.555088
4696 09:26:08.555142 ==
4697 09:26:08.558110 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 09:26:08.561722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 09:26:08.561831 ==
4700 09:26:08.561917
4701 09:26:08.562008
4702 09:26:08.564692 TX Vref Scan disable
4703 09:26:08.568239 == TX Byte 0 ==
4704 09:26:08.571724 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4705 09:26:08.574748 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4706 09:26:08.578328 == TX Byte 1 ==
4707 09:26:08.581376 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4708 09:26:08.584986 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4709 09:26:08.585064 ==
4710 09:26:08.588115 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 09:26:08.591540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 09:26:08.591622 ==
4713 09:26:08.594551
4714 09:26:08.594629
4715 09:26:08.594688 TX Vref Scan disable
4716 09:26:08.598537 == TX Byte 0 ==
4717 09:26:08.601883 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4718 09:26:08.604948 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4719 09:26:08.608343 == TX Byte 1 ==
4720 09:26:08.611419 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4721 09:26:08.614907 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4722 09:26:08.618596
4723 09:26:08.618676 [DATLAT]
4724 09:26:08.618755 Freq=600, CH1 RK1
4725 09:26:08.618828
4726 09:26:08.621699 DATLAT Default: 0x9
4727 09:26:08.621778 0, 0xFFFF, sum = 0
4728 09:26:08.625351 1, 0xFFFF, sum = 0
4729 09:26:08.625436 2, 0xFFFF, sum = 0
4730 09:26:08.628442 3, 0xFFFF, sum = 0
4731 09:26:08.628581 4, 0xFFFF, sum = 0
4732 09:26:08.631820 5, 0xFFFF, sum = 0
4733 09:26:08.631903 6, 0xFFFF, sum = 0
4734 09:26:08.635080 7, 0xFFFF, sum = 0
4735 09:26:08.635165 8, 0x0, sum = 1
4736 09:26:08.638388 9, 0x0, sum = 2
4737 09:26:08.638550 10, 0x0, sum = 3
4738 09:26:08.641918 11, 0x0, sum = 4
4739 09:26:08.642016 best_step = 9
4740 09:26:08.642078
4741 09:26:08.642133 ==
4742 09:26:08.644835 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 09:26:08.651399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 09:26:08.651509 ==
4745 09:26:08.651571 RX Vref Scan: 0
4746 09:26:08.651627
4747 09:26:08.655156 RX Vref 0 -> 0, step: 1
4748 09:26:08.655242
4749 09:26:08.658640 RX Delay -195 -> 252, step: 8
4750 09:26:08.661656 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4751 09:26:08.668237 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4752 09:26:08.671870 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4753 09:26:08.675530 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4754 09:26:08.678448 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4755 09:26:08.681906 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4756 09:26:08.688634 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4757 09:26:08.691662 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4758 09:26:08.695062 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4759 09:26:08.698368 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4760 09:26:08.702195 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4761 09:26:08.708253 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4762 09:26:08.712275 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4763 09:26:08.715192 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4764 09:26:08.718632 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4765 09:26:08.725247 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4766 09:26:08.725361 ==
4767 09:26:08.728726 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 09:26:08.731902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 09:26:08.731991 ==
4770 09:26:08.732054 DQS Delay:
4771 09:26:08.734991 DQS0 = 0, DQS1 = 0
4772 09:26:08.735073 DQM Delay:
4773 09:26:08.738606 DQM0 = 39, DQM1 = 33
4774 09:26:08.738702 DQ Delay:
4775 09:26:08.742019 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4776 09:26:08.745493 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4777 09:26:08.748768 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4778 09:26:08.752202 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4779 09:26:08.752292
4780 09:26:08.752352
4781 09:26:08.758310 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e4c, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
4782 09:26:08.761622 CH1 RK1: MR19=808, MR18=3E4C
4783 09:26:08.768411 CH1_RK1: MR19=0x808, MR18=0x3E4C, DQSOSC=395, MR23=63, INC=168, DEC=112
4784 09:26:08.772128 [RxdqsGatingPostProcess] freq 600
4785 09:26:08.778480 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4786 09:26:08.781961 Pre-setting of DQS Precalculation
4787 09:26:08.785541 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4788 09:26:08.791622 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4789 09:26:08.798896 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4790 09:26:08.799000
4791 09:26:08.799061
4792 09:26:08.801653 [Calibration Summary] 1200 Mbps
4793 09:26:08.805089 CH 0, Rank 0
4794 09:26:08.805181 SW Impedance : PASS
4795 09:26:08.808551 DUTY Scan : NO K
4796 09:26:08.808634 ZQ Calibration : PASS
4797 09:26:08.812013 Jitter Meter : NO K
4798 09:26:08.815483 CBT Training : PASS
4799 09:26:08.815568 Write leveling : PASS
4800 09:26:08.818755 RX DQS gating : PASS
4801 09:26:08.822341 RX DQ/DQS(RDDQC) : PASS
4802 09:26:08.822424 TX DQ/DQS : PASS
4803 09:26:08.825506 RX DATLAT : PASS
4804 09:26:08.828980 RX DQ/DQS(Engine): PASS
4805 09:26:08.829063 TX OE : NO K
4806 09:26:08.832114 All Pass.
4807 09:26:08.832193
4808 09:26:08.832253 CH 0, Rank 1
4809 09:26:08.835720 SW Impedance : PASS
4810 09:26:08.835797 DUTY Scan : NO K
4811 09:26:08.838724 ZQ Calibration : PASS
4812 09:26:08.842456 Jitter Meter : NO K
4813 09:26:08.842543 CBT Training : PASS
4814 09:26:08.845561 Write leveling : PASS
4815 09:26:08.845642 RX DQS gating : PASS
4816 09:26:08.848551 RX DQ/DQS(RDDQC) : PASS
4817 09:26:08.852184 TX DQ/DQS : PASS
4818 09:26:08.852264 RX DATLAT : PASS
4819 09:26:08.855287 RX DQ/DQS(Engine): PASS
4820 09:26:08.858827 TX OE : NO K
4821 09:26:08.858911 All Pass.
4822 09:26:08.858971
4823 09:26:08.859026 CH 1, Rank 0
4824 09:26:08.861861 SW Impedance : PASS
4825 09:26:08.865603 DUTY Scan : NO K
4826 09:26:08.865697 ZQ Calibration : PASS
4827 09:26:08.868666 Jitter Meter : NO K
4828 09:26:08.872155 CBT Training : PASS
4829 09:26:08.872241 Write leveling : PASS
4830 09:26:08.875354 RX DQS gating : PASS
4831 09:26:08.878731 RX DQ/DQS(RDDQC) : PASS
4832 09:26:08.878819 TX DQ/DQS : PASS
4833 09:26:08.882394 RX DATLAT : PASS
4834 09:26:08.885689 RX DQ/DQS(Engine): PASS
4835 09:26:08.885777 TX OE : NO K
4836 09:26:08.885839 All Pass.
4837 09:26:08.885894
4838 09:26:08.888706 CH 1, Rank 1
4839 09:26:08.891892 SW Impedance : PASS
4840 09:26:08.891979 DUTY Scan : NO K
4841 09:26:08.895496 ZQ Calibration : PASS
4842 09:26:08.895580 Jitter Meter : NO K
4843 09:26:08.898643 CBT Training : PASS
4844 09:26:08.902169 Write leveling : PASS
4845 09:26:08.902255 RX DQS gating : PASS
4846 09:26:08.905208 RX DQ/DQS(RDDQC) : PASS
4847 09:26:08.908634 TX DQ/DQS : PASS
4848 09:26:08.908717 RX DATLAT : PASS
4849 09:26:08.911903 RX DQ/DQS(Engine): PASS
4850 09:26:08.915348 TX OE : NO K
4851 09:26:08.915436 All Pass.
4852 09:26:08.915497
4853 09:26:08.918872 DramC Write-DBI off
4854 09:26:08.918953 PER_BANK_REFRESH: Hybrid Mode
4855 09:26:08.922301 TX_TRACKING: ON
4856 09:26:08.929144 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4857 09:26:08.932013 [FAST_K] Save calibration result to emmc
4858 09:26:08.938650 dramc_set_vcore_voltage set vcore to 662500
4859 09:26:08.938762 Read voltage for 933, 3
4860 09:26:08.942301 Vio18 = 0
4861 09:26:08.942386 Vcore = 662500
4862 09:26:08.942446 Vdram = 0
4863 09:26:08.942501 Vddq = 0
4864 09:26:08.945918 Vmddr = 0
4865 09:26:08.948944 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4866 09:26:08.955506 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4867 09:26:08.959193 MEM_TYPE=3, freq_sel=17
4868 09:26:08.959282 sv_algorithm_assistance_LP4_1600
4869 09:26:08.965961 ============ PULL DRAM RESETB DOWN ============
4870 09:26:08.968949 ========== PULL DRAM RESETB DOWN end =========
4871 09:26:08.972655 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4872 09:26:08.975692 ===================================
4873 09:26:08.979250 LPDDR4 DRAM CONFIGURATION
4874 09:26:08.982691 ===================================
4875 09:26:08.985690 EX_ROW_EN[0] = 0x0
4876 09:26:08.985775 EX_ROW_EN[1] = 0x0
4877 09:26:08.989256 LP4Y_EN = 0x0
4878 09:26:08.989343 WORK_FSP = 0x0
4879 09:26:08.992132 WL = 0x3
4880 09:26:08.992217 RL = 0x3
4881 09:26:08.995438 BL = 0x2
4882 09:26:08.995524 RPST = 0x0
4883 09:26:08.998762 RD_PRE = 0x0
4884 09:26:08.998847 WR_PRE = 0x1
4885 09:26:09.002285 WR_PST = 0x0
4886 09:26:09.002370 DBI_WR = 0x0
4887 09:26:09.005840 DBI_RD = 0x0
4888 09:26:09.005928 OTF = 0x1
4889 09:26:09.008807 ===================================
4890 09:26:09.012452 ===================================
4891 09:26:09.015380 ANA top config
4892 09:26:09.018971 ===================================
4893 09:26:09.022150 DLL_ASYNC_EN = 0
4894 09:26:09.022239 ALL_SLAVE_EN = 1
4895 09:26:09.025787 NEW_RANK_MODE = 1
4896 09:26:09.028767 DLL_IDLE_MODE = 1
4897 09:26:09.032079 LP45_APHY_COMB_EN = 1
4898 09:26:09.032167 TX_ODT_DIS = 1
4899 09:26:09.035530 NEW_8X_MODE = 1
4900 09:26:09.039160 ===================================
4901 09:26:09.042419 ===================================
4902 09:26:09.045688 data_rate = 1866
4903 09:26:09.049191 CKR = 1
4904 09:26:09.052199 DQ_P2S_RATIO = 8
4905 09:26:09.055868 ===================================
4906 09:26:09.055957 CA_P2S_RATIO = 8
4907 09:26:09.058895 DQ_CA_OPEN = 0
4908 09:26:09.062575 DQ_SEMI_OPEN = 0
4909 09:26:09.065657 CA_SEMI_OPEN = 0
4910 09:26:09.069337 CA_FULL_RATE = 0
4911 09:26:09.072350 DQ_CKDIV4_EN = 1
4912 09:26:09.072437 CA_CKDIV4_EN = 1
4913 09:26:09.075952 CA_PREDIV_EN = 0
4914 09:26:09.078961 PH8_DLY = 0
4915 09:26:09.082588 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4916 09:26:09.085684 DQ_AAMCK_DIV = 4
4917 09:26:09.089007 CA_AAMCK_DIV = 4
4918 09:26:09.089096 CA_ADMCK_DIV = 4
4919 09:26:09.092543 DQ_TRACK_CA_EN = 0
4920 09:26:09.096201 CA_PICK = 933
4921 09:26:09.099308 CA_MCKIO = 933
4922 09:26:09.102681 MCKIO_SEMI = 0
4923 09:26:09.105915 PLL_FREQ = 3732
4924 09:26:09.109216 DQ_UI_PI_RATIO = 32
4925 09:26:09.109302 CA_UI_PI_RATIO = 0
4926 09:26:09.112762 ===================================
4927 09:26:09.115458 ===================================
4928 09:26:09.118940 memory_type:LPDDR4
4929 09:26:09.122243 GP_NUM : 10
4930 09:26:09.122334 SRAM_EN : 1
4931 09:26:09.125626 MD32_EN : 0
4932 09:26:09.129125 ===================================
4933 09:26:09.132143 [ANA_INIT] >>>>>>>>>>>>>>
4934 09:26:09.135717 <<<<<< [CONFIGURE PHASE]: ANA_TX
4935 09:26:09.142006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4936 09:26:09.142139 ===================================
4937 09:26:09.142444 data_rate = 1866,PCW = 0X8f00
4938 09:26:09.145872 ===================================
4939 09:26:09.149473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4940 09:26:09.155959 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4941 09:26:09.162541 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 09:26:09.165600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4943 09:26:09.169107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4944 09:26:09.172353 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4945 09:26:09.175951 [ANA_INIT] flow start
4946 09:26:09.176039 [ANA_INIT] PLL >>>>>>>>
4947 09:26:09.178965 [ANA_INIT] PLL <<<<<<<<
4948 09:26:09.182659 [ANA_INIT] MIDPI >>>>>>>>
4949 09:26:09.182753 [ANA_INIT] MIDPI <<<<<<<<
4950 09:26:09.185693 [ANA_INIT] DLL >>>>>>>>
4951 09:26:09.188975 [ANA_INIT] flow end
4952 09:26:09.192523 ============ LP4 DIFF to SE enter ============
4953 09:26:09.196060 ============ LP4 DIFF to SE exit ============
4954 09:26:09.199137 [ANA_INIT] <<<<<<<<<<<<<
4955 09:26:09.202203 [Flow] Enable top DCM control >>>>>
4956 09:26:09.206130 [Flow] Enable top DCM control <<<<<
4957 09:26:09.209152 Enable DLL master slave shuffle
4958 09:26:09.212787 ==============================================================
4959 09:26:09.215922 Gating Mode config
4960 09:26:09.222335 ==============================================================
4961 09:26:09.222452 Config description:
4962 09:26:09.232390 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4963 09:26:09.238891 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4964 09:26:09.242767 SELPH_MODE 0: By rank 1: By Phase
4965 09:26:09.249157 ==============================================================
4966 09:26:09.252597 GAT_TRACK_EN = 1
4967 09:26:09.255581 RX_GATING_MODE = 2
4968 09:26:09.259045 RX_GATING_TRACK_MODE = 2
4969 09:26:09.262421 SELPH_MODE = 1
4970 09:26:09.265854 PICG_EARLY_EN = 1
4971 09:26:09.269532 VALID_LAT_VALUE = 1
4972 09:26:09.272670 ==============================================================
4973 09:26:09.275687 Enter into Gating configuration >>>>
4974 09:26:09.279291 Exit from Gating configuration <<<<
4975 09:26:09.282515 Enter into DVFS_PRE_config >>>>>
4976 09:26:09.292910 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4977 09:26:09.295830 Exit from DVFS_PRE_config <<<<<
4978 09:26:09.299586 Enter into PICG configuration >>>>
4979 09:26:09.302554 Exit from PICG configuration <<<<
4980 09:26:09.306257 [RX_INPUT] configuration >>>>>
4981 09:26:09.309155 [RX_INPUT] configuration <<<<<
4982 09:26:09.312731 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4983 09:26:09.319501 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4984 09:26:09.325913 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4985 09:26:09.332706 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4986 09:26:09.339661 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4987 09:26:09.342926 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4988 09:26:09.349499 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4989 09:26:09.353021 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4990 09:26:09.356246 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4991 09:26:09.359483 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4992 09:26:09.365889 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4993 09:26:09.369131 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4994 09:26:09.372775 ===================================
4995 09:26:09.376069 LPDDR4 DRAM CONFIGURATION
4996 09:26:09.379743 ===================================
4997 09:26:09.379837 EX_ROW_EN[0] = 0x0
4998 09:26:09.382892 EX_ROW_EN[1] = 0x0
4999 09:26:09.382982 LP4Y_EN = 0x0
5000 09:26:09.386310 WORK_FSP = 0x0
5001 09:26:09.386400 WL = 0x3
5002 09:26:09.389211 RL = 0x3
5003 09:26:09.389294 BL = 0x2
5004 09:26:09.392902 RPST = 0x0
5005 09:26:09.392989 RD_PRE = 0x0
5006 09:26:09.395968 WR_PRE = 0x1
5007 09:26:09.396054 WR_PST = 0x0
5008 09:26:09.399584 DBI_WR = 0x0
5009 09:26:09.402569 DBI_RD = 0x0
5010 09:26:09.402657 OTF = 0x1
5011 09:26:09.406180 ===================================
5012 09:26:09.409151 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5013 09:26:09.412745 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5014 09:26:09.419276 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5015 09:26:09.423022 ===================================
5016 09:26:09.423120 LPDDR4 DRAM CONFIGURATION
5017 09:26:09.425996 ===================================
5018 09:26:09.429486 EX_ROW_EN[0] = 0x10
5019 09:26:09.432438 EX_ROW_EN[1] = 0x0
5020 09:26:09.432529 LP4Y_EN = 0x0
5021 09:26:09.436088 WORK_FSP = 0x0
5022 09:26:09.436174 WL = 0x3
5023 09:26:09.439647 RL = 0x3
5024 09:26:09.439730 BL = 0x2
5025 09:26:09.442652 RPST = 0x0
5026 09:26:09.442735 RD_PRE = 0x0
5027 09:26:09.446223 WR_PRE = 0x1
5028 09:26:09.446310 WR_PST = 0x0
5029 09:26:09.449604 DBI_WR = 0x0
5030 09:26:09.449687 DBI_RD = 0x0
5031 09:26:09.452485 OTF = 0x1
5032 09:26:09.455897 ===================================
5033 09:26:09.462512 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5034 09:26:09.466195 nWR fixed to 30
5035 09:26:09.466301 [ModeRegInit_LP4] CH0 RK0
5036 09:26:09.469395 [ModeRegInit_LP4] CH0 RK1
5037 09:26:09.472883 [ModeRegInit_LP4] CH1 RK0
5038 09:26:09.476313 [ModeRegInit_LP4] CH1 RK1
5039 09:26:09.476411 match AC timing 9
5040 09:26:09.479255 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5041 09:26:09.485777 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5042 09:26:09.489242 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5043 09:26:09.495885 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5044 09:26:09.499601 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5045 09:26:09.499692 ==
5046 09:26:09.502646 Dram Type= 6, Freq= 0, CH_0, rank 0
5047 09:26:09.506194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5048 09:26:09.506274 ==
5049 09:26:09.512983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5050 09:26:09.519417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5051 09:26:09.523136 [CA 0] Center 38 (8~69) winsize 62
5052 09:26:09.526251 [CA 1] Center 38 (7~69) winsize 63
5053 09:26:09.529845 [CA 2] Center 35 (5~66) winsize 62
5054 09:26:09.532720 [CA 3] Center 35 (4~66) winsize 63
5055 09:26:09.536348 [CA 4] Center 34 (4~64) winsize 61
5056 09:26:09.536430 [CA 5] Center 34 (4~64) winsize 61
5057 09:26:09.539376
5058 09:26:09.543078 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5059 09:26:09.543158
5060 09:26:09.546125 [CATrainingPosCal] consider 1 rank data
5061 09:26:09.549450 u2DelayCellTimex100 = 270/100 ps
5062 09:26:09.553166 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5063 09:26:09.556124 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5064 09:26:09.559599 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5065 09:26:09.563077 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5066 09:26:09.566588 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5067 09:26:09.569662 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5068 09:26:09.569747
5069 09:26:09.573147 CA PerBit enable=1, Macro0, CA PI delay=34
5070 09:26:09.573229
5071 09:26:09.576500 [CBTSetCACLKResult] CA Dly = 34
5072 09:26:09.579828 CS Dly: 6 (0~37)
5073 09:26:09.579912 ==
5074 09:26:09.583171 Dram Type= 6, Freq= 0, CH_0, rank 1
5075 09:26:09.586770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5076 09:26:09.586858 ==
5077 09:26:09.593329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5078 09:26:09.596223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5079 09:26:09.601088 [CA 0] Center 38 (8~69) winsize 62
5080 09:26:09.603771 [CA 1] Center 38 (7~69) winsize 63
5081 09:26:09.607221 [CA 2] Center 35 (5~66) winsize 62
5082 09:26:09.610460 [CA 3] Center 35 (5~66) winsize 62
5083 09:26:09.614172 [CA 4] Center 34 (3~65) winsize 63
5084 09:26:09.617076 [CA 5] Center 33 (3~64) winsize 62
5085 09:26:09.617158
5086 09:26:09.620784 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5087 09:26:09.620862
5088 09:26:09.624138 [CATrainingPosCal] consider 2 rank data
5089 09:26:09.627174 u2DelayCellTimex100 = 270/100 ps
5090 09:26:09.630916 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5091 09:26:09.633902 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5092 09:26:09.640546 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5093 09:26:09.644136 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5094 09:26:09.647209 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5095 09:26:09.650877 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5096 09:26:09.650959
5097 09:26:09.654324 CA PerBit enable=1, Macro0, CA PI delay=34
5098 09:26:09.654406
5099 09:26:09.657211 [CBTSetCACLKResult] CA Dly = 34
5100 09:26:09.657290 CS Dly: 7 (0~39)
5101 09:26:09.657350
5102 09:26:09.660921 ----->DramcWriteLeveling(PI) begin...
5103 09:26:09.663983 ==
5104 09:26:09.664065 Dram Type= 6, Freq= 0, CH_0, rank 0
5105 09:26:09.671050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 09:26:09.671150 ==
5107 09:26:09.674316 Write leveling (Byte 0): 34 => 34
5108 09:26:09.677299 Write leveling (Byte 1): 28 => 28
5109 09:26:09.680888 DramcWriteLeveling(PI) end<-----
5110 09:26:09.680969
5111 09:26:09.681029 ==
5112 09:26:09.684268 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 09:26:09.687227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 09:26:09.687306 ==
5115 09:26:09.690427 [Gating] SW mode calibration
5116 09:26:09.697096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5117 09:26:09.700668 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5118 09:26:09.707201 0 14 0 | B1->B0 | 2323 2d2d | 1 1 | (1 1) (1 1)
5119 09:26:09.710991 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5120 09:26:09.713925 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 09:26:09.720656 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 09:26:09.724083 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 09:26:09.727451 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 09:26:09.734108 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 09:26:09.737823 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
5126 09:26:09.740907 0 15 0 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (0 0)
5127 09:26:09.747462 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 09:26:09.750587 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 09:26:09.754251 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 09:26:09.760843 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 09:26:09.764395 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 09:26:09.767581 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 09:26:09.771151 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5134 09:26:09.777718 1 0 0 | B1->B0 | 3333 4343 | 1 1 | (0 0) (0 0)
5135 09:26:09.780979 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 09:26:09.784158 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 09:26:09.791067 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 09:26:09.794478 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 09:26:09.797713 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 09:26:09.804269 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 09:26:09.807822 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 09:26:09.811224 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5143 09:26:09.817447 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5144 09:26:09.821239 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 09:26:09.824325 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 09:26:09.831193 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 09:26:09.834389 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 09:26:09.837944 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 09:26:09.841118 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 09:26:09.847721 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 09:26:09.851333 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 09:26:09.854286 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 09:26:09.861446 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 09:26:09.864199 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 09:26:09.867858 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 09:26:09.874477 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 09:26:09.877568 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5158 09:26:09.881156 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5159 09:26:09.887771 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 09:26:09.887907 Total UI for P1: 0, mck2ui 16
5161 09:26:09.894695 best dqsien dly found for B0: ( 1, 2, 30)
5162 09:26:09.894918 Total UI for P1: 0, mck2ui 16
5163 09:26:09.901209 best dqsien dly found for B1: ( 1, 3, 0)
5164 09:26:09.904364 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5165 09:26:09.908133 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5166 09:26:09.908249
5167 09:26:09.911196 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5168 09:26:09.914769 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5169 09:26:09.918192 [Gating] SW calibration Done
5170 09:26:09.918300 ==
5171 09:26:09.921377 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 09:26:09.924939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 09:26:09.925038 ==
5174 09:26:09.925122 RX Vref Scan: 0
5175 09:26:09.928023
5176 09:26:09.928111 RX Vref 0 -> 0, step: 1
5177 09:26:09.928190
5178 09:26:09.931216 RX Delay -80 -> 252, step: 8
5179 09:26:09.934748 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5180 09:26:09.937851 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5181 09:26:09.944883 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5182 09:26:09.948069 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5183 09:26:09.951290 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5184 09:26:09.954754 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5185 09:26:09.957855 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5186 09:26:09.961759 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5187 09:26:09.964747 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5188 09:26:09.971692 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5189 09:26:09.974778 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5190 09:26:09.977842 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5191 09:26:09.981446 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5192 09:26:09.984461 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5193 09:26:09.991364 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5194 09:26:09.994871 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5195 09:26:09.995015 ==
5196 09:26:09.998281 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 09:26:10.001565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 09:26:10.001671 ==
5199 09:26:10.001759 DQS Delay:
5200 09:26:10.004921 DQS0 = 0, DQS1 = 0
5201 09:26:10.005061 DQM Delay:
5202 09:26:10.008267 DQM0 = 98, DQM1 = 87
5203 09:26:10.008362 DQ Delay:
5204 09:26:10.011412 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5205 09:26:10.014641 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5206 09:26:10.018158 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =79
5207 09:26:10.021086 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5208 09:26:10.021188
5209 09:26:10.021249
5210 09:26:10.021304 ==
5211 09:26:10.024539 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 09:26:10.031117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 09:26:10.031236 ==
5214 09:26:10.031299
5215 09:26:10.031354
5216 09:26:10.031407 TX Vref Scan disable
5217 09:26:10.034922 == TX Byte 0 ==
5218 09:26:10.037836 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5219 09:26:10.044517 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5220 09:26:10.044646 == TX Byte 1 ==
5221 09:26:10.048252 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5222 09:26:10.054896 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5223 09:26:10.055010 ==
5224 09:26:10.057770 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 09:26:10.061325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 09:26:10.061451 ==
5227 09:26:10.061516
5228 09:26:10.061618
5229 09:26:10.064917 TX Vref Scan disable
5230 09:26:10.065032 == TX Byte 0 ==
5231 09:26:10.071456 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5232 09:26:10.074969 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5233 09:26:10.075088 == TX Byte 1 ==
5234 09:26:10.081395 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5235 09:26:10.084995 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5236 09:26:10.085094
5237 09:26:10.085159 [DATLAT]
5238 09:26:10.088097 Freq=933, CH0 RK0
5239 09:26:10.088179
5240 09:26:10.088239 DATLAT Default: 0xd
5241 09:26:10.091619 0, 0xFFFF, sum = 0
5242 09:26:10.091701 1, 0xFFFF, sum = 0
5243 09:26:10.094804 2, 0xFFFF, sum = 0
5244 09:26:10.094885 3, 0xFFFF, sum = 0
5245 09:26:10.098444 4, 0xFFFF, sum = 0
5246 09:26:10.098538 5, 0xFFFF, sum = 0
5247 09:26:10.101344 6, 0xFFFF, sum = 0
5248 09:26:10.101442 7, 0xFFFF, sum = 0
5249 09:26:10.104907 8, 0xFFFF, sum = 0
5250 09:26:10.104995 9, 0xFFFF, sum = 0
5251 09:26:10.108137 10, 0x0, sum = 1
5252 09:26:10.108224 11, 0x0, sum = 2
5253 09:26:10.111706 12, 0x0, sum = 3
5254 09:26:10.111794 13, 0x0, sum = 4
5255 09:26:10.115298 best_step = 11
5256 09:26:10.115380
5257 09:26:10.115439 ==
5258 09:26:10.118440 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 09:26:10.121709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 09:26:10.121804 ==
5261 09:26:10.125233 RX Vref Scan: 1
5262 09:26:10.125327
5263 09:26:10.125386 RX Vref 0 -> 0, step: 1
5264 09:26:10.125441
5265 09:26:10.128612 RX Delay -61 -> 252, step: 4
5266 09:26:10.128692
5267 09:26:10.131403 Set Vref, RX VrefLevel [Byte0]: 54
5268 09:26:10.135076 [Byte1]: 52
5269 09:26:10.138725
5270 09:26:10.138801 Final RX Vref Byte 0 = 54 to rank0
5271 09:26:10.142365 Final RX Vref Byte 1 = 52 to rank0
5272 09:26:10.145417 Final RX Vref Byte 0 = 54 to rank1
5273 09:26:10.148936 Final RX Vref Byte 1 = 52 to rank1==
5274 09:26:10.151942 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 09:26:10.155581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 09:26:10.158435 ==
5277 09:26:10.158514 DQS Delay:
5278 09:26:10.158572 DQS0 = 0, DQS1 = 0
5279 09:26:10.161973 DQM Delay:
5280 09:26:10.162092 DQM0 = 97, DQM1 = 89
5281 09:26:10.165640 DQ Delay:
5282 09:26:10.168640 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5283 09:26:10.172220 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =104
5284 09:26:10.172318 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =80
5285 09:26:10.178806 DQ12 =98, DQ13 =96, DQ14 =98, DQ15 =98
5286 09:26:10.178893
5287 09:26:10.178952
5288 09:26:10.185448 [DQSOSCAuto] RK0, (LSB)MR18= 0x1904, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5289 09:26:10.188763 CH0 RK0: MR19=505, MR18=1904
5290 09:26:10.195329 CH0_RK0: MR19=0x505, MR18=0x1904, DQSOSC=413, MR23=63, INC=63, DEC=42
5291 09:26:10.195415
5292 09:26:10.198591 ----->DramcWriteLeveling(PI) begin...
5293 09:26:10.198676 ==
5294 09:26:10.202210 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 09:26:10.205868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 09:26:10.205957 ==
5297 09:26:10.208980 Write leveling (Byte 0): 33 => 33
5298 09:26:10.212277 Write leveling (Byte 1): 27 => 27
5299 09:26:10.215630 DramcWriteLeveling(PI) end<-----
5300 09:26:10.215716
5301 09:26:10.215777 ==
5302 09:26:10.218611 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 09:26:10.222285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 09:26:10.222372 ==
5305 09:26:10.225686 [Gating] SW mode calibration
5306 09:26:10.232466 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5307 09:26:10.238935 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5308 09:26:10.242417 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5309 09:26:10.245386 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5310 09:26:10.252253 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 09:26:10.255312 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 09:26:10.259092 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 09:26:10.265598 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 09:26:10.269217 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5315 09:26:10.272332 0 14 28 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
5316 09:26:10.279415 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5317 09:26:10.282279 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 09:26:10.285970 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 09:26:10.288968 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 09:26:10.295999 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 09:26:10.299089 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 09:26:10.302590 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 09:26:10.309294 0 15 28 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
5324 09:26:10.312535 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5325 09:26:10.315698 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 09:26:10.322303 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 09:26:10.325355 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 09:26:10.328808 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 09:26:10.335690 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 09:26:10.339145 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 09:26:10.342179 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5332 09:26:10.348759 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5333 09:26:10.352286 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 09:26:10.355487 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 09:26:10.362149 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 09:26:10.365182 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 09:26:10.368753 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 09:26:10.375471 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 09:26:10.378638 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 09:26:10.382305 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 09:26:10.388610 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 09:26:10.392413 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 09:26:10.395336 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 09:26:10.398874 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 09:26:10.405517 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 09:26:10.409106 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5347 09:26:10.412166 Total UI for P1: 0, mck2ui 16
5348 09:26:10.415799 best dqsien dly found for B0: ( 1, 2, 22)
5349 09:26:10.418790 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5350 09:26:10.425798 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5351 09:26:10.429067 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 09:26:10.432191 Total UI for P1: 0, mck2ui 16
5353 09:26:10.435601 best dqsien dly found for B1: ( 1, 2, 30)
5354 09:26:10.438862 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5355 09:26:10.442139 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5356 09:26:10.442282
5357 09:26:10.445371 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5358 09:26:10.449094 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5359 09:26:10.452447 [Gating] SW calibration Done
5360 09:26:10.452591 ==
5361 09:26:10.455518 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 09:26:10.458749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 09:26:10.462460 ==
5364 09:26:10.462598 RX Vref Scan: 0
5365 09:26:10.462718
5366 09:26:10.465487 RX Vref 0 -> 0, step: 1
5367 09:26:10.465613
5368 09:26:10.465728 RX Delay -80 -> 252, step: 8
5369 09:26:10.472503 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5370 09:26:10.476146 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5371 09:26:10.479190 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5372 09:26:10.482898 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5373 09:26:10.485991 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5374 09:26:10.489596 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5375 09:26:10.496254 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5376 09:26:10.499296 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5377 09:26:10.502764 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5378 09:26:10.506496 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5379 09:26:10.509398 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5380 09:26:10.512477 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5381 09:26:10.519092 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5382 09:26:10.522797 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5383 09:26:10.526335 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5384 09:26:10.529270 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5385 09:26:10.529394 ==
5386 09:26:10.533010 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 09:26:10.536106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 09:26:10.536229 ==
5389 09:26:10.539700 DQS Delay:
5390 09:26:10.539817 DQS0 = 0, DQS1 = 0
5391 09:26:10.542651 DQM Delay:
5392 09:26:10.542771 DQM0 = 96, DQM1 = 88
5393 09:26:10.542878 DQ Delay:
5394 09:26:10.546268 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5395 09:26:10.549505 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5396 09:26:10.552679 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79
5397 09:26:10.556136 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5398 09:26:10.556258
5399 09:26:10.556370
5400 09:26:10.559409 ==
5401 09:26:10.562617 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 09:26:10.565846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 09:26:10.565965 ==
5404 09:26:10.566116
5405 09:26:10.566256
5406 09:26:10.569670 TX Vref Scan disable
5407 09:26:10.569789 == TX Byte 0 ==
5408 09:26:10.572567 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5409 09:26:10.579218 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5410 09:26:10.579373 == TX Byte 1 ==
5411 09:26:10.582864 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5412 09:26:10.589463 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5413 09:26:10.589622 ==
5414 09:26:10.592609 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 09:26:10.596124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 09:26:10.596264 ==
5417 09:26:10.596377
5418 09:26:10.596488
5419 09:26:10.599188 TX Vref Scan disable
5420 09:26:10.602986 == TX Byte 0 ==
5421 09:26:10.606145 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5422 09:26:10.609610 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5423 09:26:10.612707 == TX Byte 1 ==
5424 09:26:10.616271 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5425 09:26:10.619925 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5426 09:26:10.620035
5427 09:26:10.620100 [DATLAT]
5428 09:26:10.622783 Freq=933, CH0 RK1
5429 09:26:10.622867
5430 09:26:10.626408 DATLAT Default: 0xb
5431 09:26:10.626495 0, 0xFFFF, sum = 0
5432 09:26:10.629462 1, 0xFFFF, sum = 0
5433 09:26:10.629550 2, 0xFFFF, sum = 0
5434 09:26:10.633201 3, 0xFFFF, sum = 0
5435 09:26:10.633287 4, 0xFFFF, sum = 0
5436 09:26:10.636153 5, 0xFFFF, sum = 0
5437 09:26:10.636237 6, 0xFFFF, sum = 0
5438 09:26:10.639712 7, 0xFFFF, sum = 0
5439 09:26:10.639797 8, 0xFFFF, sum = 0
5440 09:26:10.642842 9, 0xFFFF, sum = 0
5441 09:26:10.642926 10, 0x0, sum = 1
5442 09:26:10.645970 11, 0x0, sum = 2
5443 09:26:10.646087 12, 0x0, sum = 3
5444 09:26:10.649577 13, 0x0, sum = 4
5445 09:26:10.649662 best_step = 11
5446 09:26:10.649740
5447 09:26:10.649813 ==
5448 09:26:10.653275 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 09:26:10.656240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 09:26:10.656327 ==
5451 09:26:10.659506 RX Vref Scan: 0
5452 09:26:10.659589
5453 09:26:10.663165 RX Vref 0 -> 0, step: 1
5454 09:26:10.663251
5455 09:26:10.663331 RX Delay -61 -> 252, step: 4
5456 09:26:10.671027 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5457 09:26:10.673890 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5458 09:26:10.677197 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5459 09:26:10.680985 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5460 09:26:10.683965 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5461 09:26:10.687341 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5462 09:26:10.694499 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5463 09:26:10.697395 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5464 09:26:10.700639 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5465 09:26:10.704309 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5466 09:26:10.707352 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5467 09:26:10.711190 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5468 09:26:10.717445 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5469 09:26:10.721098 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5470 09:26:10.724114 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5471 09:26:10.727272 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5472 09:26:10.727360 ==
5473 09:26:10.730983 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 09:26:10.734388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 09:26:10.734480 ==
5476 09:26:10.737545 DQS Delay:
5477 09:26:10.737625 DQS0 = 0, DQS1 = 0
5478 09:26:10.741199 DQM Delay:
5479 09:26:10.741283 DQM0 = 95, DQM1 = 87
5480 09:26:10.741343 DQ Delay:
5481 09:26:10.744203 DQ0 =94, DQ1 =96, DQ2 =94, DQ3 =94
5482 09:26:10.747858 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5483 09:26:10.751022 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5484 09:26:10.754014 DQ12 =92, DQ13 =94, DQ14 =96, DQ15 =96
5485 09:26:10.754114
5486 09:26:10.754174
5487 09:26:10.764352 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b08, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5488 09:26:10.767663 CH0 RK1: MR19=505, MR18=1B08
5489 09:26:10.774296 CH0_RK1: MR19=0x505, MR18=0x1B08, DQSOSC=413, MR23=63, INC=63, DEC=42
5490 09:26:10.774417 [RxdqsGatingPostProcess] freq 933
5491 09:26:10.780979 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5492 09:26:10.784635 best DQS0 dly(2T, 0.5T) = (0, 10)
5493 09:26:10.787640 best DQS1 dly(2T, 0.5T) = (0, 11)
5494 09:26:10.791284 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5495 09:26:10.794670 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5496 09:26:10.797730 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 09:26:10.801148 best DQS1 dly(2T, 0.5T) = (0, 10)
5498 09:26:10.804405 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 09:26:10.807493 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5500 09:26:10.811343 Pre-setting of DQS Precalculation
5501 09:26:10.814422 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5502 09:26:10.814527 ==
5503 09:26:10.817868 Dram Type= 6, Freq= 0, CH_1, rank 0
5504 09:26:10.821519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 09:26:10.821624 ==
5506 09:26:10.827532 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5507 09:26:10.834566 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5508 09:26:10.837668 [CA 0] Center 36 (6~67) winsize 62
5509 09:26:10.841149 [CA 1] Center 36 (6~67) winsize 62
5510 09:26:10.844719 [CA 2] Center 34 (4~64) winsize 61
5511 09:26:10.847775 [CA 3] Center 34 (4~64) winsize 61
5512 09:26:10.850824 [CA 4] Center 34 (4~64) winsize 61
5513 09:26:10.854585 [CA 5] Center 33 (3~64) winsize 62
5514 09:26:10.854676
5515 09:26:10.857603 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5516 09:26:10.857684
5517 09:26:10.861310 [CATrainingPosCal] consider 1 rank data
5518 09:26:10.864355 u2DelayCellTimex100 = 270/100 ps
5519 09:26:10.867998 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5520 09:26:10.870846 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5521 09:26:10.874357 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5522 09:26:10.877845 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5523 09:26:10.880915 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5524 09:26:10.884521 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5525 09:26:10.884609
5526 09:26:10.891383 CA PerBit enable=1, Macro0, CA PI delay=33
5527 09:26:10.891485
5528 09:26:10.894378 [CBTSetCACLKResult] CA Dly = 33
5529 09:26:10.894463 CS Dly: 4 (0~35)
5530 09:26:10.894543 ==
5531 09:26:10.897832 Dram Type= 6, Freq= 0, CH_1, rank 1
5532 09:26:10.900940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 09:26:10.901034 ==
5534 09:26:10.907500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 09:26:10.914345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5536 09:26:10.917937 [CA 0] Center 36 (6~67) winsize 62
5537 09:26:10.921095 [CA 1] Center 36 (6~67) winsize 62
5538 09:26:10.924713 [CA 2] Center 33 (3~64) winsize 62
5539 09:26:10.927790 [CA 3] Center 33 (3~64) winsize 62
5540 09:26:10.931247 [CA 4] Center 34 (4~64) winsize 61
5541 09:26:10.934470 [CA 5] Center 32 (2~63) winsize 62
5542 09:26:10.934559
5543 09:26:10.937927 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5544 09:26:10.938053
5545 09:26:10.941571 [CATrainingPosCal] consider 2 rank data
5546 09:26:10.944593 u2DelayCellTimex100 = 270/100 ps
5547 09:26:10.948246 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5548 09:26:10.951114 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5549 09:26:10.954575 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5550 09:26:10.958303 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5551 09:26:10.961310 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5552 09:26:10.964926 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5553 09:26:10.965054
5554 09:26:10.967924 CA PerBit enable=1, Macro0, CA PI delay=33
5555 09:26:10.971479
5556 09:26:10.971567 [CBTSetCACLKResult] CA Dly = 33
5557 09:26:10.974517 CS Dly: 5 (0~38)
5558 09:26:10.974599
5559 09:26:10.977973 ----->DramcWriteLeveling(PI) begin...
5560 09:26:10.978100 ==
5561 09:26:10.981548 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 09:26:10.984617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 09:26:10.984704 ==
5564 09:26:10.988254 Write leveling (Byte 0): 25 => 25
5565 09:26:10.991231 Write leveling (Byte 1): 26 => 26
5566 09:26:10.994875 DramcWriteLeveling(PI) end<-----
5567 09:26:10.994964
5568 09:26:10.995024 ==
5569 09:26:10.997940 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 09:26:11.001544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 09:26:11.001630 ==
5572 09:26:11.004610 [Gating] SW mode calibration
5573 09:26:11.011410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5574 09:26:11.018022 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5575 09:26:11.021694 0 14 0 | B1->B0 | 2f2f 3333 | 0 1 | (0 0) (1 1)
5576 09:26:11.028057 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 09:26:11.031734 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 09:26:11.034840 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 09:26:11.038463 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 09:26:11.045078 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 09:26:11.047946 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 09:26:11.051447 0 14 28 | B1->B0 | 3030 3131 | 1 0 | (1 1) (0 1)
5583 09:26:11.057964 0 15 0 | B1->B0 | 2626 2929 | 0 0 | (0 0) (1 0)
5584 09:26:11.061457 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 09:26:11.064699 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5586 09:26:11.071738 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 09:26:11.074808 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5588 09:26:11.078418 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 09:26:11.084945 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 09:26:11.088055 0 15 28 | B1->B0 | 3131 2a2a | 0 0 | (0 0) (0 0)
5591 09:26:11.091276 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 09:26:11.097953 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 09:26:11.101744 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 09:26:11.104528 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 09:26:11.111382 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 09:26:11.114992 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 09:26:11.117936 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 09:26:11.124625 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 09:26:11.128201 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5600 09:26:11.131443 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 09:26:11.138095 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 09:26:11.141802 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 09:26:11.144777 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 09:26:11.147803 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 09:26:11.154608 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 09:26:11.158195 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 09:26:11.161150 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 09:26:11.168385 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 09:26:11.171483 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 09:26:11.174800 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 09:26:11.181678 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 09:26:11.184821 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 09:26:11.188185 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5614 09:26:11.194771 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5615 09:26:11.198321 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5616 09:26:11.201409 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 09:26:11.205112 Total UI for P1: 0, mck2ui 16
5618 09:26:11.208268 best dqsien dly found for B0: ( 1, 2, 28)
5619 09:26:11.211417 Total UI for P1: 0, mck2ui 16
5620 09:26:11.215088 best dqsien dly found for B1: ( 1, 2, 28)
5621 09:26:11.218140 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5622 09:26:11.221703 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5623 09:26:11.221780
5624 09:26:11.224754 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5625 09:26:11.231573 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5626 09:26:11.231658 [Gating] SW calibration Done
5627 09:26:11.231718 ==
5628 09:26:11.235144 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 09:26:11.241286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 09:26:11.241366 ==
5631 09:26:11.241426 RX Vref Scan: 0
5632 09:26:11.241482
5633 09:26:11.244927 RX Vref 0 -> 0, step: 1
5634 09:26:11.245004
5635 09:26:11.247915 RX Delay -80 -> 252, step: 8
5636 09:26:11.251553 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5637 09:26:11.255286 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5638 09:26:11.258177 iDelay=200, Bit 2, Center 79 (-16 ~ 175) 192
5639 09:26:11.261375 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5640 09:26:11.268187 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5641 09:26:11.271775 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5642 09:26:11.274869 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5643 09:26:11.278457 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5644 09:26:11.281437 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5645 09:26:11.284905 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5646 09:26:11.291657 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5647 09:26:11.295422 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5648 09:26:11.298325 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5649 09:26:11.301425 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5650 09:26:11.304945 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5651 09:26:11.308224 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5652 09:26:11.311711 ==
5653 09:26:11.314849 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 09:26:11.317953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 09:26:11.318058 ==
5656 09:26:11.318118 DQS Delay:
5657 09:26:11.321760 DQS0 = 0, DQS1 = 0
5658 09:26:11.321836 DQM Delay:
5659 09:26:11.324875 DQM0 = 95, DQM1 = 89
5660 09:26:11.324952 DQ Delay:
5661 09:26:11.327986 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =95
5662 09:26:11.331938 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5663 09:26:11.334928 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5664 09:26:11.338516 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5665 09:26:11.338815
5666 09:26:11.339047
5667 09:26:11.339261 ==
5668 09:26:11.342168 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 09:26:11.345140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 09:26:11.345443 ==
5671 09:26:11.345682
5672 09:26:11.345899
5673 09:26:11.348373 TX Vref Scan disable
5674 09:26:11.351998 == TX Byte 0 ==
5675 09:26:11.355652 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5676 09:26:11.358691 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5677 09:26:11.362249 == TX Byte 1 ==
5678 09:26:11.365116 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5679 09:26:11.368547 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5680 09:26:11.368846 ==
5681 09:26:11.372311 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 09:26:11.375283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 09:26:11.378903 ==
5684 09:26:11.379204
5685 09:26:11.379438
5686 09:26:11.379655 TX Vref Scan disable
5687 09:26:11.381941 == TX Byte 0 ==
5688 09:26:11.385631 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5689 09:26:11.392051 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5690 09:26:11.392276 == TX Byte 1 ==
5691 09:26:11.395475 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5692 09:26:11.398828 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5693 09:26:11.401753
5694 09:26:11.401898 [DATLAT]
5695 09:26:11.402025 Freq=933, CH1 RK0
5696 09:26:11.402135
5697 09:26:11.405500 DATLAT Default: 0xd
5698 09:26:11.405624 0, 0xFFFF, sum = 0
5699 09:26:11.408410 1, 0xFFFF, sum = 0
5700 09:26:11.408537 2, 0xFFFF, sum = 0
5701 09:26:11.412186 3, 0xFFFF, sum = 0
5702 09:26:11.412297 4, 0xFFFF, sum = 0
5703 09:26:11.415097 5, 0xFFFF, sum = 0
5704 09:26:11.415196 6, 0xFFFF, sum = 0
5705 09:26:11.418476 7, 0xFFFF, sum = 0
5706 09:26:11.422024 8, 0xFFFF, sum = 0
5707 09:26:11.422114 9, 0xFFFF, sum = 0
5708 09:26:11.422184 10, 0x0, sum = 1
5709 09:26:11.425192 11, 0x0, sum = 2
5710 09:26:11.425274 12, 0x0, sum = 3
5711 09:26:11.428657 13, 0x0, sum = 4
5712 09:26:11.428738 best_step = 11
5713 09:26:11.428801
5714 09:26:11.428858 ==
5715 09:26:11.432209 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 09:26:11.439103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 09:26:11.439181 ==
5718 09:26:11.439241 RX Vref Scan: 1
5719 09:26:11.439296
5720 09:26:11.442053 RX Vref 0 -> 0, step: 1
5721 09:26:11.442135
5722 09:26:11.445164 RX Delay -61 -> 252, step: 4
5723 09:26:11.445247
5724 09:26:11.448700 Set Vref, RX VrefLevel [Byte0]: 60
5725 09:26:11.452239 [Byte1]: 53
5726 09:26:11.452326
5727 09:26:11.455229 Final RX Vref Byte 0 = 60 to rank0
5728 09:26:11.458646 Final RX Vref Byte 1 = 53 to rank0
5729 09:26:11.461695 Final RX Vref Byte 0 = 60 to rank1
5730 09:26:11.465356 Final RX Vref Byte 1 = 53 to rank1==
5731 09:26:11.468280 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 09:26:11.471698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 09:26:11.471777 ==
5734 09:26:11.475173 DQS Delay:
5735 09:26:11.475250 DQS0 = 0, DQS1 = 0
5736 09:26:11.478297 DQM Delay:
5737 09:26:11.478374 DQM0 = 97, DQM1 = 90
5738 09:26:11.478434 DQ Delay:
5739 09:26:11.481977 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =96
5740 09:26:11.484935 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =96
5741 09:26:11.488520 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =86
5742 09:26:11.491996 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =96
5743 09:26:11.492073
5744 09:26:11.492132
5745 09:26:11.501551 [DQSOSCAuto] RK0, (LSB)MR18= 0x1af6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 413 ps
5746 09:26:11.505074 CH1 RK0: MR19=504, MR18=1AF6
5747 09:26:11.508585 CH1_RK0: MR19=0x504, MR18=0x1AF6, DQSOSC=413, MR23=63, INC=63, DEC=42
5748 09:26:11.511605
5749 09:26:11.515170 ----->DramcWriteLeveling(PI) begin...
5750 09:26:11.515249 ==
5751 09:26:11.518433 Dram Type= 6, Freq= 0, CH_1, rank 1
5752 09:26:11.521913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 09:26:11.521997 ==
5754 09:26:11.524943 Write leveling (Byte 0): 25 => 25
5755 09:26:11.528508 Write leveling (Byte 1): 25 => 25
5756 09:26:11.531826 DramcWriteLeveling(PI) end<-----
5757 09:26:11.531902
5758 09:26:11.531961 ==
5759 09:26:11.534946 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 09:26:11.538374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 09:26:11.538452 ==
5762 09:26:11.541975 [Gating] SW mode calibration
5763 09:26:11.548677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5764 09:26:11.555285 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5765 09:26:11.558632 0 14 0 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5766 09:26:11.561690 0 14 4 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5767 09:26:11.568673 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 09:26:11.571747 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 09:26:11.575268 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5770 09:26:11.578592 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 09:26:11.585363 0 14 24 | B1->B0 | 3131 3030 | 1 0 | (1 1) (0 1)
5772 09:26:11.588600 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
5773 09:26:11.591938 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 09:26:11.598876 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 09:26:11.601915 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 09:26:11.605100 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5777 09:26:11.611827 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 09:26:11.615384 0 15 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5779 09:26:11.618389 0 15 24 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)
5780 09:26:11.625113 0 15 28 | B1->B0 | 3939 4444 | 0 0 | (1 1) (0 0)
5781 09:26:11.628802 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 09:26:11.632224 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 09:26:11.638763 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 09:26:11.642153 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 09:26:11.645398 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 09:26:11.651934 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 09:26:11.655536 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5788 09:26:11.659003 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 09:26:11.662181 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 09:26:11.668626 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 09:26:11.672296 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 09:26:11.675326 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 09:26:11.682025 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 09:26:11.685440 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 09:26:11.688948 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 09:26:11.695594 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 09:26:11.698498 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 09:26:11.702133 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 09:26:11.708815 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 09:26:11.711905 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 09:26:11.715361 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 09:26:11.722233 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 09:26:11.725162 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5804 09:26:11.728876 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5805 09:26:11.731851 Total UI for P1: 0, mck2ui 16
5806 09:26:11.735701 best dqsien dly found for B0: ( 1, 2, 24)
5807 09:26:11.739190 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5808 09:26:11.745730 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 09:26:11.748649 Total UI for P1: 0, mck2ui 16
5810 09:26:11.752153 best dqsien dly found for B1: ( 1, 2, 28)
5811 09:26:11.755350 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5812 09:26:11.759117 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5813 09:26:11.759193
5814 09:26:11.762100 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5815 09:26:11.765737 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5816 09:26:11.768759 [Gating] SW calibration Done
5817 09:26:11.768835 ==
5818 09:26:11.772264 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 09:26:11.775757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 09:26:11.775838 ==
5821 09:26:11.778880 RX Vref Scan: 0
5822 09:26:11.778958
5823 09:26:11.779018 RX Vref 0 -> 0, step: 1
5824 09:26:11.782061
5825 09:26:11.782143 RX Delay -80 -> 252, step: 8
5826 09:26:11.788910 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5827 09:26:11.791939 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5828 09:26:11.795546 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5829 09:26:11.798978 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5830 09:26:11.802097 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5831 09:26:11.805364 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5832 09:26:11.808404 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5833 09:26:11.815104 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5834 09:26:11.818871 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5835 09:26:11.821810 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5836 09:26:11.825209 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5837 09:26:11.828458 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5838 09:26:11.835089 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5839 09:26:11.838646 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5840 09:26:11.842125 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5841 09:26:11.845211 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5842 09:26:11.845288 ==
5843 09:26:11.849017 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 09:26:11.852054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 09:26:11.852135 ==
5846 09:26:11.855680 DQS Delay:
5847 09:26:11.855824 DQS0 = 0, DQS1 = 0
5848 09:26:11.858456 DQM Delay:
5849 09:26:11.858591 DQM0 = 95, DQM1 = 90
5850 09:26:11.858665 DQ Delay:
5851 09:26:11.861912 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =95
5852 09:26:11.865478 DQ4 =99, DQ5 =103, DQ6 =103, DQ7 =91
5853 09:26:11.868629 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5854 09:26:11.872013 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5855 09:26:11.872162
5856 09:26:11.875350
5857 09:26:11.875477 ==
5858 09:26:11.878638 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 09:26:11.881913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 09:26:11.882028 ==
5861 09:26:11.882100
5862 09:26:11.882165
5863 09:26:11.885564 TX Vref Scan disable
5864 09:26:11.885936 == TX Byte 0 ==
5865 09:26:11.892368 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5866 09:26:11.895692 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5867 09:26:11.896032 == TX Byte 1 ==
5868 09:26:11.899135 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5869 09:26:11.905523 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5870 09:26:11.905861 ==
5871 09:26:11.908536 Dram Type= 6, Freq= 0, CH_1, rank 1
5872 09:26:11.911968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5873 09:26:11.912309 ==
5874 09:26:11.912575
5875 09:26:11.912905
5876 09:26:11.915586 TX Vref Scan disable
5877 09:26:11.919034 == TX Byte 0 ==
5878 09:26:11.921941 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5879 09:26:11.926152 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5880 09:26:11.928798 == TX Byte 1 ==
5881 09:26:11.932321 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5882 09:26:11.935512 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5883 09:26:11.935879
5884 09:26:11.936165 [DATLAT]
5885 09:26:11.938918 Freq=933, CH1 RK1
5886 09:26:11.939287
5887 09:26:11.942044 DATLAT Default: 0xb
5888 09:26:11.942423 0, 0xFFFF, sum = 0
5889 09:26:11.945680 1, 0xFFFF, sum = 0
5890 09:26:11.946087 2, 0xFFFF, sum = 0
5891 09:26:11.948887 3, 0xFFFF, sum = 0
5892 09:26:11.949257 4, 0xFFFF, sum = 0
5893 09:26:11.952078 5, 0xFFFF, sum = 0
5894 09:26:11.952449 6, 0xFFFF, sum = 0
5895 09:26:11.955616 7, 0xFFFF, sum = 0
5896 09:26:11.955985 8, 0xFFFF, sum = 0
5897 09:26:11.959202 9, 0xFFFF, sum = 0
5898 09:26:11.959658 10, 0x0, sum = 1
5899 09:26:11.962645 11, 0x0, sum = 2
5900 09:26:11.963044 12, 0x0, sum = 3
5901 09:26:11.965318 13, 0x0, sum = 4
5902 09:26:11.965689 best_step = 11
5903 09:26:11.965971
5904 09:26:11.966282 ==
5905 09:26:11.968881 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 09:26:11.972114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 09:26:11.972508 ==
5908 09:26:11.975855 RX Vref Scan: 0
5909 09:26:11.976220
5910 09:26:11.979228 RX Vref 0 -> 0, step: 1
5911 09:26:11.979591
5912 09:26:11.979873 RX Delay -61 -> 252, step: 4
5913 09:26:11.986519 iDelay=195, Bit 0, Center 96 (7 ~ 186) 180
5914 09:26:11.990127 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5915 09:26:11.993293 iDelay=195, Bit 2, Center 84 (-5 ~ 174) 180
5916 09:26:11.996886 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5917 09:26:12.000013 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5918 09:26:12.003642 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5919 09:26:12.009797 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5920 09:26:12.013659 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
5921 09:26:12.016745 iDelay=195, Bit 8, Center 82 (-9 ~ 174) 184
5922 09:26:12.020403 iDelay=195, Bit 9, Center 80 (-9 ~ 170) 180
5923 09:26:12.023452 iDelay=195, Bit 10, Center 94 (3 ~ 186) 184
5924 09:26:12.026445 iDelay=195, Bit 11, Center 82 (-9 ~ 174) 184
5925 09:26:12.033643 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
5926 09:26:12.036560 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5927 09:26:12.040206 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5928 09:26:12.043493 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
5929 09:26:12.043890 ==
5930 09:26:12.046802 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 09:26:12.050546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 09:26:12.050911 ==
5933 09:26:12.053421 DQS Delay:
5934 09:26:12.053779 DQS0 = 0, DQS1 = 0
5935 09:26:12.056666 DQM Delay:
5936 09:26:12.057022 DQM0 = 94, DQM1 = 91
5937 09:26:12.057303 DQ Delay:
5938 09:26:12.060464 DQ0 =96, DQ1 =90, DQ2 =84, DQ3 =94
5939 09:26:12.063322 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =90
5940 09:26:12.067058 DQ8 =82, DQ9 =80, DQ10 =94, DQ11 =82
5941 09:26:12.070207 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
5942 09:26:12.070708
5943 09:26:12.071067
5944 09:26:12.080556 [DQSOSCAuto] RK1, (LSB)MR18= 0xe17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5945 09:26:12.084061 CH1 RK1: MR19=505, MR18=E17
5946 09:26:12.087289 CH1_RK1: MR19=0x505, MR18=0xE17, DQSOSC=414, MR23=63, INC=63, DEC=42
5947 09:26:12.090796 [RxdqsGatingPostProcess] freq 933
5948 09:26:12.096991 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5949 09:26:12.100755 best DQS0 dly(2T, 0.5T) = (0, 10)
5950 09:26:12.104373 best DQS1 dly(2T, 0.5T) = (0, 10)
5951 09:26:12.107204 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5952 09:26:12.110728 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5953 09:26:12.114064 best DQS0 dly(2T, 0.5T) = (0, 10)
5954 09:26:12.117080 best DQS1 dly(2T, 0.5T) = (0, 10)
5955 09:26:12.117533 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5956 09:26:12.120765 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5957 09:26:12.123842 Pre-setting of DQS Precalculation
5958 09:26:12.130681 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5959 09:26:12.137472 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5960 09:26:12.143773 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5961 09:26:12.144221
5962 09:26:12.144609
5963 09:26:12.147024 [Calibration Summary] 1866 Mbps
5964 09:26:12.147393 CH 0, Rank 0
5965 09:26:12.150318 SW Impedance : PASS
5966 09:26:12.153888 DUTY Scan : NO K
5967 09:26:12.154326 ZQ Calibration : PASS
5968 09:26:12.157450 Jitter Meter : NO K
5969 09:26:12.160984 CBT Training : PASS
5970 09:26:12.161443 Write leveling : PASS
5971 09:26:12.164307 RX DQS gating : PASS
5972 09:26:12.167704 RX DQ/DQS(RDDQC) : PASS
5973 09:26:12.168108 TX DQ/DQS : PASS
5974 09:26:12.170741 RX DATLAT : PASS
5975 09:26:12.174046 RX DQ/DQS(Engine): PASS
5976 09:26:12.174608 TX OE : NO K
5977 09:26:12.174938 All Pass.
5978 09:26:12.177436
5979 09:26:12.177830 CH 0, Rank 1
5980 09:26:12.180654 SW Impedance : PASS
5981 09:26:12.181052 DUTY Scan : NO K
5982 09:26:12.184060 ZQ Calibration : PASS
5983 09:26:12.184423 Jitter Meter : NO K
5984 09:26:12.187322 CBT Training : PASS
5985 09:26:12.190471 Write leveling : PASS
5986 09:26:12.190991 RX DQS gating : PASS
5987 09:26:12.193859 RX DQ/DQS(RDDQC) : PASS
5988 09:26:12.197027 TX DQ/DQS : PASS
5989 09:26:12.197444 RX DATLAT : PASS
5990 09:26:12.200918 RX DQ/DQS(Engine): PASS
5991 09:26:12.203932 TX OE : NO K
5992 09:26:12.204297 All Pass.
5993 09:26:12.204582
5994 09:26:12.204845 CH 1, Rank 0
5995 09:26:12.207747 SW Impedance : PASS
5996 09:26:12.210760 DUTY Scan : NO K
5997 09:26:12.211123 ZQ Calibration : PASS
5998 09:26:12.214470 Jitter Meter : NO K
5999 09:26:12.217837 CBT Training : PASS
6000 09:26:12.218315 Write leveling : PASS
6001 09:26:12.220985 RX DQS gating : PASS
6002 09:26:12.221431 RX DQ/DQS(RDDQC) : PASS
6003 09:26:12.224928 TX DQ/DQS : PASS
6004 09:26:12.227720 RX DATLAT : PASS
6005 09:26:12.228121 RX DQ/DQS(Engine): PASS
6006 09:26:12.230986 TX OE : NO K
6007 09:26:12.231466 All Pass.
6008 09:26:12.231778
6009 09:26:12.234579 CH 1, Rank 1
6010 09:26:12.234976 SW Impedance : PASS
6011 09:26:12.237949 DUTY Scan : NO K
6012 09:26:12.241854 ZQ Calibration : PASS
6013 09:26:12.242389 Jitter Meter : NO K
6014 09:26:12.244901 CBT Training : PASS
6015 09:26:12.247940 Write leveling : PASS
6016 09:26:12.248419 RX DQS gating : PASS
6017 09:26:12.250739 RX DQ/DQS(RDDQC) : PASS
6018 09:26:12.254621 TX DQ/DQS : PASS
6019 09:26:12.255104 RX DATLAT : PASS
6020 09:26:12.257512 RX DQ/DQS(Engine): PASS
6021 09:26:12.261218 TX OE : NO K
6022 09:26:12.261696 All Pass.
6023 09:26:12.262051
6024 09:26:12.262352 DramC Write-DBI off
6025 09:26:12.264548 PER_BANK_REFRESH: Hybrid Mode
6026 09:26:12.268069 TX_TRACKING: ON
6027 09:26:12.274405 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6028 09:26:12.277824 [FAST_K] Save calibration result to emmc
6029 09:26:12.284545 dramc_set_vcore_voltage set vcore to 650000
6030 09:26:12.284943 Read voltage for 400, 6
6031 09:26:12.285316 Vio18 = 0
6032 09:26:12.287891 Vcore = 650000
6033 09:26:12.288356 Vdram = 0
6034 09:26:12.288664 Vddq = 0
6035 09:26:12.291044 Vmddr = 0
6036 09:26:12.294202 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6037 09:26:12.300949 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6038 09:26:12.301494 MEM_TYPE=3, freq_sel=20
6039 09:26:12.304544 sv_algorithm_assistance_LP4_800
6040 09:26:12.310812 ============ PULL DRAM RESETB DOWN ============
6041 09:26:12.314490 ========== PULL DRAM RESETB DOWN end =========
6042 09:26:12.318086 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6043 09:26:12.321047 ===================================
6044 09:26:12.324559 LPDDR4 DRAM CONFIGURATION
6045 09:26:12.328171 ===================================
6046 09:26:12.328648 EX_ROW_EN[0] = 0x0
6047 09:26:12.331084 EX_ROW_EN[1] = 0x0
6048 09:26:12.334578 LP4Y_EN = 0x0
6049 09:26:12.334976 WORK_FSP = 0x0
6050 09:26:12.338116 WL = 0x2
6051 09:26:12.338595 RL = 0x2
6052 09:26:12.341728 BL = 0x2
6053 09:26:12.342242 RPST = 0x0
6054 09:26:12.344893 RD_PRE = 0x0
6055 09:26:12.345475 WR_PRE = 0x1
6056 09:26:12.347927 WR_PST = 0x0
6057 09:26:12.348407 DBI_WR = 0x0
6058 09:26:12.351375 DBI_RD = 0x0
6059 09:26:12.351768 OTF = 0x1
6060 09:26:12.354770 ===================================
6061 09:26:12.358084 ===================================
6062 09:26:12.361722 ANA top config
6063 09:26:12.364577 ===================================
6064 09:26:12.365062 DLL_ASYNC_EN = 0
6065 09:26:12.368212 ALL_SLAVE_EN = 1
6066 09:26:12.370768 NEW_RANK_MODE = 1
6067 09:26:12.374573 DLL_IDLE_MODE = 1
6068 09:26:12.377974 LP45_APHY_COMB_EN = 1
6069 09:26:12.378499 TX_ODT_DIS = 1
6070 09:26:12.381087 NEW_8X_MODE = 1
6071 09:26:12.384495 ===================================
6072 09:26:12.387450 ===================================
6073 09:26:12.391198 data_rate = 800
6074 09:26:12.394426 CKR = 1
6075 09:26:12.398199 DQ_P2S_RATIO = 4
6076 09:26:12.400994 ===================================
6077 09:26:12.401398 CA_P2S_RATIO = 4
6078 09:26:12.405080 DQ_CA_OPEN = 0
6079 09:26:12.408013 DQ_SEMI_OPEN = 1
6080 09:26:12.411325 CA_SEMI_OPEN = 1
6081 09:26:12.414673 CA_FULL_RATE = 0
6082 09:26:12.418103 DQ_CKDIV4_EN = 0
6083 09:26:12.418501 CA_CKDIV4_EN = 1
6084 09:26:12.421237 CA_PREDIV_EN = 0
6085 09:26:12.424555 PH8_DLY = 0
6086 09:26:12.428153 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6087 09:26:12.431390 DQ_AAMCK_DIV = 0
6088 09:26:12.431825 CA_AAMCK_DIV = 0
6089 09:26:12.434735 CA_ADMCK_DIV = 4
6090 09:26:12.437664 DQ_TRACK_CA_EN = 0
6091 09:26:12.441464 CA_PICK = 800
6092 09:26:12.444847 CA_MCKIO = 400
6093 09:26:12.447909 MCKIO_SEMI = 400
6094 09:26:12.451559 PLL_FREQ = 3016
6095 09:26:12.454897 DQ_UI_PI_RATIO = 32
6096 09:26:12.455344 CA_UI_PI_RATIO = 32
6097 09:26:12.458046 ===================================
6098 09:26:12.461300 ===================================
6099 09:26:12.465052 memory_type:LPDDR4
6100 09:26:12.467834 GP_NUM : 10
6101 09:26:12.468234 SRAM_EN : 1
6102 09:26:12.470927 MD32_EN : 0
6103 09:26:12.474366 ===================================
6104 09:26:12.478158 [ANA_INIT] >>>>>>>>>>>>>>
6105 09:26:12.480909 <<<<<< [CONFIGURE PHASE]: ANA_TX
6106 09:26:12.484550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6107 09:26:12.487694 ===================================
6108 09:26:12.488095 data_rate = 800,PCW = 0X7400
6109 09:26:12.491429 ===================================
6110 09:26:12.494269 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6111 09:26:12.500970 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6112 09:26:12.511451 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6113 09:26:12.518235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6114 09:26:12.521497 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6115 09:26:12.524568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6116 09:26:12.525045 [ANA_INIT] flow start
6117 09:26:12.528298 [ANA_INIT] PLL >>>>>>>>
6118 09:26:12.530944 [ANA_INIT] PLL <<<<<<<<
6119 09:26:12.534606 [ANA_INIT] MIDPI >>>>>>>>
6120 09:26:12.535000 [ANA_INIT] MIDPI <<<<<<<<
6121 09:26:12.538140 [ANA_INIT] DLL >>>>>>>>
6122 09:26:12.538635 [ANA_INIT] flow end
6123 09:26:12.544825 ============ LP4 DIFF to SE enter ============
6124 09:26:12.547681 ============ LP4 DIFF to SE exit ============
6125 09:26:12.550786 [ANA_INIT] <<<<<<<<<<<<<
6126 09:26:12.554908 [Flow] Enable top DCM control >>>>>
6127 09:26:12.558103 [Flow] Enable top DCM control <<<<<
6128 09:26:12.561793 Enable DLL master slave shuffle
6129 09:26:12.564607 ==============================================================
6130 09:26:12.567994 Gating Mode config
6131 09:26:12.571502 ==============================================================
6132 09:26:12.574492 Config description:
6133 09:26:12.584464 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6134 09:26:12.591185 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6135 09:26:12.594883 SELPH_MODE 0: By rank 1: By Phase
6136 09:26:12.601201 ==============================================================
6137 09:26:12.604412 GAT_TRACK_EN = 0
6138 09:26:12.608282 RX_GATING_MODE = 2
6139 09:26:12.611132 RX_GATING_TRACK_MODE = 2
6140 09:26:12.611533 SELPH_MODE = 1
6141 09:26:12.614815 PICG_EARLY_EN = 1
6142 09:26:12.617924 VALID_LAT_VALUE = 1
6143 09:26:12.625039 ==============================================================
6144 09:26:12.628246 Enter into Gating configuration >>>>
6145 09:26:12.631928 Exit from Gating configuration <<<<
6146 09:26:12.634711 Enter into DVFS_PRE_config >>>>>
6147 09:26:12.645079 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6148 09:26:12.648452 Exit from DVFS_PRE_config <<<<<
6149 09:26:12.651267 Enter into PICG configuration >>>>
6150 09:26:12.654822 Exit from PICG configuration <<<<
6151 09:26:12.658297 [RX_INPUT] configuration >>>>>
6152 09:26:12.661656 [RX_INPUT] configuration <<<<<
6153 09:26:12.664595 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6154 09:26:12.671822 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6155 09:26:12.678125 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6156 09:26:12.685151 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6157 09:26:12.688598 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6158 09:26:12.694881 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6159 09:26:12.698114 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6160 09:26:12.705127 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6161 09:26:12.708224 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6162 09:26:12.712065 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6163 09:26:12.714657 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6164 09:26:12.721569 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6165 09:26:12.725383 ===================================
6166 09:26:12.725859 LPDDR4 DRAM CONFIGURATION
6167 09:26:12.728338 ===================================
6168 09:26:12.731989 EX_ROW_EN[0] = 0x0
6169 09:26:12.735336 EX_ROW_EN[1] = 0x0
6170 09:26:12.735814 LP4Y_EN = 0x0
6171 09:26:12.738695 WORK_FSP = 0x0
6172 09:26:12.739175 WL = 0x2
6173 09:26:12.741672 RL = 0x2
6174 09:26:12.742170 BL = 0x2
6175 09:26:12.745455 RPST = 0x0
6176 09:26:12.745935 RD_PRE = 0x0
6177 09:26:12.748194 WR_PRE = 0x1
6178 09:26:12.748594 WR_PST = 0x0
6179 09:26:12.751283 DBI_WR = 0x0
6180 09:26:12.751679 DBI_RD = 0x0
6181 09:26:12.754919 OTF = 0x1
6182 09:26:12.758422 ===================================
6183 09:26:12.762133 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6184 09:26:12.765080 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6185 09:26:12.771710 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6186 09:26:12.775024 ===================================
6187 09:26:12.775422 LPDDR4 DRAM CONFIGURATION
6188 09:26:12.778349 ===================================
6189 09:26:12.781270 EX_ROW_EN[0] = 0x10
6190 09:26:12.781662 EX_ROW_EN[1] = 0x0
6191 09:26:12.784701 LP4Y_EN = 0x0
6192 09:26:12.785092 WORK_FSP = 0x0
6193 09:26:12.788350 WL = 0x2
6194 09:26:12.788835 RL = 0x2
6195 09:26:12.791665 BL = 0x2
6196 09:26:12.795113 RPST = 0x0
6197 09:26:12.795506 RD_PRE = 0x0
6198 09:26:12.798114 WR_PRE = 0x1
6199 09:26:12.798510 WR_PST = 0x0
6200 09:26:12.801354 DBI_WR = 0x0
6201 09:26:12.801744 DBI_RD = 0x0
6202 09:26:12.805140 OTF = 0x1
6203 09:26:12.808237 ===================================
6204 09:26:12.811846 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6205 09:26:12.816890 nWR fixed to 30
6206 09:26:12.820446 [ModeRegInit_LP4] CH0 RK0
6207 09:26:12.820949 [ModeRegInit_LP4] CH0 RK1
6208 09:26:12.823483 [ModeRegInit_LP4] CH1 RK0
6209 09:26:12.826705 [ModeRegInit_LP4] CH1 RK1
6210 09:26:12.827100 match AC timing 19
6211 09:26:12.833415 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6212 09:26:12.837323 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6213 09:26:12.840134 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6214 09:26:12.847081 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6215 09:26:12.850092 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6216 09:26:12.850488 ==
6217 09:26:12.854106 Dram Type= 6, Freq= 0, CH_0, rank 0
6218 09:26:12.857123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6219 09:26:12.857608 ==
6220 09:26:12.864124 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6221 09:26:12.870935 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6222 09:26:12.873645 [CA 0] Center 36 (8~64) winsize 57
6223 09:26:12.877473 [CA 1] Center 36 (8~64) winsize 57
6224 09:26:12.877954 [CA 2] Center 36 (8~64) winsize 57
6225 09:26:12.880662 [CA 3] Center 36 (8~64) winsize 57
6226 09:26:12.883897 [CA 4] Center 36 (8~64) winsize 57
6227 09:26:12.887369 [CA 5] Center 36 (8~64) winsize 57
6228 09:26:12.887846
6229 09:26:12.890183 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6230 09:26:12.890581
6231 09:26:12.896738 [CATrainingPosCal] consider 1 rank data
6232 09:26:12.897219 u2DelayCellTimex100 = 270/100 ps
6233 09:26:12.900147 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 09:26:12.907041 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 09:26:12.910187 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 09:26:12.914235 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 09:26:12.917035 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 09:26:12.920711 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 09:26:12.921197
6240 09:26:12.924031 CA PerBit enable=1, Macro0, CA PI delay=36
6241 09:26:12.924441
6242 09:26:12.926873 [CBTSetCACLKResult] CA Dly = 36
6243 09:26:12.927271 CS Dly: 1 (0~32)
6244 09:26:12.930444 ==
6245 09:26:12.934117 Dram Type= 6, Freq= 0, CH_0, rank 1
6246 09:26:12.937235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6247 09:26:12.937714 ==
6248 09:26:12.941161 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6249 09:26:12.947203 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6250 09:26:12.950977 [CA 0] Center 36 (8~64) winsize 57
6251 09:26:12.954221 [CA 1] Center 36 (8~64) winsize 57
6252 09:26:12.957326 [CA 2] Center 36 (8~64) winsize 57
6253 09:26:12.960845 [CA 3] Center 36 (8~64) winsize 57
6254 09:26:12.964130 [CA 4] Center 36 (8~64) winsize 57
6255 09:26:12.967671 [CA 5] Center 36 (8~64) winsize 57
6256 09:26:12.968150
6257 09:26:12.970971 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6258 09:26:12.971451
6259 09:26:12.973647 [CATrainingPosCal] consider 2 rank data
6260 09:26:12.977273 u2DelayCellTimex100 = 270/100 ps
6261 09:26:12.980464 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 09:26:12.983660 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 09:26:12.987444 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 09:26:12.990621 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 09:26:12.993742 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 09:26:12.997301 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 09:26:13.000608
6268 09:26:13.004098 CA PerBit enable=1, Macro0, CA PI delay=36
6269 09:26:13.004577
6270 09:26:13.006836 [CBTSetCACLKResult] CA Dly = 36
6271 09:26:13.007339 CS Dly: 1 (0~32)
6272 09:26:13.007780
6273 09:26:13.010845 ----->DramcWriteLeveling(PI) begin...
6274 09:26:13.011213 ==
6275 09:26:13.013855 Dram Type= 6, Freq= 0, CH_0, rank 0
6276 09:26:13.017065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 09:26:13.017432 ==
6278 09:26:13.020669 Write leveling (Byte 0): 40 => 8
6279 09:26:13.023710 Write leveling (Byte 1): 32 => 0
6280 09:26:13.027505 DramcWriteLeveling(PI) end<-----
6281 09:26:13.027957
6282 09:26:13.028239 ==
6283 09:26:13.030423 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 09:26:13.034070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 09:26:13.037299 ==
6286 09:26:13.037789 [Gating] SW mode calibration
6287 09:26:13.046943 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6288 09:26:13.050736 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6289 09:26:13.053910 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6290 09:26:13.061091 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6291 09:26:13.064204 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6292 09:26:13.067602 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6293 09:26:13.074452 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 09:26:13.077401 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 09:26:13.080819 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6296 09:26:13.084287 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 09:26:13.090706 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 09:26:13.093880 Total UI for P1: 0, mck2ui 16
6299 09:26:13.097850 best dqsien dly found for B0: ( 0, 14, 24)
6300 09:26:13.100867 Total UI for P1: 0, mck2ui 16
6301 09:26:13.104418 best dqsien dly found for B1: ( 0, 14, 24)
6302 09:26:13.107635 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6303 09:26:13.111222 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6304 09:26:13.111695
6305 09:26:13.114208 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6306 09:26:13.117702 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6307 09:26:13.121264 [Gating] SW calibration Done
6308 09:26:13.121737 ==
6309 09:26:13.124247 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 09:26:13.127411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 09:26:13.127807 ==
6312 09:26:13.131324 RX Vref Scan: 0
6313 09:26:13.131787
6314 09:26:13.132135 RX Vref 0 -> 0, step: 1
6315 09:26:13.134319
6316 09:26:13.134712 RX Delay -410 -> 252, step: 16
6317 09:26:13.141109 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6318 09:26:13.144578 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6319 09:26:13.147420 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6320 09:26:13.151120 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6321 09:26:13.157768 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6322 09:26:13.161285 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6323 09:26:13.164550 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6324 09:26:13.167340 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6325 09:26:13.173932 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6326 09:26:13.177284 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6327 09:26:13.181078 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6328 09:26:13.184440 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6329 09:26:13.190964 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6330 09:26:13.194224 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6331 09:26:13.198149 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6332 09:26:13.201244 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6333 09:26:13.204292 ==
6334 09:26:13.208140 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 09:26:13.211055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 09:26:13.211532 ==
6337 09:26:13.211839 DQS Delay:
6338 09:26:13.214560 DQS0 = 35, DQS1 = 51
6339 09:26:13.214955 DQM Delay:
6340 09:26:13.217701 DQM0 = 7, DQM1 = 11
6341 09:26:13.218154 DQ Delay:
6342 09:26:13.220945 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6343 09:26:13.224177 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6344 09:26:13.227759 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6345 09:26:13.230970 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6346 09:26:13.231408
6347 09:26:13.231741
6348 09:26:13.232052 ==
6349 09:26:13.233822 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 09:26:13.237782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 09:26:13.238256 ==
6352 09:26:13.238574
6353 09:26:13.238857
6354 09:26:13.241103 TX Vref Scan disable
6355 09:26:13.241495 == TX Byte 0 ==
6356 09:26:13.247751 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 09:26:13.251185 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 09:26:13.251579 == TX Byte 1 ==
6359 09:26:13.254253 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6360 09:26:13.260843 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6361 09:26:13.261304 ==
6362 09:26:13.264103 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 09:26:13.267820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 09:26:13.268253 ==
6365 09:26:13.268543
6366 09:26:13.268806
6367 09:26:13.270761 TX Vref Scan disable
6368 09:26:13.271118 == TX Byte 0 ==
6369 09:26:13.277907 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6370 09:26:13.280624 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6371 09:26:13.281028 == TX Byte 1 ==
6372 09:26:13.287331 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6373 09:26:13.290898 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6374 09:26:13.291345
6375 09:26:13.291736 [DATLAT]
6376 09:26:13.294043 Freq=400, CH0 RK0
6377 09:26:13.294461
6378 09:26:13.294772 DATLAT Default: 0xf
6379 09:26:13.297928 0, 0xFFFF, sum = 0
6380 09:26:13.298467 1, 0xFFFF, sum = 0
6381 09:26:13.300745 2, 0xFFFF, sum = 0
6382 09:26:13.301145 3, 0xFFFF, sum = 0
6383 09:26:13.304019 4, 0xFFFF, sum = 0
6384 09:26:13.304386 5, 0xFFFF, sum = 0
6385 09:26:13.307673 6, 0xFFFF, sum = 0
6386 09:26:13.308088 7, 0xFFFF, sum = 0
6387 09:26:13.310882 8, 0xFFFF, sum = 0
6388 09:26:13.311247 9, 0xFFFF, sum = 0
6389 09:26:13.313939 10, 0xFFFF, sum = 0
6390 09:26:13.314365 11, 0xFFFF, sum = 0
6391 09:26:13.317631 12, 0xFFFF, sum = 0
6392 09:26:13.318026 13, 0x0, sum = 1
6393 09:26:13.321024 14, 0x0, sum = 2
6394 09:26:13.321391 15, 0x0, sum = 3
6395 09:26:13.324051 16, 0x0, sum = 4
6396 09:26:13.324453 best_step = 14
6397 09:26:13.324890
6398 09:26:13.325277 ==
6399 09:26:13.327136 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 09:26:13.334160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 09:26:13.334525 ==
6402 09:26:13.334807 RX Vref Scan: 1
6403 09:26:13.335065
6404 09:26:13.337603 RX Vref 0 -> 0, step: 1
6405 09:26:13.337961
6406 09:26:13.341190 RX Delay -343 -> 252, step: 8
6407 09:26:13.341726
6408 09:26:13.344223 Set Vref, RX VrefLevel [Byte0]: 54
6409 09:26:13.347733 [Byte1]: 52
6410 09:26:13.348091
6411 09:26:13.350701 Final RX Vref Byte 0 = 54 to rank0
6412 09:26:13.354260 Final RX Vref Byte 1 = 52 to rank0
6413 09:26:13.357402 Final RX Vref Byte 0 = 54 to rank1
6414 09:26:13.360692 Final RX Vref Byte 1 = 52 to rank1==
6415 09:26:13.363911 Dram Type= 6, Freq= 0, CH_0, rank 0
6416 09:26:13.367551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 09:26:13.371039 ==
6418 09:26:13.371397 DQS Delay:
6419 09:26:13.371679 DQS0 = 44, DQS1 = 60
6420 09:26:13.374474 DQM Delay:
6421 09:26:13.374836 DQM0 = 11, DQM1 = 16
6422 09:26:13.377691 DQ Delay:
6423 09:26:13.378089 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6424 09:26:13.380582 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6425 09:26:13.384256 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6426 09:26:13.387451 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6427 09:26:13.387711
6428 09:26:13.387912
6429 09:26:13.397211 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6430 09:26:13.401158 CH0 RK0: MR19=C0C, MR18=8B5A
6431 09:26:13.404388 CH0_RK0: MR19=0xC0C, MR18=0x8B5A, DQSOSC=392, MR23=63, INC=384, DEC=256
6432 09:26:13.407936 ==
6433 09:26:13.408142 Dram Type= 6, Freq= 0, CH_0, rank 1
6434 09:26:13.414322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 09:26:13.414530 ==
6436 09:26:13.418000 [Gating] SW mode calibration
6437 09:26:13.424213 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6438 09:26:13.427551 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6439 09:26:13.434404 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6440 09:26:13.437782 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6441 09:26:13.441347 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 09:26:13.447418 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 09:26:13.451207 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 09:26:13.454648 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 09:26:13.461077 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 09:26:13.464350 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 09:26:13.467751 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 09:26:13.470670 Total UI for P1: 0, mck2ui 16
6449 09:26:13.474272 best dqsien dly found for B0: ( 0, 14, 24)
6450 09:26:13.477291 Total UI for P1: 0, mck2ui 16
6451 09:26:13.480711 best dqsien dly found for B1: ( 0, 14, 24)
6452 09:26:13.484220 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6453 09:26:13.487278 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6454 09:26:13.487862
6455 09:26:13.494294 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6456 09:26:13.497188 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6457 09:26:13.497562 [Gating] SW calibration Done
6458 09:26:13.500873 ==
6459 09:26:13.501346 Dram Type= 6, Freq= 0, CH_0, rank 1
6460 09:26:13.507722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 09:26:13.508086 ==
6462 09:26:13.508365 RX Vref Scan: 0
6463 09:26:13.508625
6464 09:26:13.511365 RX Vref 0 -> 0, step: 1
6465 09:26:13.511725
6466 09:26:13.514202 RX Delay -410 -> 252, step: 16
6467 09:26:13.517396 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6468 09:26:13.520813 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6469 09:26:13.527409 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6470 09:26:13.530725 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6471 09:26:13.534538 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6472 09:26:13.537795 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6473 09:26:13.544050 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6474 09:26:13.547877 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6475 09:26:13.550845 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6476 09:26:13.553956 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6477 09:26:13.560653 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6478 09:26:13.564467 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6479 09:26:13.567426 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6480 09:26:13.571149 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6481 09:26:13.577854 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6482 09:26:13.580738 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6483 09:26:13.581145 ==
6484 09:26:13.584580 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 09:26:13.587805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 09:26:13.588282 ==
6487 09:26:13.590656 DQS Delay:
6488 09:26:13.591050 DQS0 = 43, DQS1 = 51
6489 09:26:13.594390 DQM Delay:
6490 09:26:13.594783 DQM0 = 11, DQM1 = 10
6491 09:26:13.595091 DQ Delay:
6492 09:26:13.597420 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6493 09:26:13.601180 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6494 09:26:13.604019 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6495 09:26:13.608160 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6496 09:26:13.608638
6497 09:26:13.608949
6498 09:26:13.609233 ==
6499 09:26:13.610762 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 09:26:13.613976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 09:26:13.617881 ==
6502 09:26:13.618426
6503 09:26:13.618743
6504 09:26:13.619024 TX Vref Scan disable
6505 09:26:13.620676 == TX Byte 0 ==
6506 09:26:13.624468 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6507 09:26:13.627901 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6508 09:26:13.631199 == TX Byte 1 ==
6509 09:26:13.634686 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6510 09:26:13.637824 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6511 09:26:13.638241 ==
6512 09:26:13.641735 Dram Type= 6, Freq= 0, CH_0, rank 1
6513 09:26:13.644626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 09:26:13.645029 ==
6515 09:26:13.647667
6516 09:26:13.648103
6517 09:26:13.648429 TX Vref Scan disable
6518 09:26:13.651101 == TX Byte 0 ==
6519 09:26:13.654322 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6520 09:26:13.657825 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6521 09:26:13.661280 == TX Byte 1 ==
6522 09:26:13.664350 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6523 09:26:13.667612 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6524 09:26:13.668093
6525 09:26:13.668405 [DATLAT]
6526 09:26:13.671153 Freq=400, CH0 RK1
6527 09:26:13.671623
6528 09:26:13.671932 DATLAT Default: 0xe
6529 09:26:13.674608 0, 0xFFFF, sum = 0
6530 09:26:13.677914 1, 0xFFFF, sum = 0
6531 09:26:13.678452 2, 0xFFFF, sum = 0
6532 09:26:13.681103 3, 0xFFFF, sum = 0
6533 09:26:13.681587 4, 0xFFFF, sum = 0
6534 09:26:13.684523 5, 0xFFFF, sum = 0
6535 09:26:13.685007 6, 0xFFFF, sum = 0
6536 09:26:13.688283 7, 0xFFFF, sum = 0
6537 09:26:13.688763 8, 0xFFFF, sum = 0
6538 09:26:13.691124 9, 0xFFFF, sum = 0
6539 09:26:13.691609 10, 0xFFFF, sum = 0
6540 09:26:13.694549 11, 0xFFFF, sum = 0
6541 09:26:13.694949 12, 0xFFFF, sum = 0
6542 09:26:13.697443 13, 0x0, sum = 1
6543 09:26:13.697841 14, 0x0, sum = 2
6544 09:26:13.701252 15, 0x0, sum = 3
6545 09:26:13.701809 16, 0x0, sum = 4
6546 09:26:13.704907 best_step = 14
6547 09:26:13.705406
6548 09:26:13.705763 ==
6549 09:26:13.708112 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 09:26:13.710891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 09:26:13.711289 ==
6552 09:26:13.711672 RX Vref Scan: 0
6553 09:26:13.711967
6554 09:26:13.714648 RX Vref 0 -> 0, step: 1
6555 09:26:13.715140
6556 09:26:13.718117 RX Delay -343 -> 252, step: 8
6557 09:26:13.725356 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6558 09:26:13.728741 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6559 09:26:13.731734 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6560 09:26:13.735321 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6561 09:26:13.742446 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6562 09:26:13.745102 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6563 09:26:13.748498 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6564 09:26:13.751620 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6565 09:26:13.758525 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6566 09:26:13.761723 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6567 09:26:13.765336 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6568 09:26:13.768311 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6569 09:26:13.775227 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6570 09:26:13.778144 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6571 09:26:13.781800 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6572 09:26:13.784740 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6573 09:26:13.788602 ==
6574 09:26:13.788885 Dram Type= 6, Freq= 0, CH_0, rank 1
6575 09:26:13.795239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 09:26:13.795413 ==
6577 09:26:13.795544 DQS Delay:
6578 09:26:13.798320 DQS0 = 48, DQS1 = 60
6579 09:26:13.798489 DQM Delay:
6580 09:26:13.802370 DQM0 = 13, DQM1 = 13
6581 09:26:13.802540 DQ Delay:
6582 09:26:13.805274 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6583 09:26:13.808891 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6584 09:26:13.823052 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6585 09:26:13.823272 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6586 09:26:13.823407
6587 09:26:13.823530
6588 09:26:13.823648 [DQSOSCAuto] RK1, (LSB)MR18= 0x9b6d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6589 09:26:13.824971 CH0 RK1: MR19=C0C, MR18=9B6D
6590 09:26:13.831428 CH0_RK1: MR19=0xC0C, MR18=0x9B6D, DQSOSC=390, MR23=63, INC=388, DEC=258
6591 09:26:13.835029 [RxdqsGatingPostProcess] freq 400
6592 09:26:13.838200 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6593 09:26:13.841698 best DQS0 dly(2T, 0.5T) = (0, 10)
6594 09:26:13.844702 best DQS1 dly(2T, 0.5T) = (0, 10)
6595 09:26:13.848356 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6596 09:26:13.851395 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6597 09:26:13.855046 best DQS0 dly(2T, 0.5T) = (0, 10)
6598 09:26:13.858405 best DQS1 dly(2T, 0.5T) = (0, 10)
6599 09:26:13.861566 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6600 09:26:13.865104 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6601 09:26:13.868293 Pre-setting of DQS Precalculation
6602 09:26:13.871654 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6603 09:26:13.871757 ==
6604 09:26:13.874921 Dram Type= 6, Freq= 0, CH_1, rank 0
6605 09:26:13.881859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 09:26:13.882066 ==
6607 09:26:13.885442 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6608 09:26:13.891819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6609 09:26:13.894726 [CA 0] Center 36 (8~64) winsize 57
6610 09:26:13.898287 [CA 1] Center 36 (8~64) winsize 57
6611 09:26:13.901157 [CA 2] Center 36 (8~64) winsize 57
6612 09:26:13.904685 [CA 3] Center 36 (8~64) winsize 57
6613 09:26:13.908169 [CA 4] Center 36 (8~64) winsize 57
6614 09:26:13.911557 [CA 5] Center 36 (8~64) winsize 57
6615 09:26:13.911731
6616 09:26:13.915134 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6617 09:26:13.915348
6618 09:26:13.918456 [CATrainingPosCal] consider 1 rank data
6619 09:26:13.921480 u2DelayCellTimex100 = 270/100 ps
6620 09:26:13.925120 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 09:26:13.928843 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 09:26:13.931725 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 09:26:13.935064 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 09:26:13.938266 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 09:26:13.941889 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 09:26:13.942177
6627 09:26:13.948417 CA PerBit enable=1, Macro0, CA PI delay=36
6628 09:26:13.948811
6629 09:26:13.951975 [CBTSetCACLKResult] CA Dly = 36
6630 09:26:13.952335 CS Dly: 1 (0~32)
6631 09:26:13.952614 ==
6632 09:26:13.955128 Dram Type= 6, Freq= 0, CH_1, rank 1
6633 09:26:13.958568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 09:26:13.959010 ==
6635 09:26:13.965512 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6636 09:26:13.972015 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6637 09:26:13.975335 [CA 0] Center 36 (8~64) winsize 57
6638 09:26:13.978694 [CA 1] Center 36 (8~64) winsize 57
6639 09:26:13.981745 [CA 2] Center 36 (8~64) winsize 57
6640 09:26:13.985079 [CA 3] Center 36 (8~64) winsize 57
6641 09:26:13.985471 [CA 4] Center 36 (8~64) winsize 57
6642 09:26:13.988551 [CA 5] Center 36 (8~64) winsize 57
6643 09:26:13.988943
6644 09:26:13.995091 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6645 09:26:13.995485
6646 09:26:13.998162 [CATrainingPosCal] consider 2 rank data
6647 09:26:14.002448 u2DelayCellTimex100 = 270/100 ps
6648 09:26:14.005100 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 09:26:14.008509 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 09:26:14.011552 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 09:26:14.015115 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 09:26:14.018163 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 09:26:14.021525 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 09:26:14.021908
6655 09:26:14.025402 CA PerBit enable=1, Macro0, CA PI delay=36
6656 09:26:14.025942
6657 09:26:14.028483 [CBTSetCACLKResult] CA Dly = 36
6658 09:26:14.031785 CS Dly: 1 (0~32)
6659 09:26:14.032274
6660 09:26:14.035014 ----->DramcWriteLeveling(PI) begin...
6661 09:26:14.035414 ==
6662 09:26:14.038788 Dram Type= 6, Freq= 0, CH_1, rank 0
6663 09:26:14.041846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 09:26:14.042383 ==
6665 09:26:14.044937 Write leveling (Byte 0): 40 => 8
6666 09:26:14.048623 Write leveling (Byte 1): 40 => 8
6667 09:26:14.051964 DramcWriteLeveling(PI) end<-----
6668 09:26:14.052438
6669 09:26:14.052744 ==
6670 09:26:14.055735 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 09:26:14.058905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 09:26:14.059381 ==
6673 09:26:14.062042 [Gating] SW mode calibration
6674 09:26:14.068581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6675 09:26:14.075404 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6676 09:26:14.078658 0 11 0 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
6677 09:26:14.082132 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6678 09:26:14.088669 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 09:26:14.092040 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6680 09:26:14.095107 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 09:26:14.101855 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 09:26:14.105643 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6683 09:26:14.108599 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 09:26:14.112052 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 09:26:14.115203 Total UI for P1: 0, mck2ui 16
6686 09:26:14.118751 best dqsien dly found for B0: ( 0, 14, 24)
6687 09:26:14.122420 Total UI for P1: 0, mck2ui 16
6688 09:26:14.125376 best dqsien dly found for B1: ( 0, 14, 24)
6689 09:26:14.129131 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6690 09:26:14.134886 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6691 09:26:14.135411
6692 09:26:14.138993 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6693 09:26:14.143712 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6694 09:26:14.145384 [Gating] SW calibration Done
6695 09:26:14.145777 ==
6696 09:26:14.148899 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 09:26:14.152028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 09:26:14.152429 ==
6699 09:26:14.152736 RX Vref Scan: 0
6700 09:26:14.153021
6701 09:26:14.155232 RX Vref 0 -> 0, step: 1
6702 09:26:14.155628
6703 09:26:14.158799 RX Delay -410 -> 252, step: 16
6704 09:26:14.161894 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6705 09:26:14.168574 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6706 09:26:14.171691 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6707 09:26:14.175387 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6708 09:26:14.178364 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6709 09:26:14.182281 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6710 09:26:14.188638 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6711 09:26:14.192226 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6712 09:26:14.195160 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6713 09:26:14.198793 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6714 09:26:14.205714 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6715 09:26:14.208698 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6716 09:26:14.212139 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6717 09:26:14.215693 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6718 09:26:14.222389 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6719 09:26:14.225394 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6720 09:26:14.225795 ==
6721 09:26:14.228899 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 09:26:14.232380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 09:26:14.232892 ==
6724 09:26:14.235819 DQS Delay:
6725 09:26:14.236218 DQS0 = 51, DQS1 = 59
6726 09:26:14.238743 DQM Delay:
6727 09:26:14.239140 DQM0 = 18, DQM1 = 16
6728 09:26:14.239447 DQ Delay:
6729 09:26:14.242337 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6730 09:26:14.245951 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6731 09:26:14.249189 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6732 09:26:14.252898 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6733 09:26:14.253374
6734 09:26:14.253682
6735 09:26:14.253969 ==
6736 09:26:14.255776 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 09:26:14.262479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 09:26:14.262975 ==
6739 09:26:14.263297
6740 09:26:14.263583
6741 09:26:14.263858 TX Vref Scan disable
6742 09:26:14.265812 == TX Byte 0 ==
6743 09:26:14.269059 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 09:26:14.272049 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 09:26:14.275935 == TX Byte 1 ==
6746 09:26:14.278728 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 09:26:14.282539 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 09:26:14.282940 ==
6749 09:26:14.285531 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 09:26:14.292666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 09:26:14.293134 ==
6752 09:26:14.293443
6753 09:26:14.293726
6754 09:26:14.295440 TX Vref Scan disable
6755 09:26:14.295839 == TX Byte 0 ==
6756 09:26:14.299001 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 09:26:14.302324 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 09:26:14.306389 == TX Byte 1 ==
6759 09:26:14.309586 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 09:26:14.312712 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 09:26:14.313216
6762 09:26:14.315424 [DATLAT]
6763 09:26:14.315820 Freq=400, CH1 RK0
6764 09:26:14.316208
6765 09:26:14.319232 DATLAT Default: 0xf
6766 09:26:14.319708 0, 0xFFFF, sum = 0
6767 09:26:14.322350 1, 0xFFFF, sum = 0
6768 09:26:14.322833 2, 0xFFFF, sum = 0
6769 09:26:14.325579 3, 0xFFFF, sum = 0
6770 09:26:14.326109 4, 0xFFFF, sum = 0
6771 09:26:14.328553 5, 0xFFFF, sum = 0
6772 09:26:14.328955 6, 0xFFFF, sum = 0
6773 09:26:14.332684 7, 0xFFFF, sum = 0
6774 09:26:14.333171 8, 0xFFFF, sum = 0
6775 09:26:14.335345 9, 0xFFFF, sum = 0
6776 09:26:14.338943 10, 0xFFFF, sum = 0
6777 09:26:14.339430 11, 0xFFFF, sum = 0
6778 09:26:14.342203 12, 0xFFFF, sum = 0
6779 09:26:14.342687 13, 0x0, sum = 1
6780 09:26:14.345844 14, 0x0, sum = 2
6781 09:26:14.346481 15, 0x0, sum = 3
6782 09:26:14.346813 16, 0x0, sum = 4
6783 09:26:14.349103 best_step = 14
6784 09:26:14.349506
6785 09:26:14.349948 ==
6786 09:26:14.352004 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 09:26:14.355803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 09:26:14.356279 ==
6789 09:26:14.359084 RX Vref Scan: 1
6790 09:26:14.359524
6791 09:26:14.362438 RX Vref 0 -> 0, step: 1
6792 09:26:14.362913
6793 09:26:14.363220 RX Delay -359 -> 252, step: 8
6794 09:26:14.363626
6795 09:26:14.365460 Set Vref, RX VrefLevel [Byte0]: 60
6796 09:26:14.368520 [Byte1]: 53
6797 09:26:14.373863
6798 09:26:14.374291 Final RX Vref Byte 0 = 60 to rank0
6799 09:26:14.377456 Final RX Vref Byte 1 = 53 to rank0
6800 09:26:14.380654 Final RX Vref Byte 0 = 60 to rank1
6801 09:26:14.384095 Final RX Vref Byte 1 = 53 to rank1==
6802 09:26:14.387493 Dram Type= 6, Freq= 0, CH_1, rank 0
6803 09:26:14.394025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 09:26:14.394427 ==
6805 09:26:14.394742 DQS Delay:
6806 09:26:14.397302 DQS0 = 52, DQS1 = 60
6807 09:26:14.397698 DQM Delay:
6808 09:26:14.398055 DQM0 = 16, DQM1 = 12
6809 09:26:14.401247 DQ Delay:
6810 09:26:14.403952 DQ0 =20, DQ1 =12, DQ2 =0, DQ3 =16
6811 09:26:14.404361 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =16
6812 09:26:14.407532 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6813 09:26:14.410790 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6814 09:26:14.411188
6815 09:26:14.413840
6816 09:26:14.421053 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d33, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6817 09:26:14.424160 CH1 RK0: MR19=C0C, MR18=8D33
6818 09:26:14.430678 CH1_RK0: MR19=0xC0C, MR18=0x8D33, DQSOSC=392, MR23=63, INC=384, DEC=256
6819 09:26:14.431067 ==
6820 09:26:14.433722 Dram Type= 6, Freq= 0, CH_1, rank 1
6821 09:26:14.437650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 09:26:14.438092 ==
6823 09:26:14.440779 [Gating] SW mode calibration
6824 09:26:14.447464 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6825 09:26:14.450658 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6826 09:26:14.457072 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6827 09:26:14.460839 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6828 09:26:14.464153 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6829 09:26:14.470949 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6830 09:26:14.474089 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 09:26:14.477737 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 09:26:14.484571 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6833 09:26:14.487526 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 09:26:14.490826 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 09:26:14.494161 Total UI for P1: 0, mck2ui 16
6836 09:26:14.497546 best dqsien dly found for B0: ( 0, 14, 24)
6837 09:26:14.500709 Total UI for P1: 0, mck2ui 16
6838 09:26:14.504425 best dqsien dly found for B1: ( 0, 14, 24)
6839 09:26:14.507398 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6840 09:26:14.511103 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6841 09:26:14.511464
6842 09:26:14.517124 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6843 09:26:14.520404 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6844 09:26:14.520767 [Gating] SW calibration Done
6845 09:26:14.524250 ==
6846 09:26:14.527465 Dram Type= 6, Freq= 0, CH_1, rank 1
6847 09:26:14.530637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 09:26:14.530996 ==
6849 09:26:14.531274 RX Vref Scan: 0
6850 09:26:14.531636
6851 09:26:14.534123 RX Vref 0 -> 0, step: 1
6852 09:26:14.534491
6853 09:26:14.537488 RX Delay -410 -> 252, step: 16
6854 09:26:14.541301 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6855 09:26:14.544396 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6856 09:26:14.550993 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6857 09:26:14.554459 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6858 09:26:14.557742 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6859 09:26:14.561227 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6860 09:26:14.567906 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6861 09:26:14.570779 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6862 09:26:14.574555 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6863 09:26:14.577549 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6864 09:26:14.584518 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6865 09:26:14.587932 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6866 09:26:14.590903 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6867 09:26:14.594530 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6868 09:26:14.601279 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6869 09:26:14.604432 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6870 09:26:14.605014 ==
6871 09:26:14.607824 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 09:26:14.611562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 09:26:14.612047 ==
6874 09:26:14.614467 DQS Delay:
6875 09:26:14.615063 DQS0 = 51, DQS1 = 59
6876 09:26:14.617769 DQM Delay:
6877 09:26:14.618295 DQM0 = 17, DQM1 = 20
6878 09:26:14.618611 DQ Delay:
6879 09:26:14.621050 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6880 09:26:14.624543 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6881 09:26:14.628016 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6882 09:26:14.631463 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6883 09:26:14.631948
6884 09:26:14.632256
6885 09:26:14.632537 ==
6886 09:26:14.634176 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 09:26:14.641820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 09:26:14.642358 ==
6889 09:26:14.642684
6890 09:26:14.642969
6891 09:26:14.643241 TX Vref Scan disable
6892 09:26:14.644525 == TX Byte 0 ==
6893 09:26:14.647755 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6894 09:26:14.651588 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6895 09:26:14.654462 == TX Byte 1 ==
6896 09:26:14.658068 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6897 09:26:14.660855 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6898 09:26:14.661255 ==
6899 09:26:14.664909 Dram Type= 6, Freq= 0, CH_1, rank 1
6900 09:26:14.671459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 09:26:14.671951 ==
6902 09:26:14.672264
6903 09:26:14.672622
6904 09:26:14.672907 TX Vref Scan disable
6905 09:26:14.674108 == TX Byte 0 ==
6906 09:26:14.677890 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6907 09:26:14.681247 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6908 09:26:14.684733 == TX Byte 1 ==
6909 09:26:14.687750 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6910 09:26:14.691663 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6911 09:26:14.692141
6912 09:26:14.694782 [DATLAT]
6913 09:26:14.695174 Freq=400, CH1 RK1
6914 09:26:14.695482
6915 09:26:14.697595 DATLAT Default: 0xe
6916 09:26:14.698011 0, 0xFFFF, sum = 0
6917 09:26:14.701134 1, 0xFFFF, sum = 0
6918 09:26:14.701528 2, 0xFFFF, sum = 0
6919 09:26:14.705103 3, 0xFFFF, sum = 0
6920 09:26:14.705590 4, 0xFFFF, sum = 0
6921 09:26:14.708338 5, 0xFFFF, sum = 0
6922 09:26:14.708823 6, 0xFFFF, sum = 0
6923 09:26:14.711434 7, 0xFFFF, sum = 0
6924 09:26:14.711913 8, 0xFFFF, sum = 0
6925 09:26:14.714737 9, 0xFFFF, sum = 0
6926 09:26:14.715134 10, 0xFFFF, sum = 0
6927 09:26:14.717970 11, 0xFFFF, sum = 0
6928 09:26:14.718396 12, 0xFFFF, sum = 0
6929 09:26:14.720845 13, 0x0, sum = 1
6930 09:26:14.721242 14, 0x0, sum = 2
6931 09:26:14.724359 15, 0x0, sum = 3
6932 09:26:14.724757 16, 0x0, sum = 4
6933 09:26:14.727712 best_step = 14
6934 09:26:14.728103
6935 09:26:14.728408 ==
6936 09:26:14.731478 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 09:26:14.734549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 09:26:14.734946 ==
6939 09:26:14.737803 RX Vref Scan: 0
6940 09:26:14.738243
6941 09:26:14.738552 RX Vref 0 -> 0, step: 1
6942 09:26:14.738839
6943 09:26:14.741149 RX Delay -359 -> 252, step: 8
6944 09:26:14.749284 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6945 09:26:14.752341 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6946 09:26:14.755690 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6947 09:26:14.758967 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6948 09:26:14.765619 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6949 09:26:14.769337 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6950 09:26:14.772319 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6951 09:26:14.776085 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6952 09:26:14.782495 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6953 09:26:14.785735 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6954 09:26:14.789307 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6955 09:26:14.792452 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6956 09:26:14.799035 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6957 09:26:14.802505 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6958 09:26:14.805777 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6959 09:26:14.809480 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6960 09:26:14.812470 ==
6961 09:26:14.812980 Dram Type= 6, Freq= 0, CH_1, rank 1
6962 09:26:14.819515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6963 09:26:14.819913 ==
6964 09:26:14.820219 DQS Delay:
6965 09:26:14.822562 DQS0 = 52, DQS1 = 56
6966 09:26:14.822955 DQM Delay:
6967 09:26:14.826153 DQM0 = 13, DQM1 = 8
6968 09:26:14.826592 DQ Delay:
6969 09:26:14.829500 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6970 09:26:14.833148 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6971 09:26:14.833628 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6972 09:26:14.839348 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6973 09:26:14.839837
6974 09:26:14.840148
6975 09:26:14.846010 [DQSOSCAuto] RK1, (LSB)MR18= 0x7f94, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 393 ps
6976 09:26:14.849831 CH1 RK1: MR19=C0C, MR18=7F94
6977 09:26:14.855921 CH1_RK1: MR19=0xC0C, MR18=0x7F94, DQSOSC=391, MR23=63, INC=386, DEC=257
6978 09:26:14.859425 [RxdqsGatingPostProcess] freq 400
6979 09:26:14.862701 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6980 09:26:14.866526 best DQS0 dly(2T, 0.5T) = (0, 10)
6981 09:26:14.869858 best DQS1 dly(2T, 0.5T) = (0, 10)
6982 09:26:14.872702 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6983 09:26:14.875737 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6984 09:26:14.879420 best DQS0 dly(2T, 0.5T) = (0, 10)
6985 09:26:14.882825 best DQS1 dly(2T, 0.5T) = (0, 10)
6986 09:26:14.886039 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6987 09:26:14.889449 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6988 09:26:14.892424 Pre-setting of DQS Precalculation
6989 09:26:14.896022 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6990 09:26:14.902927 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6991 09:26:14.909397 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6992 09:26:14.912742
6993 09:26:14.913151
6994 09:26:14.913544 [Calibration Summary] 800 Mbps
6995 09:26:14.915836 CH 0, Rank 0
6996 09:26:14.916312 SW Impedance : PASS
6997 09:26:14.919604 DUTY Scan : NO K
6998 09:26:14.922829 ZQ Calibration : PASS
6999 09:26:14.923258 Jitter Meter : NO K
7000 09:26:14.926024 CBT Training : PASS
7001 09:26:14.929572 Write leveling : PASS
7002 09:26:14.929969 RX DQS gating : PASS
7003 09:26:14.932920 RX DQ/DQS(RDDQC) : PASS
7004 09:26:14.936126 TX DQ/DQS : PASS
7005 09:26:14.936523 RX DATLAT : PASS
7006 09:26:14.939297 RX DQ/DQS(Engine): PASS
7007 09:26:14.943188 TX OE : NO K
7008 09:26:14.943582 All Pass.
7009 09:26:14.943888
7010 09:26:14.944171 CH 0, Rank 1
7011 09:26:14.946453 SW Impedance : PASS
7012 09:26:14.946849 DUTY Scan : NO K
7013 09:26:14.949540 ZQ Calibration : PASS
7014 09:26:14.953627 Jitter Meter : NO K
7015 09:26:14.954174 CBT Training : PASS
7016 09:26:14.956517 Write leveling : NO K
7017 09:26:14.959772 RX DQS gating : PASS
7018 09:26:14.960233 RX DQ/DQS(RDDQC) : PASS
7019 09:26:14.962845 TX DQ/DQS : PASS
7020 09:26:14.966207 RX DATLAT : PASS
7021 09:26:14.966660 RX DQ/DQS(Engine): PASS
7022 09:26:14.969299 TX OE : NO K
7023 09:26:14.969700 All Pass.
7024 09:26:14.970189
7025 09:26:14.972879 CH 1, Rank 0
7026 09:26:14.973343 SW Impedance : PASS
7027 09:26:14.975731 DUTY Scan : NO K
7028 09:26:14.979430 ZQ Calibration : PASS
7029 09:26:14.979506 Jitter Meter : NO K
7030 09:26:14.982941 CBT Training : PASS
7031 09:26:14.985561 Write leveling : PASS
7032 09:26:14.985638 RX DQS gating : PASS
7033 09:26:14.989278 RX DQ/DQS(RDDQC) : PASS
7034 09:26:14.989355 TX DQ/DQS : PASS
7035 09:26:14.992910 RX DATLAT : PASS
7036 09:26:14.996108 RX DQ/DQS(Engine): PASS
7037 09:26:14.996216 TX OE : NO K
7038 09:26:14.999291 All Pass.
7039 09:26:14.999399
7040 09:26:14.999500 CH 1, Rank 1
7041 09:26:15.002731 SW Impedance : PASS
7042 09:26:15.002850 DUTY Scan : NO K
7043 09:26:15.005906 ZQ Calibration : PASS
7044 09:26:15.009374 Jitter Meter : NO K
7045 09:26:15.009488 CBT Training : PASS
7046 09:26:15.012501 Write leveling : NO K
7047 09:26:15.016236 RX DQS gating : PASS
7048 09:26:15.016381 RX DQ/DQS(RDDQC) : PASS
7049 09:26:15.019750 TX DQ/DQS : PASS
7050 09:26:15.022856 RX DATLAT : PASS
7051 09:26:15.023334 RX DQ/DQS(Engine): PASS
7052 09:26:15.026270 TX OE : NO K
7053 09:26:15.026629 All Pass.
7054 09:26:15.027110
7055 09:26:15.029512 DramC Write-DBI off
7056 09:26:15.032989 PER_BANK_REFRESH: Hybrid Mode
7057 09:26:15.033356 TX_TRACKING: ON
7058 09:26:15.042987 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7059 09:26:15.046357 [FAST_K] Save calibration result to emmc
7060 09:26:15.050339 dramc_set_vcore_voltage set vcore to 725000
7061 09:26:15.050700 Read voltage for 1600, 0
7062 09:26:15.053384 Vio18 = 0
7063 09:26:15.053744 Vcore = 725000
7064 09:26:15.054053 Vdram = 0
7065 09:26:15.056665 Vddq = 0
7066 09:26:15.057023 Vmddr = 0
7067 09:26:15.059803 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7068 09:26:15.066901 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7069 09:26:15.070164 MEM_TYPE=3, freq_sel=13
7070 09:26:15.073040 sv_algorithm_assistance_LP4_3733
7071 09:26:15.076695 ============ PULL DRAM RESETB DOWN ============
7072 09:26:15.080295 ========== PULL DRAM RESETB DOWN end =========
7073 09:26:15.086429 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7074 09:26:15.086866 ===================================
7075 09:26:15.089883 LPDDR4 DRAM CONFIGURATION
7076 09:26:15.093529 ===================================
7077 09:26:15.096708 EX_ROW_EN[0] = 0x0
7078 09:26:15.097072 EX_ROW_EN[1] = 0x0
7079 09:26:15.100000 LP4Y_EN = 0x0
7080 09:26:15.100455 WORK_FSP = 0x1
7081 09:26:15.103172 WL = 0x5
7082 09:26:15.103549 RL = 0x5
7083 09:26:15.107015 BL = 0x2
7084 09:26:15.107378 RPST = 0x0
7085 09:26:15.109963 RD_PRE = 0x0
7086 09:26:15.113347 WR_PRE = 0x1
7087 09:26:15.113712 WR_PST = 0x1
7088 09:26:15.116429 DBI_WR = 0x0
7089 09:26:15.116792 DBI_RD = 0x0
7090 09:26:15.120051 OTF = 0x1
7091 09:26:15.122921 ===================================
7092 09:26:15.126497 ===================================
7093 09:26:15.126866 ANA top config
7094 09:26:15.129935 ===================================
7095 09:26:15.133566 DLL_ASYNC_EN = 0
7096 09:26:15.136852 ALL_SLAVE_EN = 0
7097 09:26:15.137325 NEW_RANK_MODE = 1
7098 09:26:15.140092 DLL_IDLE_MODE = 1
7099 09:26:15.143228 LP45_APHY_COMB_EN = 1
7100 09:26:15.146361 TX_ODT_DIS = 0
7101 09:26:15.146821 NEW_8X_MODE = 1
7102 09:26:15.149705 ===================================
7103 09:26:15.152944 ===================================
7104 09:26:15.156712 data_rate = 3200
7105 09:26:15.159912 CKR = 1
7106 09:26:15.163068 DQ_P2S_RATIO = 8
7107 09:26:15.166324 ===================================
7108 09:26:15.170028 CA_P2S_RATIO = 8
7109 09:26:15.173167 DQ_CA_OPEN = 0
7110 09:26:15.173529 DQ_SEMI_OPEN = 0
7111 09:26:15.176806 CA_SEMI_OPEN = 0
7112 09:26:15.179931 CA_FULL_RATE = 0
7113 09:26:15.183318 DQ_CKDIV4_EN = 0
7114 09:26:15.186165 CA_CKDIV4_EN = 0
7115 09:26:15.190091 CA_PREDIV_EN = 0
7116 09:26:15.190459 PH8_DLY = 12
7117 09:26:15.193200 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7118 09:26:15.196154 DQ_AAMCK_DIV = 4
7119 09:26:15.200345 CA_AAMCK_DIV = 4
7120 09:26:15.203533 CA_ADMCK_DIV = 4
7121 09:26:15.206763 DQ_TRACK_CA_EN = 0
7122 09:26:15.207163 CA_PICK = 1600
7123 09:26:15.209929 CA_MCKIO = 1600
7124 09:26:15.213767 MCKIO_SEMI = 0
7125 09:26:15.216605 PLL_FREQ = 3068
7126 09:26:15.220153 DQ_UI_PI_RATIO = 32
7127 09:26:15.223653 CA_UI_PI_RATIO = 0
7128 09:26:15.226559 ===================================
7129 09:26:15.230552 ===================================
7130 09:26:15.231090 memory_type:LPDDR4
7131 09:26:15.233485 GP_NUM : 10
7132 09:26:15.236894 SRAM_EN : 1
7133 09:26:15.237375 MD32_EN : 0
7134 09:26:15.240152 ===================================
7135 09:26:15.243241 [ANA_INIT] >>>>>>>>>>>>>>
7136 09:26:15.246684 <<<<<< [CONFIGURE PHASE]: ANA_TX
7137 09:26:15.249576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7138 09:26:15.253403 ===================================
7139 09:26:15.257027 data_rate = 3200,PCW = 0X7600
7140 09:26:15.259711 ===================================
7141 09:26:15.263384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7142 09:26:15.266399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7143 09:26:15.273332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7144 09:26:15.276694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7145 09:26:15.279703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7146 09:26:15.283553 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7147 09:26:15.286578 [ANA_INIT] flow start
7148 09:26:15.290418 [ANA_INIT] PLL >>>>>>>>
7149 09:26:15.290786 [ANA_INIT] PLL <<<<<<<<
7150 09:26:15.293391 [ANA_INIT] MIDPI >>>>>>>>
7151 09:26:15.296525 [ANA_INIT] MIDPI <<<<<<<<
7152 09:26:15.296968 [ANA_INIT] DLL >>>>>>>>
7153 09:26:15.300394 [ANA_INIT] DLL <<<<<<<<
7154 09:26:15.303296 [ANA_INIT] flow end
7155 09:26:15.306986 ============ LP4 DIFF to SE enter ============
7156 09:26:15.310075 ============ LP4 DIFF to SE exit ============
7157 09:26:15.313225 [ANA_INIT] <<<<<<<<<<<<<
7158 09:26:15.317056 [Flow] Enable top DCM control >>>>>
7159 09:26:15.319924 [Flow] Enable top DCM control <<<<<
7160 09:26:15.323665 Enable DLL master slave shuffle
7161 09:26:15.326797 ==============================================================
7162 09:26:15.330069 Gating Mode config
7163 09:26:15.336361 ==============================================================
7164 09:26:15.336871 Config description:
7165 09:26:15.346971 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7166 09:26:15.353692 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7167 09:26:15.356658 SELPH_MODE 0: By rank 1: By Phase
7168 09:26:15.363481 ==============================================================
7169 09:26:15.366746 GAT_TRACK_EN = 1
7170 09:26:15.369679 RX_GATING_MODE = 2
7171 09:26:15.373272 RX_GATING_TRACK_MODE = 2
7172 09:26:15.376898 SELPH_MODE = 1
7173 09:26:15.380303 PICG_EARLY_EN = 1
7174 09:26:15.383521 VALID_LAT_VALUE = 1
7175 09:26:15.386704 ==============================================================
7176 09:26:15.389776 Enter into Gating configuration >>>>
7177 09:26:15.393340 Exit from Gating configuration <<<<
7178 09:26:15.397007 Enter into DVFS_PRE_config >>>>>
7179 09:26:15.406805 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7180 09:26:15.410016 Exit from DVFS_PRE_config <<<<<
7181 09:26:15.413841 Enter into PICG configuration >>>>
7182 09:26:15.416734 Exit from PICG configuration <<<<
7183 09:26:15.420649 [RX_INPUT] configuration >>>>>
7184 09:26:15.423349 [RX_INPUT] configuration <<<<<
7185 09:26:15.430164 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7186 09:26:15.433535 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7187 09:26:15.440361 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7188 09:26:15.447370 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7189 09:26:15.453681 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7190 09:26:15.460447 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7191 09:26:15.463716 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7192 09:26:15.467329 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7193 09:26:15.469946 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7194 09:26:15.473536 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7195 09:26:15.480229 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7196 09:26:15.483275 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7197 09:26:15.486450 ===================================
7198 09:26:15.490115 LPDDR4 DRAM CONFIGURATION
7199 09:26:15.493086 ===================================
7200 09:26:15.493483 EX_ROW_EN[0] = 0x0
7201 09:26:15.496684 EX_ROW_EN[1] = 0x0
7202 09:26:15.497081 LP4Y_EN = 0x0
7203 09:26:15.500136 WORK_FSP = 0x1
7204 09:26:15.500531 WL = 0x5
7205 09:26:15.503410 RL = 0x5
7206 09:26:15.503802 BL = 0x2
7207 09:26:15.506540 RPST = 0x0
7208 09:26:15.506933 RD_PRE = 0x0
7209 09:26:15.510137 WR_PRE = 0x1
7210 09:26:15.510532 WR_PST = 0x1
7211 09:26:15.513596 DBI_WR = 0x0
7212 09:26:15.516623 DBI_RD = 0x0
7213 09:26:15.517162 OTF = 0x1
7214 09:26:15.519978 ===================================
7215 09:26:15.523361 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7216 09:26:15.526944 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7217 09:26:15.533403 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7218 09:26:15.536617 ===================================
7219 09:26:15.537038 LPDDR4 DRAM CONFIGURATION
7220 09:26:15.540465 ===================================
7221 09:26:15.543638 EX_ROW_EN[0] = 0x10
7222 09:26:15.546676 EX_ROW_EN[1] = 0x0
7223 09:26:15.547072 LP4Y_EN = 0x0
7224 09:26:15.550426 WORK_FSP = 0x1
7225 09:26:15.550847 WL = 0x5
7226 09:26:15.553549 RL = 0x5
7227 09:26:15.554118 BL = 0x2
7228 09:26:15.556901 RPST = 0x0
7229 09:26:15.557401 RD_PRE = 0x0
7230 09:26:15.560134 WR_PRE = 0x1
7231 09:26:15.560649 WR_PST = 0x1
7232 09:26:15.563330 DBI_WR = 0x0
7233 09:26:15.563807 DBI_RD = 0x0
7234 09:26:15.566932 OTF = 0x1
7235 09:26:15.569854 ===================================
7236 09:26:15.576506 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7237 09:26:15.576968 ==
7238 09:26:15.579970 Dram Type= 6, Freq= 0, CH_0, rank 0
7239 09:26:15.583500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7240 09:26:15.584045 ==
7241 09:26:15.586457 [Duty_Offset_Calibration]
7242 09:26:15.586861 B0:2 B1:-1 CA:1
7243 09:26:15.587256
7244 09:26:15.590073 [DutyScan_Calibration_Flow] k_type=0
7245 09:26:15.599860
7246 09:26:15.600223 ==CLK 0==
7247 09:26:15.603676 Final CLK duty delay cell = -4
7248 09:26:15.606783 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7249 09:26:15.610013 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7250 09:26:15.613090 [-4] AVG Duty = 4922%(X100)
7251 09:26:15.613449
7252 09:26:15.616324 CH0 CLK Duty spec in!! Max-Min= 156%
7253 09:26:15.620117 [DutyScan_Calibration_Flow] ====Done====
7254 09:26:15.620480
7255 09:26:15.623103 [DutyScan_Calibration_Flow] k_type=1
7256 09:26:15.639676
7257 09:26:15.640037 ==DQS 0 ==
7258 09:26:15.642458 Final DQS duty delay cell = 0
7259 09:26:15.645690 [0] MAX Duty = 5125%(X100), DQS PI = 20
7260 09:26:15.649417 [0] MIN Duty = 5000%(X100), DQS PI = 14
7261 09:26:15.652650 [0] AVG Duty = 5062%(X100)
7262 09:26:15.653263
7263 09:26:15.653832 ==DQS 1 ==
7264 09:26:15.655945 Final DQS duty delay cell = -4
7265 09:26:15.659263 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7266 09:26:15.662377 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7267 09:26:15.666154 [-4] AVG Duty = 5046%(X100)
7268 09:26:15.666410
7269 09:26:15.669261 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7270 09:26:15.669518
7271 09:26:15.672402 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7272 09:26:15.676274 [DutyScan_Calibration_Flow] ====Done====
7273 09:26:15.676547
7274 09:26:15.679128 [DutyScan_Calibration_Flow] k_type=3
7275 09:26:15.696374
7276 09:26:15.696616 ==DQM 0 ==
7277 09:26:15.699797 Final DQM duty delay cell = 0
7278 09:26:15.703611 [0] MAX Duty = 5000%(X100), DQS PI = 20
7279 09:26:15.706584 [0] MIN Duty = 4844%(X100), DQS PI = 8
7280 09:26:15.706766 [0] AVG Duty = 4922%(X100)
7281 09:26:15.707037
7282 09:26:15.709972 ==DQM 1 ==
7283 09:26:15.713265 Final DQM duty delay cell = 0
7284 09:26:15.716534 [0] MAX Duty = 5187%(X100), DQS PI = 58
7285 09:26:15.720306 [0] MIN Duty = 4938%(X100), DQS PI = 20
7286 09:26:15.720641 [0] AVG Duty = 5062%(X100)
7287 09:26:15.720912
7288 09:26:15.727303 CH0 DQM 0 Duty spec in!! Max-Min= 156%
7289 09:26:15.727643
7290 09:26:15.730525 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7291 09:26:15.733625 [DutyScan_Calibration_Flow] ====Done====
7292 09:26:15.734092
7293 09:26:15.736722 [DutyScan_Calibration_Flow] k_type=2
7294 09:26:15.753579
7295 09:26:15.753908 ==DQ 0 ==
7296 09:26:15.756856 Final DQ duty delay cell = 0
7297 09:26:15.760733 [0] MAX Duty = 5156%(X100), DQS PI = 0
7298 09:26:15.763978 [0] MIN Duty = 5031%(X100), DQS PI = 4
7299 09:26:15.764323 [0] AVG Duty = 5093%(X100)
7300 09:26:15.764559
7301 09:26:15.766994 ==DQ 1 ==
7302 09:26:15.770344 Final DQ duty delay cell = 0
7303 09:26:15.773624 [0] MAX Duty = 5031%(X100), DQS PI = 30
7304 09:26:15.777288 [0] MIN Duty = 4907%(X100), DQS PI = 18
7305 09:26:15.777591 [0] AVG Duty = 4969%(X100)
7306 09:26:15.777830
7307 09:26:15.780448 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7308 09:26:15.780748
7309 09:26:15.783687 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7310 09:26:15.790768 [DutyScan_Calibration_Flow] ====Done====
7311 09:26:15.791083 ==
7312 09:26:15.794075 Dram Type= 6, Freq= 0, CH_1, rank 0
7313 09:26:15.797359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7314 09:26:15.797662 ==
7315 09:26:15.800510 [Duty_Offset_Calibration]
7316 09:26:15.800809 B0:1 B1:1 CA:2
7317 09:26:15.801044
7318 09:26:15.803517 [DutyScan_Calibration_Flow] k_type=0
7319 09:26:15.813658
7320 09:26:15.813958 ==CLK 0==
7321 09:26:15.816894 Final CLK duty delay cell = 0
7322 09:26:15.820687 [0] MAX Duty = 5187%(X100), DQS PI = 24
7323 09:26:15.824003 [0] MIN Duty = 4938%(X100), DQS PI = 48
7324 09:26:15.824303 [0] AVG Duty = 5062%(X100)
7325 09:26:15.827003
7326 09:26:15.830188 CH1 CLK Duty spec in!! Max-Min= 249%
7327 09:26:15.833968 [DutyScan_Calibration_Flow] ====Done====
7328 09:26:15.834295
7329 09:26:15.837201 [DutyScan_Calibration_Flow] k_type=1
7330 09:26:15.853157
7331 09:26:15.853470 ==DQS 0 ==
7332 09:26:15.856706 Final DQS duty delay cell = 0
7333 09:26:15.859831 [0] MAX Duty = 5062%(X100), DQS PI = 22
7334 09:26:15.863542 [0] MIN Duty = 4813%(X100), DQS PI = 50
7335 09:26:15.863845 [0] AVG Duty = 4937%(X100)
7336 09:26:15.866841
7337 09:26:15.867141 ==DQS 1 ==
7338 09:26:15.869915 Final DQS duty delay cell = 0
7339 09:26:15.873738 [0] MAX Duty = 5031%(X100), DQS PI = 56
7340 09:26:15.877126 [0] MIN Duty = 4938%(X100), DQS PI = 12
7341 09:26:15.879942 [0] AVG Duty = 4984%(X100)
7342 09:26:15.880242
7343 09:26:15.883610 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7344 09:26:15.883917
7345 09:26:15.886845 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7346 09:26:15.889924 [DutyScan_Calibration_Flow] ====Done====
7347 09:26:15.890261
7348 09:26:15.893285 [DutyScan_Calibration_Flow] k_type=3
7349 09:26:15.910456
7350 09:26:15.910832 ==DQM 0 ==
7351 09:26:15.914315 Final DQM duty delay cell = 0
7352 09:26:15.917549 [0] MAX Duty = 5124%(X100), DQS PI = 20
7353 09:26:15.920312 [0] MIN Duty = 4844%(X100), DQS PI = 50
7354 09:26:15.923868 [0] AVG Duty = 4984%(X100)
7355 09:26:15.924260
7356 09:26:15.924564 ==DQM 1 ==
7357 09:26:15.926824 Final DQM duty delay cell = 0
7358 09:26:15.930491 [0] MAX Duty = 5156%(X100), DQS PI = 60
7359 09:26:15.934399 [0] MIN Duty = 4907%(X100), DQS PI = 18
7360 09:26:15.937094 [0] AVG Duty = 5031%(X100)
7361 09:26:15.937488
7362 09:26:15.940488 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7363 09:26:15.941054
7364 09:26:15.943568 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7365 09:26:15.947464 [DutyScan_Calibration_Flow] ====Done====
7366 09:26:15.947866
7367 09:26:15.950473 [DutyScan_Calibration_Flow] k_type=2
7368 09:26:15.967306
7369 09:26:15.967708 ==DQ 0 ==
7370 09:26:15.971167 Final DQ duty delay cell = 0
7371 09:26:15.974436 [0] MAX Duty = 5125%(X100), DQS PI = 20
7372 09:26:15.977200 [0] MIN Duty = 4907%(X100), DQS PI = 52
7373 09:26:15.977610 [0] AVG Duty = 5016%(X100)
7374 09:26:15.978152
7375 09:26:15.980990 ==DQ 1 ==
7376 09:26:15.984329 Final DQ duty delay cell = 0
7377 09:26:15.987638 [0] MAX Duty = 5093%(X100), DQS PI = 6
7378 09:26:15.990572 [0] MIN Duty = 5031%(X100), DQS PI = 0
7379 09:26:15.990979 [0] AVG Duty = 5062%(X100)
7380 09:26:15.991370
7381 09:26:15.994252 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7382 09:26:15.994657
7383 09:26:15.997193 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7384 09:26:16.004124 [DutyScan_Calibration_Flow] ====Done====
7385 09:26:16.007110 nWR fixed to 30
7386 09:26:16.007520 [ModeRegInit_LP4] CH0 RK0
7387 09:26:16.010979 [ModeRegInit_LP4] CH0 RK1
7388 09:26:16.014083 [ModeRegInit_LP4] CH1 RK0
7389 09:26:16.014489 [ModeRegInit_LP4] CH1 RK1
7390 09:26:16.017260 match AC timing 5
7391 09:26:16.020897 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7392 09:26:16.024122 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7393 09:26:16.030813 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7394 09:26:16.033936 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7395 09:26:16.040490 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7396 09:26:16.040901 [MiockJmeterHQA]
7397 09:26:16.041295
7398 09:26:16.044224 [DramcMiockJmeter] u1RxGatingPI = 0
7399 09:26:16.044782 0 : 4252, 4027
7400 09:26:16.047504 4 : 4257, 4029
7401 09:26:16.047917 8 : 4363, 4138
7402 09:26:16.050707 12 : 4253, 4027
7403 09:26:16.051173 16 : 4252, 4027
7404 09:26:16.054086 20 : 4260, 4032
7405 09:26:16.054498 24 : 4253, 4027
7406 09:26:16.057548 28 : 4257, 4029
7407 09:26:16.058090 32 : 4363, 4137
7408 09:26:16.058506 36 : 4255, 4029
7409 09:26:16.061183 40 : 4258, 4030
7410 09:26:16.061683 44 : 4252, 4026
7411 09:26:16.063917 48 : 4252, 4027
7412 09:26:16.064329 52 : 4255, 4030
7413 09:26:16.067316 56 : 4362, 4140
7414 09:26:16.067727 60 : 4252, 4029
7415 09:26:16.068133 64 : 4250, 4026
7416 09:26:16.070955 68 : 4250, 4026
7417 09:26:16.071462 72 : 4365, 4143
7418 09:26:16.073778 76 : 4250, 4026
7419 09:26:16.074235 80 : 4250, 4027
7420 09:26:16.077396 84 : 4252, 4029
7421 09:26:16.077809 88 : 4253, 4029
7422 09:26:16.080591 92 : 4255, 4032
7423 09:26:16.081006 96 : 4250, 3331
7424 09:26:16.081408 100 : 4250, 0
7425 09:26:16.084476 104 : 4250, 0
7426 09:26:16.084968 108 : 4366, 0
7427 09:26:16.087520 112 : 4252, 0
7428 09:26:16.087933 116 : 4252, 0
7429 09:26:16.088339 120 : 4250, 0
7430 09:26:16.090556 124 : 4365, 0
7431 09:26:16.090970 128 : 4252, 0
7432 09:26:16.091377 132 : 4250, 0
7433 09:26:16.093966 136 : 4252, 0
7434 09:26:16.094422 140 : 4365, 0
7435 09:26:16.097487 144 : 4252, 0
7436 09:26:16.097900 148 : 4361, 0
7437 09:26:16.098340 152 : 4253, 0
7438 09:26:16.100827 156 : 4366, 0
7439 09:26:16.101239 160 : 4363, 0
7440 09:26:16.104156 164 : 4255, 0
7441 09:26:16.104653 168 : 4255, 0
7442 09:26:16.105063 172 : 4363, 0
7443 09:26:16.107530 176 : 4252, 0
7444 09:26:16.107942 180 : 4258, 0
7445 09:26:16.110632 184 : 4250, 0
7446 09:26:16.111058 188 : 4368, 0
7447 09:26:16.111458 192 : 4363, 0
7448 09:26:16.114115 196 : 4363, 0
7449 09:26:16.114532 200 : 4250, 0
7450 09:26:16.114937 204 : 4253, 0
7451 09:26:16.117207 208 : 4253, 0
7452 09:26:16.117617 212 : 4252, 80
7453 09:26:16.120560 216 : 4363, 3788
7454 09:26:16.120972 220 : 4252, 4026
7455 09:26:16.123851 224 : 4363, 4140
7456 09:26:16.124437 228 : 4363, 4137
7457 09:26:16.127321 232 : 4361, 4138
7458 09:26:16.127733 236 : 4252, 4029
7459 09:26:16.130861 240 : 4255, 4029
7460 09:26:16.131276 244 : 4366, 4140
7461 09:26:16.131685 248 : 4360, 4138
7462 09:26:16.134331 252 : 4250, 4027
7463 09:26:16.134826 256 : 4363, 4139
7464 09:26:16.137206 260 : 4253, 4029
7465 09:26:16.137615 264 : 4250, 4026
7466 09:26:16.140880 268 : 4361, 4137
7467 09:26:16.141289 272 : 4250, 4026
7468 09:26:16.144042 276 : 4363, 4137
7469 09:26:16.144455 280 : 4249, 4027
7470 09:26:16.147803 284 : 4252, 4029
7471 09:26:16.148225 288 : 4252, 4030
7472 09:26:16.150740 292 : 4250, 4027
7473 09:26:16.151148 296 : 4255, 4029
7474 09:26:16.151517 300 : 4362, 4140
7475 09:26:16.154220 304 : 4253, 4029
7476 09:26:16.154597 308 : 4255, 4030
7477 09:26:16.157537 312 : 4250, 4026
7478 09:26:16.157914 316 : 4250, 4027
7479 09:26:16.160556 320 : 4253, 4029
7480 09:26:16.160935 324 : 4253, 4029
7481 09:26:16.164289 328 : 4250, 4027
7482 09:26:16.164748 332 : 4252, 2756
7483 09:26:16.167449 336 : 4250, 76
7484 09:26:16.167826
7485 09:26:16.168193 MIOCK jitter meter ch=0
7486 09:26:16.168539
7487 09:26:16.171046 1T = (336-100) = 236 dly cells
7488 09:26:16.177600 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7489 09:26:16.177974 ==
7490 09:26:16.180499 Dram Type= 6, Freq= 0, CH_0, rank 0
7491 09:26:16.184607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7492 09:26:16.185056 ==
7493 09:26:16.190529 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7494 09:26:16.194156 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7495 09:26:16.197710 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7496 09:26:16.204210 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7497 09:26:16.213924 [CA 0] Center 44 (14~75) winsize 62
7498 09:26:16.217365 [CA 1] Center 44 (13~75) winsize 63
7499 09:26:16.220733 [CA 2] Center 40 (11~69) winsize 59
7500 09:26:16.223740 [CA 3] Center 39 (10~69) winsize 60
7501 09:26:16.226915 [CA 4] Center 38 (8~68) winsize 61
7502 09:26:16.230369 [CA 5] Center 37 (7~67) winsize 61
7503 09:26:16.230803
7504 09:26:16.233889 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7505 09:26:16.234348
7506 09:26:16.237328 [CATrainingPosCal] consider 1 rank data
7507 09:26:16.240414 u2DelayCellTimex100 = 275/100 ps
7508 09:26:16.243947 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7509 09:26:16.250411 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7510 09:26:16.253460 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7511 09:26:16.256773 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7512 09:26:16.260466 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7513 09:26:16.263531 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7514 09:26:16.264131
7515 09:26:16.267271 CA PerBit enable=1, Macro0, CA PI delay=37
7516 09:26:16.267740
7517 09:26:16.269957 [CBTSetCACLKResult] CA Dly = 37
7518 09:26:16.273296 CS Dly: 10 (0~41)
7519 09:26:16.276446 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7520 09:26:16.279985 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7521 09:26:16.280062 ==
7522 09:26:16.283598 Dram Type= 6, Freq= 0, CH_0, rank 1
7523 09:26:16.287335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 09:26:16.287430 ==
7525 09:26:16.293369 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7526 09:26:16.297064 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7527 09:26:16.303214 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7528 09:26:16.306898 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7529 09:26:16.317164 [CA 0] Center 44 (14~74) winsize 61
7530 09:26:16.321063 [CA 1] Center 44 (14~74) winsize 61
7531 09:26:16.324005 [CA 2] Center 39 (10~69) winsize 60
7532 09:26:16.327297 [CA 3] Center 39 (10~68) winsize 59
7533 09:26:16.330633 [CA 4] Center 37 (7~67) winsize 61
7534 09:26:16.333762 [CA 5] Center 37 (7~67) winsize 61
7535 09:26:16.333903
7536 09:26:16.337001 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7537 09:26:16.337191
7538 09:26:16.340345 [CATrainingPosCal] consider 2 rank data
7539 09:26:16.344078 u2DelayCellTimex100 = 275/100 ps
7540 09:26:16.347094 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7541 09:26:16.353944 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7542 09:26:16.357276 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7543 09:26:16.360578 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7544 09:26:16.364453 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7545 09:26:16.367593 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7546 09:26:16.367952
7547 09:26:16.370538 CA PerBit enable=1, Macro0, CA PI delay=37
7548 09:26:16.370899
7549 09:26:16.373885 [CBTSetCACLKResult] CA Dly = 37
7550 09:26:16.377178 CS Dly: 11 (0~43)
7551 09:26:16.380640 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7552 09:26:16.383999 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7553 09:26:16.384452
7554 09:26:16.387417 ----->DramcWriteLeveling(PI) begin...
7555 09:26:16.387918 ==
7556 09:26:16.390551 Dram Type= 6, Freq= 0, CH_0, rank 0
7557 09:26:16.397240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 09:26:16.397623 ==
7559 09:26:16.400627 Write leveling (Byte 0): 33 => 33
7560 09:26:16.401133 Write leveling (Byte 1): 29 => 29
7561 09:26:16.403957 DramcWriteLeveling(PI) end<-----
7562 09:26:16.404446
7563 09:26:16.404887 ==
7564 09:26:16.407140 Dram Type= 6, Freq= 0, CH_0, rank 0
7565 09:26:16.413716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7566 09:26:16.414134 ==
7567 09:26:16.416952 [Gating] SW mode calibration
7568 09:26:16.423889 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7569 09:26:16.427261 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7570 09:26:16.433712 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 09:26:16.436950 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 09:26:16.440285 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 09:26:16.446664 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 09:26:16.450473 1 4 16 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7575 09:26:16.453814 1 4 20 | B1->B0 | 2323 3130 | 0 1 | (0 0) (1 1)
7576 09:26:16.460337 1 4 24 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
7577 09:26:16.463807 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7578 09:26:16.467045 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7579 09:26:16.473208 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 09:26:16.476670 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 09:26:16.480225 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7582 09:26:16.483500 1 5 16 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
7583 09:26:16.490057 1 5 20 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
7584 09:26:16.493585 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7585 09:26:16.497082 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 09:26:16.503532 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 09:26:16.506753 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 09:26:16.510489 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 09:26:16.517472 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 09:26:16.520462 1 6 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7591 09:26:16.524269 1 6 20 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
7592 09:26:16.530693 1 6 24 | B1->B0 | 3a39 4646 | 1 0 | (0 0) (0 0)
7593 09:26:16.534171 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 09:26:16.537414 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 09:26:16.544335 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 09:26:16.547506 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 09:26:16.550736 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 09:26:16.553911 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 09:26:16.560883 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7600 09:26:16.563991 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7601 09:26:16.567601 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 09:26:16.573710 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 09:26:16.577336 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 09:26:16.580566 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 09:26:16.587398 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 09:26:16.590481 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 09:26:16.594088 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 09:26:16.600743 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 09:26:16.603826 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 09:26:16.607497 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 09:26:16.614044 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 09:26:16.617379 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 09:26:16.620765 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 09:26:16.627483 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7615 09:26:16.630469 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7616 09:26:16.634037 Total UI for P1: 0, mck2ui 16
7617 09:26:16.637086 best dqsien dly found for B0: ( 1, 9, 16)
7618 09:26:16.640763 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 09:26:16.643869 Total UI for P1: 0, mck2ui 16
7620 09:26:16.647125 best dqsien dly found for B1: ( 1, 9, 20)
7621 09:26:16.650796 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7622 09:26:16.653733 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7623 09:26:16.653897
7624 09:26:16.657365 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7625 09:26:16.663728 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7626 09:26:16.663893 [Gating] SW calibration Done
7627 09:26:16.664020 ==
7628 09:26:16.667494 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 09:26:16.674164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 09:26:16.674329 ==
7631 09:26:16.674459 RX Vref Scan: 0
7632 09:26:16.674577
7633 09:26:16.677379 RX Vref 0 -> 0, step: 1
7634 09:26:16.677543
7635 09:26:16.680546 RX Delay 0 -> 252, step: 8
7636 09:26:16.684266 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7637 09:26:16.687331 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7638 09:26:16.690753 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7639 09:26:16.694063 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7640 09:26:16.700604 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7641 09:26:16.703966 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7642 09:26:16.707026 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7643 09:26:16.710584 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7644 09:26:16.714181 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7645 09:26:16.720314 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7646 09:26:16.724081 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7647 09:26:16.727462 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7648 09:26:16.730779 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7649 09:26:16.734103 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7650 09:26:16.740647 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7651 09:26:16.744020 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7652 09:26:16.744187 ==
7653 09:26:16.747499 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 09:26:16.750693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 09:26:16.750860 ==
7656 09:26:16.750987 DQS Delay:
7657 09:26:16.753992 DQS0 = 0, DQS1 = 0
7658 09:26:16.754162 DQM Delay:
7659 09:26:16.757741 DQM0 = 132, DQM1 = 125
7660 09:26:16.757906 DQ Delay:
7661 09:26:16.760876 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7662 09:26:16.763956 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7663 09:26:16.767716 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7664 09:26:16.770755 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7665 09:26:16.770919
7666 09:26:16.774541
7667 09:26:16.774706 ==
7668 09:26:16.777570 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 09:26:16.780777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 09:26:16.780943 ==
7671 09:26:16.781071
7672 09:26:16.781190
7673 09:26:16.784651 TX Vref Scan disable
7674 09:26:16.784816 == TX Byte 0 ==
7675 09:26:16.791285 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7676 09:26:16.794437 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7677 09:26:16.794605 == TX Byte 1 ==
7678 09:26:16.800542 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7679 09:26:16.804218 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7680 09:26:16.804384 ==
7681 09:26:16.807662 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 09:26:16.810609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 09:26:16.810775 ==
7684 09:26:16.824774
7685 09:26:16.827716 TX Vref early break, caculate TX vref
7686 09:26:16.831483 TX Vref=16, minBit 1, minWin=21, winSum=364
7687 09:26:16.834584 TX Vref=18, minBit 4, minWin=22, winSum=379
7688 09:26:16.838015 TX Vref=20, minBit 4, minWin=23, winSum=389
7689 09:26:16.841677 TX Vref=22, minBit 1, minWin=24, winSum=401
7690 09:26:16.844620 TX Vref=24, minBit 2, minWin=24, winSum=409
7691 09:26:16.851474 TX Vref=26, minBit 3, minWin=25, winSum=417
7692 09:26:16.854729 TX Vref=28, minBit 4, minWin=25, winSum=427
7693 09:26:16.858561 TX Vref=30, minBit 2, minWin=25, winSum=420
7694 09:26:16.861546 TX Vref=32, minBit 2, minWin=24, winSum=412
7695 09:26:16.865452 TX Vref=34, minBit 0, minWin=24, winSum=404
7696 09:26:16.871634 [TxChooseVref] Worse bit 4, Min win 25, Win sum 427, Final Vref 28
7697 09:26:16.872002
7698 09:26:16.875224 Final TX Range 0 Vref 28
7699 09:26:16.875487
7700 09:26:16.875688 ==
7701 09:26:16.878151 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 09:26:16.881814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 09:26:16.882104 ==
7704 09:26:16.882268
7705 09:26:16.882440
7706 09:26:16.884834 TX Vref Scan disable
7707 09:26:16.887968 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7708 09:26:16.891574 == TX Byte 0 ==
7709 09:26:16.895002 u2DelayCellOfst[0]=14 cells (4 PI)
7710 09:26:16.897915 u2DelayCellOfst[1]=21 cells (6 PI)
7711 09:26:16.901687 u2DelayCellOfst[2]=14 cells (4 PI)
7712 09:26:16.904847 u2DelayCellOfst[3]=14 cells (4 PI)
7713 09:26:16.908399 u2DelayCellOfst[4]=10 cells (3 PI)
7714 09:26:16.911238 u2DelayCellOfst[5]=0 cells (0 PI)
7715 09:26:16.911404 u2DelayCellOfst[6]=21 cells (6 PI)
7716 09:26:16.915386 u2DelayCellOfst[7]=21 cells (6 PI)
7717 09:26:16.921478 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7718 09:26:16.925151 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7719 09:26:16.925561 == TX Byte 1 ==
7720 09:26:16.928585 u2DelayCellOfst[8]=0 cells (0 PI)
7721 09:26:16.931819 u2DelayCellOfst[9]=0 cells (0 PI)
7722 09:26:16.934998 u2DelayCellOfst[10]=3 cells (1 PI)
7723 09:26:16.938188 u2DelayCellOfst[11]=0 cells (0 PI)
7724 09:26:16.941368 u2DelayCellOfst[12]=10 cells (3 PI)
7725 09:26:16.945111 u2DelayCellOfst[13]=10 cells (3 PI)
7726 09:26:16.948330 u2DelayCellOfst[14]=14 cells (4 PI)
7727 09:26:16.951202 u2DelayCellOfst[15]=10 cells (3 PI)
7728 09:26:16.955109 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7729 09:26:16.958032 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7730 09:26:16.961635 DramC Write-DBI on
7731 09:26:16.961743 ==
7732 09:26:16.964339 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 09:26:16.968181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 09:26:16.968269 ==
7735 09:26:16.968337
7736 09:26:16.968399
7737 09:26:16.971397 TX Vref Scan disable
7738 09:26:16.974745 == TX Byte 0 ==
7739 09:26:16.978495 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7740 09:26:16.981496 == TX Byte 1 ==
7741 09:26:16.985099 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7742 09:26:16.985405 DramC Write-DBI off
7743 09:26:16.985645
7744 09:26:16.988206 [DATLAT]
7745 09:26:16.988510 Freq=1600, CH0 RK0
7746 09:26:16.988748
7747 09:26:16.991924 DATLAT Default: 0xf
7748 09:26:16.992227 0, 0xFFFF, sum = 0
7749 09:26:16.995140 1, 0xFFFF, sum = 0
7750 09:26:16.995451 2, 0xFFFF, sum = 0
7751 09:26:16.998066 3, 0xFFFF, sum = 0
7752 09:26:16.998403 4, 0xFFFF, sum = 0
7753 09:26:17.001757 5, 0xFFFF, sum = 0
7754 09:26:17.002122 6, 0xFFFF, sum = 0
7755 09:26:17.004761 7, 0xFFFF, sum = 0
7756 09:26:17.005073 8, 0xFFFF, sum = 0
7757 09:26:17.007906 9, 0xFFFF, sum = 0
7758 09:26:17.008214 10, 0xFFFF, sum = 0
7759 09:26:17.011696 11, 0xFFFF, sum = 0
7760 09:26:17.015106 12, 0xFFFF, sum = 0
7761 09:26:17.015418 13, 0xFFFF, sum = 0
7762 09:26:17.018367 14, 0x0, sum = 1
7763 09:26:17.018781 15, 0x0, sum = 2
7764 09:26:17.021469 16, 0x0, sum = 3
7765 09:26:17.021870 17, 0x0, sum = 4
7766 09:26:17.022236 best_step = 15
7767 09:26:17.022525
7768 09:26:17.025193 ==
7769 09:26:17.028204 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 09:26:17.031844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 09:26:17.032248 ==
7772 09:26:17.032561 RX Vref Scan: 1
7773 09:26:17.032852
7774 09:26:17.034884 Set Vref Range= 24 -> 127
7775 09:26:17.035307
7776 09:26:17.038333 RX Vref 24 -> 127, step: 1
7777 09:26:17.038728
7778 09:26:17.041670 RX Delay 11 -> 252, step: 4
7779 09:26:17.042105
7780 09:26:17.044666 Set Vref, RX VrefLevel [Byte0]: 24
7781 09:26:17.048547 [Byte1]: 24
7782 09:26:17.048944
7783 09:26:17.051857 Set Vref, RX VrefLevel [Byte0]: 25
7784 09:26:17.055160 [Byte1]: 25
7785 09:26:17.055759
7786 09:26:17.058371 Set Vref, RX VrefLevel [Byte0]: 26
7787 09:26:17.061551 [Byte1]: 26
7788 09:26:17.064667
7789 09:26:17.064946 Set Vref, RX VrefLevel [Byte0]: 27
7790 09:26:17.068158 [Byte1]: 27
7791 09:26:17.072354
7792 09:26:17.072566 Set Vref, RX VrefLevel [Byte0]: 28
7793 09:26:17.075529 [Byte1]: 28
7794 09:26:17.079992
7795 09:26:17.080135 Set Vref, RX VrefLevel [Byte0]: 29
7796 09:26:17.083526 [Byte1]: 29
7797 09:26:17.087631
7798 09:26:17.087756 Set Vref, RX VrefLevel [Byte0]: 30
7799 09:26:17.090789 [Byte1]: 30
7800 09:26:17.095103
7801 09:26:17.095200 Set Vref, RX VrefLevel [Byte0]: 31
7802 09:26:17.098093 [Byte1]: 31
7803 09:26:17.102695
7804 09:26:17.102781 Set Vref, RX VrefLevel [Byte0]: 32
7805 09:26:17.105770 [Byte1]: 32
7806 09:26:17.110007
7807 09:26:17.110093 Set Vref, RX VrefLevel [Byte0]: 33
7808 09:26:17.113826 [Byte1]: 33
7809 09:26:17.117909
7810 09:26:17.118023 Set Vref, RX VrefLevel [Byte0]: 34
7811 09:26:17.120989 [Byte1]: 34
7812 09:26:17.125387
7813 09:26:17.125474 Set Vref, RX VrefLevel [Byte0]: 35
7814 09:26:17.129438 [Byte1]: 35
7815 09:26:17.133090
7816 09:26:17.133484 Set Vref, RX VrefLevel [Byte0]: 36
7817 09:26:17.137036 [Byte1]: 36
7818 09:26:17.140994
7819 09:26:17.141071 Set Vref, RX VrefLevel [Byte0]: 37
7820 09:26:17.143734 [Byte1]: 37
7821 09:26:17.148398
7822 09:26:17.148487 Set Vref, RX VrefLevel [Byte0]: 38
7823 09:26:17.151579 [Byte1]: 38
7824 09:26:17.155958
7825 09:26:17.156053 Set Vref, RX VrefLevel [Byte0]: 39
7826 09:26:17.159002 [Byte1]: 39
7827 09:26:17.163692
7828 09:26:17.163797 Set Vref, RX VrefLevel [Byte0]: 40
7829 09:26:17.166716 [Byte1]: 40
7830 09:26:17.171079
7831 09:26:17.171188 Set Vref, RX VrefLevel [Byte0]: 41
7832 09:26:17.174510 [Byte1]: 41
7833 09:26:17.179037
7834 09:26:17.179156 Set Vref, RX VrefLevel [Byte0]: 42
7835 09:26:17.182035 [Byte1]: 42
7836 09:26:17.186062
7837 09:26:17.186156 Set Vref, RX VrefLevel [Byte0]: 43
7838 09:26:17.189507 [Byte1]: 43
7839 09:26:17.193904
7840 09:26:17.194007 Set Vref, RX VrefLevel [Byte0]: 44
7841 09:26:17.197544 [Byte1]: 44
7842 09:26:17.201443
7843 09:26:17.201541 Set Vref, RX VrefLevel [Byte0]: 45
7844 09:26:17.204792 [Byte1]: 45
7845 09:26:17.209034
7846 09:26:17.209111 Set Vref, RX VrefLevel [Byte0]: 46
7847 09:26:17.212590 [Byte1]: 46
7848 09:26:17.216907
7849 09:26:17.216983 Set Vref, RX VrefLevel [Byte0]: 47
7850 09:26:17.220146 [Byte1]: 47
7851 09:26:17.224413
7852 09:26:17.224489 Set Vref, RX VrefLevel [Byte0]: 48
7853 09:26:17.227590 [Byte1]: 48
7854 09:26:17.231956
7855 09:26:17.232032 Set Vref, RX VrefLevel [Byte0]: 49
7856 09:26:17.235103 [Byte1]: 49
7857 09:26:17.239503
7858 09:26:17.239584 Set Vref, RX VrefLevel [Byte0]: 50
7859 09:26:17.242843 [Byte1]: 50
7860 09:26:17.247174
7861 09:26:17.247324 Set Vref, RX VrefLevel [Byte0]: 51
7862 09:26:17.250691 [Byte1]: 51
7863 09:26:17.255614
7864 09:26:17.256040 Set Vref, RX VrefLevel [Byte0]: 52
7865 09:26:17.258457 [Byte1]: 52
7866 09:26:17.262707
7867 09:26:17.263097 Set Vref, RX VrefLevel [Byte0]: 53
7868 09:26:17.266371 [Byte1]: 53
7869 09:26:17.270372
7870 09:26:17.270759 Set Vref, RX VrefLevel [Byte0]: 54
7871 09:26:17.273813 [Byte1]: 54
7872 09:26:17.278670
7873 09:26:17.279143 Set Vref, RX VrefLevel [Byte0]: 55
7874 09:26:17.281653 [Byte1]: 55
7875 09:26:17.285744
7876 09:26:17.286180 Set Vref, RX VrefLevel [Byte0]: 56
7877 09:26:17.289023 [Byte1]: 56
7878 09:26:17.293350
7879 09:26:17.293776 Set Vref, RX VrefLevel [Byte0]: 57
7880 09:26:17.296701 [Byte1]: 57
7881 09:26:17.300628
7882 09:26:17.301020 Set Vref, RX VrefLevel [Byte0]: 58
7883 09:26:17.304226 [Byte1]: 58
7884 09:26:17.308470
7885 09:26:17.308857 Set Vref, RX VrefLevel [Byte0]: 59
7886 09:26:17.311969 [Byte1]: 59
7887 09:26:17.316170
7888 09:26:17.316560 Set Vref, RX VrefLevel [Byte0]: 60
7889 09:26:17.319323 [Byte1]: 60
7890 09:26:17.323539
7891 09:26:17.323931 Set Vref, RX VrefLevel [Byte0]: 61
7892 09:26:17.326825 [Byte1]: 61
7893 09:26:17.331399
7894 09:26:17.331813 Set Vref, RX VrefLevel [Byte0]: 62
7895 09:26:17.334820 [Byte1]: 62
7896 09:26:17.339065
7897 09:26:17.339458 Set Vref, RX VrefLevel [Byte0]: 63
7898 09:26:17.342272 [Byte1]: 63
7899 09:26:17.346641
7900 09:26:17.347033 Set Vref, RX VrefLevel [Byte0]: 64
7901 09:26:17.349726 [Byte1]: 64
7902 09:26:17.354028
7903 09:26:17.354238 Set Vref, RX VrefLevel [Byte0]: 65
7904 09:26:17.357331 [Byte1]: 65
7905 09:26:17.361590
7906 09:26:17.361760 Set Vref, RX VrefLevel [Byte0]: 66
7907 09:26:17.364546 [Byte1]: 66
7908 09:26:17.368908
7909 09:26:17.369029 Set Vref, RX VrefLevel [Byte0]: 67
7910 09:26:17.372542 [Byte1]: 67
7911 09:26:17.376681
7912 09:26:17.376790 Set Vref, RX VrefLevel [Byte0]: 68
7913 09:26:17.379719 [Byte1]: 68
7914 09:26:17.384253
7915 09:26:17.384340 Set Vref, RX VrefLevel [Byte0]: 69
7916 09:26:17.387970 [Byte1]: 69
7917 09:26:17.391540
7918 09:26:17.391619 Set Vref, RX VrefLevel [Byte0]: 70
7919 09:26:17.395478 [Byte1]: 70
7920 09:26:17.399670
7921 09:26:17.399969 Set Vref, RX VrefLevel [Byte0]: 71
7922 09:26:17.403294 [Byte1]: 71
7923 09:26:17.407403
7924 09:26:17.407701 Set Vref, RX VrefLevel [Byte0]: 72
7925 09:26:17.410695 [Byte1]: 72
7926 09:26:17.415112
7927 09:26:17.415422 Set Vref, RX VrefLevel [Byte0]: 73
7928 09:26:17.418182 [Byte1]: 73
7929 09:26:17.422701
7930 09:26:17.423000 Set Vref, RX VrefLevel [Byte0]: 74
7931 09:26:17.425818 [Byte1]: 74
7932 09:26:17.430064
7933 09:26:17.433809 Set Vref, RX VrefLevel [Byte0]: 75
7934 09:26:17.437225 [Byte1]: 75
7935 09:26:17.437708
7936 09:26:17.440245 Final RX Vref Byte 0 = 54 to rank0
7937 09:26:17.443284 Final RX Vref Byte 1 = 62 to rank0
7938 09:26:17.446996 Final RX Vref Byte 0 = 54 to rank1
7939 09:26:17.450102 Final RX Vref Byte 1 = 62 to rank1==
7940 09:26:17.453696 Dram Type= 6, Freq= 0, CH_0, rank 0
7941 09:26:17.457116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7942 09:26:17.457592 ==
7943 09:26:17.457901 DQS Delay:
7944 09:26:17.460562 DQS0 = 0, DQS1 = 0
7945 09:26:17.460968 DQM Delay:
7946 09:26:17.463268 DQM0 = 129, DQM1 = 122
7947 09:26:17.463665 DQ Delay:
7948 09:26:17.466597 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7949 09:26:17.470489 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =138
7950 09:26:17.473393 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =118
7951 09:26:17.477039 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
7952 09:26:17.477433
7953 09:26:17.477743
7954 09:26:17.478056
7955 09:26:17.479922 [DramC_TX_OE_Calibration] TA2
7956 09:26:17.483440 Original DQ_B0 (3 6) =30, OEN = 27
7957 09:26:17.486476 Original DQ_B1 (3 6) =30, OEN = 27
7958 09:26:17.490519 24, 0x0, End_B0=24 End_B1=24
7959 09:26:17.493464 25, 0x0, End_B0=25 End_B1=25
7960 09:26:17.493865 26, 0x0, End_B0=26 End_B1=26
7961 09:26:17.496776 27, 0x0, End_B0=27 End_B1=27
7962 09:26:17.500214 28, 0x0, End_B0=28 End_B1=28
7963 09:26:17.503300 29, 0x0, End_B0=29 End_B1=29
7964 09:26:17.506820 30, 0x0, End_B0=30 End_B1=30
7965 09:26:17.507218 31, 0x4141, End_B0=30 End_B1=30
7966 09:26:17.509880 Byte0 end_step=30 best_step=27
7967 09:26:17.513627 Byte1 end_step=30 best_step=27
7968 09:26:17.517094 Byte0 TX OE(2T, 0.5T) = (3, 3)
7969 09:26:17.519976 Byte1 TX OE(2T, 0.5T) = (3, 3)
7970 09:26:17.520370
7971 09:26:17.520676
7972 09:26:17.526764 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7973 09:26:17.530456 CH0 RK0: MR19=303, MR18=1509
7974 09:26:17.536835 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
7975 09:26:17.537230
7976 09:26:17.539907 ----->DramcWriteLeveling(PI) begin...
7977 09:26:17.540307 ==
7978 09:26:17.543704 Dram Type= 6, Freq= 0, CH_0, rank 1
7979 09:26:17.546726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7980 09:26:17.547124 ==
7981 09:26:17.550400 Write leveling (Byte 0): 33 => 33
7982 09:26:17.553696 Write leveling (Byte 1): 28 => 28
7983 09:26:17.556524 DramcWriteLeveling(PI) end<-----
7984 09:26:17.556918
7985 09:26:17.557225 ==
7986 09:26:17.559766 Dram Type= 6, Freq= 0, CH_0, rank 1
7987 09:26:17.563108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 09:26:17.566299 ==
7989 09:26:17.566512 [Gating] SW mode calibration
7990 09:26:17.573011 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7991 09:26:17.579954 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7992 09:26:17.582759 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 09:26:17.589341 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 09:26:17.593071 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7995 09:26:17.596377 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7996 09:26:17.602936 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7997 09:26:17.606015 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7998 09:26:17.609604 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 09:26:17.616247 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 09:26:17.619582 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 09:26:17.623041 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 09:26:17.626321 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8003 09:26:17.633341 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8004 09:26:17.636396 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8005 09:26:17.640456 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8006 09:26:17.646633 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8007 09:26:17.650328 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 09:26:17.653678 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 09:26:17.659728 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 09:26:17.663189 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
8011 09:26:17.666885 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8012 09:26:17.673687 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8013 09:26:17.676749 1 6 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8014 09:26:17.680320 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 09:26:17.686714 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 09:26:17.689830 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 09:26:17.693405 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 09:26:17.699679 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8019 09:26:17.703142 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8020 09:26:17.706592 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8021 09:26:17.713513 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8022 09:26:17.716673 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 09:26:17.720441 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 09:26:17.723535 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 09:26:17.730301 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 09:26:17.733616 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 09:26:17.736996 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 09:26:17.743283 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 09:26:17.746468 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 09:26:17.750283 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 09:26:17.756523 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 09:26:17.760253 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 09:26:17.763481 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 09:26:17.769966 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8035 09:26:17.773553 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8036 09:26:17.776599 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8037 09:26:17.779921 Total UI for P1: 0, mck2ui 16
8038 09:26:17.783170 best dqsien dly found for B0: ( 1, 9, 10)
8039 09:26:17.789824 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8040 09:26:17.793563 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 09:26:17.796717 Total UI for P1: 0, mck2ui 16
8042 09:26:17.800263 best dqsien dly found for B1: ( 1, 9, 20)
8043 09:26:17.803085 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8044 09:26:17.806476 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8045 09:26:17.806600
8046 09:26:17.809724 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8047 09:26:17.812934 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8048 09:26:17.816671 [Gating] SW calibration Done
8049 09:26:17.816768 ==
8050 09:26:17.819692 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 09:26:17.823607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 09:26:17.823689 ==
8053 09:26:17.826837 RX Vref Scan: 0
8054 09:26:17.826915
8055 09:26:17.829763 RX Vref 0 -> 0, step: 1
8056 09:26:17.829839
8057 09:26:17.829899 RX Delay 0 -> 252, step: 8
8058 09:26:17.836544 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8059 09:26:17.840037 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8060 09:26:17.843416 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8061 09:26:17.847008 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8062 09:26:17.850135 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8063 09:26:17.853086 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8064 09:26:17.860139 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8065 09:26:17.863102 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8066 09:26:17.866291 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8067 09:26:17.870104 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8068 09:26:17.876763 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8069 09:26:17.880398 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8070 09:26:17.883439 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8071 09:26:17.886974 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8072 09:26:17.890367 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8073 09:26:17.896826 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8074 09:26:17.897224 ==
8075 09:26:17.899993 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 09:26:17.903680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 09:26:17.904076 ==
8078 09:26:17.904423 DQS Delay:
8079 09:26:17.906867 DQS0 = 0, DQS1 = 0
8080 09:26:17.907455 DQM Delay:
8081 09:26:17.910177 DQM0 = 130, DQM1 = 123
8082 09:26:17.910646 DQ Delay:
8083 09:26:17.913353 DQ0 =131, DQ1 =131, DQ2 =123, DQ3 =131
8084 09:26:17.916801 DQ4 =131, DQ5 =115, DQ6 =139, DQ7 =139
8085 09:26:17.920009 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =115
8086 09:26:17.923473 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8087 09:26:17.923902
8088 09:26:17.924210
8089 09:26:17.926716 ==
8090 09:26:17.927123 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 09:26:17.933345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 09:26:17.933814 ==
8093 09:26:17.934232
8094 09:26:17.934526
8095 09:26:17.936701 TX Vref Scan disable
8096 09:26:17.937096 == TX Byte 0 ==
8097 09:26:17.940004 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8098 09:26:17.946874 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8099 09:26:17.947306 == TX Byte 1 ==
8100 09:26:17.950348 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8101 09:26:17.956555 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8102 09:26:17.956951 ==
8103 09:26:17.959920 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 09:26:17.963224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 09:26:17.963622 ==
8106 09:26:17.977945
8107 09:26:17.981616 TX Vref early break, caculate TX vref
8108 09:26:17.985012 TX Vref=16, minBit 0, minWin=23, winSum=379
8109 09:26:17.988185 TX Vref=18, minBit 3, minWin=23, winSum=391
8110 09:26:17.991920 TX Vref=20, minBit 7, minWin=23, winSum=394
8111 09:26:17.994682 TX Vref=22, minBit 0, minWin=24, winSum=406
8112 09:26:17.998429 TX Vref=24, minBit 0, minWin=25, winSum=413
8113 09:26:18.001760 TX Vref=26, minBit 7, minWin=25, winSum=423
8114 09:26:18.008098 TX Vref=28, minBit 7, minWin=25, winSum=426
8115 09:26:18.011252 TX Vref=30, minBit 7, minWin=25, winSum=424
8116 09:26:18.015123 TX Vref=32, minBit 4, minWin=24, winSum=415
8117 09:26:18.018104 TX Vref=34, minBit 0, minWin=24, winSum=405
8118 09:26:18.021924 TX Vref=36, minBit 0, minWin=23, winSum=398
8119 09:26:18.028550 [TxChooseVref] Worse bit 7, Min win 25, Win sum 426, Final Vref 28
8120 09:26:18.028947
8121 09:26:18.031828 Final TX Range 0 Vref 28
8122 09:26:18.032224
8123 09:26:18.032526 ==
8124 09:26:18.035576 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 09:26:18.038460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 09:26:18.038857 ==
8127 09:26:18.039163
8128 09:26:18.039443
8129 09:26:18.041382 TX Vref Scan disable
8130 09:26:18.048496 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8131 09:26:18.048974 == TX Byte 0 ==
8132 09:26:18.051785 u2DelayCellOfst[0]=14 cells (4 PI)
8133 09:26:18.054669 u2DelayCellOfst[1]=21 cells (6 PI)
8134 09:26:18.057977 u2DelayCellOfst[2]=14 cells (4 PI)
8135 09:26:18.061710 u2DelayCellOfst[3]=14 cells (4 PI)
8136 09:26:18.064747 u2DelayCellOfst[4]=10 cells (3 PI)
8137 09:26:18.068110 u2DelayCellOfst[5]=0 cells (0 PI)
8138 09:26:18.071615 u2DelayCellOfst[6]=21 cells (6 PI)
8139 09:26:18.074759 u2DelayCellOfst[7]=17 cells (5 PI)
8140 09:26:18.078178 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8141 09:26:18.081279 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8142 09:26:18.084589 == TX Byte 1 ==
8143 09:26:18.084802 u2DelayCellOfst[8]=0 cells (0 PI)
8144 09:26:18.087949 u2DelayCellOfst[9]=0 cells (0 PI)
8145 09:26:18.091441 u2DelayCellOfst[10]=7 cells (2 PI)
8146 09:26:18.094505 u2DelayCellOfst[11]=0 cells (0 PI)
8147 09:26:18.098211 u2DelayCellOfst[12]=14 cells (4 PI)
8148 09:26:18.101330 u2DelayCellOfst[13]=14 cells (4 PI)
8149 09:26:18.104697 u2DelayCellOfst[14]=14 cells (4 PI)
8150 09:26:18.107980 u2DelayCellOfst[15]=10 cells (3 PI)
8151 09:26:18.111050 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8152 09:26:18.117845 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8153 09:26:18.117976 DramC Write-DBI on
8154 09:26:18.118051 ==
8155 09:26:18.121016 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 09:26:18.124857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 09:26:18.124935 ==
8158 09:26:18.128194
8159 09:26:18.128270
8160 09:26:18.128329 TX Vref Scan disable
8161 09:26:18.131365 == TX Byte 0 ==
8162 09:26:18.134900 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8163 09:26:18.137763 == TX Byte 1 ==
8164 09:26:18.141413 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8165 09:26:18.141553 DramC Write-DBI off
8166 09:26:18.144502
8167 09:26:18.144646 [DATLAT]
8168 09:26:18.144714 Freq=1600, CH0 RK1
8169 09:26:18.144776
8170 09:26:18.148265 DATLAT Default: 0xf
8171 09:26:18.148407 0, 0xFFFF, sum = 0
8172 09:26:18.151404 1, 0xFFFF, sum = 0
8173 09:26:18.151549 2, 0xFFFF, sum = 0
8174 09:26:18.154951 3, 0xFFFF, sum = 0
8175 09:26:18.155094 4, 0xFFFF, sum = 0
8176 09:26:18.157962 5, 0xFFFF, sum = 0
8177 09:26:18.161051 6, 0xFFFF, sum = 0
8178 09:26:18.161168 7, 0xFFFF, sum = 0
8179 09:26:18.164526 8, 0xFFFF, sum = 0
8180 09:26:18.164653 9, 0xFFFF, sum = 0
8181 09:26:18.168149 10, 0xFFFF, sum = 0
8182 09:26:18.168307 11, 0xFFFF, sum = 0
8183 09:26:18.171615 12, 0xFFFF, sum = 0
8184 09:26:18.171778 13, 0xFFFF, sum = 0
8185 09:26:18.174887 14, 0x0, sum = 1
8186 09:26:18.175039 15, 0x0, sum = 2
8187 09:26:18.177951 16, 0x0, sum = 3
8188 09:26:18.178122 17, 0x0, sum = 4
8189 09:26:18.181170 best_step = 15
8190 09:26:18.181349
8191 09:26:18.181449 ==
8192 09:26:18.184657 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 09:26:18.188030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 09:26:18.188241 ==
8195 09:26:18.188362 RX Vref Scan: 0
8196 09:26:18.190984
8197 09:26:18.191139 RX Vref 0 -> 0, step: 1
8198 09:26:18.191251
8199 09:26:18.194693 RX Delay 11 -> 252, step: 4
8200 09:26:18.197860 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8201 09:26:18.204871 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8202 09:26:18.208101 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8203 09:26:18.211612 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8204 09:26:18.215252 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8205 09:26:18.217937 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8206 09:26:18.224723 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8207 09:26:18.228197 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8208 09:26:18.231493 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8209 09:26:18.234514 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8210 09:26:18.238447 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8211 09:26:18.244828 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8212 09:26:18.248369 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8213 09:26:18.251303 iDelay=191, Bit 13, Center 126 (71 ~ 182) 112
8214 09:26:18.255097 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8215 09:26:18.258013 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8216 09:26:18.258440 ==
8217 09:26:18.261882 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 09:26:18.268398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 09:26:18.268886 ==
8220 09:26:18.269199 DQS Delay:
8221 09:26:18.272062 DQS0 = 0, DQS1 = 0
8222 09:26:18.272545 DQM Delay:
8223 09:26:18.274746 DQM0 = 126, DQM1 = 122
8224 09:26:18.275140 DQ Delay:
8225 09:26:18.278160 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8226 09:26:18.281906 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =136
8227 09:26:18.284953 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8228 09:26:18.288769 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8229 09:26:18.289259
8230 09:26:18.289570
8231 09:26:18.289850
8232 09:26:18.291588 [DramC_TX_OE_Calibration] TA2
8233 09:26:18.295288 Original DQ_B0 (3 6) =30, OEN = 27
8234 09:26:18.297934 Original DQ_B1 (3 6) =30, OEN = 27
8235 09:26:18.301642 24, 0x0, End_B0=24 End_B1=24
8236 09:26:18.302084 25, 0x0, End_B0=25 End_B1=25
8237 09:26:18.304898 26, 0x0, End_B0=26 End_B1=26
8238 09:26:18.308496 27, 0x0, End_B0=27 End_B1=27
8239 09:26:18.311359 28, 0x0, End_B0=28 End_B1=28
8240 09:26:18.314929 29, 0x0, End_B0=29 End_B1=29
8241 09:26:18.315330 30, 0x0, End_B0=30 End_B1=30
8242 09:26:18.318529 31, 0x4141, End_B0=30 End_B1=30
8243 09:26:18.322134 Byte0 end_step=30 best_step=27
8244 09:26:18.324630 Byte1 end_step=30 best_step=27
8245 09:26:18.328233 Byte0 TX OE(2T, 0.5T) = (3, 3)
8246 09:26:18.331227 Byte1 TX OE(2T, 0.5T) = (3, 3)
8247 09:26:18.331621
8248 09:26:18.331924
8249 09:26:18.337977 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
8250 09:26:18.341747 CH0 RK1: MR19=303, MR18=1C10
8251 09:26:18.348288 CH0_RK1: MR19=0x303, MR18=0x1C10, DQSOSC=395, MR23=63, INC=23, DEC=15
8252 09:26:18.351657 [RxdqsGatingPostProcess] freq 1600
8253 09:26:18.354899 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8254 09:26:18.358457 best DQS0 dly(2T, 0.5T) = (1, 1)
8255 09:26:18.361377 best DQS1 dly(2T, 0.5T) = (1, 1)
8256 09:26:18.364495 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8257 09:26:18.368466 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8258 09:26:18.371463 best DQS0 dly(2T, 0.5T) = (1, 1)
8259 09:26:18.375041 best DQS1 dly(2T, 0.5T) = (1, 1)
8260 09:26:18.378305 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8261 09:26:18.381675 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8262 09:26:18.384812 Pre-setting of DQS Precalculation
8263 09:26:18.388278 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8264 09:26:18.388670 ==
8265 09:26:18.391370 Dram Type= 6, Freq= 0, CH_1, rank 0
8266 09:26:18.395416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8267 09:26:18.395900 ==
8268 09:26:18.401828 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8269 09:26:18.404752 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8270 09:26:18.411229 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8271 09:26:18.415060 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8272 09:26:18.425113 [CA 0] Center 42 (13~71) winsize 59
8273 09:26:18.427959 [CA 1] Center 42 (13~71) winsize 59
8274 09:26:18.431089 [CA 2] Center 37 (8~66) winsize 59
8275 09:26:18.434421 [CA 3] Center 36 (7~65) winsize 59
8276 09:26:18.438295 [CA 4] Center 37 (8~67) winsize 60
8277 09:26:18.441196 [CA 5] Center 36 (6~66) winsize 61
8278 09:26:18.441595
8279 09:26:18.444371 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8280 09:26:18.444769
8281 09:26:18.447978 [CATrainingPosCal] consider 1 rank data
8282 09:26:18.451438 u2DelayCellTimex100 = 275/100 ps
8283 09:26:18.454670 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8284 09:26:18.461422 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8285 09:26:18.464597 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8286 09:26:18.468079 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8287 09:26:18.471135 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8288 09:26:18.474935 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8289 09:26:18.475325
8290 09:26:18.477965 CA PerBit enable=1, Macro0, CA PI delay=36
8291 09:26:18.478390
8292 09:26:18.481795 [CBTSetCACLKResult] CA Dly = 36
8293 09:26:18.482254 CS Dly: 8 (0~39)
8294 09:26:18.488571 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8295 09:26:18.491684 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8296 09:26:18.492071 ==
8297 09:26:18.495142 Dram Type= 6, Freq= 0, CH_1, rank 1
8298 09:26:18.497969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 09:26:18.498452 ==
8300 09:26:18.504798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8301 09:26:18.508649 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8302 09:26:18.511435 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8303 09:26:18.518586 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8304 09:26:18.527780 [CA 0] Center 42 (13~72) winsize 60
8305 09:26:18.530888 [CA 1] Center 42 (14~71) winsize 58
8306 09:26:18.534659 [CA 2] Center 38 (9~67) winsize 59
8307 09:26:18.537926 [CA 3] Center 37 (8~66) winsize 59
8308 09:26:18.541155 [CA 4] Center 38 (9~67) winsize 59
8309 09:26:18.544143 [CA 5] Center 36 (7~66) winsize 60
8310 09:26:18.544652
8311 09:26:18.548277 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8312 09:26:18.548805
8313 09:26:18.551018 [CATrainingPosCal] consider 2 rank data
8314 09:26:18.554461 u2DelayCellTimex100 = 275/100 ps
8315 09:26:18.557372 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8316 09:26:18.564238 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8317 09:26:18.568000 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8318 09:26:18.571131 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8319 09:26:18.574646 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8320 09:26:18.577543 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8321 09:26:18.577953
8322 09:26:18.581000 CA PerBit enable=1, Macro0, CA PI delay=36
8323 09:26:18.581391
8324 09:26:18.584445 [CBTSetCACLKResult] CA Dly = 36
8325 09:26:18.584834 CS Dly: 11 (0~45)
8326 09:26:18.591359 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8327 09:26:18.594441 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8328 09:26:18.594846
8329 09:26:18.597502 ----->DramcWriteLeveling(PI) begin...
8330 09:26:18.597899 ==
8331 09:26:18.601134 Dram Type= 6, Freq= 0, CH_1, rank 0
8332 09:26:18.604684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 09:26:18.605077 ==
8334 09:26:18.607826 Write leveling (Byte 0): 25 => 25
8335 09:26:18.610728 Write leveling (Byte 1): 28 => 28
8336 09:26:18.614582 DramcWriteLeveling(PI) end<-----
8337 09:26:18.614971
8338 09:26:18.615277 ==
8339 09:26:18.617538 Dram Type= 6, Freq= 0, CH_1, rank 0
8340 09:26:18.624527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 09:26:18.625121 ==
8342 09:26:18.625562 [Gating] SW mode calibration
8343 09:26:18.634827 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8344 09:26:18.637866 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8345 09:26:18.641312 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 09:26:18.647996 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 09:26:18.650780 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 09:26:18.654766 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 09:26:18.661211 1 4 16 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
8350 09:26:18.664803 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 09:26:18.667850 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 09:26:18.674364 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 09:26:18.677998 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 09:26:18.681475 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 09:26:18.684448 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 09:26:18.691298 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8357 09:26:18.694516 1 5 16 | B1->B0 | 3131 3434 | 0 0 | (1 0) (0 1)
8358 09:26:18.697802 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 09:26:18.704344 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 09:26:18.707411 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 09:26:18.711013 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 09:26:18.717449 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 09:26:18.721159 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 09:26:18.724300 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 09:26:18.730823 1 6 16 | B1->B0 | 4242 3535 | 0 0 | (0 0) (0 0)
8366 09:26:18.734286 1 6 20 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8367 09:26:18.737507 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 09:26:18.744631 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 09:26:18.747762 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 09:26:18.751474 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 09:26:18.757659 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 09:26:18.761157 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 09:26:18.764910 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8374 09:26:18.771187 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 09:26:18.774994 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 09:26:18.777745 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 09:26:18.784476 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 09:26:18.787991 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 09:26:18.791753 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 09:26:18.794993 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 09:26:18.801699 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 09:26:18.804645 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 09:26:18.808099 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 09:26:18.814543 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 09:26:18.818075 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 09:26:18.821149 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 09:26:18.828418 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 09:26:18.831464 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 09:26:18.835091 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8390 09:26:18.841350 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 09:26:18.841743 Total UI for P1: 0, mck2ui 16
8392 09:26:18.848476 best dqsien dly found for B0: ( 1, 9, 16)
8393 09:26:18.848979 Total UI for P1: 0, mck2ui 16
8394 09:26:18.851357 best dqsien dly found for B1: ( 1, 9, 16)
8395 09:26:18.855300 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8396 09:26:18.861544 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8397 09:26:18.861938
8398 09:26:18.865776 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8399 09:26:18.868787 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8400 09:26:18.871815 [Gating] SW calibration Done
8401 09:26:18.872297 ==
8402 09:26:18.875246 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 09:26:18.878256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 09:26:18.878671 ==
8405 09:26:18.881786 RX Vref Scan: 0
8406 09:26:18.882380
8407 09:26:18.882700 RX Vref 0 -> 0, step: 1
8408 09:26:18.882993
8409 09:26:18.885008 RX Delay 0 -> 252, step: 8
8410 09:26:18.888548 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8411 09:26:18.891566 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8412 09:26:18.898468 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8413 09:26:18.901446 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8414 09:26:18.905152 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8415 09:26:18.908707 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8416 09:26:18.911825 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8417 09:26:18.915371 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8418 09:26:18.921718 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8419 09:26:18.925314 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8420 09:26:18.929152 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8421 09:26:18.932033 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8422 09:26:18.935628 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8423 09:26:18.941889 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8424 09:26:18.945080 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8425 09:26:18.948976 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8426 09:26:18.949506 ==
8427 09:26:18.951843 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 09:26:18.955594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 09:26:18.955978 ==
8430 09:26:18.958814 DQS Delay:
8431 09:26:18.959454 DQS0 = 0, DQS1 = 0
8432 09:26:18.961723 DQM Delay:
8433 09:26:18.962129 DQM0 = 133, DQM1 = 127
8434 09:26:18.965877 DQ Delay:
8435 09:26:18.968795 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8436 09:26:18.972519 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8437 09:26:18.975794 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8438 09:26:18.978894 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8439 09:26:18.979289
8440 09:26:18.979590
8441 09:26:18.979868 ==
8442 09:26:18.982325 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 09:26:18.985284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 09:26:18.985725 ==
8445 09:26:18.986089
8446 09:26:18.986404
8447 09:26:18.988744 TX Vref Scan disable
8448 09:26:18.992212 == TX Byte 0 ==
8449 09:26:18.995696 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8450 09:26:18.999141 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8451 09:26:19.002258 == TX Byte 1 ==
8452 09:26:19.005858 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8453 09:26:19.009197 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8454 09:26:19.009597 ==
8455 09:26:19.012186 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 09:26:19.015932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 09:26:19.016369 ==
8458 09:26:19.029842
8459 09:26:19.033428 TX Vref early break, caculate TX vref
8460 09:26:19.036768 TX Vref=16, minBit 8, minWin=21, winSum=367
8461 09:26:19.039891 TX Vref=18, minBit 8, minWin=21, winSum=379
8462 09:26:19.043428 TX Vref=20, minBit 9, minWin=22, winSum=384
8463 09:26:19.046377 TX Vref=22, minBit 8, minWin=22, winSum=394
8464 09:26:19.049961 TX Vref=24, minBit 8, minWin=22, winSum=402
8465 09:26:19.056448 TX Vref=26, minBit 8, minWin=24, winSum=415
8466 09:26:19.059720 TX Vref=28, minBit 15, minWin=25, winSum=419
8467 09:26:19.063021 TX Vref=30, minBit 1, minWin=25, winSum=419
8468 09:26:19.066769 TX Vref=32, minBit 0, minWin=25, winSum=412
8469 09:26:19.070085 TX Vref=34, minBit 8, minWin=23, winSum=395
8470 09:26:19.076775 [TxChooseVref] Worse bit 15, Min win 25, Win sum 419, Final Vref 28
8471 09:26:19.077179
8472 09:26:19.079943 Final TX Range 0 Vref 28
8473 09:26:19.080341
8474 09:26:19.080651 ==
8475 09:26:19.083099 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 09:26:19.086374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 09:26:19.086787 ==
8478 09:26:19.087093
8479 09:26:19.087373
8480 09:26:19.089899 TX Vref Scan disable
8481 09:26:19.096533 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8482 09:26:19.097178 == TX Byte 0 ==
8483 09:26:19.099929 u2DelayCellOfst[0]=14 cells (4 PI)
8484 09:26:19.103275 u2DelayCellOfst[1]=14 cells (4 PI)
8485 09:26:19.106703 u2DelayCellOfst[2]=0 cells (0 PI)
8486 09:26:19.109631 u2DelayCellOfst[3]=7 cells (2 PI)
8487 09:26:19.112790 u2DelayCellOfst[4]=7 cells (2 PI)
8488 09:26:19.116657 u2DelayCellOfst[5]=17 cells (5 PI)
8489 09:26:19.117177 u2DelayCellOfst[6]=17 cells (5 PI)
8490 09:26:19.119827 u2DelayCellOfst[7]=7 cells (2 PI)
8491 09:26:19.126450 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8492 09:26:19.129927 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8493 09:26:19.130397 == TX Byte 1 ==
8494 09:26:19.133318 u2DelayCellOfst[8]=0 cells (0 PI)
8495 09:26:19.136510 u2DelayCellOfst[9]=0 cells (0 PI)
8496 09:26:19.140156 u2DelayCellOfst[10]=7 cells (2 PI)
8497 09:26:19.277253 u2DelayCellOfst[11]=3 cells (1 PI)
8498 09:26:19.278179 u2DelayCellOfst[12]=10 cells (3 PI)
8499 09:26:19.278666 u2DelayCellOfst[13]=10 cells (3 PI)
8500 09:26:19.279127 u2DelayCellOfst[14]=14 cells (4 PI)
8501 09:26:19.279457 u2DelayCellOfst[15]=14 cells (4 PI)
8502 09:26:19.279835 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8503 09:26:19.280289 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8504 09:26:19.280691 DramC Write-DBI on
8505 09:26:19.281085 ==
8506 09:26:19.281483 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 09:26:19.281882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 09:26:19.282358 ==
8509 09:26:19.282767
8510 09:26:19.283041
8511 09:26:19.283297 TX Vref Scan disable
8512 09:26:19.283586 == TX Byte 0 ==
8513 09:26:19.283965 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8514 09:26:19.284261 == TX Byte 1 ==
8515 09:26:19.284524 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8516 09:26:19.284795 DramC Write-DBI off
8517 09:26:19.285073
8518 09:26:19.285340 [DATLAT]
8519 09:26:19.285593 Freq=1600, CH1 RK0
8520 09:26:19.285844
8521 09:26:19.286191 DATLAT Default: 0xf
8522 09:26:19.286449 0, 0xFFFF, sum = 0
8523 09:26:19.286726 1, 0xFFFF, sum = 0
8524 09:26:19.287059 2, 0xFFFF, sum = 0
8525 09:26:19.287320 3, 0xFFFF, sum = 0
8526 09:26:19.287616 4, 0xFFFF, sum = 0
8527 09:26:19.287880 5, 0xFFFF, sum = 0
8528 09:26:19.288135 6, 0xFFFF, sum = 0
8529 09:26:19.288391 7, 0xFFFF, sum = 0
8530 09:26:19.288646 8, 0xFFFF, sum = 0
8531 09:26:19.288918 9, 0xFFFF, sum = 0
8532 09:26:19.289176 10, 0xFFFF, sum = 0
8533 09:26:19.289434 11, 0xFFFF, sum = 0
8534 09:26:19.289691 12, 0xFFFF, sum = 0
8535 09:26:19.289943 13, 0xFFFF, sum = 0
8536 09:26:19.290239 14, 0x0, sum = 1
8537 09:26:19.290496 15, 0x0, sum = 2
8538 09:26:19.290751 16, 0x0, sum = 3
8539 09:26:19.291030 17, 0x0, sum = 4
8540 09:26:19.291286 best_step = 15
8541 09:26:19.291539
8542 09:26:19.291799 ==
8543 09:26:19.292063 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 09:26:19.292313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 09:26:19.292570 ==
8546 09:26:19.292821 RX Vref Scan: 1
8547 09:26:19.293096
8548 09:26:19.293344 Set Vref Range= 24 -> 127
8549 09:26:19.293591
8550 09:26:19.293843 RX Vref 24 -> 127, step: 1
8551 09:26:19.294138
8552 09:26:19.294391 RX Delay 19 -> 252, step: 4
8553 09:26:19.294639
8554 09:26:19.294939 Set Vref, RX VrefLevel [Byte0]: 24
8555 09:26:19.295379 [Byte1]: 24
8556 09:26:19.295661
8557 09:26:19.295914 Set Vref, RX VrefLevel [Byte0]: 25
8558 09:26:19.296169 [Byte1]: 25
8559 09:26:19.296419
8560 09:26:19.296665 Set Vref, RX VrefLevel [Byte0]: 26
8561 09:26:19.296915 [Byte1]: 26
8562 09:26:19.297184
8563 09:26:19.297433 Set Vref, RX VrefLevel [Byte0]: 27
8564 09:26:19.297684 [Byte1]: 27
8565 09:26:19.297932
8566 09:26:19.298250 Set Vref, RX VrefLevel [Byte0]: 28
8567 09:26:19.298565 [Byte1]: 28
8568 09:26:19.298832
8569 09:26:19.299160 Set Vref, RX VrefLevel [Byte0]: 29
8570 09:26:19.299440 [Byte1]: 29
8571 09:26:19.299700
8572 09:26:19.299950 Set Vref, RX VrefLevel [Byte0]: 30
8573 09:26:19.300202 [Byte1]: 30
8574 09:26:19.300509
8575 09:26:19.300777 Set Vref, RX VrefLevel [Byte0]: 31
8576 09:26:19.303393 [Byte1]: 31
8577 09:26:19.306980
8578 09:26:19.307304 Set Vref, RX VrefLevel [Byte0]: 32
8579 09:26:19.310330 [Byte1]: 32
8580 09:26:19.314433
8581 09:26:19.314604 Set Vref, RX VrefLevel [Byte0]: 33
8582 09:26:19.318014 [Byte1]: 33
8583 09:26:19.321850
8584 09:26:19.322045 Set Vref, RX VrefLevel [Byte0]: 34
8585 09:26:19.325204 [Byte1]: 34
8586 09:26:19.329554
8587 09:26:19.329703 Set Vref, RX VrefLevel [Byte0]: 35
8588 09:26:19.332714 [Byte1]: 35
8589 09:26:19.337084
8590 09:26:19.337175 Set Vref, RX VrefLevel [Byte0]: 36
8591 09:26:19.340258 [Byte1]: 36
8592 09:26:19.344530
8593 09:26:19.344596 Set Vref, RX VrefLevel [Byte0]: 37
8594 09:26:19.348148 [Byte1]: 37
8595 09:26:19.352127
8596 09:26:19.352197 Set Vref, RX VrefLevel [Byte0]: 38
8597 09:26:19.355510 [Byte1]: 38
8598 09:26:19.360117
8599 09:26:19.360189 Set Vref, RX VrefLevel [Byte0]: 39
8600 09:26:19.363217 [Byte1]: 39
8601 09:26:19.367408
8602 09:26:19.367473 Set Vref, RX VrefLevel [Byte0]: 40
8603 09:26:19.370983 [Byte1]: 40
8604 09:26:19.375274
8605 09:26:19.375338 Set Vref, RX VrefLevel [Byte0]: 41
8606 09:26:19.378257 [Byte1]: 41
8607 09:26:19.382748
8608 09:26:19.382812 Set Vref, RX VrefLevel [Byte0]: 42
8609 09:26:19.385758 [Byte1]: 42
8610 09:26:19.390238
8611 09:26:19.390304 Set Vref, RX VrefLevel [Byte0]: 43
8612 09:26:19.393282 [Byte1]: 43
8613 09:26:19.397518
8614 09:26:19.397606 Set Vref, RX VrefLevel [Byte0]: 44
8615 09:26:19.401030 [Byte1]: 44
8616 09:26:19.405239
8617 09:26:19.405312 Set Vref, RX VrefLevel [Byte0]: 45
8618 09:26:19.408913 [Byte1]: 45
8619 09:26:19.413058
8620 09:26:19.413154 Set Vref, RX VrefLevel [Byte0]: 46
8621 09:26:19.416101 [Byte1]: 46
8622 09:26:19.420159
8623 09:26:19.420224 Set Vref, RX VrefLevel [Byte0]: 47
8624 09:26:19.423710 [Byte1]: 47
8625 09:26:19.428172
8626 09:26:19.428238 Set Vref, RX VrefLevel [Byte0]: 48
8627 09:26:19.431532 [Byte1]: 48
8628 09:26:19.435590
8629 09:26:19.435655 Set Vref, RX VrefLevel [Byte0]: 49
8630 09:26:19.439120 [Byte1]: 49
8631 09:26:19.443300
8632 09:26:19.443370 Set Vref, RX VrefLevel [Byte0]: 50
8633 09:26:19.446450 [Byte1]: 50
8634 09:26:19.450732
8635 09:26:19.450798 Set Vref, RX VrefLevel [Byte0]: 51
8636 09:26:19.453912 [Byte1]: 51
8637 09:26:19.458107
8638 09:26:19.458196 Set Vref, RX VrefLevel [Byte0]: 52
8639 09:26:19.461452 [Byte1]: 52
8640 09:26:19.465991
8641 09:26:19.466090 Set Vref, RX VrefLevel [Byte0]: 53
8642 09:26:19.468954 [Byte1]: 53
8643 09:26:19.473267
8644 09:26:19.473330 Set Vref, RX VrefLevel [Byte0]: 54
8645 09:26:19.476810 [Byte1]: 54
8646 09:26:19.481174
8647 09:26:19.481243 Set Vref, RX VrefLevel [Byte0]: 55
8648 09:26:19.484190 [Byte1]: 55
8649 09:26:19.488548
8650 09:26:19.488608 Set Vref, RX VrefLevel [Byte0]: 56
8651 09:26:19.491714 [Byte1]: 56
8652 09:26:19.495961
8653 09:26:19.496021 Set Vref, RX VrefLevel [Byte0]: 57
8654 09:26:19.499813 [Byte1]: 57
8655 09:26:19.504141
8656 09:26:19.504235 Set Vref, RX VrefLevel [Byte0]: 58
8657 09:26:19.507006 [Byte1]: 58
8658 09:26:19.511424
8659 09:26:19.511503 Set Vref, RX VrefLevel [Byte0]: 59
8660 09:26:19.514659 [Byte1]: 59
8661 09:26:19.519130
8662 09:26:19.519202 Set Vref, RX VrefLevel [Byte0]: 60
8663 09:26:19.522179 [Byte1]: 60
8664 09:26:19.526527
8665 09:26:19.526595 Set Vref, RX VrefLevel [Byte0]: 61
8666 09:26:19.529610 [Byte1]: 61
8667 09:26:19.533845
8668 09:26:19.533907 Set Vref, RX VrefLevel [Byte0]: 62
8669 09:26:19.537517 [Byte1]: 62
8670 09:26:19.541761
8671 09:26:19.541824 Set Vref, RX VrefLevel [Byte0]: 63
8672 09:26:19.544789 [Byte1]: 63
8673 09:26:19.549285
8674 09:26:19.549354 Set Vref, RX VrefLevel [Byte0]: 64
8675 09:26:19.552440 [Byte1]: 64
8676 09:26:19.556788
8677 09:26:19.556879 Set Vref, RX VrefLevel [Byte0]: 65
8678 09:26:19.560117 [Byte1]: 65
8679 09:26:19.564353
8680 09:26:19.564428 Set Vref, RX VrefLevel [Byte0]: 66
8681 09:26:19.567566 [Byte1]: 66
8682 09:26:19.572096
8683 09:26:19.572172 Set Vref, RX VrefLevel [Byte0]: 67
8684 09:26:19.574978 [Byte1]: 67
8685 09:26:19.579459
8686 09:26:19.579537 Set Vref, RX VrefLevel [Byte0]: 68
8687 09:26:19.582538 [Byte1]: 68
8688 09:26:19.586899
8689 09:26:19.586975 Set Vref, RX VrefLevel [Byte0]: 69
8690 09:26:19.590568 [Byte1]: 69
8691 09:26:19.594340
8692 09:26:19.594416 Set Vref, RX VrefLevel [Byte0]: 70
8693 09:26:19.598163 [Byte1]: 70
8694 09:26:19.602490
8695 09:26:19.602567 Set Vref, RX VrefLevel [Byte0]: 71
8696 09:26:19.605573 [Byte1]: 71
8697 09:26:19.610008
8698 09:26:19.610098 Set Vref, RX VrefLevel [Byte0]: 72
8699 09:26:19.613038 [Byte1]: 72
8700 09:26:19.617212
8701 09:26:19.617301 Set Vref, RX VrefLevel [Byte0]: 73
8702 09:26:19.620647 [Byte1]: 73
8703 09:26:19.624994
8704 09:26:19.625069 Final RX Vref Byte 0 = 57 to rank0
8705 09:26:19.627982 Final RX Vref Byte 1 = 53 to rank0
8706 09:26:19.631793 Final RX Vref Byte 0 = 57 to rank1
8707 09:26:19.634885 Final RX Vref Byte 1 = 53 to rank1==
8708 09:26:19.638604 Dram Type= 6, Freq= 0, CH_1, rank 0
8709 09:26:19.641764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8710 09:26:19.644738 ==
8711 09:26:19.644814 DQS Delay:
8712 09:26:19.644873 DQS0 = 0, DQS1 = 0
8713 09:26:19.648371 DQM Delay:
8714 09:26:19.648446 DQM0 = 131, DQM1 = 124
8715 09:26:19.651895 DQ Delay:
8716 09:26:19.654830 DQ0 =136, DQ1 =124, DQ2 =120, DQ3 =128
8717 09:26:19.658704 DQ4 =130, DQ5 =142, DQ6 =144, DQ7 =128
8718 09:26:19.661757 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =116
8719 09:26:19.665099 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8720 09:26:19.665172
8721 09:26:19.665229
8722 09:26:19.665282
8723 09:26:19.668369 [DramC_TX_OE_Calibration] TA2
8724 09:26:19.671487 Original DQ_B0 (3 6) =30, OEN = 27
8725 09:26:19.674919 Original DQ_B1 (3 6) =30, OEN = 27
8726 09:26:19.677998 24, 0x0, End_B0=24 End_B1=24
8727 09:26:19.678081 25, 0x0, End_B0=25 End_B1=25
8728 09:26:19.681753 26, 0x0, End_B0=26 End_B1=26
8729 09:26:19.684811 27, 0x0, End_B0=27 End_B1=27
8730 09:26:19.688259 28, 0x0, End_B0=28 End_B1=28
8731 09:26:19.688324 29, 0x0, End_B0=29 End_B1=29
8732 09:26:19.691687 30, 0x0, End_B0=30 End_B1=30
8733 09:26:19.694824 31, 0x4141, End_B0=30 End_B1=30
8734 09:26:19.698165 Byte0 end_step=30 best_step=27
8735 09:26:19.701860 Byte1 end_step=30 best_step=27
8736 09:26:19.704749 Byte0 TX OE(2T, 0.5T) = (3, 3)
8737 09:26:19.704821 Byte1 TX OE(2T, 0.5T) = (3, 3)
8738 09:26:19.704886
8739 09:26:19.708444
8740 09:26:19.714768 [DQSOSCAuto] RK0, (LSB)MR18= 0x1902, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 397 ps
8741 09:26:19.718357 CH1 RK0: MR19=303, MR18=1902
8742 09:26:19.724965 CH1_RK0: MR19=0x303, MR18=0x1902, DQSOSC=397, MR23=63, INC=23, DEC=15
8743 09:26:19.725030
8744 09:26:19.728364 ----->DramcWriteLeveling(PI) begin...
8745 09:26:19.728436 ==
8746 09:26:19.731437 Dram Type= 6, Freq= 0, CH_1, rank 1
8747 09:26:19.735225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 09:26:19.735298 ==
8749 09:26:19.738254 Write leveling (Byte 0): 25 => 25
8750 09:26:19.741443 Write leveling (Byte 1): 27 => 27
8751 09:26:19.745230 DramcWriteLeveling(PI) end<-----
8752 09:26:19.745294
8753 09:26:19.745347 ==
8754 09:26:19.748317 Dram Type= 6, Freq= 0, CH_1, rank 1
8755 09:26:19.751488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 09:26:19.751549 ==
8757 09:26:19.754918 [Gating] SW mode calibration
8758 09:26:19.761451 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8759 09:26:19.768146 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8760 09:26:19.771377 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 09:26:19.775189 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 09:26:19.781738 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8763 09:26:19.784905 1 4 12 | B1->B0 | 2d2d 3434 | 0 1 | (1 1) (1 1)
8764 09:26:19.788348 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 09:26:19.795069 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 09:26:19.798157 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 09:26:19.801886 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 09:26:19.804707 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 09:26:19.811600 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8770 09:26:19.814616 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
8771 09:26:19.818334 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
8772 09:26:19.825020 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 09:26:19.828156 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 09:26:19.831733 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 09:26:19.838167 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 09:26:19.841336 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 09:26:19.845050 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8778 09:26:19.851802 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8779 09:26:19.854859 1 6 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8780 09:26:19.857915 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8781 09:26:19.865120 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 09:26:19.868643 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 09:26:19.871777 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 09:26:19.878660 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 09:26:19.881579 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8786 09:26:19.884703 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8787 09:26:19.891526 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8788 09:26:19.894798 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8789 09:26:19.898045 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 09:26:19.901586 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 09:26:19.907987 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 09:26:19.911693 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 09:26:19.914605 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 09:26:19.921744 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 09:26:19.924702 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 09:26:19.928352 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 09:26:19.935318 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 09:26:19.938545 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 09:26:19.941341 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 09:26:19.948343 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 09:26:19.951907 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 09:26:19.955061 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8803 09:26:19.958126 Total UI for P1: 0, mck2ui 16
8804 09:26:19.961872 best dqsien dly found for B0: ( 1, 9, 6)
8805 09:26:19.968631 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8806 09:26:19.971698 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8807 09:26:19.975194 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 09:26:19.978366 Total UI for P1: 0, mck2ui 16
8809 09:26:19.981378 best dqsien dly found for B1: ( 1, 9, 12)
8810 09:26:19.985077 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8811 09:26:19.988233 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8812 09:26:19.988296
8813 09:26:19.991725 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8814 09:26:19.998127 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8815 09:26:19.998191 [Gating] SW calibration Done
8816 09:26:19.998246 ==
8817 09:26:20.001701 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 09:26:20.008244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 09:26:20.008346 ==
8820 09:26:20.008438 RX Vref Scan: 0
8821 09:26:20.008521
8822 09:26:20.011588 RX Vref 0 -> 0, step: 1
8823 09:26:20.011665
8824 09:26:20.014757 RX Delay 0 -> 252, step: 8
8825 09:26:20.018171 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8826 09:26:20.021649 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8827 09:26:20.024910 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8828 09:26:20.028079 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8829 09:26:20.034890 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8830 09:26:20.038650 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8831 09:26:20.041726 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8832 09:26:20.044776 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8833 09:26:20.048422 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8834 09:26:20.054818 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8835 09:26:20.058458 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8836 09:26:20.061734 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8837 09:26:20.065214 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8838 09:26:20.068292 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8839 09:26:20.075314 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8840 09:26:20.078325 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8841 09:26:20.078403 ==
8842 09:26:20.081840 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 09:26:20.085328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 09:26:20.085405 ==
8845 09:26:20.088482 DQS Delay:
8846 09:26:20.088559 DQS0 = 0, DQS1 = 0
8847 09:26:20.088619 DQM Delay:
8848 09:26:20.091641 DQM0 = 132, DQM1 = 127
8849 09:26:20.091718 DQ Delay:
8850 09:26:20.094847 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8851 09:26:20.098492 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8852 09:26:20.101563 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8853 09:26:20.108584 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8854 09:26:20.108661
8855 09:26:20.108720
8856 09:26:20.108774 ==
8857 09:26:20.111756 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 09:26:20.115024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 09:26:20.115137 ==
8860 09:26:20.115197
8861 09:26:20.115251
8862 09:26:20.118642 TX Vref Scan disable
8863 09:26:20.118719 == TX Byte 0 ==
8864 09:26:20.125324 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8865 09:26:20.128365 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8866 09:26:20.128442 == TX Byte 1 ==
8867 09:26:20.135096 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8868 09:26:20.138555 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8869 09:26:20.138633 ==
8870 09:26:20.142096 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 09:26:20.145061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 09:26:20.145145 ==
8873 09:26:20.160749
8874 09:26:20.164305 TX Vref early break, caculate TX vref
8875 09:26:20.167349 TX Vref=16, minBit 8, minWin=22, winSum=378
8876 09:26:20.171008 TX Vref=18, minBit 8, minWin=23, winSum=390
8877 09:26:20.173903 TX Vref=20, minBit 11, minWin=23, winSum=396
8878 09:26:20.177222 TX Vref=22, minBit 9, minWin=24, winSum=406
8879 09:26:20.180542 TX Vref=24, minBit 15, minWin=24, winSum=413
8880 09:26:20.187380 TX Vref=26, minBit 15, minWin=24, winSum=420
8881 09:26:20.190462 TX Vref=28, minBit 0, minWin=25, winSum=424
8882 09:26:20.194167 TX Vref=30, minBit 13, minWin=25, winSum=424
8883 09:26:20.197202 TX Vref=32, minBit 0, minWin=26, winSum=420
8884 09:26:20.200732 TX Vref=34, minBit 0, minWin=25, winSum=409
8885 09:26:20.207497 TX Vref=36, minBit 1, minWin=24, winSum=402
8886 09:26:20.210444 TX Vref=38, minBit 0, minWin=23, winSum=393
8887 09:26:20.213715 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 32
8888 09:26:20.213815
8889 09:26:20.217506 Final TX Range 0 Vref 32
8890 09:26:20.217583
8891 09:26:20.217643 ==
8892 09:26:20.220423 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 09:26:20.227273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 09:26:20.227373 ==
8895 09:26:20.227458
8896 09:26:20.227538
8897 09:26:20.227618 TX Vref Scan disable
8898 09:26:20.234466 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8899 09:26:20.234588 == TX Byte 0 ==
8900 09:26:20.237391 u2DelayCellOfst[0]=17 cells (5 PI)
8901 09:26:20.240970 u2DelayCellOfst[1]=10 cells (3 PI)
8902 09:26:20.244440 u2DelayCellOfst[2]=0 cells (0 PI)
8903 09:26:20.247754 u2DelayCellOfst[3]=7 cells (2 PI)
8904 09:26:20.250739 u2DelayCellOfst[4]=10 cells (3 PI)
8905 09:26:20.254148 u2DelayCellOfst[5]=21 cells (6 PI)
8906 09:26:20.257984 u2DelayCellOfst[6]=14 cells (4 PI)
8907 09:26:20.261064 u2DelayCellOfst[7]=7 cells (2 PI)
8908 09:26:20.264084 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8909 09:26:20.267743 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8910 09:26:20.270910 == TX Byte 1 ==
8911 09:26:20.274214 u2DelayCellOfst[8]=0 cells (0 PI)
8912 09:26:20.277840 u2DelayCellOfst[9]=7 cells (2 PI)
8913 09:26:20.277941 u2DelayCellOfst[10]=10 cells (3 PI)
8914 09:26:20.280931 u2DelayCellOfst[11]=7 cells (2 PI)
8915 09:26:20.284474 u2DelayCellOfst[12]=14 cells (4 PI)
8916 09:26:20.288086 u2DelayCellOfst[13]=17 cells (5 PI)
8917 09:26:20.291209 u2DelayCellOfst[14]=17 cells (5 PI)
8918 09:26:20.294307 u2DelayCellOfst[15]=17 cells (5 PI)
8919 09:26:20.301235 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8920 09:26:20.304184 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8921 09:26:20.304262 DramC Write-DBI on
8922 09:26:20.304323 ==
8923 09:26:20.307552 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 09:26:20.314138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 09:26:20.314215 ==
8926 09:26:20.314275
8927 09:26:20.314329
8928 09:26:20.314382 TX Vref Scan disable
8929 09:26:20.317924 == TX Byte 0 ==
8930 09:26:20.321777 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8931 09:26:20.324921 == TX Byte 1 ==
8932 09:26:20.328091 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8933 09:26:20.331774 DramC Write-DBI off
8934 09:26:20.331852
8935 09:26:20.331911 [DATLAT]
8936 09:26:20.331967 Freq=1600, CH1 RK1
8937 09:26:20.332019
8938 09:26:20.334870 DATLAT Default: 0xf
8939 09:26:20.334947 0, 0xFFFF, sum = 0
8940 09:26:20.338484 1, 0xFFFF, sum = 0
8941 09:26:20.338562 2, 0xFFFF, sum = 0
8942 09:26:20.341442 3, 0xFFFF, sum = 0
8943 09:26:20.345109 4, 0xFFFF, sum = 0
8944 09:26:20.345187 5, 0xFFFF, sum = 0
8945 09:26:20.348204 6, 0xFFFF, sum = 0
8946 09:26:20.348282 7, 0xFFFF, sum = 0
8947 09:26:20.351319 8, 0xFFFF, sum = 0
8948 09:26:20.351396 9, 0xFFFF, sum = 0
8949 09:26:20.354982 10, 0xFFFF, sum = 0
8950 09:26:20.355060 11, 0xFFFF, sum = 0
8951 09:26:20.358367 12, 0xFFFF, sum = 0
8952 09:26:20.358449 13, 0xFFFF, sum = 0
8953 09:26:20.361757 14, 0x0, sum = 1
8954 09:26:20.361831 15, 0x0, sum = 2
8955 09:26:20.364644 16, 0x0, sum = 3
8956 09:26:20.364744 17, 0x0, sum = 4
8957 09:26:20.368337 best_step = 15
8958 09:26:20.368433
8959 09:26:20.368516 ==
8960 09:26:20.371607 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 09:26:20.375104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 09:26:20.375191 ==
8963 09:26:20.375255 RX Vref Scan: 0
8964 09:26:20.375311
8965 09:26:20.378193 RX Vref 0 -> 0, step: 1
8966 09:26:20.378269
8967 09:26:20.381313 RX Delay 11 -> 252, step: 4
8968 09:26:20.385211 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8969 09:26:20.391702 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8970 09:26:20.394775 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8971 09:26:20.398316 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8972 09:26:20.401458 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8973 09:26:20.405227 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8974 09:26:20.411498 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8975 09:26:20.414628 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8976 09:26:20.418508 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8977 09:26:20.421451 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
8978 09:26:20.424806 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8979 09:26:20.428078 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8980 09:26:20.434808 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8981 09:26:20.438528 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8982 09:26:20.441653 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8983 09:26:20.445250 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8984 09:26:20.445331 ==
8985 09:26:20.448207 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 09:26:20.454870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 09:26:20.454946 ==
8988 09:26:20.455005 DQS Delay:
8989 09:26:20.458133 DQS0 = 0, DQS1 = 0
8990 09:26:20.458199 DQM Delay:
8991 09:26:20.458259 DQM0 = 129, DQM1 = 126
8992 09:26:20.461987 DQ Delay:
8993 09:26:20.464954 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8994 09:26:20.468677 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =126
8995 09:26:20.471741 DQ8 =114, DQ9 =114, DQ10 =126, DQ11 =118
8996 09:26:20.474721 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
8997 09:26:20.474786
8998 09:26:20.474841
8999 09:26:20.474897
9000 09:26:20.478163 [DramC_TX_OE_Calibration] TA2
9001 09:26:20.481500 Original DQ_B0 (3 6) =30, OEN = 27
9002 09:26:20.484740 Original DQ_B1 (3 6) =30, OEN = 27
9003 09:26:20.488184 24, 0x0, End_B0=24 End_B1=24
9004 09:26:20.488268 25, 0x0, End_B0=25 End_B1=25
9005 09:26:20.491698 26, 0x0, End_B0=26 End_B1=26
9006 09:26:20.495126 27, 0x0, End_B0=27 End_B1=27
9007 09:26:20.498222 28, 0x0, End_B0=28 End_B1=28
9008 09:26:20.501792 29, 0x0, End_B0=29 End_B1=29
9009 09:26:20.501866 30, 0x0, End_B0=30 End_B1=30
9010 09:26:20.504708 31, 0x4141, End_B0=30 End_B1=30
9011 09:26:20.508404 Byte0 end_step=30 best_step=27
9012 09:26:20.511527 Byte1 end_step=30 best_step=27
9013 09:26:20.514795 Byte0 TX OE(2T, 0.5T) = (3, 3)
9014 09:26:20.518349 Byte1 TX OE(2T, 0.5T) = (3, 3)
9015 09:26:20.518417
9016 09:26:20.518478
9017 09:26:20.525200 [DQSOSCAuto] RK1, (LSB)MR18= 0x1318, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
9018 09:26:20.528202 CH1 RK1: MR19=303, MR18=1318
9019 09:26:20.535315 CH1_RK1: MR19=0x303, MR18=0x1318, DQSOSC=397, MR23=63, INC=23, DEC=15
9020 09:26:20.538409 [RxdqsGatingPostProcess] freq 1600
9021 09:26:20.541903 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9022 09:26:20.544972 best DQS0 dly(2T, 0.5T) = (1, 1)
9023 09:26:20.548187 best DQS1 dly(2T, 0.5T) = (1, 1)
9024 09:26:20.551632 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9025 09:26:20.554974 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9026 09:26:20.558184 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 09:26:20.561736 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 09:26:20.565220 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 09:26:20.568258 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 09:26:20.571889 Pre-setting of DQS Precalculation
9031 09:26:20.575048 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9032 09:26:20.581883 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9033 09:26:20.588224 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9034 09:26:20.588295
9035 09:26:20.588352
9036 09:26:20.591721 [Calibration Summary] 3200 Mbps
9037 09:26:20.595149 CH 0, Rank 0
9038 09:26:20.595213 SW Impedance : PASS
9039 09:26:20.598343 DUTY Scan : NO K
9040 09:26:20.601944 ZQ Calibration : PASS
9041 09:26:20.602057 Jitter Meter : NO K
9042 09:26:20.604817 CBT Training : PASS
9043 09:26:20.608449 Write leveling : PASS
9044 09:26:20.608546 RX DQS gating : PASS
9045 09:26:20.611895 RX DQ/DQS(RDDQC) : PASS
9046 09:26:20.611964 TX DQ/DQS : PASS
9047 09:26:20.615519 RX DATLAT : PASS
9048 09:26:20.618583 RX DQ/DQS(Engine): PASS
9049 09:26:20.618651 TX OE : PASS
9050 09:26:20.621706 All Pass.
9051 09:26:20.621773
9052 09:26:20.621829 CH 0, Rank 1
9053 09:26:20.625462 SW Impedance : PASS
9054 09:26:20.625527 DUTY Scan : NO K
9055 09:26:20.628608 ZQ Calibration : PASS
9056 09:26:20.631708 Jitter Meter : NO K
9057 09:26:20.631777 CBT Training : PASS
9058 09:26:20.635375 Write leveling : PASS
9059 09:26:20.638389 RX DQS gating : PASS
9060 09:26:20.638457 RX DQ/DQS(RDDQC) : PASS
9061 09:26:20.641941 TX DQ/DQS : PASS
9062 09:26:20.644998 RX DATLAT : PASS
9063 09:26:20.645063 RX DQ/DQS(Engine): PASS
9064 09:26:20.648480 TX OE : PASS
9065 09:26:20.648554 All Pass.
9066 09:26:20.648612
9067 09:26:20.648665 CH 1, Rank 0
9068 09:26:20.651720 SW Impedance : PASS
9069 09:26:20.655430 DUTY Scan : NO K
9070 09:26:20.655520 ZQ Calibration : PASS
9071 09:26:20.658615 Jitter Meter : NO K
9072 09:26:20.662202 CBT Training : PASS
9073 09:26:20.662277 Write leveling : PASS
9074 09:26:20.665203 RX DQS gating : PASS
9075 09:26:20.668396 RX DQ/DQS(RDDQC) : PASS
9076 09:26:20.668465 TX DQ/DQS : PASS
9077 09:26:20.672106 RX DATLAT : PASS
9078 09:26:20.675344 RX DQ/DQS(Engine): PASS
9079 09:26:20.675409 TX OE : PASS
9080 09:26:20.678841 All Pass.
9081 09:26:20.678904
9082 09:26:20.678958 CH 1, Rank 1
9083 09:26:20.682306 SW Impedance : PASS
9084 09:26:20.682375 DUTY Scan : NO K
9085 09:26:20.685373 ZQ Calibration : PASS
9086 09:26:20.688443 Jitter Meter : NO K
9087 09:26:20.688506 CBT Training : PASS
9088 09:26:20.692226 Write leveling : PASS
9089 09:26:20.692288 RX DQS gating : PASS
9090 09:26:20.695400 RX DQ/DQS(RDDQC) : PASS
9091 09:26:20.699148 TX DQ/DQS : PASS
9092 09:26:20.699211 RX DATLAT : PASS
9093 09:26:20.702305 RX DQ/DQS(Engine): PASS
9094 09:26:20.705324 TX OE : PASS
9095 09:26:20.705416 All Pass.
9096 09:26:20.705519
9097 09:26:20.708920 DramC Write-DBI on
9098 09:26:20.708985 PER_BANK_REFRESH: Hybrid Mode
9099 09:26:20.712198 TX_TRACKING: ON
9100 09:26:20.718699 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9101 09:26:20.728559 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9102 09:26:20.735169 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9103 09:26:20.738844 [FAST_K] Save calibration result to emmc
9104 09:26:20.741826 sync common calibartion params.
9105 09:26:20.745781 sync cbt_mode0:1, 1:1
9106 09:26:20.745859 dram_init: ddr_geometry: 2
9107 09:26:20.748685 dram_init: ddr_geometry: 2
9108 09:26:20.751761 dram_init: ddr_geometry: 2
9109 09:26:20.751842 0:dram_rank_size:100000000
9110 09:26:20.755188 1:dram_rank_size:100000000
9111 09:26:20.762013 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9112 09:26:20.765148 DFS_SHUFFLE_HW_MODE: ON
9113 09:26:20.768895 dramc_set_vcore_voltage set vcore to 725000
9114 09:26:20.768976 Read voltage for 1600, 0
9115 09:26:20.771851 Vio18 = 0
9116 09:26:20.771931 Vcore = 725000
9117 09:26:20.772009 Vdram = 0
9118 09:26:20.775391 Vddq = 0
9119 09:26:20.775470 Vmddr = 0
9120 09:26:20.778591 switch to 3200 Mbps bootup
9121 09:26:20.778670 [DramcRunTimeConfig]
9122 09:26:20.778765 PHYPLL
9123 09:26:20.782208 DPM_CONTROL_AFTERK: ON
9124 09:26:20.785548 PER_BANK_REFRESH: ON
9125 09:26:20.785628 REFRESH_OVERHEAD_REDUCTION: ON
9126 09:26:20.789041 CMD_PICG_NEW_MODE: OFF
9127 09:26:20.791768 XRTWTW_NEW_MODE: ON
9128 09:26:20.791847 XRTRTR_NEW_MODE: ON
9129 09:26:20.795106 TX_TRACKING: ON
9130 09:26:20.795185 RDSEL_TRACKING: OFF
9131 09:26:20.798597 DQS Precalculation for DVFS: ON
9132 09:26:20.798677 RX_TRACKING: OFF
9133 09:26:20.802273 HW_GATING DBG: ON
9134 09:26:20.802351 ZQCS_ENABLE_LP4: ON
9135 09:26:20.805877 RX_PICG_NEW_MODE: ON
9136 09:26:20.809028 TX_PICG_NEW_MODE: ON
9137 09:26:20.809109 ENABLE_RX_DCM_DPHY: ON
9138 09:26:20.812247 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9139 09:26:20.815932 DUMMY_READ_FOR_TRACKING: OFF
9140 09:26:20.818815 !!! SPM_CONTROL_AFTERK: OFF
9141 09:26:20.818899 !!! SPM could not control APHY
9142 09:26:20.822366 IMPEDANCE_TRACKING: ON
9143 09:26:20.822446 TEMP_SENSOR: ON
9144 09:26:20.825878 HW_SAVE_FOR_SR: OFF
9145 09:26:20.828970 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9146 09:26:20.832493 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9147 09:26:20.835311 Read ODT Tracking: ON
9148 09:26:20.835390 Refresh Rate DeBounce: ON
9149 09:26:20.839040 DFS_NO_QUEUE_FLUSH: ON
9150 09:26:20.842182 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9151 09:26:20.845730 ENABLE_DFS_RUNTIME_MRW: OFF
9152 09:26:20.845809 DDR_RESERVE_NEW_MODE: ON
9153 09:26:20.848999 MR_CBT_SWITCH_FREQ: ON
9154 09:26:20.852038 =========================
9155 09:26:20.870024 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9156 09:26:20.873063 dram_init: ddr_geometry: 2
9157 09:26:20.891692 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9158 09:26:20.894529 dram_init: dram init end (result: 0)
9159 09:26:20.901125 DRAM-K: Full calibration passed in 24545 msecs
9160 09:26:20.904518 MRC: failed to locate region type 0.
9161 09:26:20.904598 DRAM rank0 size:0x100000000,
9162 09:26:20.908422 DRAM rank1 size=0x100000000
9163 09:26:20.918186 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9164 09:26:20.924820 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9165 09:26:20.931507 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9166 09:26:20.937928 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9167 09:26:20.941798 DRAM rank0 size:0x100000000,
9168 09:26:20.944931 DRAM rank1 size=0x100000000
9169 09:26:20.945011 CBMEM:
9170 09:26:20.947813 IMD: root @ 0xfffff000 254 entries.
9171 09:26:20.951406 IMD: root @ 0xffffec00 62 entries.
9172 09:26:20.954779 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9173 09:26:20.957851 WARNING: RO_VPD is uninitialized or empty.
9174 09:26:20.964571 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9175 09:26:20.974290 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9176 09:26:20.983957 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9177 09:26:20.995549 BS: romstage times (exec / console): total (unknown) / 24056 ms
9178 09:26:20.995634
9179 09:26:20.995713
9180 09:26:21.005874 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9181 09:26:21.009125 ARM64: Exception handlers installed.
9182 09:26:21.012158 ARM64: Testing exception
9183 09:26:21.015670 ARM64: Done test exception
9184 09:26:21.015752 Enumerating buses...
9185 09:26:21.019056 Show all devs... Before device enumeration.
9186 09:26:21.022237 Root Device: enabled 1
9187 09:26:21.025860 CPU_CLUSTER: 0: enabled 1
9188 09:26:21.025941 CPU: 00: enabled 1
9189 09:26:21.029001 Compare with tree...
9190 09:26:21.029096 Root Device: enabled 1
9191 09:26:21.032183 CPU_CLUSTER: 0: enabled 1
9192 09:26:21.035805 CPU: 00: enabled 1
9193 09:26:21.035884 Root Device scanning...
9194 09:26:21.038651 scan_static_bus for Root Device
9195 09:26:21.042376 CPU_CLUSTER: 0 enabled
9196 09:26:21.045630 scan_static_bus for Root Device done
9197 09:26:21.049250 scan_bus: bus Root Device finished in 8 msecs
9198 09:26:21.049330 done
9199 09:26:21.055674 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9200 09:26:21.059280 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9201 09:26:21.065860 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9202 09:26:21.068830 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9203 09:26:21.072239 Allocating resources...
9204 09:26:21.072318 Reading resources...
9205 09:26:21.079207 Root Device read_resources bus 0 link: 0
9206 09:26:21.079288 DRAM rank0 size:0x100000000,
9207 09:26:21.082368 DRAM rank1 size=0x100000000
9208 09:26:21.085542 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9209 09:26:21.088798 CPU: 00 missing read_resources
9210 09:26:21.092318 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9211 09:26:21.099261 Root Device read_resources bus 0 link: 0 done
9212 09:26:21.099333 Done reading resources.
9213 09:26:21.105674 Show resources in subtree (Root Device)...After reading.
9214 09:26:21.108755 Root Device child on link 0 CPU_CLUSTER: 0
9215 09:26:21.112507 CPU_CLUSTER: 0 child on link 0 CPU: 00
9216 09:26:21.122311 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9217 09:26:21.122382 CPU: 00
9218 09:26:21.125934 Root Device assign_resources, bus 0 link: 0
9219 09:26:21.128833 CPU_CLUSTER: 0 missing set_resources
9220 09:26:21.132487 Root Device assign_resources, bus 0 link: 0 done
9221 09:26:21.136148 Done setting resources.
9222 09:26:21.142294 Show resources in subtree (Root Device)...After assigning values.
9223 09:26:21.145878 Root Device child on link 0 CPU_CLUSTER: 0
9224 09:26:21.149300 CPU_CLUSTER: 0 child on link 0 CPU: 00
9225 09:26:21.159041 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9226 09:26:21.159113 CPU: 00
9227 09:26:21.162213 Done allocating resources.
9228 09:26:21.165865 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9229 09:26:21.168847 Enabling resources...
9230 09:26:21.168916 done.
9231 09:26:21.172754 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9232 09:26:21.175645 Initializing devices...
9233 09:26:21.175714 Root Device init
9234 09:26:21.179255 init hardware done!
9235 09:26:21.182300 0x00000018: ctrlr->caps
9236 09:26:21.182371 52.000 MHz: ctrlr->f_max
9237 09:26:21.185876 0.400 MHz: ctrlr->f_min
9238 09:26:21.188859 0x40ff8080: ctrlr->voltages
9239 09:26:21.188928 sclk: 390625
9240 09:26:21.192663 Bus Width = 1
9241 09:26:21.192728 sclk: 390625
9242 09:26:21.192784 Bus Width = 1
9243 09:26:21.195743 Early init status = 3
9244 09:26:21.199055 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9245 09:26:21.206340 in-header: 03 fc 00 00 01 00 00 00
9246 09:26:21.206416 in-data: 00
9247 09:26:21.209389 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9248 09:26:21.214683 in-header: 03 fd 00 00 00 00 00 00
9249 09:26:21.218357 in-data:
9250 09:26:21.221399 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9251 09:26:21.225830 in-header: 03 fc 00 00 01 00 00 00
9252 09:26:21.228871 in-data: 00
9253 09:26:21.232664 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9254 09:26:21.237991 in-header: 03 fd 00 00 00 00 00 00
9255 09:26:21.241407 in-data:
9256 09:26:21.244676 [SSUSB] Setting up USB HOST controller...
9257 09:26:21.248281 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9258 09:26:21.251341 [SSUSB] phy power-on done.
9259 09:26:21.254849 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9260 09:26:21.261365 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9261 09:26:21.264467 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9262 09:26:21.271834 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9263 09:26:21.277855 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9264 09:26:21.284706 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9265 09:26:21.291408 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9266 09:26:21.297926 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9267 09:26:21.298031 SPM: binary array size = 0x9dc
9268 09:26:21.304625 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9269 09:26:21.311309 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9270 09:26:21.318166 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9271 09:26:21.321477 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9272 09:26:21.324641 configure_display: Starting display init
9273 09:26:21.361046 anx7625_power_on_init: Init interface.
9274 09:26:21.364440 anx7625_disable_pd_protocol: Disabled PD feature.
9275 09:26:21.367817 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9276 09:26:21.395948 anx7625_start_dp_work: Secure OCM version=00
9277 09:26:21.398884 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9278 09:26:21.413641 sp_tx_get_edid_block: EDID Block = 1
9279 09:26:21.516096 Extracted contents:
9280 09:26:21.519728 header: 00 ff ff ff ff ff ff 00
9281 09:26:21.522751 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9282 09:26:21.526393 version: 01 04
9283 09:26:21.529460 basic params: 95 1f 11 78 0a
9284 09:26:21.533159 chroma info: 76 90 94 55 54 90 27 21 50 54
9285 09:26:21.536148 established: 00 00 00
9286 09:26:21.542882 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9287 09:26:21.546291 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9288 09:26:21.552697 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9289 09:26:21.559551 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9290 09:26:21.566369 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9291 09:26:21.569399 extensions: 00
9292 09:26:21.569467 checksum: fb
9293 09:26:21.569524
9294 09:26:21.572467 Manufacturer: IVO Model 57d Serial Number 0
9295 09:26:21.576353 Made week 0 of 2020
9296 09:26:21.576433 EDID version: 1.4
9297 09:26:21.579388 Digital display
9298 09:26:21.582694 6 bits per primary color channel
9299 09:26:21.582776 DisplayPort interface
9300 09:26:21.585880 Maximum image size: 31 cm x 17 cm
9301 09:26:21.589518 Gamma: 220%
9302 09:26:21.589598 Check DPMS levels
9303 09:26:21.593062 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9304 09:26:21.595982 First detailed timing is preferred timing
9305 09:26:21.599453 Established timings supported:
9306 09:26:21.602893 Standard timings supported:
9307 09:26:21.602972 Detailed timings
9308 09:26:21.609148 Hex of detail: 383680a07038204018303c0035ae10000019
9309 09:26:21.612899 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9310 09:26:21.619503 0780 0798 07c8 0820 hborder 0
9311 09:26:21.622771 0438 043b 0447 0458 vborder 0
9312 09:26:21.622851 -hsync -vsync
9313 09:26:21.626575 Did detailed timing
9314 09:26:21.629671 Hex of detail: 000000000000000000000000000000000000
9315 09:26:21.632630 Manufacturer-specified data, tag 0
9316 09:26:21.639336 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9317 09:26:21.639416 ASCII string: InfoVision
9318 09:26:21.646242 Hex of detail: 000000fe00523134304e574635205248200a
9319 09:26:21.649333 ASCII string: R140NWF5 RH
9320 09:26:21.649413 Checksum
9321 09:26:21.649491 Checksum: 0xfb (valid)
9322 09:26:21.655980 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9323 09:26:21.659440 DSI data_rate: 832800000 bps
9324 09:26:21.662666 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9325 09:26:21.666245 anx7625_parse_edid: pixelclock(138800).
9326 09:26:21.672673 hactive(1920), hsync(48), hfp(24), hbp(88)
9327 09:26:21.676310 vactive(1080), vsync(12), vfp(3), vbp(17)
9328 09:26:21.679291 anx7625_dsi_config: config dsi.
9329 09:26:21.686284 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9330 09:26:21.698612 anx7625_dsi_config: success to config DSI
9331 09:26:21.701620 anx7625_dp_start: MIPI phy setup OK.
9332 09:26:21.704925 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9333 09:26:21.708255 mtk_ddp_mode_set invalid vrefresh 60
9334 09:26:21.711613 main_disp_path_setup
9335 09:26:21.711708 ovl_layer_smi_id_en
9336 09:26:21.715132 ovl_layer_smi_id_en
9337 09:26:21.715212 ccorr_config
9338 09:26:21.715290 aal_config
9339 09:26:21.718431 gamma_config
9340 09:26:21.718511 postmask_config
9341 09:26:21.721480 dither_config
9342 09:26:21.725133 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9343 09:26:21.731360 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9344 09:26:21.734804 Root Device init finished in 553 msecs
9345 09:26:21.734884 CPU_CLUSTER: 0 init
9346 09:26:21.745110 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9347 09:26:21.748265 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9348 09:26:21.751984 APU_MBOX 0x190000b0 = 0x10001
9349 09:26:21.755210 APU_MBOX 0x190001b0 = 0x10001
9350 09:26:21.758279 APU_MBOX 0x190005b0 = 0x10001
9351 09:26:21.761456 APU_MBOX 0x190006b0 = 0x10001
9352 09:26:21.765008 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9353 09:26:21.777458 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9354 09:26:21.789883 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9355 09:26:21.796208 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9356 09:26:21.808072 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9357 09:26:21.817327 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9358 09:26:21.820337 CPU_CLUSTER: 0 init finished in 81 msecs
9359 09:26:21.823632 Devices initialized
9360 09:26:21.827192 Show all devs... After init.
9361 09:26:21.827264 Root Device: enabled 1
9362 09:26:21.830562 CPU_CLUSTER: 0: enabled 1
9363 09:26:21.833925 CPU: 00: enabled 1
9364 09:26:21.837188 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9365 09:26:21.840438 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9366 09:26:21.843573 ELOG: NV offset 0x57f000 size 0x1000
9367 09:26:21.850425 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9368 09:26:21.856913 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9369 09:26:21.860118 ELOG: Event(17) added with size 13 at 2024-06-18 09:26:21 UTC
9370 09:26:21.863738 out: cmd=0x121: 03 db 21 01 00 00 00 00
9371 09:26:21.868054 in-header: 03 6c 00 00 2c 00 00 00
9372 09:26:21.881690 in-data: af 37 ea 1e b8 03 00 00 0a 00 00 00 06 80 00 00 62 84 c4 1d 06 80 00 00 85 7a b8 1e 06 80 00 00 93 7d c2 1e 06 80 00 00 51 b6 e9 1e
9373 09:26:21.888561 ELOG: Event(A1) added with size 10 at 2024-06-18 09:26:21 UTC
9374 09:26:21.895386 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9375 09:26:21.898549 ELOG: Event(A0) added with size 9 at 2024-06-18 09:26:21 UTC
9376 09:26:21.905370 elog_add_boot_reason: Logged dev mode boot
9377 09:26:21.908319 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9378 09:26:21.911793 Finalize devices...
9379 09:26:21.911866 Devices finalized
9380 09:26:21.918430 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9381 09:26:21.922123 Writing coreboot table at 0xffe64000
9382 09:26:21.925135 0. 000000000010a000-0000000000113fff: RAMSTAGE
9383 09:26:21.928404 1. 0000000040000000-00000000400fffff: RAM
9384 09:26:21.932063 2. 0000000040100000-000000004032afff: RAMSTAGE
9385 09:26:21.935660 3. 000000004032b000-00000000545fffff: RAM
9386 09:26:21.941760 4. 0000000054600000-000000005465ffff: BL31
9387 09:26:21.945376 5. 0000000054660000-00000000ffe63fff: RAM
9388 09:26:21.948892 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9389 09:26:21.951816 7. 0000000100000000-000000023fffffff: RAM
9390 09:26:21.955116 Passing 5 GPIOs to payload:
9391 09:26:21.961881 NAME | PORT | POLARITY | VALUE
9392 09:26:21.965393 EC in RW | 0x000000aa | low | undefined
9393 09:26:21.968566 EC interrupt | 0x00000005 | low | undefined
9394 09:26:21.975045 TPM interrupt | 0x000000ab | high | undefined
9395 09:26:21.978712 SD card detect | 0x00000011 | high | undefined
9396 09:26:21.985461 speaker enable | 0x00000093 | high | undefined
9397 09:26:21.988723 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9398 09:26:21.991789 in-header: 03 f9 00 00 02 00 00 00
9399 09:26:21.991866 in-data: 02 00
9400 09:26:21.995590 ADC[4]: Raw value=900221 ID=7
9401 09:26:21.998659 ADC[3]: Raw value=213336 ID=1
9402 09:26:21.998737 RAM Code: 0x71
9403 09:26:22.001695 ADC[6]: Raw value=74557 ID=0
9404 09:26:22.005416 ADC[5]: Raw value=211860 ID=1
9405 09:26:22.005493 SKU Code: 0x1
9406 09:26:22.012266 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7e0e
9407 09:26:22.015193 coreboot table: 964 bytes.
9408 09:26:22.018589 IMD ROOT 0. 0xfffff000 0x00001000
9409 09:26:22.022125 IMD SMALL 1. 0xffffe000 0x00001000
9410 09:26:22.025189 RO MCACHE 2. 0xffffc000 0x00001104
9411 09:26:22.028932 CONSOLE 3. 0xfff7c000 0x00080000
9412 09:26:22.029010 FMAP 4. 0xfff7b000 0x00000452
9413 09:26:22.031969 TIME STAMP 5. 0xfff7a000 0x00000910
9414 09:26:22.035086 VBOOT WORK 6. 0xfff66000 0x00014000
9415 09:26:22.038878 RAMOOPS 7. 0xffe66000 0x00100000
9416 09:26:22.041917 COREBOOT 8. 0xffe64000 0x00002000
9417 09:26:22.045583 IMD small region:
9418 09:26:22.049015 IMD ROOT 0. 0xffffec00 0x00000400
9419 09:26:22.052314 VPD 1. 0xffffeb80 0x0000006c
9420 09:26:22.055425 MMC STATUS 2. 0xffffeb60 0x00000004
9421 09:26:22.062349 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9422 09:26:22.062424 Probing TPM: done!
9423 09:26:22.068811 Connected to device vid:did:rid of 1ae0:0028:00
9424 09:26:22.075191 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9425 09:26:22.078830 Initialized TPM device CR50 revision 0
9426 09:26:22.082367 Checking cr50 for pending updates
9427 09:26:22.087827 Reading cr50 TPM mode
9428 09:26:22.096497 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9429 09:26:22.103014 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9430 09:26:22.143020 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9431 09:26:22.146720 Checking segment from ROM address 0x40100000
9432 09:26:22.149795 Checking segment from ROM address 0x4010001c
9433 09:26:22.156512 Loading segment from ROM address 0x40100000
9434 09:26:22.156590 code (compression=0)
9435 09:26:22.163836 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9436 09:26:22.173736 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9437 09:26:22.173814 it's not compressed!
9438 09:26:22.180675 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9439 09:26:22.183575 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9440 09:26:22.204015 Loading segment from ROM address 0x4010001c
9441 09:26:22.204095 Entry Point 0x80000000
9442 09:26:22.206727 Loaded segments
9443 09:26:22.210115 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9444 09:26:22.217106 Jumping to boot code at 0x80000000(0xffe64000)
9445 09:26:22.224149 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9446 09:26:22.230238 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9447 09:26:22.237847 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9448 09:26:22.241455 Checking segment from ROM address 0x40100000
9449 09:26:22.245085 Checking segment from ROM address 0x4010001c
9450 09:26:22.251738 Loading segment from ROM address 0x40100000
9451 09:26:22.251809 code (compression=1)
9452 09:26:22.258088 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9453 09:26:22.268224 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9454 09:26:22.268304 using LZMA
9455 09:26:22.276516 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9456 09:26:22.283337 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9457 09:26:22.286580 Loading segment from ROM address 0x4010001c
9458 09:26:22.286650 Entry Point 0x54601000
9459 09:26:22.289792 Loaded segments
9460 09:26:22.292778 NOTICE: MT8192 bl31_setup
9461 09:26:22.300120 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9462 09:26:22.303155 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9463 09:26:22.306662 WARNING: region 0:
9464 09:26:22.310398 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 09:26:22.310474 WARNING: region 1:
9466 09:26:22.316825 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9467 09:26:22.320111 WARNING: region 2:
9468 09:26:22.323330 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9469 09:26:22.326797 WARNING: region 3:
9470 09:26:22.330126 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9471 09:26:22.333355 WARNING: region 4:
9472 09:26:22.339959 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9473 09:26:22.340034 WARNING: region 5:
9474 09:26:22.343261 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 09:26:22.346568 WARNING: region 6:
9476 09:26:22.350319 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 09:26:22.350384 WARNING: region 7:
9478 09:26:22.356552 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 09:26:22.363330 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9480 09:26:22.366919 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9481 09:26:22.369928 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9482 09:26:22.377111 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9483 09:26:22.380039 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9484 09:26:22.383330 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9485 09:26:22.390340 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9486 09:26:22.393392 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9487 09:26:22.397060 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9488 09:26:22.403701 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9489 09:26:22.406807 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9490 09:26:22.410592 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9491 09:26:22.416743 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9492 09:26:22.420473 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9493 09:26:22.426716 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9494 09:26:22.430398 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9495 09:26:22.433799 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9496 09:26:22.440609 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9497 09:26:22.443509 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9498 09:26:22.447190 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9499 09:26:22.453841 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9500 09:26:22.457086 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9501 09:26:22.463895 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9502 09:26:22.467357 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9503 09:26:22.470419 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9504 09:26:22.477355 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9505 09:26:22.480585 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9506 09:26:22.487045 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9507 09:26:22.490805 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9508 09:26:22.494180 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9509 09:26:22.500756 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9510 09:26:22.503850 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9511 09:26:22.507695 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9512 09:26:22.514310 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9513 09:26:22.517483 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9514 09:26:22.520572 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9515 09:26:22.524396 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9516 09:26:22.530680 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9517 09:26:22.534461 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9518 09:26:22.537352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9519 09:26:22.540798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9520 09:26:22.544364 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9521 09:26:22.551203 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9522 09:26:22.554104 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9523 09:26:22.557748 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9524 09:26:22.564335 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9525 09:26:22.567642 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9526 09:26:22.571100 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9527 09:26:22.574504 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9528 09:26:22.581090 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9529 09:26:22.584845 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9530 09:26:22.591498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9531 09:26:22.594693 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9532 09:26:22.598181 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9533 09:26:22.604754 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9534 09:26:22.608248 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9535 09:26:22.614822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9536 09:26:22.617821 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9537 09:26:22.624560 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9538 09:26:22.627803 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9539 09:26:22.634597 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9540 09:26:22.637798 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9541 09:26:22.641547 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9542 09:26:22.647824 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9543 09:26:22.651669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9544 09:26:22.657806 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9545 09:26:22.661389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9546 09:26:22.668023 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9547 09:26:22.671240 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9548 09:26:22.674874 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9549 09:26:22.681400 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9550 09:26:22.684997 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9551 09:26:22.691576 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9552 09:26:22.694637 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9553 09:26:22.698619 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9554 09:26:22.704857 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9555 09:26:22.708447 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9556 09:26:22.715018 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9557 09:26:22.718472 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9558 09:26:22.725237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9559 09:26:22.728223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9560 09:26:22.732042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9561 09:26:22.738208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9562 09:26:22.742097 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9563 09:26:22.748817 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9564 09:26:22.751785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9565 09:26:22.758898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9566 09:26:22.761918 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9567 09:26:22.765387 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9568 09:26:22.772021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9569 09:26:22.775060 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9570 09:26:22.781717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9571 09:26:22.785432 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9572 09:26:22.792124 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9573 09:26:22.795358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9574 09:26:22.799012 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9575 09:26:22.805729 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9576 09:26:22.808496 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9577 09:26:22.811923 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9578 09:26:22.815595 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9579 09:26:22.822318 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9580 09:26:22.825610 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9581 09:26:22.828946 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9582 09:26:22.835897 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9583 09:26:22.839365 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9584 09:26:22.845771 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9585 09:26:22.849195 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9586 09:26:22.852423 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9587 09:26:22.858977 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9588 09:26:22.862549 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9589 09:26:22.865608 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9590 09:26:22.872619 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9591 09:26:22.875685 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9592 09:26:22.882992 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9593 09:26:22.885966 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9594 09:26:22.889186 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9595 09:26:22.895932 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9596 09:26:22.899400 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9597 09:26:22.902518 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9598 09:26:22.909355 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9599 09:26:22.912581 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9600 09:26:22.915766 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9601 09:26:22.919394 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9602 09:26:22.922854 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9603 09:26:22.929644 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9604 09:26:22.932581 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9605 09:26:22.939449 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9606 09:26:22.942786 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9607 09:26:22.946241 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9608 09:26:22.953013 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9609 09:26:22.956336 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9610 09:26:22.962926 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9611 09:26:22.966338 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9612 09:26:22.969794 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9613 09:26:22.976386 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9614 09:26:22.979400 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9615 09:26:22.983250 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9616 09:26:22.989878 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9617 09:26:22.993023 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9618 09:26:22.999850 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9619 09:26:23.003334 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9620 09:26:23.006279 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9621 09:26:23.013239 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9622 09:26:23.016309 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9623 09:26:23.020017 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9624 09:26:23.026793 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9625 09:26:23.029860 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9626 09:26:23.036655 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9627 09:26:23.039814 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9628 09:26:23.043557 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9629 09:26:23.049824 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9630 09:26:23.053640 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9631 09:26:23.056682 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9632 09:26:23.063623 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9633 09:26:23.067060 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9634 09:26:23.073335 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9635 09:26:23.076845 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9636 09:26:23.080433 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9637 09:26:23.086974 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9638 09:26:23.090181 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9639 09:26:23.093524 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9640 09:26:23.100526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9641 09:26:23.103430 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9642 09:26:23.110676 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9643 09:26:23.113776 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9644 09:26:23.116756 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9645 09:26:23.123874 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9646 09:26:23.126968 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9647 09:26:23.133771 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9648 09:26:23.137188 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9649 09:26:23.140507 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9650 09:26:23.147218 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9651 09:26:23.150273 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9652 09:26:23.153424 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9653 09:26:23.160331 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9654 09:26:23.163813 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9655 09:26:23.170609 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9656 09:26:23.173665 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9657 09:26:23.176672 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9658 09:26:23.183937 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9659 09:26:23.186899 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9660 09:26:23.193740 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9661 09:26:23.197182 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9662 09:26:23.200239 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9663 09:26:23.207100 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9664 09:26:23.210246 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9665 09:26:23.213712 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9666 09:26:23.220634 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9667 09:26:23.223553 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9668 09:26:23.230420 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9669 09:26:23.233583 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9670 09:26:23.240307 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9671 09:26:23.243759 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9672 09:26:23.247397 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9673 09:26:23.253895 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9674 09:26:23.256917 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9675 09:26:23.263823 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9676 09:26:23.266829 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9677 09:26:23.270476 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9678 09:26:23.276765 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9679 09:26:23.280467 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9680 09:26:23.287222 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9681 09:26:23.290242 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9682 09:26:23.293718 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9683 09:26:23.300538 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9684 09:26:23.303691 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9685 09:26:23.310486 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9686 09:26:23.313596 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9687 09:26:23.317283 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9688 09:26:23.323831 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9689 09:26:23.327100 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9690 09:26:23.333794 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9691 09:26:23.336774 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9692 09:26:23.343465 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9693 09:26:23.347330 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9694 09:26:23.350195 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9695 09:26:23.357412 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9696 09:26:23.360418 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9697 09:26:23.367234 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9698 09:26:23.370213 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9699 09:26:23.373820 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9700 09:26:23.380652 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9701 09:26:23.383807 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9702 09:26:23.390422 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9703 09:26:23.393877 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9704 09:26:23.397352 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9705 09:26:23.404024 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9706 09:26:23.407230 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9707 09:26:23.413846 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9708 09:26:23.417088 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9709 09:26:23.420187 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9710 09:26:23.424073 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9711 09:26:23.430170 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9712 09:26:23.433881 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9713 09:26:23.436888 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9714 09:26:23.443954 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9715 09:26:23.447090 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9716 09:26:23.450457 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9717 09:26:23.456885 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9718 09:26:23.460323 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9719 09:26:23.463737 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9720 09:26:23.470464 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9721 09:26:23.473557 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9722 09:26:23.476823 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9723 09:26:23.483730 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9724 09:26:23.486835 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9725 09:26:23.493681 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9726 09:26:23.496770 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9727 09:26:23.500260 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9728 09:26:23.506831 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9729 09:26:23.510388 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9730 09:26:23.513496 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9731 09:26:23.520348 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9732 09:26:23.523487 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9733 09:26:23.527384 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9734 09:26:23.533403 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9735 09:26:23.537256 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9736 09:26:23.543513 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9737 09:26:23.547025 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9738 09:26:23.550183 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9739 09:26:23.557052 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9740 09:26:23.560159 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9741 09:26:23.563794 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9742 09:26:23.570103 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9743 09:26:23.573374 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9744 09:26:23.576775 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9745 09:26:23.583593 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9746 09:26:23.586919 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9747 09:26:23.590266 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9748 09:26:23.597233 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9749 09:26:23.600184 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9750 09:26:23.603803 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9751 09:26:23.606813 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9752 09:26:23.610125 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9753 09:26:23.616622 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9754 09:26:23.620033 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9755 09:26:23.623741 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9756 09:26:23.626914 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9757 09:26:23.633710 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9758 09:26:23.636804 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9759 09:26:23.640584 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9760 09:26:23.646592 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9761 09:26:23.650145 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9762 09:26:23.653382 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9763 09:26:23.660234 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9764 09:26:23.663273 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9765 09:26:23.670163 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9766 09:26:23.673728 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9767 09:26:23.679891 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9768 09:26:23.683519 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9769 09:26:23.687137 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9770 09:26:23.693229 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9771 09:26:23.696794 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9772 09:26:23.700180 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9773 09:26:23.706665 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9774 09:26:23.710013 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9775 09:26:23.716798 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9776 09:26:23.720077 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9777 09:26:23.723402 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9778 09:26:23.729921 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9779 09:26:23.733498 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9780 09:26:23.740267 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9781 09:26:23.743451 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9782 09:26:23.750206 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9783 09:26:23.753132 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9784 09:26:23.756799 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9785 09:26:23.762993 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9786 09:26:23.766763 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9787 09:26:23.773091 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9788 09:26:23.776797 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9789 09:26:23.779958 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9790 09:26:23.786881 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9791 09:26:23.789681 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9792 09:26:23.793337 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9793 09:26:23.800031 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9794 09:26:23.803180 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9795 09:26:23.809761 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9796 09:26:23.813483 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9797 09:26:23.819570 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9798 09:26:23.823077 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9799 09:26:23.826638 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9800 09:26:23.833334 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9801 09:26:23.836382 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9802 09:26:23.843249 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9803 09:26:23.846554 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9804 09:26:23.849539 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9805 09:26:23.856339 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9806 09:26:23.859881 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9807 09:26:23.866171 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9808 09:26:23.869954 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9809 09:26:23.872965 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9810 09:26:23.879736 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9811 09:26:23.882774 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9812 09:26:23.889675 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9813 09:26:23.892738 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9814 09:26:23.899537 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9815 09:26:23.903140 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9816 09:26:23.906305 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9817 09:26:23.912971 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9818 09:26:23.916393 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9819 09:26:23.923085 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9820 09:26:23.926147 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9821 09:26:23.929243 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9822 09:26:23.936560 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9823 09:26:23.939630 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9824 09:26:23.942814 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9825 09:26:23.949437 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9826 09:26:23.953197 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9827 09:26:23.959494 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9828 09:26:23.962639 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9829 09:26:23.969467 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9830 09:26:23.972779 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9831 09:26:23.976343 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9832 09:26:23.983189 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9833 09:26:23.986260 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9834 09:26:23.993059 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9835 09:26:23.996149 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9836 09:26:24.002908 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9837 09:26:24.006488 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9838 09:26:24.009602 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9839 09:26:24.016419 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9840 09:26:24.019408 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9841 09:26:24.025919 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9842 09:26:24.029640 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9843 09:26:24.032673 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9844 09:26:24.039387 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9845 09:26:24.042955 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9846 09:26:24.049794 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9847 09:26:24.052791 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9848 09:26:24.059554 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9849 09:26:24.062548 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9850 09:26:24.066179 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9851 09:26:24.072988 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9852 09:26:24.076123 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9853 09:26:24.083088 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9854 09:26:24.086289 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9855 09:26:24.092910 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9856 09:26:24.096014 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9857 09:26:24.099636 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9858 09:26:24.106274 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9859 09:26:24.109245 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9860 09:26:24.116086 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9861 09:26:24.119088 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9862 09:26:24.125871 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9863 09:26:24.129472 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9864 09:26:24.132935 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9865 09:26:24.139491 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9866 09:26:24.143126 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9867 09:26:24.149079 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9868 09:26:24.152836 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9869 09:26:24.159508 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9870 09:26:24.162651 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9871 09:26:24.169480 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9872 09:26:24.172595 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9873 09:26:24.176286 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9874 09:26:24.182891 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9875 09:26:24.186108 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9876 09:26:24.192533 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9877 09:26:24.196226 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9878 09:26:24.202291 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9879 09:26:24.205687 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9880 09:26:24.209364 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9881 09:26:24.216143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9882 09:26:24.219243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9883 09:26:24.226198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9884 09:26:24.229088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9885 09:26:24.236208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9886 09:26:24.239041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9887 09:26:24.242596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9888 09:26:24.249114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9889 09:26:24.252734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9890 09:26:24.259514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9891 09:26:24.262538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9892 09:26:25.700516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9893 09:26:25.700692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9894 09:26:25.700810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9895 09:26:25.700919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9896 09:26:25.701007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9897 09:26:25.701096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9898 09:26:25.701179 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9899 09:26:25.701261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9900 09:26:25.701342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9901 09:26:25.701423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9902 09:26:25.701504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9903 09:26:25.701584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9904 09:26:25.701665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9905 09:26:25.701745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9906 09:26:25.701825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9907 09:26:25.701905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9908 09:26:25.701993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9909 09:26:25.702088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9910 09:26:25.702166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9911 09:26:25.702244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9912 09:26:25.702338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9913 09:26:25.702470 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9914 09:26:25.702525 INFO: [APUAPC] vio 0
9915 09:26:25.702575 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9916 09:26:25.702626 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9917 09:26:25.702676 INFO: [APUAPC] D0_APC_0: 0x400510
9918 09:26:25.702727 INFO: [APUAPC] D0_APC_1: 0x0
9919 09:26:25.702778 INFO: [APUAPC] D0_APC_2: 0x1540
9920 09:26:25.702828 INFO: [APUAPC] D0_APC_3: 0x0
9921 09:26:25.702879 INFO: [APUAPC] D1_APC_0: 0xffffffff
9922 09:26:25.702929 INFO: [APUAPC] D1_APC_1: 0xffffffff
9923 09:26:25.702979 INFO: [APUAPC] D1_APC_2: 0x3fffff
9924 09:26:25.703028 INFO: [APUAPC] D1_APC_3: 0x0
9925 09:26:25.703078 INFO: [APUAPC] D2_APC_0: 0xffffffff
9926 09:26:25.703128 INFO: [APUAPC] D2_APC_1: 0xffffffff
9927 09:26:25.703193 INFO: [APUAPC] D2_APC_2: 0x3fffff
9928 09:26:25.703306 INFO: [APUAPC] D2_APC_3: 0x0
9929 09:26:25.703359 INFO: [APUAPC] D3_APC_0: 0xffffffff
9930 09:26:25.703412 INFO: [APUAPC] D3_APC_1: 0xffffffff
9931 09:26:25.703463 INFO: [APUAPC] D3_APC_2: 0x3fffff
9932 09:26:25.703514 INFO: [APUAPC] D3_APC_3: 0x0
9933 09:26:25.703578 INFO: [APUAPC] D4_APC_0: 0xffffffff
9934 09:26:25.703628 INFO: [APUAPC] D4_APC_1: 0xffffffff
9935 09:26:25.703679 INFO: [APUAPC] D4_APC_2: 0x3fffff
9936 09:26:25.703759 INFO: [APUAPC] D4_APC_3: 0x0
9937 09:26:25.703865 INFO: [APUAPC] D5_APC_0: 0xffffffff
9938 09:26:25.703930 INFO: [APUAPC] D5_APC_1: 0xffffffff
9939 09:26:25.703980 INFO: [APUAPC] D5_APC_2: 0x3fffff
9940 09:26:25.704030 INFO: [APUAPC] D5_APC_3: 0x0
9941 09:26:25.704080 INFO: [APUAPC] D6_APC_0: 0xffffffff
9942 09:26:25.704130 INFO: [APUAPC] D6_APC_1: 0xffffffff
9943 09:26:25.704209 INFO: [APUAPC] D6_APC_2: 0x3fffff
9944 09:26:25.704259 INFO: [APUAPC] D6_APC_3: 0x0
9945 09:26:25.704308 INFO: [APUAPC] D7_APC_0: 0xffffffff
9946 09:26:25.704358 INFO: [APUAPC] D7_APC_1: 0xffffffff
9947 09:26:25.704417 INFO: [APUAPC] D7_APC_2: 0x3fffff
9948 09:26:25.704468 INFO: [APUAPC] D7_APC_3: 0x0
9949 09:26:25.704518 INFO: [APUAPC] D8_APC_0: 0xffffffff
9950 09:26:25.704567 INFO: [APUAPC] D8_APC_1: 0xffffffff
9951 09:26:25.704616 INFO: [APUAPC] D8_APC_2: 0x3fffff
9952 09:26:25.704665 INFO: [APUAPC] D8_APC_3: 0x0
9953 09:26:25.704714 INFO: [APUAPC] D9_APC_0: 0xffffffff
9954 09:26:25.704764 INFO: [APUAPC] D9_APC_1: 0xffffffff
9955 09:26:25.704813 INFO: [APUAPC] D9_APC_2: 0x3fffff
9956 09:26:25.704863 INFO: [APUAPC] D9_APC_3: 0x0
9957 09:26:25.704912 INFO: [APUAPC] D10_APC_0: 0xffffffff
9958 09:26:25.704962 INFO: [APUAPC] D10_APC_1: 0xffffffff
9959 09:26:25.705012 INFO: [APUAPC] D10_APC_2: 0x3fffff
9960 09:26:25.705061 INFO: [APUAPC] D10_APC_3: 0x0
9961 09:26:25.705111 INFO: [APUAPC] D11_APC_0: 0xffffffff
9962 09:26:25.705160 INFO: [APUAPC] D11_APC_1: 0xffffffff
9963 09:26:25.705210 INFO: [APUAPC] D11_APC_2: 0x3fffff
9964 09:26:25.705259 INFO: [APUAPC] D11_APC_3: 0x0
9965 09:26:25.705308 INFO: [APUAPC] D12_APC_0: 0xffffffff
9966 09:26:25.705359 INFO: [APUAPC] D12_APC_1: 0xffffffff
9967 09:26:25.705408 INFO: [APUAPC] D12_APC_2: 0x3fffff
9968 09:26:25.705458 INFO: [APUAPC] D12_APC_3: 0x0
9969 09:26:25.705507 INFO: [APUAPC] D13_APC_0: 0xffffffff
9970 09:26:25.705556 INFO: [APUAPC] D13_APC_1: 0xffffffff
9971 09:26:25.705605 INFO: [APUAPC] D13_APC_2: 0x3fffff
9972 09:26:25.705655 INFO: [APUAPC] D13_APC_3: 0x0
9973 09:26:25.705712 INFO: [APUAPC] D14_APC_0: 0xffffffff
9974 09:26:25.705783 INFO: [APUAPC] D14_APC_1: 0xffffffff
9975 09:26:25.705834 INFO: [APUAPC] D14_APC_2: 0x3fffff
9976 09:26:25.705883 INFO: [APUAPC] D14_APC_3: 0x0
9977 09:26:25.705967 INFO: [APUAPC] D15_APC_0: 0xffffffff
9978 09:26:25.706083 INFO: [APUAPC] D15_APC_1: 0xffffffff
9979 09:26:25.706137 INFO: [APUAPC] D15_APC_2: 0x3fffff
9980 09:26:25.706188 INFO: [APUAPC] D15_APC_3: 0x0
9981 09:26:25.706238 INFO: [APUAPC] APC_CON: 0x4
9982 09:26:25.706288 INFO: [NOCDAPC] D0_APC_0: 0x0
9983 09:26:25.706338 INFO: [NOCDAPC] D0_APC_1: 0x0
9984 09:26:25.706388 INFO: [NOCDAPC] D1_APC_0: 0x0
9985 09:26:25.706437 INFO: [NOCDAPC] D1_APC_1: 0xfff
9986 09:26:25.706486 INFO: [NOCDAPC] D2_APC_0: 0x0
9987 09:26:25.706535 INFO: [NOCDAPC] D2_APC_1: 0xfff
9988 09:26:25.706585 INFO: [NOCDAPC] D3_APC_0: 0x0
9989 09:26:25.706634 INFO: [NOCDAPC] D3_APC_1: 0xfff
9990 09:26:25.706877 INFO: [NOCDAPC] D4_APC_0: 0x0
9991 09:26:25.706933 INFO: [NOCDAPC] D4_APC_1: 0xfff
9992 09:26:25.706984 INFO: [NOCDAPC] D5_APC_0: 0x0
9993 09:26:25.707034 INFO: [NOCDAPC] D5_APC_1: 0xfff
9994 09:26:25.707083 INFO: [NOCDAPC] D6_APC_0: 0x0
9995 09:26:25.707133 INFO: [NOCDAPC] D6_APC_1: 0xfff
9996 09:26:25.707182 INFO: [NOCDAPC] D7_APC_0: 0x0
9997 09:26:25.707233 INFO: [NOCDAPC] D7_APC_1: 0xfff
9998 09:26:25.707283 INFO: [NOCDAPC] D8_APC_0: 0x0
9999 09:26:25.707333 INFO: [NOCDAPC] D8_APC_1: 0xfff
10000 09:26:25.707382 INFO: [NOCDAPC] D9_APC_0: 0x0
10001 09:26:25.707431 INFO: [NOCDAPC] D9_APC_1: 0xfff
10002 09:26:25.707481 INFO: [NOCDAPC] D10_APC_0: 0x0
10003 09:26:25.707531 INFO: [NOCDAPC] D10_APC_1: 0xfff
10004 09:26:25.707581 INFO: [NOCDAPC] D11_APC_0: 0x0
10005 09:26:25.707632 INFO: [NOCDAPC] D11_APC_1: 0xfff
10006 09:26:25.707682 INFO: [NOCDAPC] D12_APC_0: 0x0
10007 09:26:25.707732 INFO: [NOCDAPC] D12_APC_1: 0xfff
10008 09:26:25.707782 INFO: [NOCDAPC] D13_APC_0: 0x0
10009 09:26:25.707831 INFO: [NOCDAPC] D13_APC_1: 0xfff
10010 09:26:25.707880 INFO: [NOCDAPC] D14_APC_0: 0x0
10011 09:26:25.707930 INFO: [NOCDAPC] D14_APC_1: 0xfff
10012 09:26:25.708005 INFO: [NOCDAPC] D15_APC_0: 0x0
10013 09:26:25.708060 INFO: [NOCDAPC] D15_APC_1: 0xfff
10014 09:26:25.708110 INFO: [NOCDAPC] APC_CON: 0x4
10015 09:26:25.708161 INFO: [APUAPC] set_apusys_apc done
10016 09:26:25.708211 INFO: [DEVAPC] devapc_init done
10017 09:26:25.708261 INFO: GICv3 without legacy support detected.
10018 09:26:25.708311 INFO: ARM GICv3 driver initialized in EL3
10019 09:26:25.708362 INFO: Maximum SPI INTID supported: 639
10020 09:26:25.708412 INFO: BL31: Initializing runtime services
10021 09:26:25.708462 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10022 09:26:25.708512 INFO: SPM: enable CPC mode
10023 09:26:25.708562 INFO: mcdi ready for mcusys-off-idle and system suspend
10024 09:26:25.708612 INFO: BL31: Preparing for EL3 exit to normal world
10025 09:26:25.708663 INFO: Entry point address = 0x80000000
10026 09:26:25.708713 INFO: SPSR = 0x8
10027 09:26:25.708762
10028 09:26:25.708810
10029 09:26:25.708874
10030 09:26:25.708936 Starting depthcharge on Spherion...
10031 09:26:25.708987
10032 09:26:25.709036 Wipe memory regions:
10033 09:26:25.709085
10034 09:26:25.709134 [0x00000040000000, 0x00000054600000)
10035 09:26:25.709184
10036 09:26:25.709234 [0x00000054660000, 0x00000080000000)
10037 09:26:25.709283
10038 09:26:25.709331 [0x000000821a7280, 0x000000ffe64000)
10039 09:26:25.709937 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10040 09:26:25.710069 start: 2.2.4 bootloader-commands (timeout 00:04:23) [common]
10041 09:26:25.710170 Setting prompt string to ['asurada:']
10042 09:26:25.710242 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:23)
10043 09:26:25.882955
10044 09:26:25.883071 [0x00000100000000, 0x00000240000000)
10045 09:26:27.773424
10046 09:26:27.776711 Initializing XHCI USB controller at 0x11200000.
10047 09:26:28.815406
10048 09:26:28.818298 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10049 09:26:28.818386
10050 09:26:28.818448
10051 09:26:28.818715 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10053 09:26:28.919068 asurada: tftpboot 192.168.201.1 14407640/tftp-deploy-n564n2y3/kernel/image.itb 14407640/tftp-deploy-n564n2y3/kernel/cmdline
10054 09:26:28.919272 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10055 09:26:28.919351 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10056 09:26:28.923406 tftpboot 192.168.201.1 14407640/tftp-deploy-n564n2y3/kernel/image.ittp-deploy-n564n2y3/kernel/cmdline
10057 09:26:28.923525
10058 09:26:28.923626 Waiting for link
10059 09:26:29.081967
10060 09:26:29.082122 R8152: Initializing
10061 09:26:29.082183
10062 09:26:29.085181 Version 6 (ocp_data = 5c30)
10063 09:26:29.085258
10064 09:26:29.088287 R8152: Done initializing
10065 09:26:29.088364
10066 09:26:29.088424 Adding net device
10067 09:26:31.025006
10068 09:26:31.025150 done.
10069 09:26:31.025237
10070 09:26:31.025321 MAC: 00:24:32:30:78:52
10071 09:26:31.025402
10072 09:26:31.028290 Sending DHCP discover... done.
10073 09:26:31.028370
10074 09:26:31.032066 Waiting for reply... done.
10075 09:26:31.032157
10076 09:26:31.035144 Sending DHCP request... done.
10077 09:26:31.035222
10078 09:26:31.038667 Waiting for reply... done.
10079 09:26:31.038745
10080 09:26:31.038805 My ip is 192.168.201.14
10081 09:26:31.038862
10082 09:26:31.041632 The DHCP server ip is 192.168.201.1
10083 09:26:31.041732
10084 09:26:31.048591 TFTP server IP predefined by user: 192.168.201.1
10085 09:26:31.048670
10086 09:26:31.051676 Bootfile predefined by user: 14407640/tftp-deploy-n564n2y3/kernel/image.itb
10087 09:26:31.054910
10088 09:26:31.054988 Sending tftp read request... done.
10089 09:26:31.055049
10090 09:26:31.062103 Waiting for the transfer...
10091 09:26:31.062182
10092 09:26:31.598360 00000000 ################################################################
10093 09:26:31.598476
10094 09:26:32.146277 00080000 ################################################################
10095 09:26:32.146393
10096 09:26:32.701254 00100000 ################################################################
10097 09:26:32.701370
10098 09:26:33.238837 00180000 ################################################################
10099 09:26:33.238962
10100 09:26:33.767954 00200000 ################################################################
10101 09:26:33.768076
10102 09:26:34.312647 00280000 ################################################################
10103 09:26:34.312777
10104 09:26:34.861206 00300000 ################################################################
10105 09:26:34.861341
10106 09:26:35.411031 00380000 ################################################################
10107 09:26:35.411149
10108 09:26:35.992714 00400000 ################################################################
10109 09:26:35.993177
10110 09:26:36.564903 00480000 ################################################################
10111 09:26:36.565023
10112 09:26:37.111439 00500000 ################################################################
10113 09:26:37.111558
10114 09:26:37.679962 00580000 ################################################################
10115 09:26:37.680101
10116 09:26:38.275580 00600000 ################################################################
10117 09:26:38.275702
10118 09:26:38.830552 00680000 ################################################################
10119 09:26:38.830670
10120 09:26:39.513786 00700000 ################################################################
10121 09:26:39.513904
10122 09:26:40.162744 00780000 ################################################################
10123 09:26:40.163233
10124 09:26:40.814587 00800000 ################################################################
10125 09:26:40.814707
10126 09:26:41.506662 00880000 ################################################################
10127 09:26:41.507154
10128 09:26:42.236114 00900000 ################################################################
10129 09:26:42.236607
10130 09:26:42.959898 00980000 ################################################################
10131 09:26:42.960083
10132 09:26:43.616783 00a00000 ################################################################
10133 09:26:43.616900
10134 09:26:44.290403 00a80000 ################################################################
10135 09:26:44.290893
10136 09:26:44.978294 00b00000 ################################################################
10137 09:26:44.978449
10138 09:26:45.584017 00b80000 ################################################################
10139 09:26:45.584473
10140 09:26:46.172782 00c00000 ################################################################
10141 09:26:46.172912
10142 09:26:46.734321 00c80000 ################################################################
10143 09:26:46.734491
10144 09:26:47.378846 00d00000 ################################################################
10145 09:26:47.379061
10146 09:26:48.056923 00d80000 ################################################################
10147 09:26:48.057455
10148 09:26:48.654963 00e00000 ################################################################
10149 09:26:48.655109
10150 09:26:49.277497 00e80000 ################################################################
10151 09:26:49.277668
10152 09:26:49.931448 00f00000 ################################################################
10153 09:26:49.931946
10154 09:26:50.600145 00f80000 ################################################################
10155 09:26:50.600455
10156 09:26:51.258139 01000000 ################################################################
10157 09:26:51.258760
10158 09:26:51.891940 01080000 ################################################################
10159 09:26:51.892070
10160 09:26:52.502465 01100000 ################################################################
10161 09:26:52.502588
10162 09:26:53.186560 01180000 ################################################################
10163 09:26:53.186694
10164 09:26:53.867022 01200000 ################################################################
10165 09:26:53.867149
10166 09:26:54.478625 01280000 ################################################################
10167 09:26:54.478747
10168 09:26:55.035070 01300000 ################################################################
10169 09:26:55.035209
10170 09:26:55.608109 01380000 ################################################################
10171 09:26:55.608225
10172 09:26:56.185204 01400000 ################################################################
10173 09:26:56.185347
10174 09:26:56.769759 01480000 ################################################################
10175 09:26:56.769894
10176 09:26:57.351454 01500000 ################################################################
10177 09:26:57.351606
10178 09:26:57.927972 01580000 ################################################################
10179 09:26:57.928118
10180 09:26:58.504857 01600000 ################################################################
10181 09:26:58.505011
10182 09:26:59.153167 01680000 ################################################################
10183 09:26:59.153287
10184 09:26:59.714262 01700000 ################################################################
10185 09:26:59.714397
10186 09:27:00.274445 01780000 ################################################################
10187 09:27:00.274578
10188 09:27:00.840549 01800000 ################################################################
10189 09:27:00.840696
10190 09:27:01.418340 01880000 ################################################################
10191 09:27:01.418490
10192 09:27:01.982554 01900000 ################################################################
10193 09:27:01.982680
10194 09:27:02.601834 01980000 ################################################################
10195 09:27:02.602020
10196 09:27:03.199191 01a00000 ################################################################
10197 09:27:03.199324
10198 09:27:03.784152 01a80000 ################################################################
10199 09:27:03.784287
10200 09:27:04.438887 01b00000 ################################################################
10201 09:27:04.439024
10202 09:27:05.084279 01b80000 ################################################################
10203 09:27:05.084430
10204 09:27:05.721481 01c00000 ################################################################
10205 09:27:05.721620
10206 09:27:06.354957 01c80000 ################################################################
10207 09:27:06.355130
10208 09:27:06.942265 01d00000 ################################################################
10209 09:27:06.942402
10210 09:27:07.485037 01d80000 ################################################################
10211 09:27:07.485169
10212 09:27:08.059132 01e00000 ################################################################
10213 09:27:08.059253
10214 09:27:08.709519 01e80000 ################################################################
10215 09:27:08.709640
10216 09:27:09.334508 01f00000 ################################################################
10217 09:27:09.334635
10218 09:27:09.889901 01f80000 ################################################################
10219 09:27:09.890061
10220 09:27:10.444816 02000000 ################################################################
10221 09:27:10.444990
10222 09:27:11.006672 02080000 ################################################################
10223 09:27:11.006878
10224 09:27:11.701619 02100000 ################################################################
10225 09:27:11.702008
10226 09:27:12.381288 02180000 ################################################################
10227 09:27:12.381453
10228 09:27:13.052533 02200000 ################################################################
10229 09:27:13.053208
10230 09:27:13.729341 02280000 ################################################################
10231 09:27:13.729817
10232 09:27:14.367783 02300000 ################################################################
10233 09:27:14.367918
10234 09:27:15.030749 02380000 ################################################################
10235 09:27:15.031420
10236 09:27:15.719711 02400000 ################################################################
10237 09:27:15.720412
10238 09:27:16.356195 02480000 ################################################################
10239 09:27:16.356888
10240 09:27:17.013667 02500000 ################################################################
10241 09:27:17.013813
10242 09:27:17.733519 02580000 ################################################################
10243 09:27:17.734286
10244 09:27:18.442513 02600000 ################################################################
10245 09:27:18.442634
10246 09:27:19.104507 02680000 ################################################################
10247 09:27:19.104650
10248 09:27:19.782992 02700000 ################################################################
10249 09:27:19.783110
10250 09:27:20.451173 02780000 ################################################################
10251 09:27:20.451320
10252 09:27:21.071901 02800000 ################################################################
10253 09:27:21.072563
10254 09:27:21.676723 02880000 ################################################################
10255 09:27:21.676837
10256 09:27:22.273144 02900000 ################################################################
10257 09:27:22.273260
10258 09:27:22.919918 02980000 ################################################################
10259 09:27:22.920471
10260 09:27:23.539760 02a00000 ################################################################
10261 09:27:23.539877
10262 09:27:24.192839 02a80000 ################################################################
10263 09:27:24.192986
10264 09:27:24.839616 02b00000 ################################################################
10265 09:27:24.839762
10266 09:27:25.482005 02b80000 ################################################################
10267 09:27:25.482167
10268 09:27:26.107889 02c00000 ################################################################
10269 09:27:26.108052
10270 09:27:26.748190 02c80000 ################################################################
10271 09:27:26.748307
10272 09:27:27.390688 02d00000 ################################################################
10273 09:27:27.390844
10274 09:27:28.038955 02d80000 ################################################################
10275 09:27:28.039089
10276 09:27:28.672812 02e00000 ################################################################
10277 09:27:28.672928
10278 09:27:29.298964 02e80000 ################################################################
10279 09:27:29.299090
10280 09:27:29.932489 02f00000 ################################################################
10281 09:27:29.932614
10282 09:27:30.557729 02f80000 ################################################################
10283 09:27:30.557884
10284 09:27:31.179240 03000000 ################################################################
10285 09:27:31.179374
10286 09:27:31.826680 03080000 ################################################################
10287 09:27:31.826818
10288 09:27:32.467606 03100000 ################################################################
10289 09:27:32.467728
10290 09:27:34.083832 03180000 ################################################################
10291 09:27:34.084807
10292 09:27:34.085658 03200000 ################################################################
10293 09:27:34.086413
10294 09:27:34.358298 03280000 ################################################################
10295 09:27:34.358436
10296 09:27:35.028373 03300000 ################################################################
10297 09:27:35.028508
10298 09:27:35.721262 03380000 ################################################################
10299 09:27:35.721779
10300 09:27:36.373448 03400000 ################################################################
10301 09:27:36.373576
10302 09:27:37.002444 03480000 ################################################################
10303 09:27:37.002575
10304 09:27:37.651008 03500000 ################################################################
10305 09:27:37.651142
10306 09:27:38.326066 03580000 ################################################################
10307 09:27:38.326196
10308 09:27:39.010858 03600000 ################################################################
10309 09:27:39.010986
10310 09:27:39.674583 03680000 ################################################################
10311 09:27:39.674720
10312 09:27:40.359033 03700000 ################################################################
10313 09:27:40.359166
10314 09:27:40.938063 03780000 ################################################################
10315 09:27:40.938193
10316 09:27:41.514778 03800000 ################################################################
10317 09:27:41.514914
10318 09:27:42.186225 03880000 ################################################################
10319 09:27:42.186359
10320 09:27:42.854628 03900000 ################################################################
10321 09:27:42.854772
10322 09:27:43.517863 03980000 ################################################################
10323 09:27:43.518057
10324 09:27:44.193404 03a00000 ################################################################
10325 09:27:44.193532
10326 09:27:44.881126 03a80000 ################################################################
10327 09:27:44.881256
10328 09:27:45.548981 03b00000 ################################################################
10329 09:27:45.549119
10330 09:27:46.227060 03b80000 ################################################################
10331 09:27:46.227226
10332 09:27:46.904643 03c00000 ################################################################
10333 09:27:46.904787
10334 09:27:47.581592 03c80000 ################################################################
10335 09:27:47.581731
10336 09:27:48.250076 03d00000 ################################################################
10337 09:27:48.250222
10338 09:27:48.924414 03d80000 ################################################################
10339 09:27:48.924568
10340 09:27:49.333443 03e00000 ###################################### done.
10341 09:27:49.333617
10342 09:27:49.336844 The bootfile was 65322354 bytes long.
10343 09:27:49.336958
10344 09:27:49.340462 Sending tftp read request... done.
10345 09:27:49.340555
10346 09:27:49.340647 Waiting for the transfer...
10347 09:27:49.340740
10348 09:27:49.343397 00000000 # done.
10349 09:27:49.343477
10350 09:27:49.350417 Command line loaded dynamically from TFTP file: 14407640/tftp-deploy-n564n2y3/kernel/cmdline
10351 09:27:49.350494
10352 09:27:49.363552 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10353 09:27:49.363631
10354 09:27:49.366689 Loading FIT.
10355 09:27:49.366768
10356 09:27:49.370086 Image ramdisk-1 has 52146341 bytes.
10357 09:27:49.370159
10358 09:27:49.370225 Image fdt-1 has 47258 bytes.
10359 09:27:49.370281
10360 09:27:49.373588 Image kernel-1 has 13126726 bytes.
10361 09:27:49.373666
10362 09:27:49.383190 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10363 09:27:49.383264
10364 09:27:49.400361 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10365 09:27:49.400453
10366 09:27:49.406815 Choosing best match conf-1 for compat google,spherion-rev2.
10367 09:27:49.410639
10368 09:27:49.439711 Connected to device vid:did:rid of 1ae0:0028:00
10369 09:27:49.450765
10370 09:27:49.453848 tpm_get_response: command 0x17b, return code 0x0
10371 09:27:49.453976
10372 09:27:49.457463 ec_init: CrosEC protocol v3 supported (256, 248)
10373 09:27:49.460999
10374 09:27:49.464354 tpm_cleanup: add release locality here.
10375 09:27:49.464511
10376 09:27:49.464638 Shutting down all USB controllers.
10377 09:27:49.467779
10378 09:27:49.467969 Removing current net device
10379 09:27:49.468116
10380 09:27:49.474658 Exiting depthcharge with code 4 at timestamp: 114069351
10381 09:27:49.474870
10382 09:27:49.478071 LZMA decompressing kernel-1 to 0x821a6718
10383 09:27:49.478328
10384 09:27:49.481244 LZMA decompressing kernel-1 to 0x40000000
10385 09:27:51.098561
10386 09:27:51.098713 jumping to kernel
10387 09:27:51.099789 end: 2.2.4 bootloader-commands (duration 00:01:25) [common]
10388 09:27:51.099914 start: 2.2.5 auto-login-action (timeout 00:02:58) [common]
10389 09:27:51.100026 Setting prompt string to ['Linux version [0-9]']
10390 09:27:51.100139 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10391 09:27:51.100238 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10392 09:27:51.180755
10393 09:27:51.183950 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10394 09:27:51.187811 start: 2.2.5.1 login-action (timeout 00:02:57) [common]
10395 09:27:51.187914 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10396 09:27:51.187982 Setting prompt string to []
10397 09:27:51.188063 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10398 09:27:51.188215 Using line separator: #'\n'#
10399 09:27:51.188300 No login prompt set.
10400 09:27:51.188382 Parsing kernel messages
10401 09:27:51.188435 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10402 09:27:51.188538 [login-action] Waiting for messages, (timeout 00:02:57)
10403 09:27:51.188603 Waiting using forced prompt support (timeout 00:01:29)
10404 09:27:51.207587 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
10405 09:27:51.210503 [ 0.000000] random: crng init done
10406 09:27:51.214235 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10407 09:27:51.217405 [ 0.000000] efi: UEFI not found.
10408 09:27:51.227510 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10409 09:27:51.234208 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10410 09:27:51.244187 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10411 09:27:51.253895 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10412 09:27:51.260639 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10413 09:27:51.263760 [ 0.000000] printk: bootconsole [mtk8250] enabled
10414 09:27:51.272565 [ 0.000000] NUMA: No NUMA configuration found
10415 09:27:51.279253 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10416 09:27:51.286004 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10417 09:27:51.286084 [ 0.000000] Zone ranges:
10418 09:27:51.292497 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10419 09:27:51.295812 [ 0.000000] DMA32 empty
10420 09:27:51.302310 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10421 09:27:51.305479 [ 0.000000] Movable zone start for each node
10422 09:27:51.308791 [ 0.000000] Early memory node ranges
10423 09:27:51.315485 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10424 09:27:51.322229 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10425 09:27:51.328763 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10426 09:27:51.335574 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10427 09:27:51.342483 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10428 09:27:51.348787 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10429 09:27:51.405672 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10430 09:27:51.412206 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10431 09:27:51.418620 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10432 09:27:51.422001 [ 0.000000] psci: probing for conduit method from DT.
10433 09:27:51.428797 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10434 09:27:51.432240 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10435 09:27:51.438790 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10436 09:27:51.441780 [ 0.000000] psci: SMC Calling Convention v1.2
10437 09:27:51.448984 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10438 09:27:51.452100 [ 0.000000] Detected VIPT I-cache on CPU0
10439 09:27:51.458793 [ 0.000000] CPU features: detected: GIC system register CPU interface
10440 09:27:51.465630 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10441 09:27:51.472011 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10442 09:27:51.478838 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10443 09:27:51.485488 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10444 09:27:51.492266 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10445 09:27:51.498962 [ 0.000000] alternatives: applying boot alternatives
10446 09:27:51.501996 [ 0.000000] Fallback order for Node 0: 0
10447 09:27:51.508725 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10448 09:27:51.511836 [ 0.000000] Policy zone: Normal
10449 09:27:51.528913 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10450 09:27:51.538527 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10451 09:27:51.549365 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10452 09:27:51.559531 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10453 09:27:51.566256 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10454 09:27:51.569383 <6>[ 0.000000] software IO TLB: area num 8.
10455 09:27:51.625883 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10456 09:27:51.775170 <6>[ 0.000000] Memory: 7913136K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 439632K reserved, 32768K cma-reserved)
10457 09:27:51.781796 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10458 09:27:51.788380 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10459 09:27:51.792003 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10460 09:27:51.798284 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10461 09:27:51.804927 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10462 09:27:51.808350 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10463 09:27:51.818418 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10464 09:27:51.825026 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10465 09:27:51.828546 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10466 09:27:51.836308 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10467 09:27:51.839432 <6>[ 0.000000] GICv3: 608 SPIs implemented
10468 09:27:51.846098 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10469 09:27:51.849553 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10470 09:27:51.853004 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10471 09:27:51.859717 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10472 09:27:51.873475 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10473 09:27:51.886289 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10474 09:27:51.893353 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10475 09:27:51.901275 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10476 09:27:51.914870 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10477 09:27:51.921412 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10478 09:27:51.928497 <6>[ 0.009182] Console: colour dummy device 80x25
10479 09:27:51.937971 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10480 09:27:51.944527 <6>[ 0.024414] pid_max: default: 32768 minimum: 301
10481 09:27:51.948183 <6>[ 0.029316] LSM: Security Framework initializing
10482 09:27:51.954880 <6>[ 0.034255] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10483 09:27:51.964662 <6>[ 0.042068] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10484 09:27:51.971338 <6>[ 0.051491] cblist_init_generic: Setting adjustable number of callback queues.
10485 09:27:51.977696 <6>[ 0.058933] cblist_init_generic: Setting shift to 3 and lim to 1.
10486 09:27:51.987899 <6>[ 0.065311] cblist_init_generic: Setting adjustable number of callback queues.
10487 09:27:51.991402 <6>[ 0.072784] cblist_init_generic: Setting shift to 3 and lim to 1.
10488 09:27:51.997902 <6>[ 0.079185] rcu: Hierarchical SRCU implementation.
10489 09:27:52.004670 <6>[ 0.084200] rcu: Max phase no-delay instances is 1000.
10490 09:27:52.011671 <6>[ 0.091224] EFI services will not be available.
10491 09:27:52.014542 <6>[ 0.096182] smp: Bringing up secondary CPUs ...
10492 09:27:52.022409 <6>[ 0.101235] Detected VIPT I-cache on CPU1
10493 09:27:52.028886 <6>[ 0.101306] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10494 09:27:52.035786 <6>[ 0.101339] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10495 09:27:52.038906 <6>[ 0.101679] Detected VIPT I-cache on CPU2
10496 09:27:52.045776 <6>[ 0.101733] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10497 09:27:52.053069 <6>[ 0.101751] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10498 09:27:52.059701 <6>[ 0.102010] Detected VIPT I-cache on CPU3
10499 09:27:52.066317 <6>[ 0.102057] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10500 09:27:52.073028 <6>[ 0.102071] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10501 09:27:52.075977 <6>[ 0.102378] CPU features: detected: Spectre-v4
10502 09:27:52.082703 <6>[ 0.102384] CPU features: detected: Spectre-BHB
10503 09:27:52.085617 <6>[ 0.102389] Detected PIPT I-cache on CPU4
10504 09:27:52.092835 <6>[ 0.102450] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10505 09:27:52.099336 <6>[ 0.102466] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10506 09:27:52.102356 <6>[ 0.102760] Detected PIPT I-cache on CPU5
10507 09:27:52.112524 <6>[ 0.102824] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10508 09:27:52.119216 <6>[ 0.102840] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10509 09:27:52.122353 <6>[ 0.103124] Detected PIPT I-cache on CPU6
10510 09:27:52.128692 <6>[ 0.103192] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10511 09:27:52.135480 <6>[ 0.103208] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10512 09:27:52.138952 <6>[ 0.103504] Detected PIPT I-cache on CPU7
10513 09:27:52.148705 <6>[ 0.103570] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10514 09:27:52.155102 <6>[ 0.103586] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10515 09:27:52.158667 <6>[ 0.103633] smp: Brought up 1 node, 8 CPUs
10516 09:27:52.165228 <6>[ 0.244873] SMP: Total of 8 processors activated.
10517 09:27:52.168415 <6>[ 0.249795] CPU features: detected: 32-bit EL0 Support
10518 09:27:52.178148 <6>[ 0.255158] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10519 09:27:52.185259 <6>[ 0.263958] CPU features: detected: Common not Private translations
10520 09:27:52.188368 <6>[ 0.270474] CPU features: detected: CRC32 instructions
10521 09:27:52.194951 <6>[ 0.275825] CPU features: detected: RCpc load-acquire (LDAPR)
10522 09:27:52.201872 <6>[ 0.281785] CPU features: detected: LSE atomic instructions
10523 09:27:52.208613 <6>[ 0.287567] CPU features: detected: Privileged Access Never
10524 09:27:52.211645 <6>[ 0.293346] CPU features: detected: RAS Extension Support
10525 09:27:52.218205 <6>[ 0.298955] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10526 09:27:52.225163 <6>[ 0.306218] CPU: All CPU(s) started at EL2
10527 09:27:52.231579 <6>[ 0.310535] alternatives: applying system-wide alternatives
10528 09:27:52.239984 <6>[ 0.321419] devtmpfs: initialized
10529 09:27:52.252786 <6>[ 0.330318] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10530 09:27:52.262878 <6>[ 0.340279] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10531 09:27:52.269320 <6>[ 0.348294] pinctrl core: initialized pinctrl subsystem
10532 09:27:52.272360 <6>[ 0.354972] DMI not present or invalid.
10533 09:27:52.278999 <6>[ 0.359383] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10534 09:27:52.285585 <6>[ 0.366185] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10535 09:27:52.295837 <6>[ 0.373777] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10536 09:27:52.302552 <6>[ 0.382000] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10537 09:27:52.309126 <6>[ 0.390240] audit: initializing netlink subsys (disabled)
10538 09:27:52.318821 <5>[ 0.395931] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10539 09:27:52.322377 <6>[ 0.396654] thermal_sys: Registered thermal governor 'step_wise'
10540 09:27:52.329140 <6>[ 0.403897] thermal_sys: Registered thermal governor 'power_allocator'
10541 09:27:52.335526 <6>[ 0.410152] cpuidle: using governor menu
10542 09:27:52.339217 <6>[ 0.421117] NET: Registered PF_QIPCRTR protocol family
10543 09:27:52.349556 <6>[ 0.426595] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10544 09:27:52.352147 <6>[ 0.433697] ASID allocator initialised with 32768 entries
10545 09:27:52.359211 <6>[ 0.440273] Serial: AMBA PL011 UART driver
10546 09:27:52.367950 <4>[ 0.449147] Trying to register duplicate clock ID: 134
10547 09:27:52.426299 <6>[ 0.510880] KASLR enabled
10548 09:27:52.440653 <6>[ 0.518589] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10549 09:27:52.447254 <6>[ 0.525606] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10550 09:27:52.453773 <6>[ 0.532095] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10551 09:27:52.460586 <6>[ 0.539102] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10552 09:27:52.467188 <6>[ 0.545591] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10553 09:27:52.473860 <6>[ 0.552596] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10554 09:27:52.480937 <6>[ 0.559082] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10555 09:27:52.487243 <6>[ 0.566086] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10556 09:27:52.490959 <6>[ 0.573609] ACPI: Interpreter disabled.
10557 09:27:52.498706 <6>[ 0.580041] iommu: Default domain type: Translated
10558 09:27:52.505196 <6>[ 0.585152] iommu: DMA domain TLB invalidation policy: strict mode
10559 09:27:52.508838 <5>[ 0.591812] SCSI subsystem initialized
10560 09:27:52.515510 <6>[ 0.595975] usbcore: registered new interface driver usbfs
10561 09:27:52.522138 <6>[ 0.601707] usbcore: registered new interface driver hub
10562 09:27:52.525230 <6>[ 0.607260] usbcore: registered new device driver usb
10563 09:27:52.532461 <6>[ 0.613359] pps_core: LinuxPPS API ver. 1 registered
10564 09:27:52.542299 <6>[ 0.618552] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10565 09:27:52.545482 <6>[ 0.627896] PTP clock support registered
10566 09:27:52.548710 <6>[ 0.632139] EDAC MC: Ver: 3.0.0
10567 09:27:52.556000 <6>[ 0.637290] FPGA manager framework
10568 09:27:52.559595 <6>[ 0.640975] Advanced Linux Sound Architecture Driver Initialized.
10569 09:27:52.563109 <6>[ 0.647746] vgaarb: loaded
10570 09:27:52.569913 <6>[ 0.650899] clocksource: Switched to clocksource arch_sys_counter
10571 09:27:52.576506 <5>[ 0.657338] VFS: Disk quotas dquot_6.6.0
10572 09:27:52.583280 <6>[ 0.661522] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10573 09:27:52.586792 <6>[ 0.668712] pnp: PnP ACPI: disabled
10574 09:27:52.594340 <6>[ 0.675444] NET: Registered PF_INET protocol family
10575 09:27:52.603912 <6>[ 0.681035] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10576 09:27:52.615652 <6>[ 0.693362] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10577 09:27:52.625457 <6>[ 0.702179] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10578 09:27:52.632077 <6>[ 0.710150] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10579 09:27:52.638662 <6>[ 0.718850] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10580 09:27:52.651021 <6>[ 0.728606] TCP: Hash tables configured (established 65536 bind 65536)
10581 09:27:52.657012 <6>[ 0.735469] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10582 09:27:52.663879 <6>[ 0.742668] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10583 09:27:52.670448 <6>[ 0.750374] NET: Registered PF_UNIX/PF_LOCAL protocol family
10584 09:27:52.677637 <6>[ 0.756525] RPC: Registered named UNIX socket transport module.
10585 09:27:52.680557 <6>[ 0.762681] RPC: Registered udp transport module.
10586 09:27:52.687364 <6>[ 0.767616] RPC: Registered tcp transport module.
10587 09:27:52.693878 <6>[ 0.772550] RPC: Registered tcp NFSv4.1 backchannel transport module.
10588 09:27:52.697303 <6>[ 0.779216] PCI: CLS 0 bytes, default 64
10589 09:27:52.700626 <6>[ 0.783533] Unpacking initramfs...
10590 09:27:52.717630 <6>[ 0.795431] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10591 09:27:52.727929 <6>[ 0.804068] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10592 09:27:52.731028 <6>[ 0.812891] kvm [1]: IPA Size Limit: 40 bits
10593 09:27:52.737568 <6>[ 0.817421] kvm [1]: GICv3: no GICV resource entry
10594 09:27:52.741262 <6>[ 0.822441] kvm [1]: disabling GICv2 emulation
10595 09:27:52.747877 <6>[ 0.827128] kvm [1]: GIC system register CPU interface enabled
10596 09:27:52.754038 <6>[ 0.834925] kvm [1]: vgic interrupt IRQ18
10597 09:27:52.757613 <6>[ 0.839295] kvm [1]: VHE mode initialized successfully
10598 09:27:52.764873 <5>[ 0.845738] Initialise system trusted keyrings
10599 09:27:52.771021 <6>[ 0.850521] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10600 09:27:52.779551 <6>[ 0.860552] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10601 09:27:52.785881 <5>[ 0.866964] NFS: Registering the id_resolver key type
10602 09:27:52.789254 <5>[ 0.872260] Key type id_resolver registered
10603 09:27:52.796214 <5>[ 0.876677] Key type id_legacy registered
10604 09:27:52.802791 <6>[ 0.880955] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10605 09:27:52.809389 <6>[ 0.887875] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10606 09:27:52.815601 <6>[ 0.895615] 9p: Installing v9fs 9p2000 file system support
10607 09:27:52.851688 <5>[ 0.933054] Key type asymmetric registered
10608 09:27:52.855309 <5>[ 0.937384] Asymmetric key parser 'x509' registered
10609 09:27:52.865237 <6>[ 0.942528] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10610 09:27:52.868399 <6>[ 0.950151] io scheduler mq-deadline registered
10611 09:27:52.872011 <6>[ 0.954912] io scheduler kyber registered
10612 09:27:52.890531 <6>[ 0.971958] EINJ: ACPI disabled.
10613 09:27:52.923601 <4>[ 0.998039] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10614 09:27:52.933300 <4>[ 1.008677] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10615 09:27:52.948518 <6>[ 1.029913] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10616 09:27:52.956538 <6>[ 1.037943] printk: console [ttyS0] disabled
10617 09:27:52.984776 <6>[ 1.062573] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10618 09:27:52.991937 <6>[ 1.072048] printk: console [ttyS0] enabled
10619 09:27:52.994949 <6>[ 1.072048] printk: console [ttyS0] enabled
10620 09:27:52.998083 <6>[ 1.080948] printk: bootconsole [mtk8250] disabled
10621 09:27:53.004615 <6>[ 1.080948] printk: bootconsole [mtk8250] disabled
10622 09:27:53.011421 <6>[ 1.092348] SuperH (H)SCI(F) driver initialized
10623 09:27:53.014616 <6>[ 1.097657] msm_serial: driver initialized
10624 09:27:53.028878 <6>[ 1.106653] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10625 09:27:53.039018 <6>[ 1.115203] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10626 09:27:53.045290 <6>[ 1.123746] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10627 09:27:53.055542 <6>[ 1.132376] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10628 09:27:53.062134 <6>[ 1.141085] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10629 09:27:53.071965 <6>[ 1.149801] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10630 09:27:53.082322 <6>[ 1.158342] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10631 09:27:53.088461 <6>[ 1.167170] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10632 09:27:53.098665 <6>[ 1.175713] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10633 09:27:53.110633 <6>[ 1.191620] loop: module loaded
10634 09:27:53.116910 <6>[ 1.197645] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10635 09:27:53.139221 <4>[ 1.220507] mtk-pmic-keys: Failed to locate of_node [id: -1]
10636 09:27:53.146167 <6>[ 1.227385] megasas: 07.719.03.00-rc1
10637 09:27:53.155598 <6>[ 1.236931] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10638 09:27:53.169333 <6>[ 1.250272] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10639 09:27:53.185701 <6>[ 1.266794] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10640 09:27:53.242073 <6>[ 1.316794] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10641 09:27:54.931056 <6>[ 3.012529] Freeing initrd memory: 50920K
10642 09:27:54.943006 <6>[ 3.024392] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10643 09:27:54.954081 <6>[ 3.035293] tun: Universal TUN/TAP device driver, 1.6
10644 09:27:54.957579 <6>[ 3.041335] thunder_xcv, ver 1.0
10645 09:27:54.960671 <6>[ 3.044838] thunder_bgx, ver 1.0
10646 09:27:54.963690 <6>[ 3.048335] nicpf, ver 1.0
10647 09:27:54.974087 <6>[ 3.052335] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10648 09:27:54.977800 <6>[ 3.059810] hns3: Copyright (c) 2017 Huawei Corporation.
10649 09:27:54.980790 <6>[ 3.065396] hclge is initializing
10650 09:27:54.987638 <6>[ 3.068975] e1000: Intel(R) PRO/1000 Network Driver
10651 09:27:54.994338 <6>[ 3.074105] e1000: Copyright (c) 1999-2006 Intel Corporation.
10652 09:27:54.997400 <6>[ 3.080120] e1000e: Intel(R) PRO/1000 Network Driver
10653 09:27:55.004057 <6>[ 3.085335] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10654 09:27:55.010828 <6>[ 3.091519] igb: Intel(R) Gigabit Ethernet Network Driver
10655 09:27:55.017487 <6>[ 3.097169] igb: Copyright (c) 2007-2014 Intel Corporation.
10656 09:27:55.024387 <6>[ 3.103004] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10657 09:27:55.030849 <6>[ 3.109522] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10658 09:27:55.034431 <6>[ 3.115980] sky2: driver version 1.30
10659 09:27:55.040831 <6>[ 3.120903] usbcore: registered new device driver r8152-cfgselector
10660 09:27:55.047782 <6>[ 3.127440] usbcore: registered new interface driver r8152
10661 09:27:55.050962 <6>[ 3.133259] VFIO - User Level meta-driver version: 0.3
10662 09:27:55.060239 <6>[ 3.141487] usbcore: registered new interface driver usb-storage
10663 09:27:55.066578 <6>[ 3.147938] usbcore: registered new device driver onboard-usb-hub
10664 09:27:55.075820 <6>[ 3.157076] mt6397-rtc mt6359-rtc: registered as rtc0
10665 09:27:55.086026 <6>[ 3.162562] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-18T09:27:55 UTC (1718702875)
10666 09:27:55.088932 <6>[ 3.172177] i2c_dev: i2c /dev entries driver
10667 09:27:55.102904 <4>[ 3.184230] cpu cpu0: supply cpu not found, using dummy regulator
10668 09:27:55.109428 <4>[ 3.190659] cpu cpu1: supply cpu not found, using dummy regulator
10669 09:27:55.116254 <4>[ 3.197063] cpu cpu2: supply cpu not found, using dummy regulator
10670 09:27:55.123386 <4>[ 3.203471] cpu cpu3: supply cpu not found, using dummy regulator
10671 09:27:55.129897 <4>[ 3.209872] cpu cpu4: supply cpu not found, using dummy regulator
10672 09:27:55.136111 <4>[ 3.216286] cpu cpu5: supply cpu not found, using dummy regulator
10673 09:27:55.142878 <4>[ 3.222683] cpu cpu6: supply cpu not found, using dummy regulator
10674 09:27:55.149915 <4>[ 3.229079] cpu cpu7: supply cpu not found, using dummy regulator
10675 09:27:55.168377 <6>[ 3.249720] cpu cpu0: EM: created perf domain
10676 09:27:55.171561 <6>[ 3.254636] cpu cpu4: EM: created perf domain
10677 09:27:55.178988 <6>[ 3.260206] sdhci: Secure Digital Host Controller Interface driver
10678 09:27:55.185364 <6>[ 3.266640] sdhci: Copyright(c) Pierre Ossman
10679 09:27:55.192054 <6>[ 3.271595] Synopsys Designware Multimedia Card Interface Driver
10680 09:27:55.198696 <6>[ 3.278227] sdhci-pltfm: SDHCI platform and OF driver helper
10681 09:27:55.202414 <6>[ 3.278346] mmc0: CQHCI version 5.10
10682 09:27:55.208974 <6>[ 3.288327] ledtrig-cpu: registered to indicate activity on CPUs
10683 09:27:55.215543 <6>[ 3.295262] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10684 09:27:55.222158 <6>[ 3.302312] usbcore: registered new interface driver usbhid
10685 09:27:55.225517 <6>[ 3.308134] usbhid: USB HID core driver
10686 09:27:55.232076 <6>[ 3.312338] spi_master spi0: will run message pump with realtime priority
10687 09:27:55.277749 <6>[ 3.352194] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10688 09:27:55.296707 <6>[ 3.368214] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10689 09:27:55.300215 <6>[ 3.380373] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10690 09:27:55.307593 <6>[ 3.388602] cros-ec-spi spi0.0: Chrome EC device registered
10691 09:27:55.314194 <6>[ 3.394579] mmc0: Command Queue Engine enabled
10692 09:27:55.320789 <6>[ 3.399310] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10693 09:27:55.324381 <6>[ 3.406974] mmcblk0: mmc0:0001 DA4128 116 GiB
10694 09:27:55.334526 <6>[ 3.415885] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10695 09:27:55.342005 <6>[ 3.423224] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10696 09:27:55.351781 <6>[ 3.428152] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10697 09:27:55.355075 <6>[ 3.429081] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10698 09:27:55.361751 <6>[ 3.439093] NET: Registered PF_PACKET protocol family
10699 09:27:55.368431 <6>[ 3.443594] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10700 09:27:55.372018 <6>[ 3.448372] 9pnet: Installing 9P2000 support
10701 09:27:55.378643 <5>[ 3.459350] Key type dns_resolver registered
10702 09:27:55.381617 <6>[ 3.464344] registered taskstats version 1
10703 09:27:55.388199 <5>[ 3.468721] Loading compiled-in X.509 certificates
10704 09:27:55.415603 <4>[ 3.490667] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10705 09:27:55.425870 <4>[ 3.501409] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10706 09:27:55.440377 <6>[ 3.521994] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10707 09:27:55.447627 <6>[ 3.528934] xhci-mtk 11200000.usb: xHCI Host Controller
10708 09:27:55.453778 <6>[ 3.534461] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10709 09:27:55.464466 <6>[ 3.542323] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10710 09:27:55.470603 <6>[ 3.551765] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10711 09:27:55.477798 <6>[ 3.557984] xhci-mtk 11200000.usb: xHCI Host Controller
10712 09:27:55.484323 <6>[ 3.563485] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10713 09:27:55.490450 <6>[ 3.571138] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10714 09:27:55.497430 <6>[ 3.578967] hub 1-0:1.0: USB hub found
10715 09:27:55.500920 <6>[ 3.582984] hub 1-0:1.0: 1 port detected
10716 09:27:55.510452 <6>[ 3.587260] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10717 09:27:55.514196 <6>[ 3.595965] hub 2-0:1.0: USB hub found
10718 09:27:55.517409 <6>[ 3.599986] hub 2-0:1.0: 1 port detected
10719 09:27:55.525532 <6>[ 3.607018] mtk-msdc 11f70000.mmc: Got CD GPIO
10720 09:27:55.538215 <6>[ 3.616440] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10721 09:27:55.548470 <6>[ 3.624824] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10722 09:27:55.554676 <6>[ 3.633163] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10723 09:27:55.565255 <6>[ 3.641501] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10724 09:27:55.571322 <6>[ 3.649839] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10725 09:27:55.581433 <6>[ 3.658177] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10726 09:27:55.588302 <6>[ 3.666514] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10727 09:27:55.597936 <6>[ 3.674852] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10728 09:27:55.604500 <6>[ 3.683192] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10729 09:27:55.614572 <6>[ 3.691531] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10730 09:27:55.621393 <6>[ 3.699869] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10731 09:27:55.631466 <6>[ 3.708216] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10732 09:27:55.637940 <6>[ 3.716554] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10733 09:27:55.647678 <6>[ 3.724891] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10734 09:27:55.654536 <6>[ 3.733229] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10735 09:27:55.661040 <6>[ 3.741939] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10736 09:27:55.667490 <6>[ 3.749118] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10737 09:27:55.674359 <6>[ 3.755885] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10738 09:27:55.681037 <6>[ 3.762686] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10739 09:27:55.691607 <6>[ 3.769624] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10740 09:27:55.698236 <6>[ 3.776508] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10741 09:27:55.708316 <6>[ 3.785645] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10742 09:27:55.718159 <6>[ 3.794765] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10743 09:27:55.727747 <6>[ 3.804058] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10744 09:27:55.737881 <6>[ 3.813528] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10745 09:27:55.744667 <6>[ 3.822995] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10746 09:27:55.754602 <6>[ 3.832115] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10747 09:27:55.764273 <6>[ 3.841581] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10748 09:27:55.774290 <6>[ 3.850705] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10749 09:27:55.783929 <6>[ 3.860002] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10750 09:27:55.794270 <6>[ 3.870162] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10751 09:27:55.804096 <6>[ 3.881755] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10752 09:27:55.936668 <6>[ 4.015195] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10753 09:27:56.091673 <6>[ 4.173263] hub 1-1:1.0: USB hub found
10754 09:27:56.095131 <6>[ 4.177775] hub 1-1:1.0: 4 ports detected
10755 09:27:56.105879 <6>[ 4.187270] hub 1-1:1.0: USB hub found
10756 09:27:56.108840 <6>[ 4.191702] hub 1-1:1.0: 4 ports detected
10757 09:27:56.217030 <6>[ 4.295374] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10758 09:27:56.244025 <6>[ 4.325160] hub 2-1:1.0: USB hub found
10759 09:27:56.246909 <6>[ 4.329687] hub 2-1:1.0: 3 ports detected
10760 09:27:56.258437 <6>[ 4.339825] hub 2-1:1.0: USB hub found
10761 09:27:56.261697 <6>[ 4.344225] hub 2-1:1.0: 3 ports detected
10762 09:27:56.432595 <6>[ 4.511214] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10763 09:27:56.565337 <6>[ 4.646594] hub 1-1.4:1.0: USB hub found
10764 09:27:56.568382 <6>[ 4.651244] hub 1-1.4:1.0: 2 ports detected
10765 09:27:56.580321 <6>[ 4.661801] hub 1-1.4:1.0: USB hub found
10766 09:27:56.583346 <6>[ 4.666360] hub 1-1.4:1.0: 2 ports detected
10767 09:27:56.648673 <6>[ 4.727251] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10768 09:27:56.757418 <6>[ 4.835593] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10769 09:27:56.789434 <4>[ 4.867602] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10770 09:27:56.799155 <4>[ 4.876702] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10771 09:27:56.834654 <6>[ 4.916071] r8152 2-1.3:1.0 eth0: v1.12.13
10772 09:27:56.884757 <6>[ 4.963227] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10773 09:27:57.080955 <6>[ 5.159040] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10774 09:27:58.475774 <6>[ 6.557275] r8152 2-1.3:1.0 eth0: carrier on
10775 09:28:00.729421 <5>[ 6.579016] Sending DHCP requests .., OK
10776 09:28:00.735900 <6>[ 8.815338] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10777 09:28:00.739632 <6>[ 8.823632] IP-Config: Complete:
10778 09:28:00.752189 <6>[ 8.827127] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10779 09:28:00.758733 <6>[ 8.837832] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10780 09:28:00.765626 <6>[ 8.846447] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10781 09:28:00.772126 <6>[ 8.846457] nameserver0=192.168.201.1
10782 09:28:00.775780 <6>[ 8.858565] clk: Disabling unused clocks
10783 09:28:00.778820 <6>[ 8.864100] ALSA device list:
10784 09:28:00.782507 <6>[ 8.867380] No soundcards found.
10785 09:28:00.793160 <6>[ 8.875183] Freeing unused kernel memory: 8512K
10786 09:28:00.796263 <6>[ 8.880124] Run /init as init process
10787 09:28:00.825767 <6>[ 8.907730] NET: Registered PF_INET6 protocol family
10788 09:28:00.832739 <6>[ 8.914461] Segment Routing with IPv6
10789 09:28:00.835695 <6>[ 8.918427] In-situ OAM (IOAM) with IPv6
10790 09:28:00.877201 <30>[ 8.932509] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10791 09:28:00.883362 <30>[ 8.965547] systemd[1]: Detected architecture arm64.
10792 09:28:00.883446
10793 09:28:00.890018 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10794 09:28:00.890096
10795 09:28:00.905215 <30>[ 8.987302] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10796 09:28:01.039804 <30>[ 9.118227] systemd[1]: Queued start job for default target graphical.target.
10797 09:28:01.078793 <30>[ 9.156896] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10798 09:28:01.085330 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10799 09:28:01.105227 <30>[ 9.183701] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10800 09:28:01.115319 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10801 09:28:01.134504 <30>[ 9.212862] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10802 09:28:01.144519 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10803 09:28:01.162322 <30>[ 9.240628] systemd[1]: Created slice user.slice - User and Session Slice.
10804 09:28:01.168727 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10805 09:28:01.192788 <30>[ 9.267567] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10806 09:28:01.201812 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10807 09:28:01.219969 <30>[ 9.295324] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10808 09:28:01.226863 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10809 09:28:01.255409 <30>[ 9.323753] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10810 09:28:01.265270 <30>[ 9.343663] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10811 09:28:01.271793 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10812 09:28:01.288920 <30>[ 9.367304] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10813 09:28:01.295285 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10814 09:28:01.312943 <30>[ 9.391257] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10815 09:28:01.322720 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10816 09:28:01.337252 <30>[ 9.419317] systemd[1]: Reached target paths.target - Path Units.
10817 09:28:01.344324 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10818 09:28:01.364959 <30>[ 9.443639] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10819 09:28:01.371997 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10820 09:28:01.385118 <30>[ 9.467188] systemd[1]: Reached target slices.target - Slice Units.
10821 09:28:01.395326 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10822 09:28:01.409710 <30>[ 9.491686] systemd[1]: Reached target swap.target - Swaps.
10823 09:28:01.416490 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10824 09:28:01.436965 <30>[ 9.515710] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10825 09:28:01.447429 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10826 09:28:01.465250 <30>[ 9.543699] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10827 09:28:01.475183 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10828 09:28:01.494994 <30>[ 9.573307] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10829 09:28:01.504509 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10830 09:28:01.521479 <30>[ 9.599828] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10831 09:28:01.531102 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10832 09:28:01.550137 <30>[ 9.628582] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10833 09:28:01.556710 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10834 09:28:01.577621 <30>[ 9.655971] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10835 09:28:01.587556 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10836 09:28:01.606289 <30>[ 9.684579] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10837 09:28:01.616046 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10838 09:28:01.633710 <30>[ 9.712349] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10839 09:28:01.643778 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10840 09:28:01.685153 <30>[ 9.763367] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10841 09:28:01.691691 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10842 09:28:01.715045 <30>[ 9.793225] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10843 09:28:01.721034 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10844 09:28:01.743898 <30>[ 9.822289] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10845 09:28:01.750208 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10846 09:28:01.775779 <30>[ 9.847696] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10847 09:28:01.825385 <30>[ 9.903911] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10848 09:28:01.835216 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10849 09:28:01.857922 <30>[ 9.936614] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10850 09:28:01.864491 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10851 09:28:01.889738 <30>[ 9.968442] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10852 09:28:01.899752 Startin<6>[ 9.977797] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10853 09:28:01.906643 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10854 09:28:01.952776 <30>[ 10.031562] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10855 09:28:01.959681 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10856 09:28:01.980493 <30>[ 10.059167] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10857 09:28:01.987484 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10858 09:28:02.049077 <30>[ 10.127741] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10859 09:28:02.055775 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10860 09:28:02.085544 <30>[ 10.163829] systemd[1]: Starting systemd-journald.service - Journal Service...
10861 09:28:02.091937 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10862 09:28:02.111189 <30>[ 10.189899] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10863 09:28:02.117743 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10864 09:28:02.142847 <30>[ 10.218123] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10865 09:28:02.149935 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10866 09:28:02.172949 <30>[ 10.251412] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10867 09:28:02.182827 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10868 09:28:02.203453 <30>[ 10.282245] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10869 09:28:02.213558 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10870 09:28:02.233518 <30>[ 10.312312] systemd[1]: Started systemd-journald.service - Journal Service.
10871 09:28:02.240103 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10872 09:28:02.259105 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10873 09:28:02.277294 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10874 09:28:02.297322 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10875 09:28:02.318361 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10876 09:28:02.342542 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10877 09:28:02.363054 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10878 09:28:02.382737 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10879 09:28:02.403647 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10880 09:28:02.430032 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10881 09:28:02.451191 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10882 09:28:02.470943 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10883 09:28:02.495166 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10884 09:28:02.509859 See 'systemctl status systemd-remount-fs.service' for details.
10885 09:28:02.530190 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10886 09:28:02.551212 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10887 09:28:02.612850 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10888 09:28:02.633709 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10889 09:28:02.651314 <46>[ 10.730387] systemd-journald[194]: Received client request to flush runtime journal.
10890 09:28:02.664324 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10891 09:28:02.684334 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10892 09:28:02.707951 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10893 09:28:02.730814 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10894 09:28:02.754329 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10895 09:28:02.774322 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10896 09:28:02.793947 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10897 09:28:02.814310 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10898 09:28:02.861839 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10899 09:28:02.892681 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10900 09:28:02.909366 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10901 09:28:02.932759 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10902 09:28:02.985449 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10903 09:28:03.009829 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10904 09:28:03.033233 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10905 09:28:03.052520 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10906 09:28:03.076739 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10907 09:28:03.095999 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10908 09:28:03.158802 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10909 09:28:03.182656 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10910 09:28:03.222228 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10911 09:28:03.308578 <46>[ 11.390675] systemd-journald[194]: Time jumped backwards, rotating.
10912 09:28:03.327996 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10913 09:28:03.345881 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10914 09:28:03.365224 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10915 09:28:03.385537 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10916 09:28:03.406664 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10917 09:28:03.425844 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10918 09:28:03.445436 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10919 09:28:03.455855 <6>[ 11.534772] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10920 09:28:03.462454 <6>[ 11.542508] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10921 09:28:03.472813 <6>[ 11.551447] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10922 09:28:03.483173 <6>[ 11.562033] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10923 09:28:03.497333 <6>[ 11.576059] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10924 09:28:03.503985 <3>[ 11.580591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10925 09:28:03.513884 <6>[ 11.584125] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10926 09:28:03.520759 <3>[ 11.592546] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10927 09:28:03.530579 <3>[ 11.592554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10928 09:28:03.537255 <3>[ 11.593489] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10929 09:28:03.543940 <6>[ 11.597679] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10930 09:28:03.553398 <4>[ 11.600938] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10931 09:28:03.563870 <3>[ 11.608872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10932 09:28:03.570617 <6>[ 11.617355] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10933 09:28:03.577150 <3>[ 11.624727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10934 09:28:03.587173 <3>[ 11.624736] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10935 09:28:03.593812 <3>[ 11.624741] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10936 09:28:03.603463 <3>[ 11.630327] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10937 09:28:03.610239 <6>[ 11.632152] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10938 09:28:03.616993 <6>[ 11.647044] remoteproc remoteproc0: scp is available
10939 09:28:03.623743 <4>[ 11.647144] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10940 09:28:03.630211 <3>[ 11.691204] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10941 09:28:03.636838 <4>[ 11.691210] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10942 09:28:03.646711 <3>[ 11.691221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10943 09:28:03.653738 <3>[ 11.691228] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10944 09:28:03.660601 <6>[ 11.697705] remoteproc remoteproc0: powering up scp
10945 09:28:03.667275 <3>[ 11.703567] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10946 09:28:03.674089 <6>[ 11.703735] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10947 09:28:03.684325 <6>[ 11.709737] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10948 09:28:03.691254 <6>[ 11.709751] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10949 09:28:03.698245 <6>[ 11.709755] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10950 09:28:03.707879 <6>[ 11.709758] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10951 09:28:03.717381 <6>[ 11.710177] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10952 09:28:03.724039 <3>[ 11.718228] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10953 09:28:03.730687 <6>[ 11.725534] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10954 09:28:03.737151 <4>[ 11.728089] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10955 09:28:03.744229 <4>[ 11.728089] Fallback method does not support PEC.
10956 09:28:03.750389 <3>[ 11.733602] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10957 09:28:03.760171 <3>[ 11.743814] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 09:28:03.770533 <3>[ 11.746811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10959 09:28:03.777188 <6>[ 11.779078] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10960 09:28:03.784084 <3>[ 11.786073] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10961 09:28:03.790959 <3>[ 11.832724] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10962 09:28:03.797422 <6>[ 11.832803] mc: Linux media interface: v0.10
10963 09:28:03.804085 <6>[ 11.839540] pci_bus 0000:00: root bus resource [bus 00-ff]
10964 09:28:03.807608 <6>[ 11.848692] videodev: Linux video capture interface: v2.00
10965 09:28:03.814569 <6>[ 11.856275] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10966 09:28:03.824539 <3>[ 11.856544] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 09:28:03.835598 <6>[ 11.859158] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10968 09:28:03.842284 <6>[ 11.862428] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10969 09:28:03.848751 <6>[ 11.863108] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10970 09:28:03.858634 <6>[ 11.871299] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10971 09:28:03.865578 <6>[ 11.879270] remoteproc remoteproc0: remote processor scp is now up
10972 09:28:03.872963 <3>[ 11.894435] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 09:28:03.879821 <6>[ 11.895312] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10974 09:28:03.889837 <3>[ 11.924272] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 09:28:03.897032 <6>[ 11.928008] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10976 09:28:03.906939 <6>[ 11.960552] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10977 09:28:03.910382 <6>[ 11.961592] pci 0000:00:00.0: supports D1 D2
10978 09:28:03.920569 <3>[ 11.962310] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 09:28:03.930462 <6>[ 11.968450] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10980 09:28:03.936809 <5>[ 11.969572] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10981 09:28:03.943432 <6>[ 11.976624] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10982 09:28:03.953764 <6>[ 11.978081] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10983 09:28:03.960339 <3>[ 11.983714] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 09:28:03.966826 <5>[ 11.984736] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10985 09:28:03.973816 <6>[ 11.994519] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10986 09:28:03.983364 <5>[ 11.999181] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10987 09:28:03.989956 <6>[ 12.007703] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10988 09:28:04.000027 <6>[ 12.012096] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10989 09:28:04.007391 <4>[ 12.017270] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10990 09:28:04.014613 <6>[ 12.018482] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10991 09:28:04.021900 <6>[ 12.024783] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10992 09:28:04.028611 <6>[ 12.031640] cfg80211: failed to load regulatory.db
10993 09:28:04.031675 <6>[ 12.032293] Bluetooth: Core ver 2.22
10994 09:28:04.038329 <6>[ 12.032351] NET: Registered PF_BLUETOOTH protocol family
10995 09:28:04.045086 <6>[ 12.032353] Bluetooth: HCI device and connection manager initialized
10996 09:28:04.048902 <6>[ 12.032367] Bluetooth: HCI socket layer initialized
10997 09:28:04.054878 <6>[ 12.032371] Bluetooth: L2CAP socket layer initialized
10998 09:28:04.062267 <6>[ 12.032378] Bluetooth: SCO socket layer initialized
10999 09:28:04.068824 <6>[ 12.039895] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11000 09:28:04.074799 <6>[ 12.056770] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11001 09:28:04.078324 <6>[ 12.061809] pci 0000:01:00.0: supports D1 D2
11002 09:28:04.091929 <6>[ 12.071371] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11003 09:28:04.098629 <6>[ 12.077504] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11004 09:28:04.104883 <6>[ 12.078473] usbcore: registered new interface driver btusb
11005 09:28:04.115215 <4>[ 12.079171] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11006 09:28:04.122675 <3>[ 12.079183] Bluetooth: hci0: Failed to load firmware file (-2)
11007 09:28:04.126238 <3>[ 12.079188] Bluetooth: hci0: Failed to set up firmware (-2)
11008 09:28:04.135958 <4>[ 12.079195] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11009 09:28:04.143016 <6>[ 12.085934] usbcore: registered new interface driver uvcvideo
11010 09:28:04.149745 <6>[ 12.090965] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11011 09:28:04.159907 <6>[ 12.090998] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11012 09:28:04.167191 <6>[ 12.091001] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11013 09:28:04.173640 <6>[ 12.091009] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11014 09:28:04.183964 <6>[ 12.091022] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11015 09:28:04.190803 <6>[ 12.091035] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11016 09:28:04.194297 <6>[ 12.091047] pci 0000:00:00.0: PCI bridge to [bus 01]
11017 09:28:04.204108 <6>[ 12.091053] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11018 09:28:04.208337 <6>[ 12.091181] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11019 09:28:04.214897 <6>[ 12.091632] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11020 09:28:04.221549 <6>[ 12.091878] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11021 09:28:04.228707 <6>[ 12.095757] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11022 09:28:04.235870 <3>[ 12.099702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11023 09:28:04.245869 <3>[ 12.100583] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 09:28:04.255730 <3>[ 12.105218] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11025 09:28:04.262558 <6>[ 12.188732] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11026 09:28:04.272068 <3>[ 12.209128] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11027 09:28:04.275635 <6>[ 12.214387] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11028 09:28:04.285895 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11029 09:28:04.302294 <6>[ 12.384517] mt7921e 0000:01:00.0: ASIC revision: 79610010
11030 09:28:04.312679 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11031 09:28:04.374011 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11032 09:28:04.405271 <6>[ 12.484030] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11033 09:28:04.408804 <6>[ 12.484030]
11034 09:28:04.419007 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11035 09:28:04.437670 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11036 09:28:04.458475 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11037 09:28:04.505860 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11038 09:28:04.527393 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11039 09:28:04.549270 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11040 09:28:04.565902 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11041 09:28:04.585359 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11042 09:28:04.634214 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11043 09:28:04.659101 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11044 09:28:04.673978 <6>[ 12.753147] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11045 09:28:04.689039 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11046 09:28:04.712021 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11047 09:28:04.761865 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11048 09:28:04.783941 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11049 09:28:04.801842 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11050 09:28:04.816985 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11051 09:28:04.837089 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11052 09:28:04.890036 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11053 09:28:04.915190 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11054 09:28:04.937203 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11055 09:28:04.978069 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11056 09:28:05.024645
11057 09:28:05.028038 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11058 09:28:05.028118
11059 09:28:05.031653 debian-bookworm-arm64 login: root (automatic login)
11060 09:28:05.031732
11061 09:28:05.043879 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
11062 09:28:05.043959
11063 09:28:05.050398 The programs included with the Debian GNU/Linux system are free software;
11064 09:28:05.057216 the exact distribution terms for each program are described in the
11065 09:28:05.060178 individual files in /usr/share/doc/*/copyright.
11066 09:28:05.060278
11067 09:28:05.066950 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11068 09:28:05.069948 permitted by applicable law.
11069 09:28:05.070343 Matched prompt #10: / #
11071 09:28:05.070531 Setting prompt string to ['/ #']
11072 09:28:05.070618 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11074 09:28:05.070796 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11075 09:28:05.070876 start: 2.2.6 expect-shell-connection (timeout 00:02:44) [common]
11076 09:28:05.070940 Setting prompt string to ['/ #']
11077 09:28:05.070996 Forcing a shell prompt, looking for ['/ #']
11079 09:28:05.121196 / #
11080 09:28:05.121358 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11081 09:28:05.121429 Waiting using forced prompt support (timeout 00:02:30)
11082 09:28:05.126561
11083 09:28:05.126824 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11084 09:28:05.126914 start: 2.2.7 export-device-env (timeout 00:02:44) [common]
11085 09:28:05.126999 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11086 09:28:05.127081 end: 2.2 depthcharge-retry (duration 00:02:16) [common]
11087 09:28:05.127160 end: 2 depthcharge-action (duration 00:02:16) [common]
11088 09:28:05.127240 start: 3 lava-test-retry (timeout 00:05:00) [common]
11089 09:28:05.127325 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11090 09:28:05.127392 Using namespace: common
11092 09:28:05.227709 / # #
11093 09:28:05.227885 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11094 09:28:05.233039 #
11095 09:28:05.233317 Using /lava-14407640
11097 09:28:05.333616 / # export SHELL=/bin/sh
11098 09:28:05.338687 export SHELL=/bin/sh
11100 09:28:05.439202 / # . /lava-14407640/environment
11101 09:28:05.444949 . /lava-14407640/environment
11103 09:28:05.545451 / # /lava-14407640/bin/lava-test-runner /lava-14407640/0
11104 09:28:05.545662 Test shell timeout: 10s (minimum of the action and connection timeout)
11105 09:28:05.546208 /lava-14407640/bin/lava-test-runner /lava-14407640/0<6>[ 13.623221] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11106 09:28:05.550367
11107 09:28:05.594100 + export TESTRUN_ID=0_cros-ec
11108 09:28:05.594191 + c<8>[ 13.661394] <LAVA_SIGNAL_STARTRUN 0_cros-ec 14407640_1.5.2.3.1>
11109 09:28:05.594254 d /lava-14407640/0/tests/0_cros-ec
11110 09:28:05.594311 + cat uuid
11111 09:28:05.594366 + UUID=14407640_1.5.2.3.1
11112 09:28:05.594420 + set +x
11113 09:28:05.594472 + python3 -m cros.runners.lava_runner -v
11114 09:28:05.594700 Received signal: <STARTRUN> 0_cros-ec 14407640_1.5.2.3.1
11115 09:28:05.594767 Starting test lava.0_cros-ec (14407640_1.5.2.3.1)
11116 09:28:05.594843 Skipping test definition patterns.
11117 09:28:06.016097 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
11118 09:28:06.022335 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11119 09:28:06.022855
11120 09:28:06.028927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11121 09:28:06.029731 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11123 09:28:06.039205 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
11124 09:28:06.048958 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11125 09:28:06.049445
11126 09:28:06.055980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11127 09:28:06.056629 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11129 09:28:06.065513 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
11130 09:28:06.072217 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11131 09:28:06.072740
11132 09:28:06.079406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11133 09:28:06.080051 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11135 09:28:06.086208 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
11136 09:28:06.089226 Checks the standard ABI for the main Embedded Controller. ... ok
11137 09:28:06.089666
11138 09:28:06.095801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11139 09:28:06.096495 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11141 09:28:06.102837 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
11142 09:28:06.109346 Checks the main Embedded controller character device. ... ok
11143 09:28:06.109744
11144 09:28:06.115637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11145 09:28:06.115959 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11147 09:28:06.122484 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
11148 09:28:06.128966 Checks basic comunication with the main Embedded controller. ... ok
11149 09:28:06.129067
11150 09:28:06.132254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11151 09:28:06.132499 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11153 09:28:06.138679 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
11154 09:28:06.148850 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11155 09:28:06.148978
11156 09:28:06.151779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11157 09:28:06.152031 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11159 09:28:06.158860 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
11160 09:28:06.168705 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11161 09:28:06.168784
11162 09:28:06.175132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11163 09:28:06.175401 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11165 09:28:06.181841 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
11166 09:28:06.188552 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11167 09:28:06.188652
11168 09:28:06.195198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11169 09:28:06.195471 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11171 09:28:06.201872 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
11172 09:28:06.208533 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11173 09:28:06.208612
11174 09:28:06.215030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11175 09:28:06.215275 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11177 09:28:06.221597 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
11178 09:28:06.231456 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11179 09:28:06.231532
11180 09:28:06.234806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11181 09:28:06.235043 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11183 09:28:06.241486 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
11184 09:28:06.251459 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11185 09:28:06.251532
11186 09:28:06.254488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11187 09:28:06.254733 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11189 09:28:06.261044 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
11190 09:28:06.271007 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11191 09:28:06.271109
11192 09:28:06.277723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11193 09:28:06.278000 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11195 09:28:06.284403 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
11196 09:28:06.293953 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11197 09:28:06.294095
11198 09:28:06.301019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11199 09:28:06.301263 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11201 09:28:06.307508 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
11202 09:28:06.314249 Check the cros battery ABI. ... skipped 'No BAT found'
11203 09:28:06.314351
11204 09:28:06.320808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11205 09:28:06.321054 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11207 09:28:06.330746 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
11208 09:28:06.337563 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11209 09:28:06.337664
11210 09:28:06.344217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11211 09:28:06.344463 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11213 09:28:06.350831 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
11214 09:28:06.357539 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11215 09:28:06.357616
11216 09:28:06.363803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11217 09:28:06.364049 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11219 09:28:06.373871 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
11220 09:28:06.377001 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11221 09:28:06.377079
11222 09:28:06.387053 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=ski<8
11223 09:28:06.387149 Bad test result: ski<8
11224 09:28:06.390222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=ski<8>[ 14.472636] <LAVA_SIGNAL_ENDRUN 0_cros-ec 14407640_1.5.2.3.1>
11225 09:28:06.390293 p>
11226 09:28:06.390351
11227 09:28:06.390573 Received signal: <ENDRUN> 0_cros-ec 14407640_1.5.2.3.1
11228 09:28:06.390641 Ending use of test pattern.
11229 09:28:06.390696 Ending test lava.0_cros-ec (14407640_1.5.2.3.1), duration 0.80
11231 09:28:06.397053 ----------------------------------------------------------------------
11232 09:28:06.400111 Ran 18 tests in 0.338s
11233 09:28:06.400176
11234 09:28:06.400233 OK (skipped=15)
11235 09:28:06.403811 + set +x
11236 09:28:06.403889 <LAVA_TEST_RUNNER EXIT>
11237 09:28:06.404116 ok: lava_test_shell seems to have completed
11238 09:28:06.404272 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11239 09:28:06.404368 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11240 09:28:06.404447 end: 3 lava-test-retry (duration 00:00:01) [common]
11241 09:28:06.404528 start: 4 finalize (timeout 00:06:30) [common]
11242 09:28:06.404610 start: 4.1 power-off (timeout 00:00:30) [common]
11243 09:28:06.404742 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11244 09:28:06.606358 >> Command sent successfully.
11245 09:28:06.610341 Returned 0 in 0 seconds
11246 09:28:06.710706 end: 4.1 power-off (duration 00:00:00) [common]
11248 09:28:06.711161 start: 4.2 read-feedback (timeout 00:06:29) [common]
11249 09:28:06.711437 Listened to connection for namespace 'common' for up to 1s
11250 09:28:07.712383 Finalising connection for namespace 'common'
11251 09:28:07.712544 Disconnecting from shell: Finalise
11252 09:28:07.712620 / #
11253 09:28:07.812862 end: 4.2 read-feedback (duration 00:00:01) [common]
11254 09:28:07.813040 end: 4 finalize (duration 00:00:01) [common]
11255 09:28:07.813180 Cleaning after the job
11256 09:28:07.813304 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/ramdisk
11257 09:28:07.819055 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/kernel
11258 09:28:07.833510 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/dtb
11259 09:28:07.833709 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407640/tftp-deploy-n564n2y3/modules
11260 09:28:07.839662 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407640
11261 09:28:07.927510 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407640
11262 09:28:07.927680 Job finished correctly