Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 26
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 09:27:53.138089 lava-dispatcher, installed at version: 2024.03
2 09:27:53.138325 start: 0 validate
3 09:27:53.138446 Start time: 2024-06-18 09:27:53.138439+00:00 (UTC)
4 09:27:53.138583 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:27:53.138730 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 09:27:53.403776 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:27:53.403984 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:27:53.653820 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:27:53.654063 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:27:53.903838 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:27:53.904033 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:27:54.169202 validate duration: 1.03
14 09:27:54.169480 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:27:54.169593 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:27:54.169689 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:27:54.169844 Not decompressing ramdisk as can be used compressed.
18 09:27:54.169939 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 09:27:54.170014 saving as /var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/ramdisk/rootfs.cpio.gz
20 09:27:54.170085 total size: 47897469 (45 MB)
21 09:27:54.171107 progress 0 % (0 MB)
22 09:27:54.183336 progress 5 % (2 MB)
23 09:27:54.195596 progress 10 % (4 MB)
24 09:27:54.208158 progress 15 % (6 MB)
25 09:27:54.220470 progress 20 % (9 MB)
26 09:27:54.233159 progress 25 % (11 MB)
27 09:27:54.245752 progress 30 % (13 MB)
28 09:27:54.258103 progress 35 % (16 MB)
29 09:27:54.270505 progress 40 % (18 MB)
30 09:27:54.282734 progress 45 % (20 MB)
31 09:27:54.295023 progress 50 % (22 MB)
32 09:27:54.307546 progress 55 % (25 MB)
33 09:27:54.320137 progress 60 % (27 MB)
34 09:27:54.332413 progress 65 % (29 MB)
35 09:27:54.344923 progress 70 % (32 MB)
36 09:27:54.357357 progress 75 % (34 MB)
37 09:27:54.369705 progress 80 % (36 MB)
38 09:27:54.382057 progress 85 % (38 MB)
39 09:27:54.394319 progress 90 % (41 MB)
40 09:27:54.406470 progress 95 % (43 MB)
41 09:27:54.418409 progress 100 % (45 MB)
42 09:27:54.418652 45 MB downloaded in 0.25 s (183.77 MB/s)
43 09:27:54.418821 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:27:54.419047 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:27:54.419128 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:27:54.419205 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:27:54.419340 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:27:54.419402 saving as /var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/kernel/Image
50 09:27:54.419455 total size: 54813184 (52 MB)
51 09:27:54.419511 No compression specified
52 09:27:54.420504 progress 0 % (0 MB)
53 09:27:54.434203 progress 5 % (2 MB)
54 09:27:54.448159 progress 10 % (5 MB)
55 09:27:54.462152 progress 15 % (7 MB)
56 09:27:54.476146 progress 20 % (10 MB)
57 09:27:54.490633 progress 25 % (13 MB)
58 09:27:54.504738 progress 30 % (15 MB)
59 09:27:54.518803 progress 35 % (18 MB)
60 09:27:54.533118 progress 40 % (20 MB)
61 09:27:54.547596 progress 45 % (23 MB)
62 09:27:54.562050 progress 50 % (26 MB)
63 09:27:54.576214 progress 55 % (28 MB)
64 09:27:54.590365 progress 60 % (31 MB)
65 09:27:54.604459 progress 65 % (34 MB)
66 09:27:54.618295 progress 70 % (36 MB)
67 09:27:54.632487 progress 75 % (39 MB)
68 09:27:54.646400 progress 80 % (41 MB)
69 09:27:54.660113 progress 85 % (44 MB)
70 09:27:54.673991 progress 90 % (47 MB)
71 09:27:54.688091 progress 95 % (49 MB)
72 09:27:54.701598 progress 100 % (52 MB)
73 09:27:54.701845 52 MB downloaded in 0.28 s (185.12 MB/s)
74 09:27:54.701997 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:27:54.702213 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:27:54.702295 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:27:54.702372 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:27:54.702497 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:27:54.702559 saving as /var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/dtb/mt8192-asurada-spherion-r0.dtb
81 09:27:54.702612 total size: 47258 (0 MB)
82 09:27:54.702666 No compression specified
83 09:27:54.703664 progress 69 % (0 MB)
84 09:27:54.703922 progress 100 % (0 MB)
85 09:27:54.704070 0 MB downloaded in 0.00 s (30.97 MB/s)
86 09:27:54.704182 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:27:54.704385 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:27:54.704463 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:27:54.704539 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:27:54.704655 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:27:54.704720 saving as /var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/modules/modules.tar
93 09:27:54.704774 total size: 8619356 (8 MB)
94 09:27:54.704831 Using unxz to decompress xz
95 09:27:54.706116 progress 0 % (0 MB)
96 09:27:54.725781 progress 5 % (0 MB)
97 09:27:54.750063 progress 10 % (0 MB)
98 09:27:54.774600 progress 15 % (1 MB)
99 09:27:54.798972 progress 20 % (1 MB)
100 09:27:54.824047 progress 25 % (2 MB)
101 09:27:54.848345 progress 30 % (2 MB)
102 09:27:54.873376 progress 35 % (2 MB)
103 09:27:54.897543 progress 40 % (3 MB)
104 09:27:54.921791 progress 45 % (3 MB)
105 09:27:54.945448 progress 50 % (4 MB)
106 09:27:54.970061 progress 55 % (4 MB)
107 09:27:54.994172 progress 60 % (4 MB)
108 09:27:55.018022 progress 65 % (5 MB)
109 09:27:55.045737 progress 70 % (5 MB)
110 09:27:55.071182 progress 75 % (6 MB)
111 09:27:55.095397 progress 80 % (6 MB)
112 09:27:55.118968 progress 85 % (7 MB)
113 09:27:55.143252 progress 90 % (7 MB)
114 09:27:55.170964 progress 95 % (7 MB)
115 09:27:55.199837 progress 100 % (8 MB)
116 09:27:55.204293 8 MB downloaded in 0.50 s (16.46 MB/s)
117 09:27:55.204457 end: 1.4.1 http-download (duration 00:00:00) [common]
119 09:27:55.204686 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:27:55.204769 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 09:27:55.204849 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 09:27:55.204921 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:27:55.204994 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 09:27:55.205153 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad
125 09:27:55.205271 makedir: /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin
126 09:27:55.205377 makedir: /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/tests
127 09:27:55.205469 makedir: /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/results
128 09:27:55.205554 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-add-keys
129 09:27:55.205685 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-add-sources
130 09:27:55.205804 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-background-process-start
131 09:27:55.205924 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-background-process-stop
132 09:27:55.206050 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-common-functions
133 09:27:55.206167 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-echo-ipv4
134 09:27:55.206284 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-install-packages
135 09:27:55.206398 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-installed-packages
136 09:27:55.206511 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-os-build
137 09:27:55.206625 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-probe-channel
138 09:27:55.206738 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-probe-ip
139 09:27:55.206851 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-target-ip
140 09:27:55.206964 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-target-mac
141 09:27:55.207076 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-target-storage
142 09:27:55.207196 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-test-case
143 09:27:55.207308 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-test-event
144 09:27:55.207420 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-test-feedback
145 09:27:55.207536 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-test-raise
146 09:27:55.207649 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-test-reference
147 09:27:55.207763 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-test-runner
148 09:27:55.207876 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-test-set
149 09:27:55.207989 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-test-shell
150 09:27:55.208103 Updating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-install-packages (oe)
151 09:27:55.208244 Updating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/bin/lava-installed-packages (oe)
152 09:27:55.208363 Creating /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/environment
153 09:27:55.208453 LAVA metadata
154 09:27:55.208520 - LAVA_JOB_ID=14407656
155 09:27:55.208576 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:27:55.208677 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 09:27:55.208738 skipped lava-vland-overlay
158 09:27:55.208807 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:27:55.208878 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 09:27:55.208932 skipped lava-multinode-overlay
161 09:27:55.208997 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:27:55.209068 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 09:27:55.209130 Loading test definitions
164 09:27:55.209207 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 09:27:55.209266 Using /lava-14407656 at stage 0
166 09:27:55.209564 uuid=14407656_1.5.2.3.1 testdef=None
167 09:27:55.209645 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:27:55.209722 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 09:27:55.210164 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:27:55.210366 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 09:27:55.210937 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:27:55.211154 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 09:27:55.211727 runner path: /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/0/tests/0_igt-kms-mediatek test_uuid 14407656_1.5.2.3.1
176 09:27:55.211876 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:27:55.212069 Creating lava-test-runner.conf files
179 09:27:55.212127 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407656/lava-overlay-2d5p3nad/lava-14407656/0 for stage 0
180 09:27:55.212207 - 0_igt-kms-mediatek
181 09:27:55.212298 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 09:27:55.212375 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 09:27:55.218600 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 09:27:55.218700 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 09:27:55.218784 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 09:27:55.218864 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 09:27:55.218942 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 09:27:56.994383 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 09:27:56.994537 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 09:27:56.994621 extracting modules file /var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407656/extract-overlay-ramdisk-hg55bypa/ramdisk
191 09:27:57.251076 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 09:27:57.251219 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 09:27:57.251305 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407656/compress-overlay-kbfc5lr9/overlay-1.5.2.4.tar.gz to ramdisk
194 09:27:57.251369 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407656/compress-overlay-kbfc5lr9/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407656/extract-overlay-ramdisk-hg55bypa/ramdisk
195 09:27:57.257762 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 09:27:57.257874 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 09:27:57.257957 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 09:27:57.258036 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 09:27:57.258104 Building ramdisk /var/lib/lava/dispatcher/tmp/14407656/extract-overlay-ramdisk-hg55bypa/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407656/extract-overlay-ramdisk-hg55bypa/ramdisk
200 09:27:58.421589 >> 466049 blocks
201 09:28:05.273293 rename /var/lib/lava/dispatcher/tmp/14407656/extract-overlay-ramdisk-hg55bypa/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/ramdisk/ramdisk.cpio.gz
202 09:28:05.273467 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 09:28:05.273567 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 09:28:05.273648 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 09:28:05.273727 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/kernel/Image']
206 09:28:20.137809 Returned 0 in 14 seconds
207 09:28:20.238302 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/kernel/image.itb
208 09:28:21.130282 output: FIT description: Kernel Image image with one or more FDT blobs
209 09:28:21.130409 output: Created: Tue Jun 18 10:28:20 2024
210 09:28:21.130475 output: Image 0 (kernel-1)
211 09:28:21.130537 output: Description:
212 09:28:21.130595 output: Created: Tue Jun 18 10:28:20 2024
213 09:28:21.130666 output: Type: Kernel Image
214 09:28:21.130724 output: Compression: lzma compressed
215 09:28:21.130779 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
216 09:28:21.130831 output: Architecture: AArch64
217 09:28:21.130883 output: OS: Linux
218 09:28:21.130934 output: Load Address: 0x00000000
219 09:28:21.130986 output: Entry Point: 0x00000000
220 09:28:21.131035 output: Hash algo: crc32
221 09:28:21.131085 output: Hash value: 4137a6e7
222 09:28:21.131139 output: Image 1 (fdt-1)
223 09:28:21.131191 output: Description: mt8192-asurada-spherion-r0
224 09:28:21.131244 output: Created: Tue Jun 18 10:28:20 2024
225 09:28:21.131300 output: Type: Flat Device Tree
226 09:28:21.131367 output: Compression: uncompressed
227 09:28:21.131423 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 09:28:21.131479 output: Architecture: AArch64
229 09:28:21.131534 output: Hash algo: crc32
230 09:28:21.131588 output: Hash value: 0f8e4d2e
231 09:28:21.131640 output: Image 2 (ramdisk-1)
232 09:28:21.131689 output: Description: unavailable
233 09:28:21.131737 output: Created: Tue Jun 18 10:28:20 2024
234 09:28:21.131785 output: Type: RAMDisk Image
235 09:28:21.131833 output: Compression: uncompressed
236 09:28:21.131882 output: Data Size: 61023162 Bytes = 59592.93 KiB = 58.20 MiB
237 09:28:21.131931 output: Architecture: AArch64
238 09:28:21.131978 output: OS: Linux
239 09:28:21.132026 output: Load Address: unavailable
240 09:28:21.132074 output: Entry Point: unavailable
241 09:28:21.132158 output: Hash algo: crc32
242 09:28:21.132235 output: Hash value: 534e110c
243 09:28:21.132311 output: Default Configuration: 'conf-1'
244 09:28:21.132388 output: Configuration 0 (conf-1)
245 09:28:21.132464 output: Description: mt8192-asurada-spherion-r0
246 09:28:21.132541 output: Kernel: kernel-1
247 09:28:21.132617 output: Init Ramdisk: ramdisk-1
248 09:28:21.132705 output: FDT: fdt-1
249 09:28:21.132776 output: Loadables: kernel-1
250 09:28:21.132855 output:
251 09:28:21.132996 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 09:28:21.133084 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 09:28:21.133174 end: 1.5 prepare-tftp-overlay (duration 00:00:26) [common]
254 09:28:21.133255 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:33) [common]
255 09:28:21.133326 No LXC device requested
256 09:28:21.133399 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 09:28:21.133474 start: 1.7 deploy-device-env (timeout 00:09:33) [common]
258 09:28:21.133544 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 09:28:21.133605 Checking files for TFTP limit of 4294967296 bytes.
260 09:28:21.134045 end: 1 tftp-deploy (duration 00:00:27) [common]
261 09:28:21.134147 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 09:28:21.134234 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 09:28:21.134348 substitutions:
264 09:28:21.134412 - {DTB}: 14407656/tftp-deploy-_tdhyqxs/dtb/mt8192-asurada-spherion-r0.dtb
265 09:28:21.134472 - {INITRD}: 14407656/tftp-deploy-_tdhyqxs/ramdisk/ramdisk.cpio.gz
266 09:28:21.134525 - {KERNEL}: 14407656/tftp-deploy-_tdhyqxs/kernel/Image
267 09:28:21.134578 - {LAVA_MAC}: None
268 09:28:21.134630 - {PRESEED_CONFIG}: None
269 09:28:21.134685 - {PRESEED_LOCAL}: None
270 09:28:21.134736 - {RAMDISK}: 14407656/tftp-deploy-_tdhyqxs/ramdisk/ramdisk.cpio.gz
271 09:28:21.134813 - {ROOT_PART}: None
272 09:28:21.134868 - {ROOT}: None
273 09:28:21.134919 - {SERVER_IP}: 192.168.201.1
274 09:28:21.134969 - {TEE}: None
275 09:28:21.135019 Parsed boot commands:
276 09:28:21.135069 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 09:28:21.135221 Parsed boot commands: tftpboot 192.168.201.1 14407656/tftp-deploy-_tdhyqxs/kernel/image.itb 14407656/tftp-deploy-_tdhyqxs/kernel/cmdline
278 09:28:21.135305 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 09:28:21.135383 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 09:28:21.135468 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 09:28:21.135543 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 09:28:21.135605 Not connected, no need to disconnect.
283 09:28:21.135691 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 09:28:21.135765 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 09:28:21.135826 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 09:28:21.139128 Setting prompt string to ['lava-test: # ']
287 09:28:21.139466 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 09:28:21.139566 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 09:28:21.139659 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 09:28:21.139743 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 09:28:21.139911 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-8']
292 09:28:35.154108 Returned 0 in 14 seconds
293 09:28:35.254664 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 09:28:35.255030 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 09:28:35.255145 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 09:28:35.255282 Setting prompt string to 'Starting depthcharge on Spherion...'
298 09:28:35.255395 Changing prompt to 'Starting depthcharge on Spherion...'
299 09:28:35.255492 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 09:28:35.256089 [Enter `^Ec?' for help]
301 09:28:35.256226
302 09:28:35.256354
303 09:28:35.256510 F0: 102B 0000
304 09:28:35.256603
305 09:28:35.256714 F3: 1001 0000 [0200]
306 09:28:35.256774
307 09:28:35.256831 F3: 1001 0000
308 09:28:35.256886
309 09:28:35.256970 F7: 102D 0000
310 09:28:35.257025
311 09:28:35.257078 F1: 0000 0000
312 09:28:35.257128
313 09:28:35.257178 V0: 0000 0000 [0001]
314 09:28:35.257229
315 09:28:35.257279 00: 0007 8000
316 09:28:35.257329
317 09:28:35.257377 01: 0000 0000
318 09:28:35.257442
319 09:28:35.257520 BP: 0C00 0209 [0000]
320 09:28:35.257569
321 09:28:35.257618 G0: 1182 0000
322 09:28:35.257667
323 09:28:35.257716 EC: 0000 0021 [4000]
324 09:28:35.257765
325 09:28:35.257814 S7: 0000 0000 [0000]
326 09:28:35.257863
327 09:28:35.257925 CC: 0000 0000 [0001]
328 09:28:35.257988
329 09:28:35.258050 T0: 0000 0040 [010F]
330 09:28:35.258098
331 09:28:35.258145 Jump to BL
332 09:28:35.258197
333 09:28:35.258245
334 09:28:35.258293
335 09:28:35.258356 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 09:28:35.258409 ARM64: Exception handlers installed.
337 09:28:35.258460 ARM64: Testing exception
338 09:28:35.258510 ARM64: Done test exception
339 09:28:35.258559 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 09:28:35.258609 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 09:28:35.258662 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 09:28:35.258712 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 09:28:35.258763 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 09:28:35.258813 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 09:28:35.258863 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 09:28:35.258913 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 09:28:35.258962 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 09:28:35.259012 WDT: Last reset was cold boot
349 09:28:35.259062 SPI1(PAD0) initialized at 2873684 Hz
350 09:28:35.259112 SPI5(PAD0) initialized at 992727 Hz
351 09:28:35.259161 VBOOT: Loading verstage.
352 09:28:35.259210 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 09:28:35.259259 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 09:28:35.259309 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 09:28:35.259358 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 09:28:35.259407 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 09:28:35.259457 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 09:28:35.259507 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
359 09:28:35.259557
360 09:28:35.259605
361 09:28:35.259654 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 09:28:35.259704 ARM64: Exception handlers installed.
363 09:28:35.259753 ARM64: Testing exception
364 09:28:35.259801 ARM64: Done test exception
365 09:28:35.259851 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 09:28:35.259901 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 09:28:35.259951 Probing TPM: . done!
368 09:28:35.260000 TPM ready after 0 ms
369 09:28:35.260049 Connected to device vid:did:rid of 1ae0:0028:00
370 09:28:35.260099 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
371 09:28:35.260149 Initialized TPM device CR50 revision 0
372 09:28:35.260198 tlcl_send_startup: Startup return code is 0
373 09:28:35.260247 TPM: setup succeeded
374 09:28:35.260296 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 09:28:35.260346 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 09:28:35.260396 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 09:28:35.260446 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 09:28:35.260495 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 09:28:35.260545 in-header: 03 07 00 00 08 00 00 00
380 09:28:35.260594 in-data: aa e4 47 04 13 02 00 00
381 09:28:35.260648 Chrome EC: UHEPI supported
382 09:28:35.260704 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 09:28:35.260754 in-header: 03 a9 00 00 08 00 00 00
384 09:28:35.260804 in-data: 84 60 60 08 00 00 00 00
385 09:28:35.260853 Phase 1
386 09:28:35.260902 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 09:28:35.260952 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 09:28:35.261002 VB2:vb2_check_recovery() Recovery was requested manually
389 09:28:35.261052 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 09:28:35.261102 Recovery requested (1009000e)
391 09:28:35.261151 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 09:28:35.261200 tlcl_extend: response is 0
393 09:28:35.261250 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 09:28:35.261300 tlcl_extend: response is 0
395 09:28:35.261349 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 09:28:35.261399 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
397 09:28:35.261449 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 09:28:35.261498
399 09:28:35.261546
400 09:28:35.261595 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 09:28:35.261646 ARM64: Exception handlers installed.
402 09:28:35.261696 ARM64: Testing exception
403 09:28:35.261744 ARM64: Done test exception
404 09:28:35.261793 pmic_efuse_setting: Set efuses in 11 msecs
405 09:28:35.261841 pmwrap_interface_init: Select PMIF_VLD_RDY
406 09:28:35.261890 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 09:28:35.261939 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 09:28:35.262188 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 09:28:35.262306 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 09:28:35.262420 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 09:28:35.262532 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 09:28:35.262645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 09:28:35.262757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 09:28:35.262857 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 09:28:35.262911 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 09:28:35.262963 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 09:28:35.263013 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 09:28:35.263063 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 09:28:35.263113 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 09:28:35.263162 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 09:28:35.263213 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 09:28:35.263262 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 09:28:35.263312 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 09:28:35.263362 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 09:28:35.263411 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 09:28:35.263461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 09:28:35.263511 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 09:28:35.263560 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 09:28:35.263610 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 09:28:35.263659 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 09:28:35.263710 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 09:28:35.263771 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 09:28:35.263822 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 09:28:35.263872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 09:28:35.263922 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 09:28:35.263971 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 09:28:35.264021 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 09:28:35.264071 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 09:28:35.264120 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 09:28:35.264170 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 09:28:35.264219 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 09:28:35.264269 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 09:28:35.264319 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 09:28:35.264368 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 09:28:35.264417 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 09:28:35.264466 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 09:28:35.264516 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 09:28:35.264565 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 09:28:35.264614 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 09:28:35.264674 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 09:28:35.264725 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 09:28:35.264774 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 09:28:35.264823 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 09:28:35.264872 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 09:28:35.264921 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 09:28:35.264971 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 09:28:35.265020 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 09:28:35.265071 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 09:28:35.265122 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 09:28:35.265171 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 09:28:35.265220 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 09:28:35.265270 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 09:28:35.265319 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 09:28:35.265369 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 09:28:35.265418 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
466 09:28:35.265468 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 09:28:35.265518 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 09:28:35.265567 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 09:28:35.265616 [RTC]rtc_get_frequency_meter,154: input=15, output=794
470 09:28:35.265666 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
471 09:28:35.265715 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
472 09:28:35.265765 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
473 09:28:35.265815 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
474 09:28:35.265864 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
475 09:28:35.265914 ADC[4]: Raw value=898890 ID=7
476 09:28:35.265963 ADC[3]: Raw value=212700 ID=1
477 09:28:35.266012 RAM Code: 0x71
478 09:28:35.266061 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
479 09:28:35.266110 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
480 09:28:35.266352 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
481 09:28:35.266413 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
482 09:28:35.266465 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
483 09:28:35.266515 in-header: 03 07 00 00 08 00 00 00
484 09:28:35.266565 in-data: aa e4 47 04 13 02 00 00
485 09:28:35.266615 Chrome EC: UHEPI supported
486 09:28:35.266665 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
487 09:28:35.266715 in-header: 03 a9 00 00 08 00 00 00
488 09:28:35.266764 in-data: 84 60 60 08 00 00 00 00
489 09:28:35.266813 MRC: failed to locate region type 0.
490 09:28:35.266862 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
491 09:28:35.266912 DRAM-K: Running full calibration
492 09:28:35.266960 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 09:28:35.267010 header.status = 0x0
494 09:28:35.267058 header.version = 0x6 (expected: 0x6)
495 09:28:35.267108 header.size = 0xd00 (expected: 0xd00)
496 09:28:35.267157 header.flags = 0x0
497 09:28:35.267205 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
498 09:28:35.267254 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
499 09:28:35.267304 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
500 09:28:35.267354 dram_init: ddr_geometry: 2
501 09:28:35.267402 [EMI] MDL number = 2
502 09:28:35.267451 [EMI] Get MDL freq = 0
503 09:28:35.267501 dram_init: ddr_type: 0
504 09:28:35.267550 is_discrete_lpddr4: 1
505 09:28:35.267600 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
506 09:28:35.267650
507 09:28:35.267698
508 09:28:35.267747 [Bian_co] ETT version 0.0.0.1
509 09:28:35.267796 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
510 09:28:35.267845
511 09:28:35.267897 dramc_set_vcore_voltage set vcore to 650000
512 09:28:35.267955 Read voltage for 800, 4
513 09:28:35.268092 Vio18 = 0
514 09:28:35.268204 Vcore = 650000
515 09:28:35.268297 Vdram = 0
516 09:28:35.268377 Vddq = 0
517 09:28:35.268454 Vmddr = 0
518 09:28:35.268532 dram_init: config_dvfs: 1
519 09:28:35.268611 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
520 09:28:35.268689 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
521 09:28:35.268743 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
522 09:28:35.268793 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
523 09:28:35.268844 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
524 09:28:35.268893 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
525 09:28:35.268943 MEM_TYPE=3, freq_sel=18
526 09:28:35.268993 sv_algorithm_assistance_LP4_1600
527 09:28:35.269042 ============ PULL DRAM RESETB DOWN ============
528 09:28:35.269097 ========== PULL DRAM RESETB DOWN end =========
529 09:28:35.269148 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
530 09:28:35.269198 ===================================
531 09:28:35.269248 LPDDR4 DRAM CONFIGURATION
532 09:28:35.269296 ===================================
533 09:28:35.269346 EX_ROW_EN[0] = 0x0
534 09:28:35.269396 EX_ROW_EN[1] = 0x0
535 09:28:35.269445 LP4Y_EN = 0x0
536 09:28:35.269494 WORK_FSP = 0x0
537 09:28:35.269543 WL = 0x2
538 09:28:35.269592 RL = 0x2
539 09:28:35.269640 BL = 0x2
540 09:28:35.269689 RPST = 0x0
541 09:28:35.269738 RD_PRE = 0x0
542 09:28:35.269786 WR_PRE = 0x1
543 09:28:35.269835 WR_PST = 0x0
544 09:28:35.269883 DBI_WR = 0x0
545 09:28:35.269932 DBI_RD = 0x0
546 09:28:35.269981 OTF = 0x1
547 09:28:35.270031 ===================================
548 09:28:35.270080 ===================================
549 09:28:35.270130 ANA top config
550 09:28:35.270178 ===================================
551 09:28:35.270228 DLL_ASYNC_EN = 0
552 09:28:35.270276 ALL_SLAVE_EN = 1
553 09:28:35.270325 NEW_RANK_MODE = 1
554 09:28:35.270375 DLL_IDLE_MODE = 1
555 09:28:35.270424 LP45_APHY_COMB_EN = 1
556 09:28:35.270473 TX_ODT_DIS = 1
557 09:28:35.270522 NEW_8X_MODE = 1
558 09:28:35.270571 ===================================
559 09:28:35.270621 ===================================
560 09:28:35.270670 data_rate = 1600
561 09:28:35.270719 CKR = 1
562 09:28:35.270768 DQ_P2S_RATIO = 8
563 09:28:35.270817 ===================================
564 09:28:35.270866 CA_P2S_RATIO = 8
565 09:28:35.270926 DQ_CA_OPEN = 0
566 09:28:35.270977 DQ_SEMI_OPEN = 0
567 09:28:35.271026 CA_SEMI_OPEN = 0
568 09:28:35.271075 CA_FULL_RATE = 0
569 09:28:35.271125 DQ_CKDIV4_EN = 1
570 09:28:35.271173 CA_CKDIV4_EN = 1
571 09:28:35.271222 CA_PREDIV_EN = 0
572 09:28:35.271270 PH8_DLY = 0
573 09:28:35.271318 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
574 09:28:35.271367 DQ_AAMCK_DIV = 4
575 09:28:35.271416 CA_AAMCK_DIV = 4
576 09:28:35.271464 CA_ADMCK_DIV = 4
577 09:28:35.271512 DQ_TRACK_CA_EN = 0
578 09:28:35.271560 CA_PICK = 800
579 09:28:35.271610 CA_MCKIO = 800
580 09:28:35.271658 MCKIO_SEMI = 0
581 09:28:35.271707 PLL_FREQ = 3068
582 09:28:35.271756 DQ_UI_PI_RATIO = 32
583 09:28:35.271805 CA_UI_PI_RATIO = 0
584 09:28:35.271854 ===================================
585 09:28:35.271903 ===================================
586 09:28:35.271953 memory_type:LPDDR4
587 09:28:35.272002 GP_NUM : 10
588 09:28:35.272051 SRAM_EN : 1
589 09:28:35.272100 MD32_EN : 0
590 09:28:35.272149 ===================================
591 09:28:35.272197 [ANA_INIT] >>>>>>>>>>>>>>
592 09:28:35.272246 <<<<<< [CONFIGURE PHASE]: ANA_TX
593 09:28:35.272301 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
594 09:28:35.272351 ===================================
595 09:28:35.272400 data_rate = 1600,PCW = 0X7600
596 09:28:35.272449 ===================================
597 09:28:35.272498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
598 09:28:35.272548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
599 09:28:35.272598 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 09:28:35.272863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
601 09:28:35.272979 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
602 09:28:35.273093 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
603 09:28:35.273207 [ANA_INIT] flow start
604 09:28:35.273317 [ANA_INIT] PLL >>>>>>>>
605 09:28:35.273431 [ANA_INIT] PLL <<<<<<<<
606 09:28:35.273542 [ANA_INIT] MIDPI >>>>>>>>
607 09:28:35.273655 [ANA_INIT] MIDPI <<<<<<<<
608 09:28:35.273765 [ANA_INIT] DLL >>>>>>>>
609 09:28:35.273877 [ANA_INIT] flow end
610 09:28:35.273986 ============ LP4 DIFF to SE enter ============
611 09:28:35.274100 ============ LP4 DIFF to SE exit ============
612 09:28:35.274181 [ANA_INIT] <<<<<<<<<<<<<
613 09:28:35.274233 [Flow] Enable top DCM control >>>>>
614 09:28:35.274283 [Flow] Enable top DCM control <<<<<
615 09:28:35.274333 Enable DLL master slave shuffle
616 09:28:35.274382 ==============================================================
617 09:28:35.274433 Gating Mode config
618 09:28:35.274484 ==============================================================
619 09:28:35.274534 Config description:
620 09:28:35.274583 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
621 09:28:35.274634 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
622 09:28:35.274685 SELPH_MODE 0: By rank 1: By Phase
623 09:28:35.274735 ==============================================================
624 09:28:35.274786 GAT_TRACK_EN = 1
625 09:28:35.274835 RX_GATING_MODE = 2
626 09:28:35.274885 RX_GATING_TRACK_MODE = 2
627 09:28:35.274935 SELPH_MODE = 1
628 09:28:35.274984 PICG_EARLY_EN = 1
629 09:28:35.275034 VALID_LAT_VALUE = 1
630 09:28:35.275083 ==============================================================
631 09:28:35.275133 Enter into Gating configuration >>>>
632 09:28:35.275182 Exit from Gating configuration <<<<
633 09:28:35.275231 Enter into DVFS_PRE_config >>>>>
634 09:28:35.275280 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
635 09:28:35.275335 Exit from DVFS_PRE_config <<<<<
636 09:28:35.275384 Enter into PICG configuration >>>>
637 09:28:35.275433 Exit from PICG configuration <<<<
638 09:28:35.275482 [RX_INPUT] configuration >>>>>
639 09:28:35.275531 [RX_INPUT] configuration <<<<<
640 09:28:35.275580 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
641 09:28:35.275630 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
642 09:28:35.275680 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
643 09:28:35.275730 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
644 09:28:35.275779 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
645 09:28:35.275829 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
646 09:28:35.275878 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
647 09:28:35.275928 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
648 09:28:35.275976 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
649 09:28:35.276026 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
650 09:28:35.276075 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
651 09:28:35.276125 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
652 09:28:35.276174 ===================================
653 09:28:35.276224 LPDDR4 DRAM CONFIGURATION
654 09:28:35.276272 ===================================
655 09:28:35.276322 EX_ROW_EN[0] = 0x0
656 09:28:35.276371 EX_ROW_EN[1] = 0x0
657 09:28:35.276420 LP4Y_EN = 0x0
658 09:28:35.276468 WORK_FSP = 0x0
659 09:28:35.276517 WL = 0x2
660 09:28:35.276565 RL = 0x2
661 09:28:35.276614 BL = 0x2
662 09:28:35.276673 RPST = 0x0
663 09:28:35.276723 RD_PRE = 0x0
664 09:28:35.276771 WR_PRE = 0x1
665 09:28:35.276820 WR_PST = 0x0
666 09:28:35.276869 DBI_WR = 0x0
667 09:28:35.276918 DBI_RD = 0x0
668 09:28:35.276966 OTF = 0x1
669 09:28:35.277015 ===================================
670 09:28:35.277065 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
671 09:28:35.277114 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
672 09:28:35.277164 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 09:28:35.277214 ===================================
674 09:28:35.277264 LPDDR4 DRAM CONFIGURATION
675 09:28:35.277313 ===================================
676 09:28:35.277363 EX_ROW_EN[0] = 0x10
677 09:28:35.277411 EX_ROW_EN[1] = 0x0
678 09:28:35.277460 LP4Y_EN = 0x0
679 09:28:35.277508 WORK_FSP = 0x0
680 09:28:35.277557 WL = 0x2
681 09:28:35.277606 RL = 0x2
682 09:28:35.277655 BL = 0x2
683 09:28:35.277704 RPST = 0x0
684 09:28:35.277753 RD_PRE = 0x0
685 09:28:35.277802 WR_PRE = 0x1
686 09:28:35.277850 WR_PST = 0x0
687 09:28:35.277900 DBI_WR = 0x0
688 09:28:35.277948 DBI_RD = 0x0
689 09:28:35.277997 OTF = 0x1
690 09:28:35.278046 ===================================
691 09:28:35.278096 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
692 09:28:35.278146 nWR fixed to 40
693 09:28:35.278196 [ModeRegInit_LP4] CH0 RK0
694 09:28:35.278245 [ModeRegInit_LP4] CH0 RK1
695 09:28:35.278294 [ModeRegInit_LP4] CH1 RK0
696 09:28:35.278343 [ModeRegInit_LP4] CH1 RK1
697 09:28:35.278392 match AC timing 13
698 09:28:35.278440 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
699 09:28:35.278490 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
700 09:28:35.278539 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
701 09:28:35.278589 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
702 09:28:35.278639 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
703 09:28:35.278689 [EMI DOE] emi_dcm 0
704 09:28:35.278738 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
705 09:28:35.278787 ==
706 09:28:35.278837 Dram Type= 6, Freq= 0, CH_0, rank 0
707 09:28:35.278887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
708 09:28:35.278936 ==
709 09:28:35.279184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
710 09:28:35.279298 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
711 09:28:35.279413 [CA 0] Center 38 (7~69) winsize 63
712 09:28:35.279525 [CA 1] Center 38 (7~69) winsize 63
713 09:28:35.279638 [CA 2] Center 35 (5~66) winsize 62
714 09:28:35.279750 [CA 3] Center 35 (5~66) winsize 62
715 09:28:35.279849 [CA 4] Center 34 (4~65) winsize 62
716 09:28:35.279903 [CA 5] Center 34 (4~65) winsize 62
717 09:28:35.279954
718 09:28:35.280016 [CmdBusTrainingLP45] Vref(ca) range 1: 32
719 09:28:35.280188
720 09:28:35.280280 [CATrainingPosCal] consider 1 rank data
721 09:28:35.280372 u2DelayCellTimex100 = 270/100 ps
722 09:28:35.280452 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
723 09:28:35.280531 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
724 09:28:35.280609 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
725 09:28:35.280683 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
726 09:28:35.280735 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
727 09:28:35.280785 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
728 09:28:35.280835
729 09:28:35.280885 CA PerBit enable=1, Macro0, CA PI delay=34
730 09:28:35.280935
731 09:28:35.280984 [CBTSetCACLKResult] CA Dly = 34
732 09:28:35.281033 CS Dly: 6 (0~37)
733 09:28:35.281082 ==
734 09:28:35.281131 Dram Type= 6, Freq= 0, CH_0, rank 1
735 09:28:35.281181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
736 09:28:35.281230 ==
737 09:28:35.281280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
738 09:28:35.281330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
739 09:28:35.281380 [CA 0] Center 38 (7~69) winsize 63
740 09:28:35.281429 [CA 1] Center 38 (7~69) winsize 63
741 09:28:35.281477 [CA 2] Center 35 (5~66) winsize 62
742 09:28:35.281527 [CA 3] Center 35 (5~66) winsize 62
743 09:28:35.281577 [CA 4] Center 34 (4~65) winsize 62
744 09:28:35.281627 [CA 5] Center 34 (3~65) winsize 63
745 09:28:35.281675
746 09:28:35.281724 [CmdBusTrainingLP45] Vref(ca) range 1: 34
747 09:28:35.281772
748 09:28:35.281821 [CATrainingPosCal] consider 2 rank data
749 09:28:35.281871 u2DelayCellTimex100 = 270/100 ps
750 09:28:35.281920 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
751 09:28:35.281970 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
752 09:28:35.282019 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
753 09:28:35.282068 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
754 09:28:35.282116 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
755 09:28:35.282164 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
756 09:28:35.282212
757 09:28:35.282262 CA PerBit enable=1, Macro0, CA PI delay=34
758 09:28:35.282312
759 09:28:35.282361 [CBTSetCACLKResult] CA Dly = 34
760 09:28:35.282411 CS Dly: 6 (0~37)
761 09:28:35.282459
762 09:28:35.282508 ----->DramcWriteLeveling(PI) begin...
763 09:28:35.282558 ==
764 09:28:35.282607 Dram Type= 6, Freq= 0, CH_0, rank 0
765 09:28:35.282656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
766 09:28:35.282706 ==
767 09:28:35.282755 Write leveling (Byte 0): 31 => 31
768 09:28:35.282805 Write leveling (Byte 1): 30 => 30
769 09:28:35.282854 DramcWriteLeveling(PI) end<-----
770 09:28:35.282903
771 09:28:35.282952 ==
772 09:28:35.283001 Dram Type= 6, Freq= 0, CH_0, rank 0
773 09:28:35.283050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 09:28:35.283100 ==
775 09:28:35.283149 [Gating] SW mode calibration
776 09:28:35.283198 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
777 09:28:35.283248 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
778 09:28:35.283298 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
779 09:28:35.283347 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 09:28:35.283397 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
781 09:28:35.283446 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
782 09:28:35.283496 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 09:28:35.283544 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 09:28:35.283593 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 09:28:35.283643 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 09:28:35.283692 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 09:28:35.283741 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 09:28:35.283790 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 09:28:35.283840 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 09:28:35.283889 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 09:28:35.283938 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 09:28:35.283987 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 09:28:35.284036 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 09:28:35.284086 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 09:28:35.284136 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 09:28:35.284185 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 09:28:35.284234 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
798 09:28:35.284283 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 09:28:35.284333 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 09:28:35.284382 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 09:28:35.284431 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 09:28:35.284480 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 09:28:35.284529 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 09:28:35.284579 0 9 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
805 09:28:35.284628 0 9 12 | B1->B0 | 2525 3131 | 1 0 | (1 1) (0 0)
806 09:28:35.284693 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
807 09:28:35.284743 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 09:28:35.284792 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 09:28:35.284842 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 09:28:35.284892 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 09:28:35.284941 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 09:28:35.284991 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
813 09:28:35.285040 0 10 12 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
814 09:28:35.285090 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 09:28:35.285346 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 09:28:35.285404 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 09:28:35.285456 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 09:28:35.285507 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 09:28:35.285557 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 09:28:35.285606 0 11 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
821 09:28:35.285656 0 11 12 | B1->B0 | 3636 4545 | 0 0 | (1 1) (0 0)
822 09:28:35.285705 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
823 09:28:35.285754 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 09:28:35.285803 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 09:28:35.285853 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 09:28:35.285902 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 09:28:35.285952 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 09:28:35.286002 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
829 09:28:35.286051 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
830 09:28:35.286101 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 09:28:35.286150 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 09:28:35.286199 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 09:28:35.286249 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 09:28:35.286301 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 09:28:35.286351 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 09:28:35.286400 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 09:28:35.286449 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 09:28:35.286499 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 09:28:35.286548 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 09:28:35.286597 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 09:28:35.286647 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 09:28:35.286697 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 09:28:35.286746 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:28:35.286796 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
845 09:28:35.286846 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
846 09:28:35.286895 Total UI for P1: 0, mck2ui 16
847 09:28:35.286945 best dqsien dly found for B0: ( 0, 14, 8)
848 09:28:35.286995 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 09:28:35.287044 Total UI for P1: 0, mck2ui 16
850 09:28:35.287093 best dqsien dly found for B1: ( 0, 14, 12)
851 09:28:35.287143 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
852 09:28:35.287192 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
853 09:28:35.287242
854 09:28:35.287291 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
855 09:28:35.287341 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
856 09:28:35.287390 [Gating] SW calibration Done
857 09:28:35.287440 ==
858 09:28:35.287489 Dram Type= 6, Freq= 0, CH_0, rank 0
859 09:28:35.287537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 09:28:35.287587 ==
861 09:28:35.287635 RX Vref Scan: 0
862 09:28:35.287685
863 09:28:35.287734 RX Vref 0 -> 0, step: 1
864 09:28:35.287782
865 09:28:35.287831 RX Delay -130 -> 252, step: 16
866 09:28:35.287880 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
867 09:28:35.287930 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
868 09:28:35.287978 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
869 09:28:35.288028 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
870 09:28:35.288077 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
871 09:28:35.288125 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
872 09:28:35.288175 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
873 09:28:35.288223 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
874 09:28:35.288273 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
875 09:28:35.288322 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
876 09:28:35.288370 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
877 09:28:35.288419 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
878 09:28:35.288469 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
879 09:28:35.288518 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
880 09:28:35.288568 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
881 09:28:35.288617 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
882 09:28:35.288679 ==
883 09:28:35.288731 Dram Type= 6, Freq= 0, CH_0, rank 0
884 09:28:35.288780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 09:28:35.288830 ==
886 09:28:35.288879 DQS Delay:
887 09:28:35.288928 DQS0 = 0, DQS1 = 0
888 09:28:35.288977 DQM Delay:
889 09:28:35.289026 DQM0 = 81, DQM1 = 70
890 09:28:35.289076 DQ Delay:
891 09:28:35.289125 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
892 09:28:35.289174 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
893 09:28:35.289231 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
894 09:28:35.289283 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 09:28:35.289332
896 09:28:35.289380
897 09:28:35.289429 ==
898 09:28:35.289478 Dram Type= 6, Freq= 0, CH_0, rank 0
899 09:28:35.289527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 09:28:35.289580 ==
901 09:28:35.289629
902 09:28:35.289677
903 09:28:35.289726 TX Vref Scan disable
904 09:28:35.289775 == TX Byte 0 ==
905 09:28:35.289824 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
906 09:28:35.289874 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
907 09:28:35.289922 == TX Byte 1 ==
908 09:28:35.289970 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
909 09:28:35.290019 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
910 09:28:35.290069 ==
911 09:28:35.290118 Dram Type= 6, Freq= 0, CH_0, rank 0
912 09:28:35.290167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 09:28:35.290217 ==
914 09:28:35.290266 TX Vref=22, minBit 3, minWin=26, winSum=428
915 09:28:35.290316 TX Vref=24, minBit 3, minWin=26, winSum=437
916 09:28:35.290365 TX Vref=26, minBit 2, minWin=27, winSum=443
917 09:28:35.290414 TX Vref=28, minBit 11, minWin=27, winSum=444
918 09:28:35.290464 TX Vref=30, minBit 1, minWin=27, winSum=440
919 09:28:35.290514 TX Vref=32, minBit 10, minWin=26, winSum=437
920 09:28:35.290563 [TxChooseVref] Worse bit 11, Min win 27, Win sum 444, Final Vref 28
921 09:28:35.290613
922 09:28:35.290662 Final TX Range 1 Vref 28
923 09:28:35.290712
924 09:28:35.290761 ==
925 09:28:35.290810 Dram Type= 6, Freq= 0, CH_0, rank 0
926 09:28:35.291059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 09:28:35.291176 ==
928 09:28:35.291286
929 09:28:35.291395
930 09:28:35.291506 TX Vref Scan disable
931 09:28:35.291618 == TX Byte 0 ==
932 09:28:35.291727 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
933 09:28:35.291841 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
934 09:28:35.291951 == TX Byte 1 ==
935 09:28:35.292062 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
936 09:28:35.292173 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
937 09:28:35.292285
938 09:28:35.292377 [DATLAT]
939 09:28:35.292456 Freq=800, CH0 RK0
940 09:28:35.292534
941 09:28:35.292611 DATLAT Default: 0xa
942 09:28:35.292686 0, 0xFFFF, sum = 0
943 09:28:35.292739 1, 0xFFFF, sum = 0
944 09:28:35.292790 2, 0xFFFF, sum = 0
945 09:28:35.292840 3, 0xFFFF, sum = 0
946 09:28:35.292891 4, 0xFFFF, sum = 0
947 09:28:35.292941 5, 0xFFFF, sum = 0
948 09:28:35.292991 6, 0xFFFF, sum = 0
949 09:28:35.293041 7, 0xFFFF, sum = 0
950 09:28:35.293090 8, 0xFFFF, sum = 0
951 09:28:35.293140 9, 0x0, sum = 1
952 09:28:35.293191 10, 0x0, sum = 2
953 09:28:35.293241 11, 0x0, sum = 3
954 09:28:35.293291 12, 0x0, sum = 4
955 09:28:35.293341 best_step = 10
956 09:28:35.293389
957 09:28:35.293438 ==
958 09:28:35.293487 Dram Type= 6, Freq= 0, CH_0, rank 0
959 09:28:35.293537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 09:28:35.293588 ==
961 09:28:35.293637 RX Vref Scan: 1
962 09:28:35.293685
963 09:28:35.293734 Set Vref Range= 32 -> 127
964 09:28:35.293784
965 09:28:35.293833 RX Vref 32 -> 127, step: 1
966 09:28:35.293882
967 09:28:35.293930 RX Delay -111 -> 252, step: 8
968 09:28:35.293979
969 09:28:35.294028 Set Vref, RX VrefLevel [Byte0]: 32
970 09:28:35.294078 [Byte1]: 32
971 09:28:35.294127
972 09:28:35.294176 Set Vref, RX VrefLevel [Byte0]: 33
973 09:28:35.294225 [Byte1]: 33
974 09:28:35.294274
975 09:28:35.294323 Set Vref, RX VrefLevel [Byte0]: 34
976 09:28:35.294372 [Byte1]: 34
977 09:28:35.294421
978 09:28:35.294470 Set Vref, RX VrefLevel [Byte0]: 35
979 09:28:35.294519 [Byte1]: 35
980 09:28:35.294567
981 09:28:35.294616 Set Vref, RX VrefLevel [Byte0]: 36
982 09:28:35.294665 [Byte1]: 36
983 09:28:35.294714
984 09:28:35.294763 Set Vref, RX VrefLevel [Byte0]: 37
985 09:28:35.294812 [Byte1]: 37
986 09:28:35.294861
987 09:28:35.294909 Set Vref, RX VrefLevel [Byte0]: 38
988 09:28:35.294957 [Byte1]: 38
989 09:28:35.295006
990 09:28:35.295055 Set Vref, RX VrefLevel [Byte0]: 39
991 09:28:35.295104 [Byte1]: 39
992 09:28:35.295154
993 09:28:35.295202 Set Vref, RX VrefLevel [Byte0]: 40
994 09:28:35.295251 [Byte1]: 40
995 09:28:35.295299
996 09:28:35.295348 Set Vref, RX VrefLevel [Byte0]: 41
997 09:28:35.295397 [Byte1]: 41
998 09:28:35.295444
999 09:28:35.295493 Set Vref, RX VrefLevel [Byte0]: 42
1000 09:28:35.295542 [Byte1]: 42
1001 09:28:35.295591
1002 09:28:35.295639 Set Vref, RX VrefLevel [Byte0]: 43
1003 09:28:35.295688 [Byte1]: 43
1004 09:28:35.295737
1005 09:28:35.295786 Set Vref, RX VrefLevel [Byte0]: 44
1006 09:28:35.295834 [Byte1]: 44
1007 09:28:35.295883
1008 09:28:35.295931 Set Vref, RX VrefLevel [Byte0]: 45
1009 09:28:35.295981 [Byte1]: 45
1010 09:28:35.296030
1011 09:28:35.296079 Set Vref, RX VrefLevel [Byte0]: 46
1012 09:28:35.296128 [Byte1]: 46
1013 09:28:35.296177
1014 09:28:35.296227 Set Vref, RX VrefLevel [Byte0]: 47
1015 09:28:35.296277 [Byte1]: 47
1016 09:28:35.296326
1017 09:28:35.296375 Set Vref, RX VrefLevel [Byte0]: 48
1018 09:28:35.296424 [Byte1]: 48
1019 09:28:35.296472
1020 09:28:35.296520 Set Vref, RX VrefLevel [Byte0]: 49
1021 09:28:35.296569 [Byte1]: 49
1022 09:28:35.296621
1023 09:28:35.296680 Set Vref, RX VrefLevel [Byte0]: 50
1024 09:28:35.296731 [Byte1]: 50
1025 09:28:35.296780
1026 09:28:35.296829 Set Vref, RX VrefLevel [Byte0]: 51
1027 09:28:35.296878 [Byte1]: 51
1028 09:28:35.296928
1029 09:28:35.296977 Set Vref, RX VrefLevel [Byte0]: 52
1030 09:28:35.297026 [Byte1]: 52
1031 09:28:35.297076
1032 09:28:35.297125 Set Vref, RX VrefLevel [Byte0]: 53
1033 09:28:35.297175 [Byte1]: 53
1034 09:28:35.297224
1035 09:28:35.297273 Set Vref, RX VrefLevel [Byte0]: 54
1036 09:28:35.297322 [Byte1]: 54
1037 09:28:35.297371
1038 09:28:35.297420 Set Vref, RX VrefLevel [Byte0]: 55
1039 09:28:35.297469 [Byte1]: 55
1040 09:28:35.297519
1041 09:28:35.297568 Set Vref, RX VrefLevel [Byte0]: 56
1042 09:28:35.297617 [Byte1]: 56
1043 09:28:35.297666
1044 09:28:35.297715 Set Vref, RX VrefLevel [Byte0]: 57
1045 09:28:35.297764 [Byte1]: 57
1046 09:28:35.297813
1047 09:28:35.297861 Set Vref, RX VrefLevel [Byte0]: 58
1048 09:28:35.297910 [Byte1]: 58
1049 09:28:35.297960
1050 09:28:35.298009 Set Vref, RX VrefLevel [Byte0]: 59
1051 09:28:35.298059 [Byte1]: 59
1052 09:28:35.298108
1053 09:28:35.298157 Set Vref, RX VrefLevel [Byte0]: 60
1054 09:28:35.298206 [Byte1]: 60
1055 09:28:35.298255
1056 09:28:35.298303 Set Vref, RX VrefLevel [Byte0]: 61
1057 09:28:35.298352 [Byte1]: 61
1058 09:28:35.298401
1059 09:28:35.298450 Set Vref, RX VrefLevel [Byte0]: 62
1060 09:28:35.298499 [Byte1]: 62
1061 09:28:35.298549
1062 09:28:35.298598 Set Vref, RX VrefLevel [Byte0]: 63
1063 09:28:35.298647 [Byte1]: 63
1064 09:28:35.298696
1065 09:28:35.298745 Set Vref, RX VrefLevel [Byte0]: 64
1066 09:28:35.298794 [Byte1]: 64
1067 09:28:35.298842
1068 09:28:35.298891 Set Vref, RX VrefLevel [Byte0]: 65
1069 09:28:35.298940 [Byte1]: 65
1070 09:28:35.298990
1071 09:28:35.299038 Set Vref, RX VrefLevel [Byte0]: 66
1072 09:28:35.299088 [Byte1]: 66
1073 09:28:35.299137
1074 09:28:35.299186 Set Vref, RX VrefLevel [Byte0]: 67
1075 09:28:35.299235 [Byte1]: 67
1076 09:28:35.299284
1077 09:28:35.299333 Set Vref, RX VrefLevel [Byte0]: 68
1078 09:28:35.299382 [Byte1]: 68
1079 09:28:35.299431
1080 09:28:35.299495 Set Vref, RX VrefLevel [Byte0]: 69
1081 09:28:35.299547 [Byte1]: 69
1082 09:28:35.299596
1083 09:28:35.299645 Set Vref, RX VrefLevel [Byte0]: 70
1084 09:28:35.299695 [Byte1]: 70
1085 09:28:35.299744
1086 09:28:35.299792 Set Vref, RX VrefLevel [Byte0]: 71
1087 09:28:35.299841 [Byte1]: 71
1088 09:28:35.299890
1089 09:28:35.299939 Set Vref, RX VrefLevel [Byte0]: 72
1090 09:28:35.299989 [Byte1]: 72
1091 09:28:35.300037
1092 09:28:35.300086 Set Vref, RX VrefLevel [Byte0]: 73
1093 09:28:35.300136 [Byte1]: 73
1094 09:28:35.300185
1095 09:28:35.300234 Set Vref, RX VrefLevel [Byte0]: 74
1096 09:28:35.300284 [Byte1]: 74
1097 09:28:35.300332
1098 09:28:35.300583 Set Vref, RX VrefLevel [Byte0]: 75
1099 09:28:35.300719 [Byte1]: 75
1100 09:28:35.300833
1101 09:28:35.300945 Set Vref, RX VrefLevel [Byte0]: 76
1102 09:28:35.301057 [Byte1]: 76
1103 09:28:35.301168
1104 09:28:35.301278 Set Vref, RX VrefLevel [Byte0]: 77
1105 09:28:35.301346 [Byte1]: 77
1106 09:28:35.301399
1107 09:28:35.301458 Set Vref, RX VrefLevel [Byte0]: 78
1108 09:28:35.301535 [Byte1]: 78
1109 09:28:35.301622
1110 09:28:35.301701 Set Vref, RX VrefLevel [Byte0]: 79
1111 09:28:35.301782 [Byte1]: 79
1112 09:28:35.301836
1113 09:28:35.301885 Set Vref, RX VrefLevel [Byte0]: 80
1114 09:28:35.301935 [Byte1]: 80
1115 09:28:35.301985
1116 09:28:35.302034 Final RX Vref Byte 0 = 56 to rank0
1117 09:28:35.302084 Final RX Vref Byte 1 = 54 to rank0
1118 09:28:35.302134 Final RX Vref Byte 0 = 56 to rank1
1119 09:28:35.302183 Final RX Vref Byte 1 = 54 to rank1==
1120 09:28:35.302233 Dram Type= 6, Freq= 0, CH_0, rank 0
1121 09:28:35.302284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1122 09:28:35.302333 ==
1123 09:28:35.302382 DQS Delay:
1124 09:28:35.302431 DQS0 = 0, DQS1 = 0
1125 09:28:35.302480 DQM Delay:
1126 09:28:35.302529 DQM0 = 82, DQM1 = 69
1127 09:28:35.302579 DQ Delay:
1128 09:28:35.302627 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1129 09:28:35.302676 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1130 09:28:35.302725 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =64
1131 09:28:35.302775 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =76
1132 09:28:35.302824
1133 09:28:35.302872
1134 09:28:35.302921 [DQSOSCAuto] RK0, (LSB)MR18= 0x2928, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1135 09:28:35.302972 CH0 RK0: MR19=606, MR18=2928
1136 09:28:35.303022 CH0_RK0: MR19=0x606, MR18=0x2928, DQSOSC=399, MR23=63, INC=92, DEC=61
1137 09:28:35.303072
1138 09:28:35.303121 ----->DramcWriteLeveling(PI) begin...
1139 09:28:35.303172 ==
1140 09:28:35.303221 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 09:28:35.303270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 09:28:35.303320 ==
1143 09:28:35.303369 Write leveling (Byte 0): 30 => 30
1144 09:28:35.303419 Write leveling (Byte 1): 30 => 30
1145 09:28:35.303469 DramcWriteLeveling(PI) end<-----
1146 09:28:35.303519
1147 09:28:35.303567 ==
1148 09:28:35.303615 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 09:28:35.303665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 09:28:35.303714 ==
1151 09:28:35.303763 [Gating] SW mode calibration
1152 09:28:35.303812 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1153 09:28:35.303862 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1154 09:28:35.303912 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 09:28:35.303962 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1156 09:28:35.304012 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1157 09:28:35.304061 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 09:28:35.304111 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 09:28:35.304159 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 09:28:35.304208 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 09:28:35.304256 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 09:28:35.304305 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 09:28:35.304355 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 09:28:35.304404 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 09:28:35.304454 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 09:28:35.304503 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 09:28:35.304552 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 09:28:35.304601 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 09:28:35.304659 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 09:28:35.304711 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 09:28:35.304761 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1172 09:28:35.304810 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1173 09:28:35.304859 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 09:28:35.304908 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 09:28:35.304958 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 09:28:35.305007 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 09:28:35.305057 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 09:28:35.305106 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 09:28:35.305155 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 09:28:35.305204 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
1181 09:28:35.305253 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1182 09:28:35.305302 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 09:28:35.305351 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 09:28:35.305400 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 09:28:35.305449 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 09:28:35.305498 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 09:28:35.305547 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1188 09:28:35.305597 0 10 8 | B1->B0 | 3333 2525 | 1 1 | (0 1) (1 0)
1189 09:28:35.305646 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 09:28:35.305695 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 09:28:35.305744 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 09:28:35.305793 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 09:28:35.305842 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 09:28:35.305891 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 09:28:35.305940 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1196 09:28:35.305989 0 11 8 | B1->B0 | 3131 3c3c | 0 0 | (0 0) (0 0)
1197 09:28:35.306039 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1198 09:28:35.306088 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 09:28:35.306138 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 09:28:35.306187 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 09:28:35.306237 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 09:28:35.306490 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 09:28:35.306547 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 09:28:35.306597 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1205 09:28:35.306647 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1206 09:28:35.306697 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 09:28:35.306747 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 09:28:35.306795 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 09:28:35.306844 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 09:28:35.306893 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 09:28:35.306942 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 09:28:35.306991 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 09:28:35.307041 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 09:28:35.307090 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 09:28:35.307140 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 09:28:35.307188 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 09:28:35.307237 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 09:28:35.307287 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 09:28:35.307336 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1220 09:28:35.307386 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1221 09:28:35.307436 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 09:28:35.307485 Total UI for P1: 0, mck2ui 16
1223 09:28:35.307535 best dqsien dly found for B0: ( 0, 14, 6)
1224 09:28:35.307585 Total UI for P1: 0, mck2ui 16
1225 09:28:35.307634 best dqsien dly found for B1: ( 0, 14, 10)
1226 09:28:35.307683 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1227 09:28:35.307732 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1228 09:28:35.307782
1229 09:28:35.307831 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1230 09:28:35.307881 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1231 09:28:35.307930 [Gating] SW calibration Done
1232 09:28:35.307979 ==
1233 09:28:35.308029 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 09:28:35.308079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 09:28:35.308128 ==
1236 09:28:35.308176 RX Vref Scan: 0
1237 09:28:35.308225
1238 09:28:35.308274 RX Vref 0 -> 0, step: 1
1239 09:28:35.308323
1240 09:28:35.308371 RX Delay -130 -> 252, step: 16
1241 09:28:35.308420 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1242 09:28:35.308470 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1243 09:28:35.308519 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1244 09:28:35.308567 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1245 09:28:35.308616 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1246 09:28:35.308677 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1247 09:28:35.308728 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1248 09:28:35.308778 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1249 09:28:35.308827 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1250 09:28:35.308876 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1251 09:28:35.308925 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1252 09:28:35.308975 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1253 09:28:35.309024 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1254 09:28:35.309073 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1255 09:28:35.309122 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1256 09:28:35.309170 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1257 09:28:35.309220 ==
1258 09:28:35.309268 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 09:28:35.309318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 09:28:35.309368 ==
1261 09:28:35.309417 DQS Delay:
1262 09:28:35.309467 DQS0 = 0, DQS1 = 0
1263 09:28:35.309515 DQM Delay:
1264 09:28:35.309563 DQM0 = 76, DQM1 = 70
1265 09:28:35.309612 DQ Delay:
1266 09:28:35.309661 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1267 09:28:35.309710 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1268 09:28:35.309759 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1269 09:28:35.309808 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1270 09:28:35.309857
1271 09:28:35.309905
1272 09:28:35.309953 ==
1273 09:28:35.310001 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 09:28:35.310051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 09:28:35.310100 ==
1276 09:28:35.310149
1277 09:28:35.310198
1278 09:28:35.310246 TX Vref Scan disable
1279 09:28:35.310295 == TX Byte 0 ==
1280 09:28:35.310344 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1281 09:28:35.310393 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1282 09:28:35.310442 == TX Byte 1 ==
1283 09:28:35.310491 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1284 09:28:35.310540 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1285 09:28:35.310589 ==
1286 09:28:35.310638 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 09:28:35.310688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 09:28:35.310737 ==
1289 09:28:35.310786 TX Vref=22, minBit 1, minWin=26, winSum=432
1290 09:28:35.310836 TX Vref=24, minBit 2, minWin=27, winSum=439
1291 09:28:35.310886 TX Vref=26, minBit 0, minWin=27, winSum=444
1292 09:28:35.310935 TX Vref=28, minBit 8, minWin=27, winSum=443
1293 09:28:35.310984 TX Vref=30, minBit 7, minWin=27, winSum=443
1294 09:28:35.311033 TX Vref=32, minBit 6, minWin=27, winSum=442
1295 09:28:35.311082 [TxChooseVref] Worse bit 0, Min win 27, Win sum 444, Final Vref 26
1296 09:28:35.311133
1297 09:28:35.311219 Final TX Range 1 Vref 26
1298 09:28:35.311368
1299 09:28:35.311465 ==
1300 09:28:35.311547 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 09:28:35.311600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 09:28:35.311651 ==
1303 09:28:35.311700
1304 09:28:35.311747
1305 09:28:35.311796 TX Vref Scan disable
1306 09:28:35.311844 == TX Byte 0 ==
1307 09:28:35.311893 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1308 09:28:35.311942 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1309 09:28:35.311990 == TX Byte 1 ==
1310 09:28:35.312039 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1311 09:28:35.312088 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1312 09:28:35.312136
1313 09:28:35.312184 [DATLAT]
1314 09:28:35.312233 Freq=800, CH0 RK1
1315 09:28:35.312282
1316 09:28:35.312329 DATLAT Default: 0xa
1317 09:28:35.312377 0, 0xFFFF, sum = 0
1318 09:28:35.312427 1, 0xFFFF, sum = 0
1319 09:28:35.312476 2, 0xFFFF, sum = 0
1320 09:28:35.312526 3, 0xFFFF, sum = 0
1321 09:28:35.312575 4, 0xFFFF, sum = 0
1322 09:28:35.312658 5, 0xFFFF, sum = 0
1323 09:28:35.312806 6, 0xFFFF, sum = 0
1324 09:28:35.312906 7, 0xFFFF, sum = 0
1325 09:28:35.312987 8, 0xFFFF, sum = 0
1326 09:28:35.313039 9, 0x0, sum = 1
1327 09:28:35.313089 10, 0x0, sum = 2
1328 09:28:35.313139 11, 0x0, sum = 3
1329 09:28:35.313189 12, 0x0, sum = 4
1330 09:28:35.313238 best_step = 10
1331 09:28:35.313287
1332 09:28:35.313335 ==
1333 09:28:35.313581 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 09:28:35.313693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 09:28:35.313806 ==
1336 09:28:35.313916 RX Vref Scan: 0
1337 09:28:35.314026
1338 09:28:35.314136 RX Vref 0 -> 0, step: 1
1339 09:28:35.314246
1340 09:28:35.314354 RX Delay -111 -> 252, step: 8
1341 09:28:35.314465 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1342 09:28:35.314573 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1343 09:28:35.314685 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1344 09:28:35.314795 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1345 09:28:35.314877 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1346 09:28:35.314929 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1347 09:28:35.314978 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1348 09:28:35.315027 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1349 09:28:35.315076 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1350 09:28:35.315125 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1351 09:28:35.315173 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1352 09:28:35.315222 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1353 09:28:35.315270 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1354 09:28:35.315318 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1355 09:28:35.315367 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1356 09:28:35.315415 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1357 09:28:35.315463 ==
1358 09:28:35.315511 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 09:28:35.315561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 09:28:35.315611 ==
1361 09:28:35.315659 DQS Delay:
1362 09:28:35.315707 DQS0 = 0, DQS1 = 0
1363 09:28:35.315755 DQM Delay:
1364 09:28:35.315802 DQM0 = 79, DQM1 = 69
1365 09:28:35.315850 DQ Delay:
1366 09:28:35.315898 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1367 09:28:35.315947 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =88
1368 09:28:35.315996 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1369 09:28:35.316044 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1370 09:28:35.316092
1371 09:28:35.316139
1372 09:28:35.316187 [DQSOSCAuto] RK1, (LSB)MR18= 0x4722, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1373 09:28:35.316237 CH0 RK1: MR19=606, MR18=4722
1374 09:28:35.316285 CH0_RK1: MR19=0x606, MR18=0x4722, DQSOSC=392, MR23=63, INC=96, DEC=64
1375 09:28:35.316334 [RxdqsGatingPostProcess] freq 800
1376 09:28:35.316383 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 09:28:35.316433 Pre-setting of DQS Precalculation
1378 09:28:35.316481 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 09:28:35.316530 ==
1380 09:28:35.316578 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 09:28:35.316627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 09:28:35.316688 ==
1383 09:28:35.316737 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 09:28:35.316787 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 09:28:35.316835 [CA 0] Center 37 (7~67) winsize 61
1386 09:28:35.316884 [CA 1] Center 36 (6~67) winsize 62
1387 09:28:35.316933 [CA 2] Center 34 (5~64) winsize 60
1388 09:28:35.316981 [CA 3] Center 34 (4~64) winsize 61
1389 09:28:35.317030 [CA 4] Center 34 (4~65) winsize 62
1390 09:28:35.317079 [CA 5] Center 34 (4~64) winsize 61
1391 09:28:35.317133
1392 09:28:35.317181 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1393 09:28:35.317231
1394 09:28:35.317279 [CATrainingPosCal] consider 1 rank data
1395 09:28:35.317328 u2DelayCellTimex100 = 270/100 ps
1396 09:28:35.317377 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1397 09:28:35.317426 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 09:28:35.317475 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1399 09:28:35.317525 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 09:28:35.317573 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 09:28:35.317621 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1402 09:28:35.317669
1403 09:28:35.317717 CA PerBit enable=1, Macro0, CA PI delay=34
1404 09:28:35.317766
1405 09:28:35.317814 [CBTSetCACLKResult] CA Dly = 34
1406 09:28:35.317862 CS Dly: 5 (0~36)
1407 09:28:35.317911 ==
1408 09:28:35.317970 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 09:28:35.318020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 09:28:35.318069 ==
1411 09:28:35.318117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 09:28:35.318166 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 09:28:35.318215 [CA 0] Center 36 (7~66) winsize 60
1414 09:28:35.318264 [CA 1] Center 37 (6~68) winsize 63
1415 09:28:35.318314 [CA 2] Center 34 (4~65) winsize 62
1416 09:28:35.318362 [CA 3] Center 34 (4~64) winsize 61
1417 09:28:35.318410 [CA 4] Center 34 (4~65) winsize 62
1418 09:28:35.318459 [CA 5] Center 33 (3~64) winsize 62
1419 09:28:35.318506
1420 09:28:35.318553 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1421 09:28:35.318602
1422 09:28:35.318650 [CATrainingPosCal] consider 2 rank data
1423 09:28:35.318699 u2DelayCellTimex100 = 270/100 ps
1424 09:28:35.318748 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1425 09:28:35.318797 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 09:28:35.318845 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1427 09:28:35.318894 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 09:28:35.318943 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 09:28:35.318993 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1430 09:28:35.319041
1431 09:28:35.319089 CA PerBit enable=1, Macro0, CA PI delay=34
1432 09:28:35.319138
1433 09:28:35.319187 [CBTSetCACLKResult] CA Dly = 34
1434 09:28:35.319236 CS Dly: 5 (0~37)
1435 09:28:35.319284
1436 09:28:35.319332 ----->DramcWriteLeveling(PI) begin...
1437 09:28:35.319382 ==
1438 09:28:35.319430 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 09:28:35.319485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 09:28:35.319562 ==
1441 09:28:35.319623 Write leveling (Byte 0): 28 => 28
1442 09:28:35.319673 Write leveling (Byte 1): 32 => 32
1443 09:28:35.319723 DramcWriteLeveling(PI) end<-----
1444 09:28:35.319772
1445 09:28:35.319820 ==
1446 09:28:35.319868 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 09:28:35.319917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 09:28:35.319967 ==
1449 09:28:35.320015 [Gating] SW mode calibration
1450 09:28:35.320063 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 09:28:35.320113 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 09:28:35.320162 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 09:28:35.320211 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 09:28:35.320260 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1455 09:28:35.320584 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 09:28:35.320695 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 09:28:35.320771 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 09:28:35.320825 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 09:28:35.320876 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 09:28:35.320926 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 09:28:35.320975 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 09:28:35.321025 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 09:28:35.321074 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 09:28:35.321123 0 7 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1465 09:28:35.321171 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 09:28:35.321220 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 09:28:35.321268 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 09:28:35.321317 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 09:28:35.321365 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1470 09:28:35.321420 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1471 09:28:35.321474 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1472 09:28:35.321523 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 09:28:35.321572 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 09:28:35.321621 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 09:28:35.321669 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 09:28:35.321718 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 09:28:35.321767 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 09:28:35.321815 0 9 8 | B1->B0 | 2424 2323 | 0 1 | (0 0) (1 1)
1479 09:28:35.321864 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1480 09:28:35.321913 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 09:28:35.321962 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 09:28:35.322010 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 09:28:35.322059 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 09:28:35.322108 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 09:28:35.322157 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1486 09:28:35.322206 0 10 8 | B1->B0 | 2c2c 2e2e | 0 0 | (1 0) (1 0)
1487 09:28:35.322254 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 09:28:35.322304 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 09:28:35.322352 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 09:28:35.322401 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 09:28:35.322449 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 09:28:35.322498 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 09:28:35.322547 0 11 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1494 09:28:35.322608 0 11 8 | B1->B0 | 3939 4140 | 1 1 | (0 0) (0 0)
1495 09:28:35.322658 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 09:28:35.322708 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 09:28:35.322757 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 09:28:35.322805 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 09:28:35.322854 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 09:28:35.322902 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 09:28:35.322951 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 09:28:35.323000 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1503 09:28:35.323048 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 09:28:35.323097 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 09:28:35.323145 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 09:28:35.323193 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 09:28:35.323241 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 09:28:35.323289 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 09:28:35.323338 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 09:28:35.323386 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 09:28:35.323434 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 09:28:35.323483 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 09:28:35.323532 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 09:28:35.323580 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 09:28:35.323628 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 09:28:35.323676 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 09:28:35.323724 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 09:28:35.323773 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1519 09:28:35.323822 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 09:28:35.323870 Total UI for P1: 0, mck2ui 16
1521 09:28:35.323920 best dqsien dly found for B0: ( 0, 14, 8)
1522 09:28:35.323969 Total UI for P1: 0, mck2ui 16
1523 09:28:35.324018 best dqsien dly found for B1: ( 0, 14, 8)
1524 09:28:35.324067 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1525 09:28:35.324115 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1526 09:28:35.324163
1527 09:28:35.324211 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1528 09:28:35.324260 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1529 09:28:35.324309 [Gating] SW calibration Done
1530 09:28:35.324356 ==
1531 09:28:35.324404 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 09:28:35.324453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 09:28:35.324502 ==
1534 09:28:35.324550 RX Vref Scan: 0
1535 09:28:35.324597
1536 09:28:35.324654 RX Vref 0 -> 0, step: 1
1537 09:28:35.324705
1538 09:28:35.324754 RX Delay -130 -> 252, step: 16
1539 09:28:35.324803 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1540 09:28:35.324852 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1541 09:28:35.324901 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1542 09:28:35.324950 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1543 09:28:35.324999 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1544 09:28:35.325257 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1545 09:28:35.325353 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1546 09:28:35.325442 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1547 09:28:35.325504 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1548 09:28:35.325555 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1549 09:28:35.325605 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1550 09:28:35.325655 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1551 09:28:35.325705 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1552 09:28:35.325754 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1553 09:28:35.325802 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1554 09:28:35.325851 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1555 09:28:35.325900 ==
1556 09:28:35.325949 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 09:28:35.325999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 09:28:35.326048 ==
1559 09:28:35.326096 DQS Delay:
1560 09:28:35.326145 DQS0 = 0, DQS1 = 0
1561 09:28:35.326195 DQM Delay:
1562 09:28:35.326243 DQM0 = 81, DQM1 = 71
1563 09:28:35.326291 DQ Delay:
1564 09:28:35.326340 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1565 09:28:35.326389 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1566 09:28:35.326438 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1567 09:28:35.326486 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1568 09:28:35.326534
1569 09:28:35.326582
1570 09:28:35.326630 ==
1571 09:28:35.326678 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 09:28:35.326726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 09:28:35.326774 ==
1574 09:28:35.326822
1575 09:28:35.326870
1576 09:28:35.326918 TX Vref Scan disable
1577 09:28:35.326966 == TX Byte 0 ==
1578 09:28:35.327014 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1579 09:28:35.327063 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1580 09:28:35.327111 == TX Byte 1 ==
1581 09:28:35.327160 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1582 09:28:35.327208 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1583 09:28:35.327256 ==
1584 09:28:35.327304 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 09:28:35.327352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 09:28:35.327401 ==
1587 09:28:35.327452 TX Vref=22, minBit 1, minWin=27, winSum=439
1588 09:28:35.327511 TX Vref=24, minBit 1, minWin=26, winSum=440
1589 09:28:35.327561 TX Vref=26, minBit 4, minWin=27, winSum=444
1590 09:28:35.327609 TX Vref=28, minBit 5, minWin=27, winSum=446
1591 09:28:35.327658 TX Vref=30, minBit 6, minWin=27, winSum=448
1592 09:28:35.327707 TX Vref=32, minBit 0, minWin=27, winSum=445
1593 09:28:35.327756 [TxChooseVref] Worse bit 6, Min win 27, Win sum 448, Final Vref 30
1594 09:28:35.327804
1595 09:28:35.327852 Final TX Range 1 Vref 30
1596 09:28:35.327900
1597 09:28:35.327948 ==
1598 09:28:35.327996 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 09:28:35.328045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 09:28:35.328094 ==
1601 09:28:35.328141
1602 09:28:35.328189
1603 09:28:35.328238 TX Vref Scan disable
1604 09:28:35.328287 == TX Byte 0 ==
1605 09:28:35.328337 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1606 09:28:35.328386 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1607 09:28:35.328434 == TX Byte 1 ==
1608 09:28:35.328482 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1609 09:28:35.328531 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1610 09:28:35.328579
1611 09:28:35.328627 [DATLAT]
1612 09:28:35.328685 Freq=800, CH1 RK0
1613 09:28:35.328734
1614 09:28:35.328783 DATLAT Default: 0xa
1615 09:28:35.328832 0, 0xFFFF, sum = 0
1616 09:28:35.328882 1, 0xFFFF, sum = 0
1617 09:28:35.328931 2, 0xFFFF, sum = 0
1618 09:28:35.329002 3, 0xFFFF, sum = 0
1619 09:28:35.329141 4, 0xFFFF, sum = 0
1620 09:28:35.329253 5, 0xFFFF, sum = 0
1621 09:28:35.329346 6, 0xFFFF, sum = 0
1622 09:28:35.329404 7, 0xFFFF, sum = 0
1623 09:28:35.329454 8, 0xFFFF, sum = 0
1624 09:28:35.329504 9, 0x0, sum = 1
1625 09:28:35.329554 10, 0x0, sum = 2
1626 09:28:35.329604 11, 0x0, sum = 3
1627 09:28:35.329654 12, 0x0, sum = 4
1628 09:28:35.329704 best_step = 10
1629 09:28:35.329752
1630 09:28:35.329800 ==
1631 09:28:35.329848 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 09:28:35.329897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 09:28:35.329946 ==
1634 09:28:35.329995 RX Vref Scan: 1
1635 09:28:35.330044
1636 09:28:35.330093 Set Vref Range= 32 -> 127
1637 09:28:35.330141
1638 09:28:35.330189 RX Vref 32 -> 127, step: 1
1639 09:28:35.330238
1640 09:28:35.330286 RX Delay -111 -> 252, step: 8
1641 09:28:35.330334
1642 09:28:35.330381 Set Vref, RX VrefLevel [Byte0]: 32
1643 09:28:35.330430 [Byte1]: 32
1644 09:28:35.330478
1645 09:28:35.330526 Set Vref, RX VrefLevel [Byte0]: 33
1646 09:28:35.330575 [Byte1]: 33
1647 09:28:35.330624
1648 09:28:35.330673 Set Vref, RX VrefLevel [Byte0]: 34
1649 09:28:35.330722 [Byte1]: 34
1650 09:28:35.330770
1651 09:28:35.330818 Set Vref, RX VrefLevel [Byte0]: 35
1652 09:28:35.330879 [Byte1]: 35
1653 09:28:35.330928
1654 09:28:35.330977 Set Vref, RX VrefLevel [Byte0]: 36
1655 09:28:35.331025 [Byte1]: 36
1656 09:28:35.331073
1657 09:28:35.331120 Set Vref, RX VrefLevel [Byte0]: 37
1658 09:28:35.331169 [Byte1]: 37
1659 09:28:35.331217
1660 09:28:35.331265 Set Vref, RX VrefLevel [Byte0]: 38
1661 09:28:35.331313 [Byte1]: 38
1662 09:28:35.331362
1663 09:28:35.331409 Set Vref, RX VrefLevel [Byte0]: 39
1664 09:28:35.331467 [Byte1]: 39
1665 09:28:35.331516
1666 09:28:35.331563 Set Vref, RX VrefLevel [Byte0]: 40
1667 09:28:35.331612 [Byte1]: 40
1668 09:28:35.331660
1669 09:28:35.331707 Set Vref, RX VrefLevel [Byte0]: 41
1670 09:28:35.331756 [Byte1]: 41
1671 09:28:35.331803
1672 09:28:35.331851 Set Vref, RX VrefLevel [Byte0]: 42
1673 09:28:35.331899 [Byte1]: 42
1674 09:28:35.331947
1675 09:28:35.331995 Set Vref, RX VrefLevel [Byte0]: 43
1676 09:28:35.332044 [Byte1]: 43
1677 09:28:35.332092
1678 09:28:35.332140 Set Vref, RX VrefLevel [Byte0]: 44
1679 09:28:35.332188 [Byte1]: 44
1680 09:28:35.332235
1681 09:28:35.332284 Set Vref, RX VrefLevel [Byte0]: 45
1682 09:28:35.332332 [Byte1]: 45
1683 09:28:35.332380
1684 09:28:35.332428 Set Vref, RX VrefLevel [Byte0]: 46
1685 09:28:35.332476 [Byte1]: 46
1686 09:28:35.332524
1687 09:28:35.332572 Set Vref, RX VrefLevel [Byte0]: 47
1688 09:28:35.332620 [Byte1]: 47
1689 09:28:35.332679
1690 09:28:35.332729 Set Vref, RX VrefLevel [Byte0]: 48
1691 09:28:35.332778 [Byte1]: 48
1692 09:28:35.332826
1693 09:28:35.332874 Set Vref, RX VrefLevel [Byte0]: 49
1694 09:28:35.332922 [Byte1]: 49
1695 09:28:35.332970
1696 09:28:35.333019 Set Vref, RX VrefLevel [Byte0]: 50
1697 09:28:35.333067 [Byte1]: 50
1698 09:28:35.333116
1699 09:28:35.333164 Set Vref, RX VrefLevel [Byte0]: 51
1700 09:28:35.333212 [Byte1]: 51
1701 09:28:35.333259
1702 09:28:35.333307 Set Vref, RX VrefLevel [Byte0]: 52
1703 09:28:35.333358 [Byte1]: 52
1704 09:28:35.333407
1705 09:28:35.333650 Set Vref, RX VrefLevel [Byte0]: 53
1706 09:28:35.333705 [Byte1]: 53
1707 09:28:35.333754
1708 09:28:35.333803 Set Vref, RX VrefLevel [Byte0]: 54
1709 09:28:35.333852 [Byte1]: 54
1710 09:28:35.333900
1711 09:28:35.333948 Set Vref, RX VrefLevel [Byte0]: 55
1712 09:28:35.333996 [Byte1]: 55
1713 09:28:35.334045
1714 09:28:35.334093 Set Vref, RX VrefLevel [Byte0]: 56
1715 09:28:35.334141 [Byte1]: 56
1716 09:28:35.334189
1717 09:28:35.334238 Set Vref, RX VrefLevel [Byte0]: 57
1718 09:28:35.334286 [Byte1]: 57
1719 09:28:35.334335
1720 09:28:35.334382 Set Vref, RX VrefLevel [Byte0]: 58
1721 09:28:35.334430 [Byte1]: 58
1722 09:28:35.334478
1723 09:28:35.334526 Set Vref, RX VrefLevel [Byte0]: 59
1724 09:28:35.334576 [Byte1]: 59
1725 09:28:35.334624
1726 09:28:35.334673 Set Vref, RX VrefLevel [Byte0]: 60
1727 09:28:35.334721 [Byte1]: 60
1728 09:28:35.334769
1729 09:28:35.334817 Set Vref, RX VrefLevel [Byte0]: 61
1730 09:28:35.334865 [Byte1]: 61
1731 09:28:35.334913
1732 09:28:35.334961 Set Vref, RX VrefLevel [Byte0]: 62
1733 09:28:35.335010 [Byte1]: 62
1734 09:28:35.335060
1735 09:28:35.335108 Set Vref, RX VrefLevel [Byte0]: 63
1736 09:28:35.335156 [Byte1]: 63
1737 09:28:35.335204
1738 09:28:35.335252 Set Vref, RX VrefLevel [Byte0]: 64
1739 09:28:35.335308 [Byte1]: 64
1740 09:28:35.335356
1741 09:28:35.335404 Set Vref, RX VrefLevel [Byte0]: 65
1742 09:28:35.335453 [Byte1]: 65
1743 09:28:35.335501
1744 09:28:35.335549 Set Vref, RX VrefLevel [Byte0]: 66
1745 09:28:35.335598 [Byte1]: 66
1746 09:28:35.335647
1747 09:28:35.335695 Set Vref, RX VrefLevel [Byte0]: 67
1748 09:28:35.335743 [Byte1]: 67
1749 09:28:35.335791
1750 09:28:35.335838 Set Vref, RX VrefLevel [Byte0]: 68
1751 09:28:35.335887 [Byte1]: 68
1752 09:28:35.335934
1753 09:28:35.335982 Set Vref, RX VrefLevel [Byte0]: 69
1754 09:28:35.336030 [Byte1]: 69
1755 09:28:35.336077
1756 09:28:35.336125 Set Vref, RX VrefLevel [Byte0]: 70
1757 09:28:35.336173 [Byte1]: 70
1758 09:28:35.336222
1759 09:28:35.336270 Set Vref, RX VrefLevel [Byte0]: 71
1760 09:28:35.336318 [Byte1]: 71
1761 09:28:35.336365
1762 09:28:35.336412 Set Vref, RX VrefLevel [Byte0]: 72
1763 09:28:35.336461 [Byte1]: 72
1764 09:28:35.336509
1765 09:28:35.336558 Set Vref, RX VrefLevel [Byte0]: 73
1766 09:28:35.336607 [Byte1]: 73
1767 09:28:35.336665
1768 09:28:35.336714 Set Vref, RX VrefLevel [Byte0]: 74
1769 09:28:35.336763 [Byte1]: 74
1770 09:28:35.336811
1771 09:28:35.336859 Set Vref, RX VrefLevel [Byte0]: 75
1772 09:28:35.336908 [Byte1]: 75
1773 09:28:35.336957
1774 09:28:35.337006 Set Vref, RX VrefLevel [Byte0]: 76
1775 09:28:35.337055 [Byte1]: 76
1776 09:28:35.337104
1777 09:28:35.337152 Final RX Vref Byte 0 = 57 to rank0
1778 09:28:35.337200 Final RX Vref Byte 1 = 56 to rank0
1779 09:28:35.337250 Final RX Vref Byte 0 = 57 to rank1
1780 09:28:35.337298 Final RX Vref Byte 1 = 56 to rank1==
1781 09:28:35.337346 Dram Type= 6, Freq= 0, CH_1, rank 0
1782 09:28:35.337395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 09:28:35.337445 ==
1784 09:28:35.337493 DQS Delay:
1785 09:28:35.337541 DQS0 = 0, DQS1 = 0
1786 09:28:35.337590 DQM Delay:
1787 09:28:35.337638 DQM0 = 81, DQM1 = 72
1788 09:28:35.337686 DQ Delay:
1789 09:28:35.337734 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1790 09:28:35.337782 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1791 09:28:35.337830 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1792 09:28:35.337878 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1793 09:28:35.337926
1794 09:28:35.337974
1795 09:28:35.338021 [DQSOSCAuto] RK0, (LSB)MR18= 0x1721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1796 09:28:35.338071 CH1 RK0: MR19=606, MR18=1721
1797 09:28:35.338120 CH1_RK0: MR19=0x606, MR18=0x1721, DQSOSC=401, MR23=63, INC=91, DEC=61
1798 09:28:35.338168
1799 09:28:35.338216 ----->DramcWriteLeveling(PI) begin...
1800 09:28:35.338266 ==
1801 09:28:35.338315 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 09:28:35.338364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 09:28:35.338413 ==
1804 09:28:35.338461 Write leveling (Byte 0): 28 => 28
1805 09:28:35.338509 Write leveling (Byte 1): 29 => 29
1806 09:28:35.338558 DramcWriteLeveling(PI) end<-----
1807 09:28:35.338606
1808 09:28:35.338653 ==
1809 09:28:35.338700 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 09:28:35.338748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 09:28:35.338797 ==
1812 09:28:35.338845 [Gating] SW mode calibration
1813 09:28:35.338894 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1814 09:28:35.338943 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1815 09:28:35.338993 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1816 09:28:35.339046 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1817 09:28:35.339108 0 6 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1818 09:28:35.339159 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 09:28:35.339207 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 09:28:35.339256 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 09:28:35.339304 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 09:28:35.339353 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 09:28:35.339401 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 09:28:35.339459 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 09:28:35.339509 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 09:28:35.339557 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 09:28:35.339606 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 09:28:35.339655 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 09:28:35.339704 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 09:28:35.339752 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 09:28:35.339800 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 09:28:35.339849 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1833 09:28:35.339897 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1834 09:28:35.339945 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 09:28:35.339994 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 09:28:35.340236 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 09:28:35.340294 0 8 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1838 09:28:35.340344 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 09:28:35.340393 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 09:28:35.340442 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1841 09:28:35.340491 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1842 09:28:35.340541 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 09:28:35.340590 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 09:28:35.340639 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 09:28:35.340699 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 09:28:35.340749 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 09:28:35.340797 0 10 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1848 09:28:35.340847 0 10 4 | B1->B0 | 3030 2e2e | 1 1 | (1 1) (1 0)
1849 09:28:35.340897 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1850 09:28:35.340946 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 09:28:35.340995 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 09:28:35.341043 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 09:28:35.341092 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 09:28:35.341141 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 09:28:35.341190 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1856 09:28:35.341239 0 11 4 | B1->B0 | 2828 3939 | 0 0 | (0 0) (0 0)
1857 09:28:35.341288 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1858 09:28:35.341336 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 09:28:35.341385 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 09:28:35.341433 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 09:28:35.341481 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 09:28:35.341529 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 09:28:35.341578 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 09:28:35.341626 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1865 09:28:35.341675 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1866 09:28:35.341723 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 09:28:35.341772 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 09:28:35.341821 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 09:28:35.341870 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 09:28:35.341919 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 09:28:35.341968 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 09:28:35.342017 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 09:28:35.342065 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 09:28:35.342113 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 09:28:35.342161 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 09:28:35.342209 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 09:28:35.342258 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 09:28:35.342306 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 09:28:35.342354 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 09:28:35.342403 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1881 09:28:35.342452 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 09:28:35.342501 Total UI for P1: 0, mck2ui 16
1883 09:28:35.342550 best dqsien dly found for B0: ( 0, 14, 4)
1884 09:28:35.342599 Total UI for P1: 0, mck2ui 16
1885 09:28:35.342648 best dqsien dly found for B1: ( 0, 14, 6)
1886 09:28:35.342696 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1887 09:28:35.342745 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1888 09:28:35.342794
1889 09:28:35.342842 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1890 09:28:35.342891 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1891 09:28:35.342939 [Gating] SW calibration Done
1892 09:28:35.342988 ==
1893 09:28:35.343036 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 09:28:35.343085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1895 09:28:35.343134 ==
1896 09:28:35.343183 RX Vref Scan: 0
1897 09:28:35.343232
1898 09:28:35.343280 RX Vref 0 -> 0, step: 1
1899 09:28:35.343328
1900 09:28:35.343375 RX Delay -130 -> 252, step: 16
1901 09:28:35.343424 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1902 09:28:35.343473 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1903 09:28:35.343522 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1904 09:28:35.343571 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1905 09:28:35.343620 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1906 09:28:35.343667 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1907 09:28:35.343716 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1908 09:28:35.343765 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1909 09:28:35.343813 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1910 09:28:35.343860 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1911 09:28:35.343908 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1912 09:28:35.343956 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1913 09:28:35.344005 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1914 09:28:35.344054 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1915 09:28:35.344102 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1916 09:28:35.344150 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1917 09:28:35.344198 ==
1918 09:28:35.344246 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 09:28:35.509786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 09:28:35.509924 ==
1921 09:28:35.509997 DQS Delay:
1922 09:28:35.510066 DQS0 = 0, DQS1 = 0
1923 09:28:35.510120 DQM Delay:
1924 09:28:35.510172 DQM0 = 80, DQM1 = 71
1925 09:28:35.510223 DQ Delay:
1926 09:28:35.510285 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1927 09:28:35.510353 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1928 09:28:35.510419 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1929 09:28:35.510497 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1930 09:28:35.510598
1931 09:28:35.510704
1932 09:28:35.510781 ==
1933 09:28:35.510858 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 09:28:35.510911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 09:28:35.510960 ==
1936 09:28:35.511008
1937 09:28:35.511056
1938 09:28:35.511104 TX Vref Scan disable
1939 09:28:35.511153 == TX Byte 0 ==
1940 09:28:35.511201 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1941 09:28:35.511447 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1942 09:28:35.511529 == TX Byte 1 ==
1943 09:28:35.511578 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1944 09:28:35.511627 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1945 09:28:35.511686 ==
1946 09:28:35.511736 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 09:28:35.511784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 09:28:35.511832 ==
1949 09:28:35.511882 TX Vref=22, minBit 6, minWin=27, winSum=449
1950 09:28:35.511945 TX Vref=24, minBit 1, minWin=27, winSum=452
1951 09:28:35.511994 TX Vref=26, minBit 0, minWin=28, winSum=455
1952 09:28:35.512042 TX Vref=28, minBit 0, minWin=28, winSum=459
1953 09:28:35.512090 TX Vref=30, minBit 0, minWin=28, winSum=459
1954 09:28:35.512138 TX Vref=32, minBit 5, minWin=27, winSum=461
1955 09:28:35.512186 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
1956 09:28:35.512234
1957 09:28:35.512282 Final TX Range 1 Vref 28
1958 09:28:35.512330
1959 09:28:35.512376 ==
1960 09:28:35.512441 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 09:28:35.512491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 09:28:35.512539 ==
1963 09:28:35.512586
1964 09:28:35.512633
1965 09:28:35.512718 TX Vref Scan disable
1966 09:28:35.512780 == TX Byte 0 ==
1967 09:28:35.512841 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1968 09:28:35.512889 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1969 09:28:35.512953 == TX Byte 1 ==
1970 09:28:35.513001 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1971 09:28:35.513050 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1972 09:28:35.513097
1973 09:28:35.513145 [DATLAT]
1974 09:28:35.513193 Freq=800, CH1 RK1
1975 09:28:35.513241
1976 09:28:35.513289 DATLAT Default: 0xa
1977 09:28:35.513337 0, 0xFFFF, sum = 0
1978 09:28:35.513388 1, 0xFFFF, sum = 0
1979 09:28:35.513474 2, 0xFFFF, sum = 0
1980 09:28:35.513552 3, 0xFFFF, sum = 0
1981 09:28:35.513629 4, 0xFFFF, sum = 0
1982 09:28:35.513701 5, 0xFFFF, sum = 0
1983 09:28:35.513751 6, 0xFFFF, sum = 0
1984 09:28:35.513800 7, 0xFFFF, sum = 0
1985 09:28:35.513848 8, 0xFFFF, sum = 0
1986 09:28:35.513908 9, 0x0, sum = 1
1987 09:28:35.513960 10, 0x0, sum = 2
1988 09:28:35.514009 11, 0x0, sum = 3
1989 09:28:35.514058 12, 0x0, sum = 4
1990 09:28:35.514106 best_step = 10
1991 09:28:35.514153
1992 09:28:35.514200 ==
1993 09:28:35.514247 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 09:28:35.514295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 09:28:35.514372 ==
1996 09:28:35.514438 RX Vref Scan: 0
1997 09:28:35.514504
1998 09:28:35.514565 RX Vref 0 -> 0, step: 1
1999 09:28:35.514613
2000 09:28:35.514659 RX Delay -111 -> 252, step: 8
2001 09:28:35.514707 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2002 09:28:35.514754 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2003 09:28:35.514801 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2004 09:28:35.514876 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2005 09:28:35.514935 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2006 09:28:35.515001 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2007 09:28:35.515109 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2008 09:28:35.515187 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2009 09:28:35.515265 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2010 09:28:35.515339 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2011 09:28:35.515412 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2012 09:28:35.515485 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2013 09:28:35.515557 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2014 09:28:35.515626 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2015 09:28:35.515677 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2016 09:28:35.515740 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2017 09:28:35.515810 ==
2018 09:28:35.515859 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 09:28:35.515908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 09:28:35.515957 ==
2021 09:28:35.516006 DQS Delay:
2022 09:28:35.516054 DQS0 = 0, DQS1 = 0
2023 09:28:35.516102 DQM Delay:
2024 09:28:35.516149 DQM0 = 77, DQM1 = 73
2025 09:28:35.516197 DQ Delay:
2026 09:28:35.516245 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2027 09:28:35.516294 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2028 09:28:35.516342 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2029 09:28:35.516390 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2030 09:28:35.516438
2031 09:28:35.516495
2032 09:28:35.516577 [DQSOSCAuto] RK1, (LSB)MR18= 0x2239, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2033 09:28:35.516674 CH1 RK1: MR19=606, MR18=2239
2034 09:28:35.516761 CH1_RK1: MR19=0x606, MR18=0x2239, DQSOSC=395, MR23=63, INC=94, DEC=63
2035 09:28:35.516824 [RxdqsGatingPostProcess] freq 800
2036 09:28:35.516873 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2037 09:28:35.516923 Pre-setting of DQS Precalculation
2038 09:28:35.516972 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2039 09:28:35.517050 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2040 09:28:35.517129 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2041 09:28:35.517205
2042 09:28:35.517280
2043 09:28:35.517355 [Calibration Summary] 1600 Mbps
2044 09:28:35.517431 CH 0, Rank 0
2045 09:28:35.517516 SW Impedance : PASS
2046 09:28:35.517571 DUTY Scan : NO K
2047 09:28:35.517621 ZQ Calibration : PASS
2048 09:28:35.517669 Jitter Meter : NO K
2049 09:28:35.517717 CBT Training : PASS
2050 09:28:35.517788 Write leveling : PASS
2051 09:28:35.517849 RX DQS gating : PASS
2052 09:28:35.517897 RX DQ/DQS(RDDQC) : PASS
2053 09:28:35.517945 TX DQ/DQS : PASS
2054 09:28:35.518000 RX DATLAT : PASS
2055 09:28:35.518080 RX DQ/DQS(Engine): PASS
2056 09:28:35.518156 TX OE : NO K
2057 09:28:35.518231 All Pass.
2058 09:28:35.518282
2059 09:28:35.518330 CH 0, Rank 1
2060 09:28:35.518380 SW Impedance : PASS
2061 09:28:35.518429 DUTY Scan : NO K
2062 09:28:35.518477 ZQ Calibration : PASS
2063 09:28:35.518576 Jitter Meter : NO K
2064 09:28:35.518625 CBT Training : PASS
2065 09:28:35.518673 Write leveling : PASS
2066 09:28:35.518749 RX DQS gating : PASS
2067 09:28:35.518845 RX DQ/DQS(RDDQC) : PASS
2068 09:28:35.518923 TX DQ/DQS : PASS
2069 09:28:35.519003 RX DATLAT : PASS
2070 09:28:35.519114 RX DQ/DQS(Engine): PASS
2071 09:28:35.519171 TX OE : NO K
2072 09:28:35.519220 All Pass.
2073 09:28:35.519269
2074 09:28:35.519317 CH 1, Rank 0
2075 09:28:35.519365 SW Impedance : PASS
2076 09:28:35.519413 DUTY Scan : NO K
2077 09:28:35.519461 ZQ Calibration : PASS
2078 09:28:35.519509 Jitter Meter : NO K
2079 09:28:35.519557 CBT Training : PASS
2080 09:28:35.519605 Write leveling : PASS
2081 09:28:35.519666 RX DQS gating : PASS
2082 09:28:35.519728 RX DQ/DQS(RDDQC) : PASS
2083 09:28:35.519776 TX DQ/DQS : PASS
2084 09:28:35.519824 RX DATLAT : PASS
2085 09:28:35.519871 RX DQ/DQS(Engine): PASS
2086 09:28:35.519919 TX OE : NO K
2087 09:28:35.520162 All Pass.
2088 09:28:35.520230
2089 09:28:35.520280 CH 1, Rank 1
2090 09:28:35.520328 SW Impedance : PASS
2091 09:28:35.520391 DUTY Scan : NO K
2092 09:28:35.520438 ZQ Calibration : PASS
2093 09:28:35.520501 Jitter Meter : NO K
2094 09:28:35.520550 CBT Training : PASS
2095 09:28:35.520598 Write leveling : PASS
2096 09:28:35.520656 RX DQS gating : PASS
2097 09:28:35.520736 RX DQ/DQS(RDDQC) : PASS
2098 09:28:35.520798 TX DQ/DQS : PASS
2099 09:28:35.520845 RX DATLAT : PASS
2100 09:28:35.520920 RX DQ/DQS(Engine): PASS
2101 09:28:35.520969 TX OE : NO K
2102 09:28:35.521017 All Pass.
2103 09:28:35.521065
2104 09:28:35.521112 DramC Write-DBI off
2105 09:28:35.521160 PER_BANK_REFRESH: Hybrid Mode
2106 09:28:35.521208 TX_TRACKING: ON
2107 09:28:35.521302 [GetDramInforAfterCalByMRR] Vendor 6.
2108 09:28:35.521354 [GetDramInforAfterCalByMRR] Revision 606.
2109 09:28:35.521416 [GetDramInforAfterCalByMRR] Revision 2 0.
2110 09:28:35.521480 MR0 0x3b3b
2111 09:28:35.521557 MR8 0x5151
2112 09:28:35.521651 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 09:28:35.521701
2114 09:28:35.521770 MR0 0x3b3b
2115 09:28:35.521840 MR8 0x5151
2116 09:28:35.521903 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 09:28:35.521951
2118 09:28:35.521999 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2119 09:28:35.522049 [FAST_K] Save calibration result to emmc
2120 09:28:35.522097 [FAST_K] Save calibration result to emmc
2121 09:28:35.522174 dram_init: config_dvfs: 1
2122 09:28:35.522222 dramc_set_vcore_voltage set vcore to 662500
2123 09:28:35.522281 Read voltage for 1200, 2
2124 09:28:35.522333 Vio18 = 0
2125 09:28:35.522381 Vcore = 662500
2126 09:28:35.522429 Vdram = 0
2127 09:28:35.522492 Vddq = 0
2128 09:28:35.522554 Vmddr = 0
2129 09:28:35.522603 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2130 09:28:35.522651 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2131 09:28:35.522700 MEM_TYPE=3, freq_sel=15
2132 09:28:35.522749 sv_algorithm_assistance_LP4_1600
2133 09:28:35.522831 ============ PULL DRAM RESETB DOWN ============
2134 09:28:35.522897 ========== PULL DRAM RESETB DOWN end =========
2135 09:28:35.522946 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2136 09:28:35.522995 ===================================
2137 09:28:35.523043 LPDDR4 DRAM CONFIGURATION
2138 09:28:35.523091 ===================================
2139 09:28:35.523140 EX_ROW_EN[0] = 0x0
2140 09:28:35.523188 EX_ROW_EN[1] = 0x0
2141 09:28:35.523236 LP4Y_EN = 0x0
2142 09:28:35.523284 WORK_FSP = 0x0
2143 09:28:35.523348 WL = 0x4
2144 09:28:35.523440 RL = 0x4
2145 09:28:35.523502 BL = 0x2
2146 09:28:35.523550 RPST = 0x0
2147 09:28:35.523597 RD_PRE = 0x0
2148 09:28:35.523644 WR_PRE = 0x1
2149 09:28:35.523692 WR_PST = 0x0
2150 09:28:35.523740 DBI_WR = 0x0
2151 09:28:35.523788 DBI_RD = 0x0
2152 09:28:35.523854 OTF = 0x1
2153 09:28:35.523904 ===================================
2154 09:28:35.523954 ===================================
2155 09:28:35.524002 ANA top config
2156 09:28:35.524049 ===================================
2157 09:28:35.524098 DLL_ASYNC_EN = 0
2158 09:28:35.524146 ALL_SLAVE_EN = 0
2159 09:28:35.524243 NEW_RANK_MODE = 1
2160 09:28:35.524309 DLL_IDLE_MODE = 1
2161 09:28:35.524408 LP45_APHY_COMB_EN = 1
2162 09:28:35.524481 TX_ODT_DIS = 1
2163 09:28:35.524563 NEW_8X_MODE = 1
2164 09:28:35.524666 ===================================
2165 09:28:35.524771 ===================================
2166 09:28:35.524872 data_rate = 2400
2167 09:28:35.524958 CKR = 1
2168 09:28:35.525057 DQ_P2S_RATIO = 8
2169 09:28:35.525131 ===================================
2170 09:28:35.525183 CA_P2S_RATIO = 8
2171 09:28:35.525234 DQ_CA_OPEN = 0
2172 09:28:35.525298 DQ_SEMI_OPEN = 0
2173 09:28:35.525375 CA_SEMI_OPEN = 0
2174 09:28:35.525424 CA_FULL_RATE = 0
2175 09:28:35.525473 DQ_CKDIV4_EN = 0
2176 09:28:35.525536 CA_CKDIV4_EN = 0
2177 09:28:35.525590 CA_PREDIV_EN = 0
2178 09:28:35.525648 PH8_DLY = 17
2179 09:28:35.525711 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2180 09:28:35.525801 DQ_AAMCK_DIV = 4
2181 09:28:35.525850 CA_AAMCK_DIV = 4
2182 09:28:35.525899 CA_ADMCK_DIV = 4
2183 09:28:35.525946 DQ_TRACK_CA_EN = 0
2184 09:28:35.525994 CA_PICK = 1200
2185 09:28:35.526043 CA_MCKIO = 1200
2186 09:28:35.526092 MCKIO_SEMI = 0
2187 09:28:35.526187 PLL_FREQ = 2366
2188 09:28:35.526263 DQ_UI_PI_RATIO = 32
2189 09:28:35.526311 CA_UI_PI_RATIO = 0
2190 09:28:35.526360 ===================================
2191 09:28:35.526436 ===================================
2192 09:28:35.526484 memory_type:LPDDR4
2193 09:28:35.526533 GP_NUM : 10
2194 09:28:35.526581 SRAM_EN : 1
2195 09:28:35.526647 MD32_EN : 0
2196 09:28:35.526733 ===================================
2197 09:28:35.526797 [ANA_INIT] >>>>>>>>>>>>>>
2198 09:28:35.526846 <<<<<< [CONFIGURE PHASE]: ANA_TX
2199 09:28:35.526896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2200 09:28:35.526944 ===================================
2201 09:28:35.527021 data_rate = 2400,PCW = 0X5b00
2202 09:28:35.527087 ===================================
2203 09:28:35.527184 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2204 09:28:35.527294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 09:28:35.527371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 09:28:35.527426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2207 09:28:35.527491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2208 09:28:35.527542 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2209 09:28:35.527591 [ANA_INIT] flow start
2210 09:28:35.527641 [ANA_INIT] PLL >>>>>>>>
2211 09:28:35.527689 [ANA_INIT] PLL <<<<<<<<
2212 09:28:35.527767 [ANA_INIT] MIDPI >>>>>>>>
2213 09:28:35.527817 [ANA_INIT] MIDPI <<<<<<<<
2214 09:28:35.527865 [ANA_INIT] DLL >>>>>>>>
2215 09:28:35.527913 [ANA_INIT] DLL <<<<<<<<
2216 09:28:35.527993 [ANA_INIT] flow end
2217 09:28:35.528057 ============ LP4 DIFF to SE enter ============
2218 09:28:35.528106 ============ LP4 DIFF to SE exit ============
2219 09:28:35.528154 [ANA_INIT] <<<<<<<<<<<<<
2220 09:28:35.528229 [Flow] Enable top DCM control >>>>>
2221 09:28:35.528308 [Flow] Enable top DCM control <<<<<
2222 09:28:35.528554 Enable DLL master slave shuffle
2223 09:28:35.528637 ==============================================================
2224 09:28:35.528715 Gating Mode config
2225 09:28:35.528765 ==============================================================
2226 09:28:35.528832 Config description:
2227 09:28:35.528882 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2228 09:28:35.528933 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2229 09:28:35.529001 SELPH_MODE 0: By rank 1: By Phase
2230 09:28:35.529052 ==============================================================
2231 09:28:35.529102 GAT_TRACK_EN = 1
2232 09:28:35.529151 RX_GATING_MODE = 2
2233 09:28:35.529199 RX_GATING_TRACK_MODE = 2
2234 09:28:35.529247 SELPH_MODE = 1
2235 09:28:35.529296 PICG_EARLY_EN = 1
2236 09:28:35.529358 VALID_LAT_VALUE = 1
2237 09:28:35.529408 ==============================================================
2238 09:28:35.529457 Enter into Gating configuration >>>>
2239 09:28:35.529522 Exit from Gating configuration <<<<
2240 09:28:35.529572 Enter into DVFS_PRE_config >>>>>
2241 09:28:35.529651 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2242 09:28:35.529700 Exit from DVFS_PRE_config <<<<<
2243 09:28:35.529748 Enter into PICG configuration >>>>
2244 09:28:35.529797 Exit from PICG configuration <<<<
2245 09:28:35.529846 [RX_INPUT] configuration >>>>>
2246 09:28:35.529907 [RX_INPUT] configuration <<<<<
2247 09:28:35.529956 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2248 09:28:35.530041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2249 09:28:35.530108 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 09:28:35.530196 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 09:28:35.530244 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 09:28:35.530292 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 09:28:35.530340 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2254 09:28:35.530389 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2255 09:28:35.530452 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2256 09:28:35.530533 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2257 09:28:35.530598 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2258 09:28:35.530646 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2259 09:28:35.530695 ===================================
2260 09:28:35.530757 LPDDR4 DRAM CONFIGURATION
2261 09:28:35.530819 ===================================
2262 09:28:35.530881 EX_ROW_EN[0] = 0x0
2263 09:28:35.530953 EX_ROW_EN[1] = 0x0
2264 09:28:35.531033 LP4Y_EN = 0x0
2265 09:28:35.531085 WORK_FSP = 0x0
2266 09:28:35.531135 WL = 0x4
2267 09:28:35.531183 RL = 0x4
2268 09:28:35.531245 BL = 0x2
2269 09:28:35.531293 RPST = 0x0
2270 09:28:35.531341 RD_PRE = 0x0
2271 09:28:35.531403 WR_PRE = 0x1
2272 09:28:35.531465 WR_PST = 0x0
2273 09:28:35.531558 DBI_WR = 0x0
2274 09:28:35.531608 DBI_RD = 0x0
2275 09:28:35.531657 OTF = 0x1
2276 09:28:35.531705 ===================================
2277 09:28:35.531769 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2278 09:28:35.531832 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2279 09:28:35.531880 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2280 09:28:35.531929 ===================================
2281 09:28:35.531977 LPDDR4 DRAM CONFIGURATION
2282 09:28:35.532071 ===================================
2283 09:28:35.532136 EX_ROW_EN[0] = 0x10
2284 09:28:35.532198 EX_ROW_EN[1] = 0x0
2285 09:28:35.532246 LP4Y_EN = 0x0
2286 09:28:35.532294 WORK_FSP = 0x0
2287 09:28:35.532342 WL = 0x4
2288 09:28:35.532390 RL = 0x4
2289 09:28:35.532438 BL = 0x2
2290 09:28:35.532500 RPST = 0x0
2291 09:28:35.532552 RD_PRE = 0x0
2292 09:28:35.532637 WR_PRE = 0x1
2293 09:28:35.532711 WR_PST = 0x0
2294 09:28:35.532774 DBI_WR = 0x0
2295 09:28:35.532835 DBI_RD = 0x0
2296 09:28:35.532881 OTF = 0x1
2297 09:28:35.532930 ===================================
2298 09:28:35.532992 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2299 09:28:35.533042 ==
2300 09:28:35.533094 Dram Type= 6, Freq= 0, CH_0, rank 0
2301 09:28:35.533155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2302 09:28:35.533218 ==
2303 09:28:35.533265 [Duty_Offset_Calibration]
2304 09:28:35.533312 B0:2 B1:0 CA:3
2305 09:28:35.533372
2306 09:28:35.533434 [DutyScan_Calibration_Flow] k_type=0
2307 09:28:35.533510
2308 09:28:35.533557 ==CLK 0==
2309 09:28:35.533605 Final CLK duty delay cell = 0
2310 09:28:35.533668 [0] MAX Duty = 5062%(X100), DQS PI = 20
2311 09:28:35.533735 [0] MIN Duty = 4875%(X100), DQS PI = 58
2312 09:28:35.533798 [0] AVG Duty = 4968%(X100)
2313 09:28:35.533846
2314 09:28:35.533893 CH0 CLK Duty spec in!! Max-Min= 187%
2315 09:28:35.533955 [DutyScan_Calibration_Flow] ====Done====
2316 09:28:35.534016
2317 09:28:35.534101 [DutyScan_Calibration_Flow] k_type=1
2318 09:28:35.534149
2319 09:28:35.534252 ==DQS 0 ==
2320 09:28:35.534329 Final DQS duty delay cell = 0
2321 09:28:35.534406 [0] MAX Duty = 5062%(X100), DQS PI = 16
2322 09:28:35.534481 [0] MIN Duty = 4907%(X100), DQS PI = 44
2323 09:28:35.534553 [0] AVG Duty = 4984%(X100)
2324 09:28:35.534659
2325 09:28:35.534731 ==DQS 1 ==
2326 09:28:35.534797 Final DQS duty delay cell = -4
2327 09:28:35.534848 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2328 09:28:35.534896 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2329 09:28:35.534944 [-4] AVG Duty = 4922%(X100)
2330 09:28:35.534992
2331 09:28:35.535056 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2332 09:28:35.535139
2333 09:28:35.535234 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2334 09:28:35.535312 [DutyScan_Calibration_Flow] ====Done====
2335 09:28:35.535386
2336 09:28:35.535450 [DutyScan_Calibration_Flow] k_type=3
2337 09:28:35.535501
2338 09:28:35.535548 ==DQM 0 ==
2339 09:28:35.535597 Final DQM duty delay cell = 0
2340 09:28:35.535659 [0] MAX Duty = 5124%(X100), DQS PI = 28
2341 09:28:35.535721 [0] MIN Duty = 4876%(X100), DQS PI = 0
2342 09:28:35.535768 [0] AVG Duty = 5000%(X100)
2343 09:28:35.535815
2344 09:28:35.535862 ==DQM 1 ==
2345 09:28:35.535909 Final DQM duty delay cell = 4
2346 09:28:35.536148 [4] MAX Duty = 5124%(X100), DQS PI = 52
2347 09:28:35.536200 [4] MIN Duty = 5000%(X100), DQS PI = 12
2348 09:28:35.536249 [4] AVG Duty = 5062%(X100)
2349 09:28:35.536297
2350 09:28:35.536345 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2351 09:28:35.536392
2352 09:28:35.536439 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2353 09:28:35.536488 [DutyScan_Calibration_Flow] ====Done====
2354 09:28:35.536535
2355 09:28:35.536582 [DutyScan_Calibration_Flow] k_type=2
2356 09:28:35.536629
2357 09:28:35.536717 ==DQ 0 ==
2358 09:28:35.536765 Final DQ duty delay cell = -4
2359 09:28:35.536813 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2360 09:28:35.536861 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2361 09:28:35.536909 [-4] AVG Duty = 4953%(X100)
2362 09:28:35.536957
2363 09:28:35.537003 ==DQ 1 ==
2364 09:28:35.537050 Final DQ duty delay cell = -4
2365 09:28:35.537097 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2366 09:28:35.537175 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2367 09:28:35.537223 [-4] AVG Duty = 4938%(X100)
2368 09:28:35.537273
2369 09:28:35.537321 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2370 09:28:35.537368
2371 09:28:35.537415 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2372 09:28:35.537463 [DutyScan_Calibration_Flow] ====Done====
2373 09:28:35.537510 ==
2374 09:28:35.537557 Dram Type= 6, Freq= 0, CH_1, rank 0
2375 09:28:35.537604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 09:28:35.537652 ==
2377 09:28:35.537699 [Duty_Offset_Calibration]
2378 09:28:35.537746 B0:1 B1:-2 CA:0
2379 09:28:35.537794
2380 09:28:35.537858 [DutyScan_Calibration_Flow] k_type=0
2381 09:28:35.537921
2382 09:28:35.537969 ==CLK 0==
2383 09:28:35.538016 Final CLK duty delay cell = 0
2384 09:28:35.538063 [0] MAX Duty = 5031%(X100), DQS PI = 16
2385 09:28:35.538109 [0] MIN Duty = 4844%(X100), DQS PI = 58
2386 09:28:35.538157 [0] AVG Duty = 4937%(X100)
2387 09:28:35.538205
2388 09:28:35.538252 CH1 CLK Duty spec in!! Max-Min= 187%
2389 09:28:35.538299 [DutyScan_Calibration_Flow] ====Done====
2390 09:28:35.538365
2391 09:28:35.538452 [DutyScan_Calibration_Flow] k_type=1
2392 09:28:35.538518
2393 09:28:35.538569 ==DQS 0 ==
2394 09:28:35.538620 Final DQS duty delay cell = -4
2395 09:28:35.538672 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2396 09:28:35.538720 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2397 09:28:35.538768 [-4] AVG Duty = 4938%(X100)
2398 09:28:35.538815
2399 09:28:35.538872 ==DQS 1 ==
2400 09:28:35.538923 Final DQS duty delay cell = 0
2401 09:28:35.538987 [0] MAX Duty = 5062%(X100), DQS PI = 0
2402 09:28:35.539052 [0] MIN Duty = 4875%(X100), DQS PI = 26
2403 09:28:35.539101 [0] AVG Duty = 4968%(X100)
2404 09:28:35.539148
2405 09:28:35.539199 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2406 09:28:35.539252
2407 09:28:35.539313 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2408 09:28:35.539377 [DutyScan_Calibration_Flow] ====Done====
2409 09:28:35.539426
2410 09:28:35.539472 [DutyScan_Calibration_Flow] k_type=3
2411 09:28:35.539520
2412 09:28:35.539586 ==DQM 0 ==
2413 09:28:35.539650 Final DQM duty delay cell = 0
2414 09:28:35.539698 [0] MAX Duty = 5000%(X100), DQS PI = 22
2415 09:28:35.539747 [0] MIN Duty = 4844%(X100), DQS PI = 52
2416 09:28:35.539797 [0] AVG Duty = 4922%(X100)
2417 09:28:35.539860
2418 09:28:35.539937 ==DQM 1 ==
2419 09:28:35.540017 Final DQM duty delay cell = 0
2420 09:28:35.540079 [0] MAX Duty = 5031%(X100), DQS PI = 36
2421 09:28:35.540130 [0] MIN Duty = 4907%(X100), DQS PI = 2
2422 09:28:35.540223 [0] AVG Duty = 4969%(X100)
2423 09:28:35.540311
2424 09:28:35.540386 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2425 09:28:35.540461
2426 09:28:35.540552 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2427 09:28:35.540629 [DutyScan_Calibration_Flow] ====Done====
2428 09:28:35.540724
2429 09:28:35.540831 [DutyScan_Calibration_Flow] k_type=2
2430 09:28:35.540906
2431 09:28:35.540980 ==DQ 0 ==
2432 09:28:35.541056 Final DQ duty delay cell = 0
2433 09:28:35.541132 [0] MAX Duty = 5062%(X100), DQS PI = 12
2434 09:28:35.541207 [0] MIN Duty = 4938%(X100), DQS PI = 54
2435 09:28:35.541299 [0] AVG Duty = 5000%(X100)
2436 09:28:35.541386
2437 09:28:35.541461 ==DQ 1 ==
2438 09:28:35.541537 Final DQ duty delay cell = 0
2439 09:28:35.541612 [0] MAX Duty = 5125%(X100), DQS PI = 36
2440 09:28:35.541705 [0] MIN Duty = 4938%(X100), DQS PI = 26
2441 09:28:35.541852 [0] AVG Duty = 5031%(X100)
2442 09:28:35.541944
2443 09:28:35.542019 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2444 09:28:35.542094
2445 09:28:35.542170 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2446 09:28:35.542245 [DutyScan_Calibration_Flow] ====Done====
2447 09:28:35.542320 nWR fixed to 30
2448 09:28:35.542402 [ModeRegInit_LP4] CH0 RK0
2449 09:28:35.542455 [ModeRegInit_LP4] CH0 RK1
2450 09:28:35.542504 [ModeRegInit_LP4] CH1 RK0
2451 09:28:35.542551 [ModeRegInit_LP4] CH1 RK1
2452 09:28:35.542599 match AC timing 7
2453 09:28:35.542646 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2454 09:28:35.542694 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2455 09:28:35.542742 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2456 09:28:35.542790 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2457 09:28:35.542837 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2458 09:28:35.542909 ==
2459 09:28:35.543029 Dram Type= 6, Freq= 0, CH_0, rank 0
2460 09:28:35.543107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2461 09:28:35.543187 ==
2462 09:28:35.543260 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2463 09:28:35.543335 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2464 09:28:35.543408 [CA 0] Center 40 (10~71) winsize 62
2465 09:28:35.543481 [CA 1] Center 39 (9~70) winsize 62
2466 09:28:35.543550 [CA 2] Center 36 (6~66) winsize 61
2467 09:28:35.543601 [CA 3] Center 35 (5~66) winsize 62
2468 09:28:35.543650 [CA 4] Center 34 (4~65) winsize 62
2469 09:28:35.543697 [CA 5] Center 33 (3~63) winsize 61
2470 09:28:35.543744
2471 09:28:35.543792 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2472 09:28:35.543840
2473 09:28:35.543968 [CATrainingPosCal] consider 1 rank data
2474 09:28:35.544045 u2DelayCellTimex100 = 270/100 ps
2475 09:28:35.544119 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2476 09:28:35.544191 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2477 09:28:35.544242 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2478 09:28:35.544290 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2479 09:28:35.544339 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2480 09:28:35.544387 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2481 09:28:35.544435
2482 09:28:35.544482 CA PerBit enable=1, Macro0, CA PI delay=33
2483 09:28:35.544530
2484 09:28:35.544577 [CBTSetCACLKResult] CA Dly = 33
2485 09:28:35.544624 CS Dly: 7 (0~38)
2486 09:28:35.544713 ==
2487 09:28:35.544761 Dram Type= 6, Freq= 0, CH_0, rank 1
2488 09:28:35.544809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 09:28:35.544857 ==
2490 09:28:35.544906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 09:28:35.544953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2492 09:28:35.545192 [CA 0] Center 40 (10~70) winsize 61
2493 09:28:35.545245 [CA 1] Center 39 (9~70) winsize 62
2494 09:28:35.545344 [CA 2] Center 35 (5~66) winsize 62
2495 09:28:35.545448 [CA 3] Center 35 (5~66) winsize 62
2496 09:28:35.545509 [CA 4] Center 34 (4~65) winsize 62
2497 09:28:35.545557 [CA 5] Center 33 (3~63) winsize 61
2498 09:28:35.545605
2499 09:28:35.545652 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2500 09:28:35.545699
2501 09:28:35.545746 [CATrainingPosCal] consider 2 rank data
2502 09:28:35.545795 u2DelayCellTimex100 = 270/100 ps
2503 09:28:35.545858 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2504 09:28:35.545906 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2505 09:28:35.545955 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2506 09:28:35.546003 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2507 09:28:35.546053 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2508 09:28:35.546114 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2509 09:28:35.546161
2510 09:28:35.546207 CA PerBit enable=1, Macro0, CA PI delay=33
2511 09:28:35.546255
2512 09:28:35.546301 [CBTSetCACLKResult] CA Dly = 33
2513 09:28:35.546348 CS Dly: 7 (0~39)
2514 09:28:35.546411
2515 09:28:35.546473 ----->DramcWriteLeveling(PI) begin...
2516 09:28:35.546521 ==
2517 09:28:35.546568 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 09:28:35.546616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 09:28:35.546663 ==
2520 09:28:35.546710 Write leveling (Byte 0): 31 => 31
2521 09:28:35.546759 Write leveling (Byte 1): 31 => 31
2522 09:28:35.546806 DramcWriteLeveling(PI) end<-----
2523 09:28:35.546853
2524 09:28:35.546900 ==
2525 09:28:35.546947 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 09:28:35.547011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 09:28:35.547073 ==
2528 09:28:35.547120 [Gating] SW mode calibration
2529 09:28:35.547168 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2530 09:28:35.547216 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2531 09:28:35.547263 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2532 09:28:35.547310 0 15 4 | B1->B0 | 2929 3434 | 0 0 | (1 1) (0 0)
2533 09:28:35.547357 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 09:28:35.547404 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 09:28:35.547452 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 09:28:35.547500 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 09:28:35.547563 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 09:28:35.547624 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2539 09:28:35.547672 1 0 0 | B1->B0 | 3333 2626 | 1 0 | (1 0) (1 0)
2540 09:28:35.547720 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2541 09:28:35.547768 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 09:28:35.547815 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 09:28:35.547863 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 09:28:35.547911 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 09:28:35.547958 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 09:28:35.548005 1 0 28 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
2547 09:28:35.548053 1 1 0 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
2548 09:28:35.548117 1 1 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2549 09:28:35.548178 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 09:28:35.548225 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 09:28:35.548273 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 09:28:35.548320 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 09:28:35.548367 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 09:28:35.548414 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2555 09:28:35.548462 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2556 09:28:35.548509 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2557 09:28:35.548557 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 09:28:35.548607 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 09:28:35.548702 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 09:28:35.548751 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 09:28:35.548801 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 09:28:35.548849 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 09:28:35.548897 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 09:28:35.548944 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 09:28:35.548992 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 09:28:35.549039 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 09:28:35.549087 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 09:28:35.549134 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 09:28:35.549182 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 09:28:35.549229 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2571 09:28:35.549277 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2572 09:28:35.549325 Total UI for P1: 0, mck2ui 16
2573 09:28:35.549373 best dqsien dly found for B0: ( 1, 3, 28)
2574 09:28:35.549422 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2575 09:28:35.549469 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 09:28:35.549516 Total UI for P1: 0, mck2ui 16
2577 09:28:35.549565 best dqsien dly found for B1: ( 1, 4, 2)
2578 09:28:35.549612 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2579 09:28:35.549660 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2580 09:28:35.549707
2581 09:28:35.549754 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2582 09:28:35.549802 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2583 09:28:35.549849 [Gating] SW calibration Done
2584 09:28:35.549896 ==
2585 09:28:35.549944 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 09:28:35.549991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 09:28:35.550039 ==
2588 09:28:35.550086 RX Vref Scan: 0
2589 09:28:35.550133
2590 09:28:35.550179 RX Vref 0 -> 0, step: 1
2591 09:28:35.550226
2592 09:28:35.550272 RX Delay -40 -> 252, step: 8
2593 09:28:35.550319 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2594 09:28:35.550367 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2595 09:28:35.550414 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2596 09:28:35.550461 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2597 09:28:35.550705 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2598 09:28:35.550761 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2599 09:28:35.550810 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2600 09:28:35.550858 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2601 09:28:35.550906 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2602 09:28:35.550953 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2603 09:28:35.551001 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2604 09:28:35.551049 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2605 09:28:35.551098 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2606 09:28:35.551146 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2607 09:28:35.551193 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2608 09:28:35.551240 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2609 09:28:35.551288 ==
2610 09:28:35.551335 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 09:28:35.551382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 09:28:35.551430 ==
2613 09:28:35.551486 DQS Delay:
2614 09:28:35.551596 DQS0 = 0, DQS1 = 0
2615 09:28:35.551672 DQM Delay:
2616 09:28:35.551748 DQM0 = 112, DQM1 = 103
2617 09:28:35.551821 DQ Delay:
2618 09:28:35.551892 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2619 09:28:35.551965 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2620 09:28:35.552036 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2621 09:28:35.552100 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2622 09:28:35.552150
2623 09:28:35.552197
2624 09:28:35.552244 ==
2625 09:28:35.552290 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 09:28:35.552365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 09:28:35.552414 ==
2628 09:28:35.552470
2629 09:28:35.552547
2630 09:28:35.552640 TX Vref Scan disable
2631 09:28:35.552738 == TX Byte 0 ==
2632 09:28:35.552798 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2633 09:28:35.552848 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2634 09:28:35.552896 == TX Byte 1 ==
2635 09:28:35.552944 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2636 09:28:35.552992 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2637 09:28:35.553039 ==
2638 09:28:35.553086 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 09:28:35.553134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 09:28:35.553182 ==
2641 09:28:35.553228 TX Vref=22, minBit 4, minWin=25, winSum=419
2642 09:28:35.553276 TX Vref=24, minBit 5, minWin=25, winSum=423
2643 09:28:35.553324 TX Vref=26, minBit 4, minWin=26, winSum=429
2644 09:28:35.553372 TX Vref=28, minBit 0, minWin=27, winSum=439
2645 09:28:35.553421 TX Vref=30, minBit 10, minWin=26, winSum=438
2646 09:28:35.553470 TX Vref=32, minBit 1, minWin=26, winSum=432
2647 09:28:35.553518 [TxChooseVref] Worse bit 0, Min win 27, Win sum 439, Final Vref 28
2648 09:28:35.553566
2649 09:28:35.553613 Final TX Range 1 Vref 28
2650 09:28:35.553660
2651 09:28:35.553715 ==
2652 09:28:35.553813 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 09:28:35.553863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 09:28:35.553913 ==
2655 09:28:35.553961
2656 09:28:35.554008
2657 09:28:35.554055 TX Vref Scan disable
2658 09:28:35.554103 == TX Byte 0 ==
2659 09:28:35.554151 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2660 09:28:35.554198 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2661 09:28:35.554257 == TX Byte 1 ==
2662 09:28:35.554323 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2663 09:28:35.554373 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2664 09:28:35.554422
2665 09:28:35.554469 [DATLAT]
2666 09:28:35.554516 Freq=1200, CH0 RK0
2667 09:28:35.554563
2668 09:28:35.554610 DATLAT Default: 0xd
2669 09:28:35.554657 0, 0xFFFF, sum = 0
2670 09:28:35.554706 1, 0xFFFF, sum = 0
2671 09:28:35.554760 2, 0xFFFF, sum = 0
2672 09:28:35.554827 3, 0xFFFF, sum = 0
2673 09:28:35.554878 4, 0xFFFF, sum = 0
2674 09:28:35.554926 5, 0xFFFF, sum = 0
2675 09:28:35.554975 6, 0xFFFF, sum = 0
2676 09:28:35.555022 7, 0xFFFF, sum = 0
2677 09:28:35.555070 8, 0xFFFF, sum = 0
2678 09:28:35.555118 9, 0xFFFF, sum = 0
2679 09:28:35.555167 10, 0xFFFF, sum = 0
2680 09:28:35.555215 11, 0xFFFF, sum = 0
2681 09:28:35.555263 12, 0x0, sum = 1
2682 09:28:35.555337 13, 0x0, sum = 2
2683 09:28:35.555389 14, 0x0, sum = 3
2684 09:28:35.555437 15, 0x0, sum = 4
2685 09:28:35.555486 best_step = 13
2686 09:28:35.555533
2687 09:28:35.555580 ==
2688 09:28:35.555626 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 09:28:35.555675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 09:28:35.555723 ==
2691 09:28:35.555771 RX Vref Scan: 1
2692 09:28:35.555835
2693 09:28:35.555897 Set Vref Range= 32 -> 127
2694 09:28:35.555946
2695 09:28:35.555993 RX Vref 32 -> 127, step: 1
2696 09:28:35.556041
2697 09:28:35.556089 RX Delay -37 -> 252, step: 4
2698 09:28:35.556136
2699 09:28:35.556184 Set Vref, RX VrefLevel [Byte0]: 32
2700 09:28:35.556232 [Byte1]: 32
2701 09:28:35.556279
2702 09:28:35.556336 Set Vref, RX VrefLevel [Byte0]: 33
2703 09:28:35.556401 [Byte1]: 33
2704 09:28:35.556451
2705 09:28:35.556498 Set Vref, RX VrefLevel [Byte0]: 34
2706 09:28:35.556546 [Byte1]: 34
2707 09:28:35.556593
2708 09:28:35.556639 Set Vref, RX VrefLevel [Byte0]: 35
2709 09:28:35.556724 [Byte1]: 35
2710 09:28:35.556772
2711 09:28:35.556818 Set Vref, RX VrefLevel [Byte0]: 36
2712 09:28:35.556877 [Byte1]: 36
2713 09:28:35.556962
2714 09:28:35.557073 Set Vref, RX VrefLevel [Byte0]: 37
2715 09:28:35.557148 [Byte1]: 37
2716 09:28:35.557223
2717 09:28:35.557298 Set Vref, RX VrefLevel [Byte0]: 38
2718 09:28:35.557374 [Byte1]: 38
2719 09:28:35.557465
2720 09:28:35.557541 Set Vref, RX VrefLevel [Byte0]: 39
2721 09:28:35.557616 [Byte1]: 39
2722 09:28:35.557691
2723 09:28:35.557766 Set Vref, RX VrefLevel [Byte0]: 40
2724 09:28:35.557841 [Byte1]: 40
2725 09:28:35.557923
2726 09:28:35.558006 Set Vref, RX VrefLevel [Byte0]: 41
2727 09:28:35.558083 [Byte1]: 41
2728 09:28:35.558157
2729 09:28:35.558232 Set Vref, RX VrefLevel [Byte0]: 42
2730 09:28:35.558308 [Byte1]: 42
2731 09:28:35.558397
2732 09:28:35.558488 Set Vref, RX VrefLevel [Byte0]: 43
2733 09:28:35.558568 [Byte1]: 43
2734 09:28:35.558644
2735 09:28:35.558721 Set Vref, RX VrefLevel [Byte0]: 44
2736 09:28:35.558798 [Byte1]: 44
2737 09:28:35.558874
2738 09:28:35.558950 Set Vref, RX VrefLevel [Byte0]: 45
2739 09:28:35.559044 [Byte1]: 45
2740 09:28:35.559121
2741 09:28:35.559198 Set Vref, RX VrefLevel [Byte0]: 46
2742 09:28:35.559276 [Byte1]: 46
2743 09:28:35.559353
2744 09:28:35.559429 Set Vref, RX VrefLevel [Byte0]: 47
2745 09:28:35.559510 [Byte1]: 47
2746 09:28:35.559575
2747 09:28:35.559624 Set Vref, RX VrefLevel [Byte0]: 48
2748 09:28:35.559673 [Byte1]: 48
2749 09:28:35.559722
2750 09:28:35.559770 Set Vref, RX VrefLevel [Byte0]: 49
2751 09:28:35.559818 [Byte1]: 49
2752 09:28:35.559865
2753 09:28:35.559913 Set Vref, RX VrefLevel [Byte0]: 50
2754 09:28:35.559961 [Byte1]: 50
2755 09:28:35.560010
2756 09:28:35.560296 Set Vref, RX VrefLevel [Byte0]: 51
2757 09:28:35.560360 [Byte1]: 51
2758 09:28:35.560411
2759 09:28:35.560460 Set Vref, RX VrefLevel [Byte0]: 52
2760 09:28:35.560513 [Byte1]: 52
2761 09:28:35.560601
2762 09:28:35.560694 Set Vref, RX VrefLevel [Byte0]: 53
2763 09:28:35.560772 [Byte1]: 53
2764 09:28:35.560855
2765 09:28:35.560934 Set Vref, RX VrefLevel [Byte0]: 54
2766 09:28:35.561009 [Byte1]: 54
2767 09:28:35.561084
2768 09:28:35.561156 Set Vref, RX VrefLevel [Byte0]: 55
2769 09:28:35.561229 [Byte1]: 55
2770 09:28:35.561302
2771 09:28:35.561366 Set Vref, RX VrefLevel [Byte0]: 56
2772 09:28:35.561417 [Byte1]: 56
2773 09:28:35.561467
2774 09:28:35.561515 Set Vref, RX VrefLevel [Byte0]: 57
2775 09:28:35.561564 [Byte1]: 57
2776 09:28:35.561612
2777 09:28:35.561660 Set Vref, RX VrefLevel [Byte0]: 58
2778 09:28:35.561709 [Byte1]: 58
2779 09:28:35.561757
2780 09:28:35.561805 Set Vref, RX VrefLevel [Byte0]: 59
2781 09:28:35.561853 [Byte1]: 59
2782 09:28:35.561901
2783 09:28:35.561948 Set Vref, RX VrefLevel [Byte0]: 60
2784 09:28:35.561998 [Byte1]: 60
2785 09:28:35.562046
2786 09:28:35.562093 Set Vref, RX VrefLevel [Byte0]: 61
2787 09:28:35.562142 [Byte1]: 61
2788 09:28:35.562190
2789 09:28:35.562238 Set Vref, RX VrefLevel [Byte0]: 62
2790 09:28:35.562286 [Byte1]: 62
2791 09:28:35.562333
2792 09:28:35.562381 Set Vref, RX VrefLevel [Byte0]: 63
2793 09:28:35.562429 [Byte1]: 63
2794 09:28:35.562477
2795 09:28:35.562525 Set Vref, RX VrefLevel [Byte0]: 64
2796 09:28:35.562573 [Byte1]: 64
2797 09:28:35.562621
2798 09:28:35.562669 Set Vref, RX VrefLevel [Byte0]: 65
2799 09:28:35.562718 [Byte1]: 65
2800 09:28:35.562766
2801 09:28:35.562813 Set Vref, RX VrefLevel [Byte0]: 66
2802 09:28:35.562862 [Byte1]: 66
2803 09:28:35.562910
2804 09:28:35.562958 Set Vref, RX VrefLevel [Byte0]: 67
2805 09:28:35.563006 [Byte1]: 67
2806 09:28:35.563054
2807 09:28:35.563101 Set Vref, RX VrefLevel [Byte0]: 68
2808 09:28:35.563150 [Byte1]: 68
2809 09:28:35.563198
2810 09:28:35.563245 Set Vref, RX VrefLevel [Byte0]: 69
2811 09:28:35.563293 [Byte1]: 69
2812 09:28:35.563341
2813 09:28:35.563388 Set Vref, RX VrefLevel [Byte0]: 70
2814 09:28:35.563436 [Byte1]: 70
2815 09:28:35.563485
2816 09:28:35.563533 Set Vref, RX VrefLevel [Byte0]: 71
2817 09:28:35.563581 [Byte1]: 71
2818 09:28:35.563629
2819 09:28:35.563677 Set Vref, RX VrefLevel [Byte0]: 72
2820 09:28:35.563725 [Byte1]: 72
2821 09:28:35.563772
2822 09:28:35.563820 Set Vref, RX VrefLevel [Byte0]: 73
2823 09:28:35.563869 [Byte1]: 73
2824 09:28:35.563917
2825 09:28:35.563965 Set Vref, RX VrefLevel [Byte0]: 74
2826 09:28:35.564014 [Byte1]: 74
2827 09:28:35.564062
2828 09:28:35.564109 Final RX Vref Byte 0 = 61 to rank0
2829 09:28:35.564158 Final RX Vref Byte 1 = 52 to rank0
2830 09:28:35.564207 Final RX Vref Byte 0 = 61 to rank1
2831 09:28:35.564255 Final RX Vref Byte 1 = 52 to rank1==
2832 09:28:35.564304 Dram Type= 6, Freq= 0, CH_0, rank 0
2833 09:28:35.564352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 09:28:35.564402 ==
2835 09:28:35.564449 DQS Delay:
2836 09:28:35.564497 DQS0 = 0, DQS1 = 0
2837 09:28:35.564545 DQM Delay:
2838 09:28:35.564593 DQM0 = 112, DQM1 = 101
2839 09:28:35.564641 DQ Delay:
2840 09:28:35.564698 DQ0 =110, DQ1 =114, DQ2 =110, DQ3 =108
2841 09:28:35.564746 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2842 09:28:35.564795 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2843 09:28:35.564844 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2844 09:28:35.564892
2845 09:28:35.564939
2846 09:28:35.564987 [DQSOSCAuto] RK0, (LSB)MR18= 0xfffe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2847 09:28:35.565039 CH0 RK0: MR19=303, MR18=FFFE
2848 09:28:35.565088 CH0_RK0: MR19=0x303, MR18=0xFFFE, DQSOSC=410, MR23=63, INC=39, DEC=26
2849 09:28:35.565137
2850 09:28:35.565185 ----->DramcWriteLeveling(PI) begin...
2851 09:28:35.565234 ==
2852 09:28:35.565282 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 09:28:35.565332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 09:28:35.565381 ==
2855 09:28:35.565429 Write leveling (Byte 0): 31 => 31
2856 09:28:35.565477 Write leveling (Byte 1): 31 => 31
2857 09:28:35.565526 DramcWriteLeveling(PI) end<-----
2858 09:28:35.565574
2859 09:28:35.565621 ==
2860 09:28:35.565669 Dram Type= 6, Freq= 0, CH_0, rank 1
2861 09:28:35.565728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 09:28:35.565779 ==
2863 09:28:35.565828 [Gating] SW mode calibration
2864 09:28:35.565877 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2865 09:28:35.565927 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2866 09:28:35.565976 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2867 09:28:35.566025 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 09:28:35.566074 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 09:28:35.566121 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 09:28:35.566170 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 09:28:35.566218 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 09:28:35.566267 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2873 09:28:35.566315 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2874 09:28:35.566364 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2875 09:28:35.566412 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 09:28:35.566461 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 09:28:35.566509 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 09:28:35.566557 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 09:28:35.566606 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 09:28:35.566654 1 0 24 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
2881 09:28:35.566703 1 0 28 | B1->B0 | 2424 4545 | 0 1 | (0 0) (0 0)
2882 09:28:35.566751 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2883 09:28:35.566800 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 09:28:35.566848 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 09:28:35.566897 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 09:28:35.566945 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 09:28:35.567183 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 09:28:35.567237 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 09:28:35.567287 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2890 09:28:35.567336 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2891 09:28:35.567385 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 09:28:35.567433 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 09:28:35.567481 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 09:28:35.567529 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 09:28:35.567577 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 09:28:35.567626 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 09:28:35.567674 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 09:28:35.567722 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 09:28:35.567772 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 09:28:35.567821 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 09:28:35.567869 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 09:28:35.567916 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 09:28:35.567965 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 09:28:35.568013 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2905 09:28:35.568061 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2906 09:28:35.568109 Total UI for P1: 0, mck2ui 16
2907 09:28:35.568159 best dqsien dly found for B0: ( 1, 3, 24)
2908 09:28:35.568208 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2909 09:28:35.568257 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 09:28:35.568306 Total UI for P1: 0, mck2ui 16
2911 09:28:35.568354 best dqsien dly found for B1: ( 1, 4, 0)
2912 09:28:35.568402 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2913 09:28:35.568452 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2914 09:28:35.568500
2915 09:28:35.568548 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2916 09:28:35.568596 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2917 09:28:35.568653 [Gating] SW calibration Done
2918 09:28:35.568706 ==
2919 09:28:35.568789 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 09:28:35.568868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 09:28:35.568945 ==
2922 09:28:35.569020 RX Vref Scan: 0
2923 09:28:35.569071
2924 09:28:35.569119 RX Vref 0 -> 0, step: 1
2925 09:28:35.569168
2926 09:28:35.569216 RX Delay -40 -> 252, step: 8
2927 09:28:35.569265 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2928 09:28:35.569313 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2929 09:28:35.569362 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2930 09:28:35.569410 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2931 09:28:35.569458 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2932 09:28:35.569506 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2933 09:28:35.569555 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2934 09:28:35.569603 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2935 09:28:35.569652 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2936 09:28:35.690853 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2937 09:28:35.690961 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2938 09:28:35.691020 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2939 09:28:35.691074 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2940 09:28:35.691156 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2941 09:28:35.691208 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2942 09:28:35.691257 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2943 09:28:35.691306 ==
2944 09:28:35.691355 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 09:28:35.691435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 09:28:35.691484 ==
2947 09:28:35.691532 DQS Delay:
2948 09:28:35.691580 DQS0 = 0, DQS1 = 0
2949 09:28:35.691628 DQM Delay:
2950 09:28:35.691676 DQM0 = 112, DQM1 = 100
2951 09:28:35.691738 DQ Delay:
2952 09:28:35.691816 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2953 09:28:35.691878 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2954 09:28:35.691927 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2955 09:28:35.691975 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =107
2956 09:28:35.692023
2957 09:28:35.692110
2958 09:28:35.692181 ==
2959 09:28:35.692255 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 09:28:35.692317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 09:28:35.692365 ==
2962 09:28:35.692411
2963 09:28:35.692466
2964 09:28:35.692562 TX Vref Scan disable
2965 09:28:35.692639 == TX Byte 0 ==
2966 09:28:35.692716 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2967 09:28:35.692766 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2968 09:28:35.692814 == TX Byte 1 ==
2969 09:28:35.692877 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2970 09:28:35.692939 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2971 09:28:35.692986 ==
2972 09:28:35.693034 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 09:28:35.693082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 09:28:35.693144 ==
2975 09:28:35.693207 TX Vref=22, minBit 5, minWin=26, winSum=428
2976 09:28:35.693255 TX Vref=24, minBit 5, minWin=26, winSum=430
2977 09:28:35.693303 TX Vref=26, minBit 0, minWin=27, winSum=438
2978 09:28:35.693352 TX Vref=28, minBit 0, minWin=26, winSum=437
2979 09:28:35.693414 TX Vref=30, minBit 5, minWin=27, winSum=444
2980 09:28:35.693475 TX Vref=32, minBit 14, minWin=26, winSum=440
2981 09:28:35.693523 [TxChooseVref] Worse bit 5, Min win 27, Win sum 444, Final Vref 30
2982 09:28:35.693600
2983 09:28:35.693676 Final TX Range 1 Vref 30
2984 09:28:35.693724
2985 09:28:35.693835 ==
2986 09:28:35.693882 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 09:28:35.693930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 09:28:35.693978 ==
2989 09:28:35.694025
2990 09:28:35.694071
2991 09:28:35.694133 TX Vref Scan disable
2992 09:28:35.694194 == TX Byte 0 ==
2993 09:28:35.694242 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2994 09:28:35.694290 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2995 09:28:35.694338 == TX Byte 1 ==
2996 09:28:35.694385 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2997 09:28:35.694433 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2998 09:28:35.694494
2999 09:28:35.694555 [DATLAT]
3000 09:28:35.694630 Freq=1200, CH0 RK1
3001 09:28:35.694706
3002 09:28:35.694789 DATLAT Default: 0xd
3003 09:28:35.694868 0, 0xFFFF, sum = 0
3004 09:28:35.694950 1, 0xFFFF, sum = 0
3005 09:28:35.695027 2, 0xFFFF, sum = 0
3006 09:28:35.695101 3, 0xFFFF, sum = 0
3007 09:28:35.695176 4, 0xFFFF, sum = 0
3008 09:28:35.695264 5, 0xFFFF, sum = 0
3009 09:28:35.695350 6, 0xFFFF, sum = 0
3010 09:28:35.695402 7, 0xFFFF, sum = 0
3011 09:28:35.695452 8, 0xFFFF, sum = 0
3012 09:28:35.695502 9, 0xFFFF, sum = 0
3013 09:28:35.695551 10, 0xFFFF, sum = 0
3014 09:28:35.695799 11, 0xFFFF, sum = 0
3015 09:28:35.695883 12, 0x0, sum = 1
3016 09:28:35.695935 13, 0x0, sum = 2
3017 09:28:35.695984 14, 0x0, sum = 3
3018 09:28:35.696034 15, 0x0, sum = 4
3019 09:28:35.696084 best_step = 13
3020 09:28:35.696133
3021 09:28:35.696180 ==
3022 09:28:35.696228 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 09:28:35.696278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 09:28:35.696327 ==
3025 09:28:35.696377 RX Vref Scan: 0
3026 09:28:35.696426
3027 09:28:35.696475 RX Vref 0 -> 0, step: 1
3028 09:28:35.696523
3029 09:28:35.696571 RX Delay -37 -> 252, step: 4
3030 09:28:35.696621 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3031 09:28:35.696681 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3032 09:28:35.696732 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3033 09:28:35.696781 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3034 09:28:35.696830 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3035 09:28:35.696880 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3036 09:28:35.696929 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3037 09:28:35.696978 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3038 09:28:35.697027 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3039 09:28:35.697076 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3040 09:28:35.697126 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3041 09:28:35.697175 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3042 09:28:35.697224 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3043 09:28:35.697304 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3044 09:28:35.697382 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3045 09:28:35.697431 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3046 09:28:35.697481 ==
3047 09:28:35.697531 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 09:28:35.697593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 09:28:35.697657 ==
3050 09:28:35.697706 DQS Delay:
3051 09:28:35.697755 DQS0 = 0, DQS1 = 0
3052 09:28:35.697803 DQM Delay:
3053 09:28:35.697852 DQM0 = 110, DQM1 = 100
3054 09:28:35.697901 DQ Delay:
3055 09:28:35.697949 DQ0 =108, DQ1 =110, DQ2 =106, DQ3 =108
3056 09:28:35.697999 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3057 09:28:35.698048 DQ8 =90, DQ9 =82, DQ10 =104, DQ11 =92
3058 09:28:35.698097 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =108
3059 09:28:35.698146
3060 09:28:35.698194
3061 09:28:35.698243 [DQSOSCAuto] RK1, (LSB)MR18= 0x16fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 401 ps
3062 09:28:35.698293 CH0 RK1: MR19=403, MR18=16FE
3063 09:28:35.698343 CH0_RK1: MR19=0x403, MR18=0x16FE, DQSOSC=401, MR23=63, INC=40, DEC=27
3064 09:28:35.698392 [RxdqsGatingPostProcess] freq 1200
3065 09:28:35.698441 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3066 09:28:35.698491 best DQS0 dly(2T, 0.5T) = (0, 11)
3067 09:28:35.698541 best DQS1 dly(2T, 0.5T) = (0, 12)
3068 09:28:35.698590 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3069 09:28:35.698639 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3070 09:28:35.698687 best DQS0 dly(2T, 0.5T) = (0, 11)
3071 09:28:35.698769 best DQS1 dly(2T, 0.5T) = (0, 12)
3072 09:28:35.698848 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3073 09:28:35.698939 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3074 09:28:35.699029 Pre-setting of DQS Precalculation
3075 09:28:35.699096 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3076 09:28:35.699146 ==
3077 09:28:35.699195 Dram Type= 6, Freq= 0, CH_1, rank 0
3078 09:28:35.699259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 09:28:35.699321 ==
3080 09:28:35.699369 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3081 09:28:35.699418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3082 09:28:35.699467 [CA 0] Center 37 (7~67) winsize 61
3083 09:28:35.699515 [CA 1] Center 37 (7~68) winsize 62
3084 09:28:35.699576 [CA 2] Center 34 (4~64) winsize 61
3085 09:28:35.699653 [CA 3] Center 34 (4~64) winsize 61
3086 09:28:35.699716 [CA 4] Center 34 (4~64) winsize 61
3087 09:28:35.699764 [CA 5] Center 33 (3~63) winsize 61
3088 09:28:35.699812
3089 09:28:35.699859 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3090 09:28:35.699907
3091 09:28:35.699954 [CATrainingPosCal] consider 1 rank data
3092 09:28:35.700017 u2DelayCellTimex100 = 270/100 ps
3093 09:28:35.700079 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3094 09:28:35.700128 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3095 09:28:35.700176 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 09:28:35.700224 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 09:28:35.700272 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3098 09:28:35.700319 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3099 09:28:35.700383
3100 09:28:35.700444 CA PerBit enable=1, Macro0, CA PI delay=33
3101 09:28:35.700492
3102 09:28:35.700540 [CBTSetCACLKResult] CA Dly = 33
3103 09:28:35.700588 CS Dly: 6 (0~37)
3104 09:28:35.700635 ==
3105 09:28:35.700720 Dram Type= 6, Freq= 0, CH_1, rank 1
3106 09:28:35.700797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 09:28:35.700846 ==
3108 09:28:35.700894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3109 09:28:35.700943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3110 09:28:35.700991 [CA 0] Center 37 (7~67) winsize 61
3111 09:28:35.701040 [CA 1] Center 37 (7~68) winsize 62
3112 09:28:35.701130 [CA 2] Center 34 (4~65) winsize 62
3113 09:28:35.701192 [CA 3] Center 33 (3~64) winsize 62
3114 09:28:35.701240 [CA 4] Center 34 (4~65) winsize 62
3115 09:28:35.701302 [CA 5] Center 33 (3~63) winsize 61
3116 09:28:35.701392
3117 09:28:35.701440 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3118 09:28:35.701488
3119 09:28:35.701535 [CATrainingPosCal] consider 2 rank data
3120 09:28:35.701583 u2DelayCellTimex100 = 270/100 ps
3121 09:28:35.701646 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3122 09:28:35.701709 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3123 09:28:35.701757 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3124 09:28:35.701805 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 09:28:35.701853 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3126 09:28:35.701901 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3127 09:28:35.701949
3128 09:28:35.702010 CA PerBit enable=1, Macro0, CA PI delay=33
3129 09:28:35.702072
3130 09:28:35.702120 [CBTSetCACLKResult] CA Dly = 33
3131 09:28:35.702168 CS Dly: 7 (0~39)
3132 09:28:35.702216
3133 09:28:35.702263 ----->DramcWriteLeveling(PI) begin...
3134 09:28:35.702312 ==
3135 09:28:35.702374 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 09:28:35.702436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 09:28:35.702484 ==
3138 09:28:35.702532 Write leveling (Byte 0): 25 => 25
3139 09:28:35.702580 Write leveling (Byte 1): 29 => 29
3140 09:28:35.702855 DramcWriteLeveling(PI) end<-----
3141 09:28:35.702925
3142 09:28:35.703034 ==
3143 09:28:35.703114 Dram Type= 6, Freq= 0, CH_1, rank 0
3144 09:28:35.703190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 09:28:35.703264 ==
3146 09:28:35.703336 [Gating] SW mode calibration
3147 09:28:35.703438 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3148 09:28:35.703512 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3149 09:28:35.703565 0 15 0 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
3150 09:28:35.703628 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 09:28:35.703705 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 09:28:35.703783 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 09:28:35.703845 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 09:28:35.703908 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 09:28:35.703996 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3156 09:28:35.704059 0 15 28 | B1->B0 | 2a2a 2d2d | 0 0 | (0 0) (0 0)
3157 09:28:35.704107 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3158 09:28:35.704156 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 09:28:35.704204 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 09:28:35.704266 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 09:28:35.704316 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 09:28:35.704365 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3163 09:28:35.704414 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3164 09:28:35.704463 1 0 28 | B1->B0 | 3d3d 4141 | 0 0 | (1 1) (0 0)
3165 09:28:35.704512 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3166 09:28:35.704561 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 09:28:35.704610 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 09:28:35.704667 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 09:28:35.704731 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 09:28:35.704808 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 09:28:35.704856 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 09:28:35.704903 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3173 09:28:35.704951 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3174 09:28:35.704999 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 09:28:35.705046 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 09:28:35.705093 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 09:28:35.705170 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 09:28:35.705218 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 09:28:35.705266 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 09:28:35.705314 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 09:28:35.705362 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 09:28:35.705411 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 09:28:35.705459 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 09:28:35.705534 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 09:28:35.705582 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 09:28:35.705630 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 09:28:35.705678 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 09:28:35.705726 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3189 09:28:35.705774 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 09:28:35.705823 Total UI for P1: 0, mck2ui 16
3191 09:28:35.705900 best dqsien dly found for B0: ( 1, 3, 28)
3192 09:28:35.705948 Total UI for P1: 0, mck2ui 16
3193 09:28:35.705996 best dqsien dly found for B1: ( 1, 3, 30)
3194 09:28:35.706044 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3195 09:28:35.706092 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3196 09:28:35.706154
3197 09:28:35.706215 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3198 09:28:35.706291 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3199 09:28:35.706368 [Gating] SW calibration Done
3200 09:28:35.706445 ==
3201 09:28:35.706551 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 09:28:35.706605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 09:28:35.706654 ==
3204 09:28:35.706703 RX Vref Scan: 0
3205 09:28:35.706751
3206 09:28:35.706799 RX Vref 0 -> 0, step: 1
3207 09:28:35.706875
3208 09:28:35.706923 RX Delay -40 -> 252, step: 8
3209 09:28:35.706970 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3210 09:28:35.707018 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3211 09:28:35.707066 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3212 09:28:35.707115 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3213 09:28:35.707163 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3214 09:28:35.707211 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3215 09:28:35.707259 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3216 09:28:35.707306 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3217 09:28:35.707354 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3218 09:28:35.707403 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3219 09:28:35.707451 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3220 09:28:35.707526 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3221 09:28:35.707574 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3222 09:28:35.707622 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3223 09:28:35.707670 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3224 09:28:35.707718 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3225 09:28:35.707766 ==
3226 09:28:35.707814 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 09:28:35.707863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 09:28:35.707911 ==
3229 09:28:35.707959 DQS Delay:
3230 09:28:35.708006 DQS0 = 0, DQS1 = 0
3231 09:28:35.708054 DQM Delay:
3232 09:28:35.708116 DQM0 = 112, DQM1 = 106
3233 09:28:35.708178 DQ Delay:
3234 09:28:35.708226 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =111
3235 09:28:35.708274 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =107
3236 09:28:35.708322 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =103
3237 09:28:35.708371 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3238 09:28:35.708417
3239 09:28:35.708464
3240 09:28:35.708525 ==
3241 09:28:35.708574 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 09:28:35.708624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 09:28:35.708695 ==
3244 09:28:35.708758
3245 09:28:35.708852
3246 09:28:35.708900 TX Vref Scan disable
3247 09:28:35.709156 == TX Byte 0 ==
3248 09:28:35.709239 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3249 09:28:35.709290 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3250 09:28:35.709339 == TX Byte 1 ==
3251 09:28:35.709419 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3252 09:28:35.709481 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3253 09:28:35.709543 ==
3254 09:28:35.709591 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 09:28:35.709640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 09:28:35.709688 ==
3257 09:28:35.709736 TX Vref=22, minBit 3, minWin=25, winSum=415
3258 09:28:35.709813 TX Vref=24, minBit 11, minWin=24, winSum=416
3259 09:28:35.709862 TX Vref=26, minBit 8, minWin=25, winSum=422
3260 09:28:35.709910 TX Vref=28, minBit 9, minWin=25, winSum=428
3261 09:28:35.709958 TX Vref=30, minBit 9, minWin=25, winSum=429
3262 09:28:35.710006 TX Vref=32, minBit 9, minWin=25, winSum=428
3263 09:28:35.710054 [TxChooseVref] Worse bit 9, Min win 25, Win sum 429, Final Vref 30
3264 09:28:35.710116
3265 09:28:35.710177 Final TX Range 1 Vref 30
3266 09:28:35.710225
3267 09:28:35.710272 ==
3268 09:28:35.710320 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 09:28:35.710383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 09:28:35.710445 ==
3271 09:28:35.710493
3272 09:28:35.710540
3273 09:28:35.710587 TX Vref Scan disable
3274 09:28:35.710635 == TX Byte 0 ==
3275 09:28:35.710682 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3276 09:28:35.710744 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3277 09:28:35.710794 == TX Byte 1 ==
3278 09:28:35.710842 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3279 09:28:35.710892 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3280 09:28:35.710941
3281 09:28:35.710989 [DATLAT]
3282 09:28:35.711038 Freq=1200, CH1 RK0
3283 09:28:35.711101
3284 09:28:35.711149 DATLAT Default: 0xd
3285 09:28:35.711196 0, 0xFFFF, sum = 0
3286 09:28:35.711276 1, 0xFFFF, sum = 0
3287 09:28:35.711383 2, 0xFFFF, sum = 0
3288 09:28:35.711476 3, 0xFFFF, sum = 0
3289 09:28:35.711554 4, 0xFFFF, sum = 0
3290 09:28:35.711628 5, 0xFFFF, sum = 0
3291 09:28:35.711719 6, 0xFFFF, sum = 0
3292 09:28:35.711793 7, 0xFFFF, sum = 0
3293 09:28:35.711882 8, 0xFFFF, sum = 0
3294 09:28:35.711943 9, 0xFFFF, sum = 0
3295 09:28:35.712006 10, 0xFFFF, sum = 0
3296 09:28:35.712069 11, 0xFFFF, sum = 0
3297 09:28:35.712117 12, 0x0, sum = 1
3298 09:28:35.712165 13, 0x0, sum = 2
3299 09:28:35.712214 14, 0x0, sum = 3
3300 09:28:35.712261 15, 0x0, sum = 4
3301 09:28:35.712309 best_step = 13
3302 09:28:35.712369
3303 09:28:35.712444 ==
3304 09:28:35.712504 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 09:28:35.712552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 09:28:35.712600 ==
3307 09:28:35.712689 RX Vref Scan: 1
3308 09:28:35.712738
3309 09:28:35.712785 Set Vref Range= 32 -> 127
3310 09:28:35.712833
3311 09:28:35.712880 RX Vref 32 -> 127, step: 1
3312 09:28:35.712927
3313 09:28:35.712974 RX Delay -21 -> 252, step: 4
3314 09:28:35.713021
3315 09:28:35.713068 Set Vref, RX VrefLevel [Byte0]: 32
3316 09:28:35.713115 [Byte1]: 32
3317 09:28:35.713163
3318 09:28:35.713210 Set Vref, RX VrefLevel [Byte0]: 33
3319 09:28:35.713272 [Byte1]: 33
3320 09:28:35.713334
3321 09:28:35.713380 Set Vref, RX VrefLevel [Byte0]: 34
3322 09:28:35.713427 [Byte1]: 34
3323 09:28:35.713474
3324 09:28:35.713522 Set Vref, RX VrefLevel [Byte0]: 35
3325 09:28:35.713569 [Byte1]: 35
3326 09:28:35.713616
3327 09:28:35.713663 Set Vref, RX VrefLevel [Byte0]: 36
3328 09:28:35.713711 [Byte1]: 36
3329 09:28:35.713758
3330 09:28:35.713805 Set Vref, RX VrefLevel [Byte0]: 37
3331 09:28:35.713866 [Byte1]: 37
3332 09:28:35.713940
3333 09:28:35.713994 Set Vref, RX VrefLevel [Byte0]: 38
3334 09:28:35.714056 [Byte1]: 38
3335 09:28:35.714130
3336 09:28:35.714192 Set Vref, RX VrefLevel [Byte0]: 39
3337 09:28:35.714239 [Byte1]: 39
3338 09:28:35.714287
3339 09:28:35.714334 Set Vref, RX VrefLevel [Byte0]: 40
3340 09:28:35.714382 [Byte1]: 40
3341 09:28:35.714429
3342 09:28:35.714489 Set Vref, RX VrefLevel [Byte0]: 41
3343 09:28:35.714551 [Byte1]: 41
3344 09:28:35.714598
3345 09:28:35.714645 Set Vref, RX VrefLevel [Byte0]: 42
3346 09:28:35.714692 [Byte1]: 42
3347 09:28:35.714739
3348 09:28:35.714786 Set Vref, RX VrefLevel [Byte0]: 43
3349 09:28:35.714834 [Byte1]: 43
3350 09:28:35.714908
3351 09:28:35.714986 Set Vref, RX VrefLevel [Byte0]: 44
3352 09:28:35.715044 [Byte1]: 44
3353 09:28:35.715120
3354 09:28:35.715213 Set Vref, RX VrefLevel [Byte0]: 45
3355 09:28:35.715326 [Byte1]: 45
3356 09:28:35.715400
3357 09:28:35.715489 Set Vref, RX VrefLevel [Byte0]: 46
3358 09:28:35.715555 [Byte1]: 46
3359 09:28:35.715645
3360 09:28:35.715694 Set Vref, RX VrefLevel [Byte0]: 47
3361 09:28:35.715743 [Byte1]: 47
3362 09:28:35.715805
3363 09:28:35.715867 Set Vref, RX VrefLevel [Byte0]: 48
3364 09:28:35.715916 [Byte1]: 48
3365 09:28:35.715964
3366 09:28:35.716012 Set Vref, RX VrefLevel [Byte0]: 49
3367 09:28:35.716061 [Byte1]: 49
3368 09:28:35.716109
3369 09:28:35.716157 Set Vref, RX VrefLevel [Byte0]: 50
3370 09:28:35.716205 [Byte1]: 50
3371 09:28:35.716253
3372 09:28:35.716301 Set Vref, RX VrefLevel [Byte0]: 51
3373 09:28:35.716349 [Byte1]: 51
3374 09:28:35.716397
3375 09:28:35.716446 Set Vref, RX VrefLevel [Byte0]: 52
3376 09:28:35.716494 [Byte1]: 52
3377 09:28:35.716542
3378 09:28:35.716590 Set Vref, RX VrefLevel [Byte0]: 53
3379 09:28:35.716639 [Byte1]: 53
3380 09:28:35.716716
3381 09:28:35.716792 Set Vref, RX VrefLevel [Byte0]: 54
3382 09:28:35.716838 [Byte1]: 54
3383 09:28:35.716886
3384 09:28:35.716933 Set Vref, RX VrefLevel [Byte0]: 55
3385 09:28:35.716995 [Byte1]: 55
3386 09:28:35.717056
3387 09:28:35.717103 Set Vref, RX VrefLevel [Byte0]: 56
3388 09:28:35.717150 [Byte1]: 56
3389 09:28:35.717197
3390 09:28:35.717260 Set Vref, RX VrefLevel [Byte0]: 57
3391 09:28:35.717321 [Byte1]: 57
3392 09:28:35.717368
3393 09:28:35.717415 Set Vref, RX VrefLevel [Byte0]: 58
3394 09:28:35.717462 [Byte1]: 58
3395 09:28:35.717524
3396 09:28:35.717584 Set Vref, RX VrefLevel [Byte0]: 59
3397 09:28:35.717631 [Byte1]: 59
3398 09:28:35.717679
3399 09:28:35.717726 Set Vref, RX VrefLevel [Byte0]: 60
3400 09:28:35.717774 [Byte1]: 60
3401 09:28:35.717821
3402 09:28:35.717881 Set Vref, RX VrefLevel [Byte0]: 61
3403 09:28:35.717943 [Byte1]: 61
3404 09:28:35.717990
3405 09:28:35.718038 Set Vref, RX VrefLevel [Byte0]: 62
3406 09:28:35.718085 [Byte1]: 62
3407 09:28:35.718132
3408 09:28:35.718179 Set Vref, RX VrefLevel [Byte0]: 63
3409 09:28:35.718268 [Byte1]: 63
3410 09:28:35.718329
3411 09:28:35.718621 Set Vref, RX VrefLevel [Byte0]: 64
3412 09:28:35.718699 [Byte1]: 64
3413 09:28:35.718756
3414 09:28:35.718848 Set Vref, RX VrefLevel [Byte0]: 65
3415 09:28:35.718968 [Byte1]: 65
3416 09:28:35.719118
3417 09:28:35.719222 Final RX Vref Byte 0 = 54 to rank0
3418 09:28:35.719313 Final RX Vref Byte 1 = 48 to rank0
3419 09:28:35.719373 Final RX Vref Byte 0 = 54 to rank1
3420 09:28:35.719422 Final RX Vref Byte 1 = 48 to rank1==
3421 09:28:35.719470 Dram Type= 6, Freq= 0, CH_1, rank 0
3422 09:28:35.719522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 09:28:35.719572 ==
3424 09:28:35.719620 DQS Delay:
3425 09:28:35.719667 DQS0 = 0, DQS1 = 0
3426 09:28:35.719716 DQM Delay:
3427 09:28:35.719763 DQM0 = 114, DQM1 = 104
3428 09:28:35.719811 DQ Delay:
3429 09:28:35.719858 DQ0 =116, DQ1 =108, DQ2 =104, DQ3 =112
3430 09:28:35.719908 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3431 09:28:35.719957 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =100
3432 09:28:35.720019 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3433 09:28:35.720082
3434 09:28:35.720135
3435 09:28:35.720183 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3436 09:28:35.720233 CH1 RK0: MR19=303, MR18=F0F7
3437 09:28:35.720294 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3438 09:28:35.720356
3439 09:28:35.720428 ----->DramcWriteLeveling(PI) begin...
3440 09:28:35.720506 ==
3441 09:28:35.720584 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 09:28:35.720695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 09:28:35.720769 ==
3444 09:28:35.720841 Write leveling (Byte 0): 26 => 26
3445 09:28:35.720915 Write leveling (Byte 1): 28 => 28
3446 09:28:35.720985 DramcWriteLeveling(PI) end<-----
3447 09:28:35.721035
3448 09:28:35.721083 ==
3449 09:28:35.721130 Dram Type= 6, Freq= 0, CH_1, rank 1
3450 09:28:35.721179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 09:28:35.721227 ==
3452 09:28:35.721303 [Gating] SW mode calibration
3453 09:28:35.721351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3454 09:28:35.721400 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3455 09:28:35.721447 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3456 09:28:35.721494 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 09:28:35.721542 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 09:28:35.721589 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 09:28:35.721638 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 09:28:35.721685 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3461 09:28:35.721734 0 15 24 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
3462 09:28:35.721782 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3463 09:28:35.721830 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 09:28:35.721877 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 09:28:35.721924 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 09:28:35.721972 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 09:28:35.722021 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 09:28:35.722069 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 09:28:35.722116 1 0 24 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
3470 09:28:35.722185 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3471 09:28:35.722246 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 09:28:35.722294 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 09:28:35.722342 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 09:28:35.722389 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 09:28:35.722436 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 09:28:35.722484 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3477 09:28:35.722532 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3478 09:28:35.722580 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3479 09:28:35.722627 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 09:28:35.722675 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 09:28:35.722723 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 09:28:35.722771 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 09:28:35.722819 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 09:28:35.722866 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 09:28:35.722914 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 09:28:35.722961 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 09:28:35.723009 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 09:28:35.723056 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 09:28:35.723104 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 09:28:35.723151 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 09:28:35.723252 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 09:28:35.723346 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3493 09:28:35.723422 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3494 09:28:35.723499 Total UI for P1: 0, mck2ui 16
3495 09:28:35.723557 best dqsien dly found for B0: ( 1, 3, 20)
3496 09:28:35.723607 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3497 09:28:35.723655 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 09:28:35.723703 Total UI for P1: 0, mck2ui 16
3499 09:28:35.723752 best dqsien dly found for B1: ( 1, 3, 24)
3500 09:28:35.723799 best DQS0 dly(MCK, UI, PI) = (1, 3, 20)
3501 09:28:35.723847 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3502 09:28:35.723895
3503 09:28:35.723942 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 20)
3504 09:28:35.723989 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3505 09:28:35.724036 [Gating] SW calibration Done
3506 09:28:35.724084 ==
3507 09:28:35.724131 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 09:28:35.724179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 09:28:35.724227 ==
3510 09:28:35.724275 RX Vref Scan: 0
3511 09:28:35.724322
3512 09:28:35.724369 RX Vref 0 -> 0, step: 1
3513 09:28:35.724416
3514 09:28:35.724472 RX Delay -40 -> 252, step: 8
3515 09:28:35.724550 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3516 09:28:35.724648 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3517 09:28:35.724715 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3518 09:28:35.724975 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3519 09:28:35.725060 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3520 09:28:35.725113 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3521 09:28:35.725161 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3522 09:28:35.725209 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3523 09:28:35.725257 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3524 09:28:35.725304 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3525 09:28:35.725352 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3526 09:28:35.725399 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3527 09:28:35.725446 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3528 09:28:35.725493 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3529 09:28:35.725551 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3530 09:28:35.725605 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3531 09:28:35.725652 ==
3532 09:28:35.725731 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 09:28:35.725794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 09:28:35.725844 ==
3535 09:28:35.725893 DQS Delay:
3536 09:28:35.725941 DQS0 = 0, DQS1 = 0
3537 09:28:35.725990 DQM Delay:
3538 09:28:35.726053 DQM0 = 110, DQM1 = 107
3539 09:28:35.726132 DQ Delay:
3540 09:28:35.726195 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3541 09:28:35.726244 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3542 09:28:35.726292 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3543 09:28:35.726340 DQ12 =115, DQ13 =111, DQ14 =115, DQ15 =115
3544 09:28:35.726387
3545 09:28:35.726434
3546 09:28:35.726481 ==
3547 09:28:35.726528 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 09:28:35.726582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 09:28:35.726637 ==
3550 09:28:35.726686
3551 09:28:35.726733
3552 09:28:35.726780 TX Vref Scan disable
3553 09:28:35.726827 == TX Byte 0 ==
3554 09:28:35.726874 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3555 09:28:35.726922 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3556 09:28:35.726970 == TX Byte 1 ==
3557 09:28:35.727017 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3558 09:28:35.727096 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3559 09:28:35.727154 ==
3560 09:28:35.727206 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 09:28:35.727254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 09:28:35.727302 ==
3563 09:28:35.727349 TX Vref=22, minBit 9, minWin=25, winSum=423
3564 09:28:35.727398 TX Vref=24, minBit 9, minWin=25, winSum=426
3565 09:28:35.727445 TX Vref=26, minBit 3, minWin=26, winSum=429
3566 09:28:35.727493 TX Vref=28, minBit 8, minWin=26, winSum=433
3567 09:28:35.727541 TX Vref=30, minBit 8, minWin=25, winSum=430
3568 09:28:35.727588 TX Vref=32, minBit 8, minWin=26, winSum=433
3569 09:28:35.727635 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 28
3570 09:28:35.727700
3571 09:28:35.727750 Final TX Range 1 Vref 28
3572 09:28:35.727799
3573 09:28:35.727846 ==
3574 09:28:35.727895 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 09:28:35.727943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 09:28:35.727990 ==
3577 09:28:35.728037
3578 09:28:35.728083
3579 09:28:35.728130 TX Vref Scan disable
3580 09:28:35.728196 == TX Byte 0 ==
3581 09:28:35.728246 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3582 09:28:35.728295 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3583 09:28:35.728342 == TX Byte 1 ==
3584 09:28:35.728389 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3585 09:28:35.728437 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3586 09:28:35.728507
3587 09:28:35.728587 [DATLAT]
3588 09:28:35.728693 Freq=1200, CH1 RK1
3589 09:28:35.728768
3590 09:28:35.728858 DATLAT Default: 0xd
3591 09:28:35.728943 0, 0xFFFF, sum = 0
3592 09:28:35.729016 1, 0xFFFF, sum = 0
3593 09:28:35.729090 2, 0xFFFF, sum = 0
3594 09:28:35.729142 3, 0xFFFF, sum = 0
3595 09:28:35.729191 4, 0xFFFF, sum = 0
3596 09:28:35.729239 5, 0xFFFF, sum = 0
3597 09:28:35.729287 6, 0xFFFF, sum = 0
3598 09:28:35.729336 7, 0xFFFF, sum = 0
3599 09:28:35.729411 8, 0xFFFF, sum = 0
3600 09:28:35.729459 9, 0xFFFF, sum = 0
3601 09:28:35.729507 10, 0xFFFF, sum = 0
3602 09:28:35.729555 11, 0xFFFF, sum = 0
3603 09:28:35.729603 12, 0x0, sum = 1
3604 09:28:35.729651 13, 0x0, sum = 2
3605 09:28:35.729700 14, 0x0, sum = 3
3606 09:28:35.729769 15, 0x0, sum = 4
3607 09:28:35.729844 best_step = 13
3608 09:28:35.729906
3609 09:28:35.729953 ==
3610 09:28:35.730000 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 09:28:35.730048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 09:28:35.730096 ==
3613 09:28:35.730144 RX Vref Scan: 0
3614 09:28:35.730191
3615 09:28:35.730238 RX Vref 0 -> 0, step: 1
3616 09:28:35.730284
3617 09:28:35.730340 RX Delay -21 -> 252, step: 4
3618 09:28:35.730410 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3619 09:28:35.730474 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3620 09:28:35.730522 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3621 09:28:35.730570 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3622 09:28:35.730618 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3623 09:28:35.730665 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3624 09:28:35.730712 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3625 09:28:35.730759 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3626 09:28:35.730806 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3627 09:28:35.730865 iDelay=195, Bit 9, Center 102 (35 ~ 170) 136
3628 09:28:35.730916 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3629 09:28:35.730964 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3630 09:28:35.731012 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3631 09:28:35.731060 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3632 09:28:35.731107 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3633 09:28:35.731154 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3634 09:28:35.731201 ==
3635 09:28:35.731249 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 09:28:35.731298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 09:28:35.731353 ==
3638 09:28:35.731407 DQS Delay:
3639 09:28:35.731482 DQS0 = 0, DQS1 = 0
3640 09:28:35.731558 DQM Delay:
3641 09:28:35.731634 DQM0 = 111, DQM1 = 108
3642 09:28:35.731708 DQ Delay:
3643 09:28:35.731764 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3644 09:28:35.731813 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3645 09:28:35.731861 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =100
3646 09:28:35.731926 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =116
3647 09:28:35.731976
3648 09:28:35.732024
3649 09:28:35.732071 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa09, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3650 09:28:35.732120 CH1 RK1: MR19=304, MR18=FA09
3651 09:28:35.732168 CH1_RK1: MR19=0x304, MR18=0xFA09, DQSOSC=406, MR23=63, INC=39, DEC=26
3652 09:28:35.732216 [RxdqsGatingPostProcess] freq 1200
3653 09:28:35.732294 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3654 09:28:35.732341 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 09:28:35.732390 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 09:28:35.732674 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 09:28:35.732745 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 09:28:35.732795 best DQS0 dly(2T, 0.5T) = (0, 11)
3659 09:28:35.732843 best DQS1 dly(2T, 0.5T) = (0, 11)
3660 09:28:35.732891 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3661 09:28:35.732945 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3662 09:28:35.733019 Pre-setting of DQS Precalculation
3663 09:28:35.733081 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3664 09:28:35.733130 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3665 09:28:35.733179 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3666 09:28:35.733227
3667 09:28:35.733274
3668 09:28:35.733321 [Calibration Summary] 2400 Mbps
3669 09:28:35.733369 CH 0, Rank 0
3670 09:28:35.733416 SW Impedance : PASS
3671 09:28:35.733469 DUTY Scan : NO K
3672 09:28:35.733524 ZQ Calibration : PASS
3673 09:28:35.733572 Jitter Meter : NO K
3674 09:28:35.733620 CBT Training : PASS
3675 09:28:35.733666 Write leveling : PASS
3676 09:28:35.733716 RX DQS gating : PASS
3677 09:28:35.733764 RX DQ/DQS(RDDQC) : PASS
3678 09:28:35.733811 TX DQ/DQS : PASS
3679 09:28:35.733858 RX DATLAT : PASS
3680 09:28:35.733905 RX DQ/DQS(Engine): PASS
3681 09:28:35.733952 TX OE : NO K
3682 09:28:35.734016 All Pass.
3683 09:28:35.734066
3684 09:28:35.734113 CH 0, Rank 1
3685 09:28:35.734160 SW Impedance : PASS
3686 09:28:35.734207 DUTY Scan : NO K
3687 09:28:35.734255 ZQ Calibration : PASS
3688 09:28:35.734302 Jitter Meter : NO K
3689 09:28:35.734350 CBT Training : PASS
3690 09:28:35.734398 Write leveling : PASS
3691 09:28:35.734445 RX DQS gating : PASS
3692 09:28:35.734492 RX DQ/DQS(RDDQC) : PASS
3693 09:28:35.734554 TX DQ/DQS : PASS
3694 09:28:35.734602 RX DATLAT : PASS
3695 09:28:35.734649 RX DQ/DQS(Engine): PASS
3696 09:28:35.734696 TX OE : NO K
3697 09:28:35.734760 All Pass.
3698 09:28:35.734821
3699 09:28:35.734868 CH 1, Rank 0
3700 09:28:35.734916 SW Impedance : PASS
3701 09:28:35.734963 DUTY Scan : NO K
3702 09:28:35.735014 ZQ Calibration : PASS
3703 09:28:35.735073 Jitter Meter : NO K
3704 09:28:35.735121 CBT Training : PASS
3705 09:28:35.735169 Write leveling : PASS
3706 09:28:35.735216 RX DQS gating : PASS
3707 09:28:35.735263 RX DQ/DQS(RDDQC) : PASS
3708 09:28:35.735310 TX DQ/DQS : PASS
3709 09:28:35.735357 RX DATLAT : PASS
3710 09:28:35.735405 RX DQ/DQS(Engine): PASS
3711 09:28:35.735452 TX OE : NO K
3712 09:28:35.735500 All Pass.
3713 09:28:35.735565
3714 09:28:35.735614 CH 1, Rank 1
3715 09:28:35.735661 SW Impedance : PASS
3716 09:28:35.735708 DUTY Scan : NO K
3717 09:28:35.735755 ZQ Calibration : PASS
3718 09:28:35.735803 Jitter Meter : NO K
3719 09:28:35.735850 CBT Training : PASS
3720 09:28:35.735898 Write leveling : PASS
3721 09:28:35.735945 RX DQS gating : PASS
3722 09:28:35.735992 RX DQ/DQS(RDDQC) : PASS
3723 09:28:35.736040 TX DQ/DQS : PASS
3724 09:28:35.736100 RX DATLAT : PASS
3725 09:28:35.736180 RX DQ/DQS(Engine): PASS
3726 09:28:35.736227 TX OE : NO K
3727 09:28:35.736275 All Pass.
3728 09:28:35.736322
3729 09:28:35.736369 DramC Write-DBI off
3730 09:28:35.736417 PER_BANK_REFRESH: Hybrid Mode
3731 09:28:35.736464 TX_TRACKING: ON
3732 09:28:35.736512 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3733 09:28:35.736592 [FAST_K] Save calibration result to emmc
3734 09:28:35.736687 dramc_set_vcore_voltage set vcore to 650000
3735 09:28:35.736738 Read voltage for 600, 5
3736 09:28:35.736786 Vio18 = 0
3737 09:28:35.736833 Vcore = 650000
3738 09:28:35.736881 Vdram = 0
3739 09:28:35.736928 Vddq = 0
3740 09:28:35.736976 Vmddr = 0
3741 09:28:35.737023 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3742 09:28:35.737072 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3743 09:28:35.737134 MEM_TYPE=3, freq_sel=19
3744 09:28:35.737183 sv_algorithm_assistance_LP4_1600
3745 09:28:35.737231 ============ PULL DRAM RESETB DOWN ============
3746 09:28:35.737306 ========== PULL DRAM RESETB DOWN end =========
3747 09:28:35.737355 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3748 09:28:35.737421 ===================================
3749 09:28:35.737512 LPDDR4 DRAM CONFIGURATION
3750 09:28:35.737602 ===================================
3751 09:28:35.737675 EX_ROW_EN[0] = 0x0
3752 09:28:35.737746 EX_ROW_EN[1] = 0x0
3753 09:28:35.737818 LP4Y_EN = 0x0
3754 09:28:35.737889 WORK_FSP = 0x0
3755 09:28:35.737953 WL = 0x2
3756 09:28:35.738003 RL = 0x2
3757 09:28:35.738051 BL = 0x2
3758 09:28:35.738099 RPST = 0x0
3759 09:28:35.738146 RD_PRE = 0x0
3760 09:28:35.738193 WR_PRE = 0x1
3761 09:28:35.738241 WR_PST = 0x0
3762 09:28:35.738288 DBI_WR = 0x0
3763 09:28:35.738335 DBI_RD = 0x0
3764 09:28:35.738382 OTF = 0x1
3765 09:28:35.738429 ===================================
3766 09:28:35.738477 ===================================
3767 09:28:35.738524 ANA top config
3768 09:28:35.738571 ===================================
3769 09:28:35.738618 DLL_ASYNC_EN = 0
3770 09:28:35.738666 ALL_SLAVE_EN = 1
3771 09:28:35.738728 NEW_RANK_MODE = 1
3772 09:28:35.738789 DLL_IDLE_MODE = 1
3773 09:28:35.738837 LP45_APHY_COMB_EN = 1
3774 09:28:35.738884 TX_ODT_DIS = 1
3775 09:28:35.738932 NEW_8X_MODE = 1
3776 09:28:35.738979 ===================================
3777 09:28:35.739027 ===================================
3778 09:28:35.739074 data_rate = 1200
3779 09:28:35.739135 CKR = 1
3780 09:28:35.739196 DQ_P2S_RATIO = 8
3781 09:28:35.739245 ===================================
3782 09:28:35.739293 CA_P2S_RATIO = 8
3783 09:28:35.739340 DQ_CA_OPEN = 0
3784 09:28:35.739387 DQ_SEMI_OPEN = 0
3785 09:28:35.739448 CA_SEMI_OPEN = 0
3786 09:28:35.739523 CA_FULL_RATE = 0
3787 09:28:35.739643 DQ_CKDIV4_EN = 1
3788 09:28:35.739720 CA_CKDIV4_EN = 1
3789 09:28:35.739794 CA_PREDIV_EN = 0
3790 09:28:35.739863 PH8_DLY = 0
3791 09:28:35.739912 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3792 09:28:35.739961 DQ_AAMCK_DIV = 4
3793 09:28:35.740008 CA_AAMCK_DIV = 4
3794 09:28:35.740055 CA_ADMCK_DIV = 4
3795 09:28:35.740103 DQ_TRACK_CA_EN = 0
3796 09:28:35.740150 CA_PICK = 600
3797 09:28:35.740198 CA_MCKIO = 600
3798 09:28:35.740246 MCKIO_SEMI = 0
3799 09:28:35.740293 PLL_FREQ = 2288
3800 09:28:35.740368 DQ_UI_PI_RATIO = 32
3801 09:28:35.740416 CA_UI_PI_RATIO = 0
3802 09:28:35.740674 ===================================
3803 09:28:35.740742 ===================================
3804 09:28:35.740791 memory_type:LPDDR4
3805 09:28:35.740838 GP_NUM : 10
3806 09:28:35.740886 SRAM_EN : 1
3807 09:28:35.740933 MD32_EN : 0
3808 09:28:35.740979 ===================================
3809 09:28:35.742215 [ANA_INIT] >>>>>>>>>>>>>>
3810 09:28:35.745779 <<<<<< [CONFIGURE PHASE]: ANA_TX
3811 09:28:35.748805 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3812 09:28:35.752358 ===================================
3813 09:28:35.755950 data_rate = 1200,PCW = 0X5800
3814 09:28:35.756030 ===================================
3815 09:28:35.762121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3816 09:28:35.765775 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3817 09:28:35.772012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3818 09:28:35.775736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3819 09:28:35.778949 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3820 09:28:35.782242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3821 09:28:35.785374 [ANA_INIT] flow start
3822 09:28:35.789122 [ANA_INIT] PLL >>>>>>>>
3823 09:28:35.789199 [ANA_INIT] PLL <<<<<<<<
3824 09:28:35.792496 [ANA_INIT] MIDPI >>>>>>>>
3825 09:28:35.795734 [ANA_INIT] MIDPI <<<<<<<<
3826 09:28:35.795811 [ANA_INIT] DLL >>>>>>>>
3827 09:28:35.798760 [ANA_INIT] flow end
3828 09:28:35.802348 ============ LP4 DIFF to SE enter ============
3829 09:28:35.805429 ============ LP4 DIFF to SE exit ============
3830 09:28:35.809247 [ANA_INIT] <<<<<<<<<<<<<
3831 09:28:35.812289 [Flow] Enable top DCM control >>>>>
3832 09:28:35.815251 [Flow] Enable top DCM control <<<<<
3833 09:28:35.818695 Enable DLL master slave shuffle
3834 09:28:35.825694 ==============================================================
3835 09:28:35.825778 Gating Mode config
3836 09:28:35.831804 ==============================================================
3837 09:28:35.831884 Config description:
3838 09:28:35.841790 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3839 09:28:35.848520 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3840 09:28:35.855245 SELPH_MODE 0: By rank 1: By Phase
3841 09:28:35.858752 ==============================================================
3842 09:28:35.861740 GAT_TRACK_EN = 1
3843 09:28:35.865350 RX_GATING_MODE = 2
3844 09:28:35.868523 RX_GATING_TRACK_MODE = 2
3845 09:28:35.871611 SELPH_MODE = 1
3846 09:28:35.874898 PICG_EARLY_EN = 1
3847 09:28:35.878590 VALID_LAT_VALUE = 1
3848 09:28:35.885427 ==============================================================
3849 09:28:35.888510 Enter into Gating configuration >>>>
3850 09:28:35.891636 Exit from Gating configuration <<<<
3851 09:28:35.894866 Enter into DVFS_PRE_config >>>>>
3852 09:28:35.904807 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3853 09:28:35.907984 Exit from DVFS_PRE_config <<<<<
3854 09:28:35.911714 Enter into PICG configuration >>>>
3855 09:28:35.915002 Exit from PICG configuration <<<<
3856 09:28:35.917933 [RX_INPUT] configuration >>>>>
3857 09:28:35.918008 [RX_INPUT] configuration <<<<<
3858 09:28:35.924759 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3859 09:28:35.931538 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3860 09:28:35.934886 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3861 09:28:35.941417 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3862 09:28:35.947690 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3863 09:28:35.954554 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3864 09:28:35.957648 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3865 09:28:35.961332 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3866 09:28:35.968046 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3867 09:28:35.971373 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3868 09:28:35.974321 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3869 09:28:35.980638 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 09:28:35.984308 ===================================
3871 09:28:35.984391 LPDDR4 DRAM CONFIGURATION
3872 09:28:35.987444 ===================================
3873 09:28:35.991257 EX_ROW_EN[0] = 0x0
3874 09:28:35.994417 EX_ROW_EN[1] = 0x0
3875 09:28:35.994485 LP4Y_EN = 0x0
3876 09:28:35.997616 WORK_FSP = 0x0
3877 09:28:35.997680 WL = 0x2
3878 09:28:36.000787 RL = 0x2
3879 09:28:36.000865 BL = 0x2
3880 09:28:36.004519 RPST = 0x0
3881 09:28:36.004581 RD_PRE = 0x0
3882 09:28:36.007668 WR_PRE = 0x1
3883 09:28:36.007743 WR_PST = 0x0
3884 09:28:36.010767 DBI_WR = 0x0
3885 09:28:36.010858 DBI_RD = 0x0
3886 09:28:36.013915 OTF = 0x1
3887 09:28:36.017573 ===================================
3888 09:28:36.020993 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3889 09:28:36.024301 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3890 09:28:36.030567 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3891 09:28:36.034095 ===================================
3892 09:28:36.034198 LPDDR4 DRAM CONFIGURATION
3893 09:28:36.037431 ===================================
3894 09:28:36.040815 EX_ROW_EN[0] = 0x10
3895 09:28:36.040899 EX_ROW_EN[1] = 0x0
3896 09:28:36.044242 LP4Y_EN = 0x0
3897 09:28:36.047113 WORK_FSP = 0x0
3898 09:28:36.047197 WL = 0x2
3899 09:28:36.050838 RL = 0x2
3900 09:28:36.050921 BL = 0x2
3901 09:28:36.053708 RPST = 0x0
3902 09:28:36.053771 RD_PRE = 0x0
3903 09:28:36.057446 WR_PRE = 0x1
3904 09:28:36.057524 WR_PST = 0x0
3905 09:28:36.060557 DBI_WR = 0x0
3906 09:28:36.060636 DBI_RD = 0x0
3907 09:28:36.063693 OTF = 0x1
3908 09:28:36.067340 ===================================
3909 09:28:36.074014 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3910 09:28:36.077025 nWR fixed to 30
3911 09:28:36.077116 [ModeRegInit_LP4] CH0 RK0
3912 09:28:36.080400 [ModeRegInit_LP4] CH0 RK1
3913 09:28:36.083652 [ModeRegInit_LP4] CH1 RK0
3914 09:28:36.083757 [ModeRegInit_LP4] CH1 RK1
3915 09:28:36.086779 match AC timing 17
3916 09:28:36.090586 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3917 09:28:36.096779 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3918 09:28:36.099918 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3919 09:28:36.103687 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3920 09:28:36.110490 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3921 09:28:36.110568 ==
3922 09:28:36.113588 Dram Type= 6, Freq= 0, CH_0, rank 0
3923 09:28:36.116705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3924 09:28:36.116810 ==
3925 09:28:36.123717 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3926 09:28:36.130103 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3927 09:28:36.133617 [CA 0] Center 37 (7~67) winsize 61
3928 09:28:36.136584 [CA 1] Center 37 (7~67) winsize 61
3929 09:28:36.139873 [CA 2] Center 35 (5~65) winsize 61
3930 09:28:36.143184 [CA 3] Center 35 (5~65) winsize 61
3931 09:28:36.146799 [CA 4] Center 34 (4~65) winsize 62
3932 09:28:36.149724 [CA 5] Center 34 (4~64) winsize 61
3933 09:28:36.149829
3934 09:28:36.153457 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3935 09:28:36.153535
3936 09:28:36.156420 [CATrainingPosCal] consider 1 rank data
3937 09:28:36.159724 u2DelayCellTimex100 = 270/100 ps
3938 09:28:36.162959 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3939 09:28:36.166503 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3940 09:28:36.169856 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3941 09:28:36.172769 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3942 09:28:36.176163 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3943 09:28:36.179769 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3944 09:28:36.179847
3945 09:28:36.186541 CA PerBit enable=1, Macro0, CA PI delay=34
3946 09:28:36.186619
3947 09:28:36.186680 [CBTSetCACLKResult] CA Dly = 34
3948 09:28:36.189375 CS Dly: 6 (0~37)
3949 09:28:36.189454 ==
3950 09:28:36.192695 Dram Type= 6, Freq= 0, CH_0, rank 1
3951 09:28:36.196205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 09:28:36.196288 ==
3953 09:28:36.202918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3954 09:28:36.209690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3955 09:28:36.212805 [CA 0] Center 37 (7~67) winsize 61
3956 09:28:36.216016 [CA 1] Center 37 (7~67) winsize 61
3957 09:28:36.219122 [CA 2] Center 35 (5~65) winsize 61
3958 09:28:36.222895 [CA 3] Center 35 (5~65) winsize 61
3959 09:28:36.226124 [CA 4] Center 34 (4~65) winsize 62
3960 09:28:36.229250 [CA 5] Center 33 (3~64) winsize 62
3961 09:28:36.229336
3962 09:28:36.232450 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3963 09:28:36.232550
3964 09:28:36.235630 [CATrainingPosCal] consider 2 rank data
3965 09:28:36.239413 u2DelayCellTimex100 = 270/100 ps
3966 09:28:36.242618 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3967 09:28:36.245804 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3968 09:28:36.248823 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3969 09:28:36.252485 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3970 09:28:36.255863 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3971 09:28:36.261965 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3972 09:28:36.262056
3973 09:28:36.265319 CA PerBit enable=1, Macro0, CA PI delay=34
3974 09:28:36.265401
3975 09:28:36.268987 [CBTSetCACLKResult] CA Dly = 34
3976 09:28:36.269062 CS Dly: 6 (0~38)
3977 09:28:36.269151
3978 09:28:36.272141 ----->DramcWriteLeveling(PI) begin...
3979 09:28:36.272216 ==
3980 09:28:36.275691 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 09:28:36.281977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 09:28:36.282057 ==
3983 09:28:36.285331 Write leveling (Byte 0): 34 => 34
3984 09:28:36.285406 Write leveling (Byte 1): 31 => 31
3985 09:28:36.288543 DramcWriteLeveling(PI) end<-----
3986 09:28:36.288642
3987 09:28:36.291765 ==
3988 09:28:36.295295 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 09:28:36.298679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 09:28:36.298751 ==
3991 09:28:36.301800 [Gating] SW mode calibration
3992 09:28:36.308335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3993 09:28:36.311784 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3994 09:28:36.318699 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 09:28:36.321792 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 09:28:36.324900 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 09:28:36.331808 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3998 09:28:36.334990 0 9 16 | B1->B0 | 3333 2c2c | 0 0 | (0 1) (1 1)
3999 09:28:36.338137 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4000 09:28:36.345018 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 09:28:36.348164 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 09:28:36.351943 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 09:28:36.358286 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 09:28:36.361470 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 09:28:36.365063 0 10 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
4006 09:28:36.371621 0 10 16 | B1->B0 | 2f2f 3939 | 0 1 | (0 0) (0 0)
4007 09:28:36.374950 0 10 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4008 09:28:36.377808 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 09:28:36.384613 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 09:28:36.388226 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 09:28:36.391192 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 09:28:36.398056 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 09:28:36.400993 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4014 09:28:36.404482 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 09:28:36.410915 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4016 09:28:36.414633 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 09:28:36.417699 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 09:28:36.420990 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 09:28:36.427731 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 09:28:36.431220 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 09:28:36.434422 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 09:28:36.441335 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 09:28:36.444376 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 09:28:36.447491 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 09:28:36.454306 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 09:28:36.457923 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 09:28:36.461160 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 09:28:36.467377 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 09:28:36.471145 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4030 09:28:36.474332 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4031 09:28:36.477273 Total UI for P1: 0, mck2ui 16
4032 09:28:36.480793 best dqsien dly found for B0: ( 0, 13, 12)
4033 09:28:36.487672 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 09:28:36.487755 Total UI for P1: 0, mck2ui 16
4035 09:28:36.494259 best dqsien dly found for B1: ( 0, 13, 16)
4036 09:28:36.497306 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4037 09:28:36.500451 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4038 09:28:36.500557
4039 09:28:36.504260 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4040 09:28:36.507340 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4041 09:28:36.511155 [Gating] SW calibration Done
4042 09:28:36.511235 ==
4043 09:28:36.514326 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 09:28:36.517246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 09:28:36.517325 ==
4046 09:28:36.520744 RX Vref Scan: 0
4047 09:28:36.520824
4048 09:28:36.520885 RX Vref 0 -> 0, step: 1
4049 09:28:36.520941
4050 09:28:36.524169 RX Delay -230 -> 252, step: 16
4051 09:28:36.530893 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4052 09:28:36.533741 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4053 09:28:36.537120 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4054 09:28:36.540543 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4055 09:28:36.547005 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4056 09:28:36.550673 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4057 09:28:36.553722 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4058 09:28:36.556966 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4059 09:28:36.560714 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4060 09:28:36.566987 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4061 09:28:36.570127 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4062 09:28:36.573857 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4063 09:28:36.576950 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4064 09:28:36.583843 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4065 09:28:36.586848 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4066 09:28:36.590313 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4067 09:28:36.590391 ==
4068 09:28:36.593205 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 09:28:36.596592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 09:28:36.600019 ==
4071 09:28:36.600093 DQS Delay:
4072 09:28:36.600154 DQS0 = 0, DQS1 = 0
4073 09:28:36.603421 DQM Delay:
4074 09:28:36.603500 DQM0 = 38, DQM1 = 28
4075 09:28:36.606655 DQ Delay:
4076 09:28:36.610364 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4077 09:28:36.610439 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4078 09:28:36.613428 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4079 09:28:36.616520 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4080 09:28:36.620192
4081 09:28:36.620275
4082 09:28:36.620338 ==
4083 09:28:36.623130 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 09:28:36.626775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 09:28:36.626859 ==
4086 09:28:36.626921
4087 09:28:36.626977
4088 09:28:36.629846 TX Vref Scan disable
4089 09:28:36.629915 == TX Byte 0 ==
4090 09:28:36.636518 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4091 09:28:36.639891 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4092 09:28:36.639980 == TX Byte 1 ==
4093 09:28:36.646161 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4094 09:28:36.649671 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4095 09:28:36.649772 ==
4096 09:28:36.653030 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 09:28:36.656429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 09:28:36.656529 ==
4099 09:28:36.656615
4100 09:28:36.656710
4101 09:28:36.659949 TX Vref Scan disable
4102 09:28:36.663043 == TX Byte 0 ==
4103 09:28:36.666204 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4104 09:28:36.673003 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4105 09:28:36.673082 == TX Byte 1 ==
4106 09:28:36.676210 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4107 09:28:36.682885 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4108 09:28:36.682963
4109 09:28:36.683025 [DATLAT]
4110 09:28:36.683081 Freq=600, CH0 RK0
4111 09:28:36.683135
4112 09:28:36.685929 DATLAT Default: 0x9
4113 09:28:36.689148 0, 0xFFFF, sum = 0
4114 09:28:36.689229 1, 0xFFFF, sum = 0
4115 09:28:36.692842 2, 0xFFFF, sum = 0
4116 09:28:36.692920 3, 0xFFFF, sum = 0
4117 09:28:36.695966 4, 0xFFFF, sum = 0
4118 09:28:36.696045 5, 0xFFFF, sum = 0
4119 09:28:36.699657 6, 0xFFFF, sum = 0
4120 09:28:36.699738 7, 0xFFFF, sum = 0
4121 09:28:36.702638 8, 0x0, sum = 1
4122 09:28:36.702714 9, 0x0, sum = 2
4123 09:28:36.702780 10, 0x0, sum = 3
4124 09:28:36.705965 11, 0x0, sum = 4
4125 09:28:36.706070 best_step = 9
4126 09:28:36.706158
4127 09:28:36.706241 ==
4128 09:28:36.709314 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 09:28:36.715746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 09:28:36.715826 ==
4131 09:28:36.715892 RX Vref Scan: 1
4132 09:28:36.715950
4133 09:28:36.719530 RX Vref 0 -> 0, step: 1
4134 09:28:36.719606
4135 09:28:36.722703 RX Delay -195 -> 252, step: 8
4136 09:28:36.722773
4137 09:28:36.725679 Set Vref, RX VrefLevel [Byte0]: 61
4138 09:28:36.729319 [Byte1]: 52
4139 09:28:36.729394
4140 09:28:36.732328 Final RX Vref Byte 0 = 61 to rank0
4141 09:28:36.735451 Final RX Vref Byte 1 = 52 to rank0
4142 09:28:36.739263 Final RX Vref Byte 0 = 61 to rank1
4143 09:28:36.742444 Final RX Vref Byte 1 = 52 to rank1==
4144 09:28:36.745456 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 09:28:36.748820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 09:28:36.748900 ==
4147 09:28:36.752246 DQS Delay:
4148 09:28:36.752324 DQS0 = 0, DQS1 = 0
4149 09:28:36.755807 DQM Delay:
4150 09:28:36.755884 DQM0 = 33, DQM1 = 29
4151 09:28:36.755945 DQ Delay:
4152 09:28:36.758707 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =32
4153 09:28:36.762153 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4154 09:28:36.765709 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4155 09:28:36.769150 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4156 09:28:36.769230
4157 09:28:36.769291
4158 09:28:36.779214 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4159 09:28:36.782195 CH0 RK0: MR19=808, MR18=3F3E
4160 09:28:36.788523 CH0_RK0: MR19=0x808, MR18=0x3F3E, DQSOSC=397, MR23=63, INC=166, DEC=110
4161 09:28:36.788612
4162 09:28:36.792207 ----->DramcWriteLeveling(PI) begin...
4163 09:28:36.792288 ==
4164 09:28:36.795337 Dram Type= 6, Freq= 0, CH_0, rank 1
4165 09:28:36.798911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 09:28:36.799013 ==
4167 09:28:36.802014 Write leveling (Byte 0): 34 => 34
4168 09:28:36.805132 Write leveling (Byte 1): 31 => 31
4169 09:28:36.808819 DramcWriteLeveling(PI) end<-----
4170 09:28:36.808898
4171 09:28:36.808959 ==
4172 09:28:36.811873 Dram Type= 6, Freq= 0, CH_0, rank 1
4173 09:28:36.815364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 09:28:36.815447 ==
4175 09:28:36.818272 [Gating] SW mode calibration
4176 09:28:36.825364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4177 09:28:36.831625 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4178 09:28:36.835335 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 09:28:36.838301 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 09:28:36.845172 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 09:28:36.848426 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
4182 09:28:36.851484 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4183 09:28:36.858368 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 09:28:36.861851 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 09:28:36.864912 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 09:28:36.871361 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 09:28:36.874773 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 09:28:36.878290 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 09:28:36.884777 0 10 12 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0)
4190 09:28:36.887802 0 10 16 | B1->B0 | 3636 4646 | 1 0 | (1 1) (0 0)
4191 09:28:36.891523 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 09:28:36.897793 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 09:28:36.901419 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 09:28:36.904523 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 09:28:36.911445 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 09:28:36.914716 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 09:28:36.917697 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 09:28:36.924184 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4199 09:28:36.927680 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 09:28:36.931172 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 09:28:36.937893 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 09:28:36.940906 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 09:28:36.944492 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 09:28:36.951270 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 09:28:36.954418 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 09:28:36.957628 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 09:28:36.964230 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 09:28:36.967753 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 09:28:36.971041 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 09:28:36.977425 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 09:28:36.980969 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 09:28:36.984079 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 09:28:36.990510 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4214 09:28:36.990594 Total UI for P1: 0, mck2ui 16
4215 09:28:36.994195 best dqsien dly found for B0: ( 0, 13, 10)
4216 09:28:37.000502 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 09:28:37.004216 Total UI for P1: 0, mck2ui 16
4218 09:28:37.007247 best dqsien dly found for B1: ( 0, 13, 14)
4219 09:28:37.010364 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4220 09:28:37.013941 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4221 09:28:37.014011
4222 09:28:37.017170 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4223 09:28:37.020828 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4224 09:28:37.023796 [Gating] SW calibration Done
4225 09:28:37.023867 ==
4226 09:28:37.027487 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 09:28:37.030652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 09:28:37.030726 ==
4229 09:28:37.033768 RX Vref Scan: 0
4230 09:28:37.033845
4231 09:28:37.037255 RX Vref 0 -> 0, step: 1
4232 09:28:37.037326
4233 09:28:37.037385 RX Delay -230 -> 252, step: 16
4234 09:28:37.043880 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4235 09:28:37.046964 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4236 09:28:37.050470 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4237 09:28:37.054132 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4238 09:28:37.060360 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4239 09:28:37.064000 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4240 09:28:37.067134 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4241 09:28:37.070293 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4242 09:28:37.073945 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4243 09:28:37.080400 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4244 09:28:37.083710 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4245 09:28:37.086831 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4246 09:28:37.090612 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4247 09:28:37.096985 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4248 09:28:37.100493 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4249 09:28:37.103608 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4250 09:28:37.103718 ==
4251 09:28:37.106673 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 09:28:37.113440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 09:28:37.113529 ==
4254 09:28:37.113601 DQS Delay:
4255 09:28:37.113686 DQS0 = 0, DQS1 = 0
4256 09:28:37.116631 DQM Delay:
4257 09:28:37.116715 DQM0 = 38, DQM1 = 29
4258 09:28:37.120384 DQ Delay:
4259 09:28:37.123511 DQ0 =41, DQ1 =33, DQ2 =41, DQ3 =33
4260 09:28:37.123610 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4261 09:28:37.127082 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4262 09:28:37.133216 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4263 09:28:37.133299
4264 09:28:37.133360
4265 09:28:37.133416 ==
4266 09:28:37.136987 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 09:28:37.140291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 09:28:37.140388 ==
4269 09:28:37.140471
4270 09:28:37.140550
4271 09:28:37.143286 TX Vref Scan disable
4272 09:28:37.143412 == TX Byte 0 ==
4273 09:28:37.150278 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4274 09:28:37.153406 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4275 09:28:37.153484 == TX Byte 1 ==
4276 09:28:37.160216 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4277 09:28:37.163219 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4278 09:28:37.163298 ==
4279 09:28:37.166392 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 09:28:37.170114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 09:28:37.170203 ==
4282 09:28:37.170265
4283 09:28:37.173264
4284 09:28:37.173340 TX Vref Scan disable
4285 09:28:37.176963 == TX Byte 0 ==
4286 09:28:37.180078 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4287 09:28:37.186348 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4288 09:28:37.186425 == TX Byte 1 ==
4289 09:28:37.190038 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4290 09:28:37.196848 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4291 09:28:37.196926
4292 09:28:37.196986 [DATLAT]
4293 09:28:37.197041 Freq=600, CH0 RK1
4294 09:28:37.197094
4295 09:28:37.199736 DATLAT Default: 0x9
4296 09:28:37.199812 0, 0xFFFF, sum = 0
4297 09:28:37.203139 1, 0xFFFF, sum = 0
4298 09:28:37.203256 2, 0xFFFF, sum = 0
4299 09:28:37.206602 3, 0xFFFF, sum = 0
4300 09:28:37.210179 4, 0xFFFF, sum = 0
4301 09:28:37.210257 5, 0xFFFF, sum = 0
4302 09:28:37.213086 6, 0xFFFF, sum = 0
4303 09:28:37.213170 7, 0xFFFF, sum = 0
4304 09:28:37.216467 8, 0x0, sum = 1
4305 09:28:37.216560 9, 0x0, sum = 2
4306 09:28:37.216665 10, 0x0, sum = 3
4307 09:28:37.219999 11, 0x0, sum = 4
4308 09:28:37.220089 best_step = 9
4309 09:28:37.220148
4310 09:28:37.220206 ==
4311 09:28:37.223120 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 09:28:37.230031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 09:28:37.230154 ==
4314 09:28:37.230214 RX Vref Scan: 0
4315 09:28:37.230268
4316 09:28:37.233057 RX Vref 0 -> 0, step: 1
4317 09:28:37.233132
4318 09:28:37.236251 RX Delay -195 -> 252, step: 8
4319 09:28:37.239289 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4320 09:28:37.246274 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4321 09:28:37.249285 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4322 09:28:37.252782 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4323 09:28:37.256119 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4324 09:28:37.262644 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4325 09:28:37.266434 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4326 09:28:37.269701 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4327 09:28:37.272777 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4328 09:28:37.275808 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4329 09:28:37.282782 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4330 09:28:37.285929 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4331 09:28:37.289562 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4332 09:28:37.292617 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4333 09:28:37.299182 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4334 09:28:37.302653 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4335 09:28:37.302730 ==
4336 09:28:37.305760 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 09:28:37.309242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 09:28:37.309319 ==
4339 09:28:37.312222 DQS Delay:
4340 09:28:37.312295 DQS0 = 0, DQS1 = 0
4341 09:28:37.315731 DQM Delay:
4342 09:28:37.315825 DQM0 = 34, DQM1 = 28
4343 09:28:37.315916 DQ Delay:
4344 09:28:37.318913 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4345 09:28:37.322421 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4346 09:28:37.325782 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4347 09:28:37.328741 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4348 09:28:37.328827
4349 09:28:37.328883
4350 09:28:37.338688 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4351 09:28:37.342240 CH0 RK1: MR19=808, MR18=6D3D
4352 09:28:37.345978 CH0_RK1: MR19=0x808, MR18=0x6D3D, DQSOSC=389, MR23=63, INC=173, DEC=115
4353 09:28:37.349157 [RxdqsGatingPostProcess] freq 600
4354 09:28:37.355494 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4355 09:28:37.359122 Pre-setting of DQS Precalculation
4356 09:28:37.362494 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4357 09:28:37.362572 ==
4358 09:28:37.365401 Dram Type= 6, Freq= 0, CH_1, rank 0
4359 09:28:37.372527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 09:28:37.372631 ==
4361 09:28:37.375720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4362 09:28:37.381940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4363 09:28:37.385676 [CA 0] Center 35 (5~66) winsize 62
4364 09:28:37.388764 [CA 1] Center 36 (6~66) winsize 61
4365 09:28:37.392550 [CA 2] Center 34 (4~65) winsize 62
4366 09:28:37.395744 [CA 3] Center 34 (4~65) winsize 62
4367 09:28:37.398816 [CA 4] Center 34 (4~65) winsize 62
4368 09:28:37.401840 [CA 5] Center 34 (4~64) winsize 61
4369 09:28:37.401916
4370 09:28:37.405265 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4371 09:28:37.405332
4372 09:28:37.408630 [CATrainingPosCal] consider 1 rank data
4373 09:28:37.412223 u2DelayCellTimex100 = 270/100 ps
4374 09:28:37.415292 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4375 09:28:37.421837 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4376 09:28:37.425508 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4377 09:28:37.428587 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4378 09:28:37.431652 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4379 09:28:37.435305 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4380 09:28:37.435375
4381 09:28:37.438368 CA PerBit enable=1, Macro0, CA PI delay=34
4382 09:28:37.438433
4383 09:28:37.442097 [CBTSetCACLKResult] CA Dly = 34
4384 09:28:37.442194 CS Dly: 5 (0~36)
4385 09:28:37.445009 ==
4386 09:28:37.448632 Dram Type= 6, Freq= 0, CH_1, rank 1
4387 09:28:37.451670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 09:28:37.451779 ==
4389 09:28:37.455329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 09:28:37.461436 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4391 09:28:37.465731 [CA 0] Center 36 (6~66) winsize 61
4392 09:28:37.468801 [CA 1] Center 36 (5~67) winsize 63
4393 09:28:37.472171 [CA 2] Center 34 (4~65) winsize 62
4394 09:28:37.475669 [CA 3] Center 34 (3~65) winsize 63
4395 09:28:37.478673 [CA 4] Center 34 (4~65) winsize 62
4396 09:28:37.482373 [CA 5] Center 33 (3~64) winsize 62
4397 09:28:37.482447
4398 09:28:37.485420 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4399 09:28:37.485486
4400 09:28:37.489168 [CATrainingPosCal] consider 2 rank data
4401 09:28:37.492204 u2DelayCellTimex100 = 270/100 ps
4402 09:28:37.495376 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4403 09:28:37.498997 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4404 09:28:37.505808 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4405 09:28:37.508953 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4406 09:28:37.512347 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4407 09:28:37.515220 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4408 09:28:37.515291
4409 09:28:37.518780 CA PerBit enable=1, Macro0, CA PI delay=34
4410 09:28:37.518881
4411 09:28:37.522377 [CBTSetCACLKResult] CA Dly = 34
4412 09:28:37.522454 CS Dly: 5 (0~36)
4413 09:28:37.522531
4414 09:28:37.528649 ----->DramcWriteLeveling(PI) begin...
4415 09:28:37.528736 ==
4416 09:28:37.532262 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 09:28:37.535232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 09:28:37.535318 ==
4419 09:28:37.538855 Write leveling (Byte 0): 30 => 30
4420 09:28:37.541813 Write leveling (Byte 1): 31 => 31
4421 09:28:37.545547 DramcWriteLeveling(PI) end<-----
4422 09:28:37.545626
4423 09:28:37.545686 ==
4424 09:28:37.548623 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 09:28:37.552299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 09:28:37.552372 ==
4427 09:28:37.555261 [Gating] SW mode calibration
4428 09:28:37.562063 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4429 09:28:37.568354 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4430 09:28:37.572154 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4431 09:28:37.575033 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4432 09:28:37.581931 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 09:28:37.584962 0 9 12 | B1->B0 | 3333 3030 | 0 1 | (0 0) (1 0)
4434 09:28:37.588454 0 9 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4435 09:28:37.592172 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 09:28:37.598378 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 09:28:37.601541 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 09:28:37.604827 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 09:28:37.611820 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 09:28:37.615014 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 09:28:37.618498 0 10 12 | B1->B0 | 3131 2b2b | 0 1 | (0 0) (0 0)
4442 09:28:37.625181 0 10 16 | B1->B0 | 3b3b 3d3d | 0 1 | (1 1) (0 0)
4443 09:28:37.628182 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 09:28:37.631838 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 09:28:37.638653 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 09:28:37.641770 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 09:28:37.645140 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 09:28:37.651876 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 09:28:37.655153 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 09:28:37.658211 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 09:28:37.664848 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 09:28:37.668413 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 09:28:37.671496 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 09:28:37.678374 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 09:28:37.681411 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 09:28:37.684798 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 09:28:37.691296 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 09:28:37.694875 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 09:28:37.697907 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 09:28:37.704409 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 09:28:37.708180 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 09:28:37.711351 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 09:28:37.718128 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 09:28:37.721301 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 09:28:37.724391 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 09:28:37.730999 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 09:28:37.731116 Total UI for P1: 0, mck2ui 16
4468 09:28:37.734165 best dqsien dly found for B0: ( 0, 13, 14)
4469 09:28:37.737747 Total UI for P1: 0, mck2ui 16
4470 09:28:37.741235 best dqsien dly found for B1: ( 0, 13, 14)
4471 09:28:37.747595 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4472 09:28:37.751168 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4473 09:28:37.751276
4474 09:28:37.754119 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4475 09:28:37.757637 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4476 09:28:37.760676 [Gating] SW calibration Done
4477 09:28:37.760791 ==
4478 09:28:37.764396 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 09:28:37.767542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 09:28:37.767647 ==
4481 09:28:37.771183 RX Vref Scan: 0
4482 09:28:37.771286
4483 09:28:37.771376 RX Vref 0 -> 0, step: 1
4484 09:28:37.771463
4485 09:28:37.774360 RX Delay -230 -> 252, step: 16
4486 09:28:37.777470 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4487 09:28:37.784472 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4488 09:28:37.787522 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4489 09:28:37.791122 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4490 09:28:37.793998 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4491 09:28:37.801666 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4492 09:28:37.804112 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4493 09:28:37.807701 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4494 09:28:37.811127 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4495 09:28:37.814146 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4496 09:28:37.820962 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4497 09:28:37.824110 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4498 09:28:37.827798 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4499 09:28:37.830796 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4500 09:28:37.837660 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4501 09:28:37.840755 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4502 09:28:37.840859 ==
4503 09:28:37.844435 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 09:28:37.847407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 09:28:37.847511 ==
4506 09:28:37.851051 DQS Delay:
4507 09:28:37.851186 DQS0 = 0, DQS1 = 0
4508 09:28:37.851275 DQM Delay:
4509 09:28:37.853976 DQM0 = 38, DQM1 = 28
4510 09:28:37.854074 DQ Delay:
4511 09:28:37.857527 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4512 09:28:37.860558 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4513 09:28:37.864117 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4514 09:28:37.867564 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4515 09:28:37.867663
4516 09:28:37.867751
4517 09:28:37.867838 ==
4518 09:28:37.870541 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 09:28:37.877090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 09:28:37.877195 ==
4521 09:28:37.877282
4522 09:28:37.877369
4523 09:28:37.877457 TX Vref Scan disable
4524 09:28:37.880871 == TX Byte 0 ==
4525 09:28:37.884008 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4526 09:28:37.890949 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4527 09:28:37.891053 == TX Byte 1 ==
4528 09:28:37.894026 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4529 09:28:37.900545 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4530 09:28:37.900669 ==
4531 09:28:37.904031 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 09:28:37.907680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 09:28:37.907782 ==
4534 09:28:37.907874
4535 09:28:37.907960
4536 09:28:37.910824 TX Vref Scan disable
4537 09:28:37.913840 == TX Byte 0 ==
4538 09:28:37.917453 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4539 09:28:37.920541 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4540 09:28:37.924242 == TX Byte 1 ==
4541 09:28:37.927335 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4542 09:28:37.930958 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4543 09:28:37.931064
4544 09:28:37.931153 [DATLAT]
4545 09:28:37.934030 Freq=600, CH1 RK0
4546 09:28:37.934132
4547 09:28:37.934221 DATLAT Default: 0x9
4548 09:28:37.936977 0, 0xFFFF, sum = 0
4549 09:28:37.940876 1, 0xFFFF, sum = 0
4550 09:28:37.940977 2, 0xFFFF, sum = 0
4551 09:28:37.944001 3, 0xFFFF, sum = 0
4552 09:28:37.944105 4, 0xFFFF, sum = 0
4553 09:28:37.947079 5, 0xFFFF, sum = 0
4554 09:28:37.947183 6, 0xFFFF, sum = 0
4555 09:28:37.950643 7, 0xFFFF, sum = 0
4556 09:28:37.950744 8, 0x0, sum = 1
4557 09:28:37.953623 9, 0x0, sum = 2
4558 09:28:37.953725 10, 0x0, sum = 3
4559 09:28:37.953816 11, 0x0, sum = 4
4560 09:28:37.957304 best_step = 9
4561 09:28:37.957405
4562 09:28:37.957495 ==
4563 09:28:37.960230 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 09:28:37.963846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 09:28:37.963950 ==
4566 09:28:37.966861 RX Vref Scan: 1
4567 09:28:37.966963
4568 09:28:37.967052 RX Vref 0 -> 0, step: 1
4569 09:28:37.970434
4570 09:28:37.970532 RX Delay -195 -> 252, step: 8
4571 09:28:37.970623
4572 09:28:37.973560 Set Vref, RX VrefLevel [Byte0]: 54
4573 09:28:37.976609 [Byte1]: 48
4574 09:28:37.981326
4575 09:28:37.981426 Final RX Vref Byte 0 = 54 to rank0
4576 09:28:37.984459 Final RX Vref Byte 1 = 48 to rank0
4577 09:28:37.988151 Final RX Vref Byte 0 = 54 to rank1
4578 09:28:37.991218 Final RX Vref Byte 1 = 48 to rank1==
4579 09:28:37.994391 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 09:28:38.001277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 09:28:38.001380 ==
4582 09:28:38.001471 DQS Delay:
4583 09:28:38.001558 DQS0 = 0, DQS1 = 0
4584 09:28:38.004281 DQM Delay:
4585 09:28:38.004379 DQM0 = 39, DQM1 = 28
4586 09:28:38.007925 DQ Delay:
4587 09:28:38.011296 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4588 09:28:38.014353 DQ4 =36, DQ5 =44, DQ6 =52, DQ7 =36
4589 09:28:38.017950 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =20
4590 09:28:38.020867 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4591 09:28:38.020968
4592 09:28:38.021060
4593 09:28:38.027615 [DQSOSCAuto] RK0, (LSB)MR18= 0x2531, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4594 09:28:38.031390 CH1 RK0: MR19=808, MR18=2531
4595 09:28:38.037634 CH1_RK0: MR19=0x808, MR18=0x2531, DQSOSC=400, MR23=63, INC=163, DEC=109
4596 09:28:38.037740
4597 09:28:38.041341 ----->DramcWriteLeveling(PI) begin...
4598 09:28:38.041444 ==
4599 09:28:38.044333 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 09:28:38.047503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 09:28:38.047607 ==
4602 09:28:38.051282 Write leveling (Byte 0): 29 => 29
4603 09:28:38.054407 Write leveling (Byte 1): 29 => 29
4604 09:28:38.057829 DramcWriteLeveling(PI) end<-----
4605 09:28:38.057929
4606 09:28:38.058019 ==
4607 09:28:38.060946 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 09:28:38.064549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 09:28:38.064659 ==
4610 09:28:38.067562 [Gating] SW mode calibration
4611 09:28:38.074036 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4612 09:28:38.080928 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4613 09:28:38.084606 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4614 09:28:38.091022 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4615 09:28:38.094345 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4616 09:28:38.097448 0 9 12 | B1->B0 | 2f2f 2a2a | 1 1 | (1 1) (1 0)
4617 09:28:38.101256 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4618 09:28:38.107485 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 09:28:38.111259 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 09:28:38.114317 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 09:28:38.120929 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 09:28:38.123947 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 09:28:38.127763 0 10 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
4624 09:28:38.134158 0 10 12 | B1->B0 | 2b2b 3e3e | 0 0 | (1 1) (0 0)
4625 09:28:38.137292 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4626 09:28:38.140920 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 09:28:38.147693 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 09:28:38.150840 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 09:28:38.153979 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 09:28:38.160860 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 09:28:38.163874 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 09:28:38.167439 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4633 09:28:38.174040 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4634 09:28:38.177008 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 09:28:38.180651 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 09:28:38.186819 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 09:28:38.190482 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 09:28:38.193571 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 09:28:38.200308 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 09:28:38.203474 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 09:28:38.207313 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 09:28:38.213511 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 09:28:38.216640 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 09:28:38.220247 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 09:28:38.227104 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 09:28:38.230173 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 09:28:38.233862 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4648 09:28:38.240367 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 09:28:38.240475 Total UI for P1: 0, mck2ui 16
4650 09:28:38.243248 best dqsien dly found for B0: ( 0, 13, 8)
4651 09:28:38.246748 Total UI for P1: 0, mck2ui 16
4652 09:28:38.250424 best dqsien dly found for B1: ( 0, 13, 10)
4653 09:28:38.256534 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4654 09:28:38.260255 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4655 09:28:38.260363
4656 09:28:38.263379 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4657 09:28:38.266456 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4658 09:28:38.269882 [Gating] SW calibration Done
4659 09:28:38.269986 ==
4660 09:28:38.273420 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 09:28:38.276571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 09:28:38.276677 ==
4663 09:28:38.280065 RX Vref Scan: 0
4664 09:28:38.280167
4665 09:28:38.280257 RX Vref 0 -> 0, step: 1
4666 09:28:38.280346
4667 09:28:38.283426 RX Delay -230 -> 252, step: 16
4668 09:28:38.286266 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4669 09:28:38.293050 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4670 09:28:38.296021 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4671 09:28:38.299851 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4672 09:28:38.302898 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4673 09:28:38.309721 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4674 09:28:38.312839 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4675 09:28:38.315993 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4676 09:28:38.319194 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4677 09:28:38.322952 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4678 09:28:38.329545 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4679 09:28:38.332503 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4680 09:28:38.335999 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4681 09:28:38.339658 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4682 09:28:38.345867 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4683 09:28:38.349573 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4684 09:28:38.349680 ==
4685 09:28:38.352481 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 09:28:38.356024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 09:28:38.356127 ==
4688 09:28:38.358804 DQS Delay:
4689 09:28:38.358905 DQS0 = 0, DQS1 = 0
4690 09:28:38.362278 DQM Delay:
4691 09:28:38.362381 DQM0 = 35, DQM1 = 29
4692 09:28:38.362469 DQ Delay:
4693 09:28:38.365958 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4694 09:28:38.369122 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4695 09:28:38.372183 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4696 09:28:38.375738 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4697 09:28:38.375838
4698 09:28:38.375925
4699 09:28:38.378813 ==
4700 09:28:38.382523 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 09:28:38.385480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 09:28:38.385580 ==
4703 09:28:38.385698
4704 09:28:38.385788
4705 09:28:38.388444 TX Vref Scan disable
4706 09:28:38.388542 == TX Byte 0 ==
4707 09:28:38.395571 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4708 09:28:38.398660 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4709 09:28:38.398741 == TX Byte 1 ==
4710 09:28:38.405561 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4711 09:28:38.408638 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4712 09:28:38.408734 ==
4713 09:28:38.411755 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 09:28:38.415485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 09:28:38.415563 ==
4716 09:28:38.415634
4717 09:28:38.415691
4718 09:28:38.418565 TX Vref Scan disable
4719 09:28:38.421658 == TX Byte 0 ==
4720 09:28:38.424849 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4721 09:28:38.428562 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4722 09:28:38.431658 == TX Byte 1 ==
4723 09:28:38.435285 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4724 09:28:38.438459 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4725 09:28:38.438553
4726 09:28:38.441916 [DATLAT]
4727 09:28:38.441995 Freq=600, CH1 RK1
4728 09:28:38.442080
4729 09:28:38.445179 DATLAT Default: 0x9
4730 09:28:38.445251 0, 0xFFFF, sum = 0
4731 09:28:38.448266 1, 0xFFFF, sum = 0
4732 09:28:38.448362 2, 0xFFFF, sum = 0
4733 09:28:38.451857 3, 0xFFFF, sum = 0
4734 09:28:38.451952 4, 0xFFFF, sum = 0
4735 09:28:38.454987 5, 0xFFFF, sum = 0
4736 09:28:38.455052 6, 0xFFFF, sum = 0
4737 09:28:38.458235 7, 0xFFFF, sum = 0
4738 09:28:38.458323 8, 0x0, sum = 1
4739 09:28:38.461896 9, 0x0, sum = 2
4740 09:28:38.461961 10, 0x0, sum = 3
4741 09:28:38.464762 11, 0x0, sum = 4
4742 09:28:38.464831 best_step = 9
4743 09:28:38.464889
4744 09:28:38.464941 ==
4745 09:28:38.468128 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 09:28:38.474656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 09:28:38.474726 ==
4748 09:28:38.474782 RX Vref Scan: 0
4749 09:28:38.474849
4750 09:28:38.478387 RX Vref 0 -> 0, step: 1
4751 09:28:38.478448
4752 09:28:38.481361 RX Delay -195 -> 252, step: 8
4753 09:28:38.484808 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4754 09:28:38.491321 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4755 09:28:38.494947 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4756 09:28:38.498095 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4757 09:28:38.501523 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4758 09:28:38.504903 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4759 09:28:38.511667 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4760 09:28:38.514723 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4761 09:28:38.517800 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4762 09:28:38.521480 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4763 09:28:38.528024 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4764 09:28:38.531188 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4765 09:28:38.534234 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4766 09:28:38.537737 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4767 09:28:38.544531 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4768 09:28:38.547571 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4769 09:28:38.547642 ==
4770 09:28:38.551154 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 09:28:38.554503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 09:28:38.554573 ==
4773 09:28:38.557533 DQS Delay:
4774 09:28:38.557629 DQS0 = 0, DQS1 = 0
4775 09:28:38.557700 DQM Delay:
4776 09:28:38.561312 DQM0 = 36, DQM1 = 31
4777 09:28:38.561387 DQ Delay:
4778 09:28:38.564429 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4779 09:28:38.567592 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =32
4780 09:28:38.570560 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =20
4781 09:28:38.574189 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =36
4782 09:28:38.574259
4783 09:28:38.574317
4784 09:28:38.584105 [DQSOSCAuto] RK1, (LSB)MR18= 0x405f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
4785 09:28:38.584187 CH1 RK1: MR19=808, MR18=405F
4786 09:28:38.590848 CH1_RK1: MR19=0x808, MR18=0x405F, DQSOSC=391, MR23=63, INC=171, DEC=114
4787 09:28:38.593798 [RxdqsGatingPostProcess] freq 600
4788 09:28:38.600653 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4789 09:28:38.603904 Pre-setting of DQS Precalculation
4790 09:28:38.607534 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4791 09:28:38.616863 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4792 09:28:38.624108 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4793 09:28:38.624232
4794 09:28:38.624325
4795 09:28:38.627246 [Calibration Summary] 1200 Mbps
4796 09:28:38.627319 CH 0, Rank 0
4797 09:28:38.630368 SW Impedance : PASS
4798 09:28:38.630456 DUTY Scan : NO K
4799 09:28:38.633412 ZQ Calibration : PASS
4800 09:28:38.637107 Jitter Meter : NO K
4801 09:28:38.637174 CBT Training : PASS
4802 09:28:38.640162 Write leveling : PASS
4803 09:28:38.643282 RX DQS gating : PASS
4804 09:28:38.643354 RX DQ/DQS(RDDQC) : PASS
4805 09:28:38.647121 TX DQ/DQS : PASS
4806 09:28:38.650253 RX DATLAT : PASS
4807 09:28:38.650342 RX DQ/DQS(Engine): PASS
4808 09:28:38.653230 TX OE : NO K
4809 09:28:38.653319 All Pass.
4810 09:28:38.653401
4811 09:28:38.656934 CH 0, Rank 1
4812 09:28:38.657000 SW Impedance : PASS
4813 09:28:38.659884 DUTY Scan : NO K
4814 09:28:38.663214 ZQ Calibration : PASS
4815 09:28:38.663324 Jitter Meter : NO K
4816 09:28:38.666630 CBT Training : PASS
4817 09:28:38.666701 Write leveling : PASS
4818 09:28:38.670185 RX DQS gating : PASS
4819 09:28:38.673400 RX DQ/DQS(RDDQC) : PASS
4820 09:28:38.673481 TX DQ/DQS : PASS
4821 09:28:38.676466 RX DATLAT : PASS
4822 09:28:38.679686 RX DQ/DQS(Engine): PASS
4823 09:28:38.679779 TX OE : NO K
4824 09:28:38.683281 All Pass.
4825 09:28:38.683381
4826 09:28:38.683465 CH 1, Rank 0
4827 09:28:38.686744 SW Impedance : PASS
4828 09:28:38.686852 DUTY Scan : NO K
4829 09:28:38.689692 ZQ Calibration : PASS
4830 09:28:38.693226 Jitter Meter : NO K
4831 09:28:38.693321 CBT Training : PASS
4832 09:28:38.696370 Write leveling : PASS
4833 09:28:38.699911 RX DQS gating : PASS
4834 09:28:38.700011 RX DQ/DQS(RDDQC) : PASS
4835 09:28:38.702987 TX DQ/DQS : PASS
4836 09:28:38.706508 RX DATLAT : PASS
4837 09:28:38.706587 RX DQ/DQS(Engine): PASS
4838 09:28:38.709548 TX OE : NO K
4839 09:28:38.709622 All Pass.
4840 09:28:38.709687
4841 09:28:38.713403 CH 1, Rank 1
4842 09:28:38.713477 SW Impedance : PASS
4843 09:28:38.716489 DUTY Scan : NO K
4844 09:28:38.716583 ZQ Calibration : PASS
4845 09:28:38.719524 Jitter Meter : NO K
4846 09:28:38.723000 CBT Training : PASS
4847 09:28:38.723075 Write leveling : PASS
4848 09:28:38.726453 RX DQS gating : PASS
4849 09:28:38.729464 RX DQ/DQS(RDDQC) : PASS
4850 09:28:38.729537 TX DQ/DQS : PASS
4851 09:28:38.732880 RX DATLAT : PASS
4852 09:28:38.736549 RX DQ/DQS(Engine): PASS
4853 09:28:38.736657 TX OE : NO K
4854 09:28:38.739694 All Pass.
4855 09:28:38.739768
4856 09:28:38.739836 DramC Write-DBI off
4857 09:28:38.742705 PER_BANK_REFRESH: Hybrid Mode
4858 09:28:38.742781 TX_TRACKING: ON
4859 09:28:38.753271 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4860 09:28:38.756407 [FAST_K] Save calibration result to emmc
4861 09:28:38.759599 dramc_set_vcore_voltage set vcore to 662500
4862 09:28:38.762646 Read voltage for 933, 3
4863 09:28:38.762716 Vio18 = 0
4864 09:28:38.766413 Vcore = 662500
4865 09:28:38.766481 Vdram = 0
4866 09:28:38.766538 Vddq = 0
4867 09:28:38.769568 Vmddr = 0
4868 09:28:38.772621 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4869 09:28:38.779273 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4870 09:28:38.779370 MEM_TYPE=3, freq_sel=17
4871 09:28:38.782658 sv_algorithm_assistance_LP4_1600
4872 09:28:38.789367 ============ PULL DRAM RESETB DOWN ============
4873 09:28:38.792409 ========== PULL DRAM RESETB DOWN end =========
4874 09:28:38.795953 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4875 09:28:38.798975 ===================================
4876 09:28:38.802489 LPDDR4 DRAM CONFIGURATION
4877 09:28:38.805658 ===================================
4878 09:28:38.808753 EX_ROW_EN[0] = 0x0
4879 09:28:38.808823 EX_ROW_EN[1] = 0x0
4880 09:28:38.812279 LP4Y_EN = 0x0
4881 09:28:38.812373 WORK_FSP = 0x0
4882 09:28:38.815941 WL = 0x3
4883 09:28:38.816017 RL = 0x3
4884 09:28:38.819087 BL = 0x2
4885 09:28:38.819156 RPST = 0x0
4886 09:28:38.822178 RD_PRE = 0x0
4887 09:28:38.822245 WR_PRE = 0x1
4888 09:28:38.825794 WR_PST = 0x0
4889 09:28:38.825867 DBI_WR = 0x0
4890 09:28:38.828657 DBI_RD = 0x0
4891 09:28:38.828724 OTF = 0x1
4892 09:28:38.832113 ===================================
4893 09:28:38.835434 ===================================
4894 09:28:38.838945 ANA top config
4895 09:28:38.842485 ===================================
4896 09:28:38.845473 DLL_ASYNC_EN = 0
4897 09:28:38.845547 ALL_SLAVE_EN = 1
4898 09:28:38.849022 NEW_RANK_MODE = 1
4899 09:28:38.852238 DLL_IDLE_MODE = 1
4900 09:28:38.855388 LP45_APHY_COMB_EN = 1
4901 09:28:38.855462 TX_ODT_DIS = 1
4902 09:28:38.858538 NEW_8X_MODE = 1
4903 09:28:38.862431 ===================================
4904 09:28:38.865515 ===================================
4905 09:28:38.868523 data_rate = 1866
4906 09:28:38.871724 CKR = 1
4907 09:28:38.875534 DQ_P2S_RATIO = 8
4908 09:28:38.878599 ===================================
4909 09:28:38.881807 CA_P2S_RATIO = 8
4910 09:28:38.881879 DQ_CA_OPEN = 0
4911 09:28:38.885327 DQ_SEMI_OPEN = 0
4912 09:28:38.888243 CA_SEMI_OPEN = 0
4913 09:28:38.891640 CA_FULL_RATE = 0
4914 09:28:38.894958 DQ_CKDIV4_EN = 1
4915 09:28:38.898471 CA_CKDIV4_EN = 1
4916 09:28:38.898546 CA_PREDIV_EN = 0
4917 09:28:38.901544 PH8_DLY = 0
4918 09:28:38.905180 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4919 09:28:38.908163 DQ_AAMCK_DIV = 4
4920 09:28:38.911783 CA_AAMCK_DIV = 4
4921 09:28:38.914924 CA_ADMCK_DIV = 4
4922 09:28:38.914999 DQ_TRACK_CA_EN = 0
4923 09:28:38.918418 CA_PICK = 933
4924 09:28:38.921314 CA_MCKIO = 933
4925 09:28:38.925046 MCKIO_SEMI = 0
4926 09:28:38.928165 PLL_FREQ = 3732
4927 09:28:38.931456 DQ_UI_PI_RATIO = 32
4928 09:28:38.935138 CA_UI_PI_RATIO = 0
4929 09:28:38.938190 ===================================
4930 09:28:38.941686 ===================================
4931 09:28:38.941758 memory_type:LPDDR4
4932 09:28:38.944493 GP_NUM : 10
4933 09:28:38.947854 SRAM_EN : 1
4934 09:28:38.947929 MD32_EN : 0
4935 09:28:38.951412 ===================================
4936 09:28:38.954911 [ANA_INIT] >>>>>>>>>>>>>>
4937 09:28:38.957795 <<<<<< [CONFIGURE PHASE]: ANA_TX
4938 09:28:38.961148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4939 09:28:38.964961 ===================================
4940 09:28:38.968011 data_rate = 1866,PCW = 0X8f00
4941 09:28:38.971168 ===================================
4942 09:28:38.974934 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4943 09:28:38.978097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4944 09:28:38.984338 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4945 09:28:38.988151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4946 09:28:38.991288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4947 09:28:38.994372 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4948 09:28:38.997470 [ANA_INIT] flow start
4949 09:28:39.000971 [ANA_INIT] PLL >>>>>>>>
4950 09:28:39.001039 [ANA_INIT] PLL <<<<<<<<
4951 09:28:39.004291 [ANA_INIT] MIDPI >>>>>>>>
4952 09:28:39.007388 [ANA_INIT] MIDPI <<<<<<<<
4953 09:28:39.010748 [ANA_INIT] DLL >>>>>>>>
4954 09:28:39.010817 [ANA_INIT] flow end
4955 09:28:39.014199 ============ LP4 DIFF to SE enter ============
4956 09:28:39.020683 ============ LP4 DIFF to SE exit ============
4957 09:28:39.020792 [ANA_INIT] <<<<<<<<<<<<<
4958 09:28:39.024450 [Flow] Enable top DCM control >>>>>
4959 09:28:39.027400 [Flow] Enable top DCM control <<<<<
4960 09:28:39.030881 Enable DLL master slave shuffle
4961 09:28:39.037319 ==============================================================
4962 09:28:39.037402 Gating Mode config
4963 09:28:39.044179 ==============================================================
4964 09:28:39.047335 Config description:
4965 09:28:39.057296 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4966 09:28:39.063945 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4967 09:28:39.066873 SELPH_MODE 0: By rank 1: By Phase
4968 09:28:39.073658 ==============================================================
4969 09:28:39.077335 GAT_TRACK_EN = 1
4970 09:28:39.080549 RX_GATING_MODE = 2
4971 09:28:39.080638 RX_GATING_TRACK_MODE = 2
4972 09:28:39.083735 SELPH_MODE = 1
4973 09:28:39.086801 PICG_EARLY_EN = 1
4974 09:28:39.090541 VALID_LAT_VALUE = 1
4975 09:28:39.096795 ==============================================================
4976 09:28:39.100544 Enter into Gating configuration >>>>
4977 09:28:39.103596 Exit from Gating configuration <<<<
4978 09:28:39.106736 Enter into DVFS_PRE_config >>>>>
4979 09:28:39.116764 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4980 09:28:39.120145 Exit from DVFS_PRE_config <<<<<
4981 09:28:39.123438 Enter into PICG configuration >>>>
4982 09:28:39.126748 Exit from PICG configuration <<<<
4983 09:28:39.130265 [RX_INPUT] configuration >>>>>
4984 09:28:39.133371 [RX_INPUT] configuration <<<<<
4985 09:28:39.136826 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4986 09:28:39.143609 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4987 09:28:39.149804 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4988 09:28:39.156776 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4989 09:28:39.159880 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4990 09:28:39.166470 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4991 09:28:39.169900 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4992 09:28:39.176432 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4993 09:28:39.179902 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4994 09:28:39.183349 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4995 09:28:39.186776 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4996 09:28:39.193275 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4997 09:28:39.196461 ===================================
4998 09:28:39.199661 LPDDR4 DRAM CONFIGURATION
4999 09:28:39.199776 ===================================
5000 09:28:39.202818 EX_ROW_EN[0] = 0x0
5001 09:28:39.206601 EX_ROW_EN[1] = 0x0
5002 09:28:39.206703 LP4Y_EN = 0x0
5003 09:28:39.209746 WORK_FSP = 0x0
5004 09:28:39.209826 WL = 0x3
5005 09:28:39.212831 RL = 0x3
5006 09:28:39.212921 BL = 0x2
5007 09:28:39.216477 RPST = 0x0
5008 09:28:39.216556 RD_PRE = 0x0
5009 09:28:39.219584 WR_PRE = 0x1
5010 09:28:39.219663 WR_PST = 0x0
5011 09:28:39.223317 DBI_WR = 0x0
5012 09:28:39.223392 DBI_RD = 0x0
5013 09:28:39.226323 OTF = 0x1
5014 09:28:39.229729 ===================================
5015 09:28:39.232512 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5016 09:28:39.235963 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5017 09:28:39.242781 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5018 09:28:39.246202 ===================================
5019 09:28:39.246275 LPDDR4 DRAM CONFIGURATION
5020 09:28:39.249168 ===================================
5021 09:28:39.252863 EX_ROW_EN[0] = 0x10
5022 09:28:39.256014 EX_ROW_EN[1] = 0x0
5023 09:28:39.256089 LP4Y_EN = 0x0
5024 09:28:39.259594 WORK_FSP = 0x0
5025 09:28:39.259679 WL = 0x3
5026 09:28:39.262679 RL = 0x3
5027 09:28:39.262761 BL = 0x2
5028 09:28:39.265774 RPST = 0x0
5029 09:28:39.265868 RD_PRE = 0x0
5030 09:28:39.269586 WR_PRE = 0x1
5031 09:28:39.269694 WR_PST = 0x0
5032 09:28:39.272425 DBI_WR = 0x0
5033 09:28:39.272521 DBI_RD = 0x0
5034 09:28:39.275581 OTF = 0x1
5035 09:28:39.279282 ===================================
5036 09:28:39.285843 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5037 09:28:39.289376 nWR fixed to 30
5038 09:28:39.292449 [ModeRegInit_LP4] CH0 RK0
5039 09:28:39.292538 [ModeRegInit_LP4] CH0 RK1
5040 09:28:39.296001 [ModeRegInit_LP4] CH1 RK0
5041 09:28:39.299025 [ModeRegInit_LP4] CH1 RK1
5042 09:28:39.299188 match AC timing 9
5043 09:28:39.305949 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5044 09:28:39.309127 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5045 09:28:39.312352 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5046 09:28:39.319127 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5047 09:28:39.321998 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5048 09:28:39.322098 ==
5049 09:28:39.325722 Dram Type= 6, Freq= 0, CH_0, rank 0
5050 09:28:39.328895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5051 09:28:39.328976 ==
5052 09:28:39.335459 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5053 09:28:39.342010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5054 09:28:39.345763 [CA 0] Center 38 (8~69) winsize 62
5055 09:28:39.348715 [CA 1] Center 38 (8~69) winsize 62
5056 09:28:39.352037 [CA 2] Center 35 (5~66) winsize 62
5057 09:28:39.355382 [CA 3] Center 35 (5~65) winsize 61
5058 09:28:39.358628 [CA 4] Center 34 (4~65) winsize 62
5059 09:28:39.361840 [CA 5] Center 33 (3~64) winsize 62
5060 09:28:39.361922
5061 09:28:39.365718 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5062 09:28:39.365805
5063 09:28:39.368849 [CATrainingPosCal] consider 1 rank data
5064 09:28:39.371888 u2DelayCellTimex100 = 270/100 ps
5065 09:28:39.375588 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5066 09:28:39.378760 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5067 09:28:39.381789 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5068 09:28:39.385594 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5069 09:28:39.388415 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5070 09:28:39.391916 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5071 09:28:39.395032
5072 09:28:39.398630 CA PerBit enable=1, Macro0, CA PI delay=33
5073 09:28:39.398711
5074 09:28:39.401629 [CBTSetCACLKResult] CA Dly = 33
5075 09:28:39.401716 CS Dly: 7 (0~38)
5076 09:28:39.401795 ==
5077 09:28:39.405256 Dram Type= 6, Freq= 0, CH_0, rank 1
5078 09:28:39.408306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5079 09:28:39.408385 ==
5080 09:28:39.415223 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5081 09:28:39.422092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5082 09:28:39.425034 [CA 0] Center 38 (8~69) winsize 62
5083 09:28:39.428694 [CA 1] Center 38 (8~69) winsize 62
5084 09:28:39.431877 [CA 2] Center 35 (5~66) winsize 62
5085 09:28:39.435626 [CA 3] Center 35 (5~66) winsize 62
5086 09:28:39.438546 [CA 4] Center 34 (4~65) winsize 62
5087 09:28:39.441602 [CA 5] Center 33 (3~64) winsize 62
5088 09:28:39.441704
5089 09:28:39.445398 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5090 09:28:39.445477
5091 09:28:39.448485 [CATrainingPosCal] consider 2 rank data
5092 09:28:39.451487 u2DelayCellTimex100 = 270/100 ps
5093 09:28:39.455195 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5094 09:28:39.458317 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5095 09:28:39.461896 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5096 09:28:39.464655 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5097 09:28:39.471721 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5098 09:28:39.474590 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5099 09:28:39.474695
5100 09:28:39.478361 CA PerBit enable=1, Macro0, CA PI delay=33
5101 09:28:39.478439
5102 09:28:39.481399 [CBTSetCACLKResult] CA Dly = 33
5103 09:28:39.481476 CS Dly: 7 (0~39)
5104 09:28:39.481538
5105 09:28:39.484505 ----->DramcWriteLeveling(PI) begin...
5106 09:28:39.484585 ==
5107 09:28:39.488338 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 09:28:39.494426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 09:28:39.494523 ==
5110 09:28:39.497973 Write leveling (Byte 0): 28 => 28
5111 09:28:39.501459 Write leveling (Byte 1): 30 => 30
5112 09:28:39.501548 DramcWriteLeveling(PI) end<-----
5113 09:28:39.501610
5114 09:28:39.504459 ==
5115 09:28:39.508160 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 09:28:39.511110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 09:28:39.511189 ==
5118 09:28:39.514173 [Gating] SW mode calibration
5119 09:28:39.521119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5120 09:28:39.524264 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5121 09:28:39.530904 0 14 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
5122 09:28:39.534622 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5123 09:28:39.537667 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 09:28:39.543894 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 09:28:39.547570 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 09:28:39.550765 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 09:28:39.557371 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 09:28:39.560537 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5129 09:28:39.564295 0 15 0 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 0)
5130 09:28:39.570590 0 15 4 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5131 09:28:39.573736 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 09:28:39.577243 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 09:28:39.583492 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 09:28:39.586783 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 09:28:39.590513 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 09:28:39.596606 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5137 09:28:39.600380 1 0 0 | B1->B0 | 2525 3c3c | 0 0 | (0 0) (0 0)
5138 09:28:39.603333 1 0 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5139 09:28:39.610266 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 09:28:39.613317 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 09:28:39.616984 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 09:28:39.623115 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 09:28:39.626870 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 09:28:39.629931 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 09:28:39.636811 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5146 09:28:39.639851 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 09:28:39.643049 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 09:28:39.649824 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 09:28:39.652948 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 09:28:39.656481 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 09:28:39.663252 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 09:28:39.666298 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 09:28:39.669469 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 09:28:39.676312 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 09:28:39.679453 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 09:28:39.682759 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 09:28:39.689524 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 09:28:39.692484 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 09:28:39.696064 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5160 09:28:39.702885 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5161 09:28:39.706043 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5162 09:28:39.708844 Total UI for P1: 0, mck2ui 16
5163 09:28:39.712209 best dqsien dly found for B0: ( 1, 2, 26)
5164 09:28:39.715902 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5165 09:28:39.722627 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 09:28:39.722710 Total UI for P1: 0, mck2ui 16
5167 09:28:39.729204 best dqsien dly found for B1: ( 1, 3, 4)
5168 09:28:39.732197 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5169 09:28:39.735906 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5170 09:28:39.735997
5171 09:28:39.738977 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5172 09:28:39.742017 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5173 09:28:39.745182 [Gating] SW calibration Done
5174 09:28:39.745264 ==
5175 09:28:39.748939 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 09:28:39.751947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 09:28:39.752028 ==
5178 09:28:39.755148 RX Vref Scan: 0
5179 09:28:39.755249
5180 09:28:39.755345 RX Vref 0 -> 0, step: 1
5181 09:28:39.755430
5182 09:28:39.758788 RX Delay -80 -> 252, step: 8
5183 09:28:39.762082 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5184 09:28:39.768763 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5185 09:28:39.771722 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5186 09:28:39.774780 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5187 09:28:39.778516 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5188 09:28:39.781662 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5189 09:28:39.788434 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5190 09:28:39.791401 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5191 09:28:39.794705 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5192 09:28:39.798388 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5193 09:28:39.801576 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5194 09:28:39.807973 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5195 09:28:39.811612 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5196 09:28:39.814823 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5197 09:28:39.818262 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5198 09:28:39.821291 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5199 09:28:39.821386 ==
5200 09:28:39.824629 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 09:28:39.831189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 09:28:39.831292 ==
5203 09:28:39.831385 DQS Delay:
5204 09:28:39.834607 DQS0 = 0, DQS1 = 0
5205 09:28:39.834706 DQM Delay:
5206 09:28:39.837795 DQM0 = 94, DQM1 = 83
5207 09:28:39.837878 DQ Delay:
5208 09:28:39.841239 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5209 09:28:39.844651 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5210 09:28:39.847777 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5211 09:28:39.850978 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5212 09:28:39.851057
5213 09:28:39.851118
5214 09:28:39.851174 ==
5215 09:28:39.854642 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 09:28:39.857683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 09:28:39.857764 ==
5218 09:28:39.857825
5219 09:28:39.857882
5220 09:28:39.861438 TX Vref Scan disable
5221 09:28:39.864612 == TX Byte 0 ==
5222 09:28:39.867712 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5223 09:28:39.870778 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5224 09:28:39.874398 == TX Byte 1 ==
5225 09:28:39.877480 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5226 09:28:39.881185 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5227 09:28:39.881264 ==
5228 09:28:39.884287 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 09:28:39.890634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 09:28:39.890714 ==
5231 09:28:39.890776
5232 09:28:39.890837
5233 09:28:39.890893 TX Vref Scan disable
5234 09:28:39.894315 == TX Byte 0 ==
5235 09:28:39.898061 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5236 09:28:39.904829 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5237 09:28:39.904910 == TX Byte 1 ==
5238 09:28:39.907809 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5239 09:28:39.914410 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5240 09:28:39.914493
5241 09:28:39.914554 [DATLAT]
5242 09:28:39.914611 Freq=933, CH0 RK0
5243 09:28:39.914666
5244 09:28:39.918089 DATLAT Default: 0xd
5245 09:28:39.918168 0, 0xFFFF, sum = 0
5246 09:28:39.921073 1, 0xFFFF, sum = 0
5247 09:28:39.921154 2, 0xFFFF, sum = 0
5248 09:28:39.924219 3, 0xFFFF, sum = 0
5249 09:28:39.927985 4, 0xFFFF, sum = 0
5250 09:28:39.928091 5, 0xFFFF, sum = 0
5251 09:28:39.931004 6, 0xFFFF, sum = 0
5252 09:28:39.931085 7, 0xFFFF, sum = 0
5253 09:28:39.934590 8, 0xFFFF, sum = 0
5254 09:28:39.934673 9, 0xFFFF, sum = 0
5255 09:28:39.937762 10, 0x0, sum = 1
5256 09:28:39.937844 11, 0x0, sum = 2
5257 09:28:39.940774 12, 0x0, sum = 3
5258 09:28:39.940857 13, 0x0, sum = 4
5259 09:28:39.940920 best_step = 11
5260 09:28:39.940977
5261 09:28:39.944252 ==
5262 09:28:39.947639 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 09:28:39.950974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 09:28:39.951054 ==
5265 09:28:39.951116 RX Vref Scan: 1
5266 09:28:39.951175
5267 09:28:39.954336 RX Vref 0 -> 0, step: 1
5268 09:28:39.954414
5269 09:28:39.957420 RX Delay -69 -> 252, step: 4
5270 09:28:39.957522
5271 09:28:39.960742 Set Vref, RX VrefLevel [Byte0]: 61
5272 09:28:39.964399 [Byte1]: 52
5273 09:28:39.964499
5274 09:28:39.967514 Final RX Vref Byte 0 = 61 to rank0
5275 09:28:39.970728 Final RX Vref Byte 1 = 52 to rank0
5276 09:28:39.974386 Final RX Vref Byte 0 = 61 to rank1
5277 09:28:39.977604 Final RX Vref Byte 1 = 52 to rank1==
5278 09:28:39.980745 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 09:28:39.984243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 09:28:39.987374 ==
5281 09:28:39.987462 DQS Delay:
5282 09:28:39.987525 DQS0 = 0, DQS1 = 0
5283 09:28:39.991120 DQM Delay:
5284 09:28:39.991198 DQM0 = 95, DQM1 = 82
5285 09:28:39.994270 DQ Delay:
5286 09:28:39.994346 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =92
5287 09:28:39.997425 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =106
5288 09:28:40.000974 DQ8 =76, DQ9 =68, DQ10 =82, DQ11 =76
5289 09:28:40.004178 DQ12 =88, DQ13 =88, DQ14 =94, DQ15 =90
5290 09:28:40.007213
5291 09:28:40.007316
5292 09:28:40.013892 [DQSOSCAuto] RK0, (LSB)MR18= 0x1716, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5293 09:28:40.017479 CH0 RK0: MR19=505, MR18=1716
5294 09:28:40.024037 CH0_RK0: MR19=0x505, MR18=0x1716, DQSOSC=414, MR23=63, INC=63, DEC=42
5295 09:28:40.024139
5296 09:28:40.027160 ----->DramcWriteLeveling(PI) begin...
5297 09:28:40.027239 ==
5298 09:28:40.030401 Dram Type= 6, Freq= 0, CH_0, rank 1
5299 09:28:40.034032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 09:28:40.034138 ==
5301 09:28:40.037206 Write leveling (Byte 0): 33 => 33
5302 09:28:40.040314 Write leveling (Byte 1): 29 => 29
5303 09:28:40.043697 DramcWriteLeveling(PI) end<-----
5304 09:28:40.043789
5305 09:28:40.043855 ==
5306 09:28:40.047294 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 09:28:40.050556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 09:28:40.050643 ==
5309 09:28:40.053779 [Gating] SW mode calibration
5310 09:28:40.060211 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5311 09:28:40.067042 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5312 09:28:40.070456 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
5313 09:28:40.073827 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 09:28:40.080469 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 09:28:40.083693 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 09:28:40.086672 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 09:28:40.093341 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 09:28:40.097197 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5319 09:28:40.100366 0 14 28 | B1->B0 | 3434 2c2c | 0 0 | (0 1) (1 1)
5320 09:28:40.106687 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5321 09:28:40.110375 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 09:28:40.113449 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 09:28:40.120168 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 09:28:40.123414 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 09:28:40.127020 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 09:28:40.133388 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 09:28:40.136468 0 15 28 | B1->B0 | 2626 3939 | 0 0 | (0 0) (0 0)
5328 09:28:40.140274 1 0 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5329 09:28:40.146648 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 09:28:40.149830 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 09:28:40.153351 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 09:28:40.159817 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 09:28:40.163169 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 09:28:40.166666 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 09:28:40.173269 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 09:28:40.176824 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5337 09:28:40.179693 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 09:28:40.186397 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 09:28:40.189949 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 09:28:40.192967 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 09:28:40.199794 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 09:28:40.202869 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 09:28:40.206603 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 09:28:40.212833 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 09:28:40.216397 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 09:28:40.219506 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 09:28:40.226352 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 09:28:40.229351 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 09:28:40.232929 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 09:28:40.236037 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5351 09:28:40.242806 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5352 09:28:40.245945 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5353 09:28:40.249766 Total UI for P1: 0, mck2ui 16
5354 09:28:40.252832 best dqsien dly found for B0: ( 1, 2, 26)
5355 09:28:40.255891 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5356 09:28:40.262640 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 09:28:40.265685 Total UI for P1: 0, mck2ui 16
5358 09:28:40.269223 best dqsien dly found for B1: ( 1, 3, 2)
5359 09:28:40.272559 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5360 09:28:40.275940 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5361 09:28:40.276030
5362 09:28:40.279438 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5363 09:28:40.282500 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5364 09:28:40.285531 [Gating] SW calibration Done
5365 09:28:40.285609 ==
5366 09:28:40.289024 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 09:28:40.292569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 09:28:40.292705 ==
5369 09:28:40.295392 RX Vref Scan: 0
5370 09:28:40.295469
5371 09:28:40.298711 RX Vref 0 -> 0, step: 1
5372 09:28:40.298787
5373 09:28:40.298847 RX Delay -80 -> 252, step: 8
5374 09:28:40.305865 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5375 09:28:40.308881 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5376 09:28:40.312036 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5377 09:28:40.315720 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5378 09:28:40.318848 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5379 09:28:40.321993 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5380 09:28:40.328608 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5381 09:28:40.332258 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5382 09:28:40.335387 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5383 09:28:40.338953 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5384 09:28:40.342168 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5385 09:28:40.348878 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5386 09:28:40.351922 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5387 09:28:40.354930 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5388 09:28:40.358733 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5389 09:28:40.361742 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5390 09:28:40.365330 ==
5391 09:28:40.368405 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 09:28:40.371553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 09:28:40.371627 ==
5394 09:28:40.371708 DQS Delay:
5395 09:28:40.375241 DQS0 = 0, DQS1 = 0
5396 09:28:40.375370 DQM Delay:
5397 09:28:40.378170 DQM0 = 90, DQM1 = 82
5398 09:28:40.378238 DQ Delay:
5399 09:28:40.381577 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5400 09:28:40.385024 DQ4 =91, DQ5 =75, DQ6 =99, DQ7 =103
5401 09:28:40.388115 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5402 09:28:40.391466 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =87
5403 09:28:40.391544
5404 09:28:40.391604
5405 09:28:40.391659 ==
5406 09:28:40.395005 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 09:28:40.398132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 09:28:40.398218 ==
5409 09:28:40.398280
5410 09:28:40.398336
5411 09:28:40.401862 TX Vref Scan disable
5412 09:28:40.404774 == TX Byte 0 ==
5413 09:28:40.408319 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5414 09:28:40.411324 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5415 09:28:40.414845 == TX Byte 1 ==
5416 09:28:40.417848 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5417 09:28:40.421441 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5418 09:28:40.421537 ==
5419 09:28:40.424447 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 09:28:40.431019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 09:28:40.431128 ==
5422 09:28:40.431189
5423 09:28:40.431245
5424 09:28:40.431298 TX Vref Scan disable
5425 09:28:40.435081 == TX Byte 0 ==
5426 09:28:40.438577 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5427 09:28:40.445278 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5428 09:28:40.445389 == TX Byte 1 ==
5429 09:28:40.448413 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5430 09:28:40.455319 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5431 09:28:40.455425
5432 09:28:40.455485 [DATLAT]
5433 09:28:40.455541 Freq=933, CH0 RK1
5434 09:28:40.455595
5435 09:28:40.458465 DATLAT Default: 0xb
5436 09:28:40.461549 0, 0xFFFF, sum = 0
5437 09:28:40.461635 1, 0xFFFF, sum = 0
5438 09:28:40.465189 2, 0xFFFF, sum = 0
5439 09:28:40.465273 3, 0xFFFF, sum = 0
5440 09:28:40.468192 4, 0xFFFF, sum = 0
5441 09:28:40.468270 5, 0xFFFF, sum = 0
5442 09:28:40.471772 6, 0xFFFF, sum = 0
5443 09:28:40.471861 7, 0xFFFF, sum = 0
5444 09:28:40.474836 8, 0xFFFF, sum = 0
5445 09:28:40.474915 9, 0xFFFF, sum = 0
5446 09:28:40.478053 10, 0x0, sum = 1
5447 09:28:40.478132 11, 0x0, sum = 2
5448 09:28:40.481717 12, 0x0, sum = 3
5449 09:28:40.481794 13, 0x0, sum = 4
5450 09:28:40.481856 best_step = 11
5451 09:28:40.484853
5452 09:28:40.484921 ==
5453 09:28:40.488068 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 09:28:40.491635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 09:28:40.491717 ==
5456 09:28:40.491779 RX Vref Scan: 0
5457 09:28:40.491836
5458 09:28:40.494951 RX Vref 0 -> 0, step: 1
5459 09:28:40.495016
5460 09:28:40.497829 RX Delay -77 -> 252, step: 4
5461 09:28:40.504861 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5462 09:28:40.507765 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5463 09:28:40.511164 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5464 09:28:40.514471 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5465 09:28:40.517965 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5466 09:28:40.521587 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5467 09:28:40.527885 iDelay=199, Bit 6, Center 102 (7 ~ 198) 192
5468 09:28:40.531321 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5469 09:28:40.534358 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5470 09:28:40.538034 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5471 09:28:40.540964 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5472 09:28:40.548032 iDelay=199, Bit 11, Center 80 (-9 ~ 170) 180
5473 09:28:40.551192 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5474 09:28:40.554354 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5475 09:28:40.558158 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5476 09:28:40.561280 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5477 09:28:40.561361 ==
5478 09:28:40.564314 Dram Type= 6, Freq= 0, CH_0, rank 1
5479 09:28:40.571235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5480 09:28:40.571317 ==
5481 09:28:40.571397 DQS Delay:
5482 09:28:40.574289 DQS0 = 0, DQS1 = 0
5483 09:28:40.574362 DQM Delay:
5484 09:28:40.574436 DQM0 = 92, DQM1 = 85
5485 09:28:40.578017 DQ Delay:
5486 09:28:40.581161 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5487 09:28:40.584311 DQ4 =92, DQ5 =82, DQ6 =102, DQ7 =104
5488 09:28:40.587526 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =80
5489 09:28:40.591152 DQ12 =92, DQ13 =90, DQ14 =94, DQ15 =92
5490 09:28:40.591230
5491 09:28:40.591308
5492 09:28:40.597455 [DQSOSCAuto] RK1, (LSB)MR18= 0x3416, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
5493 09:28:40.601182 CH0 RK1: MR19=505, MR18=3416
5494 09:28:40.607543 CH0_RK1: MR19=0x505, MR18=0x3416, DQSOSC=405, MR23=63, INC=66, DEC=44
5495 09:28:40.611249 [RxdqsGatingPostProcess] freq 933
5496 09:28:40.614279 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5497 09:28:40.617408 best DQS0 dly(2T, 0.5T) = (0, 10)
5498 09:28:40.620731 best DQS1 dly(2T, 0.5T) = (0, 11)
5499 09:28:40.623877 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5500 09:28:40.627648 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5501 09:28:40.630709 best DQS0 dly(2T, 0.5T) = (0, 10)
5502 09:28:40.634191 best DQS1 dly(2T, 0.5T) = (0, 11)
5503 09:28:40.637183 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5504 09:28:40.640941 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5505 09:28:40.643833 Pre-setting of DQS Precalculation
5506 09:28:40.647325 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5507 09:28:40.650550 ==
5508 09:28:40.650628 Dram Type= 6, Freq= 0, CH_1, rank 0
5509 09:28:40.657080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 09:28:40.657161 ==
5511 09:28:40.660389 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5512 09:28:40.667091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5513 09:28:40.670856 [CA 0] Center 37 (7~67) winsize 61
5514 09:28:40.674208 [CA 1] Center 37 (7~68) winsize 62
5515 09:28:40.677185 [CA 2] Center 34 (5~64) winsize 60
5516 09:28:40.680966 [CA 3] Center 34 (5~64) winsize 60
5517 09:28:40.684145 [CA 4] Center 34 (5~64) winsize 60
5518 09:28:40.687302 [CA 5] Center 34 (4~64) winsize 61
5519 09:28:40.687406
5520 09:28:40.690422 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5521 09:28:40.690498
5522 09:28:40.693630 [CATrainingPosCal] consider 1 rank data
5523 09:28:40.697342 u2DelayCellTimex100 = 270/100 ps
5524 09:28:40.700462 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5525 09:28:40.707500 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5526 09:28:40.710689 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5527 09:28:40.713777 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5528 09:28:40.716960 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5529 09:28:40.720052 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5530 09:28:40.720167
5531 09:28:40.723759 CA PerBit enable=1, Macro0, CA PI delay=34
5532 09:28:40.723832
5533 09:28:40.726756 [CBTSetCACLKResult] CA Dly = 34
5534 09:28:40.726826 CS Dly: 6 (0~37)
5535 09:28:40.730343 ==
5536 09:28:40.733322 Dram Type= 6, Freq= 0, CH_1, rank 1
5537 09:28:40.736946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 09:28:40.737031 ==
5539 09:28:40.740028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5540 09:28:40.746887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5541 09:28:40.750308 [CA 0] Center 38 (8~68) winsize 61
5542 09:28:40.753770 [CA 1] Center 37 (7~68) winsize 62
5543 09:28:40.757206 [CA 2] Center 35 (5~65) winsize 61
5544 09:28:40.760630 [CA 3] Center 34 (4~64) winsize 61
5545 09:28:40.764003 [CA 4] Center 35 (5~65) winsize 61
5546 09:28:40.767317 [CA 5] Center 34 (4~64) winsize 61
5547 09:28:40.767418
5548 09:28:40.770507 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5549 09:28:40.770583
5550 09:28:40.774008 [CATrainingPosCal] consider 2 rank data
5551 09:28:40.777502 u2DelayCellTimex100 = 270/100 ps
5552 09:28:40.780337 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5553 09:28:40.783942 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5554 09:28:40.790798 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5555 09:28:40.793858 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5556 09:28:40.797010 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5557 09:28:40.800266 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5558 09:28:40.800344
5559 09:28:40.803897 CA PerBit enable=1, Macro0, CA PI delay=34
5560 09:28:40.803973
5561 09:28:40.807021 [CBTSetCACLKResult] CA Dly = 34
5562 09:28:40.807090 CS Dly: 7 (0~39)
5563 09:28:40.807151
5564 09:28:40.813363 ----->DramcWriteLeveling(PI) begin...
5565 09:28:40.813442 ==
5566 09:28:40.817151 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 09:28:40.820276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 09:28:40.820355 ==
5569 09:28:40.823385 Write leveling (Byte 0): 28 => 28
5570 09:28:40.827034 Write leveling (Byte 1): 29 => 29
5571 09:28:40.829989 DramcWriteLeveling(PI) end<-----
5572 09:28:40.830069
5573 09:28:40.830145 ==
5574 09:28:40.833587 Dram Type= 6, Freq= 0, CH_1, rank 0
5575 09:28:40.837186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5576 09:28:40.837274 ==
5577 09:28:40.840258 [Gating] SW mode calibration
5578 09:28:40.846870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5579 09:28:40.853463 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5580 09:28:40.856364 0 14 0 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
5581 09:28:40.859913 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 09:28:40.866513 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 09:28:40.870200 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 09:28:40.873279 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 09:28:40.880184 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 09:28:40.883161 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 09:28:40.886506 0 14 28 | B1->B0 | 3030 3030 | 1 0 | (1 0) (0 1)
5588 09:28:40.889883 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 09:28:40.896337 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 09:28:40.899948 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 09:28:40.903326 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 09:28:40.909618 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 09:28:40.913280 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 09:28:40.916388 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 09:28:40.923363 0 15 28 | B1->B0 | 3131 3333 | 0 0 | (0 0) (1 1)
5596 09:28:40.926396 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 09:28:40.929468 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 09:28:40.936267 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 09:28:40.939753 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 09:28:40.943275 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 09:28:40.949911 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 09:28:40.952962 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 09:28:40.956656 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5604 09:28:40.963219 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 09:28:40.966719 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 09:28:40.969649 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 09:28:40.976349 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 09:28:40.979476 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 09:28:40.983314 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 09:28:40.989678 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 09:28:40.992811 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 09:28:40.996529 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 09:28:41.002525 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 09:28:41.005908 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 09:28:41.009175 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 09:28:41.016180 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 09:28:41.019599 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 09:28:41.022628 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 09:28:41.029506 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5620 09:28:41.029586 Total UI for P1: 0, mck2ui 16
5621 09:28:41.035770 best dqsien dly found for B1: ( 1, 2, 26)
5622 09:28:41.039505 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5623 09:28:41.042611 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 09:28:41.046475 Total UI for P1: 0, mck2ui 16
5625 09:28:41.048875 best dqsien dly found for B0: ( 1, 2, 30)
5626 09:28:41.052262 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5627 09:28:41.055668 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5628 09:28:41.055814
5629 09:28:41.059235 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5630 09:28:41.065360 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5631 09:28:41.065449 [Gating] SW calibration Done
5632 09:28:41.069184 ==
5633 09:28:41.069259 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 09:28:41.075385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 09:28:41.075496 ==
5636 09:28:41.075592 RX Vref Scan: 0
5637 09:28:41.075686
5638 09:28:41.079181 RX Vref 0 -> 0, step: 1
5639 09:28:41.079272
5640 09:28:41.082106 RX Delay -80 -> 252, step: 8
5641 09:28:41.085290 iDelay=208, Bit 0, Center 103 (0 ~ 207) 208
5642 09:28:41.089110 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5643 09:28:41.092174 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5644 09:28:41.098465 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5645 09:28:41.102206 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5646 09:28:41.105296 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5647 09:28:41.108393 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5648 09:28:41.111977 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5649 09:28:41.114983 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5650 09:28:41.121817 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5651 09:28:41.125255 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5652 09:28:41.128263 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5653 09:28:41.131638 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5654 09:28:41.135085 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5655 09:28:41.141750 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5656 09:28:41.144826 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5657 09:28:41.144910 ==
5658 09:28:41.148594 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 09:28:41.151660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 09:28:41.151734 ==
5661 09:28:41.155171 DQS Delay:
5662 09:28:41.155244 DQS0 = 0, DQS1 = 0
5663 09:28:41.155309 DQM Delay:
5664 09:28:41.158109 DQM0 = 94, DQM1 = 85
5665 09:28:41.158185 DQ Delay:
5666 09:28:41.161561 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =91
5667 09:28:41.164592 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5668 09:28:41.168194 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5669 09:28:41.171684 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5670 09:28:41.171762
5671 09:28:41.171823
5672 09:28:41.174613 ==
5673 09:28:41.174688 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 09:28:41.181422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 09:28:41.181497 ==
5676 09:28:41.181555
5677 09:28:41.181609
5678 09:28:41.184470 TX Vref Scan disable
5679 09:28:41.184565 == TX Byte 0 ==
5680 09:28:41.187848 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5681 09:28:41.194630 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5682 09:28:41.194743 == TX Byte 1 ==
5683 09:28:41.200912 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5684 09:28:41.204683 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5685 09:28:41.204770 ==
5686 09:28:41.207771 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 09:28:41.210972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 09:28:41.211045 ==
5689 09:28:41.211108
5690 09:28:41.211179
5691 09:28:41.214051 TX Vref Scan disable
5692 09:28:41.217795 == TX Byte 0 ==
5693 09:28:41.220897 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5694 09:28:41.224422 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5695 09:28:41.227531 == TX Byte 1 ==
5696 09:28:41.230734 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5697 09:28:41.233951 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5698 09:28:41.234048
5699 09:28:41.237135 [DATLAT]
5700 09:28:41.237233 Freq=933, CH1 RK0
5701 09:28:41.237328
5702 09:28:41.240561 DATLAT Default: 0xd
5703 09:28:41.240661 0, 0xFFFF, sum = 0
5704 09:28:41.244149 1, 0xFFFF, sum = 0
5705 09:28:41.244243 2, 0xFFFF, sum = 0
5706 09:28:41.247517 3, 0xFFFF, sum = 0
5707 09:28:41.247622 4, 0xFFFF, sum = 0
5708 09:28:41.250403 5, 0xFFFF, sum = 0
5709 09:28:41.250499 6, 0xFFFF, sum = 0
5710 09:28:41.254205 7, 0xFFFF, sum = 0
5711 09:28:41.254304 8, 0xFFFF, sum = 0
5712 09:28:41.257331 9, 0xFFFF, sum = 0
5713 09:28:41.257403 10, 0x0, sum = 1
5714 09:28:41.260388 11, 0x0, sum = 2
5715 09:28:41.260479 12, 0x0, sum = 3
5716 09:28:41.263758 13, 0x0, sum = 4
5717 09:28:41.263844 best_step = 11
5718 09:28:41.263904
5719 09:28:41.263958 ==
5720 09:28:41.267337 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 09:28:41.273857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 09:28:41.273938 ==
5723 09:28:41.273997 RX Vref Scan: 1
5724 09:28:41.274052
5725 09:28:41.276781 RX Vref 0 -> 0, step: 1
5726 09:28:41.276877
5727 09:28:41.280353 RX Delay -69 -> 252, step: 4
5728 09:28:41.280446
5729 09:28:41.283520 Set Vref, RX VrefLevel [Byte0]: 54
5730 09:28:41.286680 [Byte1]: 48
5731 09:28:41.286759
5732 09:28:41.290483 Final RX Vref Byte 0 = 54 to rank0
5733 09:28:41.293424 Final RX Vref Byte 1 = 48 to rank0
5734 09:28:41.296371 Final RX Vref Byte 0 = 54 to rank1
5735 09:28:41.299720 Final RX Vref Byte 1 = 48 to rank1==
5736 09:28:41.303336 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 09:28:41.306473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 09:28:41.306548 ==
5739 09:28:41.309623 DQS Delay:
5740 09:28:41.309698 DQS0 = 0, DQS1 = 0
5741 09:28:41.313458 DQM Delay:
5742 09:28:41.313528 DQM0 = 96, DQM1 = 87
5743 09:28:41.313585 DQ Delay:
5744 09:28:41.316592 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =92
5745 09:28:41.319707 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =94
5746 09:28:41.322857 DQ8 =74, DQ9 =78, DQ10 =88, DQ11 =82
5747 09:28:41.326436 DQ12 =96, DQ13 =94, DQ14 =96, DQ15 =94
5748 09:28:41.329453
5749 09:28:41.329529
5750 09:28:41.336138 [DQSOSCAuto] RK0, (LSB)MR18= 0x8, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5751 09:28:41.339293 CH1 RK0: MR19=505, MR18=8
5752 09:28:41.342519 CH1_RK0: MR19=0x505, MR18=0x8, DQSOSC=419, MR23=63, INC=61, DEC=41
5753 09:28:41.342591
5754 09:28:41.346225 ----->DramcWriteLeveling(PI) begin...
5755 09:28:41.349241 ==
5756 09:28:41.353037 Dram Type= 6, Freq= 0, CH_1, rank 1
5757 09:28:41.356155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 09:28:41.356249 ==
5759 09:28:41.358894 Write leveling (Byte 0): 29 => 29
5760 09:28:41.362383 Write leveling (Byte 1): 29 => 29
5761 09:28:41.366004 DramcWriteLeveling(PI) end<-----
5762 09:28:41.366078
5763 09:28:41.366136 ==
5764 09:28:41.368931 Dram Type= 6, Freq= 0, CH_1, rank 1
5765 09:28:41.372483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 09:28:41.372583 ==
5767 09:28:41.375983 [Gating] SW mode calibration
5768 09:28:41.382546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5769 09:28:41.389075 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5770 09:28:41.392172 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 09:28:41.395342 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 09:28:41.402344 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 09:28:41.405366 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 09:28:41.408736 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 09:28:41.415369 0 14 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
5776 09:28:41.418961 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 1)
5777 09:28:41.422143 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
5778 09:28:41.428341 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 09:28:41.431941 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 09:28:41.435017 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 09:28:41.441798 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 09:28:41.444910 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 09:28:41.448090 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 09:28:41.454797 0 15 24 | B1->B0 | 2727 3030 | 1 0 | (0 0) (0 0)
5785 09:28:41.457951 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5786 09:28:41.461693 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 09:28:41.468319 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 09:28:41.471199 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 09:28:41.474560 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 09:28:41.481646 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 09:28:41.484596 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 09:28:41.488176 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5793 09:28:41.494719 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5794 09:28:41.497766 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 09:28:41.501582 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 09:28:41.507824 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 09:28:41.511481 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 09:28:41.514582 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 09:28:41.521025 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 09:28:41.524380 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 09:28:41.527903 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 09:28:41.530997 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 09:28:41.537768 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 09:28:41.541399 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 09:28:41.544429 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 09:28:41.551389 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 09:28:41.554457 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 09:28:41.557504 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5809 09:28:41.564453 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 09:28:41.567533 Total UI for P1: 0, mck2ui 16
5811 09:28:41.570674 best dqsien dly found for B0: ( 1, 2, 24)
5812 09:28:41.574430 Total UI for P1: 0, mck2ui 16
5813 09:28:41.577511 best dqsien dly found for B1: ( 1, 2, 26)
5814 09:28:41.580553 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5815 09:28:41.583794 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5816 09:28:41.583886
5817 09:28:41.587235 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5818 09:28:41.590312 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5819 09:28:41.593643 [Gating] SW calibration Done
5820 09:28:41.593708 ==
5821 09:28:41.596951 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 09:28:41.600133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 09:28:41.600221 ==
5824 09:28:41.603665 RX Vref Scan: 0
5825 09:28:41.603731
5826 09:28:41.606809 RX Vref 0 -> 0, step: 1
5827 09:28:41.606880
5828 09:28:41.606938 RX Delay -80 -> 252, step: 8
5829 09:28:41.613841 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5830 09:28:41.617095 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5831 09:28:41.620184 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5832 09:28:41.623884 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5833 09:28:41.626906 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5834 09:28:41.633354 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5835 09:28:41.636594 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5836 09:28:41.640160 iDelay=208, Bit 7, Center 87 (-16 ~ 191) 208
5837 09:28:41.643854 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5838 09:28:41.646828 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5839 09:28:41.653567 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5840 09:28:41.656615 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5841 09:28:41.659812 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5842 09:28:41.663536 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5843 09:28:41.666664 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5844 09:28:41.669714 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5845 09:28:41.673561 ==
5846 09:28:41.676623 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 09:28:41.679676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 09:28:41.679742 ==
5849 09:28:41.679805 DQS Delay:
5850 09:28:41.683307 DQS0 = 0, DQS1 = 0
5851 09:28:41.683402 DQM Delay:
5852 09:28:41.686456 DQM0 = 92, DQM1 = 87
5853 09:28:41.686581 DQ Delay:
5854 09:28:41.689619 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =87
5855 09:28:41.692841 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5856 09:28:41.696602 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5857 09:28:41.699706 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5858 09:28:41.699774
5859 09:28:41.699829
5860 09:28:41.699888 ==
5861 09:28:41.702865 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 09:28:41.706581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 09:28:41.706674 ==
5864 09:28:41.706757
5865 09:28:41.709729
5866 09:28:41.709797 TX Vref Scan disable
5867 09:28:41.713309 == TX Byte 0 ==
5868 09:28:41.716396 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5869 09:28:41.719734 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5870 09:28:41.722880 == TX Byte 1 ==
5871 09:28:41.725913 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5872 09:28:41.729584 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5873 09:28:41.729670 ==
5874 09:28:41.732980 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 09:28:41.739724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 09:28:41.739798 ==
5877 09:28:41.739856
5878 09:28:41.739916
5879 09:28:41.739966 TX Vref Scan disable
5880 09:28:41.743309 == TX Byte 0 ==
5881 09:28:41.746791 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5882 09:28:41.753428 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5883 09:28:41.753505 == TX Byte 1 ==
5884 09:28:41.756862 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5885 09:28:41.763590 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5886 09:28:41.763738
5887 09:28:41.763824 [DATLAT]
5888 09:28:41.763905 Freq=933, CH1 RK1
5889 09:28:41.763985
5890 09:28:41.766886 DATLAT Default: 0xb
5891 09:28:41.766961 0, 0xFFFF, sum = 0
5892 09:28:41.769909 1, 0xFFFF, sum = 0
5893 09:28:41.773066 2, 0xFFFF, sum = 0
5894 09:28:41.773142 3, 0xFFFF, sum = 0
5895 09:28:41.776885 4, 0xFFFF, sum = 0
5896 09:28:41.776953 5, 0xFFFF, sum = 0
5897 09:28:41.780054 6, 0xFFFF, sum = 0
5898 09:28:41.780119 7, 0xFFFF, sum = 0
5899 09:28:41.783686 8, 0xFFFF, sum = 0
5900 09:28:41.783752 9, 0xFFFF, sum = 0
5901 09:28:41.786776 10, 0x0, sum = 1
5902 09:28:41.786841 11, 0x0, sum = 2
5903 09:28:41.789752 12, 0x0, sum = 3
5904 09:28:41.789856 13, 0x0, sum = 4
5905 09:28:41.789939 best_step = 11
5906 09:28:41.790053
5907 09:28:41.793374 ==
5908 09:28:41.796394 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 09:28:41.799646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 09:28:41.799717 ==
5911 09:28:41.799782 RX Vref Scan: 0
5912 09:28:41.799836
5913 09:28:41.802879 RX Vref 0 -> 0, step: 1
5914 09:28:41.802954
5915 09:28:41.806643 RX Delay -69 -> 252, step: 4
5916 09:28:41.813229 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5917 09:28:41.816378 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5918 09:28:41.819532 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5919 09:28:41.823396 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5920 09:28:41.826398 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5921 09:28:41.829786 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5922 09:28:41.836464 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5923 09:28:41.839397 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5924 09:28:41.843077 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5925 09:28:41.846359 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5926 09:28:41.849482 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5927 09:28:41.856173 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5928 09:28:41.859491 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5929 09:28:41.862949 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5930 09:28:41.866201 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5931 09:28:41.869348 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5932 09:28:41.869427 ==
5933 09:28:41.872940 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 09:28:41.876156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 09:28:41.879101 ==
5936 09:28:41.879179 DQS Delay:
5937 09:28:41.879241 DQS0 = 0, DQS1 = 0
5938 09:28:41.882841 DQM Delay:
5939 09:28:41.882919 DQM0 = 91, DQM1 = 90
5940 09:28:41.885964 DQ Delay:
5941 09:28:41.889124 DQ0 =96, DQ1 =86, DQ2 =80, DQ3 =88
5942 09:28:41.892833 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
5943 09:28:41.895933 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =86
5944 09:28:41.899015 DQ12 =98, DQ13 =98, DQ14 =96, DQ15 =98
5945 09:28:41.899094
5946 09:28:41.899155
5947 09:28:41.906023 [DQSOSCAuto] RK1, (LSB)MR18= 0x1327, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
5948 09:28:41.909150 CH1 RK1: MR19=505, MR18=1327
5949 09:28:41.916052 CH1_RK1: MR19=0x505, MR18=0x1327, DQSOSC=409, MR23=63, INC=64, DEC=43
5950 09:28:41.919188 [RxdqsGatingPostProcess] freq 933
5951 09:28:41.922317 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5952 09:28:41.925957 best DQS0 dly(2T, 0.5T) = (0, 10)
5953 09:28:41.929091 best DQS1 dly(2T, 0.5T) = (0, 10)
5954 09:28:41.932181 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5955 09:28:41.935867 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5956 09:28:41.938891 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 09:28:41.942536 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 09:28:41.945748 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 09:28:41.948868 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 09:28:41.952667 Pre-setting of DQS Precalculation
5961 09:28:41.955739 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5962 09:28:41.965399 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5963 09:28:41.972582 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5964 09:28:41.972685
5965 09:28:41.972748
5966 09:28:41.975780 [Calibration Summary] 1866 Mbps
5967 09:28:41.975858 CH 0, Rank 0
5968 09:28:41.979002 SW Impedance : PASS
5969 09:28:41.979079 DUTY Scan : NO K
5970 09:28:41.982299 ZQ Calibration : PASS
5971 09:28:41.985675 Jitter Meter : NO K
5972 09:28:41.985752 CBT Training : PASS
5973 09:28:41.988827 Write leveling : PASS
5974 09:28:41.992197 RX DQS gating : PASS
5975 09:28:41.992273 RX DQ/DQS(RDDQC) : PASS
5976 09:28:41.995417 TX DQ/DQS : PASS
5977 09:28:41.995494 RX DATLAT : PASS
5978 09:28:41.998954 RX DQ/DQS(Engine): PASS
5979 09:28:42.001991 TX OE : NO K
5980 09:28:42.002104 All Pass.
5981 09:28:42.002163
5982 09:28:42.002219 CH 0, Rank 1
5983 09:28:42.005749 SW Impedance : PASS
5984 09:28:42.008809 DUTY Scan : NO K
5985 09:28:42.008888 ZQ Calibration : PASS
5986 09:28:42.011966 Jitter Meter : NO K
5987 09:28:42.015695 CBT Training : PASS
5988 09:28:42.015763 Write leveling : PASS
5989 09:28:42.018874 RX DQS gating : PASS
5990 09:28:42.021821 RX DQ/DQS(RDDQC) : PASS
5991 09:28:42.021887 TX DQ/DQS : PASS
5992 09:28:42.025395 RX DATLAT : PASS
5993 09:28:42.028498 RX DQ/DQS(Engine): PASS
5994 09:28:42.028563 TX OE : NO K
5995 09:28:42.032148 All Pass.
5996 09:28:42.032212
5997 09:28:42.032267 CH 1, Rank 0
5998 09:28:42.035269 SW Impedance : PASS
5999 09:28:42.035337 DUTY Scan : NO K
6000 09:28:42.039028 ZQ Calibration : PASS
6001 09:28:42.042306 Jitter Meter : NO K
6002 09:28:42.042399 CBT Training : PASS
6003 09:28:42.045295 Write leveling : PASS
6004 09:28:42.045371 RX DQS gating : PASS
6005 09:28:42.048505 RX DQ/DQS(RDDQC) : PASS
6006 09:28:42.052055 TX DQ/DQS : PASS
6007 09:28:42.052132 RX DATLAT : PASS
6008 09:28:42.055119 RX DQ/DQS(Engine): PASS
6009 09:28:42.058772 TX OE : NO K
6010 09:28:42.058848 All Pass.
6011 09:28:42.058937
6012 09:28:42.058993 CH 1, Rank 1
6013 09:28:42.062009 SW Impedance : PASS
6014 09:28:42.065077 DUTY Scan : NO K
6015 09:28:42.065153 ZQ Calibration : PASS
6016 09:28:42.068276 Jitter Meter : NO K
6017 09:28:42.071933 CBT Training : PASS
6018 09:28:42.072009 Write leveling : PASS
6019 09:28:42.074989 RX DQS gating : PASS
6020 09:28:42.078536 RX DQ/DQS(RDDQC) : PASS
6021 09:28:42.078639 TX DQ/DQS : PASS
6022 09:28:42.081554 RX DATLAT : PASS
6023 09:28:42.085158 RX DQ/DQS(Engine): PASS
6024 09:28:42.085235 TX OE : NO K
6025 09:28:42.088002 All Pass.
6026 09:28:42.088092
6027 09:28:42.088151 DramC Write-DBI off
6028 09:28:42.091838 PER_BANK_REFRESH: Hybrid Mode
6029 09:28:42.091915 TX_TRACKING: ON
6030 09:28:42.101467 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6031 09:28:42.104810 [FAST_K] Save calibration result to emmc
6032 09:28:42.107859 dramc_set_vcore_voltage set vcore to 650000
6033 09:28:42.111516 Read voltage for 400, 6
6034 09:28:42.111593 Vio18 = 0
6035 09:28:42.114740 Vcore = 650000
6036 09:28:42.114816 Vdram = 0
6037 09:28:42.114876 Vddq = 0
6038 09:28:42.117799 Vmddr = 0
6039 09:28:42.121078 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6040 09:28:42.127864 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6041 09:28:42.127955 MEM_TYPE=3, freq_sel=20
6042 09:28:42.131629 sv_algorithm_assistance_LP4_800
6043 09:28:42.134805 ============ PULL DRAM RESETB DOWN ============
6044 09:28:42.141182 ========== PULL DRAM RESETB DOWN end =========
6045 09:28:42.144836 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6046 09:28:42.147889 ===================================
6047 09:28:42.151588 LPDDR4 DRAM CONFIGURATION
6048 09:28:42.154694 ===================================
6049 09:28:42.154772 EX_ROW_EN[0] = 0x0
6050 09:28:42.158372 EX_ROW_EN[1] = 0x0
6051 09:28:42.158460 LP4Y_EN = 0x0
6052 09:28:42.161539 WORK_FSP = 0x0
6053 09:28:42.161645 WL = 0x2
6054 09:28:42.164605 RL = 0x2
6055 09:28:42.168447 BL = 0x2
6056 09:28:42.168523 RPST = 0x0
6057 09:28:42.171600 RD_PRE = 0x0
6058 09:28:42.171676 WR_PRE = 0x1
6059 09:28:42.174838 WR_PST = 0x0
6060 09:28:42.174916 DBI_WR = 0x0
6061 09:28:42.177884 DBI_RD = 0x0
6062 09:28:42.178005 OTF = 0x1
6063 09:28:42.181544 ===================================
6064 09:28:42.184771 ===================================
6065 09:28:42.187899 ANA top config
6066 09:28:42.191558 ===================================
6067 09:28:42.191636 DLL_ASYNC_EN = 0
6068 09:28:42.194418 ALL_SLAVE_EN = 1
6069 09:28:42.197759 NEW_RANK_MODE = 1
6070 09:28:42.201487 DLL_IDLE_MODE = 1
6071 09:28:42.201565 LP45_APHY_COMB_EN = 1
6072 09:28:42.204557 TX_ODT_DIS = 1
6073 09:28:42.207698 NEW_8X_MODE = 1
6074 09:28:42.211447 ===================================
6075 09:28:42.214454 ===================================
6076 09:28:42.217944 data_rate = 800
6077 09:28:42.221000 CKR = 1
6078 09:28:42.224528 DQ_P2S_RATIO = 4
6079 09:28:42.227387 ===================================
6080 09:28:42.227531 CA_P2S_RATIO = 4
6081 09:28:42.231233 DQ_CA_OPEN = 0
6082 09:28:42.234151 DQ_SEMI_OPEN = 1
6083 09:28:42.237803 CA_SEMI_OPEN = 1
6084 09:28:42.240827 CA_FULL_RATE = 0
6085 09:28:42.244363 DQ_CKDIV4_EN = 0
6086 09:28:42.244440 CA_CKDIV4_EN = 1
6087 09:28:42.247546 CA_PREDIV_EN = 0
6088 09:28:42.250650 PH8_DLY = 0
6089 09:28:42.254230 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6090 09:28:42.257427 DQ_AAMCK_DIV = 0
6091 09:28:42.261081 CA_AAMCK_DIV = 0
6092 09:28:42.261184 CA_ADMCK_DIV = 4
6093 09:28:42.264184 DQ_TRACK_CA_EN = 0
6094 09:28:42.267737 CA_PICK = 800
6095 09:28:42.270857 CA_MCKIO = 400
6096 09:28:42.274024 MCKIO_SEMI = 400
6097 09:28:42.277711 PLL_FREQ = 3016
6098 09:28:42.280792 DQ_UI_PI_RATIO = 32
6099 09:28:42.280885 CA_UI_PI_RATIO = 32
6100 09:28:42.284388 ===================================
6101 09:28:42.287394 ===================================
6102 09:28:42.290556 memory_type:LPDDR4
6103 09:28:42.294274 GP_NUM : 10
6104 09:28:42.294370 SRAM_EN : 1
6105 09:28:42.297320 MD32_EN : 0
6106 09:28:42.301024 ===================================
6107 09:28:42.303946 [ANA_INIT] >>>>>>>>>>>>>>
6108 09:28:42.307421 <<<<<< [CONFIGURE PHASE]: ANA_TX
6109 09:28:42.310934 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6110 09:28:42.314025 ===================================
6111 09:28:42.314123 data_rate = 800,PCW = 0X7400
6112 09:28:42.317138 ===================================
6113 09:28:42.320671 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6114 09:28:42.327058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6115 09:28:42.340530 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6116 09:28:42.343846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6117 09:28:42.347111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6118 09:28:42.350206 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6119 09:28:42.353677 [ANA_INIT] flow start
6120 09:28:42.353781 [ANA_INIT] PLL >>>>>>>>
6121 09:28:42.357365 [ANA_INIT] PLL <<<<<<<<
6122 09:28:42.360236 [ANA_INIT] MIDPI >>>>>>>>
6123 09:28:42.360340 [ANA_INIT] MIDPI <<<<<<<<
6124 09:28:42.363728 [ANA_INIT] DLL >>>>>>>>
6125 09:28:42.367281 [ANA_INIT] flow end
6126 09:28:42.370263 ============ LP4 DIFF to SE enter ============
6127 09:28:42.373928 ============ LP4 DIFF to SE exit ============
6128 09:28:42.377184 [ANA_INIT] <<<<<<<<<<<<<
6129 09:28:42.380285 [Flow] Enable top DCM control >>>>>
6130 09:28:42.383457 [Flow] Enable top DCM control <<<<<
6131 09:28:42.387099 Enable DLL master slave shuffle
6132 09:28:42.390028 ==============================================================
6133 09:28:42.393840 Gating Mode config
6134 09:28:42.400160 ==============================================================
6135 09:28:42.400271 Config description:
6136 09:28:42.410235 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6137 09:28:42.416566 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6138 09:28:42.423397 SELPH_MODE 0: By rank 1: By Phase
6139 09:28:42.426773 ==============================================================
6140 09:28:42.429821 GAT_TRACK_EN = 0
6141 09:28:42.432993 RX_GATING_MODE = 2
6142 09:28:42.436311 RX_GATING_TRACK_MODE = 2
6143 09:28:42.440152 SELPH_MODE = 1
6144 09:28:42.443314 PICG_EARLY_EN = 1
6145 09:28:42.446452 VALID_LAT_VALUE = 1
6146 09:28:42.449608 ==============================================================
6147 09:28:42.453261 Enter into Gating configuration >>>>
6148 09:28:42.456270 Exit from Gating configuration <<<<
6149 09:28:42.460022 Enter into DVFS_PRE_config >>>>>
6150 09:28:42.473285 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6151 09:28:42.476388 Exit from DVFS_PRE_config <<<<<
6152 09:28:42.476463 Enter into PICG configuration >>>>
6153 09:28:42.479707 Exit from PICG configuration <<<<
6154 09:28:42.483106 [RX_INPUT] configuration >>>>>
6155 09:28:42.486518 [RX_INPUT] configuration <<<<<
6156 09:28:42.492994 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6157 09:28:42.496132 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6158 09:28:42.503047 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6159 09:28:42.509363 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6160 09:28:42.516222 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 09:28:42.522508 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 09:28:42.526216 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6163 09:28:42.529162 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6164 09:28:42.532511 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6165 09:28:42.538915 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6166 09:28:42.542706 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6167 09:28:42.545834 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 09:28:42.549089 ===================================
6169 09:28:42.552284 LPDDR4 DRAM CONFIGURATION
6170 09:28:42.555943 ===================================
6171 09:28:42.559184 EX_ROW_EN[0] = 0x0
6172 09:28:42.559263 EX_ROW_EN[1] = 0x0
6173 09:28:42.562377 LP4Y_EN = 0x0
6174 09:28:42.562471 WORK_FSP = 0x0
6175 09:28:42.565937 WL = 0x2
6176 09:28:42.566010 RL = 0x2
6177 09:28:42.568988 BL = 0x2
6178 09:28:42.569062 RPST = 0x0
6179 09:28:42.572198 RD_PRE = 0x0
6180 09:28:42.572275 WR_PRE = 0x1
6181 09:28:42.575955 WR_PST = 0x0
6182 09:28:42.576045 DBI_WR = 0x0
6183 09:28:42.578863 DBI_RD = 0x0
6184 09:28:42.578932 OTF = 0x1
6185 09:28:42.582546 ===================================
6186 09:28:42.589001 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6187 09:28:42.592431 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6188 09:28:42.595439 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6189 09:28:42.598832 ===================================
6190 09:28:42.602192 LPDDR4 DRAM CONFIGURATION
6191 09:28:42.605507 ===================================
6192 09:28:42.608639 EX_ROW_EN[0] = 0x10
6193 09:28:42.608751 EX_ROW_EN[1] = 0x0
6194 09:28:42.612389 LP4Y_EN = 0x0
6195 09:28:42.612466 WORK_FSP = 0x0
6196 09:28:42.615588 WL = 0x2
6197 09:28:42.615654 RL = 0x2
6198 09:28:42.618716 BL = 0x2
6199 09:28:42.618791 RPST = 0x0
6200 09:28:42.621894 RD_PRE = 0x0
6201 09:28:42.621961 WR_PRE = 0x1
6202 09:28:42.625458 WR_PST = 0x0
6203 09:28:42.625565 DBI_WR = 0x0
6204 09:28:42.628568 DBI_RD = 0x0
6205 09:28:42.628662 OTF = 0x1
6206 09:28:42.632213 ===================================
6207 09:28:42.638784 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6208 09:28:42.643345 nWR fixed to 30
6209 09:28:42.646689 [ModeRegInit_LP4] CH0 RK0
6210 09:28:42.646824 [ModeRegInit_LP4] CH0 RK1
6211 09:28:42.649713 [ModeRegInit_LP4] CH1 RK0
6212 09:28:42.653525 [ModeRegInit_LP4] CH1 RK1
6213 09:28:42.653601 match AC timing 19
6214 09:28:42.659837 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6215 09:28:42.663019 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6216 09:28:42.666762 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6217 09:28:42.673542 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6218 09:28:42.676597 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6219 09:28:42.676697 ==
6220 09:28:42.679787 Dram Type= 6, Freq= 0, CH_0, rank 0
6221 09:28:42.683402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6222 09:28:42.683490 ==
6223 09:28:42.689509 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6224 09:28:42.696181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6225 09:28:42.699936 [CA 0] Center 36 (8~64) winsize 57
6226 09:28:42.702924 [CA 1] Center 36 (8~64) winsize 57
6227 09:28:42.706022 [CA 2] Center 36 (8~64) winsize 57
6228 09:28:42.709717 [CA 3] Center 36 (8~64) winsize 57
6229 09:28:42.709785 [CA 4] Center 36 (8~64) winsize 57
6230 09:28:42.712795 [CA 5] Center 36 (8~64) winsize 57
6231 09:28:42.716207
6232 09:28:42.719575 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6233 09:28:42.719644
6234 09:28:42.722921 [CATrainingPosCal] consider 1 rank data
6235 09:28:42.725837 u2DelayCellTimex100 = 270/100 ps
6236 09:28:42.729514 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 09:28:42.732620 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 09:28:42.735705 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 09:28:42.739445 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 09:28:42.742679 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 09:28:42.746103 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 09:28:42.746171
6243 09:28:42.749035 CA PerBit enable=1, Macro0, CA PI delay=36
6244 09:28:42.749121
6245 09:28:42.752433 [CBTSetCACLKResult] CA Dly = 36
6246 09:28:42.755717 CS Dly: 1 (0~32)
6247 09:28:42.755801 ==
6248 09:28:42.759219 Dram Type= 6, Freq= 0, CH_0, rank 1
6249 09:28:42.762293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 09:28:42.762376 ==
6251 09:28:42.769311 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 09:28:42.775405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6253 09:28:42.779174 [CA 0] Center 36 (8~64) winsize 57
6254 09:28:42.782283 [CA 1] Center 36 (8~64) winsize 57
6255 09:28:42.782367 [CA 2] Center 36 (8~64) winsize 57
6256 09:28:42.785460 [CA 3] Center 36 (8~64) winsize 57
6257 09:28:42.788983 [CA 4] Center 36 (8~64) winsize 57
6258 09:28:42.792202 [CA 5] Center 36 (8~64) winsize 57
6259 09:28:42.792278
6260 09:28:42.795173 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6261 09:28:42.798923
6262 09:28:42.802460 [CATrainingPosCal] consider 2 rank data
6263 09:28:42.802537 u2DelayCellTimex100 = 270/100 ps
6264 09:28:42.809015 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 09:28:42.812170 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 09:28:42.815405 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 09:28:42.818539 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 09:28:42.822258 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 09:28:42.825255 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 09:28:42.825333
6271 09:28:42.828832 CA PerBit enable=1, Macro0, CA PI delay=36
6272 09:28:42.828919
6273 09:28:42.832229 [CBTSetCACLKResult] CA Dly = 36
6274 09:28:42.835016 CS Dly: 1 (0~32)
6275 09:28:42.835088
6276 09:28:42.838440 ----->DramcWriteLeveling(PI) begin...
6277 09:28:42.838540 ==
6278 09:28:42.842177 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 09:28:42.845305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 09:28:42.845376 ==
6281 09:28:42.848453 Write leveling (Byte 0): 40 => 8
6282 09:28:42.851637 Write leveling (Byte 1): 40 => 8
6283 09:28:42.855445 DramcWriteLeveling(PI) end<-----
6284 09:28:42.855528
6285 09:28:42.855583 ==
6286 09:28:42.858447 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 09:28:42.861828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 09:28:42.861898 ==
6289 09:28:42.865231 [Gating] SW mode calibration
6290 09:28:42.871531 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6291 09:28:42.878529 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6292 09:28:42.881585 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6293 09:28:42.884780 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6294 09:28:42.891541 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 09:28:42.895191 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 09:28:42.898231 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 09:28:42.904909 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 09:28:42.908536 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 09:28:42.911646 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 09:28:42.917959 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 09:28:42.918031 Total UI for P1: 0, mck2ui 16
6302 09:28:42.924815 best dqsien dly found for B0: ( 0, 14, 24)
6303 09:28:42.924884 Total UI for P1: 0, mck2ui 16
6304 09:28:42.931644 best dqsien dly found for B1: ( 0, 14, 24)
6305 09:28:42.934810 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6306 09:28:42.937900 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6307 09:28:42.937966
6308 09:28:42.941559 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6309 09:28:42.944554 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6310 09:28:42.948299 [Gating] SW calibration Done
6311 09:28:42.948365 ==
6312 09:28:42.951162 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 09:28:42.954837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 09:28:42.954905 ==
6315 09:28:42.957973 RX Vref Scan: 0
6316 09:28:42.958039
6317 09:28:42.958109 RX Vref 0 -> 0, step: 1
6318 09:28:42.958163
6319 09:28:42.961151 RX Delay -410 -> 252, step: 16
6320 09:28:42.967878 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6321 09:28:42.971088 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6322 09:28:42.974597 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6323 09:28:42.977453 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6324 09:28:42.984414 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6325 09:28:42.987967 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6326 09:28:42.991099 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6327 09:28:42.994054 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6328 09:28:43.000702 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6329 09:28:43.004365 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6330 09:28:43.007546 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6331 09:28:43.010535 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6332 09:28:43.017255 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6333 09:28:43.020938 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6334 09:28:43.024043 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6335 09:28:43.027221 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6336 09:28:43.030876 ==
6337 09:28:43.033889 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 09:28:43.037175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 09:28:43.037243 ==
6340 09:28:43.037300 DQS Delay:
6341 09:28:43.040835 DQS0 = 59, DQS1 = 59
6342 09:28:43.040907 DQM Delay:
6343 09:28:43.043863 DQM0 = 18, DQM1 = 11
6344 09:28:43.043954 DQ Delay:
6345 09:28:43.047556 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6346 09:28:43.050761 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6347 09:28:43.053811 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6348 09:28:43.057337 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6349 09:28:43.057405
6350 09:28:43.057459
6351 09:28:43.057511 ==
6352 09:28:43.060354 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 09:28:43.063481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 09:28:43.063548 ==
6355 09:28:43.063603
6356 09:28:43.063654
6357 09:28:43.067245 TX Vref Scan disable
6358 09:28:43.070330 == TX Byte 0 ==
6359 09:28:43.073799 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 09:28:43.076977 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 09:28:43.077070 == TX Byte 1 ==
6362 09:28:43.083829 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 09:28:43.086786 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 09:28:43.086854 ==
6365 09:28:43.090188 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 09:28:43.093511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 09:28:43.093583 ==
6368 09:28:43.093646
6369 09:28:43.096656
6370 09:28:43.096735 TX Vref Scan disable
6371 09:28:43.100182 == TX Byte 0 ==
6372 09:28:43.103222 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 09:28:43.106770 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 09:28:43.109839 == TX Byte 1 ==
6375 09:28:43.113574 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 09:28:43.116502 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 09:28:43.116576
6378 09:28:43.116633 [DATLAT]
6379 09:28:43.120108 Freq=400, CH0 RK0
6380 09:28:43.120171
6381 09:28:43.120229 DATLAT Default: 0xf
6382 09:28:43.123164 0, 0xFFFF, sum = 0
6383 09:28:43.126479 1, 0xFFFF, sum = 0
6384 09:28:43.126554 2, 0xFFFF, sum = 0
6385 09:28:43.129699 3, 0xFFFF, sum = 0
6386 09:28:43.129771 4, 0xFFFF, sum = 0
6387 09:28:43.133326 5, 0xFFFF, sum = 0
6388 09:28:43.133398 6, 0xFFFF, sum = 0
6389 09:28:43.136364 7, 0xFFFF, sum = 0
6390 09:28:43.136441 8, 0xFFFF, sum = 0
6391 09:28:43.139545 9, 0xFFFF, sum = 0
6392 09:28:43.139624 10, 0xFFFF, sum = 0
6393 09:28:43.143325 11, 0xFFFF, sum = 0
6394 09:28:43.143403 12, 0xFFFF, sum = 0
6395 09:28:43.146266 13, 0x0, sum = 1
6396 09:28:43.146336 14, 0x0, sum = 2
6397 09:28:43.149724 15, 0x0, sum = 3
6398 09:28:43.149793 16, 0x0, sum = 4
6399 09:28:43.153517 best_step = 14
6400 09:28:43.153589
6401 09:28:43.153647 ==
6402 09:28:43.156533 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 09:28:43.159752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 09:28:43.159820 ==
6405 09:28:43.159874 RX Vref Scan: 1
6406 09:28:43.163696
6407 09:28:43.163760 RX Vref 0 -> 0, step: 1
6408 09:28:43.163814
6409 09:28:43.166566 RX Delay -359 -> 252, step: 8
6410 09:28:43.166640
6411 09:28:43.169701 Set Vref, RX VrefLevel [Byte0]: 61
6412 09:28:43.172957 [Byte1]: 52
6413 09:28:43.177229
6414 09:28:43.177310 Final RX Vref Byte 0 = 61 to rank0
6415 09:28:43.180938 Final RX Vref Byte 1 = 52 to rank0
6416 09:28:43.184142 Final RX Vref Byte 0 = 61 to rank1
6417 09:28:43.187256 Final RX Vref Byte 1 = 52 to rank1==
6418 09:28:43.190500 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 09:28:43.197080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 09:28:43.197155 ==
6421 09:28:43.197213 DQS Delay:
6422 09:28:43.200507 DQS0 = 60, DQS1 = 68
6423 09:28:43.200576 DQM Delay:
6424 09:28:43.200632 DQM0 = 15, DQM1 = 13
6425 09:28:43.203969 DQ Delay:
6426 09:28:43.207273 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =16
6427 09:28:43.210593 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6428 09:28:43.210676 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6429 09:28:43.216841 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6430 09:28:43.216918
6431 09:28:43.216976
6432 09:28:43.223655 [DQSOSCAuto] RK0, (LSB)MR18= 0x8381, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6433 09:28:43.227107 CH0 RK0: MR19=C0C, MR18=8381
6434 09:28:43.233336 CH0_RK0: MR19=0xC0C, MR18=0x8381, DQSOSC=393, MR23=63, INC=382, DEC=254
6435 09:28:43.233411 ==
6436 09:28:43.237102 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 09:28:43.240152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 09:28:43.240259 ==
6439 09:28:43.243272 [Gating] SW mode calibration
6440 09:28:43.250245 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6441 09:28:43.256718 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6442 09:28:43.259781 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 09:28:43.263586 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 09:28:43.269681 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 09:28:43.273440 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 09:28:43.276524 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 09:28:43.283103 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 09:28:43.286710 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 09:28:43.289830 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 09:28:43.296143 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 09:28:43.296217 Total UI for P1: 0, mck2ui 16
6452 09:28:43.303055 best dqsien dly found for B0: ( 0, 14, 24)
6453 09:28:43.303123 Total UI for P1: 0, mck2ui 16
6454 09:28:43.309733 best dqsien dly found for B1: ( 0, 14, 24)
6455 09:28:43.313170 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6456 09:28:43.316146 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6457 09:28:43.316215
6458 09:28:43.319769 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6459 09:28:43.322881 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6460 09:28:43.326558 [Gating] SW calibration Done
6461 09:28:43.326628 ==
6462 09:28:43.329918 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 09:28:43.333081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 09:28:43.333158 ==
6465 09:28:43.336369 RX Vref Scan: 0
6466 09:28:43.336444
6467 09:28:43.336502 RX Vref 0 -> 0, step: 1
6468 09:28:43.336557
6469 09:28:43.339825 RX Delay -410 -> 252, step: 16
6470 09:28:43.346166 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6471 09:28:43.349929 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6472 09:28:43.353030 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6473 09:28:43.356158 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6474 09:28:43.363390 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6475 09:28:43.366512 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6476 09:28:43.369497 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6477 09:28:43.372574 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6478 09:28:43.379509 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6479 09:28:43.382933 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6480 09:28:43.385874 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6481 09:28:43.389674 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6482 09:28:43.395905 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6483 09:28:43.399645 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6484 09:28:43.402817 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6485 09:28:43.405959 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6486 09:28:43.408951 ==
6487 09:28:43.412477 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 09:28:43.416072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 09:28:43.416150 ==
6490 09:28:43.416226 DQS Delay:
6491 09:28:43.419573 DQS0 = 59, DQS1 = 59
6492 09:28:43.419644 DQM Delay:
6493 09:28:43.422561 DQM0 = 16, DQM1 = 10
6494 09:28:43.422639 DQ Delay:
6495 09:28:43.425696 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6496 09:28:43.429433 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6497 09:28:43.432189 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6498 09:28:43.435830 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6499 09:28:43.435905
6500 09:28:43.435964
6501 09:28:43.436018 ==
6502 09:28:43.438818 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 09:28:43.442380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 09:28:43.442456 ==
6505 09:28:43.442515
6506 09:28:43.442569
6507 09:28:43.445831 TX Vref Scan disable
6508 09:28:43.445907 == TX Byte 0 ==
6509 09:28:43.452465 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6510 09:28:43.455754 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6511 09:28:43.455831 == TX Byte 1 ==
6512 09:28:43.462502 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6513 09:28:43.465586 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6514 09:28:43.465662 ==
6515 09:28:43.468593 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 09:28:43.471823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 09:28:43.471899 ==
6518 09:28:43.471975
6519 09:28:43.472032
6520 09:28:43.475462 TX Vref Scan disable
6521 09:28:43.478465 == TX Byte 0 ==
6522 09:28:43.482267 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6523 09:28:43.485315 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6524 09:28:43.485391 == TX Byte 1 ==
6525 09:28:43.491937 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6526 09:28:43.495011 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6527 09:28:43.495110
6528 09:28:43.495195 [DATLAT]
6529 09:28:43.498687 Freq=400, CH0 RK1
6530 09:28:43.498768
6531 09:28:43.498827 DATLAT Default: 0xe
6532 09:28:43.501832 0, 0xFFFF, sum = 0
6533 09:28:43.501916 1, 0xFFFF, sum = 0
6534 09:28:43.504948 2, 0xFFFF, sum = 0
6535 09:28:43.505050 3, 0xFFFF, sum = 0
6536 09:28:43.508143 4, 0xFFFF, sum = 0
6537 09:28:43.512001 5, 0xFFFF, sum = 0
6538 09:28:43.512078 6, 0xFFFF, sum = 0
6539 09:28:43.515126 7, 0xFFFF, sum = 0
6540 09:28:43.515203 8, 0xFFFF, sum = 0
6541 09:28:43.518670 9, 0xFFFF, sum = 0
6542 09:28:43.518749 10, 0xFFFF, sum = 0
6543 09:28:43.521500 11, 0xFFFF, sum = 0
6544 09:28:43.521591 12, 0xFFFF, sum = 0
6545 09:28:43.524846 13, 0x0, sum = 1
6546 09:28:43.524923 14, 0x0, sum = 2
6547 09:28:43.528050 15, 0x0, sum = 3
6548 09:28:43.528145 16, 0x0, sum = 4
6549 09:28:43.531424 best_step = 14
6550 09:28:43.531524
6551 09:28:43.531617 ==
6552 09:28:43.534622 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 09:28:43.538304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 09:28:43.538406 ==
6555 09:28:43.538482 RX Vref Scan: 0
6556 09:28:43.541434
6557 09:28:43.541511 RX Vref 0 -> 0, step: 1
6558 09:28:43.541588
6559 09:28:43.544390 RX Delay -359 -> 252, step: 8
6560 09:28:43.552531 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6561 09:28:43.555659 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6562 09:28:43.559370 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6563 09:28:43.562323 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6564 09:28:43.568821 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6565 09:28:43.572286 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6566 09:28:43.575338 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6567 09:28:43.578564 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6568 09:28:43.585521 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6569 09:28:43.589025 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6570 09:28:43.592130 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6571 09:28:43.598888 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6572 09:28:43.602132 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6573 09:28:43.605233 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6574 09:28:43.608303 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6575 09:28:43.615318 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6576 09:28:43.615400 ==
6577 09:28:43.618459 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 09:28:43.621657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 09:28:43.621741 ==
6580 09:28:43.621819 DQS Delay:
6581 09:28:43.625298 DQS0 = 60, DQS1 = 72
6582 09:28:43.625398 DQM Delay:
6583 09:28:43.628463 DQM0 = 11, DQM1 = 17
6584 09:28:43.628567 DQ Delay:
6585 09:28:43.632133 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6586 09:28:43.635365 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6587 09:28:43.638716 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6588 09:28:43.641843 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6589 09:28:43.641926
6590 09:28:43.641993
6591 09:28:43.648521 [DQSOSCAuto] RK1, (LSB)MR18= 0xc980, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6592 09:28:43.651635 CH0 RK1: MR19=C0C, MR18=C980
6593 09:28:43.658611 CH0_RK1: MR19=0xC0C, MR18=0xC980, DQSOSC=384, MR23=63, INC=400, DEC=267
6594 09:28:43.661839 [RxdqsGatingPostProcess] freq 400
6595 09:28:43.668007 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6596 09:28:43.668093 best DQS0 dly(2T, 0.5T) = (0, 10)
6597 09:28:43.671765 best DQS1 dly(2T, 0.5T) = (0, 10)
6598 09:28:43.674820 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6599 09:28:43.678332 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6600 09:28:43.681365 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 09:28:43.684804 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 09:28:43.688302 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 09:28:43.691181 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 09:28:43.694725 Pre-setting of DQS Precalculation
6605 09:28:43.701738 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6606 09:28:43.701822 ==
6607 09:28:43.704786 Dram Type= 6, Freq= 0, CH_1, rank 0
6608 09:28:43.707905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 09:28:43.707986 ==
6610 09:28:43.714750 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6611 09:28:43.717838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6612 09:28:43.721586 [CA 0] Center 36 (8~64) winsize 57
6613 09:28:43.724676 [CA 1] Center 36 (8~64) winsize 57
6614 09:28:43.727836 [CA 2] Center 36 (8~64) winsize 57
6615 09:28:43.731556 [CA 3] Center 36 (8~64) winsize 57
6616 09:28:43.734721 [CA 4] Center 36 (8~64) winsize 57
6617 09:28:43.737782 [CA 5] Center 36 (8~64) winsize 57
6618 09:28:43.737861
6619 09:28:43.741509 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6620 09:28:43.741591
6621 09:28:43.744413 [CATrainingPosCal] consider 1 rank data
6622 09:28:43.747931 u2DelayCellTimex100 = 270/100 ps
6623 09:28:43.750810 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 09:28:43.754098 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 09:28:43.757439 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 09:28:43.764701 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 09:28:43.767790 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 09:28:43.770923 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 09:28:43.771003
6630 09:28:43.774147 CA PerBit enable=1, Macro0, CA PI delay=36
6631 09:28:43.774227
6632 09:28:43.777961 [CBTSetCACLKResult] CA Dly = 36
6633 09:28:43.778041 CS Dly: 1 (0~32)
6634 09:28:43.778119 ==
6635 09:28:43.781094 Dram Type= 6, Freq= 0, CH_1, rank 1
6636 09:28:43.787707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 09:28:43.787794 ==
6638 09:28:43.791239 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 09:28:43.797433 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6640 09:28:43.801039 [CA 0] Center 36 (8~64) winsize 57
6641 09:28:43.804189 [CA 1] Center 36 (8~64) winsize 57
6642 09:28:43.807836 [CA 2] Center 36 (8~64) winsize 57
6643 09:28:43.810816 [CA 3] Center 36 (8~64) winsize 57
6644 09:28:43.814341 [CA 4] Center 36 (8~64) winsize 57
6645 09:28:43.817798 [CA 5] Center 36 (8~64) winsize 57
6646 09:28:43.817880
6647 09:28:43.821202 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6648 09:28:43.821289
6649 09:28:43.824164 [CATrainingPosCal] consider 2 rank data
6650 09:28:43.827717 u2DelayCellTimex100 = 270/100 ps
6651 09:28:43.830906 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 09:28:43.834028 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 09:28:43.837219 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 09:28:43.840994 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 09:28:43.844202 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 09:28:43.850484 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 09:28:43.850572
6658 09:28:43.853594 CA PerBit enable=1, Macro0, CA PI delay=36
6659 09:28:43.853675
6660 09:28:43.857337 [CBTSetCACLKResult] CA Dly = 36
6661 09:28:43.857417 CS Dly: 1 (0~32)
6662 09:28:43.857494
6663 09:28:43.860832 ----->DramcWriteLeveling(PI) begin...
6664 09:28:43.860913 ==
6665 09:28:43.864110 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 09:28:43.866969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 09:28:43.870416 ==
6668 09:28:43.870520 Write leveling (Byte 0): 40 => 8
6669 09:28:43.873989 Write leveling (Byte 1): 40 => 8
6670 09:28:43.877293 DramcWriteLeveling(PI) end<-----
6671 09:28:43.877371
6672 09:28:43.877430 ==
6673 09:28:43.880355 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 09:28:43.887178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 09:28:43.887262 ==
6676 09:28:43.887322 [Gating] SW mode calibration
6677 09:28:43.897149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6678 09:28:43.900182 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6679 09:28:43.907143 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6680 09:28:43.910282 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6681 09:28:43.913372 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 09:28:43.916945 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 09:28:43.923620 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 09:28:43.927069 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 09:28:43.930123 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 09:28:43.937030 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 09:28:43.940205 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 09:28:43.943378 Total UI for P1: 0, mck2ui 16
6689 09:28:43.947059 best dqsien dly found for B0: ( 0, 14, 24)
6690 09:28:43.950246 Total UI for P1: 0, mck2ui 16
6691 09:28:43.953337 best dqsien dly found for B1: ( 0, 14, 24)
6692 09:28:43.956528 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6693 09:28:43.960265 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6694 09:28:43.960345
6695 09:28:43.963310 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6696 09:28:43.969843 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6697 09:28:43.969935 [Gating] SW calibration Done
6698 09:28:43.969995 ==
6699 09:28:43.973439 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 09:28:43.979992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 09:28:43.980083 ==
6702 09:28:43.980144 RX Vref Scan: 0
6703 09:28:43.980200
6704 09:28:43.983452 RX Vref 0 -> 0, step: 1
6705 09:28:43.983530
6706 09:28:43.986549 RX Delay -410 -> 252, step: 16
6707 09:28:43.990126 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6708 09:28:43.993207 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6709 09:28:43.999770 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6710 09:28:44.003311 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6711 09:28:44.006578 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6712 09:28:44.009730 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6713 09:28:44.016517 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6714 09:28:44.020104 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6715 09:28:44.023257 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6716 09:28:44.026356 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6717 09:28:44.032845 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6718 09:28:44.036539 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6719 09:28:44.039451 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6720 09:28:44.042916 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6721 09:28:44.049867 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6722 09:28:44.052977 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6723 09:28:44.053065 ==
6724 09:28:44.056156 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 09:28:44.059312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 09:28:44.059418 ==
6727 09:28:44.062647 DQS Delay:
6728 09:28:44.062731 DQS0 = 51, DQS1 = 67
6729 09:28:44.065857 DQM Delay:
6730 09:28:44.065938 DQM0 = 12, DQM1 = 19
6731 09:28:44.066012 DQ Delay:
6732 09:28:44.069620 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6733 09:28:44.072753 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6734 09:28:44.075827 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6735 09:28:44.079251 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6736 09:28:44.079328
6737 09:28:44.079403
6738 09:28:44.079474 ==
6739 09:28:44.082915 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 09:28:44.089003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 09:28:44.089094 ==
6742 09:28:44.089172
6743 09:28:44.089244
6744 09:28:44.089313 TX Vref Scan disable
6745 09:28:44.092522 == TX Byte 0 ==
6746 09:28:44.096175 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 09:28:44.099248 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 09:28:44.102200 == TX Byte 1 ==
6749 09:28:44.105787 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 09:28:44.108918 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 09:28:44.109001 ==
6752 09:28:44.112455 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 09:28:44.119114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 09:28:44.119209 ==
6755 09:28:44.119288
6756 09:28:44.119360
6757 09:28:44.119430 TX Vref Scan disable
6758 09:28:44.122083 == TX Byte 0 ==
6759 09:28:44.125814 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 09:28:44.128884 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 09:28:44.132092 == TX Byte 1 ==
6762 09:28:44.135593 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 09:28:44.139027 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 09:28:44.139113
6765 09:28:44.142192 [DATLAT]
6766 09:28:44.142276 Freq=400, CH1 RK0
6767 09:28:44.142353
6768 09:28:44.145270 DATLAT Default: 0xf
6769 09:28:44.145350 0, 0xFFFF, sum = 0
6770 09:28:44.148901 1, 0xFFFF, sum = 0
6771 09:28:44.148988 2, 0xFFFF, sum = 0
6772 09:28:44.152314 3, 0xFFFF, sum = 0
6773 09:28:44.152397 4, 0xFFFF, sum = 0
6774 09:28:44.155289 5, 0xFFFF, sum = 0
6775 09:28:44.155370 6, 0xFFFF, sum = 0
6776 09:28:44.159047 7, 0xFFFF, sum = 0
6777 09:28:44.159128 8, 0xFFFF, sum = 0
6778 09:28:44.162211 9, 0xFFFF, sum = 0
6779 09:28:44.165315 10, 0xFFFF, sum = 0
6780 09:28:44.165396 11, 0xFFFF, sum = 0
6781 09:28:44.168498 12, 0xFFFF, sum = 0
6782 09:28:44.168578 13, 0x0, sum = 1
6783 09:28:44.172215 14, 0x0, sum = 2
6784 09:28:44.172297 15, 0x0, sum = 3
6785 09:28:44.175165 16, 0x0, sum = 4
6786 09:28:44.175247 best_step = 14
6787 09:28:44.175324
6788 09:28:44.175396 ==
6789 09:28:44.178626 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 09:28:44.182341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 09:28:44.182424 ==
6792 09:28:44.185243 RX Vref Scan: 1
6793 09:28:44.185322
6794 09:28:44.188900 RX Vref 0 -> 0, step: 1
6795 09:28:44.188995
6796 09:28:44.189074 RX Delay -375 -> 252, step: 8
6797 09:28:44.189146
6798 09:28:44.191950 Set Vref, RX VrefLevel [Byte0]: 54
6799 09:28:44.194975 [Byte1]: 48
6800 09:28:44.200469
6801 09:28:44.200558 Final RX Vref Byte 0 = 54 to rank0
6802 09:28:44.204083 Final RX Vref Byte 1 = 48 to rank0
6803 09:28:44.207628 Final RX Vref Byte 0 = 54 to rank1
6804 09:28:44.210803 Final RX Vref Byte 1 = 48 to rank1==
6805 09:28:44.213895 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 09:28:44.220526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 09:28:44.220684 ==
6808 09:28:44.220781 DQS Delay:
6809 09:28:44.223975 DQS0 = 56, DQS1 = 68
6810 09:28:44.224056 DQM Delay:
6811 09:28:44.224134 DQM0 = 13, DQM1 = 14
6812 09:28:44.227620 DQ Delay:
6813 09:28:44.230780 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6814 09:28:44.233861 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =12
6815 09:28:44.233945 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6816 09:28:44.237138 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6817 09:28:44.240737
6818 09:28:44.240848
6819 09:28:44.247282 [DQSOSCAuto] RK0, (LSB)MR18= 0x6275, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
6820 09:28:44.250408 CH1 RK0: MR19=C0C, MR18=6275
6821 09:28:44.257075 CH1_RK0: MR19=0xC0C, MR18=0x6275, DQSOSC=395, MR23=63, INC=378, DEC=252
6822 09:28:44.257170 ==
6823 09:28:44.260664 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 09:28:44.263678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 09:28:44.263760 ==
6826 09:28:44.266923 [Gating] SW mode calibration
6827 09:28:44.273853 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6828 09:28:44.280409 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6829 09:28:44.283376 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6830 09:28:44.287058 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6831 09:28:44.293706 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 09:28:44.296720 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 09:28:44.299899 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 09:28:44.306590 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 09:28:44.310070 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 09:28:44.313596 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 09:28:44.320326 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 09:28:44.320424 Total UI for P1: 0, mck2ui 16
6839 09:28:44.323472 best dqsien dly found for B0: ( 0, 14, 24)
6840 09:28:44.326555 Total UI for P1: 0, mck2ui 16
6841 09:28:44.330145 best dqsien dly found for B1: ( 0, 14, 24)
6842 09:28:44.336568 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6843 09:28:44.339787 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6844 09:28:44.339870
6845 09:28:44.343495 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6846 09:28:44.346482 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6847 09:28:44.349963 [Gating] SW calibration Done
6848 09:28:44.350045 ==
6849 09:28:44.353022 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 09:28:44.356706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 09:28:44.356787 ==
6852 09:28:44.359825 RX Vref Scan: 0
6853 09:28:44.359905
6854 09:28:44.359983 RX Vref 0 -> 0, step: 1
6855 09:28:44.360055
6856 09:28:44.362958 RX Delay -410 -> 252, step: 16
6857 09:28:44.369459 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6858 09:28:44.372558 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6859 09:28:44.376302 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6860 09:28:44.379307 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6861 09:28:44.385807 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6862 09:28:44.389508 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6863 09:28:44.392632 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6864 09:28:44.396206 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6865 09:28:44.402799 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6866 09:28:44.405741 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6867 09:28:44.409431 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6868 09:28:44.412614 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6869 09:28:44.419253 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6870 09:28:44.422517 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6871 09:28:44.426085 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6872 09:28:44.432261 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6873 09:28:44.432348 ==
6874 09:28:44.435894 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 09:28:44.438864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 09:28:44.438944 ==
6877 09:28:44.439008 DQS Delay:
6878 09:28:44.442418 DQS0 = 59, DQS1 = 59
6879 09:28:44.442503 DQM Delay:
6880 09:28:44.445549 DQM0 = 18, DQM1 = 12
6881 09:28:44.445628 DQ Delay:
6882 09:28:44.448601 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6883 09:28:44.452336 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6884 09:28:44.455197 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6885 09:28:44.458861 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6886 09:28:44.458947
6887 09:28:44.459025
6888 09:28:44.459097 ==
6889 09:28:44.461929 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 09:28:44.465625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 09:28:44.465708 ==
6892 09:28:44.465787
6893 09:28:44.465858
6894 09:28:44.468804 TX Vref Scan disable
6895 09:28:44.471838 == TX Byte 0 ==
6896 09:28:44.475284 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6897 09:28:44.478374 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6898 09:28:44.478457 == TX Byte 1 ==
6899 09:28:44.485068 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6900 09:28:44.488635 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6901 09:28:44.488765 ==
6902 09:28:44.491801 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 09:28:44.495046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 09:28:44.495139 ==
6905 09:28:44.498608
6906 09:28:44.498689
6907 09:28:44.498766 TX Vref Scan disable
6908 09:28:44.501565 == TX Byte 0 ==
6909 09:28:44.505212 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6910 09:28:44.508362 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6911 09:28:44.511516 == TX Byte 1 ==
6912 09:28:44.515185 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6913 09:28:44.518295 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6914 09:28:44.518376
6915 09:28:44.518436 [DATLAT]
6916 09:28:44.521450 Freq=400, CH1 RK1
6917 09:28:44.521528
6918 09:28:44.521588 DATLAT Default: 0xe
6919 09:28:44.524563 0, 0xFFFF, sum = 0
6920 09:28:44.528025 1, 0xFFFF, sum = 0
6921 09:28:44.528106 2, 0xFFFF, sum = 0
6922 09:28:44.531531 3, 0xFFFF, sum = 0
6923 09:28:44.531611 4, 0xFFFF, sum = 0
6924 09:28:44.534590 5, 0xFFFF, sum = 0
6925 09:28:44.534670 6, 0xFFFF, sum = 0
6926 09:28:44.537697 7, 0xFFFF, sum = 0
6927 09:28:44.537777 8, 0xFFFF, sum = 0
6928 09:28:44.541360 9, 0xFFFF, sum = 0
6929 09:28:44.541464 10, 0xFFFF, sum = 0
6930 09:28:44.544290 11, 0xFFFF, sum = 0
6931 09:28:44.544370 12, 0xFFFF, sum = 0
6932 09:28:44.547820 13, 0x0, sum = 1
6933 09:28:44.547899 14, 0x0, sum = 2
6934 09:28:44.551177 15, 0x0, sum = 3
6935 09:28:44.551279 16, 0x0, sum = 4
6936 09:28:44.554228 best_step = 14
6937 09:28:44.554305
6938 09:28:44.554364 ==
6939 09:28:44.557777 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 09:28:44.560690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 09:28:44.560770 ==
6942 09:28:44.564194 RX Vref Scan: 0
6943 09:28:44.564274
6944 09:28:44.564333 RX Vref 0 -> 0, step: 1
6945 09:28:44.564389
6946 09:28:44.567731 RX Delay -359 -> 252, step: 8
6947 09:28:44.575619 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6948 09:28:44.579076 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6949 09:28:44.582020 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6950 09:28:44.585164 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6951 09:28:44.591917 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6952 09:28:44.595520 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6953 09:28:44.598662 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6954 09:28:44.601812 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6955 09:28:44.608801 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6956 09:28:44.612211 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6957 09:28:44.615325 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6958 09:28:44.621669 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6959 09:28:44.625429 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6960 09:28:44.628446 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6961 09:28:44.631469 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6962 09:28:44.638129 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6963 09:28:44.638222 ==
6964 09:28:44.641841 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 09:28:44.644987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 09:28:44.645070 ==
6967 09:28:44.645130 DQS Delay:
6968 09:28:44.648156 DQS0 = 60, DQS1 = 64
6969 09:28:44.648233 DQM Delay:
6970 09:28:44.651788 DQM0 = 12, DQM1 = 10
6971 09:28:44.651867 DQ Delay:
6972 09:28:44.654845 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6973 09:28:44.658287 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6974 09:28:44.661906 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6975 09:28:44.665121 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6976 09:28:44.665207
6977 09:28:44.665266
6978 09:28:44.671553 [DQSOSCAuto] RK1, (LSB)MR18= 0x79aa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6979 09:28:44.674959 CH1 RK1: MR19=C0C, MR18=79AA
6980 09:28:44.681725 CH1_RK1: MR19=0xC0C, MR18=0x79AA, DQSOSC=388, MR23=63, INC=392, DEC=261
6981 09:28:44.684665 [RxdqsGatingPostProcess] freq 400
6982 09:28:44.691718 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6983 09:28:44.694866 best DQS0 dly(2T, 0.5T) = (0, 10)
6984 09:28:44.694952 best DQS1 dly(2T, 0.5T) = (0, 10)
6985 09:28:44.698328 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6986 09:28:44.701542 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6987 09:28:44.704581 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 09:28:44.708412 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 09:28:44.711453 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 09:28:44.714912 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 09:28:44.718262 Pre-setting of DQS Precalculation
6992 09:28:44.724861 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6993 09:28:44.731613 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6994 09:28:44.738391 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6995 09:28:44.738513
6996 09:28:44.738573
6997 09:28:44.741512 [Calibration Summary] 800 Mbps
6998 09:28:44.741639 CH 0, Rank 0
6999 09:28:44.744383 SW Impedance : PASS
7000 09:28:44.748132 DUTY Scan : NO K
7001 09:28:44.748217 ZQ Calibration : PASS
7002 09:28:44.751540 Jitter Meter : NO K
7003 09:28:44.751616 CBT Training : PASS
7004 09:28:44.754581 Write leveling : PASS
7005 09:28:44.757695 RX DQS gating : PASS
7006 09:28:44.757779 RX DQ/DQS(RDDQC) : PASS
7007 09:28:44.761323 TX DQ/DQS : PASS
7008 09:28:44.764372 RX DATLAT : PASS
7009 09:28:44.764481 RX DQ/DQS(Engine): PASS
7010 09:28:44.767747 TX OE : NO K
7011 09:28:44.767835 All Pass.
7012 09:28:44.767895
7013 09:28:44.771496 CH 0, Rank 1
7014 09:28:44.771576 SW Impedance : PASS
7015 09:28:44.774476 DUTY Scan : NO K
7016 09:28:44.777555 ZQ Calibration : PASS
7017 09:28:44.777658 Jitter Meter : NO K
7018 09:28:44.781006 CBT Training : PASS
7019 09:28:44.784460 Write leveling : NO K
7020 09:28:44.784541 RX DQS gating : PASS
7021 09:28:44.787808 RX DQ/DQS(RDDQC) : PASS
7022 09:28:44.790803 TX DQ/DQS : PASS
7023 09:28:44.790885 RX DATLAT : PASS
7024 09:28:44.794381 RX DQ/DQS(Engine): PASS
7025 09:28:44.797308 TX OE : NO K
7026 09:28:44.797389 All Pass.
7027 09:28:44.797465
7028 09:28:44.797521 CH 1, Rank 0
7029 09:28:44.800811 SW Impedance : PASS
7030 09:28:44.803857 DUTY Scan : NO K
7031 09:28:44.803936 ZQ Calibration : PASS
7032 09:28:44.807643 Jitter Meter : NO K
7033 09:28:44.810763 CBT Training : PASS
7034 09:28:44.810842 Write leveling : PASS
7035 09:28:44.813869 RX DQS gating : PASS
7036 09:28:44.817616 RX DQ/DQS(RDDQC) : PASS
7037 09:28:44.817699 TX DQ/DQS : PASS
7038 09:28:44.820700 RX DATLAT : PASS
7039 09:28:44.820777 RX DQ/DQS(Engine): PASS
7040 09:28:44.823714 TX OE : NO K
7041 09:28:44.823791 All Pass.
7042 09:28:44.823850
7043 09:28:44.827071 CH 1, Rank 1
7044 09:28:44.827148 SW Impedance : PASS
7045 09:28:44.830535 DUTY Scan : NO K
7046 09:28:44.833650 ZQ Calibration : PASS
7047 09:28:44.833751 Jitter Meter : NO K
7048 09:28:44.837516 CBT Training : PASS
7049 09:28:44.840519 Write leveling : NO K
7050 09:28:44.840625 RX DQS gating : PASS
7051 09:28:44.843655 RX DQ/DQS(RDDQC) : PASS
7052 09:28:44.847412 TX DQ/DQS : PASS
7053 09:28:44.847495 RX DATLAT : PASS
7054 09:28:44.850438 RX DQ/DQS(Engine): PASS
7055 09:28:44.854084 TX OE : NO K
7056 09:28:44.854167 All Pass.
7057 09:28:44.854227
7058 09:28:44.854281 DramC Write-DBI off
7059 09:28:44.857239 PER_BANK_REFRESH: Hybrid Mode
7060 09:28:44.860389 TX_TRACKING: ON
7061 09:28:44.866797 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7062 09:28:44.873477 [FAST_K] Save calibration result to emmc
7063 09:28:44.876995 dramc_set_vcore_voltage set vcore to 725000
7064 09:28:44.877082 Read voltage for 1600, 0
7065 09:28:44.880092 Vio18 = 0
7066 09:28:44.880170 Vcore = 725000
7067 09:28:44.880229 Vdram = 0
7068 09:28:44.883320 Vddq = 0
7069 09:28:44.883399 Vmddr = 0
7070 09:28:44.887051 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7071 09:28:44.893298 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7072 09:28:44.896680 MEM_TYPE=3, freq_sel=13
7073 09:28:44.900008 sv_algorithm_assistance_LP4_3733
7074 09:28:44.903431 ============ PULL DRAM RESETB DOWN ============
7075 09:28:44.906869 ========== PULL DRAM RESETB DOWN end =========
7076 09:28:44.913478 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7077 09:28:44.916613 ===================================
7078 09:28:44.916737 LPDDR4 DRAM CONFIGURATION
7079 09:28:44.920384 ===================================
7080 09:28:44.923507 EX_ROW_EN[0] = 0x0
7081 09:28:44.923617 EX_ROW_EN[1] = 0x0
7082 09:28:44.926440 LP4Y_EN = 0x0
7083 09:28:44.926518 WORK_FSP = 0x1
7084 09:28:44.930087 WL = 0x5
7085 09:28:44.932926 RL = 0x5
7086 09:28:44.933007 BL = 0x2
7087 09:28:44.936347 RPST = 0x0
7088 09:28:44.936464 RD_PRE = 0x0
7089 09:28:44.939602 WR_PRE = 0x1
7090 09:28:44.939681 WR_PST = 0x1
7091 09:28:44.943305 DBI_WR = 0x0
7092 09:28:44.943389 DBI_RD = 0x0
7093 09:28:44.946315 OTF = 0x1
7094 09:28:44.949487 ===================================
7095 09:28:44.953270 ===================================
7096 09:28:44.953351 ANA top config
7097 09:28:44.956230 ===================================
7098 09:28:44.959863 DLL_ASYNC_EN = 0
7099 09:28:44.962854 ALL_SLAVE_EN = 0
7100 09:28:44.962942 NEW_RANK_MODE = 1
7101 09:28:44.966610 DLL_IDLE_MODE = 1
7102 09:28:44.969806 LP45_APHY_COMB_EN = 1
7103 09:28:44.972962 TX_ODT_DIS = 0
7104 09:28:44.976169 NEW_8X_MODE = 1
7105 09:28:44.979750 ===================================
7106 09:28:44.979857 ===================================
7107 09:28:44.982761 data_rate = 3200
7108 09:28:44.986213 CKR = 1
7109 09:28:44.989459 DQ_P2S_RATIO = 8
7110 09:28:44.993211 ===================================
7111 09:28:44.996342 CA_P2S_RATIO = 8
7112 09:28:44.999331 DQ_CA_OPEN = 0
7113 09:28:45.003067 DQ_SEMI_OPEN = 0
7114 09:28:45.003152 CA_SEMI_OPEN = 0
7115 09:28:45.006156 CA_FULL_RATE = 0
7116 09:28:45.009472 DQ_CKDIV4_EN = 0
7117 09:28:45.013005 CA_CKDIV4_EN = 0
7118 09:28:45.016010 CA_PREDIV_EN = 0
7119 09:28:45.019503 PH8_DLY = 12
7120 09:28:45.019585 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7121 09:28:45.023278 DQ_AAMCK_DIV = 4
7122 09:28:45.026008 CA_AAMCK_DIV = 4
7123 09:28:45.029700 CA_ADMCK_DIV = 4
7124 09:28:45.032797 DQ_TRACK_CA_EN = 0
7125 09:28:45.035955 CA_PICK = 1600
7126 09:28:45.039705 CA_MCKIO = 1600
7127 09:28:45.039803 MCKIO_SEMI = 0
7128 09:28:45.042680 PLL_FREQ = 3068
7129 09:28:45.046290 DQ_UI_PI_RATIO = 32
7130 09:28:45.049274 CA_UI_PI_RATIO = 0
7131 09:28:45.053066 ===================================
7132 09:28:45.056294 ===================================
7133 09:28:45.059393 memory_type:LPDDR4
7134 09:28:45.059472 GP_NUM : 10
7135 09:28:45.063077 SRAM_EN : 1
7136 09:28:45.063165 MD32_EN : 0
7137 09:28:45.065948 ===================================
7138 09:28:45.069272 [ANA_INIT] >>>>>>>>>>>>>>
7139 09:28:45.072989 <<<<<< [CONFIGURE PHASE]: ANA_TX
7140 09:28:45.076158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7141 09:28:45.079381 ===================================
7142 09:28:45.082520 data_rate = 3200,PCW = 0X7600
7143 09:28:45.086064 ===================================
7144 09:28:45.089036 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7145 09:28:45.095675 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7146 09:28:45.098766 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7147 09:28:45.105822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7148 09:28:45.108936 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7149 09:28:45.112567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7150 09:28:45.112720 [ANA_INIT] flow start
7151 09:28:45.115510 [ANA_INIT] PLL >>>>>>>>
7152 09:28:45.119226 [ANA_INIT] PLL <<<<<<<<
7153 09:28:45.119312 [ANA_INIT] MIDPI >>>>>>>>
7154 09:28:45.122397 [ANA_INIT] MIDPI <<<<<<<<
7155 09:28:45.125466 [ANA_INIT] DLL >>>>>>>>
7156 09:28:45.128931 [ANA_INIT] DLL <<<<<<<<
7157 09:28:45.129043 [ANA_INIT] flow end
7158 09:28:45.131972 ============ LP4 DIFF to SE enter ============
7159 09:28:45.138993 ============ LP4 DIFF to SE exit ============
7160 09:28:45.139085 [ANA_INIT] <<<<<<<<<<<<<
7161 09:28:45.142016 [Flow] Enable top DCM control >>>>>
7162 09:28:45.145222 [Flow] Enable top DCM control <<<<<
7163 09:28:45.148832 Enable DLL master slave shuffle
7164 09:28:45.155174 ==============================================================
7165 09:28:45.155269 Gating Mode config
7166 09:28:45.162035 ==============================================================
7167 09:28:45.165213 Config description:
7168 09:28:45.175122 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7169 09:28:45.182010 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7170 09:28:45.185139 SELPH_MODE 0: By rank 1: By Phase
7171 09:28:45.192064 ==============================================================
7172 09:28:45.195109 GAT_TRACK_EN = 1
7173 09:28:45.195194 RX_GATING_MODE = 2
7174 09:28:45.198680 RX_GATING_TRACK_MODE = 2
7175 09:28:45.201516 SELPH_MODE = 1
7176 09:28:45.205288 PICG_EARLY_EN = 1
7177 09:28:45.208256 VALID_LAT_VALUE = 1
7178 09:28:45.215100 ==============================================================
7179 09:28:45.218086 Enter into Gating configuration >>>>
7180 09:28:45.221610 Exit from Gating configuration <<<<
7181 09:28:45.224600 Enter into DVFS_PRE_config >>>>>
7182 09:28:45.234610 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7183 09:28:45.238451 Exit from DVFS_PRE_config <<<<<
7184 09:28:45.241480 Enter into PICG configuration >>>>
7185 09:28:45.244562 Exit from PICG configuration <<<<
7186 09:28:45.248065 [RX_INPUT] configuration >>>>>
7187 09:28:45.251244 [RX_INPUT] configuration <<<<<
7188 09:28:45.254960 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7189 09:28:45.261380 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7190 09:28:45.268118 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7191 09:28:45.274877 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7192 09:28:45.278086 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 09:28:45.284571 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 09:28:45.287717 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7195 09:28:45.294837 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7196 09:28:45.297923 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7197 09:28:45.301035 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7198 09:28:45.304635 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7199 09:28:45.311286 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 09:28:45.314409 ===================================
7201 09:28:45.314495 LPDDR4 DRAM CONFIGURATION
7202 09:28:45.317595 ===================================
7203 09:28:45.321390 EX_ROW_EN[0] = 0x0
7204 09:28:45.324465 EX_ROW_EN[1] = 0x0
7205 09:28:45.324544 LP4Y_EN = 0x0
7206 09:28:45.327462 WORK_FSP = 0x1
7207 09:28:45.327540 WL = 0x5
7208 09:28:45.330847 RL = 0x5
7209 09:28:45.330926 BL = 0x2
7210 09:28:45.334372 RPST = 0x0
7211 09:28:45.334453 RD_PRE = 0x0
7212 09:28:45.337895 WR_PRE = 0x1
7213 09:28:45.337974 WR_PST = 0x1
7214 09:28:45.341025 DBI_WR = 0x0
7215 09:28:45.341103 DBI_RD = 0x0
7216 09:28:45.344239 OTF = 0x1
7217 09:28:45.347322 ===================================
7218 09:28:45.351013 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7219 09:28:45.353963 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7220 09:28:45.360919 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7221 09:28:45.364098 ===================================
7222 09:28:45.364187 LPDDR4 DRAM CONFIGURATION
7223 09:28:45.367283 ===================================
7224 09:28:45.370974 EX_ROW_EN[0] = 0x10
7225 09:28:45.373977 EX_ROW_EN[1] = 0x0
7226 09:28:45.374058 LP4Y_EN = 0x0
7227 09:28:45.377469 WORK_FSP = 0x1
7228 09:28:45.377550 WL = 0x5
7229 09:28:45.380799 RL = 0x5
7230 09:28:45.380911 BL = 0x2
7231 09:28:45.383884 RPST = 0x0
7232 09:28:45.383988 RD_PRE = 0x0
7233 09:28:45.387568 WR_PRE = 0x1
7234 09:28:45.387648 WR_PST = 0x1
7235 09:28:45.390453 DBI_WR = 0x0
7236 09:28:45.390532 DBI_RD = 0x0
7237 09:28:45.393932 OTF = 0x1
7238 09:28:45.397190 ===================================
7239 09:28:45.404000 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7240 09:28:45.404090 ==
7241 09:28:45.407110 Dram Type= 6, Freq= 0, CH_0, rank 0
7242 09:28:45.410656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7243 09:28:45.410737 ==
7244 09:28:45.413700 [Duty_Offset_Calibration]
7245 09:28:45.413801 B0:2 B1:0 CA:3
7246 09:28:45.413887
7247 09:28:45.417292 [DutyScan_Calibration_Flow] k_type=0
7248 09:28:45.427474
7249 09:28:45.427571 ==CLK 0==
7250 09:28:45.431253 Final CLK duty delay cell = 0
7251 09:28:45.434252 [0] MAX Duty = 5031%(X100), DQS PI = 12
7252 09:28:45.437858 [0] MIN Duty = 4907%(X100), DQS PI = 6
7253 09:28:45.437940 [0] AVG Duty = 4969%(X100)
7254 09:28:45.440921
7255 09:28:45.444461 CH0 CLK Duty spec in!! Max-Min= 124%
7256 09:28:45.447466 [DutyScan_Calibration_Flow] ====Done====
7257 09:28:45.447549
7258 09:28:45.450624 [DutyScan_Calibration_Flow] k_type=1
7259 09:28:45.467371
7260 09:28:45.467489 ==DQS 0 ==
7261 09:28:45.470499 Final DQS duty delay cell = 0
7262 09:28:45.474228 [0] MAX Duty = 5094%(X100), DQS PI = 30
7263 09:28:45.477349 [0] MIN Duty = 4875%(X100), DQS PI = 46
7264 09:28:45.480425 [0] AVG Duty = 4984%(X100)
7265 09:28:45.480508
7266 09:28:45.480569 ==DQS 1 ==
7267 09:28:45.484451 Final DQS duty delay cell = 0
7268 09:28:45.487375 [0] MAX Duty = 5156%(X100), DQS PI = 30
7269 09:28:45.490259 [0] MIN Duty = 5031%(X100), DQS PI = 14
7270 09:28:45.493777 [0] AVG Duty = 5093%(X100)
7271 09:28:45.493873
7272 09:28:45.497333 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7273 09:28:45.497415
7274 09:28:45.500323 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7275 09:28:45.503946 [DutyScan_Calibration_Flow] ====Done====
7276 09:28:45.504045
7277 09:28:45.507042 [DutyScan_Calibration_Flow] k_type=3
7278 09:28:45.525273
7279 09:28:45.525389 ==DQM 0 ==
7280 09:28:45.528490 Final DQM duty delay cell = 0
7281 09:28:45.531683 [0] MAX Duty = 5156%(X100), DQS PI = 30
7282 09:28:45.535313 [0] MIN Duty = 4875%(X100), DQS PI = 0
7283 09:28:45.538512 [0] AVG Duty = 5015%(X100)
7284 09:28:45.538595
7285 09:28:45.538655 ==DQM 1 ==
7286 09:28:45.542032 Final DQM duty delay cell = 4
7287 09:28:45.545213 [4] MAX Duty = 5187%(X100), DQS PI = 62
7288 09:28:45.548576 [4] MIN Duty = 5031%(X100), DQS PI = 12
7289 09:28:45.551498 [4] AVG Duty = 5109%(X100)
7290 09:28:45.551579
7291 09:28:45.555025 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7292 09:28:45.555109
7293 09:28:45.558122 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7294 09:28:45.561864 [DutyScan_Calibration_Flow] ====Done====
7295 09:28:45.561985
7296 09:28:45.564800 [DutyScan_Calibration_Flow] k_type=2
7297 09:28:45.581688
7298 09:28:45.581802 ==DQ 0 ==
7299 09:28:45.584895 Final DQ duty delay cell = -4
7300 09:28:45.588050 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7301 09:28:45.591040 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7302 09:28:45.594705 [-4] AVG Duty = 4938%(X100)
7303 09:28:45.594792
7304 09:28:45.594853 ==DQ 1 ==
7305 09:28:45.598010 Final DQ duty delay cell = 0
7306 09:28:45.601419 [0] MAX Duty = 5156%(X100), DQS PI = 58
7307 09:28:45.604378 [0] MIN Duty = 5000%(X100), DQS PI = 16
7308 09:28:45.607999 [0] AVG Duty = 5078%(X100)
7309 09:28:45.608110
7310 09:28:45.611087 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7311 09:28:45.611181
7312 09:28:45.614849 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7313 09:28:45.618023 [DutyScan_Calibration_Flow] ====Done====
7314 09:28:45.618124 ==
7315 09:28:45.620984 Dram Type= 6, Freq= 0, CH_1, rank 0
7316 09:28:45.624470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7317 09:28:45.624543 ==
7318 09:28:45.627948 [Duty_Offset_Calibration]
7319 09:28:45.628018 B0:1 B1:-2 CA:0
7320 09:28:45.628084
7321 09:28:45.631083 [DutyScan_Calibration_Flow] k_type=0
7322 09:28:45.641823
7323 09:28:45.641946 ==CLK 0==
7324 09:28:45.645470 Final CLK duty delay cell = 0
7325 09:28:45.648477 [0] MAX Duty = 5062%(X100), DQS PI = 22
7326 09:28:45.652224 [0] MIN Duty = 4813%(X100), DQS PI = 60
7327 09:28:45.652308 [0] AVG Duty = 4937%(X100)
7328 09:28:45.655283
7329 09:28:45.658347 CH1 CLK Duty spec in!! Max-Min= 249%
7330 09:28:45.661710 [DutyScan_Calibration_Flow] ====Done====
7331 09:28:45.661794
7332 09:28:45.665302 [DutyScan_Calibration_Flow] k_type=1
7333 09:28:45.681283
7334 09:28:45.681398 ==DQS 0 ==
7335 09:28:45.685004 Final DQS duty delay cell = 0
7336 09:28:45.688164 [0] MAX Duty = 5187%(X100), DQS PI = 26
7337 09:28:45.691385 [0] MIN Duty = 5031%(X100), DQS PI = 54
7338 09:28:45.695058 [0] AVG Duty = 5109%(X100)
7339 09:28:45.695139
7340 09:28:45.695221 ==DQS 1 ==
7341 09:28:45.698122 Final DQS duty delay cell = 0
7342 09:28:45.701338 [0] MAX Duty = 5093%(X100), DQS PI = 60
7343 09:28:45.704852 [0] MIN Duty = 4844%(X100), DQS PI = 24
7344 09:28:45.708269 [0] AVG Duty = 4968%(X100)
7345 09:28:45.708351
7346 09:28:45.711053 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7347 09:28:45.711149
7348 09:28:45.714307 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7349 09:28:45.718230 [DutyScan_Calibration_Flow] ====Done====
7350 09:28:45.718315
7351 09:28:45.721226 [DutyScan_Calibration_Flow] k_type=3
7352 09:28:45.738425
7353 09:28:45.738547 ==DQM 0 ==
7354 09:28:45.741593 Final DQM duty delay cell = 0
7355 09:28:45.744761 [0] MAX Duty = 5031%(X100), DQS PI = 26
7356 09:28:45.748493 [0] MIN Duty = 4813%(X100), DQS PI = 56
7357 09:28:45.751654 [0] AVG Duty = 4922%(X100)
7358 09:28:45.751742
7359 09:28:45.751803 ==DQM 1 ==
7360 09:28:45.754765 Final DQM duty delay cell = 0
7361 09:28:45.758488 [0] MAX Duty = 5062%(X100), DQS PI = 34
7362 09:28:45.761519 [0] MIN Duty = 4875%(X100), DQS PI = 26
7363 09:28:45.765073 [0] AVG Duty = 4968%(X100)
7364 09:28:45.765148
7365 09:28:45.768036 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7366 09:28:45.768124
7367 09:28:45.771481 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7368 09:28:45.774571 [DutyScan_Calibration_Flow] ====Done====
7369 09:28:45.774647
7370 09:28:45.778218 [DutyScan_Calibration_Flow] k_type=2
7371 09:28:45.794888
7372 09:28:45.794997 ==DQ 0 ==
7373 09:28:45.798571 Final DQ duty delay cell = 0
7374 09:28:45.801642 [0] MAX Duty = 5093%(X100), DQS PI = 20
7375 09:28:45.804816 [0] MIN Duty = 4907%(X100), DQS PI = 48
7376 09:28:45.804910 [0] AVG Duty = 5000%(X100)
7377 09:28:45.808072
7378 09:28:45.808179 ==DQ 1 ==
7379 09:28:45.811925 Final DQ duty delay cell = 0
7380 09:28:45.814932 [0] MAX Duty = 5156%(X100), DQS PI = 36
7381 09:28:45.818427 [0] MIN Duty = 4969%(X100), DQS PI = 24
7382 09:28:45.818547 [0] AVG Duty = 5062%(X100)
7383 09:28:45.821444
7384 09:28:45.824896 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7385 09:28:45.825013
7386 09:28:45.828457 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7387 09:28:45.832027 [DutyScan_Calibration_Flow] ====Done====
7388 09:28:45.834969 nWR fixed to 30
7389 09:28:45.835117 [ModeRegInit_LP4] CH0 RK0
7390 09:28:45.837997 [ModeRegInit_LP4] CH0 RK1
7391 09:28:45.841479 [ModeRegInit_LP4] CH1 RK0
7392 09:28:45.844457 [ModeRegInit_LP4] CH1 RK1
7393 09:28:45.844573 match AC timing 5
7394 09:28:45.851446 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7395 09:28:45.854977 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7396 09:28:45.858174 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7397 09:28:45.864900 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7398 09:28:45.867925 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7399 09:28:45.868015 [MiockJmeterHQA]
7400 09:28:45.868075
7401 09:28:45.871594 [DramcMiockJmeter] u1RxGatingPI = 0
7402 09:28:45.874620 0 : 4257, 4029
7403 09:28:45.874701 4 : 4255, 4030
7404 09:28:45.877690 8 : 4258, 4029
7405 09:28:45.877815 12 : 4260, 4031
7406 09:28:45.877899 16 : 4366, 4140
7407 09:28:45.881322 20 : 4365, 4140
7408 09:28:45.881437 24 : 4371, 4142
7409 09:28:45.884550 28 : 4255, 4029
7410 09:28:45.884628 32 : 4258, 4029
7411 09:28:45.888092 36 : 4260, 4032
7412 09:28:45.888184 40 : 4257, 4029
7413 09:28:45.891165 44 : 4258, 4029
7414 09:28:45.891241 48 : 4254, 4029
7415 09:28:45.891303 52 : 4366, 4140
7416 09:28:45.894171 56 : 4363, 4140
7417 09:28:45.894263 60 : 4252, 4029
7418 09:28:45.897879 64 : 4253, 4029
7419 09:28:45.897953 68 : 4255, 4029
7420 09:28:45.901053 72 : 4250, 4027
7421 09:28:45.901126 76 : 4258, 4032
7422 09:28:45.904195 80 : 4255, 4029
7423 09:28:45.904293 84 : 4255, 4029
7424 09:28:45.904379 88 : 4365, 4140
7425 09:28:45.908073 92 : 4250, 4026
7426 09:28:45.908146 96 : 4253, 4029
7427 09:28:45.911293 100 : 4361, 4137
7428 09:28:45.911362 104 : 4252, 3423
7429 09:28:45.914417 108 : 4363, 0
7430 09:28:45.914521 112 : 4365, 0
7431 09:28:45.914608 116 : 4255, 0
7432 09:28:45.917629 120 : 4253, 0
7433 09:28:45.917709 124 : 4252, 0
7434 09:28:45.921346 128 : 4250, 0
7435 09:28:45.921419 132 : 4255, 0
7436 09:28:45.921506 136 : 4252, 0
7437 09:28:45.924400 140 : 4365, 0
7438 09:28:45.924509 144 : 4252, 0
7439 09:28:45.924595 148 : 4363, 0
7440 09:28:45.927895 152 : 4254, 0
7441 09:28:45.927983 156 : 4250, 0
7442 09:28:45.930840 160 : 4255, 0
7443 09:28:45.930917 164 : 4252, 0
7444 09:28:45.930974 168 : 4255, 0
7445 09:28:45.934376 172 : 4253, 0
7446 09:28:45.934475 176 : 4252, 0
7447 09:28:45.937771 180 : 4252, 0
7448 09:28:45.937851 184 : 4258, 0
7449 09:28:45.937913 188 : 4363, 0
7450 09:28:45.940909 192 : 4365, 0
7451 09:28:45.941018 196 : 4250, 0
7452 09:28:45.944234 200 : 4363, 0
7453 09:28:45.944325 204 : 4363, 0
7454 09:28:45.944423 208 : 4253, 0
7455 09:28:45.947768 212 : 4255, 0
7456 09:28:45.947852 216 : 4252, 0
7457 09:28:45.947916 220 : 4255, 0
7458 09:28:45.950753 224 : 4253, 0
7459 09:28:45.950842 228 : 4253, 0
7460 09:28:45.953954 232 : 4253, 0
7461 09:28:45.954037 236 : 4253, 1356
7462 09:28:45.957498 240 : 4253, 4029
7463 09:28:45.957583 244 : 4365, 4140
7464 09:28:45.960616 248 : 4366, 4140
7465 09:28:45.960747 252 : 4257, 4032
7466 09:28:45.960846 256 : 4255, 4029
7467 09:28:45.964219 260 : 4255, 4029
7468 09:28:45.964305 264 : 4252, 4029
7469 09:28:45.967421 268 : 4258, 4032
7470 09:28:45.967512 272 : 4252, 4030
7471 09:28:45.970549 276 : 4365, 4140
7472 09:28:45.970633 280 : 4365, 4139
7473 09:28:45.974124 284 : 4252, 4029
7474 09:28:45.974223 288 : 4255, 4029
7475 09:28:45.977281 292 : 4253, 4029
7476 09:28:45.977378 296 : 4255, 4029
7477 09:28:45.980416 300 : 4363, 4139
7478 09:28:45.980513 304 : 4255, 4029
7479 09:28:45.984009 308 : 4255, 4030
7480 09:28:45.984090 312 : 4363, 4140
7481 09:28:45.987008 316 : 4252, 4030
7482 09:28:45.987114 320 : 4255, 4029
7483 09:28:45.987279 324 : 4366, 4140
7484 09:28:45.990711 328 : 4365, 4140
7485 09:28:45.990800 332 : 4252, 4029
7486 09:28:45.994237 336 : 4363, 4140
7487 09:28:45.994361 340 : 4255, 4029
7488 09:28:45.997155 344 : 4252, 4029
7489 09:28:45.997259 348 : 4255, 4029
7490 09:28:46.000860 352 : 4252, 3990
7491 09:28:46.000944 356 : 4257, 2706
7492 09:28:46.004113 360 : 4255, 0
7493 09:28:46.004217
7494 09:28:46.004304 MIOCK jitter meter ch=0
7495 09:28:46.004387
7496 09:28:46.007274 1T = (360-108) = 252 dly cells
7497 09:28:46.014205 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7498 09:28:46.014310 ==
7499 09:28:46.017365 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 09:28:46.020522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7501 09:28:46.020633 ==
7502 09:28:46.027006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7503 09:28:46.030671 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7504 09:28:46.033660 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7505 09:28:46.040106 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7506 09:28:46.049874 [CA 0] Center 44 (14~75) winsize 62
7507 09:28:46.053481 [CA 1] Center 43 (13~74) winsize 62
7508 09:28:46.056845 [CA 2] Center 39 (10~69) winsize 60
7509 09:28:46.060061 [CA 3] Center 39 (10~68) winsize 59
7510 09:28:46.063341 [CA 4] Center 37 (8~67) winsize 60
7511 09:28:46.066940 [CA 5] Center 37 (7~67) winsize 61
7512 09:28:46.067020
7513 09:28:46.069725 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7514 09:28:46.069800
7515 09:28:46.076506 [CATrainingPosCal] consider 1 rank data
7516 09:28:46.076623 u2DelayCellTimex100 = 258/100 ps
7517 09:28:46.083435 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7518 09:28:46.086535 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7519 09:28:46.089529 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7520 09:28:46.093084 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7521 09:28:46.096558 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7522 09:28:46.099588 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7523 09:28:46.099667
7524 09:28:46.103233 CA PerBit enable=1, Macro0, CA PI delay=37
7525 09:28:46.103309
7526 09:28:46.106291 [CBTSetCACLKResult] CA Dly = 37
7527 09:28:46.109421 CS Dly: 11 (0~42)
7528 09:28:46.113088 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7529 09:28:46.116113 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7530 09:28:46.116212 ==
7531 09:28:46.119269 Dram Type= 6, Freq= 0, CH_0, rank 1
7532 09:28:46.126267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 09:28:46.126380 ==
7534 09:28:46.129319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 09:28:46.136094 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 09:28:46.139092 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 09:28:46.145727 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 09:28:46.153918 [CA 0] Center 44 (14~75) winsize 62
7539 09:28:46.157176 [CA 1] Center 43 (13~74) winsize 62
7540 09:28:46.160383 [CA 2] Center 39 (10~69) winsize 60
7541 09:28:46.164065 [CA 3] Center 39 (10~68) winsize 59
7542 09:28:46.167272 [CA 4] Center 37 (8~67) winsize 60
7543 09:28:46.170689 [CA 5] Center 36 (7~66) winsize 60
7544 09:28:46.170789
7545 09:28:46.173931 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7546 09:28:46.174038
7547 09:28:46.177028 [CATrainingPosCal] consider 2 rank data
7548 09:28:46.180259 u2DelayCellTimex100 = 258/100 ps
7549 09:28:46.183604 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7550 09:28:46.190588 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7551 09:28:46.193686 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7552 09:28:46.196812 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7553 09:28:46.200348 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7554 09:28:46.203903 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7555 09:28:46.204004
7556 09:28:46.207013 CA PerBit enable=1, Macro0, CA PI delay=36
7557 09:28:46.207085
7558 09:28:46.210484 [CBTSetCACLKResult] CA Dly = 36
7559 09:28:46.213608 CS Dly: 11 (0~43)
7560 09:28:46.217305 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 09:28:46.220445 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 09:28:46.220555
7563 09:28:46.223731 ----->DramcWriteLeveling(PI) begin...
7564 09:28:46.223801 ==
7565 09:28:46.226809 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 09:28:46.233715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 09:28:46.233808 ==
7568 09:28:46.236957 Write leveling (Byte 0): 35 => 35
7569 09:28:46.240454 Write leveling (Byte 1): 28 => 28
7570 09:28:46.240534 DramcWriteLeveling(PI) end<-----
7571 09:28:46.240593
7572 09:28:46.243460 ==
7573 09:28:46.246567 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 09:28:46.250198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 09:28:46.250283 ==
7576 09:28:46.253585 [Gating] SW mode calibration
7577 09:28:46.259663 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7578 09:28:46.263538 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7579 09:28:46.269729 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 09:28:46.273496 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 09:28:46.276683 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 09:28:46.282807 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 09:28:46.286422 1 4 16 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7584 09:28:46.289436 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7585 09:28:46.296361 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7586 09:28:46.299660 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 09:28:46.303169 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 09:28:46.309588 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 09:28:46.313017 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 09:28:46.315795 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7591 09:28:46.322821 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
7592 09:28:46.325793 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7593 09:28:46.328948 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7594 09:28:46.335837 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 09:28:46.339118 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 09:28:46.342273 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 09:28:46.348944 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 09:28:46.352166 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7599 09:28:46.355865 1 6 16 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7600 09:28:46.362408 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7601 09:28:46.365470 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7602 09:28:46.368641 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 09:28:46.375770 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 09:28:46.379030 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 09:28:46.382122 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 09:28:46.388961 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7607 09:28:46.392267 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7608 09:28:46.395343 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7609 09:28:46.402139 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7610 09:28:46.405135 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 09:28:46.408304 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 09:28:46.415370 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 09:28:46.418542 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 09:28:46.421883 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 09:28:46.428258 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 09:28:46.431672 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 09:28:46.435019 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 09:28:46.441293 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 09:28:46.445069 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 09:28:46.448107 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 09:28:46.454829 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 09:28:46.457994 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7623 09:28:46.461142 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7624 09:28:46.467787 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7625 09:28:46.467874 Total UI for P1: 0, mck2ui 16
7626 09:28:46.474364 best dqsien dly found for B0: ( 1, 9, 14)
7627 09:28:46.477617 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7628 09:28:46.481403 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 09:28:46.484404 Total UI for P1: 0, mck2ui 16
7630 09:28:46.488197 best dqsien dly found for B1: ( 1, 9, 22)
7631 09:28:46.491338 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7632 09:28:46.494460 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7633 09:28:46.494542
7634 09:28:46.501411 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7635 09:28:46.504477 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7636 09:28:46.507439 [Gating] SW calibration Done
7637 09:28:46.507521 ==
7638 09:28:46.511032 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 09:28:46.514268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 09:28:46.514356 ==
7641 09:28:46.514433 RX Vref Scan: 0
7642 09:28:46.517451
7643 09:28:46.517561 RX Vref 0 -> 0, step: 1
7644 09:28:46.517650
7645 09:28:46.520564 RX Delay 0 -> 252, step: 8
7646 09:28:46.524069 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7647 09:28:46.527206 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7648 09:28:46.534034 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7649 09:28:46.537560 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7650 09:28:46.540546 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7651 09:28:46.544051 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7652 09:28:46.547040 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7653 09:28:46.553876 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7654 09:28:46.557437 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7655 09:28:46.560391 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7656 09:28:46.563520 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7657 09:28:46.566653 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7658 09:28:46.573503 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7659 09:28:46.577046 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7660 09:28:46.579987 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7661 09:28:46.583144 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7662 09:28:46.583227 ==
7663 09:28:46.586986 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 09:28:46.593076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 09:28:46.593167 ==
7666 09:28:46.593229 DQS Delay:
7667 09:28:46.596883 DQS0 = 0, DQS1 = 0
7668 09:28:46.596982 DQM Delay:
7669 09:28:46.600075 DQM0 = 127, DQM1 = 124
7670 09:28:46.600155 DQ Delay:
7671 09:28:46.603259 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7672 09:28:46.606332 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7673 09:28:46.610039 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7674 09:28:46.613182 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7675 09:28:46.613264
7676 09:28:46.613324
7677 09:28:46.613379 ==
7678 09:28:46.616287 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 09:28:46.623250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 09:28:46.623343 ==
7681 09:28:46.623404
7682 09:28:46.623460
7683 09:28:46.623513 TX Vref Scan disable
7684 09:28:46.626372 == TX Byte 0 ==
7685 09:28:46.629941 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7686 09:28:46.633162 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7687 09:28:46.636771 == TX Byte 1 ==
7688 09:28:46.639968 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7689 09:28:46.646477 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7690 09:28:46.646577 ==
7691 09:28:46.649920 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 09:28:46.652828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 09:28:46.652926 ==
7694 09:28:46.666435
7695 09:28:46.669792 TX Vref early break, caculate TX vref
7696 09:28:46.672830 TX Vref=16, minBit 8, minWin=20, winSum=358
7697 09:28:46.675943 TX Vref=18, minBit 8, minWin=21, winSum=368
7698 09:28:46.679143 TX Vref=20, minBit 0, minWin=23, winSum=376
7699 09:28:46.683061 TX Vref=22, minBit 8, minWin=23, winSum=391
7700 09:28:46.685970 TX Vref=24, minBit 8, minWin=23, winSum=393
7701 09:28:46.692736 TX Vref=26, minBit 1, minWin=24, winSum=405
7702 09:28:46.696356 TX Vref=28, minBit 4, minWin=24, winSum=403
7703 09:28:46.699466 TX Vref=30, minBit 8, minWin=24, winSum=399
7704 09:28:46.702623 TX Vref=32, minBit 8, minWin=23, winSum=387
7705 09:28:46.706288 TX Vref=34, minBit 8, minWin=21, winSum=377
7706 09:28:46.712370 [TxChooseVref] Worse bit 1, Min win 24, Win sum 405, Final Vref 26
7707 09:28:46.712465
7708 09:28:46.716061 Final TX Range 0 Vref 26
7709 09:28:46.716179
7710 09:28:46.716240 ==
7711 09:28:46.719566 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 09:28:46.722742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 09:28:46.722824 ==
7714 09:28:46.722884
7715 09:28:46.722939
7716 09:28:46.725779 TX Vref Scan disable
7717 09:28:46.732580 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7718 09:28:46.732694 == TX Byte 0 ==
7719 09:28:46.735710 u2DelayCellOfst[0]=15 cells (4 PI)
7720 09:28:46.739385 u2DelayCellOfst[1]=18 cells (5 PI)
7721 09:28:46.742490 u2DelayCellOfst[2]=15 cells (4 PI)
7722 09:28:46.745563 u2DelayCellOfst[3]=15 cells (4 PI)
7723 09:28:46.749210 u2DelayCellOfst[4]=7 cells (2 PI)
7724 09:28:46.752191 u2DelayCellOfst[5]=0 cells (0 PI)
7725 09:28:46.755750 u2DelayCellOfst[6]=18 cells (5 PI)
7726 09:28:46.758701 u2DelayCellOfst[7]=18 cells (5 PI)
7727 09:28:46.762029 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7728 09:28:46.765544 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7729 09:28:46.768568 == TX Byte 1 ==
7730 09:28:46.772209 u2DelayCellOfst[8]=0 cells (0 PI)
7731 09:28:46.772296 u2DelayCellOfst[9]=0 cells (0 PI)
7732 09:28:46.775042 u2DelayCellOfst[10]=7 cells (2 PI)
7733 09:28:46.778348 u2DelayCellOfst[11]=3 cells (1 PI)
7734 09:28:46.782180 u2DelayCellOfst[12]=11 cells (3 PI)
7735 09:28:46.785180 u2DelayCellOfst[13]=11 cells (3 PI)
7736 09:28:46.788376 u2DelayCellOfst[14]=15 cells (4 PI)
7737 09:28:46.792037 u2DelayCellOfst[15]=11 cells (3 PI)
7738 09:28:46.794941 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7739 09:28:46.801635 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7740 09:28:46.801737 DramC Write-DBI on
7741 09:28:46.801799 ==
7742 09:28:46.805389 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 09:28:46.811774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 09:28:46.811867 ==
7745 09:28:46.811929
7746 09:28:46.811985
7747 09:28:46.812037 TX Vref Scan disable
7748 09:28:46.815488 == TX Byte 0 ==
7749 09:28:46.819227 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7750 09:28:46.822248 == TX Byte 1 ==
7751 09:28:46.825304 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7752 09:28:46.828993 DramC Write-DBI off
7753 09:28:46.829075
7754 09:28:46.829135 [DATLAT]
7755 09:28:46.829190 Freq=1600, CH0 RK0
7756 09:28:46.829243
7757 09:28:46.832144 DATLAT Default: 0xf
7758 09:28:46.835364 0, 0xFFFF, sum = 0
7759 09:28:46.835463 1, 0xFFFF, sum = 0
7760 09:28:46.839002 2, 0xFFFF, sum = 0
7761 09:28:46.839084 3, 0xFFFF, sum = 0
7762 09:28:46.842194 4, 0xFFFF, sum = 0
7763 09:28:46.842274 5, 0xFFFF, sum = 0
7764 09:28:46.845136 6, 0xFFFF, sum = 0
7765 09:28:46.845276 7, 0xFFFF, sum = 0
7766 09:28:46.848932 8, 0xFFFF, sum = 0
7767 09:28:46.849035 9, 0xFFFF, sum = 0
7768 09:28:46.852110 10, 0xFFFF, sum = 0
7769 09:28:46.852207 11, 0xFFFF, sum = 0
7770 09:28:46.855151 12, 0xFFFF, sum = 0
7771 09:28:46.855246 13, 0xEFFF, sum = 0
7772 09:28:46.858759 14, 0x0, sum = 1
7773 09:28:46.858856 15, 0x0, sum = 2
7774 09:28:46.861875 16, 0x0, sum = 3
7775 09:28:46.861973 17, 0x0, sum = 4
7776 09:28:46.865521 best_step = 15
7777 09:28:46.865616
7778 09:28:46.865701 ==
7779 09:28:46.868537 Dram Type= 6, Freq= 0, CH_0, rank 0
7780 09:28:46.871667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7781 09:28:46.871762 ==
7782 09:28:46.875221 RX Vref Scan: 1
7783 09:28:46.875317
7784 09:28:46.875402 Set Vref Range= 24 -> 127
7785 09:28:46.875483
7786 09:28:46.878144 RX Vref 24 -> 127, step: 1
7787 09:28:46.878238
7788 09:28:46.881711 RX Delay 11 -> 252, step: 4
7789 09:28:46.881800
7790 09:28:46.885193 Set Vref, RX VrefLevel [Byte0]: 24
7791 09:28:46.888606 [Byte1]: 24
7792 09:28:46.888711
7793 09:28:46.891764 Set Vref, RX VrefLevel [Byte0]: 25
7794 09:28:46.894820 [Byte1]: 25
7795 09:28:46.898479
7796 09:28:46.898582 Set Vref, RX VrefLevel [Byte0]: 26
7797 09:28:46.901518 [Byte1]: 26
7798 09:28:46.905959
7799 09:28:46.906067 Set Vref, RX VrefLevel [Byte0]: 27
7800 09:28:46.909171 [Byte1]: 27
7801 09:28:46.913637
7802 09:28:46.913739 Set Vref, RX VrefLevel [Byte0]: 28
7803 09:28:46.916793 [Byte1]: 28
7804 09:28:46.921076
7805 09:28:46.921175 Set Vref, RX VrefLevel [Byte0]: 29
7806 09:28:46.924245 [Byte1]: 29
7807 09:28:46.929154
7808 09:28:46.929228 Set Vref, RX VrefLevel [Byte0]: 30
7809 09:28:46.932246 [Byte1]: 30
7810 09:28:46.936729
7811 09:28:46.936801 Set Vref, RX VrefLevel [Byte0]: 31
7812 09:28:46.939933 [Byte1]: 31
7813 09:28:46.944367
7814 09:28:46.944473 Set Vref, RX VrefLevel [Byte0]: 32
7815 09:28:46.947343 [Byte1]: 32
7816 09:28:46.951762
7817 09:28:46.951861 Set Vref, RX VrefLevel [Byte0]: 33
7818 09:28:46.954891 [Byte1]: 33
7819 09:28:46.959223
7820 09:28:46.959327 Set Vref, RX VrefLevel [Byte0]: 34
7821 09:28:46.962817 [Byte1]: 34
7822 09:28:46.966862
7823 09:28:46.966941 Set Vref, RX VrefLevel [Byte0]: 35
7824 09:28:46.970362 [Byte1]: 35
7825 09:28:46.974677
7826 09:28:46.974789 Set Vref, RX VrefLevel [Byte0]: 36
7827 09:28:46.977775 [Byte1]: 36
7828 09:28:46.981941
7829 09:28:46.982042 Set Vref, RX VrefLevel [Byte0]: 37
7830 09:28:46.985442 [Byte1]: 37
7831 09:28:46.990089
7832 09:28:46.990175 Set Vref, RX VrefLevel [Byte0]: 38
7833 09:28:46.992896 [Byte1]: 38
7834 09:28:46.997608
7835 09:28:46.997715 Set Vref, RX VrefLevel [Byte0]: 39
7836 09:28:47.000864 [Byte1]: 39
7837 09:28:47.005160
7838 09:28:47.005246 Set Vref, RX VrefLevel [Byte0]: 40
7839 09:28:47.008196 [Byte1]: 40
7840 09:28:47.012794
7841 09:28:47.012899 Set Vref, RX VrefLevel [Byte0]: 41
7842 09:28:47.015999 [Byte1]: 41
7843 09:28:47.020251
7844 09:28:47.020355 Set Vref, RX VrefLevel [Byte0]: 42
7845 09:28:47.023677 [Byte1]: 42
7846 09:28:47.028042
7847 09:28:47.028143 Set Vref, RX VrefLevel [Byte0]: 43
7848 09:28:47.031146 [Byte1]: 43
7849 09:28:47.035644
7850 09:28:47.035748 Set Vref, RX VrefLevel [Byte0]: 44
7851 09:28:47.038745 [Byte1]: 44
7852 09:28:47.043175
7853 09:28:47.043287 Set Vref, RX VrefLevel [Byte0]: 45
7854 09:28:47.046141 [Byte1]: 45
7855 09:28:47.050396
7856 09:28:47.050499 Set Vref, RX VrefLevel [Byte0]: 46
7857 09:28:47.054194 [Byte1]: 46
7858 09:28:47.058504
7859 09:28:47.058608 Set Vref, RX VrefLevel [Byte0]: 47
7860 09:28:47.061620 [Byte1]: 47
7861 09:28:47.065826
7862 09:28:47.065925 Set Vref, RX VrefLevel [Byte0]: 48
7863 09:28:47.069479 [Byte1]: 48
7864 09:28:47.073558
7865 09:28:47.073657 Set Vref, RX VrefLevel [Byte0]: 49
7866 09:28:47.076483 [Byte1]: 49
7867 09:28:47.081463
7868 09:28:47.081571 Set Vref, RX VrefLevel [Byte0]: 50
7869 09:28:47.084488 [Byte1]: 50
7870 09:28:47.088866
7871 09:28:47.088965 Set Vref, RX VrefLevel [Byte0]: 51
7872 09:28:47.091825 [Byte1]: 51
7873 09:28:47.096096
7874 09:28:47.096189 Set Vref, RX VrefLevel [Byte0]: 52
7875 09:28:47.099663 [Byte1]: 52
7876 09:28:47.103658
7877 09:28:47.103755 Set Vref, RX VrefLevel [Byte0]: 53
7878 09:28:47.107262 [Byte1]: 53
7879 09:28:47.111696
7880 09:28:47.111767 Set Vref, RX VrefLevel [Byte0]: 54
7881 09:28:47.114798 [Byte1]: 54
7882 09:28:47.119249
7883 09:28:47.119349 Set Vref, RX VrefLevel [Byte0]: 55
7884 09:28:47.122308 [Byte1]: 55
7885 09:28:47.126858
7886 09:28:47.126958 Set Vref, RX VrefLevel [Byte0]: 56
7887 09:28:47.129974 [Byte1]: 56
7888 09:28:47.134457
7889 09:28:47.134604 Set Vref, RX VrefLevel [Byte0]: 57
7890 09:28:47.137934 [Byte1]: 57
7891 09:28:47.142278
7892 09:28:47.142376 Set Vref, RX VrefLevel [Byte0]: 58
7893 09:28:47.145510 [Byte1]: 58
7894 09:28:47.149775
7895 09:28:47.149887 Set Vref, RX VrefLevel [Byte0]: 59
7896 09:28:47.152912 [Byte1]: 59
7897 09:28:47.157218
7898 09:28:47.157378 Set Vref, RX VrefLevel [Byte0]: 60
7899 09:28:47.160824 [Byte1]: 60
7900 09:28:47.164620
7901 09:28:47.164726 Set Vref, RX VrefLevel [Byte0]: 61
7902 09:28:47.168562 [Byte1]: 61
7903 09:28:47.172201
7904 09:28:47.172307 Set Vref, RX VrefLevel [Byte0]: 62
7905 09:28:47.175981 [Byte1]: 62
7906 09:28:47.180164
7907 09:28:47.180272 Set Vref, RX VrefLevel [Byte0]: 63
7908 09:28:47.183581 [Byte1]: 63
7909 09:28:47.187942
7910 09:28:47.188056 Set Vref, RX VrefLevel [Byte0]: 64
7911 09:28:47.191036 [Byte1]: 64
7912 09:28:47.195390
7913 09:28:47.195528 Set Vref, RX VrefLevel [Byte0]: 65
7914 09:28:47.198543 [Byte1]: 65
7915 09:28:47.202747
7916 09:28:47.202858 Set Vref, RX VrefLevel [Byte0]: 66
7917 09:28:47.206321 [Byte1]: 66
7918 09:28:47.210417
7919 09:28:47.210531 Set Vref, RX VrefLevel [Byte0]: 67
7920 09:28:47.213641 [Byte1]: 67
7921 09:28:47.217958
7922 09:28:47.218065 Set Vref, RX VrefLevel [Byte0]: 68
7923 09:28:47.221168 [Byte1]: 68
7924 09:28:47.225645
7925 09:28:47.225754 Set Vref, RX VrefLevel [Byte0]: 69
7926 09:28:47.228781 [Byte1]: 69
7927 09:28:47.233339
7928 09:28:47.233451 Set Vref, RX VrefLevel [Byte0]: 70
7929 09:28:47.236960 [Byte1]: 70
7930 09:28:47.240920
7931 09:28:47.241006 Set Vref, RX VrefLevel [Byte0]: 71
7932 09:28:47.244224 [Byte1]: 71
7933 09:28:47.248523
7934 09:28:47.248637 Set Vref, RX VrefLevel [Byte0]: 72
7935 09:28:47.252172 [Byte1]: 72
7936 09:28:47.256348
7937 09:28:47.256460 Set Vref, RX VrefLevel [Byte0]: 73
7938 09:28:47.259551 [Byte1]: 73
7939 09:28:47.263754
7940 09:28:47.263874 Set Vref, RX VrefLevel [Byte0]: 74
7941 09:28:47.266789 [Byte1]: 74
7942 09:28:47.271202
7943 09:28:47.271308 Set Vref, RX VrefLevel [Byte0]: 75
7944 09:28:47.274937 [Byte1]: 75
7945 09:28:47.279325
7946 09:28:47.279442 Set Vref, RX VrefLevel [Byte0]: 76
7947 09:28:47.282409 [Byte1]: 76
7948 09:28:47.286683
7949 09:28:47.286784 Set Vref, RX VrefLevel [Byte0]: 77
7950 09:28:47.289725 [Byte1]: 77
7951 09:28:47.294143
7952 09:28:47.294248 Set Vref, RX VrefLevel [Byte0]: 78
7953 09:28:47.297822 [Byte1]: 78
7954 09:28:47.302088
7955 09:28:47.302165 Final RX Vref Byte 0 = 63 to rank0
7956 09:28:47.305157 Final RX Vref Byte 1 = 61 to rank0
7957 09:28:47.308221 Final RX Vref Byte 0 = 63 to rank1
7958 09:28:47.311976 Final RX Vref Byte 1 = 61 to rank1==
7959 09:28:47.314957 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 09:28:47.321714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 09:28:47.321815 ==
7962 09:28:47.321884 DQS Delay:
7963 09:28:47.321942 DQS0 = 0, DQS1 = 0
7964 09:28:47.324789 DQM Delay:
7965 09:28:47.324862 DQM0 = 126, DQM1 = 119
7966 09:28:47.328563 DQ Delay:
7967 09:28:47.331666 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7968 09:28:47.335323 DQ4 =126, DQ5 =112, DQ6 =132, DQ7 =138
7969 09:28:47.338459 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7970 09:28:47.341466 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7971 09:28:47.341558
7972 09:28:47.341621
7973 09:28:47.341674
7974 09:28:47.345209 [DramC_TX_OE_Calibration] TA2
7975 09:28:47.348304 Original DQ_B0 (3 6) =30, OEN = 27
7976 09:28:47.351893 Original DQ_B1 (3 6) =30, OEN = 27
7977 09:28:47.354830 24, 0x0, End_B0=24 End_B1=24
7978 09:28:47.354937 25, 0x0, End_B0=25 End_B1=25
7979 09:28:47.358183 26, 0x0, End_B0=26 End_B1=26
7980 09:28:47.361732 27, 0x0, End_B0=27 End_B1=27
7981 09:28:47.364971 28, 0x0, End_B0=28 End_B1=28
7982 09:28:47.368344 29, 0x0, End_B0=29 End_B1=29
7983 09:28:47.368497 30, 0x0, End_B0=30 End_B1=30
7984 09:28:47.371320 31, 0x4141, End_B0=30 End_B1=30
7985 09:28:47.375051 Byte0 end_step=30 best_step=27
7986 09:28:47.378309 Byte1 end_step=30 best_step=27
7987 09:28:47.381511 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 09:28:47.384605 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 09:28:47.384743
7990 09:28:47.384827
7991 09:28:47.391369 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7992 09:28:47.394523 CH0 RK0: MR19=303, MR18=1414
7993 09:28:47.401126 CH0_RK0: MR19=0x303, MR18=0x1414, DQSOSC=399, MR23=63, INC=23, DEC=15
7994 09:28:47.401239
7995 09:28:47.404511 ----->DramcWriteLeveling(PI) begin...
7996 09:28:47.404606 ==
7997 09:28:47.407929 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 09:28:47.411392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 09:28:47.411495 ==
8000 09:28:47.414461 Write leveling (Byte 0): 34 => 34
8001 09:28:47.418167 Write leveling (Byte 1): 27 => 27
8002 09:28:47.421193 DramcWriteLeveling(PI) end<-----
8003 09:28:47.421265
8004 09:28:47.421342 ==
8005 09:28:47.424799 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 09:28:47.427955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 09:28:47.428047 ==
8008 09:28:47.431115 [Gating] SW mode calibration
8009 09:28:47.438008 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 09:28:47.444807 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 09:28:47.447999 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 09:28:47.451084 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 09:28:47.457574 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 09:28:47.461269 1 4 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8015 09:28:47.464324 1 4 16 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
8016 09:28:47.471011 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 09:28:47.474430 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 09:28:47.477549 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 09:28:47.484121 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 09:28:47.487750 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 09:28:47.490840 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8022 09:28:47.497668 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
8023 09:28:47.500845 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8024 09:28:47.503897 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8025 09:28:47.510697 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 09:28:47.514404 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 09:28:47.517225 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 09:28:47.524133 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 09:28:47.527496 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 09:28:47.530289 1 6 12 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (1 1)
8031 09:28:47.537402 1 6 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8032 09:28:47.540698 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 09:28:47.543791 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 09:28:47.550647 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 09:28:47.553800 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 09:28:47.556841 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 09:28:47.563800 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 09:28:47.566934 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8039 09:28:47.570053 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8040 09:28:47.576904 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 09:28:47.580070 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 09:28:47.583175 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 09:28:47.589805 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 09:28:47.593211 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 09:28:47.596529 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 09:28:47.603103 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 09:28:47.606237 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 09:28:47.609815 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 09:28:47.616608 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 09:28:47.619863 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 09:28:47.622958 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 09:28:47.629920 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 09:28:47.632951 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8054 09:28:47.636015 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8055 09:28:47.639406 Total UI for P1: 0, mck2ui 16
8056 09:28:47.643006 best dqsien dly found for B0: ( 1, 9, 8)
8057 09:28:47.649118 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8058 09:28:47.652489 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 09:28:47.655830 Total UI for P1: 0, mck2ui 16
8060 09:28:47.659512 best dqsien dly found for B1: ( 1, 9, 14)
8061 09:28:47.662698 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8062 09:28:47.665781 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8063 09:28:47.665883
8064 09:28:47.669026 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8065 09:28:47.672752 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8066 09:28:47.675950 [Gating] SW calibration Done
8067 09:28:47.676041 ==
8068 09:28:47.679131 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 09:28:47.685762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 09:28:47.685885 ==
8071 09:28:47.685975 RX Vref Scan: 0
8072 09:28:47.686057
8073 09:28:47.688852 RX Vref 0 -> 0, step: 1
8074 09:28:47.688944
8075 09:28:47.692637 RX Delay 0 -> 252, step: 8
8076 09:28:47.695806 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8077 09:28:47.698977 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8078 09:28:47.702528 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8079 09:28:47.705467 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8080 09:28:47.712332 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8081 09:28:47.715594 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8082 09:28:47.718847 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8083 09:28:47.722568 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8084 09:28:47.725712 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8085 09:28:47.728885 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8086 09:28:47.735687 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8087 09:28:47.738834 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8088 09:28:47.742583 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8089 09:28:47.745753 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8090 09:28:47.752377 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8091 09:28:47.755209 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8092 09:28:47.755315 ==
8093 09:28:47.758616 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 09:28:47.761910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 09:28:47.762010 ==
8096 09:28:47.765496 DQS Delay:
8097 09:28:47.765592 DQS0 = 0, DQS1 = 0
8098 09:28:47.765677 DQM Delay:
8099 09:28:47.768426 DQM0 = 127, DQM1 = 121
8100 09:28:47.768521 DQ Delay:
8101 09:28:47.772114 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8102 09:28:47.775234 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8103 09:28:47.778913 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8104 09:28:47.785586 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8105 09:28:47.785700
8106 09:28:47.785784
8107 09:28:47.785864 ==
8108 09:28:47.788571 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 09:28:47.792132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 09:28:47.792208 ==
8111 09:28:47.792265
8112 09:28:47.792317
8113 09:28:47.795237 TX Vref Scan disable
8114 09:28:47.795349 == TX Byte 0 ==
8115 09:28:47.802009 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8116 09:28:47.805021 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8117 09:28:47.805120 == TX Byte 1 ==
8118 09:28:47.811837 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8119 09:28:47.814957 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8120 09:28:47.815060 ==
8121 09:28:47.818674 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 09:28:47.821671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 09:28:47.821746 ==
8124 09:28:47.837557
8125 09:28:47.840656 TX Vref early break, caculate TX vref
8126 09:28:47.843890 TX Vref=16, minBit 0, minWin=22, winSum=364
8127 09:28:47.847654 TX Vref=18, minBit 7, minWin=22, winSum=371
8128 09:28:47.850811 TX Vref=20, minBit 8, minWin=22, winSum=380
8129 09:28:47.853965 TX Vref=22, minBit 8, minWin=23, winSum=388
8130 09:28:47.857744 TX Vref=24, minBit 0, minWin=24, winSum=398
8131 09:28:47.863914 TX Vref=26, minBit 8, minWin=24, winSum=403
8132 09:28:47.867472 TX Vref=28, minBit 8, minWin=24, winSum=406
8133 09:28:47.871041 TX Vref=30, minBit 8, minWin=24, winSum=406
8134 09:28:47.873921 TX Vref=32, minBit 8, minWin=22, winSum=393
8135 09:28:47.877312 TX Vref=34, minBit 8, minWin=22, winSum=389
8136 09:28:47.880810 TX Vref=36, minBit 0, minWin=23, winSum=380
8137 09:28:47.887529 [TxChooseVref] Worse bit 8, Min win 24, Win sum 406, Final Vref 28
8138 09:28:47.887618
8139 09:28:47.890875 Final TX Range 0 Vref 28
8140 09:28:47.890956
8141 09:28:47.891013 ==
8142 09:28:47.893657 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 09:28:47.897248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 09:28:47.897324 ==
8145 09:28:47.897380
8146 09:28:47.897445
8147 09:28:47.900312 TX Vref Scan disable
8148 09:28:47.907108 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8149 09:28:47.907221 == TX Byte 0 ==
8150 09:28:47.910791 u2DelayCellOfst[0]=11 cells (3 PI)
8151 09:28:47.914070 u2DelayCellOfst[1]=18 cells (5 PI)
8152 09:28:47.916963 u2DelayCellOfst[2]=11 cells (3 PI)
8153 09:28:47.920745 u2DelayCellOfst[3]=11 cells (3 PI)
8154 09:28:47.923928 u2DelayCellOfst[4]=7 cells (2 PI)
8155 09:28:47.927073 u2DelayCellOfst[5]=0 cells (0 PI)
8156 09:28:47.930247 u2DelayCellOfst[6]=18 cells (5 PI)
8157 09:28:47.933842 u2DelayCellOfst[7]=18 cells (5 PI)
8158 09:28:47.936816 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8159 09:28:47.940350 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8160 09:28:47.943575 == TX Byte 1 ==
8161 09:28:47.946760 u2DelayCellOfst[8]=0 cells (0 PI)
8162 09:28:47.950075 u2DelayCellOfst[9]=3 cells (1 PI)
8163 09:28:47.953670 u2DelayCellOfst[10]=11 cells (3 PI)
8164 09:28:47.953757 u2DelayCellOfst[11]=7 cells (2 PI)
8165 09:28:47.956690 u2DelayCellOfst[12]=15 cells (4 PI)
8166 09:28:47.959868 u2DelayCellOfst[13]=15 cells (4 PI)
8167 09:28:47.963677 u2DelayCellOfst[14]=15 cells (4 PI)
8168 09:28:47.966854 u2DelayCellOfst[15]=15 cells (4 PI)
8169 09:28:47.973507 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8170 09:28:47.976623 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8171 09:28:47.976729 DramC Write-DBI on
8172 09:28:47.979766 ==
8173 09:28:47.983368 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 09:28:47.986456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 09:28:47.986525 ==
8176 09:28:47.986580
8177 09:28:47.986632
8178 09:28:47.989704 TX Vref Scan disable
8179 09:28:47.989771 == TX Byte 0 ==
8180 09:28:47.996182 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8181 09:28:47.996282 == TX Byte 1 ==
8182 09:28:47.999555 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8183 09:28:48.002881 DramC Write-DBI off
8184 09:28:48.002952
8185 09:28:48.003006 [DATLAT]
8186 09:28:48.006242 Freq=1600, CH0 RK1
8187 09:28:48.006314
8188 09:28:48.006368 DATLAT Default: 0xf
8189 09:28:48.009600 0, 0xFFFF, sum = 0
8190 09:28:48.009667 1, 0xFFFF, sum = 0
8191 09:28:48.012828 2, 0xFFFF, sum = 0
8192 09:28:48.012909 3, 0xFFFF, sum = 0
8193 09:28:48.016143 4, 0xFFFF, sum = 0
8194 09:28:48.016244 5, 0xFFFF, sum = 0
8195 09:28:48.019779 6, 0xFFFF, sum = 0
8196 09:28:48.022745 7, 0xFFFF, sum = 0
8197 09:28:48.022852 8, 0xFFFF, sum = 0
8198 09:28:48.026502 9, 0xFFFF, sum = 0
8199 09:28:48.026598 10, 0xFFFF, sum = 0
8200 09:28:48.029548 11, 0xFFFF, sum = 0
8201 09:28:48.029644 12, 0xFFFF, sum = 0
8202 09:28:48.032738 13, 0xCFFF, sum = 0
8203 09:28:48.032842 14, 0x0, sum = 1
8204 09:28:48.036450 15, 0x0, sum = 2
8205 09:28:48.036543 16, 0x0, sum = 3
8206 09:28:48.039749 17, 0x0, sum = 4
8207 09:28:48.039848 best_step = 15
8208 09:28:48.039931
8209 09:28:48.040012 ==
8210 09:28:48.042906 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 09:28:48.045985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 09:28:48.046095 ==
8213 09:28:48.049624 RX Vref Scan: 0
8214 09:28:48.049703
8215 09:28:48.052499 RX Vref 0 -> 0, step: 1
8216 09:28:48.052592
8217 09:28:48.052706 RX Delay 3 -> 252, step: 4
8218 09:28:48.059881 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8219 09:28:48.063159 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8220 09:28:48.066272 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8221 09:28:48.069931 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8222 09:28:48.073183 iDelay=191, Bit 4, Center 122 (67 ~ 178) 112
8223 09:28:48.079634 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8224 09:28:48.082800 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8225 09:28:48.086570 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8226 09:28:48.089700 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8227 09:28:48.092792 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8228 09:28:48.099537 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8229 09:28:48.102673 iDelay=191, Bit 11, Center 110 (51 ~ 170) 120
8230 09:28:48.106470 iDelay=191, Bit 12, Center 122 (67 ~ 178) 112
8231 09:28:48.109625 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8232 09:28:48.116085 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8233 09:28:48.119269 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8234 09:28:48.119366 ==
8235 09:28:48.122517 Dram Type= 6, Freq= 0, CH_0, rank 1
8236 09:28:48.126303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8237 09:28:48.126404 ==
8238 09:28:48.129556 DQS Delay:
8239 09:28:48.129647 DQS0 = 0, DQS1 = 0
8240 09:28:48.129729 DQM Delay:
8241 09:28:48.132641 DQM0 = 124, DQM1 = 117
8242 09:28:48.132736 DQ Delay:
8243 09:28:48.135906 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8244 09:28:48.139133 DQ4 =122, DQ5 =112, DQ6 =134, DQ7 =134
8245 09:28:48.142924 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =110
8246 09:28:48.149170 DQ12 =122, DQ13 =122, DQ14 =128, DQ15 =124
8247 09:28:48.149266
8248 09:28:48.149326
8249 09:28:48.149385
8250 09:28:48.152911 [DramC_TX_OE_Calibration] TA2
8251 09:28:48.152979 Original DQ_B0 (3 6) =30, OEN = 27
8252 09:28:48.155989 Original DQ_B1 (3 6) =30, OEN = 27
8253 09:28:48.159617 24, 0x0, End_B0=24 End_B1=24
8254 09:28:48.162652 25, 0x0, End_B0=25 End_B1=25
8255 09:28:48.165820 26, 0x0, End_B0=26 End_B1=26
8256 09:28:48.168887 27, 0x0, End_B0=27 End_B1=27
8257 09:28:48.168983 28, 0x0, End_B0=28 End_B1=28
8258 09:28:48.172534 29, 0x0, End_B0=29 End_B1=29
8259 09:28:48.175930 30, 0x0, End_B0=30 End_B1=30
8260 09:28:48.179192 31, 0x4141, End_B0=30 End_B1=30
8261 09:28:48.182155 Byte0 end_step=30 best_step=27
8262 09:28:48.182254 Byte1 end_step=30 best_step=27
8263 09:28:48.185540 Byte0 TX OE(2T, 0.5T) = (3, 3)
8264 09:28:48.188861 Byte1 TX OE(2T, 0.5T) = (3, 3)
8265 09:28:48.188961
8266 09:28:48.189058
8267 09:28:48.198741 [DQSOSCAuto] RK1, (LSB)MR18= 0x2513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8268 09:28:48.198851 CH0 RK1: MR19=303, MR18=2513
8269 09:28:48.205749 CH0_RK1: MR19=0x303, MR18=0x2513, DQSOSC=391, MR23=63, INC=24, DEC=16
8270 09:28:48.208918 [RxdqsGatingPostProcess] freq 1600
8271 09:28:48.215896 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8272 09:28:48.219026 best DQS0 dly(2T, 0.5T) = (1, 1)
8273 09:28:48.222075 best DQS1 dly(2T, 0.5T) = (1, 1)
8274 09:28:48.225242 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8275 09:28:48.228861 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8276 09:28:48.232414 best DQS0 dly(2T, 0.5T) = (1, 1)
8277 09:28:48.232524 best DQS1 dly(2T, 0.5T) = (1, 1)
8278 09:28:48.235448 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8279 09:28:48.238865 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8280 09:28:48.242157 Pre-setting of DQS Precalculation
8281 09:28:48.248653 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8282 09:28:48.248793 ==
8283 09:28:48.252187 Dram Type= 6, Freq= 0, CH_1, rank 0
8284 09:28:48.255297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 09:28:48.255376 ==
8286 09:28:48.261905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8287 09:28:48.265551 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8288 09:28:48.268605 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8289 09:28:48.274915 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8290 09:28:48.284161 [CA 0] Center 42 (13~71) winsize 59
8291 09:28:48.287127 [CA 1] Center 42 (13~72) winsize 60
8292 09:28:48.290534 [CA 2] Center 38 (9~67) winsize 59
8293 09:28:48.294023 [CA 3] Center 37 (8~66) winsize 59
8294 09:28:48.297438 [CA 4] Center 37 (8~67) winsize 60
8295 09:28:48.300569 [CA 5] Center 36 (7~66) winsize 60
8296 09:28:48.300725
8297 09:28:48.304156 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8298 09:28:48.304239
8299 09:28:48.307614 [CATrainingPosCal] consider 1 rank data
8300 09:28:48.310915 u2DelayCellTimex100 = 258/100 ps
8301 09:28:48.313886 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8302 09:28:48.320705 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8303 09:28:48.323776 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8304 09:28:48.327409 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8305 09:28:48.330576 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8306 09:28:48.333671 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8307 09:28:48.333754
8308 09:28:48.337298 CA PerBit enable=1, Macro0, CA PI delay=36
8309 09:28:48.337381
8310 09:28:48.340415 [CBTSetCACLKResult] CA Dly = 36
8311 09:28:48.343502 CS Dly: 10 (0~41)
8312 09:28:48.347240 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8313 09:28:48.350108 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8314 09:28:48.350197 ==
8315 09:28:48.353894 Dram Type= 6, Freq= 0, CH_1, rank 1
8316 09:28:48.356795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 09:28:48.360235 ==
8318 09:28:48.363543 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8319 09:28:48.366931 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8320 09:28:48.373786 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8321 09:28:48.380177 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8322 09:28:48.387683 [CA 0] Center 41 (12~71) winsize 60
8323 09:28:48.390803 [CA 1] Center 42 (12~72) winsize 61
8324 09:28:48.393960 [CA 2] Center 37 (8~66) winsize 59
8325 09:28:48.397609 [CA 3] Center 36 (7~66) winsize 60
8326 09:28:48.400757 [CA 4] Center 37 (7~67) winsize 61
8327 09:28:48.403843 [CA 5] Center 36 (6~66) winsize 61
8328 09:28:48.403922
8329 09:28:48.407300 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8330 09:28:48.407386
8331 09:28:48.410834 [CATrainingPosCal] consider 2 rank data
8332 09:28:48.413672 u2DelayCellTimex100 = 258/100 ps
8333 09:28:48.416970 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8334 09:28:48.423735 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8335 09:28:48.427281 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8336 09:28:48.430294 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8337 09:28:48.434022 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8338 09:28:48.437135 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8339 09:28:48.437219
8340 09:28:48.440113 CA PerBit enable=1, Macro0, CA PI delay=36
8341 09:28:48.440189
8342 09:28:48.443716 [CBTSetCACLKResult] CA Dly = 36
8343 09:28:48.446824 CS Dly: 11 (0~44)
8344 09:28:48.450605 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8345 09:28:48.453689 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8346 09:28:48.453775
8347 09:28:48.457398 ----->DramcWriteLeveling(PI) begin...
8348 09:28:48.457483 ==
8349 09:28:48.460257 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 09:28:48.463559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 09:28:48.467106 ==
8352 09:28:48.467230 Write leveling (Byte 0): 25 => 25
8353 09:28:48.470145 Write leveling (Byte 1): 27 => 27
8354 09:28:48.473386 DramcWriteLeveling(PI) end<-----
8355 09:28:48.473521
8356 09:28:48.473612 ==
8357 09:28:48.476817 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 09:28:48.483545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 09:28:48.483645 ==
8360 09:28:48.486741 [Gating] SW mode calibration
8361 09:28:48.493695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8362 09:28:48.496802 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8363 09:28:48.503583 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 09:28:48.506713 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 09:28:48.510300 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 09:28:48.517181 1 4 12 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
8367 09:28:48.520163 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 09:28:48.523249 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 09:28:48.530181 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 09:28:48.533493 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 09:28:48.536673 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 09:28:48.539873 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 09:28:48.546804 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 09:28:48.550198 1 5 12 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
8375 09:28:48.553215 1 5 16 | B1->B0 | 2424 2525 | 0 0 | (1 0) (1 0)
8376 09:28:48.560134 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 09:28:48.563131 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 09:28:48.566714 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 09:28:48.573512 1 6 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8380 09:28:48.576588 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 09:28:48.579639 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 09:28:48.586516 1 6 12 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
8383 09:28:48.590134 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8384 09:28:48.593335 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 09:28:48.599513 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 09:28:48.603184 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 09:28:48.606272 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 09:28:48.613224 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 09:28:48.616340 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 09:28:48.619408 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 09:28:48.626335 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8392 09:28:48.629441 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 09:28:48.632712 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 09:28:48.639410 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 09:28:48.642415 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 09:28:48.645947 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 09:28:48.652381 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 09:28:48.655911 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 09:28:48.659273 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 09:28:48.666144 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 09:28:48.668970 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 09:28:48.672425 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 09:28:48.679083 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 09:28:48.682100 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 09:28:48.685402 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 09:28:48.692075 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8407 09:28:48.695567 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8408 09:28:48.698762 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 09:28:48.702463 Total UI for P1: 0, mck2ui 16
8410 09:28:48.705644 best dqsien dly found for B0: ( 1, 9, 14)
8411 09:28:48.708568 Total UI for P1: 0, mck2ui 16
8412 09:28:48.712333 best dqsien dly found for B1: ( 1, 9, 14)
8413 09:28:48.715475 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8414 09:28:48.718497 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8415 09:28:48.718583
8416 09:28:48.725367 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8417 09:28:48.728361 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8418 09:28:48.731464 [Gating] SW calibration Done
8419 09:28:48.731544 ==
8420 09:28:48.735239 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 09:28:48.738425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 09:28:48.738506 ==
8423 09:28:48.738566 RX Vref Scan: 0
8424 09:28:48.741462
8425 09:28:48.741539 RX Vref 0 -> 0, step: 1
8426 09:28:48.741600
8427 09:28:48.744984 RX Delay 0 -> 252, step: 8
8428 09:28:48.748140 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8429 09:28:48.751668 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8430 09:28:48.758044 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8431 09:28:48.761221 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8432 09:28:48.764897 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8433 09:28:48.768313 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8434 09:28:48.771199 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8435 09:28:48.777783 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8436 09:28:48.781175 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8437 09:28:48.784531 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8438 09:28:48.787693 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8439 09:28:48.791345 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8440 09:28:48.797530 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8441 09:28:48.800981 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8442 09:28:48.804545 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8443 09:28:48.807793 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8444 09:28:48.807880 ==
8445 09:28:48.810849 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 09:28:48.817716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 09:28:48.817813 ==
8448 09:28:48.817874 DQS Delay:
8449 09:28:48.820809 DQS0 = 0, DQS1 = 0
8450 09:28:48.820913 DQM Delay:
8451 09:28:48.823848 DQM0 = 132, DQM1 = 125
8452 09:28:48.823926 DQ Delay:
8453 09:28:48.827669 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8454 09:28:48.830791 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8455 09:28:48.833960 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8456 09:28:48.837722 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8457 09:28:48.837804
8458 09:28:48.837864
8459 09:28:48.837919 ==
8460 09:28:48.840796 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 09:28:48.847499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 09:28:48.847593 ==
8463 09:28:48.847653
8464 09:28:48.847708
8465 09:28:48.847760 TX Vref Scan disable
8466 09:28:48.850573 == TX Byte 0 ==
8467 09:28:48.854229 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8468 09:28:48.860485 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8469 09:28:48.860582 == TX Byte 1 ==
8470 09:28:48.863707 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8471 09:28:48.870620 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8472 09:28:48.870714 ==
8473 09:28:48.873628 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 09:28:48.877387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 09:28:48.877470 ==
8476 09:28:48.890627
8477 09:28:48.894101 TX Vref early break, caculate TX vref
8478 09:28:48.897320 TX Vref=16, minBit 11, minWin=21, winSum=364
8479 09:28:48.900228 TX Vref=18, minBit 10, minWin=22, winSum=374
8480 09:28:48.903515 TX Vref=20, minBit 11, minWin=22, winSum=387
8481 09:28:48.907198 TX Vref=22, minBit 9, minWin=23, winSum=396
8482 09:28:48.913688 TX Vref=24, minBit 1, minWin=24, winSum=408
8483 09:28:48.916864 TX Vref=26, minBit 1, minWin=25, winSum=414
8484 09:28:48.920227 TX Vref=28, minBit 0, minWin=25, winSum=420
8485 09:28:48.923792 TX Vref=30, minBit 0, minWin=25, winSum=416
8486 09:28:48.926793 TX Vref=32, minBit 1, minWin=23, winSum=407
8487 09:28:48.930480 TX Vref=34, minBit 0, minWin=24, winSum=400
8488 09:28:48.936835 TX Vref=36, minBit 0, minWin=23, winSum=384
8489 09:28:48.939964 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8490 09:28:48.940048
8491 09:28:48.943695 Final TX Range 0 Vref 28
8492 09:28:48.943775
8493 09:28:48.943835 ==
8494 09:28:48.946863 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 09:28:48.949940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 09:28:48.950026 ==
8497 09:28:48.953570
8498 09:28:48.953650
8499 09:28:48.953710 TX Vref Scan disable
8500 09:28:48.960270 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8501 09:28:48.960363 == TX Byte 0 ==
8502 09:28:48.963353 u2DelayCellOfst[0]=18 cells (5 PI)
8503 09:28:48.966499 u2DelayCellOfst[1]=11 cells (3 PI)
8504 09:28:48.970220 u2DelayCellOfst[2]=0 cells (0 PI)
8505 09:28:48.973312 u2DelayCellOfst[3]=3 cells (1 PI)
8506 09:28:48.976913 u2DelayCellOfst[4]=7 cells (2 PI)
8507 09:28:48.980032 u2DelayCellOfst[5]=18 cells (5 PI)
8508 09:28:48.983030 u2DelayCellOfst[6]=18 cells (5 PI)
8509 09:28:48.986708 u2DelayCellOfst[7]=3 cells (1 PI)
8510 09:28:48.989929 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8511 09:28:48.992968 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8512 09:28:48.996454 == TX Byte 1 ==
8513 09:28:48.999522 u2DelayCellOfst[8]=0 cells (0 PI)
8514 09:28:49.003106 u2DelayCellOfst[9]=11 cells (3 PI)
8515 09:28:49.006285 u2DelayCellOfst[10]=15 cells (4 PI)
8516 09:28:49.009878 u2DelayCellOfst[11]=11 cells (3 PI)
8517 09:28:49.012831 u2DelayCellOfst[12]=18 cells (5 PI)
8518 09:28:49.012912 u2DelayCellOfst[13]=22 cells (6 PI)
8519 09:28:49.016370 u2DelayCellOfst[14]=22 cells (6 PI)
8520 09:28:49.019646 u2DelayCellOfst[15]=22 cells (6 PI)
8521 09:28:49.026318 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8522 09:28:49.029636 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8523 09:28:49.029724 DramC Write-DBI on
8524 09:28:49.032834 ==
8525 09:28:49.036479 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 09:28:49.039598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 09:28:49.039683 ==
8528 09:28:49.039743
8529 09:28:49.039797
8530 09:28:49.042696 TX Vref Scan disable
8531 09:28:49.042774 == TX Byte 0 ==
8532 09:28:49.049704 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8533 09:28:49.049813 == TX Byte 1 ==
8534 09:28:49.052861 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8535 09:28:49.055829 DramC Write-DBI off
8536 09:28:49.055907
8537 09:28:49.055967 [DATLAT]
8538 09:28:49.059487 Freq=1600, CH1 RK0
8539 09:28:49.059589
8540 09:28:49.059675 DATLAT Default: 0xf
8541 09:28:49.062561 0, 0xFFFF, sum = 0
8542 09:28:49.062640 1, 0xFFFF, sum = 0
8543 09:28:49.066452 2, 0xFFFF, sum = 0
8544 09:28:49.066536 3, 0xFFFF, sum = 0
8545 09:28:49.069135 4, 0xFFFF, sum = 0
8546 09:28:49.069215 5, 0xFFFF, sum = 0
8547 09:28:49.072942 6, 0xFFFF, sum = 0
8548 09:28:49.073023 7, 0xFFFF, sum = 0
8549 09:28:49.075958 8, 0xFFFF, sum = 0
8550 09:28:49.079129 9, 0xFFFF, sum = 0
8551 09:28:49.079212 10, 0xFFFF, sum = 0
8552 09:28:49.082913 11, 0xFFFF, sum = 0
8553 09:28:49.083005 12, 0xFFFF, sum = 0
8554 09:28:49.086112 13, 0x8FFF, sum = 0
8555 09:28:49.086259 14, 0x0, sum = 1
8556 09:28:49.089345 15, 0x0, sum = 2
8557 09:28:49.089423 16, 0x0, sum = 3
8558 09:28:49.092504 17, 0x0, sum = 4
8559 09:28:49.092608 best_step = 15
8560 09:28:49.092707
8561 09:28:49.092764 ==
8562 09:28:49.095650 Dram Type= 6, Freq= 0, CH_1, rank 0
8563 09:28:49.099450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8564 09:28:49.099554 ==
8565 09:28:49.102476 RX Vref Scan: 1
8566 09:28:49.102569
8567 09:28:49.106200 Set Vref Range= 24 -> 127
8568 09:28:49.106319
8569 09:28:49.106380 RX Vref 24 -> 127, step: 1
8570 09:28:49.109435
8571 09:28:49.109514 RX Delay 11 -> 252, step: 4
8572 09:28:49.109573
8573 09:28:49.112605 Set Vref, RX VrefLevel [Byte0]: 24
8574 09:28:49.115763 [Byte1]: 24
8575 09:28:49.119327
8576 09:28:49.119433 Set Vref, RX VrefLevel [Byte0]: 25
8577 09:28:49.122384 [Byte1]: 25
8578 09:28:49.126875
8579 09:28:49.126986 Set Vref, RX VrefLevel [Byte0]: 26
8580 09:28:49.130173 [Byte1]: 26
8581 09:28:49.134489
8582 09:28:49.134565 Set Vref, RX VrefLevel [Byte0]: 27
8583 09:28:49.137985 [Byte1]: 27
8584 09:28:49.142191
8585 09:28:49.142277 Set Vref, RX VrefLevel [Byte0]: 28
8586 09:28:49.145632 [Byte1]: 28
8587 09:28:49.149546
8588 09:28:49.149671 Set Vref, RX VrefLevel [Byte0]: 29
8589 09:28:49.153046 [Byte1]: 29
8590 09:28:49.157646
8591 09:28:49.157735 Set Vref, RX VrefLevel [Byte0]: 30
8592 09:28:49.160462 [Byte1]: 30
8593 09:28:49.164828
8594 09:28:49.164914 Set Vref, RX VrefLevel [Byte0]: 31
8595 09:28:49.168492 [Byte1]: 31
8596 09:28:49.172841
8597 09:28:49.172926 Set Vref, RX VrefLevel [Byte0]: 32
8598 09:28:49.175985 [Byte1]: 32
8599 09:28:49.180420
8600 09:28:49.180503 Set Vref, RX VrefLevel [Byte0]: 33
8601 09:28:49.183522 [Byte1]: 33
8602 09:28:49.187949
8603 09:28:49.188035 Set Vref, RX VrefLevel [Byte0]: 34
8604 09:28:49.191031 [Byte1]: 34
8605 09:28:49.195337
8606 09:28:49.195423 Set Vref, RX VrefLevel [Byte0]: 35
8607 09:28:49.199002 [Byte1]: 35
8608 09:28:49.203266
8609 09:28:49.203350 Set Vref, RX VrefLevel [Byte0]: 36
8610 09:28:49.206415 [Byte1]: 36
8611 09:28:49.210627
8612 09:28:49.210714 Set Vref, RX VrefLevel [Byte0]: 37
8613 09:28:49.214187 [Byte1]: 37
8614 09:28:49.218378
8615 09:28:49.218464 Set Vref, RX VrefLevel [Byte0]: 38
8616 09:28:49.221364 [Byte1]: 38
8617 09:28:49.225676
8618 09:28:49.225761 Set Vref, RX VrefLevel [Byte0]: 39
8619 09:28:49.229291 [Byte1]: 39
8620 09:28:49.233427
8621 09:28:49.233513 Set Vref, RX VrefLevel [Byte0]: 40
8622 09:28:49.237055 [Byte1]: 40
8623 09:28:49.241196
8624 09:28:49.241278 Set Vref, RX VrefLevel [Byte0]: 41
8625 09:28:49.244153 [Byte1]: 41
8626 09:28:49.248420
8627 09:28:49.248503 Set Vref, RX VrefLevel [Byte0]: 42
8628 09:28:49.252027 [Byte1]: 42
8629 09:28:49.256281
8630 09:28:49.256369 Set Vref, RX VrefLevel [Byte0]: 43
8631 09:28:49.259842 [Byte1]: 43
8632 09:28:49.263796
8633 09:28:49.263876 Set Vref, RX VrefLevel [Byte0]: 44
8634 09:28:49.267132 [Byte1]: 44
8635 09:28:49.271628
8636 09:28:49.271707 Set Vref, RX VrefLevel [Byte0]: 45
8637 09:28:49.274948 [Byte1]: 45
8638 09:28:49.278984
8639 09:28:49.279069 Set Vref, RX VrefLevel [Byte0]: 46
8640 09:28:49.282722 [Byte1]: 46
8641 09:28:49.286909
8642 09:28:49.286990 Set Vref, RX VrefLevel [Byte0]: 47
8643 09:28:49.289924 [Byte1]: 47
8644 09:28:49.294356
8645 09:28:49.294439 Set Vref, RX VrefLevel [Byte0]: 48
8646 09:28:49.297930 [Byte1]: 48
8647 09:28:49.301689
8648 09:28:49.301772 Set Vref, RX VrefLevel [Byte0]: 49
8649 09:28:49.305436 [Byte1]: 49
8650 09:28:49.309771
8651 09:28:49.309871 Set Vref, RX VrefLevel [Byte0]: 50
8652 09:28:49.312910 [Byte1]: 50
8653 09:28:49.317242
8654 09:28:49.317327 Set Vref, RX VrefLevel [Byte0]: 51
8655 09:28:49.320201 [Byte1]: 51
8656 09:28:49.324639
8657 09:28:49.324747 Set Vref, RX VrefLevel [Byte0]: 52
8658 09:28:49.328336 [Byte1]: 52
8659 09:28:49.332578
8660 09:28:49.332689 Set Vref, RX VrefLevel [Byte0]: 53
8661 09:28:49.335519 [Byte1]: 53
8662 09:28:49.339881
8663 09:28:49.339987 Set Vref, RX VrefLevel [Byte0]: 54
8664 09:28:49.343621 [Byte1]: 54
8665 09:28:49.347422
8666 09:28:49.347503 Set Vref, RX VrefLevel [Byte0]: 55
8667 09:28:49.351024 [Byte1]: 55
8668 09:28:49.355372
8669 09:28:49.355464 Set Vref, RX VrefLevel [Byte0]: 56
8670 09:28:49.358475 [Byte1]: 56
8671 09:28:49.362787
8672 09:28:49.362868 Set Vref, RX VrefLevel [Byte0]: 57
8673 09:28:49.365959 [Byte1]: 57
8674 09:28:49.370239
8675 09:28:49.370320 Set Vref, RX VrefLevel [Byte0]: 58
8676 09:28:49.373595 [Byte1]: 58
8677 09:28:49.378285
8678 09:28:49.378373 Set Vref, RX VrefLevel [Byte0]: 59
8679 09:28:49.381204 [Byte1]: 59
8680 09:28:49.385735
8681 09:28:49.385836 Set Vref, RX VrefLevel [Byte0]: 60
8682 09:28:49.389229 [Byte1]: 60
8683 09:28:49.393441
8684 09:28:49.393525 Set Vref, RX VrefLevel [Byte0]: 61
8685 09:28:49.396595 [Byte1]: 61
8686 09:28:49.400933
8687 09:28:49.401015 Set Vref, RX VrefLevel [Byte0]: 62
8688 09:28:49.404468 [Byte1]: 62
8689 09:28:49.408848
8690 09:28:49.408932 Set Vref, RX VrefLevel [Byte0]: 63
8691 09:28:49.411949 [Byte1]: 63
8692 09:28:49.416317
8693 09:28:49.416398 Set Vref, RX VrefLevel [Byte0]: 64
8694 09:28:49.419372 [Byte1]: 64
8695 09:28:49.423638
8696 09:28:49.423739 Set Vref, RX VrefLevel [Byte0]: 65
8697 09:28:49.427388 [Byte1]: 65
8698 09:28:49.431314
8699 09:28:49.431413 Set Vref, RX VrefLevel [Byte0]: 66
8700 09:28:49.434718 [Byte1]: 66
8701 09:28:49.438922
8702 09:28:49.439008 Set Vref, RX VrefLevel [Byte0]: 67
8703 09:28:49.442523 [Byte1]: 67
8704 09:28:49.446448
8705 09:28:49.446531 Set Vref, RX VrefLevel [Byte0]: 68
8706 09:28:49.450193 [Byte1]: 68
8707 09:28:49.454537
8708 09:28:49.454623 Set Vref, RX VrefLevel [Byte0]: 69
8709 09:28:49.457475 [Byte1]: 69
8710 09:28:49.461799
8711 09:28:49.461884 Set Vref, RX VrefLevel [Byte0]: 70
8712 09:28:49.465031 [Byte1]: 70
8713 09:28:49.469422
8714 09:28:49.469506 Set Vref, RX VrefLevel [Byte0]: 71
8715 09:28:49.472511 [Byte1]: 71
8716 09:28:49.477359
8717 09:28:49.477446 Final RX Vref Byte 0 = 58 to rank0
8718 09:28:49.480341 Final RX Vref Byte 1 = 56 to rank0
8719 09:28:49.483742 Final RX Vref Byte 0 = 58 to rank1
8720 09:28:49.487357 Final RX Vref Byte 1 = 56 to rank1==
8721 09:28:49.490367 Dram Type= 6, Freq= 0, CH_1, rank 0
8722 09:28:49.496852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8723 09:28:49.496971 ==
8724 09:28:49.497049 DQS Delay:
8725 09:28:49.497121 DQS0 = 0, DQS1 = 0
8726 09:28:49.500250 DQM Delay:
8727 09:28:49.500348 DQM0 = 131, DQM1 = 123
8728 09:28:49.503382 DQ Delay:
8729 09:28:49.507122 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8730 09:28:49.510229 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8731 09:28:49.513371 DQ8 =110, DQ9 =114, DQ10 =122, DQ11 =116
8732 09:28:49.516508 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8733 09:28:49.516602
8734 09:28:49.516675
8735 09:28:49.516733
8736 09:28:49.520214 [DramC_TX_OE_Calibration] TA2
8737 09:28:49.523347 Original DQ_B0 (3 6) =30, OEN = 27
8738 09:28:49.527029 Original DQ_B1 (3 6) =30, OEN = 27
8739 09:28:49.530254 24, 0x0, End_B0=24 End_B1=24
8740 09:28:49.530355 25, 0x0, End_B0=25 End_B1=25
8741 09:28:49.533416 26, 0x0, End_B0=26 End_B1=26
8742 09:28:49.536874 27, 0x0, End_B0=27 End_B1=27
8743 09:28:49.539734 28, 0x0, End_B0=28 End_B1=28
8744 09:28:49.543151 29, 0x0, End_B0=29 End_B1=29
8745 09:28:49.543250 30, 0x0, End_B0=30 End_B1=30
8746 09:28:49.546489 31, 0x4141, End_B0=30 End_B1=30
8747 09:28:49.549600 Byte0 end_step=30 best_step=27
8748 09:28:49.553378 Byte1 end_step=30 best_step=27
8749 09:28:49.556432 Byte0 TX OE(2T, 0.5T) = (3, 3)
8750 09:28:49.559988 Byte1 TX OE(2T, 0.5T) = (3, 3)
8751 09:28:49.560072
8752 09:28:49.560132
8753 09:28:49.566389 [DQSOSCAuto] RK0, (LSB)MR18= 0xb10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
8754 09:28:49.569538 CH1 RK0: MR19=303, MR18=B10
8755 09:28:49.576330 CH1_RK0: MR19=0x303, MR18=0xB10, DQSOSC=401, MR23=63, INC=22, DEC=15
8756 09:28:49.576432
8757 09:28:49.579263 ----->DramcWriteLeveling(PI) begin...
8758 09:28:49.579346 ==
8759 09:28:49.582720 Dram Type= 6, Freq= 0, CH_1, rank 1
8760 09:28:49.586375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8761 09:28:49.586461 ==
8762 09:28:49.589365 Write leveling (Byte 0): 24 => 24
8763 09:28:49.592552 Write leveling (Byte 1): 29 => 29
8764 09:28:49.596107 DramcWriteLeveling(PI) end<-----
8765 09:28:49.596191
8766 09:28:49.596252 ==
8767 09:28:49.599123 Dram Type= 6, Freq= 0, CH_1, rank 1
8768 09:28:49.602882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8769 09:28:49.602965 ==
8770 09:28:49.605888 [Gating] SW mode calibration
8771 09:28:49.612423 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8772 09:28:49.619267 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8773 09:28:49.622383 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 09:28:49.629105 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (1 1)
8775 09:28:49.632162 1 4 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8776 09:28:49.635936 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 09:28:49.642107 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 09:28:49.645423 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 09:28:49.648934 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 09:28:49.655663 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 09:28:49.658689 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 09:28:49.662519 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8783 09:28:49.665739 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
8784 09:28:49.672473 1 5 12 | B1->B0 | 2727 2424 | 0 0 | (1 0) (1 0)
8785 09:28:49.675353 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 09:28:49.682197 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 09:28:49.685275 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 09:28:49.688272 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 09:28:49.695391 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 09:28:49.698334 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8791 09:28:49.701951 1 6 8 | B1->B0 | 2424 4242 | 0 0 | (0 0) (0 0)
8792 09:28:49.708242 1 6 12 | B1->B0 | 3f3f 4645 | 0 1 | (1 1) (0 0)
8793 09:28:49.711951 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 09:28:49.714891 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 09:28:49.718474 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 09:28:49.724747 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 09:28:49.728454 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 09:28:49.731473 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 09:28:49.738289 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8800 09:28:49.741476 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8801 09:28:49.745199 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8802 09:28:49.751889 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 09:28:49.755071 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 09:28:49.758094 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 09:28:49.764797 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 09:28:49.767804 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 09:28:49.771660 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 09:28:49.777810 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 09:28:49.781488 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 09:28:49.784533 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 09:28:49.791036 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 09:28:49.794861 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 09:28:49.797854 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 09:28:49.804833 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 09:28:49.807877 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8816 09:28:49.810985 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8817 09:28:49.817878 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 09:28:49.817972 Total UI for P1: 0, mck2ui 16
8819 09:28:49.824567 best dqsien dly found for B0: ( 1, 9, 10)
8820 09:28:49.824716 Total UI for P1: 0, mck2ui 16
8821 09:28:49.830857 best dqsien dly found for B1: ( 1, 9, 10)
8822 09:28:49.834290 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8823 09:28:49.837351 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8824 09:28:49.837433
8825 09:28:49.841199 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8826 09:28:49.844301 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8827 09:28:49.847426 [Gating] SW calibration Done
8828 09:28:49.847505 ==
8829 09:28:49.851145 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 09:28:49.854210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 09:28:49.854314 ==
8832 09:28:49.857339 RX Vref Scan: 0
8833 09:28:49.857416
8834 09:28:49.857475 RX Vref 0 -> 0, step: 1
8835 09:28:49.860538
8836 09:28:49.860639 RX Delay 0 -> 252, step: 8
8837 09:28:49.867389 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8838 09:28:49.870900 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8839 09:28:49.873792 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8840 09:28:49.877261 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8841 09:28:49.880798 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8842 09:28:49.883886 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8843 09:28:49.890584 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8844 09:28:49.893624 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8845 09:28:49.897499 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8846 09:28:49.900634 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8847 09:28:49.903790 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8848 09:28:49.910811 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8849 09:28:49.913791 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8850 09:28:49.917471 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8851 09:28:49.920597 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8852 09:28:49.927374 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8853 09:28:49.927472 ==
8854 09:28:49.930375 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 09:28:49.933505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 09:28:49.933585 ==
8857 09:28:49.933645 DQS Delay:
8858 09:28:49.937254 DQS0 = 0, DQS1 = 0
8859 09:28:49.937333 DQM Delay:
8860 09:28:49.940268 DQM0 = 129, DQM1 = 128
8861 09:28:49.940346 DQ Delay:
8862 09:28:49.943823 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8863 09:28:49.946596 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =127
8864 09:28:49.950205 DQ8 =111, DQ9 =115, DQ10 =135, DQ11 =123
8865 09:28:49.953331 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =139
8866 09:28:49.953420
8867 09:28:49.953479
8868 09:28:49.956998 ==
8869 09:28:49.960017 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 09:28:49.963188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 09:28:49.963269 ==
8872 09:28:49.963329
8873 09:28:49.963383
8874 09:28:49.966904 TX Vref Scan disable
8875 09:28:49.966983 == TX Byte 0 ==
8876 09:28:49.973183 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8877 09:28:49.976805 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8878 09:28:49.976889 == TX Byte 1 ==
8879 09:28:49.983186 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8880 09:28:49.986473 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8881 09:28:49.986556 ==
8882 09:28:49.989706 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 09:28:49.993308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 09:28:49.993390 ==
8885 09:28:50.008289
8886 09:28:50.011344 TX Vref early break, caculate TX vref
8887 09:28:50.014801 TX Vref=16, minBit 8, minWin=22, winSum=379
8888 09:28:50.017668 TX Vref=18, minBit 0, minWin=23, winSum=385
8889 09:28:50.021462 TX Vref=20, minBit 8, minWin=23, winSum=398
8890 09:28:50.024696 TX Vref=22, minBit 0, minWin=24, winSum=405
8891 09:28:50.027714 TX Vref=24, minBit 11, minWin=24, winSum=408
8892 09:28:50.034603 TX Vref=26, minBit 0, minWin=25, winSum=418
8893 09:28:50.037812 TX Vref=28, minBit 1, minWin=25, winSum=421
8894 09:28:50.041002 TX Vref=30, minBit 1, minWin=24, winSum=419
8895 09:28:50.045100 TX Vref=32, minBit 5, minWin=24, winSum=410
8896 09:28:50.047582 TX Vref=34, minBit 8, minWin=23, winSum=402
8897 09:28:50.051148 TX Vref=36, minBit 8, minWin=21, winSum=389
8898 09:28:50.058228 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
8899 09:28:50.058332
8900 09:28:50.061095 Final TX Range 0 Vref 28
8901 09:28:50.061173
8902 09:28:50.061232 ==
8903 09:28:50.064707 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 09:28:50.067888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 09:28:50.067971 ==
8906 09:28:50.068031
8907 09:28:50.068086
8908 09:28:50.071697 TX Vref Scan disable
8909 09:28:50.078016 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8910 09:28:50.078110 == TX Byte 0 ==
8911 09:28:50.081527 u2DelayCellOfst[0]=18 cells (5 PI)
8912 09:28:50.084575 u2DelayCellOfst[1]=11 cells (3 PI)
8913 09:28:50.087711 u2DelayCellOfst[2]=0 cells (0 PI)
8914 09:28:50.091397 u2DelayCellOfst[3]=7 cells (2 PI)
8915 09:28:50.094344 u2DelayCellOfst[4]=7 cells (2 PI)
8916 09:28:50.097764 u2DelayCellOfst[5]=18 cells (5 PI)
8917 09:28:50.100827 u2DelayCellOfst[6]=18 cells (5 PI)
8918 09:28:50.104685 u2DelayCellOfst[7]=7 cells (2 PI)
8919 09:28:50.107909 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8920 09:28:50.110787 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8921 09:28:50.114357 == TX Byte 1 ==
8922 09:28:50.117399 u2DelayCellOfst[8]=0 cells (0 PI)
8923 09:28:50.117480 u2DelayCellOfst[9]=7 cells (2 PI)
8924 09:28:50.120935 u2DelayCellOfst[10]=15 cells (4 PI)
8925 09:28:50.124398 u2DelayCellOfst[11]=7 cells (2 PI)
8926 09:28:50.127463 u2DelayCellOfst[12]=18 cells (5 PI)
8927 09:28:50.131190 u2DelayCellOfst[13]=18 cells (5 PI)
8928 09:28:50.134376 u2DelayCellOfst[14]=22 cells (6 PI)
8929 09:28:50.137573 u2DelayCellOfst[15]=18 cells (5 PI)
8930 09:28:50.143776 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8931 09:28:50.147575 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8932 09:28:50.147660 DramC Write-DBI on
8933 09:28:50.147719 ==
8934 09:28:50.150591 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 09:28:50.157518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 09:28:50.157619 ==
8937 09:28:50.157679
8938 09:28:50.157733
8939 09:28:50.157784 TX Vref Scan disable
8940 09:28:50.161255 == TX Byte 0 ==
8941 09:28:50.164777 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8942 09:28:50.167597 == TX Byte 1 ==
8943 09:28:50.171468 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8944 09:28:50.174586 DramC Write-DBI off
8945 09:28:50.174666
8946 09:28:50.174725 [DATLAT]
8947 09:28:50.174780 Freq=1600, CH1 RK1
8948 09:28:50.174833
8949 09:28:50.177756 DATLAT Default: 0xf
8950 09:28:50.177832 0, 0xFFFF, sum = 0
8951 09:28:50.180876 1, 0xFFFF, sum = 0
8952 09:28:50.184495 2, 0xFFFF, sum = 0
8953 09:28:50.184577 3, 0xFFFF, sum = 0
8954 09:28:50.187533 4, 0xFFFF, sum = 0
8955 09:28:50.187612 5, 0xFFFF, sum = 0
8956 09:28:50.191203 6, 0xFFFF, sum = 0
8957 09:28:50.191283 7, 0xFFFF, sum = 0
8958 09:28:50.194376 8, 0xFFFF, sum = 0
8959 09:28:50.194455 9, 0xFFFF, sum = 0
8960 09:28:50.197409 10, 0xFFFF, sum = 0
8961 09:28:50.197488 11, 0xFFFF, sum = 0
8962 09:28:50.201191 12, 0xFFFF, sum = 0
8963 09:28:50.201271 13, 0x8FFF, sum = 0
8964 09:28:50.204250 14, 0x0, sum = 1
8965 09:28:50.204327 15, 0x0, sum = 2
8966 09:28:50.207821 16, 0x0, sum = 3
8967 09:28:50.207900 17, 0x0, sum = 4
8968 09:28:50.210827 best_step = 15
8969 09:28:50.210905
8970 09:28:50.210965 ==
8971 09:28:50.214184 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 09:28:50.217426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 09:28:50.217505 ==
8974 09:28:50.220889 RX Vref Scan: 0
8975 09:28:50.220969
8976 09:28:50.221029 RX Vref 0 -> 0, step: 1
8977 09:28:50.221085
8978 09:28:50.223925 RX Delay 3 -> 252, step: 4
8979 09:28:50.227374 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8980 09:28:50.234130 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8981 09:28:50.237252 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8982 09:28:50.240553 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8983 09:28:50.244243 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8984 09:28:50.247325 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8985 09:28:50.254192 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8986 09:28:50.257247 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8987 09:28:50.260373 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8988 09:28:50.264108 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8989 09:28:50.267230 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8990 09:28:50.273924 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8991 09:28:50.277273 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8992 09:28:50.280877 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8993 09:28:50.283917 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8994 09:28:50.290192 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8995 09:28:50.290286 ==
8996 09:28:50.293830 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 09:28:50.296913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 09:28:50.296993 ==
8999 09:28:50.297053 DQS Delay:
9000 09:28:50.300049 DQS0 = 0, DQS1 = 0
9001 09:28:50.300126 DQM Delay:
9002 09:28:50.303903 DQM0 = 127, DQM1 = 125
9003 09:28:50.303983 DQ Delay:
9004 09:28:50.307059 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =126
9005 09:28:50.310169 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9006 09:28:50.313735 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =118
9007 09:28:50.316880 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =136
9008 09:28:50.316963
9009 09:28:50.317022
9010 09:28:50.319962
9011 09:28:50.320039 [DramC_TX_OE_Calibration] TA2
9012 09:28:50.323578 Original DQ_B0 (3 6) =30, OEN = 27
9013 09:28:50.326878 Original DQ_B1 (3 6) =30, OEN = 27
9014 09:28:50.330472 24, 0x0, End_B0=24 End_B1=24
9015 09:28:50.333541 25, 0x0, End_B0=25 End_B1=25
9016 09:28:50.337067 26, 0x0, End_B0=26 End_B1=26
9017 09:28:50.337154 27, 0x0, End_B0=27 End_B1=27
9018 09:28:50.340053 28, 0x0, End_B0=28 End_B1=28
9019 09:28:50.343590 29, 0x0, End_B0=29 End_B1=29
9020 09:28:50.346774 30, 0x0, End_B0=30 End_B1=30
9021 09:28:50.350188 31, 0x4545, End_B0=30 End_B1=30
9022 09:28:50.350271 Byte0 end_step=30 best_step=27
9023 09:28:50.353429 Byte1 end_step=30 best_step=27
9024 09:28:50.356554 Byte0 TX OE(2T, 0.5T) = (3, 3)
9025 09:28:50.360250 Byte1 TX OE(2T, 0.5T) = (3, 3)
9026 09:28:50.360332
9027 09:28:50.360391
9028 09:28:50.366492 [DQSOSCAuto] RK1, (LSB)MR18= 0x131f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9029 09:28:50.370283 CH1 RK1: MR19=303, MR18=131F
9030 09:28:50.376430 CH1_RK1: MR19=0x303, MR18=0x131F, DQSOSC=394, MR23=63, INC=23, DEC=15
9031 09:28:50.380182 [RxdqsGatingPostProcess] freq 1600
9032 09:28:50.386649 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9033 09:28:50.389527 best DQS0 dly(2T, 0.5T) = (1, 1)
9034 09:28:50.389611 best DQS1 dly(2T, 0.5T) = (1, 1)
9035 09:28:50.392986 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9036 09:28:50.396584 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9037 09:28:50.399721 best DQS0 dly(2T, 0.5T) = (1, 1)
9038 09:28:50.402904 best DQS1 dly(2T, 0.5T) = (1, 1)
9039 09:28:50.406134 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9040 09:28:50.409883 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9041 09:28:50.412957 Pre-setting of DQS Precalculation
9042 09:28:50.416464 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9043 09:28:50.426472 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9044 09:28:50.432990 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9045 09:28:50.433091
9046 09:28:50.433151
9047 09:28:50.436469 [Calibration Summary] 3200 Mbps
9048 09:28:50.436548 CH 0, Rank 0
9049 09:28:50.439342 SW Impedance : PASS
9050 09:28:50.443063 DUTY Scan : NO K
9051 09:28:50.443144 ZQ Calibration : PASS
9052 09:28:50.446203 Jitter Meter : NO K
9053 09:28:50.446283 CBT Training : PASS
9054 09:28:50.449287 Write leveling : PASS
9055 09:28:50.452927 RX DQS gating : PASS
9056 09:28:50.453013 RX DQ/DQS(RDDQC) : PASS
9057 09:28:50.455929 TX DQ/DQS : PASS
9058 09:28:50.459306 RX DATLAT : PASS
9059 09:28:50.459387 RX DQ/DQS(Engine): PASS
9060 09:28:50.462777 TX OE : PASS
9061 09:28:50.462855 All Pass.
9062 09:28:50.462915
9063 09:28:50.465730 CH 0, Rank 1
9064 09:28:50.465808 SW Impedance : PASS
9065 09:28:50.469571 DUTY Scan : NO K
9066 09:28:50.472583 ZQ Calibration : PASS
9067 09:28:50.472702 Jitter Meter : NO K
9068 09:28:50.476226 CBT Training : PASS
9069 09:28:50.479374 Write leveling : PASS
9070 09:28:50.479454 RX DQS gating : PASS
9071 09:28:50.482561 RX DQ/DQS(RDDQC) : PASS
9072 09:28:50.485668 TX DQ/DQS : PASS
9073 09:28:50.485748 RX DATLAT : PASS
9074 09:28:50.489263 RX DQ/DQS(Engine): PASS
9075 09:28:50.489342 TX OE : PASS
9076 09:28:50.492335 All Pass.
9077 09:28:50.492412
9078 09:28:50.492471 CH 1, Rank 0
9079 09:28:50.495832 SW Impedance : PASS
9080 09:28:50.499349 DUTY Scan : NO K
9081 09:28:50.499429 ZQ Calibration : PASS
9082 09:28:50.502806 Jitter Meter : NO K
9083 09:28:50.502884 CBT Training : PASS
9084 09:28:50.505948 Write leveling : PASS
9085 09:28:50.509052 RX DQS gating : PASS
9086 09:28:50.509131 RX DQ/DQS(RDDQC) : PASS
9087 09:28:50.512768 TX DQ/DQS : PASS
9088 09:28:50.515901 RX DATLAT : PASS
9089 09:28:50.515980 RX DQ/DQS(Engine): PASS
9090 09:28:50.518915 TX OE : PASS
9091 09:28:50.518992 All Pass.
9092 09:28:50.519052
9093 09:28:50.522488 CH 1, Rank 1
9094 09:28:50.522568 SW Impedance : PASS
9095 09:28:50.525580 DUTY Scan : NO K
9096 09:28:50.529387 ZQ Calibration : PASS
9097 09:28:50.529466 Jitter Meter : NO K
9098 09:28:50.532519 CBT Training : PASS
9099 09:28:50.535597 Write leveling : PASS
9100 09:28:50.535677 RX DQS gating : PASS
9101 09:28:50.539094 RX DQ/DQS(RDDQC) : PASS
9102 09:28:50.542655 TX DQ/DQS : PASS
9103 09:28:50.542737 RX DATLAT : PASS
9104 09:28:50.545450 RX DQ/DQS(Engine): PASS
9105 09:28:50.545528 TX OE : PASS
9106 09:28:50.549195 All Pass.
9107 09:28:50.549276
9108 09:28:50.549335 DramC Write-DBI on
9109 09:28:50.552284 PER_BANK_REFRESH: Hybrid Mode
9110 09:28:50.555447 TX_TRACKING: ON
9111 09:28:50.562339 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9112 09:28:50.571989 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9113 09:28:50.579024 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9114 09:28:50.582286 [FAST_K] Save calibration result to emmc
9115 09:28:50.585418 sync common calibartion params.
9116 09:28:50.585499 sync cbt_mode0:1, 1:1
9117 09:28:50.589211 dram_init: ddr_geometry: 2
9118 09:28:50.591906 dram_init: ddr_geometry: 2
9119 09:28:50.595480 dram_init: ddr_geometry: 2
9120 09:28:50.595564 0:dram_rank_size:100000000
9121 09:28:50.598526 1:dram_rank_size:100000000
9122 09:28:50.605424 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9123 09:28:50.605519 DFS_SHUFFLE_HW_MODE: ON
9124 09:28:50.611729 dramc_set_vcore_voltage set vcore to 725000
9125 09:28:50.611818 Read voltage for 1600, 0
9126 09:28:50.614958 Vio18 = 0
9127 09:28:50.615037 Vcore = 725000
9128 09:28:50.615096 Vdram = 0
9129 09:28:50.618626 Vddq = 0
9130 09:28:50.618706 Vmddr = 0
9131 09:28:50.621713 switch to 3200 Mbps bootup
9132 09:28:50.621793 [DramcRunTimeConfig]
9133 09:28:50.621853 PHYPLL
9134 09:28:50.625315 DPM_CONTROL_AFTERK: ON
9135 09:28:50.628426 PER_BANK_REFRESH: ON
9136 09:28:50.628505 REFRESH_OVERHEAD_REDUCTION: ON
9137 09:28:50.632242 CMD_PICG_NEW_MODE: OFF
9138 09:28:50.632322 XRTWTW_NEW_MODE: ON
9139 09:28:50.635445 XRTRTR_NEW_MODE: ON
9140 09:28:50.635523 TX_TRACKING: ON
9141 09:28:50.638574 RDSEL_TRACKING: OFF
9142 09:28:50.642221 DQS Precalculation for DVFS: ON
9143 09:28:50.642337 RX_TRACKING: OFF
9144 09:28:50.645237 HW_GATING DBG: ON
9145 09:28:50.645315 ZQCS_ENABLE_LP4: ON
9146 09:28:50.648316 RX_PICG_NEW_MODE: ON
9147 09:28:50.651770 TX_PICG_NEW_MODE: ON
9148 09:28:50.651895 ENABLE_RX_DCM_DPHY: ON
9149 09:28:50.654959 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9150 09:28:50.658692 DUMMY_READ_FOR_TRACKING: OFF
9151 09:28:50.661785 !!! SPM_CONTROL_AFTERK: OFF
9152 09:28:50.661870 !!! SPM could not control APHY
9153 09:28:50.664926 IMPEDANCE_TRACKING: ON
9154 09:28:50.665004 TEMP_SENSOR: ON
9155 09:28:50.668014 HW_SAVE_FOR_SR: OFF
9156 09:28:50.671861 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9157 09:28:50.674858 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9158 09:28:50.678570 Read ODT Tracking: ON
9159 09:28:50.678654 Refresh Rate DeBounce: ON
9160 09:28:50.681708 DFS_NO_QUEUE_FLUSH: ON
9161 09:28:50.684871 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9162 09:28:50.687993 ENABLE_DFS_RUNTIME_MRW: OFF
9163 09:28:50.688075 DDR_RESERVE_NEW_MODE: ON
9164 09:28:50.691715 MR_CBT_SWITCH_FREQ: ON
9165 09:28:50.694647 =========================
9166 09:28:50.712566 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9167 09:28:50.716084 dram_init: ddr_geometry: 2
9168 09:28:50.734577 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9169 09:28:50.737787 dram_init: dram init end (result: 0)
9170 09:28:50.744065 DRAM-K: Full calibration passed in 24592 msecs
9171 09:28:50.747601 MRC: failed to locate region type 0.
9172 09:28:50.747681 DRAM rank0 size:0x100000000,
9173 09:28:50.750791 DRAM rank1 size=0x100000000
9174 09:28:50.760985 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9175 09:28:50.767176 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9176 09:28:50.774125 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9177 09:28:50.780804 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9178 09:28:50.783951 DRAM rank0 size:0x100000000,
9179 09:28:50.786999 DRAM rank1 size=0x100000000
9180 09:28:50.787075 CBMEM:
9181 09:28:50.790768 IMD: root @ 0xfffff000 254 entries.
9182 09:28:50.793931 IMD: root @ 0xffffec00 62 entries.
9183 09:28:50.797162 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9184 09:28:50.803862 WARNING: RO_VPD is uninitialized or empty.
9185 09:28:50.806845 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9186 09:28:50.814418 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9187 09:28:50.827208 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9188 09:28:50.838655 BS: romstage times (exec / console): total (unknown) / 24053 ms
9189 09:28:50.838734
9190 09:28:50.838793
9191 09:28:50.848595 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9192 09:28:50.851637 ARM64: Exception handlers installed.
9193 09:28:50.854705 ARM64: Testing exception
9194 09:28:50.858406 ARM64: Done test exception
9195 09:28:50.858483 Enumerating buses...
9196 09:28:50.861382 Show all devs... Before device enumeration.
9197 09:28:50.864841 Root Device: enabled 1
9198 09:28:50.867919 CPU_CLUSTER: 0: enabled 1
9199 09:28:50.867996 CPU: 00: enabled 1
9200 09:28:50.871715 Compare with tree...
9201 09:28:50.871791 Root Device: enabled 1
9202 09:28:50.874870 CPU_CLUSTER: 0: enabled 1
9203 09:28:50.878013 CPU: 00: enabled 1
9204 09:28:50.878089 Root Device scanning...
9205 09:28:50.881168 scan_static_bus for Root Device
9206 09:28:50.884754 CPU_CLUSTER: 0 enabled
9207 09:28:50.887815 scan_static_bus for Root Device done
9208 09:28:50.891581 scan_bus: bus Root Device finished in 8 msecs
9209 09:28:50.891657 done
9210 09:28:50.898311 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9211 09:28:50.901482 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9212 09:28:50.907753 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9213 09:28:50.911293 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9214 09:28:50.914352 Allocating resources...
9215 09:28:50.918180 Reading resources...
9216 09:28:50.921268 Root Device read_resources bus 0 link: 0
9217 09:28:50.921344 DRAM rank0 size:0x100000000,
9218 09:28:50.924795 DRAM rank1 size=0x100000000
9219 09:28:50.927749 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9220 09:28:50.931521 CPU: 00 missing read_resources
9221 09:28:50.937877 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9222 09:28:50.940958 Root Device read_resources bus 0 link: 0 done
9223 09:28:50.941034 Done reading resources.
9224 09:28:50.947589 Show resources in subtree (Root Device)...After reading.
9225 09:28:50.951018 Root Device child on link 0 CPU_CLUSTER: 0
9226 09:28:50.954268 CPU_CLUSTER: 0 child on link 0 CPU: 00
9227 09:28:50.964473 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9228 09:28:50.964561 CPU: 00
9229 09:28:50.967442 Root Device assign_resources, bus 0 link: 0
9230 09:28:50.971059 CPU_CLUSTER: 0 missing set_resources
9231 09:28:50.977376 Root Device assign_resources, bus 0 link: 0 done
9232 09:28:50.977456 Done setting resources.
9233 09:28:50.984160 Show resources in subtree (Root Device)...After assigning values.
9234 09:28:50.987753 Root Device child on link 0 CPU_CLUSTER: 0
9235 09:28:50.990808 CPU_CLUSTER: 0 child on link 0 CPU: 00
9236 09:28:51.000794 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9237 09:28:51.000875 CPU: 00
9238 09:28:51.003900 Done allocating resources.
9239 09:28:51.010866 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9240 09:28:51.010943 Enabling resources...
9241 09:28:51.011003 done.
9242 09:28:51.017519 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9243 09:28:51.017596 Initializing devices...
9244 09:28:51.020776 Root Device init
9245 09:28:51.020852 init hardware done!
9246 09:28:51.023794 0x00000018: ctrlr->caps
9247 09:28:51.027443 52.000 MHz: ctrlr->f_max
9248 09:28:51.027522 0.400 MHz: ctrlr->f_min
9249 09:28:51.030405 0x40ff8080: ctrlr->voltages
9250 09:28:51.034071 sclk: 390625
9251 09:28:51.034147 Bus Width = 1
9252 09:28:51.034207 sclk: 390625
9253 09:28:51.037279 Bus Width = 1
9254 09:28:51.037356 Early init status = 3
9255 09:28:51.043897 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9256 09:28:51.047430 in-header: 03 fc 00 00 01 00 00 00
9257 09:28:51.047507 in-data: 00
9258 09:28:51.053736 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9259 09:28:51.057495 in-header: 03 fd 00 00 00 00 00 00
9260 09:28:51.060639 in-data:
9261 09:28:51.064219 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9262 09:28:51.068295 in-header: 03 fc 00 00 01 00 00 00
9263 09:28:51.071788 in-data: 00
9264 09:28:51.074677 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9265 09:28:51.080271 in-header: 03 fd 00 00 00 00 00 00
9266 09:28:51.083528 in-data:
9267 09:28:51.087208 [SSUSB] Setting up USB HOST controller...
9268 09:28:51.090425 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9269 09:28:51.093630 [SSUSB] phy power-on done.
9270 09:28:51.096974 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9271 09:28:51.103775 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9272 09:28:51.106852 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9273 09:28:51.113775 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9274 09:28:51.119782 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9275 09:28:51.126651 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9276 09:28:51.133485 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9277 09:28:51.140207 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9278 09:28:51.143299 SPM: binary array size = 0x9dc
9279 09:28:51.146412 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9280 09:28:51.152902 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9281 09:28:51.159796 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9282 09:28:51.166672 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9283 09:28:51.169655 configure_display: Starting display init
9284 09:28:51.203651 anx7625_power_on_init: Init interface.
9285 09:28:51.206887 anx7625_disable_pd_protocol: Disabled PD feature.
9286 09:28:51.210162 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9287 09:28:51.238285 anx7625_start_dp_work: Secure OCM version=00
9288 09:28:51.241295 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9289 09:28:51.256288 sp_tx_get_edid_block: EDID Block = 1
9290 09:28:51.358672 Extracted contents:
9291 09:28:51.361751 header: 00 ff ff ff ff ff ff 00
9292 09:28:51.365434 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9293 09:28:51.368288 version: 01 04
9294 09:28:51.371923 basic params: 95 1f 11 78 0a
9295 09:28:51.375114 chroma info: 76 90 94 55 54 90 27 21 50 54
9296 09:28:51.378261 established: 00 00 00
9297 09:28:51.384983 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9298 09:28:51.391783 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9299 09:28:51.394790 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9300 09:28:51.401748 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9301 09:28:51.408367 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9302 09:28:51.411486 extensions: 00
9303 09:28:51.411562 checksum: fb
9304 09:28:51.411622
9305 09:28:51.414735 Manufacturer: IVO Model 57d Serial Number 0
9306 09:28:51.417834 Made week 0 of 2020
9307 09:28:51.421570 EDID version: 1.4
9308 09:28:51.421645 Digital display
9309 09:28:51.424726 6 bits per primary color channel
9310 09:28:51.424801 DisplayPort interface
9311 09:28:51.427740 Maximum image size: 31 cm x 17 cm
9312 09:28:51.430880 Gamma: 220%
9313 09:28:51.430954 Check DPMS levels
9314 09:28:51.434544 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9315 09:28:51.440921 First detailed timing is preferred timing
9316 09:28:51.441000 Established timings supported:
9317 09:28:51.444343 Standard timings supported:
9318 09:28:51.447619 Detailed timings
9319 09:28:51.450865 Hex of detail: 383680a07038204018303c0035ae10000019
9320 09:28:51.457383 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9321 09:28:51.461185 0780 0798 07c8 0820 hborder 0
9322 09:28:51.464530 0438 043b 0447 0458 vborder 0
9323 09:28:51.467660 -hsync -vsync
9324 09:28:51.467737 Did detailed timing
9325 09:28:51.474423 Hex of detail: 000000000000000000000000000000000000
9326 09:28:51.477241 Manufacturer-specified data, tag 0
9327 09:28:51.480770 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9328 09:28:51.483831 ASCII string: InfoVision
9329 09:28:51.487470 Hex of detail: 000000fe00523134304e574635205248200a
9330 09:28:51.490608 ASCII string: R140NWF5 RH
9331 09:28:51.490698 Checksum
9332 09:28:51.494230 Checksum: 0xfb (valid)
9333 09:28:51.497075 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9334 09:28:51.500521 DSI data_rate: 832800000 bps
9335 09:28:51.507048 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9336 09:28:51.510724 anx7625_parse_edid: pixelclock(138800).
9337 09:28:51.513804 hactive(1920), hsync(48), hfp(24), hbp(88)
9338 09:28:51.516914 vactive(1080), vsync(12), vfp(3), vbp(17)
9339 09:28:51.520576 anx7625_dsi_config: config dsi.
9340 09:28:51.526783 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9341 09:28:51.540330 anx7625_dsi_config: success to config DSI
9342 09:28:51.544158 anx7625_dp_start: MIPI phy setup OK.
9343 09:28:51.547232 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9344 09:28:51.550323 mtk_ddp_mode_set invalid vrefresh 60
9345 09:28:51.553930 main_disp_path_setup
9346 09:28:51.554012 ovl_layer_smi_id_en
9347 09:28:51.557031 ovl_layer_smi_id_en
9348 09:28:51.557109 ccorr_config
9349 09:28:51.557169 aal_config
9350 09:28:51.560562 gamma_config
9351 09:28:51.560684 postmask_config
9352 09:28:51.563643 dither_config
9353 09:28:51.567200 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9354 09:28:51.573306 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9355 09:28:51.576562 Root Device init finished in 553 msecs
9356 09:28:51.580273 CPU_CLUSTER: 0 init
9357 09:28:51.586554 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9358 09:28:51.593251 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9359 09:28:51.593360 APU_MBOX 0x190000b0 = 0x10001
9360 09:28:51.596297 APU_MBOX 0x190001b0 = 0x10001
9361 09:28:51.600070 APU_MBOX 0x190005b0 = 0x10001
9362 09:28:51.603006 APU_MBOX 0x190006b0 = 0x10001
9363 09:28:51.609420 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9364 09:28:51.619677 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9365 09:28:51.632251 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9366 09:28:51.638780 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9367 09:28:51.650074 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9368 09:28:51.659562 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9369 09:28:51.662620 CPU_CLUSTER: 0 init finished in 81 msecs
9370 09:28:51.666176 Devices initialized
9371 09:28:51.669196 Show all devs... After init.
9372 09:28:51.669275 Root Device: enabled 1
9373 09:28:51.672923 CPU_CLUSTER: 0: enabled 1
9374 09:28:51.675964 CPU: 00: enabled 1
9375 09:28:51.679001 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9376 09:28:51.682392 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9377 09:28:51.685732 ELOG: NV offset 0x57f000 size 0x1000
9378 09:28:51.692626 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9379 09:28:51.699189 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9380 09:28:51.702246 ELOG: Event(17) added with size 13 at 2024-06-18 09:28:51 UTC
9381 09:28:51.708910 out: cmd=0x121: 03 db 21 01 00 00 00 00
9382 09:28:51.712563 in-header: 03 aa 00 00 2c 00 00 00
9383 09:28:51.722481 in-data: 92 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9384 09:28:51.729249 ELOG: Event(A1) added with size 10 at 2024-06-18 09:28:51 UTC
9385 09:28:51.735500 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9386 09:28:51.742399 ELOG: Event(A0) added with size 9 at 2024-06-18 09:28:51 UTC
9387 09:28:51.745397 elog_add_boot_reason: Logged dev mode boot
9388 09:28:51.752278 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9389 09:28:51.752383 Finalize devices...
9390 09:28:51.755384 Devices finalized
9391 09:28:51.758890 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9392 09:28:51.761878 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9393 09:28:51.765615 in-header: 03 07 00 00 08 00 00 00
9394 09:28:51.768555 in-data: aa e4 47 04 13 02 00 00
9395 09:28:51.771595 Chrome EC: UHEPI supported
9396 09:28:51.778429 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9397 09:28:51.781605 in-header: 03 a9 00 00 08 00 00 00
9398 09:28:51.785372 in-data: 84 60 60 08 00 00 00 00
9399 09:28:51.791841 ELOG: Event(91) added with size 10 at 2024-06-18 09:28:51 UTC
9400 09:28:51.795020 Chrome EC: clear events_b mask to 0x0000000020004000
9401 09:28:51.802168 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9402 09:28:51.805447 in-header: 03 fd 00 00 00 00 00 00
9403 09:28:51.805547 in-data:
9404 09:28:51.812197 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9405 09:28:51.815265 Writing coreboot table at 0xffe64000
9406 09:28:51.818429 0. 000000000010a000-0000000000113fff: RAMSTAGE
9407 09:28:51.822055 1. 0000000040000000-00000000400fffff: RAM
9408 09:28:51.828576 2. 0000000040100000-000000004032afff: RAMSTAGE
9409 09:28:51.832171 3. 000000004032b000-00000000545fffff: RAM
9410 09:28:51.835316 4. 0000000054600000-000000005465ffff: BL31
9411 09:28:51.838474 5. 0000000054660000-00000000ffe63fff: RAM
9412 09:28:51.845218 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9413 09:28:51.848424 7. 0000000100000000-000000023fffffff: RAM
9414 09:28:51.852092 Passing 5 GPIOs to payload:
9415 09:28:51.855230 NAME | PORT | POLARITY | VALUE
9416 09:28:51.858502 EC in RW | 0x000000aa | low | undefined
9417 09:28:51.864788 EC interrupt | 0x00000005 | low | undefined
9418 09:28:51.868273 TPM interrupt | 0x000000ab | high | undefined
9419 09:28:51.874757 SD card detect | 0x00000011 | high | undefined
9420 09:28:51.878298 speaker enable | 0x00000093 | high | undefined
9421 09:28:51.881382 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9422 09:28:51.884615 in-header: 03 f9 00 00 02 00 00 00
9423 09:28:51.887861 in-data: 02 00
9424 09:28:51.887931 ADC[4]: Raw value=896670 ID=7
9425 09:28:51.891731 ADC[3]: Raw value=212700 ID=1
9426 09:28:51.894699 RAM Code: 0x71
9427 09:28:51.894764 ADC[6]: Raw value=74722 ID=0
9428 09:28:51.898187 ADC[5]: Raw value=211960 ID=1
9429 09:28:51.901282 SKU Code: 0x1
9430 09:28:51.904336 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 6f89
9431 09:28:51.907942 coreboot table: 964 bytes.
9432 09:28:51.911087 IMD ROOT 0. 0xfffff000 0x00001000
9433 09:28:51.914629 IMD SMALL 1. 0xffffe000 0x00001000
9434 09:28:51.918005 RO MCACHE 2. 0xffffc000 0x00001104
9435 09:28:51.921307 CONSOLE 3. 0xfff7c000 0x00080000
9436 09:28:51.924274 FMAP 4. 0xfff7b000 0x00000452
9437 09:28:51.927511 TIME STAMP 5. 0xfff7a000 0x00000910
9438 09:28:51.930896 VBOOT WORK 6. 0xfff66000 0x00014000
9439 09:28:51.934274 RAMOOPS 7. 0xffe66000 0x00100000
9440 09:28:51.937275 COREBOOT 8. 0xffe64000 0x00002000
9441 09:28:51.940902 IMD small region:
9442 09:28:51.944184 IMD ROOT 0. 0xffffec00 0x00000400
9443 09:28:51.947233 VPD 1. 0xffffeb80 0x0000006c
9444 09:28:51.951169 MMC STATUS 2. 0xffffeb60 0x00000004
9445 09:28:51.954291 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9446 09:28:51.960605 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9447 09:28:52.001312 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9448 09:28:52.004319 Checking segment from ROM address 0x40100000
9449 09:28:52.008131 Checking segment from ROM address 0x4010001c
9450 09:28:52.014519 Loading segment from ROM address 0x40100000
9451 09:28:52.014595 code (compression=0)
9452 09:28:52.024451 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9453 09:28:52.031102 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9454 09:28:52.031185 it's not compressed!
9455 09:28:52.037571 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9456 09:28:52.044598 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9457 09:28:52.061545 Loading segment from ROM address 0x4010001c
9458 09:28:52.061677 Entry Point 0x80000000
9459 09:28:52.065272 Loaded segments
9460 09:28:52.068235 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9461 09:28:52.074623 Jumping to boot code at 0x80000000(0xffe64000)
9462 09:28:52.081257 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9463 09:28:52.088060 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9464 09:28:52.096036 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9465 09:28:52.099210 Checking segment from ROM address 0x40100000
9466 09:28:52.102957 Checking segment from ROM address 0x4010001c
9467 09:28:52.109563 Loading segment from ROM address 0x40100000
9468 09:28:52.109643 code (compression=1)
9469 09:28:52.115946 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9470 09:28:52.125905 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9471 09:28:52.125994 using LZMA
9472 09:28:52.134648 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9473 09:28:52.140921 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9474 09:28:52.144391 Loading segment from ROM address 0x4010001c
9475 09:28:52.144469 Entry Point 0x54601000
9476 09:28:52.147762 Loaded segments
9477 09:28:52.151100 NOTICE: MT8192 bl31_setup
9478 09:28:52.158055 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9479 09:28:52.161493 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9480 09:28:52.164621 WARNING: region 0:
9481 09:28:52.168485 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 09:28:52.168589 WARNING: region 1:
9483 09:28:52.174731 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9484 09:28:52.177883 WARNING: region 2:
9485 09:28:52.181627 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9486 09:28:52.184789 WARNING: region 3:
9487 09:28:52.187813 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9488 09:28:52.191360 WARNING: region 4:
9489 09:28:52.197627 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9490 09:28:52.197721 WARNING: region 5:
9491 09:28:52.201450 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 09:28:52.204626 WARNING: region 6:
9493 09:28:52.207864 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 09:28:52.211078 WARNING: region 7:
9495 09:28:52.214428 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 09:28:52.221284 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9497 09:28:52.224100 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9498 09:28:52.231122 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9499 09:28:52.234128 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9500 09:28:52.237435 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9501 09:28:52.243935 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9502 09:28:52.247534 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9503 09:28:52.250451 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9504 09:28:52.257411 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9505 09:28:52.260305 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9506 09:28:52.266868 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9507 09:28:52.270256 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9508 09:28:52.273836 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9509 09:28:52.280105 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9510 09:28:52.283797 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9511 09:28:52.287082 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9512 09:28:52.293568 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9513 09:28:52.296841 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9514 09:28:52.303520 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9515 09:28:52.306913 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9516 09:28:52.309985 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9517 09:28:52.316983 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9518 09:28:52.320165 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9519 09:28:52.326898 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9520 09:28:52.329814 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9521 09:28:52.333178 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9522 09:28:52.339718 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9523 09:28:52.343447 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9524 09:28:52.349553 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9525 09:28:52.353264 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9526 09:28:52.356408 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9527 09:28:52.363254 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9528 09:28:52.366264 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9529 09:28:52.369711 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9530 09:28:52.376537 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9531 09:28:52.379683 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9532 09:28:52.383168 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9533 09:28:52.386405 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9534 09:28:52.393047 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9535 09:28:52.396581 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9536 09:28:52.399681 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9537 09:28:52.402780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9538 09:28:52.409359 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9539 09:28:52.412930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9540 09:28:52.415828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9541 09:28:52.419451 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9542 09:28:52.425563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9543 09:28:52.429378 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9544 09:28:52.432452 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9545 09:28:52.439263 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9546 09:28:52.442196 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9547 09:28:52.449202 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9548 09:28:52.452351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9549 09:28:52.459181 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9550 09:28:52.462340 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9551 09:28:52.465549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9552 09:28:52.472334 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9553 09:28:52.475391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9554 09:28:52.482278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9555 09:28:52.485554 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9556 09:28:52.491949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9557 09:28:52.495601 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9558 09:28:52.502132 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9559 09:28:52.505530 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9560 09:28:52.508495 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9561 09:28:52.515240 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9562 09:28:52.518359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9563 09:28:52.525382 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9564 09:28:52.528501 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9565 09:28:52.535422 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9566 09:28:52.538589 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9567 09:28:52.545063 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9568 09:28:52.548110 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9569 09:28:52.551701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9570 09:28:52.558144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9571 09:28:52.561171 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9572 09:28:52.568227 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9573 09:28:52.571296 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9574 09:28:52.578237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9575 09:28:52.581298 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9576 09:28:52.587940 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9577 09:28:52.591690 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9578 09:28:52.594860 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9579 09:28:52.601208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9580 09:28:52.604959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9581 09:28:52.611697 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9582 09:28:52.614580 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9583 09:28:52.621424 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9584 09:28:52.625019 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9585 09:28:52.628191 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9586 09:28:52.634334 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9587 09:28:52.638190 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9588 09:28:52.644632 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9589 09:28:52.647736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9590 09:28:52.654654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9591 09:28:52.657778 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9592 09:28:52.661358 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9593 09:28:52.667783 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9594 09:28:52.670828 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9595 09:28:52.673963 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9596 09:28:52.677221 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9597 09:28:52.684421 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9598 09:28:52.687499 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9599 09:28:52.694103 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9600 09:28:52.696966 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9601 09:28:52.700786 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9602 09:28:52.706892 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9603 09:28:52.710518 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9604 09:28:52.716936 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9605 09:28:52.720064 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9606 09:28:52.726773 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9607 09:28:52.730443 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9608 09:28:52.733889 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9609 09:28:52.740290 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9610 09:28:52.743217 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9611 09:28:52.750066 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9612 09:28:52.753195 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9613 09:28:52.757099 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9614 09:28:52.760236 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9615 09:28:52.766536 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9616 09:28:52.770310 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9617 09:28:52.773272 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9618 09:28:52.776750 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9619 09:28:52.783293 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9620 09:28:52.786476 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9621 09:28:52.792811 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9622 09:28:52.796513 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9623 09:28:52.799634 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9624 09:28:52.806417 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9625 09:28:52.809638 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9626 09:28:52.813257 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9627 09:28:52.819635 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9628 09:28:52.822921 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9629 09:28:52.829763 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9630 09:28:52.832679 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9631 09:28:52.839664 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9632 09:28:52.842794 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9633 09:28:52.845875 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9634 09:28:52.852375 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9635 09:28:52.855979 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9636 09:28:52.859062 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9637 09:28:52.865962 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9638 09:28:52.869114 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9639 09:28:52.875494 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9640 09:28:52.879269 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9641 09:28:52.882299 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9642 09:28:52.888812 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9643 09:28:52.892509 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9644 09:28:52.898836 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9645 09:28:52.902122 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9646 09:28:52.908768 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9647 09:28:52.911885 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9648 09:28:52.915612 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9649 09:28:52.921712 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9650 09:28:52.925092 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9651 09:28:52.928844 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9652 09:28:52.935192 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9653 09:28:52.938724 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9654 09:28:52.944926 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9655 09:28:52.948130 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9656 09:28:52.951864 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9657 09:28:52.958584 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9658 09:28:52.961505 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9659 09:28:52.967894 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9660 09:28:52.971663 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9661 09:28:52.974707 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9662 09:28:52.981071 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9663 09:28:52.984915 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9664 09:28:52.991484 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9665 09:28:52.994473 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9666 09:28:52.997961 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9667 09:28:53.004623 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9668 09:28:53.007743 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9669 09:28:53.014546 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9670 09:28:53.017554 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9671 09:28:53.021138 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9672 09:28:53.027857 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9673 09:28:53.031007 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9674 09:28:53.037432 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9675 09:28:53.040546 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9676 09:28:53.044419 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9677 09:28:53.050781 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9678 09:28:53.054102 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9679 09:28:53.060730 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9680 09:28:53.063919 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9681 09:28:53.067099 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9682 09:28:53.073744 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9683 09:28:53.077053 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9684 09:28:53.083979 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9685 09:28:53.087261 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9686 09:28:53.093617 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9687 09:28:53.097366 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9688 09:28:53.100457 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9689 09:28:53.107005 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9690 09:28:53.110192 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9691 09:28:53.117089 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9692 09:28:53.120218 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9693 09:28:53.123344 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9694 09:28:53.130350 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9695 09:28:53.133389 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9696 09:28:53.140406 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9697 09:28:53.143578 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9698 09:28:53.149887 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9699 09:28:53.153702 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9700 09:28:53.156779 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9701 09:28:53.163239 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9702 09:28:53.166563 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9703 09:28:53.173487 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9704 09:28:53.176500 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9705 09:28:53.180159 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9706 09:28:53.186782 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9707 09:28:53.190189 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9708 09:28:53.196628 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9709 09:28:53.200026 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9710 09:28:53.203551 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9711 09:28:53.209814 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9712 09:28:53.213327 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9713 09:28:53.219969 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9714 09:28:53.223074 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9715 09:28:53.229877 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9716 09:28:53.233049 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9717 09:28:53.236629 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9718 09:28:53.243250 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9719 09:28:53.246408 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9720 09:28:53.252766 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9721 09:28:53.255899 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9722 09:28:53.262833 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9723 09:28:53.266234 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9724 09:28:53.269259 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9725 09:28:53.276043 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9726 09:28:53.279127 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9727 09:28:53.282433 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9728 09:28:53.286140 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9729 09:28:53.292195 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9730 09:28:53.296021 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9731 09:28:53.299081 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9732 09:28:53.305644 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9733 09:28:53.309109 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9734 09:28:53.312664 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9735 09:28:53.319021 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9736 09:28:53.322073 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9737 09:28:53.328902 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9738 09:28:53.332122 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9739 09:28:53.335313 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9740 09:28:53.342153 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9741 09:28:53.345194 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9742 09:28:53.348618 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9743 09:28:53.355579 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9744 09:28:53.358675 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9745 09:28:53.362418 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9746 09:28:53.368716 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9747 09:28:53.371931 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9748 09:28:53.378805 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9749 09:28:53.381666 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9750 09:28:53.385219 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9751 09:28:53.391678 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9752 09:28:53.395335 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9753 09:28:53.401512 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9754 09:28:53.405488 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9755 09:28:53.408510 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9756 09:28:53.415153 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9757 09:28:53.418642 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9758 09:28:53.421715 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9759 09:28:53.428017 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9760 09:28:53.431865 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9761 09:28:53.435003 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9762 09:28:53.441800 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9763 09:28:53.444957 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9764 09:28:53.448120 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9765 09:28:53.454626 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9766 09:28:53.458305 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9767 09:28:53.461645 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9768 09:28:53.464744 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9769 09:28:53.467920 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9770 09:28:53.474374 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9771 09:28:53.477649 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9772 09:28:53.480901 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9773 09:28:53.488216 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9774 09:28:53.491264 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9775 09:28:53.494267 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9776 09:28:53.497377 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9777 09:28:53.504423 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9778 09:28:53.507520 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9779 09:28:53.514314 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9780 09:28:53.517540 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9781 09:28:53.523618 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9782 09:28:53.527283 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9783 09:28:53.530454 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9784 09:28:53.536995 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9785 09:28:53.540146 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9786 09:28:53.546776 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9787 09:28:53.550281 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9788 09:28:53.553264 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9789 09:28:53.559920 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9790 09:28:53.563504 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9791 09:28:53.569826 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9792 09:28:53.573678 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9793 09:28:53.576798 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9794 09:28:53.583186 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9795 09:28:53.586409 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9796 09:28:53.593409 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9797 09:28:53.596429 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9798 09:28:53.603098 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9799 09:28:53.606281 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9800 09:28:53.613291 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9801 09:28:53.616333 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9802 09:28:53.619403 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9803 09:28:53.626364 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9804 09:28:53.629706 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9805 09:28:53.636274 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9806 09:28:53.639484 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9807 09:28:53.642547 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9808 09:28:53.649452 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9809 09:28:53.652373 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9810 09:28:53.659233 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9811 09:28:53.662533 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9812 09:28:53.665361 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9813 09:28:53.672083 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9814 09:28:53.675855 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9815 09:28:53.682331 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9816 09:28:53.685467 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9817 09:28:53.691847 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9818 09:28:53.695593 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9819 09:28:53.698694 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9820 09:28:53.705337 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9821 09:28:53.708212 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9822 09:28:53.715142 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9823 09:28:53.718361 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9824 09:28:53.724998 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9825 09:28:53.728187 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9826 09:28:53.731845 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9827 09:28:53.738373 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9828 09:28:53.741887 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9829 09:28:53.748066 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9830 09:28:53.751184 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9831 09:28:53.755013 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9832 09:28:53.761392 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9833 09:28:53.764519 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9834 09:28:53.771581 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9835 09:28:53.774501 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9836 09:28:53.777822 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9837 09:28:53.784488 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9838 09:28:53.787675 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9839 09:28:53.794603 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9840 09:28:53.797735 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9841 09:28:53.801389 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9842 09:28:53.807857 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9843 09:28:53.810990 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9844 09:28:53.817527 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9845 09:28:53.820878 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9846 09:28:53.827846 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9847 09:28:53.830914 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9848 09:28:53.834142 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9849 09:28:53.841038 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9850 09:28:53.844039 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9851 09:28:53.850596 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9852 09:28:53.854196 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9853 09:28:53.860404 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9854 09:28:53.863668 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9855 09:28:53.870687 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9856 09:28:53.873657 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9857 09:28:53.876729 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9858 09:28:53.883245 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9859 09:28:53.886889 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9860 09:28:53.893372 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9861 09:28:53.896802 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9862 09:28:53.903183 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9863 09:28:53.906860 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9864 09:28:53.913217 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9865 09:28:53.916400 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9866 09:28:53.919714 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9867 09:28:53.926302 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9868 09:28:53.929903 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9869 09:28:53.936579 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9870 09:28:53.940068 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9871 09:28:53.946193 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9872 09:28:53.949783 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9873 09:28:53.953274 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9874 09:28:53.959649 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9875 09:28:53.962752 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9876 09:28:53.969459 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9877 09:28:53.972616 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9878 09:28:53.979276 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9879 09:28:53.982418 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9880 09:28:53.989147 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9881 09:28:53.992511 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9882 09:28:53.995748 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9883 09:28:54.002451 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9884 09:28:54.005807 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9885 09:28:54.012479 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9886 09:28:54.015640 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9887 09:28:54.021860 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9888 09:28:54.025570 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9889 09:28:54.031637 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9890 09:28:54.035430 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9891 09:28:54.038505 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9892 09:28:54.044998 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9893 09:28:54.048237 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9894 09:28:54.055229 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9895 09:28:54.058083 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9896 09:28:54.064584 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9897 09:28:54.068238 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9898 09:28:54.071682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9899 09:28:54.077870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9900 09:28:54.081439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9901 09:28:54.088211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9902 09:28:54.091340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9903 09:28:54.097968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9904 09:28:54.101530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9905 09:28:54.107717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9906 09:28:54.111384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9907 09:28:54.117682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9908 09:28:54.121359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9909 09:28:54.127577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9910 09:28:54.130749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9911 09:28:54.137384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9912 09:28:54.141225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9913 09:28:54.147501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9914 09:28:54.150719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9915 09:28:54.157586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9916 09:28:54.161025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9917 09:28:54.167233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9918 09:28:54.170727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9919 09:28:54.177435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9920 09:28:54.180918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9921 09:28:54.187635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9922 09:28:54.190678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9923 09:28:54.197070 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9924 09:28:54.200624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9925 09:28:54.207331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9926 09:28:54.210326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9927 09:28:54.217178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9928 09:28:54.220306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9929 09:28:54.227408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9930 09:28:54.230588 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9931 09:28:54.233608 INFO: [APUAPC] vio 0
9932 09:28:54.237309 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9933 09:28:54.240233 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9934 09:28:54.243989 INFO: [APUAPC] D0_APC_0: 0x400510
9935 09:28:54.247072 INFO: [APUAPC] D0_APC_1: 0x0
9936 09:28:54.250224 INFO: [APUAPC] D0_APC_2: 0x1540
9937 09:28:54.253489 INFO: [APUAPC] D0_APC_3: 0x0
9938 09:28:54.257249 INFO: [APUAPC] D1_APC_0: 0xffffffff
9939 09:28:54.260445 INFO: [APUAPC] D1_APC_1: 0xffffffff
9940 09:28:54.263529 INFO: [APUAPC] D1_APC_2: 0x3fffff
9941 09:28:54.267133 INFO: [APUAPC] D1_APC_3: 0x0
9942 09:28:54.270100 INFO: [APUAPC] D2_APC_0: 0xffffffff
9943 09:28:54.273188 INFO: [APUAPC] D2_APC_1: 0xffffffff
9944 09:28:54.276872 INFO: [APUAPC] D2_APC_2: 0x3fffff
9945 09:28:54.280224 INFO: [APUAPC] D2_APC_3: 0x0
9946 09:28:54.283265 INFO: [APUAPC] D3_APC_0: 0xffffffff
9947 09:28:54.286434 INFO: [APUAPC] D3_APC_1: 0xffffffff
9948 09:28:54.290256 INFO: [APUAPC] D3_APC_2: 0x3fffff
9949 09:28:54.293126 INFO: [APUAPC] D3_APC_3: 0x0
9950 09:28:54.296536 INFO: [APUAPC] D4_APC_0: 0xffffffff
9951 09:28:54.299572 INFO: [APUAPC] D4_APC_1: 0xffffffff
9952 09:28:54.303298 INFO: [APUAPC] D4_APC_2: 0x3fffff
9953 09:28:54.306360 INFO: [APUAPC] D4_APC_3: 0x0
9954 09:28:54.309594 INFO: [APUAPC] D5_APC_0: 0xffffffff
9955 09:28:54.312723 INFO: [APUAPC] D5_APC_1: 0xffffffff
9956 09:28:54.316676 INFO: [APUAPC] D5_APC_2: 0x3fffff
9957 09:28:54.319790 INFO: [APUAPC] D5_APC_3: 0x0
9958 09:28:54.322957 INFO: [APUAPC] D6_APC_0: 0xffffffff
9959 09:28:54.326219 INFO: [APUAPC] D6_APC_1: 0xffffffff
9960 09:28:54.329309 INFO: [APUAPC] D6_APC_2: 0x3fffff
9961 09:28:54.332895 INFO: [APUAPC] D6_APC_3: 0x0
9962 09:28:54.336140 INFO: [APUAPC] D7_APC_0: 0xffffffff
9963 09:28:54.339284 INFO: [APUAPC] D7_APC_1: 0xffffffff
9964 09:28:54.342902 INFO: [APUAPC] D7_APC_2: 0x3fffff
9965 09:28:54.345940 INFO: [APUAPC] D7_APC_3: 0x0
9966 09:28:54.349139 INFO: [APUAPC] D8_APC_0: 0xffffffff
9967 09:28:54.353036 INFO: [APUAPC] D8_APC_1: 0xffffffff
9968 09:28:54.356310 INFO: [APUAPC] D8_APC_2: 0x3fffff
9969 09:28:54.359460 INFO: [APUAPC] D8_APC_3: 0x0
9970 09:28:54.362741 INFO: [APUAPC] D9_APC_0: 0xffffffff
9971 09:28:54.365872 INFO: [APUAPC] D9_APC_1: 0xffffffff
9972 09:28:54.369013 INFO: [APUAPC] D9_APC_2: 0x3fffff
9973 09:28:54.372587 INFO: [APUAPC] D9_APC_3: 0x0
9974 09:28:54.375722 INFO: [APUAPC] D10_APC_0: 0xffffffff
9975 09:28:54.378918 INFO: [APUAPC] D10_APC_1: 0xffffffff
9976 09:28:54.382602 INFO: [APUAPC] D10_APC_2: 0x3fffff
9977 09:28:54.385746 INFO: [APUAPC] D10_APC_3: 0x0
9978 09:28:54.389313 INFO: [APUAPC] D11_APC_0: 0xffffffff
9979 09:28:54.392401 INFO: [APUAPC] D11_APC_1: 0xffffffff
9980 09:28:54.395669 INFO: [APUAPC] D11_APC_2: 0x3fffff
9981 09:28:54.398930 INFO: [APUAPC] D11_APC_3: 0x0
9982 09:28:54.402513 INFO: [APUAPC] D12_APC_0: 0xffffffff
9983 09:28:54.405632 INFO: [APUAPC] D12_APC_1: 0xffffffff
9984 09:28:54.408629 INFO: [APUAPC] D12_APC_2: 0x3fffff
9985 09:28:54.412132 INFO: [APUAPC] D12_APC_3: 0x0
9986 09:28:54.415292 INFO: [APUAPC] D13_APC_0: 0xffffffff
9987 09:28:54.418877 INFO: [APUAPC] D13_APC_1: 0xffffffff
9988 09:28:54.421930 INFO: [APUAPC] D13_APC_2: 0x3fffff
9989 09:28:54.425794 INFO: [APUAPC] D13_APC_3: 0x0
9990 09:28:54.428839 INFO: [APUAPC] D14_APC_0: 0xffffffff
9991 09:28:54.432131 INFO: [APUAPC] D14_APC_1: 0xffffffff
9992 09:28:54.435303 INFO: [APUAPC] D14_APC_2: 0x3fffff
9993 09:28:54.438271 INFO: [APUAPC] D14_APC_3: 0x0
9994 09:28:54.441998 INFO: [APUAPC] D15_APC_0: 0xffffffff
9995 09:28:54.445190 INFO: [APUAPC] D15_APC_1: 0xffffffff
9996 09:28:54.448667 INFO: [APUAPC] D15_APC_2: 0x3fffff
9997 09:28:54.451829 INFO: [APUAPC] D15_APC_3: 0x0
9998 09:28:54.455003 INFO: [APUAPC] APC_CON: 0x4
9999 09:28:54.458132 INFO: [NOCDAPC] D0_APC_0: 0x0
10000 09:28:54.458250 INFO: [NOCDAPC] D0_APC_1: 0x0
10001 09:28:54.461963 INFO: [NOCDAPC] D1_APC_0: 0x0
10002 09:28:54.465218 INFO: [NOCDAPC] D1_APC_1: 0xfff
10003 09:28:54.468344 INFO: [NOCDAPC] D2_APC_0: 0x0
10004 09:28:54.471505 INFO: [NOCDAPC] D2_APC_1: 0xfff
10005 09:28:54.475189 INFO: [NOCDAPC] D3_APC_0: 0x0
10006 09:28:54.478400 INFO: [NOCDAPC] D3_APC_1: 0xfff
10007 09:28:54.481577 INFO: [NOCDAPC] D4_APC_0: 0x0
10008 09:28:54.484655 INFO: [NOCDAPC] D4_APC_1: 0xfff
10009 09:28:54.487904 INFO: [NOCDAPC] D5_APC_0: 0x0
10010 09:28:54.491613 INFO: [NOCDAPC] D5_APC_1: 0xfff
10011 09:28:54.491705 INFO: [NOCDAPC] D6_APC_0: 0x0
10012 09:28:54.494888 INFO: [NOCDAPC] D6_APC_1: 0xfff
10013 09:28:54.498016 INFO: [NOCDAPC] D7_APC_0: 0x0
10014 09:28:54.501424 INFO: [NOCDAPC] D7_APC_1: 0xfff
10015 09:28:54.504408 INFO: [NOCDAPC] D8_APC_0: 0x0
10016 09:28:54.507780 INFO: [NOCDAPC] D8_APC_1: 0xfff
10017 09:28:54.511516 INFO: [NOCDAPC] D9_APC_0: 0x0
10018 09:28:54.514819 INFO: [NOCDAPC] D9_APC_1: 0xfff
10019 09:28:54.518008 INFO: [NOCDAPC] D10_APC_0: 0x0
10020 09:28:54.521565 INFO: [NOCDAPC] D10_APC_1: 0xfff
10021 09:28:54.524351 INFO: [NOCDAPC] D11_APC_0: 0x0
10022 09:28:54.528219 INFO: [NOCDAPC] D11_APC_1: 0xfff
10023 09:28:54.528313 INFO: [NOCDAPC] D12_APC_0: 0x0
10024 09:28:54.531516 INFO: [NOCDAPC] D12_APC_1: 0xfff
10025 09:28:54.534838 INFO: [NOCDAPC] D13_APC_0: 0x0
10026 09:28:54.537829 INFO: [NOCDAPC] D13_APC_1: 0xfff
10027 09:28:54.541323 INFO: [NOCDAPC] D14_APC_0: 0x0
10028 09:28:54.544393 INFO: [NOCDAPC] D14_APC_1: 0xfff
10029 09:28:54.548052 INFO: [NOCDAPC] D15_APC_0: 0x0
10030 09:28:54.551011 INFO: [NOCDAPC] D15_APC_1: 0xfff
10031 09:28:54.554488 INFO: [NOCDAPC] APC_CON: 0x4
10032 09:28:54.557676 INFO: [APUAPC] set_apusys_apc done
10033 09:28:54.560837 INFO: [DEVAPC] devapc_init done
10034 09:28:54.564115 INFO: GICv3 without legacy support detected.
10035 09:28:54.567890 INFO: ARM GICv3 driver initialized in EL3
10036 09:28:54.571095 INFO: Maximum SPI INTID supported: 639
10037 09:28:54.577401 INFO: BL31: Initializing runtime services
10038 09:28:54.580922 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10039 09:28:54.584130 INFO: SPM: enable CPC mode
10040 09:28:54.590906 INFO: mcdi ready for mcusys-off-idle and system suspend
10041 09:28:54.593982 INFO: BL31: Preparing for EL3 exit to normal world
10042 09:28:54.597141 INFO: Entry point address = 0x80000000
10043 09:28:54.600344 INFO: SPSR = 0x8
10044 09:28:54.606013
10045 09:28:54.606090
10046 09:28:54.606150
10047 09:28:54.609847 Starting depthcharge on Spherion...
10048 09:28:54.609918
10049 09:28:54.609975 Wipe memory regions:
10050 09:28:54.610030
10051 09:28:54.610690 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10052 09:28:54.610818 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10053 09:28:54.610920 Setting prompt string to ['asurada:']
10054 09:28:54.611026 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10055 09:28:54.612813 [0x00000040000000, 0x00000054600000)
10056 09:28:54.734894
10057 09:28:54.735028 [0x00000054660000, 0x00000080000000)
10058 09:28:54.995084
10059 09:28:54.995201 [0x000000821a7280, 0x000000ffe64000)
10060 09:28:55.738907
10061 09:28:55.739024 [0x00000100000000, 0x00000240000000)
10062 09:28:57.625202
10063 09:28:57.628264 Initializing XHCI USB controller at 0x11200000.
10064 09:28:58.667258
10065 09:28:58.670305 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10066 09:28:58.670710
10067 09:28:58.671020
10068 09:28:58.671732 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10070 09:28:58.772817 asurada: tftpboot 192.168.201.1 14407656/tftp-deploy-_tdhyqxs/kernel/image.itb 14407656/tftp-deploy-_tdhyqxs/kernel/cmdline
10071 09:28:58.773422 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 09:28:58.773814 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10073 09:28:58.778722 tftpboot 192.168.201.1 14407656/tftp-deploy-_tdhyqxs/kernel/image.itp-deploy-_tdhyqxs/kernel/cmdline
10074 09:28:58.779118
10075 09:28:58.779422 Waiting for link
10076 09:28:58.936813
10077 09:28:58.937303 R8152: Initializing
10078 09:28:58.937614
10079 09:28:58.940306 Version 6 (ocp_data = 5c30)
10080 09:28:58.940738
10081 09:28:58.943403 R8152: Done initializing
10082 09:28:58.943793
10083 09:28:58.944099 Adding net device
10084 09:29:00.972469
10085 09:29:00.973083 done.
10086 09:29:00.973522
10087 09:29:00.973834 MAC: 00:24:32:30:78:ff
10088 09:29:00.974115
10089 09:29:00.975376 Sending DHCP discover... done.
10090 09:29:00.975896
10091 09:29:00.978924 Waiting for reply... done.
10092 09:29:00.979370
10093 09:29:00.982020 Sending DHCP request... done.
10094 09:29:00.982413
10095 09:29:00.985244 Waiting for reply... done.
10096 09:29:00.985634
10097 09:29:00.985939 My ip is 192.168.201.21
10098 09:29:00.986220
10099 09:29:00.988270 The DHCP server ip is 192.168.201.1
10100 09:29:00.988703
10101 09:29:00.995428 TFTP server IP predefined by user: 192.168.201.1
10102 09:29:00.995823
10103 09:29:01.001422 Bootfile predefined by user: 14407656/tftp-deploy-_tdhyqxs/kernel/image.itb
10104 09:29:01.001817
10105 09:29:01.005090 Sending tftp read request... done.
10106 09:29:01.005621
10107 09:29:01.012517 Waiting for the transfer...
10108 09:29:01.013141
10109 09:29:01.578296 00000000 ################################################################
10110 09:29:01.578412
10111 09:29:02.139725 00080000 ################################################################
10112 09:29:02.139836
10113 09:29:02.697899 00100000 ################################################################
10114 09:29:02.698029
10115 09:29:03.252151 00180000 ################################################################
10116 09:29:03.252275
10117 09:29:03.801756 00200000 ################################################################
10118 09:29:03.801865
10119 09:29:04.402061 00280000 ################################################################
10120 09:29:04.402492
10121 09:29:05.018838 00300000 ################################################################
10122 09:29:05.018952
10123 09:29:05.596652 00380000 ################################################################
10124 09:29:05.596766
10125 09:29:06.233743 00400000 ################################################################
10126 09:29:06.233996
10127 09:29:06.830620 00480000 ################################################################
10128 09:29:06.830754
10129 09:29:07.387031 00500000 ################################################################
10130 09:29:07.387165
10131 09:29:07.932156 00580000 ################################################################
10132 09:29:07.932273
10133 09:29:08.487869 00600000 ################################################################
10134 09:29:08.487986
10135 09:29:09.055539 00680000 ################################################################
10136 09:29:09.055673
10137 09:29:09.624881 00700000 ################################################################
10138 09:29:09.625020
10139 09:29:10.191763 00780000 ################################################################
10140 09:29:10.191906
10141 09:29:10.745526 00800000 ################################################################
10142 09:29:10.745639
10143 09:29:11.294503 00880000 ################################################################
10144 09:29:11.294623
10145 09:29:11.840107 00900000 ################################################################
10146 09:29:11.840237
10147 09:29:12.418191 00980000 ################################################################
10148 09:29:12.418308
10149 09:29:12.985177 00a00000 ################################################################
10150 09:29:12.985297
10151 09:29:13.548776 00a80000 ################################################################
10152 09:29:13.548892
10153 09:29:14.091036 00b00000 ################################################################
10154 09:29:14.091155
10155 09:29:14.636682 00b80000 ################################################################
10156 09:29:14.636812
10157 09:29:15.177694 00c00000 ################################################################
10158 09:29:15.177807
10159 09:29:15.722352 00c80000 ################################################################
10160 09:29:15.722480
10161 09:29:16.260665 00d00000 ################################################################
10162 09:29:16.260796
10163 09:29:16.785045 00d80000 ################################################################
10164 09:29:16.785174
10165 09:29:17.322472 00e00000 ################################################################
10166 09:29:17.322606
10167 09:29:17.859879 00e80000 ################################################################
10168 09:29:17.859998
10169 09:29:18.405627 00f00000 ################################################################
10170 09:29:18.405758
10171 09:29:18.955699 00f80000 ################################################################
10172 09:29:18.955821
10173 09:29:19.482343 01000000 ################################################################
10174 09:29:19.482471
10175 09:29:20.046997 01080000 ################################################################
10176 09:29:20.047149
10177 09:29:20.587180 01100000 ################################################################
10178 09:29:20.587321
10179 09:29:21.134473 01180000 ################################################################
10180 09:29:21.134591
10181 09:29:21.690045 01200000 ################################################################
10182 09:29:21.690168
10183 09:29:22.233071 01280000 ################################################################
10184 09:29:22.233193
10185 09:29:22.765362 01300000 ################################################################
10186 09:29:22.765487
10187 09:29:23.281482 01380000 ################################################################
10188 09:29:23.281655
10189 09:29:23.819146 01400000 ################################################################
10190 09:29:23.819294
10191 09:29:24.334123 01480000 ################################################################
10192 09:29:24.334240
10193 09:29:24.855221 01500000 ################################################################
10194 09:29:24.855356
10195 09:29:25.378318 01580000 ################################################################
10196 09:29:25.378479
10197 09:29:25.894701 01600000 ################################################################
10198 09:29:25.894844
10199 09:29:26.411695 01680000 ################################################################
10200 09:29:26.411842
10201 09:29:26.930225 01700000 ################################################################
10202 09:29:26.930374
10203 09:29:27.463649 01780000 ################################################################
10204 09:29:27.463779
10205 09:29:28.015369 01800000 ################################################################
10206 09:29:28.015493
10207 09:29:28.532604 01880000 ################################################################
10208 09:29:28.532760
10209 09:29:29.049132 01900000 ################################################################
10210 09:29:29.049277
10211 09:29:29.566298 01980000 ################################################################
10212 09:29:29.566433
10213 09:29:30.085011 01a00000 ################################################################
10214 09:29:30.085137
10215 09:29:30.605539 01a80000 ################################################################
10216 09:29:30.605687
10217 09:29:31.124567 01b00000 ################################################################
10218 09:29:31.124729
10219 09:29:31.672762 01b80000 ################################################################
10220 09:29:31.672911
10221 09:29:32.186828 01c00000 ################################################################
10222 09:29:32.186961
10223 09:29:32.711271 01c80000 ################################################################
10224 09:29:32.711411
10225 09:29:33.241944 01d00000 ################################################################
10226 09:29:33.242082
10227 09:29:33.763936 01d80000 ################################################################
10228 09:29:33.764063
10229 09:29:34.284446 01e00000 ################################################################
10230 09:29:34.284604
10231 09:29:34.792342 01e80000 ################################################################
10232 09:29:34.792475
10233 09:29:35.304325 01f00000 ################################################################
10234 09:29:35.304489
10235 09:29:35.834779 01f80000 ################################################################
10236 09:29:35.834918
10237 09:29:36.368343 02000000 ################################################################
10238 09:29:36.368451
10239 09:29:36.880043 02080000 ################################################################
10240 09:29:36.880180
10241 09:29:37.398162 02100000 ################################################################
10242 09:29:37.398298
10243 09:29:37.924727 02180000 ################################################################
10244 09:29:37.924837
10245 09:29:38.456822 02200000 ################################################################
10246 09:29:38.456934
10247 09:29:39.054240 02280000 ################################################################
10248 09:29:39.054773
10249 09:29:39.656147 02300000 ################################################################
10250 09:29:39.656262
10251 09:29:40.285949 02380000 ################################################################
10252 09:29:40.286069
10253 09:29:40.930201 02400000 ################################################################
10254 09:29:40.930339
10255 09:29:41.485999 02480000 ################################################################
10256 09:29:41.486114
10257 09:29:42.043337 02500000 ################################################################
10258 09:29:42.043476
10259 09:29:42.593617 02580000 ################################################################
10260 09:29:42.593748
10261 09:29:43.153658 02600000 ################################################################
10262 09:29:43.153796
10263 09:29:43.721988 02680000 ################################################################
10264 09:29:43.722126
10265 09:29:44.274088 02700000 ################################################################
10266 09:29:44.274202
10267 09:29:44.840349 02780000 ################################################################
10268 09:29:44.840459
10269 09:29:45.421929 02800000 ################################################################
10270 09:29:45.422062
10271 09:29:45.972538 02880000 ################################################################
10272 09:29:45.972699
10273 09:29:46.529439 02900000 ################################################################
10274 09:29:46.529552
10275 09:29:47.122309 02980000 ################################################################
10276 09:29:47.122434
10277 09:29:47.651355 02a00000 ################################################################
10278 09:29:47.651485
10279 09:29:48.180716 02a80000 ################################################################
10280 09:29:48.180864
10281 09:29:48.709284 02b00000 ################################################################
10282 09:29:48.709421
10283 09:29:49.253623 02b80000 ################################################################
10284 09:29:49.253759
10285 09:29:49.773948 02c00000 ################################################################
10286 09:29:49.774073
10287 09:29:50.296676 02c80000 ################################################################
10288 09:29:50.296811
10289 09:29:50.838688 02d00000 ################################################################
10290 09:29:50.838837
10291 09:29:51.359274 02d80000 ################################################################
10292 09:29:51.359422
10293 09:29:51.895757 02e00000 ################################################################
10294 09:29:51.895892
10295 09:29:52.445459 02e80000 ################################################################
10296 09:29:52.445587
10297 09:29:52.988782 02f00000 ################################################################
10298 09:29:52.988901
10299 09:29:53.511818 02f80000 ################################################################
10300 09:29:53.511941
10301 09:29:54.037517 03000000 ################################################################
10302 09:29:54.037664
10303 09:29:54.565061 03080000 ################################################################
10304 09:29:54.565183
10305 09:29:55.102010 03100000 ################################################################
10306 09:29:55.102164
10307 09:29:55.622212 03180000 ################################################################
10308 09:29:55.622337
10309 09:29:56.152481 03200000 ################################################################
10310 09:29:56.152620
10311 09:29:56.675993 03280000 ################################################################
10312 09:29:56.676110
10313 09:29:57.209697 03300000 ################################################################
10314 09:29:57.209821
10315 09:29:57.734387 03380000 ################################################################
10316 09:29:57.734501
10317 09:29:58.260256 03400000 ################################################################
10318 09:29:58.260375
10319 09:29:58.775709 03480000 ################################################################
10320 09:29:58.775879
10321 09:29:59.288586 03500000 ################################################################
10322 09:29:59.288738
10323 09:29:59.802493 03580000 ################################################################
10324 09:29:59.802609
10325 09:30:00.322608 03600000 ################################################################
10326 09:30:00.322790
10327 09:30:00.839413 03680000 ################################################################
10328 09:30:00.839538
10329 09:30:01.353479 03700000 ################################################################
10330 09:30:01.353625
10331 09:30:01.865417 03780000 ################################################################
10332 09:30:01.865546
10333 09:30:02.389517 03800000 ################################################################
10334 09:30:02.389630
10335 09:30:02.988754 03880000 ################################################################
10336 09:30:02.989242
10337 09:30:03.606550 03900000 ################################################################
10338 09:30:03.606705
10339 09:30:04.148190 03980000 ################################################################
10340 09:30:04.148303
10341 09:30:04.683157 03a00000 ################################################################
10342 09:30:04.683271
10343 09:30:05.236003 03a80000 ################################################################
10344 09:30:05.236112
10345 09:30:05.799553 03b00000 ################################################################
10346 09:30:05.799665
10347 09:30:06.352325 03b80000 ################################################################
10348 09:30:06.352440
10349 09:30:06.902279 03c00000 ################################################################
10350 09:30:06.902390
10351 09:30:07.435376 03c80000 ################################################################
10352 09:30:07.435487
10353 09:30:07.968254 03d00000 ################################################################
10354 09:30:07.968387
10355 09:30:08.498641 03d80000 ################################################################
10356 09:30:08.498757
10357 09:30:09.071421 03e00000 ################################################################
10358 09:30:09.071556
10359 09:30:09.632959 03e80000 ################################################################
10360 09:30:09.633074
10361 09:30:10.199616 03f00000 ################################################################
10362 09:30:10.199732
10363 09:30:10.740370 03f80000 ################################################################
10364 09:30:10.740509
10365 09:30:11.283668 04000000 ################################################################
10366 09:30:11.283799
10367 09:30:11.817520 04080000 ################################################################
10368 09:30:11.817636
10369 09:30:12.360785 04100000 ################################################################
10370 09:30:12.360918
10371 09:30:12.906314 04180000 ################################################################
10372 09:30:12.906473
10373 09:30:13.444069 04200000 ################################################################
10374 09:30:13.444277
10375 09:30:13.980194 04280000 ################################################################
10376 09:30:13.980316
10377 09:30:14.504510 04300000 ################################################################
10378 09:30:14.504637
10379 09:30:15.033607 04380000 ################################################################
10380 09:30:15.033723
10381 09:30:15.576961 04400000 ################################################################
10382 09:30:15.577120
10383 09:30:16.122033 04480000 ################################################################
10384 09:30:16.122174
10385 09:30:16.655414 04500000 ################################################################
10386 09:30:16.655531
10387 09:30:17.185789 04580000 ################################################################
10388 09:30:17.185912
10389 09:30:17.715577 04600000 ################################################################
10390 09:30:17.715714
10391 09:30:17.997433 04680000 ################################## done.
10392 09:30:17.997586
10393 09:30:18.000553 The bootfile was 74199174 bytes long.
10394 09:30:18.000664
10395 09:30:18.004173 Sending tftp read request... done.
10396 09:30:18.004274
10397 09:30:18.004360 Waiting for the transfer...
10398 09:30:18.004443
10399 09:30:18.007356 00000000 # done.
10400 09:30:18.007456
10401 09:30:18.014108 Command line loaded dynamically from TFTP file: 14407656/tftp-deploy-_tdhyqxs/kernel/cmdline
10402 09:30:18.014222
10403 09:30:18.027248 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10404 09:30:18.027363
10405 09:30:18.030704 Loading FIT.
10406 09:30:18.030804
10407 09:30:18.033676 Image ramdisk-1 has 61023162 bytes.
10408 09:30:18.033778
10409 09:30:18.037092 Image fdt-1 has 47258 bytes.
10410 09:30:18.037189
10411 09:30:18.037274 Image kernel-1 has 13126726 bytes.
10412 09:30:18.040371
10413 09:30:18.047026 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10414 09:30:18.047131
10415 09:30:18.066867 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10416 09:30:18.066998
10417 09:30:18.069953 Choosing best match conf-1 for compat google,spherion-rev2.
10418 09:30:18.074859
10419 09:30:18.079140 Connected to device vid:did:rid of 1ae0:0028:00
10420 09:30:18.087493
10421 09:30:18.090460 tpm_get_response: command 0x17b, return code 0x0
10422 09:30:18.090561
10423 09:30:18.094188 ec_init: CrosEC protocol v3 supported (256, 248)
10424 09:30:18.097922
10425 09:30:18.101196 tpm_cleanup: add release locality here.
10426 09:30:18.101275
10427 09:30:18.101336 Shutting down all USB controllers.
10428 09:30:18.104895
10429 09:30:18.104997 Removing current net device
10430 09:30:18.105088
10431 09:30:18.111483 Exiting depthcharge with code 4 at timestamp: 112858008
10432 09:30:18.111596
10433 09:30:18.114625 LZMA decompressing kernel-1 to 0x821a6718
10434 09:30:18.114728
10435 09:30:18.118153 LZMA decompressing kernel-1 to 0x40000000
10436 09:30:19.736025
10437 09:30:19.736176 jumping to kernel
10438 09:30:19.737284 end: 2.2.4 bootloader-commands (duration 00:01:25) [common]
10439 09:30:19.737409 start: 2.2.5 auto-login-action (timeout 00:03:01) [common]
10440 09:30:19.737503 Setting prompt string to ['Linux version [0-9]']
10441 09:30:19.737593 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10442 09:30:19.737693 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10443 09:30:19.817644
10444 09:30:19.821048 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10445 09:30:19.824322 start: 2.2.5.1 login-action (timeout 00:03:01) [common]
10446 09:30:19.824440 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10447 09:30:19.824535 Setting prompt string to []
10448 09:30:19.824638 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10449 09:30:19.824759 Using line separator: #'\n'#
10450 09:30:19.824814 No login prompt set.
10451 09:30:19.824873 Parsing kernel messages
10452 09:30:19.824948 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10453 09:30:19.825071 [login-action] Waiting for messages, (timeout 00:03:01)
10454 09:30:19.825134 Waiting using forced prompt support (timeout 00:01:31)
10455 09:30:19.844147 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
10456 09:30:19.847866 [ 0.000000] random: crng init done
10457 09:30:19.854007 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10458 09:30:19.857195 [ 0.000000] efi: UEFI not found.
10459 09:30:19.863742 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10460 09:30:19.870660 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10461 09:30:19.880460 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10462 09:30:19.890346 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10463 09:30:19.897093 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10464 09:30:19.903972 [ 0.000000] printk: bootconsole [mtk8250] enabled
10465 09:30:19.910516 [ 0.000000] NUMA: No NUMA configuration found
10466 09:30:19.917200 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10467 09:30:19.920203 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10468 09:30:19.923267 [ 0.000000] Zone ranges:
10469 09:30:19.930102 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10470 09:30:19.933213 [ 0.000000] DMA32 empty
10471 09:30:19.939953 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10472 09:30:19.943157 [ 0.000000] Movable zone start for each node
10473 09:30:19.947034 [ 0.000000] Early memory node ranges
10474 09:30:19.953171 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10475 09:30:19.959880 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10476 09:30:19.966347 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10477 09:30:19.972998 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10478 09:30:19.979682 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10479 09:30:19.986472 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10480 09:30:20.042286 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10481 09:30:20.049110 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10482 09:30:20.055960 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10483 09:30:20.059014 [ 0.000000] psci: probing for conduit method from DT.
10484 09:30:20.065841 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10485 09:30:20.069032 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10486 09:30:20.075357 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10487 09:30:20.078840 [ 0.000000] psci: SMC Calling Convention v1.2
10488 09:30:20.085491 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10489 09:30:20.089143 [ 0.000000] Detected VIPT I-cache on CPU0
10490 09:30:20.095382 [ 0.000000] CPU features: detected: GIC system register CPU interface
10491 09:30:20.102146 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10492 09:30:20.108888 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10493 09:30:20.115380 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10494 09:30:20.124981 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10495 09:30:20.131862 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10496 09:30:20.134992 [ 0.000000] alternatives: applying boot alternatives
10497 09:30:20.141672 [ 0.000000] Fallback order for Node 0: 0
10498 09:30:20.148276 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10499 09:30:20.151354 [ 0.000000] Policy zone: Normal
10500 09:30:20.165026 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10501 09:30:20.174413 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10502 09:30:20.186564 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10503 09:30:20.196574 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10504 09:30:20.203212 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10505 09:30:20.206213 <6>[ 0.000000] software IO TLB: area num 8.
10506 09:30:20.262862 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10507 09:30:20.412078 <6>[ 0.000000] Memory: 7904468K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 448300K reserved, 32768K cma-reserved)
10508 09:30:20.418836 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10509 09:30:20.425114 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10510 09:30:20.428169 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10511 09:30:20.434888 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10512 09:30:20.441937 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10513 09:30:20.445007 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10514 09:30:20.455052 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10515 09:30:20.461828 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10516 09:30:20.468070 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10517 09:30:20.474720 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10518 09:30:20.477847 <6>[ 0.000000] GICv3: 608 SPIs implemented
10519 09:30:20.481481 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10520 09:30:20.488063 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10521 09:30:20.491287 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10522 09:30:20.498191 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10523 09:30:20.511356 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10524 09:30:20.521146 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10525 09:30:20.531063 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10526 09:30:20.538489 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10527 09:30:20.551872 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10528 09:30:20.558554 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10529 09:30:20.565182 <6>[ 0.009178] Console: colour dummy device 80x25
10530 09:30:20.574672 <6>[ 0.013936] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10531 09:30:20.581205 <6>[ 0.024377] pid_max: default: 32768 minimum: 301
10532 09:30:20.585009 <6>[ 0.029249] LSM: Security Framework initializing
10533 09:30:20.591260 <6>[ 0.034187] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10534 09:30:20.601390 <6>[ 0.042002] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10535 09:30:20.611053 <6>[ 0.051422] cblist_init_generic: Setting adjustable number of callback queues.
10536 09:30:20.614502 <6>[ 0.058864] cblist_init_generic: Setting shift to 3 and lim to 1.
10537 09:30:20.624189 <6>[ 0.065241] cblist_init_generic: Setting adjustable number of callback queues.
10538 09:30:20.631034 <6>[ 0.072668] cblist_init_generic: Setting shift to 3 and lim to 1.
10539 09:30:20.634121 <6>[ 0.079109] rcu: Hierarchical SRCU implementation.
10540 09:30:20.640932 <6>[ 0.084155] rcu: Max phase no-delay instances is 1000.
10541 09:30:20.647616 <6>[ 0.091218] EFI services will not be available.
10542 09:30:20.650578 <6>[ 0.096177] smp: Bringing up secondary CPUs ...
10543 09:30:20.659560 <6>[ 0.101229] Detected VIPT I-cache on CPU1
10544 09:30:20.666201 <6>[ 0.101302] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10545 09:30:20.672402 <6>[ 0.101334] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10546 09:30:20.675621 <6>[ 0.101666] Detected VIPT I-cache on CPU2
10547 09:30:20.686137 <6>[ 0.101716] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10548 09:30:20.692295 <6>[ 0.101733] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10549 09:30:20.696041 <6>[ 0.101989] Detected VIPT I-cache on CPU3
10550 09:30:20.702111 <6>[ 0.102036] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10551 09:30:20.708854 <6>[ 0.102050] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10552 09:30:20.712465 <6>[ 0.102351] CPU features: detected: Spectre-v4
10553 09:30:20.718980 <6>[ 0.102357] CPU features: detected: Spectre-BHB
10554 09:30:20.722368 <6>[ 0.102362] Detected PIPT I-cache on CPU4
10555 09:30:20.728599 <6>[ 0.102423] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10556 09:30:20.735703 <6>[ 0.102439] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10557 09:30:20.741802 <6>[ 0.102729] Detected PIPT I-cache on CPU5
10558 09:30:20.748516 <6>[ 0.102791] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10559 09:30:20.755464 <6>[ 0.102807] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10560 09:30:20.758597 <6>[ 0.103086] Detected PIPT I-cache on CPU6
10561 09:30:20.765306 <6>[ 0.103150] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10562 09:30:20.771712 <6>[ 0.103167] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10563 09:30:20.778564 <6>[ 0.103464] Detected PIPT I-cache on CPU7
10564 09:30:20.785005 <6>[ 0.103529] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10565 09:30:20.791879 <6>[ 0.103545] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10566 09:30:20.794824 <6>[ 0.103592] smp: Brought up 1 node, 8 CPUs
10567 09:30:20.801671 <6>[ 0.244842] SMP: Total of 8 processors activated.
10568 09:30:20.804601 <6>[ 0.249793] CPU features: detected: 32-bit EL0 Support
10569 09:30:20.815042 <6>[ 0.255190] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10570 09:30:20.821274 <6>[ 0.263990] CPU features: detected: Common not Private translations
10571 09:30:20.828122 <6>[ 0.270466] CPU features: detected: CRC32 instructions
10572 09:30:20.831575 <6>[ 0.275817] CPU features: detected: RCpc load-acquire (LDAPR)
10573 09:30:20.837905 <6>[ 0.281777] CPU features: detected: LSE atomic instructions
10574 09:30:20.844509 <6>[ 0.287557] CPU features: detected: Privileged Access Never
10575 09:30:20.851281 <6>[ 0.293344] CPU features: detected: RAS Extension Support
10576 09:30:20.857610 <6>[ 0.298955] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10577 09:30:20.861335 <6>[ 0.306220] CPU: All CPU(s) started at EL2
10578 09:30:20.867452 <6>[ 0.310537] alternatives: applying system-wide alternatives
10579 09:30:20.877170 <6>[ 0.321376] devtmpfs: initialized
10580 09:30:20.892227 <6>[ 0.330148] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10581 09:30:20.898829 <6>[ 0.340107] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10582 09:30:20.905458 <6>[ 0.348080] pinctrl core: initialized pinctrl subsystem
10583 09:30:20.909050 <6>[ 0.354748] DMI not present or invalid.
10584 09:30:20.915698 <6>[ 0.359161] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10585 09:30:20.925551 <6>[ 0.366017] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10586 09:30:20.931974 <6>[ 0.373609] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10587 09:30:20.941764 <6>[ 0.381827] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10588 09:30:20.945459 <6>[ 0.390071] audit: initializing netlink subsys (disabled)
10589 09:30:20.955241 <5>[ 0.395765] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10590 09:30:20.962074 <6>[ 0.396473] thermal_sys: Registered thermal governor 'step_wise'
10591 09:30:20.968266 <6>[ 0.403732] thermal_sys: Registered thermal governor 'power_allocator'
10592 09:30:20.971906 <6>[ 0.409987] cpuidle: using governor menu
10593 09:30:20.978089 <6>[ 0.420946] NET: Registered PF_QIPCRTR protocol family
10594 09:30:20.984904 <6>[ 0.426420] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10595 09:30:20.991693 <6>[ 0.433525] ASID allocator initialised with 32768 entries
10596 09:30:20.994530 <6>[ 0.440092] Serial: AMBA PL011 UART driver
10597 09:30:21.004916 <4>[ 0.448897] Trying to register duplicate clock ID: 134
10598 09:30:21.062957 <6>[ 0.510387] KASLR enabled
10599 09:30:21.076958 <6>[ 0.518065] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10600 09:30:21.083842 <6>[ 0.525081] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10601 09:30:21.090630 <6>[ 0.531571] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10602 09:30:21.096861 <6>[ 0.538578] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10603 09:30:21.103950 <6>[ 0.545064] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10604 09:30:21.110165 <6>[ 0.552069] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10605 09:30:21.116627 <6>[ 0.558555] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10606 09:30:21.123061 <6>[ 0.565561] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10607 09:30:21.126585 <6>[ 0.573073] ACPI: Interpreter disabled.
10608 09:30:21.135519 <6>[ 0.579483] iommu: Default domain type: Translated
10609 09:30:21.141706 <6>[ 0.584595] iommu: DMA domain TLB invalidation policy: strict mode
10610 09:30:21.145371 <5>[ 0.591253] SCSI subsystem initialized
10611 09:30:21.151470 <6>[ 0.595420] usbcore: registered new interface driver usbfs
10612 09:30:21.158000 <6>[ 0.601152] usbcore: registered new interface driver hub
10613 09:30:21.161766 <6>[ 0.606704] usbcore: registered new device driver usb
10614 09:30:21.168493 <6>[ 0.612793] pps_core: LinuxPPS API ver. 1 registered
10615 09:30:21.178406 <6>[ 0.617987] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10616 09:30:21.181401 <6>[ 0.627332] PTP clock support registered
10617 09:30:21.185169 <6>[ 0.631574] EDAC MC: Ver: 3.0.0
10618 09:30:21.192525 <6>[ 0.636706] FPGA manager framework
10619 09:30:21.198892 <6>[ 0.640391] Advanced Linux Sound Architecture Driver Initialized.
10620 09:30:21.202528 <6>[ 0.647161] vgaarb: loaded
10621 09:30:21.208954 <6>[ 0.650311] clocksource: Switched to clocksource arch_sys_counter
10622 09:30:21.212044 <5>[ 0.656741] VFS: Disk quotas dquot_6.6.0
10623 09:30:21.219110 <6>[ 0.660928] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10624 09:30:21.222160 <6>[ 0.668113] pnp: PnP ACPI: disabled
10625 09:30:21.230511 <6>[ 0.674771] NET: Registered PF_INET protocol family
10626 09:30:21.240402 <6>[ 0.680354] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10627 09:30:21.252061 <6>[ 0.692657] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10628 09:30:21.261540 <6>[ 0.701471] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10629 09:30:21.268406 <6>[ 0.709439] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10630 09:30:21.278287 <6>[ 0.718139] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10631 09:30:21.284493 <6>[ 0.727891] TCP: Hash tables configured (established 65536 bind 65536)
10632 09:30:21.291096 <6>[ 0.734752] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10633 09:30:21.300955 <6>[ 0.741955] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10634 09:30:21.307608 <6>[ 0.749655] NET: Registered PF_UNIX/PF_LOCAL protocol family
10635 09:30:21.314236 <6>[ 0.755802] RPC: Registered named UNIX socket transport module.
10636 09:30:21.317967 <6>[ 0.761957] RPC: Registered udp transport module.
10637 09:30:21.321016 <6>[ 0.766889] RPC: Registered tcp transport module.
10638 09:30:21.327865 <6>[ 0.771821] RPC: Registered tcp NFSv4.1 backchannel transport module.
10639 09:30:21.333874 <6>[ 0.778488] PCI: CLS 0 bytes, default 64
10640 09:30:21.337506 <6>[ 0.782879] Unpacking initramfs...
10641 09:30:21.343952 <6>[ 0.786608] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10642 09:30:21.354090 <6>[ 0.795239] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10643 09:30:21.361115 <6>[ 0.804026] kvm [1]: IPA Size Limit: 40 bits
10644 09:30:21.363961 <6>[ 0.808554] kvm [1]: GICv3: no GICV resource entry
10645 09:30:21.367461 <6>[ 0.813576] kvm [1]: disabling GICv2 emulation
10646 09:30:21.374236 <6>[ 0.818260] kvm [1]: GIC system register CPU interface enabled
10647 09:30:21.380534 <6>[ 0.824425] kvm [1]: vgic interrupt IRQ18
10648 09:30:21.387156 <6>[ 0.830362] kvm [1]: VHE mode initialized successfully
10649 09:30:21.390672 <5>[ 0.836744] Initialise system trusted keyrings
10650 09:30:21.400420 <6>[ 0.841573] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10651 09:30:21.407232 <6>[ 0.851454] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10652 09:30:21.414082 <5>[ 0.857871] NFS: Registering the id_resolver key type
10653 09:30:21.417073 <5>[ 0.863174] Key type id_resolver registered
10654 09:30:21.423610 <5>[ 0.867590] Key type id_legacy registered
10655 09:30:21.430523 <6>[ 0.871869] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10656 09:30:21.436667 <6>[ 0.878790] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10657 09:30:21.443567 <6>[ 0.886493] 9p: Installing v9fs 9p2000 file system support
10658 09:30:21.481405 <5>[ 0.925735] Key type asymmetric registered
10659 09:30:21.484419 <5>[ 0.930066] Asymmetric key parser 'x509' registered
10660 09:30:21.494843 <6>[ 0.935225] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10661 09:30:21.497940 <6>[ 0.942845] io scheduler mq-deadline registered
10662 09:30:21.501009 <6>[ 0.947634] io scheduler kyber registered
10663 09:30:21.520024 <6>[ 0.964538] EINJ: ACPI disabled.
10664 09:30:21.552432 <4>[ 0.990226] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10665 09:30:21.562470 <4>[ 1.000831] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10666 09:30:21.577192 <6>[ 1.021485] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10667 09:30:21.584812 <6>[ 1.029394] printk: console [ttyS0] disabled
10668 09:30:21.613202 <6>[ 1.054026] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10669 09:30:21.619514 <6>[ 1.063505] printk: console [ttyS0] enabled
10670 09:30:21.622719 <6>[ 1.063505] printk: console [ttyS0] enabled
10671 09:30:21.629460 <6>[ 1.072398] printk: bootconsole [mtk8250] disabled
10672 09:30:21.633042 <6>[ 1.072398] printk: bootconsole [mtk8250] disabled
10673 09:30:21.639712 <6>[ 1.083433] SuperH (H)SCI(F) driver initialized
10674 09:30:21.642784 <6>[ 1.088718] msm_serial: driver initialized
10675 09:30:21.656549 <6>[ 1.097588] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10676 09:30:21.666841 <6>[ 1.106132] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10677 09:30:21.673310 <6>[ 1.114674] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10678 09:30:21.682873 <6>[ 1.123301] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10679 09:30:21.693007 <6>[ 1.132008] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10680 09:30:21.699912 <6>[ 1.140726] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10681 09:30:21.709519 <6>[ 1.149266] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10682 09:30:21.716214 <6>[ 1.158069] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10683 09:30:21.725988 <6>[ 1.166611] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10684 09:30:21.737780 <6>[ 1.182159] loop: module loaded
10685 09:30:21.744247 <6>[ 1.187894] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10686 09:30:21.767058 <4>[ 1.211122] mtk-pmic-keys: Failed to locate of_node [id: -1]
10687 09:30:21.773594 <6>[ 1.217965] megasas: 07.719.03.00-rc1
10688 09:30:21.783558 <6>[ 1.227755] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10689 09:30:21.790128 <6>[ 1.233742] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10690 09:30:21.806378 <6>[ 1.250404] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10691 09:30:21.862304 <6>[ 1.300189] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10692 09:30:24.028965 <6>[ 3.473658] Freeing initrd memory: 59588K
10693 09:30:24.040876 <6>[ 3.485476] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10694 09:30:24.052072 <6>[ 3.496480] tun: Universal TUN/TAP device driver, 1.6
10695 09:30:24.055074 <6>[ 3.502557] thunder_xcv, ver 1.0
10696 09:30:24.058838 <6>[ 3.506051] thunder_bgx, ver 1.0
10697 09:30:24.061979 <6>[ 3.509549] nicpf, ver 1.0
10698 09:30:24.072355 <6>[ 3.513574] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10699 09:30:24.075444 <6>[ 3.521050] hns3: Copyright (c) 2017 Huawei Corporation.
10700 09:30:24.082150 <6>[ 3.526638] hclge is initializing
10701 09:30:24.085730 <6>[ 3.530209] e1000: Intel(R) PRO/1000 Network Driver
10702 09:30:24.092438 <6>[ 3.535339] e1000: Copyright (c) 1999-2006 Intel Corporation.
10703 09:30:24.095299 <6>[ 3.541351] e1000e: Intel(R) PRO/1000 Network Driver
10704 09:30:24.101835 <6>[ 3.546567] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10705 09:30:24.108531 <6>[ 3.552753] igb: Intel(R) Gigabit Ethernet Network Driver
10706 09:30:24.115000 <6>[ 3.558403] igb: Copyright (c) 2007-2014 Intel Corporation.
10707 09:30:24.121474 <6>[ 3.564238] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10708 09:30:24.128081 <6>[ 3.570755] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10709 09:30:24.131671 <6>[ 3.577215] sky2: driver version 1.30
10710 09:30:24.138335 <6>[ 3.582147] usbcore: registered new device driver r8152-cfgselector
10711 09:30:24.145079 <6>[ 3.588680] usbcore: registered new interface driver r8152
10712 09:30:24.151343 <6>[ 3.594498] VFIO - User Level meta-driver version: 0.3
10713 09:30:24.158037 <6>[ 3.602744] usbcore: registered new interface driver usb-storage
10714 09:30:24.164867 <6>[ 3.609187] usbcore: registered new device driver onboard-usb-hub
10715 09:30:24.174067 <6>[ 3.618354] mt6397-rtc mt6359-rtc: registered as rtc0
10716 09:30:24.183744 <6>[ 3.623818] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-18T09:30:24 UTC (1718703024)
10717 09:30:24.186832 <6>[ 3.633373] i2c_dev: i2c /dev entries driver
10718 09:30:24.200620 <4>[ 3.645404] cpu cpu0: supply cpu not found, using dummy regulator
10719 09:30:24.207271 <4>[ 3.651837] cpu cpu1: supply cpu not found, using dummy regulator
10720 09:30:24.214186 <4>[ 3.658252] cpu cpu2: supply cpu not found, using dummy regulator
10721 09:30:24.220971 <4>[ 3.664658] cpu cpu3: supply cpu not found, using dummy regulator
10722 09:30:24.227628 <4>[ 3.671061] cpu cpu4: supply cpu not found, using dummy regulator
10723 09:30:24.234065 <4>[ 3.677471] cpu cpu5: supply cpu not found, using dummy regulator
10724 09:30:24.240608 <4>[ 3.683868] cpu cpu6: supply cpu not found, using dummy regulator
10725 09:30:24.247018 <4>[ 3.690264] cpu cpu7: supply cpu not found, using dummy regulator
10726 09:30:24.267272 <6>[ 3.711912] cpu cpu0: EM: created perf domain
10727 09:30:24.270394 <6>[ 3.716754] cpu cpu4: EM: created perf domain
10728 09:30:24.277863 <6>[ 3.722350] sdhci: Secure Digital Host Controller Interface driver
10729 09:30:24.284575 <6>[ 3.728778] sdhci: Copyright(c) Pierre Ossman
10730 09:30:24.291070 <6>[ 3.733721] Synopsys Designware Multimedia Card Interface Driver
10731 09:30:24.297485 <6>[ 3.740364] sdhci-pltfm: SDHCI platform and OF driver helper
10732 09:30:24.301200 <6>[ 3.740412] mmc0: CQHCI version 5.10
10733 09:30:24.307568 <6>[ 3.750265] ledtrig-cpu: registered to indicate activity on CPUs
10734 09:30:24.314409 <6>[ 3.757247] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10735 09:30:24.320949 <6>[ 3.764289] usbcore: registered new interface driver usbhid
10736 09:30:24.324413 <6>[ 3.770111] usbhid: USB HID core driver
10737 09:30:24.330544 <6>[ 3.774292] spi_master spi0: will run message pump with realtime priority
10738 09:30:24.375708 <6>[ 3.814059] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10739 09:30:24.394378 <6>[ 3.829330] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10740 09:30:24.398013 <6>[ 3.840440] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16414
10741 09:30:24.405286 <6>[ 3.849780] cros-ec-spi spi0.0: Chrome EC device registered
10742 09:30:24.412145 <6>[ 3.855808] mmc0: Command Queue Engine enabled
10743 09:30:24.418399 <6>[ 3.860572] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10744 09:30:24.422165 <6>[ 3.867898] mmcblk0: mmc0:0001 DA4128 116 GiB
10745 09:30:24.432887 <6>[ 3.877587] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10746 09:30:24.440469 <6>[ 3.885201] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10747 09:30:24.450326 <6>[ 3.888961] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10748 09:30:24.453941 <6>[ 3.891140] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10749 09:30:24.460470 <6>[ 3.900909] NET: Registered PF_PACKET protocol family
10750 09:30:24.466837 <6>[ 3.905716] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10751 09:30:24.470292 <6>[ 3.910342] 9pnet: Installing 9P2000 support
10752 09:30:24.477061 <5>[ 3.921344] Key type dns_resolver registered
10753 09:30:24.480248 <6>[ 3.926338] registered taskstats version 1
10754 09:30:24.487099 <5>[ 3.930709] Loading compiled-in X.509 certificates
10755 09:30:24.514890 <4>[ 3.952830] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10756 09:30:24.524519 <4>[ 3.963746] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10757 09:30:24.539655 <6>[ 3.984200] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10758 09:30:24.546932 <6>[ 3.991172] xhci-mtk 11200000.usb: xHCI Host Controller
10759 09:30:24.553333 <6>[ 3.996731] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10760 09:30:24.563463 <6>[ 4.004590] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10761 09:30:24.570291 <6>[ 4.014027] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10762 09:30:24.577056 <6>[ 4.020199] xhci-mtk 11200000.usb: xHCI Host Controller
10763 09:30:24.583164 <6>[ 4.025680] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10764 09:30:24.589905 <6>[ 4.033339] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10765 09:30:24.597001 <6>[ 4.041122] hub 1-0:1.0: USB hub found
10766 09:30:24.600558 <6>[ 4.045155] hub 1-0:1.0: 1 port detected
10767 09:30:24.606674 <6>[ 4.049435] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10768 09:30:24.614093 <6>[ 4.058093] hub 2-0:1.0: USB hub found
10769 09:30:24.617150 <6>[ 4.062114] hub 2-0:1.0: 1 port detected
10770 09:30:24.624532 <6>[ 4.069095] mtk-msdc 11f70000.mmc: Got CD GPIO
10771 09:30:24.642666 <6>[ 4.083500] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10772 09:30:24.652685 <6>[ 4.091982] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10773 09:30:24.658797 <6>[ 4.100329] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10774 09:30:24.668866 <6>[ 4.108682] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10775 09:30:24.675357 <6>[ 4.117024] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10776 09:30:24.685209 <6>[ 4.125374] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10777 09:30:24.691788 <6>[ 4.133713] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10778 09:30:24.702124 <6>[ 4.142061] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10779 09:30:24.708756 <6>[ 4.150402] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10780 09:30:24.718698 <6>[ 4.158751] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10781 09:30:24.725381 <6>[ 4.167094] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10782 09:30:24.735171 <6>[ 4.175443] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10783 09:30:24.741790 <6>[ 4.183781] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10784 09:30:24.751610 <6>[ 4.192129] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10785 09:30:24.757656 <6>[ 4.200468] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10786 09:30:24.764572 <6>[ 4.209227] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10787 09:30:24.771840 <6>[ 4.216428] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10788 09:30:24.778693 <6>[ 4.223241] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10789 09:30:24.788939 <6>[ 4.230006] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10790 09:30:24.795442 <6>[ 4.236940] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10791 09:30:24.801904 <6>[ 4.243784] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10792 09:30:24.811618 <6>[ 4.252913] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10793 09:30:24.821864 <6>[ 4.262033] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10794 09:30:24.831891 <6>[ 4.271327] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10795 09:30:24.841451 <6>[ 4.280794] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10796 09:30:24.847932 <6>[ 4.290260] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10797 09:30:24.858197 <6>[ 4.299379] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10798 09:30:24.868159 <6>[ 4.308846] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10799 09:30:24.878079 <6>[ 4.317965] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10800 09:30:24.887891 <6>[ 4.327264] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10801 09:30:24.897866 <6>[ 4.337448] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10802 09:30:24.907265 <6>[ 4.348509] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10803 09:30:25.005283 <6>[ 4.446811] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10804 09:30:25.033129 <6>[ 4.477574] hub 2-1:1.0: USB hub found
10805 09:30:25.036144 <6>[ 4.482017] hub 2-1:1.0: 3 ports detected
10806 09:30:25.045347 <6>[ 4.490232] hub 2-1:1.0: USB hub found
10807 09:30:25.048552 <6>[ 4.494672] hub 2-1:1.0: 3 ports detected
10808 09:30:25.157075 <6>[ 4.598528] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10809 09:30:25.311431 <6>[ 4.756215] hub 1-1:1.0: USB hub found
10810 09:30:25.314490 <6>[ 4.760751] hub 1-1:1.0: 4 ports detected
10811 09:30:25.326267 <6>[ 4.770751] hub 1-1:1.0: USB hub found
10812 09:30:25.329336 <6>[ 4.775165] hub 1-1:1.0: 4 ports detected
10813 09:30:25.397064 <6>[ 4.838693] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10814 09:30:25.505335 <6>[ 4.947057] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10815 09:30:25.538214 <4>[ 4.979315] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10816 09:30:25.547528 <4>[ 4.988512] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10817 09:30:25.582931 <6>[ 5.027440] r8152 2-1.3:1.0 eth0: v1.12.13
10818 09:30:25.661473 <6>[ 5.102678] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10819 09:30:25.792887 <6>[ 5.237890] hub 1-1.4:1.0: USB hub found
10820 09:30:25.796253 <6>[ 5.242440] hub 1-1.4:1.0: 2 ports detected
10821 09:30:25.810418 <6>[ 5.255084] hub 1-1.4:1.0: USB hub found
10822 09:30:25.813442 <6>[ 5.259611] hub 1-1.4:1.0: 2 ports detected
10823 09:30:26.109238 <6>[ 5.550623] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10824 09:30:26.301254 <6>[ 5.742612] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10825 09:30:27.221816 <6>[ 6.666831] r8152 2-1.3:1.0 eth0: carrier on
10826 09:30:30.029459 <5>[ 6.690336] Sending DHCP requests .., OK
10827 09:30:30.035593 <6>[ 9.478848] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10828 09:30:30.039342 <6>[ 9.487183] IP-Config: Complete:
10829 09:30:30.052345 <6>[ 9.490688] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10830 09:30:30.059064 <6>[ 9.501410] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10831 09:30:30.065324 <6>[ 9.510029] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10832 09:30:30.072187 <6>[ 9.510038] nameserver0=192.168.201.1
10833 09:30:30.075629 <6>[ 9.522226] clk: Disabling unused clocks
10834 09:30:30.079212 <6>[ 9.527777] ALSA device list:
10835 09:30:30.085446 <6>[ 9.531055] No soundcards found.
10836 09:30:30.093406 <6>[ 9.538825] Freeing unused kernel memory: 8512K
10837 09:30:30.096816 <6>[ 9.543827] Run /init as init process
10838 09:30:30.127332 <6>[ 9.572614] NET: Registered PF_INET6 protocol family
10839 09:30:30.134443 <6>[ 9.579438] Segment Routing with IPv6
10840 09:30:30.137405 <6>[ 9.583390] In-situ OAM (IOAM) with IPv6
10841 09:30:30.182387 <30>[ 9.601408] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10842 09:30:30.189038 <30>[ 9.634507] systemd[1]: Detected architecture arm64.
10843 09:30:30.189136
10844 09:30:30.195923 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10845 09:30:30.195995
10846 09:30:30.209419 <30>[ 9.654776] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10847 09:30:30.350846 <30>[ 9.792612] systemd[1]: Queued start job for default target graphical.target.
10848 09:30:30.402079 <30>[ 9.844164] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10849 09:30:30.408704 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10850 09:30:30.428997 <30>[ 9.871279] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10851 09:30:30.439136 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10852 09:30:30.457697 <30>[ 9.899683] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10853 09:30:30.467608 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10854 09:30:30.486020 <30>[ 9.928083] systemd[1]: Created slice user.slice - User and Session Slice.
10855 09:30:30.492610 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10856 09:30:30.516587 <30>[ 9.955336] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10857 09:30:30.526594 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10858 09:30:30.543965 <30>[ 9.982776] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10859 09:30:30.550910 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10860 09:30:30.578822 <30>[ 10.011180] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10861 09:30:30.589159 <30>[ 10.031076] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10862 09:30:30.595822 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10863 09:30:30.613034 <30>[ 10.054618] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10864 09:30:30.619431 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10865 09:30:30.636626 <30>[ 10.078679] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10866 09:30:30.646488 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10867 09:30:30.661210 <30>[ 10.106673] systemd[1]: Reached target paths.target - Path Units.
10868 09:30:30.671357 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10869 09:30:30.688472 <30>[ 10.130616] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10870 09:30:30.695118 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10871 09:30:30.709435 <30>[ 10.154590] systemd[1]: Reached target slices.target - Slice Units.
10872 09:30:30.719337 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10873 09:30:30.733816 <30>[ 10.179105] systemd[1]: Reached target swap.target - Swaps.
10874 09:30:30.740574 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10875 09:30:30.761381 <30>[ 10.203120] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10876 09:30:30.771067 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10877 09:30:30.788937 <30>[ 10.231108] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10878 09:30:30.798948 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10879 09:30:30.818063 <30>[ 10.259986] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10880 09:30:30.828039 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10881 09:30:30.845079 <30>[ 10.287175] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10882 09:30:30.855012 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10883 09:30:30.873563 <30>[ 10.315818] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10884 09:30:30.880631 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10885 09:30:30.901472 <30>[ 10.343275] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10886 09:30:30.911069 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10887 09:30:30.929151 <30>[ 10.371088] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10888 09:30:30.938960 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10889 09:30:30.980662 <30>[ 10.422728] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10890 09:30:30.987117 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10891 09:30:31.007324 <30>[ 10.449352] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10892 09:30:31.014038 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10893 09:30:31.037314 <30>[ 10.479063] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10894 09:30:31.043623 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10895 09:30:31.071018 <30>[ 10.506698] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10896 09:30:31.121244 <30>[ 10.563113] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10897 09:30:31.130661 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10898 09:30:31.154033 <30>[ 10.595986] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10899 09:30:31.160265 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10900 09:30:31.225511 <30>[ 10.667310] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10901 09:30:31.235119 Startin<6>[ 10.676696] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10902 09:30:31.241396 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10903 09:30:31.265598 <30>[ 10.707702] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10904 09:30:31.272408 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10905 09:30:31.297557 <30>[ 10.739835] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10906 09:30:31.307583 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10907 09:30:31.329289 <30>[ 10.771356] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10908 09:30:31.335834 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10909 09:30:31.365945 <30>[ 10.807589] systemd[1]: Starting systemd-journald.service - Journal Service...
10910 09:30:31.372134 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10911 09:30:31.391147 <30>[ 10.833219] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10912 09:30:31.398006 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10913 09:30:31.422706 <30>[ 10.861486] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10914 09:30:31.429618 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10915 09:30:31.452121 <30>[ 10.894327] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10916 09:30:31.462332 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10917 09:30:31.483864 <30>[ 10.925738] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10918 09:30:31.493606 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10919 09:30:31.516578 <30>[ 10.958603] systemd[1]: Started systemd-journald.service - Journal Service.
10920 09:30:31.523293 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10921 09:30:31.543329 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10922 09:30:31.561349 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10923 09:30:31.581928 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10924 09:30:31.601847 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10925 09:30:31.622735 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10926 09:30:31.642396 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10927 09:30:31.662164 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10928 09:30:31.681861 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10929 09:30:31.701703 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10930 09:30:31.723395 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10931 09:30:31.747441 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10932 09:30:31.767381 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10933 09:30:31.774113 See 'systemctl status systemd-remount-fs.service' for details.
10934 09:30:31.783805 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10935 09:30:31.802829 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10936 09:30:31.868936 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10937 09:30:31.890098 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10938 09:30:31.901216 <46>[ 11.343576] systemd-journald[194]: Received client request to flush runtime journal.
10939 09:30:31.917955 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10940 09:30:31.946759 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10941 09:30:31.974436 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10942 09:30:32.003330 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10943 09:30:32.026057 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10944 09:30:32.049917 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10945 09:30:32.070457 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10946 09:30:32.089636 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10947 09:30:32.137308 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10948 09:30:32.163439 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10949 09:30:32.184591 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10950 09:30:32.204513 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10951 09:30:32.245073 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10952 09:30:32.269431 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10953 09:30:32.292236 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10954 09:30:32.337467 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10955 09:30:32.369412 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10956 09:30:32.394696 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10957 09:30:32.416652 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10958 09:30:32.463135 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10959 09:30:32.487771 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10960 09:30:32.593886 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10961 09:30:32.614023 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10962 09:30:32.633875 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10963 09:30:32.654077 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10964 09:30:32.673073 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10965 09:30:32.685977 <6>[ 12.127935] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10966 09:30:32.699500 [[0;32m OK [0m] Listening on<6>[ 12.139745] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10967 09:30:32.705729 [0;1;39mdbus.s<6>[ 12.142029] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10968 09:30:32.715741 ocket[…- D-Bu<6>[ 12.145187] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10969 09:30:32.725897 s System Message<6>[ 12.145194] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10970 09:30:32.725978 Bus Socket.
10971 09:30:32.735489 <4>[ 12.145344] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10972 09:30:32.745366 <6>[ 12.145981] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10973 09:30:32.751889 <6>[ 12.145985] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10974 09:30:32.758654 <6>[ 12.146115] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10975 09:30:32.768484 <6>[ 12.146126] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10976 09:30:32.774910 <6>[ 12.146131] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10977 09:30:32.784977 <6>[ 12.146136] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10978 09:30:32.794949 <6>[ 12.148703] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10979 09:30:32.797964 <6>[ 12.160774] remoteproc remoteproc0: scp is available
10980 09:30:32.807921 <6>[ 12.167233] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10981 09:30:32.811037 <6>[ 12.176006] remoteproc remoteproc0: powering up scp
10982 09:30:32.821193 <6>[ 12.176012] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10983 09:30:32.827709 <6>[ 12.176039] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10984 09:30:32.830742 <6>[ 12.243795] mc: Linux media interface: v0.10
10985 09:30:32.837898 <3>[ 12.244334] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10986 09:30:32.847842 <3>[ 12.289937] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10987 09:30:32.857522 [[0;32m OK [<6>[ 12.291416] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10988 09:30:32.861098 <6>[ 12.292591] videodev: Linux video capture interface: v2.00
10989 09:30:32.870590 <3>[ 12.298042] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10990 09:30:32.880829 0m] Reached targ<3>[ 12.298190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10991 09:30:32.890601 et [0;1;39msock<3>[ 12.298195] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10992 09:30:32.900354 ets.target[0m -<3>[ 12.298199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10993 09:30:32.907002 <3>[ 12.298211] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10994 09:30:32.913804 <3>[ 12.298215] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10995 09:30:32.916813 Socket Units.
10996 09:30:32.924477 <6>[ 12.301749] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10997 09:30:32.924560
10998 09:30:32.931098 <6>[ 12.307272] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10999 09:30:32.940495 <4>[ 12.340989] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11000 09:30:32.947347 <4>[ 12.340989] Fallback method does not support PEC.
11001 09:30:32.950468 <6>[ 12.351537] remoteproc remoteproc0: remote processor scp is now up
11002 09:30:32.960330 <3>[ 12.357739] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11003 09:30:32.970796 <3>[ 12.372821] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 09:30:32.976870 <3>[ 12.402464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11005 09:30:32.983934 <4>[ 12.410796] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11006 09:30:32.993408 <3>[ 12.410901] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11007 09:30:33.000247 <6>[ 12.420317] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11008 09:30:33.007077 <3>[ 12.427722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11009 09:30:33.013383 [[0;32m OK [<6>[ 12.458629] pci_bus 0000:00: root bus resource [bus 00-ff]
11010 09:30:33.024061 0m] Reached targ<6>[ 12.465660] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11011 09:30:33.034275 et [0;1;39mbasi<3>[ 12.471820] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11012 09:30:33.044067 c.target[0m - B<6>[ 12.474137] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11013 09:30:33.054092 <6>[ 12.477016] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11014 09:30:33.063807 <4>[ 12.487646] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11015 09:30:33.063898 asic System.
11016 09:30:33.070517 <3>[ 12.487651] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11017 09:30:33.080392 <3>[ 12.487665] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11018 09:30:33.087270 <3>[ 12.487672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11019 09:30:33.096885 <3>[ 12.487678] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11020 09:30:33.103871 <3>[ 12.487682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11021 09:30:33.110167 <6>[ 12.495620] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11022 09:30:33.116944 <3>[ 12.512053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11023 09:30:33.126572 <6>[ 12.512979] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11024 09:30:33.133173 <6>[ 12.532999] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11025 09:30:33.140501 <6>[ 12.538571] pci 0000:00:00.0: supports D1 D2
11026 09:30:33.147546 <6>[ 12.590037] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11027 09:30:33.157897 <3>[ 12.598006] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11028 09:30:33.164003 <6>[ 12.598059] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11029 09:30:33.174403 <6>[ 12.598421] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11030 09:30:33.181426 <6>[ 12.599575] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11031 09:30:33.191248 <6>[ 12.618928] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11032 09:30:33.198136 <6>[ 12.623423] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11033 09:30:33.204761 <3>[ 12.628931] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11034 09:30:33.207784 <6>[ 12.647892] Bluetooth: Core ver 2.22
11035 09:30:33.218162 <6>[ 12.655959] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11036 09:30:33.222347 <6>[ 12.659814] NET: Registered PF_BLUETOOTH protocol family
11037 09:30:33.229122 <6>[ 12.661231] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11038 09:30:33.242413 <6>[ 12.662378] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11039 09:30:33.249146 <6>[ 12.662541] usbcore: registered new interface driver uvcvideo
11040 09:30:33.256304 <6>[ 12.667245] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11041 09:30:33.263271 <6>[ 12.672793] Bluetooth: HCI device and connection manager initialized
11042 09:30:33.269472 <3>[ 12.674823] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11043 09:30:33.277071 <6>[ 12.679839] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11044 09:30:33.286994 <3>[ 12.689595] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11045 09:30:33.293671 <3>[ 12.692197] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
11046 09:30:33.300503 <6>[ 12.692264] Bluetooth: HCI socket layer initialized
11047 09:30:33.303494 <6>[ 12.698352] pci 0000:01:00.0: supports D1 D2
11048 09:30:33.310162 <6>[ 12.705709] Bluetooth: L2CAP socket layer initialized
11049 09:30:33.317656 <6>[ 12.706245] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11050 09:30:33.324547 <3>[ 12.707516] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11051 09:30:33.331355 <6>[ 12.712305] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11052 09:30:33.337745 <6>[ 12.721083] Bluetooth: SCO socket layer initialized
11053 09:30:33.344634 <3>[ 12.729851] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11054 09:30:33.351932 <6>[ 12.739969] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11055 09:30:33.361717 <3>[ 12.768477] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11056 09:30:33.368980 <6>[ 12.775896] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11057 09:30:33.375533 <6>[ 12.776558] usbcore: registered new interface driver btusb
11058 09:30:33.385897 <4>[ 12.777469] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11059 09:30:33.393032 <3>[ 12.777488] Bluetooth: hci0: Failed to load firmware file (-2)
11060 09:30:33.396483 <3>[ 12.777493] Bluetooth: hci0: Failed to set up firmware (-2)
11061 09:30:33.409469 <4>[ 12.777499] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11062 09:30:33.416637 <6>[ 12.858895] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11063 09:30:33.423372 <6>[ 12.858904] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11064 09:30:33.433174 <6>[ 12.858917] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11065 09:30:33.440142 <6>[ 12.858930] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11066 09:30:33.446655 <6>[ 12.858942] pci 0000:00:00.0: PCI bridge to [bus 01]
11067 09:30:33.452989 <6>[ 12.858947] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11068 09:30:33.459963 <6>[ 12.859103] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11069 09:30:33.466622 Startin<6>[ 12.911195] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11070 09:30:33.476315 g [0;1;39mdbus.<6>[ 12.918436] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11071 09:30:33.479383 service[0m - D-Bus System Message Bus...
11072 09:30:33.491441 <5>[ 12.933823] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11073 09:30:33.508585 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11074 09:30:33.520468 <5>[ 12.962600] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11075 09:30:33.527299 <5>[ 12.970005] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11076 09:30:33.537076 <4>[ 12.978758] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11077 09:30:33.543223 <6>[ 12.987705] cfg80211: failed to load regulatory.db
11078 09:30:33.563322 <46>[ 12.987957] systemd-journald[194]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.2 (1539 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11079 09:30:33.579941 Startin<46>[ 13.014161] systemd-journald[194]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11080 09:30:33.586464 g [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11081 09:30:33.604114 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11082 09:30:33.626681 <6>[ 13.068240] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11083 09:30:33.633085 <6>[ 13.068482] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11084 09:30:33.642943 [[0;32m OK [0m] Finished [0;1;39msystemd-us<6>[ 13.086301] mt7921e 0000:01:00.0: ASIC revision: 79610010
11085 09:30:33.646552 er-sess…ervice[0m - Permit User Sessions.
11086 09:30:33.671609 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11087 09:30:33.694496 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11088 09:30:33.711199 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11089 09:30:33.733218 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11090 09:30:33.747321 <6>[ 13.189803] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11091 09:30:33.750642 <6>[ 13.189803]
11092 09:30:33.783000 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11093 09:30:33.809598 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11094 09:30:33.828069 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11095 09:30:33.844653 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11096 09:30:33.865697 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11097 09:30:33.921579 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11098 09:30:33.947700 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11099 09:30:33.972300 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11100 09:30:34.015646 <6>[ 13.458047] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11101 09:30:34.038087 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11102 09:30:34.058138 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11103 09:30:34.084053 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11104 09:30:34.140214
11105 09:30:34.143190 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11106 09:30:34.143269
11107 09:30:34.146881 debian-bookworm-arm64 login: root (automatic login)
11108 09:30:34.146957
11109 09:30:34.166410 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
11110 09:30:34.166489
11111 09:30:34.173244 The programs included with the Debian GNU/Linux system are free software;
11112 09:30:34.179629 the exact distribution terms for each program are described in the
11113 09:30:34.182626 individual files in /usr/share/doc/*/copyright.
11114 09:30:34.182703
11115 09:30:34.189352 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11116 09:30:34.193073 permitted by applicable law.
11117 09:30:34.193440 Matched prompt #10: / #
11119 09:30:34.193625 Setting prompt string to ['/ #']
11120 09:30:34.193711 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11122 09:30:34.193891 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11123 09:30:34.193972 start: 2.2.6 expect-shell-connection (timeout 00:02:47) [common]
11124 09:30:34.194036 Setting prompt string to ['/ #']
11125 09:30:34.194092 Forcing a shell prompt, looking for ['/ #']
11127 09:30:34.244292 / #
11128 09:30:34.244444 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11129 09:30:34.244537 Waiting using forced prompt support (timeout 00:02:30)
11130 09:30:34.249152
11131 09:30:34.249414 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11132 09:30:34.249504 start: 2.2.7 export-device-env (timeout 00:02:47) [common]
11133 09:30:34.249587 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11134 09:30:34.249668 end: 2.2 depthcharge-retry (duration 00:02:13) [common]
11135 09:30:34.249749 end: 2 depthcharge-action (duration 00:02:13) [common]
11136 09:30:34.249829 start: 3 lava-test-retry (timeout 00:07:20) [common]
11137 09:30:34.249913 start: 3.1 lava-test-shell (timeout 00:07:20) [common]
11138 09:30:34.249979 Using namespace: common
11140 09:30:34.350300 / # #
11141 09:30:34.350471 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11142 09:30:34.355502 #
11143 09:30:34.355760 Using /lava-14407656
11145 09:30:34.456097 / # export SHELL=/bin/sh
11146 09:30:34.461959 export SHELL=/bin/sh
11148 09:30:34.562473 / # . /lava-14407656/environment
11149 09:30:34.567860 . /lava-14407656/environment
11151 09:30:34.668381 / # /lava-14407656/bin/lava-test-runner /lava-14407656/0
11152 09:30:34.668562 Test shell timeout: 10s (minimum of the action and connection timeout)
11153 09:30:34.674019 /lava-14407656/bin/lava-test-runner /lava-14407656/0
11154 09:30:34.700049 + export TESTRUN_ID=0_igt-kms-medi<8>[ 14.144231] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 14407656_1.5.2.3.1>
11155 09:30:34.700305 Received signal: <STARTRUN> 0_igt-kms-mediatek 14407656_1.5.2.3.1
11156 09:30:34.700372 Starting test lava.0_igt-kms-mediatek (14407656_1.5.2.3.1)
11157 09:30:34.700451 Skipping test definition patterns.
11158 09:30:34.703114 atek
11159 09:30:34.706757 + cd /lava-14407656/0/tests/0_igt-kms-mediatek
11160 09:30:34.706835 + cat uuid
11161 09:30:34.709773 + UUID=14407656_1.5.2.3.1
11162 09:30:34.709850 + set +x
11163 09:30:34.729379 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11164 09:30:34.736186 <8>[ 14.181377] <LAVA_SIGNAL_TESTSET START core_auth>
11165 09:30:34.736431 Received signal: <TESTSET> START core_auth
11166 09:30:34.736504 Starting test_set core_auth
11167 09:30:34.754411 <14>[ 14.200020] [IGT] core_auth: executing
11168 09:30:34.761010 IGT-Version: 1.2<14>[ 14.204395] [IGT] core_auth: starting subtest getclient-simple
11169 09:30:34.771134 8-ga44ebfe (aarc<14>[ 14.212060] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11170 09:30:34.774136 h64) (Linux: 6.1<14>[ 14.220296] [IGT] core_auth: exiting, ret=0
11171 09:30:34.777211 .92-cip22 aarch64)
11172 09:30:34.787295 Using IGT_SRANDOM=1718703034<8>[ 14.230211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11173 09:30:34.787373 for randomisation
11174 09:30:34.787604 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11176 09:30:34.790383 Starting subtest: getclient-simple
11177 09:30:34.794007 Opened device: /dev/dri/card0
11178 09:30:34.800279 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11179 09:30:34.803762 <14>[ 14.251587] [IGT] core_auth: executing
11180 09:30:34.813543 IGT-Version: 1.2<14>[ 14.255979] [IGT] core_auth: starting subtest getclient-master-drop
11181 09:30:34.823857 8-ga44ebfe (aarc<14>[ 14.264205] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11182 09:30:34.826926 h64) (Linux: 6.1<14>[ 14.272779] [IGT] core_auth: exiting, ret=0
11183 09:30:34.829933 .92-cip22 aarch64)
11184 09:30:34.839980 Using IGT_SRANDOM=1718703035 for randomisati<8>[ 14.282861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11185 09:30:34.840062 on
11186 09:30:34.840296 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11188 09:30:34.846732 Starting subtest: getclient-master-drop
11189 09:30:34.846810 Opened device: /dev/dri/card0
11190 09:30:34.853530 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11191 09:30:34.862531 <14>[ 14.308444] [IGT] core_auth: executing
11192 09:30:34.869211 IGT-Version: 1.2<14>[ 14.312860] [IGT] core_auth: starting subtest basic-auth
11193 09:30:34.876033 8-ga44ebfe (aarc<14>[ 14.319841] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11194 09:30:34.882518 h64) (Linux: 6.1<14>[ 14.327604] [IGT] core_auth: exiting, ret=0
11195 09:30:34.885890 .92-cip22 aarch64)
11196 09:30:34.889350 Using IGT_SRANDOM=1718703035 for randomisation
11197 09:30:34.896066 Opened devic<6>[ 14.340080] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11198 09:30:34.902292 <8>[ 14.340161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11199 09:30:34.902370 e: /dev/dri/card0
11200 09:30:34.902599 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11202 09:30:34.905845 Starting subtest: basic-auth
11203 09:30:34.909123 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11204 09:30:34.940237 <14>[ 14.385980] [IGT] core_auth: executing
11205 09:30:34.946900 IGT-Version: 1.2<14>[ 14.390908] [IGT] core_auth: starting subtest many-magics
11206 09:30:34.950221 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11207 09:30:34.956988 Using IGT_SRANDOM=1718703035 for randomisation
11208 09:30:34.957092 Opened device: /dev/dri/card0
11209 09:30:34.966696 Starting subt<14>[ 14.408963] [IGT] core_auth: finished subtest many-magics, SUCCESS
11210 09:30:34.973449 est: many-magics<14>[ 14.416881] [IGT] core_auth: exiting, ret=0
11211 09:30:34.973527
11212 09:30:34.976542 Reopening device failed after 1020 opens
11213 09:30:34.983210 [1mSubtest many-mag<8>[ 14.427946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11214 09:30:34.983458 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11216 09:30:34.986221 ics: SUCCESS (0.011s)[0m
11217 09:30:34.989636 <8>[ 14.436705] <LAVA_SIGNAL_TESTSET STOP>
11218 09:30:34.989882 Received signal: <TESTSET> STOP
11219 09:30:34.989948 Closing test_set core_auth
11220 09:30:35.036547 <14>[ 14.482306] [IGT] core_getclient: executing
11221 09:30:35.042787 IGT-Version: 1.2<14>[ 14.487204] [IGT] core_getclient: exiting, ret=0
11222 09:30:35.046645 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11223 09:30:35.056393 Using IGT_SR<8>[ 14.497925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11224 09:30:35.056690 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11226 09:30:35.059393 ANDOM=1718703035 for randomisation
11227 09:30:35.059469 Opened device: /dev/dri/card0
11228 09:30:35.062667 SUCCESS (0.006s)
11229 09:30:35.087436 <14>[ 14.533183] [IGT] core_getstats: executing
11230 09:30:35.094163 IGT-Version: 1.2<14>[ 14.538310] [IGT] core_getstats: exiting, ret=0
11231 09:30:35.097225 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11232 09:30:35.107408 Using IGT_SR<8>[ 14.548985] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11233 09:30:35.107653 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11235 09:30:35.110669 ANDOM=1718703035 for randomisation
11236 09:30:35.110744 Opened device: /dev/dri/card0
11237 09:30:35.114142 SUCCESS (0.006s)
11238 09:30:35.138821 <14>[ 14.584829] [IGT] core_getversion: executing
11239 09:30:35.145677 IGT-Version: 1.2<14>[ 14.589844] [IGT] core_getversion: exiting, ret=0
11240 09:30:35.148679 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11241 09:30:35.158892 Using IGT_SR<8>[ 14.600861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11242 09:30:35.159137 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11244 09:30:35.162043 ANDOM=1718703035 for randomisation
11245 09:30:35.165153 Opened device: /dev/dri/card0
11246 09:30:35.165233 SUCCESS (0.006s)
11247 09:30:35.189720 <14>[ 14.635547] [IGT] core_setmaster_vs_auth: executing
11248 09:30:35.196495 IGT-Version: 1.2<14>[ 14.641407] [IGT] core_setmaster_vs_auth: exiting, ret=0
11249 09:30:35.203046 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11250 09:30:35.209862 Using IGT_SR<8>[ 14.652571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11251 09:30:35.210162 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11253 09:30:35.212923 ANDOM=1718703035 for randomisation
11254 09:30:35.216451 Opened device: /dev/dri/card0
11255 09:30:35.219383 SUCCESS (0.007s)
11256 09:30:35.231568 <8>[ 14.677438] <LAVA_SIGNAL_TESTSET START drm_read>
11257 09:30:35.231814 Received signal: <TESTSET> START drm_read
11258 09:30:35.231878 Starting test_set drm_read
11259 09:30:35.249583 <14>[ 14.695330] [IGT] drm_read: executing
11260 09:30:35.256403 IGT-Version: 1.2<14>[ 14.699971] [IGT] drm_read: exiting, ret=77
11261 09:30:35.259556 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11262 09:30:35.266278 Using IGT_SR<8>[ 14.710147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11263 09:30:35.266523 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11265 09:30:35.269433 ANDOM=1718703035 for randomisation
11266 09:30:35.272509 Opened device: /dev/dri/card0
11267 09:30:35.279441 No KMS driver or no outputs, pipes: 16, outputs: 0
11268 09:30:35.286223 [1mSubtest invalid-buffer: SKIP (0.000s)<14>[ 14.732039] [IGT] drm_read: executing
11269 09:30:35.286327 [0m
11270 09:30:35.289059 <14>[ 14.736745] [IGT] drm_read: exiting, ret=77
11271 09:30:35.302704 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<8>[ 14.745754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11272 09:30:35.302785 4)
11273 09:30:35.303015 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11275 09:30:35.308844 Using IGT_SRANDOM=1718703035 for randomisation
11276 09:30:35.308920 Opened device: /dev/dri/card0
11277 09:30:35.315548 No KMS driver or no outputs, pipes: 16, outputs: 0
11278 09:30:35.322266 [1mSubtest fault-buffer: SKIP (0.000s)[<14>[ 14.767974] [IGT] drm_read: executing
11279 09:30:35.322343 0m
11280 09:30:35.328717 IGT-Version: 1.2<14>[ 14.773888] [IGT] drm_read: exiting, ret=77
11281 09:30:35.332257 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11282 09:30:35.342615 Using IGT_SR<8>[ 14.784087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11283 09:30:35.342862 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11285 09:30:35.345146 ANDOM=1718703035 for randomisation
11286 09:30:35.348949 Opened device: /dev/dri/card0
11287 09:30:35.351960 No KMS driver or no outputs, pipes: 16, outputs: 0
11288 09:30:35.355465 [1mSubtest empty-block: SKIP (0.000s)[0m
11289 09:30:35.358340 <14>[ 14.806264] [IGT] drm_read: executing
11290 09:30:35.365398 IGT-Version: 1.2<14>[ 14.810996] [IGT] drm_read: exiting, ret=77
11291 09:30:35.368541 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11292 09:30:35.378479 Using IGT_SR<8>[ 14.820855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11293 09:30:35.378725 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11295 09:30:35.381652 ANDOM=1718703035 for randomisation
11296 09:30:35.385173 Opened device: /dev/dri/card0
11297 09:30:35.388301 No KMS driver or no outputs, pipes: 16, outputs: 0
11298 09:30:35.391783 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11299 09:30:35.398439 <14>[ 14.843114] [IGT] drm_read: executing
11300 09:30:35.401535 IGT-Version: 1.2<14>[ 14.848138] [IGT] drm_read: exiting, ret=77
11301 09:30:35.408615 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11302 09:30:35.415065 Using IGT_SR<8>[ 14.858133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11303 09:30:35.415311 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11305 09:30:35.418277 ANDOM=1718703035 for randomisation
11306 09:30:35.421433 Opened device: /dev/dri/card0
11307 09:30:35.425048 No KMS driver or no outputs, pipes: 16, outputs: 0
11308 09:30:35.434533 [1mSubtest short-buffer-block: SKIP (0.0<14>[ 14.880345] [IGT] drm_read: executing
11309 09:30:35.434614 00s)[0m
11310 09:30:35.438097 <14>[ 14.885279] [IGT] drm_read: exiting, ret=77
11311 09:30:35.451193 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<8>[ 14.894609] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11312 09:30:35.451448 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11314 09:30:35.454940 4)
11315 09:30:35.458014 Using IGT_SRANDOM=1718703035 for randomisation
11316 09:30:35.461040 Opened device: /dev/dri/card0
11317 09:30:35.464572 No KMS driver or no outputs, pipes: 16, outputs: 0
11318 09:30:35.471531 [1mSubtest short-buffer-<14>[ 14.917292] [IGT] drm_read: executing
11319 09:30:35.477829 nonblock: SKIP (<14>[ 14.922117] [IGT] drm_read: exiting, ret=77
11320 09:30:35.477907 0.000s)[0m
11321 09:30:35.490790 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92<8>[ 14.932141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11322 09:30:35.490868 -cip22 aarch64)
11323 09:30:35.491096 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11325 09:30:35.497452 Using IGT_SRAND<8>[ 14.942196] <LAVA_SIGNAL_TESTSET STOP>
11326 09:30:35.497702 Received signal: <TESTSET> STOP
11327 09:30:35.497768 Closing test_set drm_read
11328 09:30:35.501119 OM=1718703035 for randomisation
11329 09:30:35.501209 Opened device: /dev/dri/card0
11330 09:30:35.507338 No KMS driver or no outputs, pipes: 16, outputs: 0
11331 09:30:35.511095 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11332 09:30:35.518839 <8>[ 14.964473] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11333 09:30:35.519098 Received signal: <TESTSET> START kms_addfb_basic
11334 09:30:35.519162 Starting test_set kms_addfb_basic
11335 09:30:35.541826 <14>[ 14.987507] [IGT] kms_addfb_basic: executing
11336 09:30:35.555037 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<14>[ 14.996749] [IGT] kms_addfb_basic: starting subtest unused-handle
11337 09:30:35.555119 4)
11338 09:30:35.561911 Using IGT_SR<14>[ 15.004561] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11339 09:30:35.564997 ANDOM=1718703035 for randomisation
11340 09:30:35.568095 Opened device: /dev/dri/card0
11341 09:30:35.574862 Starting subtest: unused-hand<14>[ 15.021428] [IGT] kms_addfb_basic: exiting, ret=0
11342 09:30:35.574940 le
11343 09:30:35.581260 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11344 09:30:35.588066 Test requir<8>[ 15.031243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11345 09:30:35.588313 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11347 09:30:35.594878 ement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11348 09:30:35.598004 Test requirement: is_intel_device(fd)
11349 09:30:35.607720 Test requirement not met in function igt_require<14>[ 15.053045] [IGT] kms_addfb_basic: executing
11350 09:30:35.611377 _intel, file ../lib/drmtest.c:880:
11351 09:30:35.617650 Test requirement: is_intel_d<14>[ 15.062268] [IGT] kms_addfb_basic: starting subtest unused-pitches
11352 09:30:35.621174 evice(fd)
11353 09:30:35.627913 No KM<14>[ 15.070167] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11354 09:30:35.630950 S driver or no outputs, pipes: 16, outputs: 0
11355 09:30:35.640776 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.<14>[ 15.087156] [IGT] kms_addfb_basic: exiting, ret=0
11356 09:30:35.644461 92-cip22 aarch64)
11357 09:30:35.647516 Using IGT_SRANDOM=1718703035 for randomisation
11358 09:30:35.653855 Opened device<8>[ 15.098114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11359 09:30:35.654102 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11361 09:30:35.657186 : /dev/dri/card0
11362 09:30:35.660862 Starting subtest: unused-pitches
11363 09:30:35.663840 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11364 09:30:35.677271 Test requirement not met in function igt_require_intel, file ../lib/drmtes<14>[ 15.120823] [IGT] kms_addfb_basic: executing
11365 09:30:35.677349 t.c:880:
11366 09:30:35.680581 Test requirement: is_intel_device(fd)
11367 09:30:35.687400 Test requiremen<14>[ 15.130949] [IGT] kms_addfb_basic: starting subtest unused-offsets
11368 09:30:35.696979 t not met in fun<14>[ 15.138886] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11369 09:30:35.700282 ction igt_require_intel, file ../lib/drmtest.c:880:
11370 09:30:35.703917 Test requirement: is_intel_device(fd)
11371 09:30:35.710281 No K<14>[ 15.155516] [IGT] kms_addfb_basic: exiting, ret=0
11372 09:30:35.713463 MS driver or no outputs, pipes: 16, outputs: 0
11373 09:30:35.723895 IGT-Version: 1.28-ga44ebfe (aarc<8>[ 15.166631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11374 09:30:35.724142 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11376 09:30:35.726816 h64) (Linux: 6.1.92-cip22 aarch64)
11377 09:30:35.730583 Using IGT_SRANDOM=1718703035 for randomisation
11378 09:30:35.733745 Opened device: /dev/dri/card0
11379 09:30:35.736854 Starting subtest: unused-offsets
11380 09:30:35.743540 [1mSubtest unused-offsets:<14>[ 15.189534] [IGT] kms_addfb_basic: executing
11381 09:30:35.746610 SUCCESS (0.000s)[0m
11382 09:30:35.756556 Test requirement not met in function igt_<14>[ 15.199710] [IGT] kms_addfb_basic: starting subtest unused-modifier
11383 09:30:35.766371 require_intel, f<14>[ 15.207367] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11384 09:30:35.766450 ile ../lib/drmtest.c:880:
11385 09:30:35.769928 Test requirement: is_intel_device(fd)
11386 09:30:35.780018 Test requirement not met in fu<14>[ 15.224438] [IGT] kms_addfb_basic: exiting, ret=0
11387 09:30:35.783511 nction igt_require_intel, file ../lib/drmtest.c:880:
11388 09:30:35.793204 Test requirement: is_intel<8>[ 15.235267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11389 09:30:35.793283 _device(fd)
11390 09:30:35.793512 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11392 09:30:35.799479 No KMS driver or no outputs, pipes: 16, outputs: 0
11393 09:30:35.806195 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11394 09:30:35.812761 Using IGT_SRANDOM=171870303<14>[ 15.257775] [IGT] kms_addfb_basic: executing
11395 09:30:35.812847 5 for randomisation
11396 09:30:35.816193 Opened device: /dev/dri/card0
11397 09:30:35.822648 Starting sub<14>[ 15.267059] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11398 09:30:35.832637 test: unused-mod<14>[ 15.275251] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11399 09:30:35.832757 ifier
11400 09:30:35.839080 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11401 09:30:35.845842 Test requirement not met in function i<14>[ 15.292017] [IGT] kms_addfb_basic: exiting, ret=77
11402 09:30:35.848731 gt_require_intel, file ../lib/drmtest.c:880:
11403 09:30:35.862510 Test requirement: is_intel_device(<8>[ 15.303400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11404 09:30:35.862591 fd)
11405 09:30:35.862827 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11407 09:30:35.869218 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11408 09:30:35.872381 Test requirement: is_intel_device(fd)
11409 09:30:35.879061 No KMS driver or no outputs, pip<14>[ 15.326029] [IGT] kms_addfb_basic: executing
11410 09:30:35.882126 es: 16, outputs: 0
11411 09:30:35.892073 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<14>[ 15.335510] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11412 09:30:35.902351 6.1.92-cip22 aa<14>[ 15.344469] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11413 09:30:35.902431 rch64)
11414 09:30:35.908552 Using IGT_SRANDOM=1718703036 for randomisation
11415 09:30:35.912049 Opened device: /dev/dri/card0
11416 09:30:35.915593 Starting <14>[ 15.362186] [IGT] kms_addfb_basic: exiting, ret=77
11417 09:30:35.918438 subtest: clobberred-modifier
11418 09:30:35.931984 Test requirement not met in function igt_require_i<8>[ 15.373426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11419 09:30:35.932243 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11421 09:30:35.935404 915, file ../lib/drmtest.c:885:
11422 09:30:35.938795 Test requirement: is_i915_device(fd)
11423 09:30:35.941825 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11424 09:30:35.952054 Test requirement not met in function igt_require_inte<14>[ 15.397107] [IGT] kms_addfb_basic: executing
11425 09:30:35.955078 l, file ../lib/drmtest.c:880:
11426 09:30:35.964896 Test requirement: is_intel_device<14>[ 15.407180] [IGT] kms_addfb_basic: starting subtest legacy-format
11427 09:30:35.964981 (fd)
11428 09:30:35.978067 Test requirement not met in function igt_require_intel, fi<14>[ 15.420364] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11429 09:30:35.978140 le ../lib/drmtest.c:880:
11430 09:30:35.981207 Test requirement: is_intel_device(fd)
11431 09:30:35.991073 No KMS driver or no outputs, pi<14>[ 15.435873] [IGT] kms_addfb_basic: exiting, ret=0
11432 09:30:35.991176 pes: 16, outputs: 0
11433 09:30:36.004992 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 a<8>[ 15.446873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11434 09:30:36.005082 arch64)
11435 09:30:36.005342 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11437 09:30:36.008008 Using IGT_SRANDOM=1718703036 for randomisation
11438 09:30:36.011033 Opened device: /dev/dri/card0
11439 09:30:36.014703 Starting subtest: invalid-smem-bo-on-discrete
11440 09:30:36.024609 Test requirement not met <14>[ 15.469035] [IGT] kms_addfb_basic: executing
11441 09:30:36.027608 in function igt_require_intel, file ../lib/drmtest.c:880:
11442 09:30:36.034737 Test requirement: is_<14>[ 15.480683] [IGT] kms_addfb_basic: starting subtest no-handle
11443 09:30:36.044182 intel_device(fd)<14>[ 15.487124] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11444 09:30:36.044287
11445 09:30:36.050900 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11446 09:30:36.057372 Test requirement n<14>[ 15.501272] [IGT] kms_addfb_basic: exiting, ret=0
11447 09:30:36.060694 ot met in function igt_require_intel, file ../lib/drmtest.c:880:
11448 09:30:36.070713 Test requireme<8>[ 15.513188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11449 09:30:36.071000 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11451 09:30:36.073776 nt: is_intel_device(fd)
11452 09:30:36.080587 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11453 09:30:36.083794 Test requirement: is_intel_device(fd)
11454 09:30:36.087409 No KMS drive<14>[ 15.535067] [IGT] kms_addfb_basic: executing
11455 09:30:36.094100 r or no outputs, pipes: 16, outputs: 0
11456 09:30:36.100882 IGT-Version: 1.28-ga44ebfe (aarch64) (Li<14>[ 15.546625] [IGT] kms_addfb_basic: starting subtest basic
11457 09:30:36.110574 nux: 6.1.92-cip2<14>[ 15.552791] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11458 09:30:36.110678 2 aarch64)
11459 09:30:36.113656 Using IGT_SRANDOM=1718703036 for randomisation
11460 09:30:36.120194 Opened device: /dev/<14>[ 15.566612] [IGT] kms_addfb_basic: exiting, ret=0
11461 09:30:36.123886 dri/card0
11462 09:30:36.126755 Starting subtest: legacy-format
11463 09:30:36.133882 Successfully fuzzed 10000 {bpp, dept<8>[ 15.578489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11464 09:30:36.134131 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11466 09:30:36.136669 h} variations
11467 09:30:36.140373 [1mSubtest legacy-format: SUCCESS (0.005s)[0m
11468 09:30:36.147124 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11469 09:30:36.153217 Test require<14>[ 15.600037] [IGT] kms_addfb_basic: executing
11470 09:30:36.156793 ment: is_intel_device(fd)
11471 09:30:36.166692 Test requirement not met in function igt_require_inte<14>[ 15.611364] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11472 09:30:36.176458 l, file ../lib/d<14>[ 15.618204] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11473 09:30:36.176560 rmtest.c:880:
11474 09:30:36.180079 Test requirement: is_intel_device(fd)
11475 09:30:36.186463 No KMS driver or no output<14>[ 15.632416] [IGT] kms_addfb_basic: exiting, ret=0
11476 09:30:36.189734 s, pipes: 16, outputs: 0
11477 09:30:36.199949 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11479 09:30:36.202910 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-ci<8>[ 15.644531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11480 09:30:36.202988 p22 aarch64)
11481 09:30:36.206472 Using IGT_SRANDOM=1718703036 for randomisation
11482 09:30:36.209932 Opened device: /dev/dri/card0
11483 09:30:36.213390 Starting subtest: no-handle
11484 09:30:36.219948 [1mSubtest no-handle: SUCCESS (0.000s<14>[ 15.666432] [IGT] kms_addfb_basic: executing
11485 09:30:36.220025 )[0m
11486 09:30:36.233211 Test requirement not met in function igt_require_intel, file ../lib/drmte<14>[ 15.677950] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11487 09:30:36.236422 st.c:880:
11488 09:30:36.242691 Test <14>[ 15.684751] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11489 09:30:36.246269 requirement: is_intel_device(fd)
11490 09:30:36.252921 Test requirement not met in function igt_requi<14>[ 15.699179] [IGT] kms_addfb_basic: exiting, ret=0
11491 09:30:36.256319 re_intel, file ../lib/drmtest.c:880:
11492 09:30:36.262946 Test requirement: is_intel_device(fd)
11493 09:30:36.269342 No <8>[ 15.710979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11494 09:30:36.269597 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11496 09:30:36.272415 KMS driver or no outputs, pipes: 16, outputs: 0
11497 09:30:36.278986 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11498 09:30:36.286133 Using IGT_SRANDOM=1718703036 for randomisat<14>[ 15.733187] [IGT] kms_addfb_basic: executing
11499 09:30:36.288887 ion
11500 09:30:36.288990 Opened device: /dev/dri/card0
11501 09:30:36.292309 Starting subtest: basic
11502 09:30:36.298904 [1mSubtest basic: <14>[ 15.744593] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11503 09:30:36.308745 SUCCESS (0.000s)<14>[ 15.751569] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11504 09:30:36.308874 [0m
11505 09:30:36.321964 Test requirement not met in function igt_require_intel, file ../lib/drmtes<14>[ 15.765848] [IGT] kms_addfb_basic: exiting, ret=0
11506 09:30:36.322072 t.c:880:
11507 09:30:36.325587 Test requirement: is_intel_device(fd)
11508 09:30:36.335214 Test requirement not met in fun<8>[ 15.777884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11509 09:30:36.335487 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11511 09:30:36.338904 ction igt_require_intel, file ../lib/drmtest.c:880:
11512 09:30:36.342242 Test requirement: is_intel_device(fd)
11513 09:30:36.348591 No KMS driver or no outputs, pipes: 16, outputs: 0
11514 09:30:36.355112 IGT-Version: 1.2<14>[ 15.799580] [IGT] kms_addfb_basic: executing
11515 09:30:36.358724 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11516 09:30:36.368401 Using IGT_SRANDOM=1718703036<14>[ 15.811263] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11517 09:30:36.374946 for randomisati<14>[ 15.818160] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11518 09:30:36.375046 on
11519 09:30:36.378502 Opened device: /dev/dri/card0
11520 09:30:36.381486 Starting subtest: bad-pitch-0
11521 09:30:36.388403 [1mSubtest ba<14>[ 15.832782] [IGT] kms_addfb_basic: exiting, ret=0
11522 09:30:36.391373 d-pitch-0: SUCCESS (0.000s)[0m
11523 09:30:36.401418 Test requirement not met in function igt_requir<8>[ 15.844486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11524 09:30:36.401746 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11526 09:30:36.404819 e_intel, file ../lib/drmtest.c:880:
11527 09:30:36.408114 Test requirement: is_intel_device(fd)
11528 09:30:36.414868 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11529 09:30:36.421350 <14>[ 15.866753] [IGT] kms_addfb_basic: executing
11530 09:30:36.425086 Test requirement: is_intel_device(fd)
11531 09:30:36.434529 No KMS driver or no outputs, pipes: 16, o<14>[ 15.878357] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11532 09:30:36.434685 utputs: 0
11533 09:30:36.441466 IGT-V<14>[ 15.885245] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11534 09:30:36.447988 ersion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11535 09:30:36.454500 Using IGT_SRANDOM<14>[ 15.899762] [IGT] kms_addfb_basic: exiting, ret=0
11536 09:30:36.458002 =1718703036 for randomisation
11537 09:30:36.461035 Opened device: /dev/dri/card0
11538 09:30:36.467502 Starting subtest: <8>[ 15.911585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11539 09:30:36.467755 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11541 09:30:36.471193 bad-pitch-32
11542 09:30:36.474192 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11543 09:30:36.480625 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11544 09:30:36.487340 Test requireme<14>[ 15.933644] [IGT] kms_addfb_basic: executing
11545 09:30:36.490724 nt: is_intel_device(fd)
11546 09:30:36.500804 Test requirement not met in function igt_require_intel,<14>[ 15.945151] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11547 09:30:36.510624 file ../lib/drm<14>[ 15.952398] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11548 09:30:36.510719 test.c:880:
11549 09:30:36.514169 Test requirement: is_intel_device(fd)
11550 09:30:36.520556 No KMS driver or no outputs,<14>[ 15.966788] [IGT] kms_addfb_basic: exiting, ret=0
11551 09:30:36.524001 pipes: 16, outputs: 0
11552 09:30:36.533815 IGT-Version: 1.28-ga44ebfe (aarch64) (Li<8>[ 15.978490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11553 09:30:36.534090 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11555 09:30:36.537158 nux: 6.1.92-cip22 aarch64)
11556 09:30:36.540162 Using IGT_SRANDOM=1718703036 for randomisation
11557 09:30:36.543697 Opened device: /dev/dri/card0
11558 09:30:36.546725 Starting subtest: bad-pitch-63
11559 09:30:36.553377 [1mSubtest bad-pitch<14>[ 15.999528] [IGT] kms_addfb_basic: executing
11560 09:30:36.556971 -63: SUCCESS (0.000s)[0m
11561 09:30:36.566824 Test requirement not met in function igt_require_inte<14>[ 16.011188] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11562 09:30:36.576507 l, file ../lib/d<14>[ 16.018006] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11563 09:30:36.576635 rmtest.c:880:
11564 09:30:36.580056 Test requirement: is_intel_device(fd)
11565 09:30:36.586705 Test requirement not met i<14>[ 16.032712] [IGT] kms_addfb_basic: exiting, ret=0
11566 09:30:36.593207 n function igt_require_intel, file ../lib/drmtest.c:880:
11567 09:30:36.603200 Test requirement: is_i<8>[ 16.044515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11568 09:30:36.603338 ntel_device(fd)
11569 09:30:36.603603 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11571 09:30:36.606340 No KMS driver or no outputs, pipes: 16, outputs: 0
11572 09:30:36.612837 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11573 09:30:36.622541 Using IGT_SRANDOM=1718703036 for random<14>[ 16.067088] [IGT] kms_addfb_basic: executing
11574 09:30:36.622639 isation
11575 09:30:36.626197 Opened device: /dev/dri/card0
11576 09:30:36.629340 Starting subtest: bad-pitch-128
11577 09:30:36.636268 [1mSub<14>[ 16.079629] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11578 09:30:36.642734 test bad-pitch-1<14>[ 16.086569] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11579 09:30:36.645710 28: SUCCESS (0.000s)[0m
11580 09:30:36.656110 Test requirement not met in function igt_require_intel<14>[ 16.101359] [IGT] kms_addfb_basic: exiting, ret=0
11581 09:30:36.659078 , file ../lib/drmtest.c:880:
11582 09:30:36.662718 Test requirement: is_intel_device(fd)
11583 09:30:36.669361 Test requir<8>[ 16.113111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11584 09:30:36.669613 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11586 09:30:36.676019 ement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11587 09:30:36.679120 Test requirement: is_intel_device(fd)
11588 09:30:36.689373 No KMS driver or no outputs, pipes: 16, outputs:<14>[ 16.135300] [IGT] kms_addfb_basic: executing
11589 09:30:36.689487 0
11590 09:30:36.695434 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11591 09:30:36.705567 Using IGT_SRANDOM=1718703036 for randomi<14>[ 16.148866] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11592 09:30:36.705697 sation
11593 09:30:36.715162 Opened d<14>[ 16.157094] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11594 09:30:36.718797 evice: /dev/dri/card0
11595 09:30:36.725131 Starting subtest: bad-pit<14>[ 16.170543] [IGT] kms_addfb_basic: exiting, ret=0
11596 09:30:36.725217 ch-256
11597 09:30:36.728767 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11598 09:30:36.738367 Test requirement not me<8>[ 16.181549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11599 09:30:36.738623 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11601 09:30:36.745347 t in function igt_require_intel, file ../lib/drmtest.c:880:
11602 09:30:36.748659 Test requirement: is_intel_device(fd)
11603 09:30:36.758293 Test requirement not met in function igt_require_intel, file<14>[ 16.204175] [IGT] kms_addfb_basic: executing
11604 09:30:36.761750 ../lib/drmtest.c:880:
11605 09:30:36.764943 Test requirement: is_intel_device(fd)
11606 09:30:36.774740 No KMS driver or no outputs, pipes: 16, outputs: <14>[ 16.217726] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11607 09:30:36.774851 0
11608 09:30:36.784692 IGT-Version: <14>[ 16.225691] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11609 09:30:36.788261 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11610 09:30:36.794912 Using IGT<14>[ 16.238736] [IGT] kms_addfb_basic: exiting, ret=0
11611 09:30:36.798022 _SRANDOM=1718703036 for randomisation
11612 09:30:36.801055 Opened device: /dev/dri/card0
11613 09:30:36.808123 Starting s<8>[ 16.250938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11614 09:30:36.808373 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11616 09:30:36.810947 ubtest: bad-pitch-1024
11617 09:30:36.814352 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11618 09:30:36.821042 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11619 09:30:36.827439 Te<14>[ 16.273402] [IGT] kms_addfb_basic: executing
11620 09:30:36.830768 st requirement: is_intel_device(fd)
11621 09:30:36.844080 Test requirement not met in function igt_require_intel, file ../lib/drmtest<14>[ 16.286625] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11622 09:30:36.844167 .c:880:
11623 09:30:36.853865 Test re<14>[ 16.295232] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11624 09:30:36.857294 quirement: is_intel_device(fd)
11625 09:30:36.863872 No KMS driver or<14>[ 16.308312] [IGT] kms_addfb_basic: exiting, ret=0
11626 09:30:36.867253 no outputs, pipes: 16, outputs: 0
11627 09:30:36.877246 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<8>[ 16.319353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11628 09:30:36.877494 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11630 09:30:36.880524 6.1.92-cip22 aarch64)
11631 09:30:36.883879 Using IGT_SRANDOM=1718703036 for randomisation
11632 09:30:36.887305 Opened device: /dev/dri/card0
11633 09:30:36.890843 Starting subtest: bad-pitch-999
11634 09:30:36.897080 [1mSubtest bad-pitch-99<14>[ 16.341988] [IGT] kms_addfb_basic: executing
11635 09:30:36.897157 9: SUCCESS (0.000s)[0m
11636 09:30:36.907349 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11637 09:30:36.913911 Tes<14>[ 16.356101] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11638 09:30:36.920043 t requirement: i<14>[ 16.363706] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11639 09:30:36.923612 s_intel_device(fd)
11640 09:30:36.933690 Test requirement not met in function igt_req<14>[ 16.376770] [IGT] kms_addfb_basic: exiting, ret=0
11641 09:30:36.936932 uire_intel, file ../lib/drmtest.c:880:
11642 09:30:36.939885 Test requirement: is_intel_device(fd)
11643 09:30:36.946596 N<8>[ 16.389114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11644 09:30:36.946844 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11646 09:30:36.950187 o KMS driver or no outputs, pipes: 16, outputs: 0
11647 09:30:36.956855 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11648 09:30:36.966579 Using IGT_SRANDOM=1718703036 for randomis<14>[ 16.411401] [IGT] kms_addfb_basic: executing
11649 09:30:36.966656 ation
11650 09:30:36.969884 Opened device: /dev/dri/card0
11651 09:30:36.969962 Starting subtest: bad-pitch-65536
11652 09:30:36.976561 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11653 09:30:36.982988 Test<14>[ 16.426973] [IGT] kms_addfb_basic: starting subtest master-rmfb
11654 09:30:36.989664 requirement not<14>[ 16.433915] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11655 09:30:36.999726 met in function igt_require_int<14>[ 16.444346] [IGT] kms_addfb_basic: exiting, ret=0
11656 09:30:37.003154 el, file ../lib/drmtest.c:880:
11657 09:30:37.006478 Test requirement: is_intel_device(fd)
11658 09:30:37.012599 Test requ<8>[ 16.455841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11659 09:30:37.012885 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11661 09:30:37.019233 irement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11662 09:30:37.022694 Test requirement: is_intel_device(fd)
11663 09:30:37.032503 No KMS driver or no outputs, pipes: 16, output<14>[ 16.477628] [IGT] kms_addfb_basic: executing
11664 09:30:37.032582 s: 0
11665 09:30:37.039227 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11666 09:30:37.042580 Using IGT_SRANDOM=1718703036 for randomisation
11667 09:30:37.052465 Opened device: /dev/dr<14>[ 16.495282] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11668 09:30:37.052544 i/card0
11669 09:30:37.062761 Startin<14>[ 16.502792] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11670 09:30:37.068960 g subtest: inval<14>[ 16.512667] [IGT] kms_addfb_basic: exiting, ret=0
11671 09:30:37.069038 id-get-prop-any
11672 09:30:37.082290 [1mSubtest invalid-get-prop-any: SUCCESS (0.00<8>[ 16.524518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11673 09:30:37.082370 0s)[0m
11674 09:30:37.082602 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11676 09:30:37.088640 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11677 09:30:37.092001 Test requirement: is_intel_device(fd)
11678 09:30:37.098936 Test requirement not met in <14>[ 16.546402] [IGT] kms_addfb_basic: executing
11679 09:30:37.105480 function igt_require_intel, file ../lib/drmtest.c:880:
11680 09:30:37.108861 Test requirement: is_intel_device(fd)
11681 09:30:37.112066 No KMS driver or no outputs, pipes: 16, outputs: 0
11682 09:30:37.121986 IGT-Version: <14>[ 16.563872] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11683 09:30:37.125064 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11684 09:30:37.132166 Using IGT_SRANDOM=1718703036 for randomisation
11685 09:30:37.132243 Opened device: /dev/dri/card0
11686 09:30:37.134961 Starting subtest: invalid-get-prop
11687 09:30:37.141945 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11688 09:30:37.148498 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11689 09:30:37.151805 Test requirement: is_intel_device(fd)
11690 09:30:37.158014 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11691 09:30:37.161761 Test requirement: is_intel_device(fd)
11692 09:30:37.164851 No KMS driver or no outputs, pipes: 16, outputs: 0
11693 09:30:37.171602 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11694 09:30:37.178257 Using IGT_SRANDOM=1718703037 for randomisation
11695 09:30:37.178385 Opened device: /dev/dri/card0
11696 09:30:37.181421 Starting subtest: invalid-set-prop-any
11697 09:30:37.188005 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11698 09:30:37.194495 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11699 09:30:37.197949 Test requirement: is_intel_device(fd)
11700 09:30:37.204515 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11701 09:30:37.207637 Test requirement: is_intel_device(fd)
11702 09:30:37.214542 No KMS driver or no outputs, pipes: 16, outputs: 0
11703 09:30:37.220977 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11704 09:30:37.224189 Using IGT_SRANDOM=1718703037 for randomisation
11705 09:30:37.227413 Opened device: /dev/dri/card0
11706 09:30:37.230785 Starting subtest: invalid-set-prop
11707 09:30:37.234418 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11708 09:30:37.240911 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11709 09:30:37.244291 Test requirement: is_intel_device(fd)
11710 09:30:37.250493 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11711 09:30:37.254268 Test requirement: is_intel_device(fd)
11712 09:30:37.260541 No KMS driver or no outputs, pipes: 16, outputs: 0
11713 09:30:37.266921 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11714 09:30:37.270624 Using IGT_SRANDOM=1718703037 for randomisation
11715 09:30:37.273850 Opened device: /dev/dri/card0
11716 09:30:37.273951 Starting subtest: master-rmfb
11717 09:30:37.280503 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11718 09:30:37.286794 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11719 09:30:37.290193 Test requirement: is_intel_device(fd)
11720 09:30:37.296880 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11721 09:30:37.299931 Test requirement: is_intel_device(fd)
11722 09:30:37.306554 No KMS driver or no outputs, pipes: 16, outputs: 0
11723 09:30:37.310338 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11724 09:30:37.316613 Using IGT_SRANDOM=1718703037 for randomisation
11725 09:30:37.316730 Opened device: /dev/dri/card0
11726 09:30:37.319886 Starting subtest: addfb25-modifier-no-flag
11727 09:30:37.326826 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11728 09:30:37.333486 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11729 09:30:37.336327 Test requirement: is_intel_device(fd)
11730 09:30:37.343456 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11731 09:30:37.349880 Test requirement: is_intel_device(fd)
11732 09:30:37.353094 No KMS driver or no outputs, pipes: 16, outputs: 0
11733 09:30:37.359586 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11734 09:30:37.363153 Using IGT_SRANDOM=1718703037 for randomisation
11735 09:30:37.366670 Opened device: /dev/dri/card0
11736 09:30:37.369586 Starting subtest: addfb25-bad-modifier
11737 09:30:37.379628 (kms_addfb_basic:446) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11738 09:30:37.396333 (kms_addfb_basic:446) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11739 09:30:37.403037 (kms_addfb_basic:446) CRITICAL: error: 0 != -1
11740 09:30:37.403115 Stack trace:
11741 09:30:37.406034 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11742 09:30:37.409058 #1 [<unknown>+0xe96e4358]
11743 09:30:37.412795 #2 [<unknown>+0xe96e5fbc]
11744 09:30:37.412871 #3 [<unknown>+0xe96e156c]
11745 09:30:37.415885 #4 [__libc_init_first+0x80]
11746 09:30:37.418955 #5 [__libc_start_main+0x98]
11747 09:30:37.422553 #6 [<unknown>+0xe96e15b0]
11748 09:30:37.425541 Subtest addfb25-bad-modifier failed.
11749 09:30:37.425618 **** DEBUG ****
11750 09:30:37.435765 (kms_addfb_basic:446) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11751 09:30:37.445415 (kms_addfb_basic:446) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11752 09:30:37.468818 (kms_addfb_basic:446) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)<14>[ 16.911521] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11753 09:30:37.475460 ))), (&f)) == -1<14>[ 16.920572] [IGT] kms_addfb_basic: exiting, ret=98
11754 09:30:37.475550
11755 09:30:37.478910 (kms_addfb_basic:446) CRITICAL: error: 0 != -1
11756 09:30:37.492056 (kms_addfb_basic:446) igt_core<8>[ 16.932544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11757 09:30:37.492140 -INFO: Stack trace:
11758 09:30:37.492381 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11760 09:30:37.498630 (kms_addfb_basic:446) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11761 09:30:37.505311 (kms_addfb_basic:446) igt_core-INFO: #1 [<unknown>+0xe96e4358]
11762 09:30:37.511698 (kms_addfb_basic:446) igt_core-INFO: #2 [<unknown>+0xe96e5fbc]
11763 09:30:37.517860 (kms_addfb_basic:446) igt_core-IN<14>[ 16.964889] [IGT] kms_addfb_basic: executing
11764 09:30:37.521516 FO: #3 [<unknown>+0xe96e156c]
11765 09:30:37.528285 (kms_addfb_basic:446) igt_core-INFO: #4 [__libc_init_first+0x80]
11766 09:30:37.534755 (kms_addfb_basic:446) igt_core-INFO: #5 [__libc_start_main+0x98]
11767 09:30:37.538191 (kms_ad<14>[ 16.983727] [IGT] kms_addfb_basic: exiting, ret=77
11768 09:30:37.544240 dfb_basic:446) igt_core-INFO: #6 [<unknown>+0xe96e15b0]
11769 09:30:37.554731 **** <8>[ 16.995589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11770 09:30:37.554812 END ****
11771 09:30:37.555044 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11773 09:30:37.557485 [1mSubtest addfb25-bad-modifier: FAIL (0.339s)[0m
11774 09:30:37.567858 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11775 09:30:37.570856 Test requir<14>[ 17.017949] [IGT] kms_addfb_basic: executing
11776 09:30:37.574110 ement: is_intel_device(fd)
11777 09:30:37.580633 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11778 09:30:37.584215 Test requirement: is_intel_device(fd)
11779 09:30:37.590705 No KMS dr<14>[ 17.035813] [IGT] kms_addfb_basic: exiting, ret=77
11780 09:30:37.594391 iver or no outputs, pipes: 16, outputs: 0
11781 09:30:37.603961 IGT-Version: 1.28-ga4<8>[ 17.046516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11782 09:30:37.604216 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11784 09:30:37.607120 4ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11785 09:30:37.613787 Using IGT_SRANDOM=1718703037 for randomisation
11786 09:30:37.613866 Opened device: /dev/dri/card0
11787 09:30:37.623996 Test requirement not met in functi<14>[ 17.068945] [IGT] kms_addfb_basic: executing
11788 09:30:37.627033 on igt_require_intel, file ../lib/drmtest.c:880:
11789 09:30:37.630656 Test requirement: is_intel_device(fd)
11790 09:30:37.637129 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11791 09:30:37.640598 Test re<14>[ 17.086896] [IGT] kms_addfb_basic: exiting, ret=77
11792 09:30:37.657201 quirement not met in function igt_require_intel, file ../lib/drm<8>[ 17.097542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11793 09:30:37.657294 test.c:880:
11794 09:30:37.657543 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11796 09:30:37.660113 Test requirement: is_intel_device(fd)
11797 09:30:37.666843 No KMS driver or no outputs, pipes: 16, outputs: 0
11798 09:30:37.673582 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip2<14>[ 17.120753] [IGT] kms_addfb_basic: executing
11799 09:30:37.676656 2 aarch64)
11800 09:30:37.680253 Using IGT_SRANDOM=1718703037 for randomisation
11801 09:30:37.683232 Opened device: /dev/dri/card0
11802 09:30:37.693185 Test requirement not met in function igt_require_intel, file ../lib/d<14>[ 17.138924] [IGT] kms_addfb_basic: exiting, ret=77
11803 09:30:37.696506 rmtest.c:880:
11804 09:30:37.700086 Test requirement: is_intel_device(fd)
11805 09:30:37.706492 [1mSubtes<8>[ 17.149911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11806 09:30:37.706763 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11808 09:30:37.710068 t addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11809 09:30:37.719784 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11810 09:30:37.726554 Test requirement: is_intel_devi<14>[ 17.172315] [IGT] kms_addfb_basic: executing
11811 09:30:37.726631 ce(fd)
11812 09:30:37.729629 No KMS driver or no outputs, pipes: 16, outputs: 0
11813 09:30:37.736262 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11814 09:30:37.746421 Using IGT_SRANDOM=1718703037 for<14>[ 17.189905] [IGT] kms_addfb_basic: exiting, ret=77
11815 09:30:37.746500 randomisation
11816 09:30:37.749935 Opened device: /dev/dri/card0
11817 09:30:37.759598 Test requirement <8>[ 17.200890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11818 09:30:37.759844 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11820 09:30:37.766057 not met in function igt_require_intel, file ../lib/drmtest.c:880:
11821 09:30:37.769745 Test requirement: is_intel_device(fd)
11822 09:30:37.776212 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0<14>[ 17.223082] [IGT] kms_addfb_basic: executing
11823 09:30:37.779489 .000s)[0m
11824 09:30:37.785970 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11825 09:30:37.789568 Test requirement: is_intel_device(fd)
11826 09:30:37.795996 No KMS driver or no outpu<14>[ 17.241346] [IGT] kms_addfb_basic: exiting, ret=77
11827 09:30:37.799004 ts, pipes: 16, outputs: 0
11828 09:30:37.809051 IGT-Version: 1.28-ga44ebfe (aarch64) <8>[ 17.252254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11829 09:30:37.809297 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11831 09:30:37.812596 (Linux: 6.1.92-cip22 aarch64)
11832 09:30:37.815769 Using IGT_SRANDOM=1718703037 for randomisation
11833 09:30:37.818995 Opened device: /dev/dri/card0
11834 09:30:37.828843 Test requirement not met in function igt_require_i<14>[ 17.274622] [IGT] kms_addfb_basic: executing
11835 09:30:37.832574 ntel, file ../lib/drmtest.c:880:
11836 09:30:37.835712 Test requirement: is_intel_device(fd)
11837 09:30:37.842283 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11838 09:30:37.848835 Tes<14>[ 17.292179] [IGT] kms_addfb_basic: exiting, ret=77
11839 09:30:37.852295 t requirement: is_intel_device(fd)
11840 09:30:37.862393 [1mSubtest basic-x-tiled-le<8>[ 17.303141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11841 09:30:37.862470 gacy: SKIP (0.000s)[0m
11842 09:30:37.862698 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11844 09:30:37.868834 No KMS driver or no outputs, pipes: 16, outputs: 0
11845 09:30:37.871844 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11846 09:30:37.878733 Using IGT_SRAND<14>[ 17.325650] [IGT] kms_addfb_basic: executing
11847 09:30:37.882321 OM=1718703037 for randomisation
11848 09:30:37.885144 Opened device: /dev/dri/card0
11849 09:30:37.892115 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11850 09:30:37.898627 Test require<14>[ 17.343240] [IGT] kms_addfb_basic: exiting, ret=77
11851 09:30:37.902095 ment: is_intel_device(fd)
11852 09:30:37.911871 Test requirement not met in function <8>[ 17.354000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11853 09:30:37.912115 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11855 09:30:37.914960 igt_require_intel, file ../lib/drmtest.c:880:
11856 09:30:37.918563 Test requirement: is_intel_device(fd)
11857 09:30:37.921903 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11858 09:30:37.927990 No KMS driver or<14>[ 17.375078] [IGT] kms_addfb_basic: executing
11859 09:30:37.931276 no outputs, pipes: 16, outputs: 0
11860 09:30:37.938254 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11861 09:30:37.941276 Using IGT_SRANDOM=1718703037 for randomisation
11862 09:30:37.947900 Opened d<14>[ 17.393028] [IGT] kms_addfb_basic: exiting, ret=77
11863 09:30:37.951580 evice: /dev/dri/card0
11864 09:30:37.961627 Test requirement not met in function igt_<8>[ 17.403933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11865 09:30:37.961875 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11867 09:30:37.964668 require_intel, file ../lib/drmtest.c:880:
11868 09:30:37.967745 Test requirement: is_intel_device(fd)
11869 09:30:37.978032 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:<14>[ 17.425303] [IGT] kms_addfb_basic: executing
11870 09:30:37.981106 880:
11871 09:30:37.984808 Test requirement: is_intel_device(fd)
11872 09:30:37.987899 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11873 09:30:37.990912 No KMS driver or no outputs, pipes: 16, outputs: 0
11874 09:30:37.997934 IGT-Version<14>[ 17.442939] [IGT] kms_addfb_basic: exiting, ret=77
11875 09:30:38.004381 : 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11876 09:30:38.010838 Using I<8>[ 17.453936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11877 09:30:38.011084 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11879 09:30:38.014412 GT_SRANDOM=1718703037 for randomisation
11880 09:30:38.017520 Opened device: /dev/dri/card0
11881 09:30:38.024260 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11882 09:30:38.027753 Test<14>[ 17.474654] [IGT] kms_addfb_basic: executing
11883 09:30:38.030639 requirement: is_intel_device(fd)
11884 09:30:38.041043 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11885 09:30:38.044251 Test requirement: is_intel_device(fd)
11886 09:30:38.047519 [<14>[ 17.492782] [IGT] kms_addfb_basic: exiting, ret=77
11887 09:30:38.054180 1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11888 09:30:38.060866 No KMS driver<8>[ 17.504234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11889 09:30:38.061113 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11891 09:30:38.063824 or no outputs, pipes: 16, outputs: 0
11892 09:30:38.071052 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11893 09:30:38.074035 Using IGT_SRANDOM=1718703038 for randomisation
11894 09:30:38.080494 Opene<14>[ 17.525348] [IGT] kms_addfb_basic: executing
11895 09:30:38.080571 d device: /dev/dri/card0
11896 09:30:38.090329 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11897 09:30:38.093941 Test requirement: is_intel_device(fd)
11898 09:30:38.096947 Test requir<14>[ 17.543408] [IGT] kms_addfb_basic: exiting, ret=77
11899 09:30:38.110247 ement not met in function igt_require_intel, file ../lib/drmtest<8>[ 17.554228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11900 09:30:38.110323 .c:880:
11901 09:30:38.110550 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11903 09:30:38.113653 Test requirement: is_intel_device(fd)
11904 09:30:38.120498 No KMS driver or no outputs, pipes: 16, outputs: 0
11905 09:30:38.123699 [1mSubtest size-max: SKIP (0.000s)[0m
11906 09:30:38.130031 IGT-Version: 1.28-g<14>[ 17.575151] [IGT] kms_addfb_basic: executing
11907 09:30:38.133615 a44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11908 09:30:38.136494 Using IGT_SRANDOM=1718703038 for randomisation
11909 09:30:38.139900 Opened device: /dev/dri/card0
11910 09:30:38.150141 Test requirement not met in func<14>[ 17.592997] [IGT] kms_addfb_basic: exiting, ret=77
11911 09:30:38.153457 tion igt_require_intel, file ../lib/drmtest.c:880:
11912 09:30:38.162973 Test require<8>[ 17.604075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11913 09:30:38.163050 ment: is_intel_device(fd)
11914 09:30:38.163278 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11916 09:30:38.173239 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11917 09:30:38.176217 Test requirement: is_intel_device(fd)
11918 09:30:38.179885 No KMS dri<14>[ 17.626937] [IGT] kms_addfb_basic: executing
11919 09:30:38.183348 ver or no outputs, pipes: 16, outputs: 0
11920 09:30:38.190000 [1mSubtest too-wide: SKIP (0.000s)[0m
11921 09:30:38.192972 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11922 09:30:38.199549 Using IGT<14>[ 17.644728] [IGT] kms_addfb_basic: exiting, ret=77
11923 09:30:38.203207 _SRANDOM=1718703038 for randomisation
11924 09:30:38.212956 Opened device: /dev/dri/c<8>[ 17.655584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11925 09:30:38.213034 ard0
11926 09:30:38.213278 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11928 09:30:38.222711 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11929 09:30:38.226142 Test requirement: is_intel_device(fd)
11930 09:30:38.232495 Test requirement not met in fun<14>[ 17.677537] [IGT] kms_addfb_basic: executing
11931 09:30:38.236221 ction igt_require_intel, file ../lib/drmtest.c:880:
11932 09:30:38.239578 Test requirement: is_intel_device(fd)
11933 09:30:38.245695 No KMS driver or no outputs, pipes: 16, outputs: 0
11934 09:30:38.249065 <14>[ 17.695611] [IGT] kms_addfb_basic: exiting, ret=77
11935 09:30:38.252691 [1mSubtest too-high: SKIP (0.000s)[0m
11936 09:30:38.262728 IGT-Version: 1.28-ga44e<8>[ 17.705513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11937 09:30:38.262976 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11939 09:30:38.265696 bfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11940 09:30:38.272157 Using IGT_SRANDOM=1718703038 for randomisation
11941 09:30:38.275656 Opened device: /dev/dri/card0
11942 09:30:38.282424 Test requirement not met in function<14>[ 17.727622] [IGT] kms_addfb_basic: executing
11943 09:30:38.285637 igt_require_intel, file ../lib/drmtest.c:880:
11944 09:30:38.288892 Test requirement: is_intel_device(fd)
11945 09:30:38.302072 Test requirement not met in function igt_require_intel, file ../lib/drmte<14>[ 17.745717] [IGT] kms_addfb_basic: exiting, ret=77
11946 09:30:38.302151 st.c:880:
11947 09:30:38.305143 Test requirement: is_intel_device(fd)
11948 09:30:38.315034 No KMS driver <8>[ 17.756716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11949 09:30:38.315283 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11951 09:30:38.318859 or no outputs, pipes: 16, outputs: 0
11952 09:30:38.321851 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11953 09:30:38.328459 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11954 09:30:38.335213 Using IGT<14>[ 17.779108] [IGT] kms_addfb_basic: executing
11955 09:30:38.338344 _SRANDOM=1718703038 for randomisation
11956 09:30:38.338420 Opened device: /dev/dri/card0
11957 09:30:38.348434 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11958 09:30:38.352004 Test r<14>[ 17.797618] [IGT] kms_addfb_basic: exiting, ret=77
11959 09:30:38.355312 equirement: is_intel_device(fd)
11960 09:30:38.364875 Test requirement not met in fun<8>[ 17.808274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11961 09:30:38.365123 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11963 09:30:38.371765 ction igt_require_intel, file ..<8>[ 17.818168] <LAVA_SIGNAL_TESTSET STOP>
11964 09:30:38.372009 Received signal: <TESTSET> STOP
11965 09:30:38.372071 Closing test_set kms_addfb_basic
11966 09:30:38.375122 /lib/drmtest.c:880:
11967 09:30:38.378113 Test requirement: is_intel_device(fd)
11968 09:30:38.381784 No KMS driver or no outputs, pipes: 16, outputs: 0
11969 09:30:38.384794 [1mSubtest small-bo: SKIP (0.000s)[0m
11970 09:30:38.395019 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip<8>[ 17.840380] <LAVA_SIGNAL_TESTSET START kms_atomic>
11971 09:30:38.395265 Received signal: <TESTSET> START kms_atomic
11972 09:30:38.395329 Starting test_set kms_atomic
11973 09:30:38.398458 22 aarch64)
11974 09:30:38.401191 Using IGT_SRANDOM=1718703038 for randomisation
11975 09:30:38.404747 Opened device: /dev/dri/card0
11976 09:30:38.411502 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11977 09:30:38.418144 Test requirement<14>[ 17.863277] [IGT] kms_atomic: executing
11978 09:30:38.421141 : is_intel_devic<14>[ 17.868054] [IGT] kms_atomic: exiting, ret=77
11979 09:30:38.424854 e(fd)
11980 09:30:38.434668 Test requirement not met in function igt_require_intel, f<8>[ 17.878536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11981 09:30:38.434913 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11983 09:30:38.438128 ile ../lib/drmtest.c:880:
11984 09:30:38.441174 Test requirement: is_intel_device(fd)
11985 09:30:38.444774 No KMS driver or no outputs, pipes: 16, outputs: 0
11986 09:30:38.454264 [1mSubtest bo-too-small-due-to-tiling: SK<14>[ 17.900475] [IGT] kms_atomic: executing
11987 09:30:38.454341 IP (0.000s)[0m
11988 09:30:38.461266 <14>[ 17.905504] [IGT] kms_atomic: exiting, ret=77
11989 09:30:38.461342
11990 09:30:38.474309 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch<8>[ 17.915885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11991 09:30:38.474386 64)
11992 09:30:38.474613 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11994 09:30:38.477458 Using IGT_SRANDOM=1718703038 for randomisation
11995 09:30:38.480607 Opened device: /dev/dri/card0
11996 09:30:38.490499 Test requirement not met in function igt_require_intel, file ../lib/drmtest.<14>[ 17.937967] [IGT] kms_atomic: executing
11997 09:30:38.490577 c:880:
11998 09:30:38.497578 Test req<14>[ 17.943150] [IGT] kms_atomic: exiting, ret=77
11999 09:30:38.500398 uirement: is_intel_device(fd)
12000 09:30:38.510374 Test requirement not met in funct<8>[ 17.953514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
12001 09:30:38.510618 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
12003 09:30:38.517160 ion igt_require_intel, file ../lib/drmtest.c:880:
12004 09:30:38.520391 Test requirement: is_intel_device(fd)
12005 09:30:38.523995 No KMS driver or no outputs, pipes: 16, outputs: 0
12006 09:30:38.530037 [1mSubtest addfb2<14>[ 17.976675] [IGT] kms_atomic: executing
12007 09:30:38.536788 5-y-tiled-legacy<14>[ 17.981918] [IGT] kms_atomic: exiting, ret=77
12008 09:30:38.536865 : SKIP (0.000s)[0m
12009 09:30:38.550083 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<8>[ 17.992288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
12010 09:30:38.550376 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
12012 09:30:38.553292 : 6.1.92-cip22 aarch64)
12013 09:30:38.556921 Using IGT_SRANDOM=1718703038 for randomisation
12014 09:30:38.559881 Opened device: /dev/dri/card0
12015 09:30:38.567001 Test requirement not met in function igt_require_intel, <14>[ 18.013994] [IGT] kms_atomic: executing
12016 09:30:38.573483 file ../lib/drmt<14>[ 18.019515] [IGT] kms_atomic: exiting, ret=77
12017 09:30:38.576456 est.c:880:
12018 09:30:38.580045 Test requirement: is_intel_device(fd)
12019 09:30:38.586697 Test requirem<8>[ 18.030007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
12020 09:30:38.586942 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
12022 09:30:38.592892 ent not met in function igt_require_intel, file ../lib/drmtest.c:880:
12023 09:30:38.596357 Test requirement: is_intel_device(fd)
12024 09:30:38.599444 No KMS driver or no outputs, pipes: 16, outputs: 0
12025 09:30:38.606319 [1mSubtest ad<14>[ 18.051626] [IGT] kms_atomic: executing
12026 09:30:38.612885 dfb25-yf-tiled-l<14>[ 18.057550] [IGT] kms_atomic: exiting, ret=77
12027 09:30:38.612964 egacy: SKIP (0.000s)[0m
12028 09:30:38.626200 IGT-Version: 1.28-ga44ebfe (aarch64) (<8>[ 18.067742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
12029 09:30:38.626281 Linux: 6.1.92-cip22 aarch64)
12030 09:30:38.626527 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
12032 09:30:38.632945 Using IGT_SRANDOM=1718703038 for randomisation
12033 09:30:38.635963 Opened device: /dev/dri/card0
12034 09:30:38.642850 Test requirement not met in function igt_require_in<14>[ 18.089774] [IGT] kms_atomic: executing
12035 09:30:38.649363 tel, file ../lib<14>[ 18.095114] [IGT] kms_atomic: exiting, ret=77
12036 09:30:38.649444 /drmtest.c:880:
12037 09:30:38.652907 Test requirement: is_intel_device(fd)
12038 09:30:38.662787 Test req<8>[ 18.105141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
12039 09:30:38.663035 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
12041 09:30:38.669285 uirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12042 09:30:38.672568 Test requirement: is_intel_device(fd)
12043 09:30:38.675963 No KMS driver or no outputs, pipes: 16, outputs: 0
12044 09:30:38.682592 [1mSubte<14>[ 18.128125] [IGT] kms_atomic: executing
12045 09:30:38.689213 st addfb25-y-til<14>[ 18.133913] [IGT] kms_atomic: exiting, ret=77
12046 09:30:38.692702 ed-small-legacy: SKIP (0.000s)[0m
12047 09:30:38.702315 IGT-Version: 1.28-ga44ebfe (<8>[ 18.144230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
12048 09:30:38.702562 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12050 09:30:38.705999 aarch64) (Linux: 6.1.92-cip22 aarch64)
12051 09:30:38.708973 Using IGT_SRANDOM=1718703038 for randomisation
12052 09:30:38.712487 Opened device: /dev/dri/card0
12053 09:30:38.719466 Test requirement not met in function igt_<14>[ 18.167299] [IGT] kms_atomic: executing
12054 09:30:38.725518 require_intel, f<14>[ 18.172016] [IGT] kms_atomic: exiting, ret=77
12055 09:30:38.728933 ile ../lib/drmtest.c:880:
12056 09:30:38.739281 Test requirement: is_intel_device(fd)<8>[ 18.182353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12057 09:30:38.739359
12058 09:30:38.739587 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12060 09:30:38.745871 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12061 09:30:38.749006 Test requirement: is_intel_device(fd)
12062 09:30:38.758869 No KMS driver or no outputs, pipes:<14>[ 18.204162] [IGT] kms_atomic: executing
12063 09:30:38.758951 16, outputs: 0
12064 09:30:38.762514 <14>[ 18.209547] [IGT] kms_atomic: exiting, ret=77
12065 09:30:38.765589
12066 09:30:38.769375 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
12067 09:30:38.778605 IGT-Version: 1.<8>[ 18.219715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12068 09:30:38.778913 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12070 09:30:38.782162 28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12071 09:30:38.785247 Using IGT_SRANDOM=1718703038 for randomisation
12072 09:30:38.788596 Opened device: /dev/dri/card0
12073 09:30:38.798928 No KMS driver or no outputs, pipes: 16, outp<14>[ 18.242892] [IGT] kms_atomic: executing
12074 09:30:38.799053 uts: 0
12075 09:30:38.801976 [1mSubt<14>[ 18.248925] [IGT] kms_atomic: exiting, ret=77
12076 09:30:38.808636 est plane-overlay-legacy: SKIP (0.000s)[0m
12077 09:30:38.815209 IGT-Version: 1.28-g<8>[ 18.258942] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12078 09:30:38.815520 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12080 09:30:38.821735 a44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12081 09:30:38.825234 Using IGT_SRANDOM=1718703038 for randomisation
12082 09:30:38.828383 Opened device: /dev/dri/card0
12083 09:30:38.835188 No KMS driver or no outputs, pip<14>[ 18.281572] [IGT] kms_atomic: executing
12084 09:30:38.841603 es: 16, outputs:<14>[ 18.286640] [IGT] kms_atomic: exiting, ret=77
12085 09:30:38.841734 0
12086 09:30:38.845135 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
12087 09:30:38.855230 IGT-Ver<8>[ 18.296679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12088 09:30:38.855511 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12090 09:30:38.861673 sion: 1.28-ga44ebfe (aarch64) (L<8>[ 18.306852] <LAVA_SIGNAL_TESTSET STOP>
12091 09:30:38.861921 Received signal: <TESTSET> STOP
12092 09:30:38.861985 Closing test_set kms_atomic
12093 09:30:38.865357 inux: 6.1.92-cip22 aarch64)
12094 09:30:38.868446 Using IGT_SRANDOM=1718703038 for randomisation
12095 09:30:38.871623 Opened device: /dev/dri/card0
12096 09:30:38.875294 No KMS driver or no outputs, pipes: 16, outputs: 0
12097 09:30:38.884966 [1mSubtest plane-primary-overlay-mutable-zpos: <8>[ 18.329301] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12098 09:30:38.885226 Received signal: <TESTSET> START kms_flip_event_leak
12099 09:30:38.885293 Starting test_set kms_flip_event_leak
12100 09:30:38.887938 SKIP (0.000s)[0m
12101 09:30:38.891871 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12102 09:30:38.897853 Using IGT_SRANDOM=1718703038 for randomisation
12103 09:30:38.904598 Opened device: /dev/dri/c<14>[ 18.350171] [IGT] kms_flip_event_leak: executing
12104 09:30:38.904755 ard0
12105 09:30:38.911310 No KMS dri<14>[ 18.355821] [IGT] kms_flip_event_leak: exiting, ret=77
12106 09:30:38.914919 ver or no outputs, pipes: 16, outputs: 0
12107 09:30:38.924212 [1mSubtest plane-immu<8>[ 18.366817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12108 09:30:38.924325 table-zpos: SKIP (0.000s)[0m
12109 09:30:38.924557 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12111 09:30:38.931255 I<8>[ 18.375657] <LAVA_SIGNAL_TESTSET STOP>
12112 09:30:38.931516 Received signal: <TESTSET> STOP
12113 09:30:38.931580 Closing test_set kms_flip_event_leak
12114 09:30:38.934551 GT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12115 09:30:38.941767 Using IGT_SRANDOM=1718703038 for randomisation
12116 09:30:38.941905 Opened device: /dev/dri/card0
12117 09:30:38.951321 No KMS driver or no outputs, pipes: 16, output<8>[ 18.397590] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12118 09:30:38.951719 s: 0
12119 09:30:38.952207 Received signal: <TESTSET> START kms_prop_blob
12120 09:30:38.952469 Starting test_set kms_prop_blob
12121 09:30:38.957453 [1mSubtest test-only: SKIP (0.000s)[0m
12122 09:30:38.961181 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12123 09:30:38.968216 Using IGT_SRANDOM=1718703038 for randomisation
12124 09:30:38.968767 Opened device: /dev/dri/card0
12125 09:30:38.974116 No KMS driver<14>[ 18.420577] [IGT] kms_prop_blob: executing
12126 09:30:38.980962 or no outputs, <14>[ 18.426133] [IGT] kms_prop_blob: starting subtest basic
12127 09:30:38.991082 pipes: 16, outpu<14>[ 18.432875] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12128 09:30:38.991537 ts: 0
12129 09:30:38.997427 [1mSubte<14>[ 18.440678] [IGT] kms_prop_blob: exiting, ret=0
12130 09:30:39.000727 st plane-cursor-legacy: SKIP (0.000s)[0m
12131 09:30:39.007744 IGT-V<8>[ 18.451011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12132 09:30:39.008413 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12134 09:30:39.010569 ersion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12135 09:30:39.017256 Using IGT_SRANDOM=1718703038 for randomisation
12136 09:30:39.017614 Opened device: /dev/dri/card0
12137 09:30:39.023831 No KMS driver or n<14>[ 18.470861] [IGT] kms_prop_blob: executing
12138 09:30:39.034163 o outputs, pipes<14>[ 18.476166] [IGT] kms_prop_blob: starting subtest blob-prop-core
12139 09:30:39.040547 : 16, outputs: 0<14>[ 18.483693] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12140 09:30:39.040971
12141 09:30:39.047399 [1mSubtest pl<14>[ 18.492281] [IGT] kms_prop_blob: exiting, ret=0
12142 09:30:39.050539 ane-invalid-params: SKIP (0.000s)[0m
12143 09:30:39.060516 IGT-Version: 1.28-ga44ebf<8>[ 18.502692] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12144 09:30:39.061229 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12146 09:30:39.063644 e (aarch64) (Linux: 6.1.92-cip22 aarch64)
12147 09:30:39.066720 Using IGT_SRANDOM=1718703038 for randomisation
12148 09:30:39.070428 Opened device: /dev/dri/card0
12149 09:30:39.079962 No KMS driver or no outputs, pipes: 16<14>[ 18.524641] [IGT] kms_prop_blob: executing
12150 09:30:39.080405 , outputs: 0
12151 09:30:39.086596 [<14>[ 18.529884] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12152 09:30:39.096980 1mSubtest plane-<14>[ 18.537813] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12153 09:30:39.103458 invalid-params-f<14>[ 18.546694] [IGT] kms_prop_blob: exiting, ret=0
12154 09:30:39.103898 ence: SKIP (0.000s)[0m
12155 09:30:39.113455 IGT-Version: 1.28-ga44e<8>[ 18.556883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12156 09:30:39.114064 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12158 09:30:39.116572 bfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12159 09:30:39.123366 Using IGT_SRANDOM=1718703038 for randomisation
12160 09:30:39.123812 Opened device: /dev/dri/card0
12161 09:30:39.133094 No KMS driver or no outputs, pipes: <14>[ 18.578185] [IGT] kms_prop_blob: executing
12162 09:30:39.133577 16, outputs: 0
12163 09:30:39.139491 <14>[ 18.583344] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12164 09:30:39.149272 [1mSubtest crtc<14>[ 18.591356] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12165 09:30:39.156029 -invalid-params:<14>[ 18.600213] [IGT] kms_prop_blob: exiting, ret=0
12166 09:30:39.156457 SKIP (0.000s)[0m
12167 09:30:39.169333 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<8>[ 18.610707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12168 09:30:39.169707 6.1.92-cip22 aarch64)
12169 09:30:39.170307 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12171 09:30:39.176388 Using IGT_SRANDOM=1718703038 for randomisation
12172 09:30:39.179283 Opened device: /dev/dri/card0
12173 09:30:39.182292 No KMS driver or no outputs, pipes: 16, outputs: 0
12174 09:30:39.185987 [1mS<14>[ 18.633042] [IGT] kms_prop_blob: executing
12175 09:30:39.195977 ubtest crtc-inva<14>[ 18.638346] [IGT] kms_prop_blob: starting subtest blob-multiple
12176 09:30:39.202650 lid-params-fence<14>[ 18.645875] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12177 09:30:39.209179 : SKIP (0.000s)<14>[ 18.654231] [IGT] kms_prop_blob: exiting, ret=0
12178 09:30:39.209565 [0m
12179 09:30:39.222217 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<8>[ 18.664601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12180 09:30:39.222647 : 6.1.92-cip22 aarch64)
12181 09:30:39.223175 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12183 09:30:39.229047 Using IGT_SRANDOM=1718703038 for randomisation
12184 09:30:39.229673 Opened device: /dev/dri/card0
12185 09:30:39.235228 No KMS driver or no outputs, pipes: 16, outputs: 0
12186 09:30:39.238559 [1m<14>[ 18.685321] [IGT] kms_prop_blob: executing
12187 09:30:39.248736 Subtest atomic-i<14>[ 18.690591] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12188 09:30:39.254864 nvalid-params: S<14>[ 18.698630] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12189 09:30:39.261549 KIP (0.000s)[0m<14>[ 18.707685] [IGT] kms_prop_blob: exiting, ret=0
12190 09:30:39.262007
12191 09:30:39.275064 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarc<8>[ 18.718431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12192 09:30:39.275737 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12194 09:30:39.278174 h64)
12195 09:30:39.281875 Using IGT_SRANDOM=1718703038 for randomisation
12196 09:30:39.285053 Opened device: /dev/dri/card0
12197 09:30:39.288325 No KMS driver or no outputs, pipes: 16, outputs: 0
12198 09:30:39.295080 [1mSubtest atomic-plan<14>[ 18.740453] [IGT] kms_prop_blob: executing
12199 09:30:39.301812 e-damage: SKIP (<14>[ 18.745937] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12200 09:30:39.305018 0.000s)[0m
12201 09:30:39.311538 IGT<14>[ 18.753718] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12202 09:30:39.318296 -Version: 1.28-g<14>[ 18.762394] [IGT] kms_prop_blob: exiting, ret=0
12203 09:30:39.321288 a44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12204 09:30:39.328318 <8>[ 18.772739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12205 09:30:39.328810
12206 09:30:39.329345 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12208 09:30:39.334949 Using IGT_SRANDOM=1718703039 for randomisation
12209 09:30:39.335546 Opened device: /dev/dri/card0
12210 09:30:39.341258 No KMS driver or no outputs, pipes: 16, outputs: 0
12211 09:30:39.348051 [1mSubtest basic: SKIP (0.0<14>[ 18.793838] [IGT] kms_prop_blob: executing
12212 09:30:39.348549 00s)[0m
12213 09:30:39.354659 IGT-Ve<14>[ 18.798996] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12214 09:30:39.364430 rsion: 1.28-ga44<14>[ 18.806935] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12215 09:30:39.371362 ebfe (aarch64) (<14>[ 18.816090] [IGT] kms_prop_blob: exiting, ret=0
12216 09:30:39.374410 Linux: 6.1.92-cip22 aarch64)
12217 09:30:39.384486 Using IGT_SRANDOM=1718703039 for r<8>[ 18.826536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12218 09:30:39.384972 andomisation
12219 09:30:39.385495 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12221 09:30:39.387444 Opened device: /dev/dri/card0
12222 09:30:39.391182 Starting subtest: basic
12223 09:30:39.394252 [1mSubtest basic: SUCCESS (0.000s)[0m
12224 09:30:39.403977 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.<14>[ 18.848624] [IGT] kms_prop_blob: executing
12225 09:30:39.410918 92-cip22 aarch64<14>[ 18.854290] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12226 09:30:39.411286 )
12227 09:30:39.420904 Using IGT_SRA<14>[ 18.861916] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12228 09:30:39.427152 NDOM=1718703039 <14>[ 18.870776] [IGT] kms_prop_blob: exiting, ret=0
12229 09:30:39.427430 for randomisation
12230 09:30:39.430266 Opened device: /dev/dri/card0
12231 09:30:39.437062 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12233 09:30:39.440458 Starting subte<8>[ 18.881289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12234 09:30:39.440831 st: blob-prop-core
12235 09:30:39.446852 [1mSubtest <8>[ 18.891280] <LAVA_SIGNAL_TESTSET STOP>
12236 09:30:39.447433 Received signal: <TESTSET> STOP
12237 09:30:39.447767 Closing test_set kms_prop_blob
12238 09:30:39.450294 blob-prop-core: SUCCESS (0.000s)[0m
12239 09:30:39.453397 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12240 09:30:39.460405 Using IGT_SRANDOM=1718703039 for randomisation
12241 09:30:39.463433 Opened device: /dev/dri/card0
12242 09:30:39.467280 Startin<8>[ 18.913023] <LAVA_SIGNAL_TESTSET START kms_setmode>
12243 09:30:39.467920 Received signal: <TESTSET> START kms_setmode
12244 09:30:39.468358 Starting test_set kms_setmode
12245 09:30:39.470207 g subtest: blob-prop-validate
12246 09:30:39.473664 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12247 09:30:39.479830 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12248 09:30:39.486738 Using I<14>[ 18.931241] [IGT] kms_setmode: executing
12249 09:30:39.493303 GT_SRANDOM=17187<14>[ 18.937511] [IGT] kms_setmode: starting subtest basic
12250 09:30:39.500239 03039 for random<14>[ 18.943839] [IGT] kms_setmode: finished subtest basic, SKIP
12251 09:30:39.500727 isation
12252 09:30:39.506453 Opened <14>[ 18.951228] [IGT] kms_setmode: exiting, ret=77
12253 09:30:39.510013 device: /dev/dri/card0
12254 09:30:39.512854 Starting subtest: blob-prop-lifetime
12255 09:30:39.519751 [<8>[ 18.961714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12256 09:30:39.520343 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12258 09:30:39.523237 1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12259 09:30:39.529563 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12260 09:30:39.536623 Using IGT_SRANDOM=1718703039 for randomi<14>[ 18.982830] [IGT] kms_setmode: executing
12261 09:30:39.537020 sation
12262 09:30:39.545965 Opened d<14>[ 18.988067] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12263 09:30:39.552871 evice: /dev/dri/<14>[ 18.996000] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12264 09:30:39.556213 card0
12265 09:30:39.559410 Starting <14>[ 19.004950] [IGT] kms_setmode: exiting, ret=77
12266 09:30:39.562980 subtest: blob-multiple
12267 09:30:39.572689 [1mSubtest blob-multiple: SUCCESS (0.00<8>[ 19.015614] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12268 09:30:39.573293 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12270 09:30:39.575981 0s)[0m
12271 09:30:39.579477 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12272 09:30:39.586249 Using IGT_SRANDOM=1718703039 for randomisation
12273 09:30:39.586698 Opened device: /dev/dri/card0
12274 09:30:39.592797 Star<14>[ 19.037285] [IGT] kms_setmode: executing
12275 09:30:39.599294 ting subtest: in<14>[ 19.043324] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12276 09:30:39.609401 valid-get-prop-a<14>[ 19.051492] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12277 09:30:39.609857 ny
12278 09:30:39.616042 [1mSubtest <14>[ 19.060765] [IGT] kms_setmode: exiting, ret=77
12279 09:30:39.619193 invalid-get-prop-any: SUCCESS (0.000s)[0m
12280 09:30:39.629187 IGT-Version: 1.28-ga<8>[ 19.071372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12281 09:30:39.629905 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12283 09:30:39.632593 44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12284 09:30:39.639733 Using IGT_SRANDOM=1718703039 for randomisation
12285 09:30:39.642341 Opened device: /dev/dri/card0
12286 09:30:39.649170 Starting subtest: invalid-get-pro<14>[ 19.094377] [IGT] kms_setmode: executing
12287 09:30:39.649644 p
12288 09:30:39.655316 [1mSubtest i<14>[ 19.099167] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12289 09:30:39.665436 <14>[ 19.107722] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12290 09:30:39.672324 nvalid-get-prop:<14>[ 19.115739] [IGT] kms_setmode: exiting, ret=77
12291 09:30:39.672846 SUCCESS (0.000s)[0m
12292 09:30:39.685135 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<8>[ 19.126239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12293 09:30:39.685836 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12295 09:30:39.688765 ux: 6.1.92-cip22 aarch64)
12296 09:30:39.691932 Using IGT_SRANDOM=1718703039 for randomisation
12297 09:30:39.695006 Opened device: /dev/dri/card0
12298 09:30:39.698670 Starting subtest: invalid-set-prop-any
12299 09:30:39.705216 [1mSubtest invalid-set-prop-a<14>[ 19.149741] [IGT] kms_setmode: executing
12300 09:30:39.711955 ny: SUCCESS (0.0<14>[ 19.155742] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12301 09:30:39.712415 00s)[0m
12302 09:30:39.722054 IGT-Ve<14>[ 19.163620] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12303 09:30:39.728799 rsion: 1.28-ga44<14>[ 19.172174] [IGT] kms_setmode: exiting, ret=77
12304 09:30:39.731715 ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12305 09:30:39.741779 Using IGT_SRANDOM=<8>[ 19.182813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12306 09:30:39.742500 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12308 09:30:39.745560 1718703039 for randomisation
12309 09:30:39.746033 Opened device: /dev/dri/card0
12310 09:30:39.748534 Starting subtest: invalid-set-prop
12311 09:30:39.754795 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12312 09:30:39.758059 IGT-Version<14>[ 19.205215] [IGT] kms_setmode: executing
12313 09:30:39.768201 : 1.28-ga44ebfe <14>[ 19.210322] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12314 09:30:39.778256 (aarch64) (Linux<14>[ 19.219336] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12315 09:30:39.784534 : 6.1.92-cip22 a<14>[ 19.229218] [IGT] kms_setmode: exiting, ret=77
12316 09:30:39.784981 arch64)
12317 09:30:39.787745 Using IGT_SRANDOM=1718703039 for randomisation
12318 09:30:39.797498 Opened <8>[ 19.239654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12319 09:30:39.798135 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12321 09:30:39.804912 device: /dev/dri<8>[ 19.251077] <LAVA_SIGNAL_TESTSET STOP>
12322 09:30:39.805372 /card0
12323 09:30:39.805915 Received signal: <TESTSET> STOP
12324 09:30:39.806219 Closing test_set kms_setmode
12325 09:30:39.807756 Starting subtest: basic
12326 09:30:39.810674 No dynamic tests executed.
12327 09:30:39.814298 [1mSubtest basic: SKIP (0.000s)[0m
12328 09:30:39.817515 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12329 09:30:39.827621 Using IGT_SRANDOM=1718703<8>[ 19.271360] <LAVA_SIGNAL_TESTSET START kms_vblank>
12330 09:30:39.827980 039 for randomisation
12331 09:30:39.828500 Received signal: <TESTSET> START kms_vblank
12332 09:30:39.828869 Starting test_set kms_vblank
12333 09:30:39.831192 Opened device: /dev/dri/card0
12334 09:30:39.834198 Starting subtest: basic-clone-single-crtc
12335 09:30:39.837724 No dynamic tests executed.
12336 09:30:39.844627 [1mSubtest basic-clone-single-crtc<14>[ 19.290811] [IGT] kms_vblank: executing
12337 09:30:39.850919 : SKIP (0.000s)<14>[ 19.295929] [IGT] kms_vblank: exiting, ret=77
12338 09:30:39.851336 [0m
12339 09:30:39.863811 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 a<8>[ 19.306192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12340 09:30:39.864207 arch64)
12341 09:30:39.864754 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12343 09:30:39.867770 Using IGT_SRANDOM=1718703039 for randomisation
12344 09:30:39.870895 Opened device: /dev/dri/card0
12345 09:30:39.873907 Starting subtest: invalid-clone-single-crtc
12346 09:30:39.877553 No dynamic tests executed.
12347 09:30:39.880392 <14>[ 19.326622] [IGT] kms_vblank: executing
12348 09:30:39.880824
12349 09:30:39.887042 [1mSubtest inv<14>[ 19.332167] [IGT] kms_vblank: exiting, ret=77
12350 09:30:39.890798 alid-clone-single-crtc: SKIP (0.000s)[0m
12351 09:30:39.901104 IGT-Version: 1.28-ga4<8>[ 19.342963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12352 09:30:39.901840 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12354 09:30:39.903819 4ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12355 09:30:39.907046 Using IGT_SRANDOM=1718703039 for randomisation
12356 09:30:39.910034 Opened device: /dev/dri/card0
12357 09:30:39.916927 Starting subtest: invalid-clone-ex<14>[ 19.362966] [IGT] kms_vblank: executing
12358 09:30:39.917440 clusive-crtc
12359 09:30:39.923816 No<14>[ 19.368499] [IGT] kms_vblank: exiting, ret=77
12360 09:30:39.926792 dynamic tests executed.
12361 09:30:39.936890 [1mSubtest invalid-clone-exclusive-cr<8>[ 19.378877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12362 09:30:39.937383 tc: SKIP (0.000s)[0m
12363 09:30:39.937980 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12365 09:30:39.943724 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12366 09:30:39.946918 Using IGT_SRANDOM=1718703039 for randomisation
12367 09:30:39.953157 Opened device: /dev/d<14>[ 19.400069] [IGT] kms_vblank: executing
12368 09:30:39.956511 ri/card0
12369 09:30:39.959833 Starti<14>[ 19.405446] [IGT] kms_vblank: exiting, ret=77
12370 09:30:39.963276 ng subtest: clone-exclusive-crtc
12371 09:30:39.966802 No dynamic tests executed.
12372 09:30:39.973300 [<8>[ 19.415817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12373 09:30:39.974032 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12375 09:30:39.976752 1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12376 09:30:39.983237 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12377 09:30:39.986449 Using IGT_SRANDOM=1718703039 for randomisation
12378 09:30:39.993043 Opened de<14>[ 19.437698] [IGT] kms_vblank: executing
12379 09:30:40.000060 vice: /dev/dri/c<14>[ 19.443626] [IGT] kms_vblank: exiting, ret=77
12380 09:30:40.000531 ard0
12381 09:30:40.003072 Starting subtest: invalid-clone-single-crtc-stealing
12382 09:30:40.009635 No d<8>[ 19.454120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12383 09:30:40.010348 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12385 09:30:40.013129 ynamic tests executed.
12386 09:30:40.019199 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12387 09:30:40.025914 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12388 09:30:40.029671 Using IGT_SRANDOM<14>[ 19.476128] [IGT] kms_vblank: executing
12389 09:30:40.036301 =1718703039 for <14>[ 19.482065] [IGT] kms_vblank: exiting, ret=77
12390 09:30:40.039243 randomisation
12391 09:30:40.039626 Opened device: /dev/dri/card0
12392 09:30:40.049146 No KMS driver or n<8>[ 19.492259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12393 09:30:40.049781 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12395 09:30:40.052360 o outputs, pipes: 16, outputs: 0
12396 09:30:40.055908 [1mSubtest invalid: SKIP (0.000s)[0m
12397 09:30:40.062230 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12398 09:30:40.068952 Using IGT_SRANDOM=<14>[ 19.513591] [IGT] kms_vblank: executing
12399 09:30:40.071974 1718703039 for r<14>[ 19.519067] [IGT] kms_vblank: exiting, ret=77
12400 09:30:40.075715 andomisation
12401 09:30:40.078642 Opened device: /dev/dri/card0
12402 09:30:40.085471 No KMS driver or no<8>[ 19.529092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12403 09:30:40.086167 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12405 09:30:40.088569 outputs, pipes: 16, outputs: 0
12406 09:30:40.092175 [1mSubtest crtc-id: SKIP (0.000s)[0m
12407 09:30:40.098742 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12408 09:30:40.105788 Using IGT_SRANDOM=1<14>[ 19.550749] [IGT] kms_vblank: executing
12409 09:30:40.111730 718703040 for ra<14>[ 19.556297] [IGT] kms_vblank: exiting, ret=77
12410 09:30:40.112127 ndomisation
12411 09:30:40.115080 Opened device: /dev/dri/card0
12412 09:30:40.121585 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12414 09:30:40.124615 No KMS driver or no <8>[ 19.566976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12415 09:30:40.125045 outputs, pipes: 16, outputs: 0
12416 09:30:40.131401 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12417 09:30:40.135136 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12418 09:30:40.141656 Using IGT_SRANDOM=1718703040 f<14>[ 19.588430] [IGT] kms_vblank: executing
12419 09:30:40.148055 or randomisation<14>[ 19.594359] [IGT] kms_vblank: exiting, ret=77
12420 09:30:40.148507
12421 09:30:40.150833 Opened device: /dev/dri/card0
12422 09:30:40.160848 No KMS driver or no outputs, pi<8>[ 19.604945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12423 09:30:40.161093 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12425 09:30:40.163976 pes: 16, outputs: 0
12426 09:30:40.167574 [1mSubtest query-idle: SKIP (0.000s)[0m
12427 09:30:40.174441 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12428 09:30:40.180546 Using IGT_SRANDOM=1718703040<14>[ 19.626404] [IGT] kms_vblank: executing
12429 09:30:40.187400 for randomisati<14>[ 19.631656] [IGT] kms_vblank: exiting, ret=77
12430 09:30:40.187504 on
12431 09:30:40.187583 Opened device: /dev/dri/card0
12432 09:30:40.197367 No KMS driver or no outputs, <8>[ 19.641658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12433 09:30:40.197673 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12435 09:30:40.200452 pipes: 16, outputs: 0
12436 09:30:40.204027 [1mSubtest query-idle-hang: SKIP (0.000s)[0m
12437 09:30:40.210369 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12438 09:30:40.217276 Using IGT_SRANDOM=171<14>[ 19.664076] [IGT] kms_vblank: executing
12439 09:30:40.223502 8703040 for rand<14>[ 19.668831] [IGT] kms_vblank: exiting, ret=77
12440 09:30:40.223872 omisation
12441 09:30:40.226951 Opened device: /dev/dri/card0
12442 09:30:40.237198 No KMS driver or no ou<8>[ 19.679079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12443 09:30:40.237803 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12445 09:30:40.240104 tputs, pipes: 16, outputs: 0
12446 09:30:40.243914 [1mSubtest query-forked: SKIP (0.000s)[0m
12447 09:30:40.250430 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12448 09:30:40.253816 Using IGT_SRANDOM<14>[ 19.700909] [IGT] kms_vblank: executing
12449 09:30:40.260255 =1718703040 for <14>[ 19.706617] [IGT] kms_vblank: exiting, ret=77
12450 09:30:40.263352 randomisation
12451 09:30:40.267091 Opened device: /dev/dri/card0
12452 09:30:40.273479 No KMS driver or n<8>[ 19.716970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12453 09:30:40.274073 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12455 09:30:40.276409 o outputs, pipes: 16, outputs: 0
12456 09:30:40.280127 [1mSubtest query-forked-hang: SKIP (0.000s)[0m
12457 09:30:40.286265 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12458 09:30:40.293065 Using IG<14>[ 19.737539] [IGT] kms_vblank: executing
12459 09:30:40.296525 T_SRANDOM=171870<14>[ 19.743208] [IGT] kms_vblank: exiting, ret=77
12460 09:30:40.299732 3040 for randomisation
12461 09:30:40.302783 Opened device: /dev/dri/card0
12462 09:30:40.306351 No KMS driver or no outputs, pipes: 16, outputs: 0
12463 09:30:40.309215 [1mSubtest query-busy: SKIP (0.000s)[0m
12464 09:30:40.316083 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12465 09:30:40.326429 Using IGT_SRANDOM=1718703040 for rando<8>[ 19.770753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12466 09:30:40.327198 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12468 09:30:40.329797 misation
12469 09:30:40.330186 Opened device: /dev/dri/card0
12470 09:30:40.335889 No KMS driver or no outputs, pipes: 16, outputs: 0
12471 09:30:40.339708 [1mSubtest query-busy-hang: SKIP (0.000s)[0m
12472 09:30:40.346203 IGT-Version: 1.28-ga44ebfe (aarch64<14>[ 19.792930] [IGT] kms_vblank: executing
12473 09:30:40.352572 ) (Linux: 6.1.92<14>[ 19.798288] [IGT] kms_vblank: exiting, ret=77
12474 09:30:40.355991 -cip22 aarch64)
12475 09:30:40.359119 Using IGT_SRANDOM=1718703040 for randomisation
12476 09:30:40.365688 Opened device: <8>[ 19.809576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12477 09:30:40.366283 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12479 09:30:40.368733 /dev/dri/card0
12480 09:30:40.372043 No KMS driver or no outputs, pipes: 16, outputs: 0
12481 09:30:40.375589 [1mSubtest query-forked-busy: SKIP (0.000s)[0m
12482 09:30:40.382067 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12483 09:30:40.388784 Using <14>[ 19.833103] [IGT] kms_vblank: executing
12484 09:30:40.392302 IGT_SRANDOM=1718<14>[ 19.839060] [IGT] kms_vblank: exiting, ret=77
12485 09:30:40.395279 703040 for randomisation
12486 09:30:40.398846 Opened device: /dev/dri/card0
12487 09:30:40.409081 No KMS driver or no outputs, pipes: 16,<8>[ 19.852250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12488 09:30:40.409994 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12490 09:30:40.411909 outputs: 0
12491 09:30:40.415495 [1mSubtest query-forked-busy-hang: SKIP (0.000s)[0m
12492 09:30:40.422189 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12493 09:30:40.428768 Using IGT_SRANDOM=1718703040 for randomi<14>[ 19.874348] [IGT] kms_vblank: executing
12494 09:30:40.429163 sation
12495 09:30:40.435228 Opened d<14>[ 19.880430] [IGT] kms_vblank: exiting, ret=77
12496 09:30:40.438191 evice: /dev/dri/card0
12497 09:30:40.448127 No KMS driver or no outputs, pipes: 16, o<8>[ 19.890709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12498 09:30:40.448545 utputs: 0
12499 09:30:40.449314 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12501 09:30:40.451309 [1mSubtest wait-idle: SKIP (0.000s)[0m
12502 09:30:40.458004 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12503 09:30:40.461641 Using IGT_SRANDOM=1718703040 for randomisation
12504 09:30:40.464863 Opened device: /dev/dri/card0
12505 09:30:40.468018 No KMS driver or no outputs, pipes: 16, outputs: 0
12506 09:30:40.478036 [1mSubtest wait-idle-hang: SKIP (0.<14>[ 19.922902] [IGT] kms_vblank: executing
12507 09:30:40.478511 000s)[0m
12508 09:30:40.481209 IGT-V<14>[ 19.928535] [IGT] kms_vblank: exiting, ret=77
12509 09:30:40.487921 ersion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12510 09:30:40.497453 Using IGT_SRANDOM<8>[ 19.939403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12511 09:30:40.498250 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12513 09:30:40.501083 =1718703040 for randomisation
12514 09:30:40.501614 Opened device: /dev/dri/card0
12515 09:30:40.507625 No KMS driver or no outputs, pipes: 16, outputs: 0
12516 09:30:40.510896 [1mSubtest wait-forked: SKIP (0.000s)[0m
12517 09:30:40.517352 IGT-Version: 1.28-<14>[ 19.961957] [IGT] kms_vblank: executing
12518 09:30:40.524109 ga44ebfe (aarch6<14>[ 19.967900] [IGT] kms_vblank: exiting, ret=77
12519 09:30:40.524601 4) (Linux: 6.1.92-cip22 aarch64)
12520 09:30:40.533763 Using IGT_SRANDOM=1718703040 f<8>[ 19.977957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12521 09:30:40.534592 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12523 09:30:40.537571 or randomisation
12524 09:30:40.540366 Opened device: /dev/dri/card0
12525 09:30:40.544057 No KMS driver or no outputs, pipes: 16, outputs: 0
12526 09:30:40.547171 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12527 09:30:40.553999 IGT-Versio<14>[ 19.999735] [IGT] kms_vblank: executing
12528 09:30:40.559997 n: 1.28-ga44ebfe<14>[ 20.005042] [IGT] kms_vblank: exiting, ret=77
12529 09:30:40.563742 (aarch64) (Linux: 6.1.92-cip22 aarch64)
12530 09:30:40.573943 Using IGT_SRANDOM=1718<8>[ 20.015502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12531 09:30:40.574576 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12533 09:30:40.577053 703040 for randomisation
12534 09:30:40.577465 Opened device: /dev/dri/card0
12535 09:30:40.583339 No KMS driver or no outputs, pipes: 16, outputs: 0
12536 09:30:40.587082 [1mSubtest wait-busy: SKIP (0.000s)[0m
12537 09:30:40.590087 IGT-Versi<14>[ 20.037771] [IGT] kms_vblank: executing
12538 09:30:40.596952 on: 1.28-ga44ebf<14>[ 20.042749] [IGT] kms_vblank: exiting, ret=77
12539 09:30:40.599936 e (aarch64) (Linux: 6.1.92-cip22 aarch64)
12540 09:30:40.609833 Using IGT_SRANDOM=171<8>[ 20.052810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12541 09:30:40.610478 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12543 09:30:40.613518 8703040 for randomisation
12544 09:30:40.616501 Opened device: /dev/dri/card0
12545 09:30:40.619823 No KMS driver or no outputs, pipes: 16, outputs: 0
12546 09:30:40.623111 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12547 09:30:40.630025 IGT<14>[ 20.074856] [IGT] kms_vblank: executing
12548 09:30:40.636457 -Version: 1.28-g<14>[ 20.080357] [IGT] kms_vblank: exiting, ret=77
12549 09:30:40.639793 a44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12550 09:30:40.649382 Using IGT_SRAND<8>[ 20.090962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12551 09:30:40.650040 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12553 09:30:40.653120 OM=1718703040 for randomisation
12554 09:30:40.653685 Opened device: /dev/dri/card0
12555 09:30:40.659938 No KMS driver or no outputs, pipes: 16, outputs: 0
12556 09:30:40.666185 [1mSubtest wait-forked-busy: SKIP (0.000s)<14>[ 20.112707] [IGT] kms_vblank: executing
12557 09:30:40.666593 [0m
12558 09:30:40.673362 IGT-Version<14>[ 20.118374] [IGT] kms_vblank: exiting, ret=77
12559 09:30:40.676296 : 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12560 09:30:40.686571 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12562 09:30:40.689441 Using IGT_SRANDOM=17187<8>[ 20.130066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12563 09:30:40.689848 03040 for randomisation
12564 09:30:40.692946 Opened device: /dev/dri/card0
12565 09:30:40.696178 No KMS driver or no outputs, pipes: 16, outputs: 0
12566 09:30:40.706388 [1mSubtest wait-forked-busy-hang: SKIP (0.000s)[0m<14>[ 20.152783] [IGT] kms_vblank: executing
12567 09:30:40.706784
12568 09:30:40.712774 IGT-Version: 1<14>[ 20.157691] [IGT] kms_vblank: exiting, ret=77
12569 09:30:40.716275 .28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12570 09:30:40.726217 Using IGT_<8>[ 20.168227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12571 09:30:40.726850 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12573 09:30:40.729133 SRANDOM=1718703040 for randomisation
12574 09:30:40.732714 Opened device: /dev/dri/card0
12575 09:30:40.736266 No KMS driver or no outputs, pipes: 16, outputs: 0
12576 09:30:40.745747 [1mSubtest ts-continuation-idle: SKIP <14>[ 20.190497] [IGT] kms_vblank: executing
12577 09:30:40.746151 (0.000s)[0m
12578 09:30:40.749219 IG<14>[ 20.195783] [IGT] kms_vblank: exiting, ret=77
12579 09:30:40.762599 T-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)<8>[ 20.206104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12580 09:30:40.763247 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12582 09:30:40.765747
12583 09:30:40.768797 Using IGT_SRANDOM=1718703040 for randomisation
12584 09:30:40.772477 Opened device: /dev/dri/card0
12585 09:30:40.775478 No KMS driver or no outputs, pipes: 16, outputs: 0
12586 09:30:40.782246 [1mSubtest ts-continuation<14>[ 20.228308] [IGT] kms_vblank: executing
12587 09:30:40.789167 -idle-hang: SKIP<14>[ 20.233587] [IGT] kms_vblank: exiting, ret=77
12588 09:30:40.789568 (0.000s)[0m
12589 09:30:40.801607 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.<8>[ 20.243857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12590 09:30:40.801823 92-cip22 aarch64)
12591 09:30:40.802209 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12593 09:30:40.808390 Using IGT_SRANDOM=1718703040 for randomisation
12594 09:30:40.808560 Opened device: /dev/dri/card0
12595 09:30:40.815163 No KMS driver or no outputs, pipes: 16, outputs: 0
12596 09:30:40.818331 [1mSubtes<14>[ 20.266476] [IGT] kms_vblank: executing
12597 09:30:40.824904 t ts-continuatio<14>[ 20.271488] [IGT] kms_vblank: exiting, ret=77
12598 09:30:40.828292 n-dpms-rpm: SKIP (0.000s)[0m
12599 09:30:40.838301 IGT-Version: 1.28-ga44ebfe (aarch<8>[ 20.282193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12600 09:30:40.838564 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12602 09:30:40.841472 64) (Linux: 6.1.92-cip22 aarch64)
12603 09:30:40.848178 Using IGT_SRANDOM=1718703040 for randomisation
12604 09:30:40.851235 Opened device: /dev/dri/card0
12605 09:30:40.857888 No KMS driver or no outputs, pipes: 16, output<14>[ 20.305007] [IGT] kms_vblank: executing
12606 09:30:40.857993 s: 0
12607 09:30:40.864823 [1mSubtes<14>[ 20.309882] [IGT] kms_vblank: exiting, ret=77
12608 09:30:40.868083 t ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12609 09:30:40.877772 IGT-Version: <8>[ 20.320419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12610 09:30:40.878024 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12612 09:30:40.884280 1.28-ga44ebfe (aarch64) (Linux: <8>[ 20.330924] <LAVA_SIGNAL_TESTSET STOP>
12613 09:30:40.884561 Received signal: <TESTSET> STOP
12614 09:30:40.884661 Closing test_set kms_vblank
12615 09:30:40.894490 6.1.92-cip22 aar<8>[ 20.337411] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 14407656_1.5.2.3.1>
12616 09:30:40.894619 ch64)
12617 09:30:40.894882 Received signal: <ENDRUN> 0_igt-kms-mediatek 14407656_1.5.2.3.1
12618 09:30:40.894992 Ending use of test pattern.
12619 09:30:40.895085 Ending test lava.0_igt-kms-mediatek (14407656_1.5.2.3.1), duration 6.19
12621 09:30:40.897521 Using IGT_SRANDOM=1718703040 for randomisation
12622 09:30:40.901191 Opened device: /dev/dri/card0
12623 09:30:40.904252 No KMS driver or no outputs, pipes: 16, outputs: 0
12624 09:30:40.911114 [1mSubtest ts-continuation-suspend: SKIP (0.000s)[0m
12625 09:30:40.917584 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12626 09:30:40.920999 Using IGT_SRANDOM=1718703040 for randomisation
12627 09:30:40.924391 Opened device: /dev/dri/card0
12628 09:30:40.928177 No KMS driver or no outputs, pipes: 16, outputs: 0
12629 09:30:40.931271 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12630 09:30:40.937872 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12631 09:30:40.941145 Using IGT_SRANDOM=1718703040 for randomisation
12632 09:30:40.944377 Opened device: /dev/dri/card0
12633 09:30:40.951276 No KMS driver or no outputs, pipes: 16, outputs: 0
12634 09:30:40.954333 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12635 09:30:40.961233 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12636 09:30:40.964212 Using IGT_SRANDOM=1718703040 for randomisation
12637 09:30:40.967344 Opened device: /dev/dri/card0
12638 09:30:40.971048 No KMS driver or no outputs, pipes: 16, outputs: 0
12639 09:30:40.977580 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12640 09:30:40.977979 + set +x
12641 09:30:40.980536 <LAVA_TEST_RUNNER EXIT>
12642 09:30:40.981218 ok: lava_test_shell seems to have completed
12643 09:30:40.988752 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12644 09:30:40.989566 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12645 09:30:40.989986 end: 3 lava-test-retry (duration 00:00:07) [common]
12646 09:30:40.990404 start: 4 finalize (timeout 00:07:13) [common]
12647 09:30:40.990829 start: 4.1 power-off (timeout 00:00:30) [common]
12648 09:30:40.991472 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
12649 09:30:41.245287 >> Command sent successfully.
12650 09:30:41.258915 Returned 0 in 0 seconds
12651 09:30:41.360131 end: 4.1 power-off (duration 00:00:00) [common]
12653 09:30:41.361489 start: 4.2 read-feedback (timeout 00:07:13) [common]
12654 09:30:41.362622 Listened to connection for namespace 'common' for up to 1s
12655 09:30:42.363394 Finalising connection for namespace 'common'
12656 09:30:42.363984 Disconnecting from shell: Finalise
12657 09:30:42.364366 / #
12658 09:30:42.465407 end: 4.2 read-feedback (duration 00:00:01) [common]
12659 09:30:42.466021 end: 4 finalize (duration 00:00:01) [common]
12660 09:30:42.466585 Cleaning after the job
12661 09:30:42.467052 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/ramdisk
12662 09:30:42.495420 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/kernel
12663 09:30:42.522950 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/dtb
12664 09:30:42.523202 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407656/tftp-deploy-_tdhyqxs/modules
12665 09:30:42.530155 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407656
12666 09:30:42.635298 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407656
12667 09:30:42.635467 Job finished correctly