Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 48
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 88
1 09:52:17.948334 lava-dispatcher, installed at version: 2024.03
2 09:52:17.948547 start: 0 validate
3 09:52:17.948656 Start time: 2024-06-18 09:52:17.948649+00:00 (UTC)
4 09:52:17.948780 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:52:17.948914 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:52:18.204139 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:52:18.204887 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:52:18.458445 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:52:18.459283 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 09:52:18.726454 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:52:18.727072 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:52:19.232037 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:52:19.232786 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:52:19.501461 validate duration: 1.55
16 09:52:19.502721 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:52:19.503293 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:52:19.503808 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:52:19.504592 Not decompressing ramdisk as can be used compressed.
20 09:52:19.505129 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 09:52:19.505516 saving as /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/ramdisk/initrd.cpio.gz
22 09:52:19.505902 total size: 5628169 (5 MB)
23 09:52:19.511312 progress 0 % (0 MB)
24 09:52:19.521660 progress 5 % (0 MB)
25 09:52:19.527900 progress 10 % (0 MB)
26 09:52:19.531820 progress 15 % (0 MB)
27 09:52:19.535433 progress 20 % (1 MB)
28 09:52:19.538903 progress 25 % (1 MB)
29 09:52:19.541769 progress 30 % (1 MB)
30 09:52:19.544537 progress 35 % (1 MB)
31 09:52:19.546667 progress 40 % (2 MB)
32 09:52:19.548906 progress 45 % (2 MB)
33 09:52:19.550806 progress 50 % (2 MB)
34 09:52:19.552861 progress 55 % (2 MB)
35 09:52:19.554847 progress 60 % (3 MB)
36 09:52:19.556495 progress 65 % (3 MB)
37 09:52:19.558334 progress 70 % (3 MB)
38 09:52:19.559821 progress 75 % (4 MB)
39 09:52:19.561484 progress 80 % (4 MB)
40 09:52:19.563123 progress 85 % (4 MB)
41 09:52:19.564763 progress 90 % (4 MB)
42 09:52:19.566370 progress 95 % (5 MB)
43 09:52:19.567806 progress 100 % (5 MB)
44 09:52:19.568025 5 MB downloaded in 0.06 s (86.40 MB/s)
45 09:52:19.568164 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:52:19.568384 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:52:19.568464 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:52:19.568539 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:52:19.568663 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:52:19.568728 saving as /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/kernel/Image
52 09:52:19.568782 total size: 54813184 (52 MB)
53 09:52:19.568835 No compression specified
54 09:52:19.569870 progress 0 % (0 MB)
55 09:52:19.583605 progress 5 % (2 MB)
56 09:52:19.597969 progress 10 % (5 MB)
57 09:52:19.612088 progress 15 % (7 MB)
58 09:52:19.626088 progress 20 % (10 MB)
59 09:52:19.640024 progress 25 % (13 MB)
60 09:52:19.654097 progress 30 % (15 MB)
61 09:52:19.668048 progress 35 % (18 MB)
62 09:52:19.681653 progress 40 % (20 MB)
63 09:52:19.695107 progress 45 % (23 MB)
64 09:52:19.708680 progress 50 % (26 MB)
65 09:52:19.722674 progress 55 % (28 MB)
66 09:52:19.736115 progress 60 % (31 MB)
67 09:52:19.749879 progress 65 % (34 MB)
68 09:52:19.763183 progress 70 % (36 MB)
69 09:52:19.776586 progress 75 % (39 MB)
70 09:52:19.790027 progress 80 % (41 MB)
71 09:52:19.803372 progress 85 % (44 MB)
72 09:52:19.816899 progress 90 % (47 MB)
73 09:52:19.830556 progress 95 % (49 MB)
74 09:52:19.843801 progress 100 % (52 MB)
75 09:52:19.844020 52 MB downloaded in 0.28 s (189.93 MB/s)
76 09:52:19.844163 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:52:19.844369 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:52:19.844449 start: 1.3 download-retry (timeout 00:10:00) [common]
80 09:52:19.844524 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 09:52:19.844650 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 09:52:19.844711 saving as /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 09:52:19.844762 total size: 57695 (0 MB)
84 09:52:19.844815 No compression specified
85 09:52:19.845917 progress 56 % (0 MB)
86 09:52:19.846176 progress 100 % (0 MB)
87 09:52:19.846415 0 MB downloaded in 0.00 s (33.35 MB/s)
88 09:52:19.846526 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:52:19.846726 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:52:19.846800 start: 1.4 download-retry (timeout 00:10:00) [common]
92 09:52:19.846875 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 09:52:19.846974 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 09:52:19.847032 saving as /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/nfsrootfs/full.rootfs.tar
95 09:52:19.847083 total size: 120894716 (115 MB)
96 09:52:19.847135 Using unxz to decompress xz
97 09:52:19.848262 progress 0 % (0 MB)
98 09:52:20.179643 progress 5 % (5 MB)
99 09:52:20.523811 progress 10 % (11 MB)
100 09:52:20.864670 progress 15 % (17 MB)
101 09:52:21.184307 progress 20 % (23 MB)
102 09:52:21.488998 progress 25 % (28 MB)
103 09:52:21.826895 progress 30 % (34 MB)
104 09:52:22.146638 progress 35 % (40 MB)
105 09:52:22.319292 progress 40 % (46 MB)
106 09:52:22.503812 progress 45 % (51 MB)
107 09:52:22.804630 progress 50 % (57 MB)
108 09:52:23.166689 progress 55 % (63 MB)
109 09:52:23.509325 progress 60 % (69 MB)
110 09:52:23.847845 progress 65 % (74 MB)
111 09:52:24.186721 progress 70 % (80 MB)
112 09:52:24.534420 progress 75 % (86 MB)
113 09:52:24.868585 progress 80 % (92 MB)
114 09:52:25.210485 progress 85 % (98 MB)
115 09:52:25.552121 progress 90 % (103 MB)
116 09:52:25.876315 progress 95 % (109 MB)
117 09:52:26.223623 progress 100 % (115 MB)
118 09:52:26.228988 115 MB downloaded in 6.38 s (18.07 MB/s)
119 09:52:26.229153 end: 1.4.1 http-download (duration 00:00:06) [common]
121 09:52:26.229364 end: 1.4 download-retry (duration 00:00:06) [common]
122 09:52:26.229442 start: 1.5 download-retry (timeout 00:09:53) [common]
123 09:52:26.229517 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 09:52:26.229644 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:52:26.229705 saving as /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/modules/modules.tar
126 09:52:26.229759 total size: 8619356 (8 MB)
127 09:52:26.229813 Using unxz to decompress xz
128 09:52:26.231133 progress 0 % (0 MB)
129 09:52:26.250019 progress 5 % (0 MB)
130 09:52:26.273284 progress 10 % (0 MB)
131 09:52:26.296854 progress 15 % (1 MB)
132 09:52:26.320398 progress 20 % (1 MB)
133 09:52:26.345229 progress 25 % (2 MB)
134 09:52:26.368615 progress 30 % (2 MB)
135 09:52:26.392268 progress 35 % (2 MB)
136 09:52:26.415482 progress 40 % (3 MB)
137 09:52:26.439427 progress 45 % (3 MB)
138 09:52:26.462500 progress 50 % (4 MB)
139 09:52:26.486042 progress 55 % (4 MB)
140 09:52:26.509043 progress 60 % (4 MB)
141 09:52:26.531932 progress 65 % (5 MB)
142 09:52:26.558525 progress 70 % (5 MB)
143 09:52:26.582033 progress 75 % (6 MB)
144 09:52:26.604804 progress 80 % (6 MB)
145 09:52:26.627527 progress 85 % (7 MB)
146 09:52:26.650374 progress 90 % (7 MB)
147 09:52:26.676036 progress 95 % (7 MB)
148 09:52:26.703443 progress 100 % (8 MB)
149 09:52:26.707821 8 MB downloaded in 0.48 s (17.19 MB/s)
150 09:52:26.707973 end: 1.5.1 http-download (duration 00:00:00) [common]
152 09:52:26.708185 end: 1.5 download-retry (duration 00:00:00) [common]
153 09:52:26.708264 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 09:52:26.708340 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 09:52:30.208068 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14407592/extract-nfsrootfs-4guaw7ba
156 09:52:30.208246 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 09:52:30.208339 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 09:52:30.208495 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_
159 09:52:30.208609 makedir: /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin
160 09:52:30.208698 makedir: /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/tests
161 09:52:30.208784 makedir: /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/results
162 09:52:30.208864 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-add-keys
163 09:52:30.208986 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-add-sources
164 09:52:30.209100 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-background-process-start
165 09:52:30.209215 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-background-process-stop
166 09:52:30.209369 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-common-functions
167 09:52:30.209486 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-echo-ipv4
168 09:52:30.209601 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-install-packages
169 09:52:30.209712 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-installed-packages
170 09:52:30.209824 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-os-build
171 09:52:30.209935 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-probe-channel
172 09:52:30.210045 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-probe-ip
173 09:52:30.210157 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-target-ip
174 09:52:30.210274 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-target-mac
175 09:52:30.210384 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-target-storage
176 09:52:30.210496 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-test-case
177 09:52:30.210607 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-test-event
178 09:52:30.210716 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-test-feedback
179 09:52:30.210824 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-test-raise
180 09:52:30.210933 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-test-reference
181 09:52:30.211042 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-test-runner
182 09:52:30.211151 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-test-set
183 09:52:30.211260 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-test-shell
184 09:52:30.211371 Updating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-add-keys (debian)
185 09:52:30.211506 Updating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-add-sources (debian)
186 09:52:30.211628 Updating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-install-packages (debian)
187 09:52:30.211749 Updating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-installed-packages (debian)
188 09:52:30.211870 Updating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/bin/lava-os-build (debian)
189 09:52:30.211976 Creating /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/environment
190 09:52:30.212059 LAVA metadata
191 09:52:30.212122 - LAVA_JOB_ID=14407592
192 09:52:30.212177 - LAVA_DISPATCHER_IP=192.168.201.1
193 09:52:30.212267 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 09:52:30.212324 skipped lava-vland-overlay
195 09:52:30.212392 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 09:52:30.212463 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 09:52:30.212515 skipped lava-multinode-overlay
198 09:52:30.212579 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 09:52:30.212648 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 09:52:30.212708 Loading test definitions
201 09:52:30.212782 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 09:52:30.212839 Using /lava-14407592 at stage 0
203 09:52:30.213104 uuid=14407592_1.6.2.3.1 testdef=None
204 09:52:30.213182 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 09:52:30.213256 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 09:52:30.213645 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 09:52:30.213840 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 09:52:30.214431 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 09:52:30.214642 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 09:52:30.215549 runner path: /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/0/tests/0_timesync-off test_uuid 14407592_1.6.2.3.1
213 09:52:30.215692 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 09:52:30.215894 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 09:52:30.215957 Using /lava-14407592 at stage 0
217 09:52:30.216042 Fetching tests from https://github.com/kernelci/test-definitions.git
218 09:52:30.216117 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/0/tests/1_kselftest-alsa'
219 09:52:33.032920 Running '/usr/bin/git checkout kernelci.org
220 09:52:33.080587 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 09:52:33.080960 uuid=14407592_1.6.2.3.5 testdef=None
222 09:52:33.081062 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 09:52:33.081273 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 09:52:33.081906 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 09:52:33.082108 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 09:52:33.083008 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 09:52:33.083227 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 09:52:33.084063 runner path: /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/0/tests/1_kselftest-alsa test_uuid 14407592_1.6.2.3.5
232 09:52:33.084141 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 09:52:33.084200 BRANCH='cip'
234 09:52:33.084252 SKIPFILE='/dev/null'
235 09:52:33.084302 SKIP_INSTALL='True'
236 09:52:33.084351 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 09:52:33.084403 TST_CASENAME=''
238 09:52:33.084452 TST_CMDFILES='alsa'
239 09:52:33.084581 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 09:52:33.084771 Creating lava-test-runner.conf files
242 09:52:33.084824 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407592/lava-overlay-tx8zxpa_/lava-14407592/0 for stage 0
243 09:52:33.084904 - 0_timesync-off
244 09:52:33.084963 - 1_kselftest-alsa
245 09:52:33.085049 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 09:52:33.085125 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 09:52:40.259235 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 09:52:40.259374 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 09:52:40.259459 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 09:52:40.259542 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 09:52:40.259622 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 09:52:40.415370 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 09:52:40.415525 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 09:52:40.415605 extracting modules file /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407592/extract-nfsrootfs-4guaw7ba
255 09:52:40.628664 extracting modules file /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407592/extract-overlay-ramdisk-x3rzgr9z/ramdisk
256 09:52:40.860348 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 09:52:40.860517 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 09:52:40.860626 [common] Applying overlay to NFS
259 09:52:40.860712 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407592/compress-overlay-yiz58ffk/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407592/extract-nfsrootfs-4guaw7ba
260 09:52:41.699003 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 09:52:41.699144 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 09:52:41.699229 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 09:52:41.699310 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 09:52:41.699383 Building ramdisk /var/lib/lava/dispatcher/tmp/14407592/extract-overlay-ramdisk-x3rzgr9z/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407592/extract-overlay-ramdisk-x3rzgr9z/ramdisk
265 09:52:42.038407 >> 130466 blocks
266 09:52:44.101845 rename /var/lib/lava/dispatcher/tmp/14407592/extract-overlay-ramdisk-x3rzgr9z/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/ramdisk/ramdisk.cpio.gz
267 09:52:44.102021 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 09:52:44.102113 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 09:52:44.102193 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 09:52:44.102282 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/kernel/Image']
271 09:52:57.254420 Returned 0 in 13 seconds
272 09:52:57.355266 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/kernel/image.itb
273 09:52:57.819753 output: FIT description: Kernel Image image with one or more FDT blobs
274 09:52:57.819896 output: Created: Tue Jun 18 10:52:57 2024
275 09:52:57.819959 output: Image 0 (kernel-1)
276 09:52:57.820017 output: Description:
277 09:52:57.820070 output: Created: Tue Jun 18 10:52:57 2024
278 09:52:57.820122 output: Type: Kernel Image
279 09:52:57.820173 output: Compression: lzma compressed
280 09:52:57.820227 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
281 09:52:57.820277 output: Architecture: AArch64
282 09:52:57.820327 output: OS: Linux
283 09:52:57.820390 output: Load Address: 0x00000000
284 09:52:57.820441 output: Entry Point: 0x00000000
285 09:52:57.820492 output: Hash algo: crc32
286 09:52:57.820545 output: Hash value: 4137a6e7
287 09:52:57.820596 output: Image 1 (fdt-1)
288 09:52:57.820648 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 09:52:57.820702 output: Created: Tue Jun 18 10:52:57 2024
290 09:52:57.820758 output: Type: Flat Device Tree
291 09:52:57.820815 output: Compression: uncompressed
292 09:52:57.820870 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 09:52:57.820926 output: Architecture: AArch64
294 09:52:57.820982 output: Hash algo: crc32
295 09:52:57.821037 output: Hash value: a9713552
296 09:52:57.821092 output: Image 2 (ramdisk-1)
297 09:52:57.821149 output: Description: unavailable
298 09:52:57.821203 output: Created: Tue Jun 18 10:52:57 2024
299 09:52:57.821256 output: Type: RAMDisk Image
300 09:52:57.821308 output: Compression: uncompressed
301 09:52:57.821356 output: Data Size: 18742486 Bytes = 18303.21 KiB = 17.87 MiB
302 09:52:57.821405 output: Architecture: AArch64
303 09:52:57.821453 output: OS: Linux
304 09:52:57.821501 output: Load Address: unavailable
305 09:52:57.821549 output: Entry Point: unavailable
306 09:52:57.821597 output: Hash algo: crc32
307 09:52:57.821644 output: Hash value: 91b8db3c
308 09:52:57.821693 output: Default Configuration: 'conf-1'
309 09:52:57.821740 output: Configuration 0 (conf-1)
310 09:52:57.821788 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 09:52:57.821837 output: Kernel: kernel-1
312 09:52:57.821884 output: Init Ramdisk: ramdisk-1
313 09:52:57.821932 output: FDT: fdt-1
314 09:52:57.821978 output: Loadables: kernel-1
315 09:52:57.822026 output:
316 09:52:57.822160 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 09:52:57.822255 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 09:52:57.822347 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 09:52:57.822430 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 09:52:57.822498 No LXC device requested
321 09:52:57.822569 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 09:52:57.822648 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 09:52:57.822719 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 09:52:57.822782 Checking files for TFTP limit of 4294967296 bytes.
325 09:52:57.823239 end: 1 tftp-deploy (duration 00:00:38) [common]
326 09:52:57.823339 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 09:52:57.823425 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 09:52:57.823533 substitutions:
329 09:52:57.823594 - {DTB}: 14407592/tftp-deploy-paprs7ub/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 09:52:57.823653 - {INITRD}: 14407592/tftp-deploy-paprs7ub/ramdisk/ramdisk.cpio.gz
331 09:52:57.823707 - {KERNEL}: 14407592/tftp-deploy-paprs7ub/kernel/Image
332 09:52:57.823761 - {LAVA_MAC}: None
333 09:52:57.823814 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14407592/extract-nfsrootfs-4guaw7ba
334 09:52:57.823868 - {NFS_SERVER_IP}: 192.168.201.1
335 09:52:57.823921 - {PRESEED_CONFIG}: None
336 09:52:57.823978 - {PRESEED_LOCAL}: None
337 09:52:57.824031 - {RAMDISK}: 14407592/tftp-deploy-paprs7ub/ramdisk/ramdisk.cpio.gz
338 09:52:57.824082 - {ROOT_PART}: None
339 09:52:57.824133 - {ROOT}: None
340 09:52:57.824183 - {SERVER_IP}: 192.168.201.1
341 09:52:57.824233 - {TEE}: None
342 09:52:57.824283 Parsed boot commands:
343 09:52:57.824331 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 09:52:57.824481 Parsed boot commands: tftpboot 192.168.201.1 14407592/tftp-deploy-paprs7ub/kernel/image.itb 14407592/tftp-deploy-paprs7ub/kernel/cmdline
345 09:52:57.824566 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 09:52:57.824641 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 09:52:57.824722 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 09:52:57.824800 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 09:52:57.824861 Not connected, no need to disconnect.
350 09:52:57.824928 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 09:52:57.825001 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 09:52:57.825063 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-5'
353 09:52:57.828531 Setting prompt string to ['lava-test: # ']
354 09:52:57.828859 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 09:52:57.828967 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 09:52:57.829066 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 09:52:57.829156 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 09:52:57.829325 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-5', '--port=1', '--command=reboot']
359 09:53:07.048901 >> Command sent successfully.
360 09:53:07.063913 Returned 0 in 9 seconds
361 09:53:07.165324 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 09:53:07.167019 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 09:53:07.167538 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 09:53:07.167999 Setting prompt string to 'Starting depthcharge on Juniper...'
366 09:53:07.168344 Changing prompt to 'Starting depthcharge on Juniper...'
367 09:53:07.168687 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
368 09:53:07.170921 [Enter `^Ec?' for help]
369 09:53:13.303268 [DL] 00000000 00000000 010701
370 09:53:13.308143
371 09:53:13.308673
372 09:53:13.309300 F0: 102B 0000
373 09:53:13.309726
374 09:53:13.310138 F3: 1006 0033 [0200]
375 09:53:13.311492
376 09:53:13.311965 F3: 4001 00E0 [0200]
377 09:53:13.312349
378 09:53:13.312692 F3: 0000 0000
379 09:53:13.313020
380 09:53:13.314671 V0: 0000 0000 [0001]
381 09:53:13.315130
382 09:53:13.315536 00: 1027 0002
383 09:53:13.315892
384 09:53:13.317922 01: 0000 0000
385 09:53:13.318423
386 09:53:13.318799 BP: 0C00 0251 [0000]
387 09:53:13.319131
388 09:53:13.321689 G0: 1182 0000
389 09:53:13.322194
390 09:53:13.322577 EC: 0004 0000 [0001]
391 09:53:13.322882
392 09:53:13.324688 S7: 0000 0000 [0000]
393 09:53:13.325111
394 09:53:13.328453 CC: 0000 0000 [0001]
395 09:53:13.328900
396 09:53:13.329297 T0: 0000 00DB [000F]
397 09:53:13.329607
398 09:53:13.329897 Jump to BL
399 09:53:13.330177
400 09:53:13.363994
401 09:53:13.364503
402 09:53:13.370701 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
403 09:53:13.374154 ARM64: Exception handlers installed.
404 09:53:13.377366 ARM64: Testing exception
405 09:53:13.380950 ARM64: Done test exception
406 09:53:13.384765 WDT: Last reset was cold boot
407 09:53:13.387648 SPI0(PAD0) initialized at 992727 Hz
408 09:53:13.391483 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
409 09:53:13.392010 Manufacturer: ef
410 09:53:13.398167 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
411 09:53:13.410685 Probing TPM: . done!
412 09:53:13.411188 TPM ready after 0 ms
413 09:53:13.417506 Connected to device vid:did:rid of 1ae0:0028:00
414 09:53:13.424600 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b81dc66
415 09:53:13.428061 Initialized TPM device CR50 revision 0
416 09:53:13.470438 tlcl_send_startup: Startup return code is 0
417 09:53:13.470952 TPM: setup succeeded
418 09:53:13.479049 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
419 09:53:13.481987 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
420 09:53:13.486034 in-header: 03 19 00 00 08 00 00 00
421 09:53:13.488876 in-data: a2 e0 47 00 13 00 00 00
422 09:53:13.492164 Chrome EC: UHEPI supported
423 09:53:13.498975 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
424 09:53:13.501979 in-header: 03 a1 00 00 08 00 00 00
425 09:53:13.505612 in-data: 84 60 60 10 00 00 00 00
426 09:53:13.506123 Phase 1
427 09:53:13.508720 FMAP: area GBB found @ 3f5000 (12032 bytes)
428 09:53:13.515526 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
429 09:53:13.522356 VB2:vb2_check_recovery() Recovery was requested manually
430 09:53:13.525454 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
431 09:53:13.531405 Recovery requested (1009000e)
432 09:53:13.540497 tlcl_extend: response is 0
433 09:53:13.545848 tlcl_extend: response is 0
434 09:53:13.570864
435 09:53:13.571373
436 09:53:13.577763 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
437 09:53:13.580950 ARM64: Exception handlers installed.
438 09:53:13.584458 ARM64: Testing exception
439 09:53:13.587300 ARM64: Done test exception
440 09:53:13.603367 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xaa70, sec=0x2030
441 09:53:13.609965 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
442 09:53:13.613163 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
443 09:53:13.621407 [RTC]rtc_get_frequency_meter,134: input=0xf, output=776
444 09:53:13.628310 [RTC]rtc_get_frequency_meter,134: input=0x17, output=957
445 09:53:13.635280 [RTC]rtc_get_frequency_meter,134: input=0x13, output=867
446 09:53:13.642379 [RTC]rtc_get_frequency_meter,134: input=0x11, output=822
447 09:53:13.649328 [RTC]rtc_get_frequency_meter,134: input=0x10, output=799
448 09:53:13.656422 [RTC]rtc_get_frequency_meter,134: input=0xf, output=776
449 09:53:13.663013 [RTC]rtc_get_frequency_meter,134: input=0x10, output=800
450 09:53:13.669818 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xaa70
451 09:53:13.673239 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
452 09:53:13.676898 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
453 09:53:13.680085 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
454 09:53:13.683133 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
455 09:53:13.686467 in-header: 03 19 00 00 08 00 00 00
456 09:53:13.690071 in-data: a2 e0 47 00 13 00 00 00
457 09:53:13.693633 Chrome EC: UHEPI supported
458 09:53:13.700208 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
459 09:53:13.703393 in-header: 03 a1 00 00 08 00 00 00
460 09:53:13.706819 in-data: 84 60 60 10 00 00 00 00
461 09:53:13.710096 Skip loading cached calibration data
462 09:53:13.716671 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
463 09:53:13.720350 in-header: 03 a1 00 00 08 00 00 00
464 09:53:13.724300 in-data: 84 60 60 10 00 00 00 00
465 09:53:13.730653 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
466 09:53:13.733913 in-header: 03 a1 00 00 08 00 00 00
467 09:53:13.737256 in-data: 84 60 60 10 00 00 00 00
468 09:53:13.740826 ADC[3]: Raw value=1042082 ID=8
469 09:53:13.741365 Manufacturer: ef
470 09:53:13.746919 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
471 09:53:13.750987 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
472 09:53:13.753909 CBFS @ 21000 size 3d4000
473 09:53:13.757240 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
474 09:53:13.763861 CBFS: Locating 'sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB'
475 09:53:13.767434 CBFS: Found @ offset 3c880 size 4b
476 09:53:13.767960 DRAM-K: Full Calibration
477 09:53:13.774017 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
478 09:53:13.774605 CBFS @ 21000 size 3d4000
479 09:53:13.780737 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
480 09:53:13.784008 CBFS: Locating 'fallback/dram'
481 09:53:13.787075 CBFS: Found @ offset 24b00 size 12268
482 09:53:13.814526 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
483 09:53:13.818103 ddr_geometry: 1, config: 0x0
484 09:53:13.821258 header.status = 0x0
485 09:53:13.824914 header.magic = 0x44524d4b (expected: 0x44524d4b)
486 09:53:13.827974 header.version = 0x5 (expected: 0x5)
487 09:53:13.831724 header.size = 0x8f0 (expected: 0x8f0)
488 09:53:13.832250 header.config = 0x0
489 09:53:13.834816 header.flags = 0x0
490 09:53:13.835257 header.checksum = 0x0
491 09:53:13.841616 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
492 09:53:13.848297 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
493 09:53:13.851778 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
494 09:53:13.854986 ddr_geometry:1
495 09:53:13.855512 [EMI] new MDL number = 1
496 09:53:13.858153 dram_cbt_mode_extern: 0
497 09:53:13.861848 dram_cbt_mode [RK0]: 0, [RK1]: 0
498 09:53:13.868599 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
499 09:53:13.869130
500 09:53:13.869570
501 09:53:13.869974 [Bianco] ETT version 0.0.0.1
502 09:53:13.874858 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
503 09:53:13.875299
504 09:53:13.878413 vSetVcoreByFreq with vcore:762500, freq=1600
505 09:53:13.878850
506 09:53:13.879280 [DramcInit]
507 09:53:13.881559 AutoRefreshCKEOff AutoREF OFF
508 09:53:13.885506 DDRPhyPLLSetting-CKEOFF
509 09:53:13.888335 DDRPhyPLLSetting-CKEON
510 09:53:13.888856
511 09:53:13.889301 Enable WDQS
512 09:53:13.891933 [ModeRegInit_LP4] CH0 RK0
513 09:53:13.895232 Write Rank0 MR13 =0x18
514 09:53:13.895760 Write Rank0 MR12 =0x5d
515 09:53:13.898795 Write Rank0 MR1 =0x56
516 09:53:13.902264 Write Rank0 MR2 =0x1a
517 09:53:13.902795 Write Rank0 MR11 =0x0
518 09:53:13.905446 Write Rank0 MR22 =0x38
519 09:53:13.905964 Write Rank0 MR14 =0x5d
520 09:53:13.908692 Write Rank0 MR3 =0x30
521 09:53:13.912154 Write Rank0 MR13 =0x58
522 09:53:13.912681 Write Rank0 MR12 =0x5d
523 09:53:13.915497 Write Rank0 MR1 =0x56
524 09:53:13.916018 Write Rank0 MR2 =0x2d
525 09:53:13.919217 Write Rank0 MR11 =0x23
526 09:53:13.922136 Write Rank0 MR22 =0x34
527 09:53:13.922701 Write Rank0 MR14 =0x10
528 09:53:13.925471 Write Rank0 MR3 =0x30
529 09:53:13.925907 Write Rank0 MR13 =0xd8
530 09:53:13.929267 [ModeRegInit_LP4] CH0 RK1
531 09:53:13.932494 Write Rank1 MR13 =0x18
532 09:53:13.933023 Write Rank1 MR12 =0x5d
533 09:53:13.936001 Write Rank1 MR1 =0x56
534 09:53:13.939092 Write Rank1 MR2 =0x1a
535 09:53:13.939589 Write Rank1 MR11 =0x0
536 09:53:13.942324 Write Rank1 MR22 =0x38
537 09:53:13.942847 Write Rank1 MR14 =0x5d
538 09:53:13.945860 Write Rank1 MR3 =0x30
539 09:53:13.949416 Write Rank1 MR13 =0x58
540 09:53:13.949943 Write Rank1 MR12 =0x5d
541 09:53:13.952641 Write Rank1 MR1 =0x56
542 09:53:13.953166 Write Rank1 MR2 =0x2d
543 09:53:13.955885 Write Rank1 MR11 =0x23
544 09:53:13.959099 Write Rank1 MR22 =0x34
545 09:53:13.959624 Write Rank1 MR14 =0x10
546 09:53:13.962147 Write Rank1 MR3 =0x30
547 09:53:13.962624 Write Rank1 MR13 =0xd8
548 09:53:13.965651 [ModeRegInit_LP4] CH1 RK0
549 09:53:13.969479 Write Rank0 MR13 =0x18
550 09:53:13.969993 Write Rank0 MR12 =0x5d
551 09:53:13.972760 Write Rank0 MR1 =0x56
552 09:53:13.975888 Write Rank0 MR2 =0x1a
553 09:53:13.976400 Write Rank0 MR11 =0x0
554 09:53:13.979432 Write Rank0 MR22 =0x38
555 09:53:13.979946 Write Rank0 MR14 =0x5d
556 09:53:13.982296 Write Rank0 MR3 =0x30
557 09:53:13.986264 Write Rank0 MR13 =0x58
558 09:53:13.986778 Write Rank0 MR12 =0x5d
559 09:53:13.989251 Write Rank0 MR1 =0x56
560 09:53:13.989761 Write Rank0 MR2 =0x2d
561 09:53:13.992673 Write Rank0 MR11 =0x23
562 09:53:13.996107 Write Rank0 MR22 =0x34
563 09:53:13.996619 Write Rank0 MR14 =0x10
564 09:53:13.999535 Write Rank0 MR3 =0x30
565 09:53:13.999962 Write Rank0 MR13 =0xd8
566 09:53:14.002942 [ModeRegInit_LP4] CH1 RK1
567 09:53:14.006054 Write Rank1 MR13 =0x18
568 09:53:14.006663 Write Rank1 MR12 =0x5d
569 09:53:14.009654 Write Rank1 MR1 =0x56
570 09:53:14.012789 Write Rank1 MR2 =0x1a
571 09:53:14.013306 Write Rank1 MR11 =0x0
572 09:53:14.016239 Write Rank1 MR22 =0x38
573 09:53:14.016686 Write Rank1 MR14 =0x5d
574 09:53:14.019539 Write Rank1 MR3 =0x30
575 09:53:14.022841 Write Rank1 MR13 =0x58
576 09:53:14.023395 Write Rank1 MR12 =0x5d
577 09:53:14.026488 Write Rank1 MR1 =0x56
578 09:53:14.027014 Write Rank1 MR2 =0x2d
579 09:53:14.029636 Write Rank1 MR11 =0x23
580 09:53:14.033035 Write Rank1 MR22 =0x34
581 09:53:14.033562 Write Rank1 MR14 =0x10
582 09:53:14.036351 Write Rank1 MR3 =0x30
583 09:53:14.036885 Write Rank1 MR13 =0xd8
584 09:53:14.039696 match AC timing 3
585 09:53:14.050016 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
586 09:53:14.050590 [MiockJmeterHQA]
587 09:53:14.053428 vSetVcoreByFreq with vcore:762500, freq=1600
588 09:53:14.159019
589 09:53:14.159546 MIOCK jitter meter ch=0
590 09:53:14.159987
591 09:53:14.162302 1T = (101-18) = 83 dly cells
592 09:53:14.169429 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 753/100 ps
593 09:53:14.172217 vSetVcoreByFreq with vcore:725000, freq=1200
594 09:53:14.270664
595 09:53:14.271217 MIOCK jitter meter ch=0
596 09:53:14.271659
597 09:53:14.274134 1T = (95-17) = 78 dly cells
598 09:53:14.281560 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
599 09:53:14.284634 vSetVcoreByFreq with vcore:725000, freq=800
600 09:53:14.381831
601 09:53:14.382408 MIOCK jitter meter ch=0
602 09:53:14.382855
603 09:53:14.385121 1T = (95-17) = 78 dly cells
604 09:53:14.392173 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
605 09:53:14.395215 vSetVcoreByFreq with vcore:762500, freq=1600
606 09:53:14.398367 vSetVcoreByFreq with vcore:762500, freq=1600
607 09:53:14.398890
608 09:53:14.399331 K DRVP
609 09:53:14.401703 1. OCD DRVP=0 CALOUT=0
610 09:53:14.405116 1. OCD DRVP=1 CALOUT=0
611 09:53:14.405650 1. OCD DRVP=2 CALOUT=0
612 09:53:14.408422 1. OCD DRVP=3 CALOUT=0
613 09:53:14.408942 1. OCD DRVP=4 CALOUT=0
614 09:53:14.411625 1. OCD DRVP=5 CALOUT=0
615 09:53:14.415035 1. OCD DRVP=6 CALOUT=0
616 09:53:14.415467 1. OCD DRVP=7 CALOUT=0
617 09:53:14.418302 1. OCD DRVP=8 CALOUT=1
618 09:53:14.418748
619 09:53:14.421825 1. OCD DRVP calibration OK! DRVP=8
620 09:53:14.422430
621 09:53:14.422868
622 09:53:14.423275
623 09:53:14.423665 K ODTN
624 09:53:14.425083 3. OCD ODTN=0 ,CALOUT=1
625 09:53:14.428584 3. OCD ODTN=1 ,CALOUT=1
626 09:53:14.429125 3. OCD ODTN=2 ,CALOUT=1
627 09:53:14.431861 3. OCD ODTN=3 ,CALOUT=1
628 09:53:14.432308 3. OCD ODTN=4 ,CALOUT=1
629 09:53:14.435260 3. OCD ODTN=5 ,CALOUT=1
630 09:53:14.438877 3. OCD ODTN=6 ,CALOUT=1
631 09:53:14.439406 3. OCD ODTN=7 ,CALOUT=0
632 09:53:14.439849
633 09:53:14.442159 3. OCD ODTN calibration OK! ODTN=7
634 09:53:14.442735
635 09:53:14.445214 [SwImpedanceCal] DRVP=8, DRVN=9, ODTN=7
636 09:53:14.452131 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15
637 09:53:14.455175 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 (After Adjust)
638 09:53:14.455634
639 09:53:14.455966 K DRVP
640 09:53:14.458761 1. OCD DRVP=0 CALOUT=0
641 09:53:14.461954 1. OCD DRVP=1 CALOUT=0
642 09:53:14.462436 1. OCD DRVP=2 CALOUT=0
643 09:53:14.465380 1. OCD DRVP=3 CALOUT=0
644 09:53:14.468970 1. OCD DRVP=4 CALOUT=0
645 09:53:14.469494 1. OCD DRVP=5 CALOUT=0
646 09:53:14.472134 1. OCD DRVP=6 CALOUT=0
647 09:53:14.472784 1. OCD DRVP=7 CALOUT=0
648 09:53:14.475614 1. OCD DRVP=8 CALOUT=0
649 09:53:14.478892 1. OCD DRVP=9 CALOUT=1
650 09:53:14.479329
651 09:53:14.481974 1. OCD DRVP calibration OK! DRVP=9
652 09:53:14.482463
653 09:53:14.482803
654 09:53:14.483108
655 09:53:14.483397 K ODTN
656 09:53:14.485259 3. OCD ODTN=0 ,CALOUT=1
657 09:53:14.485695 3. OCD ODTN=1 ,CALOUT=1
658 09:53:14.488909 3. OCD ODTN=2 ,CALOUT=1
659 09:53:14.492222 3. OCD ODTN=3 ,CALOUT=1
660 09:53:14.492804 3. OCD ODTN=4 ,CALOUT=1
661 09:53:14.495618 3. OCD ODTN=5 ,CALOUT=1
662 09:53:14.498980 3. OCD ODTN=6 ,CALOUT=1
663 09:53:14.499419 3. OCD ODTN=7 ,CALOUT=1
664 09:53:14.502025 3. OCD ODTN=8 ,CALOUT=1
665 09:53:14.502612 3. OCD ODTN=9 ,CALOUT=1
666 09:53:14.505865 3. OCD ODTN=10 ,CALOUT=1
667 09:53:14.508970 3. OCD ODTN=11 ,CALOUT=1
668 09:53:14.509413 3. OCD ODTN=12 ,CALOUT=1
669 09:53:14.512542 3. OCD ODTN=13 ,CALOUT=0
670 09:53:14.512981
671 09:53:14.515758 3. OCD ODTN calibration OK! ODTN=13
672 09:53:14.516201
673 09:53:14.519288 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=13
674 09:53:14.522372 term_option=1, Reg: DRVP=9, DRVN=9, ODTN=13
675 09:53:14.529032 term_option=1, Reg: DRVP=9, DRVN=9, ODTN=13 (After Adjust)
676 09:53:14.529472
677 09:53:14.529807 [DramcInit]
678 09:53:14.532511 AutoRefreshCKEOff AutoREF OFF
679 09:53:14.535844 DDRPhyPLLSetting-CKEOFF
680 09:53:14.536286 DDRPhyPLLSetting-CKEON
681 09:53:14.536627
682 09:53:14.539508 Enable WDQS
683 09:53:14.540025 ==
684 09:53:14.542829 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
685 09:53:14.546308 fsp= 1, odt_onoff= 1, Byte mode= 0
686 09:53:14.546826 ==
687 09:53:14.549276 [Duty_Offset_Calibration]
688 09:53:14.549704
689 09:53:14.552496 ===========================
690 09:53:14.552928 B0:1 B1:0 CA:0
691 09:53:14.576016 ==
692 09:53:14.579301 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
693 09:53:14.582562 fsp= 1, odt_onoff= 1, Byte mode= 0
694 09:53:14.582993 ==
695 09:53:14.586045 [Duty_Offset_Calibration]
696 09:53:14.586606
697 09:53:14.589111 ===========================
698 09:53:14.589541 B0:1 B1:-1 CA:-1
699 09:53:14.623616 [ModeRegInit_LP4] CH0 RK0
700 09:53:14.626781 Write Rank0 MR13 =0x18
701 09:53:14.627236 Write Rank0 MR12 =0x5d
702 09:53:14.630426 Write Rank0 MR1 =0x56
703 09:53:14.633385 Write Rank0 MR2 =0x1a
704 09:53:14.633815 Write Rank0 MR11 =0x0
705 09:53:14.637489 Write Rank0 MR22 =0x38
706 09:53:14.637920 Write Rank0 MR14 =0x5d
707 09:53:14.640443 Write Rank0 MR3 =0x30
708 09:53:14.643573 Write Rank0 MR13 =0x58
709 09:53:14.644007 Write Rank0 MR12 =0x5d
710 09:53:14.646915 Write Rank0 MR1 =0x56
711 09:53:14.647345 Write Rank0 MR2 =0x2d
712 09:53:14.650307 Write Rank0 MR11 =0x23
713 09:53:14.654047 Write Rank0 MR22 =0x34
714 09:53:14.654630 Write Rank0 MR14 =0x10
715 09:53:14.657110 Write Rank0 MR3 =0x30
716 09:53:14.657546 Write Rank0 MR13 =0xd8
717 09:53:14.660599 [ModeRegInit_LP4] CH0 RK1
718 09:53:14.663624 Write Rank1 MR13 =0x18
719 09:53:14.664057 Write Rank1 MR12 =0x5d
720 09:53:14.667172 Write Rank1 MR1 =0x56
721 09:53:14.670485 Write Rank1 MR2 =0x1a
722 09:53:14.670917 Write Rank1 MR11 =0x0
723 09:53:14.673970 Write Rank1 MR22 =0x38
724 09:53:14.674453 Write Rank1 MR14 =0x5d
725 09:53:14.677483 Write Rank1 MR3 =0x30
726 09:53:14.680885 Write Rank1 MR13 =0x58
727 09:53:14.681321 Write Rank1 MR12 =0x5d
728 09:53:14.683907 Write Rank1 MR1 =0x56
729 09:53:14.684339 Write Rank1 MR2 =0x2d
730 09:53:14.687596 Write Rank1 MR11 =0x23
731 09:53:14.690632 Write Rank1 MR22 =0x34
732 09:53:14.691079 Write Rank1 MR14 =0x10
733 09:53:14.694448 Write Rank1 MR3 =0x30
734 09:53:14.694963 Write Rank1 MR13 =0xd8
735 09:53:14.697490 [ModeRegInit_LP4] CH1 RK0
736 09:53:14.701040 Write Rank0 MR13 =0x18
737 09:53:14.701558 Write Rank0 MR12 =0x5d
738 09:53:14.704347 Write Rank0 MR1 =0x56
739 09:53:14.707770 Write Rank0 MR2 =0x1a
740 09:53:14.708286 Write Rank0 MR11 =0x0
741 09:53:14.710891 Write Rank0 MR22 =0x38
742 09:53:14.711321 Write Rank0 MR14 =0x5d
743 09:53:14.714489 Write Rank0 MR3 =0x30
744 09:53:14.717406 Write Rank0 MR13 =0x58
745 09:53:14.717837 Write Rank0 MR12 =0x5d
746 09:53:14.721071 Write Rank0 MR1 =0x56
747 09:53:14.721587 Write Rank0 MR2 =0x2d
748 09:53:14.724440 Write Rank0 MR11 =0x23
749 09:53:14.727759 Write Rank0 MR22 =0x34
750 09:53:14.728274 Write Rank0 MR14 =0x10
751 09:53:14.731138 Write Rank0 MR3 =0x30
752 09:53:14.731657 Write Rank0 MR13 =0xd8
753 09:53:14.734336 [ModeRegInit_LP4] CH1 RK1
754 09:53:14.738073 Write Rank1 MR13 =0x18
755 09:53:14.738630 Write Rank1 MR12 =0x5d
756 09:53:14.741336 Write Rank1 MR1 =0x56
757 09:53:14.744315 Write Rank1 MR2 =0x1a
758 09:53:14.744748 Write Rank1 MR11 =0x0
759 09:53:14.748038 Write Rank1 MR22 =0x38
760 09:53:14.748559 Write Rank1 MR14 =0x5d
761 09:53:14.751528 Write Rank1 MR3 =0x30
762 09:53:14.754647 Write Rank1 MR13 =0x58
763 09:53:14.755161 Write Rank1 MR12 =0x5d
764 09:53:14.757775 Write Rank1 MR1 =0x56
765 09:53:14.758204 Write Rank1 MR2 =0x2d
766 09:53:14.761269 Write Rank1 MR11 =0x23
767 09:53:14.764527 Write Rank1 MR22 =0x34
768 09:53:14.764962 Write Rank1 MR14 =0x10
769 09:53:14.767859 Write Rank1 MR3 =0x30
770 09:53:14.768553 Write Rank1 MR13 =0xd8
771 09:53:14.771134 match AC timing 3
772 09:53:14.781981 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
773 09:53:14.782690 DramC Write-DBI off
774 09:53:14.785049 DramC Read-DBI off
775 09:53:14.785557 Write Rank0 MR13 =0x59
776 09:53:14.788117 ==
777 09:53:14.791563 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
778 09:53:14.794901 fsp= 1, odt_onoff= 1, Byte mode= 0
779 09:53:14.795337 ==
780 09:53:14.798279 === u2Vref_new: 0x56 --> 0x2d
781 09:53:14.801559 === u2Vref_new: 0x58 --> 0x38
782 09:53:14.805078 === u2Vref_new: 0x5a --> 0x39
783 09:53:14.808219 === u2Vref_new: 0x5c --> 0x3c
784 09:53:14.808741 === u2Vref_new: 0x5e --> 0x3d
785 09:53:14.812035 === u2Vref_new: 0x60 --> 0xa0
786 09:53:14.815215 [CA 0] Center 33 (4~63) winsize 60
787 09:53:14.818643 [CA 1] Center 34 (6~63) winsize 58
788 09:53:14.822052 [CA 2] Center 27 (-1~56) winsize 58
789 09:53:14.825401 [CA 3] Center 23 (-4~51) winsize 56
790 09:53:14.828834 [CA 4] Center 24 (-3~52) winsize 56
791 09:53:14.831922 [CA 5] Center 28 (-1~58) winsize 60
792 09:53:14.832356
793 09:53:14.835863 [CATrainingPosCal] consider 1 rank data
794 09:53:14.838754 u2DelayCellTimex100 = 753/100 ps
795 09:53:14.842380 CA0 delay=33 (4~63),Diff = 10 PI (12 cell)
796 09:53:14.845398 CA1 delay=34 (6~63),Diff = 11 PI (14 cell)
797 09:53:14.849096 CA2 delay=27 (-1~56),Diff = 4 PI (5 cell)
798 09:53:14.852409 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
799 09:53:14.859165 CA4 delay=24 (-3~52),Diff = 1 PI (1 cell)
800 09:53:14.862410 CA5 delay=28 (-1~58),Diff = 5 PI (6 cell)
801 09:53:14.862929
802 09:53:14.865800 CA PerBit enable=1, Macro0, CA PI delay=23
803 09:53:14.869006 === u2Vref_new: 0x56 --> 0x2d
804 09:53:14.869506
805 09:53:14.869841 Vref(ca) range 1: 22
806 09:53:14.870153
807 09:53:14.872327 CS Dly= 10 (41-0-32)
808 09:53:14.875702 Write Rank0 MR13 =0xd8
809 09:53:14.876216 Write Rank0 MR13 =0xd8
810 09:53:14.878980 Write Rank0 MR12 =0x56
811 09:53:14.879410 Write Rank1 MR13 =0x59
812 09:53:14.882306 ==
813 09:53:14.885793 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
814 09:53:14.889125 fsp= 1, odt_onoff= 1, Byte mode= 0
815 09:53:14.889612 ==
816 09:53:14.892508 === u2Vref_new: 0x56 --> 0x2d
817 09:53:14.895858 === u2Vref_new: 0x58 --> 0x38
818 09:53:14.899261 === u2Vref_new: 0x5a --> 0x39
819 09:53:14.902387 === u2Vref_new: 0x5c --> 0x3c
820 09:53:14.902865 === u2Vref_new: 0x5e --> 0x3d
821 09:53:14.906460 === u2Vref_new: 0x60 --> 0xa0
822 09:53:14.909832 [CA 0] Center 33 (4~63) winsize 60
823 09:53:14.912944 [CA 1] Center 34 (5~63) winsize 59
824 09:53:14.916523 [CA 2] Center 28 (0~56) winsize 57
825 09:53:14.919665 [CA 3] Center 23 (-4~51) winsize 56
826 09:53:14.923124 [CA 4] Center 24 (-3~52) winsize 56
827 09:53:14.926502 [CA 5] Center 29 (1~58) winsize 58
828 09:53:14.927018
829 09:53:14.930043 [CATrainingPosCal] consider 2 rank data
830 09:53:14.933202 u2DelayCellTimex100 = 753/100 ps
831 09:53:14.936617 CA0 delay=33 (4~63),Diff = 10 PI (12 cell)
832 09:53:14.939800 CA1 delay=34 (6~63),Diff = 11 PI (14 cell)
833 09:53:14.943374 CA2 delay=28 (0~56),Diff = 5 PI (6 cell)
834 09:53:14.946618 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
835 09:53:14.953261 CA4 delay=24 (-3~52),Diff = 1 PI (1 cell)
836 09:53:14.956870 CA5 delay=29 (1~58),Diff = 6 PI (7 cell)
837 09:53:14.957384
838 09:53:14.960075 CA PerBit enable=1, Macro0, CA PI delay=23
839 09:53:14.963483 === u2Vref_new: 0x56 --> 0x2d
840 09:53:14.964004
841 09:53:14.964338 Vref(ca) range 1: 22
842 09:53:14.964645
843 09:53:14.966658 CS Dly= 7 (38-0-32)
844 09:53:14.967177 Write Rank1 MR13 =0xd8
845 09:53:14.969965 Write Rank1 MR13 =0xd8
846 09:53:14.973379 Write Rank1 MR12 =0x56
847 09:53:14.976658 [RankSwap] Rank num 2, (Multi 1), Rank 0
848 09:53:14.977176 Write Rank0 MR2 =0xad
849 09:53:14.980022 [Write Leveling]
850 09:53:14.983616 delay byte0 byte1 byte2 byte3
851 09:53:14.984140
852 09:53:14.984478 10 0 0
853 09:53:14.986674 11 0 0
854 09:53:14.987113 12 0 0
855 09:53:14.987452 13 0 0
856 09:53:14.989814 14 0 0
857 09:53:14.990274 15 0 0
858 09:53:14.993425 16 0 0
859 09:53:14.993950 17 0 0
860 09:53:14.994352 18 0 0
861 09:53:14.996810 19 0 0
862 09:53:14.997330 20 0 0
863 09:53:15.000186 21 0 0
864 09:53:15.000712 22 0 0
865 09:53:15.003191 23 0 0
866 09:53:15.003626 24 0 0
867 09:53:15.003963 25 0 0
868 09:53:15.006766 26 0 0
869 09:53:15.007291 27 0 0
870 09:53:15.010393 28 0 ff
871 09:53:15.010919 29 0 ff
872 09:53:15.011264 30 0 ff
873 09:53:15.013338 31 0 ff
874 09:53:15.013715 32 0 ff
875 09:53:15.016899 33 0 ff
876 09:53:15.017424 34 ff ff
877 09:53:15.020106 35 ff ff
878 09:53:15.020562 36 ff ff
879 09:53:15.023723 37 ff ff
880 09:53:15.024254 38 ff ff
881 09:53:15.026797 39 ff ff
882 09:53:15.027238 40 ff ff
883 09:53:15.030372 pass bytecount = 0xff (0xff: all bytes pass)
884 09:53:15.030901
885 09:53:15.033617 DQS0 dly: 34
886 09:53:15.034048 DQS1 dly: 28
887 09:53:15.037262 Write Rank0 MR2 =0x2d
888 09:53:15.040422 [RankSwap] Rank num 2, (Multi 1), Rank 0
889 09:53:15.040943 Write Rank0 MR1 =0xd6
890 09:53:15.043804 [Gating]
891 09:53:15.044324 ==
892 09:53:15.046941 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
893 09:53:15.050668 fsp= 1, odt_onoff= 1, Byte mode= 0
894 09:53:15.051189 ==
895 09:53:15.054026 3 1 0 |3534 1d1d |(11 11)(11 11) |(1 1)(1 1)| 0
896 09:53:15.060680 3 1 4 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
897 09:53:15.063966 3 1 8 |3534 e0d |(11 11)(11 11) |(0 0)(1 1)| 0
898 09:53:15.067356 3 1 12 |3534 3332 |(11 11)(11 11) |(0 0)(0 1)| 0
899 09:53:15.073967 3 1 16 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
900 09:53:15.077235 3 1 20 |3534 3434 |(11 11)(11 11) |(0 0)(0 1)| 0
901 09:53:15.080631 3 1 24 |3534 3232 |(11 11)(0 0) |(0 1)(0 1)| 0
902 09:53:15.083885 3 1 28 |3534 909 |(11 11)(11 11) |(0 1)(0 1)| 0
903 09:53:15.090719 3 2 0 |3534 3433 |(11 11)(11 11) |(1 1)(0 1)| 0
904 09:53:15.093831 3 2 4 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
905 09:53:15.097433 3 2 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
906 09:53:15.103970 3 2 12 |3d3d 202 |(11 11)(11 11) |(1 1)(1 1)| 0
907 09:53:15.107512 [Byte 1] Lead/lag Transition tap number (1)
908 09:53:15.111212 3 2 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(0 0)| 0
909 09:53:15.114009 3 2 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
910 09:53:15.120630 3 2 24 |3d3d 3939 |(11 11)(11 11) |(1 1)(1 1)| 0
911 09:53:15.124303 3 2 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
912 09:53:15.127521 3 3 0 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
913 09:53:15.134321 3 3 4 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
914 09:53:15.137819 3 3 8 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
915 09:53:15.140892 [Byte 0] Lead/lag Transition tap number (1)
916 09:53:15.144261 [Byte 1] Lead/lag falling Transition (3, 3, 8)
917 09:53:15.147878 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
918 09:53:15.154648 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
919 09:53:15.157980 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
920 09:53:15.161295 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
921 09:53:15.167838 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
922 09:53:15.171532 3 4 0 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
923 09:53:15.174593 3 4 4 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
924 09:53:15.177957 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
925 09:53:15.184957 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
926 09:53:15.188214 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
927 09:53:15.191346 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 09:53:15.198189 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 09:53:15.201792 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 09:53:15.204892 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 09:53:15.211689 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 09:53:15.214909 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 09:53:15.218490 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
934 09:53:15.221896 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
935 09:53:15.228386 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
936 09:53:15.231931 [Byte 0] Lead/lag falling Transition (3, 5, 20)
937 09:53:15.235549 [Byte 1] Lead/lag falling Transition (3, 5, 20)
938 09:53:15.241778 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
939 09:53:15.245423 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
940 09:53:15.248827 [Byte 0] Lead/lag Transition tap number (3)
941 09:53:15.252038 [Byte 1] Lead/lag Transition tap number (3)
942 09:53:15.255363 3 6 0 |202 2726 |(11 11)(11 11) |(0 0)(0 0)| 0
943 09:53:15.262087 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
944 09:53:15.262635 [Byte 0]First pass (3, 6, 4)
945 09:53:15.268531 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
946 09:53:15.269040 [Byte 1]First pass (3, 6, 8)
947 09:53:15.275363 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
948 09:53:15.278760 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
949 09:53:15.282322 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 09:53:15.285582 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 09:53:15.288952 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 09:53:15.296055 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
953 09:53:15.299004 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
954 09:53:15.302503 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
955 09:53:15.306144 All bytes gating window > 1UI, Early break!
956 09:53:15.306688
957 09:53:15.309185 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 26)
958 09:53:15.309696
959 09:53:15.312247 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 26)
960 09:53:15.312674
961 09:53:15.313004
962 09:53:15.315592
963 09:53:15.319283 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 26)
964 09:53:15.319797
965 09:53:15.322526 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 26)
966 09:53:15.322953
967 09:53:15.323280
968 09:53:15.325946 Write Rank0 MR1 =0x56
969 09:53:15.326494
970 09:53:15.326834 best RODT dly(2T, 0.5T) = (2, 2)
971 09:53:15.329314
972 09:53:15.329842 best RODT dly(2T, 0.5T) = (2, 2)
973 09:53:15.332449 ==
974 09:53:15.336128 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
975 09:53:15.339302 fsp= 1, odt_onoff= 1, Byte mode= 0
976 09:53:15.339817 ==
977 09:53:15.342900 Start DQ dly to find pass range UseTestEngine =0
978 09:53:15.346049 x-axis: bit #, y-axis: DQ dly (-127~63)
979 09:53:15.349508 RX Vref Scan = 0
980 09:53:15.352862 -26, [0] xxxxxxxx xxxxxxxx [MSB]
981 09:53:15.356023 -25, [0] xxxxxxxx xxxxxxxx [MSB]
982 09:53:15.356545 -24, [0] xxxxxxxx xxxxxxxx [MSB]
983 09:53:15.359483 -23, [0] xxxxxxxx xxxxxxxx [MSB]
984 09:53:15.363083 -22, [0] xxxxxxxx xxxxxxxx [MSB]
985 09:53:15.366077 -21, [0] xxxxxxxx xxxxxxxx [MSB]
986 09:53:15.369516 -20, [0] xxxxxxxx xxxxxxxx [MSB]
987 09:53:15.372754 -19, [0] xxxxxxxx xxxxxxxx [MSB]
988 09:53:15.376167 -18, [0] xxxxxxxx xxxxxxxx [MSB]
989 09:53:15.379627 -17, [0] xxxxxxxx xxxxxxxx [MSB]
990 09:53:15.380157 -16, [0] xxxxxxxx xxxxxxxx [MSB]
991 09:53:15.382737 -15, [0] xxxxxxxx xxxxxxxx [MSB]
992 09:53:15.386360 -14, [0] xxxxxxxx xxxxxxxx [MSB]
993 09:53:15.389559 -13, [0] xxxxxxxx xxxxxxxx [MSB]
994 09:53:15.392824 -12, [0] xxxxxxxx xxxxxxxx [MSB]
995 09:53:15.396349 -11, [0] xxxxxxxx xxxxxxxx [MSB]
996 09:53:15.399751 -10, [0] xxxxxxxx xxxxxxxx [MSB]
997 09:53:15.400298 -9, [0] xxxxxxxx xxxxxxxx [MSB]
998 09:53:15.402933 -8, [0] xxxxxxxx xxxxxxxx [MSB]
999 09:53:15.406377 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1000 09:53:15.410180 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1001 09:53:15.413394 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1002 09:53:15.416619 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1003 09:53:15.419928 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1004 09:53:15.420370 -2, [0] xxxoxxxx xxxxxxxx [MSB]
1005 09:53:15.423785 -1, [0] xxxoxxxx xxxxxxxx [MSB]
1006 09:53:15.426881 0, [0] xxxoxoox xxxxxoxx [MSB]
1007 09:53:15.430385 1, [0] xxxoxooo xoxxxoxx [MSB]
1008 09:53:15.433448 2, [0] xxxoxooo ooxxxoxx [MSB]
1009 09:53:15.433897 3, [0] xxxoxooo ooxoooxx [MSB]
1010 09:53:15.437315 4, [0] xxxoxooo ooxooooo [MSB]
1011 09:53:15.440355 5, [0] xxxoxooo ooxooooo [MSB]
1012 09:53:15.444022 6, [0] xxoooooo oooooooo [MSB]
1013 09:53:15.447011 7, [0] xooooooo oooooooo [MSB]
1014 09:53:15.450374 30, [0] oooxoooo oooooooo [MSB]
1015 09:53:15.450904 31, [0] oooxoooo oooooooo [MSB]
1016 09:53:15.453582 32, [0] oooxoxxo oooooooo [MSB]
1017 09:53:15.456975 33, [0] oooxoxxo ooooooxo [MSB]
1018 09:53:15.460282 34, [0] oooxoxxo oooxooxo [MSB]
1019 09:53:15.463767 35, [0] oooxoxxo xooxooxo [MSB]
1020 09:53:15.467130 36, [0] oooxoxxx xooxooxo [MSB]
1021 09:53:15.470387 37, [0] oooxoxxx xooxxxxo [MSB]
1022 09:53:15.470921 38, [0] oooxxxxx xxoxxxxx [MSB]
1023 09:53:15.473446 39, [0] oxoxxxxx xxoxxxxx [MSB]
1024 09:53:15.477329 40, [0] oxxxxxxx xxoxxxxx [MSB]
1025 09:53:15.480415 41, [0] xxxxxxxx xxxxxxxx [MSB]
1026 09:53:15.483857 iDelay=41, Bit 0, Center 24 (8 ~ 40) 33
1027 09:53:15.487007 iDelay=41, Bit 1, Center 22 (7 ~ 38) 32
1028 09:53:15.490760 iDelay=41, Bit 2, Center 22 (6 ~ 39) 34
1029 09:53:15.494014 iDelay=41, Bit 3, Center 13 (-2 ~ 29) 32
1030 09:53:15.497156 iDelay=41, Bit 4, Center 21 (6 ~ 37) 32
1031 09:53:15.500952 iDelay=41, Bit 5, Center 15 (0 ~ 31) 32
1032 09:53:15.504037 iDelay=41, Bit 6, Center 15 (0 ~ 31) 32
1033 09:53:15.507163 iDelay=41, Bit 7, Center 18 (1 ~ 35) 35
1034 09:53:15.510861 iDelay=41, Bit 8, Center 18 (2 ~ 34) 33
1035 09:53:15.517123 iDelay=41, Bit 9, Center 19 (1 ~ 37) 37
1036 09:53:15.520419 iDelay=41, Bit 10, Center 23 (6 ~ 40) 35
1037 09:53:15.523752 iDelay=41, Bit 11, Center 18 (3 ~ 33) 31
1038 09:53:15.527164 iDelay=41, Bit 12, Center 19 (3 ~ 36) 34
1039 09:53:15.530548 iDelay=41, Bit 13, Center 18 (0 ~ 36) 37
1040 09:53:15.533861 iDelay=41, Bit 14, Center 18 (4 ~ 32) 29
1041 09:53:15.537696 iDelay=41, Bit 15, Center 20 (4 ~ 37) 34
1042 09:53:15.538290 ==
1043 09:53:15.544396 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1044 09:53:15.544921 fsp= 1, odt_onoff= 1, Byte mode= 0
1045 09:53:15.547535 ==
1046 09:53:15.547969 DQS Delay:
1047 09:53:15.548309 DQS0 = 0, DQS1 = 0
1048 09:53:15.551140 DQM Delay:
1049 09:53:15.551661 DQM0 = 18, DQM1 = 19
1050 09:53:15.554449 DQ Delay:
1051 09:53:15.554972 DQ0 =24, DQ1 =22, DQ2 =22, DQ3 =13
1052 09:53:15.557876 DQ4 =21, DQ5 =15, DQ6 =15, DQ7 =18
1053 09:53:15.561258 DQ8 =18, DQ9 =19, DQ10 =23, DQ11 =18
1054 09:53:15.564387 DQ12 =19, DQ13 =18, DQ14 =18, DQ15 =20
1055 09:53:15.564907
1056 09:53:15.567677
1057 09:53:15.568194 DramC Write-DBI off
1058 09:53:15.568530 ==
1059 09:53:15.574404 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1060 09:53:15.577571 fsp= 1, odt_onoff= 1, Byte mode= 0
1061 09:53:15.578007 ==
1062 09:53:15.581234 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1063 09:53:15.581754
1064 09:53:15.584805 Begin, DQ Scan Range 924~1180
1065 09:53:15.585325
1066 09:53:15.585658
1067 09:53:15.585964 TX Vref Scan disable
1068 09:53:15.591161 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1069 09:53:15.594624 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1070 09:53:15.597926 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1071 09:53:15.601406 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1072 09:53:15.604361 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1073 09:53:15.608108 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1074 09:53:15.611088 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1075 09:53:15.614693 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1076 09:53:15.617915 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1077 09:53:15.621257 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1078 09:53:15.625021 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1079 09:53:15.628146 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1080 09:53:15.631431 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1081 09:53:15.634921 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1082 09:53:15.638170 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1083 09:53:15.641467 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1084 09:53:15.644775 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1085 09:53:15.648069 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1086 09:53:15.651535 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1087 09:53:15.658369 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1088 09:53:15.661769 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1089 09:53:15.664833 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1090 09:53:15.668533 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1091 09:53:15.671657 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1092 09:53:15.675359 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1093 09:53:15.678562 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1094 09:53:15.682003 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1095 09:53:15.685464 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1096 09:53:15.688660 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1097 09:53:15.691988 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1098 09:53:15.695184 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1099 09:53:15.698818 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1100 09:53:15.702318 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1101 09:53:15.705334 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1102 09:53:15.708869 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1103 09:53:15.712053 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1104 09:53:15.715617 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1105 09:53:15.719003 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1106 09:53:15.722156 962 |3 6 2|[0] xxxxxxxx oxxxxxxx [MSB]
1107 09:53:15.725606 963 |3 6 3|[0] xxxxxxxx oxxoxxxx [MSB]
1108 09:53:15.728893 964 |3 6 4|[0] xxxxxxxx ooxoooox [MSB]
1109 09:53:15.732258 965 |3 6 5|[0] xxxxxxxx ooxoooox [MSB]
1110 09:53:15.735744 966 |3 6 6|[0] xxxxxxxx ooxoooox [MSB]
1111 09:53:15.739082 967 |3 6 7|[0] xxxxxxxx ooxooooo [MSB]
1112 09:53:15.745578 968 |3 6 8|[0] xxxxxxxx ooxooooo [MSB]
1113 09:53:15.748922 969 |3 6 9|[0] xxxxxxxx oooooooo [MSB]
1114 09:53:15.752441 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB]
1115 09:53:15.755679 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
1116 09:53:15.758951 972 |3 6 12|[0] xxxoxoxx oooooooo [MSB]
1117 09:53:15.762472 973 |3 6 13|[0] xxxoxooo oooooooo [MSB]
1118 09:53:15.765612 974 |3 6 14|[0] xxxoxooo oooooooo [MSB]
1119 09:53:15.769259 975 |3 6 15|[0] xxxooooo oooooooo [MSB]
1120 09:53:15.772457 976 |3 6 16|[0] xooooooo oooooooo [MSB]
1121 09:53:15.779619 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1122 09:53:15.782598 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1123 09:53:15.786074 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1124 09:53:15.789246 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1125 09:53:15.792975 993 |3 6 33|[0] oooxoxoo xxxxxxxx [MSB]
1126 09:53:15.796427 994 |3 6 34|[0] oooxoxoo xxxxxxxx [MSB]
1127 09:53:15.799263 995 |3 6 35|[0] oooxoxxo xxxxxxxx [MSB]
1128 09:53:15.802632 996 |3 6 36|[0] oooxoxxo xxxxxxxx [MSB]
1129 09:53:15.806069 997 |3 6 37|[0] xxxxxxxx xxxxxxxx [MSB]
1130 09:53:15.809747 Byte0, DQ PI dly=984, DQM PI dly= 984
1131 09:53:15.812826 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
1132 09:53:15.813345
1133 09:53:15.819391 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
1134 09:53:15.819827
1135 09:53:15.822583 Byte1, DQ PI dly=976, DQM PI dly= 976
1136 09:53:15.826309 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
1137 09:53:15.826784
1138 09:53:15.829417 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
1139 09:53:15.829853
1140 09:53:15.830185 ==
1141 09:53:15.836320 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1142 09:53:15.839696 fsp= 1, odt_onoff= 1, Byte mode= 0
1143 09:53:15.840222 ==
1144 09:53:15.842813 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1145 09:53:15.843248
1146 09:53:15.846392 Begin, DQ Scan Range 952~1016
1147 09:53:15.849627 Write Rank0 MR14 =0x0
1148 09:53:15.857174
1149 09:53:15.857693 CH=0, VrefRange= 0, VrefLevel = 0
1150 09:53:15.864236 TX Bit0 (978~997) 20 987, Bit8 (965~984) 20 974,
1151 09:53:15.867265 TX Bit1 (977~994) 18 985, Bit9 (967~986) 20 976,
1152 09:53:15.870850 TX Bit2 (977~995) 19 986, Bit10 (970~990) 21 980,
1153 09:53:15.877308 TX Bit3 (971~990) 20 980, Bit11 (967~984) 18 975,
1154 09:53:15.880907 TX Bit4 (977~996) 20 986, Bit12 (967~985) 19 976,
1155 09:53:15.887780 TX Bit5 (975~990) 16 982, Bit13 (967~984) 18 975,
1156 09:53:15.891004 TX Bit6 (975~991) 17 983, Bit14 (968~985) 18 976,
1157 09:53:15.894183 TX Bit7 (976~993) 18 984, Bit15 (969~989) 21 979,
1158 09:53:15.894663
1159 09:53:15.897801 Write Rank0 MR14 =0x2
1160 09:53:15.906648
1161 09:53:15.907167 CH=0, VrefRange= 0, VrefLevel = 2
1162 09:53:15.913461 TX Bit0 (978~997) 20 987, Bit8 (965~984) 20 974,
1163 09:53:15.916230 TX Bit1 (978~994) 17 986, Bit9 (967~987) 21 977,
1164 09:53:15.919783 TX Bit2 (977~996) 20 986, Bit10 (970~990) 21 980,
1165 09:53:15.926918 TX Bit3 (971~990) 20 980, Bit11 (966~985) 20 975,
1166 09:53:15.929968 TX Bit4 (976~996) 21 986, Bit12 (967~986) 20 976,
1167 09:53:15.936762 TX Bit5 (975~990) 16 982, Bit13 (967~984) 18 975,
1168 09:53:15.940765 TX Bit6 (976~991) 16 983, Bit14 (967~985) 19 976,
1169 09:53:15.943686 TX Bit7 (976~994) 19 985, Bit15 (969~989) 21 979,
1170 09:53:15.944209
1171 09:53:15.947031 Write Rank0 MR14 =0x4
1172 09:53:15.955650
1173 09:53:15.956167 CH=0, VrefRange= 0, VrefLevel = 4
1174 09:53:15.962335 TX Bit0 (977~997) 21 987, Bit8 (965~984) 20 974,
1175 09:53:15.965443 TX Bit1 (977~995) 19 986, Bit9 (967~987) 21 977,
1176 09:53:15.972214 TX Bit2 (977~996) 20 986, Bit10 (970~990) 21 980,
1177 09:53:15.975698 TX Bit3 (971~990) 20 980, Bit11 (965~986) 22 975,
1178 09:53:15.978632 TX Bit4 (976~997) 22 986, Bit12 (967~987) 21 977,
1179 09:53:15.985532 TX Bit5 (975~991) 17 983, Bit13 (967~985) 19 976,
1180 09:53:15.989030 TX Bit6 (975~991) 17 983, Bit14 (967~986) 20 976,
1181 09:53:15.992205 TX Bit7 (976~994) 19 985, Bit15 (969~989) 21 979,
1182 09:53:15.992727
1183 09:53:15.995565 wait MRW command Rank0 MR14 =0x6 fired (1)
1184 09:53:15.998704 Write Rank0 MR14 =0x6
1185 09:53:16.008595
1186 09:53:16.009110 CH=0, VrefRange= 0, VrefLevel = 6
1187 09:53:16.015036 TX Bit0 (977~998) 22 987, Bit8 (964~985) 22 974,
1188 09:53:16.018348 TX Bit1 (977~995) 19 986, Bit9 (966~988) 23 977,
1189 09:53:16.021698 TX Bit2 (977~997) 21 987, Bit10 (969~990) 22 979,
1190 09:53:16.028650 TX Bit3 (970~990) 21 980, Bit11 (965~986) 22 975,
1191 09:53:16.031815 TX Bit4 (976~997) 22 986, Bit12 (966~988) 23 977,
1192 09:53:16.038615 TX Bit5 (974~991) 18 982, Bit13 (967~985) 19 976,
1193 09:53:16.042197 TX Bit6 (975~991) 17 983, Bit14 (967~987) 21 977,
1194 09:53:16.045424 TX Bit7 (975~995) 21 985, Bit15 (968~989) 22 978,
1195 09:53:16.045953
1196 09:53:16.048718 Write Rank0 MR14 =0x8
1197 09:53:16.057803
1198 09:53:16.058364 CH=0, VrefRange= 0, VrefLevel = 8
1199 09:53:16.064212 TX Bit0 (977~998) 22 987, Bit8 (964~985) 22 974,
1200 09:53:16.067785 TX Bit1 (977~996) 20 986, Bit9 (965~988) 24 976,
1201 09:53:16.074340 TX Bit2 (977~997) 21 987, Bit10 (969~991) 23 980,
1202 09:53:16.077653 TX Bit3 (970~991) 22 980, Bit11 (965~987) 23 976,
1203 09:53:16.080979 TX Bit4 (976~998) 23 987, Bit12 (967~988) 22 977,
1204 09:53:16.087825 TX Bit5 (974~991) 18 982, Bit13 (966~986) 21 976,
1205 09:53:16.091134 TX Bit6 (975~992) 18 983, Bit14 (966~988) 23 977,
1206 09:53:16.094612 TX Bit7 (975~996) 22 985, Bit15 (968~990) 23 979,
1207 09:53:16.095149
1208 09:53:16.145845 Write Rank0 MR14 =0xa
1209 09:53:16.146448
1210 09:53:16.146791 CH=0, VrefRange= 0, VrefLevel = 10
1211 09:53:16.147104 TX Bit0 (977~998) 22 987, Bit8 (963~986) 24 974,
1212 09:53:16.147741 TX Bit1 (977~997) 21 987, Bit9 (965~989) 25 977,
1213 09:53:16.148070 TX Bit2 (977~997) 21 987, Bit10 (969~991) 23 980,
1214 09:53:16.148369 TX Bit3 (969~991) 23 980, Bit11 (964~988) 25 976,
1215 09:53:16.148656 TX Bit4 (976~998) 23 987, Bit12 (966~988) 23 977,
1216 09:53:16.148938 TX Bit5 (973~992) 20 982, Bit13 (966~987) 22 976,
1217 09:53:16.149218 TX Bit6 (974~992) 19 983, Bit14 (966~988) 23 977,
1218 09:53:16.149560 TX Bit7 (975~996) 22 985, Bit15 (968~990) 23 979,
1219 09:53:16.149850
1220 09:53:16.150129 Write Rank0 MR14 =0xc
1221 09:53:16.156013
1222 09:53:16.159386 CH=0, VrefRange= 0, VrefLevel = 12
1223 09:53:16.162959 TX Bit0 (977~998) 22 987, Bit8 (963~986) 24 974,
1224 09:53:16.166368 TX Bit1 (977~997) 21 987, Bit9 (965~989) 25 977,
1225 09:53:16.173000 TX Bit2 (976~998) 23 987, Bit10 (969~991) 23 980,
1226 09:53:16.176225 TX Bit3 (969~991) 23 980, Bit11 (964~988) 25 976,
1227 09:53:16.179204 TX Bit4 (976~998) 23 987, Bit12 (965~989) 25 977,
1228 09:53:16.186201 TX Bit5 (973~992) 20 982, Bit13 (966~988) 23 977,
1229 09:53:16.189426 TX Bit6 (974~993) 20 983, Bit14 (965~988) 24 976,
1230 09:53:16.192895 TX Bit7 (974~997) 24 985, Bit15 (968~990) 23 979,
1231 09:53:16.193411
1232 09:53:16.196028 Write Rank0 MR14 =0xe
1233 09:53:16.205288
1234 09:53:16.208538 CH=0, VrefRange= 0, VrefLevel = 14
1235 09:53:16.211895 TX Bit0 (977~998) 22 987, Bit8 (963~987) 25 975,
1236 09:53:16.215272 TX Bit1 (976~997) 22 986, Bit9 (964~989) 26 976,
1237 09:53:16.221988 TX Bit2 (976~998) 23 987, Bit10 (969~992) 24 980,
1238 09:53:16.225780 TX Bit3 (969~992) 24 980, Bit11 (964~989) 26 976,
1239 09:53:16.228942 TX Bit4 (975~998) 24 986, Bit12 (966~989) 24 977,
1240 09:53:16.235290 TX Bit5 (972~993) 22 982, Bit13 (965~988) 24 976,
1241 09:53:16.239106 TX Bit6 (973~994) 22 983, Bit14 (965~989) 25 977,
1242 09:53:16.242323 TX Bit7 (974~997) 24 985, Bit15 (967~990) 24 978,
1243 09:53:16.242841
1244 09:53:16.245414 Write Rank0 MR14 =0x10
1245 09:53:16.254756
1246 09:53:16.255263 CH=0, VrefRange= 0, VrefLevel = 16
1247 09:53:16.261595 TX Bit0 (976~999) 24 987, Bit8 (962~988) 27 975,
1248 09:53:16.264890 TX Bit1 (976~997) 22 986, Bit9 (964~989) 26 976,
1249 09:53:16.271665 TX Bit2 (976~998) 23 987, Bit10 (968~992) 25 980,
1250 09:53:16.274959 TX Bit3 (969~992) 24 980, Bit11 (963~989) 27 976,
1251 09:53:16.278467 TX Bit4 (975~999) 25 987, Bit12 (965~990) 26 977,
1252 09:53:16.285085 TX Bit5 (971~993) 23 982, Bit13 (964~988) 25 976,
1253 09:53:16.288539 TX Bit6 (973~994) 22 983, Bit14 (964~989) 26 976,
1254 09:53:16.291439 TX Bit7 (973~997) 25 985, Bit15 (967~991) 25 979,
1255 09:53:16.291875
1256 09:53:16.295105 Write Rank0 MR14 =0x12
1257 09:53:16.304378
1258 09:53:16.307333 CH=0, VrefRange= 0, VrefLevel = 18
1259 09:53:16.310892 TX Bit0 (976~999) 24 987, Bit8 (962~988) 27 975,
1260 09:53:16.314348 TX Bit1 (976~998) 23 987, Bit9 (963~989) 27 976,
1261 09:53:16.321124 TX Bit2 (976~999) 24 987, Bit10 (969~992) 24 980,
1262 09:53:16.324544 TX Bit3 (968~992) 25 980, Bit11 (963~989) 27 976,
1263 09:53:16.327950 TX Bit4 (975~999) 25 987, Bit12 (964~990) 27 977,
1264 09:53:16.334467 TX Bit5 (971~993) 23 982, Bit13 (964~989) 26 976,
1265 09:53:16.337957 TX Bit6 (972~995) 24 983, Bit14 (964~989) 26 976,
1266 09:53:16.341308 TX Bit7 (973~998) 26 985, Bit15 (967~991) 25 979,
1267 09:53:16.341823
1268 09:53:16.344561 Write Rank0 MR14 =0x14
1269 09:53:16.354085
1270 09:53:16.357484 CH=0, VrefRange= 0, VrefLevel = 20
1271 09:53:16.360688 TX Bit0 (976~1000) 25 988, Bit8 (962~989) 28 975,
1272 09:53:16.363793 TX Bit1 (976~998) 23 987, Bit9 (964~989) 26 976,
1273 09:53:16.370916 TX Bit2 (976~999) 24 987, Bit10 (968~992) 25 980,
1274 09:53:16.374162 TX Bit3 (968~992) 25 980, Bit11 (963~989) 27 976,
1275 09:53:16.377568 TX Bit4 (975~999) 25 987, Bit12 (964~990) 27 977,
1276 09:53:16.384292 TX Bit5 (971~994) 24 982, Bit13 (963~989) 27 976,
1277 09:53:16.387499 TX Bit6 (972~995) 24 983, Bit14 (963~989) 27 976,
1278 09:53:16.390832 TX Bit7 (972~998) 27 985, Bit15 (966~991) 26 978,
1279 09:53:16.391269
1280 09:53:16.394106 Write Rank0 MR14 =0x16
1281 09:53:16.403550
1282 09:53:16.406944 CH=0, VrefRange= 0, VrefLevel = 22
1283 09:53:16.410456 TX Bit0 (976~1000) 25 988, Bit8 (963~989) 27 976,
1284 09:53:16.413837 TX Bit1 (975~998) 24 986, Bit9 (964~989) 26 976,
1285 09:53:16.420661 TX Bit2 (975~999) 25 987, Bit10 (968~992) 25 980,
1286 09:53:16.423520 TX Bit3 (968~993) 26 980, Bit11 (963~989) 27 976,
1287 09:53:16.427150 TX Bit4 (975~999) 25 987, Bit12 (964~989) 26 976,
1288 09:53:16.434093 TX Bit5 (970~994) 25 982, Bit13 (963~989) 27 976,
1289 09:53:16.437373 TX Bit6 (971~996) 26 983, Bit14 (964~989) 26 976,
1290 09:53:16.440592 TX Bit7 (972~997) 26 984, Bit15 (967~991) 25 979,
1291 09:53:16.441110
1292 09:53:16.443904 Write Rank0 MR14 =0x18
1293 09:53:16.453449
1294 09:53:16.456937 CH=0, VrefRange= 0, VrefLevel = 24
1295 09:53:16.460563 TX Bit0 (976~1000) 25 988, Bit8 (963~989) 27 976,
1296 09:53:16.463245 TX Bit1 (975~998) 24 986, Bit9 (964~989) 26 976,
1297 09:53:16.470181 TX Bit2 (975~999) 25 987, Bit10 (968~992) 25 980,
1298 09:53:16.473583 TX Bit3 (968~993) 26 980, Bit11 (963~989) 27 976,
1299 09:53:16.477007 TX Bit4 (975~999) 25 987, Bit12 (964~989) 26 976,
1300 09:53:16.483410 TX Bit5 (970~994) 25 982, Bit13 (963~989) 27 976,
1301 09:53:16.486916 TX Bit6 (971~996) 26 983, Bit14 (964~989) 26 976,
1302 09:53:16.490309 TX Bit7 (972~997) 26 984, Bit15 (967~991) 25 979,
1303 09:53:16.490822
1304 09:53:16.493604 Write Rank0 MR14 =0x1a
1305 09:53:16.503069
1306 09:53:16.506400 CH=0, VrefRange= 0, VrefLevel = 26
1307 09:53:16.510112 TX Bit0 (976~1000) 25 988, Bit8 (963~989) 27 976,
1308 09:53:16.513244 TX Bit1 (975~998) 24 986, Bit9 (964~989) 26 976,
1309 09:53:16.519779 TX Bit2 (975~999) 25 987, Bit10 (968~992) 25 980,
1310 09:53:16.523277 TX Bit3 (968~993) 26 980, Bit11 (963~989) 27 976,
1311 09:53:16.526488 TX Bit4 (975~999) 25 987, Bit12 (964~989) 26 976,
1312 09:53:16.533520 TX Bit5 (970~994) 25 982, Bit13 (963~989) 27 976,
1313 09:53:16.536947 TX Bit6 (971~996) 26 983, Bit14 (964~989) 26 976,
1314 09:53:16.540051 TX Bit7 (972~997) 26 984, Bit15 (967~991) 25 979,
1315 09:53:16.540572
1316 09:53:16.543409 Write Rank0 MR14 =0x1c
1317 09:53:16.552957
1318 09:53:16.556613 CH=0, VrefRange= 0, VrefLevel = 28
1319 09:53:16.559737 TX Bit0 (976~1000) 25 988, Bit8 (963~989) 27 976,
1320 09:53:16.563114 TX Bit1 (975~998) 24 986, Bit9 (964~989) 26 976,
1321 09:53:16.569729 TX Bit2 (975~999) 25 987, Bit10 (968~992) 25 980,
1322 09:53:16.573063 TX Bit3 (968~993) 26 980, Bit11 (963~989) 27 976,
1323 09:53:16.576342 TX Bit4 (975~999) 25 987, Bit12 (964~989) 26 976,
1324 09:53:16.583130 TX Bit5 (970~994) 25 982, Bit13 (963~989) 27 976,
1325 09:53:16.586718 TX Bit6 (971~996) 26 983, Bit14 (964~989) 26 976,
1326 09:53:16.589969 TX Bit7 (972~997) 26 984, Bit15 (967~991) 25 979,
1327 09:53:16.590526
1328 09:53:16.590863
1329 09:53:16.593301 TX Vref found, early break! 381< 390
1330 09:53:16.599877 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
1331 09:53:16.603505 u1DelayCellOfst[0]=10 cells (8 PI)
1332 09:53:16.606737 u1DelayCellOfst[1]=7 cells (6 PI)
1333 09:53:16.610233 u1DelayCellOfst[2]=9 cells (7 PI)
1334 09:53:16.610751 u1DelayCellOfst[3]=0 cells (0 PI)
1335 09:53:16.613347 u1DelayCellOfst[4]=9 cells (7 PI)
1336 09:53:16.616595 u1DelayCellOfst[5]=2 cells (2 PI)
1337 09:53:16.620319 u1DelayCellOfst[6]=3 cells (3 PI)
1338 09:53:16.623253 u1DelayCellOfst[7]=5 cells (4 PI)
1339 09:53:16.626761 Byte0, DQ PI dly=980, DQM PI dly= 984
1340 09:53:16.630473 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1341 09:53:16.630999
1342 09:53:16.637690 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1343 09:53:16.638126
1344 09:53:16.640268 u1DelayCellOfst[8]=0 cells (0 PI)
1345 09:53:16.643592 u1DelayCellOfst[9]=0 cells (0 PI)
1346 09:53:16.644113 u1DelayCellOfst[10]=5 cells (4 PI)
1347 09:53:16.647133 u1DelayCellOfst[11]=0 cells (0 PI)
1348 09:53:16.650370 u1DelayCellOfst[12]=0 cells (0 PI)
1349 09:53:16.653799 u1DelayCellOfst[13]=0 cells (0 PI)
1350 09:53:16.657244 u1DelayCellOfst[14]=0 cells (0 PI)
1351 09:53:16.660126 u1DelayCellOfst[15]=3 cells (3 PI)
1352 09:53:16.663733 Byte1, DQ PI dly=976, DQM PI dly= 978
1353 09:53:16.667015 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
1354 09:53:16.667538
1355 09:53:16.673878 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
1356 09:53:16.674443
1357 09:53:16.674787 Write Rank0 MR14 =0x16
1358 09:53:16.675097
1359 09:53:16.677068 Final TX Range 0 Vref 22
1360 09:53:16.677593
1361 09:53:16.683965 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1362 09:53:16.684482
1363 09:53:16.690314 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1364 09:53:16.697113 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1365 09:53:16.704103 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1366 09:53:16.707232 Write Rank0 MR3 =0xb0
1367 09:53:16.707686 DramC Write-DBI on
1368 09:53:16.708124 ==
1369 09:53:16.713977 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1370 09:53:16.717132 fsp= 1, odt_onoff= 1, Byte mode= 0
1371 09:53:16.717841 ==
1372 09:53:16.720712 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1373 09:53:16.721233
1374 09:53:16.723985 Begin, DQ Scan Range 698~762
1375 09:53:16.724506
1376 09:53:16.724964
1377 09:53:16.727453 TX Vref Scan disable
1378 09:53:16.730618 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1379 09:53:16.733891 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1380 09:53:16.737261 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1381 09:53:16.741084 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1382 09:53:16.744268 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1383 09:53:16.747685 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1384 09:53:16.751217 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1385 09:53:16.754451 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1386 09:53:16.757710 706 |2 6 2|[0] xxxxxxxx oooooooo [MSB]
1387 09:53:16.760934 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
1388 09:53:16.764166 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
1389 09:53:16.767914 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
1390 09:53:16.770897 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1391 09:53:16.774081 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1392 09:53:16.777685 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1393 09:53:16.781087 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1394 09:53:16.784104 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1395 09:53:16.793619 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB]
1396 09:53:16.797090 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1397 09:53:16.800418 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1398 09:53:16.803713 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1399 09:53:16.807100 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1400 09:53:16.810904 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1401 09:53:16.813906 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1402 09:53:16.817034 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1403 09:53:16.820265 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1404 09:53:16.823986 743 |2 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1405 09:53:16.827120 Byte0, DQ PI dly=728, DQM PI dly= 728
1406 09:53:16.830798 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
1407 09:53:16.831307
1408 09:53:16.837100 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
1409 09:53:16.837531
1410 09:53:16.840852 Byte1, DQ PI dly=719, DQM PI dly= 719
1411 09:53:16.844402 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 15)
1412 09:53:16.844920
1413 09:53:16.847508 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 15)
1414 09:53:16.848018
1415 09:53:16.854369 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1416 09:53:16.860723 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1417 09:53:16.867578 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1418 09:53:16.870840 Write Rank0 MR3 =0x30
1419 09:53:16.874205 DramC Write-DBI off
1420 09:53:16.874758
1421 09:53:16.875089 [DATLAT]
1422 09:53:16.877592 Freq=1600, CH0 RK0, use_rxtx_scan=0
1423 09:53:16.878106
1424 09:53:16.878480 DATLAT Default: 0xf
1425 09:53:16.880895 7, 0xFFFF, sum=0
1426 09:53:16.881474 8, 0xFFFF, sum=0
1427 09:53:16.884233 9, 0xFFFF, sum=0
1428 09:53:16.884756 10, 0xFFFF, sum=0
1429 09:53:16.887678 11, 0xFFFF, sum=0
1430 09:53:16.888198 12, 0xFFFF, sum=0
1431 09:53:16.891100 13, 0xFFFF, sum=0
1432 09:53:16.891538 14, 0x0, sum=1
1433 09:53:16.894062 15, 0x0, sum=2
1434 09:53:16.894526 16, 0x0, sum=3
1435 09:53:16.894865 17, 0x0, sum=4
1436 09:53:16.901291 pattern=2 first_step=14 total pass=5 best_step=16
1437 09:53:16.901813 ==
1438 09:53:16.904341 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1439 09:53:16.907742 fsp= 1, odt_onoff= 1, Byte mode= 0
1440 09:53:16.908269 ==
1441 09:53:16.914263 Start DQ dly to find pass range UseTestEngine =1
1442 09:53:16.917750 x-axis: bit #, y-axis: DQ dly (-127~63)
1443 09:53:16.918274 RX Vref Scan = 1
1444 09:53:17.040764
1445 09:53:17.041280 RX Vref found, early break!
1446 09:53:17.041618
1447 09:53:17.047411 Final RX Vref 13, apply to both rank0 and 1
1448 09:53:17.047933 ==
1449 09:53:17.050465 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1450 09:53:17.053952 fsp= 1, odt_onoff= 1, Byte mode= 0
1451 09:53:17.054512 ==
1452 09:53:17.054849 DQS Delay:
1453 09:53:17.057541 DQS0 = 0, DQS1 = 0
1454 09:53:17.058076 DQM Delay:
1455 09:53:17.060566 DQM0 = 19, DQM1 = 18
1456 09:53:17.060996 DQ Delay:
1457 09:53:17.064259 DQ0 =24, DQ1 =22, DQ2 =23, DQ3 =13
1458 09:53:17.067838 DQ4 =22, DQ5 =15, DQ6 =17, DQ7 =18
1459 09:53:17.070681 DQ8 =17, DQ9 =19, DQ10 =22, DQ11 =17
1460 09:53:17.074128 DQ12 =19, DQ13 =16, DQ14 =17, DQ15 =19
1461 09:53:17.074679
1462 09:53:17.075014
1463 09:53:17.075318
1464 09:53:17.077709 [DramC_TX_OE_Calibration] TA2
1465 09:53:17.080793 Original DQ_B0 (3 6) =30, OEN = 27
1466 09:53:17.084243 Original DQ_B1 (3 6) =30, OEN = 27
1467 09:53:17.084676 23, 0x0, End_B0=23 End_B1=23
1468 09:53:17.087656 24, 0x0, End_B0=24 End_B1=24
1469 09:53:17.091355 25, 0x0, End_B0=25 End_B1=25
1470 09:53:17.094368 26, 0x0, End_B0=26 End_B1=26
1471 09:53:17.097736 27, 0x0, End_B0=27 End_B1=27
1472 09:53:17.098307 28, 0x0, End_B0=28 End_B1=28
1473 09:53:17.101260 29, 0x0, End_B0=29 End_B1=29
1474 09:53:17.104450 30, 0x0, End_B0=30 End_B1=30
1475 09:53:17.107760 31, 0xFFFF, End_B0=30 End_B1=30
1476 09:53:17.111081 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1477 09:53:17.118165 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1478 09:53:17.118855
1479 09:53:17.119202
1480 09:53:17.121176 Write Rank0 MR23 =0x3f
1481 09:53:17.121605 [DQSOSC]
1482 09:53:17.128113 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0, (MSB)MR19= 0x3, tDQSOscB0 = 339 ps tDQSOscB1 = 0 ps
1483 09:53:17.134302 CH0_RK0: MR19=0x3, MR18=0xA0, DQSOSC=339, MR23=63, INC=21, DEC=32
1484 09:53:17.137835 Write Rank0 MR23 =0x3f
1485 09:53:17.138291 [DQSOSC]
1486 09:53:17.144824 [DQSOSCAuto] RK0, (LSB)MR18= 0x9c, (MSB)MR19= 0x3, tDQSOscB0 = 340 ps tDQSOscB1 = 0 ps
1487 09:53:17.148325 CH0 RK0: MR19=3, MR18=9C
1488 09:53:17.151482 [RankSwap] Rank num 2, (Multi 1), Rank 1
1489 09:53:17.151917 Write Rank0 MR2 =0xad
1490 09:53:17.154724 [Write Leveling]
1491 09:53:17.158079 delay byte0 byte1 byte2 byte3
1492 09:53:17.158582
1493 09:53:17.158926 10 0 0
1494 09:53:17.161555 11 0 0
1495 09:53:17.161991 12 0 0
1496 09:53:17.162358 13 0 0
1497 09:53:17.164843 14 0 0
1498 09:53:17.165277 15 0 0
1499 09:53:17.168299 16 0 0
1500 09:53:17.168992 17 0 0
1501 09:53:17.169367 18 0 0
1502 09:53:17.171532 19 0 0
1503 09:53:17.171967 20 0 0
1504 09:53:17.174932 21 0 0
1505 09:53:17.175370 22 0 0
1506 09:53:17.178392 23 0 0
1507 09:53:17.178835 24 0 0
1508 09:53:17.179175 25 0 0
1509 09:53:17.181619 26 0 0
1510 09:53:17.182054 27 0 0
1511 09:53:17.185056 28 0 0
1512 09:53:17.185501 29 0 ff
1513 09:53:17.185845 30 0 ff
1514 09:53:17.188652 31 0 ff
1515 09:53:17.189177 32 0 ff
1516 09:53:17.191809 33 0 ff
1517 09:53:17.192249 34 ff ff
1518 09:53:17.195292 35 ff ff
1519 09:53:17.195731 36 ff ff
1520 09:53:17.198331 37 ff ff
1521 09:53:17.198773 38 ff ff
1522 09:53:17.201703 39 ff ff
1523 09:53:17.202139 40 ff ff
1524 09:53:17.205649 pass bytecount = 0xff (0xff: all bytes pass)
1525 09:53:17.206172
1526 09:53:17.208585 DQS0 dly: 34
1527 09:53:17.209014 DQS1 dly: 29
1528 09:53:17.212157 Write Rank0 MR2 =0x2d
1529 09:53:17.215679 [RankSwap] Rank num 2, (Multi 1), Rank 0
1530 09:53:17.216195 Write Rank1 MR1 =0xd6
1531 09:53:17.216530 [Gating]
1532 09:53:17.218875 ==
1533 09:53:17.222191 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1534 09:53:17.225425 fsp= 1, odt_onoff= 1, Byte mode= 0
1535 09:53:17.225861 ==
1536 09:53:17.229013 3 1 0 |3534 1c1b |(11 11)(11 11) |(1 1)(0 0)| 0
1537 09:53:17.235595 3 1 4 |3534 3030 |(11 11)(11 11) |(1 1)(0 0)| 0
1538 09:53:17.239331 3 1 8 |3534 1918 |(11 11)(11 11) |(1 1)(1 1)| 0
1539 09:53:17.242242 3 1 12 |3534 303 |(11 11)(11 11) |(1 1)(1 1)| 0
1540 09:53:17.245534 3 1 16 |3534 3434 |(11 11)(11 11) |(0 0)(0 1)| 0
1541 09:53:17.252501 3 1 20 |3534 707 |(11 11)(11 11) |(0 0)(1 0)| 0
1542 09:53:17.255643 3 1 24 |3534 2524 |(11 11)(11 11) |(0 0)(0 1)| 0
1543 09:53:17.259009 3 1 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1544 09:53:17.265953 3 2 0 |3534 1110 |(11 11)(11 11) |(0 0)(0 1)| 0
1545 09:53:17.269028 3 2 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1546 09:53:17.272851 3 2 8 |b0a 3333 |(11 11)(0 11) |(1 1)(1 1)| 0
1547 09:53:17.275897 3 2 12 |3d3d 807 |(11 11)(11 11) |(1 1)(1 1)| 0
1548 09:53:17.282890 3 2 16 |3d3d 3d3d |(11 11)(0 0) |(1 1)(1 1)| 0
1549 09:53:17.285835 3 2 20 |3d3d d0c |(11 11)(11 11) |(1 1)(1 1)| 0
1550 09:53:17.289315 [Byte 1] Lead/lag Transition tap number (1)
1551 09:53:17.292681 3 2 24 |3d3d 404 |(11 11)(11 11) |(1 1)(0 0)| 0
1552 09:53:17.299539 3 2 28 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
1553 09:53:17.302599 3 3 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1554 09:53:17.306305 3 3 4 |3d3d 3c3c |(11 11)(0 0) |(1 1)(1 1)| 0
1555 09:53:17.312928 3 3 8 |3d3d 302f |(11 11)(11 11) |(1 1)(1 1)| 0
1556 09:53:17.316424 3 3 12 |3d3d 605 |(11 11)(11 11) |(1 1)(1 1)| 0
1557 09:53:17.319105 3 3 16 |3d3d 0 |(11 11)(11 11) |(1 1)(1 1)| 0
1558 09:53:17.322914 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1559 09:53:17.329672 [Byte 0] Lead/lag Transition tap number (1)
1560 09:53:17.333206 [Byte 1] Lead/lag falling Transition (3, 3, 20)
1561 09:53:17.336194 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1562 09:53:17.339956 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1563 09:53:17.346506 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1564 09:53:17.349925 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1565 09:53:17.353375 3 4 8 |201 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1566 09:53:17.359649 3 4 12 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
1567 09:53:17.362836 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1568 09:53:17.366341 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1569 09:53:17.373310 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1570 09:53:17.376609 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1571 09:53:17.379625 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1572 09:53:17.383168 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1573 09:53:17.390062 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1574 09:53:17.393254 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1575 09:53:17.396514 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1576 09:53:17.403154 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1577 09:53:17.406450 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1578 09:53:17.409828 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1579 09:53:17.413615 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1580 09:53:17.420102 [Byte 0] Lead/lag falling Transition (3, 6, 0)
1581 09:53:17.423632 [Byte 1] Lead/lag falling Transition (3, 6, 0)
1582 09:53:17.426661 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1583 09:53:17.430624 [Byte 0] Lead/lag Transition tap number (2)
1584 09:53:17.436750 [Byte 1] Lead/lag Transition tap number (2)
1585 09:53:17.439878 3 6 8 |403 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
1586 09:53:17.443621 3 6 12 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
1587 09:53:17.446824 [Byte 0]First pass (3, 6, 12)
1588 09:53:17.450273 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1589 09:53:17.453619 [Byte 1]First pass (3, 6, 16)
1590 09:53:17.457015 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1591 09:53:17.460555 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1592 09:53:17.463495 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1593 09:53:17.470108 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1594 09:53:17.473560 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1595 09:53:17.476775 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1596 09:53:17.480373 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1597 09:53:17.483946 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1598 09:53:17.490335 All bytes gating window > 1UI, Early break!
1599 09:53:17.490856
1600 09:53:17.493487 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 4)
1601 09:53:17.493922
1602 09:53:17.497052 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 4)
1603 09:53:17.497572
1604 09:53:17.497907
1605 09:53:17.498261
1606 09:53:17.500390 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1607 09:53:17.500912
1608 09:53:17.504005 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1609 09:53:17.504528
1610 09:53:17.504865
1611 09:53:17.506807 Write Rank1 MR1 =0x56
1612 09:53:17.507241
1613 09:53:17.510246 best RODT dly(2T, 0.5T) = (2, 3)
1614 09:53:17.510685
1615 09:53:17.513742 best RODT dly(2T, 0.5T) = (2, 3)
1616 09:53:17.514317 ==
1617 09:53:17.516963 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1618 09:53:17.520060 fsp= 1, odt_onoff= 1, Byte mode= 0
1619 09:53:17.520502 ==
1620 09:53:17.526943 Start DQ dly to find pass range UseTestEngine =0
1621 09:53:17.530437 x-axis: bit #, y-axis: DQ dly (-127~63)
1622 09:53:17.530959 RX Vref Scan = 0
1623 09:53:17.533600 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1624 09:53:17.536848 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1625 09:53:17.540673 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1626 09:53:17.543706 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1627 09:53:17.547341 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1628 09:53:17.550653 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1629 09:53:17.551178 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1630 09:53:17.553866 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1631 09:53:17.557245 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1632 09:53:17.560618 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1633 09:53:17.563999 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1634 09:53:17.567364 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1635 09:53:17.570782 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1636 09:53:17.574203 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1637 09:53:17.574886 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1638 09:53:17.577378 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1639 09:53:17.580686 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1640 09:53:17.584428 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1641 09:53:17.587231 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1642 09:53:17.590514 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1643 09:53:17.594509 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1644 09:53:17.595020 -5, [0] xxxoxxxx xxxxxxxx [MSB]
1645 09:53:17.597584 -4, [0] xxxoxxxx xxxxxxxx [MSB]
1646 09:53:17.601266 -3, [0] xxxoxxxx xxxxxxxx [MSB]
1647 09:53:17.604392 -2, [0] xxxoxoxx xxxxxxxx [MSB]
1648 09:53:17.607426 -1, [0] xxxoxooo oxxxxxxx [MSB]
1649 09:53:17.610882 0, [0] xxxoxooo oxxxxxxx [MSB]
1650 09:53:17.611317 1, [0] xxxoxooo ooxoooox [MSB]
1651 09:53:17.614203 2, [0] xxxoxooo ooxooooo [MSB]
1652 09:53:17.617491 3, [0] xxxoxooo ooxooooo [MSB]
1653 09:53:17.620960 4, [0] xoxooooo oooooooo [MSB]
1654 09:53:17.624747 5, [0] xooooooo oooooooo [MSB]
1655 09:53:17.627831 32, [0] oooxoooo oooooooo [MSB]
1656 09:53:17.628321 33, [0] oooxoooo oooooooo [MSB]
1657 09:53:17.631049 34, [0] oooxoxoo oooooooo [MSB]
1658 09:53:17.634591 35, [0] oooxoxoo oooxooxo [MSB]
1659 09:53:17.638154 36, [0] oooxoxxx xooxooxo [MSB]
1660 09:53:17.641251 37, [0] oooxoxxx xooxoxxo [MSB]
1661 09:53:17.644682 38, [0] oooxoxxx xxoxoxxo [MSB]
1662 09:53:17.645201 39, [0] oooxoxxx xxoxxxxo [MSB]
1663 09:53:17.647693 40, [0] oxoxxxxx xxoxxxxx [MSB]
1664 09:53:17.651303 41, [0] oxxxxxxx xxoxxxxx [MSB]
1665 09:53:17.654615 42, [0] xxxxxxxx xxoxxxxx [MSB]
1666 09:53:17.658144 43, [0] xxxxxxxx xxxxxxxx [MSB]
1667 09:53:17.661332 iDelay=43, Bit 0, Center 23 (6 ~ 41) 36
1668 09:53:17.664624 iDelay=43, Bit 1, Center 21 (4 ~ 39) 36
1669 09:53:17.668220 iDelay=43, Bit 2, Center 22 (5 ~ 40) 36
1670 09:53:17.671189 iDelay=43, Bit 3, Center 13 (-5 ~ 31) 37
1671 09:53:17.674671 iDelay=43, Bit 4, Center 21 (4 ~ 39) 36
1672 09:53:17.677905 iDelay=43, Bit 5, Center 15 (-2 ~ 33) 36
1673 09:53:17.681202 iDelay=43, Bit 6, Center 17 (-1 ~ 35) 37
1674 09:53:17.684358 iDelay=43, Bit 7, Center 17 (-1 ~ 35) 37
1675 09:53:17.691428 iDelay=43, Bit 8, Center 17 (-1 ~ 35) 37
1676 09:53:17.694656 iDelay=43, Bit 9, Center 19 (1 ~ 37) 37
1677 09:53:17.697901 iDelay=43, Bit 10, Center 23 (4 ~ 42) 39
1678 09:53:17.701887 iDelay=43, Bit 11, Center 17 (1 ~ 34) 34
1679 09:53:17.705084 iDelay=43, Bit 12, Center 19 (1 ~ 38) 38
1680 09:53:17.708121 iDelay=43, Bit 13, Center 18 (1 ~ 36) 36
1681 09:53:17.711539 iDelay=43, Bit 14, Center 17 (1 ~ 34) 34
1682 09:53:17.714812 iDelay=43, Bit 15, Center 20 (2 ~ 39) 38
1683 09:53:17.715259 ==
1684 09:53:17.721847 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1685 09:53:17.722390 fsp= 1, odt_onoff= 1, Byte mode= 0
1686 09:53:17.725323 ==
1687 09:53:17.725830 DQS Delay:
1688 09:53:17.726305 DQS0 = 0, DQS1 = 0
1689 09:53:17.728634 DQM Delay:
1690 09:53:17.729232 DQM0 = 18, DQM1 = 18
1691 09:53:17.731791 DQ Delay:
1692 09:53:17.734877 DQ0 =23, DQ1 =21, DQ2 =22, DQ3 =13
1693 09:53:17.735309 DQ4 =21, DQ5 =15, DQ6 =17, DQ7 =17
1694 09:53:17.738347 DQ8 =17, DQ9 =19, DQ10 =23, DQ11 =17
1695 09:53:17.741575 DQ12 =19, DQ13 =18, DQ14 =17, DQ15 =20
1696 09:53:17.742003
1697 09:53:17.745384
1698 09:53:17.745900 DramC Write-DBI off
1699 09:53:17.746318 ==
1700 09:53:17.751847 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1701 09:53:17.755171 fsp= 1, odt_onoff= 1, Byte mode= 0
1702 09:53:17.755680 ==
1703 09:53:17.758868 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1704 09:53:17.759376
1705 09:53:17.761917 Begin, DQ Scan Range 925~1181
1706 09:53:17.762502
1707 09:53:17.762843
1708 09:53:17.763148 TX Vref Scan disable
1709 09:53:17.768839 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1710 09:53:17.772304 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1711 09:53:17.775501 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1712 09:53:17.778981 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1713 09:53:17.782080 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1714 09:53:17.785546 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1715 09:53:17.788644 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1716 09:53:17.792231 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1717 09:53:17.795675 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1718 09:53:17.799018 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1719 09:53:17.802367 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1720 09:53:17.805770 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1721 09:53:17.808968 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1722 09:53:17.812629 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1723 09:53:17.815724 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1724 09:53:17.818924 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1725 09:53:17.822359 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1726 09:53:17.825503 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1727 09:53:17.829079 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1728 09:53:17.835640 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1729 09:53:17.838939 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1730 09:53:17.842711 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1731 09:53:17.845942 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1732 09:53:17.849331 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1733 09:53:17.852709 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1734 09:53:17.855969 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1735 09:53:17.859539 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1736 09:53:17.862481 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1737 09:53:17.866252 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1738 09:53:17.869416 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1739 09:53:17.873032 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1740 09:53:17.875788 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1741 09:53:17.879454 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1742 09:53:17.882662 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1743 09:53:17.886202 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1744 09:53:17.889147 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1745 09:53:17.892812 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1746 09:53:17.896121 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1747 09:53:17.899719 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1748 09:53:17.903117 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1749 09:53:17.909483 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1750 09:53:17.913050 966 |3 6 6|[0] xxxxxxxx oxxoxxxx [MSB]
1751 09:53:17.916238 967 |3 6 7|[0] xxxxxxxx ooxoooox [MSB]
1752 09:53:17.919317 968 |3 6 8|[0] xxxxxxxx ooxooooo [MSB]
1753 09:53:17.922773 969 |3 6 9|[0] xxxxxxxx ooxooooo [MSB]
1754 09:53:17.926656 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB]
1755 09:53:17.929950 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
1756 09:53:17.933147 972 |3 6 12|[0] xxxoxoox oooooooo [MSB]
1757 09:53:17.936433 973 |3 6 13|[0] xxxoxoox oooooooo [MSB]
1758 09:53:17.940075 974 |3 6 14|[0] xxxoxoox oooooooo [MSB]
1759 09:53:17.943151 975 |3 6 15|[0] xxxoxoox oooooooo [MSB]
1760 09:53:17.946615 976 |3 6 16|[0] xoxooooo oooooooo [MSB]
1761 09:53:17.953374 989 |3 6 29|[0] oooooooo oxxxxxxx [MSB]
1762 09:53:17.956809 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1763 09:53:17.959873 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1764 09:53:17.963376 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1765 09:53:17.966694 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1766 09:53:17.970141 994 |3 6 34|[0] oooxoxoo xxxxxxxx [MSB]
1767 09:53:17.973530 995 |3 6 35|[0] oooxoxxo xxxxxxxx [MSB]
1768 09:53:17.976626 996 |3 6 36|[0] xoxxxxxx xxxxxxxx [MSB]
1769 09:53:17.979993 997 |3 6 37|[0] xxxxxxxx xxxxxxxx [MSB]
1770 09:53:17.983345 Byte0, DQ PI dly=984, DQM PI dly= 984
1771 09:53:17.986796 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
1772 09:53:17.987229
1773 09:53:17.993703 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
1774 09:53:17.994463
1775 09:53:17.997137 Byte1, DQ PI dly=978, DQM PI dly= 978
1776 09:53:18.000210 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
1777 09:53:18.000644
1778 09:53:18.003574 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
1779 09:53:18.004009
1780 09:53:18.004338 ==
1781 09:53:18.010512 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1782 09:53:18.013979 fsp= 1, odt_onoff= 1, Byte mode= 0
1783 09:53:18.014542 ==
1784 09:53:18.017263 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1785 09:53:18.017783
1786 09:53:18.020648 Begin, DQ Scan Range 954~1018
1787 09:53:18.023621 Write Rank1 MR14 =0x0
1788 09:53:18.031412
1789 09:53:18.031923 CH=0, VrefRange= 0, VrefLevel = 0
1790 09:53:18.037870 TX Bit0 (978~998) 21 988, Bit8 (967~986) 20 976,
1791 09:53:18.041413 TX Bit1 (978~996) 19 987, Bit9 (968~987) 20 977,
1792 09:53:18.048164 TX Bit2 (978~996) 19 987, Bit10 (973~990) 18 981,
1793 09:53:18.051204 TX Bit3 (974~990) 17 982, Bit11 (968~986) 19 977,
1794 09:53:18.054623 TX Bit4 (977~997) 21 987, Bit12 (969~989) 21 979,
1795 09:53:18.061297 TX Bit5 (975~990) 16 982, Bit13 (969~985) 17 977,
1796 09:53:18.064731 TX Bit6 (975~991) 17 983, Bit14 (969~987) 19 978,
1797 09:53:18.068078 TX Bit7 (977~993) 17 985, Bit15 (971~990) 20 980,
1798 09:53:18.068595
1799 09:53:18.071423 Write Rank1 MR14 =0x2
1800 09:53:18.080173
1801 09:53:18.080691 CH=0, VrefRange= 0, VrefLevel = 2
1802 09:53:18.086881 TX Bit0 (978~998) 21 988, Bit8 (967~987) 21 977,
1803 09:53:18.090311 TX Bit1 (977~996) 20 986, Bit9 (968~988) 21 978,
1804 09:53:18.096966 TX Bit2 (978~996) 19 987, Bit10 (973~990) 18 981,
1805 09:53:18.100435 TX Bit3 (973~990) 18 981, Bit11 (968~987) 20 977,
1806 09:53:18.103510 TX Bit4 (977~997) 21 987, Bit12 (968~988) 21 978,
1807 09:53:18.110398 TX Bit5 (975~990) 16 982, Bit13 (969~986) 18 977,
1808 09:53:18.113809 TX Bit6 (975~991) 17 983, Bit14 (969~988) 20 978,
1809 09:53:18.117127 TX Bit7 (977~993) 17 985, Bit15 (970~990) 21 980,
1810 09:53:18.117642
1811 09:53:18.120190 Write Rank1 MR14 =0x4
1812 09:53:18.129060
1813 09:53:18.129573 CH=0, VrefRange= 0, VrefLevel = 4
1814 09:53:18.135882 TX Bit0 (977~998) 22 987, Bit8 (967~987) 21 977,
1815 09:53:18.139214 TX Bit1 (977~997) 21 987, Bit9 (968~989) 22 978,
1816 09:53:18.146164 TX Bit2 (977~997) 21 987, Bit10 (972~991) 20 981,
1817 09:53:18.149020 TX Bit3 (973~990) 18 981, Bit11 (968~988) 21 978,
1818 09:53:18.152782 TX Bit4 (977~998) 22 987, Bit12 (968~989) 22 978,
1819 09:53:18.159243 TX Bit5 (975~991) 17 983, Bit13 (968~986) 19 977,
1820 09:53:18.162958 TX Bit6 (975~992) 18 983, Bit14 (968~989) 22 978,
1821 09:53:18.166304 TX Bit7 (977~994) 18 985, Bit15 (970~990) 21 980,
1822 09:53:18.166827
1823 09:53:18.169538 Write Rank1 MR14 =0x6
1824 09:53:18.177982
1825 09:53:18.178530 CH=0, VrefRange= 0, VrefLevel = 6
1826 09:53:18.184733 TX Bit0 (977~998) 22 987, Bit8 (967~988) 22 977,
1827 09:53:18.188256 TX Bit1 (977~997) 21 987, Bit9 (968~989) 22 978,
1828 09:53:18.191375 TX Bit2 (977~997) 21 987, Bit10 (972~991) 20 981,
1829 09:53:18.198296 TX Bit3 (972~990) 19 981, Bit11 (968~988) 21 978,
1830 09:53:18.201635 TX Bit4 (977~998) 22 987, Bit12 (968~989) 22 978,
1831 09:53:18.208564 TX Bit5 (974~991) 18 982, Bit13 (968~987) 20 977,
1832 09:53:18.211821 TX Bit6 (974~992) 19 983, Bit14 (968~989) 22 978,
1833 09:53:18.214735 TX Bit7 (977~994) 18 985, Bit15 (969~990) 22 979,
1834 09:53:18.215173
1835 09:53:18.218386 Write Rank1 MR14 =0x8
1836 09:53:18.227024
1837 09:53:18.227629 CH=0, VrefRange= 0, VrefLevel = 8
1838 09:53:18.233588 TX Bit0 (977~998) 22 987, Bit8 (966~988) 23 977,
1839 09:53:18.237090 TX Bit1 (976~997) 22 986, Bit9 (968~989) 22 978,
1840 09:53:18.243684 TX Bit2 (977~997) 21 987, Bit10 (972~991) 20 981,
1841 09:53:18.247155 TX Bit3 (972~991) 20 981, Bit11 (967~989) 23 978,
1842 09:53:18.250714 TX Bit4 (976~998) 23 987, Bit12 (968~989) 22 978,
1843 09:53:18.257343 TX Bit5 (974~991) 18 982, Bit13 (968~988) 21 978,
1844 09:53:18.260531 TX Bit6 (974~993) 20 983, Bit14 (968~989) 22 978,
1845 09:53:18.263600 TX Bit7 (976~995) 20 985, Bit15 (969~991) 23 980,
1846 09:53:18.264120
1847 09:53:18.267379 Write Rank1 MR14 =0xa
1848 09:53:18.276089
1849 09:53:18.279615 CH=0, VrefRange= 0, VrefLevel = 10
1850 09:53:18.282922 TX Bit0 (977~999) 23 988, Bit8 (966~989) 24 977,
1851 09:53:18.286334 TX Bit1 (977~998) 22 987, Bit9 (968~989) 22 978,
1852 09:53:18.292763 TX Bit2 (977~998) 22 987, Bit10 (972~992) 21 982,
1853 09:53:18.296368 TX Bit3 (971~991) 21 981, Bit11 (967~989) 23 978,
1854 09:53:18.299538 TX Bit4 (976~998) 23 987, Bit12 (968~990) 23 979,
1855 09:53:18.306428 TX Bit5 (973~992) 20 982, Bit13 (968~988) 21 978,
1856 09:53:18.309421 TX Bit6 (974~993) 20 983, Bit14 (968~989) 22 978,
1857 09:53:18.313050 TX Bit7 (976~996) 21 986, Bit15 (969~991) 23 980,
1858 09:53:18.313568
1859 09:53:18.316397 Write Rank1 MR14 =0xc
1860 09:53:18.325403
1861 09:53:18.328439 CH=0, VrefRange= 0, VrefLevel = 12
1862 09:53:18.331809 TX Bit0 (977~999) 23 988, Bit8 (966~989) 24 977,
1863 09:53:18.335032 TX Bit1 (977~998) 22 987, Bit9 (967~990) 24 978,
1864 09:53:18.341939 TX Bit2 (977~998) 22 987, Bit10 (971~992) 22 981,
1865 09:53:18.345698 TX Bit3 (971~992) 22 981, Bit11 (967~989) 23 978,
1866 09:53:18.348621 TX Bit4 (976~998) 23 987, Bit12 (968~990) 23 979,
1867 09:53:18.355281 TX Bit5 (973~992) 20 982, Bit13 (968~989) 22 978,
1868 09:53:18.358625 TX Bit6 (973~993) 21 983, Bit14 (968~990) 23 979,
1869 09:53:18.362156 TX Bit7 (976~997) 22 986, Bit15 (969~991) 23 980,
1870 09:53:18.362630
1871 09:53:18.365052 Write Rank1 MR14 =0xe
1872 09:53:18.374622
1873 09:53:18.377930 CH=0, VrefRange= 0, VrefLevel = 14
1874 09:53:18.381329 TX Bit0 (977~1000) 24 988, Bit8 (966~989) 24 977,
1875 09:53:18.385238 TX Bit1 (976~998) 23 987, Bit9 (967~990) 24 978,
1876 09:53:18.391245 TX Bit2 (976~998) 23 987, Bit10 (971~992) 22 981,
1877 09:53:18.394564 TX Bit3 (971~992) 22 981, Bit11 (967~990) 24 978,
1878 09:53:18.398037 TX Bit4 (976~999) 24 987, Bit12 (967~990) 24 978,
1879 09:53:18.404530 TX Bit5 (972~992) 21 982, Bit13 (967~989) 23 978,
1880 09:53:18.407953 TX Bit6 (973~994) 22 983, Bit14 (967~990) 24 978,
1881 09:53:18.411416 TX Bit7 (976~997) 22 986, Bit15 (969~992) 24 980,
1882 09:53:18.411856
1883 09:53:18.414666 Write Rank1 MR14 =0x10
1884 09:53:18.424324
1885 09:53:18.424759 CH=0, VrefRange= 0, VrefLevel = 16
1886 09:53:18.430720 TX Bit0 (977~1000) 24 988, Bit8 (965~990) 26 977,
1887 09:53:18.433925 TX Bit1 (977~998) 22 987, Bit9 (967~990) 24 978,
1888 09:53:18.441097 TX Bit2 (976~999) 24 987, Bit10 (970~993) 24 981,
1889 09:53:18.444452 TX Bit3 (970~993) 24 981, Bit11 (966~990) 25 978,
1890 09:53:18.447378 TX Bit4 (976~999) 24 987, Bit12 (967~990) 24 978,
1891 09:53:18.454028 TX Bit5 (971~993) 23 982, Bit13 (967~989) 23 978,
1892 09:53:18.457346 TX Bit6 (972~995) 24 983, Bit14 (967~990) 24 978,
1893 09:53:18.461091 TX Bit7 (975~997) 23 986, Bit15 (968~992) 25 980,
1894 09:53:18.461616
1895 09:53:18.464249 Write Rank1 MR14 =0x12
1896 09:53:18.473919
1897 09:53:18.477057 CH=0, VrefRange= 0, VrefLevel = 18
1898 09:53:18.480378 TX Bit0 (977~1000) 24 988, Bit8 (965~990) 26 977,
1899 09:53:18.483798 TX Bit1 (976~998) 23 987, Bit9 (967~990) 24 978,
1900 09:53:18.490550 TX Bit2 (976~999) 24 987, Bit10 (971~994) 24 982,
1901 09:53:18.493837 TX Bit3 (970~993) 24 981, Bit11 (966~990) 25 978,
1902 09:53:18.496711 TX Bit4 (976~999) 24 987, Bit12 (967~991) 25 979,
1903 09:53:18.504000 TX Bit5 (971~993) 23 982, Bit13 (967~989) 23 978,
1904 09:53:18.507044 TX Bit6 (971~995) 25 983, Bit14 (967~990) 24 978,
1905 09:53:18.510452 TX Bit7 (975~998) 24 986, Bit15 (968~993) 26 980,
1906 09:53:18.510889
1907 09:53:18.513836 Write Rank1 MR14 =0x14
1908 09:53:18.522940
1909 09:53:18.526406 CH=0, VrefRange= 0, VrefLevel = 20
1910 09:53:18.529835 TX Bit0 (976~1000) 25 988, Bit8 (965~990) 26 977,
1911 09:53:18.533483 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1912 09:53:18.539664 TX Bit2 (976~999) 24 987, Bit10 (970~994) 25 982,
1913 09:53:18.543196 TX Bit3 (969~994) 26 981, Bit11 (966~990) 25 978,
1914 09:53:18.546868 TX Bit4 (975~1000) 26 987, Bit12 (967~990) 24 978,
1915 09:53:18.553368 TX Bit5 (971~994) 24 982, Bit13 (967~989) 23 978,
1916 09:53:18.556892 TX Bit6 (972~996) 25 984, Bit14 (967~990) 24 978,
1917 09:53:18.560285 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
1918 09:53:18.560835
1919 09:53:18.563526 Write Rank1 MR14 =0x16
1920 09:53:18.572825
1921 09:53:18.576162 CH=0, VrefRange= 0, VrefLevel = 22
1922 09:53:18.579436 TX Bit0 (976~1001) 26 988, Bit8 (965~990) 26 977,
1923 09:53:18.583138 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1924 09:53:18.589645 TX Bit2 (976~1000) 25 988, Bit10 (969~995) 27 982,
1925 09:53:18.592788 TX Bit3 (969~993) 25 981, Bit11 (966~990) 25 978,
1926 09:53:18.596076 TX Bit4 (975~1000) 26 987, Bit12 (967~991) 25 979,
1927 09:53:18.603035 TX Bit5 (971~994) 24 982, Bit13 (966~990) 25 978,
1928 09:53:18.606270 TX Bit6 (971~996) 26 983, Bit14 (966~990) 25 978,
1929 09:53:18.609758 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
1930 09:53:18.610387
1931 09:53:18.612899 Write Rank1 MR14 =0x18
1932 09:53:18.622542
1933 09:53:18.625714 CH=0, VrefRange= 0, VrefLevel = 24
1934 09:53:18.629106 TX Bit0 (976~1001) 26 988, Bit8 (965~990) 26 977,
1935 09:53:18.632684 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1936 09:53:18.639629 TX Bit2 (976~1000) 25 988, Bit10 (969~995) 27 982,
1937 09:53:18.643122 TX Bit3 (969~993) 25 981, Bit11 (966~990) 25 978,
1938 09:53:18.646177 TX Bit4 (975~1000) 26 987, Bit12 (967~991) 25 979,
1939 09:53:18.652825 TX Bit5 (971~994) 24 982, Bit13 (966~990) 25 978,
1940 09:53:18.656320 TX Bit6 (971~996) 26 983, Bit14 (966~990) 25 978,
1941 09:53:18.659635 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
1942 09:53:18.660159
1943 09:53:18.662800 Write Rank1 MR14 =0x1a
1944 09:53:18.672395
1945 09:53:18.675846 CH=0, VrefRange= 0, VrefLevel = 26
1946 09:53:18.679207 TX Bit0 (976~1001) 26 988, Bit8 (965~990) 26 977,
1947 09:53:18.682399 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1948 09:53:18.689114 TX Bit2 (976~1000) 25 988, Bit10 (969~995) 27 982,
1949 09:53:18.692350 TX Bit3 (969~993) 25 981, Bit11 (966~990) 25 978,
1950 09:53:18.695972 TX Bit4 (975~1000) 26 987, Bit12 (967~991) 25 979,
1951 09:53:18.703053 TX Bit5 (971~994) 24 982, Bit13 (966~990) 25 978,
1952 09:53:18.705926 TX Bit6 (971~996) 26 983, Bit14 (966~990) 25 978,
1953 09:53:18.709472 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
1954 09:53:18.709999
1955 09:53:18.712597 Write Rank1 MR14 =0x1c
1956 09:53:18.722064
1957 09:53:18.725402 CH=0, VrefRange= 0, VrefLevel = 28
1958 09:53:18.728815 TX Bit0 (976~1001) 26 988, Bit8 (965~990) 26 977,
1959 09:53:18.732150 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1960 09:53:18.738747 TX Bit2 (976~1000) 25 988, Bit10 (969~995) 27 982,
1961 09:53:18.742187 TX Bit3 (969~993) 25 981, Bit11 (966~990) 25 978,
1962 09:53:18.745808 TX Bit4 (975~1000) 26 987, Bit12 (967~991) 25 979,
1963 09:53:18.752160 TX Bit5 (971~994) 24 982, Bit13 (966~990) 25 978,
1964 09:53:18.755824 TX Bit6 (971~996) 26 983, Bit14 (966~990) 25 978,
1965 09:53:18.758992 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
1966 09:53:18.759513
1967 09:53:18.762299 Write Rank1 MR14 =0x1e
1968 09:53:18.771723
1969 09:53:18.775057 CH=0, VrefRange= 0, VrefLevel = 30
1970 09:53:18.778428 TX Bit0 (976~1001) 26 988, Bit8 (965~990) 26 977,
1971 09:53:18.781885 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1972 09:53:18.788576 TX Bit2 (976~1000) 25 988, Bit10 (969~995) 27 982,
1973 09:53:18.791789 TX Bit3 (969~993) 25 981, Bit11 (966~990) 25 978,
1974 09:53:18.795024 TX Bit4 (975~1000) 26 987, Bit12 (967~991) 25 979,
1975 09:53:18.801758 TX Bit5 (971~994) 24 982, Bit13 (966~990) 25 978,
1976 09:53:18.805354 TX Bit6 (971~996) 26 983, Bit14 (966~990) 25 978,
1977 09:53:18.808948 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
1978 09:53:18.809485
1979 09:53:18.809826
1980 09:53:18.812009 TX Vref found, early break! 378< 381
1981 09:53:18.818762 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
1982 09:53:18.822058 u1DelayCellOfst[0]=9 cells (7 PI)
1983 09:53:18.825443 u1DelayCellOfst[1]=7 cells (6 PI)
1984 09:53:18.829199 u1DelayCellOfst[2]=9 cells (7 PI)
1985 09:53:18.832074 u1DelayCellOfst[3]=0 cells (0 PI)
1986 09:53:18.832591 u1DelayCellOfst[4]=7 cells (6 PI)
1987 09:53:18.835417 u1DelayCellOfst[5]=1 cells (1 PI)
1988 09:53:18.838612 u1DelayCellOfst[6]=2 cells (2 PI)
1989 09:53:18.842366 u1DelayCellOfst[7]=6 cells (5 PI)
1990 09:53:18.845697 Byte0, DQ PI dly=981, DQM PI dly= 984
1991 09:53:18.848975 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1992 09:53:18.849494
1993 09:53:18.855851 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1994 09:53:18.856378
1995 09:53:18.859206 u1DelayCellOfst[8]=0 cells (0 PI)
1996 09:53:18.862106 u1DelayCellOfst[9]=1 cells (1 PI)
1997 09:53:18.862724 u1DelayCellOfst[10]=6 cells (5 PI)
1998 09:53:18.865501 u1DelayCellOfst[11]=1 cells (1 PI)
1999 09:53:18.869057 u1DelayCellOfst[12]=2 cells (2 PI)
2000 09:53:18.872415 u1DelayCellOfst[13]=1 cells (1 PI)
2001 09:53:18.875284 u1DelayCellOfst[14]=1 cells (1 PI)
2002 09:53:18.879074 u1DelayCellOfst[15]=3 cells (3 PI)
2003 09:53:18.882333 Byte1, DQ PI dly=977, DQM PI dly= 979
2004 09:53:18.885507 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
2005 09:53:18.888975
2006 09:53:18.892495 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
2007 09:53:18.893033
2008 09:53:18.893373 Write Rank1 MR14 =0x16
2009 09:53:18.893682
2010 09:53:18.895747 Final TX Range 0 Vref 22
2011 09:53:18.896190
2012 09:53:18.902427 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2013 09:53:18.903003
2014 09:53:18.908938 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2015 09:53:18.915588 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2016 09:53:18.922157 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2017 09:53:18.925551 Write Rank1 MR3 =0xb0
2018 09:53:18.925986 DramC Write-DBI on
2019 09:53:18.929162 ==
2020 09:53:18.932070 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2021 09:53:18.935804 fsp= 1, odt_onoff= 1, Byte mode= 0
2022 09:53:18.936318 ==
2023 09:53:18.938863 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2024 09:53:18.939299
2025 09:53:18.942186 Begin, DQ Scan Range 699~763
2026 09:53:18.942668
2027 09:53:18.943002
2028 09:53:18.945816 TX Vref Scan disable
2029 09:53:18.949254 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2030 09:53:18.952731 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2031 09:53:18.955831 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2032 09:53:18.959292 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2033 09:53:18.962622 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2034 09:53:18.966022 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2035 09:53:18.969383 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2036 09:53:18.972697 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2037 09:53:18.975955 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
2038 09:53:18.979332 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
2039 09:53:18.982663 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
2040 09:53:18.986140 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
2041 09:53:18.989560 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2042 09:53:18.992643 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2043 09:53:18.995932 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2044 09:53:18.999478 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2045 09:53:19.002795 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2046 09:53:19.012215 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
2047 09:53:19.015762 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2048 09:53:19.018926 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2049 09:53:19.022658 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2050 09:53:19.026285 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2051 09:53:19.029418 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2052 09:53:19.032444 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2053 09:53:19.036123 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2054 09:53:19.039403 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2055 09:53:19.042455 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
2056 09:53:19.046080 Byte0, DQ PI dly=729, DQM PI dly= 729
2057 09:53:19.049441 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 25)
2058 09:53:19.049957
2059 09:53:19.056283 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 25)
2060 09:53:19.056798
2061 09:53:19.059544 Byte1, DQ PI dly=720, DQM PI dly= 720
2062 09:53:19.062855 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 16)
2063 09:53:19.063372
2064 09:53:19.066295 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 16)
2065 09:53:19.066827
2066 09:53:19.072877 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2067 09:53:19.079838 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2068 09:53:19.086234 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2069 09:53:19.089884 Write Rank1 MR3 =0x30
2070 09:53:19.093132 DramC Write-DBI off
2071 09:53:19.093642
2072 09:53:19.093977 [DATLAT]
2073 09:53:19.096311 Freq=1600, CH0 RK1, use_rxtx_scan=0
2074 09:53:19.096746
2075 09:53:19.097081 DATLAT Default: 0x10
2076 09:53:19.099995 7, 0xFFFF, sum=0
2077 09:53:19.100513 8, 0xFFFF, sum=0
2078 09:53:19.102976 9, 0xFFFF, sum=0
2079 09:53:19.103415 10, 0xFFFF, sum=0
2080 09:53:19.106289 11, 0xFFFF, sum=0
2081 09:53:19.106738 12, 0xFFFF, sum=0
2082 09:53:19.109541 13, 0xFFFF, sum=0
2083 09:53:19.109975 14, 0x0, sum=1
2084 09:53:19.112846 15, 0x0, sum=2
2085 09:53:19.113331 16, 0x0, sum=3
2086 09:53:19.113842 17, 0x0, sum=4
2087 09:53:19.120636 pattern=2 first_step=14 total pass=5 best_step=16
2088 09:53:19.121141 ==
2089 09:53:19.124289 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2090 09:53:19.128079 fsp= 1, odt_onoff= 1, Byte mode= 0
2091 09:53:19.128602 ==
2092 09:53:19.130901 Start DQ dly to find pass range UseTestEngine =1
2093 09:53:19.134284 x-axis: bit #, y-axis: DQ dly (-127~63)
2094 09:53:19.137752 RX Vref Scan = 0
2095 09:53:19.140766 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2096 09:53:19.144437 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2097 09:53:19.144963 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2098 09:53:19.148218 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2099 09:53:19.151092 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2100 09:53:19.154533 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2101 09:53:19.158182 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2102 09:53:19.161732 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2103 09:53:19.164947 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2104 09:53:19.168121 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2105 09:53:19.168652 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2106 09:53:19.171277 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2107 09:53:19.174673 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2108 09:53:19.178497 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2109 09:53:19.181395 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2110 09:53:19.184679 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2111 09:53:19.188262 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2112 09:53:19.191131 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2113 09:53:19.191571 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2114 09:53:19.195178 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2115 09:53:19.198121 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2116 09:53:19.202511 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2117 09:53:19.203037 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2118 09:53:19.207002 -3, [0] xxxoxxxx xxxxxxxx [MSB]
2119 09:53:19.210714 -2, [0] xxxoxxxx xxxxxxxx [MSB]
2120 09:53:19.215072 -1, [0] xxxoxoxx xxxxxxxx [MSB]
2121 09:53:19.215508 0, [0] xxxoxoxx oxxoxxxx [MSB]
2122 09:53:19.219114 1, [0] xxxoxoxx oxxoxxox [MSB]
2123 09:53:19.222908 2, [0] xxxoxoox oxxoxoox [MSB]
2124 09:53:19.223502 3, [0] xxxoxooo ooxooooo [MSB]
2125 09:53:19.226296 4, [0] xxxoxooo ooxooooo [MSB]
2126 09:53:19.229387 5, [0] xxxoxooo ooxooooo [MSB]
2127 09:53:19.232986 6, [0] xoxoxooo oooooooo [MSB]
2128 09:53:19.236173 32, [0] oooxoooo oooooooo [MSB]
2129 09:53:19.239465 33, [0] oooxoooo oooooooo [MSB]
2130 09:53:19.242840 34, [0] oooxoxoo oooooxoo [MSB]
2131 09:53:19.246280 35, [0] oooxoxxx oooxoxxo [MSB]
2132 09:53:19.249709 36, [0] oooxoxxx xooxoxxo [MSB]
2133 09:53:19.250158 37, [0] oooxoxxx xxoxoxxo [MSB]
2134 09:53:19.253378 38, [0] oooxoxxx xxoxxxxx [MSB]
2135 09:53:19.256590 39, [0] ooxxoxxx xxoxxxxx [MSB]
2136 09:53:19.259671 40, [0] ooxxoxxx xxxxxxxx [MSB]
2137 09:53:19.263245 41, [0] oxxxxxxx xxxxxxxx [MSB]
2138 09:53:19.266316 42, [0] xxxxxxxx xxxxxxxx [MSB]
2139 09:53:19.269761 iDelay=42, Bit 0, Center 24 (7 ~ 41) 35
2140 09:53:19.273155 iDelay=42, Bit 1, Center 23 (6 ~ 40) 35
2141 09:53:19.276721 iDelay=42, Bit 2, Center 22 (7 ~ 38) 32
2142 09:53:19.279952 iDelay=42, Bit 3, Center 14 (-3 ~ 31) 35
2143 09:53:19.283158 iDelay=42, Bit 4, Center 23 (7 ~ 40) 34
2144 09:53:19.287655 iDelay=42, Bit 5, Center 16 (-1 ~ 33) 35
2145 09:53:19.290353 iDelay=42, Bit 6, Center 18 (2 ~ 34) 33
2146 09:53:19.293846 iDelay=42, Bit 7, Center 18 (3 ~ 34) 32
2147 09:53:19.297141 iDelay=42, Bit 8, Center 17 (0 ~ 35) 36
2148 09:53:19.300468 iDelay=42, Bit 9, Center 19 (3 ~ 36) 34
2149 09:53:19.303569 iDelay=42, Bit 10, Center 22 (6 ~ 39) 34
2150 09:53:19.306931 iDelay=42, Bit 11, Center 17 (0 ~ 34) 35
2151 09:53:19.310454 iDelay=42, Bit 12, Center 20 (3 ~ 37) 35
2152 09:53:19.313672 iDelay=42, Bit 13, Center 17 (2 ~ 33) 32
2153 09:53:19.317202 iDelay=42, Bit 14, Center 17 (1 ~ 34) 34
2154 09:53:19.320458 iDelay=42, Bit 15, Center 20 (3 ~ 37) 35
2155 09:53:19.323612 ==
2156 09:53:19.327228 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2157 09:53:19.330426 fsp= 1, odt_onoff= 1, Byte mode= 0
2158 09:53:19.330535 ==
2159 09:53:19.330632 DQS Delay:
2160 09:53:19.333571 DQS0 = 0, DQS1 = 0
2161 09:53:19.333669 DQM Delay:
2162 09:53:19.337332 DQM0 = 19, DQM1 = 18
2163 09:53:19.337636 DQ Delay:
2164 09:53:19.341016 DQ0 =24, DQ1 =23, DQ2 =22, DQ3 =14
2165 09:53:19.344387 DQ4 =23, DQ5 =16, DQ6 =18, DQ7 =18
2166 09:53:19.347697 DQ8 =17, DQ9 =19, DQ10 =22, DQ11 =17
2167 09:53:19.350888 DQ12 =20, DQ13 =17, DQ14 =17, DQ15 =20
2168 09:53:19.351189
2169 09:53:19.351421
2170 09:53:19.351635
2171 09:53:19.354410 [DramC_TX_OE_Calibration] TA2
2172 09:53:19.357603 Original DQ_B0 (3 6) =30, OEN = 27
2173 09:53:19.360879 Original DQ_B1 (3 6) =30, OEN = 27
2174 09:53:19.361189 23, 0x0, End_B0=23 End_B1=23
2175 09:53:19.364462 24, 0x0, End_B0=24 End_B1=24
2176 09:53:19.367541 25, 0x0, End_B0=25 End_B1=25
2177 09:53:19.370971 26, 0x0, End_B0=26 End_B1=26
2178 09:53:19.374601 27, 0x0, End_B0=27 End_B1=27
2179 09:53:19.375055 28, 0x0, End_B0=28 End_B1=28
2180 09:53:19.377939 29, 0x0, End_B0=29 End_B1=29
2181 09:53:19.381437 30, 0x0, End_B0=30 End_B1=30
2182 09:53:19.384618 31, 0xFFFF, End_B0=30 End_B1=30
2183 09:53:19.388105 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2184 09:53:19.394505 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2185 09:53:19.395028
2186 09:53:19.395360
2187 09:53:19.397641 Write Rank1 MR23 =0x3f
2188 09:53:19.398073 [DQSOSC]
2189 09:53:19.404703 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e, (MSB)MR19= 0x3, tDQSOscB0 = 346 ps tDQSOscB1 = 0 ps
2190 09:53:19.411282 CH0_RK1: MR19=0x3, MR18=0x8E, DQSOSC=346, MR23=63, INC=20, DEC=30
2191 09:53:19.414864 Write Rank1 MR23 =0x3f
2192 09:53:19.415301 [DQSOSC]
2193 09:53:19.421322 [DQSOSCAuto] RK1, (LSB)MR18= 0x8c, (MSB)MR19= 0x3, tDQSOscB0 = 346 ps tDQSOscB1 = 0 ps
2194 09:53:19.424957 CH0 RK1: MR19=3, MR18=8C
2195 09:53:19.428392 [RxdqsGatingPostProcess] freq 1600
2196 09:53:19.431529 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2197 09:53:19.435141 Rank: 0
2198 09:53:19.435650 best DQS0 dly(2T, 0.5T) = (2, 5)
2199 09:53:19.438411 best DQS1 dly(2T, 0.5T) = (2, 5)
2200 09:53:19.441601 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2201 09:53:19.445486 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2202 09:53:19.446001 Rank: 1
2203 09:53:19.448317 best DQS0 dly(2T, 0.5T) = (2, 6)
2204 09:53:19.451845 best DQS1 dly(2T, 0.5T) = (2, 6)
2205 09:53:19.454850 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2206 09:53:19.458620 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2207 09:53:19.465011 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2208 09:53:19.468462 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2209 09:53:19.471876 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2210 09:53:19.475168 Write Rank0 MR13 =0x59
2211 09:53:19.475675 ==
2212 09:53:19.478791 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2213 09:53:19.481886 fsp= 1, odt_onoff= 1, Byte mode= 0
2214 09:53:19.482367 ==
2215 09:53:19.485540 === u2Vref_new: 0x56 --> 0x3a
2216 09:53:19.488587 === u2Vref_new: 0x58 --> 0x58
2217 09:53:19.491794 === u2Vref_new: 0x5a --> 0x5a
2218 09:53:19.495234 === u2Vref_new: 0x5c --> 0x78
2219 09:53:19.498376 === u2Vref_new: 0x5e --> 0x7a
2220 09:53:19.501548 === u2Vref_new: 0x60 --> 0x90
2221 09:53:19.505512 [CA 0] Center 37 (11~63) winsize 53
2222 09:53:19.508304 [CA 1] Center 35 (8~63) winsize 56
2223 09:53:19.511613 [CA 2] Center 34 (5~63) winsize 59
2224 09:53:19.512048 [CA 3] Center 33 (4~63) winsize 60
2225 09:53:19.515037 [CA 4] Center 34 (6~63) winsize 58
2226 09:53:19.518664 [CA 5] Center 28 (-1~57) winsize 59
2227 09:53:19.519468
2228 09:53:19.521862 [CATrainingPosCal] consider 1 rank data
2229 09:53:19.525354 u2DelayCellTimex100 = 753/100 ps
2230 09:53:19.528971 CA0 delay=37 (11~63),Diff = 9 PI (11 cell)
2231 09:53:19.531891 CA1 delay=35 (8~63),Diff = 7 PI (9 cell)
2232 09:53:19.538794 CA2 delay=34 (5~63),Diff = 6 PI (7 cell)
2233 09:53:19.542128 CA3 delay=33 (4~63),Diff = 5 PI (6 cell)
2234 09:53:19.545583 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2235 09:53:19.548962 CA5 delay=28 (-1~57),Diff = 0 PI (0 cell)
2236 09:53:19.549470
2237 09:53:19.552272 CA PerBit enable=1, Macro0, CA PI delay=28
2238 09:53:19.555578 === u2Vref_new: 0x58 --> 0x58
2239 09:53:19.556090
2240 09:53:19.556427 Vref(ca) range 1: 24
2241 09:53:19.559147
2242 09:53:19.559656 CS Dly= 12 (43-0-32)
2243 09:53:19.562040 Write Rank0 MR13 =0xd8
2244 09:53:19.562561 Write Rank0 MR13 =0xd8
2245 09:53:19.565486 Write Rank0 MR12 =0x58
2246 09:53:19.568832 Write Rank1 MR13 =0x59
2247 09:53:19.569308 ==
2248 09:53:19.572276 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2249 09:53:19.575696 fsp= 1, odt_onoff= 1, Byte mode= 0
2250 09:53:19.576205 ==
2251 09:53:19.578832 === u2Vref_new: 0x56 --> 0x3a
2252 09:53:19.581968 === u2Vref_new: 0x58 --> 0x58
2253 09:53:19.585679 === u2Vref_new: 0x5a --> 0x5a
2254 09:53:19.588937 === u2Vref_new: 0x5c --> 0x78
2255 09:53:19.592085 === u2Vref_new: 0x5e --> 0x7a
2256 09:53:19.595883 === u2Vref_new: 0x60 --> 0x90
2257 09:53:19.596396
2258 09:53:19.598792 CBT Vref found, early break!
2259 09:53:19.599225 [CA 0] Center 37 (11~63) winsize 53
2260 09:53:19.602316 [CA 1] Center 35 (7~63) winsize 57
2261 09:53:19.605518 [CA 2] Center 33 (4~63) winsize 60
2262 09:53:19.608942 [CA 3] Center 33 (4~63) winsize 60
2263 09:53:19.612199 [CA 4] Center 35 (7~63) winsize 57
2264 09:53:19.616153 [CA 5] Center 27 (-2~57) winsize 60
2265 09:53:19.616680
2266 09:53:19.619321 [CATrainingPosCal] consider 2 rank data
2267 09:53:19.622304 u2DelayCellTimex100 = 753/100 ps
2268 09:53:19.625833 CA0 delay=37 (11~63),Diff = 9 PI (11 cell)
2269 09:53:19.629385 CA1 delay=35 (8~63),Diff = 7 PI (9 cell)
2270 09:53:19.632709 CA2 delay=34 (5~63),Diff = 6 PI (7 cell)
2271 09:53:19.636039 CA3 delay=33 (4~63),Diff = 5 PI (6 cell)
2272 09:53:19.639195 CA4 delay=35 (7~63),Diff = 7 PI (9 cell)
2273 09:53:19.645838 CA5 delay=28 (-1~57),Diff = 0 PI (0 cell)
2274 09:53:19.646463
2275 09:53:19.649447 CA PerBit enable=1, Macro0, CA PI delay=28
2276 09:53:19.652897 === u2Vref_new: 0x56 --> 0x3a
2277 09:53:19.653340
2278 09:53:19.653676 Vref(ca) range 1: 22
2279 09:53:19.653990
2280 09:53:19.655920 CS Dly= 12 (43-0-32)
2281 09:53:19.656367 Write Rank1 MR13 =0xd8
2282 09:53:19.659451 Write Rank1 MR13 =0xd8
2283 09:53:19.662768 Write Rank1 MR12 =0x56
2284 09:53:19.666126 [RankSwap] Rank num 2, (Multi 1), Rank 0
2285 09:53:19.666588 Write Rank0 MR2 =0xad
2286 09:53:19.669418 [Write Leveling]
2287 09:53:19.672872 delay byte0 byte1 byte2 byte3
2288 09:53:19.673386
2289 09:53:19.673725 10 0 0
2290 09:53:19.676379 11 0 0
2291 09:53:19.676910 12 0 0
2292 09:53:19.677258 13 0 0
2293 09:53:19.679907 14 0 0
2294 09:53:19.680426 15 0 0
2295 09:53:19.682886 16 0 0
2296 09:53:19.683325 17 0 0
2297 09:53:19.683667 18 0 0
2298 09:53:19.686487 19 0 0
2299 09:53:19.687035 20 0 0
2300 09:53:19.689413 21 0 0
2301 09:53:19.689854 22 0 0
2302 09:53:19.693383 23 0 0
2303 09:53:19.693908 24 0 0
2304 09:53:19.694293 25 0 0
2305 09:53:19.696525 26 0 0
2306 09:53:19.697050 27 0 0
2307 09:53:19.699889 28 0 0
2308 09:53:19.700333 29 0 0
2309 09:53:19.700677 30 0 0
2310 09:53:19.703026 31 0 ff
2311 09:53:19.703471 32 0 0
2312 09:53:19.706390 33 0 ff
2313 09:53:19.706836 34 0 ff
2314 09:53:19.709721 35 ff ff
2315 09:53:19.710161 36 ff ff
2316 09:53:19.713112 37 ff ff
2317 09:53:19.713549 38 ff ff
2318 09:53:19.713891 39 ff ff
2319 09:53:19.716994 40 ff ff
2320 09:53:19.717520 41 ff ff
2321 09:53:19.723271 pass bytecount = 0xff (0xff: all bytes pass)
2322 09:53:19.723791
2323 09:53:19.724186 DQS0 dly: 35
2324 09:53:19.724750 DQS1 dly: 33
2325 09:53:19.726688 Write Rank0 MR2 =0x2d
2326 09:53:19.730335 [RankSwap] Rank num 2, (Multi 1), Rank 0
2327 09:53:19.733445 Write Rank0 MR1 =0xd6
2328 09:53:19.733958 [Gating]
2329 09:53:19.734434 ==
2330 09:53:19.736892 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2331 09:53:19.739988 fsp= 1, odt_onoff= 1, Byte mode= 0
2332 09:53:19.740422 ==
2333 09:53:19.747011 3 1 0 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2334 09:53:19.750440 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2335 09:53:19.753448 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2336 09:53:19.760143 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2337 09:53:19.763807 3 1 16 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2338 09:53:19.767103 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2339 09:53:19.773661 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2340 09:53:19.776995 3 1 28 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2341 09:53:19.780220 3 2 0 |403 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2342 09:53:19.783728 3 2 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2343 09:53:19.790569 3 2 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2344 09:53:19.793830 3 2 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2345 09:53:19.797262 3 2 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2346 09:53:19.803841 3 2 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2347 09:53:19.807113 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2348 09:53:19.810294 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2349 09:53:19.817271 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2350 09:53:19.820529 3 3 4 |201 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2351 09:53:19.823839 3 3 8 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2352 09:53:19.827065 [Byte 0] Lead/lag Transition tap number (1)
2353 09:53:19.834027 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2354 09:53:19.837708 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2355 09:53:19.840731 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2356 09:53:19.844069 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2357 09:53:19.850820 3 3 28 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2358 09:53:19.853896 3 4 0 |505 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2359 09:53:19.857426 3 4 4 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
2360 09:53:19.864130 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2361 09:53:19.867695 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2362 09:53:19.871192 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2363 09:53:19.874181 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2364 09:53:19.881434 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2365 09:53:19.884256 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2366 09:53:19.887526 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2367 09:53:19.894283 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2368 09:53:19.897813 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2369 09:53:19.900806 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2370 09:53:19.907861 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2371 09:53:19.911112 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2372 09:53:19.914297 [Byte 0] Lead/lag falling Transition (3, 5, 20)
2373 09:53:19.917613 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2374 09:53:19.924253 [Byte 0] Lead/lag Transition tap number (2)
2375 09:53:19.927919 [Byte 1] Lead/lag falling Transition (3, 5, 24)
2376 09:53:19.931033 3 5 28 |d0c 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2377 09:53:19.934530 3 6 0 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2378 09:53:19.941224 [Byte 1] Lead/lag Transition tap number (3)
2379 09:53:19.944179 3 6 4 |4646 4646 |(0 0)(10 10) |(0 0)(0 0)| 0
2380 09:53:19.947902 [Byte 0]First pass (3, 6, 4)
2381 09:53:19.950889 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2382 09:53:19.954415 [Byte 1]First pass (3, 6, 8)
2383 09:53:19.957715 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2384 09:53:19.961167 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2385 09:53:19.964531 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2386 09:53:19.967669 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2387 09:53:19.974463 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2388 09:53:19.977984 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2389 09:53:19.981194 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2390 09:53:19.984607 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2391 09:53:19.988022 All bytes gating window > 1UI, Early break!
2392 09:53:19.988531
2393 09:53:19.991445 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 24)
2394 09:53:19.994643
2395 09:53:19.997786 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 30)
2396 09:53:19.998244
2397 09:53:19.998583
2398 09:53:19.998887
2399 09:53:20.001294 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 24)
2400 09:53:20.001722
2401 09:53:20.004429 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
2402 09:53:20.004854
2403 09:53:20.005185
2404 09:53:20.008069 Write Rank0 MR1 =0x56
2405 09:53:20.008579
2406 09:53:20.011410 best RODT dly(2T, 0.5T) = (2, 2)
2407 09:53:20.011920
2408 09:53:20.014591 best RODT dly(2T, 0.5T) = (2, 2)
2409 09:53:20.015024 ==
2410 09:53:20.017598 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2411 09:53:20.021187 fsp= 1, odt_onoff= 1, Byte mode= 0
2412 09:53:20.021690 ==
2413 09:53:20.028287 Start DQ dly to find pass range UseTestEngine =0
2414 09:53:20.031050 x-axis: bit #, y-axis: DQ dly (-127~63)
2415 09:53:20.031474 RX Vref Scan = 0
2416 09:53:20.034859 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2417 09:53:20.037990 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2418 09:53:20.041135 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2419 09:53:20.044905 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2420 09:53:20.048123 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2421 09:53:20.048638 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2422 09:53:20.051259 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2423 09:53:20.054673 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2424 09:53:20.058079 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2425 09:53:20.061345 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2426 09:53:20.064527 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2427 09:53:20.068260 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2428 09:53:20.071466 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2429 09:53:20.071978 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2430 09:53:20.074784 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2431 09:53:20.078283 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2432 09:53:20.081441 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2433 09:53:20.085127 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2434 09:53:20.088008 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2435 09:53:20.091309 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2436 09:53:20.091830 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2437 09:53:20.094863 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2438 09:53:20.098295 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2439 09:53:20.101204 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2440 09:53:20.105082 -2, [0] xxxxxxxx xxxxxxxo [MSB]
2441 09:53:20.107910 -1, [0] xxxxxxxx xxxxxxxo [MSB]
2442 09:53:20.111680 0, [0] xxxxxxxx xxxxxxxo [MSB]
2443 09:53:20.112194 1, [0] xxxoxxxx xxxxxxxo [MSB]
2444 09:53:20.114693 2, [0] xxxoxxxx xxxxxxxo [MSB]
2445 09:53:20.118318 3, [0] xxoooxxo oooxxxxo [MSB]
2446 09:53:20.121448 4, [0] xxoooxxo oooxxooo [MSB]
2447 09:53:20.124730 5, [0] xxoooxxo oooooooo [MSB]
2448 09:53:20.127701 6, [0] xooooxxo oooooooo [MSB]
2449 09:53:20.128138 31, [0] oooxoooo oooooooo [MSB]
2450 09:53:20.131328 32, [0] ooxxoooo ooooooox [MSB]
2451 09:53:20.134769 33, [0] ooxxoooo oxooooox [MSB]
2452 09:53:20.137808 34, [0] ooxxoooo oxxxooox [MSB]
2453 09:53:20.141446 35, [0] ooxxoooo xxxxooox [MSB]
2454 09:53:20.144432 36, [0] ooxxxoox xxxxoxxx [MSB]
2455 09:53:20.148073 37, [0] ooxxxoox xxxxoxxx [MSB]
2456 09:53:20.148590 38, [0] ooxxxoox xxxxxxxx [MSB]
2457 09:53:20.151074 39, [0] ooxxxoox xxxxxxxx [MSB]
2458 09:53:20.154750 40, [0] ooxxxoox xxxxxxxx [MSB]
2459 09:53:20.157998 41, [0] xxxxxxxx xxxxxxxx [MSB]
2460 09:53:20.161451 iDelay=41, Bit 0, Center 23 (7 ~ 40) 34
2461 09:53:20.164502 iDelay=41, Bit 1, Center 23 (6 ~ 40) 35
2462 09:53:20.167918 iDelay=41, Bit 2, Center 17 (3 ~ 31) 29
2463 09:53:20.171231 iDelay=41, Bit 3, Center 15 (1 ~ 30) 30
2464 09:53:20.174550 iDelay=41, Bit 4, Center 19 (3 ~ 35) 33
2465 09:53:20.177888 iDelay=41, Bit 5, Center 23 (7 ~ 40) 34
2466 09:53:20.181046 iDelay=41, Bit 6, Center 23 (7 ~ 40) 34
2467 09:53:20.184687 iDelay=41, Bit 7, Center 19 (3 ~ 35) 33
2468 09:53:20.191107 iDelay=41, Bit 8, Center 18 (3 ~ 34) 32
2469 09:53:20.194976 iDelay=41, Bit 9, Center 17 (3 ~ 32) 30
2470 09:53:20.197886 iDelay=41, Bit 10, Center 18 (3 ~ 33) 31
2471 09:53:20.201413 iDelay=41, Bit 11, Center 19 (5 ~ 33) 29
2472 09:53:20.204583 iDelay=41, Bit 12, Center 21 (5 ~ 37) 33
2473 09:53:20.207870 iDelay=41, Bit 13, Center 19 (4 ~ 35) 32
2474 09:53:20.211086 iDelay=41, Bit 14, Center 19 (4 ~ 35) 32
2475 09:53:20.214504 iDelay=41, Bit 15, Center 14 (-2 ~ 31) 34
2476 09:53:20.214942 ==
2477 09:53:20.221305 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2478 09:53:20.224719 fsp= 1, odt_onoff= 1, Byte mode= 0
2479 09:53:20.225255 ==
2480 09:53:20.225758 DQS Delay:
2481 09:53:20.227935 DQS0 = 0, DQS1 = 0
2482 09:53:20.228369 DQM Delay:
2483 09:53:20.228705 DQM0 = 20, DQM1 = 18
2484 09:53:20.231039 DQ Delay:
2485 09:53:20.234547 DQ0 =23, DQ1 =23, DQ2 =17, DQ3 =15
2486 09:53:20.237919 DQ4 =19, DQ5 =23, DQ6 =23, DQ7 =19
2487 09:53:20.241576 DQ8 =18, DQ9 =17, DQ10 =18, DQ11 =19
2488 09:53:20.244406 DQ12 =21, DQ13 =19, DQ14 =19, DQ15 =14
2489 09:53:20.244839
2490 09:53:20.245172
2491 09:53:20.245540 DramC Write-DBI off
2492 09:53:20.245846 ==
2493 09:53:20.251208 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2494 09:53:20.254666 fsp= 1, odt_onoff= 1, Byte mode= 0
2495 09:53:20.255179 ==
2496 09:53:20.257822 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2497 09:53:20.258449
2498 09:53:20.261685 Begin, DQ Scan Range 929~1185
2499 09:53:20.262192
2500 09:53:20.262572
2501 09:53:20.264473 TX Vref Scan disable
2502 09:53:20.268251 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2503 09:53:20.271313 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2504 09:53:20.274796 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2505 09:53:20.278135 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2506 09:53:20.281603 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2507 09:53:20.284697 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2508 09:53:20.287978 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2509 09:53:20.291069 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2510 09:53:20.294925 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2511 09:53:20.297824 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2512 09:53:20.301483 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2513 09:53:20.304588 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2514 09:53:20.308021 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2515 09:53:20.311506 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2516 09:53:20.314786 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2517 09:53:20.321573 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2518 09:53:20.324881 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2519 09:53:20.328017 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2520 09:53:20.331388 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2521 09:53:20.334649 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2522 09:53:20.338251 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2523 09:53:20.341639 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2524 09:53:20.344849 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2525 09:53:20.348525 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2526 09:53:20.351654 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2527 09:53:20.355090 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2528 09:53:20.358127 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2529 09:53:20.361737 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2530 09:53:20.364899 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2531 09:53:20.368377 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2532 09:53:20.371736 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2533 09:53:20.375198 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2534 09:53:20.378662 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2535 09:53:20.381733 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2536 09:53:20.388509 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2537 09:53:20.391806 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2538 09:53:20.395144 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2539 09:53:20.398707 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2540 09:53:20.401394 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2541 09:53:20.404895 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2542 09:53:20.408288 969 |3 6 9|[0] xxxxxxxx xxxxxxxo [MSB]
2543 09:53:20.411935 970 |3 6 10|[0] xxxoxxxx ooxxxxxo [MSB]
2544 09:53:20.414730 971 |3 6 11|[0] xxxoxxxx oooxxxxo [MSB]
2545 09:53:20.418659 972 |3 6 12|[0] xxxoxxxx oooooxoo [MSB]
2546 09:53:20.421831 973 |3 6 13|[0] xxooxxxx oooooooo [MSB]
2547 09:53:20.425401 974 |3 6 14|[0] xxoooxxx oooooooo [MSB]
2548 09:53:20.428362 975 |3 6 15|[0] xxoooxxo oooooooo [MSB]
2549 09:53:20.431894 976 |3 6 16|[0] xooooooo oooooooo [MSB]
2550 09:53:20.439682 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2551 09:53:20.442756 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
2552 09:53:20.446425 994 |3 6 34|[0] ooxxoooo xxxxxxxx [MSB]
2553 09:53:20.449585 995 |3 6 35|[0] ooxxoooo xxxxxxxx [MSB]
2554 09:53:20.452900 996 |3 6 36|[0] ooxxooox xxxxxxxx [MSB]
2555 09:53:20.456101 997 |3 6 37|[0] ooxxxoox xxxxxxxx [MSB]
2556 09:53:20.459649 998 |3 6 38|[0] oxxxxoox xxxxxxxx [MSB]
2557 09:53:20.462540 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
2558 09:53:20.466309 Byte0, DQ PI dly=984, DQM PI dly= 984
2559 09:53:20.469537 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
2560 09:53:20.470049
2561 09:53:20.476238 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
2562 09:53:20.476754
2563 09:53:20.479501 Byte1, DQ PI dly=981, DQM PI dly= 981
2564 09:53:20.482740 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
2565 09:53:20.483256
2566 09:53:20.486168 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
2567 09:53:20.486716
2568 09:53:20.487049 ==
2569 09:53:20.492799 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2570 09:53:20.496164 fsp= 1, odt_onoff= 1, Byte mode= 0
2571 09:53:20.496600 ==
2572 09:53:20.499359 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2573 09:53:20.499875
2574 09:53:20.502892 Begin, DQ Scan Range 957~1021
2575 09:53:20.505830 Write Rank0 MR14 =0x0
2576 09:53:20.513064
2577 09:53:20.513586 CH=1, VrefRange= 0, VrefLevel = 0
2578 09:53:20.519968 TX Bit0 (978~996) 19 987, Bit8 (972~991) 20 981,
2579 09:53:20.522944 TX Bit1 (977~993) 17 985, Bit9 (972~989) 18 980,
2580 09:53:20.530120 TX Bit2 (976~990) 15 983, Bit10 (974~989) 16 981,
2581 09:53:20.533180 TX Bit3 (974~989) 16 981, Bit11 (975~991) 17 983,
2582 09:53:20.536498 TX Bit4 (976~991) 16 983, Bit12 (976~992) 17 984,
2583 09:53:20.543317 TX Bit5 (977~996) 20 986, Bit13 (976~991) 16 983,
2584 09:53:20.546445 TX Bit6 (978~996) 19 987, Bit14 (976~991) 16 983,
2585 09:53:20.549919 TX Bit7 (977~991) 15 984, Bit15 (970~988) 19 979,
2586 09:53:20.550475
2587 09:53:20.553214 Write Rank0 MR14 =0x2
2588 09:53:20.561318
2589 09:53:20.561826 CH=1, VrefRange= 0, VrefLevel = 2
2590 09:53:20.568003 TX Bit0 (977~996) 20 986, Bit8 (972~991) 20 981,
2591 09:53:20.571245 TX Bit1 (977~994) 18 985, Bit9 (971~990) 20 980,
2592 09:53:20.578185 TX Bit2 (976~990) 15 983, Bit10 (974~991) 18 982,
2593 09:53:20.581019 TX Bit3 (973~989) 17 981, Bit11 (975~992) 18 983,
2594 09:53:20.585109 TX Bit4 (976~991) 16 983, Bit12 (975~992) 18 983,
2595 09:53:20.591112 TX Bit5 (977~996) 20 986, Bit13 (975~991) 17 983,
2596 09:53:20.594591 TX Bit6 (978~996) 19 987, Bit14 (975~991) 17 983,
2597 09:53:20.597650 TX Bit7 (976~991) 16 983, Bit15 (970~988) 19 979,
2598 09:53:20.598083
2599 09:53:20.601342 Write Rank0 MR14 =0x4
2600 09:53:20.609482
2601 09:53:20.609989 CH=1, VrefRange= 0, VrefLevel = 4
2602 09:53:20.616397 TX Bit0 (977~997) 21 987, Bit8 (971~991) 21 981,
2603 09:53:20.619648 TX Bit1 (977~995) 19 986, Bit9 (971~991) 21 981,
2604 09:53:20.626112 TX Bit2 (975~990) 16 982, Bit10 (974~991) 18 982,
2605 09:53:20.629540 TX Bit3 (973~990) 18 981, Bit11 (974~992) 19 983,
2606 09:53:20.632738 TX Bit4 (976~992) 17 984, Bit12 (975~992) 18 983,
2607 09:53:20.639487 TX Bit5 (977~997) 21 987, Bit13 (975~992) 18 983,
2608 09:53:20.642768 TX Bit6 (977~997) 21 987, Bit14 (975~991) 17 983,
2609 09:53:20.646271 TX Bit7 (976~991) 16 983, Bit15 (970~989) 20 979,
2610 09:53:20.646710
2611 09:53:20.649281 Write Rank0 MR14 =0x6
2612 09:53:20.658033
2613 09:53:20.658598 CH=1, VrefRange= 0, VrefLevel = 6
2614 09:53:20.664441 TX Bit0 (977~997) 21 987, Bit8 (971~991) 21 981,
2615 09:53:20.667733 TX Bit1 (977~995) 19 986, Bit9 (971~991) 21 981,
2616 09:53:20.674470 TX Bit2 (975~990) 16 982, Bit10 (972~991) 20 981,
2617 09:53:20.677966 TX Bit3 (973~990) 18 981, Bit11 (974~992) 19 983,
2618 09:53:20.681135 TX Bit4 (976~993) 18 984, Bit12 (975~993) 19 984,
2619 09:53:20.688013 TX Bit5 (977~997) 21 987, Bit13 (975~992) 18 983,
2620 09:53:20.691133 TX Bit6 (977~997) 21 987, Bit14 (974~991) 18 982,
2621 09:53:20.694371 TX Bit7 (976~992) 17 984, Bit15 (969~990) 22 979,
2622 09:53:20.694909
2623 09:53:20.697405 Write Rank0 MR14 =0x8
2624 09:53:20.705972
2625 09:53:20.706532 CH=1, VrefRange= 0, VrefLevel = 8
2626 09:53:20.712826 TX Bit0 (977~997) 21 987, Bit8 (971~992) 22 981,
2627 09:53:20.715919 TX Bit1 (976~996) 21 986, Bit9 (971~991) 21 981,
2628 09:53:20.722654 TX Bit2 (975~991) 17 983, Bit10 (972~991) 20 981,
2629 09:53:20.725801 TX Bit3 (972~990) 19 981, Bit11 (974~992) 19 983,
2630 09:53:20.729263 TX Bit4 (975~993) 19 984, Bit12 (974~993) 20 983,
2631 09:53:20.736057 TX Bit5 (977~997) 21 987, Bit13 (975~992) 18 983,
2632 09:53:20.739311 TX Bit6 (977~997) 21 987, Bit14 (974~992) 19 983,
2633 09:53:20.742491 TX Bit7 (976~992) 17 984, Bit15 (969~990) 22 979,
2634 09:53:20.743068
2635 09:53:20.745959 Write Rank0 MR14 =0xa
2636 09:53:20.754202
2637 09:53:20.757735 CH=1, VrefRange= 0, VrefLevel = 10
2638 09:53:20.761387 TX Bit0 (977~997) 21 987, Bit8 (970~992) 23 981,
2639 09:53:20.764075 TX Bit1 (976~996) 21 986, Bit9 (970~991) 22 980,
2640 09:53:20.770665 TX Bit2 (975~991) 17 983, Bit10 (972~992) 21 982,
2641 09:53:20.774130 TX Bit3 (972~990) 19 981, Bit11 (973~993) 21 983,
2642 09:53:20.777948 TX Bit4 (975~994) 20 984, Bit12 (974~993) 20 983,
2643 09:53:20.784672 TX Bit5 (977~997) 21 987, Bit13 (974~992) 19 983,
2644 09:53:20.787670 TX Bit6 (977~997) 21 987, Bit14 (973~992) 20 982,
2645 09:53:20.790924 TX Bit7 (976~993) 18 984, Bit15 (969~991) 23 980,
2646 09:53:20.791438
2647 09:53:20.794443 Write Rank0 MR14 =0xc
2648 09:53:20.802620
2649 09:53:20.805937 CH=1, VrefRange= 0, VrefLevel = 12
2650 09:53:20.809376 TX Bit0 (977~998) 22 987, Bit8 (970~992) 23 981,
2651 09:53:20.812651 TX Bit1 (976~997) 22 986, Bit9 (970~991) 22 980,
2652 09:53:20.819222 TX Bit2 (974~991) 18 982, Bit10 (972~992) 21 982,
2653 09:53:20.822790 TX Bit3 (971~991) 21 981, Bit11 (973~993) 21 983,
2654 09:53:20.826010 TX Bit4 (975~994) 20 984, Bit12 (973~994) 22 983,
2655 09:53:20.832849 TX Bit5 (976~998) 23 987, Bit13 (974~992) 19 983,
2656 09:53:20.836430 TX Bit6 (977~998) 22 987, Bit14 (973~992) 20 982,
2657 09:53:20.839235 TX Bit7 (976~993) 18 984, Bit15 (969~991) 23 980,
2658 09:53:20.839669
2659 09:53:20.842530 Write Rank0 MR14 =0xe
2660 09:53:20.850610
2661 09:53:20.854300 CH=1, VrefRange= 0, VrefLevel = 14
2662 09:53:20.857706 TX Bit0 (976~998) 23 987, Bit8 (970~992) 23 981,
2663 09:53:20.860838 TX Bit1 (976~997) 22 986, Bit9 (970~992) 23 981,
2664 09:53:20.867766 TX Bit2 (974~992) 19 983, Bit10 (971~992) 22 981,
2665 09:53:20.870880 TX Bit3 (971~991) 21 981, Bit11 (972~993) 22 982,
2666 09:53:20.874298 TX Bit4 (975~995) 21 985, Bit12 (973~994) 22 983,
2667 09:53:20.880977 TX Bit5 (976~998) 23 987, Bit13 (973~993) 21 983,
2668 09:53:20.884077 TX Bit6 (977~998) 22 987, Bit14 (972~992) 21 982,
2669 09:53:20.887672 TX Bit7 (975~994) 20 984, Bit15 (969~991) 23 980,
2670 09:53:20.887886
2671 09:53:20.890762 Write Rank0 MR14 =0x10
2672 09:53:20.899745
2673 09:53:20.902695 CH=1, VrefRange= 0, VrefLevel = 16
2674 09:53:20.906362 TX Bit0 (977~998) 22 987, Bit8 (970~992) 23 981,
2675 09:53:20.909702 TX Bit1 (976~997) 22 986, Bit9 (970~992) 23 981,
2676 09:53:20.916187 TX Bit2 (974~992) 19 983, Bit10 (970~993) 24 981,
2677 09:53:20.919560 TX Bit3 (970~992) 23 981, Bit11 (972~993) 22 982,
2678 09:53:20.922862 TX Bit4 (974~996) 23 985, Bit12 (972~994) 23 983,
2679 09:53:20.929629 TX Bit5 (976~998) 23 987, Bit13 (972~993) 22 982,
2680 09:53:20.933492 TX Bit6 (976~998) 23 987, Bit14 (972~992) 21 982,
2681 09:53:20.936564 TX Bit7 (975~995) 21 985, Bit15 (969~991) 23 980,
2682 09:53:20.937076
2683 09:53:20.939730 Write Rank0 MR14 =0x12
2684 09:53:20.948347
2685 09:53:20.951473 CH=1, VrefRange= 0, VrefLevel = 18
2686 09:53:20.955150 TX Bit0 (976~998) 23 987, Bit8 (970~993) 24 981,
2687 09:53:20.958583 TX Bit1 (976~997) 22 986, Bit9 (970~992) 23 981,
2688 09:53:20.965257 TX Bit2 (973~993) 21 983, Bit10 (970~993) 24 981,
2689 09:53:20.968762 TX Bit3 (970~992) 23 981, Bit11 (972~994) 23 983,
2690 09:53:20.971521 TX Bit4 (974~996) 23 985, Bit12 (972~995) 24 983,
2691 09:53:20.978183 TX Bit5 (976~998) 23 987, Bit13 (971~993) 23 982,
2692 09:53:20.982025 TX Bit6 (976~998) 23 987, Bit14 (972~993) 22 982,
2693 09:53:20.984872 TX Bit7 (974~995) 22 984, Bit15 (968~992) 25 980,
2694 09:53:20.985384
2695 09:53:20.988426 Write Rank0 MR14 =0x14
2696 09:53:20.997271
2697 09:53:21.000935 CH=1, VrefRange= 0, VrefLevel = 20
2698 09:53:21.004503 TX Bit0 (976~999) 24 987, Bit8 (969~992) 24 980,
2699 09:53:21.007163 TX Bit1 (975~998) 24 986, Bit9 (969~992) 24 980,
2700 09:53:21.014189 TX Bit2 (972~994) 23 983, Bit10 (970~993) 24 981,
2701 09:53:21.017119 TX Bit3 (970~993) 24 981, Bit11 (971~994) 24 982,
2702 09:53:21.020540 TX Bit4 (974~997) 24 985, Bit12 (972~995) 24 983,
2703 09:53:21.026898 TX Bit5 (976~998) 23 987, Bit13 (971~994) 24 982,
2704 09:53:21.030535 TX Bit6 (976~999) 24 987, Bit14 (971~993) 23 982,
2705 09:53:21.033661 TX Bit7 (975~996) 22 985, Bit15 (968~992) 25 980,
2706 09:53:21.034099
2707 09:53:21.036703 Write Rank0 MR14 =0x16
2708 09:53:21.045659
2709 09:53:21.048884 CH=1, VrefRange= 0, VrefLevel = 22
2710 09:53:21.052320 TX Bit0 (976~999) 24 987, Bit8 (969~992) 24 980,
2711 09:53:21.055878 TX Bit1 (975~998) 24 986, Bit9 (969~992) 24 980,
2712 09:53:21.062593 TX Bit2 (972~994) 23 983, Bit10 (970~993) 24 981,
2713 09:53:21.065828 TX Bit3 (970~993) 24 981, Bit11 (971~994) 24 982,
2714 09:53:21.069131 TX Bit4 (973~997) 25 985, Bit12 (972~995) 24 983,
2715 09:53:21.076018 TX Bit5 (975~998) 24 986, Bit13 (972~994) 23 983,
2716 09:53:21.079201 TX Bit6 (976~999) 24 987, Bit14 (971~993) 23 982,
2717 09:53:21.082319 TX Bit7 (974~997) 24 985, Bit15 (968~992) 25 980,
2718 09:53:21.082759
2719 09:53:21.085944 Write Rank0 MR14 =0x18
2720 09:53:21.094687
2721 09:53:21.097775 CH=1, VrefRange= 0, VrefLevel = 24
2722 09:53:21.101401 TX Bit0 (976~999) 24 987, Bit8 (969~992) 24 980,
2723 09:53:21.104496 TX Bit1 (975~998) 24 986, Bit9 (969~992) 24 980,
2724 09:53:21.111338 TX Bit2 (972~995) 24 983, Bit10 (970~993) 24 981,
2725 09:53:21.114948 TX Bit3 (969~993) 25 981, Bit11 (971~994) 24 982,
2726 09:53:21.117986 TX Bit4 (973~997) 25 985, Bit12 (971~994) 24 982,
2727 09:53:21.124605 TX Bit5 (975~998) 24 986, Bit13 (971~993) 23 982,
2728 09:53:21.127778 TX Bit6 (976~999) 24 987, Bit14 (971~993) 23 982,
2729 09:53:21.131096 TX Bit7 (974~997) 24 985, Bit15 (968~992) 25 980,
2730 09:53:21.131562
2731 09:53:21.134618 Write Rank0 MR14 =0x1a
2732 09:53:21.143307
2733 09:53:21.146940 CH=1, VrefRange= 0, VrefLevel = 26
2734 09:53:21.149780 TX Bit0 (976~999) 24 987, Bit8 (969~992) 24 980,
2735 09:53:21.153539 TX Bit1 (975~998) 24 986, Bit9 (969~992) 24 980,
2736 09:53:21.160280 TX Bit2 (972~995) 24 983, Bit10 (970~993) 24 981,
2737 09:53:21.163629 TX Bit3 (969~993) 25 981, Bit11 (971~994) 24 982,
2738 09:53:21.167211 TX Bit4 (973~997) 25 985, Bit12 (971~994) 24 982,
2739 09:53:21.173636 TX Bit5 (975~998) 24 986, Bit13 (971~993) 23 982,
2740 09:53:21.177248 TX Bit6 (976~999) 24 987, Bit14 (971~993) 23 982,
2741 09:53:21.180134 TX Bit7 (974~997) 24 985, Bit15 (968~992) 25 980,
2742 09:53:21.180652
2743 09:53:21.183385 Write Rank0 MR14 =0x1c
2744 09:53:21.192015
2745 09:53:21.195632 CH=1, VrefRange= 0, VrefLevel = 28
2746 09:53:21.198676 TX Bit0 (976~999) 24 987, Bit8 (969~992) 24 980,
2747 09:53:21.202355 TX Bit1 (975~998) 24 986, Bit9 (969~992) 24 980,
2748 09:53:21.208754 TX Bit2 (972~995) 24 983, Bit10 (970~993) 24 981,
2749 09:53:21.212279 TX Bit3 (969~993) 25 981, Bit11 (971~994) 24 982,
2750 09:53:21.215336 TX Bit4 (973~997) 25 985, Bit12 (971~994) 24 982,
2751 09:53:21.222105 TX Bit5 (975~998) 24 986, Bit13 (971~993) 23 982,
2752 09:53:21.225593 TX Bit6 (976~999) 24 987, Bit14 (971~993) 23 982,
2753 09:53:21.228779 TX Bit7 (974~997) 24 985, Bit15 (968~992) 25 980,
2754 09:53:21.229228
2755 09:53:21.232192 Write Rank0 MR14 =0x1e
2756 09:53:21.240681
2757 09:53:21.243855 CH=1, VrefRange= 0, VrefLevel = 30
2758 09:53:21.247474 TX Bit0 (976~999) 24 987, Bit8 (969~992) 24 980,
2759 09:53:21.250878 TX Bit1 (975~998) 24 986, Bit9 (969~992) 24 980,
2760 09:53:21.257875 TX Bit2 (972~995) 24 983, Bit10 (970~993) 24 981,
2761 09:53:21.261436 TX Bit3 (969~993) 25 981, Bit11 (971~994) 24 982,
2762 09:53:21.264648 TX Bit4 (973~997) 25 985, Bit12 (971~994) 24 982,
2763 09:53:21.270952 TX Bit5 (975~998) 24 986, Bit13 (971~993) 23 982,
2764 09:53:21.274343 TX Bit6 (976~999) 24 987, Bit14 (971~993) 23 982,
2765 09:53:21.277550 TX Bit7 (974~997) 24 985, Bit15 (968~992) 25 980,
2766 09:53:21.278075
2767 09:53:21.278562
2768 09:53:21.284561 TX Vref found, early break! 364< 365
2769 09:53:21.287678 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
2770 09:53:21.291068 u1DelayCellOfst[0]=7 cells (6 PI)
2771 09:53:21.294345 u1DelayCellOfst[1]=6 cells (5 PI)
2772 09:53:21.297592 u1DelayCellOfst[2]=2 cells (2 PI)
2773 09:53:21.300783 u1DelayCellOfst[3]=0 cells (0 PI)
2774 09:53:21.301310 u1DelayCellOfst[4]=5 cells (4 PI)
2775 09:53:21.304082 u1DelayCellOfst[5]=6 cells (5 PI)
2776 09:53:21.307322 u1DelayCellOfst[6]=7 cells (6 PI)
2777 09:53:21.310780 u1DelayCellOfst[7]=5 cells (4 PI)
2778 09:53:21.314118 Byte0, DQ PI dly=981, DQM PI dly= 984
2779 09:53:21.320685 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
2780 09:53:21.321212
2781 09:53:21.324080 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
2782 09:53:21.324606
2783 09:53:21.327300 u1DelayCellOfst[8]=0 cells (0 PI)
2784 09:53:21.330533 u1DelayCellOfst[9]=0 cells (0 PI)
2785 09:53:21.334556 u1DelayCellOfst[10]=1 cells (1 PI)
2786 09:53:21.337374 u1DelayCellOfst[11]=2 cells (2 PI)
2787 09:53:21.337883 u1DelayCellOfst[12]=2 cells (2 PI)
2788 09:53:21.340627 u1DelayCellOfst[13]=2 cells (2 PI)
2789 09:53:21.343979 u1DelayCellOfst[14]=2 cells (2 PI)
2790 09:53:21.347544 u1DelayCellOfst[15]=0 cells (0 PI)
2791 09:53:21.350952 Byte1, DQ PI dly=980, DQM PI dly= 981
2792 09:53:21.357511 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
2793 09:53:21.358025
2794 09:53:21.360786 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
2795 09:53:21.361443
2796 09:53:21.364396 Write Rank0 MR14 =0x18
2797 09:53:21.364910
2798 09:53:21.365249 Final TX Range 0 Vref 24
2799 09:53:21.365559
2800 09:53:21.371186 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2801 09:53:21.371701
2802 09:53:21.377754 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2803 09:53:21.384412 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2804 09:53:21.390969 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2805 09:53:21.394194 Write Rank0 MR3 =0xb0
2806 09:53:21.398054 DramC Write-DBI on
2807 09:53:21.398624 ==
2808 09:53:21.401087 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2809 09:53:21.404200 fsp= 1, odt_onoff= 1, Byte mode= 0
2810 09:53:21.404715 ==
2811 09:53:21.407503 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2812 09:53:21.410754
2813 09:53:21.411184 Begin, DQ Scan Range 701~765
2814 09:53:21.411518
2815 09:53:21.411820
2816 09:53:21.413870 TX Vref Scan disable
2817 09:53:21.417438 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2818 09:53:21.420760 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2819 09:53:21.424409 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2820 09:53:21.427505 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2821 09:53:21.430746 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2822 09:53:21.434316 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2823 09:53:21.437555 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2824 09:53:21.440685 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2825 09:53:21.444205 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2826 09:53:21.447632 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2827 09:53:21.450793 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2828 09:53:21.454071 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2829 09:53:21.457715 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2830 09:53:21.464156 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2831 09:53:21.467280 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2832 09:53:21.474670 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2833 09:53:21.478267 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2834 09:53:21.481372 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2835 09:53:21.484595 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2836 09:53:21.487603 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2837 09:53:21.490976 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2838 09:53:21.494802 743 |2 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
2839 09:53:21.497864 Byte0, DQ PI dly=729, DQM PI dly= 729
2840 09:53:21.501307 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 25)
2841 09:53:21.501819
2842 09:53:21.508274 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 25)
2843 09:53:21.508794
2844 09:53:21.510903 Byte1, DQ PI dly=724, DQM PI dly= 724
2845 09:53:21.514629 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
2846 09:53:21.515144
2847 09:53:21.518012 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
2848 09:53:21.518558
2849 09:53:21.524708 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2850 09:53:21.531461 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2851 09:53:21.537922 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2852 09:53:21.541662 Write Rank0 MR3 =0x30
2853 09:53:21.544939 DramC Write-DBI off
2854 09:53:21.545634
2855 09:53:21.546066 [DATLAT]
2856 09:53:21.548164 Freq=1600, CH1 RK0, use_rxtx_scan=0
2857 09:53:21.548677
2858 09:53:21.549009 DATLAT Default: 0xf
2859 09:53:21.551117 7, 0xFFFF, sum=0
2860 09:53:21.551553 8, 0xFFFF, sum=0
2861 09:53:21.554646 9, 0xFFFF, sum=0
2862 09:53:21.555080 10, 0xFFFF, sum=0
2863 09:53:21.557877 11, 0xFFFF, sum=0
2864 09:53:21.558440 12, 0xFFFF, sum=0
2865 09:53:21.561274 13, 0xFFFF, sum=0
2866 09:53:21.561799 14, 0x0, sum=1
2867 09:53:21.564627 15, 0x0, sum=2
2868 09:53:21.565187 16, 0x0, sum=3
2869 09:53:21.565539 17, 0x0, sum=4
2870 09:53:21.571400 pattern=2 first_step=14 total pass=5 best_step=16
2871 09:53:21.571987 ==
2872 09:53:21.574695 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2873 09:53:21.578190 fsp= 1, odt_onoff= 1, Byte mode= 0
2874 09:53:21.578761 ==
2875 09:53:21.584506 Start DQ dly to find pass range UseTestEngine =1
2876 09:53:21.587910 x-axis: bit #, y-axis: DQ dly (-127~63)
2877 09:53:21.588422 RX Vref Scan = 1
2878 09:53:21.711261
2879 09:53:21.711977 RX Vref found, early break!
2880 09:53:21.712334
2881 09:53:21.714161 Final RX Vref 13, apply to both rank0 and 1
2882 09:53:21.717408 ==
2883 09:53:21.721390 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2884 09:53:21.724575 fsp= 1, odt_onoff= 1, Byte mode= 0
2885 09:53:21.725091 ==
2886 09:53:21.725428 DQS Delay:
2887 09:53:21.727698 DQS0 = 0, DQS1 = 0
2888 09:53:21.728164 DQM Delay:
2889 09:53:21.730909 DQM0 = 20, DQM1 = 18
2890 09:53:21.731334 DQ Delay:
2891 09:53:21.734472 DQ0 =23, DQ1 =23, DQ2 =17, DQ3 =15
2892 09:53:21.737857 DQ4 =19, DQ5 =24, DQ6 =24, DQ7 =19
2893 09:53:21.741187 DQ8 =18, DQ9 =18, DQ10 =17, DQ11 =19
2894 09:53:21.744239 DQ12 =21, DQ13 =19, DQ14 =20, DQ15 =14
2895 09:53:21.744673
2896 09:53:21.745005
2897 09:53:21.745306
2898 09:53:21.747552 [DramC_TX_OE_Calibration] TA2
2899 09:53:21.751136 Original DQ_B0 (3 6) =30, OEN = 27
2900 09:53:21.754434 Original DQ_B1 (3 6) =30, OEN = 27
2901 09:53:21.757840 23, 0x0, End_B0=23 End_B1=23
2902 09:53:21.758393 24, 0x0, End_B0=24 End_B1=24
2903 09:53:21.761448 25, 0x0, End_B0=25 End_B1=25
2904 09:53:21.764188 26, 0x0, End_B0=26 End_B1=26
2905 09:53:21.767636 27, 0x0, End_B0=27 End_B1=27
2906 09:53:21.768070 28, 0x0, End_B0=28 End_B1=28
2907 09:53:21.770964 29, 0x0, End_B0=29 End_B1=29
2908 09:53:21.774727 30, 0x0, End_B0=30 End_B1=30
2909 09:53:21.777927 31, 0xFFFF, End_B0=30 End_B1=30
2910 09:53:21.781449 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2911 09:53:21.788012 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2912 09:53:21.788525
2913 09:53:21.788856
2914 09:53:21.791371 Write Rank0 MR23 =0x3f
2915 09:53:21.791881 [DQSOSC]
2916 09:53:21.797943 [DQSOSCAuto] RK0, (LSB)MR18= 0xa3, (MSB)MR19= 0x3, tDQSOscB0 = 338 ps tDQSOscB1 = 0 ps
2917 09:53:21.804525 CH1_RK0: MR19=0x3, MR18=0xA3, DQSOSC=338, MR23=63, INC=21, DEC=32
2918 09:53:21.807866 Write Rank0 MR23 =0x3f
2919 09:53:21.808379 [DQSOSC]
2920 09:53:21.814484 [DQSOSCAuto] RK0, (LSB)MR18= 0xa2, (MSB)MR19= 0x3, tDQSOscB0 = 338 ps tDQSOscB1 = 0 ps
2921 09:53:21.817771 CH1 RK0: MR19=3, MR18=A2
2922 09:53:21.821273 [RankSwap] Rank num 2, (Multi 1), Rank 1
2923 09:53:21.824677 Write Rank0 MR2 =0xad
2924 09:53:21.825189 [Write Leveling]
2925 09:53:21.827698 delay byte0 byte1 byte2 byte3
2926 09:53:21.828123
2927 09:53:21.828450 10 0 0
2928 09:53:21.831049 11 0 0
2929 09:53:21.831659 12 0 0
2930 09:53:21.834595 13 0 0
2931 09:53:21.835026 14 0 0
2932 09:53:21.835361 15 0 0
2933 09:53:21.837786 16 0 0
2934 09:53:21.838255 17 0 0
2935 09:53:21.841055 18 0 0
2936 09:53:21.841506 19 0 0
2937 09:53:21.844396 20 0 0
2938 09:53:21.844836 21 0 0
2939 09:53:21.845207 22 0 0
2940 09:53:21.848086 23 0 0
2941 09:53:21.848613 24 0 0
2942 09:53:21.851376 25 0 0
2943 09:53:21.851904 26 0 0
2944 09:53:21.852247 27 0 0
2945 09:53:21.854690 28 0 0
2946 09:53:21.855127 29 0 0
2947 09:53:21.858106 30 0 ff
2948 09:53:21.858678 31 0 ff
2949 09:53:21.861712 32 0 ff
2950 09:53:21.862275 33 0 ff
2951 09:53:21.862627 34 0 ff
2952 09:53:21.864719 35 0 ff
2953 09:53:21.865154 36 0 ff
2954 09:53:21.868043 37 ff ff
2955 09:53:21.868482 38 ff ff
2956 09:53:21.871595 39 ff ff
2957 09:53:21.872240 40 ff ff
2958 09:53:21.874903 41 ff ff
2959 09:53:21.875338 42 ff ff
2960 09:53:21.878484 43 ff ff
2961 09:53:21.881955 pass bytecount = 0xff (0xff: all bytes pass)
2962 09:53:21.882515
2963 09:53:21.882857 DQS0 dly: 37
2964 09:53:21.883168 DQS1 dly: 30
2965 09:53:21.885033 Write Rank0 MR2 =0x2d
2966 09:53:21.888370 [RankSwap] Rank num 2, (Multi 1), Rank 0
2967 09:53:21.891785 Write Rank1 MR1 =0xd6
2968 09:53:21.892300 [Gating]
2969 09:53:21.892634 ==
2970 09:53:21.898657 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2971 09:53:21.901674 fsp= 1, odt_onoff= 1, Byte mode= 0
2972 09:53:21.902193 ==
2973 09:53:21.905144 3 1 0 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
2974 09:53:21.908355 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2975 09:53:21.911936 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2976 09:53:21.918577 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2977 09:53:21.921802 3 1 16 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2978 09:53:21.925102 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2979 09:53:21.931672 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2980 09:53:21.934997 3 1 28 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2981 09:53:21.938334 3 2 0 |908 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2982 09:53:21.945110 3 2 4 |3d3d f0f |(11 11)(11 11) |(1 1)(0 0)| 0
2983 09:53:21.948308 3 2 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2984 09:53:21.951496 3 2 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2985 09:53:21.958277 3 2 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2986 09:53:21.961732 3 2 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2987 09:53:21.965047 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2988 09:53:21.968363 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2989 09:53:21.974868 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2990 09:53:21.978138 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2991 09:53:21.981861 3 3 8 |201f 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2992 09:53:21.988774 [Byte 0] Lead/lag Transition tap number (1)
2993 09:53:21.991829 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2994 09:53:21.995048 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2995 09:53:21.998258 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2996 09:53:22.005497 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2997 09:53:22.008725 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2998 09:53:22.011630 3 4 0 |908 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2999 09:53:22.018337 3 4 4 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
3000 09:53:22.021482 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3001 09:53:22.025057 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3002 09:53:22.031483 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3003 09:53:22.035165 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3004 09:53:22.038274 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3005 09:53:22.044886 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3006 09:53:22.048602 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3007 09:53:22.051806 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3008 09:53:22.055005 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3009 09:53:22.061824 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3010 09:53:22.064967 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3011 09:53:22.068279 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3012 09:53:22.074958 [Byte 0] Lead/lag falling Transition (3, 5, 20)
3013 09:53:22.078322 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3014 09:53:22.081529 [Byte 0] Lead/lag Transition tap number (2)
3015 09:53:22.085129 [Byte 1] Lead/lag falling Transition (3, 5, 24)
3016 09:53:22.091813 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3017 09:53:22.095018 3 6 0 |404 3e3d |(11 11)(11 11) |(0 0)(1 0)| 0
3018 09:53:22.098661 [Byte 1] Lead/lag Transition tap number (3)
3019 09:53:22.101810 3 6 4 |4646 404 |(0 0)(11 11) |(0 0)(0 0)| 0
3020 09:53:22.105246 [Byte 0]First pass (3, 6, 4)
3021 09:53:22.108694 3 6 8 |4646 4646 |(0 0)(10 10) |(0 0)(0 0)| 0
3022 09:53:22.112014 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3023 09:53:22.115331 [Byte 1]First pass (3, 6, 12)
3024 09:53:22.118717 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3025 09:53:22.125459 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3026 09:53:22.128908 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3027 09:53:22.132029 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3028 09:53:22.135390 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3029 09:53:22.138819 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3030 09:53:22.145006 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3031 09:53:22.148804 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3032 09:53:22.151936 All bytes gating window > 1UI, Early break!
3033 09:53:22.152367
3034 09:53:22.155400 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 24)
3035 09:53:22.155838
3036 09:53:22.158558 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 30)
3037 09:53:22.158990
3038 09:53:22.159394
3039 09:53:22.162048
3040 09:53:22.165116 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 24)
3041 09:53:22.165550
3042 09:53:22.168963 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
3043 09:53:22.169480
3044 09:53:22.169815
3045 09:53:22.171887 Write Rank1 MR1 =0x56
3046 09:53:22.172315
3047 09:53:22.175129 best RODT dly(2T, 0.5T) = (2, 2)
3048 09:53:22.175561
3049 09:53:22.178372 best RODT dly(2T, 0.5T) = (2, 2)
3050 09:53:22.178803 ==
3051 09:53:22.181787 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3052 09:53:22.185114 fsp= 1, odt_onoff= 1, Byte mode= 0
3053 09:53:22.185596 ==
3054 09:53:22.188545 Start DQ dly to find pass range UseTestEngine =0
3055 09:53:22.191639 x-axis: bit #, y-axis: DQ dly (-127~63)
3056 09:53:22.194936 RX Vref Scan = 0
3057 09:53:22.198323 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3058 09:53:22.201584 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3059 09:53:22.205001 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3060 09:53:22.205444 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3061 09:53:22.208417 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3062 09:53:22.211677 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3063 09:53:22.215018 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3064 09:53:22.218285 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3065 09:53:22.221842 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3066 09:53:22.224902 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3067 09:53:22.228834 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3068 09:53:22.229356 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3069 09:53:22.231966 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3070 09:53:22.235486 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3071 09:53:22.238662 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3072 09:53:22.241678 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3073 09:53:22.245400 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3074 09:53:22.248556 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3075 09:53:22.251940 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3076 09:53:22.252465 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3077 09:53:22.255293 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3078 09:53:22.258695 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3079 09:53:22.261992 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3080 09:53:22.265491 -3, [0] xxxoxxxx xxxxxxxx [MSB]
3081 09:53:22.268771 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3082 09:53:22.271856 -1, [0] xxooxxxx xxxxxxxo [MSB]
3083 09:53:22.272295 0, [0] xxooxxxx oxoxxxxo [MSB]
3084 09:53:22.275513 1, [0] xxooxxxo oooxxxxo [MSB]
3085 09:53:22.278571 2, [0] xxoooxxo oooxxxxo [MSB]
3086 09:53:22.281950 3, [0] xxoooxxo ooooxxoo [MSB]
3087 09:53:22.285118 4, [0] xxoooxxo ooooxooo [MSB]
3088 09:53:22.285555 5, [0] xooooxxo oooooooo [MSB]
3089 09:53:22.288886 6, [0] xooooxoo oooooooo [MSB]
3090 09:53:22.291854 33, [0] oooxoooo oooooooo [MSB]
3091 09:53:22.295234 34, [0] oooxoooo ooooooox [MSB]
3092 09:53:22.298571 35, [0] ooxxoooo ooooooox [MSB]
3093 09:53:22.301901 36, [0] ooxxoooo oxooooox [MSB]
3094 09:53:22.305324 37, [0] ooxxoooo oxxoooox [MSB]
3095 09:53:22.305852 38, [0] ooxxoooo xxxxooox [MSB]
3096 09:53:22.308473 39, [0] ooxxxoox xxxxooxx [MSB]
3097 09:53:22.311745 40, [0] ooxxxoox xxxxoxxx [MSB]
3098 09:53:22.315276 41, [0] ooxxxoox xxxxxxxx [MSB]
3099 09:53:22.318638 42, [0] ooxxxxox xxxxxxxx [MSB]
3100 09:53:22.321826 43, [0] oxxxxxxx xxxxxxxx [MSB]
3101 09:53:22.325475 44, [0] xxxxxxxx xxxxxxxx [MSB]
3102 09:53:22.328556 iDelay=44, Bit 0, Center 25 (7 ~ 43) 37
3103 09:53:22.331929 iDelay=44, Bit 1, Center 23 (5 ~ 42) 38
3104 09:53:22.335568 iDelay=44, Bit 2, Center 16 (-1 ~ 34) 36
3105 09:53:22.338743 iDelay=44, Bit 3, Center 14 (-3 ~ 32) 36
3106 09:53:22.342156 iDelay=44, Bit 4, Center 20 (2 ~ 38) 37
3107 09:53:22.345614 iDelay=44, Bit 5, Center 24 (7 ~ 41) 35
3108 09:53:22.349049 iDelay=44, Bit 6, Center 24 (6 ~ 42) 37
3109 09:53:22.352141 iDelay=44, Bit 7, Center 19 (1 ~ 38) 38
3110 09:53:22.355435 iDelay=44, Bit 8, Center 18 (0 ~ 37) 38
3111 09:53:22.358815 iDelay=44, Bit 9, Center 18 (1 ~ 35) 35
3112 09:53:22.362456 iDelay=44, Bit 10, Center 18 (0 ~ 36) 37
3113 09:53:22.365631 iDelay=44, Bit 11, Center 20 (3 ~ 37) 35
3114 09:53:22.368919 iDelay=44, Bit 12, Center 22 (5 ~ 40) 36
3115 09:53:22.372243 iDelay=44, Bit 13, Center 21 (4 ~ 39) 36
3116 09:53:22.378884 iDelay=44, Bit 14, Center 20 (3 ~ 38) 36
3117 09:53:22.382418 iDelay=44, Bit 15, Center 15 (-2 ~ 33) 36
3118 09:53:22.383111 ==
3119 09:53:22.385560 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3120 09:53:22.388850 fsp= 1, odt_onoff= 1, Byte mode= 0
3121 09:53:22.389364 ==
3122 09:53:22.392378 DQS Delay:
3123 09:53:22.392895 DQS0 = 0, DQS1 = 0
3124 09:53:22.393228 DQM Delay:
3125 09:53:22.395222 DQM0 = 20, DQM1 = 19
3126 09:53:22.395650 DQ Delay:
3127 09:53:22.398976 DQ0 =25, DQ1 =23, DQ2 =16, DQ3 =14
3128 09:53:22.402493 DQ4 =20, DQ5 =24, DQ6 =24, DQ7 =19
3129 09:53:22.405520 DQ8 =18, DQ9 =18, DQ10 =18, DQ11 =20
3130 09:53:22.409271 DQ12 =22, DQ13 =21, DQ14 =20, DQ15 =15
3131 09:53:22.409787
3132 09:53:22.410118
3133 09:53:22.412389 DramC Write-DBI off
3134 09:53:22.412902 ==
3135 09:53:22.415648 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3136 09:53:22.418837 fsp= 1, odt_onoff= 1, Byte mode= 0
3137 09:53:22.419270 ==
3138 09:53:22.426034 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3139 09:53:22.426605
3140 09:53:22.426943 Begin, DQ Scan Range 926~1182
3141 09:53:22.428772
3142 09:53:22.429195
3143 09:53:22.429524 TX Vref Scan disable
3144 09:53:22.432283 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3145 09:53:22.435786 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3146 09:53:22.439199 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3147 09:53:22.442833 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3148 09:53:22.445881 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3149 09:53:22.452646 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3150 09:53:22.455972 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3151 09:53:22.459151 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3152 09:53:22.462697 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3153 09:53:22.466083 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3154 09:53:22.469515 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3155 09:53:22.473020 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3156 09:53:22.475955 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3157 09:53:22.479301 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3158 09:53:22.483104 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3159 09:53:22.485948 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3160 09:53:22.489487 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3161 09:53:22.492902 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3162 09:53:22.495999 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3163 09:53:22.499288 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3164 09:53:22.502916 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3165 09:53:22.505986 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3166 09:53:22.509189 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3167 09:53:22.516097 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3168 09:53:22.519310 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3169 09:53:22.522682 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3170 09:53:22.525850 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3171 09:53:22.529342 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3172 09:53:22.532534 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3173 09:53:22.536059 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3174 09:53:22.539297 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3175 09:53:22.542797 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3176 09:53:22.546309 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3177 09:53:22.549351 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3178 09:53:22.552790 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3179 09:53:22.556228 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3180 09:53:22.559683 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3181 09:53:22.562927 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3182 09:53:22.565994 964 |3 6 4|[0] xxxxxxxx xxxxxxxo [MSB]
3183 09:53:22.569575 965 |3 6 5|[0] xxxxxxxx xxxxxxxo [MSB]
3184 09:53:22.573122 966 |3 6 6|[0] xxxxxxxx ooxxxxxo [MSB]
3185 09:53:22.575839 967 |3 6 7|[0] xxxxxxxx oooxxxxo [MSB]
3186 09:53:22.579435 968 |3 6 8|[0] xxxxxxxx oooxxxoo [MSB]
3187 09:53:22.583056 969 |3 6 9|[0] xxxxxxxx ooooxooo [MSB]
3188 09:53:22.589662 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB]
3189 09:53:22.593042 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
3190 09:53:22.596387 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
3191 09:53:22.599751 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
3192 09:53:22.602722 974 |3 6 14|[0] xxooxxxx oooooooo [MSB]
3193 09:53:22.606063 975 |3 6 15|[0] xxoooxxo oooooooo [MSB]
3194 09:53:22.609151 976 |3 6 16|[0] xoooooxo oooooooo [MSB]
3195 09:53:22.616010 989 |3 6 29|[0] oooooooo ooooooox [MSB]
3196 09:53:22.619181 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
3197 09:53:22.622847 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3198 09:53:22.625992 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3199 09:53:22.629481 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3200 09:53:22.632841 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3201 09:53:22.635945 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3202 09:53:22.639305 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3203 09:53:22.642807 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
3204 09:53:22.646001 998 |3 6 38|[0] ooxxxoox xxxxxxxx [MSB]
3205 09:53:22.649225 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
3206 09:53:22.652877 Byte0, DQ PI dly=986, DQM PI dly= 986
3207 09:53:22.656082 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
3208 09:53:22.656635
3209 09:53:22.662577 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
3210 09:53:22.663058
3211 09:53:22.665981 Byte1, DQ PI dly=977, DQM PI dly= 977
3212 09:53:22.669582 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
3213 09:53:22.670096
3214 09:53:22.675971 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
3215 09:53:22.676475
3216 09:53:22.676810 ==
3217 09:53:22.679208 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3218 09:53:22.682909 fsp= 1, odt_onoff= 1, Byte mode= 0
3219 09:53:22.683424 ==
3220 09:53:22.686322 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3221 09:53:22.686834
3222 09:53:22.689636 Begin, DQ Scan Range 953~1017
3223 09:53:22.692608 Write Rank1 MR14 =0x0
3224 09:53:22.701399
3225 09:53:22.701910 CH=1, VrefRange= 0, VrefLevel = 0
3226 09:53:22.707834 TX Bit0 (978~998) 21 988, Bit8 (969~986) 18 977,
3227 09:53:22.711319 TX Bit1 (977~997) 21 987, Bit9 (969~985) 17 977,
3228 09:53:22.717671 TX Bit2 (975~992) 18 983, Bit10 (970~985) 16 977,
3229 09:53:22.721166 TX Bit3 (975~991) 17 983, Bit11 (971~988) 18 979,
3230 09:53:22.724845 TX Bit4 (976~994) 19 985, Bit12 (971~990) 20 980,
3231 09:53:22.731140 TX Bit5 (978~998) 21 988, Bit13 (970~986) 17 978,
3232 09:53:22.734908 TX Bit6 (978~998) 21 988, Bit14 (970~986) 17 978,
3233 09:53:22.738336 TX Bit7 (977~995) 19 986, Bit15 (966~985) 20 975,
3234 09:53:22.738872
3235 09:53:22.741666 Write Rank1 MR14 =0x2
3236 09:53:22.750198
3237 09:53:22.750738 CH=1, VrefRange= 0, VrefLevel = 2
3238 09:53:22.757390 TX Bit0 (977~998) 22 987, Bit8 (969~987) 19 978,
3239 09:53:22.760755 TX Bit1 (977~997) 21 987, Bit9 (969~986) 18 977,
3240 09:53:22.766873 TX Bit2 (975~992) 18 983, Bit10 (970~985) 16 977,
3241 09:53:22.770496 TX Bit3 (974~991) 18 982, Bit11 (970~989) 20 979,
3242 09:53:22.773671 TX Bit4 (976~995) 20 985, Bit12 (971~990) 20 980,
3243 09:53:22.780299 TX Bit5 (977~998) 22 987, Bit13 (970~987) 18 978,
3244 09:53:22.783641 TX Bit6 (977~998) 22 987, Bit14 (970~987) 18 978,
3245 09:53:22.787013 TX Bit7 (977~995) 19 986, Bit15 (966~985) 20 975,
3246 09:53:22.787534
3247 09:53:22.790330 Write Rank1 MR14 =0x4
3248 09:53:22.799608
3249 09:53:22.800125 CH=1, VrefRange= 0, VrefLevel = 4
3250 09:53:22.806539 TX Bit0 (977~999) 23 988, Bit8 (968~987) 20 977,
3251 09:53:22.809808 TX Bit1 (976~997) 22 986, Bit9 (968~986) 19 977,
3252 09:53:22.816170 TX Bit2 (975~993) 19 984, Bit10 (969~986) 18 977,
3253 09:53:22.819261 TX Bit3 (974~992) 19 983, Bit11 (970~989) 20 979,
3254 09:53:22.822973 TX Bit4 (976~996) 21 986, Bit12 (971~990) 20 980,
3255 09:53:22.829648 TX Bit5 (977~998) 22 987, Bit13 (970~987) 18 978,
3256 09:53:22.833300 TX Bit6 (977~999) 23 988, Bit14 (970~987) 18 978,
3257 09:53:22.836548 TX Bit7 (977~996) 20 986, Bit15 (965~985) 21 975,
3258 09:53:22.837063
3259 09:53:22.839292 Write Rank1 MR14 =0x6
3260 09:53:22.849167
3261 09:53:22.849678 CH=1, VrefRange= 0, VrefLevel = 6
3262 09:53:22.855420 TX Bit0 (977~998) 22 987, Bit8 (968~988) 21 978,
3263 09:53:22.859089 TX Bit1 (976~998) 23 987, Bit9 (968~987) 20 977,
3264 09:53:22.862373 TX Bit2 (974~993) 20 983, Bit10 (969~986) 18 977,
3265 09:53:22.869061 TX Bit3 (974~992) 19 983, Bit11 (970~990) 21 980,
3266 09:53:22.872248 TX Bit4 (976~996) 21 986, Bit12 (970~991) 22 980,
3267 09:53:22.879167 TX Bit5 (977~998) 22 987, Bit13 (970~988) 19 979,
3268 09:53:22.882735 TX Bit6 (977~999) 23 988, Bit14 (970~988) 19 979,
3269 09:53:22.885698 TX Bit7 (976~996) 21 986, Bit15 (965~985) 21 975,
3270 09:53:22.886445
3271 09:53:22.888824 Write Rank1 MR14 =0x8
3272 09:53:22.898150
3273 09:53:22.898707 CH=1, VrefRange= 0, VrefLevel = 8
3274 09:53:22.905048 TX Bit0 (977~999) 23 988, Bit8 (968~988) 21 978,
3275 09:53:22.908184 TX Bit1 (976~998) 23 987, Bit9 (967~988) 22 977,
3276 09:53:22.914858 TX Bit2 (974~994) 21 984, Bit10 (969~987) 19 978,
3277 09:53:22.918279 TX Bit3 (973~993) 21 983, Bit11 (970~990) 21 980,
3278 09:53:22.921446 TX Bit4 (976~996) 21 986, Bit12 (970~991) 22 980,
3279 09:53:22.928472 TX Bit5 (977~998) 22 987, Bit13 (970~990) 21 980,
3280 09:53:22.931490 TX Bit6 (977~999) 23 988, Bit14 (970~989) 20 979,
3281 09:53:22.934820 TX Bit7 (976~997) 22 986, Bit15 (964~986) 23 975,
3282 09:53:22.935254
3283 09:53:22.938475 Write Rank1 MR14 =0xa
3284 09:53:22.947254
3285 09:53:22.950827 CH=1, VrefRange= 0, VrefLevel = 10
3286 09:53:22.954034 TX Bit0 (977~999) 23 988, Bit8 (967~989) 23 978,
3287 09:53:22.957937 TX Bit1 (976~998) 23 987, Bit9 (967~989) 23 978,
3288 09:53:22.964023 TX Bit2 (974~994) 21 984, Bit10 (969~988) 20 978,
3289 09:53:22.967351 TX Bit3 (973~994) 22 983, Bit11 (970~991) 22 980,
3290 09:53:22.970581 TX Bit4 (975~997) 23 986, Bit12 (970~991) 22 980,
3291 09:53:22.976987 TX Bit5 (977~999) 23 988, Bit13 (970~990) 21 980,
3292 09:53:22.981087 TX Bit6 (977~999) 23 988, Bit14 (969~990) 22 979,
3293 09:53:22.983892 TX Bit7 (976~997) 22 986, Bit15 (964~986) 23 975,
3294 09:53:22.987122
3295 09:53:22.987551 Write Rank1 MR14 =0xc
3296 09:53:22.997119
3297 09:53:23.000402 CH=1, VrefRange= 0, VrefLevel = 12
3298 09:53:23.003250 TX Bit0 (977~1000) 24 988, Bit8 (967~990) 24 978,
3299 09:53:23.006658 TX Bit1 (976~998) 23 987, Bit9 (967~989) 23 978,
3300 09:53:23.013512 TX Bit2 (973~995) 23 984, Bit10 (968~989) 22 978,
3301 09:53:23.016874 TX Bit3 (973~994) 22 983, Bit11 (969~991) 23 980,
3302 09:53:23.020008 TX Bit4 (975~997) 23 986, Bit12 (970~991) 22 980,
3303 09:53:23.027131 TX Bit5 (977~999) 23 988, Bit13 (969~990) 22 979,
3304 09:53:23.030024 TX Bit6 (977~1000) 24 988, Bit14 (969~990) 22 979,
3305 09:53:23.033269 TX Bit7 (976~997) 22 986, Bit15 (964~987) 24 975,
3306 09:53:23.036716
3307 09:53:23.037234 Write Rank1 MR14 =0xe
3308 09:53:23.046712
3309 09:53:23.050315 CH=1, VrefRange= 0, VrefLevel = 14
3310 09:53:23.053361 TX Bit0 (977~1000) 24 988, Bit8 (966~990) 25 978,
3311 09:53:23.056855 TX Bit1 (976~998) 23 987, Bit9 (966~990) 25 978,
3312 09:53:23.063538 TX Bit2 (973~996) 24 984, Bit10 (968~989) 22 978,
3313 09:53:23.066957 TX Bit3 (972~995) 24 983, Bit11 (969~991) 23 980,
3314 09:53:23.070151 TX Bit4 (975~997) 23 986, Bit12 (970~992) 23 981,
3315 09:53:23.076832 TX Bit5 (976~999) 24 987, Bit13 (969~990) 22 979,
3316 09:53:23.080139 TX Bit6 (977~1000) 24 988, Bit14 (969~991) 23 980,
3317 09:53:23.083712 TX Bit7 (976~997) 22 986, Bit15 (964~988) 25 976,
3318 09:53:23.084236
3319 09:53:23.086969 Write Rank1 MR14 =0x10
3320 09:53:23.096756
3321 09:53:23.100149 CH=1, VrefRange= 0, VrefLevel = 16
3322 09:53:23.103491 TX Bit0 (977~1001) 25 989, Bit8 (966~990) 25 978,
3323 09:53:23.106575 TX Bit1 (976~998) 23 987, Bit9 (966~990) 25 978,
3324 09:53:23.113088 TX Bit2 (973~996) 24 984, Bit10 (968~990) 23 979,
3325 09:53:23.116774 TX Bit3 (971~996) 26 983, Bit11 (969~992) 24 980,
3326 09:53:23.119987 TX Bit4 (975~997) 23 986, Bit12 (969~992) 24 980,
3327 09:53:23.126571 TX Bit5 (976~1000) 25 988, Bit13 (969~991) 23 980,
3328 09:53:23.129893 TX Bit6 (976~1000) 25 988, Bit14 (968~991) 24 979,
3329 09:53:23.133863 TX Bit7 (975~998) 24 986, Bit15 (963~988) 26 975,
3330 09:53:23.136314
3331 09:53:23.136740 Write Rank1 MR14 =0x12
3332 09:53:23.146422
3333 09:53:23.149872 CH=1, VrefRange= 0, VrefLevel = 18
3334 09:53:23.153458 TX Bit0 (976~1001) 26 988, Bit8 (966~991) 26 978,
3335 09:53:23.156294 TX Bit1 (975~999) 25 987, Bit9 (965~990) 26 977,
3336 09:53:23.163149 TX Bit2 (972~997) 26 984, Bit10 (967~990) 24 978,
3337 09:53:23.166595 TX Bit3 (971~996) 26 983, Bit11 (969~992) 24 980,
3338 09:53:23.170092 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3339 09:53:23.176553 TX Bit5 (976~1000) 25 988, Bit13 (968~991) 24 979,
3340 09:53:23.179872 TX Bit6 (976~1001) 26 988, Bit14 (968~991) 24 979,
3341 09:53:23.186563 TX Bit7 (975~998) 24 986, Bit15 (963~989) 27 976,
3342 09:53:23.187082
3343 09:53:23.187420 Write Rank1 MR14 =0x14
3344 09:53:23.196412
3345 09:53:23.199940 CH=1, VrefRange= 0, VrefLevel = 20
3346 09:53:23.203472 TX Bit0 (976~1001) 26 988, Bit8 (965~991) 27 978,
3347 09:53:23.206748 TX Bit1 (975~999) 25 987, Bit9 (965~991) 27 978,
3348 09:53:23.213067 TX Bit2 (972~997) 26 984, Bit10 (966~991) 26 978,
3349 09:53:23.217076 TX Bit3 (970~996) 27 983, Bit11 (968~992) 25 980,
3350 09:53:23.219744 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3351 09:53:23.226875 TX Bit5 (976~1000) 25 988, Bit13 (968~991) 24 979,
3352 09:53:23.229923 TX Bit6 (976~1001) 26 988, Bit14 (968~991) 24 979,
3353 09:53:23.233322 TX Bit7 (975~998) 24 986, Bit15 (963~990) 28 976,
3354 09:53:23.233750
3355 09:53:23.236459 Write Rank1 MR14 =0x16
3356 09:53:23.246492
3357 09:53:23.249948 CH=1, VrefRange= 0, VrefLevel = 22
3358 09:53:23.253354 TX Bit0 (976~1001) 26 988, Bit8 (965~991) 27 978,
3359 09:53:23.256728 TX Bit1 (975~999) 25 987, Bit9 (965~991) 27 978,
3360 09:53:23.263336 TX Bit2 (972~997) 26 984, Bit10 (966~991) 26 978,
3361 09:53:23.266554 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3362 09:53:23.269872 TX Bit4 (973~998) 26 985, Bit12 (969~992) 24 980,
3363 09:53:23.276690 TX Bit5 (976~1001) 26 988, Bit13 (968~991) 24 979,
3364 09:53:23.280003 TX Bit6 (976~1001) 26 988, Bit14 (967~991) 25 979,
3365 09:53:23.283243 TX Bit7 (975~998) 24 986, Bit15 (963~990) 28 976,
3366 09:53:23.286786
3367 09:53:23.287298 Write Rank1 MR14 =0x18
3368 09:53:23.296549
3369 09:53:23.299885 CH=1, VrefRange= 0, VrefLevel = 24
3370 09:53:23.303475 TX Bit0 (976~1001) 26 988, Bit8 (965~991) 27 978,
3371 09:53:23.306542 TX Bit1 (975~999) 25 987, Bit9 (964~991) 28 977,
3372 09:53:23.313028 TX Bit2 (971~997) 27 984, Bit10 (965~991) 27 978,
3373 09:53:23.316514 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3374 09:53:23.319926 TX Bit4 (973~998) 26 985, Bit12 (969~992) 24 980,
3375 09:53:23.326761 TX Bit5 (976~1001) 26 988, Bit13 (967~991) 25 979,
3376 09:53:23.329620 TX Bit6 (976~1001) 26 988, Bit14 (967~991) 25 979,
3377 09:53:23.333195 TX Bit7 (974~998) 25 986, Bit15 (963~989) 27 976,
3378 09:53:23.336234
3379 09:53:23.336539 Write Rank1 MR14 =0x1a
3380 09:53:23.346283
3381 09:53:23.349559 CH=1, VrefRange= 0, VrefLevel = 26
3382 09:53:23.352950 TX Bit0 (976~1001) 26 988, Bit8 (965~991) 27 978,
3383 09:53:23.356202 TX Bit1 (975~999) 25 987, Bit9 (964~991) 28 977,
3384 09:53:23.363221 TX Bit2 (971~997) 27 984, Bit10 (965~991) 27 978,
3385 09:53:23.366491 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3386 09:53:23.369752 TX Bit4 (973~998) 26 985, Bit12 (969~992) 24 980,
3387 09:53:23.376434 TX Bit5 (976~1001) 26 988, Bit13 (967~991) 25 979,
3388 09:53:23.380003 TX Bit6 (976~1001) 26 988, Bit14 (967~991) 25 979,
3389 09:53:23.383197 TX Bit7 (974~998) 25 986, Bit15 (963~989) 27 976,
3390 09:53:23.386540
3391 09:53:23.386925 Write Rank1 MR14 =0x1c
3392 09:53:23.396822
3393 09:53:23.400263 CH=1, VrefRange= 0, VrefLevel = 28
3394 09:53:23.403284 TX Bit0 (976~1001) 26 988, Bit8 (965~991) 27 978,
3395 09:53:23.406778 TX Bit1 (975~999) 25 987, Bit9 (964~991) 28 977,
3396 09:53:23.413390 TX Bit2 (971~997) 27 984, Bit10 (965~991) 27 978,
3397 09:53:23.416382 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3398 09:53:23.419841 TX Bit4 (973~998) 26 985, Bit12 (969~992) 24 980,
3399 09:53:23.426622 TX Bit5 (976~1001) 26 988, Bit13 (967~991) 25 979,
3400 09:53:23.429725 TX Bit6 (976~1001) 26 988, Bit14 (967~991) 25 979,
3401 09:53:23.433214 TX Bit7 (974~998) 25 986, Bit15 (963~989) 27 976,
3402 09:53:23.436622
3403 09:53:23.437129 Write Rank1 MR14 =0x1e
3404 09:53:23.446598
3405 09:53:23.447106 CH=1, VrefRange= 0, VrefLevel = 30
3406 09:53:23.453162 TX Bit0 (976~1001) 26 988, Bit8 (965~991) 27 978,
3407 09:53:23.456568 TX Bit1 (975~999) 25 987, Bit9 (964~991) 28 977,
3408 09:53:23.463010 TX Bit2 (971~997) 27 984, Bit10 (965~991) 27 978,
3409 09:53:23.466239 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3410 09:53:23.469540 TX Bit4 (973~998) 26 985, Bit12 (969~992) 24 980,
3411 09:53:23.476662 TX Bit5 (976~1001) 26 988, Bit13 (967~991) 25 979,
3412 09:53:23.479796 TX Bit6 (976~1001) 26 988, Bit14 (967~991) 25 979,
3413 09:53:23.483085 TX Bit7 (974~998) 25 986, Bit15 (963~989) 27 976,
3414 09:53:23.486567
3415 09:53:23.486986
3416 09:53:23.489856 TX Vref found, early break! 388< 396
3417 09:53:23.493064 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
3418 09:53:23.496561 u1DelayCellOfst[0]=6 cells (5 PI)
3419 09:53:23.499874 u1DelayCellOfst[1]=5 cells (4 PI)
3420 09:53:23.503324 u1DelayCellOfst[2]=1 cells (1 PI)
3421 09:53:23.506433 u1DelayCellOfst[3]=0 cells (0 PI)
3422 09:53:23.506858 u1DelayCellOfst[4]=2 cells (2 PI)
3423 09:53:23.509633 u1DelayCellOfst[5]=6 cells (5 PI)
3424 09:53:23.513363 u1DelayCellOfst[6]=6 cells (5 PI)
3425 09:53:23.516530 u1DelayCellOfst[7]=3 cells (3 PI)
3426 09:53:23.519809 Byte0, DQ PI dly=983, DQM PI dly= 985
3427 09:53:23.526412 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
3428 09:53:23.526842
3429 09:53:23.529527 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
3430 09:53:23.529987
3431 09:53:23.533178 u1DelayCellOfst[8]=2 cells (2 PI)
3432 09:53:23.536818 u1DelayCellOfst[9]=1 cells (1 PI)
3433 09:53:23.539773 u1DelayCellOfst[10]=2 cells (2 PI)
3434 09:53:23.543137 u1DelayCellOfst[11]=5 cells (4 PI)
3435 09:53:23.543618 u1DelayCellOfst[12]=5 cells (4 PI)
3436 09:53:23.546535 u1DelayCellOfst[13]=3 cells (3 PI)
3437 09:53:23.549873 u1DelayCellOfst[14]=3 cells (3 PI)
3438 09:53:23.553395 u1DelayCellOfst[15]=0 cells (0 PI)
3439 09:53:23.556503 Byte1, DQ PI dly=976, DQM PI dly= 978
3440 09:53:23.563260 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
3441 09:53:23.563778
3442 09:53:23.566897 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
3443 09:53:23.567470
3444 09:53:23.569961 Write Rank1 MR14 =0x18
3445 09:53:23.570515
3446 09:53:23.570851 Final TX Range 0 Vref 24
3447 09:53:23.571163
3448 09:53:23.576408 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3449 09:53:23.576937
3450 09:53:23.583325 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3451 09:53:23.589970 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3452 09:53:23.599733 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3453 09:53:23.600253 Write Rank1 MR3 =0xb0
3454 09:53:23.603363 DramC Write-DBI on
3455 09:53:23.603877 ==
3456 09:53:23.606810 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3457 09:53:23.609937 fsp= 1, odt_onoff= 1, Byte mode= 0
3458 09:53:23.610498 ==
3459 09:53:23.616484 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3460 09:53:23.617002
3461 09:53:23.617342 Begin, DQ Scan Range 698~762
3462 09:53:23.617656
3463 09:53:23.617949
3464 09:53:23.619626 TX Vref Scan disable
3465 09:53:23.622931 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3466 09:53:23.626523 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3467 09:53:23.629740 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3468 09:53:23.632882 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3469 09:53:23.636424 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3470 09:53:23.639988 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3471 09:53:23.646205 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3472 09:53:23.649675 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3473 09:53:23.652643 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3474 09:53:23.656228 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
3475 09:53:23.659793 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
3476 09:53:23.663018 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
3477 09:53:23.666143 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
3478 09:53:23.669301 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
3479 09:53:23.672638 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3480 09:53:23.676656 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3481 09:53:23.679225 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3482 09:53:23.682947 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3483 09:53:23.686318 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3484 09:53:23.694452 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
3485 09:53:23.697981 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3486 09:53:23.701278 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3487 09:53:23.704297 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3488 09:53:23.708112 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3489 09:53:23.711149 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3490 09:53:23.714660 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3491 09:53:23.717971 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3492 09:53:23.721421 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
3493 09:53:23.724998 Byte0, DQ PI dly=730, DQM PI dly= 730
3494 09:53:23.728078 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
3495 09:53:23.728606
3496 09:53:23.734330 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
3497 09:53:23.734762
3498 09:53:23.737845 Byte1, DQ PI dly=721, DQM PI dly= 721
3499 09:53:23.741040 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 17)
3500 09:53:23.741480
3501 09:53:23.744592 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 17)
3502 09:53:23.745109
3503 09:53:23.751248 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3504 09:53:23.758103 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3505 09:53:23.764744 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3506 09:53:23.767881 Write Rank1 MR3 =0x30
3507 09:53:23.771142 DramC Write-DBI off
3508 09:53:23.771570
3509 09:53:23.771905 [DATLAT]
3510 09:53:23.774872 Freq=1600, CH1 RK1, use_rxtx_scan=0
3511 09:53:23.775391
3512 09:53:23.775728 DATLAT Default: 0x10
3513 09:53:23.777930 7, 0xFFFF, sum=0
3514 09:53:23.778467 8, 0xFFFF, sum=0
3515 09:53:23.781677 9, 0xFFFF, sum=0
3516 09:53:23.782306 10, 0xFFFF, sum=0
3517 09:53:23.784693 11, 0xFFFF, sum=0
3518 09:53:23.785216 12, 0xFFFF, sum=0
3519 09:53:23.788041 13, 0xFFFF, sum=0
3520 09:53:23.788563 14, 0x0, sum=1
3521 09:53:23.791295 15, 0x0, sum=2
3522 09:53:23.791813 16, 0x0, sum=3
3523 09:53:23.792163 17, 0x0, sum=4
3524 09:53:23.798173 pattern=2 first_step=14 total pass=5 best_step=16
3525 09:53:23.798722 ==
3526 09:53:23.801175 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3527 09:53:23.804730 fsp= 1, odt_onoff= 1, Byte mode= 0
3528 09:53:23.805251 ==
3529 09:53:23.811515 Start DQ dly to find pass range UseTestEngine =1
3530 09:53:23.815007 x-axis: bit #, y-axis: DQ dly (-127~63)
3531 09:53:23.815540 RX Vref Scan = 0
3532 09:53:23.818133 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3533 09:53:23.821355 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3534 09:53:23.824577 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3535 09:53:23.827981 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3536 09:53:23.831823 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3537 09:53:23.832361 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3538 09:53:23.834835 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3539 09:53:23.838135 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3540 09:53:23.841532 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3541 09:53:23.845141 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3542 09:53:23.848101 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3543 09:53:23.851451 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3544 09:53:23.854938 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3545 09:53:23.855467 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3546 09:53:23.858603 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3547 09:53:23.861590 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3548 09:53:23.864871 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3549 09:53:23.868004 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3550 09:53:23.871417 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3551 09:53:23.874770 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3552 09:53:23.878396 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3553 09:53:23.878930 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3554 09:53:23.881707 -4, [0] xxxoxxxx xxxxxxxx [MSB]
3555 09:53:23.885059 -3, [0] xxxoxxxx xxxxxxxx [MSB]
3556 09:53:23.888449 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3557 09:53:23.891667 -1, [0] xxooxxxx xxxxxxxo [MSB]
3558 09:53:23.895043 0, [0] xxooxxxx ooxxxxxo [MSB]
3559 09:53:23.895569 1, [0] xxooxxxx oooxxxxo [MSB]
3560 09:53:23.898045 2, [0] xxooxxxx ooooxxxo [MSB]
3561 09:53:23.901755 3, [0] xxoooxxo ooooxxoo [MSB]
3562 09:53:23.905096 4, [0] xxoooxxo ooooxooo [MSB]
3563 09:53:23.908400 5, [0] xxoooxxo oooooooo [MSB]
3564 09:53:23.911811 6, [0] xooooxxo oooooooo [MSB]
3565 09:53:23.915040 33, [0] oooxoooo ooooooox [MSB]
3566 09:53:23.918462 34, [0] oooxoooo ooooooox [MSB]
3567 09:53:23.921673 35, [0] oooxoooo ooooooox [MSB]
3568 09:53:23.924937 36, [0] ooxxoooo ooxoooox [MSB]
3569 09:53:23.925375 37, [0] ooxxxooo xxxoooxx [MSB]
3570 09:53:23.928366 38, [0] ooxxxoox xxxxooxx [MSB]
3571 09:53:23.931752 39, [0] ooxxxoox xxxxoxxx [MSB]
3572 09:53:23.935050 40, [0] ooxxxoox xxxxxxxx [MSB]
3573 09:53:23.938381 41, [0] ooxxxxox xxxxxxxx [MSB]
3574 09:53:23.941733 42, [0] xxxxxxxx xxxxxxxx [MSB]
3575 09:53:23.945222 iDelay=42, Bit 0, Center 24 (7 ~ 41) 35
3576 09:53:23.948534 iDelay=42, Bit 1, Center 23 (6 ~ 41) 36
3577 09:53:23.951993 iDelay=42, Bit 2, Center 17 (-1 ~ 35) 37
3578 09:53:23.955376 iDelay=42, Bit 3, Center 14 (-4 ~ 32) 37
3579 09:53:23.958510 iDelay=42, Bit 4, Center 19 (3 ~ 36) 34
3580 09:53:23.962301 iDelay=42, Bit 5, Center 23 (7 ~ 40) 34
3581 09:53:23.965406 iDelay=42, Bit 6, Center 24 (7 ~ 41) 35
3582 09:53:23.968659 iDelay=42, Bit 7, Center 20 (3 ~ 37) 35
3583 09:53:23.972037 iDelay=42, Bit 8, Center 18 (0 ~ 36) 37
3584 09:53:23.975151 iDelay=42, Bit 9, Center 18 (0 ~ 36) 37
3585 09:53:23.978508 iDelay=42, Bit 10, Center 18 (1 ~ 35) 35
3586 09:53:23.985256 iDelay=42, Bit 11, Center 19 (2 ~ 37) 36
3587 09:53:23.988490 iDelay=42, Bit 12, Center 22 (5 ~ 39) 35
3588 09:53:23.991979 iDelay=42, Bit 13, Center 21 (4 ~ 38) 35
3589 09:53:23.995285 iDelay=42, Bit 14, Center 19 (3 ~ 36) 34
3590 09:53:23.998723 iDelay=42, Bit 15, Center 15 (-2 ~ 32) 35
3591 09:53:23.999244 ==
3592 09:53:24.002007 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3593 09:53:24.005173 fsp= 1, odt_onoff= 1, Byte mode= 0
3594 09:53:24.005628 ==
3595 09:53:24.008813 DQS Delay:
3596 09:53:24.009326 DQS0 = 0, DQS1 = 0
3597 09:53:24.012143 DQM Delay:
3598 09:53:24.012656 DQM0 = 20, DQM1 = 18
3599 09:53:24.012993 DQ Delay:
3600 09:53:24.015274 DQ0 =24, DQ1 =23, DQ2 =17, DQ3 =14
3601 09:53:24.018680 DQ4 =19, DQ5 =23, DQ6 =24, DQ7 =20
3602 09:53:24.022019 DQ8 =18, DQ9 =18, DQ10 =18, DQ11 =19
3603 09:53:24.025155 DQ12 =22, DQ13 =21, DQ14 =19, DQ15 =15
3604 09:53:24.025597
3605 09:53:24.025932
3606 09:53:24.026268
3607 09:53:24.028744 [DramC_TX_OE_Calibration] TA2
3608 09:53:24.032243 Original DQ_B0 (3 6) =30, OEN = 27
3609 09:53:24.035303 Original DQ_B1 (3 6) =30, OEN = 27
3610 09:53:24.038959 23, 0x0, End_B0=23 End_B1=23
3611 09:53:24.041919 24, 0x0, End_B0=24 End_B1=24
3612 09:53:24.042401 25, 0x0, End_B0=25 End_B1=25
3613 09:53:24.045523 26, 0x0, End_B0=26 End_B1=26
3614 09:53:24.048812 27, 0x0, End_B0=27 End_B1=27
3615 09:53:24.052135 28, 0x0, End_B0=28 End_B1=28
3616 09:53:24.055361 29, 0x0, End_B0=29 End_B1=29
3617 09:53:24.055891 30, 0x0, End_B0=30 End_B1=30
3618 09:53:24.058879 31, 0xFFFF, End_B0=30 End_B1=30
3619 09:53:24.065490 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3620 09:53:24.068554 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3621 09:53:24.071944
3622 09:53:24.072376
3623 09:53:24.072709 Write Rank1 MR23 =0x3f
3624 09:53:24.073018 [DQSOSC]
3625 09:53:24.082391 [DQSOSCAuto] RK1, (LSB)MR18= 0xa8, (MSB)MR19= 0x3, tDQSOscB0 = 336 ps tDQSOscB1 = 0 ps
3626 09:53:24.085482 CH1_RK1: MR19=0x3, MR18=0xA8, DQSOSC=336, MR23=63, INC=21, DEC=32
3627 09:53:24.088640 Write Rank1 MR23 =0x3f
3628 09:53:24.089075 [DQSOSC]
3629 09:53:24.098977 [DQSOSCAuto] RK1, (LSB)MR18= 0xa7, (MSB)MR19= 0x3, tDQSOscB0 = 336 ps tDQSOscB1 = 0 ps
3630 09:53:24.099504 CH1 RK1: MR19=3, MR18=A7
3631 09:53:24.102392 [RxdqsGatingPostProcess] freq 1600
3632 09:53:24.108943 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3633 09:53:24.109465 Rank: 0
3634 09:53:24.112102 best DQS0 dly(2T, 0.5T) = (2, 5)
3635 09:53:24.115441 best DQS1 dly(2T, 0.5T) = (2, 5)
3636 09:53:24.118925 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3637 09:53:24.122364 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3638 09:53:24.122803 Rank: 1
3639 09:53:24.125486 best DQS0 dly(2T, 0.5T) = (2, 5)
3640 09:53:24.129168 best DQS1 dly(2T, 0.5T) = (2, 5)
3641 09:53:24.132324 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3642 09:53:24.135701 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3643 09:53:24.138902 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3644 09:53:24.142463 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3645 09:53:24.145727 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3646 09:53:24.149127
3647 09:53:24.149643
3648 09:53:24.152597 [Calibration Summary] Freqency 1600
3649 09:53:24.153302 CH 0, Rank 0
3650 09:53:24.153659 All Pass.
3651 09:53:24.153973
3652 09:53:24.155638 CH 0, Rank 1
3653 09:53:24.156070 All Pass.
3654 09:53:24.156406
3655 09:53:24.156717 CH 1, Rank 0
3656 09:53:24.158828 All Pass.
3657 09:53:24.159262
3658 09:53:24.159598 CH 1, Rank 1
3659 09:53:24.159907 All Pass.
3660 09:53:24.160200
3661 09:53:24.165642 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3662 09:53:24.172115 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3663 09:53:24.178851 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3664 09:53:24.182587 Write Rank0 MR3 =0xb0
3665 09:53:24.189192 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3666 09:53:24.195946 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3667 09:53:24.202463 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3668 09:53:24.205817 Write Rank1 MR3 =0xb0
3669 09:53:24.212634 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3670 09:53:24.219144 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3671 09:53:24.225827 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3672 09:53:24.226489 Write Rank0 MR3 =0xb0
3673 09:53:24.232701 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3674 09:53:24.242715 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3675 09:53:24.249280 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3676 09:53:24.249801 Write Rank1 MR3 =0xb0
3677 09:53:24.252657 DramC Write-DBI on
3678 09:53:24.255824 [GetDramInforAfterCalByMRR] Vendor 1.
3679 09:53:24.259130 [GetDramInforAfterCalByMRR] Revision 7.
3680 09:53:24.259661 MR8 12
3681 09:53:24.266044 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3682 09:53:24.266601 MR8 12
3683 09:53:24.269335 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3684 09:53:24.269858 MR8 12
3685 09:53:24.275717 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3686 09:53:24.276269 MR8 12
3687 09:53:24.282415 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3688 09:53:24.289224 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3689 09:53:24.292387 Write Rank0 MR13 =0xd0
3690 09:53:24.292906 Write Rank1 MR13 =0xd0
3691 09:53:24.295665 Write Rank0 MR13 =0xd0
3692 09:53:24.298968 Write Rank1 MR13 =0xd0
3693 09:53:24.302477 Save calibration result to emmc
3694 09:53:24.302997
3695 09:53:24.303335
3696 09:53:24.305545 [DramcModeReg_Check] Freq_1600, FSP_1
3697 09:53:24.306071 FSP_1, CH_0, RK0
3698 09:53:24.308834 Write Rank0 MR13 =0xd8
3699 09:53:24.312073 MR12 = 0x56 (global = 0x56) match
3700 09:53:24.315363 MR14 = 0x16 (global = 0x16) match
3701 09:53:24.315800 FSP_1, CH_0, RK1
3702 09:53:24.318913 Write Rank1 MR13 =0xd8
3703 09:53:24.321789 MR12 = 0x56 (global = 0x56) match
3704 09:53:24.325270 MR14 = 0x16 (global = 0x16) match
3705 09:53:24.325708 FSP_1, CH_1, RK0
3706 09:53:24.328673 Write Rank0 MR13 =0xd8
3707 09:53:24.331829 MR12 = 0x58 (global = 0x58) match
3708 09:53:24.335000 MR14 = 0x18 (global = 0x18) match
3709 09:53:24.335633 FSP_1, CH_1, RK1
3710 09:53:24.338871 Write Rank1 MR13 =0xd8
3711 09:53:24.342134 MR12 = 0x56 (global = 0x56) match
3712 09:53:24.345469 MR14 = 0x18 (global = 0x18) match
3713 09:53:24.345991
3714 09:53:24.348267 [MEM_TEST] 02: After DFS, before run time config
3715 09:53:24.359893 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3716 09:53:24.360417
3717 09:53:24.360759 [TA2_TEST]
3718 09:53:24.361070 === TA2 HW
3719 09:53:24.363049 TA2 PAT: XTALK
3720 09:53:24.366268 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3721 09:53:24.373018 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3722 09:53:24.376741 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3723 09:53:24.379524 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3724 09:53:24.383180
3725 09:53:24.383689
3726 09:53:24.384025 Settings after calibration
3727 09:53:24.384334
3728 09:53:24.386268 [DramcRunTimeConfig]
3729 09:53:24.389767 TransferPLLToSPMControl - MODE SW PHYPLL
3730 09:53:24.390203 TX_TRACKING: ON
3731 09:53:24.393211 RX_TRACKING: ON
3732 09:53:24.393729 HW_GATING: ON
3733 09:53:24.396593 HW_GATING DBG: OFF
3734 09:53:24.397107 ddr_geometry:1
3735 09:53:24.399948 ddr_geometry:1
3736 09:53:24.400383 ddr_geometry:1
3737 09:53:24.400720 ddr_geometry:1
3738 09:53:24.402964 ddr_geometry:1
3739 09:53:24.403396 ddr_geometry:1
3740 09:53:24.406586 ddr_geometry:1
3741 09:53:24.407022 ddr_geometry:1
3742 09:53:24.410137 High Freq DUMMY_READ_FOR_TRACKING: ON
3743 09:53:24.413541 ZQCS_ENABLE_LP4: OFF
3744 09:53:24.416787 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3745 09:53:24.419727 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3746 09:53:24.420162 SPM_CONTROL_AFTERK: ON
3747 09:53:24.423056 IMPEDANCE_TRACKING: ON
3748 09:53:24.423491 TEMP_SENSOR: ON
3749 09:53:24.426642 PER_BANK_REFRESH: ON
3750 09:53:24.427079 HW_SAVE_FOR_SR: ON
3751 09:53:24.429795 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3752 09:53:24.433007 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3753 09:53:24.436405 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3754 09:53:24.440021 Read ODT Tracking: ON
3755 09:53:24.443058 =========================
3756 09:53:24.443494
3757 09:53:24.443830 [TA2_TEST]
3758 09:53:24.444139 === TA2 HW
3759 09:53:24.450356 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3760 09:53:24.453575 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3761 09:53:24.460388 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3762 09:53:24.463559 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3763 09:53:24.464096
3764 09:53:24.466452 [MEM_TEST] 03: After run time config
3765 09:53:24.477613 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3766 09:53:24.480843 [complex_mem_test] start addr:0x40024000, len:131072
3767 09:53:24.684918 1st complex R/W mem test pass
3768 09:53:24.691353 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3769 09:53:24.694749 sync preloader write leveling
3770 09:53:24.698134 sync preloader cbt_mr12
3771 09:53:24.698595 sync preloader cbt_clk_dly
3772 09:53:24.701537 sync preloader cbt_cmd_dly
3773 09:53:24.705333 sync preloader cbt_cs
3774 09:53:24.708616 sync preloader cbt_ca_perbit_delay
3775 09:53:24.709254 sync preloader clk_delay
3776 09:53:24.711942 sync preloader dqs_delay
3777 09:53:24.714991 sync preloader u1Gating2T_Save
3778 09:53:24.718526 sync preloader u1Gating05T_Save
3779 09:53:24.721482 sync preloader u1Gatingfine_tune_Save
3780 09:53:24.724834 sync preloader u1Gatingucpass_count_Save
3781 09:53:24.728280 sync preloader u1TxWindowPerbitVref_Save
3782 09:53:24.731553 sync preloader u1TxCenter_min_Save
3783 09:53:24.735200 sync preloader u1TxCenter_max_Save
3784 09:53:24.738128 sync preloader u1Txwin_center_Save
3785 09:53:24.741725 sync preloader u1Txfirst_pass_Save
3786 09:53:24.745102 sync preloader u1Txlast_pass_Save
3787 09:53:24.745618 sync preloader u1RxDatlat_Save
3788 09:53:24.748509 sync preloader u1RxWinPerbitVref_Save
3789 09:53:24.755123 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3790 09:53:24.758836 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3791 09:53:24.761476 sync preloader delay_cell_unit
3792 09:53:24.768503 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
3793 09:53:24.771681 sync preloader write leveling
3794 09:53:24.772198 sync preloader cbt_mr12
3795 09:53:24.774962 sync preloader cbt_clk_dly
3796 09:53:24.778420 sync preloader cbt_cmd_dly
3797 09:53:24.778937 sync preloader cbt_cs
3798 09:53:24.782027 sync preloader cbt_ca_perbit_delay
3799 09:53:24.785155 sync preloader clk_delay
3800 09:53:24.788833 sync preloader dqs_delay
3801 09:53:24.789347 sync preloader u1Gating2T_Save
3802 09:53:24.792103 sync preloader u1Gating05T_Save
3803 09:53:24.795431 sync preloader u1Gatingfine_tune_Save
3804 09:53:24.798751 sync preloader u1Gatingucpass_count_Save
3805 09:53:24.801862 sync preloader u1TxWindowPerbitVref_Save
3806 09:53:24.805483 sync preloader u1TxCenter_min_Save
3807 09:53:24.808338 sync preloader u1TxCenter_max_Save
3808 09:53:24.812117 sync preloader u1Txwin_center_Save
3809 09:53:24.815232 sync preloader u1Txfirst_pass_Save
3810 09:53:24.818548 sync preloader u1Txlast_pass_Save
3811 09:53:24.821691 sync preloader u1RxDatlat_Save
3812 09:53:24.825132 sync preloader u1RxWinPerbitVref_Save
3813 09:53:24.828288 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3814 09:53:24.831760 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3815 09:53:24.835093 sync preloader delay_cell_unit
3816 09:53:24.841729 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
3817 09:53:24.845006 sync preloader write leveling
3818 09:53:24.848642 sync preloader cbt_mr12
3819 09:53:24.849159 sync preloader cbt_clk_dly
3820 09:53:24.852065 sync preloader cbt_cmd_dly
3821 09:53:24.855273 sync preloader cbt_cs
3822 09:53:24.858808 sync preloader cbt_ca_perbit_delay
3823 09:53:24.859338 sync preloader clk_delay
3824 09:53:24.861882 sync preloader dqs_delay
3825 09:53:24.865286 sync preloader u1Gating2T_Save
3826 09:53:24.868660 sync preloader u1Gating05T_Save
3827 09:53:24.872068 sync preloader u1Gatingfine_tune_Save
3828 09:53:24.875359 sync preloader u1Gatingucpass_count_Save
3829 09:53:24.878585 sync preloader u1TxWindowPerbitVref_Save
3830 09:53:24.882102 sync preloader u1TxCenter_min_Save
3831 09:53:24.885532 sync preloader u1TxCenter_max_Save
3832 09:53:24.886047 sync preloader u1Txwin_center_Save
3833 09:53:24.889018 sync preloader u1Txfirst_pass_Save
3834 09:53:24.892108 sync preloader u1Txlast_pass_Save
3835 09:53:24.895271 sync preloader u1RxDatlat_Save
3836 09:53:24.898802 sync preloader u1RxWinPerbitVref_Save
3837 09:53:24.902081 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3838 09:53:24.908747 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3839 09:53:24.912299 sync preloader delay_cell_unit
3840 09:53:24.915312 just_for_test_dump_coreboot_params dump all params
3841 09:53:24.915831 dump source = 0x0
3842 09:53:24.918785 dump params frequency:1600
3843 09:53:24.922307 dump params rank number:2
3844 09:53:24.922906
3845 09:53:24.925337 dump params write leveling
3846 09:53:24.925766 write leveling[0][0][0] = 0x22
3847 09:53:24.928500 write leveling[0][0][1] = 0x1c
3848 09:53:24.931889 write leveling[0][1][0] = 0x22
3849 09:53:24.935189 write leveling[0][1][1] = 0x1d
3850 09:53:24.938524 write leveling[1][0][0] = 0x23
3851 09:53:24.941977 write leveling[1][0][1] = 0x21
3852 09:53:24.942555 write leveling[1][1][0] = 0x25
3853 09:53:24.945204 write leveling[1][1][1] = 0x1e
3854 09:53:24.948583 dump params cbt_cs
3855 09:53:24.949097 cbt_cs[0][0] = 0x8
3856 09:53:24.951928 cbt_cs[0][1] = 0x8
3857 09:53:24.952395 cbt_cs[1][0] = 0xc
3858 09:53:24.955511 cbt_cs[1][1] = 0xc
3859 09:53:24.956034 dump params cbt_mr12
3860 09:53:24.958465 cbt_mr12[0][0] = 0x16
3861 09:53:24.962174 cbt_mr12[0][1] = 0x16
3862 09:53:24.962729 cbt_mr12[1][0] = 0x18
3863 09:53:24.965333 cbt_mr12[1][1] = 0x16
3864 09:53:24.965851 dump params tx window
3865 09:53:24.968470 tx_center_min[0][0][0] = 980
3866 09:53:24.972273 tx_center_max[0][0][0] = 988
3867 09:53:24.975467 tx_center_min[0][0][1] = 976
3868 09:53:24.975902 tx_center_max[0][0][1] = 980
3869 09:53:24.978642 tx_center_min[0][1][0] = 981
3870 09:53:24.981751 tx_center_max[0][1][0] = 988
3871 09:53:24.985682 tx_center_min[0][1][1] = 977
3872 09:53:24.988773 tx_center_max[0][1][1] = 982
3873 09:53:24.989296 tx_center_min[1][0][0] = 981
3874 09:53:24.992188 tx_center_max[1][0][0] = 987
3875 09:53:24.995464 tx_center_min[1][0][1] = 980
3876 09:53:24.998848 tx_center_max[1][0][1] = 982
3877 09:53:25.002336 tx_center_min[1][1][0] = 983
3878 09:53:25.002857 tx_center_max[1][1][0] = 988
3879 09:53:25.005571 tx_center_min[1][1][1] = 976
3880 09:53:25.008773 tx_center_max[1][1][1] = 980
3881 09:53:25.009295 dump params tx window
3882 09:53:25.012211 tx_win_center[0][0][0] = 988
3883 09:53:25.015302 tx_first_pass[0][0][0] = 976
3884 09:53:25.018590 tx_last_pass[0][0][0] = 1000
3885 09:53:25.022608 tx_win_center[0][0][1] = 986
3886 09:53:25.023127 tx_first_pass[0][0][1] = 975
3887 09:53:25.025341 tx_last_pass[0][0][1] = 998
3888 09:53:25.028927 tx_win_center[0][0][2] = 987
3889 09:53:25.032024 tx_first_pass[0][0][2] = 975
3890 09:53:25.032469 tx_last_pass[0][0][2] = 999
3891 09:53:25.035629 tx_win_center[0][0][3] = 980
3892 09:53:25.038848 tx_first_pass[0][0][3] = 968
3893 09:53:25.042311 tx_last_pass[0][0][3] = 993
3894 09:53:25.045594 tx_win_center[0][0][4] = 987
3895 09:53:25.046130 tx_first_pass[0][0][4] = 975
3896 09:53:25.048976 tx_last_pass[0][0][4] = 999
3897 09:53:25.052003 tx_win_center[0][0][5] = 982
3898 09:53:25.055697 tx_first_pass[0][0][5] = 970
3899 09:53:25.056211 tx_last_pass[0][0][5] = 994
3900 09:53:25.058810 tx_win_center[0][0][6] = 983
3901 09:53:25.062609 tx_first_pass[0][0][6] = 971
3902 09:53:25.066093 tx_last_pass[0][0][6] = 996
3903 09:53:25.066659 tx_win_center[0][0][7] = 984
3904 09:53:25.069128 tx_first_pass[0][0][7] = 972
3905 09:53:25.072133 tx_last_pass[0][0][7] = 997
3906 09:53:25.075713 tx_win_center[0][0][8] = 976
3907 09:53:25.079029 tx_first_pass[0][0][8] = 963
3908 09:53:25.079542 tx_last_pass[0][0][8] = 989
3909 09:53:25.082331 tx_win_center[0][0][9] = 976
3910 09:53:25.085786 tx_first_pass[0][0][9] = 964
3911 09:53:25.088951 tx_last_pass[0][0][9] = 989
3912 09:53:25.089484 tx_win_center[0][0][10] = 980
3913 09:53:25.092488 tx_first_pass[0][0][10] = 968
3914 09:53:25.095565 tx_last_pass[0][0][10] = 992
3915 09:53:25.099163 tx_win_center[0][0][11] = 976
3916 09:53:25.102395 tx_first_pass[0][0][11] = 963
3917 09:53:25.102930 tx_last_pass[0][0][11] = 989
3918 09:53:25.105589 tx_win_center[0][0][12] = 976
3919 09:53:25.109063 tx_first_pass[0][0][12] = 964
3920 09:53:25.112657 tx_last_pass[0][0][12] = 989
3921 09:53:25.115827 tx_win_center[0][0][13] = 976
3922 09:53:25.116360 tx_first_pass[0][0][13] = 963
3923 09:53:25.119240 tx_last_pass[0][0][13] = 989
3924 09:53:25.122656 tx_win_center[0][0][14] = 976
3925 09:53:25.125555 tx_first_pass[0][0][14] = 964
3926 09:53:25.128956 tx_last_pass[0][0][14] = 989
3927 09:53:25.129402 tx_win_center[0][0][15] = 979
3928 09:53:25.132169 tx_first_pass[0][0][15] = 967
3929 09:53:25.135737 tx_last_pass[0][0][15] = 991
3930 09:53:25.139072 tx_win_center[0][1][0] = 988
3931 09:53:25.142125 tx_first_pass[0][1][0] = 976
3932 09:53:25.142580 tx_last_pass[0][1][0] = 1001
3933 09:53:25.145604 tx_win_center[0][1][1] = 987
3934 09:53:25.149370 tx_first_pass[0][1][1] = 976
3935 09:53:25.152293 tx_last_pass[0][1][1] = 999
3936 09:53:25.155787 tx_win_center[0][1][2] = 988
3937 09:53:25.156229 tx_first_pass[0][1][2] = 976
3938 09:53:25.158998 tx_last_pass[0][1][2] = 1000
3939 09:53:25.162674 tx_win_center[0][1][3] = 981
3940 09:53:25.165856 tx_first_pass[0][1][3] = 969
3941 09:53:25.166401 tx_last_pass[0][1][3] = 993
3942 09:53:25.169073 tx_win_center[0][1][4] = 987
3943 09:53:25.172557 tx_first_pass[0][1][4] = 975
3944 09:53:25.175635 tx_last_pass[0][1][4] = 1000
3945 09:53:25.179528 tx_win_center[0][1][5] = 982
3946 09:53:25.180041 tx_first_pass[0][1][5] = 971
3947 09:53:25.182705 tx_last_pass[0][1][5] = 994
3948 09:53:25.186066 tx_win_center[0][1][6] = 983
3949 09:53:25.189669 tx_first_pass[0][1][6] = 971
3950 09:53:25.190183 tx_last_pass[0][1][6] = 996
3951 09:53:25.192862 tx_win_center[0][1][7] = 986
3952 09:53:25.196374 tx_first_pass[0][1][7] = 975
3953 09:53:25.199629 tx_last_pass[0][1][7] = 998
3954 09:53:25.200149 tx_win_center[0][1][8] = 977
3955 09:53:25.202847 tx_first_pass[0][1][8] = 965
3956 09:53:25.206507 tx_last_pass[0][1][8] = 990
3957 09:53:25.209491 tx_win_center[0][1][9] = 978
3958 09:53:25.212759 tx_first_pass[0][1][9] = 967
3959 09:53:25.213276 tx_last_pass[0][1][9] = 990
3960 09:53:25.216337 tx_win_center[0][1][10] = 982
3961 09:53:25.219623 tx_first_pass[0][1][10] = 969
3962 09:53:25.222955 tx_last_pass[0][1][10] = 995
3963 09:53:25.223473 tx_win_center[0][1][11] = 978
3964 09:53:25.226073 tx_first_pass[0][1][11] = 966
3965 09:53:25.229286 tx_last_pass[0][1][11] = 990
3966 09:53:25.232727 tx_win_center[0][1][12] = 979
3967 09:53:25.236305 tx_first_pass[0][1][12] = 967
3968 09:53:25.236831 tx_last_pass[0][1][12] = 991
3969 09:53:25.239552 tx_win_center[0][1][13] = 978
3970 09:53:25.242948 tx_first_pass[0][1][13] = 966
3971 09:53:25.246061 tx_last_pass[0][1][13] = 990
3972 09:53:25.249425 tx_win_center[0][1][14] = 978
3973 09:53:25.252661 tx_first_pass[0][1][14] = 966
3974 09:53:25.253100 tx_last_pass[0][1][14] = 990
3975 09:53:25.256549 tx_win_center[0][1][15] = 980
3976 09:53:25.259667 tx_first_pass[0][1][15] = 968
3977 09:53:25.262756 tx_last_pass[0][1][15] = 992
3978 09:53:25.263193 tx_win_center[1][0][0] = 987
3979 09:53:25.266396 tx_first_pass[1][0][0] = 976
3980 09:53:25.269612 tx_last_pass[1][0][0] = 999
3981 09:53:25.272737 tx_win_center[1][0][1] = 986
3982 09:53:25.276304 tx_first_pass[1][0][1] = 975
3983 09:53:25.276820 tx_last_pass[1][0][1] = 998
3984 09:53:25.279590 tx_win_center[1][0][2] = 983
3985 09:53:25.282698 tx_first_pass[1][0][2] = 972
3986 09:53:25.285926 tx_last_pass[1][0][2] = 995
3987 09:53:25.286393 tx_win_center[1][0][3] = 981
3988 09:53:25.288998 tx_first_pass[1][0][3] = 969
3989 09:53:25.292883 tx_last_pass[1][0][3] = 993
3990 09:53:25.295996 tx_win_center[1][0][4] = 985
3991 09:53:25.299497 tx_first_pass[1][0][4] = 973
3992 09:53:25.300017 tx_last_pass[1][0][4] = 997
3993 09:53:25.303032 tx_win_center[1][0][5] = 986
3994 09:53:25.306369 tx_first_pass[1][0][5] = 975
3995 09:53:25.309520 tx_last_pass[1][0][5] = 998
3996 09:53:25.310037 tx_win_center[1][0][6] = 987
3997 09:53:25.312684 tx_first_pass[1][0][6] = 976
3998 09:53:25.316387 tx_last_pass[1][0][6] = 999
3999 09:53:25.319518 tx_win_center[1][0][7] = 985
4000 09:53:25.323167 tx_first_pass[1][0][7] = 974
4001 09:53:25.323683 tx_last_pass[1][0][7] = 997
4002 09:53:25.325715 tx_win_center[1][0][8] = 980
4003 09:53:25.329339 tx_first_pass[1][0][8] = 969
4004 09:53:25.332593 tx_last_pass[1][0][8] = 992
4005 09:53:25.333027 tx_win_center[1][0][9] = 980
4006 09:53:25.336214 tx_first_pass[1][0][9] = 969
4007 09:53:25.339591 tx_last_pass[1][0][9] = 992
4008 09:53:25.342930 tx_win_center[1][0][10] = 981
4009 09:53:25.346049 tx_first_pass[1][0][10] = 970
4010 09:53:25.346622 tx_last_pass[1][0][10] = 993
4011 09:53:25.349480 tx_win_center[1][0][11] = 982
4012 09:53:25.352927 tx_first_pass[1][0][11] = 971
4013 09:53:25.356296 tx_last_pass[1][0][11] = 994
4014 09:53:25.359693 tx_win_center[1][0][12] = 982
4015 09:53:25.360212 tx_first_pass[1][0][12] = 971
4016 09:53:25.363171 tx_last_pass[1][0][12] = 994
4017 09:53:25.366637 tx_win_center[1][0][13] = 982
4018 09:53:25.369567 tx_first_pass[1][0][13] = 971
4019 09:53:25.373052 tx_last_pass[1][0][13] = 993
4020 09:53:25.373566 tx_win_center[1][0][14] = 982
4021 09:53:25.376070 tx_first_pass[1][0][14] = 971
4022 09:53:25.379351 tx_last_pass[1][0][14] = 993
4023 09:53:25.382726 tx_win_center[1][0][15] = 980
4024 09:53:25.386396 tx_first_pass[1][0][15] = 968
4025 09:53:25.386915 tx_last_pass[1][0][15] = 992
4026 09:53:25.389577 tx_win_center[1][1][0] = 988
4027 09:53:25.393254 tx_first_pass[1][1][0] = 976
4028 09:53:25.396211 tx_last_pass[1][1][0] = 1001
4029 09:53:25.399676 tx_win_center[1][1][1] = 987
4030 09:53:25.400187 tx_first_pass[1][1][1] = 975
4031 09:53:25.402685 tx_last_pass[1][1][1] = 999
4032 09:53:25.406496 tx_win_center[1][1][2] = 984
4033 09:53:25.409305 tx_first_pass[1][1][2] = 971
4034 09:53:25.409734 tx_last_pass[1][1][2] = 997
4035 09:53:25.413033 tx_win_center[1][1][3] = 983
4036 09:53:25.416326 tx_first_pass[1][1][3] = 970
4037 09:53:25.419582 tx_last_pass[1][1][3] = 997
4038 09:53:25.420099 tx_win_center[1][1][4] = 985
4039 09:53:25.423053 tx_first_pass[1][1][4] = 973
4040 09:53:25.426060 tx_last_pass[1][1][4] = 998
4041 09:53:25.429724 tx_win_center[1][1][5] = 988
4042 09:53:25.432690 tx_first_pass[1][1][5] = 976
4043 09:53:25.433123 tx_last_pass[1][1][5] = 1001
4044 09:53:25.436177 tx_win_center[1][1][6] = 988
4045 09:53:25.439459 tx_first_pass[1][1][6] = 976
4046 09:53:25.442667 tx_last_pass[1][1][6] = 1001
4047 09:53:25.445918 tx_win_center[1][1][7] = 986
4048 09:53:25.446494 tx_first_pass[1][1][7] = 974
4049 09:53:25.449445 tx_last_pass[1][1][7] = 998
4050 09:53:25.452636 tx_win_center[1][1][8] = 978
4051 09:53:25.456357 tx_first_pass[1][1][8] = 965
4052 09:53:25.456871 tx_last_pass[1][1][8] = 991
4053 09:53:25.459583 tx_win_center[1][1][9] = 977
4054 09:53:25.462937 tx_first_pass[1][1][9] = 964
4055 09:53:25.466321 tx_last_pass[1][1][9] = 991
4056 09:53:25.469629 tx_win_center[1][1][10] = 978
4057 09:53:25.470141 tx_first_pass[1][1][10] = 965
4058 09:53:25.472886 tx_last_pass[1][1][10] = 991
4059 09:53:25.476049 tx_win_center[1][1][11] = 980
4060 09:53:25.479470 tx_first_pass[1][1][11] = 968
4061 09:53:25.482764 tx_last_pass[1][1][11] = 992
4062 09:53:25.483197 tx_win_center[1][1][12] = 980
4063 09:53:25.486491 tx_first_pass[1][1][12] = 969
4064 09:53:25.489624 tx_last_pass[1][1][12] = 992
4065 09:53:25.492654 tx_win_center[1][1][13] = 979
4066 09:53:25.496474 tx_first_pass[1][1][13] = 967
4067 09:53:25.496987 tx_last_pass[1][1][13] = 991
4068 09:53:25.499901 tx_win_center[1][1][14] = 979
4069 09:53:25.502938 tx_first_pass[1][1][14] = 967
4070 09:53:25.506347 tx_last_pass[1][1][14] = 991
4071 09:53:25.509611 tx_win_center[1][1][15] = 976
4072 09:53:25.510126 tx_first_pass[1][1][15] = 963
4073 09:53:25.513110 tx_last_pass[1][1][15] = 989
4074 09:53:25.516117 dump params rx window
4075 09:53:25.516546 rx_firspass[0][0][0] = 9
4076 09:53:25.519761 rx_lastpass[0][0][0] = 40
4077 09:53:25.522969 rx_firspass[0][0][1] = 7
4078 09:53:25.523397 rx_lastpass[0][0][1] = 38
4079 09:53:25.526271 rx_firspass[0][0][2] = 9
4080 09:53:25.529755 rx_lastpass[0][0][2] = 38
4081 09:53:25.532927 rx_firspass[0][0][3] = -3
4082 09:53:25.533353 rx_lastpass[0][0][3] = 28
4083 09:53:25.536339 rx_firspass[0][0][4] = 7
4084 09:53:25.539520 rx_lastpass[0][0][4] = 38
4085 09:53:25.540023 rx_firspass[0][0][5] = 0
4086 09:53:25.542963 rx_lastpass[0][0][5] = 30
4087 09:53:25.546252 rx_firspass[0][0][6] = 1
4088 09:53:25.546686 rx_lastpass[0][0][6] = 32
4089 09:53:25.549924 rx_firspass[0][0][7] = 3
4090 09:53:25.552912 rx_lastpass[0][0][7] = 32
4091 09:53:25.556486 rx_firspass[0][0][8] = 0
4092 09:53:25.557000 rx_lastpass[0][0][8] = 34
4093 09:53:25.559828 rx_firspass[0][0][9] = 5
4094 09:53:25.563112 rx_lastpass[0][0][9] = 34
4095 09:53:25.563553 rx_firspass[0][0][10] = 7
4096 09:53:25.566493 rx_lastpass[0][0][10] = 38
4097 09:53:25.569899 rx_firspass[0][0][11] = 1
4098 09:53:25.573090 rx_lastpass[0][0][11] = 34
4099 09:53:25.573601 rx_firspass[0][0][12] = 2
4100 09:53:25.576222 rx_lastpass[0][0][12] = 36
4101 09:53:25.579648 rx_firspass[0][0][13] = 2
4102 09:53:25.580131 rx_lastpass[0][0][13] = 30
4103 09:53:25.583186 rx_firspass[0][0][14] = 0
4104 09:53:25.586762 rx_lastpass[0][0][14] = 35
4105 09:53:25.589835 rx_firspass[0][0][15] = 3
4106 09:53:25.590385 rx_lastpass[0][0][15] = 36
4107 09:53:25.593346 rx_firspass[0][1][0] = 7
4108 09:53:25.597094 rx_lastpass[0][1][0] = 41
4109 09:53:25.597608 rx_firspass[0][1][1] = 6
4110 09:53:25.599628 rx_lastpass[0][1][1] = 40
4111 09:53:25.603218 rx_firspass[0][1][2] = 7
4112 09:53:25.606486 rx_lastpass[0][1][2] = 38
4113 09:53:25.607001 rx_firspass[0][1][3] = -3
4114 09:53:25.609929 rx_lastpass[0][1][3] = 31
4115 09:53:25.613370 rx_firspass[0][1][4] = 7
4116 09:53:25.613884 rx_lastpass[0][1][4] = 40
4117 09:53:25.616811 rx_firspass[0][1][5] = -1
4118 09:53:25.620132 rx_lastpass[0][1][5] = 33
4119 09:53:25.620645 rx_firspass[0][1][6] = 2
4120 09:53:25.623250 rx_lastpass[0][1][6] = 34
4121 09:53:25.626598 rx_firspass[0][1][7] = 3
4122 09:53:25.627107 rx_lastpass[0][1][7] = 34
4123 09:53:25.630373 rx_firspass[0][1][8] = 0
4124 09:53:25.633343 rx_lastpass[0][1][8] = 35
4125 09:53:25.636731 rx_firspass[0][1][9] = 3
4126 09:53:25.637241 rx_lastpass[0][1][9] = 36
4127 09:53:25.640019 rx_firspass[0][1][10] = 6
4128 09:53:25.643089 rx_lastpass[0][1][10] = 39
4129 09:53:25.643525 rx_firspass[0][1][11] = 0
4130 09:53:25.646499 rx_lastpass[0][1][11] = 34
4131 09:53:25.650096 rx_firspass[0][1][12] = 3
4132 09:53:25.653078 rx_lastpass[0][1][12] = 37
4133 09:53:25.653601 rx_firspass[0][1][13] = 2
4134 09:53:25.656788 rx_lastpass[0][1][13] = 33
4135 09:53:25.660457 rx_firspass[0][1][14] = 1
4136 09:53:25.663202 rx_lastpass[0][1][14] = 34
4137 09:53:25.663710 rx_firspass[0][1][15] = 3
4138 09:53:25.666426 rx_lastpass[0][1][15] = 37
4139 09:53:25.670162 rx_firspass[1][0][0] = 7
4140 09:53:25.670725 rx_lastpass[1][0][0] = 39
4141 09:53:25.673181 rx_firspass[1][0][1] = 7
4142 09:53:25.676520 rx_lastpass[1][0][1] = 39
4143 09:53:25.676948 rx_firspass[1][0][2] = 0
4144 09:53:25.680136 rx_lastpass[1][0][2] = 34
4145 09:53:25.683579 rx_firspass[1][0][3] = -2
4146 09:53:25.686691 rx_lastpass[1][0][3] = 32
4147 09:53:25.687206 rx_firspass[1][0][4] = 4
4148 09:53:25.689982 rx_lastpass[1][0][4] = 34
4149 09:53:25.693498 rx_firspass[1][0][5] = 9
4150 09:53:25.694007 rx_lastpass[1][0][5] = 40
4151 09:53:25.696844 rx_firspass[1][0][6] = 9
4152 09:53:25.699984 rx_lastpass[1][0][6] = 40
4153 09:53:25.700500 rx_firspass[1][0][7] = 3
4154 09:53:25.702938 rx_lastpass[1][0][7] = 34
4155 09:53:25.706964 rx_firspass[1][0][8] = 1
4156 09:53:25.709907 rx_lastpass[1][0][8] = 35
4157 09:53:25.710440 rx_firspass[1][0][9] = 1
4158 09:53:25.713349 rx_lastpass[1][0][9] = 35
4159 09:53:25.716681 rx_firspass[1][0][10] = 2
4160 09:53:25.717193 rx_lastpass[1][0][10] = 33
4161 09:53:25.719799 rx_firspass[1][0][11] = 2
4162 09:53:25.723291 rx_lastpass[1][0][11] = 36
4163 09:53:25.726968 rx_firspass[1][0][12] = 4
4164 09:53:25.727481 rx_lastpass[1][0][12] = 37
4165 09:53:25.730356 rx_firspass[1][0][13] = 3
4166 09:53:25.733407 rx_lastpass[1][0][13] = 35
4167 09:53:25.733917 rx_firspass[1][0][14] = 3
4168 09:53:25.736439 rx_lastpass[1][0][14] = 35
4169 09:53:25.740239 rx_firspass[1][0][15] = -2
4170 09:53:25.743012 rx_lastpass[1][0][15] = 30
4171 09:53:25.743444 rx_firspass[1][1][0] = 7
4172 09:53:25.746401 rx_lastpass[1][1][0] = 41
4173 09:53:25.749984 rx_firspass[1][1][1] = 6
4174 09:53:25.750549 rx_lastpass[1][1][1] = 41
4175 09:53:25.753048 rx_firspass[1][1][2] = -1
4176 09:53:25.756423 rx_lastpass[1][1][2] = 35
4177 09:53:25.759908 rx_firspass[1][1][3] = -4
4178 09:53:25.760421 rx_lastpass[1][1][3] = 32
4179 09:53:25.762938 rx_firspass[1][1][4] = 3
4180 09:53:25.766342 rx_lastpass[1][1][4] = 36
4181 09:53:25.766774 rx_firspass[1][1][5] = 7
4182 09:53:25.769816 rx_lastpass[1][1][5] = 40
4183 09:53:25.772978 rx_firspass[1][1][6] = 7
4184 09:53:25.776583 rx_lastpass[1][1][6] = 41
4185 09:53:25.777010 rx_firspass[1][1][7] = 3
4186 09:53:25.779897 rx_lastpass[1][1][7] = 37
4187 09:53:25.782925 rx_firspass[1][1][8] = 0
4188 09:53:25.783352 rx_lastpass[1][1][8] = 36
4189 09:53:25.786337 rx_firspass[1][1][9] = 0
4190 09:53:25.789609 rx_lastpass[1][1][9] = 36
4191 09:53:25.790035 rx_firspass[1][1][10] = 1
4192 09:53:25.792991 rx_lastpass[1][1][10] = 35
4193 09:53:25.796308 rx_firspass[1][1][11] = 2
4194 09:53:25.800060 rx_lastpass[1][1][11] = 37
4195 09:53:25.800491 rx_firspass[1][1][12] = 5
4196 09:53:25.803200 rx_lastpass[1][1][12] = 39
4197 09:53:25.806839 rx_firspass[1][1][13] = 4
4198 09:53:25.807403 rx_lastpass[1][1][13] = 38
4199 09:53:25.809735 rx_firspass[1][1][14] = 3
4200 09:53:25.813151 rx_lastpass[1][1][14] = 36
4201 09:53:25.816894 rx_firspass[1][1][15] = -2
4202 09:53:25.817408 rx_lastpass[1][1][15] = 32
4203 09:53:25.820004 dump params clk_delay
4204 09:53:25.820532 clk_delay[0] = 0
4205 09:53:25.823127 clk_delay[1] = 0
4206 09:53:25.826452 dump params dqs_delay
4207 09:53:25.826881 dqs_delay[0][0] = -1
4208 09:53:25.830429 dqs_delay[0][1] = 2
4209 09:53:25.830945 dqs_delay[1][0] = 0
4210 09:53:25.833070 dqs_delay[1][1] = 1
4211 09:53:25.836450 dump params delay_cell_unit = 753
4212 09:53:25.836881 dump source = 0x0
4213 09:53:25.839868 dump params frequency:1200
4214 09:53:25.843176 dump params rank number:2
4215 09:53:25.843642
4216 09:53:25.843975 dump params write leveling
4217 09:53:25.846853 write leveling[0][0][0] = 0x0
4218 09:53:25.850048 write leveling[0][0][1] = 0x0
4219 09:53:25.853198 write leveling[0][1][0] = 0x0
4220 09:53:25.856545 write leveling[0][1][1] = 0x0
4221 09:53:25.856973 write leveling[1][0][0] = 0x0
4222 09:53:25.860424 write leveling[1][0][1] = 0x0
4223 09:53:25.863622 write leveling[1][1][0] = 0x0
4224 09:53:25.866508 write leveling[1][1][1] = 0x0
4225 09:53:25.866938 dump params cbt_cs
4226 09:53:25.869923 cbt_cs[0][0] = 0x0
4227 09:53:25.870378 cbt_cs[0][1] = 0x0
4228 09:53:25.873430 cbt_cs[1][0] = 0x0
4229 09:53:25.874070 cbt_cs[1][1] = 0x0
4230 09:53:25.876752 dump params cbt_mr12
4231 09:53:25.877177 cbt_mr12[0][0] = 0x0
4232 09:53:25.880197 cbt_mr12[0][1] = 0x0
4233 09:53:25.883292 cbt_mr12[1][0] = 0x0
4234 09:53:25.883723 cbt_mr12[1][1] = 0x0
4235 09:53:25.886460 dump params tx window
4236 09:53:25.886888 tx_center_min[0][0][0] = 0
4237 09:53:25.890060 tx_center_max[0][0][0] = 0
4238 09:53:25.893218 tx_center_min[0][0][1] = 0
4239 09:53:25.896590 tx_center_max[0][0][1] = 0
4240 09:53:25.897097 tx_center_min[0][1][0] = 0
4241 09:53:25.900096 tx_center_max[0][1][0] = 0
4242 09:53:25.903371 tx_center_min[0][1][1] = 0
4243 09:53:25.906372 tx_center_max[0][1][1] = 0
4244 09:53:25.906806 tx_center_min[1][0][0] = 0
4245 09:53:25.910209 tx_center_max[1][0][0] = 0
4246 09:53:25.913367 tx_center_min[1][0][1] = 0
4247 09:53:25.916539 tx_center_max[1][0][1] = 0
4248 09:53:25.917103 tx_center_min[1][1][0] = 0
4249 09:53:25.919803 tx_center_max[1][1][0] = 0
4250 09:53:25.923294 tx_center_min[1][1][1] = 0
4251 09:53:25.926455 tx_center_max[1][1][1] = 0
4252 09:53:25.926886 dump params tx window
4253 09:53:25.929868 tx_win_center[0][0][0] = 0
4254 09:53:25.933430 tx_first_pass[0][0][0] = 0
4255 09:53:25.934193 tx_last_pass[0][0][0] = 0
4256 09:53:25.936546 tx_win_center[0][0][1] = 0
4257 09:53:25.939825 tx_first_pass[0][0][1] = 0
4258 09:53:25.940254 tx_last_pass[0][0][1] = 0
4259 09:53:25.942946 tx_win_center[0][0][2] = 0
4260 09:53:25.946794 tx_first_pass[0][0][2] = 0
4261 09:53:25.950052 tx_last_pass[0][0][2] = 0
4262 09:53:25.950624 tx_win_center[0][0][3] = 0
4263 09:53:25.953271 tx_first_pass[0][0][3] = 0
4264 09:53:25.956750 tx_last_pass[0][0][3] = 0
4265 09:53:25.960291 tx_win_center[0][0][4] = 0
4266 09:53:25.960804 tx_first_pass[0][0][4] = 0
4267 09:53:25.963492 tx_last_pass[0][0][4] = 0
4268 09:53:25.966411 tx_win_center[0][0][5] = 0
4269 09:53:25.966841 tx_first_pass[0][0][5] = 0
4270 09:53:25.970191 tx_last_pass[0][0][5] = 0
4271 09:53:25.973805 tx_win_center[0][0][6] = 0
4272 09:53:25.976923 tx_first_pass[0][0][6] = 0
4273 09:53:25.977438 tx_last_pass[0][0][6] = 0
4274 09:53:25.980071 tx_win_center[0][0][7] = 0
4275 09:53:25.983265 tx_first_pass[0][0][7] = 0
4276 09:53:25.983778 tx_last_pass[0][0][7] = 0
4277 09:53:25.986774 tx_win_center[0][0][8] = 0
4278 09:53:25.990085 tx_first_pass[0][0][8] = 0
4279 09:53:25.993654 tx_last_pass[0][0][8] = 0
4280 09:53:25.994247 tx_win_center[0][0][9] = 0
4281 09:53:25.996509 tx_first_pass[0][0][9] = 0
4282 09:53:26.000541 tx_last_pass[0][0][9] = 0
4283 09:53:26.003496 tx_win_center[0][0][10] = 0
4284 09:53:26.004008 tx_first_pass[0][0][10] = 0
4285 09:53:26.006912 tx_last_pass[0][0][10] = 0
4286 09:53:26.010269 tx_win_center[0][0][11] = 0
4287 09:53:26.013862 tx_first_pass[0][0][11] = 0
4288 09:53:26.014412 tx_last_pass[0][0][11] = 0
4289 09:53:26.016871 tx_win_center[0][0][12] = 0
4290 09:53:26.020008 tx_first_pass[0][0][12] = 0
4291 09:53:26.023501 tx_last_pass[0][0][12] = 0
4292 09:53:26.024018 tx_win_center[0][0][13] = 0
4293 09:53:26.026727 tx_first_pass[0][0][13] = 0
4294 09:53:26.030154 tx_last_pass[0][0][13] = 0
4295 09:53:26.033330 tx_win_center[0][0][14] = 0
4296 09:53:26.033890 tx_first_pass[0][0][14] = 0
4297 09:53:26.036571 tx_last_pass[0][0][14] = 0
4298 09:53:26.040113 tx_win_center[0][0][15] = 0
4299 09:53:26.043612 tx_first_pass[0][0][15] = 0
4300 09:53:26.044120 tx_last_pass[0][0][15] = 0
4301 09:53:26.046713 tx_win_center[0][1][0] = 0
4302 09:53:26.050389 tx_first_pass[0][1][0] = 0
4303 09:53:26.050901 tx_last_pass[0][1][0] = 0
4304 09:53:26.053438 tx_win_center[0][1][1] = 0
4305 09:53:26.057129 tx_first_pass[0][1][1] = 0
4306 09:53:26.060347 tx_last_pass[0][1][1] = 0
4307 09:53:26.060866 tx_win_center[0][1][2] = 0
4308 09:53:26.063696 tx_first_pass[0][1][2] = 0
4309 09:53:26.067390 tx_last_pass[0][1][2] = 0
4310 09:53:26.067907 tx_win_center[0][1][3] = 0
4311 09:53:26.070151 tx_first_pass[0][1][3] = 0
4312 09:53:26.073680 tx_last_pass[0][1][3] = 0
4313 09:53:26.076712 tx_win_center[0][1][4] = 0
4314 09:53:26.077143 tx_first_pass[0][1][4] = 0
4315 09:53:26.080454 tx_last_pass[0][1][4] = 0
4316 09:53:26.083334 tx_win_center[0][1][5] = 0
4317 09:53:26.086923 tx_first_pass[0][1][5] = 0
4318 09:53:26.087436 tx_last_pass[0][1][5] = 0
4319 09:53:26.090346 tx_win_center[0][1][6] = 0
4320 09:53:26.093692 tx_first_pass[0][1][6] = 0
4321 09:53:26.094208 tx_last_pass[0][1][6] = 0
4322 09:53:26.097478 tx_win_center[0][1][7] = 0
4323 09:53:26.099989 tx_first_pass[0][1][7] = 0
4324 09:53:26.103702 tx_last_pass[0][1][7] = 0
4325 09:53:26.104217 tx_win_center[0][1][8] = 0
4326 09:53:26.107093 tx_first_pass[0][1][8] = 0
4327 09:53:26.110317 tx_last_pass[0][1][8] = 0
4328 09:53:26.113439 tx_win_center[0][1][9] = 0
4329 09:53:26.113866 tx_first_pass[0][1][9] = 0
4330 09:53:26.117254 tx_last_pass[0][1][9] = 0
4331 09:53:26.120595 tx_win_center[0][1][10] = 0
4332 09:53:26.121111 tx_first_pass[0][1][10] = 0
4333 09:53:26.123371 tx_last_pass[0][1][10] = 0
4334 09:53:26.126797 tx_win_center[0][1][11] = 0
4335 09:53:26.130569 tx_first_pass[0][1][11] = 0
4336 09:53:26.131087 tx_last_pass[0][1][11] = 0
4337 09:53:26.133871 tx_win_center[0][1][12] = 0
4338 09:53:26.136859 tx_first_pass[0][1][12] = 0
4339 09:53:26.140133 tx_last_pass[0][1][12] = 0
4340 09:53:26.140570 tx_win_center[0][1][13] = 0
4341 09:53:26.143442 tx_first_pass[0][1][13] = 0
4342 09:53:26.147240 tx_last_pass[0][1][13] = 0
4343 09:53:26.150308 tx_win_center[0][1][14] = 0
4344 09:53:26.150822 tx_first_pass[0][1][14] = 0
4345 09:53:26.153672 tx_last_pass[0][1][14] = 0
4346 09:53:26.157010 tx_win_center[0][1][15] = 0
4347 09:53:26.160177 tx_first_pass[0][1][15] = 0
4348 09:53:26.160689 tx_last_pass[0][1][15] = 0
4349 09:53:26.163696 tx_win_center[1][0][0] = 0
4350 09:53:26.167192 tx_first_pass[1][0][0] = 0
4351 09:53:26.170650 tx_last_pass[1][0][0] = 0
4352 09:53:26.171166 tx_win_center[1][0][1] = 0
4353 09:53:26.173899 tx_first_pass[1][0][1] = 0
4354 09:53:26.177083 tx_last_pass[1][0][1] = 0
4355 09:53:26.177597 tx_win_center[1][0][2] = 0
4356 09:53:26.180637 tx_first_pass[1][0][2] = 0
4357 09:53:26.183765 tx_last_pass[1][0][2] = 0
4358 09:53:26.187253 tx_win_center[1][0][3] = 0
4359 09:53:26.187878 tx_first_pass[1][0][3] = 0
4360 09:53:26.190655 tx_last_pass[1][0][3] = 0
4361 09:53:26.193809 tx_win_center[1][0][4] = 0
4362 09:53:26.197171 tx_first_pass[1][0][4] = 0
4363 09:53:26.197688 tx_last_pass[1][0][4] = 0
4364 09:53:26.200600 tx_win_center[1][0][5] = 0
4365 09:53:26.203722 tx_first_pass[1][0][5] = 0
4366 09:53:26.204235 tx_last_pass[1][0][5] = 0
4367 09:53:26.207125 tx_win_center[1][0][6] = 0
4368 09:53:26.210294 tx_first_pass[1][0][6] = 0
4369 09:53:26.213672 tx_last_pass[1][0][6] = 0
4370 09:53:26.214103 tx_win_center[1][0][7] = 0
4371 09:53:26.216550 tx_first_pass[1][0][7] = 0
4372 09:53:26.220125 tx_last_pass[1][0][7] = 0
4373 09:53:26.223317 tx_win_center[1][0][8] = 0
4374 09:53:26.223741 tx_first_pass[1][0][8] = 0
4375 09:53:26.226785 tx_last_pass[1][0][8] = 0
4376 09:53:26.230433 tx_win_center[1][0][9] = 0
4377 09:53:26.230859 tx_first_pass[1][0][9] = 0
4378 09:53:26.233451 tx_last_pass[1][0][9] = 0
4379 09:53:26.236732 tx_win_center[1][0][10] = 0
4380 09:53:26.240084 tx_first_pass[1][0][10] = 0
4381 09:53:26.240451 tx_last_pass[1][0][10] = 0
4382 09:53:26.243743 tx_win_center[1][0][11] = 0
4383 09:53:26.246919 tx_first_pass[1][0][11] = 0
4384 09:53:26.250534 tx_last_pass[1][0][11] = 0
4385 09:53:26.250914 tx_win_center[1][0][12] = 0
4386 09:53:26.253721 tx_first_pass[1][0][12] = 0
4387 09:53:26.257025 tx_last_pass[1][0][12] = 0
4388 09:53:26.260244 tx_win_center[1][0][13] = 0
4389 09:53:26.260710 tx_first_pass[1][0][13] = 0
4390 09:53:26.263552 tx_last_pass[1][0][13] = 0
4391 09:53:26.266761 tx_win_center[1][0][14] = 0
4392 09:53:26.270340 tx_first_pass[1][0][14] = 0
4393 09:53:26.270872 tx_last_pass[1][0][14] = 0
4394 09:53:26.273433 tx_win_center[1][0][15] = 0
4395 09:53:26.276889 tx_first_pass[1][0][15] = 0
4396 09:53:26.280438 tx_last_pass[1][0][15] = 0
4397 09:53:26.280948 tx_win_center[1][1][0] = 0
4398 09:53:26.283478 tx_first_pass[1][1][0] = 0
4399 09:53:26.286924 tx_last_pass[1][1][0] = 0
4400 09:53:26.290204 tx_win_center[1][1][1] = 0
4401 09:53:26.290736 tx_first_pass[1][1][1] = 0
4402 09:53:26.293818 tx_last_pass[1][1][1] = 0
4403 09:53:26.296876 tx_win_center[1][1][2] = 0
4404 09:53:26.297301 tx_first_pass[1][1][2] = 0
4405 09:53:26.300192 tx_last_pass[1][1][2] = 0
4406 09:53:26.303850 tx_win_center[1][1][3] = 0
4407 09:53:26.306842 tx_first_pass[1][1][3] = 0
4408 09:53:26.307271 tx_last_pass[1][1][3] = 0
4409 09:53:26.310704 tx_win_center[1][1][4] = 0
4410 09:53:26.313929 tx_first_pass[1][1][4] = 0
4411 09:53:26.314480 tx_last_pass[1][1][4] = 0
4412 09:53:26.316921 tx_win_center[1][1][5] = 0
4413 09:53:26.320778 tx_first_pass[1][1][5] = 0
4414 09:53:26.323829 tx_last_pass[1][1][5] = 0
4415 09:53:26.324341 tx_win_center[1][1][6] = 0
4416 09:53:26.327415 tx_first_pass[1][1][6] = 0
4417 09:53:26.330798 tx_last_pass[1][1][6] = 0
4418 09:53:26.331307 tx_win_center[1][1][7] = 0
4419 09:53:26.333861 tx_first_pass[1][1][7] = 0
4420 09:53:26.337438 tx_last_pass[1][1][7] = 0
4421 09:53:26.340322 tx_win_center[1][1][8] = 0
4422 09:53:26.340941 tx_first_pass[1][1][8] = 0
4423 09:53:26.343926 tx_last_pass[1][1][8] = 0
4424 09:53:26.347188 tx_win_center[1][1][9] = 0
4425 09:53:26.350734 tx_first_pass[1][1][9] = 0
4426 09:53:26.351242 tx_last_pass[1][1][9] = 0
4427 09:53:26.353967 tx_win_center[1][1][10] = 0
4428 09:53:26.357122 tx_first_pass[1][1][10] = 0
4429 09:53:26.360767 tx_last_pass[1][1][10] = 0
4430 09:53:26.361273 tx_win_center[1][1][11] = 0
4431 09:53:26.363810 tx_first_pass[1][1][11] = 0
4432 09:53:26.367491 tx_last_pass[1][1][11] = 0
4433 09:53:26.370950 tx_win_center[1][1][12] = 0
4434 09:53:26.371458 tx_first_pass[1][1][12] = 0
4435 09:53:26.373871 tx_last_pass[1][1][12] = 0
4436 09:53:26.377151 tx_win_center[1][1][13] = 0
4437 09:53:26.380810 tx_first_pass[1][1][13] = 0
4438 09:53:26.381318 tx_last_pass[1][1][13] = 0
4439 09:53:26.383780 tx_win_center[1][1][14] = 0
4440 09:53:26.387130 tx_first_pass[1][1][14] = 0
4441 09:53:26.390815 tx_last_pass[1][1][14] = 0
4442 09:53:26.391320 tx_win_center[1][1][15] = 0
4443 09:53:26.394127 tx_first_pass[1][1][15] = 0
4444 09:53:26.397532 tx_last_pass[1][1][15] = 0
4445 09:53:26.398025 dump params rx window
4446 09:53:26.400548 rx_firspass[0][0][0] = 0
4447 09:53:26.403689 rx_lastpass[0][0][0] = 0
4448 09:53:26.404118 rx_firspass[0][0][1] = 0
4449 09:53:26.407625 rx_lastpass[0][0][1] = 0
4450 09:53:26.410988 rx_firspass[0][0][2] = 0
4451 09:53:26.411503 rx_lastpass[0][0][2] = 0
4452 09:53:26.413963 rx_firspass[0][0][3] = 0
4453 09:53:26.417484 rx_lastpass[0][0][3] = 0
4454 09:53:26.417993 rx_firspass[0][0][4] = 0
4455 09:53:26.420974 rx_lastpass[0][0][4] = 0
4456 09:53:26.424224 rx_firspass[0][0][5] = 0
4457 09:53:26.427057 rx_lastpass[0][0][5] = 0
4458 09:53:26.427484 rx_firspass[0][0][6] = 0
4459 09:53:26.430902 rx_lastpass[0][0][6] = 0
4460 09:53:26.434109 rx_firspass[0][0][7] = 0
4461 09:53:26.434675 rx_lastpass[0][0][7] = 0
4462 09:53:26.437159 rx_firspass[0][0][8] = 0
4463 09:53:26.440476 rx_lastpass[0][0][8] = 0
4464 09:53:26.441078 rx_firspass[0][0][9] = 0
4465 09:53:26.443945 rx_lastpass[0][0][9] = 0
4466 09:53:26.447108 rx_firspass[0][0][10] = 0
4467 09:53:26.447538 rx_lastpass[0][0][10] = 0
4468 09:53:26.450905 rx_firspass[0][0][11] = 0
4469 09:53:26.454265 rx_lastpass[0][0][11] = 0
4470 09:53:26.457318 rx_firspass[0][0][12] = 0
4471 09:53:26.457821 rx_lastpass[0][0][12] = 0
4472 09:53:26.460741 rx_firspass[0][0][13] = 0
4473 09:53:26.464163 rx_lastpass[0][0][13] = 0
4474 09:53:26.464675 rx_firspass[0][0][14] = 0
4475 09:53:26.467255 rx_lastpass[0][0][14] = 0
4476 09:53:26.470804 rx_firspass[0][0][15] = 0
4477 09:53:26.474004 rx_lastpass[0][0][15] = 0
4478 09:53:26.474561 rx_firspass[0][1][0] = 0
4479 09:53:26.477405 rx_lastpass[0][1][0] = 0
4480 09:53:26.480767 rx_firspass[0][1][1] = 0
4481 09:53:26.481294 rx_lastpass[0][1][1] = 0
4482 09:53:26.484246 rx_firspass[0][1][2] = 0
4483 09:53:26.487483 rx_lastpass[0][1][2] = 0
4484 09:53:26.487995 rx_firspass[0][1][3] = 0
4485 09:53:26.490566 rx_lastpass[0][1][3] = 0
4486 09:53:26.494070 rx_firspass[0][1][4] = 0
4487 09:53:26.494633 rx_lastpass[0][1][4] = 0
4488 09:53:26.497313 rx_firspass[0][1][5] = 0
4489 09:53:26.500432 rx_lastpass[0][1][5] = 0
4490 09:53:26.500945 rx_firspass[0][1][6] = 0
4491 09:53:26.504124 rx_lastpass[0][1][6] = 0
4492 09:53:26.507170 rx_firspass[0][1][7] = 0
4493 09:53:26.510909 rx_lastpass[0][1][7] = 0
4494 09:53:26.511427 rx_firspass[0][1][8] = 0
4495 09:53:26.513973 rx_lastpass[0][1][8] = 0
4496 09:53:26.517538 rx_firspass[0][1][9] = 0
4497 09:53:26.518107 rx_lastpass[0][1][9] = 0
4498 09:53:26.520703 rx_firspass[0][1][10] = 0
4499 09:53:26.523958 rx_lastpass[0][1][10] = 0
4500 09:53:26.524470 rx_firspass[0][1][11] = 0
4501 09:53:26.527528 rx_lastpass[0][1][11] = 0
4502 09:53:26.530338 rx_firspass[0][1][12] = 0
4503 09:53:26.533958 rx_lastpass[0][1][12] = 0
4504 09:53:26.534426 rx_firspass[0][1][13] = 0
4505 09:53:26.537215 rx_lastpass[0][1][13] = 0
4506 09:53:26.540382 rx_firspass[0][1][14] = 0
4507 09:53:26.540871 rx_lastpass[0][1][14] = 0
4508 09:53:26.544030 rx_firspass[0][1][15] = 0
4509 09:53:26.547061 rx_lastpass[0][1][15] = 0
4510 09:53:26.547495 rx_firspass[1][0][0] = 0
4511 09:53:26.550602 rx_lastpass[1][0][0] = 0
4512 09:53:26.554348 rx_firspass[1][0][1] = 0
4513 09:53:26.557181 rx_lastpass[1][0][1] = 0
4514 09:53:26.557605 rx_firspass[1][0][2] = 0
4515 09:53:26.560743 rx_lastpass[1][0][2] = 0
4516 09:53:26.563937 rx_firspass[1][0][3] = 0
4517 09:53:26.564455 rx_lastpass[1][0][3] = 0
4518 09:53:26.567445 rx_firspass[1][0][4] = 0
4519 09:53:26.570430 rx_lastpass[1][0][4] = 0
4520 09:53:26.570859 rx_firspass[1][0][5] = 0
4521 09:53:26.574301 rx_lastpass[1][0][5] = 0
4522 09:53:26.577192 rx_firspass[1][0][6] = 0
4523 09:53:26.577622 rx_lastpass[1][0][6] = 0
4524 09:53:26.580663 rx_firspass[1][0][7] = 0
4525 09:53:26.584038 rx_lastpass[1][0][7] = 0
4526 09:53:26.584469 rx_firspass[1][0][8] = 0
4527 09:53:26.587663 rx_lastpass[1][0][8] = 0
4528 09:53:26.590743 rx_firspass[1][0][9] = 0
4529 09:53:26.591175 rx_lastpass[1][0][9] = 0
4530 09:53:26.594076 rx_firspass[1][0][10] = 0
4531 09:53:26.597462 rx_lastpass[1][0][10] = 0
4532 09:53:26.600816 rx_firspass[1][0][11] = 0
4533 09:53:26.601343 rx_lastpass[1][0][11] = 0
4534 09:53:26.604006 rx_firspass[1][0][12] = 0
4535 09:53:26.607451 rx_lastpass[1][0][12] = 0
4536 09:53:26.607977 rx_firspass[1][0][13] = 0
4537 09:53:26.610496 rx_lastpass[1][0][13] = 0
4538 09:53:26.614338 rx_firspass[1][0][14] = 0
4539 09:53:26.617571 rx_lastpass[1][0][14] = 0
4540 09:53:26.618094 rx_firspass[1][0][15] = 0
4541 09:53:26.620847 rx_lastpass[1][0][15] = 0
4542 09:53:26.624153 rx_firspass[1][1][0] = 0
4543 09:53:26.624676 rx_lastpass[1][1][0] = 0
4544 09:53:26.627281 rx_firspass[1][1][1] = 0
4545 09:53:26.630736 rx_lastpass[1][1][1] = 0
4546 09:53:26.631259 rx_firspass[1][1][2] = 0
4547 09:53:26.634025 rx_lastpass[1][1][2] = 0
4548 09:53:26.637522 rx_firspass[1][1][3] = 0
4549 09:53:26.637965 rx_lastpass[1][1][3] = 0
4550 09:53:26.640775 rx_firspass[1][1][4] = 0
4551 09:53:26.644512 rx_lastpass[1][1][4] = 0
4552 09:53:26.645024 rx_firspass[1][1][5] = 0
4553 09:53:26.647450 rx_lastpass[1][1][5] = 0
4554 09:53:26.650829 rx_firspass[1][1][6] = 0
4555 09:53:26.654256 rx_lastpass[1][1][6] = 0
4556 09:53:26.654796 rx_firspass[1][1][7] = 0
4557 09:53:26.657411 rx_lastpass[1][1][7] = 0
4558 09:53:26.661032 rx_firspass[1][1][8] = 0
4559 09:53:26.661546 rx_lastpass[1][1][8] = 0
4560 09:53:26.664505 rx_firspass[1][1][9] = 0
4561 09:53:26.667700 rx_lastpass[1][1][9] = 0
4562 09:53:26.668134 rx_firspass[1][1][10] = 0
4563 09:53:26.670908 rx_lastpass[1][1][10] = 0
4564 09:53:26.674286 rx_firspass[1][1][11] = 0
4565 09:53:26.674726 rx_lastpass[1][1][11] = 0
4566 09:53:26.677695 rx_firspass[1][1][12] = 0
4567 09:53:26.681213 rx_lastpass[1][1][12] = 0
4568 09:53:26.684349 rx_firspass[1][1][13] = 0
4569 09:53:26.684861 rx_lastpass[1][1][13] = 0
4570 09:53:26.687648 rx_firspass[1][1][14] = 0
4571 09:53:26.691166 rx_lastpass[1][1][14] = 0
4572 09:53:26.691713 rx_firspass[1][1][15] = 0
4573 09:53:26.694533 rx_lastpass[1][1][15] = 0
4574 09:53:26.697787 dump params clk_delay
4575 09:53:26.698323 clk_delay[0] = 0
4576 09:53:26.701161 clk_delay[1] = 0
4577 09:53:26.701674 dump params dqs_delay
4578 09:53:26.704412 dqs_delay[0][0] = 0
4579 09:53:26.704929 dqs_delay[0][1] = 0
4580 09:53:26.707831 dqs_delay[1][0] = 0
4581 09:53:26.708345 dqs_delay[1][1] = 0
4582 09:53:26.711157 dump params delay_cell_unit = 753
4583 09:53:26.714308 dump source = 0x0
4584 09:53:26.717840 dump params frequency:800
4585 09:53:26.718384 dump params rank number:2
4586 09:53:26.718720
4587 09:53:26.720817 dump params write leveling
4588 09:53:26.724757 write leveling[0][0][0] = 0x0
4589 09:53:26.727449 write leveling[0][0][1] = 0x0
4590 09:53:26.727877 write leveling[0][1][0] = 0x0
4591 09:53:26.731151 write leveling[0][1][1] = 0x0
4592 09:53:26.734798 write leveling[1][0][0] = 0x0
4593 09:53:26.737413 write leveling[1][0][1] = 0x0
4594 09:53:26.741011 write leveling[1][1][0] = 0x0
4595 09:53:26.741693 write leveling[1][1][1] = 0x0
4596 09:53:26.744557 dump params cbt_cs
4597 09:53:26.745082 cbt_cs[0][0] = 0x0
4598 09:53:26.747545 cbt_cs[0][1] = 0x0
4599 09:53:26.750943 cbt_cs[1][0] = 0x0
4600 09:53:26.751370 cbt_cs[1][1] = 0x0
4601 09:53:26.754521 dump params cbt_mr12
4602 09:53:26.755097 cbt_mr12[0][0] = 0x0
4603 09:53:26.757795 cbt_mr12[0][1] = 0x0
4604 09:53:26.758336 cbt_mr12[1][0] = 0x0
4605 09:53:26.761269 cbt_mr12[1][1] = 0x0
4606 09:53:26.761776 dump params tx window
4607 09:53:26.764847 tx_center_min[0][0][0] = 0
4608 09:53:26.767651 tx_center_max[0][0][0] = 0
4609 09:53:26.771062 tx_center_min[0][0][1] = 0
4610 09:53:26.771577 tx_center_max[0][0][1] = 0
4611 09:53:26.774442 tx_center_min[0][1][0] = 0
4612 09:53:26.777757 tx_center_max[0][1][0] = 0
4613 09:53:26.781250 tx_center_min[0][1][1] = 0
4614 09:53:26.781761 tx_center_max[0][1][1] = 0
4615 09:53:26.784599 tx_center_min[1][0][0] = 0
4616 09:53:26.787590 tx_center_max[1][0][0] = 0
4617 09:53:26.788027 tx_center_min[1][0][1] = 0
4618 09:53:26.791336 tx_center_max[1][0][1] = 0
4619 09:53:26.794401 tx_center_min[1][1][0] = 0
4620 09:53:26.797942 tx_center_max[1][1][0] = 0
4621 09:53:26.798491 tx_center_min[1][1][1] = 0
4622 09:53:26.801819 tx_center_max[1][1][1] = 0
4623 09:53:26.804906 dump params tx window
4624 09:53:26.805419 tx_win_center[0][0][0] = 0
4625 09:53:26.807908 tx_first_pass[0][0][0] = 0
4626 09:53:26.811521 tx_last_pass[0][0][0] = 0
4627 09:53:26.814788 tx_win_center[0][0][1] = 0
4628 09:53:26.815306 tx_first_pass[0][0][1] = 0
4629 09:53:26.818154 tx_last_pass[0][0][1] = 0
4630 09:53:26.821373 tx_win_center[0][0][2] = 0
4631 09:53:26.824620 tx_first_pass[0][0][2] = 0
4632 09:53:26.825135 tx_last_pass[0][0][2] = 0
4633 09:53:26.827777 tx_win_center[0][0][3] = 0
4634 09:53:26.831023 tx_first_pass[0][0][3] = 0
4635 09:53:26.831451 tx_last_pass[0][0][3] = 0
4636 09:53:26.834888 tx_win_center[0][0][4] = 0
4637 09:53:26.838019 tx_first_pass[0][0][4] = 0
4638 09:53:26.841261 tx_last_pass[0][0][4] = 0
4639 09:53:26.841758 tx_win_center[0][0][5] = 0
4640 09:53:26.844673 tx_first_pass[0][0][5] = 0
4641 09:53:26.848279 tx_last_pass[0][0][5] = 0
4642 09:53:26.848799 tx_win_center[0][0][6] = 0
4643 09:53:26.851209 tx_first_pass[0][0][6] = 0
4644 09:53:26.854832 tx_last_pass[0][0][6] = 0
4645 09:53:26.857929 tx_win_center[0][0][7] = 0
4646 09:53:26.858470 tx_first_pass[0][0][7] = 0
4647 09:53:26.861749 tx_last_pass[0][0][7] = 0
4648 09:53:26.864835 tx_win_center[0][0][8] = 0
4649 09:53:26.867820 tx_first_pass[0][0][8] = 0
4650 09:53:26.868250 tx_last_pass[0][0][8] = 0
4651 09:53:26.871362 tx_win_center[0][0][9] = 0
4652 09:53:26.874624 tx_first_pass[0][0][9] = 0
4653 09:53:26.875140 tx_last_pass[0][0][9] = 0
4654 09:53:26.878245 tx_win_center[0][0][10] = 0
4655 09:53:26.881635 tx_first_pass[0][0][10] = 0
4656 09:53:26.884841 tx_last_pass[0][0][10] = 0
4657 09:53:26.885274 tx_win_center[0][0][11] = 0
4658 09:53:26.888272 tx_first_pass[0][0][11] = 0
4659 09:53:26.891762 tx_last_pass[0][0][11] = 0
4660 09:53:26.894764 tx_win_center[0][0][12] = 0
4661 09:53:26.895199 tx_first_pass[0][0][12] = 0
4662 09:53:26.898317 tx_last_pass[0][0][12] = 0
4663 09:53:26.901471 tx_win_center[0][0][13] = 0
4664 09:53:26.905052 tx_first_pass[0][0][13] = 0
4665 09:53:26.905570 tx_last_pass[0][0][13] = 0
4666 09:53:26.908266 tx_win_center[0][0][14] = 0
4667 09:53:26.911500 tx_first_pass[0][0][14] = 0
4668 09:53:26.914960 tx_last_pass[0][0][14] = 0
4669 09:53:26.915472 tx_win_center[0][0][15] = 0
4670 09:53:26.918156 tx_first_pass[0][0][15] = 0
4671 09:53:26.921630 tx_last_pass[0][0][15] = 0
4672 09:53:26.924821 tx_win_center[0][1][0] = 0
4673 09:53:26.925333 tx_first_pass[0][1][0] = 0
4674 09:53:26.927884 tx_last_pass[0][1][0] = 0
4675 09:53:26.931374 tx_win_center[0][1][1] = 0
4676 09:53:26.934651 tx_first_pass[0][1][1] = 0
4677 09:53:26.935083 tx_last_pass[0][1][1] = 0
4678 09:53:26.937907 tx_win_center[0][1][2] = 0
4679 09:53:26.941265 tx_first_pass[0][1][2] = 0
4680 09:53:26.941719 tx_last_pass[0][1][2] = 0
4681 09:53:26.944605 tx_win_center[0][1][3] = 0
4682 09:53:26.948217 tx_first_pass[0][1][3] = 0
4683 09:53:26.951827 tx_last_pass[0][1][3] = 0
4684 09:53:26.952346 tx_win_center[0][1][4] = 0
4685 09:53:26.954571 tx_first_pass[0][1][4] = 0
4686 09:53:26.957859 tx_last_pass[0][1][4] = 0
4687 09:53:26.961368 tx_win_center[0][1][5] = 0
4688 09:53:26.961888 tx_first_pass[0][1][5] = 0
4689 09:53:26.965042 tx_last_pass[0][1][5] = 0
4690 09:53:26.968287 tx_win_center[0][1][6] = 0
4691 09:53:26.968737 tx_first_pass[0][1][6] = 0
4692 09:53:26.971289 tx_last_pass[0][1][6] = 0
4693 09:53:26.974547 tx_win_center[0][1][7] = 0
4694 09:53:26.978043 tx_first_pass[0][1][7] = 0
4695 09:53:26.978518 tx_last_pass[0][1][7] = 0
4696 09:53:26.981457 tx_win_center[0][1][8] = 0
4697 09:53:26.984572 tx_first_pass[0][1][8] = 0
4698 09:53:26.985007 tx_last_pass[0][1][8] = 0
4699 09:53:26.988010 tx_win_center[0][1][9] = 0
4700 09:53:26.991506 tx_first_pass[0][1][9] = 0
4701 09:53:26.994829 tx_last_pass[0][1][9] = 0
4702 09:53:26.995264 tx_win_center[0][1][10] = 0
4703 09:53:26.998322 tx_first_pass[0][1][10] = 0
4704 09:53:27.001464 tx_last_pass[0][1][10] = 0
4705 09:53:27.004836 tx_win_center[0][1][11] = 0
4706 09:53:27.005268 tx_first_pass[0][1][11] = 0
4707 09:53:27.008371 tx_last_pass[0][1][11] = 0
4708 09:53:27.011466 tx_win_center[0][1][12] = 0
4709 09:53:27.014804 tx_first_pass[0][1][12] = 0
4710 09:53:27.015238 tx_last_pass[0][1][12] = 0
4711 09:53:27.018356 tx_win_center[0][1][13] = 0
4712 09:53:27.021739 tx_first_pass[0][1][13] = 0
4713 09:53:27.025031 tx_last_pass[0][1][13] = 0
4714 09:53:27.025544 tx_win_center[0][1][14] = 0
4715 09:53:27.028421 tx_first_pass[0][1][14] = 0
4716 09:53:27.031695 tx_last_pass[0][1][14] = 0
4717 09:53:27.034978 tx_win_center[0][1][15] = 0
4718 09:53:27.035496 tx_first_pass[0][1][15] = 0
4719 09:53:27.037921 tx_last_pass[0][1][15] = 0
4720 09:53:27.041352 tx_win_center[1][0][0] = 0
4721 09:53:27.044952 tx_first_pass[1][0][0] = 0
4722 09:53:27.045416 tx_last_pass[1][0][0] = 0
4723 09:53:27.047983 tx_win_center[1][0][1] = 0
4724 09:53:27.051525 tx_first_pass[1][0][1] = 0
4725 09:53:27.052048 tx_last_pass[1][0][1] = 0
4726 09:53:27.055067 tx_win_center[1][0][2] = 0
4727 09:53:27.058118 tx_first_pass[1][0][2] = 0
4728 09:53:27.061378 tx_last_pass[1][0][2] = 0
4729 09:53:27.061895 tx_win_center[1][0][3] = 0
4730 09:53:27.064833 tx_first_pass[1][0][3] = 0
4731 09:53:27.068405 tx_last_pass[1][0][3] = 0
4732 09:53:27.069206 tx_win_center[1][0][4] = 0
4733 09:53:27.071933 tx_first_pass[1][0][4] = 0
4734 09:53:27.074657 tx_last_pass[1][0][4] = 0
4735 09:53:27.078369 tx_win_center[1][0][5] = 0
4736 09:53:27.078798 tx_first_pass[1][0][5] = 0
4737 09:53:27.081935 tx_last_pass[1][0][5] = 0
4738 09:53:27.085332 tx_win_center[1][0][6] = 0
4739 09:53:27.088817 tx_first_pass[1][0][6] = 0
4740 09:53:27.089562 tx_last_pass[1][0][6] = 0
4741 09:53:27.091606 tx_win_center[1][0][7] = 0
4742 09:53:27.095225 tx_first_pass[1][0][7] = 0
4743 09:53:27.095742 tx_last_pass[1][0][7] = 0
4744 09:53:27.098569 tx_win_center[1][0][8] = 0
4745 09:53:27.102306 tx_first_pass[1][0][8] = 0
4746 09:53:27.105395 tx_last_pass[1][0][8] = 0
4747 09:53:27.105910 tx_win_center[1][0][9] = 0
4748 09:53:27.108802 tx_first_pass[1][0][9] = 0
4749 09:53:27.111957 tx_last_pass[1][0][9] = 0
4750 09:53:27.112475 tx_win_center[1][0][10] = 0
4751 09:53:27.114861 tx_first_pass[1][0][10] = 0
4752 09:53:27.118286 tx_last_pass[1][0][10] = 0
4753 09:53:27.122030 tx_win_center[1][0][11] = 0
4754 09:53:27.122591 tx_first_pass[1][0][11] = 0
4755 09:53:27.125394 tx_last_pass[1][0][11] = 0
4756 09:53:27.128263 tx_win_center[1][0][12] = 0
4757 09:53:27.132038 tx_first_pass[1][0][12] = 0
4758 09:53:27.132573 tx_last_pass[1][0][12] = 0
4759 09:53:27.135311 tx_win_center[1][0][13] = 0
4760 09:53:27.138313 tx_first_pass[1][0][13] = 0
4761 09:53:27.141909 tx_last_pass[1][0][13] = 0
4762 09:53:27.142550 tx_win_center[1][0][14] = 0
4763 09:53:27.145246 tx_first_pass[1][0][14] = 0
4764 09:53:27.148715 tx_last_pass[1][0][14] = 0
4765 09:53:27.151985 tx_win_center[1][0][15] = 0
4766 09:53:27.152516 tx_first_pass[1][0][15] = 0
4767 09:53:27.155157 tx_last_pass[1][0][15] = 0
4768 09:53:27.158509 tx_win_center[1][1][0] = 0
4769 09:53:27.161905 tx_first_pass[1][1][0] = 0
4770 09:53:27.162460 tx_last_pass[1][1][0] = 0
4771 09:53:27.164919 tx_win_center[1][1][1] = 0
4772 09:53:27.168650 tx_first_pass[1][1][1] = 0
4773 09:53:27.172050 tx_last_pass[1][1][1] = 0
4774 09:53:27.172566 tx_win_center[1][1][2] = 0
4775 09:53:27.175476 tx_first_pass[1][1][2] = 0
4776 09:53:27.178555 tx_last_pass[1][1][2] = 0
4777 09:53:27.178987 tx_win_center[1][1][3] = 0
4778 09:53:27.182154 tx_first_pass[1][1][3] = 0
4779 09:53:27.185272 tx_last_pass[1][1][3] = 0
4780 09:53:27.188436 tx_win_center[1][1][4] = 0
4781 09:53:27.188997 tx_first_pass[1][1][4] = 0
4782 09:53:27.191876 tx_last_pass[1][1][4] = 0
4783 09:53:27.195208 tx_win_center[1][1][5] = 0
4784 09:53:27.195734 tx_first_pass[1][1][5] = 0
4785 09:53:27.198568 tx_last_pass[1][1][5] = 0
4786 09:53:27.201681 tx_win_center[1][1][6] = 0
4787 09:53:27.205733 tx_first_pass[1][1][6] = 0
4788 09:53:27.206292 tx_last_pass[1][1][6] = 0
4789 09:53:27.208912 tx_win_center[1][1][7] = 0
4790 09:53:27.212612 tx_first_pass[1][1][7] = 0
4791 09:53:27.213228 tx_last_pass[1][1][7] = 0
4792 09:53:27.215233 tx_win_center[1][1][8] = 0
4793 09:53:27.218764 tx_first_pass[1][1][8] = 0
4794 09:53:27.221900 tx_last_pass[1][1][8] = 0
4795 09:53:27.222357 tx_win_center[1][1][9] = 0
4796 09:53:27.225687 tx_first_pass[1][1][9] = 0
4797 09:53:27.228780 tx_last_pass[1][1][9] = 0
4798 09:53:27.232220 tx_win_center[1][1][10] = 0
4799 09:53:27.232652 tx_first_pass[1][1][10] = 0
4800 09:53:27.235004 tx_last_pass[1][1][10] = 0
4801 09:53:27.238599 tx_win_center[1][1][11] = 0
4802 09:53:27.241866 tx_first_pass[1][1][11] = 0
4803 09:53:27.242350 tx_last_pass[1][1][11] = 0
4804 09:53:27.245759 tx_win_center[1][1][12] = 0
4805 09:53:27.249069 tx_first_pass[1][1][12] = 0
4806 09:53:27.252075 tx_last_pass[1][1][12] = 0
4807 09:53:27.252591 tx_win_center[1][1][13] = 0
4808 09:53:27.255293 tx_first_pass[1][1][13] = 0
4809 09:53:27.258538 tx_last_pass[1][1][13] = 0
4810 09:53:27.261931 tx_win_center[1][1][14] = 0
4811 09:53:27.262400 tx_first_pass[1][1][14] = 0
4812 09:53:27.265196 tx_last_pass[1][1][14] = 0
4813 09:53:27.268842 tx_win_center[1][1][15] = 0
4814 09:53:27.272443 tx_first_pass[1][1][15] = 0
4815 09:53:27.272961 tx_last_pass[1][1][15] = 0
4816 09:53:27.275612 dump params rx window
4817 09:53:27.278569 rx_firspass[0][0][0] = 0
4818 09:53:27.279002 rx_lastpass[0][0][0] = 0
4819 09:53:27.282035 rx_firspass[0][0][1] = 0
4820 09:53:27.285544 rx_lastpass[0][0][1] = 0
4821 09:53:27.285973 rx_firspass[0][0][2] = 0
4822 09:53:27.288849 rx_lastpass[0][0][2] = 0
4823 09:53:27.292141 rx_firspass[0][0][3] = 0
4824 09:53:27.292568 rx_lastpass[0][0][3] = 0
4825 09:53:27.295528 rx_firspass[0][0][4] = 0
4826 09:53:27.298807 rx_lastpass[0][0][4] = 0
4827 09:53:27.299234 rx_firspass[0][0][5] = 0
4828 09:53:27.302038 rx_lastpass[0][0][5] = 0
4829 09:53:27.305437 rx_firspass[0][0][6] = 0
4830 09:53:27.306141 rx_lastpass[0][0][6] = 0
4831 09:53:27.308695 rx_firspass[0][0][7] = 0
4832 09:53:27.312230 rx_lastpass[0][0][7] = 0
4833 09:53:27.315364 rx_firspass[0][0][8] = 0
4834 09:53:27.315794 rx_lastpass[0][0][8] = 0
4835 09:53:27.318854 rx_firspass[0][0][9] = 0
4836 09:53:27.322028 rx_lastpass[0][0][9] = 0
4837 09:53:27.322545 rx_firspass[0][0][10] = 0
4838 09:53:27.325697 rx_lastpass[0][0][10] = 0
4839 09:53:27.328748 rx_firspass[0][0][11] = 0
4840 09:53:27.329175 rx_lastpass[0][0][11] = 0
4841 09:53:27.331824 rx_firspass[0][0][12] = 0
4842 09:53:27.335382 rx_lastpass[0][0][12] = 0
4843 09:53:27.338895 rx_firspass[0][0][13] = 0
4844 09:53:27.339323 rx_lastpass[0][0][13] = 0
4845 09:53:27.342008 rx_firspass[0][0][14] = 0
4846 09:53:27.345383 rx_lastpass[0][0][14] = 0
4847 09:53:27.345810 rx_firspass[0][0][15] = 0
4848 09:53:27.348499 rx_lastpass[0][0][15] = 0
4849 09:53:27.352221 rx_firspass[0][1][0] = 0
4850 09:53:27.352648 rx_lastpass[0][1][0] = 0
4851 09:53:27.355185 rx_firspass[0][1][1] = 0
4852 09:53:27.358731 rx_lastpass[0][1][1] = 0
4853 09:53:27.362207 rx_firspass[0][1][2] = 0
4854 09:53:27.362764 rx_lastpass[0][1][2] = 0
4855 09:53:27.365315 rx_firspass[0][1][3] = 0
4856 09:53:27.368732 rx_lastpass[0][1][3] = 0
4857 09:53:27.369159 rx_firspass[0][1][4] = 0
4858 09:53:27.372132 rx_lastpass[0][1][4] = 0
4859 09:53:27.375586 rx_firspass[0][1][5] = 0
4860 09:53:27.376109 rx_lastpass[0][1][5] = 0
4861 09:53:27.378880 rx_firspass[0][1][6] = 0
4862 09:53:27.382343 rx_lastpass[0][1][6] = 0
4863 09:53:27.382869 rx_firspass[0][1][7] = 0
4864 09:53:27.385834 rx_lastpass[0][1][7] = 0
4865 09:53:27.389060 rx_firspass[0][1][8] = 0
4866 09:53:27.389587 rx_lastpass[0][1][8] = 0
4867 09:53:27.392332 rx_firspass[0][1][9] = 0
4868 09:53:27.395556 rx_lastpass[0][1][9] = 0
4869 09:53:27.398842 rx_firspass[0][1][10] = 0
4870 09:53:27.399367 rx_lastpass[0][1][10] = 0
4871 09:53:27.402299 rx_firspass[0][1][11] = 0
4872 09:53:27.405623 rx_lastpass[0][1][11] = 0
4873 09:53:27.406146 rx_firspass[0][1][12] = 0
4874 09:53:27.408614 rx_lastpass[0][1][12] = 0
4875 09:53:27.412117 rx_firspass[0][1][13] = 0
4876 09:53:27.415552 rx_lastpass[0][1][13] = 0
4877 09:53:27.416073 rx_firspass[0][1][14] = 0
4878 09:53:27.419032 rx_lastpass[0][1][14] = 0
4879 09:53:27.422500 rx_firspass[0][1][15] = 0
4880 09:53:27.423023 rx_lastpass[0][1][15] = 0
4881 09:53:27.425662 rx_firspass[1][0][0] = 0
4882 09:53:27.428633 rx_lastpass[1][0][0] = 0
4883 09:53:27.429064 rx_firspass[1][0][1] = 0
4884 09:53:27.432162 rx_lastpass[1][0][1] = 0
4885 09:53:27.435690 rx_firspass[1][0][2] = 0
4886 09:53:27.436202 rx_lastpass[1][0][2] = 0
4887 09:53:27.438849 rx_firspass[1][0][3] = 0
4888 09:53:27.441966 rx_lastpass[1][0][3] = 0
4889 09:53:27.445227 rx_firspass[1][0][4] = 0
4890 09:53:27.445672 rx_lastpass[1][0][4] = 0
4891 09:53:27.448865 rx_firspass[1][0][5] = 0
4892 09:53:27.452193 rx_lastpass[1][0][5] = 0
4893 09:53:27.452715 rx_firspass[1][0][6] = 0
4894 09:53:27.455332 rx_lastpass[1][0][6] = 0
4895 09:53:27.458680 rx_firspass[1][0][7] = 0
4896 09:53:27.459125 rx_lastpass[1][0][7] = 0
4897 09:53:27.461924 rx_firspass[1][0][8] = 0
4898 09:53:27.465534 rx_lastpass[1][0][8] = 0
4899 09:53:27.466054 rx_firspass[1][0][9] = 0
4900 09:53:27.468880 rx_lastpass[1][0][9] = 0
4901 09:53:27.472001 rx_firspass[1][0][10] = 0
4902 09:53:27.475287 rx_lastpass[1][0][10] = 0
4903 09:53:27.475733 rx_firspass[1][0][11] = 0
4904 09:53:27.478670 rx_lastpass[1][0][11] = 0
4905 09:53:27.482256 rx_firspass[1][0][12] = 0
4906 09:53:27.482800 rx_lastpass[1][0][12] = 0
4907 09:53:27.485457 rx_firspass[1][0][13] = 0
4908 09:53:27.488909 rx_lastpass[1][0][13] = 0
4909 09:53:27.489435 rx_firspass[1][0][14] = 0
4910 09:53:27.492517 rx_lastpass[1][0][14] = 0
4911 09:53:27.495806 rx_firspass[1][0][15] = 0
4912 09:53:27.499148 rx_lastpass[1][0][15] = 0
4913 09:53:27.499670 rx_firspass[1][1][0] = 0
4914 09:53:27.502318 rx_lastpass[1][1][0] = 0
4915 09:53:27.505584 rx_firspass[1][1][1] = 0
4916 09:53:27.506111 rx_lastpass[1][1][1] = 0
4917 09:53:27.508949 rx_firspass[1][1][2] = 0
4918 09:53:27.512636 rx_lastpass[1][1][2] = 0
4919 09:53:27.513161 rx_firspass[1][1][3] = 0
4920 09:53:27.515595 rx_lastpass[1][1][3] = 0
4921 09:53:27.518757 rx_firspass[1][1][4] = 0
4922 09:53:27.519248 rx_lastpass[1][1][4] = 0
4923 09:53:27.522447 rx_firspass[1][1][5] = 0
4924 09:53:27.525656 rx_lastpass[1][1][5] = 0
4925 09:53:27.526181 rx_firspass[1][1][6] = 0
4926 09:53:27.528669 rx_lastpass[1][1][6] = 0
4927 09:53:27.532334 rx_firspass[1][1][7] = 0
4928 09:53:27.535504 rx_lastpass[1][1][7] = 0
4929 09:53:27.536026 rx_firspass[1][1][8] = 0
4930 09:53:27.538886 rx_lastpass[1][1][8] = 0
4931 09:53:27.542394 rx_firspass[1][1][9] = 0
4932 09:53:27.542984 rx_lastpass[1][1][9] = 0
4933 09:53:27.545634 rx_firspass[1][1][10] = 0
4934 09:53:27.549213 rx_lastpass[1][1][10] = 0
4935 09:53:27.549736 rx_firspass[1][1][11] = 0
4936 09:53:27.552593 rx_lastpass[1][1][11] = 0
4937 09:53:27.555569 rx_firspass[1][1][12] = 0
4938 09:53:27.556015 rx_lastpass[1][1][12] = 0
4939 09:53:27.558933 rx_firspass[1][1][13] = 0
4940 09:53:27.562580 rx_lastpass[1][1][13] = 0
4941 09:53:27.565870 rx_firspass[1][1][14] = 0
4942 09:53:27.566434 rx_lastpass[1][1][14] = 0
4943 09:53:27.569151 rx_firspass[1][1][15] = 0
4944 09:53:27.572549 rx_lastpass[1][1][15] = 0
4945 09:53:27.573077 dump params clk_delay
4946 09:53:27.575552 clk_delay[0] = 0
4947 09:53:27.575997 clk_delay[1] = 0
4948 09:53:27.579067 dump params dqs_delay
4949 09:53:27.579589 dqs_delay[0][0] = 0
4950 09:53:27.582306 dqs_delay[0][1] = 0
4951 09:53:27.585799 dqs_delay[1][0] = 0
4952 09:53:27.586363 dqs_delay[1][1] = 0
4953 09:53:27.589001 dump params delay_cell_unit = 753
4954 09:53:27.592089 mt_set_emi_preloader end
4955 09:53:27.595996 [mt_mem_init] dram size: 0x100000000, rank number: 2
4956 09:53:27.599194 [complex_mem_test] start addr:0x40000000, len:20480
4957 09:53:27.637187 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
4958 09:53:27.643462 [complex_mem_test] start addr:0x80000000, len:20480
4959 09:53:27.679520 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
4960 09:53:27.686068 [complex_mem_test] start addr:0xc0000000, len:20480
4961 09:53:27.721728 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
4962 09:53:27.728139 [complex_mem_test] start addr:0x56000000, len:8192
4963 09:53:27.744772 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
4964 09:53:27.745293 ddr_geometry:1
4965 09:53:27.751498 [complex_mem_test] start addr:0x80000000, len:8192
4966 09:53:27.768759 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
4967 09:53:27.772615 dram_init: dram init end (result: 0)
4968 09:53:27.778651 Successfully loaded DRAM blobs and ran DRAM calibration
4969 09:53:27.788813 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
4970 09:53:27.789342 CBMEM:
4971 09:53:27.791941 IMD: root @ 00000000fffff000 254 entries.
4972 09:53:27.795367 IMD: root @ 00000000ffffec00 62 entries.
4973 09:53:27.801908 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
4974 09:53:27.808848 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
4975 09:53:27.812185 in-header: 03 a1 00 00 08 00 00 00
4976 09:53:27.815180 in-data: 84 60 60 10 00 00 00 00
4977 09:53:27.818739 Chrome EC: clear events_b mask to 0x0000000020004000
4978 09:53:27.825842 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
4979 09:53:27.829135 in-header: 03 fd 00 00 00 00 00 00
4980 09:53:27.829769 in-data:
4981 09:53:27.835679 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
4982 09:53:27.836193 CBFS @ 21000 size 3d4000
4983 09:53:27.842410 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
4984 09:53:27.845557 CBFS: Locating 'fallback/ramstage'
4985 09:53:27.848794 CBFS: Found @ offset 10d40 size d563
4986 09:53:27.870679 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
4987 09:53:27.882869 Accumulated console time in romstage 12648 ms
4988 09:53:27.883409
4989 09:53:27.883855
4990 09:53:27.892851 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
4991 09:53:27.896273 ARM64: Exception handlers installed.
4992 09:53:27.896801 ARM64: Testing exception
4993 09:53:27.899502 ARM64: Done test exception
4994 09:53:27.902859 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
4995 09:53:27.906666 Manufacturer: ef
4996 09:53:27.909611 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
4997 09:53:27.916262 WARNING: RO_VPD is uninitialized or empty.
4998 09:53:27.919542 FMAP: area RW_VPD found @ 550000 (16384 bytes)
4999 09:53:27.922775 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5000 09:53:27.932615 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5001 09:53:27.935497 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5002 09:53:27.942347 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5003 09:53:27.942864 Enumerating buses...
5004 09:53:27.949121 Show all devs... Before device enumeration.
5005 09:53:27.949638 Root Device: enabled 1
5006 09:53:27.952491 CPU_CLUSTER: 0: enabled 1
5007 09:53:27.953019 CPU: 00: enabled 1
5008 09:53:27.955553 Compare with tree...
5009 09:53:27.958914 Root Device: enabled 1
5010 09:53:27.959359 CPU_CLUSTER: 0: enabled 1
5011 09:53:27.962430 CPU: 00: enabled 1
5012 09:53:27.965929 Root Device scanning...
5013 09:53:27.966493 root_dev_scan_bus for Root Device
5014 09:53:27.969075 CPU_CLUSTER: 0 enabled
5015 09:53:27.972604 root_dev_scan_bus for Root Device done
5016 09:53:27.979211 scan_bus: scanning of bus Root Device took 10689 usecs
5017 09:53:27.979735 done
5018 09:53:27.982372 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5019 09:53:27.986006 Allocating resources...
5020 09:53:27.986569 Reading resources...
5021 09:53:27.989315 Root Device read_resources bus 0 link: 0
5022 09:53:27.996158 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5023 09:53:27.996681 CPU: 00 missing read_resources
5024 09:53:28.002386 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5025 09:53:28.005940 Root Device read_resources bus 0 link: 0 done
5026 09:53:28.006522 Done reading resources.
5027 09:53:28.012797 Show resources in subtree (Root Device)...After reading.
5028 09:53:28.016215 Root Device child on link 0 CPU_CLUSTER: 0
5029 09:53:28.019103 CPU_CLUSTER: 0 child on link 0 CPU: 00
5030 09:53:28.029504 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5031 09:53:28.030103 CPU: 00
5032 09:53:28.032869 Setting resources...
5033 09:53:28.035887 Root Device assign_resources, bus 0 link: 0
5034 09:53:28.039140 CPU_CLUSTER: 0 missing set_resources
5035 09:53:28.042574 Root Device assign_resources, bus 0 link: 0
5036 09:53:28.045935 Done setting resources.
5037 09:53:28.049225 Show resources in subtree (Root Device)...After assigning values.
5038 09:53:28.055944 Root Device child on link 0 CPU_CLUSTER: 0
5039 09:53:28.058838 CPU_CLUSTER: 0 child on link 0 CPU: 00
5040 09:53:28.065906 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5041 09:53:28.069103 CPU: 00
5042 09:53:28.069623 Done allocating resources.
5043 09:53:28.075942 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5044 09:53:28.076515 Enabling resources...
5045 09:53:28.079118 done.
5046 09:53:28.082700 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5047 09:53:28.086195 Initializing devices...
5048 09:53:28.086764 Root Device init ...
5049 09:53:28.089269 mainboard_init: Starting display init.
5050 09:53:28.092859 ADC[4]: Raw value=77032 ID=0
5051 09:53:28.115005 anx7625_power_on_init: Init interface.
5052 09:53:28.118657 anx7625_disable_pd_protocol: Disabled PD feature.
5053 09:53:28.125074 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5054 09:53:28.181942 anx7625_start_dp_work: Secure OCM version=00
5055 09:53:28.185397 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5056 09:53:28.202548 sp_tx_get_edid_block: EDID Block = 1
5057 09:53:28.320005 Extracted contents:
5058 09:53:28.323208 header: 00 ff ff ff ff ff ff 00
5059 09:53:28.326277 serial number: 06 af 5c 14 00 00 00 00 00 1a
5060 09:53:28.329855 version: 01 04
5061 09:53:28.333297 basic params: 95 1a 0e 78 02
5062 09:53:28.336515 chroma info: 99 85 95 55 56 92 28 22 50 54
5063 09:53:28.339631 established: 00 00 00
5064 09:53:28.343335 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5065 09:53:28.350114 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5066 09:53:28.356297 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5067 09:53:28.363196 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5068 09:53:28.369840 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5069 09:53:28.373469 extensions: 00
5070 09:53:28.373989 checksum: ae
5071 09:53:28.374375
5072 09:53:28.376674 Manufacturer: AUO Model 145c Serial Number 0
5073 09:53:28.380003 Made week 0 of 2016
5074 09:53:28.380543 EDID version: 1.4
5075 09:53:28.382951 Digital display
5076 09:53:28.386965 6 bits per primary color channel
5077 09:53:28.387497 DisplayPort interface
5078 09:53:28.389923 Maximum image size: 26 cm x 14 cm
5079 09:53:28.390499 Gamma: 220%
5080 09:53:28.393278 Check DPMS levels
5081 09:53:28.396903 Supported color formats: RGB 4:4:4
5082 09:53:28.400199 First detailed timing is preferred timing
5083 09:53:28.403623 Established timings supported:
5084 09:53:28.406698 Standard timings supported:
5085 09:53:28.407222 Detailed timings
5086 09:53:28.409977 Hex of detail: ce1d56ea50001a3030204600009010000018
5087 09:53:28.416820 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5088 09:53:28.419961 0556 0586 05a6 0640 hborder 0
5089 09:53:28.423194 0300 0304 030a 031a vborder 0
5090 09:53:28.426535 -hsync -vsync
5091 09:53:28.430103 Did detailed timing
5092 09:53:28.433306 Hex of detail: 0000000f0000000000000000000000000020
5093 09:53:28.436846 Manufacturer-specified data, tag 15
5094 09:53:28.439929 Hex of detail: 000000fe0041554f0a202020202020202020
5095 09:53:28.443264 ASCII string: AUO
5096 09:53:28.446539 Hex of detail: 000000fe004231313658414230312e34200a
5097 09:53:28.449800 ASCII string: B116XAB01.4
5098 09:53:28.450263 Checksum
5099 09:53:28.453287 Checksum: 0xae (valid)
5100 09:53:28.456861 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5101 09:53:28.459735 DSI data_rate: 457800000 bps
5102 09:53:28.466523 anx7625_parse_edid: set default k value to 0x3d for panel
5103 09:53:28.470129 anx7625_parse_edid: pixelclock(76300).
5104 09:53:28.473340 hactive(1366), hsync(32), hfp(48), hbp(154)
5105 09:53:28.476777 vactive(768), vsync(6), vfp(4), vbp(16)
5106 09:53:28.479790 anx7625_dsi_config: config dsi.
5107 09:53:28.487880 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5108 09:53:28.508962 anx7625_dsi_config: success to config DSI
5109 09:53:28.511999 anx7625_dp_start: MIPI phy setup OK.
5110 09:53:28.515357 [SSUSB] Setting up USB HOST controller...
5111 09:53:28.518954 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5112 09:53:28.522412 [SSUSB] phy power-on done.
5113 09:53:28.525886 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5114 09:53:28.529372 in-header: 03 fc 01 00 00 00 00 00
5115 09:53:28.529809 in-data:
5116 09:53:28.532571 handle_proto3_response: EC response with error code: 1
5117 09:53:28.535819 SPM: pcm index = 1
5118 09:53:28.539352 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5119 09:53:28.543033 CBFS @ 21000 size 3d4000
5120 09:53:28.549303 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5121 09:53:28.552605 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5122 09:53:28.556096 CBFS: Found @ offset 1e7c0 size 1026
5123 09:53:28.562664 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5124 09:53:28.566163 SPM: binary array size = 2988
5125 09:53:28.569708 SPM: version = pcm_allinone_v1.17.2_20180829
5126 09:53:28.572484 SPM binary loaded in 32 msecs
5127 09:53:28.580069 spm_kick_im_to_fetch: ptr = 000000004021eec2
5128 09:53:28.583412 spm_kick_im_to_fetch: len = 2988
5129 09:53:28.583924 SPM: spm_kick_pcm_to_run
5130 09:53:28.586732 SPM: spm_kick_pcm_to_run done
5131 09:53:28.589844 SPM: spm_init done in 52 msecs
5132 09:53:28.593246 Root Device init finished in 505265 usecs
5133 09:53:28.597116 CPU_CLUSTER: 0 init ...
5134 09:53:28.606910 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5135 09:53:28.610075 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5136 09:53:28.613467 CBFS @ 21000 size 3d4000
5137 09:53:28.616864 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5138 09:53:28.620055 CBFS: Locating 'sspm.bin'
5139 09:53:28.623121 CBFS: Found @ offset 208c0 size 41cb
5140 09:53:28.633032 read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps
5141 09:53:28.641210 CPU_CLUSTER: 0 init finished in 42799 usecs
5142 09:53:28.641723 Devices initialized
5143 09:53:28.644467 Show all devs... After init.
5144 09:53:28.647687 Root Device: enabled 1
5145 09:53:28.648123 CPU_CLUSTER: 0: enabled 1
5146 09:53:28.651023 CPU: 00: enabled 1
5147 09:53:28.654426 BS: BS_DEV_INIT times (ms): entry 0 run 234 exit 0
5148 09:53:28.657993 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5149 09:53:28.661184 ELOG: NV offset 0x558000 size 0x1000
5150 09:53:28.668717 read SPI 0x558000 0x1000: 1263 us, 3243 KB/s, 25.944 Mbps
5151 09:53:28.675546 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5152 09:53:28.678543 ELOG: Event(17) added with size 13 at 2024-06-18 09:53:27 UTC
5153 09:53:28.682035 out: cmd=0x121: 03 db 21 01 00 00 00 00
5154 09:53:28.685731 in-header: 03 28 00 00 2c 00 00 00
5155 09:53:28.699186 in-data: c3 48 00 00 00 00 00 00 02 10 00 00 06 80 00 00 09 1f 03 00 06 80 00 00 91 fe 00 00 06 80 00 00 07 ba 19 00 06 80 00 00 d0 f6 1a 00
5156 09:53:28.702191 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5157 09:53:28.705686 in-header: 03 19 00 00 08 00 00 00
5158 09:53:28.708782 in-data: a2 e0 47 00 13 00 00 00
5159 09:53:28.712535 Chrome EC: UHEPI supported
5160 09:53:28.719027 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5161 09:53:28.722142 in-header: 03 e1 00 00 08 00 00 00
5162 09:53:28.725480 in-data: 84 20 60 10 00 00 00 00
5163 09:53:28.728817 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5164 09:53:28.735513 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5165 09:53:28.739040 in-header: 03 e1 00 00 08 00 00 00
5166 09:53:28.742431 in-data: 84 20 60 10 00 00 00 00
5167 09:53:28.748949 ELOG: Event(A1) added with size 10 at 2024-06-18 09:53:28 UTC
5168 09:53:28.755437 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5169 09:53:28.758869 ELOG: Event(A0) added with size 9 at 2024-06-18 09:53:28 UTC
5170 09:53:28.762297 elog_add_boot_reason: Logged dev mode boot
5171 09:53:28.765724 Finalize devices...
5172 09:53:28.768889 Devices finalized
5173 09:53:28.772257 BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0
5174 09:53:28.775736 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5175 09:53:28.781987 ELOG: Event(91) added with size 10 at 2024-06-18 09:53:28 UTC
5176 09:53:28.785596 Writing coreboot table at 0xffeda000
5177 09:53:28.788745 0. 0000000000114000-000000000011efff: RAMSTAGE
5178 09:53:28.795464 1. 0000000040000000-000000004023cfff: RAMSTAGE
5179 09:53:28.798843 2. 000000004023d000-00000000545fffff: RAM
5180 09:53:28.802037 3. 0000000054600000-000000005465ffff: BL31
5181 09:53:28.805568 4. 0000000054660000-00000000ffed9fff: RAM
5182 09:53:28.811807 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5183 09:53:28.815137 6. 0000000100000000-000000013fffffff: RAM
5184 09:53:28.815657 Passing 5 GPIOs to payload:
5185 09:53:28.822016 NAME | PORT | POLARITY | VALUE
5186 09:53:28.825245 write protect | 0x00000096 | low | high
5187 09:53:28.832009 EC in RW | 0x000000b1 | high | undefined
5188 09:53:28.835462 EC interrupt | 0x00000097 | low | undefined
5189 09:53:28.838597 TPM interrupt | 0x00000099 | high | undefined
5190 09:53:28.845311 speaker enable | 0x000000af | high | undefined
5191 09:53:28.848515 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5192 09:53:28.852064 in-header: 03 f7 00 00 02 00 00 00
5193 09:53:28.852574 in-data: 04 00
5194 09:53:28.855347 Board ID: 4
5195 09:53:28.858714 ADC[3]: Raw value=1040656 ID=8
5196 09:53:28.859224 RAM code: 8
5197 09:53:28.859558 SKU ID: 16
5198 09:53:28.861807 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5199 09:53:28.865517 CBFS @ 21000 size 3d4000
5200 09:53:28.871939 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5201 09:53:28.878686 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 5eb1
5202 09:53:28.879205 coreboot table: 940 bytes.
5203 09:53:28.882568 IMD ROOT 0. 00000000fffff000 00001000
5204 09:53:28.885742 IMD SMALL 1. 00000000ffffe000 00001000
5205 09:53:28.892572 CONSOLE 2. 00000000fffde000 00020000
5206 09:53:28.895577 FMAP 3. 00000000fffdd000 0000047c
5207 09:53:28.899037 TIME STAMP 4. 00000000fffdc000 00000910
5208 09:53:28.902194 RAMOOPS 5. 00000000ffedc000 00100000
5209 09:53:28.905516 COREBOOT 6. 00000000ffeda000 00002000
5210 09:53:28.906028 IMD small region:
5211 09:53:28.912155 IMD ROOT 0. 00000000ffffec00 00000400
5212 09:53:28.915582 VBOOT WORK 1. 00000000ffffeb00 00000100
5213 09:53:28.919012 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5214 09:53:28.922187 VPD 3. 00000000ffffea60 0000006c
5215 09:53:28.925845 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5216 09:53:28.932230 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5217 09:53:28.935357 in-header: 03 e1 00 00 08 00 00 00
5218 09:53:28.939166 in-data: 84 20 60 10 00 00 00 00
5219 09:53:28.945650 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5220 09:53:28.946172 CBFS @ 21000 size 3d4000
5221 09:53:28.952316 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5222 09:53:28.955272 CBFS: Locating 'fallback/payload'
5223 09:53:28.962704 CBFS: Found @ offset dc040 size 439a0
5224 09:53:29.051005 read SPI 0xfd078 0x439a0: 84378 us, 3281 KB/s, 26.248 Mbps
5225 09:53:29.054269 Checking segment from ROM address 0x0000000040003a00
5226 09:53:29.060754 Checking segment from ROM address 0x0000000040003a1c
5227 09:53:29.064010 Loading segment from ROM address 0x0000000040003a00
5228 09:53:29.067673 code (compression=0)
5229 09:53:29.074240 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5230 09:53:29.084460 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5231 09:53:29.087791 it's not compressed!
5232 09:53:29.090769 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5233 09:53:29.097624 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5234 09:53:29.105396 Loading segment from ROM address 0x0000000040003a1c
5235 09:53:29.108561 Entry Point 0x0000000080000000
5236 09:53:29.109073 Loaded segments
5237 09:53:29.115084 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5238 09:53:29.118156 Jumping to boot code at 0000000080000000(00000000ffeda000)
5239 09:53:29.128615 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5240 09:53:29.131854 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5241 09:53:29.134972 CBFS @ 21000 size 3d4000
5242 09:53:29.141933 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5243 09:53:29.142513 CBFS: Locating 'fallback/bl31'
5244 09:53:29.145594 CBFS: Found @ offset 36dc0 size 5820
5245 09:53:29.159126 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5246 09:53:29.161983 Checking segment from ROM address 0x0000000040003a00
5247 09:53:29.169164 Checking segment from ROM address 0x0000000040003a1c
5248 09:53:29.172427 Loading segment from ROM address 0x0000000040003a00
5249 09:53:29.175404 code (compression=1)
5250 09:53:29.182310 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5251 09:53:29.191941 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5252 09:53:29.192442 using LZMA
5253 09:53:29.200859 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5254 09:53:29.207543 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5255 09:53:29.210984 Loading segment from ROM address 0x0000000040003a1c
5256 09:53:29.214379 Entry Point 0x0000000054601000
5257 09:53:29.214893 Loaded segments
5258 09:53:29.217817 NOTICE: MT8183 bl31_setup
5259 09:53:29.224695 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5260 09:53:29.228057 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5261 09:53:29.231390 INFO: [DEVAPC] dump DEVAPC registers:
5262 09:53:29.241273 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5263 09:53:29.248229 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5264 09:53:29.255048 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5265 09:53:29.264547 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5266 09:53:29.274999 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5267 09:53:29.281292 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5268 09:53:29.288247 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5269 09:53:29.298332 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5270 09:53:29.304972 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5271 09:53:29.314957 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5272 09:53:29.321682 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5273 09:53:29.331455 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5274 09:53:29.338194 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5275 09:53:29.345168 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5276 09:53:29.354680 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5277 09:53:29.361528 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5278 09:53:29.368108 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5279 09:53:29.374819 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5280 09:53:29.381664 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5281 09:53:29.391449 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5282 09:53:29.398055 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5283 09:53:29.404910 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5284 09:53:29.408433 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5285 09:53:29.411335 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5286 09:53:29.414541 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5287 09:53:29.417910 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5288 09:53:29.421465 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5289 09:53:29.427941 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5290 09:53:29.431080 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5291 09:53:29.434593 WARNING: region 0:
5292 09:53:29.438034 WARNING: apc:0x168, sa:0x0, ea:0xfff
5293 09:53:29.438622 WARNING: region 1:
5294 09:53:29.441150 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5295 09:53:29.444642 WARNING: region 2:
5296 09:53:29.448117 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5297 09:53:29.451144 WARNING: region 3:
5298 09:53:29.454470 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5299 09:53:29.454912 WARNING: region 4:
5300 09:53:29.457719 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5301 09:53:29.461104 WARNING: region 5:
5302 09:53:29.464318 WARNING: apc:0x0, sa:0x0, ea:0x0
5303 09:53:29.464758 WARNING: region 6:
5304 09:53:29.467901 WARNING: apc:0x0, sa:0x0, ea:0x0
5305 09:53:29.471381 WARNING: region 7:
5306 09:53:29.474818 WARNING: apc:0x0, sa:0x0, ea:0x0
5307 09:53:29.481363 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5308 09:53:29.484536 INFO: SPM: enable SPMC mode
5309 09:53:29.488226 NOTICE: spm_boot_init() start
5310 09:53:29.488758 NOTICE: spm_boot_init() end
5311 09:53:29.491592 INFO: BL31: Initializing runtime services
5312 09:53:29.498116 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5313 09:53:29.504738 INFO: BL31: Preparing for EL3 exit to normal world
5314 09:53:29.508265 INFO: Entry point address = 0x80000000
5315 09:53:29.508781 INFO: SPSR = 0x8
5316 09:53:29.531130
5317 09:53:29.531634
5318 09:53:29.531990
5319 09:53:29.533601 end: 2.2.3 depthcharge-start (duration 00:00:22) [common]
5320 09:53:29.534143 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
5321 09:53:29.534648 Setting prompt string to ['jacuzzi:']
5322 09:53:29.535046 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:28)
5323 09:53:29.535713 Starting depthcharge on Juniper...
5324 09:53:29.536067
5325 09:53:29.537835 vboot_handoff: creating legacy vboot_handoff structure
5326 09:53:29.538306
5327 09:53:29.541203 ec_init(0): CrosEC protocol v3 supported (544, 544)
5328 09:53:29.541790
5329 09:53:29.544543 Wipe memory regions:
5330 09:53:29.545050
5331 09:53:29.547731 [0x00000040000000, 0x00000054600000)
5332 09:53:29.590899
5333 09:53:29.591398 [0x00000054660000, 0x00000080000000)
5334 09:53:29.682001
5335 09:53:29.682725 [0x000000811994a0, 0x000000ffeda000)
5336 09:53:29.942403
5337 09:53:29.942998 [0x00000100000000, 0x00000140000000)
5338 09:53:30.074917
5339 09:53:30.078367 Initializing XHCI USB controller at 0x11200000.
5340 09:53:30.101459
5341 09:53:30.104618 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5342 09:53:30.105175
5343 09:53:30.105517
5344 09:53:30.106325 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5346 09:53:30.207540 jacuzzi: tftpboot 192.168.201.1 14407592/tftp-deploy-paprs7ub/kernel/image.itb 14407592/tftp-deploy-paprs7ub/kernel/cmdline
5347 09:53:30.208224 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5348 09:53:30.208654 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:28)
5349 09:53:30.213406 tftpboot 192.168.201.1 14407592/tftp-deploy-paprs7ub/kernel/image.itp-deploy-paprs7ub/kernel/cmdline
5350 09:53:30.213976
5351 09:53:30.214354 Waiting for link
5352 09:53:30.761708
5353 09:53:30.762258 R8152: Initializing
5354 09:53:30.762604
5355 09:53:30.764731 Version 9 (ocp_data = 6010)
5356 09:53:30.765162
5357 09:53:30.767989 R8152: Done initializing
5358 09:53:30.768413
5359 09:53:30.768740 Adding net device
5360 09:53:30.947586
5361 09:53:30.948093 R8152: Initializing
5362 09:53:30.948431
5363 09:53:30.950770 Version 9 (ocp_data = 6010)
5364 09:53:30.951277
5365 09:53:30.953816 R8152: Done initializing
5366 09:53:30.954375
5367 09:53:30.957354 net_add_device: Attemp to include the same device
5368 09:53:31.343640
5369 09:53:31.344149 done.
5370 09:53:31.344481
5371 09:53:31.344791 MAC: 00:e0:4c:68:03:2b
5372 09:53:31.345087
5373 09:53:31.346479 Sending DHCP discover... done.
5374 09:53:31.346902
5375 09:53:31.350038 Waiting for reply... done.
5376 09:53:31.350507
5377 09:53:31.353004 Sending DHCP request... done.
5378 09:53:31.353429
5379 09:53:31.359112 Waiting for reply... done.
5380 09:53:31.359583
5381 09:53:31.359950 My ip is 192.168.201.17
5382 09:53:31.360258
5383 09:53:31.362495 The DHCP server ip is 192.168.201.1
5384 09:53:31.362921
5385 09:53:31.368762 TFTP server IP predefined by user: 192.168.201.1
5386 09:53:31.369249
5387 09:53:31.375721 Bootfile predefined by user: 14407592/tftp-deploy-paprs7ub/kernel/image.itb
5388 09:53:31.376150
5389 09:53:31.376478 Sending tftp read request... done.
5390 09:53:31.376732
5391 09:53:31.384639 Waiting for the transfer...
5392 09:53:31.385045
5393 09:53:31.685486 00000000 ################################################################
5394 09:53:31.685610
5395 09:53:31.990943 00080000 ################################################################
5396 09:53:31.991075
5397 09:53:32.272082 00100000 ################################################################
5398 09:53:32.272203
5399 09:53:32.541360 00180000 ################################################################
5400 09:53:32.541480
5401 09:53:32.800544 00200000 ################################################################
5402 09:53:32.800673
5403 09:53:33.062292 00280000 ################################################################
5404 09:53:33.062438
5405 09:53:33.360614 00300000 ################################################################
5406 09:53:33.360738
5407 09:53:33.629073 00380000 ################################################################
5408 09:53:33.629192
5409 09:53:33.899683 00400000 ################################################################
5410 09:53:33.899806
5411 09:53:34.154961 00480000 ################################################################
5412 09:53:34.155078
5413 09:53:34.409624 00500000 ################################################################
5414 09:53:34.409747
5415 09:53:34.679945 00580000 ################################################################
5416 09:53:34.680074
5417 09:53:34.937147 00600000 ################################################################
5418 09:53:34.937262
5419 09:53:35.194099 00680000 ################################################################
5420 09:53:35.194284
5421 09:53:35.449698 00700000 ################################################################
5422 09:53:35.449816
5423 09:53:35.703480 00780000 ################################################################
5424 09:53:35.703601
5425 09:53:35.957576 00800000 ################################################################
5426 09:53:35.957705
5427 09:53:36.213467 00880000 ################################################################
5428 09:53:36.213587
5429 09:53:36.468292 00900000 ################################################################
5430 09:53:36.468410
5431 09:53:36.722215 00980000 ################################################################
5432 09:53:36.722340
5433 09:53:36.976917 00a00000 ################################################################
5434 09:53:36.977041
5435 09:53:37.231546 00a80000 ################################################################
5436 09:53:37.231664
5437 09:53:37.485545 00b00000 ################################################################
5438 09:53:37.485666
5439 09:53:37.739989 00b80000 ################################################################
5440 09:53:37.740105
5441 09:53:37.993634 00c00000 ################################################################
5442 09:53:37.993758
5443 09:53:38.246672 00c80000 ################################################################
5444 09:53:38.246818
5445 09:53:38.500544 00d00000 ################################################################
5446 09:53:38.500670
5447 09:53:38.755132 00d80000 ################################################################
5448 09:53:38.755252
5449 09:53:39.009859 00e00000 ################################################################
5450 09:53:39.009980
5451 09:53:39.264312 00e80000 ################################################################
5452 09:53:39.264429
5453 09:53:39.517663 00f00000 ################################################################
5454 09:53:39.517787
5455 09:53:39.772327 00f80000 ################################################################
5456 09:53:39.772453
5457 09:53:40.026499 01000000 ################################################################
5458 09:53:40.026621
5459 09:53:40.281817 01080000 ################################################################
5460 09:53:40.281940
5461 09:53:40.536102 01100000 ################################################################
5462 09:53:40.536224
5463 09:53:40.794402 01180000 ################################################################
5464 09:53:40.794530
5465 09:53:41.048731 01200000 ################################################################
5466 09:53:41.048854
5467 09:53:41.304140 01280000 ################################################################
5468 09:53:41.304263
5469 09:53:41.558986 01300000 ################################################################
5470 09:53:41.559108
5471 09:53:41.814331 01380000 ################################################################
5472 09:53:41.814456
5473 09:53:42.068423 01400000 ################################################################
5474 09:53:42.068551
5475 09:53:42.322938 01480000 ################################################################
5476 09:53:42.323057
5477 09:53:42.580543 01500000 ################################################################
5478 09:53:42.580666
5479 09:53:42.835842 01580000 ################################################################
5480 09:53:42.835962
5481 09:53:43.089142 01600000 ################################################################
5482 09:53:43.089273
5483 09:53:43.341590 01680000 ################################################################
5484 09:53:43.341711
5485 09:53:43.600166 01700000 ################################################################
5486 09:53:43.600304
5487 09:53:43.854679 01780000 ################################################################
5488 09:53:43.854809
5489 09:53:44.109710 01800000 ################################################################
5490 09:53:44.109836
5491 09:53:44.364918 01880000 ################################################################
5492 09:53:44.365036
5493 09:53:44.617533 01900000 ################################################################
5494 09:53:44.617657
5495 09:53:44.872163 01980000 ################################################################
5496 09:53:44.872286
5497 09:53:45.143838 01a00000 ################################################################
5498 09:53:45.143958
5499 09:53:45.400289 01a80000 ################################################################
5500 09:53:45.400410
5501 09:53:45.655911 01b00000 ################################################################
5502 09:53:45.656033
5503 09:53:45.908772 01b80000 ################################################################
5504 09:53:45.908895
5505 09:53:46.163457 01c00000 ################################################################
5506 09:53:46.163576
5507 09:53:46.418633 01c80000 ################################################################
5508 09:53:46.418755
5509 09:53:46.680757 01d00000 ################################################################
5510 09:53:46.680883
5511 09:53:46.948014 01d80000 ################################################################
5512 09:53:46.948140
5513 09:53:47.192150 01e00000 ########################################################## done.
5514 09:53:47.192276
5515 09:53:47.195722 The bootfile was 31928950 bytes long.
5516 09:53:47.195800
5517 09:53:47.198939 Sending tftp read request... done.
5518 09:53:47.199021
5519 09:53:47.202164 Waiting for the transfer...
5520 09:53:47.202262
5521 09:53:47.205665 00000000 # done.
5522 09:53:47.205754
5523 09:53:47.212408 Command line loaded dynamically from TFTP file: 14407592/tftp-deploy-paprs7ub/kernel/cmdline
5524 09:53:47.212584
5525 09:53:47.239173 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407592/extract-nfsrootfs-4guaw7ba,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5526 09:53:47.239439
5527 09:53:47.239592 Loading FIT.
5528 09:53:47.239732
5529 09:53:47.242331 Image ramdisk-1 has 18742486 bytes.
5530 09:53:47.242554
5531 09:53:47.246100 Image fdt-1 has 57695 bytes.
5532 09:53:47.246422
5533 09:53:47.249480 Image kernel-1 has 13126726 bytes.
5534 09:53:47.249830
5535 09:53:47.255953 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5536 09:53:47.256388
5537 09:53:47.269475 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5538 09:53:47.269983
5539 09:53:47.272635 Choosing best match conf-1 for compat google,juniper-sku16.
5540 09:53:47.276035
5541 09:53:47.279641 Connected to device vid:did:rid of 1ae0:0028:00
5542 09:53:47.290465
5543 09:53:47.293515 tpm_get_response: command 0x17b, return code 0x0
5544 09:53:47.293951
5545 09:53:47.297314 tpm_cleanup: add release locality here.
5546 09:53:47.297829
5547 09:53:47.300361 Shutting down all USB controllers.
5548 09:53:47.300794
5549 09:53:47.303922 Removing current net device
5550 09:53:47.304433
5551 09:53:47.307050 Exiting depthcharge with code 4 at timestamp: 33965899
5552 09:53:47.307490
5553 09:53:47.310394 LZMA decompressing kernel-1 to 0x80193568
5554 09:53:47.310830
5555 09:53:47.313613 LZMA decompressing kernel-1 to 0x40000000
5556 09:53:49.182530
5557 09:53:49.183053 jumping to kernel
5558 09:53:49.184777 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
5559 09:53:49.185293 start: 2.2.5 auto-login-action (timeout 00:04:09) [common]
5560 09:53:49.185674 Setting prompt string to ['Linux version [0-9]']
5561 09:53:49.186023 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5562 09:53:49.186416 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5563 09:53:49.257513
5564 09:53:49.261081 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5565 09:53:49.264698 start: 2.2.5.1 login-action (timeout 00:04:09) [common]
5566 09:53:49.265280 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5567 09:53:49.265665 Setting prompt string to []
5568 09:53:49.266056 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5569 09:53:49.266486 Using line separator: #'\n'#
5570 09:53:49.266800 No login prompt set.
5571 09:53:49.267117 Parsing kernel messages
5572 09:53:49.267406 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5573 09:53:49.267937 [login-action] Waiting for messages, (timeout 00:04:09)
5574 09:53:49.268272 Waiting using forced prompt support (timeout 00:02:04)
5575 09:53:49.283886 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
5576 09:53:49.287493 [ 0.000000] random: crng init done
5577 09:53:49.294176 [ 0.000000] Machine model: Google juniper sku16 board
5578 09:53:49.294343 [ 0.000000] efi: UEFI not found.
5579 09:53:49.304378 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5580 09:53:49.311014 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5581 09:53:49.321076 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5582 09:53:49.324234 [ 0.000000] printk: bootconsole [mtk8250] enabled
5583 09:53:49.332518 [ 0.000000] NUMA: No NUMA configuration found
5584 09:53:49.339201 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5585 09:53:49.346034 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5586 09:53:49.346597 [ 0.000000] Zone ranges:
5587 09:53:49.352614 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5588 09:53:49.355821 [ 0.000000] DMA32 empty
5589 09:53:49.362312 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5590 09:53:49.366142 [ 0.000000] Movable zone start for each node
5591 09:53:49.369651 [ 0.000000] Early memory node ranges
5592 09:53:49.376112 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5593 09:53:49.382829 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5594 09:53:49.389037 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5595 09:53:49.396236 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5596 09:53:49.402409 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5597 09:53:49.409420 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5598 09:53:49.425057 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5599 09:53:49.431708 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5600 09:53:49.438388 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5601 09:53:49.441562 [ 0.000000] psci: probing for conduit method from DT.
5602 09:53:49.448200 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5603 09:53:49.451539 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5604 09:53:49.457729 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5605 09:53:49.460958 [ 0.000000] psci: SMC Calling Convention v1.1
5606 09:53:49.467923 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5607 09:53:49.470992 [ 0.000000] Detected VIPT I-cache on CPU0
5608 09:53:49.477725 [ 0.000000] CPU features: detected: GIC system register CPU interface
5609 09:53:49.484324 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5610 09:53:49.490940 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5611 09:53:49.497567 [ 0.000000] CPU features: detected: ARM erratum 845719
5612 09:53:49.500985 [ 0.000000] alternatives: applying boot alternatives
5613 09:53:49.504289 [ 0.000000] Fallback order for Node 0: 0
5614 09:53:49.511010 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5615 09:53:49.514252 [ 0.000000] Policy zone: Normal
5616 09:53:49.540907 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407592/extract-nfsrootfs-4guaw7ba,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5617 09:53:49.554371 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5618 09:53:49.563938 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5619 09:53:49.570840 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5620 09:53:49.577097 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5621 09:53:49.583841 <6>[ 0.000000] software IO TLB: area num 8.
5622 09:53:49.608161 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5623 09:53:49.666332 <6>[ 0.000000] Memory: 3896768K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 261696K reserved, 32768K cma-reserved)
5624 09:53:49.673017 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5625 09:53:49.679665 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5626 09:53:49.683057 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5627 09:53:49.689865 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5628 09:53:49.696444 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5629 09:53:49.699755 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5630 09:53:49.709611 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5631 09:53:49.716312 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5632 09:53:49.719223 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5633 09:53:49.731270 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5634 09:53:49.737729 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5635 09:53:49.741407 <6>[ 0.000000] GICv3: 640 SPIs implemented
5636 09:53:49.744750 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5637 09:53:49.751356 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5638 09:53:49.754848 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5639 09:53:49.761288 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5640 09:53:49.774523 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5641 09:53:49.784632 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5642 09:53:49.790957 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5643 09:53:49.803108 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5644 09:53:49.816709 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5645 09:53:49.823023 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5646 09:53:49.829692 <6>[ 0.009469] Console: colour dummy device 80x25
5647 09:53:49.833143 <6>[ 0.014512] printk: console [tty1] enabled
5648 09:53:49.843196 <6>[ 0.018897] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5649 09:53:49.849779 <6>[ 0.029363] pid_max: default: 32768 minimum: 301
5650 09:53:49.853159 <6>[ 0.034244] LSM: Security Framework initializing
5651 09:53:49.863276 <6>[ 0.039159] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5652 09:53:49.870169 <6>[ 0.046783] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5653 09:53:49.876885 <4>[ 0.055657] cacheinfo: Unable to detect cache hierarchy for CPU 0
5654 09:53:49.886801 <6>[ 0.062285] cblist_init_generic: Setting adjustable number of callback queues.
5655 09:53:49.889969 <6>[ 0.069731] cblist_init_generic: Setting shift to 3 and lim to 1.
5656 09:53:49.899906 <6>[ 0.076083] cblist_init_generic: Setting adjustable number of callback queues.
5657 09:53:49.906547 <6>[ 0.083528] cblist_init_generic: Setting shift to 3 and lim to 1.
5658 09:53:49.909913 <6>[ 0.089926] rcu: Hierarchical SRCU implementation.
5659 09:53:49.916684 <6>[ 0.094953] rcu: Max phase no-delay instances is 1000.
5660 09:53:49.923584 <6>[ 0.102880] EFI services will not be available.
5661 09:53:49.926524 <6>[ 0.107827] smp: Bringing up secondary CPUs ...
5662 09:53:49.937560 <6>[ 0.113079] Detected VIPT I-cache on CPU1
5663 09:53:49.943951 <4>[ 0.113127] cacheinfo: Unable to detect cache hierarchy for CPU 1
5664 09:53:49.950334 <6>[ 0.113136] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5665 09:53:49.957280 <6>[ 0.113167] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5666 09:53:49.960423 <6>[ 0.113649] Detected VIPT I-cache on CPU2
5667 09:53:49.967151 <4>[ 0.113682] cacheinfo: Unable to detect cache hierarchy for CPU 2
5668 09:53:49.973665 <6>[ 0.113688] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5669 09:53:49.980316 <6>[ 0.113699] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5670 09:53:49.983779 <6>[ 0.114143] Detected VIPT I-cache on CPU3
5671 09:53:49.990078 <4>[ 0.114173] cacheinfo: Unable to detect cache hierarchy for CPU 3
5672 09:53:49.996940 <6>[ 0.114178] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5673 09:53:50.003384 <6>[ 0.114189] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5674 09:53:50.010523 <6>[ 0.114764] CPU features: detected: Spectre-v2
5675 09:53:50.013812 <6>[ 0.114774] CPU features: detected: Spectre-BHB
5676 09:53:50.020333 <6>[ 0.114778] CPU features: detected: ARM erratum 858921
5677 09:53:50.023971 <6>[ 0.114784] Detected VIPT I-cache on CPU4
5678 09:53:50.030599 <4>[ 0.114832] cacheinfo: Unable to detect cache hierarchy for CPU 4
5679 09:53:50.037262 <6>[ 0.114839] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5680 09:53:50.043654 <6>[ 0.114847] arch_timer: Enabling local workaround for ARM erratum 858921
5681 09:53:50.050292 <6>[ 0.114858] arch_timer: CPU4: Trapping CNTVCT access
5682 09:53:50.057100 <6>[ 0.114866] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5683 09:53:50.060375 <6>[ 0.115350] Detected VIPT I-cache on CPU5
5684 09:53:50.066745 <4>[ 0.115390] cacheinfo: Unable to detect cache hierarchy for CPU 5
5685 09:53:50.073657 <6>[ 0.115396] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5686 09:53:50.079956 <6>[ 0.115402] arch_timer: Enabling local workaround for ARM erratum 858921
5687 09:53:50.086770 <6>[ 0.115409] arch_timer: CPU5: Trapping CNTVCT access
5688 09:53:50.093665 <6>[ 0.115414] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5689 09:53:50.096962 <6>[ 0.115851] Detected VIPT I-cache on CPU6
5690 09:53:50.103455 <4>[ 0.115896] cacheinfo: Unable to detect cache hierarchy for CPU 6
5691 09:53:50.110301 <6>[ 0.115902] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5692 09:53:50.117330 <6>[ 0.115909] arch_timer: Enabling local workaround for ARM erratum 858921
5693 09:53:50.123796 <6>[ 0.115916] arch_timer: CPU6: Trapping CNTVCT access
5694 09:53:50.130755 <6>[ 0.115920] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5695 09:53:50.134114 <6>[ 0.116451] Detected VIPT I-cache on CPU7
5696 09:53:50.140869 <4>[ 0.116494] cacheinfo: Unable to detect cache hierarchy for CPU 7
5697 09:53:50.147041 <6>[ 0.116500] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5698 09:53:50.153756 <6>[ 0.116507] arch_timer: Enabling local workaround for ARM erratum 858921
5699 09:53:50.160588 <6>[ 0.116513] arch_timer: CPU7: Trapping CNTVCT access
5700 09:53:50.166951 <6>[ 0.116519] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5701 09:53:50.170205 <6>[ 0.116567] smp: Brought up 1 node, 8 CPUs
5702 09:53:50.177014 <6>[ 0.355467] SMP: Total of 8 processors activated.
5703 09:53:50.180420 <6>[ 0.360401] CPU features: detected: 32-bit EL0 Support
5704 09:53:50.187330 <6>[ 0.365779] CPU features: detected: 32-bit EL1 Support
5705 09:53:50.193696 <6>[ 0.371147] CPU features: detected: CRC32 instructions
5706 09:53:50.196757 <6>[ 0.376571] CPU: All CPU(s) started at EL2
5707 09:53:50.203713 <6>[ 0.380910] alternatives: applying system-wide alternatives
5708 09:53:50.206676 <6>[ 0.388900] devtmpfs: initialized
5709 09:53:50.221820 <6>[ 0.397850] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5710 09:53:50.231386 <6>[ 0.407799] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5711 09:53:50.235078 <6>[ 0.415524] pinctrl core: initialized pinctrl subsystem
5712 09:53:50.243323 <6>[ 0.422627] DMI not present or invalid.
5713 09:53:50.249788 <6>[ 0.426998] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5714 09:53:50.256701 <6>[ 0.433906] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5715 09:53:50.266302 <6>[ 0.441434] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5716 09:53:50.273363 <6>[ 0.449684] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5717 09:53:50.279669 <6>[ 0.457860] audit: initializing netlink subsys (disabled)
5718 09:53:50.286286 <5>[ 0.463563] audit: type=2000 audit(0.328:1): state=initialized audit_enabled=0 res=1
5719 09:53:50.292769 <6>[ 0.464527] thermal_sys: Registered thermal governor 'step_wise'
5720 09:53:50.299811 <6>[ 0.471530] thermal_sys: Registered thermal governor 'power_allocator'
5721 09:53:50.303103 <6>[ 0.477826] cpuidle: using governor menu
5722 09:53:50.309747 <6>[ 0.488788] NET: Registered PF_QIPCRTR protocol family
5723 09:53:50.316382 <6>[ 0.494285] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5724 09:53:50.322802 <6>[ 0.501380] ASID allocator initialised with 32768 entries
5725 09:53:50.326388 <6>[ 0.508143] Serial: AMBA PL011 UART driver
5726 09:53:50.339028 <4>[ 0.518546] Trying to register duplicate clock ID: 113
5727 09:53:50.398445 <6>[ 0.574742] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5728 09:53:50.413246 <6>[ 0.589077] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5729 09:53:50.416175 <6>[ 0.598840] KASLR enabled
5730 09:53:50.430871 <6>[ 0.606848] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5731 09:53:50.437621 <6>[ 0.613850] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5732 09:53:50.444217 <6>[ 0.620327] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5733 09:53:50.450942 <6>[ 0.627318] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5734 09:53:50.457450 <6>[ 0.633792] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5735 09:53:50.464062 <6>[ 0.640783] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5736 09:53:50.470506 <6>[ 0.647256] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5737 09:53:50.477455 <6>[ 0.654245] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5738 09:53:50.480629 <6>[ 0.661811] ACPI: Interpreter disabled.
5739 09:53:50.490494 <6>[ 0.669805] iommu: Default domain type: Translated
5740 09:53:50.496888 <6>[ 0.674910] iommu: DMA domain TLB invalidation policy: strict mode
5741 09:53:50.500222 <5>[ 0.681544] SCSI subsystem initialized
5742 09:53:50.506730 <6>[ 0.685957] usbcore: registered new interface driver usbfs
5743 09:53:50.513517 <6>[ 0.691684] usbcore: registered new interface driver hub
5744 09:53:50.516864 <6>[ 0.697226] usbcore: registered new device driver usb
5745 09:53:50.524240 <6>[ 0.703525] pps_core: LinuxPPS API ver. 1 registered
5746 09:53:50.534140 <6>[ 0.708710] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5747 09:53:50.537126 <6>[ 0.718034] PTP clock support registered
5748 09:53:50.540295 <6>[ 0.722287] EDAC MC: Ver: 3.0.0
5749 09:53:50.548540 <6>[ 0.727917] FPGA manager framework
5750 09:53:50.555091 <6>[ 0.731600] Advanced Linux Sound Architecture Driver Initialized.
5751 09:53:50.558326 <6>[ 0.738356] vgaarb: loaded
5752 09:53:50.564713 <6>[ 0.741486] clocksource: Switched to clocksource arch_sys_counter
5753 09:53:50.568250 <5>[ 0.747915] VFS: Disk quotas dquot_6.6.0
5754 09:53:50.575072 <6>[ 0.752090] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5755 09:53:50.578300 <6>[ 0.759264] pnp: PnP ACPI: disabled
5756 09:53:50.586902 <6>[ 0.766140] NET: Registered PF_INET protocol family
5757 09:53:50.593350 <6>[ 0.771362] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5758 09:53:50.605262 <6>[ 0.781267] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5759 09:53:50.611921 <6>[ 0.790020] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5760 09:53:50.621907 <6>[ 0.797971] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5761 09:53:50.628588 <6>[ 0.806206] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5762 09:53:50.634981 <6>[ 0.814301] TCP: Hash tables configured (established 32768 bind 32768)
5763 09:53:50.645247 <6>[ 0.821127] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5764 09:53:50.651963 <6>[ 0.828100] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5765 09:53:50.658456 <6>[ 0.835580] NET: Registered PF_UNIX/PF_LOCAL protocol family
5766 09:53:50.661913 <6>[ 0.841708] RPC: Registered named UNIX socket transport module.
5767 09:53:50.668581 <6>[ 0.847852] RPC: Registered udp transport module.
5768 09:53:50.671694 <6>[ 0.852776] RPC: Registered tcp transport module.
5769 09:53:50.678619 <6>[ 0.857700] RPC: Registered tcp NFSv4.1 backchannel transport module.
5770 09:53:50.685187 <6>[ 0.864352] PCI: CLS 0 bytes, default 64
5771 09:53:50.688276 <6>[ 0.868638] Unpacking initramfs...
5772 09:53:50.702029 <6>[ 0.878202] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
5773 09:53:50.712001 <6>[ 0.886826] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
5774 09:53:50.715023 <6>[ 0.895674] kvm [1]: IPA Size Limit: 40 bits
5775 09:53:50.722275 <6>[ 0.902005] kvm [1]: vgic-v2@c420000
5776 09:53:50.725783 <6>[ 0.905821] kvm [1]: GIC system register CPU interface enabled
5777 09:53:50.732446 <6>[ 0.912000] kvm [1]: vgic interrupt IRQ18
5778 09:53:50.735646 <6>[ 0.916364] kvm [1]: Hyp mode initialized successfully
5779 09:53:50.743494 <5>[ 0.922647] Initialise system trusted keyrings
5780 09:53:50.749673 <6>[ 0.927478] workingset: timestamp_bits=42 max_order=20 bucket_order=0
5781 09:53:50.758061 <6>[ 0.937389] squashfs: version 4.0 (2009/01/31) Phillip Lougher
5782 09:53:50.764566 <5>[ 0.943889] NFS: Registering the id_resolver key type
5783 09:53:50.768042 <5>[ 0.949197] Key type id_resolver registered
5784 09:53:50.774495 <5>[ 0.953609] Key type id_legacy registered
5785 09:53:50.781031 <6>[ 0.957916] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
5786 09:53:50.787704 <6>[ 0.964836] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
5787 09:53:50.794244 <6>[ 0.972629] 9p: Installing v9fs 9p2000 file system support
5788 09:53:50.822318 <5>[ 1.001736] Key type asymmetric registered
5789 09:53:50.825527 <5>[ 1.006080] Asymmetric key parser 'x509' registered
5790 09:53:50.835773 <6>[ 1.011241] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
5791 09:53:50.838790 <6>[ 1.018855] io scheduler mq-deadline registered
5792 09:53:50.842332 <6>[ 1.023614] io scheduler kyber registered
5793 09:53:50.864921 <6>[ 1.044436] EINJ: ACPI disabled.
5794 09:53:50.871424 <4>[ 1.048223] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
5795 09:53:50.909316 <6>[ 1.089074] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
5796 09:53:50.918061 <6>[ 1.097586] printk: console [ttyS0] disabled
5797 09:53:50.946288 <6>[ 1.122230] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
5798 09:53:50.952581 <6>[ 1.131715] printk: console [ttyS0] enabled
5799 09:53:50.955986 <6>[ 1.131715] printk: console [ttyS0] enabled
5800 09:53:50.962456 <6>[ 1.140636] printk: bootconsole [mtk8250] disabled
5801 09:53:50.965582 <6>[ 1.140636] printk: bootconsole [mtk8250] disabled
5802 09:53:50.975966 <3>[ 1.151177] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
5803 09:53:50.982569 <3>[ 1.159559] mt6577-uart 11003000.serial: Error applying setting, reverse things back
5804 09:53:51.012159 <6>[ 1.187974] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
5805 09:53:51.018482 <6>[ 1.197632] serial serial0: tty port ttyS1 registered
5806 09:53:51.025279 <6>[ 1.204200] SuperH (H)SCI(F) driver initialized
5807 09:53:51.028431 <6>[ 1.209716] msm_serial: driver initialized
5808 09:53:51.043653 <6>[ 1.220040] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
5809 09:53:51.054044 <6>[ 1.228641] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
5810 09:53:51.060572 <6>[ 1.237222] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
5811 09:53:51.070578 <6>[ 1.245795] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
5812 09:53:51.077419 <6>[ 1.254449] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
5813 09:53:51.087052 <6>[ 1.263109] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
5814 09:53:51.097307 <6>[ 1.271847] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
5815 09:53:51.103795 <6>[ 1.280585] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
5816 09:53:51.113642 <6>[ 1.289163] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
5817 09:53:51.123508 <6>[ 1.297968] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
5818 09:53:51.131059 <4>[ 1.310356] cacheinfo: Unable to detect cache hierarchy for CPU 0
5819 09:53:51.140262 <6>[ 1.319713] loop: module loaded
5820 09:53:51.152262 <6>[ 1.331648] vsim1: Bringing 1800000uV into 2700000-2700000uV
5821 09:53:51.170408 <6>[ 1.349710] megasas: 07.719.03.00-rc1
5822 09:53:51.179094 <6>[ 1.358484] spi-nor spi1.0: w25q64dw (8192 Kbytes)
5823 09:53:51.193418 <6>[ 1.372890] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
5824 09:53:51.210432 <6>[ 1.389666] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
5825 09:53:51.266591 <6>[ 1.439528] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b8
5826 09:53:51.298781 <6>[ 1.478401] Freeing initrd memory: 18296K
5827 09:53:51.314365 <4>[ 1.490251] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
5828 09:53:51.320882 <4>[ 1.499483] CPU: 5 PID: 1 Comm: swapper/0 Not tainted 6.1.92-cip22 #1
5829 09:53:51.327540 <4>[ 1.506181] Hardware name: Google juniper sku16 board (DT)
5830 09:53:51.331211 <4>[ 1.511920] Call trace:
5831 09:53:51.334396 <4>[ 1.514620] dump_backtrace.part.0+0xe0/0xf0
5832 09:53:51.337480 <4>[ 1.519157] show_stack+0x18/0x30
5833 09:53:51.340869 <4>[ 1.522729] dump_stack_lvl+0x68/0x84
5834 09:53:51.344527 <4>[ 1.526650] dump_stack+0x18/0x34
5835 09:53:51.350908 <4>[ 1.530220] sysfs_warn_dup+0x64/0x80
5836 09:53:51.354188 <4>[ 1.534142] sysfs_do_create_link_sd+0xf0/0x100
5837 09:53:51.357712 <4>[ 1.538929] sysfs_create_link+0x20/0x40
5838 09:53:51.363999 <4>[ 1.543109] bus_add_device+0x68/0x10c
5839 09:53:51.367322 <4>[ 1.547115] device_add+0x340/0x7ac
5840 09:53:51.371037 <4>[ 1.550858] of_device_add+0x44/0x60
5841 09:53:51.374956 <4>[ 1.554691] of_platform_device_create_pdata+0x90/0x120
5842 09:53:51.380877 <4>[ 1.560173] of_platform_bus_create+0x170/0x370
5843 09:53:51.384486 <4>[ 1.564959] of_platform_populate+0x50/0xfc
5844 09:53:51.390847 <4>[ 1.569399] parse_mtd_partitions+0x1dc/0x510
5845 09:53:51.394354 <4>[ 1.574012] mtd_device_parse_register+0xf8/0x2e0
5846 09:53:51.397285 <4>[ 1.578970] spi_nor_probe+0x21c/0x2f0
5847 09:53:51.401200 <4>[ 1.582977] spi_mem_probe+0x6c/0xb0
5848 09:53:51.404310 <4>[ 1.586809] spi_probe+0x84/0xe4
5849 09:53:51.410669 <4>[ 1.590291] really_probe+0xbc/0x2e0
5850 09:53:51.414294 <4>[ 1.594121] __driver_probe_device+0x78/0x11c
5851 09:53:51.417530 <4>[ 1.598733] driver_probe_device+0xd8/0x160
5852 09:53:51.424229 <4>[ 1.603171] __device_attach_driver+0xb8/0x134
5853 09:53:51.427639 <4>[ 1.607870] bus_for_each_drv+0x78/0xd0
5854 09:53:51.431197 <4>[ 1.611960] __device_attach+0xa8/0x1c0
5855 09:53:51.437703 <4>[ 1.616050] device_initial_probe+0x14/0x20
5856 09:53:51.441110 <4>[ 1.620488] bus_probe_device+0x9c/0xa4
5857 09:53:51.444492 <4>[ 1.624579] device_add+0x3ac/0x7ac
5858 09:53:51.447914 <4>[ 1.628321] __spi_add_device+0x78/0x120
5859 09:53:51.450962 <4>[ 1.632499] spi_add_device+0x40/0x7c
5860 09:53:51.457965 <4>[ 1.636416] spi_register_controller+0x610/0xad0
5861 09:53:51.461011 <4>[ 1.641289] devm_spi_register_controller+0x4c/0xa4
5862 09:53:51.464348 <4>[ 1.646422] mtk_spi_probe+0x3f8/0x650
5863 09:53:51.471066 <4>[ 1.650426] platform_probe+0x68/0xe0
5864 09:53:51.474392 <4>[ 1.654345] really_probe+0xbc/0x2e0
5865 09:53:51.477930 <4>[ 1.658175] __driver_probe_device+0x78/0x11c
5866 09:53:51.481604 <4>[ 1.662786] driver_probe_device+0xd8/0x160
5867 09:53:51.487747 <4>[ 1.667224] __driver_attach+0x94/0x19c
5868 09:53:51.491098 <4>[ 1.671314] bus_for_each_dev+0x70/0xd0
5869 09:53:51.494922 <4>[ 1.675404] driver_attach+0x24/0x30
5870 09:53:51.497775 <4>[ 1.679234] bus_add_driver+0x154/0x20c
5871 09:53:51.504446 <4>[ 1.683324] driver_register+0x78/0x130
5872 09:53:51.507729 <4>[ 1.687415] __platform_driver_register+0x28/0x34
5873 09:53:51.511260 <4>[ 1.692374] mtk_spi_driver_init+0x1c/0x28
5874 09:53:51.518026 <4>[ 1.696728] do_one_initcall+0x50/0x1d0
5875 09:53:51.521395 <4>[ 1.700818] kernel_init_freeable+0x21c/0x288
5876 09:53:51.524548 <4>[ 1.705432] kernel_init+0x24/0x12c
5877 09:53:51.527755 <4>[ 1.709177] ret_from_fork+0x10/0x20
5878 09:53:51.538539 <6>[ 1.718091] tun: Universal TUN/TAP device driver, 1.6
5879 09:53:51.542364 <6>[ 1.724378] thunder_xcv, ver 1.0
5880 09:53:51.545684 <6>[ 1.727892] thunder_bgx, ver 1.0
5881 09:53:51.549009 <6>[ 1.731398] nicpf, ver 1.0
5882 09:53:51.559697 <6>[ 1.735776] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
5883 09:53:51.563175 <6>[ 1.743260] hns3: Copyright (c) 2017 Huawei Corporation.
5884 09:53:51.566170 <6>[ 1.748867] hclge is initializing
5885 09:53:51.573161 <6>[ 1.752453] e1000: Intel(R) PRO/1000 Network Driver
5886 09:53:51.579756 <6>[ 1.757588] e1000: Copyright (c) 1999-2006 Intel Corporation.
5887 09:53:51.583120 <6>[ 1.763611] e1000e: Intel(R) PRO/1000 Network Driver
5888 09:53:51.589732 <6>[ 1.768832] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
5889 09:53:51.596595 <6>[ 1.775025] igb: Intel(R) Gigabit Ethernet Network Driver
5890 09:53:51.603191 <6>[ 1.780680] igb: Copyright (c) 2007-2014 Intel Corporation.
5891 09:53:51.609985 <6>[ 1.786522] igbvf: Intel(R) Gigabit Virtual Function Network Driver
5892 09:53:51.616433 <6>[ 1.793045] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
5893 09:53:51.619744 <6>[ 1.799599] sky2: driver version 1.30
5894 09:53:51.626560 <6>[ 1.804845] usbcore: registered new device driver r8152-cfgselector
5895 09:53:51.633536 <6>[ 1.811390] usbcore: registered new interface driver r8152
5896 09:53:51.639717 <6>[ 1.817222] VFIO - User Level meta-driver version: 0.3
5897 09:53:51.646313 <6>[ 1.825021] mtu3 11201000.usb: uwk - reg:0x420, version:101
5898 09:53:51.653008 <4>[ 1.830895] mtu3 11201000.usb: supply vbus not found, using dummy regulator
5899 09:53:51.659871 <6>[ 1.838165] mtu3 11201000.usb: dr_mode: 1, drd: auto
5900 09:53:51.663345 <6>[ 1.843390] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
5901 09:53:51.670348 <6>[ 1.849572] mtu3 11201000.usb: usb3-drd: 0
5902 09:53:51.676450 <6>[ 1.855121] mtu3 11201000.usb: xHCI platform device register success...
5903 09:53:51.687630 <4>[ 1.863739] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
5904 09:53:51.694022 <6>[ 1.871703] xhci-mtk 11200000.usb: xHCI Host Controller
5905 09:53:51.700661 <6>[ 1.877215] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
5906 09:53:51.707506 <6>[ 1.884937] xhci-mtk 11200000.usb: USB3 root hub has no ports
5907 09:53:51.714307 <6>[ 1.890945] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
5908 09:53:51.720918 <6>[ 1.900393] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
5909 09:53:51.727943 <6>[ 1.906477] xhci-mtk 11200000.usb: xHCI Host Controller
5910 09:53:51.734289 <6>[ 1.911966] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
5911 09:53:51.741067 <6>[ 1.919623] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
5912 09:53:51.744104 <6>[ 1.926441] hub 1-0:1.0: USB hub found
5913 09:53:51.750839 <6>[ 1.930477] hub 1-0:1.0: 1 port detected
5914 09:53:51.761195 <6>[ 1.935834] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
5915 09:53:51.764318 <6>[ 1.944444] hub 2-0:1.0: USB hub found
5916 09:53:51.770915 <3>[ 1.948472] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
5917 09:53:51.777941 <6>[ 1.956359] usbcore: registered new interface driver usb-storage
5918 09:53:51.784344 <6>[ 1.962970] usbcore: registered new device driver onboard-usb-hub
5919 09:53:51.801693 <4>[ 1.977596] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
5920 09:53:51.810539 <6>[ 1.989859] mt6397-rtc mt6358-rtc: registered as rtc0
5921 09:53:51.820646 <6>[ 1.995339] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-18T09:53:51 UTC (1718704431)
5922 09:53:51.823795 <6>[ 2.005229] i2c_dev: i2c /dev entries driver
5923 09:53:51.835655 <6>[ 2.011643] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5924 09:53:51.845669 <6>[ 2.020023] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5925 09:53:51.849084 <6>[ 2.028930] i2c 4-0058: Fixed dependency cycle(s) with /panel
5926 09:53:51.858991 <6>[ 2.034998] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
5927 09:53:51.865397 <3>[ 2.042447] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
5928 09:53:51.883197 <6>[ 2.062455] cpu cpu0: EM: created perf domain
5929 09:53:51.893002 <6>[ 2.067932] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
5930 09:53:51.899562 <6>[ 2.079243] cpu cpu4: EM: created perf domain
5931 09:53:51.906498 <6>[ 2.086352] sdhci: Secure Digital Host Controller Interface driver
5932 09:53:51.913291 <6>[ 2.092810] sdhci: Copyright(c) Pierre Ossman
5933 09:53:51.919981 <6>[ 2.098225] Synopsys Designware Multimedia Card Interface Driver
5934 09:53:51.926369 <6>[ 2.098729] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
5935 09:53:51.930010 <6>[ 2.105289] sdhci-pltfm: SDHCI platform and OF driver helper
5936 09:53:51.938238 <6>[ 2.117977] ledtrig-cpu: registered to indicate activity on CPUs
5937 09:53:51.945995 <6>[ 2.125749] usbcore: registered new interface driver usbhid
5938 09:53:51.949372 <6>[ 2.131587] usbhid: USB HID core driver
5939 09:53:51.960362 <6>[ 2.135853] spi_master spi2: will run message pump with realtime priority
5940 09:53:51.964380 <4>[ 2.135853] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
5941 09:53:51.971065 <4>[ 2.135907] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
5942 09:53:51.984495 <6>[ 2.154235] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
5943 09:53:52.005887 <6>[ 2.175186] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
5944 09:53:52.012266 <4>[ 2.183090] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
5945 09:53:52.018939 <6>[ 2.196301] cros-ec-spi spi2.0: Chrome EC device registered
5946 09:53:52.025597 <4>[ 2.203419] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
5947 09:53:52.039021 <4>[ 2.215258] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
5948 09:53:52.045718 <4>[ 2.224444] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
5949 09:53:52.058857 <6>[ 2.234893] mmc1: new ultra high speed SDR104 SDIO card at address 0001
5950 09:53:52.079294 <6>[ 2.258622] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x11c14
5951 09:53:52.085648 <6>[ 2.264968] mmc0: new HS400 MMC card at address 0001
5952 09:53:52.092378 <6>[ 2.271189] mmcblk0: mmc0:0001 TB2932 29.2 GiB
5953 09:53:52.101401 <6>[ 2.280625] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
5954 09:53:52.111049 <6>[ 2.283136] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
5955 09:53:52.114403 <6>[ 2.288717] mmcblk0boot0: mmc0:0001 TB2932 4.00 MiB
5956 09:53:52.127641 <6>[ 2.298954] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
5957 09:53:52.137913 <6>[ 2.305258] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
5958 09:53:52.144461 <6>[ 2.312337] mmcblk0boot1: mmc0:0001 TB2932 4.00 MiB
5959 09:53:52.147699 <6>[ 2.313450] NET: Registered PF_PACKET protocol family
5960 09:53:52.154536 <6>[ 2.313606] 9pnet: Installing 9P2000 support
5961 09:53:52.157855 <5>[ 2.313656] Key type dns_resolver registered
5962 09:53:52.161356 <6>[ 2.314114] registered taskstats version 1
5963 09:53:52.167863 <5>[ 2.314136] Loading compiled-in X.509 certificates
5964 09:53:52.177756 <6>[ 2.324230] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
5965 09:53:52.184555 <6>[ 2.329877] mmcblk0rpmb: mmc0:0001 TB2932 4.00 MiB, chardev (507:0)
5966 09:53:52.191148 <6>[ 2.368903] usb 1-1: new high-speed USB device number 2 using xhci-mtk
5967 09:53:52.201200 <3>[ 2.374950] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
5968 09:53:52.224905 <6>[ 2.398042] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
5969 09:53:52.235022 <6>[ 2.411229] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
5970 09:53:52.245099 <6>[ 2.419806] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
5971 09:53:52.251587 <6>[ 2.428329] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
5972 09:53:52.261782 <6>[ 2.436849] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
5973 09:53:52.268261 <6>[ 2.445368] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
5974 09:53:52.278306 <6>[ 2.453885] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
5975 09:53:52.284751 <6>[ 2.462403] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
5976 09:53:52.292025 <6>[ 2.471614] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
5977 09:53:52.299754 <6>[ 2.479129] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
5978 09:53:52.306904 <6>[ 2.486450] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
5979 09:53:52.317421 <6>[ 2.493755] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
5980 09:53:52.324331 <6>[ 2.501223] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
5981 09:53:52.330958 <6>[ 2.509580] panfrost 13040000.gpu: clock rate = 511999970
5982 09:53:52.341036 <6>[ 2.515266] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
5983 09:53:52.344255 <6>[ 2.524396] hub 1-1:1.0: USB hub found
5984 09:53:52.350863 <6>[ 2.525400] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
5985 09:53:52.357375 <6>[ 2.529368] hub 1-1:1.0: 3 ports detected
5986 09:53:52.364336 <6>[ 2.536823] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
5987 09:53:52.377862 <6>[ 2.549524] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
5988 09:53:52.384124 <6>[ 2.561601] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
5989 09:53:52.395978 <6>[ 2.572038] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
5990 09:53:52.405977 <6>[ 2.580962] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
5991 09:53:52.415777 <6>[ 2.590113] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
5992 09:53:52.422748 <6>[ 2.599242] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
5993 09:53:52.432481 <6>[ 2.608370] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
5994 09:53:52.442680 <6>[ 2.617670] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
5995 09:53:52.452563 <6>[ 2.626971] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
5996 09:53:52.462348 <6>[ 2.636446] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
5997 09:53:52.468859 <6>[ 2.645920] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
5998 09:53:52.478823 <6>[ 2.655046] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
5999 09:53:52.555162 <6>[ 2.730957] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6000 09:53:52.564746 <6>[ 2.739857] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6001 09:53:52.576251 <6>[ 2.752283] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6002 09:53:52.653391 <6>[ 2.829523] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
6003 09:53:53.276968 <6>[ 2.934779] hub 1-1.1:1.0: USB hub found
6004 09:53:53.280079 <6>[ 2.934844] hub 1-1.1:1.0: 4 ports detected
6005 09:53:53.286593 <6>[ 3.439561] Console: switching to colour frame buffer device 170x48
6006 09:53:53.296268 <6>[ 3.471723] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6007 09:53:53.315153 <6>[ 3.488050] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6008 09:53:53.334768 <6>[ 3.507612] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6009 09:53:53.341564 <6>[ 3.520122] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6010 09:53:53.353287 <6>[ 3.529533] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6011 09:53:53.363570 <6>[ 3.534618] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6012 09:53:53.381158 <6>[ 3.553928] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6013 09:53:53.388037 <6>[ 3.561518] usb 1-1.2: new high-speed USB device number 4 using xhci-mtk
6014 09:53:53.394716 <6>[ 3.565252] Trying to probe devices needed for running init ...
6015 09:53:53.405803 <3>[ 3.581845] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: could not get audiosys reset:-517
6016 09:53:53.419697 <6>[ 3.592846] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6017 09:53:53.573551 <6>[ 3.749702] r8152-cfgselector 1-1.2: reset high-speed USB device number 4 using xhci-mtk
6018 09:53:53.685482 <4>[ 3.861233] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6019 09:53:53.694949 <4>[ 3.870507] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6020 09:53:53.734888 <6>[ 3.914262] r8152 1-1.2:1.0 eth0: v1.12.13
6021 09:53:53.754726 <6>[ 3.927523] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6022 09:53:53.764961 <6>[ 3.941133] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
6023 09:53:53.953508 <6>[ 4.129515] usb 1-1.3: new high-speed USB device number 6 using xhci-mtk
6024 09:53:54.093647 <6>[ 4.266395] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6025 09:53:54.146145 <6>[ 4.322132] r8152-cfgselector 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
6026 09:53:54.274658 <4>[ 4.450714] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6027 09:53:54.287669 <4>[ 4.463683] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6028 09:53:54.344120 <6>[ 4.523627] r8152 1-1.1.1:1.0 eth1: v1.12.13
6029 09:53:54.369830 <6>[ 4.542416] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6030 09:53:55.337103 <6>[ 5.516430] r8152 1-1.2:1.0 eth0: carrier on
6031 09:53:57.485838 <5>[ 5.545520] Sending DHCP requests .., OK
6032 09:53:57.498746 <6>[ 7.674826] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.17
6033 09:53:57.508606 <6>[ 7.688145] IP-Config: Complete:
6034 09:53:57.523790 <6>[ 7.696575] device=eth0, hwaddr=00:e0:4c:68:03:2b, ipaddr=192.168.201.17, mask=255.255.255.0, gw=192.168.201.1
6035 09:53:57.536531 <6>[ 7.712395] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-5, domain=lava-rack, nis-domain=(none)
6036 09:53:57.549951 <6>[ 7.725713] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6037 09:53:57.557170 <6>[ 7.725721] nameserver0=192.168.201.1
6038 09:53:57.588978 <6>[ 7.768203] clk: Disabling unused clocks
6039 09:53:57.595851 <6>[ 7.778255] ALSA device list:
6040 09:53:57.603953 <6>[ 7.783420] No soundcards found.
6041 09:53:57.611939 <6>[ 7.791312] Freeing unused kernel memory: 8512K
6042 09:53:57.618898 <6>[ 7.798201] Run /init as init process
6043 09:53:57.628666 Loading, please wait...
6044 09:53:57.659022 Starting systemd-udevd version 252.22-1~deb12u1
6045 09:53:57.977347 <6>[ 8.152957] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6046 09:53:57.994570 <4>[ 8.170125] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6047 09:53:58.006377 <6>[ 8.181981] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6048 09:53:58.015562 <3>[ 8.194705] mtk-scp 10500000.scp: invalid resource
6049 09:53:58.025593 <6>[ 8.195064] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6050 09:53:58.035157 <6>[ 8.199996] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6051 09:53:58.041829 <4>[ 8.215586] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6052 09:53:58.045422 <6>[ 8.220088] remoteproc remoteproc0: scp is available
6053 09:53:58.055092 <3>[ 8.220248] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6054 09:53:58.061711 <3>[ 8.220256] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6055 09:53:58.075560 <3>[ 8.220261] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6056 09:53:58.081684 <3>[ 8.220266] elan_i2c 2-0015: Error applying setting, reverse things back
6057 09:53:58.095112 <3>[ 8.220950] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6058 09:53:58.101718 <4>[ 8.225747] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6059 09:53:58.112262 <4>[ 8.230889] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6060 09:53:58.119500 <6>[ 8.235012] r8152 1-1.1.1:1.0 enx88541f0f7aca: renamed from eth1
6061 09:53:58.127601 <6>[ 8.241165] mc: Linux media interface: v0.10
6062 09:53:58.137738 <3>[ 8.241682] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6063 09:53:58.147813 <3>[ 8.241695] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6064 09:53:58.158342 <3>[ 8.241702] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6065 09:53:58.169271 <3>[ 8.241759] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6066 09:53:58.179607 <3>[ 8.241764] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6067 09:53:58.190458 <3>[ 8.241769] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6068 09:53:58.200782 <3>[ 8.241774] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6069 09:53:58.211508 <3>[ 8.241779] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6070 09:53:58.221879 <3>[ 8.241801] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6071 09:53:58.229232 <6>[ 8.247632] remoteproc remoteproc0: powering up scp
6072 09:53:58.240155 <4>[ 8.247662] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6073 09:53:58.251192 <6>[ 8.272164] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6074 09:53:58.257808 <3>[ 8.278781] remoteproc remoteproc0: request_firmware failed: -2
6075 09:53:58.264456 <6>[ 8.286802] cs_system_cfg: CoreSight Configuration manager initialised
6076 09:53:58.274431 <6>[ 8.424544] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6077 09:53:58.284464 <5>[ 8.439444] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6078 09:53:58.290980 <6>[ 8.450748] videodev: Linux video capture interface: v2.00
6079 09:53:58.297672 <6>[ 8.450950] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6080 09:53:58.307753 <6>[ 8.451076] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6081 09:53:58.310648 <6>[ 8.469150] Bluetooth: Core ver 2.22
6082 09:53:58.323531 <6>[ 8.502565] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6083 09:53:58.333211 <6>[ 8.502965] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6084 09:53:58.339725 <6>[ 8.518788] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6085 09:53:58.346180 <5>[ 8.519869] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6086 09:53:58.359743 <6>[ 8.527752] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6087 09:53:58.366475 <5>[ 8.532734] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6088 09:53:58.376173 <6>[ 8.535444] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6089 09:53:58.382723 <6>[ 8.536585] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video2 (81,2)
6090 09:53:58.389437 <6>[ 8.537978] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video3
6091 09:53:58.396529 <6>[ 8.544284] NET: Registered PF_BLUETOOTH protocol family
6092 09:53:58.402708 <6>[ 8.544463] usbcore: registered new interface driver uvcvideo
6093 09:53:58.409452 <6>[ 8.544684] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6094 09:53:58.419544 <4>[ 8.552488] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6095 09:53:58.426275 <6>[ 8.553050] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6096 09:53:58.435993 <6>[ 8.554285] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6097 09:53:58.442773 <6>[ 8.554484] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6098 09:53:58.453448 <6>[ 8.554729] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6099 09:53:58.460130 <6>[ 8.559575] Bluetooth: HCI device and connection manager initialized
6100 09:53:58.468351 <6>[ 8.568035] cfg80211: failed to load regulatory.db
6101 09:53:58.474981 <6>[ 8.575493] Bluetooth: HCI socket layer initialized
6102 09:53:58.485048 <3>[ 8.575924] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6103 09:53:58.491322 <3>[ 8.582036] debugfs: File 'Playback' in directory 'dapm' already present!
6104 09:53:58.498184 <6>[ 8.586969] Bluetooth: L2CAP socket layer initialized
6105 09:53:58.504760 <3>[ 8.594876] debugfs: File 'Capture' in directory 'dapm' already present!
6106 09:53:58.508111 <6>[ 8.603847] Bluetooth: SCO socket layer initialized
6107 09:53:58.521442 <6>[ 8.615686] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6108 09:53:58.524721 <6>[ 8.646411] Bluetooth: HCI UART driver ver 2.3
6109 09:53:58.531389 <3>[ 8.650682] thermal_sys: Failed to find 'trips' node
6110 09:53:58.534868 <6>[ 8.652820] Bluetooth: HCI UART protocol H4 registered
6111 09:53:58.544494 <3>[ 8.657954] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6112 09:53:58.547897 <6>[ 8.669794] Bluetooth: HCI UART protocol LL registered
6113 09:53:58.557902 <3>[ 8.676800] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6114 09:53:58.564675 <6>[ 8.682107] Bluetooth: HCI UART protocol Three-wire (H5) registered
6115 09:53:58.574604 <6>[ 8.687217] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6116 09:53:58.584877 <6>[ 8.687222] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6117 09:53:58.598041 Begin: Loading essential drivers<6>[ 8.687312] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6118 09:53:58.598622 ... done.
6119 09:53:58.607917 Begin: Running /scri<4>[ 8.689068] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6120 09:53:58.611147 pts/init-premount ... done.
6121 09:53:58.617962 Beg<6>[ 8.694501] Bluetooth: HCI UART protocol Broadcom registered
6122 09:53:58.624409 in: Mounting root file system ..<3>[ 8.706118] thermal_sys: Failed to find 'trips' node
6123 09:53:58.634699 . Begin: Running /scripts/nfs-to<6>[ 8.709620] Bluetooth: HCI UART protocol QCA registered
6124 09:53:58.635209 p ... done.
6125 09:53:58.641171 Begin: Running /scr<6>[ 8.711278] Bluetooth: hci0: setting up ROME/QCA6390
6126 09:53:58.651206 ipts/nfs-premount ... Waiting up<3>[ 8.714785] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6127 09:53:58.661204 to 60 secs for any ethernet to <6>[ 8.720208] Bluetooth: HCI UART protocol Marvell registered
6128 09:53:58.661723 become available
6129 09:53:58.671191 Device /sys/cl<3>[ 8.727469] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6130 09:53:58.674197 ass/net/enx88541f0f7aca found
6131 09:53:58.680830 d<4>[ 8.727473] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6132 09:53:58.684466 one.
6133 09:53:58.694069 Begin: Waiting up to 180 s<4>[ 8.759223] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6134 09:53:58.697801 <4>[ 8.759223] Fallback method does not support PEC.
6135 09:53:58.710779 ecs for any network device to be<6>[ 8.836071] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6136 09:53:58.711293 come available ... done.
6137 09:53:58.748681 <3>[ 8.925268] Bluetooth: hci0: Frame reassembly failed (-84)
6138 09:53:58.755223 <3>[ 8.930042] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6139 09:53:58.769731 IP-Config: enx88541f0f7aca hardware address 88:54:1f:0f:7a:ca mtu 1500 DHCP
6140 09:53:58.810305 <3>[ 8.986314] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6141 09:53:58.838459 IP-Config: eth0 hardware address 00:e0:4c:68:03:2b mtu 1500 DHCP
6142 09:53:58.844995 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6143 09:53:58.851618 address: 192.168.201.17 broadcast: 192.168.201.255 netmask: 255.255.255.0
6144 09:53:58.858092 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6145 09:53:58.865111 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-5
6146 09:53:58.871537 domain : lava-rack
6147 09:53:58.874490 rootserver: 192.168.201.1 rootpath:
6148 09:53:58.875001 filename :
6149 09:53:58.909548 done.
6150 09:53:58.918072 Begin: Running /scripts/nfs-bottom ... done.
6151 09:53:58.936489 Begin: Running /scripts/init-bottom ... done.
6152 09:53:59.015045 <6>[ 9.194220] Bluetooth: hci0: QCA Product ID :0x00000008
6153 09:53:59.023199 <6>[ 9.202715] Bluetooth: hci0: QCA SOC Version :0x00000044
6154 09:53:59.031549 <6>[ 9.210773] Bluetooth: hci0: QCA ROM Version :0x00000302
6155 09:53:59.039125 <6>[ 9.218569] Bluetooth: hci0: QCA Patch Version:0x00000111
6156 09:53:59.046583 <6>[ 9.226146] Bluetooth: hci0: QCA controller version 0x00440302
6157 09:53:59.057884 <6>[ 9.233949] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6158 09:53:59.067803 <4>[ 9.243042] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6159 09:53:59.078290 <3>[ 9.254403] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6160 09:53:59.084957 <3>[ 9.254409] Bluetooth: hci0: QCA Failed to download patch (-2)
6161 09:53:59.102358 <6>[ 9.278320] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6162 09:53:59.190550 <4>[ 9.366313] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6163 09:53:59.212487 <4>[ 9.388285] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6164 09:53:59.227991 <4>[ 9.403915] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6165 09:53:59.239461 <4>[ 9.418341] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6166 09:54:00.382443 <6>[ 10.562277] NET: Registered PF_INET6 protocol family
6167 09:54:00.394876 <6>[ 10.574490] Segment Routing with IPv6
6168 09:54:00.402775 <6>[ 10.582627] In-situ OAM (IOAM) with IPv6
6169 09:54:00.594583 <30>[ 10.744509] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6170 09:54:00.611116 <30>[ 10.790886] systemd[1]: Detected architecture arm64.
6171 09:54:00.624997
6172 09:54:00.627721 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6173 09:54:00.627987
6174 09:54:00.652139 <30>[ 10.831460] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6175 09:54:01.797855 <30>[ 11.974155] systemd[1]: Queued start job for default target graphical.target.
6176 09:54:01.839534 <30>[ 12.015254] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6177 09:54:01.852135 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6178 09:54:01.871988 <30>[ 12.047697] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6179 09:54:01.884893 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6180 09:54:01.903785 <30>[ 12.079915] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6181 09:54:01.917989 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6182 09:54:01.934914 <30>[ 12.111081] systemd[1]: Created slice user.slice - User and Session Slice.
6183 09:54:01.947149 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6184 09:54:01.969555 <30>[ 12.142073] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6185 09:54:01.982378 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6186 09:54:02.001042 <30>[ 12.173905] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6187 09:54:02.013311 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6188 09:54:02.039606 <30>[ 12.205863] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6189 09:54:02.058547 <30>[ 12.234636] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6190 09:54:02.066171 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6191 09:54:02.085765 <30>[ 12.261690] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6192 09:54:02.098799 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6193 09:54:02.117720 <30>[ 12.293750] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6194 09:54:02.131695 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6195 09:54:02.146330 <30>[ 12.325775] systemd[1]: Reached target paths.target - Path Units.
6196 09:54:02.161082 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6197 09:54:02.177646 <30>[ 12.353679] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6198 09:54:02.190024 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6199 09:54:02.202415 <30>[ 12.381658] systemd[1]: Reached target slices.target - Slice Units.
6200 09:54:02.216737 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6201 09:54:02.230327 <30>[ 12.409762] systemd[1]: Reached target swap.target - Swaps.
6202 09:54:02.241071 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6203 09:54:02.261697 <30>[ 12.437748] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6204 09:54:02.274958 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6205 09:54:02.294259 <30>[ 12.470215] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6206 09:54:02.308204 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6207 09:54:02.328874 <30>[ 12.504847] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6208 09:54:02.342265 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6209 09:54:02.359414 <30>[ 12.535497] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6210 09:54:02.373486 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6211 09:54:02.390175 <30>[ 12.566428] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6212 09:54:02.402509 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6213 09:54:02.423565 <30>[ 12.599581] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6214 09:54:02.437435 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6215 09:54:02.457052 <30>[ 12.633393] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6216 09:54:02.470272 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6217 09:54:02.490368 <30>[ 12.666315] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6218 09:54:02.503186 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6219 09:54:02.546143 <30>[ 12.721834] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6220 09:54:02.557461 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6221 09:54:02.579042 <30>[ 12.755593] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6222 09:54:02.592178 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6223 09:54:02.612412 <30>[ 12.789090] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6224 09:54:02.624428 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6225 09:54:02.648521 <30>[ 12.818048] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6226 09:54:02.668875 <30>[ 12.845190] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6227 09:54:02.680886 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6228 09:54:02.702287 <30>[ 12.878431] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6229 09:54:02.713970 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6230 09:54:02.746811 <30>[ 12.922759] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6231 09:54:02.758183 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6232 09:54:02.782713 <30>[ 12.958749] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6233 09:54:02.798000 Starting [0;1;39mmodpr<6>[ 12.972375] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6234 09:54:02.801220 obe@drm.service[0m - Load Kernel Module drm...
6235 09:54:02.828159 <30>[ 13.004176] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6236 09:54:02.839840 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6237 09:54:02.886273 <30>[ 13.062485] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6238 09:54:02.898287 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6239 09:54:02.919043 <30>[ 13.095255] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6240 09:54:02.935726 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 13.113908] fuse: init (API version 7.37)
6241 09:54:02.936260 el Module loop...
6242 09:54:02.994907 <30>[ 13.170767] systemd[1]: Starting systemd-journald.service - Journal Service...
6243 09:54:03.005032 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6244 09:54:03.031206 <30>[ 13.207465] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6245 09:54:03.042352 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6246 09:54:03.064888 <30>[ 13.237781] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6247 09:54:03.076057 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6248 09:54:03.097339 <30>[ 13.273228] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6249 09:54:03.110839 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6250 09:54:03.134167 <30>[ 13.310768] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6251 09:54:03.146537 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6252 09:54:03.171985 <30>[ 13.348236] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6253 09:54:03.181913 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6254 09:54:03.198051 <30>[ 13.374427] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6255 09:54:03.211388 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
6256 09:54:03.217890 <3>[ 13.394590] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6257 09:54:03.231179 <30>[ 13.406580] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6258 09:54:03.237591 <3>[ 13.411137] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6259 09:54:03.249989 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6260 09:54:03.255883 <3>[ 13.433537] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6261 09:54:03.268775 <30>[ 13.443454] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6262 09:54:03.275254 <3>[ 13.448674] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6263 09:54:03.289784 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6264 09:54:03.296656 <3>[ 13.473568] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6265 09:54:03.305471 <30>[ 13.483938] systemd[1]: modprobe@configfs.service: Deactivated successfully.
6266 09:54:03.315971 <3>[ 13.489465] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6267 09:54:03.323452 <30>[ 13.491883] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
6268 09:54:03.333608 <3>[ 13.505284] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6269 09:54:03.349250 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6270 09:54:03.355682 <3>[ 13.531112] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6271 09:54:03.367955 <30>[ 13.542639] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
6272 09:54:03.374934 <30>[ 13.552564] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
6273 09:54:03.387505 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6274 09:54:03.406561 <30>[ 13.582283] systemd[1]: Started systemd-journald.service - Journal Service.
6275 09:54:03.416204 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6276 09:54:03.442300 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6277 09:54:03.464492 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6278 09:54:03.484680 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6279 09:54:03.504504 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6280 09:54:03.523625 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6281 09:54:03.543430 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6282 09:54:03.567253 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6283 09:54:03.588837 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6284 09:54:03.619387 <4>[ 13.788594] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6285 09:54:03.630532 <3>[ 13.806393] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6286 09:54:03.672617 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6287 09:54:03.696247 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6288 09:54:03.717694 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6289 09:54:03.737758 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6290 09:54:03.760557 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6291 09:54:03.787840 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6292 09:54:03.798011 <46>[ 13.973119] systemd-journald[316]: Received client request to flush runtime journal.
6293 09:54:03.824066 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6294 09:54:03.843470 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6295 09:54:03.862811 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6296 09:54:03.888741 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6297 09:54:04.609162 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6298 09:54:04.927149 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6299 09:54:04.982529 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6300 09:54:05.283395 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6301 09:54:05.377482 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6302 09:54:05.394458 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6303 09:54:05.410125 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6304 09:54:05.470692 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6305 09:54:05.494559 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6306 09:54:05.765461 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6307 09:54:05.829681 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6308 09:54:05.894347 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6309 09:54:06.069748 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6310 09:54:06.114681 Startin<4>[ 16.290461] power_supply_show_property: 4 callbacks suppressed
6311 09:54:06.121691 g [0;1;39msyste<3>[ 16.290472] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6312 09:54:06.131709 md-backlight…e<3>[ 16.290893] power_supply sbs-12-000b: driver failed to report `technology' property: -6
6313 09:54:06.141589 ss of backlight:backlight_lcd0..<3>[ 16.303395] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6314 09:54:06.144891 .
6315 09:54:06.163605 [[0;32m OK [<3>[ 16.340546] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6316 09:54:06.170018 0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6317 09:54:06.182531 <3>[ 16.358619] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6318 09:54:06.197404 <3>[ 16.373706] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6319 09:54:06.213047 <3>[ 16.389200] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6320 09:54:06.227960 <3>[ 16.404032] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6321 09:54:06.242536 <3>[ 16.418743] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6322 09:54:06.257229 <3>[ 16.433521] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6323 09:54:06.274794 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6324 09:54:06.290109 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6325 09:54:06.362331 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6326 09:54:06.382151 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6327 09:54:06.400695 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6328 09:54:06.449825 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6329 09:54:06.560629 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6330 09:54:06.581826 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6331 09:54:06.601485 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6332 09:54:06.634679 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6333 09:54:06.655670 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6334 09:54:06.679636 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6335 09:54:06.702340 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6336 09:54:06.725485 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6337 09:54:06.751247 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6338 09:54:06.773403 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6339 09:54:06.795527 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6340 09:54:06.817867 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6341 09:54:06.841002 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6342 09:54:06.868344 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6343 09:54:06.907319 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6344 09:54:06.926487 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6345 09:54:06.949856 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6346 09:54:06.971499 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6347 09:54:06.990756 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6348 09:54:07.010502 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6349 09:54:07.029886 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6350 09:54:07.046541 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6351 09:54:07.053469 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6352 09:54:07.099376 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6353 09:54:07.123721 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6354 09:54:07.155862 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6355 09:54:07.266634 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6356 09:54:07.293297 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6357 09:54:07.316272 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6358 09:54:07.335166 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6359 09:54:07.422530 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6360 09:54:07.461458 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6361 09:54:07.484035 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6362 09:54:07.504479 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6363 09:54:07.547544 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6364 09:54:07.590111 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6365 09:54:07.628029 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6366 09:54:07.650133 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6367 09:54:07.671404 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6368 09:54:07.712449 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6369 09:54:07.773379 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6370 09:54:07.855372
6371 09:54:07.858805 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6372 09:54:07.858931
6373 09:54:07.861729 debian-bookworm-arm64 login: root (automatic login)
6374 09:54:07.861870
6375 09:54:08.155733 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
6376 09:54:08.156220
6377 09:54:08.162491 The programs included with the Debian GNU/Linux system are free software;
6378 09:54:08.168775 the exact distribution terms for each program are described in the
6379 09:54:08.171929 individual files in /usr/share/doc/*/copyright.
6380 09:54:08.172356
6381 09:54:08.178774 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6382 09:54:08.182064 permitted by applicable law.
6383 09:54:09.322104 Matched prompt #10: / #
6385 09:54:09.323262 Setting prompt string to ['/ #']
6386 09:54:09.323712 end: 2.2.5.1 login-action (duration 00:00:20) [common]
6388 09:54:09.324716 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
6389 09:54:09.325192 start: 2.2.6 expect-shell-connection (timeout 00:03:48) [common]
6390 09:54:09.325562 Setting prompt string to ['/ #']
6391 09:54:09.325875 Forcing a shell prompt, looking for ['/ #']
6393 09:54:09.376983 / #
6394 09:54:09.377642 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6395 09:54:09.378113 Waiting using forced prompt support (timeout 00:02:30)
6396 09:54:09.383307
6397 09:54:09.384175 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6398 09:54:09.384697 start: 2.2.7 export-device-env (timeout 00:03:48) [common]
6400 09:54:09.486088 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407592/extract-nfsrootfs-4guaw7ba'
6401 09:54:09.492206 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407592/extract-nfsrootfs-4guaw7ba'
6403 09:54:09.593814 / # export NFS_SERVER_IP='192.168.201.1'
6404 09:54:09.599807 export NFS_SERVER_IP='192.168.201.1'
6405 09:54:09.600619 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6406 09:54:09.601124 end: 2.2 depthcharge-retry (duration 00:01:12) [common]
6407 09:54:09.601612 end: 2 depthcharge-action (duration 00:01:12) [common]
6408 09:54:09.602069 start: 3 lava-test-retry (timeout 00:08:10) [common]
6409 09:54:09.602581 start: 3.1 lava-test-shell (timeout 00:08:10) [common]
6410 09:54:09.602978 Using namespace: common
6412 09:54:09.704095 / # #
6413 09:54:09.704822 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6414 09:54:09.710341 #
6415 09:54:09.711127 Using /lava-14407592
6417 09:54:09.812380 / # export SHELL=/bin/bash
6418 09:54:09.818764 export SHELL=/bin/bash
6420 09:54:09.920501 / # . /lava-14407592/environment
6421 09:54:09.927002 . /lava-14407592/environment
6423 09:54:10.035506 / # /lava-14407592/bin/lava-test-runner /lava-14407592/0
6424 09:54:10.036158 Test shell timeout: 10s (minimum of the action and connection timeout)
6425 09:54:10.041686 /lava-14407592/bin/lava-test-runner /lava-14407592/0
6426 09:54:10.344728 + export TESTRUN_ID=0_timesync-off
6427 09:54:10.347982 + TESTRUN_ID=0_timesync-off
6428 09:54:10.351341 + cd /lava-14407592/0/tests/0_timesync-off
6429 09:54:10.354767 ++ cat uuid
6430 09:54:10.360567 + UUID=14407592_1.6.2.3.1
6431 09:54:10.361009 + set +x
6432 09:54:10.366819 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14407592_1.6.2.3.1>
6433 09:54:10.367502 Received signal: <STARTRUN> 0_timesync-off 14407592_1.6.2.3.1
6434 09:54:10.367861 Starting test lava.0_timesync-off (14407592_1.6.2.3.1)
6435 09:54:10.368376 Skipping test definition patterns.
6436 09:54:10.370136 + systemctl stop systemd-timesyncd
6437 09:54:10.435859 + set +x
6438 09:54:10.438915 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14407592_1.6.2.3.1>
6439 09:54:10.439626 Received signal: <ENDRUN> 0_timesync-off 14407592_1.6.2.3.1
6440 09:54:10.440042 Ending use of test pattern.
6441 09:54:10.440387 Ending test lava.0_timesync-off (14407592_1.6.2.3.1), duration 0.07
6443 09:54:10.507645 + export TESTRUN_ID=1_kselftest-alsa
6444 09:54:10.510883 + TESTRUN_ID=1_kselftest-alsa
6445 09:54:10.514068 + cd /lava-14407592/0/tests/1_kselftest-alsa
6446 09:54:10.517405 ++ cat uuid
6447 09:54:10.522492 + UUID=14407592_1.6.2.3.5
6448 09:54:10.522918 + set +x
6449 09:54:10.529198 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14407592_1.6.2.3.5>
6450 09:54:10.529825 Received signal: <STARTRUN> 1_kselftest-alsa 14407592_1.6.2.3.5
6451 09:54:10.530145 Starting test lava.1_kselftest-alsa (14407592_1.6.2.3.5)
6452 09:54:10.530528 Skipping test definition patterns.
6453 09:54:10.532308 + cd ./automated/linux/kselftest/
6454 09:54:10.558888 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
6455 09:54:10.603443 INFO: install_deps skipped
6456 09:54:11.107727 --2024-06-18 09:54:10-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
6457 09:54:11.120270 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6458 09:54:11.244703 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6459 09:54:11.371941 HTTP request sent, awaiting response... 200 OK
6460 09:54:11.375654 Length: 1642672 (1.6M) [application/octet-stream]
6461 09:54:11.378830 Saving to: 'kselftest_armhf.tar.gz'
6462 09:54:11.379342
6463 09:54:11.379685
6464 09:54:11.623248 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6465 09:54:11.872352 kselftest_armhf.tar 2%[ ] 46.39K 181KB/s
6466 09:54:12.297715 kselftest_armhf.tar 13%[=> ] 214.67K 420KB/s
6467 09:54:12.374863 kselftest_armhf.tar 49%[========> ] 799.60K 845KB/s
6468 09:54:12.381418 kselftest_armhf.tar 100%[===================>] 1.57M 1.53MB/s in 1.0s
6469 09:54:12.381855
6470 09:54:12.525524 2024-06-18 09:54:12 (1.53 MB/s) - 'kselftest_armhf.tar.gz' saved [1642672/1642672]
6471 09:54:12.525650
6472 09:54:16.564235 skiplist:
6473 09:54:16.567178 ========================================
6474 09:54:16.570585 ========================================
6475 09:54:16.616662 alsa:mixer-test
6476 09:54:16.635857 ============== Tests to run ===============
6477 09:54:16.635938 alsa:mixer-test
6478 09:54:16.639143 ===========End Tests to run ===============
6479 09:54:16.642427 shardfile-alsa pass
6480 09:54:16.746086 <12>[ 26.925065] kselftest: Running tests in alsa
6481 09:54:16.757911 TAP version 13
6482 09:54:16.774025 1..1
6483 09:54:16.790048 # selftests: alsa: mixer-test
6484 09:54:16.902425 <6>[ 27.075001] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6485 09:54:16.915835 <6>[ 27.087302] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6486 09:54:16.929254 <6>[ 27.100045] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 1
6487 09:54:16.939177 <6>[ 27.112267] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6488 09:54:16.952329 <6>[ 27.124465] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6489 09:54:16.962502 <6>[ 27.136710] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6490 09:54:16.976210 <6>[ 27.148098] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6491 09:54:16.985686 <6>[ 27.159444] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 1
6492 09:54:16.998967 <6>[ 27.170781] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6493 09:54:17.009167 <6>[ 27.182120] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6494 09:54:17.018732 <6>[ 27.193460] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6495 09:54:17.032169 <6>[ 27.204795] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6496 09:54:17.042146 <6>[ 27.216126] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 1
6497 09:54:17.055273 <6>[ 27.227460] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6498 09:54:17.065400 <6>[ 27.238797] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6499 09:54:17.078491 <6>[ 27.250138] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6500 09:54:17.088563 <6>[ 27.261478] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6501 09:54:17.098265 <6>[ 27.272814] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 1
6502 09:54:17.111567 <6>[ 27.284148] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6503 09:54:17.121505 <6>[ 27.295484] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6504 09:54:17.135207 <6>[ 27.306821] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6505 09:54:17.145125 <6>[ 27.318152] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6506 09:54:17.157858 <6>[ 27.329481] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 1
6507 09:54:17.168457 <6>[ 27.340812] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6508 09:54:17.177976 <6>[ 27.352145] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6509 09:54:17.191408 <6>[ 27.363481] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6510 09:54:17.201459 <6>[ 27.374814] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6511 09:54:17.214345 <6>[ 27.386150] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 1
6512 09:54:17.224382 <6>[ 27.397485] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6513 09:54:17.234285 <6>[ 27.408823] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6514 09:54:17.238601 # TAP version 13
6515 09:54:17.239033 # 1..658
6516 09:54:17.241996 # ok 1 get_value.0.93
6517 09:54:17.242485 # ok 2 name.0.93
6518 09:54:17.245248 # ok 3 write_default.0.93
6519 09:54:17.248974 # ok 4 write_valid.0.93
6520 09:54:17.249486 # ok 5 write_invalid.0.93
6521 09:54:17.251738 # ok 6 event_missing.0.93
6522 09:54:17.255332 # ok 7 event_spurious.0.93
6523 09:54:17.255760 # ok 8 get_value.0.92
6524 09:54:17.258547 # ok 9 name.0.92
6525 09:54:17.261875 # ok 10 write_default.0.92
6526 09:54:17.262337 # ok 11 write_valid.0.92
6527 09:54:17.265104 # ok 12 write_invalid.0.92
6528 09:54:17.268631 # ok 13 event_missing.0.92
6529 09:54:17.271906 # ok 14 event_spurious.0.92
6530 09:54:17.272369 # ok 15 get_value.0.91
6531 09:54:17.275714 # ok 16 name.0.91
6532 09:54:17.276223 # ok 17 write_default.0.91
6533 09:54:17.278590 # ok 18 write_valid.0.91
6534 09:54:17.282166 # ok 19 write_invalid.0.91
6535 09:54:17.285501 # ok 20 event_missing.0.91
6536 09:54:17.285986 # ok 21 event_spurious.0.91
6537 09:54:17.288580 # ok 22 get_value.0.90
6538 09:54:17.289009 # ok 23 name.0.90
6539 09:54:17.292820 # ok 24 write_default.0.90
6540 09:54:17.295975 # ok 25 write_valid.0.90
6541 09:54:17.298927 # ok 26 write_invalid.0.90
6542 09:54:17.299358 # ok 27 event_missing.0.90
6543 09:54:17.302005 # ok 28 event_spurious.0.90
6544 09:54:17.305571 # ok 29 get_value.0.89
6545 09:54:17.306076 # ok 30 name.0.89
6546 09:54:17.308835 # ok 31 write_default.0.89
6547 09:54:17.312050 # ok 32 write_valid.0.89
6548 09:54:17.312481 # ok 33 write_invalid.0.89
6549 09:54:17.315127 # ok 34 event_missing.0.89
6550 09:54:17.318803 # ok 35 event_spurious.0.89
6551 09:54:17.322309 # ok 36 get_value.0.88
6552 09:54:17.322744 # ok 37 name.0.88
6553 09:54:17.325233 # ok 38 write_default.0.88
6554 09:54:17.329059 # # Spurious event generated for AIF Out Mux
6555 09:54:17.335266 # # AIF Out Mux.0 expected 1 but read 0, is_volatile 0
6556 09:54:17.338548 # # Spurious event generated for AIF Out Mux
6557 09:54:17.341875 # not ok 39 write_valid.0.88
6558 09:54:17.342498 # ok 40 write_invalid.0.88
6559 09:54:17.345005 # ok 41 event_missing.0.88
6560 09:54:17.348324 # not ok 42 event_spurious.0.88
6561 09:54:17.351975 # ok 43 get_value.0.87
6562 09:54:17.352404 # ok 44 name.0.87
6563 09:54:17.355044 # ok 45 write_default.0.87
6564 09:54:17.358555 # ok 46 write_valid.0.87
6565 09:54:17.359133 # ok 47 write_invalid.0.87
6566 09:54:17.361595 # ok 48 event_missing.0.87
6567 09:54:17.364888 # ok 49 event_spurious.0.87
6568 09:54:17.368343 # ok 50 get_value.0.86
6569 09:54:17.368775 # ok 51 name.0.86
6570 09:54:17.372061 # ok 52 write_default.0.86
6571 09:54:17.375235 # # HPR Mux.0 expected 5 but read 0, is_volatile 0
6572 09:54:17.382036 # # HPR Mux.0 expected 6 but read 0, is_volatile 0
6573 09:54:17.385219 # # HPR Mux.0 expected 7 but read 0, is_volatile 0
6574 09:54:17.388852 # not ok 53 write_valid.0.86
6575 09:54:17.392135 # ok 54 write_invalid.0.86
6576 09:54:17.392643 # ok 55 event_missing.0.86
6577 09:54:17.395308 # ok 56 event_spurious.0.86
6578 09:54:17.398482 # ok 57 get_value.0.85
6579 09:54:17.398913 # ok 58 name.0.85
6580 09:54:17.401820 # ok 59 write_default.0.85
6581 09:54:17.408685 # # HPL Mux.0 expected 5 but read 0, is_volatile 0
6582 09:54:17.411821 # # HPL Mux.0 expected 6 but read 0, is_volatile 0
6583 09:54:17.415059 # # HPL Mux.0 expected 7 but read 0, is_volatile 0
6584 09:54:17.418507 # not ok 60 write_valid.0.85
6585 09:54:17.421726 # ok 61 write_invalid.0.85
6586 09:54:17.425203 # ok 62 event_missing.0.85
6587 09:54:17.425708 # ok 63 event_spurious.0.85
6588 09:54:17.428726 # ok 64 get_value.0.84
6589 09:54:17.431936 # ok 65 name.0.84
6590 09:54:17.432447 # ok 66 write_default.0.84
6591 09:54:17.435055 # ok 67 write_valid.0.84
6592 09:54:17.438593 # ok 68 write_invalid.0.84
6593 09:54:17.441634 # ok 69 event_missing.0.84
6594 09:54:17.442076 # ok 70 event_spurious.0.84
6595 09:54:17.444913 # ok 71 get_value.0.83
6596 09:54:17.448221 # ok 72 name.0.83
6597 09:54:17.448652 # ok 73 write_default.0.83
6598 09:54:17.451697 # ok 74 write_valid.0.83
6599 09:54:17.455248 # ok 75 write_invalid.0.83
6600 09:54:17.458320 # ok 76 event_missing.0.83
6601 09:54:17.458751 # ok 77 event_spurious.0.83
6602 09:54:17.461660 # ok 78 get_value.0.82
6603 09:54:17.462088 # ok 79 name.0.82
6604 09:54:17.464988 # # Headset Jack is not writeable
6605 09:54:17.468592 # ok 80 # SKIP write_default.0.82
6606 09:54:17.471909 # # Headset Jack is not writeable
6607 09:54:17.475181 # ok 81 # SKIP write_valid.0.82
6608 09:54:17.478282 # # Headset Jack is not writeable
6609 09:54:17.481653 # ok 82 # SKIP write_invalid.0.82
6610 09:54:17.484668 # ok 83 event_missing.0.82
6611 09:54:17.488287 # ok 84 event_spurious.0.82
6612 09:54:17.488799 # ok 85 get_value.0.81
6613 09:54:17.491633 # ok 86 name.0.81
6614 09:54:17.495092 # ok 87 write_default.0.81
6615 09:54:17.498652 # # No event generated for Wake-on-Voice Phase2 Switch
6616 09:54:17.504912 # # No event generated for Wake-on-Voice Phase2 Switch
6617 09:54:17.505431 # ok 88 write_valid.0.81
6618 09:54:17.511592 # # Wake-on-Voice Phase2 Switch.0 Invalid boolean value 2
6619 09:54:17.514703 # # No event generated for Wake-on-Voice Phase2 Switch
6620 09:54:17.518402 # not ok 89 write_invalid.0.81
6621 09:54:17.521176 # not ok 90 event_missing.0.81
6622 09:54:17.524899 # ok 91 event_spurious.0.81
6623 09:54:17.528169 # ok 92 get_value.0.80
6624 09:54:17.528677 # ok 93 name.0.80
6625 09:54:17.531450 # ok 94 write_default.0.80
6626 09:54:17.534994 # ok 95 write_valid.0.80
6627 09:54:17.535426 # ok 96 write_invalid.0.80
6628 09:54:17.537933 # ok 97 event_missing.0.80
6629 09:54:17.541368 # ok 98 event_spurious.0.80
6630 09:54:17.544777 # # Handset Volume.0 value -13 less than minimum 0
6631 09:54:17.547850 # not ok 99 get_value.0.79
6632 09:54:17.548274 # ok 100 name.0.79
6633 09:54:17.554826 # # snd_ctl_elem_write() failed: Invalid argument
6634 09:54:17.557949 # not ok 101 write_default.0.79
6635 09:54:17.561457 # # snd_ctl_elem_write() failed: Invalid argument
6636 09:54:17.565022 # not ok 102 write_valid.0.79
6637 09:54:17.567833 # # snd_ctl_elem_write() failed: Invalid argument
6638 09:54:17.571383 # not ok 103 write_invalid.0.79
6639 09:54:17.574625 # ok 104 event_missing.0.79
6640 09:54:17.578182 # ok 105 event_spurious.0.79
6641 09:54:17.581451 # # Lineout Volume.0 value -13 less than minimum 0
6642 09:54:17.584611 # # Lineout Volume.1 value -13 less than minimum 0
6643 09:54:17.588306 # not ok 106 get_value.0.78
6644 09:54:17.591667 # ok 107 name.0.78
6645 09:54:17.594925 # # snd_ctl_elem_write() failed: Invalid argument
6646 09:54:17.598249 # not ok 108 write_default.0.78
6647 09:54:17.601508 # # snd_ctl_elem_write() failed: Invalid argument
6648 09:54:17.604843 # not ok 109 write_valid.0.78
6649 09:54:17.608175 # # snd_ctl_elem_write() failed: Invalid argument
6650 09:54:17.611361 # not ok 110 write_invalid.0.78
6651 09:54:17.614541 # ok 111 event_missing.0.78
6652 09:54:17.618016 # ok 112 event_spurious.0.78
6653 09:54:17.621236 # # Headphone Volume.0 value -13 less than minimum 0
6654 09:54:17.627902 # # Headphone Volume.1 value -13 less than minimum 0
6655 09:54:17.631465 # not ok 113 get_value.0.77
6656 09:54:17.631976 # ok 114 name.0.77
6657 09:54:17.637624 # # snd_ctl_elem_write() failed: Invalid argument
6658 09:54:17.638055 # not ok 115 write_default.0.77
6659 09:54:17.644246 # # snd_ctl_elem_write() failed: Invalid argument
6660 09:54:17.647815 # not ok 116 write_valid.0.77
6661 09:54:17.651082 # # snd_ctl_elem_write() failed: Invalid argument
6662 09:54:17.654167 # not ok 117 write_invalid.0.77
6663 09:54:17.657852 # ok 118 event_missing.0.77
6664 09:54:17.661110 # ok 119 event_spurious.0.77
6665 09:54:17.661622 # ok 120 get_value.0.76
6666 09:54:17.667644 # # 0.76 ADDA_DL_CH2 PCM_2_CAP_CH2 is a writeable boolean but not a Switch
6667 09:54:17.670924 # not ok 121 name.0.76
6668 09:54:17.674007 # ok 122 write_default.0.76
6669 09:54:17.674493 # ok 123 write_valid.0.76
6670 09:54:17.677316 # ok 124 write_invalid.0.76
6671 09:54:17.681081 # ok 125 event_missing.0.76
6672 09:54:17.684093 # ok 126 event_spurious.0.76
6673 09:54:17.687276 # ok 127 get_value.0.75
6674 09:54:17.694103 # # 0.75 ADDA_DL_CH2 PCM_1_CAP_CH2 is a writeable boolean but not a Switch
6675 09:54:17.694662 # not ok 128 name.0.75
6676 09:54:17.697812 # ok 129 write_default.0.75
6677 09:54:17.700652 # ok 130 write_valid.0.75
6678 09:54:17.704198 # ok 131 write_invalid.0.75
6679 09:54:17.704713 # ok 132 event_missing.0.75
6680 09:54:17.707517 # ok 133 event_spurious.0.75
6681 09:54:17.710525 # ok 134 get_value.0.74
6682 09:54:17.717461 # # 0.74 ADDA_DL_CH2 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6683 09:54:17.721033 # not ok 135 name.0.74
6684 09:54:17.721543 # ok 136 write_default.0.74
6685 09:54:17.724198 # ok 137 write_valid.0.74
6686 09:54:17.727526 # ok 138 write_invalid.0.74
6687 09:54:17.730838 # ok 139 event_missing.0.74
6688 09:54:17.731346 # ok 140 event_spurious.0.74
6689 09:54:17.734203 # ok 141 get_value.0.73
6690 09:54:17.740671 # # 0.73 ADDA_DL_CH2 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6691 09:54:17.743962 # not ok 142 name.0.73
6692 09:54:17.747586 # ok 143 write_default.0.73
6693 09:54:17.748095 # ok 144 write_valid.0.73
6694 09:54:17.750730 # ok 145 write_invalid.0.73
6695 09:54:17.754171 # ok 146 event_missing.0.73
6696 09:54:17.757529 # ok 147 event_spurious.0.73
6697 09:54:17.758042 # ok 148 get_value.0.72
6698 09:54:17.764260 # # 0.72 ADDA_DL_CH2 ADDA_UL_CH1 is a writeable boolean but not a Switch
6699 09:54:17.767442 # not ok 149 name.0.72
6700 09:54:17.770769 # ok 150 write_default.0.72
6701 09:54:17.771285 # ok 151 write_valid.0.72
6702 09:54:17.774304 # ok 152 write_invalid.0.72
6703 09:54:17.777081 # ok 153 event_missing.0.72
6704 09:54:17.780668 # ok 154 event_spurious.0.72
6705 09:54:17.783870 # ok 155 get_value.0.71
6706 09:54:17.790893 # # 0.71 ADDA_DL_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
6707 09:54:17.791409 # not ok 156 name.0.71
6708 09:54:17.793868 # ok 157 write_default.0.71
6709 09:54:17.796908 # ok 158 write_valid.0.71
6710 09:54:17.800490 # ok 159 write_invalid.0.71
6711 09:54:17.801004 # ok 160 event_missing.0.71
6712 09:54:17.803707 # ok 161 event_spurious.0.71
6713 09:54:17.807128 # ok 162 get_value.0.70
6714 09:54:17.813456 # # 0.70 ADDA_DL_CH2 DL3_CH2 is a writeable boolean but not a Switch
6715 09:54:17.813958 # not ok 163 name.0.70
6716 09:54:17.817165 # ok 164 write_default.0.70
6717 09:54:17.820677 # ok 165 write_valid.0.70
6718 09:54:17.823564 # ok 166 write_invalid.0.70
6719 09:54:17.824002 # ok 167 event_missing.0.70
6720 09:54:17.826790 # ok 168 event_spurious.0.70
6721 09:54:17.830275 # ok 169 get_value.0.69
6722 09:54:17.837306 # # 0.69 ADDA_DL_CH2 DL3_CH1 is a writeable boolean but not a Switch
6723 09:54:17.840091 # not ok 170 name.0.69
6724 09:54:17.840524 # ok 171 write_default.0.69
6725 09:54:17.843172 # ok 172 write_valid.0.69
6726 09:54:17.846820 # ok 173 write_invalid.0.69
6727 09:54:17.850811 # ok 174 event_missing.0.69
6728 09:54:17.851364 # ok 175 event_spurious.0.69
6729 09:54:17.853297 # ok 176 get_value.0.68
6730 09:54:17.860040 # # 0.68 ADDA_DL_CH2 DL2_CH2 is a writeable boolean but not a Switch
6731 09:54:17.863182 # not ok 177 name.0.68
6732 09:54:17.863616 # ok 178 write_default.0.68
6733 09:54:17.866667 # ok 179 write_valid.0.68
6734 09:54:17.870136 # ok 180 write_invalid.0.68
6735 09:54:17.873399 # ok 181 event_missing.0.68
6736 09:54:17.876854 # ok 182 event_spurious.0.68
6737 09:54:17.877369 # ok 183 get_value.0.67
6738 09:54:17.883364 # # 0.67 ADDA_DL_CH2 DL2_CH1 is a writeable boolean but not a Switch
6739 09:54:17.886921 # not ok 184 name.0.67
6740 09:54:17.890065 # ok 185 write_default.0.67
6741 09:54:17.890617 # ok 186 write_valid.0.67
6742 09:54:17.893424 # ok 187 write_invalid.0.67
6743 09:54:17.896862 # ok 188 event_missing.0.67
6744 09:54:17.899822 # ok 189 event_spurious.0.67
6745 09:54:17.900257 # ok 190 get_value.0.66
6746 09:54:17.906665 # # 0.66 ADDA_DL_CH2 DL1_CH2 is a writeable boolean but not a Switch
6747 09:54:17.910138 # not ok 191 name.0.66
6748 09:54:17.913080 # ok 192 write_default.0.66
6749 09:54:17.913517 # ok 193 write_valid.0.66
6750 09:54:17.916465 # ok 194 write_invalid.0.66
6751 09:54:17.919919 # ok 195 event_missing.0.66
6752 09:54:17.923109 # ok 196 event_spurious.0.66
6753 09:54:17.923542 # ok 197 get_value.0.65
6754 09:54:17.930278 # # 0.65 ADDA_DL_CH2 DL1_CH1 is a writeable boolean but not a Switch
6755 09:54:17.933466 # not ok 198 name.0.65
6756 09:54:17.936727 # ok 199 write_default.0.65
6757 09:54:17.937240 # ok 200 write_valid.0.65
6758 09:54:17.939708 # ok 201 write_invalid.0.65
6759 09:54:17.943150 # ok 202 event_missing.0.65
6760 09:54:17.946404 # ok 203 event_spurious.0.65
6761 09:54:17.950133 # ok 204 get_value.0.64
6762 09:54:17.956350 # # 0.64 ADDA_DL_CH1 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6763 09:54:17.956851 # not ok 205 name.0.64
6764 09:54:17.960088 # ok 206 write_default.0.64
6765 09:54:17.963108 # ok 207 write_valid.0.64
6766 09:54:17.966828 # ok 208 write_invalid.0.64
6767 09:54:17.967340 # ok 209 event_missing.0.64
6768 09:54:17.970004 # ok 210 event_spurious.0.64
6769 09:54:17.973441 # ok 211 get_value.0.63
6770 09:54:17.979782 # # 0.63 ADDA_DL_CH1 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6771 09:54:17.983046 # not ok 212 name.0.63
6772 09:54:17.983476 # ok 213 write_default.0.63
6773 09:54:17.986289 # ok 214 write_valid.0.63
6774 09:54:17.989649 # ok 215 write_invalid.0.63
6775 09:54:17.993441 # ok 216 event_missing.0.63
6776 09:54:17.996390 # ok 217 event_spurious.0.63
6777 09:54:17.996823 # ok 218 get_value.0.62
6778 09:54:18.003088 # # 0.62 ADDA_DL_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
6779 09:54:18.006455 # not ok 219 name.0.62
6780 09:54:18.009649 # ok 220 write_default.0.62
6781 09:54:18.010156 # ok 221 write_valid.0.62
6782 09:54:18.012995 # ok 222 write_invalid.0.62
6783 09:54:18.016216 # ok 223 event_missing.0.62
6784 09:54:18.019776 # ok 224 event_spurious.0.62
6785 09:54:18.020287 # ok 225 get_value.0.61
6786 09:54:18.025999 # # 0.61 ADDA_DL_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
6787 09:54:18.029358 # not ok 226 name.0.61
6788 09:54:18.032739 # ok 227 write_default.0.61
6789 09:54:18.035910 # ok 228 write_valid.0.61
6790 09:54:18.036344 # ok 229 write_invalid.0.61
6791 09:54:18.039151 # ok 230 event_missing.0.61
6792 09:54:18.042523 # ok 231 event_spurious.0.61
6793 09:54:18.045882 # ok 232 get_value.0.60
6794 09:54:18.052790 # # 0.60 ADDA_DL_CH1 DL3_CH1 is a writeable boolean but not a Switch
6795 09:54:18.053312 # not ok 233 name.0.60
6796 09:54:18.056079 # ok 234 write_default.0.60
6797 09:54:18.059682 # ok 235 write_valid.0.60
6798 09:54:18.060374 # ok 236 write_invalid.0.60
6799 09:54:18.062591 # ok 237 event_missing.0.60
6800 09:54:18.066170 # ok 238 event_spurious.0.60
6801 09:54:18.069378 # ok 239 get_value.0.59
6802 09:54:18.076354 # # 0.59 ADDA_DL_CH1 DL2_CH1 is a writeable boolean but not a Switch
6803 09:54:18.076868 # not ok 240 name.0.59
6804 09:54:18.079432 # ok 241 write_default.0.59
6805 09:54:18.082918 # ok 242 write_valid.0.59
6806 09:54:18.085905 # ok 243 write_invalid.0.59
6807 09:54:18.086461 # ok 244 event_missing.0.59
6808 09:54:18.089195 # ok 245 event_spurious.0.59
6809 09:54:18.092740 # ok 246 get_value.0.58
6810 09:54:18.099014 # # 0.58 ADDA_DL_CH1 DL1_CH1 is a writeable boolean but not a Switch
6811 09:54:18.099530 # not ok 247 name.0.58
6812 09:54:18.102574 # ok 248 write_default.0.58
6813 09:54:18.105862 # ok 249 write_valid.0.58
6814 09:54:18.108889 # ok 250 write_invalid.0.58
6815 09:54:18.112115 # ok 251 event_missing.0.58
6816 09:54:18.112559 # ok 252 event_spurious.0.58
6817 09:54:18.115465 # ok 253 get_value.0.57
6818 09:54:18.122392 # # 0.57 I2S5_CH2 DL3_CH2 is a writeable boolean but not a Switch
6819 09:54:18.125679 # not ok 254 name.0.57
6820 09:54:18.126109 # ok 255 write_default.0.57
6821 09:54:18.128874 # ok 256 write_valid.0.57
6822 09:54:18.132327 # ok 257 write_invalid.0.57
6823 09:54:18.135514 # ok 258 event_missing.0.57
6824 09:54:18.136028 # ok 259 event_spurious.0.57
6825 09:54:18.139047 # ok 260 get_value.0.56
6826 09:54:18.145228 # # 0.56 I2S5_CH2 DL2_CH2 is a writeable boolean but not a Switch
6827 09:54:18.148749 # not ok 261 name.0.56
6828 09:54:18.149175 # ok 262 write_default.0.56
6829 09:54:18.151992 # ok 263 write_valid.0.56
6830 09:54:18.155693 # ok 264 write_invalid.0.56
6831 09:54:18.158789 # ok 265 event_missing.0.56
6832 09:54:18.162118 # ok 266 event_spurious.0.56
6833 09:54:18.162630 # ok 267 get_value.0.55
6834 09:54:18.169128 # # 0.55 I2S5_CH2 DL1_CH2 is a writeable boolean but not a Switch
6835 09:54:18.172476 # not ok 268 name.0.55
6836 09:54:18.172985 # ok 269 write_default.0.55
6837 09:54:18.175644 # ok 270 write_valid.0.55
6838 09:54:18.178800 # ok 271 write_invalid.0.55
6839 09:54:18.182395 # ok 272 event_missing.0.55
6840 09:54:18.182906 # ok 273 event_spurious.0.55
6841 09:54:18.185990 # ok 274 get_value.0.54
6842 09:54:18.192176 # # 0.54 I2S5_CH1 DL3_CH1 is a writeable boolean but not a Switch
6843 09:54:18.195587 # not ok 275 name.0.54
6844 09:54:18.196098 # ok 276 write_default.0.54
6845 09:54:18.198927 # ok 277 write_valid.0.54
6846 09:54:18.202109 # ok 278 write_invalid.0.54
6847 09:54:18.205416 # ok 279 event_missing.0.54
6848 09:54:18.205923 # ok 280 event_spurious.0.54
6849 09:54:18.208740 # ok 281 get_value.0.53
6850 09:54:18.215012 # # 0.53 I2S5_CH1 DL2_CH1 is a writeable boolean but not a Switch
6851 09:54:18.218519 # not ok 282 name.0.53
6852 09:54:18.218946 # ok 283 write_default.0.53
6853 09:54:18.222103 # ok 284 write_valid.0.53
6854 09:54:18.225210 # ok 285 write_invalid.0.53
6855 09:54:18.228346 # ok 286 event_missing.0.53
6856 09:54:18.228789 # ok 287 event_spurious.0.53
6857 09:54:18.232001 # ok 288 get_value.0.52
6858 09:54:18.238550 # # 0.52 I2S5_CH1 DL1_CH1 is a writeable boolean but not a Switch
6859 09:54:18.241748 # not ok 289 name.0.52
6860 09:54:18.242289 # ok 290 write_default.0.52
6861 09:54:18.244900 # ok 291 write_valid.0.52
6862 09:54:18.248193 # ok 292 write_invalid.0.52
6863 09:54:18.251572 # ok 293 event_missing.0.52
6864 09:54:18.252083 # ok 294 event_spurious.0.52
6865 09:54:18.254435 # ok 295 get_value.0.51
6866 09:54:18.261452 # # 0.51 I2S3_CH2 DL3_CH2 is a writeable boolean but not a Switch
6867 09:54:18.261967 # not ok 296 name.0.51
6868 09:54:18.264631 # ok 297 write_default.0.51
6869 09:54:18.268039 # ok 298 write_valid.0.51
6870 09:54:18.271399 # ok 299 write_invalid.0.51
6871 09:54:18.271910 # ok 300 event_missing.0.51
6872 09:54:18.274769 # ok 301 event_spurious.0.51
6873 09:54:18.277826 # ok 302 get_value.0.50
6874 09:54:18.284913 # # 0.50 I2S3_CH2 DL2_CH2 is a writeable boolean but not a Switch
6875 09:54:18.285425 # not ok 303 name.0.50
6876 09:54:18.288130 # ok 304 write_default.0.50
6877 09:54:18.291158 # ok 305 write_valid.0.50
6878 09:54:18.291666 # ok 306 write_invalid.0.50
6879 09:54:18.294282 # ok 307 event_missing.0.50
6880 09:54:18.298026 # ok 308 event_spurious.0.50
6881 09:54:18.301087 # ok 309 get_value.0.49
6882 09:54:18.304392 # # 0.49 I2S3_CH2 DL1_CH2 is a writeable boolean but not a Switch
6883 09:54:18.307907 # not ok 310 name.0.49
6884 09:54:18.311349 # ok 311 write_default.0.49
6885 09:54:18.311863 # ok 312 write_valid.0.49
6886 09:54:18.314455 # ok 313 write_invalid.0.49
6887 09:54:18.318245 # ok 314 event_missing.0.49
6888 09:54:18.321307 # ok 315 event_spurious.0.49
6889 09:54:18.321739 # ok 316 get_value.0.48
6890 09:54:18.327723 # # 0.48 I2S3_CH1 DL3_CH1 is a writeable boolean but not a Switch
6891 09:54:18.331169 # not ok 317 name.0.48
6892 09:54:18.334587 # ok 318 write_default.0.48
6893 09:54:18.335098 # ok 319 write_valid.0.48
6894 09:54:18.337746 # ok 320 write_invalid.0.48
6895 09:54:18.341124 # ok 321 event_missing.0.48
6896 09:54:18.344476 # ok 322 event_spurious.0.48
6897 09:54:18.345047 # ok 323 get_value.0.47
6898 09:54:18.350826 # # 0.47 I2S3_CH1 DL2_CH1 is a writeable boolean but not a Switch
6899 09:54:18.354474 # not ok 324 name.0.47
6900 09:54:18.354988 # ok 325 write_default.0.47
6901 09:54:18.357580 # ok 326 write_valid.0.47
6902 09:54:18.360971 # ok 327 write_invalid.0.47
6903 09:54:18.363958 # ok 328 event_missing.0.47
6904 09:54:18.364401 # ok 329 event_spurious.0.47
6905 09:54:18.367563 # ok 330 get_value.0.46
6906 09:54:18.374556 # # 0.46 I2S3_CH1 DL1_CH1 is a writeable boolean but not a Switch
6907 09:54:18.377448 # not ok 331 name.0.46
6908 09:54:18.377959 # ok 332 write_default.0.46
6909 09:54:18.380909 # ok 333 write_valid.0.46
6910 09:54:18.384290 # ok 334 write_invalid.0.46
6911 09:54:18.387330 # ok 335 event_missing.0.46
6912 09:54:18.390920 # ok 336 event_spurious.0.46
6913 09:54:18.391428 # ok 337 get_value.0.45
6914 09:54:18.397462 # # 0.45 I2S1_CH2 DL3_CH2 is a writeable boolean but not a Switch
6915 09:54:18.400465 # not ok 338 name.0.45
6916 09:54:18.400892 # ok 339 write_default.0.45
6917 09:54:18.403901 # ok 340 write_valid.0.45
6918 09:54:18.407155 # ok 341 write_invalid.0.45
6919 09:54:18.410518 # ok 342 event_missing.0.45
6920 09:54:18.413608 # ok 343 event_spurious.0.45
6921 09:54:18.414083 # ok 344 get_value.0.44
6922 09:54:18.420344 # # 0.44 I2S1_CH2 DL2_CH2 is a writeable boolean but not a Switch
6923 09:54:18.423901 # not ok 345 name.0.44
6924 09:54:18.424331 # ok 346 write_default.0.44
6925 09:54:18.426971 # ok 347 write_valid.0.44
6926 09:54:18.430310 # ok 348 write_invalid.0.44
6927 09:54:18.433435 # ok 349 event_missing.0.44
6928 09:54:18.433863 # ok 350 event_spurious.0.44
6929 09:54:18.437289 # ok 351 get_value.0.43
6930 09:54:18.443664 # # 0.43 I2S1_CH2 DL1_CH2 is a writeable boolean but not a Switch
6931 09:54:18.444168 # not ok 352 name.0.43
6932 09:54:18.446875 # ok 353 write_default.0.43
6933 09:54:18.450082 # ok 354 write_valid.0.43
6934 09:54:18.453708 # ok 355 write_invalid.0.43
6935 09:54:18.454475 # ok 356 event_missing.0.43
6936 09:54:18.456838 # ok 357 event_spurious.0.43
6937 09:54:18.460051 # ok 358 get_value.0.42
6938 09:54:18.466687 # # 0.42 I2S1_CH1 DL3_CH1 is a writeable boolean but not a Switch
6939 09:54:18.467117 # not ok 359 name.0.42
6940 09:54:18.470080 # ok 360 write_default.0.42
6941 09:54:18.473721 # ok 361 write_valid.0.42
6942 09:54:18.474289 # ok 362 write_invalid.0.42
6943 09:54:18.476652 # ok 363 event_missing.0.42
6944 09:54:18.480269 # ok 364 event_spurious.0.42
6945 09:54:18.483836 # ok 365 get_value.0.41
6946 09:54:18.486744 # # 0.41 I2S1_CH1 DL2_CH1 is a writeable boolean but not a Switch
6947 09:54:18.489900 # not ok 366 name.0.41
6948 09:54:18.493386 # ok 367 write_default.0.41
6949 09:54:18.496734 # ok 368 write_valid.0.41
6950 09:54:18.497160 # ok 369 write_invalid.0.41
6951 09:54:18.499920 # ok 370 event_missing.0.41
6952 09:54:18.502860 # ok 371 event_spurious.0.41
6953 09:54:18.503351 # ok 372 get_value.0.40
6954 09:54:18.509583 # # 0.40 I2S1_CH1 DL1_CH1 is a writeable boolean but not a Switch
6955 09:54:18.512878 # not ok 373 name.0.40
6956 09:54:18.516480 # ok 374 write_default.0.40
6957 09:54:18.516908 # ok 375 write_valid.0.40
6958 09:54:18.519715 # ok 376 write_invalid.0.40
6959 09:54:18.523270 # ok 377 event_missing.0.40
6960 09:54:18.526347 # ok 378 event_spurious.0.40
6961 09:54:18.526778 # ok 379 get_value.0.39
6962 09:54:18.532929 # # 0.39 PCM_2_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
6963 09:54:18.536403 # not ok 380 name.0.39
6964 09:54:18.539534 # ok 381 write_default.0.39
6965 09:54:18.539966 # ok 382 write_valid.0.39
6966 09:54:18.542823 # ok 383 write_invalid.0.39
6967 09:54:18.546022 # ok 384 event_missing.0.39
6968 09:54:18.549431 # ok 385 event_spurious.0.39
6969 09:54:18.549865 # ok 386 get_value.0.38
6970 09:54:18.556438 # # 0.38 PCM_2_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
6971 09:54:18.559416 # not ok 387 name.0.38
6972 09:54:18.559895 # ok 388 write_default.0.38
6973 09:54:18.562840 # ok 389 write_valid.0.38
6974 09:54:18.565883 # ok 390 write_invalid.0.38
6975 09:54:18.569408 # ok 391 event_missing.0.38
6976 09:54:18.569916 # ok 392 event_spurious.0.38
6977 09:54:18.573110 # ok 393 get_value.0.37
6978 09:54:18.579785 # # 0.37 PCM_2_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
6979 09:54:18.582915 # not ok 394 name.0.37
6980 09:54:18.583426 # ok 395 write_default.0.37
6981 09:54:18.586263 # ok 396 write_valid.0.37
6982 09:54:18.589583 # ok 397 write_invalid.0.37
6983 09:54:18.592419 # ok 398 event_missing.0.37
6984 09:54:18.592852 # ok 399 event_spurious.0.37
6985 09:54:18.596377 # ok 400 get_value.0.36
6986 09:54:18.602446 # # 0.36 PCM_2_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
6987 09:54:18.606063 # not ok 401 name.0.36
6988 09:54:18.606624 # ok 402 write_default.0.36
6989 09:54:18.609290 # ok 403 write_valid.0.36
6990 09:54:18.612403 # ok 404 write_invalid.0.36
6991 09:54:18.615624 # ok 405 event_missing.0.36
6992 09:54:18.616058 # ok 406 event_spurious.0.36
6993 09:54:18.618782 # ok 407 get_value.0.35
6994 09:54:18.625744 # # 0.35 PCM_2_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
6995 09:54:18.628929 # not ok 408 name.0.35
6996 09:54:18.632490 # ok 409 write_default.0.35
6997 09:54:18.633053 # ok 410 write_valid.0.35
6998 09:54:18.635890 # ok 411 write_invalid.0.35
6999 09:54:18.638929 # ok 412 event_missing.0.35
7000 09:54:18.642172 # ok 413 event_spurious.0.35
7001 09:54:18.642764 # ok 414 get_value.0.34
7002 09:54:18.649174 # # 0.34 PCM_1_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7003 09:54:18.652644 # not ok 415 name.0.34
7004 09:54:18.655576 # ok 416 write_default.0.34
7005 09:54:18.656014 # ok 417 write_valid.0.34
7006 09:54:18.658792 # ok 418 write_invalid.0.34
7007 09:54:18.662414 # ok 419 event_missing.0.34
7008 09:54:18.665801 # ok 420 event_spurious.0.34
7009 09:54:18.668855 # ok 421 get_value.0.33
7010 09:54:18.675805 # # 0.33 PCM_1_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7011 09:54:18.676321 # not ok 422 name.0.33
7012 09:54:18.678918 # ok 423 write_default.0.33
7013 09:54:18.682434 # ok 424 write_valid.0.33
7014 09:54:18.685613 # ok 425 write_invalid.0.33
7015 09:54:18.686129 # ok 426 event_missing.0.33
7016 09:54:18.688801 # ok 427 event_spurious.0.33
7017 09:54:18.692415 # ok 428 get_value.0.32
7018 09:54:18.698968 # # 0.32 PCM_1_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7019 09:54:18.699484 # not ok 429 name.0.32
7020 09:54:18.702488 # ok 430 write_default.0.32
7021 09:54:18.705731 # ok 431 write_valid.0.32
7022 09:54:18.709052 # ok 432 write_invalid.0.32
7023 09:54:18.712191 # ok 433 event_missing.0.32
7024 09:54:18.712697 # ok 434 event_spurious.0.32
7025 09:54:18.716015 # ok 435 get_value.0.31
7026 09:54:18.722314 # # 0.31 PCM_1_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7027 09:54:18.725631 # not ok 436 name.0.31
7028 09:54:18.726141 # ok 437 write_default.0.31
7029 09:54:18.728762 # ok 438 write_valid.0.31
7030 09:54:18.731799 # ok 439 write_invalid.0.31
7031 09:54:18.735730 # ok 440 event_missing.0.31
7032 09:54:18.738517 # ok 441 event_spurious.0.31
7033 09:54:18.738944 # ok 442 get_value.0.30
7034 09:54:18.744945 # # 0.30 PCM_1_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7035 09:54:18.748647 # not ok 443 name.0.30
7036 09:54:18.751944 # ok 444 write_default.0.30
7037 09:54:18.752465 # ok 445 write_valid.0.30
7038 09:54:18.755052 # ok 446 write_invalid.0.30
7039 09:54:18.758695 # ok 447 event_missing.0.30
7040 09:54:18.762085 # ok 448 event_spurious.0.30
7041 09:54:18.762642 # ok 449 get_value.0.29
7042 09:54:18.765247 # ok 450 name.0.29
7043 09:54:18.768598 # ok 451 write_default.0.29
7044 09:54:18.772098 # ok 452 write_valid.0.29
7045 09:54:18.772626 # ok 453 write_invalid.0.29
7046 09:54:18.774997 # ok 454 event_missing.0.29
7047 09:54:18.778766 # ok 455 event_spurious.0.29
7048 09:54:18.781672 # ok 456 get_value.0.28
7049 09:54:18.782187 # ok 457 name.0.28
7050 09:54:18.785007 # ok 458 write_default.0.28
7051 09:54:18.788392 # ok 459 write_valid.0.28
7052 09:54:18.788902 # ok 460 write_invalid.0.28
7053 09:54:18.791594 # ok 461 event_missing.0.28
7054 09:54:18.794729 # ok 462 event_spurious.0.28
7055 09:54:18.798348 # ok 463 get_value.0.27
7056 09:54:18.798856 # ok 464 name.0.27
7057 09:54:18.801854 # ok 465 write_default.0.27
7058 09:54:18.805006 # ok 466 write_valid.0.27
7059 09:54:18.808254 # ok 467 write_invalid.0.27
7060 09:54:18.808765 # ok 468 event_missing.0.27
7061 09:54:18.811482 # ok 469 event_spurious.0.27
7062 09:54:18.814775 # ok 470 get_value.0.26
7063 09:54:18.815204 # ok 471 name.0.26
7064 09:54:18.818348 # ok 472 write_default.0.26
7065 09:54:18.821581 # ok 473 write_valid.0.26
7066 09:54:18.824996 # ok 474 write_invalid.0.26
7067 09:54:18.827850 # ok 475 event_missing.0.26
7068 09:54:18.828287 # ok 476 event_spurious.0.26
7069 09:54:18.831308 # ok 477 get_value.0.25
7070 09:54:18.834924 # ok 478 name.0.25
7071 09:54:18.835434 # ok 479 write_default.0.25
7072 09:54:18.838615 # ok 480 write_valid.0.25
7073 09:54:18.841294 # ok 481 write_invalid.0.25
7074 09:54:18.844391 # ok 482 event_missing.0.25
7075 09:54:18.844820 # ok 483 event_spurious.0.25
7076 09:54:18.847799 # ok 484 get_value.0.24
7077 09:54:18.851378 # ok 485 name.0.24
7078 09:54:18.851895 # ok 486 write_default.0.24
7079 09:54:18.856517 # ok 487 write_valid.0.24
7080 09:54:18.857986 # ok 488 write_invalid.0.24
7081 09:54:18.861346 # ok 489 event_missing.0.24
7082 09:54:18.864753 # ok 490 event_spurious.0.24
7083 09:54:18.865263 # ok 491 get_value.0.23
7084 09:54:18.868142 # ok 492 name.0.23
7085 09:54:18.871162 # ok 493 write_default.0.23
7086 09:54:18.871651 # ok 494 write_valid.0.23
7087 09:54:18.874868 # ok 495 write_invalid.0.23
7088 09:54:18.877904 # ok 496 event_missing.0.23
7089 09:54:18.881482 # ok 497 event_spurious.0.23
7090 09:54:18.881996 # ok 498 get_value.0.22
7091 09:54:18.884709 # ok 499 name.0.22
7092 09:54:18.885215 # ok 500 write_default.0.22
7093 09:54:18.888361 # ok 501 write_valid.0.22
7094 09:54:18.891246 # ok 502 write_invalid.0.22
7095 09:54:18.894597 # ok 503 event_missing.0.22
7096 09:54:18.895113 # ok 504 event_spurious.0.22
7097 09:54:18.897858 # ok 505 get_value.0.21
7098 09:54:18.904344 # # 0.21 UL_MONO_1_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7099 09:54:18.907877 # not ok 506 name.0.21
7100 09:54:18.911053 # ok 507 write_default.0.21
7101 09:54:18.911573 # ok 508 write_valid.0.21
7102 09:54:18.914316 # ok 509 write_invalid.0.21
7103 09:54:18.917530 # ok 510 event_missing.0.21
7104 09:54:18.920936 # ok 511 event_spurious.0.21
7105 09:54:18.921447 # ok 512 get_value.0.20
7106 09:54:18.927847 # # 0.20 UL_MONO_1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7107 09:54:18.930725 # not ok 513 name.0.20
7108 09:54:18.933778 # ok 514 write_default.0.20
7109 09:54:18.934208 # ok 515 write_valid.0.20
7110 09:54:18.937383 # ok 516 write_invalid.0.20
7111 09:54:18.940687 # ok 517 event_missing.0.20
7112 09:54:18.943896 # ok 518 event_spurious.0.20
7113 09:54:18.944332 # ok 519 get_value.0.19
7114 09:54:18.950475 # # 0.19 UL4_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7115 09:54:18.953940 # not ok 520 name.0.19
7116 09:54:18.957287 # ok 521 write_default.0.19
7117 09:54:18.957798 # ok 522 write_valid.0.19
7118 09:54:18.960654 # ok 523 write_invalid.0.19
7119 09:54:18.964013 # ok 524 event_missing.0.19
7120 09:54:18.967379 # ok 525 event_spurious.0.19
7121 09:54:18.967889 # ok 526 get_value.0.18
7122 09:54:18.973771 # # 0.18 UL4_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7123 09:54:18.976872 # not ok 527 name.0.18
7124 09:54:18.977303 # ok 528 write_default.0.18
7125 09:54:18.980148 # ok 529 write_valid.0.18
7126 09:54:18.983872 # ok 530 write_invalid.0.18
7127 09:54:18.987170 # ok 531 event_missing.0.18
7128 09:54:18.987678 # ok 532 event_spurious.0.18
7129 09:54:18.990641 # ok 533 get_value.0.17
7130 09:54:18.997308 # # 0.17 UL3_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7131 09:54:18.997818 # not ok 534 name.0.17
7132 09:54:19.000435 # ok 535 write_default.0.17
7133 09:54:19.003497 # ok 536 write_valid.0.17
7134 09:54:19.007011 # ok 537 write_invalid.0.17
7135 09:54:19.007528 # ok 538 event_missing.0.17
7136 09:54:19.010256 # ok 539 event_spurious.0.17
7137 09:54:19.013539 # ok 540 get_value.0.16
7138 09:54:19.020465 # # 0.16 UL3_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7139 09:54:19.020979 # not ok 541 name.0.16
7140 09:54:19.023351 # ok 542 write_default.0.16
7141 09:54:19.027080 # ok 543 write_valid.0.16
7142 09:54:19.029930 # ok 544 write_invalid.0.16
7143 09:54:19.030399 # ok 545 event_missing.0.16
7144 09:54:19.033317 # ok 546 event_spurious.0.16
7145 09:54:19.037019 # ok 547 get_value.0.15
7146 09:54:19.043169 # # 0.15 UL3_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7147 09:54:19.043745 # not ok 548 name.0.15
7148 09:54:19.046965 # ok 549 write_default.0.15
7149 09:54:19.050122 # ok 550 write_valid.0.15
7150 09:54:19.053476 # ok 551 write_invalid.0.15
7151 09:54:19.053986 # ok 552 event_missing.0.15
7152 09:54:19.056664 # ok 553 event_spurious.0.15
7153 09:54:19.060022 # ok 554 get_value.0.14
7154 09:54:19.066419 # # 0.14 UL3_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7155 09:54:19.066919 # not ok 555 name.0.14
7156 09:54:19.070047 # ok 556 write_default.0.14
7157 09:54:19.073356 # ok 557 write_valid.0.14
7158 09:54:19.076953 # ok 558 write_invalid.0.14
7159 09:54:19.077469 # ok 559 event_missing.0.14
7160 09:54:19.080037 # ok 560 event_spurious.0.14
7161 09:54:19.083395 # ok 561 get_value.0.13
7162 09:54:19.089820 # # 0.13 UL2_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7163 09:54:19.090350 # not ok 562 name.0.13
7164 09:54:19.093220 # ok 563 write_default.0.13
7165 09:54:19.096350 # ok 564 write_valid.0.13
7166 09:54:19.099632 # ok 565 write_invalid.0.13
7167 09:54:19.100193 # ok 566 event_missing.0.13
7168 09:54:19.103157 # ok 567 event_spurious.0.13
7169 09:54:19.106352 # ok 568 get_value.0.12
7170 09:54:19.113523 # # 0.12 UL2_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7171 09:54:19.114042 # not ok 569 name.0.12
7172 09:54:19.116203 # ok 570 write_default.0.12
7173 09:54:19.119847 # ok 571 write_valid.0.12
7174 09:54:19.120361 # ok 572 write_invalid.0.12
7175 09:54:19.122920 # ok 573 event_missing.0.12
7176 09:54:19.126585 # ok 574 event_spurious.0.12
7177 09:54:19.129524 # ok 575 get_value.0.11
7178 09:54:19.132635 # # 0.11 UL2_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7179 09:54:19.136271 # not ok 576 name.0.11
7180 09:54:19.139627 # ok 577 write_default.0.11
7181 09:54:19.140141 # ok 578 write_valid.0.11
7182 09:54:19.142839 # ok 579 write_invalid.0.11
7183 09:54:19.146396 # ok 580 event_missing.0.11
7184 09:54:19.149771 # ok 581 event_spurious.0.11
7185 09:54:19.150321 # ok 582 get_value.0.10
7186 09:54:19.155860 # # 0.10 UL2_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7187 09:54:19.159376 # not ok 583 name.0.10
7188 09:54:19.162839 # ok 584 write_default.0.10
7189 09:54:19.163349 # ok 585 write_valid.0.10
7190 09:54:19.166018 # ok 586 write_invalid.0.10
7191 09:54:19.169315 # ok 587 event_missing.0.10
7192 09:54:19.172602 # ok 588 event_spurious.0.10
7193 09:54:19.173114 # ok 589 get_value.0.9
7194 09:54:19.179160 # # 0.9 UL1_CH2 I2S0_CH2 is a writeable boolean but not a Switch
7195 09:54:19.182573 # not ok 590 name.0.9
7196 09:54:19.183084 # ok 591 write_default.0.9
7197 09:54:19.185994 # ok 592 write_valid.0.9
7198 09:54:19.188939 # ok 593 write_invalid.0.9
7199 09:54:19.192727 # ok 594 event_missing.0.9
7200 09:54:19.193239 # ok 595 event_spurious.0.9
7201 09:54:19.195779 # ok 596 get_value.0.8
7202 09:54:19.202205 # # 0.8 UL1_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7203 09:54:19.202765 # not ok 597 name.0.8
7204 09:54:19.205622 # ok 598 write_default.0.8
7205 09:54:19.209013 # ok 599 write_valid.0.8
7206 09:54:19.209524 # ok 600 write_invalid.0.8
7207 09:54:19.212321 # ok 601 event_missing.0.8
7208 09:54:19.215484 # ok 602 event_spurious.0.8
7209 09:54:19.219018 # ok 603 get_value.0.7
7210 09:54:19.222464 # # 0.7 UL1_CH1 I2S0_CH1 is a writeable boolean but not a Switch
7211 09:54:19.225717 # not ok 604 name.0.7
7212 09:54:19.228704 # ok 605 write_default.0.7
7213 09:54:19.229138 # ok 606 write_valid.0.7
7214 09:54:19.232277 # ok 607 write_invalid.0.7
7215 09:54:19.236006 # ok 608 event_missing.0.7
7216 09:54:19.238995 # ok 609 event_spurious.0.7
7217 09:54:19.239426 # ok 610 get_value.0.6
7218 09:54:19.245636 # # 0.6 UL1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7219 09:54:19.248915 # not ok 611 name.0.6
7220 09:54:19.252439 # ok 612 write_default.0.6
7221 09:54:19.252949 # ok 613 write_valid.0.6
7222 09:54:19.255436 # ok 614 write_invalid.0.6
7223 09:54:19.258929 # ok 615 event_missing.0.6
7224 09:54:19.262374 # ok 616 event_spurious.0.6
7225 09:54:19.262887 # ok 617 get_value.0.5
7226 09:54:19.265559 # ok 618 name.0.5
7227 09:54:19.266068 # ok 619 write_default.0.5
7228 09:54:19.272257 # # No event generated for MTKAIF_DMIC
7229 09:54:19.275840 # # No event generated for MTKAIF_DMIC
7230 09:54:19.276351 # ok 620 write_valid.0.5
7231 09:54:19.278825 # ok 621 write_invalid.0.5
7232 09:54:19.282372 # not ok 622 event_missing.0.5
7233 09:54:19.285571 # ok 623 event_spurious.0.5
7234 09:54:19.286083 # ok 624 get_value.0.4
7235 09:54:19.288886 # ok 625 name.0.4
7236 09:54:19.291928 # ok 626 write_default.0.4
7237 09:54:19.295377 # # No event generated for I2S5_HD_Mux
7238 09:54:19.298747 # # No event generated for I2S5_HD_Mux
7239 09:54:19.302147 # ok 627 write_valid.0.4
7240 09:54:19.302700 # ok 628 write_invalid.0.4
7241 09:54:19.305461 # not ok 629 event_missing.0.4
7242 09:54:19.308431 # ok 630 event_spurious.0.4
7243 09:54:19.311818 # ok 631 get_value.0.3
7244 09:54:19.312249 # ok 632 name.0.3
7245 09:54:19.315191 # ok 633 write_default.0.3
7246 09:54:19.318412 # # No event generated for I2S3_HD_Mux
7247 09:54:19.321693 # # No event generated for I2S3_HD_Mux
7248 09:54:19.325015 # ok 634 write_valid.0.3
7249 09:54:19.325444 # ok 635 write_invalid.0.3
7250 09:54:19.328322 # not ok 636 event_missing.0.3
7251 09:54:19.331878 # ok 637 event_spurious.0.3
7252 09:54:19.335223 # ok 638 get_value.0.2
7253 09:54:19.335711 # ok 639 name.0.2
7254 09:54:19.338617 # ok 640 write_default.0.2
7255 09:54:19.341807 # # No event generated for I2S2_HD_Mux
7256 09:54:19.345180 # # No event generated for I2S2_HD_Mux
7257 09:54:19.348265 # ok 641 write_valid.0.2
7258 09:54:19.348698 # ok 642 write_invalid.0.2
7259 09:54:19.351764 # not ok 643 event_missing.0.2
7260 09:54:19.355075 # ok 644 event_spurious.0.2
7261 09:54:19.358314 # ok 645 get_value.0.1
7262 09:54:19.358743 # ok 646 name.0.1
7263 09:54:19.361755 # ok 647 write_default.0.1
7264 09:54:19.365044 # # No event generated for I2S1_HD_Mux
7265 09:54:19.368220 # # No event generated for I2S1_HD_Mux
7266 09:54:19.371528 # ok 648 write_valid.0.1
7267 09:54:19.371958 # ok 649 write_invalid.0.1
7268 09:54:19.374774 # not ok 650 event_missing.0.1
7269 09:54:19.378117 # ok 651 event_spurious.0.1
7270 09:54:19.381257 # ok 652 get_value.0.0
7271 09:54:19.381741 # ok 653 name.0.0
7272 09:54:19.384616 # ok 654 write_default.0.0
7273 09:54:19.388022 # # No event generated for I2S0_HD_Mux
7274 09:54:19.391312 # # No event generated for I2S0_HD_Mux
7275 09:54:19.394582 # ok 655 write_valid.0.0
7276 09:54:19.395009 # ok 656 write_invalid.0.0
7277 09:54:19.397822 # not ok 657 event_missing.0.0
7278 09:54:19.401136 # ok 658 event_spurious.0.0
7279 09:54:19.407798 # # Totals: pass:568 fail:87 xfail:0 xpass:0 skip:3 error:0
7280 09:54:19.408228 ok 1 selftests: alsa: mixer-test
7281 09:54:21.013808 alsa_mixer-test_get_value_0_93 pass
7282 09:54:21.017370 alsa_mixer-test_name_0_93 pass
7283 09:54:21.020152 alsa_mixer-test_write_default_0_93 pass
7284 09:54:21.023760 alsa_mixer-test_write_valid_0_93 pass
7285 09:54:21.027030 alsa_mixer-test_write_invalid_0_93 pass
7286 09:54:21.030652 alsa_mixer-test_event_missing_0_93 pass
7287 09:54:21.037349 alsa_mixer-test_event_spurious_0_93 pass
7288 09:54:21.040424 alsa_mixer-test_get_value_0_92 pass
7289 09:54:21.040874 alsa_mixer-test_name_0_92 pass
7290 09:54:21.043752 alsa_mixer-test_write_default_0_92 pass
7291 09:54:21.046981 alsa_mixer-test_write_valid_0_92 pass
7292 09:54:21.053850 alsa_mixer-test_write_invalid_0_92 pass
7293 09:54:21.057109 alsa_mixer-test_event_missing_0_92 pass
7294 09:54:21.060523 alsa_mixer-test_event_spurious_0_92 pass
7295 09:54:21.063653 alsa_mixer-test_get_value_0_91 pass
7296 09:54:21.066978 alsa_mixer-test_name_0_91 pass
7297 09:54:21.070386 alsa_mixer-test_write_default_0_91 pass
7298 09:54:21.073586 alsa_mixer-test_write_valid_0_91 pass
7299 09:54:21.077041 alsa_mixer-test_write_invalid_0_91 pass
7300 09:54:21.080388 alsa_mixer-test_event_missing_0_91 pass
7301 09:54:21.083817 alsa_mixer-test_event_spurious_0_91 pass
7302 09:54:21.087180 alsa_mixer-test_get_value_0_90 pass
7303 09:54:21.090360 alsa_mixer-test_name_0_90 pass
7304 09:54:21.093884 alsa_mixer-test_write_default_0_90 pass
7305 09:54:21.097256 alsa_mixer-test_write_valid_0_90 pass
7306 09:54:21.100257 alsa_mixer-test_write_invalid_0_90 pass
7307 09:54:21.103591 alsa_mixer-test_event_missing_0_90 pass
7308 09:54:21.106867 alsa_mixer-test_event_spurious_0_90 pass
7309 09:54:21.110454 alsa_mixer-test_get_value_0_89 pass
7310 09:54:21.113827 alsa_mixer-test_name_0_89 pass
7311 09:54:21.117440 alsa_mixer-test_write_default_0_89 pass
7312 09:54:21.120515 alsa_mixer-test_write_valid_0_89 pass
7313 09:54:21.123662 alsa_mixer-test_write_invalid_0_89 pass
7314 09:54:21.130444 alsa_mixer-test_event_missing_0_89 pass
7315 09:54:21.133766 alsa_mixer-test_event_spurious_0_89 pass
7316 09:54:21.137075 alsa_mixer-test_get_value_0_88 pass
7317 09:54:21.140305 alsa_mixer-test_name_0_88 pass
7318 09:54:21.143542 alsa_mixer-test_write_default_0_88 pass
7319 09:54:21.147230 alsa_mixer-test_write_valid_0_88 fail
7320 09:54:21.150527 alsa_mixer-test_write_invalid_0_88 pass
7321 09:54:21.153830 alsa_mixer-test_event_missing_0_88 pass
7322 09:54:21.157138 alsa_mixer-test_event_spurious_0_88 fail
7323 09:54:21.160754 alsa_mixer-test_get_value_0_87 pass
7324 09:54:21.163757 alsa_mixer-test_name_0_87 pass
7325 09:54:21.170576 alsa_mixer-test_write_default_0_87 pass
7326 09:54:21.174251 alsa_mixer-test_write_valid_0_87 pass
7327 09:54:21.177165 alsa_mixer-test_write_invalid_0_87 pass
7328 09:54:21.180292 alsa_mixer-test_event_missing_0_87 pass
7329 09:54:21.183880 alsa_mixer-test_event_spurious_0_87 pass
7330 09:54:21.187371 alsa_mixer-test_get_value_0_86 pass
7331 09:54:21.190605 alsa_mixer-test_name_0_86 pass
7332 09:54:21.194157 alsa_mixer-test_write_default_0_86 pass
7333 09:54:21.197351 alsa_mixer-test_write_valid_0_86 fail
7334 09:54:21.204108 alsa_mixer-test_write_invalid_0_86 pass
7335 09:54:21.207463 alsa_mixer-test_event_missing_0_86 pass
7336 09:54:21.210896 alsa_mixer-test_event_spurious_0_86 pass
7337 09:54:21.214095 alsa_mixer-test_get_value_0_85 pass
7338 09:54:21.217109 alsa_mixer-test_name_0_85 pass
7339 09:54:21.220729 alsa_mixer-test_write_default_0_85 pass
7340 09:54:21.224002 alsa_mixer-test_write_valid_0_85 fail
7341 09:54:21.227403 alsa_mixer-test_write_invalid_0_85 pass
7342 09:54:21.234312 alsa_mixer-test_event_missing_0_85 pass
7343 09:54:21.237649 alsa_mixer-test_event_spurious_0_85 pass
7344 09:54:21.240854 alsa_mixer-test_get_value_0_84 pass
7345 09:54:21.244337 alsa_mixer-test_name_0_84 pass
7346 09:54:21.247247 alsa_mixer-test_write_default_0_84 pass
7347 09:54:21.250642 alsa_mixer-test_write_valid_0_84 pass
7348 09:54:21.254069 alsa_mixer-test_write_invalid_0_84 pass
7349 09:54:21.257694 alsa_mixer-test_event_missing_0_84 pass
7350 09:54:21.261060 alsa_mixer-test_event_spurious_0_84 pass
7351 09:54:21.267437 alsa_mixer-test_get_value_0_83 pass
7352 09:54:21.267957 alsa_mixer-test_name_0_83 pass
7353 09:54:21.274182 alsa_mixer-test_write_default_0_83 pass
7354 09:54:21.277550 alsa_mixer-test_write_valid_0_83 pass
7355 09:54:21.280558 alsa_mixer-test_write_invalid_0_83 pass
7356 09:54:21.284258 alsa_mixer-test_event_missing_0_83 pass
7357 09:54:21.287290 alsa_mixer-test_event_spurious_0_83 pass
7358 09:54:21.290396 alsa_mixer-test_get_value_0_82 pass
7359 09:54:21.294086 alsa_mixer-test_name_0_82 pass
7360 09:54:21.296852 alsa_mixer-test_write_default_0_82 skip
7361 09:54:21.303757 alsa_mixer-test_write_valid_0_82 skip
7362 09:54:21.306894 alsa_mixer-test_write_invalid_0_82 skip
7363 09:54:21.310457 alsa_mixer-test_event_missing_0_82 pass
7364 09:54:21.314259 alsa_mixer-test_event_spurious_0_82 pass
7365 09:54:21.317390 alsa_mixer-test_get_value_0_81 pass
7366 09:54:21.320529 alsa_mixer-test_name_0_81 pass
7367 09:54:21.323544 alsa_mixer-test_write_default_0_81 pass
7368 09:54:21.327020 alsa_mixer-test_write_valid_0_81 pass
7369 09:54:21.333617 alsa_mixer-test_write_invalid_0_81 fail
7370 09:54:21.336986 alsa_mixer-test_event_missing_0_81 fail
7371 09:54:21.340123 alsa_mixer-test_event_spurious_0_81 pass
7372 09:54:21.343696 alsa_mixer-test_get_value_0_80 pass
7373 09:54:21.347101 alsa_mixer-test_name_0_80 pass
7374 09:54:21.350331 alsa_mixer-test_write_default_0_80 pass
7375 09:54:21.353668 alsa_mixer-test_write_valid_0_80 pass
7376 09:54:21.356991 alsa_mixer-test_write_invalid_0_80 pass
7377 09:54:21.360168 alsa_mixer-test_event_missing_0_80 pass
7378 09:54:21.363478 alsa_mixer-test_event_spurious_0_80 pass
7379 09:54:21.366604 alsa_mixer-test_get_value_0_79 fail
7380 09:54:21.370178 alsa_mixer-test_name_0_79 pass
7381 09:54:21.373514 alsa_mixer-test_write_default_0_79 fail
7382 09:54:21.376768 alsa_mixer-test_write_valid_0_79 fail
7383 09:54:21.380004 alsa_mixer-test_write_invalid_0_79 fail
7384 09:54:21.383727 alsa_mixer-test_event_missing_0_79 pass
7385 09:54:21.390022 alsa_mixer-test_event_spurious_0_79 pass
7386 09:54:21.393504 alsa_mixer-test_get_value_0_78 fail
7387 09:54:21.394033 alsa_mixer-test_name_0_78 pass
7388 09:54:21.400065 alsa_mixer-test_write_default_0_78 fail
7389 09:54:21.403204 alsa_mixer-test_write_valid_0_78 fail
7390 09:54:21.406467 alsa_mixer-test_write_invalid_0_78 fail
7391 09:54:21.409900 alsa_mixer-test_event_missing_0_78 pass
7392 09:54:21.413153 alsa_mixer-test_event_spurious_0_78 pass
7393 09:54:21.416495 alsa_mixer-test_get_value_0_77 fail
7394 09:54:21.419648 alsa_mixer-test_name_0_77 pass
7395 09:54:21.423168 alsa_mixer-test_write_default_0_77 fail
7396 09:54:21.426698 alsa_mixer-test_write_valid_0_77 fail
7397 09:54:21.429853 alsa_mixer-test_write_invalid_0_77 fail
7398 09:54:21.433314 alsa_mixer-test_event_missing_0_77 pass
7399 09:54:21.436591 alsa_mixer-test_event_spurious_0_77 pass
7400 09:54:21.439691 alsa_mixer-test_get_value_0_76 pass
7401 09:54:21.443323 alsa_mixer-test_name_0_76 fail
7402 09:54:21.446326 alsa_mixer-test_write_default_0_76 pass
7403 09:54:21.453274 alsa_mixer-test_write_valid_0_76 pass
7404 09:54:21.456593 alsa_mixer-test_write_invalid_0_76 pass
7405 09:54:21.459752 alsa_mixer-test_event_missing_0_76 pass
7406 09:54:21.462924 alsa_mixer-test_event_spurious_0_76 pass
7407 09:54:21.466635 alsa_mixer-test_get_value_0_75 pass
7408 09:54:21.470102 alsa_mixer-test_name_0_75 fail
7409 09:54:21.472894 alsa_mixer-test_write_default_0_75 pass
7410 09:54:21.476488 alsa_mixer-test_write_valid_0_75 pass
7411 09:54:21.479865 alsa_mixer-test_write_invalid_0_75 pass
7412 09:54:21.483079 alsa_mixer-test_event_missing_0_75 pass
7413 09:54:21.486539 alsa_mixer-test_event_spurious_0_75 pass
7414 09:54:21.489726 alsa_mixer-test_get_value_0_74 pass
7415 09:54:21.493125 alsa_mixer-test_name_0_74 fail
7416 09:54:21.496489 alsa_mixer-test_write_default_0_74 pass
7417 09:54:21.499860 alsa_mixer-test_write_valid_0_74 pass
7418 09:54:21.503307 alsa_mixer-test_write_invalid_0_74 pass
7419 09:54:21.506656 alsa_mixer-test_event_missing_0_74 pass
7420 09:54:21.509610 alsa_mixer-test_event_spurious_0_74 pass
7421 09:54:21.513019 alsa_mixer-test_get_value_0_73 pass
7422 09:54:21.516333 alsa_mixer-test_name_0_73 fail
7423 09:54:21.519641 alsa_mixer-test_write_default_0_73 pass
7424 09:54:21.522913 alsa_mixer-test_write_valid_0_73 pass
7425 09:54:21.526418 alsa_mixer-test_write_invalid_0_73 pass
7426 09:54:21.529738 alsa_mixer-test_event_missing_0_73 pass
7427 09:54:21.533021 alsa_mixer-test_event_spurious_0_73 pass
7428 09:54:21.536280 alsa_mixer-test_get_value_0_72 pass
7429 09:54:21.539290 alsa_mixer-test_name_0_72 fail
7430 09:54:21.542528 alsa_mixer-test_write_default_0_72 pass
7431 09:54:21.545761 alsa_mixer-test_write_valid_0_72 pass
7432 09:54:21.549130 alsa_mixer-test_write_invalid_0_72 pass
7433 09:54:21.556420 alsa_mixer-test_event_missing_0_72 pass
7434 09:54:21.559460 alsa_mixer-test_event_spurious_0_72 pass
7435 09:54:21.562553 alsa_mixer-test_get_value_0_71 pass
7436 09:54:21.563065 alsa_mixer-test_name_0_71 fail
7437 09:54:21.565815 alsa_mixer-test_write_default_0_71 pass
7438 09:54:21.569496 alsa_mixer-test_write_valid_0_71 pass
7439 09:54:21.575865 alsa_mixer-test_write_invalid_0_71 pass
7440 09:54:21.579271 alsa_mixer-test_event_missing_0_71 pass
7441 09:54:21.582766 alsa_mixer-test_event_spurious_0_71 pass
7442 09:54:21.585874 alsa_mixer-test_get_value_0_70 pass
7443 09:54:21.589333 alsa_mixer-test_name_0_70 fail
7444 09:54:21.592649 alsa_mixer-test_write_default_0_70 pass
7445 09:54:21.595834 alsa_mixer-test_write_valid_0_70 pass
7446 09:54:21.598946 alsa_mixer-test_write_invalid_0_70 pass
7447 09:54:21.602698 alsa_mixer-test_event_missing_0_70 pass
7448 09:54:21.605817 alsa_mixer-test_event_spurious_0_70 pass
7449 09:54:21.609174 alsa_mixer-test_get_value_0_69 pass
7450 09:54:21.612372 alsa_mixer-test_name_0_69 fail
7451 09:54:21.615764 alsa_mixer-test_write_default_0_69 pass
7452 09:54:21.618922 alsa_mixer-test_write_valid_0_69 pass
7453 09:54:21.622319 alsa_mixer-test_write_invalid_0_69 pass
7454 09:54:21.628758 alsa_mixer-test_event_missing_0_69 pass
7455 09:54:21.632224 alsa_mixer-test_event_spurious_0_69 pass
7456 09:54:21.635418 alsa_mixer-test_get_value_0_68 pass
7457 09:54:21.638928 alsa_mixer-test_name_0_68 fail
7458 09:54:21.641958 alsa_mixer-test_write_default_0_68 pass
7459 09:54:21.645502 alsa_mixer-test_write_valid_0_68 pass
7460 09:54:21.648657 alsa_mixer-test_write_invalid_0_68 pass
7461 09:54:21.652056 alsa_mixer-test_event_missing_0_68 pass
7462 09:54:21.655537 alsa_mixer-test_event_spurious_0_68 pass
7463 09:54:21.658724 alsa_mixer-test_get_value_0_67 pass
7464 09:54:21.662035 alsa_mixer-test_name_0_67 fail
7465 09:54:21.665824 alsa_mixer-test_write_default_0_67 pass
7466 09:54:21.669148 alsa_mixer-test_write_valid_0_67 pass
7467 09:54:21.672344 alsa_mixer-test_write_invalid_0_67 pass
7468 09:54:21.675425 alsa_mixer-test_event_missing_0_67 pass
7469 09:54:21.679130 alsa_mixer-test_event_spurious_0_67 pass
7470 09:54:21.682580 alsa_mixer-test_get_value_0_66 pass
7471 09:54:21.685619 alsa_mixer-test_name_0_66 fail
7472 09:54:21.689194 alsa_mixer-test_write_default_0_66 pass
7473 09:54:21.692411 alsa_mixer-test_write_valid_0_66 pass
7474 09:54:21.695796 alsa_mixer-test_write_invalid_0_66 pass
7475 09:54:21.702360 alsa_mixer-test_event_missing_0_66 pass
7476 09:54:21.705840 alsa_mixer-test_event_spurious_0_66 pass
7477 09:54:21.709102 alsa_mixer-test_get_value_0_65 pass
7478 09:54:21.712383 alsa_mixer-test_name_0_65 fail
7479 09:54:21.715758 alsa_mixer-test_write_default_0_65 pass
7480 09:54:21.718717 alsa_mixer-test_write_valid_0_65 pass
7481 09:54:21.722475 alsa_mixer-test_write_invalid_0_65 pass
7482 09:54:21.725473 alsa_mixer-test_event_missing_0_65 pass
7483 09:54:21.728856 alsa_mixer-test_event_spurious_0_65 pass
7484 09:54:21.732593 alsa_mixer-test_get_value_0_64 pass
7485 09:54:21.735622 alsa_mixer-test_name_0_64 fail
7486 09:54:21.738803 alsa_mixer-test_write_default_0_64 pass
7487 09:54:21.741952 alsa_mixer-test_write_valid_0_64 pass
7488 09:54:21.745251 alsa_mixer-test_write_invalid_0_64 pass
7489 09:54:21.748724 alsa_mixer-test_event_missing_0_64 pass
7490 09:54:21.752138 alsa_mixer-test_event_spurious_0_64 pass
7491 09:54:21.755476 alsa_mixer-test_get_value_0_63 pass
7492 09:54:21.758738 alsa_mixer-test_name_0_63 fail
7493 09:54:21.762304 alsa_mixer-test_write_default_0_63 pass
7494 09:54:21.765790 alsa_mixer-test_write_valid_0_63 pass
7495 09:54:21.769009 alsa_mixer-test_write_invalid_0_63 pass
7496 09:54:21.772163 alsa_mixer-test_event_missing_0_63 pass
7497 09:54:21.778983 alsa_mixer-test_event_spurious_0_63 pass
7498 09:54:21.782341 alsa_mixer-test_get_value_0_62 pass
7499 09:54:21.782879 alsa_mixer-test_name_0_62 fail
7500 09:54:21.785714 alsa_mixer-test_write_default_0_62 pass
7501 09:54:21.789254 alsa_mixer-test_write_valid_0_62 pass
7502 09:54:21.795846 alsa_mixer-test_write_invalid_0_62 pass
7503 09:54:21.799149 alsa_mixer-test_event_missing_0_62 pass
7504 09:54:21.802739 alsa_mixer-test_event_spurious_0_62 pass
7505 09:54:21.805481 alsa_mixer-test_get_value_0_61 pass
7506 09:54:21.808834 alsa_mixer-test_name_0_61 fail
7507 09:54:21.812423 alsa_mixer-test_write_default_0_61 pass
7508 09:54:21.815675 alsa_mixer-test_write_valid_0_61 pass
7509 09:54:21.819178 alsa_mixer-test_write_invalid_0_61 pass
7510 09:54:21.822274 alsa_mixer-test_event_missing_0_61 pass
7511 09:54:21.825346 alsa_mixer-test_event_spurious_0_61 pass
7512 09:54:21.828813 alsa_mixer-test_get_value_0_60 pass
7513 09:54:21.832298 alsa_mixer-test_name_0_60 fail
7514 09:54:21.835855 alsa_mixer-test_write_default_0_60 pass
7515 09:54:21.838700 alsa_mixer-test_write_valid_0_60 pass
7516 09:54:21.842043 alsa_mixer-test_write_invalid_0_60 pass
7517 09:54:21.845383 alsa_mixer-test_event_missing_0_60 pass
7518 09:54:21.848633 alsa_mixer-test_event_spurious_0_60 pass
7519 09:54:21.852333 alsa_mixer-test_get_value_0_59 pass
7520 09:54:21.855263 alsa_mixer-test_name_0_59 fail
7521 09:54:21.858611 alsa_mixer-test_write_default_0_59 pass
7522 09:54:21.861760 alsa_mixer-test_write_valid_0_59 pass
7523 09:54:21.865583 alsa_mixer-test_write_invalid_0_59 pass
7524 09:54:21.872303 alsa_mixer-test_event_missing_0_59 pass
7525 09:54:21.875354 alsa_mixer-test_event_spurious_0_59 pass
7526 09:54:21.878718 alsa_mixer-test_get_value_0_58 pass
7527 09:54:21.879230 alsa_mixer-test_name_0_58 fail
7528 09:54:21.882123 alsa_mixer-test_write_default_0_58 pass
7529 09:54:21.888739 alsa_mixer-test_write_valid_0_58 pass
7530 09:54:21.892063 alsa_mixer-test_write_invalid_0_58 pass
7531 09:54:21.895339 alsa_mixer-test_event_missing_0_58 pass
7532 09:54:21.898876 alsa_mixer-test_event_spurious_0_58 pass
7533 09:54:21.902163 alsa_mixer-test_get_value_0_57 pass
7534 09:54:21.905251 alsa_mixer-test_name_0_57 fail
7535 09:54:21.908951 alsa_mixer-test_write_default_0_57 pass
7536 09:54:21.911938 alsa_mixer-test_write_valid_0_57 pass
7537 09:54:21.915197 alsa_mixer-test_write_invalid_0_57 pass
7538 09:54:21.918907 alsa_mixer-test_event_missing_0_57 pass
7539 09:54:21.922119 alsa_mixer-test_event_spurious_0_57 pass
7540 09:54:21.925088 alsa_mixer-test_get_value_0_56 pass
7541 09:54:21.928652 alsa_mixer-test_name_0_56 fail
7542 09:54:21.932091 alsa_mixer-test_write_default_0_56 pass
7543 09:54:21.935123 alsa_mixer-test_write_valid_0_56 pass
7544 09:54:21.938316 alsa_mixer-test_write_invalid_0_56 pass
7545 09:54:21.941866 alsa_mixer-test_event_missing_0_56 pass
7546 09:54:21.944831 alsa_mixer-test_event_spurious_0_56 pass
7547 09:54:21.948199 alsa_mixer-test_get_value_0_55 pass
7548 09:54:21.951447 alsa_mixer-test_name_0_55 fail
7549 09:54:21.955183 alsa_mixer-test_write_default_0_55 pass
7550 09:54:21.958325 alsa_mixer-test_write_valid_0_55 pass
7551 09:54:21.961888 alsa_mixer-test_write_invalid_0_55 pass
7552 09:54:21.965845 alsa_mixer-test_event_missing_0_55 pass
7553 09:54:21.968264 alsa_mixer-test_event_spurious_0_55 pass
7554 09:54:21.971622 alsa_mixer-test_get_value_0_54 pass
7555 09:54:21.974660 alsa_mixer-test_name_0_54 fail
7556 09:54:21.978171 alsa_mixer-test_write_default_0_54 pass
7557 09:54:21.981401 alsa_mixer-test_write_valid_0_54 pass
7558 09:54:21.984668 alsa_mixer-test_write_invalid_0_54 pass
7559 09:54:21.987989 alsa_mixer-test_event_missing_0_54 pass
7560 09:54:21.991246 alsa_mixer-test_event_spurious_0_54 pass
7561 09:54:21.994412 alsa_mixer-test_get_value_0_53 pass
7562 09:54:21.997978 alsa_mixer-test_name_0_53 fail
7563 09:54:22.001058 alsa_mixer-test_write_default_0_53 pass
7564 09:54:22.005059 alsa_mixer-test_write_valid_0_53 pass
7565 09:54:22.008114 alsa_mixer-test_write_invalid_0_53 pass
7566 09:54:22.011512 alsa_mixer-test_event_missing_0_53 pass
7567 09:54:22.017733 alsa_mixer-test_event_spurious_0_53 pass
7568 09:54:22.018171 alsa_mixer-test_get_value_0_52 pass
7569 09:54:22.021111 alsa_mixer-test_name_0_52 fail
7570 09:54:22.024777 alsa_mixer-test_write_default_0_52 pass
7571 09:54:22.028091 alsa_mixer-test_write_valid_0_52 pass
7572 09:54:22.031596 alsa_mixer-test_write_invalid_0_52 pass
7573 09:54:22.037919 alsa_mixer-test_event_missing_0_52 pass
7574 09:54:22.041267 alsa_mixer-test_event_spurious_0_52 pass
7575 09:54:22.044474 alsa_mixer-test_get_value_0_51 pass
7576 09:54:22.045024 alsa_mixer-test_name_0_51 fail
7577 09:54:22.047654 alsa_mixer-test_write_default_0_51 pass
7578 09:54:22.051065 alsa_mixer-test_write_valid_0_51 pass
7579 09:54:22.057723 alsa_mixer-test_write_invalid_0_51 pass
7580 09:54:22.061015 alsa_mixer-test_event_missing_0_51 pass
7581 09:54:22.064597 alsa_mixer-test_event_spurious_0_51 pass
7582 09:54:22.067639 alsa_mixer-test_get_value_0_50 pass
7583 09:54:22.071264 alsa_mixer-test_name_0_50 fail
7584 09:54:22.074511 alsa_mixer-test_write_default_0_50 pass
7585 09:54:22.077760 alsa_mixer-test_write_valid_0_50 pass
7586 09:54:22.081219 alsa_mixer-test_write_invalid_0_50 pass
7587 09:54:22.084465 alsa_mixer-test_event_missing_0_50 pass
7588 09:54:22.087566 alsa_mixer-test_event_spurious_0_50 pass
7589 09:54:22.091236 alsa_mixer-test_get_value_0_49 pass
7590 09:54:22.094543 alsa_mixer-test_name_0_49 fail
7591 09:54:22.097929 alsa_mixer-test_write_default_0_49 pass
7592 09:54:22.101400 alsa_mixer-test_write_valid_0_49 pass
7593 09:54:22.104403 alsa_mixer-test_write_invalid_0_49 pass
7594 09:54:22.107658 alsa_mixer-test_event_missing_0_49 pass
7595 09:54:22.111242 alsa_mixer-test_event_spurious_0_49 pass
7596 09:54:22.114614 alsa_mixer-test_get_value_0_48 pass
7597 09:54:22.117540 alsa_mixer-test_name_0_48 fail
7598 09:54:22.120818 alsa_mixer-test_write_default_0_48 pass
7599 09:54:22.124063 alsa_mixer-test_write_valid_0_48 pass
7600 09:54:22.127647 alsa_mixer-test_write_invalid_0_48 pass
7601 09:54:22.130596 alsa_mixer-test_event_missing_0_48 pass
7602 09:54:22.134075 alsa_mixer-test_event_spurious_0_48 pass
7603 09:54:22.138046 alsa_mixer-test_get_value_0_47 pass
7604 09:54:22.140725 alsa_mixer-test_name_0_47 fail
7605 09:54:22.143983 alsa_mixer-test_write_default_0_47 pass
7606 09:54:22.147388 alsa_mixer-test_write_valid_0_47 pass
7607 09:54:22.150853 alsa_mixer-test_write_invalid_0_47 pass
7608 09:54:22.154066 alsa_mixer-test_event_missing_0_47 pass
7609 09:54:22.157274 alsa_mixer-test_event_spurious_0_47 pass
7610 09:54:22.161273 alsa_mixer-test_get_value_0_46 pass
7611 09:54:22.164297 alsa_mixer-test_name_0_46 fail
7612 09:54:22.167566 alsa_mixer-test_write_default_0_46 pass
7613 09:54:22.170434 alsa_mixer-test_write_valid_0_46 pass
7614 09:54:22.174279 alsa_mixer-test_write_invalid_0_46 pass
7615 09:54:22.177125 alsa_mixer-test_event_missing_0_46 pass
7616 09:54:22.180865 alsa_mixer-test_event_spurious_0_46 pass
7617 09:54:22.184041 alsa_mixer-test_get_value_0_45 pass
7618 09:54:22.187460 alsa_mixer-test_name_0_45 fail
7619 09:54:22.190821 alsa_mixer-test_write_default_0_45 pass
7620 09:54:22.193861 alsa_mixer-test_write_valid_0_45 pass
7621 09:54:22.197381 alsa_mixer-test_write_invalid_0_45 pass
7622 09:54:22.200475 alsa_mixer-test_event_missing_0_45 pass
7623 09:54:22.207071 alsa_mixer-test_event_spurious_0_45 pass
7624 09:54:22.210457 alsa_mixer-test_get_value_0_44 pass
7625 09:54:22.210890 alsa_mixer-test_name_0_44 fail
7626 09:54:22.213719 alsa_mixer-test_write_default_0_44 pass
7627 09:54:22.217035 alsa_mixer-test_write_valid_0_44 pass
7628 09:54:22.223882 alsa_mixer-test_write_invalid_0_44 pass
7629 09:54:22.226932 alsa_mixer-test_event_missing_0_44 pass
7630 09:54:22.230294 alsa_mixer-test_event_spurious_0_44 pass
7631 09:54:22.233678 alsa_mixer-test_get_value_0_43 pass
7632 09:54:22.236634 alsa_mixer-test_name_0_43 fail
7633 09:54:22.240162 alsa_mixer-test_write_default_0_43 pass
7634 09:54:22.243213 alsa_mixer-test_write_valid_0_43 pass
7635 09:54:22.246659 alsa_mixer-test_write_invalid_0_43 pass
7636 09:54:22.250004 alsa_mixer-test_event_missing_0_43 pass
7637 09:54:22.253276 alsa_mixer-test_event_spurious_0_43 pass
7638 09:54:22.256893 alsa_mixer-test_get_value_0_42 pass
7639 09:54:22.259979 alsa_mixer-test_name_0_42 fail
7640 09:54:22.263088 alsa_mixer-test_write_default_0_42 pass
7641 09:54:22.266434 alsa_mixer-test_write_valid_0_42 pass
7642 09:54:22.269808 alsa_mixer-test_write_invalid_0_42 pass
7643 09:54:22.273188 alsa_mixer-test_event_missing_0_42 pass
7644 09:54:22.276591 alsa_mixer-test_event_spurious_0_42 pass
7645 09:54:22.279826 alsa_mixer-test_get_value_0_41 pass
7646 09:54:22.283273 alsa_mixer-test_name_0_41 fail
7647 09:54:22.286534 alsa_mixer-test_write_default_0_41 pass
7648 09:54:22.289896 alsa_mixer-test_write_valid_0_41 pass
7649 09:54:22.293124 alsa_mixer-test_write_invalid_0_41 pass
7650 09:54:22.296582 alsa_mixer-test_event_missing_0_41 pass
7651 09:54:22.299906 alsa_mixer-test_event_spurious_0_41 pass
7652 09:54:22.304053 alsa_mixer-test_get_value_0_40 pass
7653 09:54:22.306729 alsa_mixer-test_name_0_40 fail
7654 09:54:22.309937 alsa_mixer-test_write_default_0_40 pass
7655 09:54:22.313259 alsa_mixer-test_write_valid_0_40 pass
7656 09:54:22.316373 alsa_mixer-test_write_invalid_0_40 pass
7657 09:54:22.319871 alsa_mixer-test_event_missing_0_40 pass
7658 09:54:22.323465 alsa_mixer-test_event_spurious_0_40 pass
7659 09:54:22.326734 alsa_mixer-test_get_value_0_39 pass
7660 09:54:22.329924 alsa_mixer-test_name_0_39 fail
7661 09:54:22.333155 alsa_mixer-test_write_default_0_39 pass
7662 09:54:22.336246 alsa_mixer-test_write_valid_0_39 pass
7663 09:54:22.339934 alsa_mixer-test_write_invalid_0_39 pass
7664 09:54:22.342969 alsa_mixer-test_event_missing_0_39 pass
7665 09:54:22.346913 alsa_mixer-test_event_spurious_0_39 pass
7666 09:54:22.349655 alsa_mixer-test_get_value_0_38 pass
7667 09:54:22.352913 alsa_mixer-test_name_0_38 fail
7668 09:54:22.356322 alsa_mixer-test_write_default_0_38 pass
7669 09:54:22.359672 alsa_mixer-test_write_valid_0_38 pass
7670 09:54:22.362976 alsa_mixer-test_write_invalid_0_38 pass
7671 09:54:22.366155 alsa_mixer-test_event_missing_0_38 pass
7672 09:54:22.372646 alsa_mixer-test_event_spurious_0_38 pass
7673 09:54:22.375962 alsa_mixer-test_get_value_0_37 pass
7674 09:54:22.376265 alsa_mixer-test_name_0_37 fail
7675 09:54:22.379719 alsa_mixer-test_write_default_0_37 pass
7676 09:54:22.382724 alsa_mixer-test_write_valid_0_37 pass
7677 09:54:22.389455 alsa_mixer-test_write_invalid_0_37 pass
7678 09:54:22.393182 alsa_mixer-test_event_missing_0_37 pass
7679 09:54:22.396371 alsa_mixer-test_event_spurious_0_37 pass
7680 09:54:22.399666 alsa_mixer-test_get_value_0_36 pass
7681 09:54:22.402878 alsa_mixer-test_name_0_36 fail
7682 09:54:22.406506 alsa_mixer-test_write_default_0_36 pass
7683 09:54:22.409618 alsa_mixer-test_write_valid_0_36 pass
7684 09:54:22.412910 alsa_mixer-test_write_invalid_0_36 pass
7685 09:54:22.416382 alsa_mixer-test_event_missing_0_36 pass
7686 09:54:22.419500 alsa_mixer-test_event_spurious_0_36 pass
7687 09:54:22.422663 alsa_mixer-test_get_value_0_35 pass
7688 09:54:22.425966 alsa_mixer-test_name_0_35 fail
7689 09:54:22.429724 alsa_mixer-test_write_default_0_35 pass
7690 09:54:22.432808 alsa_mixer-test_write_valid_0_35 pass
7691 09:54:22.436560 alsa_mixer-test_write_invalid_0_35 pass
7692 09:54:22.439672 alsa_mixer-test_event_missing_0_35 pass
7693 09:54:22.442664 alsa_mixer-test_event_spurious_0_35 pass
7694 09:54:22.445862 alsa_mixer-test_get_value_0_34 pass
7695 09:54:22.449312 alsa_mixer-test_name_0_34 fail
7696 09:54:22.452657 alsa_mixer-test_write_default_0_34 pass
7697 09:54:22.456002 alsa_mixer-test_write_valid_0_34 pass
7698 09:54:22.459611 alsa_mixer-test_write_invalid_0_34 pass
7699 09:54:22.462663 alsa_mixer-test_event_missing_0_34 pass
7700 09:54:22.469613 alsa_mixer-test_event_spurious_0_34 pass
7701 09:54:22.472584 alsa_mixer-test_get_value_0_33 pass
7702 09:54:22.473117 alsa_mixer-test_name_0_33 fail
7703 09:54:22.475956 alsa_mixer-test_write_default_0_33 pass
7704 09:54:22.479437 alsa_mixer-test_write_valid_0_33 pass
7705 09:54:22.485703 alsa_mixer-test_write_invalid_0_33 pass
7706 09:54:22.489125 alsa_mixer-test_event_missing_0_33 pass
7707 09:54:22.492582 alsa_mixer-test_event_spurious_0_33 pass
7708 09:54:22.495687 alsa_mixer-test_get_value_0_32 pass
7709 09:54:22.499161 alsa_mixer-test_name_0_32 fail
7710 09:54:22.502812 alsa_mixer-test_write_default_0_32 pass
7711 09:54:22.505876 alsa_mixer-test_write_valid_0_32 pass
7712 09:54:22.509538 alsa_mixer-test_write_invalid_0_32 pass
7713 09:54:22.512658 alsa_mixer-test_event_missing_0_32 pass
7714 09:54:22.515932 alsa_mixer-test_event_spurious_0_32 pass
7715 09:54:22.519150 alsa_mixer-test_get_value_0_31 pass
7716 09:54:22.522415 alsa_mixer-test_name_0_31 fail
7717 09:54:22.525612 alsa_mixer-test_write_default_0_31 pass
7718 09:54:22.528920 alsa_mixer-test_write_valid_0_31 pass
7719 09:54:22.532480 alsa_mixer-test_write_invalid_0_31 pass
7720 09:54:22.536103 alsa_mixer-test_event_missing_0_31 pass
7721 09:54:22.539140 alsa_mixer-test_event_spurious_0_31 pass
7722 09:54:22.542302 alsa_mixer-test_get_value_0_30 pass
7723 09:54:22.545478 alsa_mixer-test_name_0_30 fail
7724 09:54:22.548885 alsa_mixer-test_write_default_0_30 pass
7725 09:54:22.552188 alsa_mixer-test_write_valid_0_30 pass
7726 09:54:22.555904 alsa_mixer-test_write_invalid_0_30 pass
7727 09:54:22.559186 alsa_mixer-test_event_missing_0_30 pass
7728 09:54:22.562429 alsa_mixer-test_event_spurious_0_30 pass
7729 09:54:22.565801 alsa_mixer-test_get_value_0_29 pass
7730 09:54:22.569093 alsa_mixer-test_name_0_29 pass
7731 09:54:22.572421 alsa_mixer-test_write_default_0_29 pass
7732 09:54:22.575418 alsa_mixer-test_write_valid_0_29 pass
7733 09:54:22.579065 alsa_mixer-test_write_invalid_0_29 pass
7734 09:54:22.582584 alsa_mixer-test_event_missing_0_29 pass
7735 09:54:22.585807 alsa_mixer-test_event_spurious_0_29 pass
7736 09:54:22.589151 alsa_mixer-test_get_value_0_28 pass
7737 09:54:22.592531 alsa_mixer-test_name_0_28 pass
7738 09:54:22.595471 alsa_mixer-test_write_default_0_28 pass
7739 09:54:22.599057 alsa_mixer-test_write_valid_0_28 pass
7740 09:54:22.605938 alsa_mixer-test_write_invalid_0_28 pass
7741 09:54:22.609003 alsa_mixer-test_event_missing_0_28 pass
7742 09:54:22.611866 alsa_mixer-test_event_spurious_0_28 pass
7743 09:54:22.615446 alsa_mixer-test_get_value_0_27 pass
7744 09:54:22.618894 alsa_mixer-test_name_0_27 pass
7745 09:54:22.621930 alsa_mixer-test_write_default_0_27 pass
7746 09:54:22.625334 alsa_mixer-test_write_valid_0_27 pass
7747 09:54:22.628755 alsa_mixer-test_write_invalid_0_27 pass
7748 09:54:22.632396 alsa_mixer-test_event_missing_0_27 pass
7749 09:54:22.635257 alsa_mixer-test_event_spurious_0_27 pass
7750 09:54:22.638610 alsa_mixer-test_get_value_0_26 pass
7751 09:54:22.642183 alsa_mixer-test_name_0_26 pass
7752 09:54:22.645564 alsa_mixer-test_write_default_0_26 pass
7753 09:54:22.648595 alsa_mixer-test_write_valid_0_26 pass
7754 09:54:22.651823 alsa_mixer-test_write_invalid_0_26 pass
7755 09:54:22.655078 alsa_mixer-test_event_missing_0_26 pass
7756 09:54:22.661867 alsa_mixer-test_event_spurious_0_26 pass
7757 09:54:22.665148 alsa_mixer-test_get_value_0_25 pass
7758 09:54:22.665658 alsa_mixer-test_name_0_25 pass
7759 09:54:22.671725 alsa_mixer-test_write_default_0_25 pass
7760 09:54:22.675428 alsa_mixer-test_write_valid_0_25 pass
7761 09:54:22.678388 alsa_mixer-test_write_invalid_0_25 pass
7762 09:54:22.682093 alsa_mixer-test_event_missing_0_25 pass
7763 09:54:22.685217 alsa_mixer-test_event_spurious_0_25 pass
7764 09:54:22.688529 alsa_mixer-test_get_value_0_24 pass
7765 09:54:22.691905 alsa_mixer-test_name_0_24 pass
7766 09:54:22.695484 alsa_mixer-test_write_default_0_24 pass
7767 09:54:22.698674 alsa_mixer-test_write_valid_0_24 pass
7768 09:54:22.702167 alsa_mixer-test_write_invalid_0_24 pass
7769 09:54:22.705170 alsa_mixer-test_event_missing_0_24 pass
7770 09:54:22.708674 alsa_mixer-test_event_spurious_0_24 pass
7771 09:54:22.711864 alsa_mixer-test_get_value_0_23 pass
7772 09:54:22.715137 alsa_mixer-test_name_0_23 pass
7773 09:54:22.718631 alsa_mixer-test_write_default_0_23 pass
7774 09:54:22.721742 alsa_mixer-test_write_valid_0_23 pass
7775 09:54:22.725043 alsa_mixer-test_write_invalid_0_23 pass
7776 09:54:22.728559 alsa_mixer-test_event_missing_0_23 pass
7777 09:54:22.731514 alsa_mixer-test_event_spurious_0_23 pass
7778 09:54:22.735083 alsa_mixer-test_get_value_0_22 pass
7779 09:54:22.738610 alsa_mixer-test_name_0_22 pass
7780 09:54:22.741758 alsa_mixer-test_write_default_0_22 pass
7781 09:54:22.744910 alsa_mixer-test_write_valid_0_22 pass
7782 09:54:22.748453 alsa_mixer-test_write_invalid_0_22 pass
7783 09:54:22.751672 alsa_mixer-test_event_missing_0_22 pass
7784 09:54:22.754899 alsa_mixer-test_event_spurious_0_22 pass
7785 09:54:22.758485 alsa_mixer-test_get_value_0_21 pass
7786 09:54:22.761771 alsa_mixer-test_name_0_21 fail
7787 09:54:22.765128 alsa_mixer-test_write_default_0_21 pass
7788 09:54:22.768550 alsa_mixer-test_write_valid_0_21 pass
7789 09:54:22.771724 alsa_mixer-test_write_invalid_0_21 pass
7790 09:54:22.775216 alsa_mixer-test_event_missing_0_21 pass
7791 09:54:22.778521 alsa_mixer-test_event_spurious_0_21 pass
7792 09:54:22.781545 alsa_mixer-test_get_value_0_20 pass
7793 09:54:22.784970 alsa_mixer-test_name_0_20 fail
7794 09:54:22.788492 alsa_mixer-test_write_default_0_20 pass
7795 09:54:22.791672 alsa_mixer-test_write_valid_0_20 pass
7796 09:54:22.794938 alsa_mixer-test_write_invalid_0_20 pass
7797 09:54:22.798398 alsa_mixer-test_event_missing_0_20 pass
7798 09:54:22.804890 alsa_mixer-test_event_spurious_0_20 pass
7799 09:54:22.808075 alsa_mixer-test_get_value_0_19 pass
7800 09:54:22.808603 alsa_mixer-test_name_0_19 fail
7801 09:54:22.811452 alsa_mixer-test_write_default_0_19 pass
7802 09:54:22.814794 alsa_mixer-test_write_valid_0_19 pass
7803 09:54:22.817994 alsa_mixer-test_write_invalid_0_19 pass
7804 09:54:22.824858 alsa_mixer-test_event_missing_0_19 pass
7805 09:54:22.828132 alsa_mixer-test_event_spurious_0_19 pass
7806 09:54:22.831267 alsa_mixer-test_get_value_0_18 pass
7807 09:54:22.831716 alsa_mixer-test_name_0_18 fail
7808 09:54:22.838333 alsa_mixer-test_write_default_0_18 pass
7809 09:54:22.841221 alsa_mixer-test_write_valid_0_18 pass
7810 09:54:22.844640 alsa_mixer-test_write_invalid_0_18 pass
7811 09:54:22.847724 alsa_mixer-test_event_missing_0_18 pass
7812 09:54:22.851108 alsa_mixer-test_event_spurious_0_18 pass
7813 09:54:22.854383 alsa_mixer-test_get_value_0_17 pass
7814 09:54:22.857765 alsa_mixer-test_name_0_17 fail
7815 09:54:22.861503 alsa_mixer-test_write_default_0_17 pass
7816 09:54:22.864554 alsa_mixer-test_write_valid_0_17 pass
7817 09:54:22.867843 alsa_mixer-test_write_invalid_0_17 pass
7818 09:54:22.871180 alsa_mixer-test_event_missing_0_17 pass
7819 09:54:22.874653 alsa_mixer-test_event_spurious_0_17 pass
7820 09:54:22.877568 alsa_mixer-test_get_value_0_16 pass
7821 09:54:22.881121 alsa_mixer-test_name_0_16 fail
7822 09:54:22.884512 alsa_mixer-test_write_default_0_16 pass
7823 09:54:22.887709 alsa_mixer-test_write_valid_0_16 pass
7824 09:54:22.891287 alsa_mixer-test_write_invalid_0_16 pass
7825 09:54:22.894403 alsa_mixer-test_event_missing_0_16 pass
7826 09:54:22.897894 alsa_mixer-test_event_spurious_0_16 pass
7827 09:54:22.901095 alsa_mixer-test_get_value_0_15 pass
7828 09:54:22.904293 alsa_mixer-test_name_0_15 fail
7829 09:54:22.907587 alsa_mixer-test_write_default_0_15 pass
7830 09:54:22.911130 alsa_mixer-test_write_valid_0_15 pass
7831 09:54:22.914105 alsa_mixer-test_write_invalid_0_15 pass
7832 09:54:22.918009 alsa_mixer-test_event_missing_0_15 pass
7833 09:54:22.920803 alsa_mixer-test_event_spurious_0_15 pass
7834 09:54:22.924130 alsa_mixer-test_get_value_0_14 pass
7835 09:54:22.927655 alsa_mixer-test_name_0_14 fail
7836 09:54:22.930742 alsa_mixer-test_write_default_0_14 pass
7837 09:54:22.934138 alsa_mixer-test_write_valid_0_14 pass
7838 09:54:22.937517 alsa_mixer-test_write_invalid_0_14 pass
7839 09:54:22.940918 alsa_mixer-test_event_missing_0_14 pass
7840 09:54:22.944192 alsa_mixer-test_event_spurious_0_14 pass
7841 09:54:22.947150 alsa_mixer-test_get_value_0_13 pass
7842 09:54:22.950536 alsa_mixer-test_name_0_13 fail
7843 09:54:22.953862 alsa_mixer-test_write_default_0_13 pass
7844 09:54:22.957334 alsa_mixer-test_write_valid_0_13 pass
7845 09:54:22.960676 alsa_mixer-test_write_invalid_0_13 pass
7846 09:54:22.964210 alsa_mixer-test_event_missing_0_13 pass
7847 09:54:22.970452 alsa_mixer-test_event_spurious_0_13 pass
7848 09:54:22.974137 alsa_mixer-test_get_value_0_12 pass
7849 09:54:22.974697 alsa_mixer-test_name_0_12 fail
7850 09:54:22.977465 alsa_mixer-test_write_default_0_12 pass
7851 09:54:22.980973 alsa_mixer-test_write_valid_0_12 pass
7852 09:54:22.984256 alsa_mixer-test_write_invalid_0_12 pass
7853 09:54:22.990721 alsa_mixer-test_event_missing_0_12 pass
7854 09:54:22.994295 alsa_mixer-test_event_spurious_0_12 pass
7855 09:54:22.997507 alsa_mixer-test_get_value_0_11 pass
7856 09:54:22.998026 alsa_mixer-test_name_0_11 fail
7857 09:54:23.000916 alsa_mixer-test_write_default_0_11 pass
7858 09:54:23.003955 alsa_mixer-test_write_valid_0_11 pass
7859 09:54:23.010860 alsa_mixer-test_write_invalid_0_11 pass
7860 09:54:23.013999 alsa_mixer-test_event_missing_0_11 pass
7861 09:54:23.017221 alsa_mixer-test_event_spurious_0_11 pass
7862 09:54:23.020418 alsa_mixer-test_get_value_0_10 pass
7863 09:54:23.023893 alsa_mixer-test_name_0_10 fail
7864 09:54:23.027363 alsa_mixer-test_write_default_0_10 pass
7865 09:54:23.030304 alsa_mixer-test_write_valid_0_10 pass
7866 09:54:23.033739 alsa_mixer-test_write_invalid_0_10 pass
7867 09:54:23.037218 alsa_mixer-test_event_missing_0_10 pass
7868 09:54:23.040550 alsa_mixer-test_event_spurious_0_10 pass
7869 09:54:23.043878 alsa_mixer-test_get_value_0_9 pass
7870 09:54:23.047225 alsa_mixer-test_name_0_9 fail
7871 09:54:23.050060 alsa_mixer-test_write_default_0_9 pass
7872 09:54:23.053621 alsa_mixer-test_write_valid_0_9 pass
7873 09:54:23.056910 alsa_mixer-test_write_invalid_0_9 pass
7874 09:54:23.060076 alsa_mixer-test_event_missing_0_9 pass
7875 09:54:23.063504 alsa_mixer-test_event_spurious_0_9 pass
7876 09:54:23.067022 alsa_mixer-test_get_value_0_8 pass
7877 09:54:23.070147 alsa_mixer-test_name_0_8 fail
7878 09:54:23.073449 alsa_mixer-test_write_default_0_8 pass
7879 09:54:23.076830 alsa_mixer-test_write_valid_0_8 pass
7880 09:54:23.079877 alsa_mixer-test_write_invalid_0_8 pass
7881 09:54:23.083454 alsa_mixer-test_event_missing_0_8 pass
7882 09:54:23.086645 alsa_mixer-test_event_spurious_0_8 pass
7883 09:54:23.090005 alsa_mixer-test_get_value_0_7 pass
7884 09:54:23.093365 alsa_mixer-test_name_0_7 fail
7885 09:54:23.096628 alsa_mixer-test_write_default_0_7 pass
7886 09:54:23.099872 alsa_mixer-test_write_valid_0_7 pass
7887 09:54:23.103154 alsa_mixer-test_write_invalid_0_7 pass
7888 09:54:23.106742 alsa_mixer-test_event_missing_0_7 pass
7889 09:54:23.109960 alsa_mixer-test_event_spurious_0_7 pass
7890 09:54:23.113522 alsa_mixer-test_get_value_0_6 pass
7891 09:54:23.116711 alsa_mixer-test_name_0_6 fail
7892 09:54:23.119929 alsa_mixer-test_write_default_0_6 pass
7893 09:54:23.123223 alsa_mixer-test_write_valid_0_6 pass
7894 09:54:23.126570 alsa_mixer-test_write_invalid_0_6 pass
7895 09:54:23.129825 alsa_mixer-test_event_missing_0_6 pass
7896 09:54:23.133148 alsa_mixer-test_event_spurious_0_6 pass
7897 09:54:23.136518 alsa_mixer-test_get_value_0_5 pass
7898 09:54:23.139998 alsa_mixer-test_name_0_5 pass
7899 09:54:23.143259 alsa_mixer-test_write_default_0_5 pass
7900 09:54:23.146315 alsa_mixer-test_write_valid_0_5 pass
7901 09:54:23.149626 alsa_mixer-test_write_invalid_0_5 pass
7902 09:54:23.153253 alsa_mixer-test_event_missing_0_5 fail
7903 09:54:23.156415 alsa_mixer-test_event_spurious_0_5 pass
7904 09:54:23.159837 alsa_mixer-test_get_value_0_4 pass
7905 09:54:23.163214 alsa_mixer-test_name_0_4 pass
7906 09:54:23.166328 alsa_mixer-test_write_default_0_4 pass
7907 09:54:23.169835 alsa_mixer-test_write_valid_0_4 pass
7908 09:54:23.173126 alsa_mixer-test_write_invalid_0_4 pass
7909 09:54:23.176188 alsa_mixer-test_event_missing_0_4 fail
7910 09:54:23.179561 alsa_mixer-test_event_spurious_0_4 pass
7911 09:54:23.182866 alsa_mixer-test_get_value_0_3 pass
7912 09:54:23.186478 alsa_mixer-test_name_0_3 pass
7913 09:54:23.189492 alsa_mixer-test_write_default_0_3 pass
7914 09:54:23.192967 alsa_mixer-test_write_valid_0_3 pass
7915 09:54:23.196228 alsa_mixer-test_write_invalid_0_3 pass
7916 09:54:23.199708 alsa_mixer-test_event_missing_0_3 fail
7917 09:54:23.202843 alsa_mixer-test_event_spurious_0_3 pass
7918 09:54:23.206193 alsa_mixer-test_get_value_0_2 pass
7919 09:54:23.209290 alsa_mixer-test_name_0_2 pass
7920 09:54:23.212732 alsa_mixer-test_write_default_0_2 pass
7921 09:54:23.215889 alsa_mixer-test_write_valid_0_2 pass
7922 09:54:23.219229 alsa_mixer-test_write_invalid_0_2 pass
7923 09:54:23.222586 alsa_mixer-test_event_missing_0_2 fail
7924 09:54:23.225944 alsa_mixer-test_event_spurious_0_2 pass
7925 09:54:23.229362 alsa_mixer-test_get_value_0_1 pass
7926 09:54:23.232722 alsa_mixer-test_name_0_1 pass
7927 09:54:23.235956 alsa_mixer-test_write_default_0_1 pass
7928 09:54:23.239356 alsa_mixer-test_write_valid_0_1 pass
7929 09:54:23.242724 alsa_mixer-test_write_invalid_0_1 pass
7930 09:54:23.246109 alsa_mixer-test_event_missing_0_1 fail
7931 09:54:23.249054 alsa_mixer-test_event_spurious_0_1 pass
7932 09:54:23.252319 alsa_mixer-test_get_value_0_0 pass
7933 09:54:23.252690 alsa_mixer-test_name_0_0 pass
7934 09:54:23.256031 alsa_mixer-test_write_default_0_0 pass
7935 09:54:23.259330 alsa_mixer-test_write_valid_0_0 pass
7936 09:54:23.266041 alsa_mixer-test_write_invalid_0_0 pass
7937 09:54:23.269347 alsa_mixer-test_event_missing_0_0 fail
7938 09:54:23.272681 alsa_mixer-test_event_spurious_0_0 pass
7939 09:54:23.273150 alsa_mixer-test pass
7940 09:54:23.279067 + ../../utils/send-to-lava.sh ./output/result.txt
7941 09:54:23.282320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
7942 09:54:23.283028 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
7944 09:54:23.289053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass>
7945 09:54:23.289644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass
7947 09:54:23.295883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass>
7948 09:54:23.296640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass
7950 09:54:23.302613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass>
7951 09:54:23.303300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass
7953 09:54:23.345146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass>
7954 09:54:23.345454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass
7956 09:54:23.397843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass>
7957 09:54:23.398733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass
7959 09:54:23.447674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass>
7960 09:54:23.447942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass
7962 09:54:23.496830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass>
7963 09:54:23.497495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass
7965 09:54:23.555107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass>
7966 09:54:23.555922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass
7968 09:54:23.602421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass>
7969 09:54:23.603171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass
7971 09:54:23.671496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass>
7972 09:54:23.672191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass
7974 09:54:23.727627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass>
7975 09:54:23.727993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass
7977 09:54:23.776371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass>
7978 09:54:23.776643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass
7980 09:54:23.823832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass>
7981 09:54:23.824094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass
7983 09:54:23.868806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass>
7984 09:54:23.869108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass
7986 09:54:23.912045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass>
7987 09:54:23.912349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass
7989 09:54:23.949619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass>
7990 09:54:23.950268 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass
7992 09:54:23.999381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass>
7993 09:54:24.000067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass
7995 09:54:24.047842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass>
7996 09:54:24.048734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass
7998 09:54:24.114459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass>
7999 09:54:24.115237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass
8001 09:54:24.176260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass>
8002 09:54:24.176944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass
8004 09:54:24.227827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass>
8005 09:54:24.228205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass
8007 09:54:24.273162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass>
8008 09:54:24.273847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass
8010 09:54:24.332135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass
8012 09:54:24.335150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass>
8013 09:54:24.388990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass>
8014 09:54:24.389621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass
8016 09:54:24.448603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass>
8017 09:54:24.448861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass
8019 09:54:24.497696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass>
8020 09:54:24.498416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass
8022 09:54:24.545782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass>
8023 09:54:24.546085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass
8025 09:54:24.595688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass>
8026 09:54:24.596379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass
8028 09:54:24.645385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass>
8029 09:54:24.646010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass
8031 09:54:24.694680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass>
8032 09:54:24.695335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass
8034 09:54:24.749206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass>
8035 09:54:24.749857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass
8037 09:54:24.796724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass>
8038 09:54:24.797370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass
8040 09:54:24.842153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass>
8041 09:54:24.842864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass
8043 09:54:24.886979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass>
8044 09:54:24.887232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass
8046 09:54:24.925840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass>
8047 09:54:24.926591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass
8049 09:54:24.971104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass>
8050 09:54:24.971732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass
8052 09:54:25.010157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass>
8053 09:54:25.010828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass
8055 09:54:25.059361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass>
8056 09:54:25.060109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass
8058 09:54:25.103613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail>
8059 09:54:25.104292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail
8061 09:54:25.147692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass>
8062 09:54:25.148041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass
8064 09:54:25.196370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass>
8065 09:54:25.197047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass
8067 09:54:25.245953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail>
8068 09:54:25.246315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail
8070 09:54:25.289612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass>
8071 09:54:25.290328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass
8073 09:54:25.337960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass>
8074 09:54:25.338755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass
8076 09:54:25.390770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass>
8077 09:54:25.391406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass
8079 09:54:25.438168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass>
8080 09:54:25.438875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass
8082 09:54:25.485656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass>
8083 09:54:25.486323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass
8085 09:54:25.530884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass>
8086 09:54:25.531575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass
8088 09:54:25.580676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass>
8089 09:54:25.581316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass
8091 09:54:25.633595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass>
8092 09:54:25.634298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass
8094 09:54:25.680946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass>
8095 09:54:25.681200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass
8097 09:54:25.730862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass>
8098 09:54:25.731560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass
8100 09:54:25.779529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail>
8101 09:54:25.780229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail
8103 09:54:25.828903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass>
8104 09:54:25.829236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass
8106 09:54:25.873252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass>
8107 09:54:25.873934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass
8109 09:54:25.920897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass>
8110 09:54:25.921729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass
8112 09:54:25.966824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass>
8113 09:54:25.967527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass
8115 09:54:26.018488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass>
8116 09:54:26.019108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass
8118 09:54:26.077743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass>
8119 09:54:26.078380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass
8121 09:54:26.129695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail>
8122 09:54:26.130365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail
8124 09:54:26.174854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass>
8125 09:54:26.175561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass
8127 09:54:26.229316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass>
8128 09:54:26.230057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass
8130 09:54:26.272826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass>
8131 09:54:26.273119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass
8133 09:54:26.318829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass>
8134 09:54:26.319087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass
8136 09:54:26.363606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass>
8137 09:54:26.364127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass
8139 09:54:26.413196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass>
8140 09:54:26.413850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass
8142 09:54:26.466170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass>
8143 09:54:26.466440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass
8145 09:54:26.511308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass>
8146 09:54:26.511866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass
8148 09:54:26.553637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass>
8149 09:54:26.553979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass
8151 09:54:26.594700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass>
8152 09:54:26.595393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass
8154 09:54:26.639328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass>
8155 09:54:26.639574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass
8157 09:54:26.680613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass>
8158 09:54:26.681246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass
8160 09:54:26.728782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass>
8161 09:54:26.729066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass
8163 09:54:26.771135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass>
8164 09:54:26.771588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass
8166 09:54:26.814133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass>
8167 09:54:26.814418 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass
8169 09:54:26.856809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass>
8170 09:54:26.857559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass
8172 09:54:26.907614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass>
8173 09:54:26.907931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass
8175 09:54:26.951820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass
8177 09:54:26.954767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass>
8178 09:54:26.998336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass>
8179 09:54:26.999053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass
8181 09:54:27.042845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip>
8182 09:54:27.043177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip
8184 09:54:27.087980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip>
8185 09:54:27.088698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip
8187 09:54:27.137841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip>
8188 09:54:27.138683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip
8190 09:54:27.187236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass>
8191 09:54:27.187970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass
8193 09:54:27.233044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass>
8194 09:54:27.233895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass
8196 09:54:27.278568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass>
8197 09:54:27.279367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass
8199 09:54:27.323274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass>
8200 09:54:27.323960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass
8202 09:54:27.374039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass>
8203 09:54:27.374805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass
8205 09:54:27.422758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass>
8206 09:54:27.423420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass
8208 09:54:27.474681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail>
8209 09:54:27.475070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail
8211 09:54:27.521478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail>
8212 09:54:27.521809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail
8214 09:54:27.528958 <6>[ 37.711253] vaux18: disabling
8215 09:54:27.532915 <6>[ 37.715290] vio28: disabling
8216 09:54:27.568631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass>
8217 09:54:27.568996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass
8219 09:54:27.613996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass>
8220 09:54:27.614233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass
8222 09:54:27.655396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass>
8223 09:54:27.656020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass
8225 09:54:27.707393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass>
8226 09:54:27.708031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass
8228 09:54:27.750500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass>
8229 09:54:27.751191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass
8231 09:54:27.796152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass>
8232 09:54:27.796838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass
8234 09:54:27.848951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass>
8235 09:54:27.849627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass
8237 09:54:27.904030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass>
8238 09:54:27.904666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass
8240 09:54:27.956224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail>
8241 09:54:27.956960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail
8243 09:54:28.002552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass>
8244 09:54:28.003172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass
8246 09:54:28.061070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail>
8247 09:54:28.061707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail
8249 09:54:28.104164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail>
8250 09:54:28.104851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail
8252 09:54:28.163683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail>
8253 09:54:28.164308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail
8255 09:54:28.218080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass>
8256 09:54:28.218743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass
8258 09:54:28.269007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass>
8259 09:54:28.269263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass
8261 09:54:28.312215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail>
8262 09:54:28.312638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail
8264 09:54:28.356487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass>
8265 09:54:28.357112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass
8267 09:54:28.412740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail>
8268 09:54:28.412994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail
8270 09:54:28.464888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail>
8271 09:54:28.465318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail
8273 09:54:28.521757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail>
8274 09:54:28.522490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail
8276 09:54:28.569811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass>
8277 09:54:28.570061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass
8279 09:54:28.611989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass>
8280 09:54:28.612320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass
8282 09:54:28.657895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail>
8283 09:54:28.658195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail
8285 09:54:28.702941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass>
8286 09:54:28.703261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass
8288 09:54:28.747449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail>
8289 09:54:28.747705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail
8291 09:54:28.787690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail>
8292 09:54:28.787953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail
8294 09:54:28.829763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail>
8295 09:54:28.830536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail
8297 09:54:28.880263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass>
8298 09:54:28.881032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass
8300 09:54:28.930611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass>
8301 09:54:28.930872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass
8303 09:54:28.971486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass>
8304 09:54:28.971850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass
8306 09:54:29.016160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail>
8307 09:54:29.016416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail
8309 09:54:29.058161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass>
8310 09:54:29.058442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass
8312 09:54:29.104795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass>
8313 09:54:29.105537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass
8315 09:54:29.154355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass>
8316 09:54:29.154613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass
8318 09:54:29.196032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass>
8319 09:54:29.196634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass
8321 09:54:29.241647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass>
8322 09:54:29.241937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass
8324 09:54:29.285286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass>
8325 09:54:29.285550 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass
8327 09:54:29.330751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail>
8328 09:54:29.331238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail
8330 09:54:29.382579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass>
8331 09:54:29.382830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass
8333 09:54:29.429463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass>
8334 09:54:29.429728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass
8336 09:54:29.471505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass>
8337 09:54:29.471749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass
8339 09:54:29.512936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass>
8340 09:54:29.513592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass
8342 09:54:29.554685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass>
8343 09:54:29.554927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass
8345 09:54:29.597470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass>
8346 09:54:29.597761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass
8348 09:54:29.639631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail>
8349 09:54:29.640382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail
8351 09:54:29.683406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass>
8352 09:54:29.683656 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass
8354 09:54:29.725722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass>
8355 09:54:29.726404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass
8357 09:54:29.770549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass>
8358 09:54:29.770796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass
8360 09:54:29.809288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass>
8361 09:54:29.810189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass
8363 09:54:29.851740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass>
8364 09:54:29.851988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass
8366 09:54:29.894972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass>
8367 09:54:29.895220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass
8369 09:54:29.933228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail>
8370 09:54:29.933473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail
8372 09:54:29.980622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass>
8373 09:54:29.980885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass
8375 09:54:30.023402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass>
8376 09:54:30.024078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass
8378 09:54:30.072199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass>
8379 09:54:30.072986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass
8381 09:54:30.124394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass>
8382 09:54:30.124703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass
8384 09:54:30.165315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass>
8385 09:54:30.165695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass
8387 09:54:30.211951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass>
8388 09:54:30.212696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass
8390 09:54:30.253087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail>
8391 09:54:30.253330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail
8393 09:54:30.301308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass>
8394 09:54:30.301993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass
8396 09:54:30.352961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass>
8397 09:54:30.353632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass
8399 09:54:30.402943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass>
8400 09:54:30.403629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass
8402 09:54:30.452280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass>
8403 09:54:30.452664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass
8405 09:54:30.503506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass>
8406 09:54:30.503836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass
8408 09:54:30.548209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass>
8409 09:54:30.548894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass
8411 09:54:30.595382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail>
8412 09:54:30.596081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail
8414 09:54:30.644899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass>
8415 09:54:30.645216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass
8417 09:54:30.688599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass>
8418 09:54:30.688861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass
8420 09:54:30.730984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass>
8421 09:54:30.731299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass
8423 09:54:30.772590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass>
8424 09:54:30.772886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass
8426 09:54:30.810045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass>
8427 09:54:30.810336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass
8429 09:54:30.847518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass>
8430 09:54:30.848121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass
8432 09:54:30.893001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail>
8433 09:54:30.893696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail
8435 09:54:30.943321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass>
8436 09:54:30.944001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass
8438 09:54:30.995465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass>
8439 09:54:30.996126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass
8441 09:54:31.045760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass>
8442 09:54:31.046442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass
8444 09:54:31.092171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass>
8445 09:54:31.092910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass
8447 09:54:31.139356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass>
8448 09:54:31.140034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass
8450 09:54:31.187886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass>
8451 09:54:31.188536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass
8453 09:54:31.230551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail>
8454 09:54:31.231203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail
8456 09:54:31.276917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass>
8457 09:54:31.277592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass
8459 09:54:31.320285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass>
8460 09:54:31.320906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass
8462 09:54:31.368860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass>
8463 09:54:31.369555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass
8465 09:54:31.416976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass>
8466 09:54:31.417606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass
8468 09:54:31.465295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass>
8469 09:54:31.465913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass
8471 09:54:31.512041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass>
8472 09:54:31.512710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass
8474 09:54:31.555844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail>
8475 09:54:31.556569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail
8477 09:54:31.608607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass>
8478 09:54:31.609366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass
8480 09:54:31.657646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass>
8481 09:54:31.657946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass
8483 09:54:31.700469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass>
8484 09:54:31.700876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass
8486 09:54:31.751262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass>
8487 09:54:31.751931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass
8489 09:54:31.798122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass>
8490 09:54:31.798846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass
8492 09:54:31.847077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass>
8493 09:54:31.847749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass
8495 09:54:31.895285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail>
8496 09:54:31.895964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail
8498 09:54:31.941998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass>
8499 09:54:31.942343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass
8501 09:54:31.986280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass>
8502 09:54:31.986910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass
8504 09:54:32.029076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass>
8505 09:54:32.029326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass
8507 09:54:32.072094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass>
8508 09:54:32.072776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass
8510 09:54:32.119727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass>
8511 09:54:32.119985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass
8513 09:54:32.159866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass>
8514 09:54:32.160109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass
8516 09:54:32.200282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail>
8517 09:54:32.200912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail
8519 09:54:32.258658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass>
8520 09:54:32.258957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass
8522 09:54:32.298942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass>
8523 09:54:32.299250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass
8525 09:54:32.349712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass>
8526 09:54:32.350377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass
8528 09:54:32.397278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass>
8529 09:54:32.397963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass
8531 09:54:32.445824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass>
8532 09:54:32.446522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass
8534 09:54:32.489423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass>
8535 09:54:32.489713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass
8537 09:54:32.532408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail>
8538 09:54:32.532880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail
8540 09:54:32.579927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass>
8541 09:54:32.580546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass
8543 09:54:32.621407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass>
8544 09:54:32.621652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass
8546 09:54:32.659146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass>
8547 09:54:32.659392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass
8549 09:54:32.700240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass>
8550 09:54:32.700540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass
8552 09:54:32.742575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass>
8553 09:54:32.743217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass
8555 09:54:32.788450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass>
8556 09:54:32.788857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass
8558 09:54:32.826682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail>
8559 09:54:32.826940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail
8561 09:54:32.871194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass>
8562 09:54:32.871473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass
8564 09:54:32.911774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass>
8565 09:54:32.912020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass
8567 09:54:32.952968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass>
8568 09:54:32.953210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass
8570 09:54:32.992251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass>
8571 09:54:32.992521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass
8573 09:54:33.034693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass>
8574 09:54:33.034992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass
8576 09:54:33.073543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass>
8577 09:54:33.074256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass
8579 09:54:33.113599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail>
8580 09:54:33.114256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail
8582 09:54:33.160069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass>
8583 09:54:33.160869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass
8585 09:54:33.203446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass>
8586 09:54:33.203693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass
8588 09:54:33.243998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass>
8589 09:54:33.244241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass
8591 09:54:33.286787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass>
8592 09:54:33.287510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass
8594 09:54:33.335350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass>
8595 09:54:33.335967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass
8597 09:54:33.380515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass>
8598 09:54:33.381185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass
8600 09:54:33.428222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail>
8601 09:54:33.428849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail
8603 09:54:33.484419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass>
8604 09:54:33.485076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass
8606 09:54:33.528275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass>
8607 09:54:33.528903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass
8609 09:54:33.580112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass>
8610 09:54:33.580858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass
8612 09:54:33.627773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass>
8613 09:54:33.628024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass
8615 09:54:33.665039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass>
8616 09:54:33.665711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass
8618 09:54:33.706199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass>
8619 09:54:33.706928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass
8621 09:54:33.747235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail>
8622 09:54:33.747912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail
8624 09:54:33.795208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass>
8625 09:54:33.795516 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass
8627 09:54:33.837961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass>
8628 09:54:33.838598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass
8630 09:54:33.889760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass>
8631 09:54:33.890598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass
8633 09:54:33.940885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass>
8634 09:54:33.941143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass
8636 09:54:33.978981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass>
8637 09:54:33.979602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass
8639 09:54:34.019688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass>
8640 09:54:34.020357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass
8642 09:54:34.060240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail>
8643 09:54:34.060890 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail
8645 09:54:34.110821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass>
8646 09:54:34.111118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass
8648 09:54:34.155910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass>
8649 09:54:34.156268 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass
8651 09:54:34.206765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass>
8652 09:54:34.207078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass
8654 09:54:34.259672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass>
8655 09:54:34.260411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass
8657 09:54:34.309158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass>
8658 09:54:34.309833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass
8660 09:54:34.358270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass>
8661 09:54:34.358951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass
8663 09:54:34.404972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail>
8664 09:54:34.405266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail
8666 09:54:34.450154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass>
8667 09:54:34.450422 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass
8669 09:54:34.489496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass>
8670 09:54:34.489743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass
8672 09:54:34.530860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass>
8673 09:54:34.531159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass
8675 09:54:34.572331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass>
8676 09:54:34.572602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass
8678 09:54:34.613276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass>
8679 09:54:34.613965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass
8681 09:54:34.666932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass>
8682 09:54:34.667229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass
8684 09:54:34.709870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail>
8685 09:54:34.710557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail
8687 09:54:34.762083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass>
8688 09:54:34.762377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass
8690 09:54:34.810995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass>
8691 09:54:34.811251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass
8693 09:54:34.854359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass>
8694 09:54:34.854604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass
8696 09:54:34.901827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass>
8697 09:54:34.902135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass
8699 09:54:34.946773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass>
8700 09:54:34.947073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass
8702 09:54:34.995227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass>
8703 09:54:34.995959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass
8705 09:54:35.037491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail>
8706 09:54:35.038135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail
8708 09:54:35.086406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass>
8709 09:54:35.087076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass
8711 09:54:35.128748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass>
8712 09:54:35.129000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass
8714 09:54:35.173469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass>
8715 09:54:35.174287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass
8717 09:54:35.220469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass>
8718 09:54:35.220725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass
8720 09:54:35.266194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass>
8721 09:54:35.266542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass
8723 09:54:35.314367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass>
8724 09:54:35.314616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass
8726 09:54:35.359889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail>
8727 09:54:35.360213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail
8729 09:54:35.413206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass>
8730 09:54:35.413512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass
8732 09:54:35.456482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass>
8733 09:54:35.456730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass
8735 09:54:35.499448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass>
8736 09:54:35.499701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass
8738 09:54:35.542979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass>
8739 09:54:35.543282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass
8741 09:54:35.583906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass>
8742 09:54:35.584160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass
8744 09:54:35.629571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass>
8745 09:54:35.629875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass
8747 09:54:35.666437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail>
8748 09:54:35.666684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail
8750 09:54:35.712410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass>
8751 09:54:35.712831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass
8753 09:54:35.758168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass>
8754 09:54:35.758471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass
8756 09:54:35.803102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass>
8757 09:54:35.803371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass
8759 09:54:35.844285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass>
8760 09:54:35.844540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass
8762 09:54:35.891266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass>
8763 09:54:35.891515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass
8765 09:54:35.927907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass>
8766 09:54:35.928173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass
8768 09:54:35.968270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail>
8769 09:54:35.968964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail
8771 09:54:36.021391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass>
8772 09:54:36.022263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass
8774 09:54:36.073578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass>
8775 09:54:36.074260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass
8777 09:54:36.124769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass>
8778 09:54:36.125501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass
8780 09:54:36.179844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass>
8781 09:54:36.180552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass
8783 09:54:36.230944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass>
8784 09:54:36.231641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass
8786 09:54:36.279766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass>
8787 09:54:36.280478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass
8789 09:54:36.330114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail>
8790 09:54:36.330846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail
8792 09:54:36.388692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass>
8793 09:54:36.389368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass
8795 09:54:36.437744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass>
8796 09:54:36.438365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass
8798 09:54:36.493777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass>
8799 09:54:36.494558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass
8801 09:54:36.552307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass>
8802 09:54:36.553002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass
8804 09:54:36.604495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass>
8805 09:54:36.605250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass
8807 09:54:36.658424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass>
8808 09:54:36.659114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass
8810 09:54:36.696699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail>
8811 09:54:36.697386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail
8813 09:54:36.741609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass>
8814 09:54:36.741923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass
8816 09:54:36.781395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass>
8817 09:54:36.781820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass
8819 09:54:36.822199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass>
8820 09:54:36.822518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass
8822 09:54:36.866969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass>
8823 09:54:36.867519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass
8825 09:54:36.917140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass>
8826 09:54:36.917820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass
8828 09:54:36.972765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass>
8829 09:54:36.973518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass
8831 09:54:37.018171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail>
8832 09:54:37.018506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail
8834 09:54:37.068506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass>
8835 09:54:37.068853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass
8837 09:54:37.115245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass>
8838 09:54:37.115937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass
8840 09:54:37.166756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass>
8841 09:54:37.167399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass
8843 09:54:37.215402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass>
8844 09:54:37.215784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass
8846 09:54:37.262453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass>
8847 09:54:37.263078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass
8849 09:54:37.312504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass>
8850 09:54:37.312920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass
8852 09:54:37.356226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail>
8853 09:54:37.356940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail
8855 09:54:37.412055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass>
8856 09:54:37.412749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass
8858 09:54:37.462138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass>
8859 09:54:37.462845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass
8861 09:54:37.513064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass>
8862 09:54:37.513956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass
8864 09:54:37.564817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass>
8865 09:54:37.565066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass
8867 09:54:37.612069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass>
8868 09:54:37.612454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass
8870 09:54:37.668287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass>
8871 09:54:37.668822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass
8873 09:54:37.713637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail>
8874 09:54:37.714013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail
8876 09:54:37.762448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass>
8877 09:54:37.762697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass
8879 09:54:37.806482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass>
8880 09:54:37.806830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass
8882 09:54:37.855719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass>
8883 09:54:37.856338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass
8885 09:54:37.905981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass>
8886 09:54:37.906815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass
8888 09:54:37.952308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass>
8889 09:54:37.952619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass
8891 09:54:37.995093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass>
8892 09:54:37.995654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass
8894 09:54:38.036010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail>
8895 09:54:38.036332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail
8897 09:54:38.082327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass>
8898 09:54:38.082761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass
8900 09:54:38.127275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass>
8901 09:54:38.127958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass
8903 09:54:38.169400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass>
8904 09:54:38.169643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass
8906 09:54:38.212464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass>
8907 09:54:38.213145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass
8909 09:54:38.257518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass>
8910 09:54:38.257848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass
8912 09:54:38.301724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass>
8913 09:54:38.302243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass
8915 09:54:38.345149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail>
8916 09:54:38.345804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail
8918 09:54:38.395775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass>
8919 09:54:38.396024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass
8921 09:54:38.443530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass>
8922 09:54:38.443779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass
8924 09:54:38.482395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass>
8925 09:54:38.482663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass
8927 09:54:38.524841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass>
8928 09:54:38.525498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass
8930 09:54:38.569817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass>
8931 09:54:38.570159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass
8933 09:54:38.615411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass>
8934 09:54:38.615757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass
8936 09:54:38.657256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail>
8937 09:54:38.657968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail
8939 09:54:38.704565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass>
8940 09:54:38.704815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass
8942 09:54:38.744360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass>
8943 09:54:38.744608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass
8945 09:54:38.784087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass>
8946 09:54:38.784337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass
8948 09:54:38.827507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass>
8949 09:54:38.827924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass
8951 09:54:38.872969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass>
8952 09:54:38.873287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass
8954 09:54:38.921714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass>
8955 09:54:38.921969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass
8957 09:54:38.960347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail>
8958 09:54:38.960650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail
8960 09:54:39.008607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass>
8961 09:54:39.008861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass
8963 09:54:39.056284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass>
8964 09:54:39.056601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass
8966 09:54:39.097297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass>
8967 09:54:39.097612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass
8969 09:54:39.145118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass>
8970 09:54:39.145370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass
8972 09:54:39.187828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass>
8973 09:54:39.188074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass
8975 09:54:39.234729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass>
8976 09:54:39.234977 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass
8978 09:54:39.270695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail>
8979 09:54:39.270945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail
8981 09:54:39.313289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass>
8982 09:54:39.313970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass
8984 09:54:39.357548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass>
8985 09:54:39.357805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass
8987 09:54:39.403286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass>
8988 09:54:39.403588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass
8990 09:54:39.444154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass>
8991 09:54:39.444413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass
8993 09:54:39.484130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass>
8994 09:54:39.484375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass
8996 09:54:39.527687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass>
8997 09:54:39.527946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass
8999 09:54:39.571688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail>
9000 09:54:39.572006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail
9002 09:54:39.618639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass>
9003 09:54:39.618914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass
9005 09:54:39.659865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass>
9006 09:54:39.660112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass
9008 09:54:39.710699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass>
9009 09:54:39.711015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass
9011 09:54:39.760052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass>
9012 09:54:39.760744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass
9014 09:54:39.810278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass>
9015 09:54:39.810988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass
9017 09:54:39.855731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass>
9018 09:54:39.855981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass
9020 09:54:39.894054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail>
9021 09:54:39.894358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail
9023 09:54:39.939840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass>
9024 09:54:39.940493 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass
9026 09:54:39.981682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass>
9027 09:54:39.981943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass
9029 09:54:40.030381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass>
9030 09:54:40.030938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass
9032 09:54:40.074024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass>
9033 09:54:40.074336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass
9035 09:54:40.115993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass>
9036 09:54:40.116247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass
9038 09:54:40.158947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass>
9039 09:54:40.159633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass
9041 09:54:40.206178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail>
9042 09:54:40.206892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail
9044 09:54:40.257959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass>
9045 09:54:40.258669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass
9047 09:54:40.304985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass>
9048 09:54:40.305664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass
9050 09:54:40.355907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass>
9051 09:54:40.356582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass
9053 09:54:40.407677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass>
9054 09:54:40.408358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass
9056 09:54:40.466652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass>
9057 09:54:40.467379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass
9059 09:54:40.526197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass>
9060 09:54:40.526909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass
9062 09:54:40.572330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail>
9063 09:54:40.572671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail
9065 09:54:40.625257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass>
9066 09:54:40.625976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass
9068 09:54:40.675057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass>
9069 09:54:40.675321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass
9071 09:54:40.724555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass>
9072 09:54:40.725228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass
9074 09:54:40.783252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass>
9075 09:54:40.783946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass
9077 09:54:40.831239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass>
9078 09:54:40.831584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass
9080 09:54:40.878398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass>
9081 09:54:40.879077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass
9083 09:54:40.920360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail>
9084 09:54:40.920616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail
9086 09:54:40.967880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass>
9087 09:54:40.968322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass
9089 09:54:41.017989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass>
9090 09:54:41.018675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass
9092 09:54:41.064958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass>
9093 09:54:41.065214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass
9095 09:54:41.111663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass>
9096 09:54:41.112356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass
9098 09:54:41.160023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass>
9099 09:54:41.160950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass
9101 09:54:41.205217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass>
9102 09:54:41.205481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass
9104 09:54:41.244609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail>
9105 09:54:41.244861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail
9107 09:54:41.286313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass>
9108 09:54:41.286562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass
9110 09:54:41.323348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass>
9111 09:54:41.323601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass
9113 09:54:41.367064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass>
9114 09:54:41.367307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass
9116 09:54:41.405714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass>
9117 09:54:41.405973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass
9119 09:54:41.446080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass>
9120 09:54:41.446521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass
9122 09:54:41.497314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass>
9123 09:54:41.497676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass
9125 09:54:41.537574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail>
9126 09:54:41.538293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail
9128 09:54:41.587612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass>
9129 09:54:41.587860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass
9131 09:54:41.631251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass>
9132 09:54:41.631511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass
9134 09:54:41.676606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass>
9135 09:54:41.676849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass
9137 09:54:41.718352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass>
9138 09:54:41.718599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass
9140 09:54:41.757644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass>
9141 09:54:41.758321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass
9143 09:54:41.801396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass>
9144 09:54:41.801679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass
9146 09:54:41.843242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail>
9147 09:54:41.843920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail
9149 09:54:41.895157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass>
9150 09:54:41.895903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass
9152 09:54:41.941793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass>
9153 09:54:41.942143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass
9155 09:54:41.991439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass>
9156 09:54:41.991758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass
9158 09:54:42.041131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass>
9159 09:54:42.041809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass
9161 09:54:42.083162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass>
9162 09:54:42.083413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass
9164 09:54:42.127949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass>
9165 09:54:42.128381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass
9167 09:54:42.168747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail>
9168 09:54:42.168993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail
9170 09:54:42.211852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass>
9171 09:54:42.212182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass
9173 09:54:42.258670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass>
9174 09:54:42.259367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass
9176 09:54:42.305803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass>
9177 09:54:42.306471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass
9179 09:54:42.346706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass>
9180 09:54:42.346963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass
9182 09:54:42.388928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass>
9183 09:54:42.389178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass
9185 09:54:42.430315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass>
9186 09:54:42.430564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass
9188 09:54:42.475737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail>
9189 09:54:42.476718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail
9191 09:54:42.524632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass>
9192 09:54:42.524889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass
9194 09:54:42.559544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass>
9195 09:54:42.559788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass
9197 09:54:42.606363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass>
9198 09:54:42.606790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass
9200 09:54:42.648288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass>
9201 09:54:42.648549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass
9203 09:54:42.700902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass>
9204 09:54:42.701730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass
9206 09:54:42.754288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass>
9207 09:54:42.755083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass
9209 09:54:42.799732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail>
9210 09:54:42.800543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail
9212 09:54:42.858165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass>
9213 09:54:42.858459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass
9215 09:54:42.904803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass>
9216 09:54:42.905051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass
9218 09:54:42.948963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass>
9219 09:54:42.949259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass
9221 09:54:42.989435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass>
9222 09:54:42.989721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass
9224 09:54:43.029934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass>
9225 09:54:43.030201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass
9227 09:54:43.073486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass>
9228 09:54:43.073730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass
9230 09:54:43.109633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail>
9231 09:54:43.109879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail
9233 09:54:43.152824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass>
9234 09:54:43.153102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass
9236 09:54:43.194208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass>
9237 09:54:43.194494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass
9239 09:54:43.243440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass>
9240 09:54:43.243738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass
9242 09:54:43.286624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass>
9243 09:54:43.286900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass
9245 09:54:43.327978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass>
9246 09:54:43.328317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass
9248 09:54:43.378100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass>
9249 09:54:43.378403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass
9251 09:54:43.414343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail>
9252 09:54:43.415035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail
9254 09:54:43.463651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass>
9255 09:54:43.464394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass
9257 09:54:43.516409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass>
9258 09:54:43.517184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass
9260 09:54:43.567435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass>
9261 09:54:43.568218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass
9263 09:54:43.608128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass>
9264 09:54:43.609082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass
9266 09:54:43.661099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass>
9267 09:54:43.661865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass
9269 09:54:43.708913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass>
9270 09:54:43.709662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass
9272 09:54:43.753520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail>
9273 09:54:43.753828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail
9275 09:54:43.798959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass>
9276 09:54:43.799348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass
9278 09:54:43.847665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass>
9279 09:54:43.848409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass
9281 09:54:43.895348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass>
9282 09:54:43.895615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass
9284 09:54:43.934141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass>
9285 09:54:43.934449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass
9287 09:54:43.978144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass>
9288 09:54:43.978465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass
9290 09:54:44.023303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass>
9291 09:54:44.023605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass
9293 09:54:44.069565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass>
9294 09:54:44.070316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass
9296 09:54:44.127705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass>
9297 09:54:44.127963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass
9299 09:54:44.168251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass>
9300 09:54:44.168496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass
9302 09:54:44.210262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass>
9303 09:54:44.211012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass
9305 09:54:44.263966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass>
9306 09:54:44.264213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass
9308 09:54:44.303140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass>
9309 09:54:44.303410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass
9311 09:54:44.339668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass>
9312 09:54:44.339932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass
9314 09:54:44.380862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass>
9315 09:54:44.381113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass
9317 09:54:44.426630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass>
9318 09:54:44.427313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass
9320 09:54:44.480455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass>
9321 09:54:44.480713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass
9323 09:54:44.529180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass>
9324 09:54:44.529865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass
9326 09:54:44.581760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass>
9327 09:54:44.582439 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass
9329 09:54:44.625805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass>
9330 09:54:44.626121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass
9332 09:54:44.672510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass>
9333 09:54:44.673220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass
9335 09:54:44.720742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass>
9336 09:54:44.721486 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass
9338 09:54:44.774113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass>
9339 09:54:44.774876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass
9341 09:54:44.829363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass>
9342 09:54:44.829828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass
9344 09:54:44.878445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass>
9345 09:54:44.879277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass
9347 09:54:44.923613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass>
9348 09:54:44.924474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass
9350 09:54:44.965623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass>
9351 09:54:44.966407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass
9353 09:54:45.014085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass>
9354 09:54:45.014902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass
9356 09:54:45.059639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass>
9357 09:54:45.059935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass
9359 09:54:45.107755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass>
9360 09:54:45.108590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass
9362 09:54:45.155474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass>
9363 09:54:45.156209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass
9365 09:54:45.199437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass>
9366 09:54:45.200121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass
9368 09:54:45.247729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass>
9369 09:54:45.248409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass
9371 09:54:45.295253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass>
9372 09:54:45.295911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass
9374 09:54:45.339391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass>
9375 09:54:45.339677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass
9377 09:54:45.387945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass>
9378 09:54:45.388567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass
9380 09:54:45.448025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass>
9381 09:54:45.448655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass
9383 09:54:45.496523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass>
9384 09:54:45.496782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass
9386 09:54:45.540966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass>
9387 09:54:45.541226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass
9389 09:54:45.579577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass>
9390 09:54:45.580253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass
9392 09:54:45.622556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass>
9393 09:54:45.622801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass
9395 09:54:45.656345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass>
9396 09:54:45.656589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass
9398 09:54:45.692265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass>
9399 09:54:45.692540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass
9401 09:54:45.749335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass>
9402 09:54:45.749994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass
9404 09:54:45.799848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass>
9405 09:54:45.800604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass
9407 09:54:45.842564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass>
9408 09:54:45.843190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass
9410 09:54:45.885963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass>
9411 09:54:45.886745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass
9413 09:54:45.931470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass>
9414 09:54:45.932143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass
9416 09:54:45.975631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass>
9417 09:54:45.976257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass
9419 09:54:46.020555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass>
9420 09:54:46.021203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass
9422 09:54:46.074701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass>
9423 09:54:46.075374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass
9425 09:54:46.121941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass>
9426 09:54:46.122743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass
9428 09:54:46.175647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass>
9429 09:54:46.176306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass
9431 09:54:46.225058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass>
9432 09:54:46.225842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass
9434 09:54:46.279225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass>
9435 09:54:46.279491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass
9437 09:54:46.319209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass>
9438 09:54:46.319842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass
9440 09:54:46.371326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass>
9441 09:54:46.372083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass
9443 09:54:46.429230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass>
9444 09:54:46.429906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass
9446 09:54:46.480961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass>
9447 09:54:46.481586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass
9449 09:54:46.530977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass>
9450 09:54:46.531901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass
9452 09:54:46.581087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass>
9453 09:54:46.581336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass
9455 09:54:46.618585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass>
9456 09:54:46.619210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass
9458 09:54:46.670196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass>
9459 09:54:46.670908 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass
9461 09:54:46.716824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail>
9462 09:54:46.717154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail
9464 09:54:46.759584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass>
9465 09:54:46.760031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass
9467 09:54:46.804926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass>
9468 09:54:46.805765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass
9470 09:54:46.856369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass>
9471 09:54:46.856678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass
9473 09:54:46.913532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass>
9474 09:54:46.913920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass
9476 09:54:46.964419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass>
9477 09:54:46.965282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass
9479 09:54:47.021621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass>
9480 09:54:47.022473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass
9482 09:54:47.066290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail>
9483 09:54:47.066547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail
9485 09:54:47.111967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass>
9486 09:54:47.112299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass
9488 09:54:47.159226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass>
9489 09:54:47.159907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass
9491 09:54:47.213869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass>
9492 09:54:47.214710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass
9494 09:54:47.261197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass>
9495 09:54:47.261874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass
9497 09:54:47.313568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass>
9498 09:54:47.313879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass
9500 09:54:47.360896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass>
9501 09:54:47.361397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass
9503 09:54:47.406963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail>
9504 09:54:47.407735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail
9506 09:54:47.456882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass>
9507 09:54:47.457161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass
9509 09:54:47.495939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass>
9510 09:54:47.496757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass
9512 09:54:47.542516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass>
9513 09:54:47.542814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass
9515 09:54:47.584969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass>
9516 09:54:47.585234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass
9518 09:54:47.629845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass>
9519 09:54:47.630175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass
9521 09:54:47.676544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass>
9522 09:54:47.676812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass
9524 09:54:47.727382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail>
9525 09:54:47.728173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail
9527 09:54:47.783236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass>
9528 09:54:47.783935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass
9530 09:54:47.841412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass>
9531 09:54:47.841725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass
9533 09:54:47.883333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass>
9534 09:54:47.884046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass
9536 09:54:47.930083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass>
9537 09:54:47.930327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass
9539 09:54:47.970964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass>
9540 09:54:47.971210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass
9542 09:54:48.011265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass>
9543 09:54:48.011508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass
9545 09:54:48.050796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail>
9546 09:54:48.051045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail
9548 09:54:48.099616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass>
9549 09:54:48.099876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass
9551 09:54:48.147281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass>
9552 09:54:48.147525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass
9554 09:54:48.194912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass>
9555 09:54:48.195211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass
9557 09:54:48.237658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass>
9558 09:54:48.238349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass
9560 09:54:48.290756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass>
9561 09:54:48.291447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass
9563 09:54:48.337884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass>
9564 09:54:48.338178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass
9566 09:54:48.378647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail>
9567 09:54:48.379270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail
9569 09:54:48.430350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass>
9570 09:54:48.430609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass
9572 09:54:48.475780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass>
9573 09:54:48.476271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass
9575 09:54:48.524711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass>
9576 09:54:48.525003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass
9578 09:54:48.569962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass>
9579 09:54:48.570709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass
9581 09:54:48.616657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass>
9582 09:54:48.617296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass
9584 09:54:48.667741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass>
9585 09:54:48.668429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass
9587 09:54:48.718536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail>
9588 09:54:48.719271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail
9590 09:54:48.766559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass>
9591 09:54:48.766953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass
9593 09:54:48.813153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass>
9594 09:54:48.813818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass
9596 09:54:48.861398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass>
9597 09:54:48.862097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass
9599 09:54:48.907828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass>
9600 09:54:48.908121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass
9602 09:54:48.952048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass>
9603 09:54:48.952317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass
9605 09:54:48.996535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass>
9606 09:54:48.997278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass
9608 09:54:49.043142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail>
9609 09:54:49.043910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail
9611 09:54:49.093607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass>
9612 09:54:49.093853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass
9614 09:54:49.141269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass>
9615 09:54:49.141676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass
9617 09:54:49.185911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass>
9618 09:54:49.186206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass
9620 09:54:49.233659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass>
9621 09:54:49.233972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass
9623 09:54:49.277322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass>
9624 09:54:49.277775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass
9626 09:54:49.320256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass>
9627 09:54:49.320562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass
9629 09:54:49.364036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail>
9630 09:54:49.364316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail
9632 09:54:49.408117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass>
9633 09:54:49.408366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass
9635 09:54:49.452451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass>
9636 09:54:49.453214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass
9638 09:54:49.499178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass>
9639 09:54:49.499445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass
9641 09:54:49.539491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass>
9642 09:54:49.539743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass
9644 09:54:49.580208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass>
9645 09:54:49.580478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass
9647 09:54:49.626018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass>
9648 09:54:49.626316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass
9650 09:54:49.666058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail>
9651 09:54:49.666310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail
9653 09:54:49.715520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass>
9654 09:54:49.715766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass
9656 09:54:49.758459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass>
9657 09:54:49.758714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass
9659 09:54:49.800501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass>
9660 09:54:49.800752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass
9662 09:54:49.846887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass>
9663 09:54:49.847537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass
9665 09:54:49.893701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass>
9666 09:54:49.894377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass
9668 09:54:49.944911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass>
9669 09:54:49.945541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass
9671 09:54:49.990290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail>
9672 09:54:49.990536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail
9674 09:54:50.035055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass>
9675 09:54:50.035347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass
9677 09:54:50.080245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass>
9678 09:54:50.080508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass
9680 09:54:50.128610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass>
9681 09:54:50.129101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass
9683 09:54:50.173735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass>
9684 09:54:50.174007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass
9686 09:54:50.220404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass>
9687 09:54:50.220721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass
9689 09:54:50.266195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass>
9690 09:54:50.267014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass
9692 09:54:50.307706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail>
9693 09:54:50.308047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail
9695 09:54:50.357028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass>
9696 09:54:50.357358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass
9698 09:54:50.406586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass>
9699 09:54:50.407144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass
9701 09:54:50.451404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass>
9702 09:54:50.451652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass
9704 09:54:50.492888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass>
9705 09:54:50.493203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass
9707 09:54:50.539629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass>
9708 09:54:50.540377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass
9710 09:54:50.591103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass>
9711 09:54:50.591414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass
9713 09:54:50.632988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail>
9714 09:54:50.633243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail
9716 09:54:50.680062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass>
9717 09:54:50.680316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass
9719 09:54:50.723230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass>
9720 09:54:50.723532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass
9722 09:54:50.773409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass>
9723 09:54:50.773706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass
9725 09:54:50.819888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass>
9726 09:54:50.820137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass
9728 09:54:50.862163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass>
9729 09:54:50.862462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass
9731 09:54:50.901835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass>
9732 09:54:50.902087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass
9734 09:54:50.947718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail>
9735 09:54:50.948280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail
9737 09:54:50.998749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass>
9738 09:54:50.999013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass
9740 09:54:51.047495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass>
9741 09:54:51.048254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass
9743 09:54:51.097494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass>
9744 09:54:51.097774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass
9746 09:54:51.140330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass>
9747 09:54:51.140592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass
9749 09:54:51.183184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass>
9750 09:54:51.183461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass
9752 09:54:51.227125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass>
9753 09:54:51.227410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass
9755 09:54:51.264795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail>
9756 09:54:51.265052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail
9758 09:54:51.310506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass>
9759 09:54:51.310770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass
9761 09:54:51.356210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass>
9762 09:54:51.356468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass
9764 09:54:51.397329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass>
9765 09:54:51.397608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass
9767 09:54:51.443229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass>
9768 09:54:51.443502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass
9770 09:54:51.485522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass>
9771 09:54:51.486449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass
9773 09:54:51.535048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass>
9774 09:54:51.535784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass
9776 09:54:51.586156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail>
9777 09:54:51.586967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail
9779 09:54:51.639490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass>
9780 09:54:51.639757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass
9782 09:54:51.683815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass>
9783 09:54:51.684063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass
9785 09:54:51.724622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass>
9786 09:54:51.724869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass
9788 09:54:51.764625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass>
9789 09:54:51.764870 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass
9791 09:54:51.809261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass>
9792 09:54:51.809495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass
9794 09:54:51.855568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass>
9795 09:54:51.855813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass
9797 09:54:51.892883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass>
9798 09:54:51.893704 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass
9800 09:54:51.939346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass>
9801 09:54:51.939591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass
9803 09:54:51.980625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass>
9804 09:54:51.981412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass
9806 09:54:52.032022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass>
9807 09:54:52.032357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass
9809 09:54:52.078868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail>
9810 09:54:52.079138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail
9812 09:54:52.121721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass>
9813 09:54:52.121969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass
9815 09:54:52.160608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass>
9816 09:54:52.160881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass
9818 09:54:52.199835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass>
9819 09:54:52.200089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass
9821 09:54:52.243903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass>
9822 09:54:52.244349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass
9824 09:54:52.281083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass>
9825 09:54:52.281365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass
9827 09:54:52.322893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass>
9828 09:54:52.323203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass
9830 09:54:52.362903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail>
9831 09:54:52.363168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail
9833 09:54:52.406684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass>
9834 09:54:52.406959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass
9836 09:54:52.450149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass>
9837 09:54:52.450445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass
9839 09:54:52.492713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass>
9840 09:54:52.493740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass
9842 09:54:52.544691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass>
9843 09:54:52.545370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass
9845 09:54:52.595023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass>
9846 09:54:52.595337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass
9848 09:54:52.641627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass>
9849 09:54:52.642320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass
9851 09:54:52.687852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail>
9852 09:54:52.688116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail
9854 09:54:52.726651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass>
9855 09:54:52.727464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass
9857 09:54:52.765001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass>
9858 09:54:52.765250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass
9860 09:54:52.799322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass>
9861 09:54:52.799586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass
9863 09:54:52.841837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass>
9864 09:54:52.842709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass
9866 09:54:52.892973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass>
9867 09:54:52.893860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass
9869 09:54:52.940540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass>
9870 09:54:52.940788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass
9872 09:54:52.986199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail>
9873 09:54:52.987019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail
9875 09:54:53.032115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass>
9876 09:54:53.033000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass
9878 09:54:53.080881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass
9880 09:54:53.083732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass>
9881 09:54:53.129234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass>
9882 09:54:53.129487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass
9884 09:54:53.181668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass>
9885 09:54:53.182320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass
9887 09:54:53.233413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass>
9888 09:54:53.233772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass
9890 09:54:53.285822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass>
9891 09:54:53.286126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass
9893 09:54:53.329380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail>
9894 09:54:53.329705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail
9896 09:54:53.372307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass>
9897 09:54:53.373002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass
9899 09:54:53.421237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass>
9900 09:54:53.422023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass
9902 09:54:53.465860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass>
9903 09:54:53.466590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass
9905 09:54:53.516909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass>
9906 09:54:53.517680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass
9908 09:54:53.562573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass>
9909 09:54:53.563560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass
9911 09:54:53.607264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass>
9912 09:54:53.607517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass
9914 09:54:53.652612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail>
9915 09:54:53.653533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail
9917 09:54:53.702724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass>
9918 09:54:53.703510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass
9920 09:54:53.749153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
9921 09:54:53.749574 + set +x
9922 09:54:53.750132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
9924 09:54:53.755691 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14407592_1.6.2.3.5>
9925 09:54:53.756366 Received signal: <ENDRUN> 1_kselftest-alsa 14407592_1.6.2.3.5
9926 09:54:53.756743 Ending use of test pattern.
9927 09:54:53.757060 Ending test lava.1_kselftest-alsa (14407592_1.6.2.3.5), duration 43.23
9929 09:54:53.758799 <LAVA_TEST_RUNNER EXIT>
9930 09:54:53.759463 ok: lava_test_shell seems to have completed
9931 09:54:53.776663 alsa_mixer-test: pass
alsa_mixer-test_event_missing_0_0: fail
alsa_mixer-test_event_missing_0_1: fail
alsa_mixer-test_event_missing_0_10: pass
alsa_mixer-test_event_missing_0_11: pass
alsa_mixer-test_event_missing_0_12: pass
alsa_mixer-test_event_missing_0_13: pass
alsa_mixer-test_event_missing_0_14: pass
alsa_mixer-test_event_missing_0_15: pass
alsa_mixer-test_event_missing_0_16: pass
alsa_mixer-test_event_missing_0_17: pass
alsa_mixer-test_event_missing_0_18: pass
alsa_mixer-test_event_missing_0_19: pass
alsa_mixer-test_event_missing_0_2: fail
alsa_mixer-test_event_missing_0_20: pass
alsa_mixer-test_event_missing_0_21: pass
alsa_mixer-test_event_missing_0_22: pass
alsa_mixer-test_event_missing_0_23: pass
alsa_mixer-test_event_missing_0_24: pass
alsa_mixer-test_event_missing_0_25: pass
alsa_mixer-test_event_missing_0_26: pass
alsa_mixer-test_event_missing_0_27: pass
alsa_mixer-test_event_missing_0_28: pass
alsa_mixer-test_event_missing_0_29: pass
alsa_mixer-test_event_missing_0_3: fail
alsa_mixer-test_event_missing_0_30: pass
alsa_mixer-test_event_missing_0_31: pass
alsa_mixer-test_event_missing_0_32: pass
alsa_mixer-test_event_missing_0_33: pass
alsa_mixer-test_event_missing_0_34: pass
alsa_mixer-test_event_missing_0_35: pass
alsa_mixer-test_event_missing_0_36: pass
alsa_mixer-test_event_missing_0_37: pass
alsa_mixer-test_event_missing_0_38: pass
alsa_mixer-test_event_missing_0_39: pass
alsa_mixer-test_event_missing_0_4: fail
alsa_mixer-test_event_missing_0_40: pass
alsa_mixer-test_event_missing_0_41: pass
alsa_mixer-test_event_missing_0_42: pass
alsa_mixer-test_event_missing_0_43: pass
alsa_mixer-test_event_missing_0_44: pass
alsa_mixer-test_event_missing_0_45: pass
alsa_mixer-test_event_missing_0_46: pass
alsa_mixer-test_event_missing_0_47: pass
alsa_mixer-test_event_missing_0_48: pass
alsa_mixer-test_event_missing_0_49: pass
alsa_mixer-test_event_missing_0_5: fail
alsa_mixer-test_event_missing_0_50: pass
alsa_mixer-test_event_missing_0_51: pass
alsa_mixer-test_event_missing_0_52: pass
alsa_mixer-test_event_missing_0_53: pass
alsa_mixer-test_event_missing_0_54: pass
alsa_mixer-test_event_missing_0_55: pass
alsa_mixer-test_event_missing_0_56: pass
alsa_mixer-test_event_missing_0_57: pass
alsa_mixer-test_event_missing_0_58: pass
alsa_mixer-test_event_missing_0_59: pass
alsa_mixer-test_event_missing_0_6: pass
alsa_mixer-test_event_missing_0_60: pass
alsa_mixer-test_event_missing_0_61: pass
alsa_mixer-test_event_missing_0_62: pass
alsa_mixer-test_event_missing_0_63: pass
alsa_mixer-test_event_missing_0_64: pass
alsa_mixer-test_event_missing_0_65: pass
alsa_mixer-test_event_missing_0_66: pass
alsa_mixer-test_event_missing_0_67: pass
alsa_mixer-test_event_missing_0_68: pass
alsa_mixer-test_event_missing_0_69: pass
alsa_mixer-test_event_missing_0_7: pass
alsa_mixer-test_event_missing_0_70: pass
alsa_mixer-test_event_missing_0_71: pass
alsa_mixer-test_event_missing_0_72: pass
alsa_mixer-test_event_missing_0_73: pass
alsa_mixer-test_event_missing_0_74: pass
alsa_mixer-test_event_missing_0_75: pass
alsa_mixer-test_event_missing_0_76: pass
alsa_mixer-test_event_missing_0_77: pass
alsa_mixer-test_event_missing_0_78: pass
alsa_mixer-test_event_missing_0_79: pass
alsa_mixer-test_event_missing_0_8: pass
alsa_mixer-test_event_missing_0_80: pass
alsa_mixer-test_event_missing_0_81: fail
alsa_mixer-test_event_missing_0_82: pass
alsa_mixer-test_event_missing_0_83: pass
alsa_mixer-test_event_missing_0_84: pass
alsa_mixer-test_event_missing_0_85: pass
alsa_mixer-test_event_missing_0_86: pass
alsa_mixer-test_event_missing_0_87: pass
alsa_mixer-test_event_missing_0_88: pass
alsa_mixer-test_event_missing_0_89: pass
alsa_mixer-test_event_missing_0_9: pass
alsa_mixer-test_event_missing_0_90: pass
alsa_mixer-test_event_missing_0_91: pass
alsa_mixer-test_event_missing_0_92: pass
alsa_mixer-test_event_missing_0_93: pass
alsa_mixer-test_event_spurious_0_0: pass
alsa_mixer-test_event_spurious_0_1: pass
alsa_mixer-test_event_spurious_0_10: pass
alsa_mixer-test_event_spurious_0_11: pass
alsa_mixer-test_event_spurious_0_12: pass
alsa_mixer-test_event_spurious_0_13: pass
alsa_mixer-test_event_spurious_0_14: pass
alsa_mixer-test_event_spurious_0_15: pass
alsa_mixer-test_event_spurious_0_16: pass
alsa_mixer-test_event_spurious_0_17: pass
alsa_mixer-test_event_spurious_0_18: pass
alsa_mixer-test_event_spurious_0_19: pass
alsa_mixer-test_event_spurious_0_2: pass
alsa_mixer-test_event_spurious_0_20: pass
alsa_mixer-test_event_spurious_0_21: pass
alsa_mixer-test_event_spurious_0_22: pass
alsa_mixer-test_event_spurious_0_23: pass
alsa_mixer-test_event_spurious_0_24: pass
alsa_mixer-test_event_spurious_0_25: pass
alsa_mixer-test_event_spurious_0_26: pass
alsa_mixer-test_event_spurious_0_27: pass
alsa_mixer-test_event_spurious_0_28: pass
alsa_mixer-test_event_spurious_0_29: pass
alsa_mixer-test_event_spurious_0_3: pass
alsa_mixer-test_event_spurious_0_30: pass
alsa_mixer-test_event_spurious_0_31: pass
alsa_mixer-test_event_spurious_0_32: pass
alsa_mixer-test_event_spurious_0_33: pass
alsa_mixer-test_event_spurious_0_34: pass
alsa_mixer-test_event_spurious_0_35: pass
alsa_mixer-test_event_spurious_0_36: pass
alsa_mixer-test_event_spurious_0_37: pass
alsa_mixer-test_event_spurious_0_38: pass
alsa_mixer-test_event_spurious_0_39: pass
alsa_mixer-test_event_spurious_0_4: pass
alsa_mixer-test_event_spurious_0_40: pass
alsa_mixer-test_event_spurious_0_41: pass
alsa_mixer-test_event_spurious_0_42: pass
alsa_mixer-test_event_spurious_0_43: pass
alsa_mixer-test_event_spurious_0_44: pass
alsa_mixer-test_event_spurious_0_45: pass
alsa_mixer-test_event_spurious_0_46: pass
alsa_mixer-test_event_spurious_0_47: pass
alsa_mixer-test_event_spurious_0_48: pass
alsa_mixer-test_event_spurious_0_49: pass
alsa_mixer-test_event_spurious_0_5: pass
alsa_mixer-test_event_spurious_0_50: pass
alsa_mixer-test_event_spurious_0_51: pass
alsa_mixer-test_event_spurious_0_52: pass
alsa_mixer-test_event_spurious_0_53: pass
alsa_mixer-test_event_spurious_0_54: pass
alsa_mixer-test_event_spurious_0_55: pass
alsa_mixer-test_event_spurious_0_56: pass
alsa_mixer-test_event_spurious_0_57: pass
alsa_mixer-test_event_spurious_0_58: pass
alsa_mixer-test_event_spurious_0_59: pass
alsa_mixer-test_event_spurious_0_6: pass
alsa_mixer-test_event_spurious_0_60: pass
alsa_mixer-test_event_spurious_0_61: pass
alsa_mixer-test_event_spurious_0_62: pass
alsa_mixer-test_event_spurious_0_63: pass
alsa_mixer-test_event_spurious_0_64: pass
alsa_mixer-test_event_spurious_0_65: pass
alsa_mixer-test_event_spurious_0_66: pass
alsa_mixer-test_event_spurious_0_67: pass
alsa_mixer-test_event_spurious_0_68: pass
alsa_mixer-test_event_spurious_0_69: pass
alsa_mixer-test_event_spurious_0_7: pass
alsa_mixer-test_event_spurious_0_70: pass
alsa_mixer-test_event_spurious_0_71: pass
alsa_mixer-test_event_spurious_0_72: pass
alsa_mixer-test_event_spurious_0_73: pass
alsa_mixer-test_event_spurious_0_74: pass
alsa_mixer-test_event_spurious_0_75: pass
alsa_mixer-test_event_spurious_0_76: pass
alsa_mixer-test_event_spurious_0_77: pass
alsa_mixer-test_event_spurious_0_78: pass
alsa_mixer-test_event_spurious_0_79: pass
alsa_mixer-test_event_spurious_0_8: pass
alsa_mixer-test_event_spurious_0_80: pass
alsa_mixer-test_event_spurious_0_81: pass
alsa_mixer-test_event_spurious_0_82: pass
alsa_mixer-test_event_spurious_0_83: pass
alsa_mixer-test_event_spurious_0_84: pass
alsa_mixer-test_event_spurious_0_85: pass
alsa_mixer-test_event_spurious_0_86: pass
alsa_mixer-test_event_spurious_0_87: pass
alsa_mixer-test_event_spurious_0_88: fail
alsa_mixer-test_event_spurious_0_89: pass
alsa_mixer-test_event_spurious_0_9: pass
alsa_mixer-test_event_spurious_0_90: pass
alsa_mixer-test_event_spurious_0_91: pass
alsa_mixer-test_event_spurious_0_92: pass
alsa_mixer-test_event_spurious_0_93: pass
alsa_mixer-test_get_value_0_0: pass
alsa_mixer-test_get_value_0_1: pass
alsa_mixer-test_get_value_0_10: pass
alsa_mixer-test_get_value_0_11: pass
alsa_mixer-test_get_value_0_12: pass
alsa_mixer-test_get_value_0_13: pass
alsa_mixer-test_get_value_0_14: pass
alsa_mixer-test_get_value_0_15: pass
alsa_mixer-test_get_value_0_16: pass
alsa_mixer-test_get_value_0_17: pass
alsa_mixer-test_get_value_0_18: pass
alsa_mixer-test_get_value_0_19: pass
alsa_mixer-test_get_value_0_2: pass
alsa_mixer-test_get_value_0_20: pass
alsa_mixer-test_get_value_0_21: pass
alsa_mixer-test_get_value_0_22: pass
alsa_mixer-test_get_value_0_23: pass
alsa_mixer-test_get_value_0_24: pass
alsa_mixer-test_get_value_0_25: pass
alsa_mixer-test_get_value_0_26: pass
alsa_mixer-test_get_value_0_27: pass
alsa_mixer-test_get_value_0_28: pass
alsa_mixer-test_get_value_0_29: pass
alsa_mixer-test_get_value_0_3: pass
alsa_mixer-test_get_value_0_30: pass
alsa_mixer-test_get_value_0_31: pass
alsa_mixer-test_get_value_0_32: pass
alsa_mixer-test_get_value_0_33: pass
alsa_mixer-test_get_value_0_34: pass
alsa_mixer-test_get_value_0_35: pass
alsa_mixer-test_get_value_0_36: pass
alsa_mixer-test_get_value_0_37: pass
alsa_mixer-test_get_value_0_38: pass
alsa_mixer-test_get_value_0_39: pass
alsa_mixer-test_get_value_0_4: pass
alsa_mixer-test_get_value_0_40: pass
alsa_mixer-test_get_value_0_41: pass
alsa_mixer-test_get_value_0_42: pass
alsa_mixer-test_get_value_0_43: pass
alsa_mixer-test_get_value_0_44: pass
alsa_mixer-test_get_value_0_45: pass
alsa_mixer-test_get_value_0_46: pass
alsa_mixer-test_get_value_0_47: pass
alsa_mixer-test_get_value_0_48: pass
alsa_mixer-test_get_value_0_49: pass
alsa_mixer-test_get_value_0_5: pass
alsa_mixer-test_get_value_0_50: pass
alsa_mixer-test_get_value_0_51: pass
alsa_mixer-test_get_value_0_52: pass
alsa_mixer-test_get_value_0_53: pass
alsa_mixer-test_get_value_0_54: pass
alsa_mixer-test_get_value_0_55: pass
alsa_mixer-test_get_value_0_56: pass
alsa_mixer-test_get_value_0_57: pass
alsa_mixer-test_get_value_0_58: pass
alsa_mixer-test_get_value_0_59: pass
alsa_mixer-test_get_value_0_6: pass
alsa_mixer-test_get_value_0_60: pass
alsa_mixer-test_get_value_0_61: pass
alsa_mixer-test_get_value_0_62: pass
alsa_mixer-test_get_value_0_63: pass
alsa_mixer-test_get_value_0_64: pass
alsa_mixer-test_get_value_0_65: pass
alsa_mixer-test_get_value_0_66: pass
alsa_mixer-test_get_value_0_67: pass
alsa_mixer-test_get_value_0_68: pass
alsa_mixer-test_get_value_0_69: pass
alsa_mixer-test_get_value_0_7: pass
alsa_mixer-test_get_value_0_70: pass
alsa_mixer-test_get_value_0_71: pass
alsa_mixer-test_get_value_0_72: pass
alsa_mixer-test_get_value_0_73: pass
alsa_mixer-test_get_value_0_74: pass
alsa_mixer-test_get_value_0_75: pass
alsa_mixer-test_get_value_0_76: pass
alsa_mixer-test_get_value_0_77: fail
alsa_mixer-test_get_value_0_78: fail
alsa_mixer-test_get_value_0_79: fail
alsa_mixer-test_get_value_0_8: pass
alsa_mixer-test_get_value_0_80: pass
alsa_mixer-test_get_value_0_81: pass
alsa_mixer-test_get_value_0_82: pass
alsa_mixer-test_get_value_0_83: pass
alsa_mixer-test_get_value_0_84: pass
alsa_mixer-test_get_value_0_85: pass
alsa_mixer-test_get_value_0_86: pass
alsa_mixer-test_get_value_0_87: pass
alsa_mixer-test_get_value_0_88: pass
alsa_mixer-test_get_value_0_89: pass
alsa_mixer-test_get_value_0_9: pass
alsa_mixer-test_get_value_0_90: pass
alsa_mixer-test_get_value_0_91: pass
alsa_mixer-test_get_value_0_92: pass
alsa_mixer-test_get_value_0_93: pass
alsa_mixer-test_name_0_0: pass
alsa_mixer-test_name_0_1: pass
alsa_mixer-test_name_0_10: fail
alsa_mixer-test_name_0_11: fail
alsa_mixer-test_name_0_12: fail
alsa_mixer-test_name_0_13: fail
alsa_mixer-test_name_0_14: fail
alsa_mixer-test_name_0_15: fail
alsa_mixer-test_name_0_16: fail
alsa_mixer-test_name_0_17: fail
alsa_mixer-test_name_0_18: fail
alsa_mixer-test_name_0_19: fail
alsa_mixer-test_name_0_2: pass
alsa_mixer-test_name_0_20: fail
alsa_mixer-test_name_0_21: fail
alsa_mixer-test_name_0_22: pass
alsa_mixer-test_name_0_23: pass
alsa_mixer-test_name_0_24: pass
alsa_mixer-test_name_0_25: pass
alsa_mixer-test_name_0_26: pass
alsa_mixer-test_name_0_27: pass
alsa_mixer-test_name_0_28: pass
alsa_mixer-test_name_0_29: pass
alsa_mixer-test_name_0_3: pass
alsa_mixer-test_name_0_30: fail
alsa_mixer-test_name_0_31: fail
alsa_mixer-test_name_0_32: fail
alsa_mixer-test_name_0_33: fail
alsa_mixer-test_name_0_34: fail
alsa_mixer-test_name_0_35: fail
alsa_mixer-test_name_0_36: fail
alsa_mixer-test_name_0_37: fail
alsa_mixer-test_name_0_38: fail
alsa_mixer-test_name_0_39: fail
alsa_mixer-test_name_0_4: pass
alsa_mixer-test_name_0_40: fail
alsa_mixer-test_name_0_41: fail
alsa_mixer-test_name_0_42: fail
alsa_mixer-test_name_0_43: fail
alsa_mixer-test_name_0_44: fail
alsa_mixer-test_name_0_45: fail
alsa_mixer-test_name_0_46: fail
alsa_mixer-test_name_0_47: fail
alsa_mixer-test_name_0_48: fail
alsa_mixer-test_name_0_49: fail
alsa_mixer-test_name_0_5: pass
alsa_mixer-test_name_0_50: fail
alsa_mixer-test_name_0_51: fail
alsa_mixer-test_name_0_52: fail
alsa_mixer-test_name_0_53: fail
alsa_mixer-test_name_0_54: fail
alsa_mixer-test_name_0_55: fail
alsa_mixer-test_name_0_56: fail
alsa_mixer-test_name_0_57: fail
alsa_mixer-test_name_0_58: fail
alsa_mixer-test_name_0_59: fail
alsa_mixer-test_name_0_6: fail
alsa_mixer-test_name_0_60: fail
alsa_mixer-test_name_0_61: fail
alsa_mixer-test_name_0_62: fail
alsa_mixer-test_name_0_63: fail
alsa_mixer-test_name_0_64: fail
alsa_mixer-test_name_0_65: fail
alsa_mixer-test_name_0_66: fail
alsa_mixer-test_name_0_67: fail
alsa_mixer-test_name_0_68: fail
alsa_mixer-test_name_0_69: fail
alsa_mixer-test_name_0_7: fail
alsa_mixer-test_name_0_70: fail
alsa_mixer-test_name_0_71: fail
alsa_mixer-test_name_0_72: fail
alsa_mixer-test_name_0_73: fail
alsa_mixer-test_name_0_74: fail
alsa_mixer-test_name_0_75: fail
alsa_mixer-test_name_0_76: fail
alsa_mixer-test_name_0_77: pass
alsa_mixer-test_name_0_78: pass
alsa_mixer-test_name_0_79: pass
alsa_mixer-test_name_0_8: fail
alsa_mixer-test_name_0_80: pass
alsa_mixer-test_name_0_81: pass
alsa_mixer-test_name_0_82: pass
alsa_mixer-test_name_0_83: pass
alsa_mixer-test_name_0_84: pass
alsa_mixer-test_name_0_85: pass
alsa_mixer-test_name_0_86: pass
alsa_mixer-test_name_0_87: pass
alsa_mixer-test_name_0_88: pass
alsa_mixer-test_name_0_89: pass
alsa_mixer-test_name_0_9: fail
alsa_mixer-test_name_0_90: pass
alsa_mixer-test_name_0_91: pass
alsa_mixer-test_name_0_92: pass
alsa_mixer-test_name_0_93: pass
alsa_mixer-test_write_default_0_0: pass
alsa_mixer-test_write_default_0_1: pass
alsa_mixer-test_write_default_0_10: pass
alsa_mixer-test_write_default_0_11: pass
alsa_mixer-test_write_default_0_12: pass
alsa_mixer-test_write_default_0_13: pass
alsa_mixer-test_write_default_0_14: pass
alsa_mixer-test_write_default_0_15: pass
alsa_mixer-test_write_default_0_16: pass
alsa_mixer-test_write_default_0_17: pass
alsa_mixer-test_write_default_0_18: pass
alsa_mixer-test_write_default_0_19: pass
alsa_mixer-test_write_default_0_2: pass
alsa_mixer-test_write_default_0_20: pass
alsa_mixer-test_write_default_0_21: pass
alsa_mixer-test_write_default_0_22: pass
alsa_mixer-test_write_default_0_23: pass
alsa_mixer-test_write_default_0_24: pass
alsa_mixer-test_write_default_0_25: pass
alsa_mixer-test_write_default_0_26: pass
alsa_mixer-test_write_default_0_27: pass
alsa_mixer-test_write_default_0_28: pass
alsa_mixer-test_write_default_0_29: pass
alsa_mixer-test_write_default_0_3: pass
alsa_mixer-test_write_default_0_30: pass
alsa_mixer-test_write_default_0_31: pass
alsa_mixer-test_write_default_0_32: pass
alsa_mixer-test_write_default_0_33: pass
alsa_mixer-test_write_default_0_34: pass
alsa_mixer-test_write_default_0_35: pass
alsa_mixer-test_write_default_0_36: pass
alsa_mixer-test_write_default_0_37: pass
alsa_mixer-test_write_default_0_38: pass
alsa_mixer-test_write_default_0_39: pass
alsa_mixer-test_write_default_0_4: pass
alsa_mixer-test_write_default_0_40: pass
alsa_mixer-test_write_default_0_41: pass
alsa_mixer-test_write_default_0_42: pass
alsa_mixer-test_write_default_0_43: pass
alsa_mixer-test_write_default_0_44: pass
alsa_mixer-test_write_default_0_45: pass
alsa_mixer-test_write_default_0_46: pass
alsa_mixer-test_write_default_0_47: pass
alsa_mixer-test_write_default_0_48: pass
alsa_mixer-test_write_default_0_49: pass
alsa_mixer-test_write_default_0_5: pass
alsa_mixer-test_write_default_0_50: pass
alsa_mixer-test_write_default_0_51: pass
alsa_mixer-test_write_default_0_52: pass
alsa_mixer-test_write_default_0_53: pass
alsa_mixer-test_write_default_0_54: pass
alsa_mixer-test_write_default_0_55: pass
alsa_mixer-test_write_default_0_56: pass
alsa_mixer-test_write_default_0_57: pass
alsa_mixer-test_write_default_0_58: pass
alsa_mixer-test_write_default_0_59: pass
alsa_mixer-test_write_default_0_6: pass
alsa_mixer-test_write_default_0_60: pass
alsa_mixer-test_write_default_0_61: pass
alsa_mixer-test_write_default_0_62: pass
alsa_mixer-test_write_default_0_63: pass
alsa_mixer-test_write_default_0_64: pass
alsa_mixer-test_write_default_0_65: pass
alsa_mixer-test_write_default_0_66: pass
alsa_mixer-test_write_default_0_67: pass
alsa_mixer-test_write_default_0_68: pass
alsa_mixer-test_write_default_0_69: pass
alsa_mixer-test_write_default_0_7: pass
alsa_mixer-test_write_default_0_70: pass
alsa_mixer-test_write_default_0_71: pass
alsa_mixer-test_write_default_0_72: pass
alsa_mixer-test_write_default_0_73: pass
alsa_mixer-test_write_default_0_74: pass
alsa_mixer-test_write_default_0_75: pass
alsa_mixer-test_write_default_0_76: pass
alsa_mixer-test_write_default_0_77: fail
alsa_mixer-test_write_default_0_78: fail
alsa_mixer-test_write_default_0_79: fail
alsa_mixer-test_write_default_0_8: pass
alsa_mixer-test_write_default_0_80: pass
alsa_mixer-test_write_default_0_81: pass
alsa_mixer-test_write_default_0_82: skip
alsa_mixer-test_write_default_0_83: pass
alsa_mixer-test_write_default_0_84: pass
alsa_mixer-test_write_default_0_85: pass
alsa_mixer-test_write_default_0_86: pass
alsa_mixer-test_write_default_0_87: pass
alsa_mixer-test_write_default_0_88: pass
alsa_mixer-test_write_default_0_89: pass
alsa_mixer-test_write_default_0_9: pass
alsa_mixer-test_write_default_0_90: pass
alsa_mixer-test_write_default_0_91: pass
alsa_mixer-test_write_default_0_92: pass
alsa_mixer-test_write_default_0_93: pass
alsa_mixer-test_write_invalid_0_0: pass
alsa_mixer-test_write_invalid_0_1: pass
alsa_mixer-test_write_invalid_0_10: pass
alsa_mixer-test_write_invalid_0_11: pass
alsa_mixer-test_write_invalid_0_12: pass
alsa_mixer-test_write_invalid_0_13: pass
alsa_mixer-test_write_invalid_0_14: pass
alsa_mixer-test_write_invalid_0_15: pass
alsa_mixer-test_write_invalid_0_16: pass
alsa_mixer-test_write_invalid_0_17: pass
alsa_mixer-test_write_invalid_0_18: pass
alsa_mixer-test_write_invalid_0_19: pass
alsa_mixer-test_write_invalid_0_2: pass
alsa_mixer-test_write_invalid_0_20: pass
alsa_mixer-test_write_invalid_0_21: pass
alsa_mixer-test_write_invalid_0_22: pass
alsa_mixer-test_write_invalid_0_23: pass
alsa_mixer-test_write_invalid_0_24: pass
alsa_mixer-test_write_invalid_0_25: pass
alsa_mixer-test_write_invalid_0_26: pass
alsa_mixer-test_write_invalid_0_27: pass
alsa_mixer-test_write_invalid_0_28: pass
alsa_mixer-test_write_invalid_0_29: pass
alsa_mixer-test_write_invalid_0_3: pass
alsa_mixer-test_write_invalid_0_30: pass
alsa_mixer-test_write_invalid_0_31: pass
alsa_mixer-test_write_invalid_0_32: pass
alsa_mixer-test_write_invalid_0_33: pass
alsa_mixer-test_write_invalid_0_34: pass
alsa_mixer-test_write_invalid_0_35: pass
alsa_mixer-test_write_invalid_0_36: pass
alsa_mixer-test_write_invalid_0_37: pass
alsa_mixer-test_write_invalid_0_38: pass
alsa_mixer-test_write_invalid_0_39: pass
alsa_mixer-test_write_invalid_0_4: pass
alsa_mixer-test_write_invalid_0_40: pass
alsa_mixer-test_write_invalid_0_41: pass
alsa_mixer-test_write_invalid_0_42: pass
alsa_mixer-test_write_invalid_0_43: pass
alsa_mixer-test_write_invalid_0_44: pass
alsa_mixer-test_write_invalid_0_45: pass
alsa_mixer-test_write_invalid_0_46: pass
alsa_mixer-test_write_invalid_0_47: pass
alsa_mixer-test_write_invalid_0_48: pass
alsa_mixer-test_write_invalid_0_49: pass
alsa_mixer-test_write_invalid_0_5: pass
alsa_mixer-test_write_invalid_0_50: pass
alsa_mixer-test_write_invalid_0_51: pass
alsa_mixer-test_write_invalid_0_52: pass
alsa_mixer-test_write_invalid_0_53: pass
alsa_mixer-test_write_invalid_0_54: pass
alsa_mixer-test_write_invalid_0_55: pass
alsa_mixer-test_write_invalid_0_56: pass
alsa_mixer-test_write_invalid_0_57: pass
alsa_mixer-test_write_invalid_0_58: pass
alsa_mixer-test_write_invalid_0_59: pass
alsa_mixer-test_write_invalid_0_6: pass
alsa_mixer-test_write_invalid_0_60: pass
alsa_mixer-test_write_invalid_0_61: pass
alsa_mixer-test_write_invalid_0_62: pass
alsa_mixer-test_write_invalid_0_63: pass
alsa_mixer-test_write_invalid_0_64: pass
alsa_mixer-test_write_invalid_0_65: pass
alsa_mixer-test_write_invalid_0_66: pass
alsa_mixer-test_write_invalid_0_67: pass
alsa_mixer-test_write_invalid_0_68: pass
alsa_mixer-test_write_invalid_0_69: pass
alsa_mixer-test_write_invalid_0_7: pass
alsa_mixer-test_write_invalid_0_70: pass
alsa_mixer-test_write_invalid_0_71: pass
alsa_mixer-test_write_invalid_0_72: pass
alsa_mixer-test_write_invalid_0_73: pass
alsa_mixer-test_write_invalid_0_74: pass
alsa_mixer-test_write_invalid_0_75: pass
alsa_mixer-test_write_invalid_0_76: pass
alsa_mixer-test_write_invalid_0_77: fail
alsa_mixer-test_write_invalid_0_78: fail
alsa_mixer-test_write_invalid_0_79: fail
alsa_mixer-test_write_invalid_0_8: pass
alsa_mixer-test_write_invalid_0_80: pass
alsa_mixer-test_write_invalid_0_81: fail
alsa_mixer-test_write_invalid_0_82: skip
alsa_mixer-test_write_invalid_0_83: pass
alsa_mixer-test_write_invalid_0_84: pass
alsa_mixer-test_write_invalid_0_85: pass
alsa_mixer-test_write_invalid_0_86: pass
alsa_mixer-test_write_invalid_0_87: pass
alsa_mixer-test_write_invalid_0_88: pass
alsa_mixer-test_write_invalid_0_89: pass
alsa_mixer-test_write_invalid_0_9: pass
alsa_mixer-test_write_invalid_0_90: pass
alsa_mixer-test_write_invalid_0_91: pass
alsa_mixer-test_write_invalid_0_92: pass
alsa_mixer-test_write_invalid_0_93: pass
alsa_mixer-test_write_valid_0_0: pass
alsa_mixer-test_write_valid_0_1: pass
alsa_mixer-test_write_valid_0_10: pass
alsa_mixer-test_write_valid_0_11: pass
alsa_mixer-test_write_valid_0_12: pass
alsa_mixer-test_write_valid_0_13: pass
alsa_mixer-test_write_valid_0_14: pass
alsa_mixer-test_write_valid_0_15: pass
alsa_mixer-test_write_valid_0_16: pass
alsa_mixer-test_write_valid_0_17: pass
alsa_mixer-test_write_valid_0_18: pass
alsa_mixer-test_write_valid_0_19: pass
alsa_mixer-test_write_valid_0_2: pass
alsa_mixer-test_write_valid_0_20: pass
alsa_mixer-test_write_valid_0_21: pass
alsa_mixer-test_write_valid_0_22: pass
alsa_mixer-test_write_valid_0_23: pass
alsa_mixer-test_write_valid_0_24: pass
alsa_mixer-test_write_valid_0_25: pass
alsa_mixer-test_write_valid_0_26: pass
alsa_mixer-test_write_valid_0_27: pass
alsa_mixer-test_write_valid_0_28: pass
alsa_mixer-test_write_valid_0_29: pass
alsa_mixer-test_write_valid_0_3: pass
alsa_mixer-test_write_valid_0_30: pass
alsa_mixer-test_write_valid_0_31: pass
alsa_mixer-test_write_valid_0_32: pass
alsa_mixer-test_write_valid_0_33: pass
alsa_mixer-test_write_valid_0_34: pass
alsa_mixer-test_write_valid_0_35: pass
alsa_mixer-test_write_valid_0_36: pass
alsa_mixer-test_write_valid_0_37: pass
alsa_mixer-test_write_valid_0_38: pass
alsa_mixer-test_write_valid_0_39: pass
alsa_mixer-test_write_valid_0_4: pass
alsa_mixer-test_write_valid_0_40: pass
alsa_mixer-test_write_valid_0_41: pass
alsa_mixer-test_write_valid_0_42: pass
alsa_mixer-test_write_valid_0_43: pass
alsa_mixer-test_write_valid_0_44: pass
alsa_mixer-test_write_valid_0_45: pass
alsa_mixer-test_write_valid_0_46: pass
alsa_mixer-test_write_valid_0_47: pass
alsa_mixer-test_write_valid_0_48: pass
alsa_mixer-test_write_valid_0_49: pass
alsa_mixer-test_write_valid_0_5: pass
alsa_mixer-test_write_valid_0_50: pass
alsa_mixer-test_write_valid_0_51: pass
alsa_mixer-test_write_valid_0_52: pass
alsa_mixer-test_write_valid_0_53: pass
alsa_mixer-test_write_valid_0_54: pass
alsa_mixer-test_write_valid_0_55: pass
alsa_mixer-test_write_valid_0_56: pass
alsa_mixer-test_write_valid_0_57: pass
alsa_mixer-test_write_valid_0_58: pass
alsa_mixer-test_write_valid_0_59: pass
alsa_mixer-test_write_valid_0_6: pass
alsa_mixer-test_write_valid_0_60: pass
alsa_mixer-test_write_valid_0_61: pass
alsa_mixer-test_write_valid_0_62: pass
alsa_mixer-test_write_valid_0_63: pass
alsa_mixer-test_write_valid_0_64: pass
alsa_mixer-test_write_valid_0_65: pass
alsa_mixer-test_write_valid_0_66: pass
alsa_mixer-test_write_valid_0_67: pass
alsa_mixer-test_write_valid_0_68: pass
alsa_mixer-test_write_valid_0_69: pass
alsa_mixer-test_write_valid_0_7: pass
alsa_mixer-test_write_valid_0_70: pass
alsa_mixer-test_write_valid_0_71: pass
alsa_mixer-test_write_valid_0_72: pass
alsa_mixer-test_write_valid_0_73: pass
alsa_mixer-test_write_valid_0_74: pass
alsa_mixer-test_write_valid_0_75: pass
alsa_mixer-test_write_valid_0_76: pass
alsa_mixer-test_write_valid_0_77: fail
alsa_mixer-test_write_valid_0_78: fail
alsa_mixer-test_write_valid_0_79: fail
alsa_mixer-test_write_valid_0_8: pass
alsa_mixer-test_write_valid_0_80: pass
alsa_mixer-test_write_valid_0_81: pass
alsa_mixer-test_write_valid_0_82: skip
alsa_mixer-test_write_valid_0_83: pass
alsa_mixer-test_write_valid_0_84: pass
alsa_mixer-test_write_valid_0_85: fail
alsa_mixer-test_write_valid_0_86: fail
alsa_mixer-test_write_valid_0_87: pass
alsa_mixer-test_write_valid_0_88: fail
alsa_mixer-test_write_valid_0_89: pass
alsa_mixer-test_write_valid_0_9: pass
alsa_mixer-test_write_valid_0_90: pass
alsa_mixer-test_write_valid_0_91: pass
alsa_mixer-test_write_valid_0_92: pass
alsa_mixer-test_write_valid_0_93: pass
shardfile-alsa: pass
9932 09:54:53.778548 end: 3.1 lava-test-shell (duration 00:00:44) [common]
9933 09:54:53.778969 end: 3 lava-test-retry (duration 00:00:44) [common]
9934 09:54:53.779403 start: 4 finalize (timeout 00:07:26) [common]
9935 09:54:53.779836 start: 4.1 power-off (timeout 00:00:30) [common]
9936 09:54:53.780505 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-5', '--port=1', '--command=off']
9937 09:54:55.904402 >> Command sent successfully.
9938 09:54:55.911410 Returned 0 in 2 seconds
9939 09:54:56.012225 end: 4.1 power-off (duration 00:00:02) [common]
9941 09:54:56.013750 start: 4.2 read-feedback (timeout 00:07:23) [common]
9942 09:54:56.015128 Listened to connection for namespace 'common' for up to 1s
9943 09:54:57.015777 Finalising connection for namespace 'common'
9944 09:54:57.016432 Disconnecting from shell: Finalise
9945 09:54:57.016899 / #
9946 09:54:57.117880 end: 4.2 read-feedback (duration 00:00:01) [common]
9947 09:54:57.118635 end: 4 finalize (duration 00:00:03) [common]
9948 09:54:57.119263 Cleaning after the job
9949 09:54:57.119775 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/ramdisk
9950 09:54:57.124504 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/kernel
9951 09:54:57.135004 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/dtb
9952 09:54:57.135166 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/nfsrootfs
9953 09:54:57.198750 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407592/tftp-deploy-paprs7ub/modules
9954 09:54:57.204409 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407592
9955 09:54:57.760542 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407592
9956 09:54:57.760719 Job finished correctly