Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 88
1 10:01:32.350809 lava-dispatcher, installed at version: 2024.03
2 10:01:32.351038 start: 0 validate
3 10:01:32.351183 Start time: 2024-06-18 10:01:32.351174+00:00 (UTC)
4 10:01:32.351314 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:01:32.351474 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 10:01:32.636427 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:01:32.637183 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:01:32.896873 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:01:32.897683 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 10:01:33.154352 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:01:33.155093 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:01:33.412185 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:01:33.412936 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:01:33.686258 validate duration: 1.34
16 10:01:33.687725 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:01:33.688414 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:01:33.688945 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:01:33.689595 Not decompressing ramdisk as can be used compressed.
20 10:01:33.690065 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 10:01:33.690441 saving as /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/ramdisk/initrd.cpio.gz
22 10:01:33.690815 total size: 5628169 (5 MB)
23 10:01:33.697283 progress 0 % (0 MB)
24 10:01:33.706583 progress 5 % (0 MB)
25 10:01:33.712721 progress 10 % (0 MB)
26 10:01:33.716859 progress 15 % (0 MB)
27 10:01:33.720420 progress 20 % (1 MB)
28 10:01:33.723402 progress 25 % (1 MB)
29 10:01:33.726386 progress 30 % (1 MB)
30 10:01:33.729064 progress 35 % (1 MB)
31 10:01:33.731360 progress 40 % (2 MB)
32 10:01:33.733617 progress 45 % (2 MB)
33 10:01:33.735574 progress 50 % (2 MB)
34 10:01:33.737590 progress 55 % (2 MB)
35 10:01:33.739485 progress 60 % (3 MB)
36 10:01:33.741160 progress 65 % (3 MB)
37 10:01:33.742965 progress 70 % (3 MB)
38 10:01:33.744514 progress 75 % (4 MB)
39 10:01:33.746305 progress 80 % (4 MB)
40 10:01:33.747847 progress 85 % (4 MB)
41 10:01:33.749560 progress 90 % (4 MB)
42 10:01:33.751269 progress 95 % (5 MB)
43 10:01:33.752898 progress 100 % (5 MB)
44 10:01:33.753129 5 MB downloaded in 0.06 s (86.10 MB/s)
45 10:01:33.753297 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:01:33.753568 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:01:33.753664 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:01:33.753757 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:01:33.753905 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:01:33.753986 saving as /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/kernel/Image
52 10:01:33.754054 total size: 54813184 (52 MB)
53 10:01:33.754122 No compression specified
54 10:01:33.755318 progress 0 % (0 MB)
55 10:01:33.771232 progress 5 % (2 MB)
56 10:01:33.786974 progress 10 % (5 MB)
57 10:01:33.802494 progress 15 % (7 MB)
58 10:01:33.818181 progress 20 % (10 MB)
59 10:01:33.833647 progress 25 % (13 MB)
60 10:01:33.849147 progress 30 % (15 MB)
61 10:01:33.864587 progress 35 % (18 MB)
62 10:01:33.880261 progress 40 % (20 MB)
63 10:01:33.895615 progress 45 % (23 MB)
64 10:01:33.911174 progress 50 % (26 MB)
65 10:01:33.926747 progress 55 % (28 MB)
66 10:01:33.942107 progress 60 % (31 MB)
67 10:01:33.957736 progress 65 % (34 MB)
68 10:01:33.972958 progress 70 % (36 MB)
69 10:01:33.988405 progress 75 % (39 MB)
70 10:01:34.003845 progress 80 % (41 MB)
71 10:01:34.019163 progress 85 % (44 MB)
72 10:01:34.034731 progress 90 % (47 MB)
73 10:01:34.050016 progress 95 % (49 MB)
74 10:01:34.064991 progress 100 % (52 MB)
75 10:01:34.065246 52 MB downloaded in 0.31 s (167.98 MB/s)
76 10:01:34.065414 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:01:34.065686 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:01:34.065784 start: 1.3 download-retry (timeout 00:10:00) [common]
80 10:01:34.065879 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 10:01:34.066029 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 10:01:34.066117 saving as /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 10:01:34.066186 total size: 57695 (0 MB)
84 10:01:34.066254 No compression specified
85 10:01:34.067579 progress 56 % (0 MB)
86 10:01:34.067880 progress 100 % (0 MB)
87 10:01:34.068104 0 MB downloaded in 0.00 s (28.72 MB/s)
88 10:01:34.068241 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:01:34.068493 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:01:34.068589 start: 1.4 download-retry (timeout 00:10:00) [common]
92 10:01:34.068681 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 10:01:34.068804 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 10:01:34.068880 saving as /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/nfsrootfs/full.rootfs.tar
95 10:01:34.068949 total size: 120894716 (115 MB)
96 10:01:34.069017 Using unxz to decompress xz
97 10:01:34.073334 progress 0 % (0 MB)
98 10:01:34.452241 progress 5 % (5 MB)
99 10:01:34.849068 progress 10 % (11 MB)
100 10:01:35.232911 progress 15 % (17 MB)
101 10:01:35.593443 progress 20 % (23 MB)
102 10:01:35.918483 progress 25 % (28 MB)
103 10:01:36.310756 progress 30 % (34 MB)
104 10:01:36.679261 progress 35 % (40 MB)
105 10:01:36.860426 progress 40 % (46 MB)
106 10:01:37.056607 progress 45 % (51 MB)
107 10:01:37.399644 progress 50 % (57 MB)
108 10:01:37.807911 progress 55 % (63 MB)
109 10:01:38.184774 progress 60 % (69 MB)
110 10:01:38.557618 progress 65 % (74 MB)
111 10:01:38.934908 progress 70 % (80 MB)
112 10:01:39.326805 progress 75 % (86 MB)
113 10:01:39.699560 progress 80 % (92 MB)
114 10:01:40.071287 progress 85 % (98 MB)
115 10:01:40.462041 progress 90 % (103 MB)
116 10:01:40.821245 progress 95 % (109 MB)
117 10:01:41.215499 progress 100 % (115 MB)
118 10:01:41.221477 115 MB downloaded in 7.15 s (16.12 MB/s)
119 10:01:41.221773 end: 1.4.1 http-download (duration 00:00:07) [common]
121 10:01:41.222137 end: 1.4 download-retry (duration 00:00:07) [common]
122 10:01:41.222265 start: 1.5 download-retry (timeout 00:09:52) [common]
123 10:01:41.222367 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 10:01:41.222533 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:01:41.222617 saving as /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/modules/modules.tar
126 10:01:41.222686 total size: 8619356 (8 MB)
127 10:01:41.222758 Using unxz to decompress xz
128 10:01:41.227203 progress 0 % (0 MB)
129 10:01:41.249043 progress 5 % (0 MB)
130 10:01:41.276196 progress 10 % (0 MB)
131 10:01:41.304355 progress 15 % (1 MB)
132 10:01:41.331997 progress 20 % (1 MB)
133 10:01:41.360829 progress 25 % (2 MB)
134 10:01:41.388539 progress 30 % (2 MB)
135 10:01:41.416344 progress 35 % (2 MB)
136 10:01:41.443714 progress 40 % (3 MB)
137 10:01:41.471370 progress 45 % (3 MB)
138 10:01:41.498152 progress 50 % (4 MB)
139 10:01:41.525640 progress 55 % (4 MB)
140 10:01:41.552853 progress 60 % (4 MB)
141 10:01:41.579449 progress 65 % (5 MB)
142 10:01:41.610610 progress 70 % (5 MB)
143 10:01:41.638262 progress 75 % (6 MB)
144 10:01:41.664287 progress 80 % (6 MB)
145 10:01:41.690673 progress 85 % (7 MB)
146 10:01:41.717007 progress 90 % (7 MB)
147 10:01:41.748643 progress 95 % (7 MB)
148 10:01:41.782638 progress 100 % (8 MB)
149 10:01:41.787871 8 MB downloaded in 0.57 s (14.54 MB/s)
150 10:01:41.788154 end: 1.5.1 http-download (duration 00:00:01) [common]
152 10:01:41.788457 end: 1.5 download-retry (duration 00:00:01) [common]
153 10:01:41.788567 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 10:01:41.788673 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 10:01:45.686857 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14407643/extract-nfsrootfs-ypalcua5
156 10:01:45.687098 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 10:01:45.687213 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 10:01:45.687434 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii
159 10:01:45.687593 makedir: /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin
160 10:01:45.687720 makedir: /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/tests
161 10:01:45.687851 makedir: /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/results
162 10:01:45.687964 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-add-keys
163 10:01:45.688145 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-add-sources
164 10:01:45.688293 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-background-process-start
165 10:01:45.688451 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-background-process-stop
166 10:01:45.688628 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-common-functions
167 10:01:45.688776 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-echo-ipv4
168 10:01:45.688920 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-install-packages
169 10:01:45.689077 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-installed-packages
170 10:01:45.689238 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-os-build
171 10:01:45.689400 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-probe-channel
172 10:01:45.689541 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-probe-ip
173 10:01:45.689679 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-target-ip
174 10:01:45.689818 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-target-mac
175 10:01:45.689956 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-target-storage
176 10:01:45.690111 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-test-case
177 10:01:45.690268 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-test-event
178 10:01:45.690417 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-test-feedback
179 10:01:45.690558 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-test-raise
180 10:01:45.690710 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-test-reference
181 10:01:45.690876 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-test-runner
182 10:01:45.691034 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-test-set
183 10:01:45.691177 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-test-shell
184 10:01:45.691319 Updating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-add-keys (debian)
185 10:01:45.691504 Updating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-add-sources (debian)
186 10:01:45.691677 Updating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-install-packages (debian)
187 10:01:45.691849 Updating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-installed-packages (debian)
188 10:01:45.692020 Updating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/bin/lava-os-build (debian)
189 10:01:45.692171 Creating /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/environment
190 10:01:45.692293 LAVA metadata
191 10:01:45.692368 - LAVA_JOB_ID=14407643
192 10:01:45.692437 - LAVA_DISPATCHER_IP=192.168.201.1
193 10:01:45.692588 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 10:01:45.692676 skipped lava-vland-overlay
195 10:01:45.692763 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 10:01:45.692865 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 10:01:45.692934 skipped lava-multinode-overlay
198 10:01:45.693014 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 10:01:45.693104 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 10:01:45.693186 Loading test definitions
201 10:01:45.693284 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 10:01:45.693364 Using /lava-14407643 at stage 0
203 10:01:45.693682 uuid=14407643_1.6.2.3.1 testdef=None
204 10:01:45.693796 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 10:01:45.693891 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 10:01:45.694433 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 10:01:45.694694 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 10:01:45.695343 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 10:01:45.695792 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 10:01:45.696428 runner path: /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/0/tests/0_timesync-off test_uuid 14407643_1.6.2.3.1
213 10:01:45.696602 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 10:01:45.696854 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 10:01:45.696947 Using /lava-14407643 at stage 0
217 10:01:45.697054 Fetching tests from https://github.com/kernelci/test-definitions.git
218 10:01:45.697171 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/0/tests/1_kselftest-arm64'
219 10:01:48.578919 Running '/usr/bin/git checkout kernelci.org
220 10:01:48.741820 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 10:01:48.742696 uuid=14407643_1.6.2.3.5 testdef=None
222 10:01:48.742882 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 10:01:48.743169 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 10:01:48.744037 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 10:01:48.744296 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 10:01:48.745375 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 10:01:48.745643 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 10:01:48.746676 runner path: /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/0/tests/1_kselftest-arm64 test_uuid 14407643_1.6.2.3.5
232 10:01:48.746778 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 10:01:48.746851 BRANCH='cip'
234 10:01:48.746919 SKIPFILE='/dev/null'
235 10:01:48.746986 SKIP_INSTALL='True'
236 10:01:48.747050 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 10:01:48.747113 TST_CASENAME=''
238 10:01:48.747177 TST_CMDFILES='arm64'
239 10:01:48.747335 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 10:01:48.747575 Creating lava-test-runner.conf files
242 10:01:48.747647 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407643/lava-overlay-6xx1hnii/lava-14407643/0 for stage 0
243 10:01:48.747751 - 0_timesync-off
244 10:01:48.747837 - 1_kselftest-arm64
245 10:01:48.747977 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 10:01:48.748083 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 10:01:57.154215 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 10:01:57.154387 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 10:01:57.154492 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 10:01:57.154604 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 10:01:57.154709 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 10:01:57.337070 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 10:01:57.337503 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 10:01:57.337641 extracting modules file /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407643/extract-nfsrootfs-ypalcua5
255 10:01:57.577168 extracting modules file /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407643/extract-overlay-ramdisk-xdyq90yi/ramdisk
256 10:01:57.822835 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 10:01:57.823020 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 10:01:57.823126 [common] Applying overlay to NFS
259 10:01:57.823204 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407643/compress-overlay-1jnwvv5f/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407643/extract-nfsrootfs-ypalcua5
260 10:01:58.844594 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 10:01:58.844775 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 10:01:58.844884 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 10:01:58.844984 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 10:01:58.845074 Building ramdisk /var/lib/lava/dispatcher/tmp/14407643/extract-overlay-ramdisk-xdyq90yi/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407643/extract-overlay-ramdisk-xdyq90yi/ramdisk
265 10:01:59.214769 >> 130466 blocks
266 10:02:01.465644 rename /var/lib/lava/dispatcher/tmp/14407643/extract-overlay-ramdisk-xdyq90yi/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/ramdisk/ramdisk.cpio.gz
267 10:02:01.466148 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 10:02:01.466284 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 10:02:01.466400 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 10:02:01.466524 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/kernel/Image']
271 10:02:15.559428 Returned 0 in 14 seconds
272 10:02:15.660447 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/kernel/image.itb
273 10:02:16.086824 output: FIT description: Kernel Image image with one or more FDT blobs
274 10:02:16.087249 output: Created: Tue Jun 18 11:02:16 2024
275 10:02:16.087334 output: Image 0 (kernel-1)
276 10:02:16.087413 output: Description:
277 10:02:16.087488 output: Created: Tue Jun 18 11:02:16 2024
278 10:02:16.087556 output: Type: Kernel Image
279 10:02:16.087625 output: Compression: lzma compressed
280 10:02:16.087691 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
281 10:02:16.087759 output: Architecture: AArch64
282 10:02:16.087824 output: OS: Linux
283 10:02:16.087889 output: Load Address: 0x00000000
284 10:02:16.087955 output: Entry Point: 0x00000000
285 10:02:16.088017 output: Hash algo: crc32
286 10:02:16.088081 output: Hash value: 4137a6e7
287 10:02:16.088143 output: Image 1 (fdt-1)
288 10:02:16.088206 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 10:02:16.088270 output: Created: Tue Jun 18 11:02:16 2024
290 10:02:16.088330 output: Type: Flat Device Tree
291 10:02:16.088389 output: Compression: uncompressed
292 10:02:16.088448 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 10:02:16.088507 output: Architecture: AArch64
294 10:02:16.088567 output: Hash algo: crc32
295 10:02:16.088626 output: Hash value: a9713552
296 10:02:16.088684 output: Image 2 (ramdisk-1)
297 10:02:16.088742 output: Description: unavailable
298 10:02:16.088801 output: Created: Tue Jun 18 11:02:16 2024
299 10:02:16.088860 output: Type: RAMDisk Image
300 10:02:16.088918 output: Compression: Unknown Compression
301 10:02:16.088977 output: Data Size: 18744902 Bytes = 18305.57 KiB = 17.88 MiB
302 10:02:16.089039 output: Architecture: AArch64
303 10:02:16.089098 output: OS: Linux
304 10:02:16.089157 output: Load Address: unavailable
305 10:02:16.089215 output: Entry Point: unavailable
306 10:02:16.089274 output: Hash algo: crc32
307 10:02:16.089331 output: Hash value: ce26028d
308 10:02:16.089390 output: Default Configuration: 'conf-1'
309 10:02:16.089448 output: Configuration 0 (conf-1)
310 10:02:16.089506 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 10:02:16.089564 output: Kernel: kernel-1
312 10:02:16.089623 output: Init Ramdisk: ramdisk-1
313 10:02:16.089681 output: FDT: fdt-1
314 10:02:16.089740 output: Loadables: kernel-1
315 10:02:16.089798 output:
316 10:02:16.090027 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 10:02:16.090138 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 10:02:16.090259 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 10:02:16.090359 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 10:02:16.090449 No LXC device requested
321 10:02:16.090537 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 10:02:16.090635 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 10:02:16.090721 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 10:02:16.090796 Checking files for TFTP limit of 4294967296 bytes.
325 10:02:16.091351 end: 1 tftp-deploy (duration 00:00:42) [common]
326 10:02:16.091484 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 10:02:16.091587 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 10:02:16.091727 substitutions:
329 10:02:16.091806 - {DTB}: 14407643/tftp-deploy-suje0j50/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 10:02:16.091879 - {INITRD}: 14407643/tftp-deploy-suje0j50/ramdisk/ramdisk.cpio.gz
331 10:02:16.091946 - {KERNEL}: 14407643/tftp-deploy-suje0j50/kernel/Image
332 10:02:16.092010 - {LAVA_MAC}: None
333 10:02:16.092073 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14407643/extract-nfsrootfs-ypalcua5
334 10:02:16.092137 - {NFS_SERVER_IP}: 192.168.201.1
335 10:02:16.092200 - {PRESEED_CONFIG}: None
336 10:02:16.092261 - {PRESEED_LOCAL}: None
337 10:02:16.092321 - {RAMDISK}: 14407643/tftp-deploy-suje0j50/ramdisk/ramdisk.cpio.gz
338 10:02:16.092382 - {ROOT_PART}: None
339 10:02:16.092443 - {ROOT}: None
340 10:02:16.092504 - {SERVER_IP}: 192.168.201.1
341 10:02:16.092564 - {TEE}: None
342 10:02:16.092624 Parsed boot commands:
343 10:02:16.092683 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 10:02:16.092887 Parsed boot commands: tftpboot 192.168.201.1 14407643/tftp-deploy-suje0j50/kernel/image.itb 14407643/tftp-deploy-suje0j50/kernel/cmdline
345 10:02:16.092986 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 10:02:16.093077 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 10:02:16.093176 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 10:02:16.093271 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 10:02:16.093356 Not connected, no need to disconnect.
350 10:02:16.093441 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 10:02:16.093535 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 10:02:16.093614 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-0'
353 10:02:16.097756 Setting prompt string to ['lava-test: # ']
354 10:02:16.098174 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 10:02:16.098297 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 10:02:16.098407 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 10:02:16.098513 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 10:02:16.098716 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-0']
359 10:02:41.335129 Returned 0 in 25 seconds
360 10:02:41.436222 end: 2.2.2.1 pdu-reboot (duration 00:00:25) [common]
362 10:02:41.437816 end: 2.2.2 reset-device (duration 00:00:25) [common]
363 10:02:41.438403 start: 2.2.3 depthcharge-start (timeout 00:04:35) [common]
364 10:02:41.438906 Setting prompt string to 'Starting depthcharge on Juniper...'
365 10:02:41.439281 Changing prompt to 'Starting depthcharge on Juniper...'
366 10:02:41.439704 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
367 10:02:41.440954 [Enter `^Ec?' for help]
368 10:02:41.441045 [DL] 00000000 00000000 010701
369 10:02:41.441124
370 10:02:41.441197
371 10:02:41.441265 F0: 102B 0000
372 10:02:41.441332
373 10:02:41.441399 F3: 1006 0033 [0200]
374 10:02:41.441465
375 10:02:41.441527 F3: 4001 00E0 [0200]
376 10:02:41.441589
377 10:02:41.441650 F3: 0000 0000
378 10:02:41.441715
379 10:02:41.441776 V0: 0000 0000 [0001]
380 10:02:41.441837
381 10:02:41.441932 00: 1027 0002
382 10:02:41.442033
383 10:02:41.442098 01: 0000 0000
384 10:02:41.442161
385 10:02:41.442223 BP: 0C00 0251 [0000]
386 10:02:41.442285
387 10:02:41.442346 G0: 1182 0000
388 10:02:41.442407
389 10:02:41.442468 EC: 0004 0000 [0001]
390 10:02:41.442529
391 10:02:41.442588 S7: 0000 0000 [0000]
392 10:02:41.442650
393 10:02:41.442710 CC: 0000 0000 [0001]
394 10:02:41.442769
395 10:02:41.442829 T0: 0000 00DB [000F]
396 10:02:41.442890
397 10:02:41.442950 Jump to BL
398 10:02:41.443010
399 10:02:41.443069
400 10:02:41.443129
401 10:02:41.443188 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
402 10:02:41.443252 ARM64: Exception handlers installed.
403 10:02:41.443314 ARM64: Testing exception
404 10:02:41.443374 ARM64: Done test exception
405 10:02:41.443445 WDT: Last reset was cold boot
406 10:02:41.443507 SPI0(PAD0) initialized at 992727 Hz
407 10:02:41.443567 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
408 10:02:41.443629 Manufacturer: ef
409 10:02:41.443689 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
410 10:02:41.443749 Probing TPM: . done!
411 10:02:41.443809 TPM ready after 0 ms
412 10:02:41.443870 Connected to device vid:did:rid of 1ae0:0028:00
413 10:02:41.443931 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
414 10:02:41.443992 Initialized TPM device CR50 revision 0
415 10:02:41.444052 tlcl_send_startup: Startup return code is 0
416 10:02:41.444113 TPM: setup succeeded
417 10:02:41.444173 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
418 10:02:41.444234 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
419 10:02:41.444296 in-header: 03 19 00 00 08 00 00 00
420 10:02:41.444356 in-data: a2 e0 47 00 13 00 00 00
421 10:02:41.444417 Chrome EC: UHEPI supported
422 10:02:41.444476 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
423 10:02:41.444537 in-header: 03 a1 00 00 08 00 00 00
424 10:02:41.444597 in-data: 84 60 60 10 00 00 00 00
425 10:02:41.444657 Phase 1
426 10:02:41.444717 FMAP: area GBB found @ 3f5000 (12032 bytes)
427 10:02:41.444779 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
428 10:02:41.444841 VB2:vb2_check_recovery() Recovery was requested manually
429 10:02:41.444901 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
430 10:02:41.444961 Recovery requested (1009000e)
431 10:02:41.445021 tlcl_extend: response is 0
432 10:02:41.445082 tlcl_extend: response is 0
433 10:02:41.445142
434 10:02:41.445202
435 10:02:41.445262 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
436 10:02:41.445322 ARM64: Exception handlers installed.
437 10:02:41.445382 ARM64: Testing exception
438 10:02:41.445443 ARM64: Done test exception
439 10:02:41.445503 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xc27f, sec=0x2014
440 10:02:41.445563 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
441 10:02:41.445624 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
442 10:02:41.445685 [RTC]rtc_get_frequency_meter,134: input=0xf, output=914
443 10:02:41.445745 [RTC]rtc_get_frequency_meter,134: input=0x7, output=778
444 10:02:41.445806 [RTC]rtc_get_frequency_meter,134: input=0xb, output=847
445 10:02:41.445866 [RTC]rtc_get_frequency_meter,134: input=0x9, output=814
446 10:02:41.445927 [RTC]rtc_get_frequency_meter,134: input=0x8, output=795
447 10:02:41.445987 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xc268
448 10:02:41.446047 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
449 10:02:41.446107 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
450 10:02:41.446167 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
451 10:02:41.446227 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
452 10:02:41.446288 in-header: 03 19 00 00 08 00 00 00
453 10:02:41.446348 in-data: a2 e0 47 00 13 00 00 00
454 10:02:41.446408 Chrome EC: UHEPI supported
455 10:02:41.446468 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
456 10:02:41.446530 in-header: 03 a1 00 00 08 00 00 00
457 10:02:41.446589 in-data: 84 60 60 10 00 00 00 00
458 10:02:41.446649 Skip loading cached calibration data
459 10:02:41.446709 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
460 10:02:41.446769 in-header: 03 a1 00 00 08 00 00 00
461 10:02:41.446828 in-data: 84 60 60 10 00 00 00 00
462 10:02:41.446889 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
463 10:02:41.446949 in-header: 03 a1 00 00 08 00 00 00
464 10:02:41.447009 in-data: 84 60 60 10 00 00 00 00
465 10:02:41.447069 ADC[3]: Raw value=216571 ID=1
466 10:02:41.447129 Manufacturer: ef
467 10:02:41.447189 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
468 10:02:41.447250 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
469 10:02:41.447310 CBFS @ 21000 size 3d4000
470 10:02:41.447371 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
471 10:02:41.447442 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
472 10:02:41.447503 CBFS: Found @ offset 3c700 size 44
473 10:02:41.447564 DRAM-K: Full Calibration
474 10:02:41.447624 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
475 10:02:41.447685 CBFS @ 21000 size 3d4000
476 10:02:41.447745 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
477 10:02:41.447806 CBFS: Locating 'fallback/dram'
478 10:02:41.447866 CBFS: Found @ offset 24b00 size 12268
479 10:02:41.447926 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
480 10:02:41.447986 ddr_geometry: 1, config: 0x0
481 10:02:41.448046 header.status = 0x0
482 10:02:41.448106 header.magic = 0x44524d4b (expected: 0x44524d4b)
483 10:02:41.448166 header.version = 0x5 (expected: 0x5)
484 10:02:41.448225 header.size = 0x8f0 (expected: 0x8f0)
485 10:02:41.448285 header.config = 0x0
486 10:02:41.448345 header.flags = 0x0
487 10:02:41.448405 header.checksum = 0x0
488 10:02:41.448657 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
489 10:02:41.448725 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
490 10:02:41.448787 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
491 10:02:41.448848 ddr_geometry:1
492 10:02:41.448908 [EMI] new MDL number = 1
493 10:02:41.448968 dram_cbt_mode_extern: 0
494 10:02:41.449028 dram_cbt_mode [RK0]: 0, [RK1]: 0
495 10:02:41.449088 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
496 10:02:41.449148
497 10:02:41.449207
498 10:02:41.449267 [Bianco] ETT version 0.0.0.1
499 10:02:41.449327 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
500 10:02:41.449388
501 10:02:41.449448 vSetVcoreByFreq with vcore:762500, freq=1600
502 10:02:41.449511
503 10:02:41.449570 [DramcInit]
504 10:02:41.449630 AutoRefreshCKEOff AutoREF OFF
505 10:02:41.449691 DDRPhyPLLSetting-CKEOFF
506 10:02:41.449752 DDRPhyPLLSetting-CKEON
507 10:02:41.449811
508 10:02:41.449872 Enable WDQS
509 10:02:41.449931 [ModeRegInit_LP4] CH0 RK0
510 10:02:41.449992 Write Rank0 MR13 =0x18
511 10:02:41.450052 Write Rank0 MR12 =0x5d
512 10:02:41.450112 Write Rank0 MR1 =0x56
513 10:02:41.450172 Write Rank0 MR2 =0x1a
514 10:02:41.450231 Write Rank0 MR11 =0x0
515 10:02:41.450291 Write Rank0 MR22 =0x38
516 10:02:41.450350 Write Rank0 MR14 =0x5d
517 10:02:41.450409 Write Rank0 MR3 =0x30
518 10:02:41.450469 Write Rank0 MR13 =0x58
519 10:02:41.450528 Write Rank0 MR12 =0x5d
520 10:02:41.450588 Write Rank0 MR1 =0x56
521 10:02:41.450647 Write Rank0 MR2 =0x2d
522 10:02:41.450707 Write Rank0 MR11 =0x23
523 10:02:41.450766 Write Rank0 MR22 =0x34
524 10:02:41.450826 Write Rank0 MR14 =0x10
525 10:02:41.450886 Write Rank0 MR3 =0x30
526 10:02:41.450945 Write Rank0 MR13 =0xd8
527 10:02:41.451005 [ModeRegInit_LP4] CH0 RK1
528 10:02:41.451076 Write Rank1 MR13 =0x18
529 10:02:41.451164 Write Rank1 MR12 =0x5d
530 10:02:41.451268 Write Rank1 MR1 =0x56
531 10:02:41.451373 Write Rank1 MR2 =0x1a
532 10:02:41.451487 Write Rank1 MR11 =0x0
533 10:02:41.451592 Write Rank1 MR22 =0x38
534 10:02:41.451695 Write Rank1 MR14 =0x5d
535 10:02:41.451800 Write Rank1 MR3 =0x30
536 10:02:41.451908 Write Rank1 MR13 =0x58
537 10:02:41.452013 Write Rank1 MR12 =0x5d
538 10:02:41.452117 Write Rank1 MR1 =0x56
539 10:02:41.452221 Write Rank1 MR2 =0x2d
540 10:02:41.452325 Write Rank1 MR11 =0x23
541 10:02:41.452429 Write Rank1 MR22 =0x34
542 10:02:41.452533 Write Rank1 MR14 =0x10
543 10:02:41.452637 Write Rank1 MR3 =0x30
544 10:02:41.452741 Write Rank1 MR13 =0xd8
545 10:02:41.452846 [ModeRegInit_LP4] CH1 RK0
546 10:02:41.452950 Write Rank0 MR13 =0x18
547 10:02:41.453057 Write Rank0 MR12 =0x5d
548 10:02:41.453161 Write Rank0 MR1 =0x56
549 10:02:41.453266 Write Rank0 MR2 =0x1a
550 10:02:41.453370 Write Rank0 MR11 =0x0
551 10:02:41.453474 Write Rank0 MR22 =0x38
552 10:02:41.453579 Write Rank0 MR14 =0x5d
553 10:02:41.453683 Write Rank0 MR3 =0x30
554 10:02:41.453790 Write Rank0 MR13 =0x58
555 10:02:41.453895 Write Rank0 MR12 =0x5d
556 10:02:41.454002 Write Rank0 MR1 =0x56
557 10:02:41.454107 Write Rank0 MR2 =0x2d
558 10:02:41.454211 Write Rank0 MR11 =0x23
559 10:02:41.454315 Write Rank0 MR22 =0x34
560 10:02:41.454419 Write Rank0 MR14 =0x10
561 10:02:41.454523 Write Rank0 MR3 =0x30
562 10:02:41.454627 Write Rank0 MR13 =0xd8
563 10:02:41.454730 [ModeRegInit_LP4] CH1 RK1
564 10:02:41.454834 Write Rank1 MR13 =0x18
565 10:02:41.454938 Write Rank1 MR12 =0x5d
566 10:02:41.455042 Write Rank1 MR1 =0x56
567 10:02:41.455145 Write Rank1 MR2 =0x1a
568 10:02:41.455249 Write Rank1 MR11 =0x0
569 10:02:41.455352 Write Rank1 MR22 =0x38
570 10:02:41.455464 Write Rank1 MR14 =0x5d
571 10:02:41.455569 Write Rank1 MR3 =0x30
572 10:02:41.455673 Write Rank1 MR13 =0x58
573 10:02:41.455777 Write Rank1 MR12 =0x5d
574 10:02:41.455880 Write Rank1 MR1 =0x56
575 10:02:41.455983 Write Rank1 MR2 =0x2d
576 10:02:41.456087 Write Rank1 MR11 =0x23
577 10:02:41.456191 Write Rank1 MR22 =0x34
578 10:02:41.456294 Write Rank1 MR14 =0x10
579 10:02:41.456398 Write Rank1 MR3 =0x30
580 10:02:41.456502 Write Rank1 MR13 =0xd8
581 10:02:41.456607 match AC timing 3
582 10:02:41.456714 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
583 10:02:41.456819 [MiockJmeterHQA]
584 10:02:41.456924 vSetVcoreByFreq with vcore:762500, freq=1600
585 10:02:41.457029
586 10:02:41.457133 MIOCK jitter meter ch=0
587 10:02:41.457238
588 10:02:41.457353 1T = (102-17) = 85 dly cells
589 10:02:41.457473 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 735/100 ps
590 10:02:41.457583 vSetVcoreByFreq with vcore:725000, freq=1200
591 10:02:41.457690
592 10:02:41.457796 MIOCK jitter meter ch=0
593 10:02:41.457906
594 10:02:41.458012 1T = (97-17) = 80 dly cells
595 10:02:41.458126 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
596 10:02:41.458234 vSetVcoreByFreq with vcore:725000, freq=800
597 10:02:41.458340
598 10:02:41.458446 MIOCK jitter meter ch=0
599 10:02:41.458552
600 10:02:41.458657 1T = (97-17) = 80 dly cells
601 10:02:41.458764 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
602 10:02:41.458871 vSetVcoreByFreq with vcore:762500, freq=1600
603 10:02:41.458976 vSetVcoreByFreq with vcore:762500, freq=1600
604 10:02:41.459084
605 10:02:41.459196 K DRVP
606 10:02:41.459302 1. OCD DRVP=0 CALOUT=0
607 10:02:41.459418 1. OCD DRVP=1 CALOUT=0
608 10:02:41.459529 1. OCD DRVP=2 CALOUT=0
609 10:02:41.459647 1. OCD DRVP=3 CALOUT=0
610 10:02:41.459770 1. OCD DRVP=4 CALOUT=0
611 10:02:41.459882 1. OCD DRVP=5 CALOUT=0
612 10:02:41.459998 1. OCD DRVP=6 CALOUT=0
613 10:02:41.460112 1. OCD DRVP=7 CALOUT=0
614 10:02:41.460234 1. OCD DRVP=8 CALOUT=0
615 10:02:41.460344 1. OCD DRVP=9 CALOUT=1
616 10:02:41.460454
617 10:02:41.460561 1. OCD DRVP calibration OK! DRVP=9
618 10:02:41.460670
619 10:02:41.460776
620 10:02:41.460888
621 10:02:41.460996 K ODTN
622 10:02:41.461102 3. OCD ODTN=0 ,CALOUT=1
623 10:02:41.461216 3. OCD ODTN=1 ,CALOUT=1
624 10:02:41.461325 3. OCD ODTN=2 ,CALOUT=1
625 10:02:41.461435 3. OCD ODTN=3 ,CALOUT=1
626 10:02:41.461544 3. OCD ODTN=4 ,CALOUT=1
627 10:02:41.461653 3. OCD ODTN=5 ,CALOUT=1
628 10:02:41.461761 3. OCD ODTN=6 ,CALOUT=1
629 10:02:41.461868 3. OCD ODTN=7 ,CALOUT=0
630 10:02:41.461975
631 10:02:41.462080 3. OCD ODTN calibration OK! ODTN=7
632 10:02:41.462187
633 10:02:41.462292 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=7
634 10:02:41.462397 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15
635 10:02:41.462503 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15 (After Adjust)
636 10:02:41.462608
637 10:02:41.462713 K DRVP
638 10:02:41.462818 1. OCD DRVP=0 CALOUT=0
639 10:02:41.462925 1. OCD DRVP=1 CALOUT=0
640 10:02:41.463031 1. OCD DRVP=2 CALOUT=0
641 10:02:41.463138 1. OCD DRVP=3 CALOUT=0
642 10:02:41.463245 1. OCD DRVP=4 CALOUT=0
643 10:02:41.463350 1. OCD DRVP=5 CALOUT=0
644 10:02:41.463469 1. OCD DRVP=6 CALOUT=0
645 10:02:41.463584 1. OCD DRVP=7 CALOUT=0
646 10:02:41.463701 1. OCD DRVP=8 CALOUT=0
647 10:02:41.463810 1. OCD DRVP=9 CALOUT=0
648 10:02:41.463922 1. OCD DRVP=10 CALOUT=0
649 10:02:41.464038 1. OCD DRVP=11 CALOUT=1
650 10:02:41.464151
651 10:02:41.464259 1. OCD DRVP calibration OK! DRVP=11
652 10:02:41.464370
653 10:02:41.464476
654 10:02:41.464581
655 10:02:41.464686 K ODTN
656 10:02:41.464791 3. OCD ODTN=0 ,CALOUT=1
657 10:02:41.465093 3. OCD ODTN=1 ,CALOUT=1
658 10:02:41.465203 3. OCD ODTN=2 ,CALOUT=1
659 10:02:41.465314 3. OCD ODTN=3 ,CALOUT=1
660 10:02:41.465423 3. OCD ODTN=4 ,CALOUT=1
661 10:02:41.465532 3. OCD ODTN=5 ,CALOUT=1
662 10:02:41.465640 3. OCD ODTN=6 ,CALOUT=1
663 10:02:41.465747 3. OCD ODTN=7 ,CALOUT=1
664 10:02:41.465855 3. OCD ODTN=8 ,CALOUT=1
665 10:02:41.465968 3. OCD ODTN=9 ,CALOUT=1
666 10:02:41.466078 3. OCD ODTN=10 ,CALOUT=1
667 10:02:41.466186 3. OCD ODTN=11 ,CALOUT=1
668 10:02:41.466296 3. OCD ODTN=12 ,CALOUT=1
669 10:02:41.466404 3. OCD ODTN=13 ,CALOUT=1
670 10:02:41.466512 3. OCD ODTN=14 ,CALOUT=1
671 10:02:41.466622 3. OCD ODTN=15 ,CALOUT=0
672 10:02:41.466732
673 10:02:41.466838 3. OCD ODTN calibration OK! ODTN=15
674 10:02:41.466947
675 10:02:41.467052 [SwImpedanceCal] DRVP=11, DRVN=9, ODTN=15
676 10:02:41.467157 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15
677 10:02:41.467263 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15 (After Adjust)
678 10:02:41.467369
679 10:02:41.467494 [DramcInit]
680 10:02:41.467601 AutoRefreshCKEOff AutoREF OFF
681 10:02:41.467709 DDRPhyPLLSetting-CKEOFF
682 10:02:41.467814 DDRPhyPLLSetting-CKEON
683 10:02:41.467919
684 10:02:41.468024 Enable WDQS
685 10:02:41.468129 ==
686 10:02:41.468236 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
687 10:02:41.468343 fsp= 1, odt_onoff= 1, Byte mode= 0
688 10:02:41.468449 ==
689 10:02:41.468555 [Duty_Offset_Calibration]
690 10:02:41.468659
691 10:02:41.468764 ===========================
692 10:02:41.468873 B0:1 B1:1 CA:1
693 10:02:41.468974 ==
694 10:02:41.469071 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
695 10:02:41.469167 fsp= 1, odt_onoff= 1, Byte mode= 0
696 10:02:41.469261 ==
697 10:02:41.469365 [Duty_Offset_Calibration]
698 10:02:41.469465
699 10:02:41.469566 ===========================
700 10:02:41.469661 B0:1 B1:0 CA:2
701 10:02:41.469755 [ModeRegInit_LP4] CH0 RK0
702 10:02:41.469849 Write Rank0 MR13 =0x18
703 10:02:41.469943 Write Rank0 MR12 =0x5d
704 10:02:41.470045 Write Rank0 MR1 =0x56
705 10:02:41.470141 Write Rank0 MR2 =0x1a
706 10:02:41.470237 Write Rank0 MR11 =0x0
707 10:02:41.470302 Write Rank0 MR22 =0x38
708 10:02:41.470363 Write Rank0 MR14 =0x5d
709 10:02:41.470424 Write Rank0 MR3 =0x30
710 10:02:41.470484 Write Rank0 MR13 =0x58
711 10:02:41.470544 Write Rank0 MR12 =0x5d
712 10:02:41.470604 Write Rank0 MR1 =0x56
713 10:02:41.470664 Write Rank0 MR2 =0x2d
714 10:02:41.470724 Write Rank0 MR11 =0x23
715 10:02:41.470784 Write Rank0 MR22 =0x34
716 10:02:41.470844 Write Rank0 MR14 =0x10
717 10:02:41.470904 Write Rank0 MR3 =0x30
718 10:02:41.470963 Write Rank0 MR13 =0xd8
719 10:02:41.471023 [ModeRegInit_LP4] CH0 RK1
720 10:02:41.471083 Write Rank1 MR13 =0x18
721 10:02:41.471143 Write Rank1 MR12 =0x5d
722 10:02:41.471202 Write Rank1 MR1 =0x56
723 10:02:41.471262 Write Rank1 MR2 =0x1a
724 10:02:41.471322 Write Rank1 MR11 =0x0
725 10:02:41.471382 Write Rank1 MR22 =0x38
726 10:02:41.471452 Write Rank1 MR14 =0x5d
727 10:02:41.471513 Write Rank1 MR3 =0x30
728 10:02:41.471573 Write Rank1 MR13 =0x58
729 10:02:41.471633 Write Rank1 MR12 =0x5d
730 10:02:41.471693 Write Rank1 MR1 =0x56
731 10:02:41.471756 Write Rank1 MR2 =0x2d
732 10:02:41.471817 Write Rank1 MR11 =0x23
733 10:02:41.471884 Write Rank1 MR22 =0x34
734 10:02:41.471945 Write Rank1 MR14 =0x10
735 10:02:41.472009 Write Rank1 MR3 =0x30
736 10:02:41.472068 Write Rank1 MR13 =0xd8
737 10:02:41.472129 [ModeRegInit_LP4] CH1 RK0
738 10:02:41.472189 Write Rank0 MR13 =0x18
739 10:02:41.472252 Write Rank0 MR12 =0x5d
740 10:02:41.472316 Write Rank0 MR1 =0x56
741 10:02:41.472380 Write Rank0 MR2 =0x1a
742 10:02:41.472445 Write Rank0 MR11 =0x0
743 10:02:41.472538 Write Rank0 MR22 =0x38
744 10:02:41.472632 Write Rank0 MR14 =0x5d
745 10:02:41.472725 Write Rank0 MR3 =0x30
746 10:02:41.472818 Write Rank0 MR13 =0x58
747 10:02:41.472914 Write Rank0 MR12 =0x5d
748 10:02:41.473008 Write Rank0 MR1 =0x56
749 10:02:41.473101 Write Rank0 MR2 =0x2d
750 10:02:41.473193 Write Rank0 MR11 =0x23
751 10:02:41.473286 Write Rank0 MR22 =0x34
752 10:02:41.473379 Write Rank0 MR14 =0x10
753 10:02:41.473472 Write Rank0 MR3 =0x30
754 10:02:41.473564 Write Rank0 MR13 =0xd8
755 10:02:41.473657 [ModeRegInit_LP4] CH1 RK1
756 10:02:41.473750 Write Rank1 MR13 =0x18
757 10:02:41.473843 Write Rank1 MR12 =0x5d
758 10:02:41.473936 Write Rank1 MR1 =0x56
759 10:02:41.474029 Write Rank1 MR2 =0x1a
760 10:02:41.474121 Write Rank1 MR11 =0x0
761 10:02:41.474214 Write Rank1 MR22 =0x38
762 10:02:41.474307 Write Rank1 MR14 =0x5d
763 10:02:41.474399 Write Rank1 MR3 =0x30
764 10:02:41.474499 Write Rank1 MR13 =0x58
765 10:02:41.474594 Write Rank1 MR12 =0x5d
766 10:02:41.474671 Write Rank1 MR1 =0x56
767 10:02:41.474733 Write Rank1 MR2 =0x2d
768 10:02:41.474794 Write Rank1 MR11 =0x23
769 10:02:41.474890 Write Rank1 MR22 =0x34
770 10:02:41.474983 Write Rank1 MR14 =0x10
771 10:02:41.475076 Write Rank1 MR3 =0x30
772 10:02:41.475169 Write Rank1 MR13 =0xd8
773 10:02:41.475271 match AC timing 3
774 10:02:41.475368 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
775 10:02:41.475454 DramC Write-DBI off
776 10:02:41.475516 DramC Read-DBI off
777 10:02:41.475576 Write Rank0 MR13 =0x59
778 10:02:41.475637 ==
779 10:02:41.475697 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
780 10:02:41.475758 fsp= 1, odt_onoff= 1, Byte mode= 0
781 10:02:41.475819 ==
782 10:02:41.475914 === u2Vref_new: 0x56 --> 0x2d
783 10:02:41.476008 === u2Vref_new: 0x58 --> 0x38
784 10:02:41.476102 === u2Vref_new: 0x5a --> 0x39
785 10:02:41.476195 === u2Vref_new: 0x5c --> 0x3c
786 10:02:41.476289 === u2Vref_new: 0x5e --> 0x3d
787 10:02:41.476365 === u2Vref_new: 0x60 --> 0xa0
788 10:02:41.476427 [CA 0] Center 34 (6~63) winsize 58
789 10:02:41.476488 [CA 1] Center 36 (9~63) winsize 55
790 10:02:41.476559 [CA 2] Center 29 (0~58) winsize 59
791 10:02:41.476628 [CA 3] Center 24 (-3~52) winsize 56
792 10:02:41.476718 [CA 4] Center 25 (-3~53) winsize 57
793 10:02:41.476839 [CA 5] Center 29 (0~59) winsize 60
794 10:02:41.476992
795 10:02:41.477110 [CATrainingPosCal] consider 1 rank data
796 10:02:41.477207 u2DelayCellTimex100 = 735/100 ps
797 10:02:41.477302 CA0 delay=34 (6~63),Diff = 10 PI (13 cell)
798 10:02:41.477397 CA1 delay=36 (9~63),Diff = 12 PI (15 cell)
799 10:02:41.477492 CA2 delay=29 (0~58),Diff = 5 PI (6 cell)
800 10:02:41.477586 CA3 delay=24 (-3~52),Diff = 0 PI (0 cell)
801 10:02:41.477679 CA4 delay=25 (-3~53),Diff = 1 PI (1 cell)
802 10:02:41.477773 CA5 delay=29 (0~59),Diff = 5 PI (6 cell)
803 10:02:41.477865
804 10:02:41.477959 CA PerBit enable=1, Macro0, CA PI delay=24
805 10:02:41.478052 === u2Vref_new: 0x5e --> 0x3d
806 10:02:41.478145
807 10:02:41.478238 Vref(ca) range 1: 30
808 10:02:41.478331
809 10:02:41.478424 CS Dly= 9 (40-0-32)
810 10:02:41.478517 Write Rank0 MR13 =0xd8
811 10:02:41.478610 Write Rank0 MR13 =0xd8
812 10:02:41.478702 Write Rank0 MR12 =0x5e
813 10:02:41.478795 Write Rank1 MR13 =0x59
814 10:02:41.478887 ==
815 10:02:41.478981 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
816 10:02:41.479292 fsp= 1, odt_onoff= 1, Byte mode= 0
817 10:02:41.479393 ==
818 10:02:41.479471 === u2Vref_new: 0x56 --> 0x2d
819 10:02:41.479534 === u2Vref_new: 0x58 --> 0x38
820 10:02:41.479595 === u2Vref_new: 0x5a --> 0x39
821 10:02:41.479656 === u2Vref_new: 0x5c --> 0x3c
822 10:02:41.479717 === u2Vref_new: 0x5e --> 0x3d
823 10:02:41.479777 === u2Vref_new: 0x60 --> 0xa0
824 10:02:41.479838 [CA 0] Center 36 (9~63) winsize 55
825 10:02:41.479935 [CA 1] Center 35 (8~63) winsize 56
826 10:02:41.480022 [CA 2] Center 31 (3~60) winsize 58
827 10:02:41.480085 [CA 3] Center 26 (-2~54) winsize 57
828 10:02:41.480152 [CA 4] Center 26 (-2~54) winsize 57
829 10:02:41.480276 [CA 5] Center 31 (2~61) winsize 60
830 10:02:41.480426
831 10:02:41.480524 [CATrainingPosCal] consider 2 rank data
832 10:02:41.480589 u2DelayCellTimex100 = 735/100 ps
833 10:02:41.480652 CA0 delay=36 (9~63),Diff = 11 PI (14 cell)
834 10:02:41.480714 CA1 delay=36 (9~63),Diff = 11 PI (14 cell)
835 10:02:41.480775 CA2 delay=30 (3~58),Diff = 5 PI (6 cell)
836 10:02:41.480836 CA3 delay=25 (-2~52),Diff = 0 PI (0 cell)
837 10:02:41.480897 CA4 delay=25 (-2~53),Diff = 0 PI (0 cell)
838 10:02:41.480957 CA5 delay=30 (2~59),Diff = 5 PI (6 cell)
839 10:02:41.481018
840 10:02:41.481078 CA PerBit enable=1, Macro0, CA PI delay=25
841 10:02:41.481138 === u2Vref_new: 0x5e --> 0x3d
842 10:02:41.481199
843 10:02:41.481259 Vref(ca) range 1: 30
844 10:02:41.481319
845 10:02:41.481379 CS Dly= 7 (38-0-32)
846 10:02:41.481439 Write Rank1 MR13 =0xd8
847 10:02:41.481500 Write Rank1 MR13 =0xd8
848 10:02:41.481560 Write Rank1 MR12 =0x5e
849 10:02:41.481620 [RankSwap] Rank num 2, (Multi 1), Rank 0
850 10:02:41.481681 Write Rank0 MR2 =0xad
851 10:02:41.481741 [Write Leveling]
852 10:02:41.481802 delay byte0 byte1 byte2 byte3
853 10:02:41.481889
854 10:02:41.482049 10 0 0
855 10:02:41.482182 11 0 0
856 10:02:41.482290 12 0 0
857 10:02:41.482387 13 0 0
858 10:02:41.482483 14 0 0
859 10:02:41.482579 15 0 0
860 10:02:41.482678 16 0 0
861 10:02:41.482752 17 0 0
862 10:02:41.482816 18 0 0
863 10:02:41.482878 19 0 0
864 10:02:41.482938 20 0 0
865 10:02:41.482999 21 0 0
866 10:02:41.483061 22 0 0
867 10:02:41.483122 23 0 0
868 10:02:41.483183 24 0 ff
869 10:02:41.483243 25 0 ff
870 10:02:41.483304 26 0 ff
871 10:02:41.483379 27 0 ff
872 10:02:41.483470 28 0 ff
873 10:02:41.483535 29 0 ff
874 10:02:41.483596 30 0 ff
875 10:02:41.483785 31 0 ff
876 10:02:41.483907 32 ff ff
877 10:02:41.483980 33 ff ff
878 10:02:41.484050 34 ff ff
879 10:02:41.484144 35 ff ff
880 10:02:41.484252 36 ff ff
881 10:02:41.484406 37 ff ff
882 10:02:41.484572 38 ff ff
883 10:02:41.484696 pass bytecount = 0xff (0xff: all bytes pass)
884 10:02:41.484802
885 10:02:41.484978 DQS0 dly: 32
886 10:02:41.485117 DQS1 dly: 24
887 10:02:41.485230 Write Rank0 MR2 =0x2d
888 10:02:41.485339 [RankSwap] Rank num 2, (Multi 1), Rank 0
889 10:02:41.485440 Write Rank0 MR1 =0xd6
890 10:02:41.485536 [Gating]
891 10:02:41.485631 ==
892 10:02:41.485727 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
893 10:02:41.485822 fsp= 1, odt_onoff= 1, Byte mode= 0
894 10:02:41.485928 ==
895 10:02:41.486035 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
896 10:02:41.486151 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
897 10:02:41.486252 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
898 10:02:41.486350 3 1 12 |2c2c 3534 |(0 0)(11 11) |(1 0)(0 1)| 0
899 10:02:41.486454 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
900 10:02:41.486651 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
901 10:02:41.486770 3 1 24 |2c2b 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
902 10:02:41.486886 3 1 28 |201 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
903 10:02:41.487071 3 2 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
904 10:02:41.487191 3 2 4 |3534 201 |(11 11)(11 11) |(0 0)(1 1)| 0
905 10:02:41.487344 3 2 8 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
906 10:02:41.487516 3 2 12 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
907 10:02:41.487661 3 2 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
908 10:02:41.487826 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
909 10:02:41.487942 3 2 24 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
910 10:02:41.488055 3 2 28 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
911 10:02:41.488232 3 3 0 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
912 10:02:41.488358 3 3 4 |3534 201 |(11 11)(11 11) |(0 0)(1 1)| 0
913 10:02:41.488459 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
914 10:02:41.488558 [Byte 1] Lead/lag falling Transition (3, 3, 8)
915 10:02:41.488654 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
916 10:02:41.488752 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
917 10:02:41.488851 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
918 10:02:41.488948 3 3 24 |201 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
919 10:02:41.489046 3 3 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
920 10:02:41.489150 3 4 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
921 10:02:41.489335 3 4 4 |3d3d 2120 |(11 11)(11 11) |(1 1)(1 1)| 0
922 10:02:41.489459 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
923 10:02:41.489563 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
924 10:02:41.489664 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
925 10:02:41.489761 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
926 10:02:41.489893 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
927 10:02:41.490046 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 10:02:41.490162 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 10:02:41.490262 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 10:02:41.490363 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 10:02:41.490460 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 10:02:41.490557 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 10:02:41.490652 [Byte 0] Lead/lag falling Transition (3, 5, 16)
934 10:02:41.490747 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
935 10:02:41.490843 [Byte 0] Lead/lag Transition tap number (2)
936 10:02:41.490937 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
937 10:02:41.491033 [Byte 1] Lead/lag falling Transition (3, 5, 24)
938 10:02:41.491126 3 5 28 |4646 3d3d |(0 0)(11 11) |(0 0)(1 0)| 0
939 10:02:41.491231 [Byte 0]First pass (3, 5, 28)
940 10:02:41.491536 3 6 0 |4646 909 |(0 0)(11 11) |(0 0)(1 0)| 0
941 10:02:41.491646 [Byte 1] Lead/lag Transition tap number (3)
942 10:02:41.491806 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
943 10:02:41.491957 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
944 10:02:41.492045 [Byte 1]First pass (3, 6, 8)
945 10:02:41.492110 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
946 10:02:41.492174 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
947 10:02:41.492236 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
948 10:02:41.492302 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
949 10:02:41.492364 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 10:02:41.492426 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 10:02:41.492488 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 10:02:41.492550 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
953 10:02:41.492611 All bytes gating window > 1UI, Early break!
954 10:02:41.492671
955 10:02:41.492745 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 20)
956 10:02:41.492853
957 10:02:41.492958 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 30)
958 10:02:41.493125
959 10:02:41.493226
960 10:02:41.493294
961 10:02:41.493360 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 20)
962 10:02:41.493467
963 10:02:41.493562 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
964 10:02:41.493655
965 10:02:41.493747
966 10:02:41.493849 Write Rank0 MR1 =0x56
967 10:02:41.493945
968 10:02:41.494043 best RODT dly(2T, 0.5T) = (2, 2)
969 10:02:41.494137
970 10:02:41.494230 best RODT dly(2T, 0.5T) = (2, 2)
971 10:02:41.494322 ==
972 10:02:41.494416 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
973 10:02:41.494510 fsp= 1, odt_onoff= 1, Byte mode= 0
974 10:02:41.494603 ==
975 10:02:41.494696 Start DQ dly to find pass range UseTestEngine =0
976 10:02:41.494789 x-axis: bit #, y-axis: DQ dly (-127~63)
977 10:02:41.494882 RX Vref Scan = 0
978 10:02:41.495054 -26, [0] xxxxxxxx xxxxxxxx [MSB]
979 10:02:41.495185 -25, [0] xxxxxxxx xxxxxxxx [MSB]
980 10:02:41.495291 -24, [0] xxxxxxxx xxxxxxxx [MSB]
981 10:02:41.495392 -23, [0] xxxxxxxx xxxxxxxx [MSB]
982 10:02:41.495473 -22, [0] xxxxxxxx xxxxxxxx [MSB]
983 10:02:41.495545 -21, [0] xxxxxxxx xxxxxxxx [MSB]
984 10:02:41.495616 -20, [0] xxxxxxxx xxxxxxxx [MSB]
985 10:02:41.495687 -19, [0] xxxxxxxx xxxxxxxx [MSB]
986 10:02:41.495778 -18, [0] xxxxxxxx xxxxxxxx [MSB]
987 10:02:41.495893 -17, [0] xxxxxxxx xxxxxxxx [MSB]
988 10:02:41.496000 -16, [0] xxxxxxxx xxxxxxxx [MSB]
989 10:02:41.496159 -15, [0] xxxxxxxx xxxxxxxx [MSB]
990 10:02:41.496291 -14, [0] xxxxxxxx xxxxxxxx [MSB]
991 10:02:41.496408 -13, [0] xxxxxxxx xxxxxxxx [MSB]
992 10:02:41.496518 -12, [0] xxxxxxxx xxxxxxxx [MSB]
993 10:02:41.496707 -11, [0] xxxxxxxx xxxxxxxx [MSB]
994 10:02:41.496834 -10, [0] xxxxxxxx xxxxxxxx [MSB]
995 10:02:41.496939 -9, [0] xxxxxxxx xxxxxxxx [MSB]
996 10:02:41.497049 -8, [0] xxxxxxxx xxxxxxxx [MSB]
997 10:02:41.497151 -7, [0] xxxxxxxx xxxxxxxx [MSB]
998 10:02:41.497247 -6, [0] xxxxxxxx xxxxxxxx [MSB]
999 10:02:41.497343 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1000 10:02:41.497442 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1001 10:02:41.497542 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1002 10:02:41.497647 -2, [0] xxxoxxxx oxxxxxxx [MSB]
1003 10:02:41.497752 -1, [0] xxxoxxxx ooxoxxxx [MSB]
1004 10:02:41.497850 0, [0] xxxoxoxx ooxoxxxx [MSB]
1005 10:02:41.497946 1, [0] xxxoxoox ooxoooxx [MSB]
1006 10:02:41.498041 2, [0] xxxoxoox ooxoooxx [MSB]
1007 10:02:41.498137 3, [0] xxxoxoox ooxoooox [MSB]
1008 10:02:41.498315 4, [0] xooooooo ooxooooo [MSB]
1009 10:02:41.498437 5, [0] xooooooo ooxooooo [MSB]
1010 10:02:41.498540 6, [0] oooooooo ooxooooo [MSB]
1011 10:02:41.498643 7, [0] oooooooo ooxooooo [MSB]
1012 10:02:41.498740 32, [0] oooxoooo xooooooo [MSB]
1013 10:02:41.498843 33, [0] oooxoooo xooooooo [MSB]
1014 10:02:41.498943 34, [0] oooxoooo xooooooo [MSB]
1015 10:02:41.499039 35, [0] oooxoooo xooooooo [MSB]
1016 10:02:41.499135 36, [0] oooxoxox xooxoooo [MSB]
1017 10:02:41.499230 37, [0] oooxoxxx xxoxoooo [MSB]
1018 10:02:41.499329 38, [0] oooxoxxx xxoxxoxo [MSB]
1019 10:02:41.499428 39, [0] oooxxxxx xxoxxxxo [MSB]
1020 10:02:41.499493 40, [0] xooxxxxx xxoxxxxo [MSB]
1021 10:02:41.499555 41, [0] xxxxxxxx xxoxxxxo [MSB]
1022 10:02:41.499617 42, [0] xxxxxxxx xxoxxxxx [MSB]
1023 10:02:41.499678 43, [0] xxxxxxxx xxoxxxxx [MSB]
1024 10:02:41.499740 44, [0] xxxxxxxx xxxxxxxx [MSB]
1025 10:02:41.499809 iDelay=44, Bit 0, Center 22 (6 ~ 39) 34
1026 10:02:41.499875 iDelay=44, Bit 1, Center 22 (4 ~ 40) 37
1027 10:02:41.499937 iDelay=44, Bit 2, Center 22 (4 ~ 40) 37
1028 10:02:41.499997 iDelay=44, Bit 3, Center 14 (-2 ~ 31) 34
1029 10:02:41.500058 iDelay=44, Bit 4, Center 21 (4 ~ 38) 35
1030 10:02:41.500117 iDelay=44, Bit 5, Center 17 (0 ~ 35) 36
1031 10:02:41.500177 iDelay=44, Bit 6, Center 18 (1 ~ 36) 36
1032 10:02:41.500237 iDelay=44, Bit 7, Center 19 (4 ~ 35) 32
1033 10:02:41.500297 iDelay=44, Bit 8, Center 14 (-2 ~ 31) 34
1034 10:02:41.500356 iDelay=44, Bit 9, Center 17 (-1 ~ 36) 38
1035 10:02:41.500416 iDelay=44, Bit 10, Center 25 (8 ~ 43) 36
1036 10:02:41.500475 iDelay=44, Bit 11, Center 17 (-1 ~ 35) 37
1037 10:02:41.500534 iDelay=44, Bit 12, Center 19 (1 ~ 37) 37
1038 10:02:41.500604 iDelay=44, Bit 13, Center 19 (1 ~ 38) 38
1039 10:02:41.500664 iDelay=44, Bit 14, Center 20 (3 ~ 37) 35
1040 10:02:41.500723 iDelay=44, Bit 15, Center 22 (4 ~ 41) 38
1041 10:02:41.500782 ==
1042 10:02:41.500842 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1043 10:02:41.500901 fsp= 1, odt_onoff= 1, Byte mode= 0
1044 10:02:41.500961 ==
1045 10:02:41.501020 DQS Delay:
1046 10:02:41.501079 DQS0 = 0, DQS1 = 0
1047 10:02:41.501138 DQM Delay:
1048 10:02:41.501197 DQM0 = 19, DQM1 = 19
1049 10:02:41.501257 DQ Delay:
1050 10:02:41.501316 DQ0 =22, DQ1 =22, DQ2 =22, DQ3 =14
1051 10:02:41.501375 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =19
1052 10:02:41.501435 DQ8 =14, DQ9 =17, DQ10 =25, DQ11 =17
1053 10:02:41.501494 DQ12 =19, DQ13 =19, DQ14 =20, DQ15 =22
1054 10:02:41.501554
1055 10:02:41.501613
1056 10:02:41.501672 DramC Write-DBI off
1057 10:02:41.501732 ==
1058 10:02:41.501791 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1059 10:02:41.501851 fsp= 1, odt_onoff= 1, Byte mode= 0
1060 10:02:41.501910 ==
1061 10:02:41.501970 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1062 10:02:41.502029
1063 10:02:41.502088 Begin, DQ Scan Range 920~1176
1064 10:02:41.502147
1065 10:02:41.502206
1066 10:02:41.502265 TX Vref Scan disable
1067 10:02:41.502324 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1068 10:02:41.502386 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1069 10:02:41.502446 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1070 10:02:41.502507 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1071 10:02:41.502763 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1072 10:02:41.502831 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1073 10:02:41.502892 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1074 10:02:41.502954 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1075 10:02:41.503015 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1076 10:02:41.503076 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1077 10:02:41.503136 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1078 10:02:41.503196 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1079 10:02:41.503257 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1080 10:02:41.503317 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1081 10:02:41.503377 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1082 10:02:41.503452 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1083 10:02:41.503514 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1084 10:02:41.503575 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1085 10:02:41.503635 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1086 10:02:41.503699 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1087 10:02:41.503759 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1088 10:02:41.503819 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1089 10:02:41.503879 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1090 10:02:41.503940 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1091 10:02:41.504000 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1092 10:02:41.504061 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1093 10:02:41.504121 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1094 10:02:41.504181 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1095 10:02:41.504242 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1096 10:02:41.504302 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1097 10:02:41.504363 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1098 10:02:41.504425 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1099 10:02:41.504487 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1100 10:02:41.504547 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1101 10:02:41.504607 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1102 10:02:41.504668 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1103 10:02:41.504728 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1104 10:02:41.504788 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1105 10:02:41.504848 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1106 10:02:41.504909 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1107 10:02:41.504969 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1108 10:02:41.505029 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1109 10:02:41.505089 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1110 10:02:41.505149 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1111 10:02:41.505209 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1112 10:02:41.505270 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1113 10:02:41.505330 966 |3 6 6|[0] xxxxxxxx oxxxxxxx [MSB]
1114 10:02:41.505390 967 |3 6 7|[0] xxxxxxxx oxxoxxxx [MSB]
1115 10:02:41.505450 968 |3 6 8|[0] xxxxxxxx ooxoooox [MSB]
1116 10:02:41.505510 969 |3 6 9|[0] xxxxxxxx ooxoooox [MSB]
1117 10:02:41.505570 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1118 10:02:41.505631 971 |3 6 11|[0] xxxxxxxx ooxooooo [MSB]
1119 10:02:41.505691 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
1120 10:02:41.505750 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
1121 10:02:41.505810 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
1122 10:02:41.505870 975 |3 6 15|[0] xxxoxoox oooooooo [MSB]
1123 10:02:41.505931 976 |3 6 16|[0] ooooooox oooooooo [MSB]
1124 10:02:41.505991 985 |3 6 25|[0] oooooooo xooooooo [MSB]
1125 10:02:41.506051 986 |3 6 26|[0] oooooooo xooooooo [MSB]
1126 10:02:41.506111 987 |3 6 27|[0] oooooooo xxxxxxxx [MSB]
1127 10:02:41.506172 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1128 10:02:41.506231 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1129 10:02:41.506291 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1130 10:02:41.506351 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1131 10:02:41.506411 992 |3 6 32|[0] oooxoooo xxxxxxxx [MSB]
1132 10:02:41.506472 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
1133 10:02:41.506532 994 |3 6 34|[0] oooxoxoo xxxxxxxx [MSB]
1134 10:02:41.506592 995 |3 6 35|[0] oooxoxxo xxxxxxxx [MSB]
1135 10:02:41.506653 996 |3 6 36|[0] oooxxxxx xxxxxxxx [MSB]
1136 10:02:41.506712 997 |3 6 37|[0] oxoxxxxx xxxxxxxx [MSB]
1137 10:02:41.506772 998 |3 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
1138 10:02:41.506832 Byte0, DQ PI dly=984, DQM PI dly= 984
1139 10:02:41.506892 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
1140 10:02:41.506951
1141 10:02:41.507011 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
1142 10:02:41.507071
1143 10:02:41.507130 Byte1, DQ PI dly=977, DQM PI dly= 977
1144 10:02:41.507189 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
1145 10:02:41.507249
1146 10:02:41.507309 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
1147 10:02:41.507370
1148 10:02:41.507438 ==
1149 10:02:41.507499 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1150 10:02:41.507560 fsp= 1, odt_onoff= 1, Byte mode= 0
1151 10:02:41.507620 ==
1152 10:02:41.507679 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1153 10:02:41.507739
1154 10:02:41.507799 Begin, DQ Scan Range 953~1017
1155 10:02:41.507859 Write Rank0 MR14 =0x0
1156 10:02:41.507919
1157 10:02:41.507978 CH=0, VrefRange= 0, VrefLevel = 0
1158 10:02:41.508038 TX Bit0 (978~993) 16 985, Bit8 (967~978) 12 972,
1159 10:02:41.508098 TX Bit1 (977~992) 16 984, Bit9 (969~984) 16 976,
1160 10:02:41.508158 TX Bit2 (979~993) 15 986, Bit10 (975~987) 13 981,
1161 10:02:41.508217 TX Bit3 (975~985) 11 980, Bit11 (968~982) 15 975,
1162 10:02:41.508278 TX Bit4 (978~991) 14 984, Bit12 (971~983) 13 977,
1163 10:02:41.508337 TX Bit5 (976~988) 13 982, Bit13 (969~984) 16 976,
1164 10:02:41.508397 TX Bit6 (977~990) 14 983, Bit14 (969~984) 16 976,
1165 10:02:41.508456 TX Bit7 (978~991) 14 984, Bit15 (974~985) 12 979,
1166 10:02:41.508516
1167 10:02:41.508575 Write Rank0 MR14 =0x2
1168 10:02:41.508635
1169 10:02:41.508694 CH=0, VrefRange= 0, VrefLevel = 2
1170 10:02:41.508753 TX Bit0 (978~993) 16 985, Bit8 (967~979) 13 973,
1171 10:02:41.508813 TX Bit1 (977~992) 16 984, Bit9 (969~984) 16 976,
1172 10:02:41.508874 TX Bit2 (978~993) 16 985, Bit10 (975~988) 14 981,
1173 10:02:41.508933 TX Bit3 (975~986) 12 980, Bit11 (968~982) 15 975,
1174 10:02:41.508993 TX Bit4 (977~991) 15 984, Bit12 (969~983) 15 976,
1175 10:02:41.509052 TX Bit5 (976~991) 16 983, Bit13 (969~984) 16 976,
1176 10:02:41.509111 TX Bit6 (976~991) 16 983, Bit14 (969~985) 17 977,
1177 10:02:41.509374 TX Bit7 (978~991) 14 984, Bit15 (974~987) 14 980,
1178 10:02:41.509444
1179 10:02:41.509505 Write Rank0 MR14 =0x4
1180 10:02:41.509565
1181 10:02:41.509624 CH=0, VrefRange= 0, VrefLevel = 4
1182 10:02:41.509685 TX Bit0 (978~993) 16 985, Bit8 (967~981) 15 974,
1183 10:02:41.509746 TX Bit1 (977~993) 17 985, Bit9 (969~984) 16 976,
1184 10:02:41.509807 TX Bit2 (978~993) 16 985, Bit10 (974~989) 16 981,
1185 10:02:41.509867 TX Bit3 (974~987) 14 980, Bit11 (968~983) 16 975,
1186 10:02:41.509928 TX Bit4 (977~992) 16 984, Bit12 (970~984) 15 977,
1187 10:02:41.509988 TX Bit5 (975~991) 17 983, Bit13 (969~984) 16 976,
1188 10:02:41.510048 TX Bit6 (976~991) 16 983, Bit14 (969~985) 17 977,
1189 10:02:41.510108 TX Bit7 (977~992) 16 984, Bit15 (973~988) 16 980,
1190 10:02:41.510168
1191 10:02:41.510228 Write Rank0 MR14 =0x6
1192 10:02:41.510287
1193 10:02:41.510350 CH=0, VrefRange= 0, VrefLevel = 6
1194 10:02:41.510410 TX Bit0 (978~995) 18 986, Bit8 (967~982) 16 974,
1195 10:02:41.510470 TX Bit1 (977~993) 17 985, Bit9 (969~985) 17 977,
1196 10:02:41.510530 TX Bit2 (978~994) 17 986, Bit10 (974~990) 17 982,
1197 10:02:41.510590 TX Bit3 (973~988) 16 980, Bit11 (968~983) 16 975,
1198 10:02:41.510649 TX Bit4 (977~992) 16 984, Bit12 (970~985) 16 977,
1199 10:02:41.510709 TX Bit5 (975~991) 17 983, Bit13 (969~985) 17 977,
1200 10:02:41.510768 TX Bit6 (976~992) 17 984, Bit14 (968~986) 19 977,
1201 10:02:41.510828 TX Bit7 (977~992) 16 984, Bit15 (974~989) 16 981,
1202 10:02:41.510888
1203 10:02:41.510947 Write Rank0 MR14 =0x8
1204 10:02:41.511006
1205 10:02:41.511065 CH=0, VrefRange= 0, VrefLevel = 8
1206 10:02:41.511125 TX Bit0 (977~995) 19 986, Bit8 (967~982) 16 974,
1207 10:02:41.511185 TX Bit1 (977~994) 18 985, Bit9 (968~985) 18 976,
1208 10:02:41.511244 TX Bit2 (977~995) 19 986, Bit10 (974~990) 17 982,
1209 10:02:41.511304 TX Bit3 (973~989) 17 981, Bit11 (967~983) 17 975,
1210 10:02:41.511364 TX Bit4 (977~993) 17 985, Bit12 (969~985) 17 977,
1211 10:02:41.511452 TX Bit5 (975~992) 18 983, Bit13 (969~985) 17 977,
1212 10:02:41.511517 TX Bit6 (976~992) 17 984, Bit14 (968~987) 20 977,
1213 10:02:41.511577 TX Bit7 (977~993) 17 985, Bit15 (973~990) 18 981,
1214 10:02:41.511637
1215 10:02:41.511697 Write Rank0 MR14 =0xa
1216 10:02:41.511757
1217 10:02:41.511816 CH=0, VrefRange= 0, VrefLevel = 10
1218 10:02:41.511876 TX Bit0 (977~996) 20 986, Bit8 (966~983) 18 974,
1219 10:02:41.511936 TX Bit1 (977~994) 18 985, Bit9 (968~985) 18 976,
1220 10:02:41.511996 TX Bit2 (977~995) 19 986, Bit10 (973~990) 18 981,
1221 10:02:41.512056 TX Bit3 (972~990) 19 981, Bit11 (967~984) 18 975,
1222 10:02:41.512116 TX Bit4 (977~993) 17 985, Bit12 (969~985) 17 977,
1223 10:02:41.512176 TX Bit5 (975~992) 18 983, Bit13 (969~986) 18 977,
1224 10:02:41.512236 TX Bit6 (976~993) 18 984, Bit14 (968~987) 20 977,
1225 10:02:41.512296 TX Bit7 (977~993) 17 985, Bit15 (972~990) 19 981,
1226 10:02:41.512356
1227 10:02:41.512416 Write Rank0 MR14 =0xc
1228 10:02:41.512475
1229 10:02:41.512534 CH=0, VrefRange= 0, VrefLevel = 12
1230 10:02:41.512593 TX Bit0 (977~997) 21 987, Bit8 (966~983) 18 974,
1231 10:02:41.512653 TX Bit1 (976~995) 20 985, Bit9 (968~986) 19 977,
1232 10:02:41.512713 TX Bit2 (977~996) 20 986, Bit10 (973~991) 19 982,
1233 10:02:41.512773 TX Bit3 (972~991) 20 981, Bit11 (967~985) 19 976,
1234 10:02:41.512832 TX Bit4 (976~994) 19 985, Bit12 (969~986) 18 977,
1235 10:02:41.512892 TX Bit5 (974~993) 20 983, Bit13 (968~986) 19 977,
1236 10:02:41.512951 TX Bit6 (975~993) 19 984, Bit14 (968~988) 21 978,
1237 10:02:41.513011 TX Bit7 (977~994) 18 985, Bit15 (972~990) 19 981,
1238 10:02:41.513070
1239 10:02:41.513129 Write Rank0 MR14 =0xe
1240 10:02:41.513189
1241 10:02:41.513248 CH=0, VrefRange= 0, VrefLevel = 14
1242 10:02:41.513308 TX Bit0 (977~997) 21 987, Bit8 (966~984) 19 975,
1243 10:02:41.513368 TX Bit1 (976~996) 21 986, Bit9 (968~986) 19 977,
1244 10:02:41.513427 TX Bit2 (977~997) 21 987, Bit10 (972~991) 20 981,
1245 10:02:41.513487 TX Bit3 (971~991) 21 981, Bit11 (967~985) 19 976,
1246 10:02:41.513547 TX Bit4 (976~995) 20 985, Bit12 (969~987) 19 978,
1247 10:02:41.513606 TX Bit5 (974~993) 20 983, Bit13 (968~987) 20 977,
1248 10:02:41.513666 TX Bit6 (975~993) 19 984, Bit14 (968~989) 22 978,
1249 10:02:41.513726 TX Bit7 (976~995) 20 985, Bit15 (972~991) 20 981,
1250 10:02:41.513785
1251 10:02:41.513844 Write Rank0 MR14 =0x10
1252 10:02:41.513904
1253 10:02:41.513964 CH=0, VrefRange= 0, VrefLevel = 16
1254 10:02:41.514024 TX Bit0 (977~998) 22 987, Bit8 (965~984) 20 974,
1255 10:02:41.514084 TX Bit1 (976~996) 21 986, Bit9 (967~988) 22 977,
1256 10:02:41.514144 TX Bit2 (977~998) 22 987, Bit10 (972~992) 21 982,
1257 10:02:41.514205 TX Bit3 (971~991) 21 981, Bit11 (966~985) 20 975,
1258 10:02:41.514264 TX Bit4 (976~995) 20 985, Bit12 (968~988) 21 978,
1259 10:02:41.514324 TX Bit5 (974~993) 20 983, Bit13 (968~988) 21 978,
1260 10:02:41.514384 TX Bit6 (975~994) 20 984, Bit14 (968~989) 22 978,
1261 10:02:41.514444 TX Bit7 (976~995) 20 985, Bit15 (971~991) 21 981,
1262 10:02:41.514504
1263 10:02:41.514563 Write Rank0 MR14 =0x12
1264 10:02:41.514623
1265 10:02:41.514683 CH=0, VrefRange= 0, VrefLevel = 18
1266 10:02:41.514743 TX Bit0 (977~998) 22 987, Bit8 (965~984) 20 974,
1267 10:02:41.514802 TX Bit1 (976~997) 22 986, Bit9 (966~988) 23 977,
1268 10:02:41.514862 TX Bit2 (976~998) 23 987, Bit10 (971~992) 22 981,
1269 10:02:41.514921 TX Bit3 (971~992) 22 981, Bit11 (966~986) 21 976,
1270 10:02:41.514981 TX Bit4 (976~996) 21 986, Bit12 (968~989) 22 978,
1271 10:02:41.515041 TX Bit5 (973~994) 22 983, Bit13 (968~989) 22 978,
1272 10:02:41.515101 TX Bit6 (974~994) 21 984, Bit14 (967~990) 24 978,
1273 10:02:41.515161 TX Bit7 (976~996) 21 986, Bit15 (971~991) 21 981,
1274 10:02:41.515221
1275 10:02:41.515281 Write Rank0 MR14 =0x14
1276 10:02:41.515340
1277 10:02:41.515400 CH=0, VrefRange= 0, VrefLevel = 20
1278 10:02:41.515469 TX Bit0 (977~999) 23 988, Bit8 (965~985) 21 975,
1279 10:02:41.515723 TX Bit1 (976~998) 23 987, Bit9 (967~989) 23 978,
1280 10:02:41.515790 TX Bit2 (977~998) 22 987, Bit10 (971~992) 22 981,
1281 10:02:41.515852 TX Bit3 (970~992) 23 981, Bit11 (966~987) 22 976,
1282 10:02:41.515913 TX Bit4 (976~997) 22 986, Bit12 (968~989) 22 978,
1283 10:02:41.515973 TX Bit5 (973~994) 22 983, Bit13 (968~989) 22 978,
1284 10:02:41.516033 TX Bit6 (974~995) 22 984, Bit14 (967~990) 24 978,
1285 10:02:41.516094 TX Bit7 (976~996) 21 986, Bit15 (971~992) 22 981,
1286 10:02:41.516153
1287 10:02:41.516213 Write Rank0 MR14 =0x16
1288 10:02:41.516273
1289 10:02:41.516332 CH=0, VrefRange= 0, VrefLevel = 22
1290 10:02:41.516392 TX Bit0 (976~999) 24 987, Bit8 (965~986) 22 975,
1291 10:02:41.516452 TX Bit1 (976~998) 23 987, Bit9 (967~989) 23 978,
1292 10:02:41.516512 TX Bit2 (976~999) 24 987, Bit10 (970~993) 24 981,
1293 10:02:41.516572 TX Bit3 (970~992) 23 981, Bit11 (966~988) 23 977,
1294 10:02:41.516632 TX Bit4 (975~998) 24 986, Bit12 (968~990) 23 979,
1295 10:02:41.516692 TX Bit5 (972~995) 24 983, Bit13 (967~990) 24 978,
1296 10:02:41.516752 TX Bit6 (974~996) 23 985, Bit14 (967~990) 24 978,
1297 10:02:41.516812 TX Bit7 (976~997) 22 986, Bit15 (970~992) 23 981,
1298 10:02:41.516871
1299 10:02:41.516930 Write Rank0 MR14 =0x18
1300 10:02:41.516990
1301 10:02:41.517050 CH=0, VrefRange= 0, VrefLevel = 24
1302 10:02:41.517110 TX Bit0 (976~999) 24 987, Bit8 (964~986) 23 975,
1303 10:02:41.517170 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1304 10:02:41.517230 TX Bit2 (976~999) 24 987, Bit10 (970~993) 24 981,
1305 10:02:41.517290 TX Bit3 (970~993) 24 981, Bit11 (966~989) 24 977,
1306 10:02:41.517350 TX Bit4 (975~998) 24 986, Bit12 (968~990) 23 979,
1307 10:02:41.517409 TX Bit5 (972~995) 24 983, Bit13 (967~990) 24 978,
1308 10:02:41.517469 TX Bit6 (974~996) 23 985, Bit14 (967~990) 24 978,
1309 10:02:41.517528 TX Bit7 (976~998) 23 987, Bit15 (970~992) 23 981,
1310 10:02:41.517588
1311 10:02:41.517647 Write Rank0 MR14 =0x1a
1312 10:02:41.517706
1313 10:02:41.517766 CH=0, VrefRange= 0, VrefLevel = 26
1314 10:02:41.517826 TX Bit0 (976~999) 24 987, Bit8 (964~987) 24 975,
1315 10:02:41.517886 TX Bit1 (975~999) 25 987, Bit9 (966~990) 25 978,
1316 10:02:41.517946 TX Bit2 (976~999) 24 987, Bit10 (969~993) 25 981,
1317 10:02:41.518006 TX Bit3 (969~993) 25 981, Bit11 (965~989) 25 977,
1318 10:02:41.518066 TX Bit4 (975~999) 25 987, Bit12 (968~990) 23 979,
1319 10:02:41.518126 TX Bit5 (972~995) 24 983, Bit13 (967~990) 24 978,
1320 10:02:41.518186 TX Bit6 (973~996) 24 984, Bit14 (967~991) 25 979,
1321 10:02:41.518246 TX Bit7 (976~999) 24 987, Bit15 (969~993) 25 981,
1322 10:02:41.518306
1323 10:02:41.518366 Write Rank0 MR14 =0x1c
1324 10:02:41.518425
1325 10:02:41.518484 CH=0, VrefRange= 0, VrefLevel = 28
1326 10:02:41.518544 TX Bit0 (976~1000) 25 988, Bit8 (963~987) 25 975,
1327 10:02:41.518603 TX Bit1 (975~999) 25 987, Bit9 (967~989) 23 978,
1328 10:02:41.518663 TX Bit2 (976~1000) 25 988, Bit10 (969~994) 26 981,
1329 10:02:41.518722 TX Bit3 (969~993) 25 981, Bit11 (965~989) 25 977,
1330 10:02:41.518782 TX Bit4 (975~999) 25 987, Bit12 (967~990) 24 978,
1331 10:02:41.518842 TX Bit5 (971~995) 25 983, Bit13 (967~990) 24 978,
1332 10:02:41.518901 TX Bit6 (973~998) 26 985, Bit14 (967~991) 25 979,
1333 10:02:41.518961 TX Bit7 (975~999) 25 987, Bit15 (969~993) 25 981,
1334 10:02:41.519020
1335 10:02:41.519080 Write Rank0 MR14 =0x1e
1336 10:02:41.519139
1337 10:02:41.519198 CH=0, VrefRange= 0, VrefLevel = 30
1338 10:02:41.519258 TX Bit0 (976~1000) 25 988, Bit8 (963~987) 25 975,
1339 10:02:41.519317 TX Bit1 (975~999) 25 987, Bit9 (967~989) 23 978,
1340 10:02:41.519377 TX Bit2 (976~1000) 25 988, Bit10 (969~994) 26 981,
1341 10:02:41.519450 TX Bit3 (969~993) 25 981, Bit11 (965~989) 25 977,
1342 10:02:41.519511 TX Bit4 (975~999) 25 987, Bit12 (967~990) 24 978,
1343 10:02:41.519571 TX Bit5 (971~995) 25 983, Bit13 (967~990) 24 978,
1344 10:02:41.519631 TX Bit6 (973~998) 26 985, Bit14 (967~991) 25 979,
1345 10:02:41.519691 TX Bit7 (975~999) 25 987, Bit15 (969~993) 25 981,
1346 10:02:41.519751
1347 10:02:41.519810 Write Rank0 MR14 =0x20
1348 10:02:41.519870
1349 10:02:41.519929 CH=0, VrefRange= 0, VrefLevel = 32
1350 10:02:41.519989 TX Bit0 (976~1000) 25 988, Bit8 (963~987) 25 975,
1351 10:02:41.520049 TX Bit1 (975~999) 25 987, Bit9 (967~989) 23 978,
1352 10:02:41.520109 TX Bit2 (976~1000) 25 988, Bit10 (969~994) 26 981,
1353 10:02:41.520170 TX Bit3 (969~993) 25 981, Bit11 (965~989) 25 977,
1354 10:02:41.520230 TX Bit4 (975~999) 25 987, Bit12 (967~990) 24 978,
1355 10:02:41.520290 TX Bit5 (971~995) 25 983, Bit13 (967~990) 24 978,
1356 10:02:41.520350 TX Bit6 (973~998) 26 985, Bit14 (967~991) 25 979,
1357 10:02:41.520409 TX Bit7 (975~999) 25 987, Bit15 (969~993) 25 981,
1358 10:02:41.520469
1359 10:02:41.520529 Write Rank0 MR14 =0x22
1360 10:02:41.520588
1361 10:02:41.520647 CH=0, VrefRange= 0, VrefLevel = 34
1362 10:02:41.520707 TX Bit0 (976~1000) 25 988, Bit8 (963~987) 25 975,
1363 10:02:41.520767 TX Bit1 (975~999) 25 987, Bit9 (967~989) 23 978,
1364 10:02:41.520826 TX Bit2 (976~1000) 25 988, Bit10 (969~994) 26 981,
1365 10:02:41.520885 TX Bit3 (969~993) 25 981, Bit11 (965~989) 25 977,
1366 10:02:41.520945 TX Bit4 (975~999) 25 987, Bit12 (967~990) 24 978,
1367 10:02:41.521004 TX Bit5 (971~995) 25 983, Bit13 (967~990) 24 978,
1368 10:02:41.521063 TX Bit6 (973~998) 26 985, Bit14 (967~991) 25 979,
1369 10:02:41.521122 TX Bit7 (975~999) 25 987, Bit15 (969~993) 25 981,
1370 10:02:41.521181
1371 10:02:41.521239 Write Rank0 MR14 =0x24
1372 10:02:41.521298
1373 10:02:41.521357 CH=0, VrefRange= 0, VrefLevel = 36
1374 10:02:41.521416 TX Bit0 (976~1000) 25 988, Bit8 (963~987) 25 975,
1375 10:02:41.521475 TX Bit1 (975~999) 25 987, Bit9 (967~989) 23 978,
1376 10:02:41.521535 TX Bit2 (976~1000) 25 988, Bit10 (969~994) 26 981,
1377 10:02:41.521594 TX Bit3 (969~993) 25 981, Bit11 (965~989) 25 977,
1378 10:02:41.521654 TX Bit4 (975~999) 25 987, Bit12 (967~990) 24 978,
1379 10:02:41.521910 TX Bit5 (971~995) 25 983, Bit13 (967~990) 24 978,
1380 10:02:41.521978 TX Bit6 (973~998) 26 985, Bit14 (967~991) 25 979,
1381 10:02:41.522039 TX Bit7 (975~999) 25 987, Bit15 (969~993) 25 981,
1382 10:02:41.522099
1383 10:02:41.522159
1384 10:02:41.522218 TX Vref found, early break! 370< 378
1385 10:02:41.522279 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
1386 10:02:41.522338 u1DelayCellOfst[0]=9 cells (7 PI)
1387 10:02:41.522398 u1DelayCellOfst[1]=7 cells (6 PI)
1388 10:02:41.522457 u1DelayCellOfst[2]=9 cells (7 PI)
1389 10:02:41.522515 u1DelayCellOfst[3]=0 cells (0 PI)
1390 10:02:41.522574 u1DelayCellOfst[4]=7 cells (6 PI)
1391 10:02:41.522633 u1DelayCellOfst[5]=2 cells (2 PI)
1392 10:02:41.522692 u1DelayCellOfst[6]=5 cells (4 PI)
1393 10:02:41.522751 u1DelayCellOfst[7]=7 cells (6 PI)
1394 10:02:41.522810 Byte0, DQ PI dly=981, DQM PI dly= 984
1395 10:02:41.522869 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1396 10:02:41.522928
1397 10:02:41.522988 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1398 10:02:41.523049
1399 10:02:41.523108 u1DelayCellOfst[8]=0 cells (0 PI)
1400 10:02:41.523167 u1DelayCellOfst[9]=3 cells (3 PI)
1401 10:02:41.523227 u1DelayCellOfst[10]=7 cells (6 PI)
1402 10:02:41.523286 u1DelayCellOfst[11]=2 cells (2 PI)
1403 10:02:41.523346 u1DelayCellOfst[12]=3 cells (3 PI)
1404 10:02:41.523412 u1DelayCellOfst[13]=3 cells (3 PI)
1405 10:02:41.523475 u1DelayCellOfst[14]=5 cells (4 PI)
1406 10:02:41.523533 u1DelayCellOfst[15]=7 cells (6 PI)
1407 10:02:41.523592 Byte1, DQ PI dly=975, DQM PI dly= 978
1408 10:02:41.523651 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15)
1409 10:02:41.523711
1410 10:02:41.523769 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15)
1411 10:02:41.523829
1412 10:02:41.523888 Write Rank0 MR14 =0x1c
1413 10:02:41.523948
1414 10:02:41.524007 Final TX Range 0 Vref 28
1415 10:02:41.524066
1416 10:02:41.524125 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1417 10:02:41.524188
1418 10:02:41.524248 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1419 10:02:41.524308 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1420 10:02:41.524368 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1421 10:02:41.524437 Write Rank0 MR3 =0xb0
1422 10:02:41.524497 DramC Write-DBI on
1423 10:02:41.524557 ==
1424 10:02:41.524617 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1425 10:02:41.524677 fsp= 1, odt_onoff= 1, Byte mode= 0
1426 10:02:41.524737 ==
1427 10:02:41.524796 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1428 10:02:41.524855
1429 10:02:41.524914 Begin, DQ Scan Range 698~762
1430 10:02:41.524973
1431 10:02:41.525031
1432 10:02:41.525090 TX Vref Scan disable
1433 10:02:41.525149 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1434 10:02:41.525209 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1435 10:02:41.525270 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1436 10:02:41.525330 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1437 10:02:41.525390 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1438 10:02:41.525451 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1439 10:02:41.525511 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1440 10:02:41.525571 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1441 10:02:41.525630 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1442 10:02:41.525690 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1443 10:02:41.525750 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1444 10:02:41.525811 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1445 10:02:41.525871 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1446 10:02:41.525931 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1447 10:02:41.525991 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1448 10:02:41.526051 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1449 10:02:41.526116 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1450 10:02:41.526188 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1451 10:02:41.526264 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1452 10:02:41.526328 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1453 10:02:41.526389 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1454 10:02:41.526453 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1455 10:02:41.526514 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1456 10:02:41.526574 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1457 10:02:41.526635 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1458 10:02:41.526696 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1459 10:02:41.526756 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1460 10:02:41.526816 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1461 10:02:41.526876 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1462 10:02:41.526936 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1463 10:02:41.526996 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1464 10:02:41.527055 745 |2 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
1465 10:02:41.527116 Byte0, DQ PI dly=731, DQM PI dly= 731
1466 10:02:41.527175 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
1467 10:02:41.527234
1468 10:02:41.527293 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
1469 10:02:41.527352
1470 10:02:41.527423 Byte1, DQ PI dly=722, DQM PI dly= 722
1471 10:02:41.527487 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 18)
1472 10:02:41.527547
1473 10:02:41.527607 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 18)
1474 10:02:41.527667
1475 10:02:41.527726 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1476 10:02:41.527787 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1477 10:02:41.527848 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1478 10:02:41.527907 Write Rank0 MR3 =0x30
1479 10:02:41.527966 DramC Write-DBI off
1480 10:02:41.528024
1481 10:02:41.528126 [DATLAT]
1482 10:02:41.528218 Freq=1600, CH0 RK0, use_rxtx_scan=0
1483 10:02:41.528310
1484 10:02:41.528401 DATLAT Default: 0xf
1485 10:02:41.528469 7, 0xFFFF, sum=0
1486 10:02:41.528530 8, 0xFFFF, sum=0
1487 10:02:41.528591 9, 0xFFFF, sum=0
1488 10:02:41.528651 10, 0xFFFF, sum=0
1489 10:02:41.528711 11, 0xFFFF, sum=0
1490 10:02:41.528771 12, 0xFFFF, sum=0
1491 10:02:41.528830 13, 0xFFFF, sum=0
1492 10:02:41.528890 14, 0x0, sum=1
1493 10:02:41.528949 15, 0x0, sum=2
1494 10:02:41.529009 16, 0x0, sum=3
1495 10:02:41.529068 17, 0x0, sum=4
1496 10:02:41.529128 pattern=2 first_step=14 total pass=5 best_step=16
1497 10:02:41.529187 ==
1498 10:02:41.529247 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1499 10:02:41.529307 fsp= 1, odt_onoff= 1, Byte mode= 0
1500 10:02:41.529366 ==
1501 10:02:41.529425 Start DQ dly to find pass range UseTestEngine =1
1502 10:02:41.529485 x-axis: bit #, y-axis: DQ dly (-127~63)
1503 10:02:41.529743 RX Vref Scan = 1
1504 10:02:41.529813
1505 10:02:41.529873 RX Vref found, early break!
1506 10:02:41.529934
1507 10:02:41.529993 Final RX Vref 12, apply to both rank0 and 1
1508 10:02:41.530053 ==
1509 10:02:41.530112 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1510 10:02:41.530172 fsp= 1, odt_onoff= 1, Byte mode= 0
1511 10:02:41.530231 ==
1512 10:02:41.530290 DQS Delay:
1513 10:02:41.530349 DQS0 = 0, DQS1 = 0
1514 10:02:41.530408 DQM Delay:
1515 10:02:41.530467 DQM0 = 19, DQM1 = 18
1516 10:02:41.530526 DQ Delay:
1517 10:02:41.530585 DQ0 =22, DQ1 =21, DQ2 =21, DQ3 =15
1518 10:02:41.530645 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =20
1519 10:02:41.530704 DQ8 =14, DQ9 =16, DQ10 =25, DQ11 =16
1520 10:02:41.530763 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
1521 10:02:41.530822
1522 10:02:41.530880
1523 10:02:41.530938
1524 10:02:41.530996 [DramC_TX_OE_Calibration] TA2
1525 10:02:41.531055 Original DQ_B0 (3 6) =30, OEN = 27
1526 10:02:41.531114 Original DQ_B1 (3 6) =30, OEN = 27
1527 10:02:41.531173 23, 0x0, End_B0=23 End_B1=23
1528 10:02:41.531233 24, 0x0, End_B0=24 End_B1=24
1529 10:02:41.531292 25, 0x0, End_B0=25 End_B1=25
1530 10:02:41.531352 26, 0x0, End_B0=26 End_B1=26
1531 10:02:41.531422 27, 0x0, End_B0=27 End_B1=27
1532 10:02:41.531484 28, 0x0, End_B0=28 End_B1=28
1533 10:02:41.531544 29, 0x0, End_B0=29 End_B1=29
1534 10:02:41.531603 30, 0x0, End_B0=30 End_B1=30
1535 10:02:41.531663 31, 0xFFFF, End_B0=30 End_B1=30
1536 10:02:41.531723 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1537 10:02:41.531783 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1538 10:02:41.531842
1539 10:02:41.531941
1540 10:02:41.532029 Write Rank0 MR23 =0x3f
1541 10:02:41.532091 [DQSOSC]
1542 10:02:41.532150 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1543 10:02:41.532235 CH0_RK0: MR19=0x303, MR18=0x1313, DQSOSC=400, MR23=63, INC=15, DEC=23
1544 10:02:41.532296 Write Rank0 MR23 =0x3f
1545 10:02:41.532355 [DQSOSC]
1546 10:02:41.532415 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
1547 10:02:41.532475 CH0 RK0: MR19=303, MR18=F0F
1548 10:02:41.532534 [RankSwap] Rank num 2, (Multi 1), Rank 1
1549 10:02:41.532593 Write Rank0 MR2 =0xad
1550 10:02:41.532652 [Write Leveling]
1551 10:02:41.532710 delay byte0 byte1 byte2 byte3
1552 10:02:41.532770
1553 10:02:41.532829 10 0 0
1554 10:02:41.532889 11 0 0
1555 10:02:41.532949 12 0 0
1556 10:02:41.533009 13 0 0
1557 10:02:41.533068 14 0 0
1558 10:02:41.533128 15 0 0
1559 10:02:41.533188 16 0 0
1560 10:02:41.533248 17 0 0
1561 10:02:41.533308 18 0 0
1562 10:02:41.533368 19 0 0
1563 10:02:41.533427 20 0 0
1564 10:02:41.533486 21 0 0
1565 10:02:41.533546 22 0 0
1566 10:02:41.533605 23 0 0
1567 10:02:41.533664 24 0 ff
1568 10:02:41.533724 25 0 ff
1569 10:02:41.533782 26 ff ff
1570 10:02:41.533842 27 ff ff
1571 10:02:41.533901 28 ff ff
1572 10:02:41.533960 29 ff ff
1573 10:02:41.534020 30 ff ff
1574 10:02:41.534079 31 ff ff
1575 10:02:41.534138 32 ff ff
1576 10:02:41.534197 pass bytecount = 0xff (0xff: all bytes pass)
1577 10:02:41.534257
1578 10:02:41.534315 DQS0 dly: 26
1579 10:02:41.534374 DQS1 dly: 24
1580 10:02:41.534432 Write Rank0 MR2 =0x2d
1581 10:02:41.534490 [RankSwap] Rank num 2, (Multi 1), Rank 0
1582 10:02:41.534549 Write Rank1 MR1 =0xd6
1583 10:02:41.534608 [Gating]
1584 10:02:41.534666 ==
1585 10:02:41.534738 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1586 10:02:41.534803 fsp= 1, odt_onoff= 1, Byte mode= 0
1587 10:02:41.534863 ==
1588 10:02:41.534939 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1589 10:02:41.535027 3 1 4 |2c2b 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1590 10:02:41.535093 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1591 10:02:41.535196 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1592 10:02:41.535292 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1593 10:02:41.535390 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1594 10:02:41.535467 3 1 24 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1595 10:02:41.535536 3 1 28 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1596 10:02:41.535598 3 2 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1597 10:02:41.535659 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1598 10:02:41.535724 3 2 8 |201 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1599 10:02:41.535785 3 2 12 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1600 10:02:41.535846 3 2 16 |3534 403 |(11 11)(11 11) |(0 0)(1 1)| 0
1601 10:02:41.535911 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1602 10:02:41.535971 3 2 24 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1603 10:02:41.536031 3 2 28 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1604 10:02:41.536095 3 3 0 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1605 10:02:41.536155 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1606 10:02:41.536215 3 3 8 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1607 10:02:41.536275 3 3 12 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1608 10:02:41.536334 3 3 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1609 10:02:41.536395 3 3 20 |3534 706 |(11 11)(11 11) |(0 0)(1 1)| 0
1610 10:02:41.536455 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1611 10:02:41.536515 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1612 10:02:41.536576 [Byte 1] Lead/lag falling Transition (3, 3, 28)
1613 10:02:41.536635 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1614 10:02:41.536695 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1615 10:02:41.536755 3 4 8 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1616 10:02:41.536815 3 4 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1617 10:02:41.536875 3 4 16 |3d3d 1c1c |(11 11)(11 11) |(1 1)(1 1)| 0
1618 10:02:41.536935 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1619 10:02:41.536995 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1620 10:02:41.537055 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1621 10:02:41.537115 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1622 10:02:41.537175 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1623 10:02:41.537235 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1624 10:02:41.537295 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1625 10:02:41.537354 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1626 10:02:41.537414 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1627 10:02:41.537474 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1628 10:02:41.537732 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1629 10:02:41.537799 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1630 10:02:41.537860 [Byte 0] Lead/lag falling Transition (3, 6, 0)
1631 10:02:41.537920 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1632 10:02:41.537981 [Byte 1] Lead/lag falling Transition (3, 6, 4)
1633 10:02:41.538040 3 6 8 |d0c 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1634 10:02:41.538102 [Byte 0] Lead/lag Transition tap number (3)
1635 10:02:41.538162 [Byte 1] Lead/lag Transition tap number (2)
1636 10:02:41.538221 3 6 12 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
1637 10:02:41.538282 [Byte 0]First pass (3, 6, 12)
1638 10:02:41.538341 3 6 16 |4646 404 |(0 0)(11 11) |(0 0)(0 0)| 0
1639 10:02:41.538400 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1640 10:02:41.538460 [Byte 1]First pass (3, 6, 20)
1641 10:02:41.538518 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1642 10:02:41.538578 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1643 10:02:41.538638 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1644 10:02:41.538698 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1645 10:02:41.538757 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1646 10:02:41.538817 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1647 10:02:41.538877 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1648 10:02:41.538937 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1649 10:02:41.538996 All bytes gating window > 1UI, Early break!
1650 10:02:41.539055
1651 10:02:41.539113 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
1652 10:02:41.539173
1653 10:02:41.539232 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
1654 10:02:41.539291
1655 10:02:41.539349
1656 10:02:41.539416
1657 10:02:41.539477 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
1658 10:02:41.539536
1659 10:02:41.539594 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
1660 10:02:41.539653
1661 10:02:41.539712
1662 10:02:41.539771 Write Rank1 MR1 =0x56
1663 10:02:41.539830
1664 10:02:41.539888 best RODT dly(2T, 0.5T) = (2, 3)
1665 10:02:41.539948
1666 10:02:41.540006 best RODT dly(2T, 0.5T) = (2, 3)
1667 10:02:41.540065 ==
1668 10:02:41.540124 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1669 10:02:41.540183 fsp= 1, odt_onoff= 1, Byte mode= 0
1670 10:02:41.540242 ==
1671 10:02:41.540301 Start DQ dly to find pass range UseTestEngine =0
1672 10:02:41.540360 x-axis: bit #, y-axis: DQ dly (-127~63)
1673 10:02:41.540419 RX Vref Scan = 0
1674 10:02:41.540479 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1675 10:02:41.540540 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1676 10:02:41.540600 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1677 10:02:41.540659 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1678 10:02:41.540719 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1679 10:02:41.540778 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1680 10:02:41.540837 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1681 10:02:41.540897 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1682 10:02:41.540956 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1683 10:02:41.541017 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1684 10:02:41.541075 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1685 10:02:41.541136 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1686 10:02:41.541195 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1687 10:02:41.541255 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1688 10:02:41.541314 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1689 10:02:41.541373 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1690 10:02:41.541432 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1691 10:02:41.541491 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1692 10:02:41.541550 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1693 10:02:41.541610 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1694 10:02:41.541669 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1695 10:02:41.541728 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1696 10:02:41.541787 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1697 10:02:41.541847 -3, [0] xxxxxxxx oxxxxxxx [MSB]
1698 10:02:41.541906 -2, [0] xxxoxxxx oxxoxxxx [MSB]
1699 10:02:41.541965 -1, [0] xxxoxxxx oxxoxxxx [MSB]
1700 10:02:41.542025 0, [0] xxxoxoxx ooxoxxxx [MSB]
1701 10:02:41.542085 1, [0] xxxoxoxx ooxoooxx [MSB]
1702 10:02:41.542144 2, [0] xxxoxoox ooxoooxx [MSB]
1703 10:02:41.542204 3, [0] xxxooooo ooxoooox [MSB]
1704 10:02:41.542263 4, [0] xoxooooo ooxoooox [MSB]
1705 10:02:41.542322 5, [0] oooooooo ooxooooo [MSB]
1706 10:02:41.542382 6, [0] oooooooo ooxooooo [MSB]
1707 10:02:41.542441 34, [0] oooooooo xooooooo [MSB]
1708 10:02:41.542500 35, [0] oooxoooo xooooooo [MSB]
1709 10:02:41.542559 36, [0] oooxoooo xooxoooo [MSB]
1710 10:02:41.542619 37, [0] oooxoxoo xxoxoxoo [MSB]
1711 10:02:41.542678 38, [0] oooxoxoo xxoxoxxo [MSB]
1712 10:02:41.542737 39, [0] oooxoxox xxoxxxxo [MSB]
1713 10:02:41.542798 40, [0] oooxoxxx xxoxxxxo [MSB]
1714 10:02:41.542857 41, [0] oxxxxxxx xxoxxxxx [MSB]
1715 10:02:41.542917 42, [0] oxxxxxxx xxoxxxxx [MSB]
1716 10:02:41.542976 43, [0] xxxxxxxx xxoxxxxx [MSB]
1717 10:02:41.543035 44, [0] xxxxxxxx xxoxxxxx [MSB]
1718 10:02:41.543094 45, [0] xxxxxxxx xxxxxxxx [MSB]
1719 10:02:41.543154 iDelay=45, Bit 0, Center 23 (5 ~ 42) 38
1720 10:02:41.543212 iDelay=45, Bit 1, Center 22 (4 ~ 40) 37
1721 10:02:41.543271 iDelay=45, Bit 2, Center 22 (5 ~ 40) 36
1722 10:02:41.543368 iDelay=45, Bit 3, Center 16 (-2 ~ 34) 37
1723 10:02:41.543476 iDelay=45, Bit 4, Center 21 (3 ~ 40) 38
1724 10:02:41.543552 iDelay=45, Bit 5, Center 18 (0 ~ 36) 37
1725 10:02:41.543612 iDelay=45, Bit 6, Center 20 (2 ~ 39) 38
1726 10:02:41.543704 iDelay=45, Bit 7, Center 20 (3 ~ 38) 36
1727 10:02:41.543807 iDelay=45, Bit 8, Center 15 (-3 ~ 33) 37
1728 10:02:41.543907 iDelay=45, Bit 9, Center 18 (0 ~ 36) 37
1729 10:02:41.544002 iDelay=45, Bit 10, Center 25 (7 ~ 44) 38
1730 10:02:41.544097 iDelay=45, Bit 11, Center 16 (-2 ~ 35) 38
1731 10:02:41.544162 iDelay=45, Bit 12, Center 19 (1 ~ 38) 38
1732 10:02:41.544222 iDelay=45, Bit 13, Center 18 (1 ~ 36) 36
1733 10:02:41.544289 iDelay=45, Bit 14, Center 20 (3 ~ 37) 35
1734 10:02:41.544350 iDelay=45, Bit 15, Center 22 (5 ~ 40) 36
1735 10:02:41.544409 ==
1736 10:02:41.544484 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1737 10:02:41.544547 fsp= 1, odt_onoff= 1, Byte mode= 0
1738 10:02:41.544607 ==
1739 10:02:41.544667 DQS Delay:
1740 10:02:41.544728 DQS0 = 0, DQS1 = 0
1741 10:02:41.544788 DQM Delay:
1742 10:02:41.544848 DQM0 = 20, DQM1 = 19
1743 10:02:41.544907 DQ Delay:
1744 10:02:41.544966 DQ0 =23, DQ1 =22, DQ2 =22, DQ3 =16
1745 10:02:41.545025 DQ4 =21, DQ5 =18, DQ6 =20, DQ7 =20
1746 10:02:41.545084 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =16
1747 10:02:41.545143 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
1748 10:02:41.545201
1749 10:02:41.545260
1750 10:02:41.545318 DramC Write-DBI off
1751 10:02:41.545378 ==
1752 10:02:41.545437 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1753 10:02:41.545694 fsp= 1, odt_onoff= 1, Byte mode= 0
1754 10:02:41.545762 ==
1755 10:02:41.545822 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1756 10:02:41.545881
1757 10:02:41.545940 Begin, DQ Scan Range 920~1176
1758 10:02:41.546000
1759 10:02:41.546058
1760 10:02:41.546116 TX Vref Scan disable
1761 10:02:41.546175 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1762 10:02:41.546236 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1763 10:02:41.546297 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1764 10:02:41.546357 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1765 10:02:41.546417 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1766 10:02:41.546477 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1767 10:02:41.546538 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1768 10:02:41.546597 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1769 10:02:41.546656 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1770 10:02:41.546716 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1771 10:02:41.546776 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1772 10:02:41.546836 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1773 10:02:41.546897 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1774 10:02:41.546957 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1775 10:02:41.547017 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1776 10:02:41.547077 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1777 10:02:41.547137 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1778 10:02:41.547197 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1779 10:02:41.547257 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1780 10:02:41.547317 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1781 10:02:41.547377 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1782 10:02:41.547448 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1783 10:02:41.547511 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1784 10:02:41.547571 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1785 10:02:41.547632 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1786 10:02:41.547692 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1787 10:02:41.547753 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1788 10:02:41.547813 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1789 10:02:41.547872 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1790 10:02:41.547932 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1791 10:02:41.547993 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1792 10:02:41.548053 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1793 10:02:41.548113 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1794 10:02:41.548173 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1795 10:02:41.548233 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1796 10:02:41.548293 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1797 10:02:41.548352 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1798 10:02:41.548412 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1799 10:02:41.548471 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1800 10:02:41.548531 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1801 10:02:41.548592 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1802 10:02:41.548652 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1803 10:02:41.548712 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1804 10:02:41.548772 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1805 10:02:41.548832 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1806 10:02:41.548892 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1807 10:02:41.548951 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1808 10:02:41.549011 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1809 10:02:41.549070 968 |3 6 8|[0] xxxxxxxx oxxoxxxx [MSB]
1810 10:02:41.549129 969 |3 6 9|[0] xxxxxxxx ooxoxxxx [MSB]
1811 10:02:41.549189 970 |3 6 10|[0] xxxxxxxx ooxooxox [MSB]
1812 10:02:41.549249 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1813 10:02:41.549309 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1814 10:02:41.549369 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1815 10:02:41.549429 974 |3 6 14|[0] xxxooooo ooxooooo [MSB]
1816 10:02:41.549488 975 |3 6 15|[0] ooxooooo oooooooo [MSB]
1817 10:02:41.549547 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1818 10:02:41.549607 989 |3 6 29|[0] oooxoooo xxxxxxxx [MSB]
1819 10:02:41.549667 990 |3 6 30|[0] oooxoooo xxxxxxxx [MSB]
1820 10:02:41.549727 991 |3 6 31|[0] oooxoooo xxxxxxxx [MSB]
1821 10:02:41.549787 992 |3 6 32|[0] oooxoxoo xxxxxxxx [MSB]
1822 10:02:41.549847 993 |3 6 33|[0] xxxxxxxx xxxxxxxx [MSB]
1823 10:02:41.549906 Byte0, DQ PI dly=982, DQM PI dly= 982
1824 10:02:41.549966 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
1825 10:02:41.550025
1826 10:02:41.550083 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
1827 10:02:41.550142
1828 10:02:41.550201 Byte1, DQ PI dly=979, DQM PI dly= 979
1829 10:02:41.550259 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1830 10:02:41.550319
1831 10:02:41.550377 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1832 10:02:41.550436
1833 10:02:41.550494 ==
1834 10:02:41.550553 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1835 10:02:41.550613 fsp= 1, odt_onoff= 1, Byte mode= 0
1836 10:02:41.550672 ==
1837 10:02:41.550730 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1838 10:02:41.550789
1839 10:02:41.550847 Begin, DQ Scan Range 955~1019
1840 10:02:41.550906 Write Rank1 MR14 =0x0
1841 10:02:41.550964
1842 10:02:41.551023 CH=0, VrefRange= 0, VrefLevel = 0
1843 10:02:41.551082 TX Bit0 (977~991) 15 984, Bit8 (969~982) 14 975,
1844 10:02:41.551141 TX Bit1 (977~988) 12 982, Bit9 (971~985) 15 978,
1845 10:02:41.551200 TX Bit2 (977~990) 14 983, Bit10 (977~985) 9 981,
1846 10:02:41.551259 TX Bit3 (971~982) 12 976, Bit11 (970~983) 14 976,
1847 10:02:41.551318 TX Bit4 (976~988) 13 982, Bit12 (973~985) 13 979,
1848 10:02:41.551376 TX Bit5 (973~985) 13 979, Bit13 (975~983) 9 979,
1849 10:02:41.551444 TX Bit6 (975~987) 13 981, Bit14 (974~984) 11 979,
1850 10:02:41.551504 TX Bit7 (976~989) 14 982, Bit15 (976~985) 10 980,
1851 10:02:41.551564
1852 10:02:41.551623 Write Rank1 MR14 =0x2
1853 10:02:41.551681
1854 10:02:41.551739 CH=0, VrefRange= 0, VrefLevel = 2
1855 10:02:41.551798 TX Bit0 (977~991) 15 984, Bit8 (969~983) 15 976,
1856 10:02:41.551857 TX Bit1 (976~989) 14 982, Bit9 (970~985) 16 977,
1857 10:02:41.551916 TX Bit2 (977~990) 14 983, Bit10 (977~990) 14 983,
1858 10:02:41.551975 TX Bit3 (970~983) 14 976, Bit11 (970~983) 14 976,
1859 10:02:41.552047 TX Bit4 (976~990) 15 983, Bit12 (972~985) 14 978,
1860 10:02:41.552107 TX Bit5 (973~986) 14 979, Bit13 (974~983) 10 978,
1861 10:02:41.552166 TX Bit6 (974~988) 15 981, Bit14 (974~985) 12 979,
1862 10:02:41.552440 TX Bit7 (975~990) 16 982, Bit15 (976~990) 15 983,
1863 10:02:41.552514
1864 10:02:41.552575 Write Rank1 MR14 =0x4
1865 10:02:41.552659
1866 10:02:41.552732 CH=0, VrefRange= 0, VrefLevel = 4
1867 10:02:41.552795 TX Bit0 (977~992) 16 984, Bit8 (969~983) 15 976,
1868 10:02:41.552856 TX Bit1 (976~990) 15 983, Bit9 (970~985) 16 977,
1869 10:02:41.552949 TX Bit2 (977~991) 15 984, Bit10 (976~990) 15 983,
1870 10:02:41.553047 TX Bit3 (970~984) 15 977, Bit11 (970~984) 15 977,
1871 10:02:41.553140 TX Bit4 (975~990) 16 982, Bit12 (971~986) 16 978,
1872 10:02:41.553236 TX Bit5 (972~987) 16 979, Bit13 (974~984) 11 979,
1873 10:02:41.553335 TX Bit6 (974~989) 16 981, Bit14 (973~986) 14 979,
1874 10:02:41.553429 TX Bit7 (975~990) 16 982, Bit15 (975~990) 16 982,
1875 10:02:41.553524
1876 10:02:41.553616 Write Rank1 MR14 =0x6
1877 10:02:41.553711
1878 10:02:41.553805 CH=0, VrefRange= 0, VrefLevel = 6
1879 10:02:41.553897 TX Bit0 (977~992) 16 984, Bit8 (969~984) 16 976,
1880 10:02:41.553990 TX Bit1 (976~990) 15 983, Bit9 (970~986) 17 978,
1881 10:02:41.554082 TX Bit2 (977~991) 15 984, Bit10 (976~991) 16 983,
1882 10:02:41.554175 TX Bit3 (970~985) 16 977, Bit11 (969~984) 16 976,
1883 10:02:41.554267 TX Bit4 (975~991) 17 983, Bit12 (971~987) 17 979,
1884 10:02:41.554359 TX Bit5 (972~988) 17 980, Bit13 (973~984) 12 978,
1885 10:02:41.554452 TX Bit6 (973~990) 18 981, Bit14 (972~987) 16 979,
1886 10:02:41.554544 TX Bit7 (975~991) 17 983, Bit15 (975~991) 17 983,
1887 10:02:41.554635
1888 10:02:41.554725 Write Rank1 MR14 =0x8
1889 10:02:41.554816
1890 10:02:41.554907 CH=0, VrefRange= 0, VrefLevel = 8
1891 10:02:41.554999 TX Bit0 (977~992) 16 984, Bit8 (969~984) 16 976,
1892 10:02:41.555091 TX Bit1 (975~991) 17 983, Bit9 (970~987) 18 978,
1893 10:02:41.555183 TX Bit2 (977~991) 15 984, Bit10 (975~991) 17 983,
1894 10:02:41.555275 TX Bit3 (969~985) 17 977, Bit11 (969~984) 16 976,
1895 10:02:41.555367 TX Bit4 (975~991) 17 983, Bit12 (971~988) 18 979,
1896 10:02:41.555457 TX Bit5 (971~988) 18 979, Bit13 (973~985) 13 979,
1897 10:02:41.555519 TX Bit6 (973~990) 18 981, Bit14 (971~988) 18 979,
1898 10:02:41.555578 TX Bit7 (974~991) 18 982, Bit15 (975~991) 17 983,
1899 10:02:41.555638
1900 10:02:41.555696 Write Rank1 MR14 =0xa
1901 10:02:41.555755
1902 10:02:41.555814 CH=0, VrefRange= 0, VrefLevel = 10
1903 10:02:41.555873 TX Bit0 (976~993) 18 984, Bit8 (968~985) 18 976,
1904 10:02:41.555934 TX Bit1 (975~991) 17 983, Bit9 (969~987) 19 978,
1905 10:02:41.555993 TX Bit2 (976~992) 17 984, Bit10 (976~992) 17 984,
1906 10:02:41.556053 TX Bit3 (969~986) 18 977, Bit11 (969~985) 17 977,
1907 10:02:41.556112 TX Bit4 (974~991) 18 982, Bit12 (970~988) 19 979,
1908 10:02:41.556172 TX Bit5 (971~989) 19 980, Bit13 (972~986) 15 979,
1909 10:02:41.556231 TX Bit6 (972~991) 20 981, Bit14 (972~989) 18 980,
1910 10:02:41.556290 TX Bit7 (974~992) 19 983, Bit15 (974~992) 19 983,
1911 10:02:41.556349
1912 10:02:41.556407 Write Rank1 MR14 =0xc
1913 10:02:41.556466
1914 10:02:41.556525 CH=0, VrefRange= 0, VrefLevel = 12
1915 10:02:41.556584 TX Bit0 (976~993) 18 984, Bit8 (968~985) 18 976,
1916 10:02:41.556644 TX Bit1 (975~991) 17 983, Bit9 (969~989) 21 979,
1917 10:02:41.556703 TX Bit2 (976~992) 17 984, Bit10 (975~992) 18 983,
1918 10:02:41.556762 TX Bit3 (969~987) 19 978, Bit11 (969~986) 18 977,
1919 10:02:41.556821 TX Bit4 (974~992) 19 983, Bit12 (970~989) 20 979,
1920 10:02:41.556880 TX Bit5 (970~990) 21 980, Bit13 (971~986) 16 978,
1921 10:02:41.556938 TX Bit6 (972~991) 20 981, Bit14 (971~989) 19 980,
1922 10:02:41.556998 TX Bit7 (973~992) 20 982, Bit15 (975~992) 18 983,
1923 10:02:41.557057
1924 10:02:41.557115 Write Rank1 MR14 =0xe
1925 10:02:41.557174
1926 10:02:41.557232 CH=0, VrefRange= 0, VrefLevel = 14
1927 10:02:41.557291 TX Bit0 (976~994) 19 985, Bit8 (968~986) 19 977,
1928 10:02:41.557350 TX Bit1 (975~992) 18 983, Bit9 (969~989) 21 979,
1929 10:02:41.557408 TX Bit2 (976~993) 18 984, Bit10 (975~992) 18 983,
1930 10:02:41.557467 TX Bit3 (969~987) 19 978, Bit11 (968~986) 19 977,
1931 10:02:41.557526 TX Bit4 (974~992) 19 983, Bit12 (970~990) 21 980,
1932 10:02:41.557585 TX Bit5 (970~990) 21 980, Bit13 (971~987) 17 979,
1933 10:02:41.557644 TX Bit6 (971~991) 21 981, Bit14 (970~990) 21 980,
1934 10:02:41.557704 TX Bit7 (972~992) 21 982, Bit15 (974~992) 19 983,
1935 10:02:41.557763
1936 10:02:41.557822 Write Rank1 MR14 =0x10
1937 10:02:41.557881
1938 10:02:41.557939 CH=0, VrefRange= 0, VrefLevel = 16
1939 10:02:41.557998 TX Bit0 (975~994) 20 984, Bit8 (968~987) 20 977,
1940 10:02:41.558058 TX Bit1 (974~992) 19 983, Bit9 (969~990) 22 979,
1941 10:02:41.558118 TX Bit2 (976~993) 18 984, Bit10 (975~993) 19 984,
1942 10:02:41.558176 TX Bit3 (968~988) 21 978, Bit11 (968~987) 20 977,
1943 10:02:41.558236 TX Bit4 (973~993) 21 983, Bit12 (969~990) 22 979,
1944 10:02:41.558295 TX Bit5 (970~991) 22 980, Bit13 (971~988) 18 979,
1945 10:02:41.558354 TX Bit6 (971~992) 22 981, Bit14 (970~990) 21 980,
1946 10:02:41.558412 TX Bit7 (973~993) 21 983, Bit15 (973~993) 21 983,
1947 10:02:41.558471
1948 10:02:41.558529 Write Rank1 MR14 =0x12
1949 10:02:41.558587
1950 10:02:41.558645 CH=0, VrefRange= 0, VrefLevel = 18
1951 10:02:41.558704 TX Bit0 (975~995) 21 985, Bit8 (967~987) 21 977,
1952 10:02:41.558763 TX Bit1 (974~993) 20 983, Bit9 (969~990) 22 979,
1953 10:02:41.558823 TX Bit2 (976~994) 19 985, Bit10 (975~994) 20 984,
1954 10:02:41.558882 TX Bit3 (968~988) 21 978, Bit11 (968~987) 20 977,
1955 10:02:41.558942 TX Bit4 (973~993) 21 983, Bit12 (969~990) 22 979,
1956 10:02:41.559001 TX Bit5 (970~991) 22 980, Bit13 (970~989) 20 979,
1957 10:02:41.559060 TX Bit6 (971~992) 22 981, Bit14 (970~990) 21 980,
1958 10:02:41.559119 TX Bit7 (972~993) 22 982, Bit15 (973~993) 21 983,
1959 10:02:41.559178
1960 10:02:41.559236 Write Rank1 MR14 =0x14
1961 10:02:41.559295
1962 10:02:41.559353 CH=0, VrefRange= 0, VrefLevel = 20
1963 10:02:41.559419 TX Bit0 (975~996) 22 985, Bit8 (967~989) 23 978,
1964 10:02:41.559481 TX Bit1 (974~994) 21 984, Bit9 (969~990) 22 979,
1965 10:02:41.559735 TX Bit2 (975~994) 20 984, Bit10 (975~994) 20 984,
1966 10:02:41.559802 TX Bit3 (968~989) 22 978, Bit11 (968~989) 22 978,
1967 10:02:41.559863 TX Bit4 (972~994) 23 983, Bit12 (969~991) 23 980,
1968 10:02:41.559922 TX Bit5 (970~991) 22 980, Bit13 (970~989) 20 979,
1969 10:02:41.559981 TX Bit6 (970~992) 23 981, Bit14 (969~991) 23 980,
1970 10:02:41.560059 TX Bit7 (971~994) 24 982, Bit15 (972~994) 23 983,
1971 10:02:41.560120
1972 10:02:41.560179 Write Rank1 MR14 =0x16
1973 10:02:41.560238
1974 10:02:41.560296 CH=0, VrefRange= 0, VrefLevel = 22
1975 10:02:41.560355 TX Bit0 (975~996) 22 985, Bit8 (967~989) 23 978,
1976 10:02:41.694269 TX Bit1 (973~994) 22 983, Bit9 (968~991) 24 979,
1977 10:02:41.694810 TX Bit2 (975~995) 21 985, Bit10 (974~995) 22 984,
1978 10:02:41.695175 TX Bit3 (968~989) 22 978, Bit11 (967~989) 23 978,
1979 10:02:41.695560 TX Bit4 (972~994) 23 983, Bit12 (969~991) 23 980,
1980 10:02:41.695892 TX Bit5 (970~992) 23 981, Bit13 (970~990) 21 980,
1981 10:02:41.696212 TX Bit6 (970~993) 24 981, Bit14 (969~991) 23 980,
1982 10:02:41.696527 TX Bit7 (972~994) 23 983, Bit15 (973~994) 22 983,
1983 10:02:41.696838
1984 10:02:41.697144 Write Rank1 MR14 =0x18
1985 10:02:41.697449
1986 10:02:41.697750 CH=0, VrefRange= 0, VrefLevel = 24
1987 10:02:41.698053 TX Bit0 (974~997) 24 985, Bit8 (966~989) 24 977,
1988 10:02:41.698355 TX Bit1 (973~995) 23 984, Bit9 (968~991) 24 979,
1989 10:02:41.698654 TX Bit2 (975~995) 21 985, Bit10 (974~996) 23 985,
1990 10:02:41.698956 TX Bit3 (968~990) 23 979, Bit11 (967~990) 24 978,
1991 10:02:41.699255 TX Bit4 (972~995) 24 983, Bit12 (969~991) 23 980,
1992 10:02:41.699580 TX Bit5 (969~992) 24 980, Bit13 (969~990) 22 979,
1993 10:02:41.699799 TX Bit6 (970~993) 24 981, Bit14 (969~992) 24 980,
1994 10:02:41.699861 TX Bit7 (971~995) 25 983, Bit15 (971~995) 25 983,
1995 10:02:41.699921
1996 10:02:41.699981 Write Rank1 MR14 =0x1a
1997 10:02:41.700040
1998 10:02:41.700099 CH=0, VrefRange= 0, VrefLevel = 26
1999 10:02:41.700158 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
2000 10:02:41.700217 TX Bit1 (972~995) 24 983, Bit9 (968~991) 24 979,
2001 10:02:41.700275 TX Bit2 (975~996) 22 985, Bit10 (973~997) 25 985,
2002 10:02:41.700335 TX Bit3 (967~990) 24 978, Bit11 (967~990) 24 978,
2003 10:02:41.700394 TX Bit4 (971~995) 25 983, Bit12 (969~992) 24 980,
2004 10:02:41.700452 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
2005 10:02:41.700511 TX Bit6 (970~994) 25 982, Bit14 (969~992) 24 980,
2006 10:02:41.700570 TX Bit7 (970~995) 26 982, Bit15 (972~995) 24 983,
2007 10:02:41.700629
2008 10:02:41.700687 Write Rank1 MR14 =0x1c
2009 10:02:41.700744
2010 10:02:41.700803 CH=0, VrefRange= 0, VrefLevel = 28
2011 10:02:41.700862 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
2012 10:02:41.700921 TX Bit1 (972~995) 24 983, Bit9 (968~991) 24 979,
2013 10:02:41.700980 TX Bit2 (974~997) 24 985, Bit10 (972~997) 26 984,
2014 10:02:41.701039 TX Bit3 (967~991) 25 979, Bit11 (967~990) 24 978,
2015 10:02:41.701098 TX Bit4 (971~995) 25 983, Bit12 (969~992) 24 980,
2016 10:02:41.701157 TX Bit5 (969~992) 24 980, Bit13 (969~991) 23 980,
2017 10:02:41.701216 TX Bit6 (970~994) 25 982, Bit14 (969~992) 24 980,
2018 10:02:41.701274 TX Bit7 (970~996) 27 983, Bit15 (971~996) 26 983,
2019 10:02:41.701332
2020 10:02:41.701390 Write Rank1 MR14 =0x1e
2021 10:02:41.701449
2022 10:02:41.701507 CH=0, VrefRange= 0, VrefLevel = 30
2023 10:02:41.701566 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
2024 10:02:41.701625 TX Bit1 (972~995) 24 983, Bit9 (968~991) 24 979,
2025 10:02:41.701685 TX Bit2 (974~997) 24 985, Bit10 (972~997) 26 984,
2026 10:02:41.701744 TX Bit3 (967~991) 25 979, Bit11 (967~991) 25 979,
2027 10:02:41.701802 TX Bit4 (971~995) 25 983, Bit12 (968~992) 25 980,
2028 10:02:41.701861 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
2029 10:02:41.701920 TX Bit6 (969~994) 26 981, Bit14 (968~992) 25 980,
2030 10:02:41.701979 TX Bit7 (970~995) 26 982, Bit15 (971~995) 25 983,
2031 10:02:41.702038
2032 10:02:41.702097 Write Rank1 MR14 =0x20
2033 10:02:41.702155
2034 10:02:41.702213 CH=0, VrefRange= 0, VrefLevel = 32
2035 10:02:41.702273 TX Bit0 (973~998) 26 985, Bit8 (966~990) 25 978,
2036 10:02:41.702332 TX Bit1 (972~996) 25 984, Bit9 (968~990) 23 979,
2037 10:02:41.702391 TX Bit2 (973~998) 26 985, Bit10 (972~997) 26 984,
2038 10:02:41.702450 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
2039 10:02:41.702509 TX Bit4 (971~996) 26 983, Bit12 (968~992) 25 980,
2040 10:02:41.702568 TX Bit5 (968~993) 26 980, Bit13 (969~992) 24 980,
2041 10:02:41.702626 TX Bit6 (969~995) 27 982, Bit14 (968~992) 25 980,
2042 10:02:41.702686 TX Bit7 (971~996) 26 983, Bit15 (971~995) 25 983,
2043 10:02:41.702745
2044 10:02:41.702803 Write Rank1 MR14 =0x22
2045 10:02:41.702862
2046 10:02:41.702920 CH=0, VrefRange= 0, VrefLevel = 34
2047 10:02:41.702978 TX Bit0 (973~998) 26 985, Bit8 (966~990) 25 978,
2048 10:02:41.703037 TX Bit1 (972~996) 25 984, Bit9 (968~990) 23 979,
2049 10:02:41.703096 TX Bit2 (973~998) 26 985, Bit10 (972~997) 26 984,
2050 10:02:41.703155 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
2051 10:02:41.703214 TX Bit4 (971~996) 26 983, Bit12 (968~992) 25 980,
2052 10:02:41.703273 TX Bit5 (968~993) 26 980, Bit13 (969~992) 24 980,
2053 10:02:41.703332 TX Bit6 (969~995) 27 982, Bit14 (968~992) 25 980,
2054 10:02:41.703391 TX Bit7 (971~996) 26 983, Bit15 (971~995) 25 983,
2055 10:02:41.703454
2056 10:02:41.703513 Write Rank1 MR14 =0x24
2057 10:02:41.703571
2058 10:02:41.703630 CH=0, VrefRange= 0, VrefLevel = 36
2059 10:02:41.703688 TX Bit0 (973~998) 26 985, Bit8 (966~990) 25 978,
2060 10:02:41.703747 TX Bit1 (972~996) 25 984, Bit9 (968~990) 23 979,
2061 10:02:41.703806 TX Bit2 (973~998) 26 985, Bit10 (972~997) 26 984,
2062 10:02:41.703865 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
2063 10:02:41.703923 TX Bit4 (971~996) 26 983, Bit12 (968~992) 25 980,
2064 10:02:41.703982 TX Bit5 (968~993) 26 980, Bit13 (969~992) 24 980,
2065 10:02:41.704252 TX Bit6 (969~995) 27 982, Bit14 (968~992) 25 980,
2066 10:02:41.704322 TX Bit7 (971~996) 26 983, Bit15 (971~995) 25 983,
2067 10:02:41.704382
2068 10:02:41.704442 Write Rank1 MR14 =0x26
2069 10:02:41.704501
2070 10:02:41.704560 CH=0, VrefRange= 0, VrefLevel = 38
2071 10:02:41.704620 TX Bit0 (973~998) 26 985, Bit8 (966~990) 25 978,
2072 10:02:41.704680 TX Bit1 (972~996) 25 984, Bit9 (968~990) 23 979,
2073 10:02:41.704740 TX Bit2 (973~998) 26 985, Bit10 (972~997) 26 984,
2074 10:02:41.704800 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
2075 10:02:41.704859 TX Bit4 (971~996) 26 983, Bit12 (968~992) 25 980,
2076 10:02:41.704918 TX Bit5 (968~993) 26 980, Bit13 (969~992) 24 980,
2077 10:02:41.704977 TX Bit6 (969~995) 27 982, Bit14 (968~992) 25 980,
2078 10:02:41.705036 TX Bit7 (971~996) 26 983, Bit15 (971~995) 25 983,
2079 10:02:41.705095
2080 10:02:41.705153
2081 10:02:41.705211 TX Vref found, early break! 375< 382
2082 10:02:41.705271 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2083 10:02:41.705331 u1DelayCellOfst[0]=7 cells (6 PI)
2084 10:02:41.705389 u1DelayCellOfst[1]=6 cells (5 PI)
2085 10:02:41.705448 u1DelayCellOfst[2]=7 cells (6 PI)
2086 10:02:41.705506 u1DelayCellOfst[3]=0 cells (0 PI)
2087 10:02:41.705564 u1DelayCellOfst[4]=5 cells (4 PI)
2088 10:02:41.705623 u1DelayCellOfst[5]=1 cells (1 PI)
2089 10:02:41.705682 u1DelayCellOfst[6]=3 cells (3 PI)
2090 10:02:41.705741 u1DelayCellOfst[7]=5 cells (4 PI)
2091 10:02:41.705799 Byte0, DQ PI dly=979, DQM PI dly= 982
2092 10:02:41.705858 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2093 10:02:41.705918
2094 10:02:41.705977 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2095 10:02:41.706038
2096 10:02:41.706097 u1DelayCellOfst[8]=0 cells (0 PI)
2097 10:02:41.706156 u1DelayCellOfst[9]=1 cells (1 PI)
2098 10:02:41.706215 u1DelayCellOfst[10]=7 cells (6 PI)
2099 10:02:41.706274 u1DelayCellOfst[11]=0 cells (0 PI)
2100 10:02:41.706332 u1DelayCellOfst[12]=2 cells (2 PI)
2101 10:02:41.706391 u1DelayCellOfst[13]=2 cells (2 PI)
2102 10:02:41.706449 u1DelayCellOfst[14]=2 cells (2 PI)
2103 10:02:41.706508 u1DelayCellOfst[15]=6 cells (5 PI)
2104 10:02:41.706567 Byte1, DQ PI dly=978, DQM PI dly= 981
2105 10:02:41.706627 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
2106 10:02:41.706686
2107 10:02:41.706746 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
2108 10:02:41.706809
2109 10:02:41.706888 Write Rank1 MR14 =0x20
2110 10:02:41.706949
2111 10:02:41.707008 Final TX Range 0 Vref 32
2112 10:02:41.707068
2113 10:02:41.707128 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2114 10:02:41.707188
2115 10:02:41.707248 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2116 10:02:41.707309 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2117 10:02:41.707368 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2118 10:02:41.707439 Write Rank1 MR3 =0xb0
2119 10:02:41.707500 DramC Write-DBI on
2120 10:02:41.707560 ==
2121 10:02:41.707620 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2122 10:02:41.707681 fsp= 1, odt_onoff= 1, Byte mode= 0
2123 10:02:41.707741 ==
2124 10:02:41.707801 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2125 10:02:41.707860
2126 10:02:41.707920 Begin, DQ Scan Range 701~765
2127 10:02:41.707979
2128 10:02:41.708038
2129 10:02:41.708096 TX Vref Scan disable
2130 10:02:41.708155 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2131 10:02:41.708216 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2132 10:02:41.708277 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2133 10:02:41.708338 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2134 10:02:41.708398 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2135 10:02:41.708457 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2136 10:02:41.708518 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2137 10:02:41.708577 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2138 10:02:41.708637 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2139 10:02:41.708697 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2140 10:02:41.708758 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2141 10:02:41.708817 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2142 10:02:41.708884 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2143 10:02:41.708946 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2144 10:02:41.709006 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2145 10:02:41.709067 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2146 10:02:41.709128 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2147 10:02:41.709189 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2148 10:02:41.709294 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2149 10:02:41.709380 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2150 10:02:41.709443 742 |2 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
2151 10:02:41.709505 Byte0, DQ PI dly=728, DQM PI dly= 728
2152 10:02:41.709565 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
2153 10:02:41.709625
2154 10:02:41.709685 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
2155 10:02:41.709746
2156 10:02:41.709806 Byte1, DQ PI dly=723, DQM PI dly= 723
2157 10:02:41.709866 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
2158 10:02:41.709926
2159 10:02:41.709985 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
2160 10:02:41.710045
2161 10:02:41.710104 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2162 10:02:41.710165 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2163 10:02:41.710225 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2164 10:02:41.710285 Write Rank1 MR3 =0x30
2165 10:02:41.710345 DramC Write-DBI off
2166 10:02:41.710405
2167 10:02:41.710464 [DATLAT]
2168 10:02:41.710523 Freq=1600, CH0 RK1, use_rxtx_scan=0
2169 10:02:41.710583
2170 10:02:41.710643 DATLAT Default: 0x10
2171 10:02:41.710703 7, 0xFFFF, sum=0
2172 10:02:41.710763 8, 0xFFFF, sum=0
2173 10:02:41.710825 9, 0xFFFF, sum=0
2174 10:02:41.710908 10, 0xFFFF, sum=0
2175 10:02:41.710975 11, 0xFFFF, sum=0
2176 10:02:41.711036 12, 0xFFFF, sum=0
2177 10:02:41.711096 13, 0xFFFF, sum=0
2178 10:02:41.711156 14, 0x0, sum=1
2179 10:02:41.711216 15, 0x0, sum=2
2180 10:02:41.711275 16, 0x0, sum=3
2181 10:02:41.711335 17, 0x0, sum=4
2182 10:02:41.711395 pattern=2 first_step=14 total pass=5 best_step=16
2183 10:02:41.711464 ==
2184 10:02:41.711524 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2185 10:02:41.711585 fsp= 1, odt_onoff= 1, Byte mode= 0
2186 10:02:41.711645 ==
2187 10:02:41.711705 Start DQ dly to find pass range UseTestEngine =1
2188 10:02:41.711765 x-axis: bit #, y-axis: DQ dly (-127~63)
2189 10:02:41.712018 RX Vref Scan = 0
2190 10:02:41.712084 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2191 10:02:41.712146 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2192 10:02:41.712208 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2193 10:02:41.712269 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2194 10:02:41.712329 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2195 10:02:41.712390 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2196 10:02:41.712451 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2197 10:02:41.712511 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2198 10:02:41.712572 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2199 10:02:41.712632 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2200 10:02:41.712692 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2201 10:02:41.712752 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2202 10:02:41.712813 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2203 10:02:41.712880 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2204 10:02:41.712941 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2205 10:02:41.713002 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2206 10:02:41.713062 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2207 10:02:41.713123 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2208 10:02:41.713183 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2209 10:02:41.713243 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2210 10:02:41.713303 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2211 10:02:41.713363 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2212 10:02:41.713423 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2213 10:02:41.713483 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2214 10:02:41.713543 -2, [0] xxxoxxxx oxxoxxxx [MSB]
2215 10:02:41.713604 -1, [0] xxxoxxxx oxxoxxxx [MSB]
2216 10:02:41.713664 0, [0] xxxoxxxx oxxoxxxx [MSB]
2217 10:02:41.713725 1, [0] xxxoxoxx ooxooxxx [MSB]
2218 10:02:41.713785 2, [0] xxxoxoxx ooxoooox [MSB]
2219 10:02:41.713845 3, [0] xxxoxooo ooxoooox [MSB]
2220 10:02:41.713905 4, [0] xxxoxooo ooxoooox [MSB]
2221 10:02:41.713965 5, [0] xoxooooo ooxoooox [MSB]
2222 10:02:41.714025 6, [0] oooooooo ooxooooo [MSB]
2223 10:02:41.714084 33, [0] oooooooo xooooooo [MSB]
2224 10:02:41.714145 34, [0] oooxoooo xooooooo [MSB]
2225 10:02:41.714205 35, [0] oooxoxoo xooxoooo [MSB]
2226 10:02:41.714265 36, [0] oooxoxoo xooxoxoo [MSB]
2227 10:02:41.714325 37, [0] oooxoxoo xxoxoxoo [MSB]
2228 10:02:41.714385 38, [0] oooxoxxo xxoxxxxo [MSB]
2229 10:02:41.714445 39, [0] oxxxoxxx xxoxxxxo [MSB]
2230 10:02:41.714504 40, [0] oxxxxxxx xxoxxxxx [MSB]
2231 10:02:41.714565 41, [0] xxxxxxxx xxoxxxxx [MSB]
2232 10:02:41.714624 42, [0] xxxxxxxx xxoxxxxx [MSB]
2233 10:02:41.714684 43, [0] xxxxxxxx xxoxxxxx [MSB]
2234 10:02:41.714745 44, [0] xxxxxxxx xxxxxxxx [MSB]
2235 10:02:41.714804 iDelay=44, Bit 0, Center 23 (6 ~ 40) 35
2236 10:02:41.714886 iDelay=44, Bit 1, Center 21 (5 ~ 38) 34
2237 10:02:41.714988 iDelay=44, Bit 2, Center 22 (6 ~ 38) 33
2238 10:02:41.715052 iDelay=44, Bit 3, Center 15 (-2 ~ 33) 36
2239 10:02:41.715113 iDelay=44, Bit 4, Center 22 (5 ~ 39) 35
2240 10:02:41.715174 iDelay=44, Bit 5, Center 17 (1 ~ 34) 34
2241 10:02:41.715234 iDelay=44, Bit 6, Center 20 (3 ~ 37) 35
2242 10:02:41.715294 iDelay=44, Bit 7, Center 20 (3 ~ 38) 36
2243 10:02:41.715353 iDelay=44, Bit 8, Center 15 (-2 ~ 32) 35
2244 10:02:41.715431 iDelay=44, Bit 9, Center 18 (1 ~ 36) 36
2245 10:02:41.715494 iDelay=44, Bit 10, Center 25 (7 ~ 43) 37
2246 10:02:41.715554 iDelay=44, Bit 11, Center 16 (-2 ~ 34) 37
2247 10:02:41.715614 iDelay=44, Bit 12, Center 19 (1 ~ 37) 37
2248 10:02:41.715673 iDelay=44, Bit 13, Center 18 (2 ~ 35) 34
2249 10:02:41.715732 iDelay=44, Bit 14, Center 19 (2 ~ 37) 36
2250 10:02:41.715791 iDelay=44, Bit 15, Center 22 (6 ~ 39) 34
2251 10:02:41.715850 ==
2252 10:02:41.715911 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2253 10:02:41.715971 fsp= 1, odt_onoff= 1, Byte mode= 0
2254 10:02:41.716032 ==
2255 10:02:41.716092 DQS Delay:
2256 10:02:41.716151 DQS0 = 0, DQS1 = 0
2257 10:02:41.716210 DQM Delay:
2258 10:02:41.716269 DQM0 = 20, DQM1 = 19
2259 10:02:41.716329 DQ Delay:
2260 10:02:41.716388 DQ0 =23, DQ1 =21, DQ2 =22, DQ3 =15
2261 10:02:41.716448 DQ4 =22, DQ5 =17, DQ6 =20, DQ7 =20
2262 10:02:41.716508 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =16
2263 10:02:41.716568 DQ12 =19, DQ13 =18, DQ14 =19, DQ15 =22
2264 10:02:41.716627
2265 10:02:41.716687
2266 10:02:41.716746
2267 10:02:41.716805 [DramC_TX_OE_Calibration] TA2
2268 10:02:41.716864 Original DQ_B0 (3 6) =30, OEN = 27
2269 10:02:41.716924 Original DQ_B1 (3 6) =30, OEN = 27
2270 10:02:41.716983 23, 0x0, End_B0=23 End_B1=23
2271 10:02:41.717044 24, 0x0, End_B0=24 End_B1=24
2272 10:02:41.717104 25, 0x0, End_B0=25 End_B1=25
2273 10:02:41.717164 26, 0x0, End_B0=26 End_B1=26
2274 10:02:41.717224 27, 0x0, End_B0=27 End_B1=27
2275 10:02:41.717299 28, 0x0, End_B0=28 End_B1=28
2276 10:02:41.717363 29, 0x0, End_B0=29 End_B1=29
2277 10:02:41.717424 30, 0x0, End_B0=30 End_B1=30
2278 10:02:41.720903 31, 0xFFFF, End_B0=30 End_B1=30
2279 10:02:41.727976 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2280 10:02:41.734118 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2281 10:02:41.734631
2282 10:02:41.734966
2283 10:02:41.735375 Write Rank1 MR23 =0x3f
2284 10:02:41.737442 [DQSOSC]
2285 10:02:41.744811 [DQSOSCAuto] RK1, (LSB)MR18= 0xd9d9, (MSB)MR19= 0x202, tDQSOscB0 = 432 ps tDQSOscB1 = 432 ps
2286 10:02:41.751166 CH0_RK1: MR19=0x202, MR18=0xD9D9, DQSOSC=432, MR23=63, INC=13, DEC=19
2287 10:02:41.751907 Write Rank1 MR23 =0x3f
2288 10:02:41.754129 [DQSOSC]
2289 10:02:41.760897 [DQSOSCAuto] RK1, (LSB)MR18= 0xd6d6, (MSB)MR19= 0x202, tDQSOscB0 = 433 ps tDQSOscB1 = 433 ps
2290 10:02:41.764972 CH0 RK1: MR19=202, MR18=D6D6
2291 10:02:41.767928 [RxdqsGatingPostProcess] freq 1600
2292 10:02:41.771242 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2293 10:02:41.774455 Rank: 0
2294 10:02:41.777594 best DQS0 dly(2T, 0.5T) = (2, 5)
2295 10:02:41.778016 best DQS1 dly(2T, 0.5T) = (2, 5)
2296 10:02:41.781508 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2297 10:02:41.784665 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2298 10:02:41.788119 Rank: 1
2299 10:02:41.788699 best DQS0 dly(2T, 0.5T) = (2, 6)
2300 10:02:41.791607 best DQS1 dly(2T, 0.5T) = (2, 6)
2301 10:02:41.794581 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2302 10:02:41.797517 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2303 10:02:41.804744 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2304 10:02:41.808103 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2305 10:02:41.811383 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2306 10:02:41.814925 Write Rank0 MR13 =0x59
2307 10:02:41.815497 ==
2308 10:02:41.818121 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2309 10:02:41.821658 fsp= 1, odt_onoff= 1, Byte mode= 0
2310 10:02:41.822177 ==
2311 10:02:41.824778 === u2Vref_new: 0x56 --> 0x3a
2312 10:02:41.828040 === u2Vref_new: 0x58 --> 0x58
2313 10:02:41.831646 === u2Vref_new: 0x5a --> 0x5a
2314 10:02:41.835014 === u2Vref_new: 0x5c --> 0x78
2315 10:02:41.838355 === u2Vref_new: 0x5e --> 0x7a
2316 10:02:41.841656 === u2Vref_new: 0x60 --> 0x90
2317 10:02:41.844713 [CA 0] Center 38 (13~63) winsize 51
2318 10:02:41.848358 [CA 1] Center 37 (12~63) winsize 52
2319 10:02:41.852107 [CA 2] Center 34 (6~63) winsize 58
2320 10:02:41.854889 [CA 3] Center 34 (6~63) winsize 58
2321 10:02:41.855500 [CA 4] Center 35 (7~63) winsize 57
2322 10:02:41.858149 [CA 5] Center 28 (-2~58) winsize 61
2323 10:02:41.858627
2324 10:02:41.864881 [CATrainingPosCal] consider 1 rank data
2325 10:02:41.865409 u2DelayCellTimex100 = 735/100 ps
2326 10:02:41.871448 CA0 delay=38 (13~63),Diff = 10 PI (13 cell)
2327 10:02:41.874727 CA1 delay=37 (12~63),Diff = 9 PI (11 cell)
2328 10:02:41.878369 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2329 10:02:41.881674 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2330 10:02:41.884835 CA4 delay=35 (7~63),Diff = 7 PI (9 cell)
2331 10:02:41.888117 CA5 delay=28 (-2~58),Diff = 0 PI (0 cell)
2332 10:02:41.888764
2333 10:02:41.891594 CA PerBit enable=1, Macro0, CA PI delay=28
2334 10:02:41.894661 === u2Vref_new: 0x60 --> 0x90
2335 10:02:41.895125
2336 10:02:41.898212 Vref(ca) range 1: 32
2337 10:02:41.898727
2338 10:02:41.899059 CS Dly= 11 (42-0-32)
2339 10:02:41.901114 Write Rank0 MR13 =0xd8
2340 10:02:41.904680 Write Rank0 MR13 =0xd8
2341 10:02:41.905097 Write Rank0 MR12 =0x60
2342 10:02:41.908215 Write Rank1 MR13 =0x59
2343 10:02:41.908633 ==
2344 10:02:41.911602 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2345 10:02:41.914942 fsp= 1, odt_onoff= 1, Byte mode= 0
2346 10:02:41.915363 ==
2347 10:02:41.918267 === u2Vref_new: 0x56 --> 0x3a
2348 10:02:41.921710 === u2Vref_new: 0x58 --> 0x58
2349 10:02:41.925100 === u2Vref_new: 0x5a --> 0x5a
2350 10:02:41.928257 === u2Vref_new: 0x5c --> 0x78
2351 10:02:41.931456 === u2Vref_new: 0x5e --> 0x7a
2352 10:02:41.934512 === u2Vref_new: 0x60 --> 0x90
2353 10:02:41.937740 [CA 0] Center 38 (13~63) winsize 51
2354 10:02:41.941493 [CA 1] Center 37 (12~63) winsize 52
2355 10:02:41.944312 [CA 2] Center 35 (7~63) winsize 57
2356 10:02:41.948239 [CA 3] Center 34 (6~63) winsize 58
2357 10:02:41.950999 [CA 4] Center 35 (7~63) winsize 57
2358 10:02:41.954286 [CA 5] Center 27 (-3~57) winsize 61
2359 10:02:41.954400
2360 10:02:41.957689 [CATrainingPosCal] consider 2 rank data
2361 10:02:41.961518 u2DelayCellTimex100 = 735/100 ps
2362 10:02:41.964728 CA0 delay=38 (13~63),Diff = 11 PI (14 cell)
2363 10:02:41.968117 CA1 delay=37 (12~63),Diff = 10 PI (13 cell)
2364 10:02:41.971414 CA2 delay=35 (7~63),Diff = 8 PI (10 cell)
2365 10:02:41.974958 CA3 delay=34 (6~63),Diff = 7 PI (9 cell)
2366 10:02:41.977878 CA4 delay=35 (7~63),Diff = 8 PI (10 cell)
2367 10:02:41.981327 CA5 delay=27 (-2~57),Diff = 0 PI (0 cell)
2368 10:02:41.981455
2369 10:02:41.984797 CA PerBit enable=1, Macro0, CA PI delay=27
2370 10:02:41.988137 === u2Vref_new: 0x5e --> 0x7a
2371 10:02:41.988229
2372 10:02:41.991089 Vref(ca) range 1: 30
2373 10:02:41.991181
2374 10:02:41.994507 CS Dly= 12 (43-0-32)
2375 10:02:41.994598 Write Rank1 MR13 =0xd8
2376 10:02:41.998093 Write Rank1 MR13 =0xd8
2377 10:02:41.998261 Write Rank1 MR12 =0x5e
2378 10:02:42.004636 [RankSwap] Rank num 2, (Multi 1), Rank 0
2379 10:02:42.004823 Write Rank0 MR2 =0xad
2380 10:02:42.007676 [Write Leveling]
2381 10:02:42.011200 delay byte0 byte1 byte2 byte3
2382 10:02:42.011365
2383 10:02:42.011486 10 0 0
2384 10:02:42.011583 11 0 0
2385 10:02:42.014415 12 0 0
2386 10:02:42.014619 13 0 0
2387 10:02:42.018125 14 0 0
2388 10:02:42.018297 15 0 0
2389 10:02:42.018397 16 0 0
2390 10:02:42.021281 17 0 0
2391 10:02:42.021475 18 0 0
2392 10:02:42.024586 19 0 0
2393 10:02:42.024733 20 0 0
2394 10:02:42.028008 21 0 0
2395 10:02:42.028154 22 0 0
2396 10:02:42.028269 23 0 0
2397 10:02:42.031355 24 0 ff
2398 10:02:42.031544 25 0 ff
2399 10:02:42.034778 26 0 ff
2400 10:02:42.035055 27 0 ff
2401 10:02:42.038327 28 0 ff
2402 10:02:42.038603 29 0 ff
2403 10:02:42.038789 30 0 ff
2404 10:02:42.041387 31 0 ff
2405 10:02:42.041709 32 0 ff
2406 10:02:42.044809 33 ff ff
2407 10:02:42.045088 34 ff ff
2408 10:02:42.048169 35 ff ff
2409 10:02:42.048536 36 ff ff
2410 10:02:42.051545 37 ff ff
2411 10:02:42.051992 38 ff ff
2412 10:02:42.055143 39 ff ff
2413 10:02:42.058786 pass bytecount = 0xff (0xff: all bytes pass)
2414 10:02:42.059294
2415 10:02:42.059684 DQS0 dly: 33
2416 10:02:42.061860 DQS1 dly: 24
2417 10:02:42.062269 Write Rank0 MR2 =0x2d
2418 10:02:42.065143 [RankSwap] Rank num 2, (Multi 1), Rank 0
2419 10:02:42.068251 Write Rank0 MR1 =0xd6
2420 10:02:42.068664 [Gating]
2421 10:02:42.068989 ==
2422 10:02:42.075175 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2423 10:02:42.078610 fsp= 1, odt_onoff= 1, Byte mode= 0
2424 10:02:42.079122 ==
2425 10:02:42.082241 3 1 0 |e0e 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2426 10:02:42.085574 3 1 4 |1919 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2427 10:02:42.092310 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2428 10:02:42.095592 3 1 12 |3635 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2429 10:02:42.098818 3 1 16 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
2430 10:02:42.101961 3 1 20 |3534 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2431 10:02:42.108706 [Byte 1] Lead/lag falling Transition (3, 1, 20)
2432 10:02:42.111542 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2433 10:02:42.115134 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2434 10:02:42.121930 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2435 10:02:42.125390 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2436 10:02:42.128403 3 2 8 |3434 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2437 10:02:42.135118 3 2 12 |3434 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2438 10:02:42.138975 3 2 16 |807 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2439 10:02:42.142073 [Byte 1] Lead/lag Transition tap number (8)
2440 10:02:42.145686 3 2 20 |201 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
2441 10:02:42.152063 3 2 24 |2221 302 |(11 11)(11 11) |(1 1)(0 0)| 0
2442 10:02:42.155636 3 2 28 |3d3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2443 10:02:42.158616 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2444 10:02:42.161667 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2445 10:02:42.168977 3 3 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2446 10:02:42.172265 3 3 12 |3d3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2447 10:02:42.175663 3 3 16 |1a1a 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2448 10:02:42.182499 3 3 20 |b0a 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2449 10:02:42.185553 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2450 10:02:42.189008 [Byte 0] Lead/lag falling Transition (3, 3, 24)
2451 10:02:42.195158 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2452 10:02:42.198847 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2453 10:02:42.202498 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2454 10:02:42.205460 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2455 10:02:42.211928 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2456 10:02:42.215320 3 4 16 |504 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2457 10:02:42.219189 3 4 20 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2458 10:02:42.226529 3 4 24 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
2459 10:02:42.228814 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2460 10:02:42.231850 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2461 10:02:42.238741 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2462 10:02:42.242463 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2463 10:02:42.245307 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2464 10:02:42.248820 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2465 10:02:42.255311 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2466 10:02:42.258486 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2467 10:02:42.261933 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2468 10:02:42.268612 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2469 10:02:42.272211 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2470 10:02:42.275167 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2471 10:02:42.281805 [Byte 0] Lead/lag falling Transition (3, 6, 8)
2472 10:02:42.284959 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2473 10:02:42.288447 [Byte 0] Lead/lag Transition tap number (2)
2474 10:02:42.291840 3 6 16 |1e1e 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2475 10:02:42.297890 [Byte 1] Lead/lag falling Transition (3, 6, 16)
2476 10:02:42.301787 3 6 20 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2477 10:02:42.304500 [Byte 1] Lead/lag Transition tap number (2)
2478 10:02:42.307898 3 6 24 |4646 403 |(0 0)(11 11) |(0 0)(0 0)| 0
2479 10:02:42.311706 [Byte 0]First pass (3, 6, 24)
2480 10:02:42.314433 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2481 10:02:42.317815 [Byte 1]First pass (3, 6, 28)
2482 10:02:42.321241 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2483 10:02:42.327827 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2484 10:02:42.331353 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2485 10:02:42.334615 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2486 10:02:42.337809 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2487 10:02:42.341304 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2488 10:02:42.348230 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2489 10:02:42.351589 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2490 10:02:42.355019 All bytes gating window > 1UI, Early break!
2491 10:02:42.355132
2492 10:02:42.358151 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
2493 10:02:42.358242
2494 10:02:42.361449 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 20)
2495 10:02:42.361540
2496 10:02:42.361614
2497 10:02:42.361681
2498 10:02:42.368133 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
2499 10:02:42.368300
2500 10:02:42.371333 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 20)
2501 10:02:42.371476
2502 10:02:42.371563
2503 10:02:42.374635 Write Rank0 MR1 =0x56
2504 10:02:42.374813
2505 10:02:42.374903 best RODT dly(2T, 0.5T) = (2, 3)
2506 10:02:42.377669
2507 10:02:42.377849 best RODT dly(2T, 0.5T) = (2, 3)
2508 10:02:42.381615 ==
2509 10:02:42.384708 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2510 10:02:42.387944 fsp= 1, odt_onoff= 1, Byte mode= 0
2511 10:02:42.388119 ==
2512 10:02:42.391563 Start DQ dly to find pass range UseTestEngine =0
2513 10:02:42.395068 x-axis: bit #, y-axis: DQ dly (-127~63)
2514 10:02:42.398529 RX Vref Scan = 0
2515 10:02:42.401810 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2516 10:02:42.405299 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2517 10:02:42.405577 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2518 10:02:42.408266 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2519 10:02:42.411691 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2520 10:02:42.414777 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2521 10:02:42.417952 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2522 10:02:42.421484 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2523 10:02:42.425076 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2524 10:02:42.428327 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2525 10:02:42.428854 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2526 10:02:42.431538 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2527 10:02:42.435112 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2528 10:02:42.438451 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2529 10:02:42.441564 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2530 10:02:42.444877 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2531 10:02:42.448256 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2532 10:02:42.451737 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2533 10:02:42.452269 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2534 10:02:42.454741 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2535 10:02:42.458748 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2536 10:02:42.461588 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2537 10:02:42.465008 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2538 10:02:42.468410 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2539 10:02:42.471758 -2, [0] xxxxxxxx xoxxxxxo [MSB]
2540 10:02:42.472192 -1, [0] xxxxxxxx xoxxxxxo [MSB]
2541 10:02:42.475327 0, [0] xxxoxxxx ooxxxxxo [MSB]
2542 10:02:42.478234 1, [0] xxooxxxx ooxxxxxo [MSB]
2543 10:02:42.481528 2, [0] xxooxxxx oooxxxxo [MSB]
2544 10:02:42.484882 3, [0] xxooxxxo oooxxxxo [MSB]
2545 10:02:42.488363 4, [0] oxooxxxo oooxxxxo [MSB]
2546 10:02:42.488928 5, [0] oooooxoo ooooooxo [MSB]
2547 10:02:42.492067 31, [0] oooooooo ooooooox [MSB]
2548 10:02:42.494944 32, [0] oooooooo ooooooox [MSB]
2549 10:02:42.498081 33, [0] oooooooo ooooooox [MSB]
2550 10:02:42.501260 34, [0] oooooooo ooooooox [MSB]
2551 10:02:42.504590 35, [0] oooxoooo xxooooox [MSB]
2552 10:02:42.507724 36, [0] oooxoooo xxooooox [MSB]
2553 10:02:42.511250 37, [0] ooxxoooo xxooooox [MSB]
2554 10:02:42.511919 38, [0] ooxxoooo xxooooox [MSB]
2555 10:02:42.514581 39, [0] ooxxooox xxooooox [MSB]
2556 10:02:42.517777 40, [0] oxxxxoox xxxoooox [MSB]
2557 10:02:42.521359 41, [0] xxxxxoox xxxxxxxx [MSB]
2558 10:02:42.524700 42, [0] xxxxxoxx xxxxxxxx [MSB]
2559 10:02:42.527910 43, [0] xxxxxxxx xxxxxxxx [MSB]
2560 10:02:42.531196 iDelay=43, Bit 0, Center 22 (4 ~ 40) 37
2561 10:02:42.533980 iDelay=43, Bit 1, Center 22 (5 ~ 39) 35
2562 10:02:42.537206 iDelay=43, Bit 2, Center 18 (1 ~ 36) 36
2563 10:02:42.540661 iDelay=43, Bit 3, Center 17 (0 ~ 34) 35
2564 10:02:42.544031 iDelay=43, Bit 4, Center 22 (5 ~ 39) 35
2565 10:02:42.547301 iDelay=43, Bit 5, Center 24 (6 ~ 42) 37
2566 10:02:42.550675 iDelay=43, Bit 6, Center 23 (5 ~ 41) 37
2567 10:02:42.554266 iDelay=43, Bit 7, Center 20 (3 ~ 38) 36
2568 10:02:42.557443 iDelay=43, Bit 8, Center 17 (0 ~ 34) 35
2569 10:02:42.560484 iDelay=43, Bit 9, Center 16 (-2 ~ 34) 37
2570 10:02:42.564155 iDelay=43, Bit 10, Center 20 (2 ~ 39) 38
2571 10:02:42.567271 iDelay=43, Bit 11, Center 22 (5 ~ 40) 36
2572 10:02:42.574373 iDelay=43, Bit 12, Center 22 (5 ~ 40) 36
2573 10:02:42.577203 iDelay=43, Bit 13, Center 22 (5 ~ 40) 36
2574 10:02:42.580592 iDelay=43, Bit 14, Center 23 (6 ~ 40) 35
2575 10:02:42.584036 iDelay=43, Bit 15, Center 13 (-3 ~ 30) 34
2576 10:02:42.584195 ==
2577 10:02:42.587223 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2578 10:02:42.590490 fsp= 1, odt_onoff= 1, Byte mode= 0
2579 10:02:42.590673 ==
2580 10:02:42.594154 DQS Delay:
2581 10:02:42.594366 DQS0 = 0, DQS1 = 0
2582 10:02:42.597933 DQM Delay:
2583 10:02:42.598147 DQM0 = 21, DQM1 = 19
2584 10:02:42.598318 DQ Delay:
2585 10:02:42.600551 DQ0 =22, DQ1 =22, DQ2 =18, DQ3 =17
2586 10:02:42.603875 DQ4 =22, DQ5 =24, DQ6 =23, DQ7 =20
2587 10:02:42.607532 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =22
2588 10:02:42.610980 DQ12 =22, DQ13 =22, DQ14 =23, DQ15 =13
2589 10:02:42.611462
2590 10:02:42.611820
2591 10:02:42.614098 DramC Write-DBI off
2592 10:02:42.614532 ==
2593 10:02:42.620602 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2594 10:02:42.623928 fsp= 1, odt_onoff= 1, Byte mode= 0
2595 10:02:42.624349 ==
2596 10:02:42.627538 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2597 10:02:42.627959
2598 10:02:42.630731 Begin, DQ Scan Range 920~1176
2599 10:02:42.631152
2600 10:02:42.631520
2601 10:02:42.631840 TX Vref Scan disable
2602 10:02:42.637417 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
2603 10:02:42.640820 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
2604 10:02:42.644223 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
2605 10:02:42.647742 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
2606 10:02:42.650718 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
2607 10:02:42.654262 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
2608 10:02:42.657391 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
2609 10:02:42.660883 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2610 10:02:42.663892 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2611 10:02:42.667302 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2612 10:02:42.670370 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2613 10:02:42.673775 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2614 10:02:42.677066 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2615 10:02:42.680362 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2616 10:02:42.683798 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2617 10:02:42.690799 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2618 10:02:42.694147 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2619 10:02:42.697454 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2620 10:02:42.700755 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2621 10:02:42.704169 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2622 10:02:42.707176 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2623 10:02:42.710114 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2624 10:02:42.713569 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2625 10:02:42.716848 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2626 10:02:42.720204 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2627 10:02:42.723375 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2628 10:02:42.727028 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2629 10:02:42.730149 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2630 10:02:42.733086 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2631 10:02:42.740075 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2632 10:02:42.743265 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2633 10:02:42.746290 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2634 10:02:42.749754 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2635 10:02:42.753131 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2636 10:02:42.756952 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2637 10:02:42.760239 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2638 10:02:42.763506 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2639 10:02:42.766789 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2640 10:02:42.770453 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2641 10:02:42.773681 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2642 10:02:42.776817 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2643 10:02:42.779603 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2644 10:02:42.783078 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2645 10:02:42.786549 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2646 10:02:42.789689 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2647 10:02:42.793278 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2648 10:02:42.796267 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2649 10:02:42.803174 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2650 10:02:42.806628 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2651 10:02:42.809663 969 |3 6 9|[0] xxxxxxxx xxxxxxxo [MSB]
2652 10:02:42.813173 970 |3 6 10|[0] xxxxxxxx ooxxxxxo [MSB]
2653 10:02:42.816190 971 |3 6 11|[0] xxxxxxxx ooxxxxxo [MSB]
2654 10:02:42.819867 972 |3 6 12|[0] xxxxxxxx ooxxxxoo [MSB]
2655 10:02:42.823273 973 |3 6 13|[0] xxxxxxxx oooxoxoo [MSB]
2656 10:02:42.826584 974 |3 6 14|[0] xxxxxxxx oooooxoo [MSB]
2657 10:02:42.829943 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
2658 10:02:42.832747 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
2659 10:02:42.836345 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
2660 10:02:42.839653 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
2661 10:02:42.843238 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
2662 10:02:42.846140 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
2663 10:02:42.849859 981 |3 6 21|[0] xooooxoo oooooooo [MSB]
2664 10:02:42.852791 982 |3 6 22|[0] oooooxoo oooooooo [MSB]
2665 10:02:42.859628 986 |3 6 26|[0] oooooooo ooooooox [MSB]
2666 10:02:42.862951 987 |3 6 27|[0] oooooooo ooooooox [MSB]
2667 10:02:42.866358 988 |3 6 28|[0] oooooooo oxooooox [MSB]
2668 10:02:42.869421 989 |3 6 29|[0] oooooooo xxooooox [MSB]
2669 10:02:42.872774 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
2670 10:02:42.876356 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
2671 10:02:42.879602 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2672 10:02:42.883167 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2673 10:02:42.886200 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2674 10:02:42.889589 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
2675 10:02:42.893230 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
2676 10:02:42.896041 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
2677 10:02:42.899935 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
2678 10:02:42.902758 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
2679 10:02:42.906001 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
2680 10:02:42.912935 1001 |3 6 41|[0] oxxxoooo xxxxxxxx [MSB]
2681 10:02:42.915954 1002 |3 6 42|[0] oxxxxxxx xxxxxxxx [MSB]
2682 10:02:42.919616 1003 |3 6 43|[0] xxxxxxxx xxxxxxxx [MSB]
2683 10:02:42.922939 Byte0, DQ PI dly=990, DQM PI dly= 990
2684 10:02:42.926164 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 30)
2685 10:02:42.926717
2686 10:02:42.930055 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 30)
2687 10:02:42.930615
2688 10:02:42.932933 Byte1, DQ PI dly=979, DQM PI dly= 979
2689 10:02:42.939543 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2690 10:02:42.939966
2691 10:02:42.943118 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2692 10:02:42.943664
2693 10:02:42.943998 ==
2694 10:02:42.949639 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2695 10:02:42.952920 fsp= 1, odt_onoff= 1, Byte mode= 0
2696 10:02:42.953432 ==
2697 10:02:42.956164 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2698 10:02:42.956582
2699 10:02:42.959384 Begin, DQ Scan Range 955~1019
2700 10:02:42.959827 Write Rank0 MR14 =0x0
2701 10:02:42.969420
2702 10:02:42.969978 CH=1, VrefRange= 0, VrefLevel = 0
2703 10:02:42.976493 TX Bit0 (984~999) 16 991, Bit8 (972~984) 13 978,
2704 10:02:42.979805 TX Bit1 (983~996) 14 989, Bit9 (974~983) 10 978,
2705 10:02:42.986495 TX Bit2 (981~995) 15 988, Bit10 (975~986) 12 980,
2706 10:02:42.989734 TX Bit3 (980~992) 13 986, Bit11 (977~987) 11 982,
2707 10:02:42.992748 TX Bit4 (983~998) 16 990, Bit12 (976~987) 12 981,
2708 10:02:43.000015 TX Bit5 (985~998) 14 991, Bit13 (977~987) 11 982,
2709 10:02:43.002661 TX Bit6 (983~998) 16 990, Bit14 (975~986) 12 980,
2710 10:02:43.006340 TX Bit7 (983~996) 14 989, Bit15 (969~979) 11 974,
2711 10:02:43.006764
2712 10:02:43.009178 Write Rank0 MR14 =0x2
2713 10:02:43.018777
2714 10:02:43.019194 CH=1, VrefRange= 0, VrefLevel = 2
2715 10:02:43.025176 TX Bit0 (984~1000) 17 992, Bit8 (974~984) 11 979,
2716 10:02:43.028469 TX Bit1 (983~997) 15 990, Bit9 (973~983) 11 978,
2717 10:02:43.035162 TX Bit2 (981~996) 16 988, Bit10 (976~987) 12 981,
2718 10:02:43.038202 TX Bit3 (979~992) 14 985, Bit11 (975~987) 13 981,
2719 10:02:43.041744 TX Bit4 (982~998) 17 990, Bit12 (975~988) 14 981,
2720 10:02:43.048450 TX Bit5 (984~999) 16 991, Bit13 (976~989) 14 982,
2721 10:02:43.051820 TX Bit6 (983~998) 16 990, Bit14 (975~987) 13 981,
2722 10:02:43.055160 TX Bit7 (983~997) 15 990, Bit15 (969~980) 12 974,
2723 10:02:43.055291
2724 10:02:43.058176 Write Rank0 MR14 =0x4
2725 10:02:43.067274
2726 10:02:43.067377 CH=1, VrefRange= 0, VrefLevel = 4
2727 10:02:43.074084 TX Bit0 (984~1000) 17 992, Bit8 (972~985) 14 978,
2728 10:02:43.077564 TX Bit1 (982~998) 17 990, Bit9 (972~984) 13 978,
2729 10:02:43.083990 TX Bit2 (980~997) 18 988, Bit10 (976~988) 13 982,
2730 10:02:43.087102 TX Bit3 (979~993) 15 986, Bit11 (975~989) 15 982,
2731 10:02:43.090915 TX Bit4 (982~999) 18 990, Bit12 (975~988) 14 981,
2732 10:02:43.097598 TX Bit5 (984~999) 16 991, Bit13 (976~989) 14 982,
2733 10:02:43.100474 TX Bit6 (983~999) 17 991, Bit14 (974~988) 15 981,
2734 10:02:43.104125 TX Bit7 (983~998) 16 990, Bit15 (969~982) 14 975,
2735 10:02:43.104217
2736 10:02:43.107292 Write Rank0 MR14 =0x6
2737 10:02:43.116821
2738 10:02:43.116921 CH=1, VrefRange= 0, VrefLevel = 6
2739 10:02:43.123525 TX Bit0 (983~1001) 19 992, Bit8 (971~985) 15 978,
2740 10:02:43.126827 TX Bit1 (982~998) 17 990, Bit9 (972~984) 13 978,
2741 10:02:43.133390 TX Bit2 (980~998) 19 989, Bit10 (975~988) 14 981,
2742 10:02:43.136398 TX Bit3 (978~994) 17 986, Bit11 (975~990) 16 982,
2743 10:02:43.139771 TX Bit4 (982~999) 18 990, Bit12 (975~990) 16 982,
2744 10:02:43.146752 TX Bit5 (984~999) 16 991, Bit13 (976~990) 15 983,
2745 10:02:43.149854 TX Bit6 (983~999) 17 991, Bit14 (974~988) 15 981,
2746 10:02:43.153653 TX Bit7 (982~998) 17 990, Bit15 (969~983) 15 976,
2747 10:02:43.156577
2748 10:02:43.156668 Write Rank0 MR14 =0x8
2749 10:02:43.166025
2750 10:02:43.166118 CH=1, VrefRange= 0, VrefLevel = 8
2751 10:02:43.172635 TX Bit0 (983~1001) 19 992, Bit8 (971~985) 15 978,
2752 10:02:43.175717 TX Bit1 (982~998) 17 990, Bit9 (971~985) 15 978,
2753 10:02:43.182693 TX Bit2 (979~999) 21 989, Bit10 (974~990) 17 982,
2754 10:02:43.185930 TX Bit3 (978~995) 18 986, Bit11 (975~991) 17 983,
2755 10:02:43.189079 TX Bit4 (981~1000) 20 990, Bit12 (975~991) 17 983,
2756 10:02:43.195717 TX Bit5 (984~1000) 17 992, Bit13 (976~991) 16 983,
2757 10:02:43.198977 TX Bit6 (982~1000) 19 991, Bit14 (974~990) 17 982,
2758 10:02:43.205950 TX Bit7 (982~999) 18 990, Bit15 (968~983) 16 975,
2759 10:02:43.206045
2760 10:02:43.206118 Write Rank0 MR14 =0xa
2761 10:02:43.215524
2762 10:02:43.218700 CH=1, VrefRange= 0, VrefLevel = 10
2763 10:02:43.222117 TX Bit0 (983~1002) 20 992, Bit8 (971~986) 16 978,
2764 10:02:43.225717 TX Bit1 (981~999) 19 990, Bit9 (971~985) 15 978,
2765 10:02:43.232297 TX Bit2 (979~999) 21 989, Bit10 (973~990) 18 981,
2766 10:02:43.235826 TX Bit3 (978~996) 19 987, Bit11 (975~991) 17 983,
2767 10:02:43.238831 TX Bit4 (981~1000) 20 990, Bit12 (974~991) 18 982,
2768 10:02:43.245644 TX Bit5 (983~1001) 19 992, Bit13 (976~991) 16 983,
2769 10:02:43.248804 TX Bit6 (982~1000) 19 991, Bit14 (974~991) 18 982,
2770 10:02:43.255544 TX Bit7 (981~999) 19 990, Bit15 (968~984) 17 976,
2771 10:02:43.255636
2772 10:02:43.255708 Write Rank0 MR14 =0xc
2773 10:02:43.265894
2774 10:02:43.268772 CH=1, VrefRange= 0, VrefLevel = 12
2775 10:02:43.271869 TX Bit0 (983~1002) 20 992, Bit8 (970~987) 18 978,
2776 10:02:43.275588 TX Bit1 (980~1000) 21 990, Bit9 (970~985) 16 977,
2777 10:02:43.281950 TX Bit2 (978~999) 22 988, Bit10 (973~991) 19 982,
2778 10:02:43.285468 TX Bit3 (978~996) 19 987, Bit11 (975~991) 17 983,
2779 10:02:43.288711 TX Bit4 (981~1001) 21 991, Bit12 (973~992) 20 982,
2780 10:02:43.295658 TX Bit5 (983~1001) 19 992, Bit13 (975~991) 17 983,
2781 10:02:43.298756 TX Bit6 (981~1000) 20 990, Bit14 (972~991) 20 981,
2782 10:02:43.305192 TX Bit7 (981~1000) 20 990, Bit15 (968~984) 17 976,
2783 10:02:43.305290
2784 10:02:43.305363 Write Rank0 MR14 =0xe
2785 10:02:43.315427
2786 10:02:43.315555 CH=1, VrefRange= 0, VrefLevel = 14
2787 10:02:43.322064 TX Bit0 (982~1003) 22 992, Bit8 (970~988) 19 979,
2788 10:02:43.325563 TX Bit1 (980~1000) 21 990, Bit9 (970~986) 17 978,
2789 10:02:43.332144 TX Bit2 (978~1000) 23 989, Bit10 (973~991) 19 982,
2790 10:02:43.335483 TX Bit3 (977~997) 21 987, Bit11 (974~991) 18 982,
2791 10:02:43.339187 TX Bit4 (980~1001) 22 990, Bit12 (972~992) 21 982,
2792 10:02:43.345380 TX Bit5 (983~1001) 19 992, Bit13 (975~992) 18 983,
2793 10:02:43.348530 TX Bit6 (981~1001) 21 991, Bit14 (973~991) 19 982,
2794 10:02:43.355570 TX Bit7 (980~1000) 21 990, Bit15 (968~985) 18 976,
2795 10:02:43.355692
2796 10:02:43.355797 Write Rank0 MR14 =0x10
2797 10:02:43.366082
2798 10:02:43.366176 CH=1, VrefRange= 0, VrefLevel = 16
2799 10:02:43.372684 TX Bit0 (981~1003) 23 992, Bit8 (970~989) 20 979,
2800 10:02:43.375798 TX Bit1 (979~1001) 23 990, Bit9 (970~987) 18 978,
2801 10:02:43.382273 TX Bit2 (978~1000) 23 989, Bit10 (972~992) 21 982,
2802 10:02:43.385587 TX Bit3 (977~998) 22 987, Bit11 (974~992) 19 983,
2803 10:02:43.388931 TX Bit4 (980~1002) 23 991, Bit12 (973~992) 20 982,
2804 10:02:43.395180 TX Bit5 (983~1001) 19 992, Bit13 (975~992) 18 983,
2805 10:02:43.399005 TX Bit6 (980~1001) 22 990, Bit14 (972~992) 21 982,
2806 10:02:43.405162 TX Bit7 (980~1000) 21 990, Bit15 (968~985) 18 976,
2807 10:02:43.405254
2808 10:02:43.405327 Write Rank0 MR14 =0x12
2809 10:02:43.416115
2810 10:02:43.419409 CH=1, VrefRange= 0, VrefLevel = 18
2811 10:02:43.423071 TX Bit0 (981~1003) 23 992, Bit8 (970~990) 21 980,
2812 10:02:43.426298 TX Bit1 (979~1001) 23 990, Bit9 (970~987) 18 978,
2813 10:02:43.432756 TX Bit2 (978~1000) 23 989, Bit10 (972~992) 21 982,
2814 10:02:43.436068 TX Bit3 (977~998) 22 987, Bit11 (973~992) 20 982,
2815 10:02:43.439300 TX Bit4 (979~1002) 24 990, Bit12 (972~993) 22 982,
2816 10:02:43.445858 TX Bit5 (982~1002) 21 992, Bit13 (974~992) 19 983,
2817 10:02:43.449121 TX Bit6 (980~1001) 22 990, Bit14 (972~992) 21 982,
2818 10:02:43.455901 TX Bit7 (980~1001) 22 990, Bit15 (967~986) 20 976,
2819 10:02:43.455996
2820 10:02:43.456070 Write Rank0 MR14 =0x14
2821 10:02:43.466359
2822 10:02:43.470259 CH=1, VrefRange= 0, VrefLevel = 20
2823 10:02:43.473322 TX Bit0 (982~1004) 23 993, Bit8 (969~990) 22 979,
2824 10:02:43.476708 TX Bit1 (979~1001) 23 990, Bit9 (970~988) 19 979,
2825 10:02:43.483362 TX Bit2 (978~1001) 24 989, Bit10 (971~992) 22 981,
2826 10:02:43.486291 TX Bit3 (977~999) 23 988, Bit11 (972~993) 22 982,
2827 10:02:43.490162 TX Bit4 (979~1002) 24 990, Bit12 (972~993) 22 982,
2828 10:02:43.496749 TX Bit5 (982~1003) 22 992, Bit13 (974~993) 20 983,
2829 10:02:43.499778 TX Bit6 (980~1002) 23 991, Bit14 (971~992) 22 981,
2830 10:02:43.506784 TX Bit7 (980~1001) 22 990, Bit15 (967~986) 20 976,
2831 10:02:43.507250
2832 10:02:43.507618 Write Rank0 MR14 =0x16
2833 10:02:43.517246
2834 10:02:43.517661 CH=1, VrefRange= 0, VrefLevel = 22
2835 10:02:43.524220 TX Bit0 (980~1004) 25 992, Bit8 (969~990) 22 979,
2836 10:02:43.528031 TX Bit1 (979~1002) 24 990, Bit9 (970~989) 20 979,
2837 10:02:43.533944 TX Bit2 (978~1001) 24 989, Bit10 (971~992) 22 981,
2838 10:02:43.537412 TX Bit3 (977~999) 23 988, Bit11 (971~993) 23 982,
2839 10:02:43.540944 TX Bit4 (979~1003) 25 991, Bit12 (971~994) 24 982,
2840 10:02:43.547296 TX Bit5 (981~1004) 24 992, Bit13 (973~993) 21 983,
2841 10:02:43.550909 TX Bit6 (980~1002) 23 991, Bit14 (971~993) 23 982,
2842 10:02:43.557181 TX Bit7 (980~1002) 23 991, Bit15 (966~986) 21 976,
2843 10:02:43.557733
2844 10:02:43.558119 Write Rank0 MR14 =0x18
2845 10:02:43.568123
2846 10:02:43.571199 CH=1, VrefRange= 0, VrefLevel = 24
2847 10:02:43.574574 TX Bit0 (980~1005) 26 992, Bit8 (969~991) 23 980,
2848 10:02:43.578055 TX Bit1 (979~1003) 25 991, Bit9 (969~989) 21 979,
2849 10:02:43.584597 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2850 10:02:43.588153 TX Bit3 (977~999) 23 988, Bit11 (972~993) 22 982,
2851 10:02:43.591139 TX Bit4 (979~1004) 26 991, Bit12 (971~994) 24 982,
2852 10:02:43.598079 TX Bit5 (981~1004) 24 992, Bit13 (974~993) 20 983,
2853 10:02:43.600947 TX Bit6 (979~1003) 25 991, Bit14 (971~993) 23 982,
2854 10:02:43.607483 TX Bit7 (980~1003) 24 991, Bit15 (966~987) 22 976,
2855 10:02:43.608082
2856 10:02:43.608564 Write Rank0 MR14 =0x1a
2857 10:02:43.618355
2858 10:02:43.622005 CH=1, VrefRange= 0, VrefLevel = 26
2859 10:02:43.625468 TX Bit0 (980~1006) 27 993, Bit8 (969~991) 23 980,
2860 10:02:43.628338 TX Bit1 (979~1003) 25 991, Bit9 (969~990) 22 979,
2861 10:02:43.634904 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2862 10:02:43.638751 TX Bit3 (976~1000) 25 988, Bit11 (971~993) 23 982,
2863 10:02:43.641806 TX Bit4 (978~1004) 27 991, Bit12 (971~994) 24 982,
2864 10:02:43.649368 TX Bit5 (981~1004) 24 992, Bit13 (972~993) 22 982,
2865 10:02:43.652105 TX Bit6 (979~1004) 26 991, Bit14 (970~993) 24 981,
2866 10:02:43.658537 TX Bit7 (979~1003) 25 991, Bit15 (966~988) 23 977,
2867 10:02:43.658920
2868 10:02:43.659163 Write Rank0 MR14 =0x1c
2869 10:02:43.669297
2870 10:02:43.669541 CH=1, VrefRange= 0, VrefLevel = 28
2871 10:02:43.676134 TX Bit0 (979~1006) 28 992, Bit8 (969~992) 24 980,
2872 10:02:43.678987 TX Bit1 (978~1003) 26 990, Bit9 (969~990) 22 979,
2873 10:02:43.685945 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2874 10:02:43.689469 TX Bit3 (976~1000) 25 988, Bit11 (971~994) 24 982,
2875 10:02:43.692393 TX Bit4 (978~1005) 28 991, Bit12 (971~994) 24 982,
2876 10:02:43.699608 TX Bit5 (980~1005) 26 992, Bit13 (973~994) 22 983,
2877 10:02:43.702547 TX Bit6 (979~1004) 26 991, Bit14 (970~994) 25 982,
2878 10:02:43.709651 TX Bit7 (978~1004) 27 991, Bit15 (966~988) 23 977,
2879 10:02:43.709820
2880 10:02:43.709901 Write Rank0 MR14 =0x1e
2881 10:02:43.720093
2882 10:02:43.723302 CH=1, VrefRange= 0, VrefLevel = 30
2883 10:02:43.726979 TX Bit0 (979~1006) 28 992, Bit8 (968~992) 25 980,
2884 10:02:43.730633 TX Bit1 (978~1004) 27 991, Bit9 (969~991) 23 980,
2885 10:02:43.736589 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2886 10:02:43.740146 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2887 10:02:43.743236 TX Bit4 (979~1005) 27 992, Bit12 (970~994) 25 982,
2888 10:02:43.750212 TX Bit5 (980~1005) 26 992, Bit13 (973~994) 22 983,
2889 10:02:43.753461 TX Bit6 (979~1005) 27 992, Bit14 (970~993) 24 981,
2890 10:02:43.759832 TX Bit7 (978~1004) 27 991, Bit15 (966~988) 23 977,
2891 10:02:43.760117
2892 10:02:43.760289 Write Rank0 MR14 =0x20
2893 10:02:43.770950
2894 10:02:43.774446 CH=1, VrefRange= 0, VrefLevel = 32
2895 10:02:43.777717 TX Bit0 (979~1006) 28 992, Bit8 (968~991) 24 979,
2896 10:02:43.781366 TX Bit1 (978~1005) 28 991, Bit9 (969~991) 23 980,
2897 10:02:43.787764 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2898 10:02:43.791579 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2899 10:02:43.794626 TX Bit4 (979~1005) 27 992, Bit12 (971~993) 23 982,
2900 10:02:43.801269 TX Bit5 (980~1006) 27 993, Bit13 (972~994) 23 983,
2901 10:02:43.804294 TX Bit6 (978~1005) 28 991, Bit14 (971~993) 23 982,
2902 10:02:43.810983 TX Bit7 (978~1005) 28 991, Bit15 (965~987) 23 976,
2903 10:02:43.811600
2904 10:02:43.811982 Write Rank0 MR14 =0x22
2905 10:02:43.821983
2906 10:02:43.825730 CH=1, VrefRange= 0, VrefLevel = 34
2907 10:02:43.828481 TX Bit0 (979~1006) 28 992, Bit8 (968~991) 24 979,
2908 10:02:43.832253 TX Bit1 (978~1005) 28 991, Bit9 (969~991) 23 980,
2909 10:02:43.838637 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2910 10:02:43.842009 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2911 10:02:43.845872 TX Bit4 (979~1005) 27 992, Bit12 (971~993) 23 982,
2912 10:02:43.851698 TX Bit5 (980~1006) 27 993, Bit13 (972~994) 23 983,
2913 10:02:43.855589 TX Bit6 (978~1005) 28 991, Bit14 (971~993) 23 982,
2914 10:02:43.862169 TX Bit7 (978~1005) 28 991, Bit15 (965~987) 23 976,
2915 10:02:43.862734
2916 10:02:43.863101 Write Rank0 MR14 =0x24
2917 10:02:43.872661
2918 10:02:43.876159 CH=1, VrefRange= 0, VrefLevel = 36
2919 10:02:43.879692 TX Bit0 (979~1006) 28 992, Bit8 (968~991) 24 979,
2920 10:02:43.882594 TX Bit1 (978~1005) 28 991, Bit9 (969~991) 23 980,
2921 10:02:43.889137 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2922 10:02:43.892592 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2923 10:02:43.895741 TX Bit4 (979~1005) 27 992, Bit12 (971~993) 23 982,
2924 10:02:43.902728 TX Bit5 (980~1006) 27 993, Bit13 (972~994) 23 983,
2925 10:02:43.906423 TX Bit6 (978~1005) 28 991, Bit14 (971~993) 23 982,
2926 10:02:43.912627 TX Bit7 (978~1005) 28 991, Bit15 (965~987) 23 976,
2927 10:02:43.913148
2928 10:02:43.913514 Write Rank0 MR14 =0x26
2929 10:02:43.923734
2930 10:02:43.926872 CH=1, VrefRange= 0, VrefLevel = 38
2931 10:02:43.930376 TX Bit0 (979~1006) 28 992, Bit8 (968~991) 24 979,
2932 10:02:43.933490 TX Bit1 (978~1005) 28 991, Bit9 (969~991) 23 980,
2933 10:02:43.940148 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
2934 10:02:43.943498 TX Bit3 (976~1000) 25 988, Bit11 (970~994) 25 982,
2935 10:02:43.946760 TX Bit4 (979~1005) 27 992, Bit12 (971~993) 23 982,
2936 10:02:43.954080 TX Bit5 (980~1006) 27 993, Bit13 (972~994) 23 983,
2937 10:02:43.956733 TX Bit6 (978~1005) 28 991, Bit14 (971~993) 23 982,
2938 10:02:43.963558 TX Bit7 (978~1005) 28 991, Bit15 (965~987) 23 976,
2939 10:02:43.964120
2940 10:02:43.964502
2941 10:02:43.966673 TX Vref found, early break! 376< 384
2942 10:02:43.970562 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2943 10:02:43.973678 u1DelayCellOfst[0]=5 cells (4 PI)
2944 10:02:43.976749 u1DelayCellOfst[1]=3 cells (3 PI)
2945 10:02:43.980510 u1DelayCellOfst[2]=1 cells (1 PI)
2946 10:02:43.983948 u1DelayCellOfst[3]=0 cells (0 PI)
2947 10:02:43.986656 u1DelayCellOfst[4]=5 cells (4 PI)
2948 10:02:43.990463 u1DelayCellOfst[5]=6 cells (5 PI)
2949 10:02:43.993670 u1DelayCellOfst[6]=3 cells (3 PI)
2950 10:02:43.994222 u1DelayCellOfst[7]=3 cells (3 PI)
2951 10:02:43.996765 Byte0, DQ PI dly=988, DQM PI dly= 990
2952 10:02:44.003662 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
2953 10:02:44.004419
2954 10:02:44.006383 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
2955 10:02:44.006957
2956 10:02:44.009522 u1DelayCellOfst[8]=3 cells (3 PI)
2957 10:02:44.013092 u1DelayCellOfst[9]=5 cells (4 PI)
2958 10:02:44.016292 u1DelayCellOfst[10]=6 cells (5 PI)
2959 10:02:44.019991 u1DelayCellOfst[11]=7 cells (6 PI)
2960 10:02:44.023175 u1DelayCellOfst[12]=7 cells (6 PI)
2961 10:02:44.026212 u1DelayCellOfst[13]=9 cells (7 PI)
2962 10:02:44.029460 u1DelayCellOfst[14]=7 cells (6 PI)
2963 10:02:44.032759 u1DelayCellOfst[15]=0 cells (0 PI)
2964 10:02:44.036208 Byte1, DQ PI dly=976, DQM PI dly= 979
2965 10:02:44.040042 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
2966 10:02:44.040560
2967 10:02:44.043001 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
2968 10:02:44.043449
2969 10:02:44.046349 Write Rank0 MR14 =0x20
2970 10:02:44.046761
2971 10:02:44.049910 Final TX Range 0 Vref 32
2972 10:02:44.050424
2973 10:02:44.056364 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2974 10:02:44.056874
2975 10:02:44.063508 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2976 10:02:44.070127 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2977 10:02:44.076559 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2978 10:02:44.077156 Write Rank0 MR3 =0xb0
2979 10:02:44.079817 DramC Write-DBI on
2980 10:02:44.080274 ==
2981 10:02:44.086349 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2982 10:02:44.086903 fsp= 1, odt_onoff= 1, Byte mode= 0
2983 10:02:44.089732 ==
2984 10:02:44.092985 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2985 10:02:44.093548
2986 10:02:44.096251 Begin, DQ Scan Range 699~763
2987 10:02:44.096710
2988 10:02:44.097069
2989 10:02:44.097404 TX Vref Scan disable
2990 10:02:44.099684 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2991 10:02:44.106382 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2992 10:02:44.109667 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2993 10:02:44.113610 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2994 10:02:44.116748 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2995 10:02:44.119239 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2996 10:02:44.122568 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2997 10:02:44.126356 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2998 10:02:44.129637 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2999 10:02:44.132692 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3000 10:02:44.136269 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3001 10:02:44.139206 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3002 10:02:44.142588 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3003 10:02:44.146296 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3004 10:02:44.149494 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3005 10:02:44.152816 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3006 10:02:44.156251 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3007 10:02:44.159266 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3008 10:02:44.162749 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3009 10:02:44.166048 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3010 10:02:44.169586 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3011 10:02:44.172873 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3012 10:02:44.179451 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3013 10:02:44.182868 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3014 10:02:44.185688 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3015 10:02:44.189245 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3016 10:02:44.192561 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3017 10:02:44.199477 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3018 10:02:44.202833 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3019 10:02:44.205866 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3020 10:02:44.209349 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3021 10:02:44.212724 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3022 10:02:44.216052 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3023 10:02:44.219171 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3024 10:02:44.222812 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3025 10:02:44.225853 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3026 10:02:44.229413 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3027 10:02:44.232480 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3028 10:02:44.235718 751 |2 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
3029 10:02:44.239399 Byte0, DQ PI dly=736, DQM PI dly= 736
3030 10:02:44.245614 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 32)
3031 10:02:44.246177
3032 10:02:44.249241 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 32)
3033 10:02:44.249703
3034 10:02:44.252372 Byte1, DQ PI dly=724, DQM PI dly= 724
3035 10:02:44.255711 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
3036 10:02:44.256278
3037 10:02:44.262398 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
3038 10:02:44.262969
3039 10:02:44.269031 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3040 10:02:44.275343 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3041 10:02:44.282591 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3042 10:02:44.283154 Write Rank0 MR3 =0x30
3043 10:02:44.285984 DramC Write-DBI off
3044 10:02:44.286544
3045 10:02:44.286911 [DATLAT]
3046 10:02:44.288632 Freq=1600, CH1 RK0, use_rxtx_scan=0
3047 10:02:44.289117
3048 10:02:44.292130 DATLAT Default: 0xf
3049 10:02:44.292591 7, 0xFFFF, sum=0
3050 10:02:44.295552 8, 0xFFFF, sum=0
3051 10:02:44.296022 9, 0xFFFF, sum=0
3052 10:02:44.298887 10, 0xFFFF, sum=0
3053 10:02:44.299487 11, 0xFFFF, sum=0
3054 10:02:44.302023 12, 0xFFFF, sum=0
3055 10:02:44.302561 13, 0xFFFF, sum=0
3056 10:02:44.305503 14, 0x0, sum=1
3057 10:02:44.305928 15, 0x0, sum=2
3058 10:02:44.308678 16, 0x0, sum=3
3059 10:02:44.309098 17, 0x0, sum=4
3060 10:02:44.312161 pattern=2 first_step=14 total pass=5 best_step=16
3061 10:02:44.312624 ==
3062 10:02:44.318836 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3063 10:02:44.321796 fsp= 1, odt_onoff= 1, Byte mode= 0
3064 10:02:44.322217 ==
3065 10:02:44.325693 Start DQ dly to find pass range UseTestEngine =1
3066 10:02:44.328883 x-axis: bit #, y-axis: DQ dly (-127~63)
3067 10:02:44.331889 RX Vref Scan = 1
3068 10:02:44.438794
3069 10:02:44.439355 RX Vref found, early break!
3070 10:02:44.439766
3071 10:02:44.444939 Final RX Vref 11, apply to both rank0 and 1
3072 10:02:44.445500 ==
3073 10:02:44.448231 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3074 10:02:44.451680 fsp= 1, odt_onoff= 1, Byte mode= 0
3075 10:02:44.452138 ==
3076 10:02:44.452503 DQS Delay:
3077 10:02:44.455524 DQS0 = 0, DQS1 = 0
3078 10:02:44.456073 DQM Delay:
3079 10:02:44.458453 DQM0 = 20, DQM1 = 19
3080 10:02:44.458960 DQ Delay:
3081 10:02:44.461597 DQ0 =22, DQ1 =22, DQ2 =18, DQ3 =17
3082 10:02:44.465107 DQ4 =22, DQ5 =23, DQ6 =23, DQ7 =20
3083 10:02:44.468501 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =22
3084 10:02:44.471675 DQ12 =22, DQ13 =21, DQ14 =23, DQ15 =13
3085 10:02:44.472235
3086 10:02:44.472600
3087 10:02:44.472934
3088 10:02:44.475004 [DramC_TX_OE_Calibration] TA2
3089 10:02:44.478130 Original DQ_B0 (3 6) =30, OEN = 27
3090 10:02:44.481579 Original DQ_B1 (3 6) =30, OEN = 27
3091 10:02:44.485109 23, 0x0, End_B0=23 End_B1=23
3092 10:02:44.485680 24, 0x0, End_B0=24 End_B1=24
3093 10:02:44.488313 25, 0x0, End_B0=25 End_B1=25
3094 10:02:44.491534 26, 0x0, End_B0=26 End_B1=26
3095 10:02:44.495391 27, 0x0, End_B0=27 End_B1=27
3096 10:02:44.496006 28, 0x0, End_B0=28 End_B1=28
3097 10:02:44.498259 29, 0x0, End_B0=29 End_B1=29
3098 10:02:44.501696 30, 0x0, End_B0=30 End_B1=30
3099 10:02:44.504642 31, 0xFFFF, End_B0=30 End_B1=30
3100 10:02:44.511958 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3101 10:02:44.515306 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3102 10:02:44.515929
3103 10:02:44.516297
3104 10:02:44.518209 Write Rank0 MR23 =0x3f
3105 10:02:44.518767 [DQSOSC]
3106 10:02:44.528391 [DQSOSCAuto] RK0, (LSB)MR18= 0xc1c1, (MSB)MR19= 0x202, tDQSOscB0 = 446 ps tDQSOscB1 = 446 ps
3107 10:02:44.531492 CH1_RK0: MR19=0x202, MR18=0xC1C1, DQSOSC=446, MR23=63, INC=12, DEC=18
3108 10:02:44.534827 Write Rank0 MR23 =0x3f
3109 10:02:44.535300 [DQSOSC]
3110 10:02:44.544694 [DQSOSCAuto] RK0, (LSB)MR18= 0xbfbf, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
3111 10:02:44.548037 CH1 RK0: MR19=202, MR18=BFBF
3112 10:02:44.551452 [RankSwap] Rank num 2, (Multi 1), Rank 1
3113 10:02:44.552030 Write Rank0 MR2 =0xad
3114 10:02:44.554635 [Write Leveling]
3115 10:02:44.558174 delay byte0 byte1 byte2 byte3
3116 10:02:44.558736
3117 10:02:44.559101 10 0 0
3118 10:02:44.561736 11 0 0
3119 10:02:44.562302 12 0 0
3120 10:02:44.562674 13 0 0
3121 10:02:44.564681 14 0 0
3122 10:02:44.565187 15 0 0
3123 10:02:44.567911 16 0 0
3124 10:02:44.568377 17 0 0
3125 10:02:44.568745 18 0 0
3126 10:02:44.570942 19 0 0
3127 10:02:44.571439 20 0 0
3128 10:02:44.574502 21 0 0
3129 10:02:44.574924 22 0 0
3130 10:02:44.577950 23 0 0
3131 10:02:44.578376 24 0 ff
3132 10:02:44.578712 25 0 ff
3133 10:02:44.581243 26 0 ff
3134 10:02:44.581789 27 0 ff
3135 10:02:44.584241 28 0 ff
3136 10:02:44.584661 29 0 ff
3137 10:02:44.587558 30 0 ff
3138 10:02:44.588092 31 0 ff
3139 10:02:44.591172 32 0 ff
3140 10:02:44.591630 33 0 ff
3141 10:02:44.592016 34 ff ff
3142 10:02:44.594253 35 ff ff
3143 10:02:44.594678 36 ff ff
3144 10:02:44.597906 37 ff ff
3145 10:02:44.598432 38 ff ff
3146 10:02:44.601468 39 ff ff
3147 10:02:44.601992 40 ff ff
3148 10:02:44.604608 pass bytecount = 0xff (0xff: all bytes pass)
3149 10:02:44.607778
3150 10:02:44.608302 DQS0 dly: 34
3151 10:02:44.608637 DQS1 dly: 24
3152 10:02:44.610708 Write Rank0 MR2 =0x2d
3153 10:02:44.614241 [RankSwap] Rank num 2, (Multi 1), Rank 0
3154 10:02:44.617993 Write Rank1 MR1 =0xd6
3155 10:02:44.618514 [Gating]
3156 10:02:44.618852 ==
3157 10:02:44.621151 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3158 10:02:44.624039 fsp= 1, odt_onoff= 1, Byte mode= 0
3159 10:02:44.624459 ==
3160 10:02:44.630818 3 1 0 |1515 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
3161 10:02:44.634119 3 1 4 |3433 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
3162 10:02:44.637132 3 1 8 |3433 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3163 10:02:44.644486 3 1 12 |2221 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3164 10:02:44.647399 3 1 16 |2827 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3165 10:02:44.650575 3 1 20 |b0a 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3166 10:02:44.657310 3 1 24 |3434 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3167 10:02:44.660685 3 1 28 |3332 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3168 10:02:44.663673 3 2 0 |2120 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3169 10:02:44.667367 3 2 4 |201 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3170 10:02:44.674065 [Byte 0] Lead/lag Transition tap number (1)
3171 10:02:44.677172 3 2 8 |3b3a 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
3172 10:02:44.680658 3 2 12 |1d1d 302 |(11 11)(11 1) |(1 1)(0 0)| 0
3173 10:02:44.683715 3 2 16 |3d3d 3534 |(0 0)(11 11) |(1 1)(0 0)| 0
3174 10:02:44.690530 3 2 20 |3b3b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3175 10:02:44.693877 3 2 24 |3b3a 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3176 10:02:44.697653 3 2 28 |3d3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3177 10:02:44.703921 3 3 0 |3c3b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3178 10:02:44.707751 3 3 4 |202 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3179 10:02:44.710665 3 3 8 |100f 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3180 10:02:44.717249 [Byte 0] Lead/lag falling Transition (3, 3, 8)
3181 10:02:44.720469 3 3 12 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3182 10:02:44.723713 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3183 10:02:44.727332 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3184 10:02:44.734225 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3185 10:02:44.737268 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3186 10:02:44.740781 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3187 10:02:44.747052 3 4 4 |504 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3188 10:02:44.750295 3 4 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3189 10:02:44.754187 3 4 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3190 10:02:44.760399 3 4 16 |3d3d 494f |(11 11)(11 11) |(1 1)(1 1)| 0
3191 10:02:44.763666 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3192 10:02:44.767038 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3193 10:02:44.773828 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3194 10:02:44.776913 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3195 10:02:44.780231 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3196 10:02:44.783943 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3197 10:02:44.790302 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3198 10:02:44.793697 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3199 10:02:44.797043 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3200 10:02:44.803887 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3201 10:02:44.806909 [Byte 0] Lead/lag falling Transition (3, 5, 24)
3202 10:02:44.810369 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3203 10:02:44.817111 3 6 0 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3204 10:02:44.820255 [Byte 0] Lead/lag Transition tap number (3)
3205 10:02:44.823463 3 6 4 |202 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3206 10:02:44.826752 [Byte 1] Lead/lag falling Transition (3, 6, 4)
3207 10:02:44.833903 3 6 8 |4646 3d3d |(0 0)(11 11) |(0 0)(1 0)| 0
3208 10:02:44.834492 [Byte 0]First pass (3, 6, 8)
3209 10:02:44.840167 [Byte 1] Lead/lag Transition tap number (2)
3210 10:02:44.843973 3 6 12 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
3211 10:02:44.846697 3 6 16 |4646 606 |(0 0)(1 1) |(0 0)(0 0)| 0
3212 10:02:44.850055 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3213 10:02:44.853241 [Byte 1]First pass (3, 6, 20)
3214 10:02:44.856689 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3215 10:02:44.860061 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3216 10:02:44.866731 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3217 10:02:44.870102 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3218 10:02:44.873345 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3219 10:02:44.876546 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3220 10:02:44.880176 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3221 10:02:44.887096 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3222 10:02:44.889992 All bytes gating window > 1UI, Early break!
3223 10:02:44.890549
3224 10:02:44.893676 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 30)
3225 10:02:44.894375
3226 10:02:44.896313 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
3227 10:02:44.896774
3228 10:02:44.897139
3229 10:02:44.897471
3230 10:02:44.900476 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
3231 10:02:44.903549
3232 10:02:44.906619 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
3233 10:02:44.907177
3234 10:02:44.907587
3235 10:02:44.907932 Write Rank1 MR1 =0x56
3236 10:02:44.908262
3237 10:02:44.909800 best RODT dly(2T, 0.5T) = (2, 2)
3238 10:02:44.910305
3239 10:02:44.912872 best RODT dly(2T, 0.5T) = (2, 3)
3240 10:02:44.913334 ==
3241 10:02:44.920010 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3242 10:02:44.923102 fsp= 1, odt_onoff= 1, Byte mode= 0
3243 10:02:44.923563 ==
3244 10:02:44.926531 Start DQ dly to find pass range UseTestEngine =0
3245 10:02:44.930164 x-axis: bit #, y-axis: DQ dly (-127~63)
3246 10:02:44.932942 RX Vref Scan = 0
3247 10:02:44.936508 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3248 10:02:44.936931 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3249 10:02:44.939875 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3250 10:02:44.943077 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3251 10:02:44.946428 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3252 10:02:44.949567 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3253 10:02:44.952829 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3254 10:02:44.956356 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3255 10:02:44.959727 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3256 10:02:44.962724 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3257 10:02:44.963150 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3258 10:02:44.966503 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3259 10:02:44.969503 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3260 10:02:44.972916 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3261 10:02:44.976261 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3262 10:02:44.979600 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3263 10:02:44.982859 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3264 10:02:44.986615 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3265 10:02:44.987144 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3266 10:02:44.990041 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3267 10:02:44.993285 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3268 10:02:44.996281 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3269 10:02:44.999545 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3270 10:02:45.003536 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3271 10:02:45.006242 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3272 10:02:45.006682 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3273 10:02:45.009692 0, [0] xxooxxxx ooxxxxxo [MSB]
3274 10:02:45.012666 1, [0] xxooxxxx ooxxxxxo [MSB]
3275 10:02:45.016131 2, [0] xxooxxxx ooxxxxxo [MSB]
3276 10:02:45.019349 3, [0] xxoooxxo oooxxxxo [MSB]
3277 10:02:45.022928 4, [0] oxoooxxo oooxooxo [MSB]
3278 10:02:45.023354 31, [0] oooooooo ooooooox [MSB]
3279 10:02:45.026414 32, [0] oooooooo ooooooox [MSB]
3280 10:02:45.029475 33, [0] oooooooo ooooooox [MSB]
3281 10:02:45.032559 34, [0] oooooooo ooooooox [MSB]
3282 10:02:45.035772 35, [0] oooxoooo xxooooox [MSB]
3283 10:02:45.039250 36, [0] oooxoooo xxooooox [MSB]
3284 10:02:45.042701 37, [0] ooxxoooo xxooooox [MSB]
3285 10:02:45.043127 38, [0] ooxxoooo xxooooox [MSB]
3286 10:02:45.045820 39, [0] oxxxxoox xxooooox [MSB]
3287 10:02:45.049423 40, [0] oxxxxoox xxxoooox [MSB]
3288 10:02:45.052503 41, [0] oxxxxoox xxxxxoox [MSB]
3289 10:02:45.056331 42, [0] xxxxxxxx xxxxxxxx [MSB]
3290 10:02:45.059169 iDelay=42, Bit 0, Center 22 (4 ~ 41) 38
3291 10:02:45.062654 iDelay=42, Bit 1, Center 21 (5 ~ 38) 34
3292 10:02:45.065611 iDelay=42, Bit 2, Center 18 (0 ~ 36) 37
3293 10:02:45.069035 iDelay=42, Bit 3, Center 16 (-2 ~ 34) 37
3294 10:02:45.072474 iDelay=42, Bit 4, Center 20 (3 ~ 38) 36
3295 10:02:45.075378 iDelay=42, Bit 5, Center 23 (5 ~ 41) 37
3296 10:02:45.079303 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
3297 10:02:45.082500 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
3298 10:02:45.089131 iDelay=42, Bit 8, Center 17 (0 ~ 34) 35
3299 10:02:45.092202 iDelay=42, Bit 9, Center 16 (-1 ~ 34) 36
3300 10:02:45.095697 iDelay=42, Bit 10, Center 21 (3 ~ 39) 37
3301 10:02:45.098757 iDelay=42, Bit 11, Center 22 (5 ~ 40) 36
3302 10:02:45.102109 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
3303 10:02:45.105516 iDelay=42, Bit 13, Center 22 (4 ~ 41) 38
3304 10:02:45.109303 iDelay=42, Bit 14, Center 23 (5 ~ 41) 37
3305 10:02:45.112428 iDelay=42, Bit 15, Center 13 (-3 ~ 30) 34
3306 10:02:45.112941 ==
3307 10:02:45.119211 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3308 10:02:45.122991 fsp= 1, odt_onoff= 1, Byte mode= 0
3309 10:02:45.123548 ==
3310 10:02:45.123945 DQS Delay:
3311 10:02:45.125756 DQS0 = 0, DQS1 = 0
3312 10:02:45.126173 DQM Delay:
3313 10:02:45.126504 DQM0 = 20, DQM1 = 19
3314 10:02:45.129058 DQ Delay:
3315 10:02:45.132533 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =16
3316 10:02:45.135639 DQ4 =20, DQ5 =23, DQ6 =23, DQ7 =20
3317 10:02:45.139096 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
3318 10:02:45.142434 DQ12 =22, DQ13 =22, DQ14 =23, DQ15 =13
3319 10:02:45.142944
3320 10:02:45.143276
3321 10:02:45.143615 DramC Write-DBI off
3322 10:02:45.143914 ==
3323 10:02:45.148903 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3324 10:02:45.152227 fsp= 1, odt_onoff= 1, Byte mode= 0
3325 10:02:45.152652 ==
3326 10:02:45.155533 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3327 10:02:45.155951
3328 10:02:45.159195 Begin, DQ Scan Range 920~1176
3329 10:02:45.159773
3330 10:02:45.160113
3331 10:02:45.162433 TX Vref Scan disable
3332 10:02:45.165540 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
3333 10:02:45.169093 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
3334 10:02:45.172877 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
3335 10:02:45.175660 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
3336 10:02:45.178711 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
3337 10:02:45.182109 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3338 10:02:45.185429 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3339 10:02:45.188799 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3340 10:02:45.192192 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3341 10:02:45.195992 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3342 10:02:45.198676 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3343 10:02:45.202225 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3344 10:02:45.208918 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3345 10:02:45.212474 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3346 10:02:45.215372 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3347 10:02:45.219128 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3348 10:02:45.222284 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3349 10:02:45.225265 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3350 10:02:45.228664 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3351 10:02:45.232066 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3352 10:02:45.235621 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3353 10:02:45.238719 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3354 10:02:45.242258 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3355 10:02:45.245258 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3356 10:02:45.248748 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3357 10:02:45.252313 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3358 10:02:45.255264 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3359 10:02:45.258939 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3360 10:02:45.265248 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3361 10:02:45.268384 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3362 10:02:45.272015 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3363 10:02:45.274963 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3364 10:02:45.278307 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3365 10:02:45.281869 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3366 10:02:45.285006 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3367 10:02:45.288506 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3368 10:02:45.291928 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3369 10:02:45.299464 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3370 10:02:45.299897 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3371 10:02:45.301822 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3372 10:02:45.304854 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3373 10:02:45.308369 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3374 10:02:45.311733 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3375 10:02:45.315114 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3376 10:02:45.318698 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3377 10:02:45.321628 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3378 10:02:45.324903 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3379 10:02:45.331869 967 |3 6 7|[0] xxxxxxxx xxxxxxxo [MSB]
3380 10:02:45.335310 968 |3 6 8|[0] xxxxxxxx oxxxxxxo [MSB]
3381 10:02:45.338293 969 |3 6 9|[0] xxxxxxxx ooxxxxxo [MSB]
3382 10:02:45.341645 970 |3 6 10|[0] xxxxxxxx oooxxxxo [MSB]
3383 10:02:45.345416 971 |3 6 11|[0] xxxxxxxx ooooxxoo [MSB]
3384 10:02:45.348342 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
3385 10:02:45.351322 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
3386 10:02:45.354922 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
3387 10:02:45.357968 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
3388 10:02:45.361448 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
3389 10:02:45.364718 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
3390 10:02:45.368355 978 |3 6 18|[0] xooooxxx oooooooo [MSB]
3391 10:02:45.371465 979 |3 6 19|[0] xooooxox oooooooo [MSB]
3392 10:02:45.378248 985 |3 6 25|[0] oooooooo ooooooox [MSB]
3393 10:02:45.381515 986 |3 6 26|[0] oooooooo ooooooox [MSB]
3394 10:02:45.385230 987 |3 6 27|[0] oooooooo ooooooox [MSB]
3395 10:02:45.388530 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
3396 10:02:45.391830 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
3397 10:02:45.394860 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
3398 10:02:45.398468 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3399 10:02:45.401403 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3400 10:02:45.405185 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3401 10:02:45.408224 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3402 10:02:45.411514 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3403 10:02:45.415067 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3404 10:02:45.418003 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
3405 10:02:45.421394 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
3406 10:02:45.424508 999 |3 6 39|[0] ooxxoooo xxxxxxxx [MSB]
3407 10:02:45.428246 1000 |3 6 40|[0] ooxxooox xxxxxxxx [MSB]
3408 10:02:45.434901 1001 |3 6 41|[0] oxxxxoxx xxxxxxxx [MSB]
3409 10:02:45.438546 1002 |3 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
3410 10:02:45.441440 Byte0, DQ PI dly=988, DQM PI dly= 988
3411 10:02:45.444919 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
3412 10:02:45.445480
3413 10:02:45.448112 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
3414 10:02:45.448573
3415 10:02:45.451455 Byte1, DQ PI dly=977, DQM PI dly= 977
3416 10:02:45.458389 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
3417 10:02:45.458958
3418 10:02:45.461271 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
3419 10:02:45.461735
3420 10:02:45.462191 ==
3421 10:02:45.468333 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3422 10:02:45.471778 fsp= 1, odt_onoff= 1, Byte mode= 0
3423 10:02:45.472348 ==
3424 10:02:45.474453 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3425 10:02:45.475029
3426 10:02:45.478222 Begin, DQ Scan Range 953~1017
3427 10:02:45.478790 Write Rank1 MR14 =0x0
3428 10:02:45.488268
3429 10:02:45.488829 CH=1, VrefRange= 0, VrefLevel = 0
3430 10:02:45.495184 TX Bit0 (982~998) 17 990, Bit8 (971~984) 14 977,
3431 10:02:45.498666 TX Bit1 (982~997) 16 989, Bit9 (971~984) 14 977,
3432 10:02:45.505060 TX Bit2 (979~993) 15 986, Bit10 (974~985) 12 979,
3433 10:02:45.508859 TX Bit3 (978~990) 13 984, Bit11 (975~986) 12 980,
3434 10:02:45.511536 TX Bit4 (981~995) 15 988, Bit12 (975~985) 11 980,
3435 10:02:45.518512 TX Bit5 (983~998) 16 990, Bit13 (975~987) 13 981,
3436 10:02:45.521761 TX Bit6 (982~997) 16 989, Bit14 (976~984) 9 980,
3437 10:02:45.524737 TX Bit7 (983~993) 11 988, Bit15 (969~978) 10 973,
3438 10:02:45.527892
3439 10:02:45.528362 Write Rank1 MR14 =0x2
3440 10:02:45.537337
3441 10:02:45.537901 CH=1, VrefRange= 0, VrefLevel = 2
3442 10:02:45.544285 TX Bit0 (982~998) 17 990, Bit8 (970~984) 15 977,
3443 10:02:45.547538 TX Bit1 (981~997) 17 989, Bit9 (970~984) 15 977,
3444 10:02:45.554119 TX Bit2 (979~994) 16 986, Bit10 (974~985) 12 979,
3445 10:02:45.557605 TX Bit3 (978~991) 14 984, Bit11 (975~987) 13 981,
3446 10:02:45.560772 TX Bit4 (981~997) 17 989, Bit12 (975~985) 11 980,
3447 10:02:45.567752 TX Bit5 (982~998) 17 990, Bit13 (974~987) 14 980,
3448 10:02:45.570692 TX Bit6 (982~997) 16 989, Bit14 (975~985) 11 980,
3449 10:02:45.574116 TX Bit7 (983~995) 13 989, Bit15 (968~978) 11 973,
3450 10:02:45.574704
3451 10:02:45.576924 Write Rank1 MR14 =0x4
3452 10:02:45.586668
3453 10:02:45.587239 CH=1, VrefRange= 0, VrefLevel = 4
3454 10:02:45.593714 TX Bit0 (981~999) 19 990, Bit8 (970~984) 15 977,
3455 10:02:45.596764 TX Bit1 (980~997) 18 988, Bit9 (970~984) 15 977,
3456 10:02:45.603249 TX Bit2 (978~995) 18 986, Bit10 (973~986) 14 979,
3457 10:02:45.607253 TX Bit3 (978~992) 15 985, Bit11 (974~987) 14 980,
3458 10:02:45.610329 TX Bit4 (980~997) 18 988, Bit12 (974~986) 13 980,
3459 10:02:45.616640 TX Bit5 (982~999) 18 990, Bit13 (974~988) 15 981,
3460 10:02:45.619591 TX Bit6 (980~998) 19 989, Bit14 (974~986) 13 980,
3461 10:02:45.623239 TX Bit7 (983~995) 13 989, Bit15 (968~980) 13 974,
3462 10:02:45.623848
3463 10:02:45.626378 Write Rank1 MR14 =0x6
3464 10:02:45.635724
3465 10:02:45.636224 CH=1, VrefRange= 0, VrefLevel = 6
3466 10:02:45.642852 TX Bit0 (981~999) 19 990, Bit8 (969~985) 17 977,
3467 10:02:45.646048 TX Bit1 (980~998) 19 989, Bit9 (970~985) 16 977,
3468 10:02:45.652939 TX Bit2 (978~996) 19 987, Bit10 (972~986) 15 979,
3469 10:02:45.656049 TX Bit3 (977~992) 16 984, Bit11 (973~988) 16 980,
3470 10:02:45.659145 TX Bit4 (979~997) 19 988, Bit12 (974~987) 14 980,
3471 10:02:45.666203 TX Bit5 (981~999) 19 990, Bit13 (974~989) 16 981,
3472 10:02:45.669488 TX Bit6 (980~998) 19 989, Bit14 (973~986) 14 979,
3473 10:02:45.672926 TX Bit7 (982~997) 16 989, Bit15 (968~981) 14 974,
3474 10:02:45.673502
3475 10:02:45.675844 Write Rank1 MR14 =0x8
3476 10:02:45.685105
3477 10:02:45.685694 CH=1, VrefRange= 0, VrefLevel = 8
3478 10:02:45.691701 TX Bit0 (981~999) 19 990, Bit8 (969~985) 17 977,
3479 10:02:45.694673 TX Bit1 (979~998) 20 988, Bit9 (969~985) 17 977,
3480 10:02:45.701144 TX Bit2 (978~997) 20 987, Bit10 (972~988) 17 980,
3481 10:02:45.704958 TX Bit3 (977~993) 17 985, Bit11 (973~989) 17 981,
3482 10:02:45.708038 TX Bit4 (979~998) 20 988, Bit12 (973~988) 16 980,
3483 10:02:45.714473 TX Bit5 (981~999) 19 990, Bit13 (973~990) 18 981,
3484 10:02:45.717734 TX Bit6 (980~999) 20 989, Bit14 (972~987) 16 979,
3485 10:02:45.721509 TX Bit7 (981~997) 17 989, Bit15 (967~982) 16 974,
3486 10:02:45.724606
3487 10:02:45.725040 Write Rank1 MR14 =0xa
3488 10:02:45.735369
3489 10:02:45.737816 CH=1, VrefRange= 0, VrefLevel = 10
3490 10:02:45.741317 TX Bit0 (980~1000) 21 990, Bit8 (969~985) 17 977,
3491 10:02:45.744242 TX Bit1 (979~999) 21 989, Bit9 (969~985) 17 977,
3492 10:02:45.751021 TX Bit2 (978~998) 21 988, Bit10 (971~988) 18 979,
3493 10:02:45.754712 TX Bit3 (977~993) 17 985, Bit11 (973~990) 18 981,
3494 10:02:45.757977 TX Bit4 (979~999) 21 989, Bit12 (973~989) 17 981,
3495 10:02:45.764623 TX Bit5 (981~1000) 20 990, Bit13 (973~991) 19 982,
3496 10:02:45.767911 TX Bit6 (980~999) 20 989, Bit14 (972~988) 17 980,
3497 10:02:45.774166 TX Bit7 (981~998) 18 989, Bit15 (967~983) 17 975,
3498 10:02:45.774711
3499 10:02:45.775079 Write Rank1 MR14 =0xc
3500 10:02:45.784328
3501 10:02:45.788095 CH=1, VrefRange= 0, VrefLevel = 12
3502 10:02:45.791209 TX Bit0 (980~1001) 22 990, Bit8 (969~986) 18 977,
3503 10:02:45.793947 TX Bit1 (979~999) 21 989, Bit9 (969~986) 18 977,
3504 10:02:45.800960 TX Bit2 (978~998) 21 988, Bit10 (972~989) 18 980,
3505 10:02:45.804638 TX Bit3 (977~994) 18 985, Bit11 (972~990) 19 981,
3506 10:02:45.807283 TX Bit4 (979~999) 21 989, Bit12 (972~990) 19 981,
3507 10:02:45.814607 TX Bit5 (981~1000) 20 990, Bit13 (972~991) 20 981,
3508 10:02:45.817512 TX Bit6 (979~999) 21 989, Bit14 (972~989) 18 980,
3509 10:02:45.824073 TX Bit7 (980~998) 19 989, Bit15 (967~983) 17 975,
3510 10:02:45.824636
3511 10:02:45.825005 Write Rank1 MR14 =0xe
3512 10:02:45.834685
3513 10:02:45.837481 CH=1, VrefRange= 0, VrefLevel = 14
3514 10:02:45.841143 TX Bit0 (980~1001) 22 990, Bit8 (968~987) 20 977,
3515 10:02:45.844297 TX Bit1 (979~999) 21 989, Bit9 (968~986) 19 977,
3516 10:02:45.851010 TX Bit2 (978~998) 21 988, Bit10 (971~990) 20 980,
3517 10:02:45.853893 TX Bit3 (977~995) 19 986, Bit11 (971~991) 21 981,
3518 10:02:45.857687 TX Bit4 (979~999) 21 989, Bit12 (972~990) 19 981,
3519 10:02:45.863887 TX Bit5 (980~1001) 22 990, Bit13 (972~991) 20 981,
3520 10:02:45.867507 TX Bit6 (979~1000) 22 989, Bit14 (971~990) 20 980,
3521 10:02:45.874004 TX Bit7 (980~999) 20 989, Bit15 (966~984) 19 975,
3522 10:02:45.874571
3523 10:02:45.874936 Write Rank1 MR14 =0x10
3524 10:02:45.884303
3525 10:02:45.887778 CH=1, VrefRange= 0, VrefLevel = 16
3526 10:02:45.890843 TX Bit0 (979~1002) 24 990, Bit8 (968~987) 20 977,
3527 10:02:45.894654 TX Bit1 (978~1000) 23 989, Bit9 (969~987) 19 978,
3528 10:02:45.901383 TX Bit2 (977~998) 22 987, Bit10 (970~990) 21 980,
3529 10:02:45.904710 TX Bit3 (976~996) 21 986, Bit11 (971~991) 21 981,
3530 10:02:45.907785 TX Bit4 (978~1000) 23 989, Bit12 (971~991) 21 981,
3531 10:02:45.914763 TX Bit5 (979~1001) 23 990, Bit13 (972~992) 21 982,
3532 10:02:45.918007 TX Bit6 (979~1000) 22 989, Bit14 (971~990) 20 980,
3533 10:02:45.924279 TX Bit7 (980~999) 20 989, Bit15 (966~984) 19 975,
3534 10:02:45.924846
3535 10:02:45.925209 Write Rank1 MR14 =0x12
3536 10:02:45.935236
3537 10:02:45.935838 CH=1, VrefRange= 0, VrefLevel = 18
3538 10:02:45.941552 TX Bit0 (979~1002) 24 990, Bit8 (968~988) 21 978,
3539 10:02:45.944686 TX Bit1 (978~1000) 23 989, Bit9 (969~988) 20 978,
3540 10:02:45.951439 TX Bit2 (977~999) 23 988, Bit10 (970~991) 22 980,
3541 10:02:45.955043 TX Bit3 (976~997) 22 986, Bit11 (971~991) 21 981,
3542 10:02:45.958386 TX Bit4 (978~1000) 23 989, Bit12 (971~991) 21 981,
3543 10:02:45.964466 TX Bit5 (979~1002) 24 990, Bit13 (971~992) 22 981,
3544 10:02:45.967897 TX Bit6 (978~1001) 24 989, Bit14 (970~991) 22 980,
3545 10:02:45.974788 TX Bit7 (979~1000) 22 989, Bit15 (966~985) 20 975,
3546 10:02:45.975333
3547 10:02:45.975896 Write Rank1 MR14 =0x14
3548 10:02:45.985715
3549 10:02:45.988597 CH=1, VrefRange= 0, VrefLevel = 20
3550 10:02:45.992006 TX Bit0 (979~1003) 25 991, Bit8 (968~989) 22 978,
3551 10:02:45.995522 TX Bit1 (978~1001) 24 989, Bit9 (969~988) 20 978,
3552 10:02:46.001524 TX Bit2 (977~999) 23 988, Bit10 (970~991) 22 980,
3553 10:02:46.004824 TX Bit3 (976~997) 22 986, Bit11 (971~992) 22 981,
3554 10:02:46.008140 TX Bit4 (978~1001) 24 989, Bit12 (971~991) 21 981,
3555 10:02:46.014937 TX Bit5 (978~1002) 25 990, Bit13 (971~992) 22 981,
3556 10:02:46.018357 TX Bit6 (978~1001) 24 989, Bit14 (971~991) 21 981,
3557 10:02:46.024855 TX Bit7 (979~1000) 22 989, Bit15 (966~985) 20 975,
3558 10:02:46.025368
3559 10:02:46.025701 Write Rank1 MR14 =0x16
3560 10:02:46.036318
3561 10:02:46.039447 CH=1, VrefRange= 0, VrefLevel = 22
3562 10:02:46.042895 TX Bit0 (979~1003) 25 991, Bit8 (968~990) 23 979,
3563 10:02:46.046242 TX Bit1 (978~1001) 24 989, Bit9 (968~989) 22 978,
3564 10:02:46.052933 TX Bit2 (977~999) 23 988, Bit10 (970~991) 22 980,
3565 10:02:46.056372 TX Bit3 (976~998) 23 987, Bit11 (970~992) 23 981,
3566 10:02:46.059653 TX Bit4 (978~1001) 24 989, Bit12 (970~992) 23 981,
3567 10:02:46.065708 TX Bit5 (978~1003) 26 990, Bit13 (970~992) 23 981,
3568 10:02:46.069020 TX Bit6 (978~1001) 24 989, Bit14 (970~991) 22 980,
3569 10:02:46.075974 TX Bit7 (979~1000) 22 989, Bit15 (965~985) 21 975,
3570 10:02:46.076404
3571 10:02:46.076732 Write Rank1 MR14 =0x18
3572 10:02:46.086438
3573 10:02:46.090009 CH=1, VrefRange= 0, VrefLevel = 24
3574 10:02:46.092956 TX Bit0 (978~1003) 26 990, Bit8 (968~990) 23 979,
3575 10:02:46.096665 TX Bit1 (978~1002) 25 990, Bit9 (968~990) 23 979,
3576 10:02:46.103500 TX Bit2 (977~1000) 24 988, Bit10 (969~992) 24 980,
3577 10:02:46.106483 TX Bit3 (976~998) 23 987, Bit11 (970~993) 24 981,
3578 10:02:46.109635 TX Bit4 (978~1001) 24 989, Bit12 (970~992) 23 981,
3579 10:02:46.116078 TX Bit5 (978~1003) 26 990, Bit13 (971~993) 23 982,
3580 10:02:46.119850 TX Bit6 (978~1003) 26 990, Bit14 (970~992) 23 981,
3581 10:02:46.126173 TX Bit7 (979~1001) 23 990, Bit15 (965~986) 22 975,
3582 10:02:46.126742
3583 10:02:46.127103 Write Rank1 MR14 =0x1a
3584 10:02:46.137839
3585 10:02:46.140908 CH=1, VrefRange= 0, VrefLevel = 26
3586 10:02:46.144233 TX Bit0 (978~1005) 28 991, Bit8 (967~991) 25 979,
3587 10:02:46.147785 TX Bit1 (978~1002) 25 990, Bit9 (968~990) 23 979,
3588 10:02:46.153963 TX Bit2 (977~1000) 24 988, Bit10 (969~992) 24 980,
3589 10:02:46.157514 TX Bit3 (975~999) 25 987, Bit11 (970~993) 24 981,
3590 10:02:46.161011 TX Bit4 (978~1002) 25 990, Bit12 (970~992) 23 981,
3591 10:02:46.167143 TX Bit5 (978~1004) 27 991, Bit13 (970~993) 24 981,
3592 10:02:46.171055 TX Bit6 (978~1003) 26 990, Bit14 (970~992) 23 981,
3593 10:02:46.177077 TX Bit7 (979~1001) 23 990, Bit15 (964~986) 23 975,
3594 10:02:46.177598
3595 10:02:46.178149 Write Rank1 MR14 =0x1c
3596 10:02:46.188331
3597 10:02:46.191935 CH=1, VrefRange= 0, VrefLevel = 28
3598 10:02:46.195570 TX Bit0 (978~1005) 28 991, Bit8 (967~991) 25 979,
3599 10:02:46.198161 TX Bit1 (978~1003) 26 990, Bit9 (968~991) 24 979,
3600 10:02:46.205195 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3601 10:02:46.208552 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
3602 10:02:46.211596 TX Bit4 (978~1003) 26 990, Bit12 (970~992) 23 981,
3603 10:02:46.218328 TX Bit5 (978~1005) 28 991, Bit13 (970~993) 24 981,
3604 10:02:46.221562 TX Bit6 (978~1003) 26 990, Bit14 (970~992) 23 981,
3605 10:02:46.228179 TX Bit7 (978~1002) 25 990, Bit15 (964~986) 23 975,
3606 10:02:46.228745
3607 10:02:46.229114 Write Rank1 MR14 =0x1e
3608 10:02:46.239277
3609 10:02:46.243181 CH=1, VrefRange= 0, VrefLevel = 30
3610 10:02:46.246567 TX Bit0 (978~1005) 28 991, Bit8 (967~990) 24 978,
3611 10:02:46.249957 TX Bit1 (978~1003) 26 990, Bit9 (968~990) 23 979,
3612 10:02:46.256382 TX Bit2 (976~1001) 26 988, Bit10 (969~992) 24 980,
3613 10:02:46.259627 TX Bit3 (975~998) 24 986, Bit11 (969~993) 25 981,
3614 10:02:46.262918 TX Bit4 (978~1003) 26 990, Bit12 (970~993) 24 981,
3615 10:02:46.269176 TX Bit5 (978~1005) 28 991, Bit13 (970~993) 24 981,
3616 10:02:46.272259 TX Bit6 (977~1004) 28 990, Bit14 (969~992) 24 980,
3617 10:02:46.279476 TX Bit7 (978~1003) 26 990, Bit15 (964~987) 24 975,
3618 10:02:46.280047
3619 10:02:46.280413 Write Rank1 MR14 =0x20
3620 10:02:46.290367
3621 10:02:46.293852 CH=1, VrefRange= 0, VrefLevel = 32
3622 10:02:46.297438 TX Bit0 (978~1005) 28 991, Bit8 (967~990) 24 978,
3623 10:02:46.300658 TX Bit1 (977~1002) 26 989, Bit9 (967~990) 24 978,
3624 10:02:46.307212 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3625 10:02:46.310455 TX Bit3 (974~998) 25 986, Bit11 (969~993) 25 981,
3626 10:02:46.313624 TX Bit4 (978~1003) 26 990, Bit12 (970~993) 24 981,
3627 10:02:46.320291 TX Bit5 (978~1005) 28 991, Bit13 (970~993) 24 981,
3628 10:02:46.324179 TX Bit6 (977~1004) 28 990, Bit14 (969~993) 25 981,
3629 10:02:46.330629 TX Bit7 (978~1002) 25 990, Bit15 (963~987) 25 975,
3630 10:02:46.331487
3631 10:02:46.331901 Write Rank1 MR14 =0x22
3632 10:02:46.341821
3633 10:02:46.344605 CH=1, VrefRange= 0, VrefLevel = 34
3634 10:02:46.348429 TX Bit0 (978~1005) 28 991, Bit8 (967~990) 24 978,
3635 10:02:46.351457 TX Bit1 (977~1002) 26 989, Bit9 (967~990) 24 978,
3636 10:02:46.358201 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3637 10:02:46.361529 TX Bit3 (974~998) 25 986, Bit11 (969~993) 25 981,
3638 10:02:46.364348 TX Bit4 (978~1003) 26 990, Bit12 (970~993) 24 981,
3639 10:02:46.371684 TX Bit5 (978~1005) 28 991, Bit13 (970~993) 24 981,
3640 10:02:46.374970 TX Bit6 (977~1004) 28 990, Bit14 (969~993) 25 981,
3641 10:02:46.381232 TX Bit7 (978~1002) 25 990, Bit15 (963~987) 25 975,
3642 10:02:46.381704
3643 10:02:46.382069 Write Rank1 MR14 =0x24
3644 10:02:46.392226
3645 10:02:46.395693 CH=1, VrefRange= 0, VrefLevel = 36
3646 10:02:46.399370 TX Bit0 (978~1005) 28 991, Bit8 (967~990) 24 978,
3647 10:02:46.402775 TX Bit1 (977~1002) 26 989, Bit9 (967~990) 24 978,
3648 10:02:46.408879 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3649 10:02:46.412377 TX Bit3 (974~998) 25 986, Bit11 (969~993) 25 981,
3650 10:02:46.415448 TX Bit4 (978~1003) 26 990, Bit12 (970~993) 24 981,
3651 10:02:46.422210 TX Bit5 (978~1005) 28 991, Bit13 (970~993) 24 981,
3652 10:02:46.425455 TX Bit6 (977~1004) 28 990, Bit14 (969~993) 25 981,
3653 10:02:46.431774 TX Bit7 (978~1002) 25 990, Bit15 (963~987) 25 975,
3654 10:02:46.432288
3655 10:02:46.432656 Write Rank1 MR14 =0x26
3656 10:02:46.443118
3657 10:02:46.446545 CH=1, VrefRange= 0, VrefLevel = 38
3658 10:02:46.449985 TX Bit0 (978~1005) 28 991, Bit8 (967~990) 24 978,
3659 10:02:46.453379 TX Bit1 (977~1002) 26 989, Bit9 (967~990) 24 978,
3660 10:02:46.459947 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3661 10:02:46.463047 TX Bit3 (974~998) 25 986, Bit11 (969~993) 25 981,
3662 10:02:46.466233 TX Bit4 (978~1003) 26 990, Bit12 (970~993) 24 981,
3663 10:02:46.472815 TX Bit5 (978~1005) 28 991, Bit13 (970~993) 24 981,
3664 10:02:46.476711 TX Bit6 (977~1004) 28 990, Bit14 (969~993) 25 981,
3665 10:02:46.483235 TX Bit7 (978~1002) 25 990, Bit15 (963~987) 25 975,
3666 10:02:46.483871
3667 10:02:46.484243
3668 10:02:46.486172 TX Vref found, early break! 376< 385
3669 10:02:46.490181 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
3670 10:02:46.493172 u1DelayCellOfst[0]=6 cells (5 PI)
3671 10:02:46.496867 u1DelayCellOfst[1]=3 cells (3 PI)
3672 10:02:46.500041 u1DelayCellOfst[2]=3 cells (3 PI)
3673 10:02:46.503442 u1DelayCellOfst[3]=0 cells (0 PI)
3674 10:02:46.506563 u1DelayCellOfst[4]=5 cells (4 PI)
3675 10:02:46.509686 u1DelayCellOfst[5]=6 cells (5 PI)
3676 10:02:46.510254 u1DelayCellOfst[6]=5 cells (4 PI)
3677 10:02:46.513044 u1DelayCellOfst[7]=5 cells (4 PI)
3678 10:02:46.516433 Byte0, DQ PI dly=986, DQM PI dly= 988
3679 10:02:46.523135 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
3680 10:02:46.523735
3681 10:02:46.526395 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
3682 10:02:46.526966
3683 10:02:46.530114 u1DelayCellOfst[8]=3 cells (3 PI)
3684 10:02:46.532852 u1DelayCellOfst[9]=3 cells (3 PI)
3685 10:02:46.536278 u1DelayCellOfst[10]=6 cells (5 PI)
3686 10:02:46.539686 u1DelayCellOfst[11]=7 cells (6 PI)
3687 10:02:46.543393 u1DelayCellOfst[12]=7 cells (6 PI)
3688 10:02:46.546370 u1DelayCellOfst[13]=7 cells (6 PI)
3689 10:02:46.549560 u1DelayCellOfst[14]=7 cells (6 PI)
3690 10:02:46.552548 u1DelayCellOfst[15]=0 cells (0 PI)
3691 10:02:46.556003 Byte1, DQ PI dly=975, DQM PI dly= 978
3692 10:02:46.559502 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15)
3693 10:02:46.559991
3694 10:02:46.562673 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15)
3695 10:02:46.563296
3696 10:02:46.566113 Write Rank1 MR14 =0x20
3697 10:02:46.566577
3698 10:02:46.569052 Final TX Range 0 Vref 32
3699 10:02:46.569473
3700 10:02:46.575802 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3701 10:02:46.576226
3702 10:02:46.582888 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3703 10:02:46.589647 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3704 10:02:46.595773 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3705 10:02:46.596301 Write Rank1 MR3 =0xb0
3706 10:02:46.599598 DramC Write-DBI on
3707 10:02:46.600120 ==
3708 10:02:46.606001 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3709 10:02:46.606532 fsp= 1, odt_onoff= 1, Byte mode= 0
3710 10:02:46.609222 ==
3711 10:02:46.612347 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3712 10:02:46.612933
3713 10:02:46.615515 Begin, DQ Scan Range 698~762
3714 10:02:46.616053
3715 10:02:46.616429
3716 10:02:46.616776 TX Vref Scan disable
3717 10:02:46.619393 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3718 10:02:46.625604 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3719 10:02:46.628999 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3720 10:02:46.632312 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3721 10:02:46.635447 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3722 10:02:46.638674 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3723 10:02:46.642063 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3724 10:02:46.646064 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3725 10:02:46.648747 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3726 10:02:46.652375 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3727 10:02:46.655774 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3728 10:02:46.659040 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3729 10:02:46.662422 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3730 10:02:46.665713 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
3731 10:02:46.668806 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3732 10:02:46.672979 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3733 10:02:46.675650 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3734 10:02:46.678857 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3735 10:02:46.682223 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3736 10:02:46.685653 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3737 10:02:46.688923 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3738 10:02:46.692571 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3739 10:02:46.699269 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3740 10:02:46.702426 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3741 10:02:46.705417 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3742 10:02:46.708909 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3743 10:02:46.715602 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3744 10:02:46.718879 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3745 10:02:46.722036 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3746 10:02:46.725459 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3747 10:02:46.728471 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3748 10:02:46.731726 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3749 10:02:46.735401 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3750 10:02:46.738374 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3751 10:02:46.742070 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3752 10:02:46.745176 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3753 10:02:46.748646 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3754 10:02:46.752017 750 |2 6 46|[0] xxxxxxxx xxxxxxxx [MSB]
3755 10:02:46.755105 Byte0, DQ PI dly=735, DQM PI dly= 735
3756 10:02:46.761715 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 31)
3757 10:02:46.762302
3758 10:02:46.765556 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 31)
3759 10:02:46.766231
3760 10:02:46.768728 Byte1, DQ PI dly=723, DQM PI dly= 723
3761 10:02:46.772019 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
3762 10:02:46.772698
3763 10:02:46.778706 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
3764 10:02:46.779440
3765 10:02:46.785308 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3766 10:02:46.791996 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3767 10:02:46.798761 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3768 10:02:46.799364 Write Rank1 MR3 =0x30
3769 10:02:46.801754 DramC Write-DBI off
3770 10:02:46.802280
3771 10:02:46.802750 [DATLAT]
3772 10:02:46.805095 Freq=1600, CH1 RK1, use_rxtx_scan=0
3773 10:02:46.805522
3774 10:02:46.808289 DATLAT Default: 0x10
3775 10:02:46.808737 7, 0xFFFF, sum=0
3776 10:02:46.811942 8, 0xFFFF, sum=0
3777 10:02:46.812505 9, 0xFFFF, sum=0
3778 10:02:46.814813 10, 0xFFFF, sum=0
3779 10:02:46.815402 11, 0xFFFF, sum=0
3780 10:02:46.818160 12, 0xFFFF, sum=0
3781 10:02:46.818676 13, 0xFFFF, sum=0
3782 10:02:46.821718 14, 0x0, sum=1
3783 10:02:46.822283 15, 0x0, sum=2
3784 10:02:46.822781 16, 0x0, sum=3
3785 10:02:46.824685 17, 0x0, sum=4
3786 10:02:46.828379 pattern=2 first_step=14 total pass=5 best_step=16
3787 10:02:46.828802 ==
3788 10:02:46.834856 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3789 10:02:46.838568 fsp= 1, odt_onoff= 1, Byte mode= 0
3790 10:02:46.838991 ==
3791 10:02:46.842080 Start DQ dly to find pass range UseTestEngine =1
3792 10:02:46.845401 x-axis: bit #, y-axis: DQ dly (-127~63)
3793 10:02:46.848299 RX Vref Scan = 0
3794 10:02:46.851574 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3795 10:02:46.852094 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3796 10:02:46.854929 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3797 10:02:46.858393 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3798 10:02:46.862294 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3799 10:02:46.864958 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3800 10:02:46.868246 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3801 10:02:46.871688 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3802 10:02:46.874650 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3803 10:02:46.875078 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3804 10:02:46.878276 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3805 10:02:46.881623 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3806 10:02:46.885146 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3807 10:02:46.888395 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3808 10:02:46.892137 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3809 10:02:46.895069 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3810 10:02:46.898558 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3811 10:02:46.899102 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3812 10:02:46.902013 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3813 10:02:46.904934 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3814 10:02:46.908480 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3815 10:02:46.912126 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3816 10:02:46.915135 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3817 10:02:46.918451 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3818 10:02:46.918977 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3819 10:02:46.921548 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3820 10:02:46.925217 0, [0] xxooxxxx ooxxxxxo [MSB]
3821 10:02:46.928487 1, [0] xxooxxxx ooxxxxxo [MSB]
3822 10:02:46.931435 2, [0] xxooxxxx ooxxxxxo [MSB]
3823 10:02:46.935048 3, [0] xxooxxxo oooxxxxo [MSB]
3824 10:02:46.935618 4, [0] oooooxxo ooooooxo [MSB]
3825 10:02:46.940293 32, [0] oooooooo ooooooox [MSB]
3826 10:02:46.944289 33, [0] oooooooo ooooooox [MSB]
3827 10:02:46.946810 34, [0] oooooooo ooooooox [MSB]
3828 10:02:46.950401 35, [0] oooxoooo oxooooox [MSB]
3829 10:02:46.953790 36, [0] oooxoooo xxooooox [MSB]
3830 10:02:46.957087 37, [0] ooxxoooo xxooooox [MSB]
3831 10:02:46.957518 38, [0] ooxxoooo xxooooox [MSB]
3832 10:02:46.960064 39, [0] ooxxooox xxxoooox [MSB]
3833 10:02:46.964063 40, [0] oxxxxoox xxxooxox [MSB]
3834 10:02:46.966642 41, [0] xxxxxxox xxxxxxxx [MSB]
3835 10:02:46.969919 42, [0] xxxxxxxx xxxxxxxx [MSB]
3836 10:02:46.973643 iDelay=42, Bit 0, Center 22 (4 ~ 40) 37
3837 10:02:46.976535 iDelay=42, Bit 1, Center 21 (4 ~ 39) 36
3838 10:02:46.980144 iDelay=42, Bit 2, Center 18 (0 ~ 36) 37
3839 10:02:46.983335 iDelay=42, Bit 3, Center 16 (-2 ~ 34) 37
3840 10:02:46.986862 iDelay=42, Bit 4, Center 21 (4 ~ 39) 36
3841 10:02:46.990426 iDelay=42, Bit 5, Center 22 (5 ~ 40) 36
3842 10:02:46.993732 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
3843 10:02:46.996729 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
3844 10:02:47.003296 iDelay=42, Bit 8, Center 17 (0 ~ 35) 36
3845 10:02:47.006538 iDelay=42, Bit 9, Center 16 (-1 ~ 34) 36
3846 10:02:47.010540 iDelay=42, Bit 10, Center 20 (3 ~ 38) 36
3847 10:02:47.013499 iDelay=42, Bit 11, Center 22 (4 ~ 40) 37
3848 10:02:47.016972 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
3849 10:02:47.020044 iDelay=42, Bit 13, Center 21 (4 ~ 39) 36
3850 10:02:47.023291 iDelay=42, Bit 14, Center 22 (5 ~ 40) 36
3851 10:02:47.026663 iDelay=42, Bit 15, Center 14 (-3 ~ 31) 35
3852 10:02:47.027087 ==
3853 10:02:47.033409 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3854 10:02:47.036940 fsp= 1, odt_onoff= 1, Byte mode= 0
3855 10:02:47.037364 ==
3856 10:02:47.037714 DQS Delay:
3857 10:02:47.040181 DQS0 = 0, DQS1 = 0
3858 10:02:47.040601 DQM Delay:
3859 10:02:47.040959 DQM0 = 20, DQM1 = 19
3860 10:02:47.043175 DQ Delay:
3861 10:02:47.046784 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =16
3862 10:02:47.050258 DQ4 =21, DQ5 =22, DQ6 =23, DQ7 =20
3863 10:02:47.053697 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =22
3864 10:02:47.056395 DQ12 =22, DQ13 =21, DQ14 =22, DQ15 =14
3865 10:02:47.056864
3866 10:02:47.057236
3867 10:02:47.057847
3868 10:02:47.059916 [DramC_TX_OE_Calibration] TA2
3869 10:02:47.063541 Original DQ_B0 (3 6) =30, OEN = 27
3870 10:02:47.064121 Original DQ_B1 (3 6) =30, OEN = 27
3871 10:02:47.066612 23, 0x0, End_B0=23 End_B1=23
3872 10:02:47.070002 24, 0x0, End_B0=24 End_B1=24
3873 10:02:47.073226 25, 0x0, End_B0=25 End_B1=25
3874 10:02:47.076566 26, 0x0, End_B0=26 End_B1=26
3875 10:02:47.077042 27, 0x0, End_B0=27 End_B1=27
3876 10:02:47.079766 28, 0x0, End_B0=28 End_B1=28
3877 10:02:47.083493 29, 0x0, End_B0=29 End_B1=29
3878 10:02:47.086342 30, 0x0, End_B0=30 End_B1=30
3879 10:02:47.090087 31, 0xFFFF, End_B0=30 End_B1=30
3880 10:02:47.093081 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3881 10:02:47.099896 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3882 10:02:47.100472
3883 10:02:47.100842
3884 10:02:47.103536 Write Rank1 MR23 =0x3f
3885 10:02:47.104109 [DQSOSC]
3886 10:02:47.109825 [DQSOSCAuto] RK1, (LSB)MR18= 0xcdcd, (MSB)MR19= 0x202, tDQSOscB0 = 439 ps tDQSOscB1 = 439 ps
3887 10:02:47.116452 CH1_RK1: MR19=0x202, MR18=0xCDCD, DQSOSC=439, MR23=63, INC=12, DEC=19
3888 10:02:47.120266 Write Rank1 MR23 =0x3f
3889 10:02:47.120831 [DQSOSC]
3890 10:02:47.126419 [DQSOSCAuto] RK1, (LSB)MR18= 0xcccc, (MSB)MR19= 0x202, tDQSOscB0 = 439 ps tDQSOscB1 = 439 ps
3891 10:02:47.129841 CH1 RK1: MR19=202, MR18=CCCC
3892 10:02:47.133154 [RxdqsGatingPostProcess] freq 1600
3893 10:02:47.139397 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3894 10:02:47.139905 Rank: 0
3895 10:02:47.143021 best DQS0 dly(2T, 0.5T) = (2, 6)
3896 10:02:47.145999 best DQS1 dly(2T, 0.5T) = (2, 6)
3897 10:02:47.149560 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3898 10:02:47.153177 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3899 10:02:47.153644 Rank: 1
3900 10:02:47.155955 best DQS0 dly(2T, 0.5T) = (2, 5)
3901 10:02:47.159386 best DQS1 dly(2T, 0.5T) = (2, 6)
3902 10:02:47.162728 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3903 10:02:47.166496 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3904 10:02:47.169773 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3905 10:02:47.173067 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3906 10:02:47.179641 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3907 10:02:47.180122
3908 10:02:47.180492
3909 10:02:47.182623 [Calibration Summary] Freqency 1600
3910 10:02:47.183129 CH 0, Rank 0
3911 10:02:47.183549 All Pass.
3912 10:02:47.183900
3913 10:02:47.185915 CH 0, Rank 1
3914 10:02:47.186391 All Pass.
3915 10:02:47.186760
3916 10:02:47.187184 CH 1, Rank 0
3917 10:02:47.189442 All Pass.
3918 10:02:47.190010
3919 10:02:47.190376 CH 1, Rank 1
3920 10:02:47.190718 All Pass.
3921 10:02:47.192594
3922 10:02:47.195934 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3923 10:02:47.206200 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3924 10:02:47.212896 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3925 10:02:47.213418 Write Rank0 MR3 =0xb0
3926 10:02:47.218949 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3927 10:02:47.226017 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3928 10:02:47.232597 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3929 10:02:47.235954 Write Rank1 MR3 =0xb0
3930 10:02:47.243230 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3931 10:02:47.249475 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3932 10:02:47.256314 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3933 10:02:47.259319 Write Rank0 MR3 =0xb0
3934 10:02:47.266060 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3935 10:02:47.272350 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3936 10:02:47.279491 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3937 10:02:47.282459 Write Rank1 MR3 =0xb0
3938 10:02:47.283019 DramC Write-DBI on
3939 10:02:47.285603 [GetDramInforAfterCalByMRR] Vendor 6.
3940 10:02:47.289461 [GetDramInforAfterCalByMRR] Revision 505.
3941 10:02:47.292591 MR8 1111
3942 10:02:47.295993 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3943 10:02:47.296591 MR8 1111
3944 10:02:47.302310 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3945 10:02:47.302872 MR8 1111
3946 10:02:47.305786 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3947 10:02:47.309248 MR8 1111
3948 10:02:47.312159 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3949 10:02:47.322202 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3950 10:02:47.322774 Write Rank0 MR13 =0xd0
3951 10:02:47.325404 Write Rank1 MR13 =0xd0
3952 10:02:47.328935 Write Rank0 MR13 =0xd0
3953 10:02:47.329496 Write Rank1 MR13 =0xd0
3954 10:02:47.332174 Save calibration result to emmc
3955 10:02:47.332734
3956 10:02:47.333098
3957 10:02:47.335462 [DramcModeReg_Check] Freq_1600, FSP_1
3958 10:02:47.338589 FSP_1, CH_0, RK0
3959 10:02:47.339067 Write Rank0 MR13 =0xd8
3960 10:02:47.341657 MR12 = 0x5e (global = 0x5e) match
3961 10:02:47.345174 MR14 = 0x1c (global = 0x1c) match
3962 10:02:47.348637 FSP_1, CH_0, RK1
3963 10:02:47.349104 Write Rank1 MR13 =0xd8
3964 10:02:47.351939 MR12 = 0x5e (global = 0x5e) match
3965 10:02:47.355033 MR14 = 0x20 (global = 0x20) match
3966 10:02:47.358493 FSP_1, CH_1, RK0
3967 10:02:47.359019 Write Rank0 MR13 =0xd8
3968 10:02:47.361909 MR12 = 0x60 (global = 0x60) match
3969 10:02:47.365214 MR14 = 0x20 (global = 0x20) match
3970 10:02:47.368361 FSP_1, CH_1, RK1
3971 10:02:47.368782 Write Rank1 MR13 =0xd8
3972 10:02:47.371597 MR12 = 0x5e (global = 0x5e) match
3973 10:02:47.375221 MR14 = 0x20 (global = 0x20) match
3974 10:02:47.375670
3975 10:02:47.381833 [MEM_TEST] 02: After DFS, before run time config
3976 10:02:47.392164 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3977 10:02:47.392720
3978 10:02:47.393093 [TA2_TEST]
3979 10:02:47.393436 === TA2 HW
3980 10:02:47.394965 TA2 PAT: XTALK
3981 10:02:47.398547 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3982 10:02:47.405397 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3983 10:02:47.408264 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3984 10:02:47.411881 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3985 10:02:47.412431
3986 10:02:47.415007
3987 10:02:47.415460 Settings after calibration
3988 10:02:47.415829
3989 10:02:47.418009 [DramcRunTimeConfig]
3990 10:02:47.421394 TransferPLLToSPMControl - MODE SW PHYPLL
3991 10:02:47.421812 TX_TRACKING: ON
3992 10:02:47.425220 RX_TRACKING: ON
3993 10:02:47.425735 HW_GATING: ON
3994 10:02:47.428245 HW_GATING DBG: OFF
3995 10:02:47.428677 ddr_geometry:1
3996 10:02:47.431860 ddr_geometry:1
3997 10:02:47.432381 ddr_geometry:1
3998 10:02:47.432715 ddr_geometry:1
3999 10:02:47.435219 ddr_geometry:1
4000 10:02:47.435781 ddr_geometry:1
4001 10:02:47.438173 ddr_geometry:1
4002 10:02:47.438672 ddr_geometry:1
4003 10:02:47.441671 High Freq DUMMY_READ_FOR_TRACKING: ON
4004 10:02:47.444876 ZQCS_ENABLE_LP4: OFF
4005 10:02:47.447949 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
4006 10:02:47.451729 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
4007 10:02:47.452240 SPM_CONTROL_AFTERK: ON
4008 10:02:47.454710 IMPEDANCE_TRACKING: ON
4009 10:02:47.455125 TEMP_SENSOR: ON
4010 10:02:47.458603 PER_BANK_REFRESH: ON
4011 10:02:47.459116 HW_SAVE_FOR_SR: ON
4012 10:02:47.461650 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4013 10:02:47.464789 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
4014 10:02:47.467947 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
4015 10:02:47.471561 Read ODT Tracking: ON
4016 10:02:47.475105 =========================
4017 10:02:47.475710
4018 10:02:47.476076 [TA2_TEST]
4019 10:02:47.476489 === TA2 HW
4020 10:02:47.481032 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
4021 10:02:47.484341 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
4022 10:02:47.491390 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
4023 10:02:47.494529 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
4024 10:02:47.495082
4025 10:02:47.498043 [MEM_TEST] 03: After run time config
4026 10:02:47.509539 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
4027 10:02:47.512870 [complex_mem_test] start addr:0x40024000, len:131072
4028 10:02:47.717274 1st complex R/W mem test pass
4029 10:02:47.723543 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
4030 10:02:47.727027 sync preloader write leveling
4031 10:02:47.730770 sync preloader cbt_mr12
4032 10:02:47.733987 sync preloader cbt_clk_dly
4033 10:02:47.734543 sync preloader cbt_cmd_dly
4034 10:02:47.737126 sync preloader cbt_cs
4035 10:02:47.740265 sync preloader cbt_ca_perbit_delay
4036 10:02:47.740729 sync preloader clk_delay
4037 10:02:47.743971 sync preloader dqs_delay
4038 10:02:47.747272 sync preloader u1Gating2T_Save
4039 10:02:47.750529 sync preloader u1Gating05T_Save
4040 10:02:47.753475 sync preloader u1Gatingfine_tune_Save
4041 10:02:47.757346 sync preloader u1Gatingucpass_count_Save
4042 10:02:47.760256 sync preloader u1TxWindowPerbitVref_Save
4043 10:02:47.763745 sync preloader u1TxCenter_min_Save
4044 10:02:47.766880 sync preloader u1TxCenter_max_Save
4045 10:02:47.770870 sync preloader u1Txwin_center_Save
4046 10:02:47.773810 sync preloader u1Txfirst_pass_Save
4047 10:02:47.777197 sync preloader u1Txlast_pass_Save
4048 10:02:47.777664 sync preloader u1RxDatlat_Save
4049 10:02:47.779994 sync preloader u1RxWinPerbitVref_Save
4050 10:02:47.787273 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4051 10:02:47.790317 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4052 10:02:47.793776 sync preloader delay_cell_unit
4053 10:02:47.799992 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4054 10:02:47.804304 sync preloader write leveling
4055 10:02:47.804861 sync preloader cbt_mr12
4056 10:02:47.806725 sync preloader cbt_clk_dly
4057 10:02:47.810750 sync preloader cbt_cmd_dly
4058 10:02:47.811312 sync preloader cbt_cs
4059 10:02:47.813714 sync preloader cbt_ca_perbit_delay
4060 10:02:47.816938 sync preloader clk_delay
4061 10:02:47.820374 sync preloader dqs_delay
4062 10:02:47.820929 sync preloader u1Gating2T_Save
4063 10:02:47.823512 sync preloader u1Gating05T_Save
4064 10:02:47.827202 sync preloader u1Gatingfine_tune_Save
4065 10:02:47.830464 sync preloader u1Gatingucpass_count_Save
4066 10:02:47.833464 sync preloader u1TxWindowPerbitVref_Save
4067 10:02:47.836548 sync preloader u1TxCenter_min_Save
4068 10:02:47.839777 sync preloader u1TxCenter_max_Save
4069 10:02:47.843440 sync preloader u1Txwin_center_Save
4070 10:02:47.846563 sync preloader u1Txfirst_pass_Save
4071 10:02:47.850025 sync preloader u1Txlast_pass_Save
4072 10:02:47.853214 sync preloader u1RxDatlat_Save
4073 10:02:47.856216 sync preloader u1RxWinPerbitVref_Save
4074 10:02:47.859727 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4075 10:02:47.862914 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4076 10:02:47.866472 sync preloader delay_cell_unit
4077 10:02:47.873248 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4078 10:02:47.876282 sync preloader write leveling
4079 10:02:47.879973 sync preloader cbt_mr12
4080 10:02:47.880698 sync preloader cbt_clk_dly
4081 10:02:47.882991 sync preloader cbt_cmd_dly
4082 10:02:47.886245 sync preloader cbt_cs
4083 10:02:47.889686 sync preloader cbt_ca_perbit_delay
4084 10:02:47.890100 sync preloader clk_delay
4085 10:02:47.893012 sync preloader dqs_delay
4086 10:02:47.896259 sync preloader u1Gating2T_Save
4087 10:02:47.899603 sync preloader u1Gating05T_Save
4088 10:02:47.903176 sync preloader u1Gatingfine_tune_Save
4089 10:02:47.906790 sync preloader u1Gatingucpass_count_Save
4090 10:02:47.910055 sync preloader u1TxWindowPerbitVref_Save
4091 10:02:47.913233 sync preloader u1TxCenter_min_Save
4092 10:02:47.916784 sync preloader u1TxCenter_max_Save
4093 10:02:47.919833 sync preloader u1Txwin_center_Save
4094 10:02:47.923465 sync preloader u1Txfirst_pass_Save
4095 10:02:47.926756 sync preloader u1Txlast_pass_Save
4096 10:02:47.927290 sync preloader u1RxDatlat_Save
4097 10:02:47.929639 sync preloader u1RxWinPerbitVref_Save
4098 10:02:47.936345 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4099 10:02:47.939858 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4100 10:02:47.943006 sync preloader delay_cell_unit
4101 10:02:47.946589 just_for_test_dump_coreboot_params dump all params
4102 10:02:47.949709 dump source = 0x0
4103 10:02:47.950135 dump params frequency:1600
4104 10:02:47.952845 dump params rank number:2
4105 10:02:47.953278
4106 10:02:47.956105 dump params write leveling
4107 10:02:47.960000 write leveling[0][0][0] = 0x20
4108 10:02:47.960520 write leveling[0][0][1] = 0x18
4109 10:02:47.962971 write leveling[0][1][0] = 0x1a
4110 10:02:47.966705 write leveling[0][1][1] = 0x18
4111 10:02:47.969548 write leveling[1][0][0] = 0x21
4112 10:02:47.973177 write leveling[1][0][1] = 0x18
4113 10:02:47.976548 write leveling[1][1][0] = 0x22
4114 10:02:47.976975 write leveling[1][1][1] = 0x18
4115 10:02:47.979659 dump params cbt_cs
4116 10:02:47.980363 cbt_cs[0][0] = 0x8
4117 10:02:47.982889 cbt_cs[0][1] = 0x8
4118 10:02:47.986525 cbt_cs[1][0] = 0xb
4119 10:02:47.986946 cbt_cs[1][1] = 0xb
4120 10:02:47.989757 dump params cbt_mr12
4121 10:02:47.990179 cbt_mr12[0][0] = 0x1e
4122 10:02:47.993038 cbt_mr12[0][1] = 0x1e
4123 10:02:47.993556 cbt_mr12[1][0] = 0x20
4124 10:02:47.996626 cbt_mr12[1][1] = 0x1e
4125 10:02:48.000197 dump params tx window
4126 10:02:48.000712 tx_center_min[0][0][0] = 981
4127 10:02:48.003023 tx_center_max[0][0][0] = 988
4128 10:02:48.006478 tx_center_min[0][0][1] = 975
4129 10:02:48.010083 tx_center_max[0][0][1] = 981
4130 10:02:48.010599 tx_center_min[0][1][0] = 979
4131 10:02:48.013012 tx_center_max[0][1][0] = 985
4132 10:02:48.016278 tx_center_min[0][1][1] = 978
4133 10:02:48.019661 tx_center_max[0][1][1] = 984
4134 10:02:48.022881 tx_center_min[1][0][0] = 988
4135 10:02:48.023293 tx_center_max[1][0][0] = 993
4136 10:02:48.026176 tx_center_min[1][0][1] = 976
4137 10:02:48.029700 tx_center_max[1][0][1] = 983
4138 10:02:48.032785 tx_center_min[1][1][0] = 986
4139 10:02:48.036281 tx_center_max[1][1][0] = 991
4140 10:02:48.036844 tx_center_min[1][1][1] = 975
4141 10:02:48.039165 tx_center_max[1][1][1] = 981
4142 10:02:48.042788 dump params tx window
4143 10:02:48.046251 tx_win_center[0][0][0] = 988
4144 10:02:48.046784 tx_first_pass[0][0][0] = 976
4145 10:02:48.049201 tx_last_pass[0][0][0] = 1000
4146 10:02:48.052692 tx_win_center[0][0][1] = 987
4147 10:02:48.056402 tx_first_pass[0][0][1] = 975
4148 10:02:48.059932 tx_last_pass[0][0][1] = 999
4149 10:02:48.060465 tx_win_center[0][0][2] = 988
4150 10:02:48.062588 tx_first_pass[0][0][2] = 976
4151 10:02:48.066006 tx_last_pass[0][0][2] = 1000
4152 10:02:48.069527 tx_win_center[0][0][3] = 981
4153 10:02:48.069960 tx_first_pass[0][0][3] = 969
4154 10:02:48.072779 tx_last_pass[0][0][3] = 993
4155 10:02:48.076127 tx_win_center[0][0][4] = 987
4156 10:02:48.079015 tx_first_pass[0][0][4] = 975
4157 10:02:48.082367 tx_last_pass[0][0][4] = 999
4158 10:02:48.082797 tx_win_center[0][0][5] = 983
4159 10:02:48.086461 tx_first_pass[0][0][5] = 971
4160 10:02:48.089248 tx_last_pass[0][0][5] = 995
4161 10:02:48.092915 tx_win_center[0][0][6] = 985
4162 10:02:48.093446 tx_first_pass[0][0][6] = 973
4163 10:02:48.095759 tx_last_pass[0][0][6] = 998
4164 10:02:48.099392 tx_win_center[0][0][7] = 987
4165 10:02:48.102363 tx_first_pass[0][0][7] = 975
4166 10:02:48.106544 tx_last_pass[0][0][7] = 999
4167 10:02:48.107076 tx_win_center[0][0][8] = 975
4168 10:02:48.109437 tx_first_pass[0][0][8] = 963
4169 10:02:48.112378 tx_last_pass[0][0][8] = 987
4170 10:02:48.115902 tx_win_center[0][0][9] = 978
4171 10:02:48.116432 tx_first_pass[0][0][9] = 967
4172 10:02:48.119111 tx_last_pass[0][0][9] = 989
4173 10:02:48.122409 tx_win_center[0][0][10] = 981
4174 10:02:48.125929 tx_first_pass[0][0][10] = 969
4175 10:02:48.128682 tx_last_pass[0][0][10] = 994
4176 10:02:48.129107 tx_win_center[0][0][11] = 977
4177 10:02:48.132152 tx_first_pass[0][0][11] = 965
4178 10:02:48.135779 tx_last_pass[0][0][11] = 989
4179 10:02:48.138803 tx_win_center[0][0][12] = 978
4180 10:02:48.142053 tx_first_pass[0][0][12] = 967
4181 10:02:48.145582 tx_last_pass[0][0][12] = 990
4182 10:02:48.146005 tx_win_center[0][0][13] = 978
4183 10:02:48.148743 tx_first_pass[0][0][13] = 967
4184 10:02:48.152417 tx_last_pass[0][0][13] = 990
4185 10:02:48.155485 tx_win_center[0][0][14] = 979
4186 10:02:48.158688 tx_first_pass[0][0][14] = 967
4187 10:02:48.159112 tx_last_pass[0][0][14] = 991
4188 10:02:48.162259 tx_win_center[0][0][15] = 981
4189 10:02:48.165591 tx_first_pass[0][0][15] = 969
4190 10:02:48.168691 tx_last_pass[0][0][15] = 993
4191 10:02:48.171880 tx_win_center[0][1][0] = 985
4192 10:02:48.172304 tx_first_pass[0][1][0] = 973
4193 10:02:48.175931 tx_last_pass[0][1][0] = 998
4194 10:02:48.178969 tx_win_center[0][1][1] = 984
4195 10:02:48.182199 tx_first_pass[0][1][1] = 972
4196 10:02:48.182748 tx_last_pass[0][1][1] = 996
4197 10:02:48.185128 tx_win_center[0][1][2] = 985
4198 10:02:48.188947 tx_first_pass[0][1][2] = 973
4199 10:02:48.191958 tx_last_pass[0][1][2] = 998
4200 10:02:48.195266 tx_win_center[0][1][3] = 979
4201 10:02:48.195814 tx_first_pass[0][1][3] = 968
4202 10:02:48.198520 tx_last_pass[0][1][3] = 991
4203 10:02:48.202118 tx_win_center[0][1][4] = 983
4204 10:02:48.205458 tx_first_pass[0][1][4] = 971
4205 10:02:48.205984 tx_last_pass[0][1][4] = 996
4206 10:02:48.208319 tx_win_center[0][1][5] = 980
4207 10:02:48.212187 tx_first_pass[0][1][5] = 968
4208 10:02:48.215227 tx_last_pass[0][1][5] = 993
4209 10:02:48.219102 tx_win_center[0][1][6] = 982
4210 10:02:48.219656 tx_first_pass[0][1][6] = 969
4211 10:02:48.221671 tx_last_pass[0][1][6] = 995
4212 10:02:48.225254 tx_win_center[0][1][7] = 983
4213 10:02:48.228754 tx_first_pass[0][1][7] = 971
4214 10:02:48.229275 tx_last_pass[0][1][7] = 996
4215 10:02:48.232147 tx_win_center[0][1][8] = 978
4216 10:02:48.235115 tx_first_pass[0][1][8] = 966
4217 10:02:48.238722 tx_last_pass[0][1][8] = 990
4218 10:02:48.241875 tx_win_center[0][1][9] = 979
4219 10:02:48.242337 tx_first_pass[0][1][9] = 968
4220 10:02:48.245115 tx_last_pass[0][1][9] = 990
4221 10:02:48.248214 tx_win_center[0][1][10] = 984
4222 10:02:48.251605 tx_first_pass[0][1][10] = 972
4223 10:02:48.255049 tx_last_pass[0][1][10] = 997
4224 10:02:48.255599 tx_win_center[0][1][11] = 978
4225 10:02:48.258824 tx_first_pass[0][1][11] = 967
4226 10:02:48.261826 tx_last_pass[0][1][11] = 990
4227 10:02:48.265343 tx_win_center[0][1][12] = 980
4228 10:02:48.268588 tx_first_pass[0][1][12] = 968
4229 10:02:48.269014 tx_last_pass[0][1][12] = 992
4230 10:02:48.271849 tx_win_center[0][1][13] = 980
4231 10:02:48.275108 tx_first_pass[0][1][13] = 969
4232 10:02:48.278658 tx_last_pass[0][1][13] = 992
4233 10:02:48.281885 tx_win_center[0][1][14] = 980
4234 10:02:48.282309 tx_first_pass[0][1][14] = 968
4235 10:02:48.285142 tx_last_pass[0][1][14] = 992
4236 10:02:48.288262 tx_win_center[0][1][15] = 983
4237 10:02:48.292250 tx_first_pass[0][1][15] = 971
4238 10:02:48.295013 tx_last_pass[0][1][15] = 995
4239 10:02:48.295655 tx_win_center[1][0][0] = 992
4240 10:02:48.298242 tx_first_pass[1][0][0] = 979
4241 10:02:48.302062 tx_last_pass[1][0][0] = 1006
4242 10:02:48.305067 tx_win_center[1][0][1] = 991
4243 10:02:48.305573 tx_first_pass[1][0][1] = 978
4244 10:02:48.308647 tx_last_pass[1][0][1] = 1005
4245 10:02:48.311919 tx_win_center[1][0][2] = 989
4246 10:02:48.315386 tx_first_pass[1][0][2] = 977
4247 10:02:48.318719 tx_last_pass[1][0][2] = 1002
4248 10:02:48.319251 tx_win_center[1][0][3] = 988
4249 10:02:48.321816 tx_first_pass[1][0][3] = 976
4250 10:02:48.324743 tx_last_pass[1][0][3] = 1000
4251 10:02:48.328304 tx_win_center[1][0][4] = 992
4252 10:02:48.331671 tx_first_pass[1][0][4] = 979
4253 10:02:48.332181 tx_last_pass[1][0][4] = 1005
4254 10:02:48.335445 tx_win_center[1][0][5] = 993
4255 10:02:48.338491 tx_first_pass[1][0][5] = 980
4256 10:02:48.341529 tx_last_pass[1][0][5] = 1006
4257 10:02:48.341993 tx_win_center[1][0][6] = 991
4258 10:02:48.345183 tx_first_pass[1][0][6] = 978
4259 10:02:48.348698 tx_last_pass[1][0][6] = 1005
4260 10:02:48.351278 tx_win_center[1][0][7] = 991
4261 10:02:48.354874 tx_first_pass[1][0][7] = 978
4262 10:02:48.355345 tx_last_pass[1][0][7] = 1005
4263 10:02:48.358122 tx_win_center[1][0][8] = 979
4264 10:02:48.361899 tx_first_pass[1][0][8] = 968
4265 10:02:48.364758 tx_last_pass[1][0][8] = 991
4266 10:02:48.368142 tx_win_center[1][0][9] = 980
4267 10:02:48.368565 tx_first_pass[1][0][9] = 969
4268 10:02:48.371572 tx_last_pass[1][0][9] = 991
4269 10:02:48.375772 tx_win_center[1][0][10] = 981
4270 10:02:48.378515 tx_first_pass[1][0][10] = 970
4271 10:02:48.379034 tx_last_pass[1][0][10] = 993
4272 10:02:48.381509 tx_win_center[1][0][11] = 982
4273 10:02:48.385090 tx_first_pass[1][0][11] = 970
4274 10:02:48.388249 tx_last_pass[1][0][11] = 994
4275 10:02:48.391472 tx_win_center[1][0][12] = 982
4276 10:02:48.391897 tx_first_pass[1][0][12] = 971
4277 10:02:48.395325 tx_last_pass[1][0][12] = 993
4278 10:02:48.398420 tx_win_center[1][0][13] = 983
4279 10:02:48.401591 tx_first_pass[1][0][13] = 972
4280 10:02:48.405330 tx_last_pass[1][0][13] = 994
4281 10:02:48.405846 tx_win_center[1][0][14] = 982
4282 10:02:48.408189 tx_first_pass[1][0][14] = 971
4283 10:02:48.412029 tx_last_pass[1][0][14] = 993
4284 10:02:48.414835 tx_win_center[1][0][15] = 976
4285 10:02:48.418091 tx_first_pass[1][0][15] = 965
4286 10:02:48.418514 tx_last_pass[1][0][15] = 987
4287 10:02:48.421796 tx_win_center[1][1][0] = 991
4288 10:02:48.424838 tx_first_pass[1][1][0] = 978
4289 10:02:48.428345 tx_last_pass[1][1][0] = 1005
4290 10:02:48.431629 tx_win_center[1][1][1] = 989
4291 10:02:48.432135 tx_first_pass[1][1][1] = 977
4292 10:02:48.435159 tx_last_pass[1][1][1] = 1002
4293 10:02:48.438611 tx_win_center[1][1][2] = 989
4294 10:02:48.441289 tx_first_pass[1][1][2] = 977
4295 10:02:48.444892 tx_last_pass[1][1][2] = 1001
4296 10:02:48.445427 tx_win_center[1][1][3] = 986
4297 10:02:48.448135 tx_first_pass[1][1][3] = 974
4298 10:02:48.451786 tx_last_pass[1][1][3] = 998
4299 10:02:48.454995 tx_win_center[1][1][4] = 990
4300 10:02:48.455566 tx_first_pass[1][1][4] = 978
4301 10:02:48.458170 tx_last_pass[1][1][4] = 1003
4302 10:02:48.461872 tx_win_center[1][1][5] = 991
4303 10:02:48.464867 tx_first_pass[1][1][5] = 978
4304 10:02:48.468323 tx_last_pass[1][1][5] = 1005
4305 10:02:48.468745 tx_win_center[1][1][6] = 990
4306 10:02:48.471582 tx_first_pass[1][1][6] = 977
4307 10:02:48.475134 tx_last_pass[1][1][6] = 1004
4308 10:02:48.478523 tx_win_center[1][1][7] = 990
4309 10:02:48.481520 tx_first_pass[1][1][7] = 978
4310 10:02:48.481948 tx_last_pass[1][1][7] = 1002
4311 10:02:48.484442 tx_win_center[1][1][8] = 978
4312 10:02:48.488394 tx_first_pass[1][1][8] = 967
4313 10:02:48.491642 tx_last_pass[1][1][8] = 990
4314 10:02:48.492187 tx_win_center[1][1][9] = 978
4315 10:02:48.495015 tx_first_pass[1][1][9] = 967
4316 10:02:48.498190 tx_last_pass[1][1][9] = 990
4317 10:02:48.501521 tx_win_center[1][1][10] = 980
4318 10:02:48.505059 tx_first_pass[1][1][10] = 969
4319 10:02:48.505571 tx_last_pass[1][1][10] = 992
4320 10:02:48.507961 tx_win_center[1][1][11] = 981
4321 10:02:48.511634 tx_first_pass[1][1][11] = 969
4322 10:02:48.514906 tx_last_pass[1][1][11] = 993
4323 10:02:48.518350 tx_win_center[1][1][12] = 981
4324 10:02:48.518867 tx_first_pass[1][1][12] = 970
4325 10:02:48.521989 tx_last_pass[1][1][12] = 993
4326 10:02:48.524627 tx_win_center[1][1][13] = 981
4327 10:02:48.528060 tx_first_pass[1][1][13] = 970
4328 10:02:48.531558 tx_last_pass[1][1][13] = 993
4329 10:02:48.532119 tx_win_center[1][1][14] = 981
4330 10:02:48.534679 tx_first_pass[1][1][14] = 969
4331 10:02:48.538023 tx_last_pass[1][1][14] = 993
4332 10:02:48.541416 tx_win_center[1][1][15] = 975
4333 10:02:48.544344 tx_first_pass[1][1][15] = 963
4334 10:02:48.544812 tx_last_pass[1][1][15] = 987
4335 10:02:48.548281 dump params rx window
4336 10:02:48.551325 rx_firspass[0][0][0] = 4
4337 10:02:48.551939 rx_lastpass[0][0][0] = 38
4338 10:02:48.554778 rx_firspass[0][0][1] = 5
4339 10:02:48.558188 rx_lastpass[0][0][1] = 36
4340 10:02:48.561595 rx_firspass[0][0][2] = 6
4341 10:02:48.562161 rx_lastpass[0][0][2] = 36
4342 10:02:48.564554 rx_firspass[0][0][3] = -2
4343 10:02:48.567800 rx_lastpass[0][0][3] = 31
4344 10:02:48.568265 rx_firspass[0][0][4] = 4
4345 10:02:48.571395 rx_lastpass[0][0][4] = 37
4346 10:02:48.574583 rx_firspass[0][0][5] = 1
4347 10:02:48.575002 rx_lastpass[0][0][5] = 32
4348 10:02:48.578061 rx_firspass[0][0][6] = 3
4349 10:02:48.580988 rx_lastpass[0][0][6] = 34
4350 10:02:48.584685 rx_firspass[0][0][7] = 5
4351 10:02:48.585105 rx_lastpass[0][0][7] = 36
4352 10:02:48.587918 rx_firspass[0][0][8] = -4
4353 10:02:48.591180 rx_lastpass[0][0][8] = 33
4354 10:02:48.591738 rx_firspass[0][0][9] = 0
4355 10:02:48.594684 rx_lastpass[0][0][9] = 32
4356 10:02:48.598009 rx_firspass[0][0][10] = 7
4357 10:02:48.601582 rx_lastpass[0][0][10] = 41
4358 10:02:48.602091 rx_firspass[0][0][11] = 1
4359 10:02:48.604473 rx_lastpass[0][0][11] = 32
4360 10:02:48.607753 rx_firspass[0][0][12] = 1
4361 10:02:48.608172 rx_lastpass[0][0][12] = 37
4362 10:02:48.610820 rx_firspass[0][0][13] = 3
4363 10:02:48.614035 rx_lastpass[0][0][13] = 33
4364 10:02:48.617605 rx_firspass[0][0][14] = 2
4365 10:02:48.618021 rx_lastpass[0][0][14] = 37
4366 10:02:48.620777 rx_firspass[0][0][15] = 5
4367 10:02:48.624573 rx_lastpass[0][0][15] = 37
4368 10:02:48.624990 rx_firspass[0][1][0] = 6
4369 10:02:48.627612 rx_lastpass[0][1][0] = 40
4370 10:02:48.631002 rx_firspass[0][1][1] = 5
4371 10:02:48.634464 rx_lastpass[0][1][1] = 38
4372 10:02:48.635122 rx_firspass[0][1][2] = 6
4373 10:02:48.637669 rx_lastpass[0][1][2] = 38
4374 10:02:48.641060 rx_firspass[0][1][3] = -2
4375 10:02:48.641553 rx_lastpass[0][1][3] = 33
4376 10:02:48.644309 rx_firspass[0][1][4] = 5
4377 10:02:48.647568 rx_lastpass[0][1][4] = 39
4378 10:02:48.651061 rx_firspass[0][1][5] = 1
4379 10:02:48.651608 rx_lastpass[0][1][5] = 34
4380 10:02:48.654374 rx_firspass[0][1][6] = 3
4381 10:02:48.657333 rx_lastpass[0][1][6] = 37
4382 10:02:48.657754 rx_firspass[0][1][7] = 3
4383 10:02:48.660904 rx_lastpass[0][1][7] = 38
4384 10:02:48.663860 rx_firspass[0][1][8] = -2
4385 10:02:48.664475 rx_lastpass[0][1][8] = 32
4386 10:02:48.667370 rx_firspass[0][1][9] = 1
4387 10:02:48.670967 rx_lastpass[0][1][9] = 36
4388 10:02:48.673939 rx_firspass[0][1][10] = 7
4389 10:02:48.674356 rx_lastpass[0][1][10] = 43
4390 10:02:48.677555 rx_firspass[0][1][11] = -2
4391 10:02:48.680707 rx_lastpass[0][1][11] = 34
4392 10:02:48.681128 rx_firspass[0][1][12] = 1
4393 10:02:48.683964 rx_lastpass[0][1][12] = 37
4394 10:02:48.687562 rx_firspass[0][1][13] = 2
4395 10:02:48.691441 rx_lastpass[0][1][13] = 35
4396 10:02:48.691965 rx_firspass[0][1][14] = 2
4397 10:02:48.694146 rx_lastpass[0][1][14] = 37
4398 10:02:48.697781 rx_firspass[0][1][15] = 6
4399 10:02:48.700576 rx_lastpass[0][1][15] = 39
4400 10:02:48.700996 rx_firspass[1][0][0] = 5
4401 10:02:48.704452 rx_lastpass[1][0][0] = 39
4402 10:02:48.707827 rx_firspass[1][0][1] = 5
4403 10:02:48.708334 rx_lastpass[1][0][1] = 38
4404 10:02:48.710908 rx_firspass[1][0][2] = 2
4405 10:02:48.714606 rx_lastpass[1][0][2] = 36
4406 10:02:48.715116 rx_firspass[1][0][3] = -1
4407 10:02:48.717999 rx_lastpass[1][0][3] = 33
4408 10:02:48.720632 rx_firspass[1][0][4] = 5
4409 10:02:48.724141 rx_lastpass[1][0][4] = 38
4410 10:02:48.724641 rx_firspass[1][0][5] = 7
4411 10:02:48.727273 rx_lastpass[1][0][5] = 39
4412 10:02:48.730506 rx_firspass[1][0][6] = 6
4413 10:02:48.731010 rx_lastpass[1][0][6] = 40
4414 10:02:48.734273 rx_firspass[1][0][7] = 5
4415 10:02:48.737439 rx_lastpass[1][0][7] = 38
4416 10:02:48.737942 rx_firspass[1][0][8] = 1
4417 10:02:48.740945 rx_lastpass[1][0][8] = 33
4418 10:02:48.743846 rx_firspass[1][0][9] = 0
4419 10:02:48.747580 rx_lastpass[1][0][9] = 32
4420 10:02:48.748052 rx_firspass[1][0][10] = 5
4421 10:02:48.751111 rx_lastpass[1][0][10] = 35
4422 10:02:48.754624 rx_firspass[1][0][11] = 5
4423 10:02:48.755135 rx_lastpass[1][0][11] = 38
4424 10:02:48.757320 rx_firspass[1][0][12] = 6
4425 10:02:48.761136 rx_lastpass[1][0][12] = 38
4426 10:02:48.764579 rx_firspass[1][0][13] = 5
4427 10:02:48.765087 rx_lastpass[1][0][13] = 37
4428 10:02:48.767667 rx_firspass[1][0][14] = 6
4429 10:02:48.770884 rx_lastpass[1][0][14] = 38
4430 10:02:48.774323 rx_firspass[1][0][15] = -3
4431 10:02:48.774776 rx_lastpass[1][0][15] = 30
4432 10:02:48.777760 rx_firspass[1][1][0] = 4
4433 10:02:48.781471 rx_lastpass[1][1][0] = 40
4434 10:02:48.781986 rx_firspass[1][1][1] = 4
4435 10:02:48.784089 rx_lastpass[1][1][1] = 39
4436 10:02:48.788298 rx_firspass[1][1][2] = 0
4437 10:02:48.788717 rx_lastpass[1][1][2] = 36
4438 10:02:48.791303 rx_firspass[1][1][3] = -2
4439 10:02:48.794373 rx_lastpass[1][1][3] = 34
4440 10:02:48.797900 rx_firspass[1][1][4] = 4
4441 10:02:48.798357 rx_lastpass[1][1][4] = 39
4442 10:02:48.800931 rx_firspass[1][1][5] = 5
4443 10:02:48.804298 rx_lastpass[1][1][5] = 40
4444 10:02:48.804741 rx_firspass[1][1][6] = 5
4445 10:02:48.807393 rx_lastpass[1][1][6] = 41
4446 10:02:48.810803 rx_firspass[1][1][7] = 3
4447 10:02:48.811221 rx_lastpass[1][1][7] = 38
4448 10:02:48.814205 rx_firspass[1][1][8] = 0
4449 10:02:48.818061 rx_lastpass[1][1][8] = 35
4450 10:02:48.821442 rx_firspass[1][1][9] = -1
4451 10:02:48.821959 rx_lastpass[1][1][9] = 34
4452 10:02:48.824194 rx_firspass[1][1][10] = 3
4453 10:02:48.827699 rx_lastpass[1][1][10] = 38
4454 10:02:48.828215 rx_firspass[1][1][11] = 4
4455 10:02:48.831005 rx_lastpass[1][1][11] = 40
4456 10:02:48.834353 rx_firspass[1][1][12] = 4
4457 10:02:48.837866 rx_lastpass[1][1][12] = 40
4458 10:02:48.838389 rx_firspass[1][1][13] = 4
4459 10:02:48.840933 rx_lastpass[1][1][13] = 39
4460 10:02:48.844044 rx_firspass[1][1][14] = 5
4461 10:02:48.844582 rx_lastpass[1][1][14] = 40
4462 10:02:48.847332 rx_firspass[1][1][15] = -3
4463 10:02:48.850969 rx_lastpass[1][1][15] = 31
4464 10:02:48.854585 dump params clk_delay
4465 10:02:48.855005 clk_delay[0] = 1
4466 10:02:48.855338 clk_delay[1] = 0
4467 10:02:48.857446 dump params dqs_delay
4468 10:02:48.861230 dqs_delay[0][0] = -2
4469 10:02:48.861744 dqs_delay[0][1] = 0
4470 10:02:48.864642 dqs_delay[1][0] = 0
4471 10:02:48.865157 dqs_delay[1][1] = 0
4472 10:02:48.867530 dump params delay_cell_unit = 735
4473 10:02:48.870637 dump source = 0x0
4474 10:02:48.871159 dump params frequency:1200
4475 10:02:48.873755 dump params rank number:2
4476 10:02:48.874180
4477 10:02:48.877820 dump params write leveling
4478 10:02:48.880950 write leveling[0][0][0] = 0x0
4479 10:02:48.883933 write leveling[0][0][1] = 0x0
4480 10:02:48.884359 write leveling[0][1][0] = 0x0
4481 10:02:48.887249 write leveling[0][1][1] = 0x0
4482 10:02:48.891162 write leveling[1][0][0] = 0x0
4483 10:02:48.894038 write leveling[1][0][1] = 0x0
4484 10:02:48.897093 write leveling[1][1][0] = 0x0
4485 10:02:48.897608 write leveling[1][1][1] = 0x0
4486 10:02:48.900438 dump params cbt_cs
4487 10:02:48.900873 cbt_cs[0][0] = 0x0
4488 10:02:48.903780 cbt_cs[0][1] = 0x0
4489 10:02:48.904206 cbt_cs[1][0] = 0x0
4490 10:02:48.906981 cbt_cs[1][1] = 0x0
4491 10:02:48.910291 dump params cbt_mr12
4492 10:02:48.910933 cbt_mr12[0][0] = 0x0
4493 10:02:48.913625 cbt_mr12[0][1] = 0x0
4494 10:02:48.914136 cbt_mr12[1][0] = 0x0
4495 10:02:48.916953 cbt_mr12[1][1] = 0x0
4496 10:02:48.917507 dump params tx window
4497 10:02:48.920288 tx_center_min[0][0][0] = 0
4498 10:02:48.924114 tx_center_max[0][0][0] = 0
4499 10:02:48.927266 tx_center_min[0][0][1] = 0
4500 10:02:48.927855 tx_center_max[0][0][1] = 0
4501 10:02:48.930305 tx_center_min[0][1][0] = 0
4502 10:02:48.934160 tx_center_max[0][1][0] = 0
4503 10:02:48.937343 tx_center_min[0][1][1] = 0
4504 10:02:48.937806 tx_center_max[0][1][1] = 0
4505 10:02:48.940705 tx_center_min[1][0][0] = 0
4506 10:02:48.943709 tx_center_max[1][0][0] = 0
4507 10:02:48.947098 tx_center_min[1][0][1] = 0
4508 10:02:48.947578 tx_center_max[1][0][1] = 0
4509 10:02:48.950083 tx_center_min[1][1][0] = 0
4510 10:02:48.953826 tx_center_max[1][1][0] = 0
4511 10:02:48.954251 tx_center_min[1][1][1] = 0
4512 10:02:48.956827 tx_center_max[1][1][1] = 0
4513 10:02:48.960737 dump params tx window
4514 10:02:48.963681 tx_win_center[0][0][0] = 0
4515 10:02:48.964130 tx_first_pass[0][0][0] = 0
4516 10:02:48.966992 tx_last_pass[0][0][0] = 0
4517 10:02:48.970741 tx_win_center[0][0][1] = 0
4518 10:02:48.971263 tx_first_pass[0][0][1] = 0
4519 10:02:48.973814 tx_last_pass[0][0][1] = 0
4520 10:02:48.977026 tx_win_center[0][0][2] = 0
4521 10:02:48.980430 tx_first_pass[0][0][2] = 0
4522 10:02:48.980844 tx_last_pass[0][0][2] = 0
4523 10:02:48.983667 tx_win_center[0][0][3] = 0
4524 10:02:48.987179 tx_first_pass[0][0][3] = 0
4525 10:02:48.990928 tx_last_pass[0][0][3] = 0
4526 10:02:48.991528 tx_win_center[0][0][4] = 0
4527 10:02:48.994237 tx_first_pass[0][0][4] = 0
4528 10:02:48.997278 tx_last_pass[0][0][4] = 0
4529 10:02:48.997797 tx_win_center[0][0][5] = 0
4530 10:02:49.000101 tx_first_pass[0][0][5] = 0
4531 10:02:49.003644 tx_last_pass[0][0][5] = 0
4532 10:02:49.007241 tx_win_center[0][0][6] = 0
4533 10:02:49.007788 tx_first_pass[0][0][6] = 0
4534 10:02:49.010234 tx_last_pass[0][0][6] = 0
4535 10:02:49.014039 tx_win_center[0][0][7] = 0
4536 10:02:49.016671 tx_first_pass[0][0][7] = 0
4537 10:02:49.017141 tx_last_pass[0][0][7] = 0
4538 10:02:49.020229 tx_win_center[0][0][8] = 0
4539 10:02:49.023353 tx_first_pass[0][0][8] = 0
4540 10:02:49.023814 tx_last_pass[0][0][8] = 0
4541 10:02:49.027083 tx_win_center[0][0][9] = 0
4542 10:02:49.030155 tx_first_pass[0][0][9] = 0
4543 10:02:49.033854 tx_last_pass[0][0][9] = 0
4544 10:02:49.034372 tx_win_center[0][0][10] = 0
4545 10:02:49.036981 tx_first_pass[0][0][10] = 0
4546 10:02:49.040144 tx_last_pass[0][0][10] = 0
4547 10:02:49.043240 tx_win_center[0][0][11] = 0
4548 10:02:49.043850 tx_first_pass[0][0][11] = 0
4549 10:02:49.047018 tx_last_pass[0][0][11] = 0
4550 10:02:49.050045 tx_win_center[0][0][12] = 0
4551 10:02:49.053420 tx_first_pass[0][0][12] = 0
4552 10:02:49.053996 tx_last_pass[0][0][12] = 0
4553 10:02:49.056500 tx_win_center[0][0][13] = 0
4554 10:02:49.060237 tx_first_pass[0][0][13] = 0
4555 10:02:49.063717 tx_last_pass[0][0][13] = 0
4556 10:02:49.064232 tx_win_center[0][0][14] = 0
4557 10:02:49.066857 tx_first_pass[0][0][14] = 0
4558 10:02:49.069978 tx_last_pass[0][0][14] = 0
4559 10:02:49.073115 tx_win_center[0][0][15] = 0
4560 10:02:49.073541 tx_first_pass[0][0][15] = 0
4561 10:02:49.076526 tx_last_pass[0][0][15] = 0
4562 10:02:49.080008 tx_win_center[0][1][0] = 0
4563 10:02:49.083152 tx_first_pass[0][1][0] = 0
4564 10:02:49.083628 tx_last_pass[0][1][0] = 0
4565 10:02:49.086889 tx_win_center[0][1][1] = 0
4566 10:02:49.089737 tx_first_pass[0][1][1] = 0
4567 10:02:49.093429 tx_last_pass[0][1][1] = 0
4568 10:02:49.093915 tx_win_center[0][1][2] = 0
4569 10:02:49.096660 tx_first_pass[0][1][2] = 0
4570 10:02:49.100040 tx_last_pass[0][1][2] = 0
4571 10:02:49.100520 tx_win_center[0][1][3] = 0
4572 10:02:49.103314 tx_first_pass[0][1][3] = 0
4573 10:02:49.106577 tx_last_pass[0][1][3] = 0
4574 10:02:49.109449 tx_win_center[0][1][4] = 0
4575 10:02:49.109874 tx_first_pass[0][1][4] = 0
4576 10:02:49.113347 tx_last_pass[0][1][4] = 0
4577 10:02:49.116860 tx_win_center[0][1][5] = 0
4578 10:02:49.120268 tx_first_pass[0][1][5] = 0
4579 10:02:49.120790 tx_last_pass[0][1][5] = 0
4580 10:02:49.122953 tx_win_center[0][1][6] = 0
4581 10:02:49.126893 tx_first_pass[0][1][6] = 0
4582 10:02:49.127483 tx_last_pass[0][1][6] = 0
4583 10:02:49.129488 tx_win_center[0][1][7] = 0
4584 10:02:49.133384 tx_first_pass[0][1][7] = 0
4585 10:02:49.136603 tx_last_pass[0][1][7] = 0
4586 10:02:49.137111 tx_win_center[0][1][8] = 0
4587 10:02:49.140010 tx_first_pass[0][1][8] = 0
4588 10:02:49.143104 tx_last_pass[0][1][8] = 0
4589 10:02:49.146190 tx_win_center[0][1][9] = 0
4590 10:02:49.146630 tx_first_pass[0][1][9] = 0
4591 10:02:49.149504 tx_last_pass[0][1][9] = 0
4592 10:02:49.152998 tx_win_center[0][1][10] = 0
4593 10:02:49.156282 tx_first_pass[0][1][10] = 0
4594 10:02:49.156820 tx_last_pass[0][1][10] = 0
4595 10:02:49.159999 tx_win_center[0][1][11] = 0
4596 10:02:49.162849 tx_first_pass[0][1][11] = 0
4597 10:02:49.166559 tx_last_pass[0][1][11] = 0
4598 10:02:49.167120 tx_win_center[0][1][12] = 0
4599 10:02:49.169484 tx_first_pass[0][1][12] = 0
4600 10:02:49.172945 tx_last_pass[0][1][12] = 0
4601 10:02:49.176749 tx_win_center[0][1][13] = 0
4602 10:02:49.177269 tx_first_pass[0][1][13] = 0
4603 10:02:49.179659 tx_last_pass[0][1][13] = 0
4604 10:02:49.182510 tx_win_center[0][1][14] = 0
4605 10:02:49.185685 tx_first_pass[0][1][14] = 0
4606 10:02:49.186129 tx_last_pass[0][1][14] = 0
4607 10:02:49.189409 tx_win_center[0][1][15] = 0
4608 10:02:49.192469 tx_first_pass[0][1][15] = 0
4609 10:02:49.196045 tx_last_pass[0][1][15] = 0
4610 10:02:49.196581 tx_win_center[1][0][0] = 0
4611 10:02:49.199391 tx_first_pass[1][0][0] = 0
4612 10:02:49.202902 tx_last_pass[1][0][0] = 0
4613 10:02:49.205738 tx_win_center[1][0][1] = 0
4614 10:02:49.206272 tx_first_pass[1][0][1] = 0
4615 10:02:49.209340 tx_last_pass[1][0][1] = 0
4616 10:02:49.212321 tx_win_center[1][0][2] = 0
4617 10:02:49.212745 tx_first_pass[1][0][2] = 0
4618 10:02:49.216093 tx_last_pass[1][0][2] = 0
4619 10:02:49.219304 tx_win_center[1][0][3] = 0
4620 10:02:49.222559 tx_first_pass[1][0][3] = 0
4621 10:02:49.223079 tx_last_pass[1][0][3] = 0
4622 10:02:49.225904 tx_win_center[1][0][4] = 0
4623 10:02:49.229480 tx_first_pass[1][0][4] = 0
4624 10:02:49.232630 tx_last_pass[1][0][4] = 0
4625 10:02:49.233151 tx_win_center[1][0][5] = 0
4626 10:02:49.235669 tx_first_pass[1][0][5] = 0
4627 10:02:49.238852 tx_last_pass[1][0][5] = 0
4628 10:02:49.239368 tx_win_center[1][0][6] = 0
4629 10:02:49.242330 tx_first_pass[1][0][6] = 0
4630 10:02:49.245846 tx_last_pass[1][0][6] = 0
4631 10:02:49.248824 tx_win_center[1][0][7] = 0
4632 10:02:49.249260 tx_first_pass[1][0][7] = 0
4633 10:02:49.252104 tx_last_pass[1][0][7] = 0
4634 10:02:49.255597 tx_win_center[1][0][8] = 0
4635 10:02:49.258929 tx_first_pass[1][0][8] = 0
4636 10:02:49.259485 tx_last_pass[1][0][8] = 0
4637 10:02:49.262322 tx_win_center[1][0][9] = 0
4638 10:02:49.266148 tx_first_pass[1][0][9] = 0
4639 10:02:49.266740 tx_last_pass[1][0][9] = 0
4640 10:02:49.268680 tx_win_center[1][0][10] = 0
4641 10:02:49.272415 tx_first_pass[1][0][10] = 0
4642 10:02:49.275627 tx_last_pass[1][0][10] = 0
4643 10:02:49.276190 tx_win_center[1][0][11] = 0
4644 10:02:49.278997 tx_first_pass[1][0][11] = 0
4645 10:02:49.282561 tx_last_pass[1][0][11] = 0
4646 10:02:49.285378 tx_win_center[1][0][12] = 0
4647 10:02:49.288791 tx_first_pass[1][0][12] = 0
4648 10:02:49.289354 tx_last_pass[1][0][12] = 0
4649 10:02:49.292091 tx_win_center[1][0][13] = 0
4650 10:02:49.295568 tx_first_pass[1][0][13] = 0
4651 10:02:49.296080 tx_last_pass[1][0][13] = 0
4652 10:02:49.299120 tx_win_center[1][0][14] = 0
4653 10:02:49.302334 tx_first_pass[1][0][14] = 0
4654 10:02:49.305446 tx_last_pass[1][0][14] = 0
4655 10:02:49.309132 tx_win_center[1][0][15] = 0
4656 10:02:49.309652 tx_first_pass[1][0][15] = 0
4657 10:02:49.312308 tx_last_pass[1][0][15] = 0
4658 10:02:49.315454 tx_win_center[1][1][0] = 0
4659 10:02:49.315981 tx_first_pass[1][1][0] = 0
4660 10:02:49.318572 tx_last_pass[1][1][0] = 0
4661 10:02:49.322209 tx_win_center[1][1][1] = 0
4662 10:02:49.325022 tx_first_pass[1][1][1] = 0
4663 10:02:49.325448 tx_last_pass[1][1][1] = 0
4664 10:02:49.328711 tx_win_center[1][1][2] = 0
4665 10:02:49.332075 tx_first_pass[1][1][2] = 0
4666 10:02:49.335824 tx_last_pass[1][1][2] = 0
4667 10:02:49.336342 tx_win_center[1][1][3] = 0
4668 10:02:49.338848 tx_first_pass[1][1][3] = 0
4669 10:02:49.342040 tx_last_pass[1][1][3] = 0
4670 10:02:49.342560 tx_win_center[1][1][4] = 0
4671 10:02:49.345964 tx_first_pass[1][1][4] = 0
4672 10:02:49.349001 tx_last_pass[1][1][4] = 0
4673 10:02:49.351958 tx_win_center[1][1][5] = 0
4674 10:02:49.352705 tx_first_pass[1][1][5] = 0
4675 10:02:49.355250 tx_last_pass[1][1][5] = 0
4676 10:02:49.358532 tx_win_center[1][1][6] = 0
4677 10:02:49.359050 tx_first_pass[1][1][6] = 0
4678 10:02:49.362130 tx_last_pass[1][1][6] = 0
4679 10:02:49.365437 tx_win_center[1][1][7] = 0
4680 10:02:49.368709 tx_first_pass[1][1][7] = 0
4681 10:02:49.369135 tx_last_pass[1][1][7] = 0
4682 10:02:49.371701 tx_win_center[1][1][8] = 0
4683 10:02:49.375228 tx_first_pass[1][1][8] = 0
4684 10:02:49.379361 tx_last_pass[1][1][8] = 0
4685 10:02:49.379918 tx_win_center[1][1][9] = 0
4686 10:02:49.381988 tx_first_pass[1][1][9] = 0
4687 10:02:49.385167 tx_last_pass[1][1][9] = 0
4688 10:02:49.388518 tx_win_center[1][1][10] = 0
4689 10:02:49.389031 tx_first_pass[1][1][10] = 0
4690 10:02:49.392301 tx_last_pass[1][1][10] = 0
4691 10:02:49.395189 tx_win_center[1][1][11] = 0
4692 10:02:49.398703 tx_first_pass[1][1][11] = 0
4693 10:02:49.399281 tx_last_pass[1][1][11] = 0
4694 10:02:49.402081 tx_win_center[1][1][12] = 0
4695 10:02:49.405099 tx_first_pass[1][1][12] = 0
4696 10:02:49.408416 tx_last_pass[1][1][12] = 0
4697 10:02:49.408934 tx_win_center[1][1][13] = 0
4698 10:02:49.411741 tx_first_pass[1][1][13] = 0
4699 10:02:49.414996 tx_last_pass[1][1][13] = 0
4700 10:02:49.418630 tx_win_center[1][1][14] = 0
4701 10:02:49.419058 tx_first_pass[1][1][14] = 0
4702 10:02:49.422258 tx_last_pass[1][1][14] = 0
4703 10:02:49.425174 tx_win_center[1][1][15] = 0
4704 10:02:49.428200 tx_first_pass[1][1][15] = 0
4705 10:02:49.428625 tx_last_pass[1][1][15] = 0
4706 10:02:49.431735 dump params rx window
4707 10:02:49.435147 rx_firspass[0][0][0] = 0
4708 10:02:49.435763 rx_lastpass[0][0][0] = 0
4709 10:02:49.438799 rx_firspass[0][0][1] = 0
4710 10:02:49.442036 rx_lastpass[0][0][1] = 0
4711 10:02:49.442574 rx_firspass[0][0][2] = 0
4712 10:02:49.444879 rx_lastpass[0][0][2] = 0
4713 10:02:49.448068 rx_firspass[0][0][3] = 0
4714 10:02:49.448488 rx_lastpass[0][0][3] = 0
4715 10:02:49.451586 rx_firspass[0][0][4] = 0
4716 10:02:49.455502 rx_lastpass[0][0][4] = 0
4717 10:02:49.456012 rx_firspass[0][0][5] = 0
4718 10:02:49.458343 rx_lastpass[0][0][5] = 0
4719 10:02:49.461899 rx_firspass[0][0][6] = 0
4720 10:02:49.465065 rx_lastpass[0][0][6] = 0
4721 10:02:49.465584 rx_firspass[0][0][7] = 0
4722 10:02:49.468383 rx_lastpass[0][0][7] = 0
4723 10:02:49.471679 rx_firspass[0][0][8] = 0
4724 10:02:49.472181 rx_lastpass[0][0][8] = 0
4725 10:02:49.474939 rx_firspass[0][0][9] = 0
4726 10:02:49.478409 rx_lastpass[0][0][9] = 0
4727 10:02:49.478916 rx_firspass[0][0][10] = 0
4728 10:02:49.481290 rx_lastpass[0][0][10] = 0
4729 10:02:49.485104 rx_firspass[0][0][11] = 0
4730 10:02:49.485528 rx_lastpass[0][0][11] = 0
4731 10:02:49.488223 rx_firspass[0][0][12] = 0
4732 10:02:49.491706 rx_lastpass[0][0][12] = 0
4733 10:02:49.494956 rx_firspass[0][0][13] = 0
4734 10:02:49.495511 rx_lastpass[0][0][13] = 0
4735 10:02:49.498872 rx_firspass[0][0][14] = 0
4736 10:02:49.501513 rx_lastpass[0][0][14] = 0
4737 10:02:49.501937 rx_firspass[0][0][15] = 0
4738 10:02:49.504979 rx_lastpass[0][0][15] = 0
4739 10:02:49.508689 rx_firspass[0][1][0] = 0
4740 10:02:49.511342 rx_lastpass[0][1][0] = 0
4741 10:02:49.511818 rx_firspass[0][1][1] = 0
4742 10:02:49.514926 rx_lastpass[0][1][1] = 0
4743 10:02:49.518438 rx_firspass[0][1][2] = 0
4744 10:02:49.518967 rx_lastpass[0][1][2] = 0
4745 10:02:49.521383 rx_firspass[0][1][3] = 0
4746 10:02:49.525142 rx_lastpass[0][1][3] = 0
4747 10:02:49.525564 rx_firspass[0][1][4] = 0
4748 10:02:49.528089 rx_lastpass[0][1][4] = 0
4749 10:02:49.531385 rx_firspass[0][1][5] = 0
4750 10:02:49.531844 rx_lastpass[0][1][5] = 0
4751 10:02:49.535262 rx_firspass[0][1][6] = 0
4752 10:02:49.538436 rx_lastpass[0][1][6] = 0
4753 10:02:49.538953 rx_firspass[0][1][7] = 0
4754 10:02:49.541558 rx_lastpass[0][1][7] = 0
4755 10:02:49.544964 rx_firspass[0][1][8] = 0
4756 10:02:49.545485 rx_lastpass[0][1][8] = 0
4757 10:02:49.548182 rx_firspass[0][1][9] = 0
4758 10:02:49.551958 rx_lastpass[0][1][9] = 0
4759 10:02:49.555159 rx_firspass[0][1][10] = 0
4760 10:02:49.555720 rx_lastpass[0][1][10] = 0
4761 10:02:49.558543 rx_firspass[0][1][11] = 0
4762 10:02:49.561980 rx_lastpass[0][1][11] = 0
4763 10:02:49.562497 rx_firspass[0][1][12] = 0
4764 10:02:49.565173 rx_lastpass[0][1][12] = 0
4765 10:02:49.568378 rx_firspass[0][1][13] = 0
4766 10:02:49.571479 rx_lastpass[0][1][13] = 0
4767 10:02:49.571969 rx_firspass[0][1][14] = 0
4768 10:02:49.574831 rx_lastpass[0][1][14] = 0
4769 10:02:49.578104 rx_firspass[0][1][15] = 0
4770 10:02:49.578578 rx_lastpass[0][1][15] = 0
4771 10:02:49.581264 rx_firspass[1][0][0] = 0
4772 10:02:49.584613 rx_lastpass[1][0][0] = 0
4773 10:02:49.588095 rx_firspass[1][0][1] = 0
4774 10:02:49.588655 rx_lastpass[1][0][1] = 0
4775 10:02:49.591282 rx_firspass[1][0][2] = 0
4776 10:02:49.594544 rx_lastpass[1][0][2] = 0
4777 10:02:49.594966 rx_firspass[1][0][3] = 0
4778 10:02:49.598409 rx_lastpass[1][0][3] = 0
4779 10:02:49.601534 rx_firspass[1][0][4] = 0
4780 10:02:49.601960 rx_lastpass[1][0][4] = 0
4781 10:02:49.604606 rx_firspass[1][0][5] = 0
4782 10:02:49.607580 rx_lastpass[1][0][5] = 0
4783 10:02:49.608003 rx_firspass[1][0][6] = 0
4784 10:02:49.611269 rx_lastpass[1][0][6] = 0
4785 10:02:49.614929 rx_firspass[1][0][7] = 0
4786 10:02:49.615540 rx_lastpass[1][0][7] = 0
4787 10:02:49.618016 rx_firspass[1][0][8] = 0
4788 10:02:49.621190 rx_lastpass[1][0][8] = 0
4789 10:02:49.621613 rx_firspass[1][0][9] = 0
4790 10:02:49.625042 rx_lastpass[1][0][9] = 0
4791 10:02:49.628178 rx_firspass[1][0][10] = 0
4792 10:02:49.631469 rx_lastpass[1][0][10] = 0
4793 10:02:49.631988 rx_firspass[1][0][11] = 0
4794 10:02:49.634773 rx_lastpass[1][0][11] = 0
4795 10:02:49.638103 rx_firspass[1][0][12] = 0
4796 10:02:49.638613 rx_lastpass[1][0][12] = 0
4797 10:02:49.641613 rx_firspass[1][0][13] = 0
4798 10:02:49.644837 rx_lastpass[1][0][13] = 0
4799 10:02:49.647979 rx_firspass[1][0][14] = 0
4800 10:02:49.648418 rx_lastpass[1][0][14] = 0
4801 10:02:49.651060 rx_firspass[1][0][15] = 0
4802 10:02:49.654181 rx_lastpass[1][0][15] = 0
4803 10:02:49.654750 rx_firspass[1][1][0] = 0
4804 10:02:49.657711 rx_lastpass[1][1][0] = 0
4805 10:02:49.661280 rx_firspass[1][1][1] = 0
4806 10:02:49.664185 rx_lastpass[1][1][1] = 0
4807 10:02:49.664617 rx_firspass[1][1][2] = 0
4808 10:02:49.667623 rx_lastpass[1][1][2] = 0
4809 10:02:49.671234 rx_firspass[1][1][3] = 0
4810 10:02:49.671712 rx_lastpass[1][1][3] = 0
4811 10:02:49.674505 rx_firspass[1][1][4] = 0
4812 10:02:49.677649 rx_lastpass[1][1][4] = 0
4813 10:02:49.678176 rx_firspass[1][1][5] = 0
4814 10:02:49.681339 rx_lastpass[1][1][5] = 0
4815 10:02:49.684234 rx_firspass[1][1][6] = 0
4816 10:02:49.684661 rx_lastpass[1][1][6] = 0
4817 10:02:49.687374 rx_firspass[1][1][7] = 0
4818 10:02:49.690807 rx_lastpass[1][1][7] = 0
4819 10:02:49.691275 rx_firspass[1][1][8] = 0
4820 10:02:49.694782 rx_lastpass[1][1][8] = 0
4821 10:02:49.697818 rx_firspass[1][1][9] = 0
4822 10:02:49.701071 rx_lastpass[1][1][9] = 0
4823 10:02:49.701533 rx_firspass[1][1][10] = 0
4824 10:02:49.704272 rx_lastpass[1][1][10] = 0
4825 10:02:49.707593 rx_firspass[1][1][11] = 0
4826 10:02:49.708256 rx_lastpass[1][1][11] = 0
4827 10:02:49.711241 rx_firspass[1][1][12] = 0
4828 10:02:49.713995 rx_lastpass[1][1][12] = 0
4829 10:02:49.717240 rx_firspass[1][1][13] = 0
4830 10:02:49.717663 rx_lastpass[1][1][13] = 0
4831 10:02:49.721111 rx_firspass[1][1][14] = 0
4832 10:02:49.724078 rx_lastpass[1][1][14] = 0
4833 10:02:49.724597 rx_firspass[1][1][15] = 0
4834 10:02:49.727797 rx_lastpass[1][1][15] = 0
4835 10:02:49.731128 dump params clk_delay
4836 10:02:49.731676 clk_delay[0] = 0
4837 10:02:49.734474 clk_delay[1] = 0
4838 10:02:49.734989 dump params dqs_delay
4839 10:02:49.737622 dqs_delay[0][0] = 0
4840 10:02:49.738187 dqs_delay[0][1] = 0
4841 10:02:49.741303 dqs_delay[1][0] = 0
4842 10:02:49.741860 dqs_delay[1][1] = 0
4843 10:02:49.744156 dump params delay_cell_unit = 735
4844 10:02:49.747607 dump source = 0x0
4845 10:02:49.748156 dump params frequency:800
4846 10:02:49.750975 dump params rank number:2
4847 10:02:49.751472
4848 10:02:49.754232 dump params write leveling
4849 10:02:49.757802 write leveling[0][0][0] = 0x0
4850 10:02:49.761191 write leveling[0][0][1] = 0x0
4851 10:02:49.761746 write leveling[0][1][0] = 0x0
4852 10:02:49.763910 write leveling[0][1][1] = 0x0
4853 10:02:49.767782 write leveling[1][0][0] = 0x0
4854 10:02:49.770881 write leveling[1][0][1] = 0x0
4855 10:02:49.773891 write leveling[1][1][0] = 0x0
4856 10:02:49.774374 write leveling[1][1][1] = 0x0
4857 10:02:49.777668 dump params cbt_cs
4858 10:02:49.778222 cbt_cs[0][0] = 0x0
4859 10:02:49.780645 cbt_cs[0][1] = 0x0
4860 10:02:49.783764 cbt_cs[1][0] = 0x0
4861 10:02:49.784377 cbt_cs[1][1] = 0x0
4862 10:02:49.787116 dump params cbt_mr12
4863 10:02:49.787573 cbt_mr12[0][0] = 0x0
4864 10:02:49.790348 cbt_mr12[0][1] = 0x0
4865 10:02:49.790769 cbt_mr12[1][0] = 0x0
4866 10:02:49.793923 cbt_mr12[1][1] = 0x0
4867 10:02:49.794496 dump params tx window
4868 10:02:49.797384 tx_center_min[0][0][0] = 0
4869 10:02:49.800440 tx_center_max[0][0][0] = 0
4870 10:02:49.804036 tx_center_min[0][0][1] = 0
4871 10:02:49.804568 tx_center_max[0][0][1] = 0
4872 10:02:49.807337 tx_center_min[0][1][0] = 0
4873 10:02:49.810720 tx_center_max[0][1][0] = 0
4874 10:02:49.813558 tx_center_min[0][1][1] = 0
4875 10:02:49.813983 tx_center_max[0][1][1] = 0
4876 10:02:49.817129 tx_center_min[1][0][0] = 0
4877 10:02:49.820413 tx_center_max[1][0][0] = 0
4878 10:02:49.823899 tx_center_min[1][0][1] = 0
4879 10:02:49.824457 tx_center_max[1][0][1] = 0
4880 10:02:49.827344 tx_center_min[1][1][0] = 0
4881 10:02:49.830827 tx_center_max[1][1][0] = 0
4882 10:02:49.834196 tx_center_min[1][1][1] = 0
4883 10:02:49.834868 tx_center_max[1][1][1] = 0
4884 10:02:49.837453 dump params tx window
4885 10:02:49.840468 tx_win_center[0][0][0] = 0
4886 10:02:49.840983 tx_first_pass[0][0][0] = 0
4887 10:02:49.843950 tx_last_pass[0][0][0] = 0
4888 10:02:49.847497 tx_win_center[0][0][1] = 0
4889 10:02:49.850498 tx_first_pass[0][0][1] = 0
4890 10:02:49.850954 tx_last_pass[0][0][1] = 0
4891 10:02:49.853993 tx_win_center[0][0][2] = 0
4892 10:02:49.857497 tx_first_pass[0][0][2] = 0
4893 10:02:49.858053 tx_last_pass[0][0][2] = 0
4894 10:02:49.860577 tx_win_center[0][0][3] = 0
4895 10:02:49.863568 tx_first_pass[0][0][3] = 0
4896 10:02:49.867503 tx_last_pass[0][0][3] = 0
4897 10:02:49.868023 tx_win_center[0][0][4] = 0
4898 10:02:49.870476 tx_first_pass[0][0][4] = 0
4899 10:02:49.873534 tx_last_pass[0][0][4] = 0
4900 10:02:49.873950 tx_win_center[0][0][5] = 0
4901 10:02:49.877078 tx_first_pass[0][0][5] = 0
4902 10:02:49.880519 tx_last_pass[0][0][5] = 0
4903 10:02:49.883718 tx_win_center[0][0][6] = 0
4904 10:02:49.884131 tx_first_pass[0][0][6] = 0
4905 10:02:49.886752 tx_last_pass[0][0][6] = 0
4906 10:02:49.890105 tx_win_center[0][0][7] = 0
4907 10:02:49.893383 tx_first_pass[0][0][7] = 0
4908 10:02:49.893798 tx_last_pass[0][0][7] = 0
4909 10:02:49.896834 tx_win_center[0][0][8] = 0
4910 10:02:49.899857 tx_first_pass[0][0][8] = 0
4911 10:02:49.900273 tx_last_pass[0][0][8] = 0
4912 10:02:49.903675 tx_win_center[0][0][9] = 0
4913 10:02:49.907590 tx_first_pass[0][0][9] = 0
4914 10:02:49.910361 tx_last_pass[0][0][9] = 0
4915 10:02:49.910886 tx_win_center[0][0][10] = 0
4916 10:02:49.913845 tx_first_pass[0][0][10] = 0
4917 10:02:49.917160 tx_last_pass[0][0][10] = 0
4918 10:02:49.920217 tx_win_center[0][0][11] = 0
4919 10:02:49.920768 tx_first_pass[0][0][11] = 0
4920 10:02:49.923588 tx_last_pass[0][0][11] = 0
4921 10:02:49.927004 tx_win_center[0][0][12] = 0
4922 10:02:49.930163 tx_first_pass[0][0][12] = 0
4923 10:02:49.930620 tx_last_pass[0][0][12] = 0
4924 10:02:49.933579 tx_win_center[0][0][13] = 0
4925 10:02:49.936830 tx_first_pass[0][0][13] = 0
4926 10:02:49.940745 tx_last_pass[0][0][13] = 0
4927 10:02:49.941260 tx_win_center[0][0][14] = 0
4928 10:02:49.943993 tx_first_pass[0][0][14] = 0
4929 10:02:49.946752 tx_last_pass[0][0][14] = 0
4930 10:02:49.950230 tx_win_center[0][0][15] = 0
4931 10:02:49.950641 tx_first_pass[0][0][15] = 0
4932 10:02:49.953999 tx_last_pass[0][0][15] = 0
4933 10:02:49.957107 tx_win_center[0][1][0] = 0
4934 10:02:49.960276 tx_first_pass[0][1][0] = 0
4935 10:02:49.960712 tx_last_pass[0][1][0] = 0
4936 10:02:49.963563 tx_win_center[0][1][1] = 0
4937 10:02:49.967141 tx_first_pass[0][1][1] = 0
4938 10:02:49.967704 tx_last_pass[0][1][1] = 0
4939 10:02:49.970604 tx_win_center[0][1][2] = 0
4940 10:02:49.973666 tx_first_pass[0][1][2] = 0
4941 10:02:49.976536 tx_last_pass[0][1][2] = 0
4942 10:02:49.977079 tx_win_center[0][1][3] = 0
4943 10:02:49.980139 tx_first_pass[0][1][3] = 0
4944 10:02:49.983385 tx_last_pass[0][1][3] = 0
4945 10:02:49.986615 tx_win_center[0][1][4] = 0
4946 10:02:49.987251 tx_first_pass[0][1][4] = 0
4947 10:02:49.990320 tx_last_pass[0][1][4] = 0
4948 10:02:49.993205 tx_win_center[0][1][5] = 0
4949 10:02:49.996426 tx_first_pass[0][1][5] = 0
4950 10:02:49.997062 tx_last_pass[0][1][5] = 0
4951 10:02:50.000056 tx_win_center[0][1][6] = 0
4952 10:02:50.003121 tx_first_pass[0][1][6] = 0
4953 10:02:50.003734 tx_last_pass[0][1][6] = 0
4954 10:02:50.006310 tx_win_center[0][1][7] = 0
4955 10:02:50.009630 tx_first_pass[0][1][7] = 0
4956 10:02:50.013186 tx_last_pass[0][1][7] = 0
4957 10:02:50.013609 tx_win_center[0][1][8] = 0
4958 10:02:50.016713 tx_first_pass[0][1][8] = 0
4959 10:02:50.019946 tx_last_pass[0][1][8] = 0
4960 10:02:50.023041 tx_win_center[0][1][9] = 0
4961 10:02:50.023605 tx_first_pass[0][1][9] = 0
4962 10:02:50.026188 tx_last_pass[0][1][9] = 0
4963 10:02:50.030178 tx_win_center[0][1][10] = 0
4964 10:02:50.033049 tx_first_pass[0][1][10] = 0
4965 10:02:50.033561 tx_last_pass[0][1][10] = 0
4966 10:02:50.036037 tx_win_center[0][1][11] = 0
4967 10:02:50.039655 tx_first_pass[0][1][11] = 0
4968 10:02:50.043192 tx_last_pass[0][1][11] = 0
4969 10:02:50.043760 tx_win_center[0][1][12] = 0
4970 10:02:50.046552 tx_first_pass[0][1][12] = 0
4971 10:02:50.049904 tx_last_pass[0][1][12] = 0
4972 10:02:50.053223 tx_win_center[0][1][13] = 0
4973 10:02:50.053739 tx_first_pass[0][1][13] = 0
4974 10:02:50.056024 tx_last_pass[0][1][13] = 0
4975 10:02:50.059609 tx_win_center[0][1][14] = 0
4976 10:02:50.063382 tx_first_pass[0][1][14] = 0
4977 10:02:50.063947 tx_last_pass[0][1][14] = 0
4978 10:02:50.066413 tx_win_center[0][1][15] = 0
4979 10:02:50.069672 tx_first_pass[0][1][15] = 0
4980 10:02:50.072644 tx_last_pass[0][1][15] = 0
4981 10:02:50.073294 tx_win_center[1][0][0] = 0
4982 10:02:50.076096 tx_first_pass[1][0][0] = 0
4983 10:02:50.079565 tx_last_pass[1][0][0] = 0
4984 10:02:50.080075 tx_win_center[1][0][1] = 0
4985 10:02:50.082567 tx_first_pass[1][0][1] = 0
4986 10:02:50.086343 tx_last_pass[1][0][1] = 0
4987 10:02:50.089722 tx_win_center[1][0][2] = 0
4988 10:02:50.090240 tx_first_pass[1][0][2] = 0
4989 10:02:50.092983 tx_last_pass[1][0][2] = 0
4990 10:02:50.096105 tx_win_center[1][0][3] = 0
4991 10:02:50.099831 tx_first_pass[1][0][3] = 0
4992 10:02:50.100343 tx_last_pass[1][0][3] = 0
4993 10:02:50.103063 tx_win_center[1][0][4] = 0
4994 10:02:50.106199 tx_first_pass[1][0][4] = 0
4995 10:02:50.106712 tx_last_pass[1][0][4] = 0
4996 10:02:50.109538 tx_win_center[1][0][5] = 0
4997 10:02:50.112796 tx_first_pass[1][0][5] = 0
4998 10:02:50.115973 tx_last_pass[1][0][5] = 0
4999 10:02:50.116421 tx_win_center[1][0][6] = 0
5000 10:02:50.119037 tx_first_pass[1][0][6] = 0
5001 10:02:50.122541 tx_last_pass[1][0][6] = 0
5002 10:02:50.126216 tx_win_center[1][0][7] = 0
5003 10:02:50.126731 tx_first_pass[1][0][7] = 0
5004 10:02:50.129092 tx_last_pass[1][0][7] = 0
5005 10:02:50.132273 tx_win_center[1][0][8] = 0
5006 10:02:50.135744 tx_first_pass[1][0][8] = 0
5007 10:02:50.136168 tx_last_pass[1][0][8] = 0
5008 10:02:50.139345 tx_win_center[1][0][9] = 0
5009 10:02:50.142574 tx_first_pass[1][0][9] = 0
5010 10:02:50.143121 tx_last_pass[1][0][9] = 0
5011 10:02:50.146235 tx_win_center[1][0][10] = 0
5012 10:02:50.149319 tx_first_pass[1][0][10] = 0
5013 10:02:50.152255 tx_last_pass[1][0][10] = 0
5014 10:02:50.152695 tx_win_center[1][0][11] = 0
5015 10:02:50.156173 tx_first_pass[1][0][11] = 0
5016 10:02:50.159337 tx_last_pass[1][0][11] = 0
5017 10:02:50.162702 tx_win_center[1][0][12] = 0
5018 10:02:50.163124 tx_first_pass[1][0][12] = 0
5019 10:02:50.165986 tx_last_pass[1][0][12] = 0
5020 10:02:50.169472 tx_win_center[1][0][13] = 0
5021 10:02:50.172836 tx_first_pass[1][0][13] = 0
5022 10:02:50.173294 tx_last_pass[1][0][13] = 0
5023 10:02:50.175963 tx_win_center[1][0][14] = 0
5024 10:02:50.179525 tx_first_pass[1][0][14] = 0
5025 10:02:50.182568 tx_last_pass[1][0][14] = 0
5026 10:02:50.183095 tx_win_center[1][0][15] = 0
5027 10:02:50.185851 tx_first_pass[1][0][15] = 0
5028 10:02:50.189368 tx_last_pass[1][0][15] = 0
5029 10:02:50.192556 tx_win_center[1][1][0] = 0
5030 10:02:50.193074 tx_first_pass[1][1][0] = 0
5031 10:02:50.195937 tx_last_pass[1][1][0] = 0
5032 10:02:50.199204 tx_win_center[1][1][1] = 0
5033 10:02:50.202732 tx_first_pass[1][1][1] = 0
5034 10:02:50.203240 tx_last_pass[1][1][1] = 0
5035 10:02:50.206028 tx_win_center[1][1][2] = 0
5036 10:02:50.209127 tx_first_pass[1][1][2] = 0
5037 10:02:50.209642 tx_last_pass[1][1][2] = 0
5038 10:02:50.212595 tx_win_center[1][1][3] = 0
5039 10:02:50.215764 tx_first_pass[1][1][3] = 0
5040 10:02:50.219493 tx_last_pass[1][1][3] = 0
5041 10:02:50.220050 tx_win_center[1][1][4] = 0
5042 10:02:50.222466 tx_first_pass[1][1][4] = 0
5043 10:02:50.225571 tx_last_pass[1][1][4] = 0
5044 10:02:50.229311 tx_win_center[1][1][5] = 0
5045 10:02:50.229862 tx_first_pass[1][1][5] = 0
5046 10:02:50.232168 tx_last_pass[1][1][5] = 0
5047 10:02:50.236143 tx_win_center[1][1][6] = 0
5048 10:02:50.236748 tx_first_pass[1][1][6] = 0
5049 10:02:50.239159 tx_last_pass[1][1][6] = 0
5050 10:02:50.242133 tx_win_center[1][1][7] = 0
5051 10:02:50.245384 tx_first_pass[1][1][7] = 0
5052 10:02:50.245845 tx_last_pass[1][1][7] = 0
5053 10:02:50.248874 tx_win_center[1][1][8] = 0
5054 10:02:50.252104 tx_first_pass[1][1][8] = 0
5055 10:02:50.255495 tx_last_pass[1][1][8] = 0
5056 10:02:50.255914 tx_win_center[1][1][9] = 0
5057 10:02:50.258601 tx_first_pass[1][1][9] = 0
5058 10:02:50.262892 tx_last_pass[1][1][9] = 0
5059 10:02:50.263446 tx_win_center[1][1][10] = 0
5060 10:02:50.265655 tx_first_pass[1][1][10] = 0
5061 10:02:50.268758 tx_last_pass[1][1][10] = 0
5062 10:02:50.272070 tx_win_center[1][1][11] = 0
5063 10:02:50.272504 tx_first_pass[1][1][11] = 0
5064 10:02:50.275277 tx_last_pass[1][1][11] = 0
5065 10:02:50.278848 tx_win_center[1][1][12] = 0
5066 10:02:50.282266 tx_first_pass[1][1][12] = 0
5067 10:02:50.282875 tx_last_pass[1][1][12] = 0
5068 10:02:50.285107 tx_win_center[1][1][13] = 0
5069 10:02:50.288610 tx_first_pass[1][1][13] = 0
5070 10:02:50.291873 tx_last_pass[1][1][13] = 0
5071 10:02:50.295219 tx_win_center[1][1][14] = 0
5072 10:02:50.295676 tx_first_pass[1][1][14] = 0
5073 10:02:50.298729 tx_last_pass[1][1][14] = 0
5074 10:02:50.302090 tx_win_center[1][1][15] = 0
5075 10:02:50.305573 tx_first_pass[1][1][15] = 0
5076 10:02:50.306084 tx_last_pass[1][1][15] = 0
5077 10:02:50.308620 dump params rx window
5078 10:02:50.311678 rx_firspass[0][0][0] = 0
5079 10:02:50.312096 rx_lastpass[0][0][0] = 0
5080 10:02:50.315723 rx_firspass[0][0][1] = 0
5081 10:02:50.318994 rx_lastpass[0][0][1] = 0
5082 10:02:50.319553 rx_firspass[0][0][2] = 0
5083 10:02:50.322287 rx_lastpass[0][0][2] = 0
5084 10:02:50.325160 rx_firspass[0][0][3] = 0
5085 10:02:50.325581 rx_lastpass[0][0][3] = 0
5086 10:02:50.328441 rx_firspass[0][0][4] = 0
5087 10:02:50.332208 rx_lastpass[0][0][4] = 0
5088 10:02:50.332714 rx_firspass[0][0][5] = 0
5089 10:02:50.336017 rx_lastpass[0][0][5] = 0
5090 10:02:50.338857 rx_firspass[0][0][6] = 0
5091 10:02:50.339447 rx_lastpass[0][0][6] = 0
5092 10:02:50.342415 rx_firspass[0][0][7] = 0
5093 10:02:50.345352 rx_lastpass[0][0][7] = 0
5094 10:02:50.345770 rx_firspass[0][0][8] = 0
5095 10:02:50.348717 rx_lastpass[0][0][8] = 0
5096 10:02:50.351989 rx_firspass[0][0][9] = 0
5097 10:02:50.355088 rx_lastpass[0][0][9] = 0
5098 10:02:50.355603 rx_firspass[0][0][10] = 0
5099 10:02:50.359177 rx_lastpass[0][0][10] = 0
5100 10:02:50.362484 rx_firspass[0][0][11] = 0
5101 10:02:50.363038 rx_lastpass[0][0][11] = 0
5102 10:02:50.365468 rx_firspass[0][0][12] = 0
5103 10:02:50.368559 rx_lastpass[0][0][12] = 0
5104 10:02:50.371942 rx_firspass[0][0][13] = 0
5105 10:02:50.372496 rx_lastpass[0][0][13] = 0
5106 10:02:50.375354 rx_firspass[0][0][14] = 0
5107 10:02:50.378450 rx_lastpass[0][0][14] = 0
5108 10:02:50.379001 rx_firspass[0][0][15] = 0
5109 10:02:50.381628 rx_lastpass[0][0][15] = 0
5110 10:02:50.384884 rx_firspass[0][1][0] = 0
5111 10:02:50.385349 rx_lastpass[0][1][0] = 0
5112 10:02:50.388516 rx_firspass[0][1][1] = 0
5113 10:02:50.391870 rx_lastpass[0][1][1] = 0
5114 10:02:50.395260 rx_firspass[0][1][2] = 0
5115 10:02:50.395834 rx_lastpass[0][1][2] = 0
5116 10:02:50.398406 rx_firspass[0][1][3] = 0
5117 10:02:50.401555 rx_lastpass[0][1][3] = 0
5118 10:02:50.401979 rx_firspass[0][1][4] = 0
5119 10:02:50.405305 rx_lastpass[0][1][4] = 0
5120 10:02:50.408455 rx_firspass[0][1][5] = 0
5121 10:02:50.409042 rx_lastpass[0][1][5] = 0
5122 10:02:50.411750 rx_firspass[0][1][6] = 0
5123 10:02:50.414690 rx_lastpass[0][1][6] = 0
5124 10:02:50.415105 rx_firspass[0][1][7] = 0
5125 10:02:50.418242 rx_lastpass[0][1][7] = 0
5126 10:02:50.421786 rx_firspass[0][1][8] = 0
5127 10:02:50.422205 rx_lastpass[0][1][8] = 0
5128 10:02:50.424929 rx_firspass[0][1][9] = 0
5129 10:02:50.428656 rx_lastpass[0][1][9] = 0
5130 10:02:50.432019 rx_firspass[0][1][10] = 0
5131 10:02:50.432534 rx_lastpass[0][1][10] = 0
5132 10:02:50.435486 rx_firspass[0][1][11] = 0
5133 10:02:50.438564 rx_lastpass[0][1][11] = 0
5134 10:02:50.439078 rx_firspass[0][1][12] = 0
5135 10:02:50.441568 rx_lastpass[0][1][12] = 0
5136 10:02:50.444867 rx_firspass[0][1][13] = 0
5137 10:02:50.448211 rx_lastpass[0][1][13] = 0
5138 10:02:50.448766 rx_firspass[0][1][14] = 0
5139 10:02:50.451178 rx_lastpass[0][1][14] = 0
5140 10:02:50.455181 rx_firspass[0][1][15] = 0
5141 10:02:50.455810 rx_lastpass[0][1][15] = 0
5142 10:02:50.458199 rx_firspass[1][0][0] = 0
5143 10:02:50.461700 rx_lastpass[1][0][0] = 0
5144 10:02:50.464637 rx_firspass[1][0][1] = 0
5145 10:02:50.465099 rx_lastpass[1][0][1] = 0
5146 10:02:50.467937 rx_firspass[1][0][2] = 0
5147 10:02:50.471644 rx_lastpass[1][0][2] = 0
5148 10:02:50.472195 rx_firspass[1][0][3] = 0
5149 10:02:50.474545 rx_lastpass[1][0][3] = 0
5150 10:02:50.478398 rx_firspass[1][0][4] = 0
5151 10:02:50.478949 rx_lastpass[1][0][4] = 0
5152 10:02:50.481800 rx_firspass[1][0][5] = 0
5153 10:02:50.484767 rx_lastpass[1][0][5] = 0
5154 10:02:50.485226 rx_firspass[1][0][6] = 0
5155 10:02:50.488427 rx_lastpass[1][0][6] = 0
5156 10:02:50.491488 rx_firspass[1][0][7] = 0
5157 10:02:50.492054 rx_lastpass[1][0][7] = 0
5158 10:02:50.494341 rx_firspass[1][0][8] = 0
5159 10:02:50.497860 rx_lastpass[1][0][8] = 0
5160 10:02:50.501419 rx_firspass[1][0][9] = 0
5161 10:02:50.501978 rx_lastpass[1][0][9] = 0
5162 10:02:50.504146 rx_firspass[1][0][10] = 0
5163 10:02:50.508098 rx_lastpass[1][0][10] = 0
5164 10:02:50.508622 rx_firspass[1][0][11] = 0
5165 10:02:50.511071 rx_lastpass[1][0][11] = 0
5166 10:02:50.514505 rx_firspass[1][0][12] = 0
5167 10:02:50.517694 rx_lastpass[1][0][12] = 0
5168 10:02:50.518209 rx_firspass[1][0][13] = 0
5169 10:02:50.520633 rx_lastpass[1][0][13] = 0
5170 10:02:50.524833 rx_firspass[1][0][14] = 0
5171 10:02:50.525350 rx_lastpass[1][0][14] = 0
5172 10:02:50.527815 rx_firspass[1][0][15] = 0
5173 10:02:50.530869 rx_lastpass[1][0][15] = 0
5174 10:02:50.534506 rx_firspass[1][1][0] = 0
5175 10:02:50.535039 rx_lastpass[1][1][0] = 0
5176 10:02:50.537364 rx_firspass[1][1][1] = 0
5177 10:02:50.540985 rx_lastpass[1][1][1] = 0
5178 10:02:50.541498 rx_firspass[1][1][2] = 0
5179 10:02:50.543849 rx_lastpass[1][1][2] = 0
5180 10:02:50.547348 rx_firspass[1][1][3] = 0
5181 10:02:50.547877 rx_lastpass[1][1][3] = 0
5182 10:02:50.550800 rx_firspass[1][1][4] = 0
5183 10:02:50.553872 rx_lastpass[1][1][4] = 0
5184 10:02:50.554287 rx_firspass[1][1][5] = 0
5185 10:02:50.557525 rx_lastpass[1][1][5] = 0
5186 10:02:50.561067 rx_firspass[1][1][6] = 0
5187 10:02:50.564333 rx_lastpass[1][1][6] = 0
5188 10:02:50.564793 rx_firspass[1][1][7] = 0
5189 10:02:50.567241 rx_lastpass[1][1][7] = 0
5190 10:02:50.570607 rx_firspass[1][1][8] = 0
5191 10:02:50.571123 rx_lastpass[1][1][8] = 0
5192 10:02:50.574144 rx_firspass[1][1][9] = 0
5193 10:02:50.577862 rx_lastpass[1][1][9] = 0
5194 10:02:50.578427 rx_firspass[1][1][10] = 0
5195 10:02:50.581126 rx_lastpass[1][1][10] = 0
5196 10:02:50.584025 rx_firspass[1][1][11] = 0
5197 10:02:50.587236 rx_lastpass[1][1][11] = 0
5198 10:02:50.587839 rx_firspass[1][1][12] = 0
5199 10:02:50.590794 rx_lastpass[1][1][12] = 0
5200 10:02:50.594035 rx_firspass[1][1][13] = 0
5201 10:02:50.594677 rx_lastpass[1][1][13] = 0
5202 10:02:50.597160 rx_firspass[1][1][14] = 0
5203 10:02:50.600421 rx_lastpass[1][1][14] = 0
5204 10:02:50.600995 rx_firspass[1][1][15] = 0
5205 10:02:50.603812 rx_lastpass[1][1][15] = 0
5206 10:02:50.607263 dump params clk_delay
5207 10:02:50.607882 clk_delay[0] = 0
5208 10:02:50.610600 clk_delay[1] = 0
5209 10:02:50.611205 dump params dqs_delay
5210 10:02:50.613846 dqs_delay[0][0] = 0
5211 10:02:50.614304 dqs_delay[0][1] = 0
5212 10:02:50.617357 dqs_delay[1][0] = 0
5213 10:02:50.620389 dqs_delay[1][1] = 0
5214 10:02:50.620952 dump params delay_cell_unit = 735
5215 10:02:50.624014 mt_set_emi_preloader end
5216 10:02:50.630602 [mt_mem_init] dram size: 0x100000000, rank number: 2
5217 10:02:50.633576 [complex_mem_test] start addr:0x40000000, len:20480
5218 10:02:50.670190 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5219 10:02:50.676271 [complex_mem_test] start addr:0x80000000, len:20480
5220 10:02:50.712462 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5221 10:02:50.719015 [complex_mem_test] start addr:0xc0000000, len:20480
5222 10:02:50.755151 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5223 10:02:50.761494 [complex_mem_test] start addr:0x56000000, len:8192
5224 10:02:50.778089 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5225 10:02:50.781829 ddr_geometry:1
5226 10:02:50.784475 [complex_mem_test] start addr:0x80000000, len:8192
5227 10:02:50.801406 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5228 10:02:50.805040 dram_init: dram init end (result: 0)
5229 10:02:50.811337 Successfully loaded DRAM blobs and ran DRAM calibration
5230 10:02:50.821647 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5231 10:02:50.822221 CBMEM:
5232 10:02:50.825192 IMD: root @ 00000000fffff000 254 entries.
5233 10:02:50.828004 IMD: root @ 00000000ffffec00 62 entries.
5234 10:02:50.835261 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5235 10:02:50.841569 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5236 10:02:50.844765 in-header: 03 a1 00 00 08 00 00 00
5237 10:02:50.848132 in-data: 84 60 60 10 00 00 00 00
5238 10:02:50.851681 Chrome EC: clear events_b mask to 0x0000000020004000
5239 10:02:50.859055 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5240 10:02:50.862188 in-header: 03 fd 00 00 00 00 00 00
5241 10:02:50.862740 in-data:
5242 10:02:50.868678 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5243 10:02:50.869253 CBFS @ 21000 size 3d4000
5244 10:02:50.875579 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5245 10:02:50.878615 CBFS: Locating 'fallback/ramstage'
5246 10:02:50.882051 CBFS: Found @ offset 10d40 size d563
5247 10:02:50.903514 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5248 10:02:50.915434 Accumulated console time in romstage 13605 ms
5249 10:02:50.915983
5250 10:02:50.916342
5251 10:02:50.925439 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5252 10:02:50.928850 ARM64: Exception handlers installed.
5253 10:02:50.929406 ARM64: Testing exception
5254 10:02:50.932323 ARM64: Done test exception
5255 10:02:50.935475 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5256 10:02:50.938923 Manufacturer: ef
5257 10:02:50.942437 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5258 10:02:50.948636 WARNING: RO_VPD is uninitialized or empty.
5259 10:02:50.951986 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5260 10:02:50.955536 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5261 10:02:50.965194 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5262 10:02:50.968399 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5263 10:02:50.975237 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5264 10:02:50.975755 Enumerating buses...
5265 10:02:50.982260 Show all devs... Before device enumeration.
5266 10:02:50.982816 Root Device: enabled 1
5267 10:02:50.984754 CPU_CLUSTER: 0: enabled 1
5268 10:02:50.985334 CPU: 00: enabled 1
5269 10:02:50.988421 Compare with tree...
5270 10:02:50.991730 Root Device: enabled 1
5271 10:02:50.992147 CPU_CLUSTER: 0: enabled 1
5272 10:02:50.995084 CPU: 00: enabled 1
5273 10:02:50.998325 Root Device scanning...
5274 10:02:50.998834 root_dev_scan_bus for Root Device
5275 10:02:51.001845 CPU_CLUSTER: 0 enabled
5276 10:02:51.004913 root_dev_scan_bus for Root Device done
5277 10:02:51.011802 scan_bus: scanning of bus Root Device took 10689 usecs
5278 10:02:51.012250 done
5279 10:02:51.014611 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5280 10:02:51.018159 Allocating resources...
5281 10:02:51.018569 Reading resources...
5282 10:02:51.024764 Root Device read_resources bus 0 link: 0
5283 10:02:51.028163 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5284 10:02:51.031250 CPU: 00 missing read_resources
5285 10:02:51.034906 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5286 10:02:51.037920 Root Device read_resources bus 0 link: 0 done
5287 10:02:51.041361 Done reading resources.
5288 10:02:51.044576 Show resources in subtree (Root Device)...After reading.
5289 10:02:51.047912 Root Device child on link 0 CPU_CLUSTER: 0
5290 10:02:51.051127 CPU_CLUSTER: 0 child on link 0 CPU: 00
5291 10:02:51.061424 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5292 10:02:51.061849 CPU: 00
5293 10:02:51.064508 Setting resources...
5294 10:02:51.067961 Root Device assign_resources, bus 0 link: 0
5295 10:02:51.071121 CPU_CLUSTER: 0 missing set_resources
5296 10:02:51.074721 Root Device assign_resources, bus 0 link: 0
5297 10:02:51.077859 Done setting resources.
5298 10:02:51.084707 Show resources in subtree (Root Device)...After assigning values.
5299 10:02:51.088536 Root Device child on link 0 CPU_CLUSTER: 0
5300 10:02:51.091550 CPU_CLUSTER: 0 child on link 0 CPU: 00
5301 10:02:51.101585 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5302 10:02:51.102113 CPU: 00
5303 10:02:51.104552 Done allocating resources.
5304 10:02:51.108025 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5305 10:02:51.111152 Enabling resources...
5306 10:02:51.111720 done.
5307 10:02:51.114933 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5308 10:02:51.117860 Initializing devices...
5309 10:02:51.118276 Root Device init ...
5310 10:02:51.121422 mainboard_init: Starting display init.
5311 10:02:51.124100 ADC[4]: Raw value=76102 ID=0
5312 10:02:51.147944 anx7625_power_on_init: Init interface.
5313 10:02:51.151649 anx7625_disable_pd_protocol: Disabled PD feature.
5314 10:02:51.157917 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5315 10:02:51.204718 anx7625_start_dp_work: Secure OCM version=00
5316 10:02:51.208246 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5317 10:02:51.225337 sp_tx_get_edid_block: EDID Block = 1
5318 10:02:51.342814 Extracted contents:
5319 10:02:51.345970 header: 00 ff ff ff ff ff ff 00
5320 10:02:51.349129 serial number: 06 af 5c 14 00 00 00 00 00 1a
5321 10:02:51.352022 version: 01 04
5322 10:02:51.355545 basic params: 95 1a 0e 78 02
5323 10:02:51.359147 chroma info: 99 85 95 55 56 92 28 22 50 54
5324 10:02:51.362363 established: 00 00 00
5325 10:02:51.369562 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5326 10:02:51.372436 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5327 10:02:51.378572 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5328 10:02:51.385480 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5329 10:02:51.392367 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5330 10:02:51.395626 extensions: 00
5331 10:02:51.396305 checksum: ae
5332 10:02:51.396678
5333 10:02:51.398936 Manufacturer: AUO Model 145c Serial Number 0
5334 10:02:51.402469 Made week 0 of 2016
5335 10:02:51.402929 EDID version: 1.4
5336 10:02:51.405689 Digital display
5337 10:02:51.408836 6 bits per primary color channel
5338 10:02:51.409341 DisplayPort interface
5339 10:02:51.412019 Maximum image size: 26 cm x 14 cm
5340 10:02:51.415072 Gamma: 220%
5341 10:02:51.415590 Check DPMS levels
5342 10:02:51.418607 Supported color formats: RGB 4:4:4
5343 10:02:51.421928 First detailed timing is preferred timing
5344 10:02:51.425750 Established timings supported:
5345 10:02:51.428942 Standard timings supported:
5346 10:02:51.429462 Detailed timings
5347 10:02:51.435983 Hex of detail: ce1d56ea50001a3030204600009010000018
5348 10:02:51.439086 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5349 10:02:51.442533 0556 0586 05a6 0640 hborder 0
5350 10:02:51.445345 0300 0304 030a 031a vborder 0
5351 10:02:51.448420 -hsync -vsync
5352 10:02:51.452258 Did detailed timing
5353 10:02:51.455338 Hex of detail: 0000000f0000000000000000000000000020
5354 10:02:51.458452 Manufacturer-specified data, tag 15
5355 10:02:51.465588 Hex of detail: 000000fe0041554f0a202020202020202020
5356 10:02:51.466104 ASCII string: AUO
5357 10:02:51.468952 Hex of detail: 000000fe004231313658414230312e34200a
5358 10:02:51.471601 ASCII string: B116XAB01.4
5359 10:02:51.472020 Checksum
5360 10:02:51.475145 Checksum: 0xae (valid)
5361 10:02:51.481571 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5362 10:02:51.481984 DSI data_rate: 457800000 bps
5363 10:02:51.489588 anx7625_parse_edid: set default k value to 0x3d for panel
5364 10:02:51.492817 anx7625_parse_edid: pixelclock(76300).
5365 10:02:51.495737 hactive(1366), hsync(32), hfp(48), hbp(154)
5366 10:02:51.499609 vactive(768), vsync(6), vfp(4), vbp(16)
5367 10:02:51.502685 anx7625_dsi_config: config dsi.
5368 10:02:51.510927 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5369 10:02:51.531714 anx7625_dsi_config: success to config DSI
5370 10:02:51.534764 anx7625_dp_start: MIPI phy setup OK.
5371 10:02:51.538639 [SSUSB] Setting up USB HOST controller...
5372 10:02:51.541903 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5373 10:02:51.544978 [SSUSB] phy power-on done.
5374 10:02:51.548603 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5375 10:02:51.552136 in-header: 03 fc 01 00 00 00 00 00
5376 10:02:51.552600 in-data:
5377 10:02:51.555638 handle_proto3_response: EC response with error code: 1
5378 10:02:51.558731 SPM: pcm index = 1
5379 10:02:51.562208 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5380 10:02:51.565619 CBFS @ 21000 size 3d4000
5381 10:02:51.572023 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5382 10:02:51.575070 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5383 10:02:51.578663 CBFS: Found @ offset 1e7c0 size 1026
5384 10:02:51.585043 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5385 10:02:51.588970 SPM: binary array size = 2988
5386 10:02:51.591889 SPM: version = pcm_allinone_v1.17.2_20180829
5387 10:02:51.595007 SPM binary loaded in 32 msecs
5388 10:02:51.603082 spm_kick_im_to_fetch: ptr = 000000004021eec2
5389 10:02:51.606615 spm_kick_im_to_fetch: len = 2988
5390 10:02:51.607138 SPM: spm_kick_pcm_to_run
5391 10:02:51.609226 SPM: spm_kick_pcm_to_run done
5392 10:02:51.612416 SPM: spm_init done in 52 msecs
5393 10:02:51.616175 Root Device init finished in 494999 usecs
5394 10:02:51.619539 CPU_CLUSTER: 0 init ...
5395 10:02:51.629346 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5396 10:02:51.632498 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5397 10:02:51.635954 CBFS @ 21000 size 3d4000
5398 10:02:51.639624 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5399 10:02:51.642786 CBFS: Locating 'sspm.bin'
5400 10:02:51.645896 CBFS: Found @ offset 208c0 size 41cb
5401 10:02:51.656349 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5402 10:02:51.664200 CPU_CLUSTER: 0 init finished in 42801 usecs
5403 10:02:51.664766 Devices initialized
5404 10:02:51.667599 Show all devs... After init.
5405 10:02:51.670939 Root Device: enabled 1
5406 10:02:51.671553 CPU_CLUSTER: 0: enabled 1
5407 10:02:51.673741 CPU: 00: enabled 1
5408 10:02:51.676914 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5409 10:02:51.680907 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5410 10:02:51.683971 ELOG: NV offset 0x558000 size 0x1000
5411 10:02:51.691719 read SPI 0x558000 0x1000: 1258 us, 3255 KB/s, 26.040 Mbps
5412 10:02:51.698499 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5413 10:02:51.701612 ELOG: Event(17) added with size 13 at 2024-06-18 10:01:53 UTC
5414 10:02:51.708330 out: cmd=0x121: 03 db 21 01 00 00 00 00
5415 10:02:51.711574 in-header: 03 34 00 00 2c 00 00 00
5416 10:02:51.721093 in-data: 5d 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 92 1f 01 00 06 80 00 00 8e 2b 02 00 06 80 00 00 07 0c 01 00 06 80 00 00 0d 3b 02 00
5417 10:02:51.724425 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5418 10:02:51.727568 in-header: 03 19 00 00 08 00 00 00
5419 10:02:51.730851 in-data: a2 e0 47 00 13 00 00 00
5420 10:02:51.734544 Chrome EC: UHEPI supported
5421 10:02:51.740899 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5422 10:02:51.744143 in-header: 03 e1 00 00 08 00 00 00
5423 10:02:51.747275 in-data: 84 20 60 10 00 00 00 00
5424 10:02:51.750699 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5425 10:02:51.757380 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5426 10:02:51.761057 in-header: 03 e1 00 00 08 00 00 00
5427 10:02:51.763862 in-data: 84 20 60 10 00 00 00 00
5428 10:02:51.770687 ELOG: Event(A1) added with size 10 at 2024-06-18 10:01:53 UTC
5429 10:02:51.777260 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5430 10:02:51.780456 ELOG: Event(A0) added with size 9 at 2024-06-18 10:01:53 UTC
5431 10:02:51.787657 elog_add_boot_reason: Logged dev mode boot
5432 10:02:51.788202 Finalize devices...
5433 10:02:51.791374 Devices finalized
5434 10:02:51.794427 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
5435 10:02:51.801369 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5436 10:02:51.804306 ELOG: Event(91) added with size 10 at 2024-06-18 10:01:53 UTC
5437 10:02:51.807607 Writing coreboot table at 0xffeda000
5438 10:02:51.811305 0. 0000000000114000-000000000011efff: RAMSTAGE
5439 10:02:51.817692 1. 0000000040000000-000000004023cfff: RAMSTAGE
5440 10:02:51.820713 2. 000000004023d000-00000000545fffff: RAM
5441 10:02:51.824372 3. 0000000054600000-000000005465ffff: BL31
5442 10:02:51.827966 4. 0000000054660000-00000000ffed9fff: RAM
5443 10:02:51.834579 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5444 10:02:51.837386 6. 0000000100000000-000000013fffffff: RAM
5445 10:02:51.840776 Passing 5 GPIOs to payload:
5446 10:02:51.844463 NAME | PORT | POLARITY | VALUE
5447 10:02:51.847704 write protect | 0x00000096 | low | low
5448 10:02:51.853924 EC in RW | 0x000000b1 | high | undefined
5449 10:02:51.857594 EC interrupt | 0x00000097 | low | undefined
5450 10:02:51.864270 TPM interrupt | 0x00000099 | high | undefined
5451 10:02:51.867568 speaker enable | 0x000000af | high | undefined
5452 10:02:51.870702 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5453 10:02:51.874084 in-header: 03 f7 00 00 02 00 00 00
5454 10:02:51.877511 in-data: 04 00
5455 10:02:51.878141 Board ID: 4
5456 10:02:51.880538 ADC[3]: Raw value=215504 ID=1
5457 10:02:51.880999 RAM code: 1
5458 10:02:51.881362 SKU ID: 16
5459 10:02:51.887180 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5460 10:02:51.887823 CBFS @ 21000 size 3d4000
5461 10:02:51.893928 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5462 10:02:51.900194 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 77ff
5463 10:02:51.904067 coreboot table: 940 bytes.
5464 10:02:51.907143 IMD ROOT 0. 00000000fffff000 00001000
5465 10:02:51.910704 IMD SMALL 1. 00000000ffffe000 00001000
5466 10:02:51.914011 CONSOLE 2. 00000000fffde000 00020000
5467 10:02:51.916776 FMAP 3. 00000000fffdd000 0000047c
5468 10:02:51.919882 TIME STAMP 4. 00000000fffdc000 00000910
5469 10:02:51.923494 RAMOOPS 5. 00000000ffedc000 00100000
5470 10:02:51.927219 COREBOOT 6. 00000000ffeda000 00002000
5471 10:02:51.930506 IMD small region:
5472 10:02:51.933764 IMD ROOT 0. 00000000ffffec00 00000400
5473 10:02:51.936544 VBOOT WORK 1. 00000000ffffeb00 00000100
5474 10:02:51.940323 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5475 10:02:51.943385 VPD 3. 00000000ffffea60 0000006c
5476 10:02:51.950062 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5477 10:02:51.956901 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5478 10:02:51.959877 in-header: 03 e1 00 00 08 00 00 00
5479 10:02:51.962941 in-data: 84 20 60 10 00 00 00 00
5480 10:02:51.966395 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5481 10:02:51.969506 CBFS @ 21000 size 3d4000
5482 10:02:51.973033 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5483 10:02:51.976124 CBFS: Locating 'fallback/payload'
5484 10:02:51.986141 CBFS: Found @ offset dc040 size 439a0
5485 10:02:52.073159 read SPI 0xfd078 0x439a0: 84378 us, 3281 KB/s, 26.248 Mbps
5486 10:02:52.076738 Checking segment from ROM address 0x0000000040003a00
5487 10:02:52.083457 Checking segment from ROM address 0x0000000040003a1c
5488 10:02:52.086558 Loading segment from ROM address 0x0000000040003a00
5489 10:02:52.089824 code (compression=0)
5490 10:02:52.099689 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5491 10:02:52.106401 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5492 10:02:52.109469 it's not compressed!
5493 10:02:52.112694 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5494 10:02:52.119306 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5495 10:02:52.127741 Loading segment from ROM address 0x0000000040003a1c
5496 10:02:52.131579 Entry Point 0x0000000080000000
5497 10:02:52.132004 Loaded segments
5498 10:02:52.137903 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5499 10:02:52.141252 Jumping to boot code at 0000000080000000(00000000ffeda000)
5500 10:02:52.151115 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5501 10:02:52.154320 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5502 10:02:52.157931 CBFS @ 21000 size 3d4000
5503 10:02:52.164761 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5504 10:02:52.165292 CBFS: Locating 'fallback/bl31'
5505 10:02:52.168100 CBFS: Found @ offset 36dc0 size 5820
5506 10:02:52.181817 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5507 10:02:52.184833 Checking segment from ROM address 0x0000000040003a00
5508 10:02:52.191539 Checking segment from ROM address 0x0000000040003a1c
5509 10:02:52.194652 Loading segment from ROM address 0x0000000040003a00
5510 10:02:52.197942 code (compression=1)
5511 10:02:52.205059 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5512 10:02:52.214549 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5513 10:02:52.215118 using LZMA
5514 10:02:52.223386 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5515 10:02:52.230186 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5516 10:02:52.234212 Loading segment from ROM address 0x0000000040003a1c
5517 10:02:52.236828 Entry Point 0x0000000054601000
5518 10:02:52.237295 Loaded segments
5519 10:02:52.240345 NOTICE: MT8183 bl31_setup
5520 10:02:52.247126 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5521 10:02:52.250433 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5522 10:02:52.253699 INFO: [DEVAPC] dump DEVAPC registers:
5523 10:02:52.264126 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5524 10:02:52.270744 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5525 10:02:52.280571 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5526 10:02:52.287320 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5527 10:02:52.297294 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5528 10:02:52.303786 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5529 10:02:52.313876 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5530 10:02:52.320203 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5531 10:02:52.327127 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5532 10:02:52.337033 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5533 10:02:52.343281 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5534 10:02:52.353149 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5535 10:02:52.360090 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5536 10:02:52.370028 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5537 10:02:52.376603 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5538 10:02:52.383508 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5539 10:02:52.390363 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5540 10:02:52.396790 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5541 10:02:52.406492 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5542 10:02:52.413228 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5543 10:02:52.419522 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5544 10:02:52.426700 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5545 10:02:52.429567 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5546 10:02:52.433130 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5547 10:02:52.436319 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5548 10:02:52.439817 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5549 10:02:52.443312 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5550 10:02:52.449554 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5551 10:02:52.456295 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5552 10:02:52.456869 WARNING: region 0:
5553 10:02:52.459499 WARNING: apc:0x168, sa:0x0, ea:0xfff
5554 10:02:52.462821 WARNING: region 1:
5555 10:02:52.465967 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5556 10:02:52.466432 WARNING: region 2:
5557 10:02:52.469611 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5558 10:02:52.472913 WARNING: region 3:
5559 10:02:52.476183 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5560 10:02:52.476604 WARNING: region 4:
5561 10:02:52.482976 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5562 10:02:52.483393 WARNING: region 5:
5563 10:02:52.486306 WARNING: apc:0x0, sa:0x0, ea:0x0
5564 10:02:52.489373 WARNING: region 6:
5565 10:02:52.493044 WARNING: apc:0x0, sa:0x0, ea:0x0
5566 10:02:52.493461 WARNING: region 7:
5567 10:02:52.496188 WARNING: apc:0x0, sa:0x0, ea:0x0
5568 10:02:52.502867 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5569 10:02:52.506288 INFO: SPM: enable SPMC mode
5570 10:02:52.509399 NOTICE: spm_boot_init() start
5571 10:02:52.513172 NOTICE: spm_boot_init() end
5572 10:02:52.516003 INFO: BL31: Initializing runtime services
5573 10:02:52.523025 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5574 10:02:52.525866 INFO: BL31: Preparing for EL3 exit to normal world
5575 10:02:52.529437 INFO: Entry point address = 0x80000000
5576 10:02:52.532467 INFO: SPSR = 0x8
5577 10:02:52.553592
5578 10:02:52.554145
5579 10:02:52.554512
5580 10:02:52.554921 Starting depthcharge on Juniper...
5581 10:02:52.556692 end: 2.2.3 depthcharge-start (duration 00:00:11) [common]
5582 10:02:52.557249 start: 2.2.4 bootloader-commands (timeout 00:04:24) [common]
5583 10:02:52.557687 Setting prompt string to ['jacuzzi:']
5584 10:02:52.558148 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:24)
5585 10:02:52.558946
5586 10:02:52.560137 vboot_handoff: creating legacy vboot_handoff structure
5587 10:02:52.560597
5588 10:02:52.563795 ec_init(0): CrosEC protocol v3 supported (544, 544)
5589 10:02:52.564258
5590 10:02:52.566891 Wipe memory regions:
5591 10:02:52.567294
5592 10:02:52.570337 [0x00000040000000, 0x00000054600000)
5593 10:02:52.612764
5594 10:02:52.613318 [0x00000054660000, 0x00000080000000)
5595 10:02:52.704258
5596 10:02:52.704814 [0x000000811994a0, 0x000000ffeda000)
5597 10:02:52.964626
5598 10:02:52.965182 [0x00000100000000, 0x00000140000000)
5599 10:02:53.096877
5600 10:02:53.100515 Initializing XHCI USB controller at 0x11200000.
5601 10:02:53.123765
5602 10:02:53.126622 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5603 10:02:53.127085
5604 10:02:53.127484
5605 10:02:53.128458 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5607 10:02:53.230099 jacuzzi: tftpboot 192.168.201.1 14407643/tftp-deploy-suje0j50/kernel/image.itb 14407643/tftp-deploy-suje0j50/kernel/cmdline
5608 10:02:53.230773 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5609 10:02:53.231226 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
5610 10:02:53.236321 tftpboot 192.168.201.1 14407643/tftp-deploy-suje0j50/kernel/image.ittp-deploy-suje0j50/kernel/cmdline
5611 10:02:53.236796
5612 10:02:53.237159 Waiting for link
5613 10:02:53.637521
5614 10:02:53.638089 R8152: Initializing
5615 10:02:53.638463
5616 10:02:53.640735 Version 9 (ocp_data = 6010)
5617 10:02:53.641295
5618 10:02:53.643649 R8152: Done initializing
5619 10:02:53.644112
5620 10:02:53.644480 Adding net device
5621 10:02:54.029550
5622 10:02:54.030225 done.
5623 10:02:54.030602
5624 10:02:54.030947 MAC: 00:e0:4c:68:0b:b9
5625 10:02:54.031280
5626 10:02:54.032583 Sending DHCP discover... done.
5627 10:02:54.033048
5628 10:02:54.036265 Waiting for reply... done.
5629 10:02:54.036730
5630 10:02:54.039244 Sending DHCP request... done.
5631 10:02:54.039753
5632 10:02:54.040086 Waiting for reply... done.
5633 10:02:54.040399
5634 10:02:54.042510 My ip is 192.168.201.13
5635 10:02:54.042928
5636 10:02:54.046139 The DHCP server ip is 192.168.201.1
5637 10:02:54.046674
5638 10:02:54.049737 TFTP server IP predefined by user: 192.168.201.1
5639 10:02:54.050258
5640 10:02:54.056435 Bootfile predefined by user: 14407643/tftp-deploy-suje0j50/kernel/image.itb
5641 10:02:54.056960
5642 10:02:54.059630 Sending tftp read request... done.
5643 10:02:54.060116
5644 10:02:54.067550 Waiting for the transfer...
5645 10:02:54.068012
5646 10:02:54.380699 00000000 ################################################################
5647 10:02:54.380862
5648 10:02:54.673412 00080000 ################################################################
5649 10:02:54.673606
5650 10:02:54.943819 00100000 ################################################################
5651 10:02:54.943973
5652 10:02:55.240486 00180000 ################################################################
5653 10:02:55.240641
5654 10:02:55.510856 00200000 ################################################################
5655 10:02:55.511023
5656 10:02:55.805997 00280000 ################################################################
5657 10:02:55.806154
5658 10:02:56.103862 00300000 ################################################################
5659 10:02:56.104012
5660 10:02:56.376756 00380000 ################################################################
5661 10:02:56.376913
5662 10:02:56.648401 00400000 ################################################################
5663 10:02:56.648548
5664 10:02:56.936094 00480000 ################################################################
5665 10:02:56.936252
5666 10:02:57.236290 00500000 ################################################################
5667 10:02:57.236443
5668 10:02:57.498082 00580000 ################################################################
5669 10:02:57.498266
5670 10:02:57.758444 00600000 ################################################################
5671 10:02:57.758638
5672 10:02:58.011051 00680000 ################################################################
5673 10:02:58.011232
5674 10:02:58.264165 00700000 ################################################################
5675 10:02:58.264323
5676 10:02:58.516467 00780000 ################################################################
5677 10:02:58.516623
5678 10:02:58.772799 00800000 ################################################################
5679 10:02:58.772950
5680 10:02:59.025846 00880000 ################################################################
5681 10:02:59.025999
5682 10:02:59.278189 00900000 ################################################################
5683 10:02:59.278344
5684 10:02:59.530792 00980000 ################################################################
5685 10:02:59.530948
5686 10:02:59.783864 00a00000 ################################################################
5687 10:02:59.784011
5688 10:03:00.037127 00a80000 ################################################################
5689 10:03:00.037275
5690 10:03:00.292752 00b00000 ################################################################
5691 10:03:00.292900
5692 10:03:00.547372 00b80000 ################################################################
5693 10:03:00.547537
5694 10:03:00.800818 00c00000 ################################################################
5695 10:03:00.800964
5696 10:03:01.054101 00c80000 ################################################################
5697 10:03:01.054248
5698 10:03:01.307058 00d00000 ################################################################
5699 10:03:01.307206
5700 10:03:01.561886 00d80000 ################################################################
5701 10:03:01.562044
5702 10:03:01.815544 00e00000 ################################################################
5703 10:03:01.815696
5704 10:03:02.070906 00e80000 ################################################################
5705 10:03:02.071060
5706 10:03:02.327350 00f00000 ################################################################
5707 10:03:02.327513
5708 10:03:02.584197 00f80000 ################################################################
5709 10:03:02.584346
5710 10:03:02.865166 01000000 ################################################################
5711 10:03:02.865345
5712 10:03:03.165654 01080000 ################################################################
5713 10:03:03.165808
5714 10:03:03.419330 01100000 ################################################################
5715 10:03:03.419502
5716 10:03:03.677559 01180000 ################################################################
5717 10:03:03.677710
5718 10:03:03.931943 01200000 ################################################################
5719 10:03:03.932101
5720 10:03:04.191697 01280000 ################################################################
5721 10:03:04.191847
5722 10:03:04.488246 01300000 ################################################################
5723 10:03:04.488398
5724 10:03:04.765557 01380000 ################################################################
5725 10:03:04.765714
5726 10:03:05.024910 01400000 ################################################################
5727 10:03:05.025062
5728 10:03:05.288925 01480000 ################################################################
5729 10:03:05.289071
5730 10:03:05.541859 01500000 ################################################################
5731 10:03:05.542008
5732 10:03:05.799737 01580000 ################################################################
5733 10:03:05.799915
5734 10:03:06.052760 01600000 ################################################################
5735 10:03:06.052912
5736 10:03:06.370731 01680000 ################################################################
5737 10:03:06.371244
5738 10:03:06.727769 01700000 ################################################################
5739 10:03:06.727926
5740 10:03:06.980501 01780000 ################################################################
5741 10:03:06.980656
5742 10:03:07.233956 01800000 ################################################################
5743 10:03:07.234100
5744 10:03:07.487265 01880000 ################################################################
5745 10:03:07.487425
5746 10:03:07.739804 01900000 ################################################################
5747 10:03:07.739961
5748 10:03:07.991554 01980000 ################################################################
5749 10:03:07.991712
5750 10:03:08.244327 01a00000 ################################################################
5751 10:03:08.244481
5752 10:03:08.498186 01a80000 ################################################################
5753 10:03:08.498338
5754 10:03:08.753319 01b00000 ################################################################
5755 10:03:08.753470
5756 10:03:09.006681 01b80000 ################################################################
5757 10:03:09.006836
5758 10:03:09.261792 01c00000 ################################################################
5759 10:03:09.261952
5760 10:03:09.517329 01c80000 ################################################################
5761 10:03:09.517514
5762 10:03:09.770722 01d00000 ################################################################
5763 10:03:09.770901
5764 10:03:10.023422 01d80000 ################################################################
5765 10:03:10.023605
5766 10:03:10.252832 01e00000 ########################################################## done.
5767 10:03:10.252981
5768 10:03:10.255941 The bootfile was 31931374 bytes long.
5769 10:03:10.256036
5770 10:03:10.259611 Sending tftp read request... done.
5771 10:03:10.259702
5772 10:03:10.259774 Waiting for the transfer...
5773 10:03:10.259841
5774 10:03:10.262867 00000000 # done.
5775 10:03:10.262962
5776 10:03:10.269243 Command line loaded dynamically from TFTP file: 14407643/tftp-deploy-suje0j50/kernel/cmdline
5777 10:03:10.269336
5778 10:03:10.295888 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407643/extract-nfsrootfs-ypalcua5,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5779 10:03:10.296014
5780 10:03:10.296153 Loading FIT.
5781 10:03:10.296248
5782 10:03:10.299385 Image ramdisk-1 has 18744902 bytes.
5783 10:03:10.299521
5784 10:03:10.302693 Image fdt-1 has 57695 bytes.
5785 10:03:10.302828
5786 10:03:10.305861 Image kernel-1 has 13126726 bytes.
5787 10:03:10.306042
5788 10:03:10.315955 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5789 10:03:10.316149
5790 10:03:10.325682 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5791 10:03:10.325970
5792 10:03:10.332758 Choosing best match conf-1 for compat google,juniper-sku16.
5793 10:03:10.337265
5794 10:03:10.342990 Connected to device vid:did:rid of 1ae0:0028:00
5795 10:03:10.349553
5796 10:03:10.352770 tpm_get_response: command 0x17b, return code 0x0
5797 10:03:10.353303
5798 10:03:10.356712 tpm_cleanup: add release locality here.
5799 10:03:10.357177
5800 10:03:10.359880 Shutting down all USB controllers.
5801 10:03:10.360370
5802 10:03:10.362888 Removing current net device
5803 10:03:10.363390
5804 10:03:10.366465 Exiting depthcharge with code 4 at timestamp: 35059991
5805 10:03:10.367012
5806 10:03:10.369163 LZMA decompressing kernel-1 to 0x80193568
5807 10:03:10.369634
5808 10:03:10.376374 LZMA decompressing kernel-1 to 0x40000000
5809 10:03:12.241735
5810 10:03:12.242366 jumping to kernel
5811 10:03:12.245302 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
5812 10:03:12.246095 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
5813 10:03:12.246688 Setting prompt string to ['Linux version [0-9]']
5814 10:03:12.247281 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5815 10:03:12.247974 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5816 10:03:12.316868
5817 10:03:12.320382 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5818 10:03:12.324588 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
5819 10:03:12.325207 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5820 10:03:12.325674 Setting prompt string to []
5821 10:03:12.326343 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5822 10:03:12.326874 Using line separator: #'\n'#
5823 10:03:12.327287 No login prompt set.
5824 10:03:12.327794 Parsing kernel messages
5825 10:03:12.328199 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5826 10:03:12.328899 [login-action] Waiting for messages, (timeout 00:04:04)
5827 10:03:12.329349 Waiting using forced prompt support (timeout 00:02:02)
5828 10:03:12.343469 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
5829 10:03:12.346658 [ 0.000000] random: crng init done
5830 10:03:12.353335 [ 0.000000] Machine model: Google juniper sku16 board
5831 10:03:12.356418 [ 0.000000] efi: UEFI not found.
5832 10:03:12.363294 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5833 10:03:12.373273 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5834 10:03:12.379832 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5835 10:03:12.382663 [ 0.000000] printk: bootconsole [mtk8250] enabled
5836 10:03:12.391998 [ 0.000000] NUMA: No NUMA configuration found
5837 10:03:12.398643 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5838 10:03:12.405602 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5839 10:03:12.406178 [ 0.000000] Zone ranges:
5840 10:03:12.411879 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5841 10:03:12.414777 [ 0.000000] DMA32 empty
5842 10:03:12.421651 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5843 10:03:12.424626 [ 0.000000] Movable zone start for each node
5844 10:03:12.428110 [ 0.000000] Early memory node ranges
5845 10:03:12.435244 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5846 10:03:12.441497 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5847 10:03:12.447997 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5848 10:03:12.454964 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5849 10:03:12.461799 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5850 10:03:12.468395 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5851 10:03:12.484171 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5852 10:03:12.491374 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5853 10:03:12.497428 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5854 10:03:12.500457 [ 0.000000] psci: probing for conduit method from DT.
5855 10:03:12.507544 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5856 10:03:12.510809 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5857 10:03:12.517933 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5858 10:03:12.520409 [ 0.000000] psci: SMC Calling Convention v1.1
5859 10:03:12.527310 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5860 10:03:12.530615 [ 0.000000] Detected VIPT I-cache on CPU0
5861 10:03:12.537234 [ 0.000000] CPU features: detected: GIC system register CPU interface
5862 10:03:12.544034 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5863 10:03:12.550684 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5864 10:03:12.557077 [ 0.000000] CPU features: detected: ARM erratum 845719
5865 10:03:12.560445 [ 0.000000] alternatives: applying boot alternatives
5866 10:03:12.564022 [ 0.000000] Fallback order for Node 0: 0
5867 10:03:12.570517 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5868 10:03:12.573336 [ 0.000000] Policy zone: Normal
5869 10:03:12.600089 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407643/extract-nfsrootfs-ypalcua5,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5870 10:03:12.613706 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5871 10:03:12.623886 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5872 10:03:12.629868 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5873 10:03:12.636962 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5874 10:03:12.643155 <6>[ 0.000000] software IO TLB: area num 8.
5875 10:03:12.667607 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5876 10:03:12.725867 <6>[ 0.000000] Memory: 3896768K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 261696K reserved, 32768K cma-reserved)
5877 10:03:12.731997 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5878 10:03:12.738598 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5879 10:03:12.742390 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5880 10:03:12.748657 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5881 10:03:12.755768 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5882 10:03:12.758955 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5883 10:03:12.768578 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5884 10:03:12.775351 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5885 10:03:12.781909 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5886 10:03:12.791948 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5887 10:03:12.795105 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5888 10:03:12.798730 <6>[ 0.000000] GICv3: 640 SPIs implemented
5889 10:03:12.804831 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5890 10:03:12.808076 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5891 10:03:12.815144 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5892 10:03:12.821605 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5893 10:03:12.831735 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5894 10:03:12.844931 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5895 10:03:12.851797 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5896 10:03:12.862977 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5897 10:03:12.875766 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5898 10:03:12.882260 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5899 10:03:12.889010 <6>[ 0.009471] Console: colour dummy device 80x25
5900 10:03:12.892594 <6>[ 0.014514] printk: console [tty1] enabled
5901 10:03:12.902931 <6>[ 0.018902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5902 10:03:12.909123 <6>[ 0.029367] pid_max: default: 32768 minimum: 301
5903 10:03:12.912754 <6>[ 0.034248] LSM: Security Framework initializing
5904 10:03:12.922361 <6>[ 0.039164] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5905 10:03:12.929314 <6>[ 0.046788] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5906 10:03:12.935751 <4>[ 0.055656] cacheinfo: Unable to detect cache hierarchy for CPU 0
5907 10:03:12.946018 <6>[ 0.062285] cblist_init_generic: Setting adjustable number of callback queues.
5908 10:03:12.952088 <6>[ 0.069731] cblist_init_generic: Setting shift to 3 and lim to 1.
5909 10:03:12.958993 <6>[ 0.076084] cblist_init_generic: Setting adjustable number of callback queues.
5910 10:03:12.965687 <6>[ 0.083528] cblist_init_generic: Setting shift to 3 and lim to 1.
5911 10:03:12.968892 <6>[ 0.089927] rcu: Hierarchical SRCU implementation.
5912 10:03:12.975664 <6>[ 0.094953] rcu: Max phase no-delay instances is 1000.
5913 10:03:12.982479 <6>[ 0.102878] EFI services will not be available.
5914 10:03:12.986031 <6>[ 0.107827] smp: Bringing up secondary CPUs ...
5915 10:03:12.996592 <6>[ 0.113099] Detected VIPT I-cache on CPU1
5916 10:03:13.002818 <4>[ 0.113146] cacheinfo: Unable to detect cache hierarchy for CPU 1
5917 10:03:13.009471 <6>[ 0.113155] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5918 10:03:13.016381 <6>[ 0.113185] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5919 10:03:13.019955 <6>[ 0.113669] Detected VIPT I-cache on CPU2
5920 10:03:13.026668 <4>[ 0.113702] cacheinfo: Unable to detect cache hierarchy for CPU 2
5921 10:03:13.033000 <6>[ 0.113707] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5922 10:03:13.039932 <6>[ 0.113718] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5923 10:03:13.042987 <6>[ 0.114164] Detected VIPT I-cache on CPU3
5924 10:03:13.049457 <4>[ 0.114195] cacheinfo: Unable to detect cache hierarchy for CPU 3
5925 10:03:13.059613 <6>[ 0.114200] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5926 10:03:13.066107 <6>[ 0.114211] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5927 10:03:13.069535 <6>[ 0.114785] CPU features: detected: Spectre-v2
5928 10:03:13.072615 <6>[ 0.114795] CPU features: detected: Spectre-BHB
5929 10:03:13.079546 <6>[ 0.114799] CPU features: detected: ARM erratum 858921
5930 10:03:13.082922 <6>[ 0.114804] Detected VIPT I-cache on CPU4
5931 10:03:13.089358 <4>[ 0.114851] cacheinfo: Unable to detect cache hierarchy for CPU 4
5932 10:03:13.096364 <6>[ 0.114859] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5933 10:03:13.102730 <6>[ 0.114867] arch_timer: Enabling local workaround for ARM erratum 858921
5934 10:03:13.109227 <6>[ 0.114877] arch_timer: CPU4: Trapping CNTVCT access
5935 10:03:13.115907 <6>[ 0.114885] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5936 10:03:13.119186 <6>[ 0.115371] Detected VIPT I-cache on CPU5
5937 10:03:13.125768 <4>[ 0.115413] cacheinfo: Unable to detect cache hierarchy for CPU 5
5938 10:03:13.132515 <6>[ 0.115419] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5939 10:03:13.142253 <6>[ 0.115426] arch_timer: Enabling local workaround for ARM erratum 858921
5940 10:03:13.146053 <6>[ 0.115432] arch_timer: CPU5: Trapping CNTVCT access
5941 10:03:13.152148 <6>[ 0.115437] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5942 10:03:13.155632 <6>[ 0.115871] Detected VIPT I-cache on CPU6
5943 10:03:13.162616 <4>[ 0.115917] cacheinfo: Unable to detect cache hierarchy for CPU 6
5944 10:03:13.168733 <6>[ 0.115923] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5945 10:03:13.178932 <6>[ 0.115931] arch_timer: Enabling local workaround for ARM erratum 858921
5946 10:03:13.182285 <6>[ 0.115937] arch_timer: CPU6: Trapping CNTVCT access
5947 10:03:13.188581 <6>[ 0.115942] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5948 10:03:13.191809 <6>[ 0.116472] Detected VIPT I-cache on CPU7
5949 10:03:13.198707 <4>[ 0.116516] cacheinfo: Unable to detect cache hierarchy for CPU 7
5950 10:03:13.208341 <6>[ 0.116522] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5951 10:03:13.214767 <6>[ 0.116529] arch_timer: Enabling local workaround for ARM erratum 858921
5952 10:03:13.218137 <6>[ 0.116535] arch_timer: CPU7: Trapping CNTVCT access
5953 10:03:13.224861 <6>[ 0.116540] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5954 10:03:13.231444 <6>[ 0.116614] smp: Brought up 1 node, 8 CPUs
5955 10:03:13.234729 <6>[ 0.355482] SMP: Total of 8 processors activated.
5956 10:03:13.241157 <6>[ 0.360418] CPU features: detected: 32-bit EL0 Support
5957 10:03:13.244698 <6>[ 0.365789] CPU features: detected: 32-bit EL1 Support
5958 10:03:13.251649 <6>[ 0.371154] CPU features: detected: CRC32 instructions
5959 10:03:13.254516 <6>[ 0.376581] CPU: All CPU(s) started at EL2
5960 10:03:13.261253 <6>[ 0.380919] alternatives: applying system-wide alternatives
5961 10:03:13.268449 <6>[ 0.388900] devtmpfs: initialized
5962 10:03:13.281128 <6>[ 0.397865] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5963 10:03:13.291263 <6>[ 0.407814] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5964 10:03:13.294438 <6>[ 0.415543] pinctrl core: initialized pinctrl subsystem
5965 10:03:13.302808 <6>[ 0.422637] DMI not present or invalid.
5966 10:03:13.309564 <6>[ 0.427005] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5967 10:03:13.315868 <6>[ 0.433914] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5968 10:03:13.325716 <6>[ 0.441442] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5969 10:03:13.332487 <6>[ 0.449694] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5970 10:03:13.338913 <6>[ 0.457872] audit: initializing netlink subsys (disabled)
5971 10:03:13.345707 <5>[ 0.463576] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5972 10:03:13.352135 <6>[ 0.464553] thermal_sys: Registered thermal governor 'step_wise'
5973 10:03:13.358538 <6>[ 0.471543] thermal_sys: Registered thermal governor 'power_allocator'
5974 10:03:13.361910 <6>[ 0.477840] cpuidle: using governor menu
5975 10:03:13.368408 <6>[ 0.488801] NET: Registered PF_QIPCRTR protocol family
5976 10:03:13.375555 <6>[ 0.494295] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5977 10:03:13.381799 <6>[ 0.501389] ASID allocator initialised with 32768 entries
5978 10:03:13.388624 <6>[ 0.508156] Serial: AMBA PL011 UART driver
5979 10:03:13.398493 <4>[ 0.518565] Trying to register duplicate clock ID: 113
5980 10:03:13.458306 <6>[ 0.575288] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5981 10:03:13.472929 <6>[ 0.589635] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5982 10:03:13.476337 <6>[ 0.599384] KASLR enabled
5983 10:03:13.490818 <6>[ 0.607392] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5984 10:03:13.497380 <6>[ 0.614394] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5985 10:03:13.504181 <6>[ 0.620870] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5986 10:03:13.510827 <6>[ 0.627861] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5987 10:03:13.517185 <6>[ 0.634334] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5988 10:03:13.523630 <6>[ 0.641325] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5989 10:03:13.530991 <6>[ 0.647798] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5990 10:03:13.536909 <6>[ 0.654788] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5991 10:03:13.540919 <6>[ 0.662354] ACPI: Interpreter disabled.
5992 10:03:13.550326 <6>[ 0.670346] iommu: Default domain type: Translated
5993 10:03:13.557246 <6>[ 0.675453] iommu: DMA domain TLB invalidation policy: strict mode
5994 10:03:13.560153 <5>[ 0.682085] SCSI subsystem initialized
5995 10:03:13.567068 <6>[ 0.686497] usbcore: registered new interface driver usbfs
5996 10:03:13.573953 <6>[ 0.692225] usbcore: registered new interface driver hub
5997 10:03:13.576841 <6>[ 0.697767] usbcore: registered new device driver usb
5998 10:03:13.584137 <6>[ 0.704076] pps_core: LinuxPPS API ver. 1 registered
5999 10:03:13.593736 <6>[ 0.709260] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
6000 10:03:13.597871 <6>[ 0.718584] PTP clock support registered
6001 10:03:13.600546 <6>[ 0.722838] EDAC MC: Ver: 3.0.0
6002 10:03:13.608055 <6>[ 0.728472] FPGA manager framework
6003 10:03:13.611484 <6>[ 0.732156] Advanced Linux Sound Architecture Driver Initialized.
6004 10:03:13.615545 <6>[ 0.738909] vgaarb: loaded
6005 10:03:13.622419 <6>[ 0.742038] clocksource: Switched to clocksource arch_sys_counter
6006 10:03:13.628605 <5>[ 0.748467] VFS: Disk quotas dquot_6.6.0
6007 10:03:13.635592 <6>[ 0.752644] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
6008 10:03:13.638528 <6>[ 0.759816] pnp: PnP ACPI: disabled
6009 10:03:13.646528 <6>[ 0.766707] NET: Registered PF_INET protocol family
6010 10:03:13.653559 <6>[ 0.771939] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
6011 10:03:13.665010 <6>[ 0.781852] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
6012 10:03:13.675055 <6>[ 0.790607] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
6013 10:03:13.681441 <6>[ 0.798557] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
6014 10:03:13.688366 <6>[ 0.806790] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
6015 10:03:13.698049 <6>[ 0.814883] TCP: Hash tables configured (established 32768 bind 32768)
6016 10:03:13.704724 <6>[ 0.821711] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
6017 10:03:13.711717 <6>[ 0.828681] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
6018 10:03:13.718059 <6>[ 0.836162] NET: Registered PF_UNIX/PF_LOCAL protocol family
6019 10:03:13.724535 <6>[ 0.842253] RPC: Registered named UNIX socket transport module.
6020 10:03:13.727551 <6>[ 0.848396] RPC: Registered udp transport module.
6021 10:03:13.734688 <6>[ 0.853321] RPC: Registered tcp transport module.
6022 10:03:13.741224 <6>[ 0.858244] RPC: Registered tcp NFSv4.1 backchannel transport module.
6023 10:03:13.744743 <6>[ 0.864896] PCI: CLS 0 bytes, default 64
6024 10:03:13.747870 <6>[ 0.869178] Unpacking initramfs...
6025 10:03:13.769390 <6>[ 0.886168] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6026 10:03:13.779292 <6>[ 0.894793] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6027 10:03:13.782486 <6>[ 0.903642] kvm [1]: IPA Size Limit: 40 bits
6028 10:03:13.789744 <6>[ 0.909964] kvm [1]: vgic-v2@c420000
6029 10:03:13.793104 <6>[ 0.913779] kvm [1]: GIC system register CPU interface enabled
6030 10:03:13.799936 <6>[ 0.919940] kvm [1]: vgic interrupt IRQ18
6031 10:03:13.803544 <6>[ 0.924288] kvm [1]: Hyp mode initialized successfully
6032 10:03:13.810362 <5>[ 0.930588] Initialise system trusted keyrings
6033 10:03:13.816921 <6>[ 0.935421] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6034 10:03:13.825569 <6>[ 0.945389] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6035 10:03:13.831915 <5>[ 0.951830] NFS: Registering the id_resolver key type
6036 10:03:13.835230 <5>[ 0.957138] Key type id_resolver registered
6037 10:03:13.842065 <5>[ 0.961549] Key type id_legacy registered
6038 10:03:13.848299 <6>[ 0.965856] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6039 10:03:13.855271 <6>[ 0.972791] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6040 10:03:13.861597 <6>[ 0.980548] 9p: Installing v9fs 9p2000 file system support
6041 10:03:13.889719 <5>[ 1.009904] Key type asymmetric registered
6042 10:03:13.892833 <5>[ 1.014245] Asymmetric key parser 'x509' registered
6043 10:03:13.902886 <6>[ 1.019407] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6044 10:03:13.906233 <6>[ 1.027024] io scheduler mq-deadline registered
6045 10:03:13.909558 <6>[ 1.031780] io scheduler kyber registered
6046 10:03:13.932378 <6>[ 1.052577] EINJ: ACPI disabled.
6047 10:03:13.939084 <4>[ 1.056352] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6048 10:03:13.977245 <6>[ 1.097215] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6049 10:03:13.985144 <6>[ 1.105716] printk: console [ttyS0] disabled
6050 10:03:14.013807 <6>[ 1.130368] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6051 10:03:14.020230 <6>[ 1.139843] printk: console [ttyS0] enabled
6052 10:03:14.023817 <6>[ 1.139843] printk: console [ttyS0] enabled
6053 10:03:14.029770 <6>[ 1.148761] printk: bootconsole [mtk8250] disabled
6054 10:03:14.033298 <6>[ 1.148761] printk: bootconsole [mtk8250] disabled
6055 10:03:14.043526 <3>[ 1.159295] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6056 10:03:14.049865 <3>[ 1.167680] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6057 10:03:14.079526 <6>[ 1.196094] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6058 10:03:14.085775 <6>[ 1.205754] serial serial0: tty port ttyS1 registered
6059 10:03:14.092590 <6>[ 1.212304] SuperH (H)SCI(F) driver initialized
6060 10:03:14.095643 <6>[ 1.217783] msm_serial: driver initialized
6061 10:03:14.111234 <6>[ 1.228115] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6062 10:03:14.121260 <6>[ 1.236715] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6063 10:03:14.128083 <6>[ 1.245292] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6064 10:03:14.137969 <6>[ 1.253864] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6065 10:03:14.144690 <6>[ 1.262519] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6066 10:03:14.154520 <6>[ 1.271181] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6067 10:03:14.164392 <6>[ 1.279919] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6068 10:03:14.170984 <6>[ 1.288657] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6069 10:03:14.181260 <6>[ 1.297221] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6070 10:03:14.191135 <6>[ 1.306025] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6071 10:03:14.198589 <4>[ 1.318414] cacheinfo: Unable to detect cache hierarchy for CPU 0
6072 10:03:14.207971 <6>[ 1.327784] loop: module loaded
6073 10:03:14.219626 <6>[ 1.339719] vsim1: Bringing 1800000uV into 2700000-2700000uV
6074 10:03:14.237312 <6>[ 1.357758] megasas: 07.719.03.00-rc1
6075 10:03:14.246496 <6>[ 1.366639] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6076 10:03:14.261168 <6>[ 1.381418] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6077 10:03:14.277802 <6>[ 1.398199] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6078 10:03:14.334447 <6>[ 1.448235] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1d
6079 10:03:14.357559 <6>[ 1.477913] Freeing initrd memory: 18300K
6080 10:03:14.373017 <4>[ 1.489736] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6081 10:03:14.380056 <4>[ 1.498964] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 6.1.92-cip22 #1
6082 10:03:14.386464 <4>[ 1.505663] Hardware name: Google juniper sku16 board (DT)
6083 10:03:14.390045 <4>[ 1.511402] Call trace:
6084 10:03:14.392754 <4>[ 1.514102] dump_backtrace.part.0+0xe0/0xf0
6085 10:03:14.396699 <4>[ 1.518639] show_stack+0x18/0x30
6086 10:03:14.400030 <4>[ 1.522211] dump_stack_lvl+0x68/0x84
6087 10:03:14.406275 <4>[ 1.526132] dump_stack+0x18/0x34
6088 10:03:14.409937 <4>[ 1.529702] sysfs_warn_dup+0x64/0x80
6089 10:03:14.412688 <4>[ 1.533624] sysfs_do_create_link_sd+0xf0/0x100
6090 10:03:14.416229 <4>[ 1.538411] sysfs_create_link+0x20/0x40
6091 10:03:14.422818 <4>[ 1.542591] bus_add_device+0x68/0x10c
6092 10:03:14.426321 <4>[ 1.546597] device_add+0x340/0x7ac
6093 10:03:14.429890 <4>[ 1.550340] of_device_add+0x44/0x60
6094 10:03:14.432929 <4>[ 1.554174] of_platform_device_create_pdata+0x90/0x120
6095 10:03:14.439922 <4>[ 1.559655] of_platform_bus_create+0x170/0x370
6096 10:03:14.442867 <4>[ 1.564442] of_platform_populate+0x50/0xfc
6097 10:03:14.449843 <4>[ 1.568882] parse_mtd_partitions+0x1dc/0x510
6098 10:03:14.452901 <4>[ 1.573495] mtd_device_parse_register+0xf8/0x2e0
6099 10:03:14.455954 <4>[ 1.578453] spi_nor_probe+0x21c/0x2f0
6100 10:03:14.463319 <4>[ 1.582460] spi_mem_probe+0x6c/0xb0
6101 10:03:14.466478 <4>[ 1.586292] spi_probe+0x84/0xe4
6102 10:03:14.469616 <4>[ 1.589774] really_probe+0xbc/0x2e0
6103 10:03:14.472962 <4>[ 1.593604] __driver_probe_device+0x78/0x11c
6104 10:03:14.475972 <4>[ 1.598216] driver_probe_device+0xd8/0x160
6105 10:03:14.482945 <4>[ 1.602654] __device_attach_driver+0xb8/0x134
6106 10:03:14.485706 <4>[ 1.607353] bus_for_each_drv+0x78/0xd0
6107 10:03:14.489660 <4>[ 1.611443] __device_attach+0xa8/0x1c0
6108 10:03:14.496400 <4>[ 1.615534] device_initial_probe+0x14/0x20
6109 10:03:14.499477 <4>[ 1.619972] bus_probe_device+0x9c/0xa4
6110 10:03:14.502752 <4>[ 1.624063] device_add+0x3ac/0x7ac
6111 10:03:14.505864 <4>[ 1.627805] __spi_add_device+0x78/0x120
6112 10:03:14.509646 <4>[ 1.631983] spi_add_device+0x40/0x7c
6113 10:03:14.515591 <4>[ 1.635901] spi_register_controller+0x610/0xad0
6114 10:03:14.518936 <4>[ 1.640774] devm_spi_register_controller+0x4c/0xa4
6115 10:03:14.525860 <4>[ 1.645907] mtk_spi_probe+0x3f8/0x650
6116 10:03:14.528910 <4>[ 1.649912] platform_probe+0x68/0xe0
6117 10:03:14.532491 <4>[ 1.653831] really_probe+0xbc/0x2e0
6118 10:03:14.535975 <4>[ 1.657661] __driver_probe_device+0x78/0x11c
6119 10:03:14.542448 <4>[ 1.662272] driver_probe_device+0xd8/0x160
6120 10:03:14.545556 <4>[ 1.666710] __driver_attach+0x94/0x19c
6121 10:03:14.549157 <4>[ 1.670802] bus_for_each_dev+0x70/0xd0
6122 10:03:14.552543 <4>[ 1.674892] driver_attach+0x24/0x30
6123 10:03:14.559251 <4>[ 1.678722] bus_add_driver+0x154/0x20c
6124 10:03:14.562429 <4>[ 1.682812] driver_register+0x78/0x130
6125 10:03:14.565945 <4>[ 1.686903] __platform_driver_register+0x28/0x34
6126 10:03:14.572404 <4>[ 1.691863] mtk_spi_driver_init+0x1c/0x28
6127 10:03:14.576042 <4>[ 1.696216] do_one_initcall+0x50/0x1d0
6128 10:03:14.579079 <4>[ 1.700306] kernel_init_freeable+0x21c/0x288
6129 10:03:14.582185 <4>[ 1.704920] kernel_init+0x24/0x12c
6130 10:03:14.588857 <4>[ 1.708665] ret_from_fork+0x10/0x20
6131 10:03:14.597611 <6>[ 1.717560] tun: Universal TUN/TAP device driver, 1.6
6132 10:03:14.600831 <6>[ 1.723853] thunder_xcv, ver 1.0
6133 10:03:14.604288 <6>[ 1.727370] thunder_bgx, ver 1.0
6134 10:03:14.607545 <6>[ 1.730874] nicpf, ver 1.0
6135 10:03:14.618167 <6>[ 1.735245] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6136 10:03:14.622121 <6>[ 1.742729] hns3: Copyright (c) 2017 Huawei Corporation.
6137 10:03:14.625362 <6>[ 1.748327] hclge is initializing
6138 10:03:14.631644 <6>[ 1.751911] e1000: Intel(R) PRO/1000 Network Driver
6139 10:03:14.638632 <6>[ 1.757046] e1000: Copyright (c) 1999-2006 Intel Corporation.
6140 10:03:14.642326 <6>[ 1.763070] e1000e: Intel(R) PRO/1000 Network Driver
6141 10:03:14.648556 <6>[ 1.768290] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6142 10:03:14.655083 <6>[ 1.774484] igb: Intel(R) Gigabit Ethernet Network Driver
6143 10:03:14.662284 <6>[ 1.780139] igb: Copyright (c) 2007-2014 Intel Corporation.
6144 10:03:14.668194 <6>[ 1.785982] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6145 10:03:14.675563 <6>[ 1.792505] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6146 10:03:14.678504 <6>[ 1.799057] sky2: driver version 1.30
6147 10:03:14.685444 <6>[ 1.804301] usbcore: registered new device driver r8152-cfgselector
6148 10:03:14.692341 <6>[ 1.810844] usbcore: registered new interface driver r8152
6149 10:03:14.698502 <6>[ 1.816675] VFIO - User Level meta-driver version: 0.3
6150 10:03:14.705282 <6>[ 1.824491] mtu3 11201000.usb: uwk - reg:0x420, version:101
6151 10:03:14.711832 <4>[ 1.830369] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6152 10:03:14.718339 <6>[ 1.837655] mtu3 11201000.usb: dr_mode: 1, drd: auto
6153 10:03:14.725420 <6>[ 1.842880] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6154 10:03:14.728305 <6>[ 1.849071] mtu3 11201000.usb: usb3-drd: 0
6155 10:03:14.734925 <6>[ 1.854661] mtu3 11201000.usb: xHCI platform device register success...
6156 10:03:14.746988 <4>[ 1.863302] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6157 10:03:14.750046 <6>[ 1.871237] xhci-mtk 11200000.usb: xHCI Host Controller
6158 10:03:14.760258 <6>[ 1.876741] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6159 10:03:14.766775 <6>[ 1.884459] xhci-mtk 11200000.usb: USB3 root hub has no ports
6160 10:03:14.772979 <6>[ 1.890468] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6161 10:03:14.779941 <6>[ 1.899913] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6162 10:03:14.786181 <6>[ 1.905981] xhci-mtk 11200000.usb: xHCI Host Controller
6163 10:03:14.792802 <6>[ 1.911469] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6164 10:03:14.799999 <6>[ 1.919127] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6165 10:03:14.806996 <6>[ 1.925937] hub 1-0:1.0: USB hub found
6166 10:03:14.810195 <6>[ 1.929966] hub 1-0:1.0: 1 port detected
6167 10:03:14.819845 <6>[ 1.935325] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6168 10:03:14.823040 <6>[ 1.943955] hub 2-0:1.0: USB hub found
6169 10:03:14.829853 <3>[ 1.948007] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6170 10:03:14.836093 <6>[ 1.955907] usbcore: registered new interface driver usb-storage
6171 10:03:14.843041 <6>[ 1.962516] usbcore: registered new device driver onboard-usb-hub
6172 10:03:14.857599 <4>[ 1.974155] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6173 10:03:14.866496 <6>[ 1.986425] mt6397-rtc mt6358-rtc: registered as rtc0
6174 10:03:14.876893 <6>[ 1.991905] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-18T10:02:16 UTC (1718704936)
6175 10:03:14.880016 <6>[ 2.001788] i2c_dev: i2c /dev entries driver
6176 10:03:14.891497 <6>[ 2.008197] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6177 10:03:14.901966 <6>[ 2.016538] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6178 10:03:14.904985 <6>[ 2.025446] i2c 4-0058: Fixed dependency cycle(s) with /panel
6179 10:03:14.914645 <6>[ 2.031476] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6180 10:03:14.921026 <3>[ 2.038933] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
6181 10:03:14.938718 <6>[ 2.058799] cpu cpu0: EM: created perf domain
6182 10:03:14.948785 <6>[ 2.064237] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6183 10:03:14.955772 <6>[ 2.075517] cpu cpu4: EM: created perf domain
6184 10:03:14.962241 <6>[ 2.082211] sdhci: Secure Digital Host Controller Interface driver
6185 10:03:14.968721 <6>[ 2.088663] sdhci: Copyright(c) Pierre Ossman
6186 10:03:14.976017 <6>[ 2.094073] Synopsys Designware Multimedia Card Interface Driver
6187 10:03:14.981967 <6>[ 2.094618] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6188 10:03:14.985602 <6>[ 2.101148] sdhci-pltfm: SDHCI platform and OF driver helper
6189 10:03:14.993716 <6>[ 2.113829] ledtrig-cpu: registered to indicate activity on CPUs
6190 10:03:15.001835 <6>[ 2.121589] usbcore: registered new interface driver usbhid
6191 10:03:15.005167 <6>[ 2.127435] usbhid: USB HID core driver
6192 10:03:15.015513 <6>[ 2.131753] spi_master spi2: will run message pump with realtime priority
6193 10:03:15.019596 <4>[ 2.131900] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6194 10:03:15.026996 <4>[ 2.146095] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6195 10:03:15.040228 <6>[ 2.151165] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6196 10:03:15.057703 <6>[ 2.167788] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6197 10:03:15.064358 <4>[ 2.177048] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6198 10:03:15.070967 <6>[ 2.188689] cros-ec-spi spi2.0: Chrome EC device registered
6199 10:03:15.078329 <4>[ 2.196613] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6200 10:03:15.091440 <4>[ 2.208187] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6201 10:03:15.098228 <4>[ 2.217334] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6202 10:03:15.111628 <6>[ 2.228071] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6203 10:03:15.117955 <6>[ 2.236098] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x13014
6204 10:03:15.124541 <6>[ 2.243747] mmc0: new HS400 MMC card at address 0001
6205 10:03:15.131213 <6>[ 2.250103] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6206 10:03:15.139219 <6>[ 2.259298] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6207 10:03:15.148896 <6>[ 2.268934] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6208 10:03:15.155807 <6>[ 2.275602] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6209 10:03:15.165585 <6>[ 2.278792] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6210 10:03:15.172233 <6>[ 2.281786] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6211 10:03:15.182380 <6>[ 2.293944] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6212 10:03:15.195241 <6>[ 2.299907] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6213 10:03:15.199151 <6>[ 2.308649] NET: Registered PF_PACKET protocol family
6214 10:03:15.208772 <6>[ 2.319236] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6215 10:03:15.212339 <6>[ 2.324415] 9pnet: Installing 9P2000 support
6216 10:03:15.218956 <5>[ 2.338961] Key type dns_resolver registered
6217 10:03:15.222391 <6>[ 2.344250] registered taskstats version 1
6218 10:03:15.228875 <5>[ 2.348620] Loading compiled-in X.509 certificates
6219 10:03:15.235239 <6>[ 2.354053] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6220 10:03:15.271059 <3>[ 2.387681] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6221 10:03:15.296235 <6>[ 2.409854] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6222 10:03:15.306299 <6>[ 2.423164] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6223 10:03:15.316214 <6>[ 2.431742] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6224 10:03:15.322720 <6>[ 2.440262] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6225 10:03:15.332514 <6>[ 2.448781] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6226 10:03:15.339296 <6>[ 2.457299] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6227 10:03:15.349295 <6>[ 2.465816] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6228 10:03:15.355744 <6>[ 2.474334] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6229 10:03:15.363638 <6>[ 2.483523] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6230 10:03:15.371235 <6>[ 2.491040] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6231 10:03:15.378473 <6>[ 2.498363] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6232 10:03:15.385038 <6>[ 2.505653] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6233 10:03:15.391981 <6>[ 2.510116] hub 1-1:1.0: USB hub found
6234 10:03:15.398259 <6>[ 2.513170] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6235 10:03:15.401771 <6>[ 2.516839] hub 1-1:1.0: 3 ports detected
6236 10:03:15.408540 <6>[ 2.524740] panfrost 13040000.gpu: clock rate = 511999970
6237 10:03:15.418488 <6>[ 2.533002] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6238 10:03:15.424943 <6>[ 2.542968] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6239 10:03:15.434951 <6>[ 2.550976] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6240 10:03:15.444936 <6>[ 2.559410] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6241 10:03:15.451412 <6>[ 2.571488] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6242 10:03:15.464066 <6>[ 2.581242] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6243 10:03:15.473853 <6>[ 2.590151] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6244 10:03:15.483965 <6>[ 2.599303] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6245 10:03:15.490758 <6>[ 2.608432] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6246 10:03:15.500616 <6>[ 2.617558] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6247 10:03:15.510329 <6>[ 2.626859] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6248 10:03:15.520704 <6>[ 2.636158] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6249 10:03:15.530623 <6>[ 2.645632] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6250 10:03:15.540113 <6>[ 2.655105] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6251 10:03:15.546930 <6>[ 2.664230] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6252 10:03:15.620538 <6>[ 2.737673] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6253 10:03:15.630248 <6>[ 2.746577] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6254 10:03:15.641326 <6>[ 2.758479] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6255 10:03:15.700828 <6>[ 2.818201] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6256 10:03:16.327542 <6>[ 3.002391] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6257 10:03:16.337733 <4>[ 3.105758] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6258 10:03:16.344055 <4>[ 3.105778] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6259 10:03:16.351030 <6>[ 3.143037] r8152 1-1.2:1.0 eth0: v1.12.13
6260 10:03:16.357246 <6>[ 3.222067] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6261 10:03:16.364120 <6>[ 3.427772] Console: switching to colour frame buffer device 170x48
6262 10:03:16.370387 <6>[ 3.488421] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6263 10:03:16.392195 <6>[ 3.505728] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6264 10:03:16.409851 <6>[ 3.523139] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6265 10:03:16.419868 <6>[ 3.535718] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6266 10:03:16.426278 <6>[ 3.544186] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6267 10:03:16.436472 <6>[ 3.551595] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6268 10:03:16.456682 <6>[ 3.570343] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6269 10:03:17.786393 <6>[ 4.906568] r8152 1-1.2:1.0 eth0: carrier on
6270 10:03:17.830102 <5>[ 4.934070] Sending DHCP requests ., OK
6271 10:03:17.836631 <6>[ 4.954451] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.13
6272 10:03:17.840242 <6>[ 4.962883] IP-Config: Complete:
6273 10:03:17.853216 <6>[ 4.966476] device=eth0, hwaddr=00:e0:4c:68:0b:b9, ipaddr=192.168.201.13, mask=255.255.255.0, gw=192.168.201.1
6274 10:03:17.863057 <6>[ 4.977377] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0, domain=lava-rack, nis-domain=(none)
6275 10:03:17.874737 <6>[ 4.991650] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6276 10:03:17.883373 <6>[ 4.991660] nameserver0=192.168.201.1
6277 10:03:17.891294 <6>[ 5.011432] clk: Disabling unused clocks
6278 10:03:17.895879 <6>[ 5.019380] ALSA device list:
6279 10:03:17.905112 <6>[ 5.025411] No soundcards found.
6280 10:03:17.914470 <6>[ 5.034377] Freeing unused kernel memory: 8512K
6281 10:03:17.921135 <6>[ 5.041430] Run /init as init process
6282 10:03:17.933245 Loading, please wait...
6283 10:03:17.967352 Starting systemd-udevd version 252.22-1~deb12u1
6284 10:03:18.286488 <3>[ 5.406473] thermal_sys: Failed to find 'trips' node
6285 10:03:18.296850 <3>[ 5.413567] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6286 10:03:18.307119 <3>[ 5.422796] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6287 10:03:18.313472 <6>[ 5.423216] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6288 10:03:18.323326 <4>[ 5.431243] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6289 10:03:18.330165 <4>[ 5.447626] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6290 10:03:18.336513 <3>[ 5.448897] mtk-scp 10500000.scp: invalid resource
6291 10:03:18.339989 <3>[ 5.451287] thermal_sys: Failed to find 'trips' node
6292 10:03:18.350028 <3>[ 5.451293] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6293 10:03:18.360379 <3>[ 5.451302] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6294 10:03:18.367056 <4>[ 5.451306] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6295 10:03:18.377265 <4>[ 5.454509] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6296 10:03:18.386587 <6>[ 5.455152] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6297 10:03:18.396661 <4>[ 5.456107] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6298 10:03:18.406763 <3>[ 5.457240] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6299 10:03:18.413039 <3>[ 5.457248] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6300 10:03:18.426445 <3>[ 5.457251] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6301 10:03:18.433270 <3>[ 5.457256] elan_i2c 2-0015: Error applying setting, reverse things back
6302 10:03:18.443079 <6>[ 5.458408] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6303 10:03:18.449888 <6>[ 5.461149] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6304 10:03:18.459713 <6>[ 5.462355] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6305 10:03:18.466118 <3>[ 5.477750] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6306 10:03:18.479449 <3>[ 5.485646] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6307 10:03:18.486003 <3>[ 5.491536] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6308 10:03:18.493675 <6>[ 5.498290] mc: Linux media interface: v0.10
6309 10:03:18.496994 <6>[ 5.498529] remoteproc remoteproc0: scp is available
6310 10:03:18.507821 <4>[ 5.499399] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6311 10:03:18.514085 <6>[ 5.499410] remoteproc remoteproc0: powering up scp
6312 10:03:18.520591 <4>[ 5.499429] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6313 10:03:18.527124 <3>[ 5.499433] remoteproc remoteproc0: request_firmware failed: -2
6314 10:03:18.538425 <6>[ 5.523954] cs_system_cfg: CoreSight Configuration manager initialised
6315 10:03:18.548954 <3>[ 5.532567] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6316 10:03:18.551995 <6>[ 5.547001] videodev: Linux video capture interface: v2.00
6317 10:03:18.561962 <5>[ 5.552456] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6318 10:03:18.568493 <3>[ 5.558435] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6319 10:03:18.578394 <6>[ 5.559435] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6320 10:03:18.585443 <6>[ 5.559547] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6321 10:03:18.591972 <6>[ 5.559646] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6322 10:03:18.602315 <6>[ 5.559728] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6323 10:03:18.612590 Begin: Loading e<6>[ 5.559822] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6324 10:03:18.619008 ssential drivers<6>[ 5.568130] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6325 10:03:18.628656 <3>[ 5.575914] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6326 10:03:18.629164 ... done.
6327 10:03:18.635543 Begi<5>[ 5.580230] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6328 10:03:18.645235 n: Running /scri<5>[ 5.580713] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6329 10:03:18.655673 pts/init-premoun<4>[ 5.580798] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6330 10:03:18.658752 t ... done.
6331 10:03:18.662319 Beg<6>[ 5.580808] cfg80211: failed to load regulatory.db
6332 10:03:18.672197 in: Mounting roo<6>[ 5.583639] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6333 10:03:18.682134 t file system ..<3>[ 5.591953] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6334 10:03:18.691933 . Begin: Running<6>[ 5.598183] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6335 10:03:18.701370 /scripts/nfs-to<6>[ 5.612976] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6336 10:03:18.704927 p ... done.
6337 10:03:18.708646 Beg<6>[ 5.613511] Bluetooth: Core ver 2.22
6338 10:03:18.714874 in: Running /scr<6>[ 5.613563] NET: Registered PF_BLUETOOTH protocol family
6339 10:03:18.721261 ipts/nfs-premoun<6>[ 5.613565] Bluetooth: HCI device and connection manager initialized
6340 10:03:18.728117 t ... Waiting up<6>[ 5.613577] Bluetooth: HCI socket layer initialized
6341 10:03:18.735992 <6>[ 5.613583] Bluetooth: L2CAP socket layer initialized
6342 10:03:18.742470 to 60 secs for <6>[ 5.613590] Bluetooth: SCO socket layer initialized
6343 10:03:18.752278 any ethernet to <3>[ 5.613782] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6344 10:03:18.759301 become available<6>[ 5.635384] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6345 10:03:18.759883
6346 10:03:18.768614 Device /sys/cl<3>[ 5.638919] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6347 10:03:18.775112 ass/net/eth0 fou<6>[ 5.639223] Bluetooth: HCI UART driver ver 2.3
6348 10:03:18.775567 nd
6349 10:03:18.775912 done.
6350 10:03:18.782640 Begin<6>[ 5.639229] Bluetooth: HCI UART protocol H4 registered
6351 10:03:18.789598 : Waiting up to <6>[ 5.639278] Bluetooth: HCI UART protocol LL registered
6352 10:03:18.796861 180 secs for any<6>[ 5.639292] Bluetooth: HCI UART protocol Three-wire (H5) registered
6353 10:03:18.802589 network device <6>[ 5.639665] Bluetooth: HCI UART protocol Broadcom registered
6354 10:03:18.809197 to become availa<6>[ 5.639687] Bluetooth: HCI UART protocol QCA registered
6355 10:03:18.812351 ble ... done.
6356 10:03:18.819327 I<6>[ 5.639700] Bluetooth: HCI UART protocol Marvell registered
6357 10:03:18.825811 P-Config: eth0 h<6>[ 5.639773] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6358 10:03:18.832082 ardware address <6>[ 5.639829] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6359 10:03:18.841977 00:e0:4c:68:0b:b<6>[ 5.640378] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6360 10:03:18.845649 9 mtu 1500 DHCP
6361 10:03:18.848647 <6>[ 5.640559] Bluetooth: hci0: setting up ROME/QCA6390
6362 10:03:18.848763
6363 10:03:18.858633 IP-Config: eth0<6>[ 5.640767] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6364 10:03:18.871960 complete (dhcp <6>[ 5.665420] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6365 10:03:18.881286 from 192.168.201<3>[ 5.672539] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6366 10:03:18.881381 .1):
6367 10:03:18.888246 address: <6>[ 5.678503] usbcore: registered new interface driver uvcvideo
6368 10:03:18.901531 192.168.201.13 <3>[ 5.686536] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6369 10:03:18.914387 broadcast: 192.<6>[ 5.696850] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6370 10:03:18.921279 168.201.255 net<3>[ 5.703704] debugfs: File 'Playback' in directory 'dapm' already present!
6371 10:03:18.931169 mask: 255.255.25<6>[ 5.710498] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6372 10:03:18.931262 5.0
6373 10:03:18.941185 gateway<3>[ 5.718521] debugfs: File 'Capture' in directory 'dapm' already present!
6374 10:03:18.954013 : 192.168.201.1 <6>[ 5.726528] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6375 10:03:18.963993 dns0 : 19<6>[ 5.739726] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6376 10:03:18.974242 2.168.201.1 d<4>[ 5.833107] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6377 10:03:18.980551 <4>[ 5.833107] Fallback method does not support PEC.
6378 10:03:18.987429 ns1 : 0.0.0.0 <3>[ 5.853490] Bluetooth: hci0: Frame reassembly failed (-84)
6379 10:03:18.987523
6380 10:03:18.997473 host <3>[ 5.857071] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6381 10:03:19.007055 : mt8183-kukui<6>[ 5.896458] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6382 10:03:19.010651 -jacuzzi-juniper-sku16-cbg-0
6383 10:03:19.020302 domain : <3>[ 5.906859] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6384 10:03:19.030454 lava-rack <6>[ 6.118376] Bluetooth: hci0: QCA Product ID :0x00000008
6385 10:03:19.030632
6386 10:03:19.033818 rootserver: 192.168.201.1 rootpath:
6387 10:03:19.036976 filename :
6388 10:03:19.037178 done.
6389 10:03:19.040533 Begin: Running /scripts/nfs-bottom ... done.
6390 10:03:19.043908 Begin: Running /scripts/init-bottom ... done.
6391 10:03:19.109448 <6>[ 6.229009] Bluetooth: hci0: QCA SOC Version :0x00000044
6392 10:03:19.115761 <6>[ 6.235487] Bluetooth: hci0: QCA ROM Version :0x00000302
6393 10:03:19.122811 <6>[ 6.241867] Bluetooth: hci0: QCA Patch Version:0x00000111
6394 10:03:19.128952 <6>[ 6.241873] Bluetooth: hci0: QCA controller version 0x00440302
6395 10:03:19.135857 <6>[ 6.241876] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6396 10:03:19.145512 <4>[ 6.241926] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6397 10:03:19.156056 <6>[ 6.271903] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6398 10:03:19.165594 <3>[ 6.272327] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6399 10:03:19.171794 <3>[ 6.291543] Bluetooth: hci0: QCA Failed to download patch (-2)
6400 10:03:19.234503 <4>[ 6.351293] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6401 10:03:19.252953 <4>[ 6.369496] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6402 10:03:19.265515 <4>[ 6.382164] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6403 10:03:19.273270 <4>[ 6.393317] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6404 10:03:20.510144 <6>[ 7.629966] NET: Registered PF_INET6 protocol family
6405 10:03:20.522480 <6>[ 7.642140] Segment Routing with IPv6
6406 10:03:20.530162 <6>[ 7.650438] In-situ OAM (IOAM) with IPv6
6407 10:03:20.708972 <30>[ 7.799057] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6408 10:03:20.726339 <30>[ 7.846507] systemd[1]: Detected architecture arm64.
6409 10:03:20.738518
6410 10:03:20.742228 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6411 10:03:20.742759
6412 10:03:20.767356 <30>[ 7.887249] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6413 10:03:21.903158 <30>[ 9.019811] systemd[1]: Queued start job for default target graphical.target.
6414 10:03:21.938306 <30>[ 9.055335] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6415 10:03:21.951904 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6416 10:03:21.971211 <30>[ 9.088289] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6417 10:03:21.985108 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6418 10:03:22.003468 <30>[ 9.120403] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6419 10:03:22.018272 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6420 10:03:22.038736 <30>[ 9.155662] systemd[1]: Created slice user.slice - User and Session Slice.
6421 10:03:22.051387 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6422 10:03:22.073153 <30>[ 9.186631] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6423 10:03:22.086663 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6424 10:03:22.109224 <30>[ 9.222466] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6425 10:03:22.122077 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6426 10:03:22.147748 <30>[ 9.254433] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6427 10:03:22.166926 <30>[ 9.283935] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6428 10:03:22.175393 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6429 10:03:22.193531 <30>[ 9.310241] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6430 10:03:22.206410 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6431 10:03:22.225738 <30>[ 9.342288] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6432 10:03:22.240230 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6433 10:03:22.254421 <30>[ 9.374317] systemd[1]: Reached target paths.target - Path Units.
6434 10:03:22.268886 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6435 10:03:22.285517 <30>[ 9.402237] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6436 10:03:22.297907 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6437 10:03:22.310445 <30>[ 9.430210] systemd[1]: Reached target slices.target - Slice Units.
6438 10:03:22.324973 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6439 10:03:22.338645 <30>[ 9.458257] systemd[1]: Reached target swap.target - Swaps.
6440 10:03:22.349126 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6441 10:03:22.369589 <30>[ 9.486305] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6442 10:03:22.383027 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6443 10:03:22.402264 <30>[ 9.518606] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6444 10:03:22.416075 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6445 10:03:22.437394 <30>[ 9.553835] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6446 10:03:22.450459 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6447 10:03:22.471238 <30>[ 9.588100] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6448 10:03:22.485837 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6449 10:03:22.502397 <30>[ 9.619044] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6450 10:03:22.514440 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6451 10:03:22.535622 <30>[ 9.651982] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6452 10:03:22.548980 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6453 10:03:22.569068 <30>[ 9.685623] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6454 10:03:22.582537 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6455 10:03:22.602535 <30>[ 9.718849] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6456 10:03:22.615371 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6457 10:03:22.657543 <30>[ 9.774433] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6458 10:03:22.669728 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6459 10:03:22.691275 <30>[ 9.808053] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6460 10:03:22.704607 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6461 10:03:22.725453 <30>[ 9.842078] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6462 10:03:22.736650 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6463 10:03:22.760383 <30>[ 9.870653] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6464 10:03:22.798191 <30>[ 9.915234] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6465 10:03:22.810942 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6466 10:03:22.835752 <30>[ 9.952557] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6467 10:03:22.847099 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6468 10:03:22.869001 <30>[ 9.985837] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6469 10:03:22.880944 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6470 10:03:22.902606 <30>[ 10.019400] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6471 10:03:22.917351 Starting [0;1;39mmodpr<6>[ 10.032704] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6472 10:03:22.920833 obe@drm.service[0m - Load Kernel Module drm...
6473 10:03:22.966684 <30>[ 10.083548] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6474 10:03:22.979057 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6475 10:03:23.002919 <30>[ 10.119402] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6476 10:03:23.013744 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6477 10:03:23.033524 <30>[ 10.150440] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6478 10:03:23.045458 Starting [0;1;39mmodprobe@loop.ser…e<6>[ 10.165986] fuse: init (API version 7.37)
6479 10:03:23.048902 [0m - Load Kernel Module loop...
6480 10:03:23.072393 <30>[ 10.189152] systemd[1]: Starting systemd-journald.service - Journal Service...
6481 10:03:23.084525 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6482 10:03:23.150009 <30>[ 10.266741] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6483 10:03:23.161318 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6484 10:03:23.186679 <30>[ 10.300006] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6485 10:03:23.197352 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6486 10:03:23.217380 <30>[ 10.333785] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6487 10:03:23.235561 Starting [0;1;39msystemd-remount-f…nt Root and Kerne<3>[ 10.353197] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6488 10:03:23.238836 l File Systems...
6489 10:03:23.254660 <3>[ 10.371370] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6490 10:03:23.277450 <3>[ 10.393585] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6491 10:03:23.293873 <3>[ 10.409655] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6492 10:03:23.301447 <30>[ 10.411311] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6493 10:03:23.310987 <3>[ 10.424209] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6494 10:03:23.324678 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6495 10:03:23.330965 <3>[ 10.447751] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6496 10:03:23.349216 <3>[ 10.465166] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6497 10:03:23.356569 <30>[ 10.467564] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6498 10:03:23.363094 <3>[ 10.479936] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6499 10:03:23.380992 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6500 10:03:23.398516 <30>[ 10.515133] systemd[1]: Started systemd-journald.service - Journal Service.
6501 10:03:23.410285 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6502 10:03:23.438279 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
6503 10:03:23.459843 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6504 10:03:23.483169 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6505 10:03:23.507810 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6506 10:03:23.527887 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6507 10:03:23.553094 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6508 10:03:23.572448 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6509 10:03:23.593030 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6510 10:03:23.612224 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6511 10:03:23.631781 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6512 10:03:23.651353 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6513 10:03:23.671213 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6514 10:03:23.692942 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6515 10:03:23.742089 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6516 10:03:23.766862 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6517 10:03:23.791273 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6518 10:03:23.800888 <4>[ 10.920729] power_supply_show_property: 2 callbacks suppressed
6519 10:03:23.812302 <3>[ 10.920739] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6520 10:03:23.818699 <3>[ 10.934321] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6521 10:03:23.836053 <4>[ 10.935805] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6522 10:03:23.842349 <3>[ 10.950746] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6523 10:03:23.856283 <3>[ 10.960368] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6524 10:03:23.894091 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed..<3>[ 11.009424] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6525 10:03:23.894512 .
6526 10:03:23.912643 <3>[ 11.029364] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6527 10:03:23.930918 <3>[ 11.046986] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6528 10:03:23.947541 <3>[ 11.064100] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6529 10:03:23.965107 <3>[ 11.081690] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6530 10:03:23.973376 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6531 10:03:23.982913 <3>[ 11.099392] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6532 10:03:24.001768 Startin<3>[ 11.118106] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6533 10:03:24.011316 g [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6534 10:03:24.026853 <46>[ 11.143668] systemd-journald[317]: Received client request to flush runtime journal.
6535 10:03:24.046451 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6536 10:03:24.067135 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6537 10:03:24.087005 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6538 10:03:24.109679 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6539 10:03:24.129501 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6540 10:03:24.816313 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6541 10:03:24.858886 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6542 10:03:25.496309 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6543 10:03:25.531096 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6544 10:03:25.550609 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6545 10:03:25.570087 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6546 10:03:25.614493 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6547 10:03:25.639805 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6548 10:03:25.904466 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6549 10:03:25.977573 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6550 10:03:25.994848 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6551 10:03:26.061716 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6552 10:03:26.261236 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6553 10:03:26.277081 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6554 10:03:26.337936 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6555 10:03:26.394498 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6556 10:03:26.420964 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6557 10:03:26.464376 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6558 10:03:26.542691 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6559 10:03:26.564325 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6560 10:03:26.615174 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6561 10:03:26.669771 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6562 10:03:26.714676 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6563 10:03:26.738290 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6564 10:03:26.761231 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6565 10:03:26.783034 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6566 10:03:26.803586 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6567 10:03:26.824905 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6568 10:03:26.845252 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6569 10:03:26.865235 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6570 10:03:26.880235 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6571 10:03:26.898060 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6572 10:03:26.914005 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6573 10:03:26.937225 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6574 10:03:26.957199 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6575 10:03:26.973740 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6576 10:03:26.993159 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6577 10:03:27.012917 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6578 10:03:27.029948 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6579 10:03:27.045702 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6580 10:03:27.065783 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6581 10:03:27.081942 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6582 10:03:27.098188 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6583 10:03:27.143604 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6584 10:03:27.164534 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6585 10:03:27.236554 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6586 10:03:27.281221 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6587 10:03:27.339655 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6588 10:03:27.360432 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6589 10:03:27.378632 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6590 10:03:27.468714 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6591 10:03:27.518873 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6592 10:03:27.538355 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6593 10:03:27.558721 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6594 10:03:27.596559 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6595 10:03:27.637065 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6596 10:03:27.661155 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6597 10:03:27.680397 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6598 10:03:27.699692 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6599 10:03:27.749220 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6600 10:03:27.814206 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6601 10:03:27.909951
6602 10:03:27.913216 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6603 10:03:27.913639
6604 10:03:27.916686 debian-bookworm-arm64 login: root (automatic login)
6605 10:03:27.917108
6606 10:03:28.237774 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
6607 10:03:28.238294
6608 10:03:28.244488 The programs included with the Debian GNU/Linux system are free software;
6609 10:03:28.251227 the exact distribution terms for each program are described in the
6610 10:03:28.254645 individual files in /usr/share/doc/*/copyright.
6611 10:03:28.255067
6612 10:03:28.261116 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6613 10:03:28.264029 permitted by applicable law.
6614 10:03:29.391261 Matched prompt #10: / #
6616 10:03:29.392452 Setting prompt string to ['/ #']
6617 10:03:29.392886 end: 2.2.5.1 login-action (duration 00:00:17) [common]
6619 10:03:29.393852 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
6620 10:03:29.394307 start: 2.2.6 expect-shell-connection (timeout 00:03:47) [common]
6621 10:03:29.394674 Setting prompt string to ['/ #']
6622 10:03:29.394983 Forcing a shell prompt, looking for ['/ #']
6624 10:03:29.445792 / #
6625 10:03:29.446238 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6626 10:03:29.446600 Waiting using forced prompt support (timeout 00:02:30)
6627 10:03:29.451705
6628 10:03:29.452386 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6629 10:03:29.452782 start: 2.2.7 export-device-env (timeout 00:03:47) [common]
6631 10:03:29.554093 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407643/extract-nfsrootfs-ypalcua5'
6632 10:03:29.560523 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407643/extract-nfsrootfs-ypalcua5'
6634 10:03:29.662075 / # export NFS_SERVER_IP='192.168.201.1'
6635 10:03:29.668850 export NFS_SERVER_IP='192.168.201.1'
6636 10:03:29.669776 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6637 10:03:29.670316 end: 2.2 depthcharge-retry (duration 00:01:14) [common]
6638 10:03:29.670803 end: 2 depthcharge-action (duration 00:01:14) [common]
6639 10:03:29.671313 start: 3 lava-test-retry (timeout 00:08:04) [common]
6640 10:03:29.671844 start: 3.1 lava-test-shell (timeout 00:08:04) [common]
6641 10:03:29.672264 Using namespace: common
6643 10:03:29.773692 / # #
6644 10:03:29.774353 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6645 10:03:29.780185 #
6646 10:03:29.781051 Using /lava-14407643
6648 10:03:29.882268 / # export SHELL=/bin/bash
6649 10:03:29.888688 export SHELL=/bin/bash
6651 10:03:29.990401 / # . /lava-14407643/environment
6652 10:03:29.996892 . /lava-14407643/environment
6654 10:03:30.104935 / # /lava-14407643/bin/lava-test-runner /lava-14407643/0
6655 10:03:30.105589 Test shell timeout: 10s (minimum of the action and connection timeout)
6656 10:03:30.110796 /lava-14407643/bin/lava-test-runner /lava-14407643/0
6657 10:03:30.365186 + export TESTRUN_ID=0_timesync-off
6658 10:03:30.368571 + TESTRUN_ID=0_timesync-off
6659 10:03:30.371632 + cd /lava-14407643/0/tests/0_timesync-off
6660 10:03:30.375063 ++ cat uuid
6661 10:03:30.378264 + UUID=14407643_1.6.2.3.1
6662 10:03:30.378686 + set +x
6663 10:03:30.384675 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14407643_1.6.2.3.1>
6664 10:03:30.385370 Received signal: <STARTRUN> 0_timesync-off 14407643_1.6.2.3.1
6665 10:03:30.385743 Starting test lava.0_timesync-off (14407643_1.6.2.3.1)
6666 10:03:30.386174 Skipping test definition patterns.
6667 10:03:30.388057 + systemctl stop systemd-timesyncd
6668 10:03:30.469720 + set +x
6669 10:03:30.473244 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14407643_1.6.2.3.1>
6670 10:03:30.473919 Received signal: <ENDRUN> 0_timesync-off 14407643_1.6.2.3.1
6671 10:03:30.474317 Ending use of test pattern.
6672 10:03:30.474635 Ending test lava.0_timesync-off (14407643_1.6.2.3.1), duration 0.09
6674 10:03:30.548791 + export TESTRUN_ID=1_kselftest-arm64
6675 10:03:30.549379 + TESTRUN_ID=1_kselftest-arm64
6676 10:03:30.555535 + cd /lava-14407643/0/tests/1_kselftest-arm64
6677 10:03:30.556055 ++ cat uuid
6678 10:03:30.563863 + UUID=14407643_1.6.2.3.5
6679 10:03:30.564281 + set +x
6680 10:03:30.570704 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14407643_1.6.2.3.5>
6681 10:03:30.571521 Received signal: <STARTRUN> 1_kselftest-arm64 14407643_1.6.2.3.5
6682 10:03:30.571941 Starting test lava.1_kselftest-arm64 (14407643_1.6.2.3.5)
6683 10:03:30.572354 Skipping test definition patterns.
6684 10:03:30.573740 + cd ./automated/linux/kselftest/
6685 10:03:30.600574 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
6686 10:03:30.659215 INFO: install_deps skipped
6687 10:03:31.166972 --2024-06-18 10:02:32-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
6688 10:03:31.194110 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6689 10:03:31.318445 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6690 10:03:31.443036 HTTP request sent, awaiting response... 200 OK
6691 10:03:31.446179 Length: 1642672 (1.6M) [application/octet-stream]
6692 10:03:31.449859 Saving to: 'kselftest_armhf.tar.gz'
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6700 10:03:32.369028
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6702 10:03:32.512727
6703 10:03:36.755579 skiplist:
6704 10:03:36.758625 ========================================
6705 10:03:36.762126 ========================================
6706 10:03:36.817500 arm64:tags_test
6707 10:03:36.820794 arm64:run_tags_test.sh
6708 10:03:36.821214 arm64:fake_sigreturn_bad_magic
6709 10:03:36.823980 arm64:fake_sigreturn_bad_size
6710 10:03:36.827283 arm64:fake_sigreturn_bad_size_for_magic0
6711 10:03:36.830719 arm64:fake_sigreturn_duplicated_fpsimd
6712 10:03:36.834248 arm64:fake_sigreturn_misaligned_sp
6713 10:03:36.837317 arm64:fake_sigreturn_missing_fpsimd
6714 10:03:36.840791 arm64:fake_sigreturn_sme_change_vl
6715 10:03:36.843818 arm64:fake_sigreturn_sve_change_vl
6716 10:03:36.847470 arm64:mangle_pstate_invalid_compat_toggle
6717 10:03:36.850670 arm64:mangle_pstate_invalid_daif_bits
6718 10:03:36.853817 arm64:mangle_pstate_invalid_mode_el1h
6719 10:03:36.857531 arm64:mangle_pstate_invalid_mode_el1t
6720 10:03:36.860948 arm64:mangle_pstate_invalid_mode_el2h
6721 10:03:36.863957 arm64:mangle_pstate_invalid_mode_el2t
6722 10:03:36.867042 arm64:mangle_pstate_invalid_mode_el3h
6723 10:03:36.870908 arm64:mangle_pstate_invalid_mode_el3t
6724 10:03:36.874190 arm64:sme_trap_no_sm
6725 10:03:36.877372 arm64:sme_trap_non_streaming
6726 10:03:36.877880 arm64:sme_trap_za
6727 10:03:36.880689 arm64:sme_vl
6728 10:03:36.881256 arm64:ssve_regs
6729 10:03:36.883726 arm64:sve_regs
6730 10:03:36.884146 arm64:sve_vl
6731 10:03:36.884477 arm64:za_no_regs
6732 10:03:36.887319 arm64:za_regs
6733 10:03:36.887814 arm64:pac
6734 10:03:36.888193 arm64:fp-stress
6735 10:03:36.890644 arm64:sve-ptrace
6736 10:03:36.891150 arm64:sve-probe-vls
6737 10:03:36.893624 arm64:vec-syscfg
6738 10:03:36.894040 arm64:za-fork
6739 10:03:36.897108 arm64:za-ptrace
6740 10:03:36.897549 arm64:check_buffer_fill
6741 10:03:36.900659 arm64:check_child_memory
6742 10:03:36.903841 arm64:check_gcr_el1_cswitch
6743 10:03:36.907238 arm64:check_ksm_options
6744 10:03:36.907723 arm64:check_mmap_options
6745 10:03:36.910645 arm64:check_prctl
6746 10:03:36.914289 arm64:check_tags_inclusion
6747 10:03:36.914733 arm64:check_user_mem
6748 10:03:36.917653 arm64:btitest
6749 10:03:36.918073 arm64:nobtitest
6750 10:03:36.918448 arm64:hwcap
6751 10:03:36.920536 arm64:ptrace
6752 10:03:36.920955 arm64:syscall-abi
6753 10:03:36.923644 arm64:tpidr2
6754 10:03:36.927038 ============== Tests to run ===============
6755 10:03:36.927548 arm64:tags_test
6756 10:03:36.930492 arm64:run_tags_test.sh
6757 10:03:36.933560 arm64:fake_sigreturn_bad_magic
6758 10:03:36.937242 arm64:fake_sigreturn_bad_size
6759 10:03:36.940205 arm64:fake_sigreturn_bad_size_for_magic0
6760 10:03:36.943918 arm64:fake_sigreturn_duplicated_fpsimd
6761 10:03:36.946952 arm64:fake_sigreturn_misaligned_sp
6762 10:03:36.950406 arm64:fake_sigreturn_missing_fpsimd
6763 10:03:36.953894 arm64:fake_sigreturn_sme_change_vl
6764 10:03:36.954317 arm64:fake_sigreturn_sve_change_vl
6765 10:03:36.960602 arm64:mangle_pstate_invalid_compat_toggle
6766 10:03:36.964115 arm64:mangle_pstate_invalid_daif_bits
6767 10:03:36.967311 arm64:mangle_pstate_invalid_mode_el1h
6768 10:03:36.970767 arm64:mangle_pstate_invalid_mode_el1t
6769 10:03:36.973741 arm64:mangle_pstate_invalid_mode_el2h
6770 10:03:36.976655 arm64:mangle_pstate_invalid_mode_el2t
6771 10:03:36.980323 arm64:mangle_pstate_invalid_mode_el3h
6772 10:03:36.983566 arm64:mangle_pstate_invalid_mode_el3t
6773 10:03:36.983978 arm64:sme_trap_no_sm
6774 10:03:36.986949 arm64:sme_trap_non_streaming
6775 10:03:36.990166 arm64:sme_trap_za
6776 10:03:36.990575 arm64:sme_vl
6777 10:03:36.990898 arm64:ssve_regs
6778 10:03:36.993575 arm64:sve_regs
6779 10:03:36.993984 arm64:sve_vl
6780 10:03:36.996887 arm64:za_no_regs
6781 10:03:36.997295 arm64:za_regs
6782 10:03:36.997623 arm64:pac
6783 10:03:37.000146 arm64:fp-stress
6784 10:03:37.000559 arm64:sve-ptrace
6785 10:03:37.003321 arm64:sve-probe-vls
6786 10:03:37.003764 arm64:vec-syscfg
6787 10:03:37.007050 arm64:za-fork
6788 10:03:37.007519 arm64:za-ptrace
6789 10:03:37.010199 arm64:check_buffer_fill
6790 10:03:37.010656 arm64:check_child_memory
6791 10:03:37.013570 arm64:check_gcr_el1_cswitch
6792 10:03:37.016714 arm64:check_ksm_options
6793 10:03:37.020245 arm64:check_mmap_options
6794 10:03:37.020682 arm64:check_prctl
6795 10:03:37.023278 arm64:check_tags_inclusion
6796 10:03:37.023793 arm64:check_user_mem
6797 10:03:37.026816 arm64:btitest
6798 10:03:37.027248 arm64:nobtitest
6799 10:03:37.029891 arm64:hwcap
6800 10:03:37.030323 arm64:ptrace
6801 10:03:37.030788 arm64:syscall-abi
6802 10:03:37.033395 arm64:tpidr2
6803 10:03:37.036353 ===========End Tests to run ===============
6804 10:03:37.039951 shardfile-arm64 pass
6805 10:03:37.338874 <12>[ 24.458395] kselftest: Running tests in arm64
6806 10:03:37.350151 TAP version 13
6807 10:03:37.364829 1..48
6808 10:03:37.386068 # selftests: arm64: tags_test
6809 10:03:37.854232 ok 1 selftests: arm64: tags_test
6810 10:03:37.873664 # selftests: arm64: run_tags_test.sh
6811 10:03:37.947543 # --------------------
6812 10:03:37.950362 # running tags test
6813 10:03:37.950814 # --------------------
6814 10:03:37.954088 # [PASS]
6815 10:03:37.956853 ok 2 selftests: arm64: run_tags_test.sh
6816 10:03:37.972084 # selftests: arm64: fake_sigreturn_bad_magic
6817 10:03:38.064707 # Registered handlers for all signals.
6818 10:03:38.065279 # Detected MINSTKSIGSZ:4720
6819 10:03:38.067985 # Testcase initialized.
6820 10:03:38.071252 # uc context validated.
6821 10:03:38.074321 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6822 10:03:38.077564 # Handled SIG_COPYCTX
6823 10:03:38.078038 # Available space:3568
6824 10:03:38.084187 # Using badly built context - ERR: BAD MAGIC !
6825 10:03:38.091039 # SIG_OK -- SP:0xFFFFF95D3820 si_addr@:0xfffff95d3820 si_code:2 token@:0xfffff95d25c0 offset:-4704
6826 10:03:38.094487 # ==>> completed. PASS(1)
6827 10:03:38.101200 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
6828 10:03:38.107853 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF95D25C0
6829 10:03:38.110889 ok 3 selftests: arm64: fake_sigreturn_bad_magic
6830 10:03:38.117448 # selftests: arm64: fake_sigreturn_bad_size
6831 10:03:38.171795 # Registered handlers for all signals.
6832 10:03:38.172353 # Detected MINSTKSIGSZ:4720
6833 10:03:38.175119 # Testcase initialized.
6834 10:03:38.178029 # uc context validated.
6835 10:03:38.181231 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6836 10:03:38.185077 # Handled SIG_COPYCTX
6837 10:03:38.185486 # Available space:3568
6838 10:03:38.188074 # uc context validated.
6839 10:03:38.194433 # Using badly built context - ERR: Bad size for esr_context
6840 10:03:38.201130 # SIG_OK -- SP:0xFFFFC751F170 si_addr@:0xffffc751f170 si_code:2 token@:0xffffc751df10 offset:-4704
6841 10:03:38.204400 # ==>> completed. PASS(1)
6842 10:03:38.211253 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
6843 10:03:38.217557 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC751DF10
6844 10:03:38.221435 ok 4 selftests: arm64: fake_sigreturn_bad_size
6845 10:03:38.227761 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
6846 10:03:38.282494 # Registered handlers for all signals.
6847 10:03:38.283084 # Detected MINSTKSIGSZ:4720
6848 10:03:38.286522 # Testcase initialized.
6849 10:03:38.289688 # uc context validated.
6850 10:03:38.292963 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6851 10:03:38.296009 # Handled SIG_COPYCTX
6852 10:03:38.296423 # Available space:3568
6853 10:03:38.302490 # Using badly built context - ERR: Bad size for terminator
6854 10:03:38.312676 # SIG_OK -- SP:0xFFFFFBB3A1D0 si_addr@:0xfffffbb3a1d0 si_code:2 token@:0xfffffbb38f70 offset:-4704
6855 10:03:38.313096 # ==>> completed. PASS(1)
6856 10:03:38.322559 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
6857 10:03:38.329390 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFBB38F70
6858 10:03:38.332654 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
6859 10:03:38.338972 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
6860 10:03:38.376373 # Registered handlers for all signals.
6861 10:03:38.376892 # Detected MINSTKSIGSZ:4720
6862 10:03:38.379441 # Testcase initialized.
6863 10:03:38.382444 # uc context validated.
6864 10:03:38.386067 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6865 10:03:38.389360 # Handled SIG_COPYCTX
6866 10:03:38.389877 # Available space:3568
6867 10:03:38.395996 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
6868 10:03:38.405941 # SIG_OK -- SP:0xFFFFD2774380 si_addr@:0xffffd2774380 si_code:2 token@:0xffffd2773120 offset:-4704
6869 10:03:38.406569 # ==>> completed. PASS(1)
6870 10:03:38.415392 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
6871 10:03:38.422661 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD2773120
6872 10:03:38.425919 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
6873 10:03:38.428982 # selftests: arm64: fake_sigreturn_misaligned_sp
6874 10:03:38.442918 # Registered handlers for all signals.
6875 10:03:38.443385 # Detected MINSTKSIGSZ:4720
6876 10:03:38.446539 # Testcase initialized.
6877 10:03:38.449578 # uc context validated.
6878 10:03:38.453054 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6879 10:03:38.456142 # Handled SIG_COPYCTX
6880 10:03:38.462882 # SIG_OK -- SP:0xFFFFD11811C3 si_addr@:0xffffd11811c3 si_code:2 token@:0xffffd11811c3 offset:0
6881 10:03:38.466007 # ==>> completed. PASS(1)
6882 10:03:38.472835 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
6883 10:03:38.479383 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD11811C3
6884 10:03:38.486009 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
6885 10:03:38.489088 # selftests: arm64: fake_sigreturn_missing_fpsimd
6886 10:03:38.543290 # Registered handlers for all signals.
6887 10:03:38.543944 # Detected MINSTKSIGSZ:4720
6888 10:03:38.546011 # Testcase initialized.
6889 10:03:38.549452 # uc context validated.
6890 10:03:38.553248 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6891 10:03:38.556195 # Handled SIG_COPYCTX
6892 10:03:38.559545 # Mangling template header. Spare space:4096
6893 10:03:38.562620 # Using badly built context - ERR: Missing FPSIMD
6894 10:03:38.572547 # SIG_OK -- SP:0xFFFFECC9FD70 si_addr@:0xffffecc9fd70 si_code:2 token@:0xffffecc9eb10 offset:-4704
6895 10:03:38.576178 # ==>> completed. PASS(1)
6896 10:03:38.582646 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
6897 10:03:38.588933 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFECC9EB10
6898 10:03:38.592487 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
6899 10:03:38.599242 # selftests: arm64: fake_sigreturn_sme_change_vl
6900 10:03:38.635117 # Registered handlers for all signals.
6901 10:03:38.635712 # Detected MINSTKSIGSZ:4720
6902 10:03:38.638147 # ==>> completed. SKIP.
6903 10:03:38.645323 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
6904 10:03:38.648486 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
6905 10:03:38.661168 # selftests: arm64: fake_sigreturn_sve_change_vl
6906 10:03:38.731231 # Registered handlers for all signals.
6907 10:03:38.731902 # Detected MINSTKSIGSZ:4720
6908 10:03:38.734525 # ==>> completed. SKIP.
6909 10:03:38.740999 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
6910 10:03:38.744421 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
6911 10:03:38.753559 # selftests: arm64: mangle_pstate_invalid_compat_toggle
6912 10:03:38.817263 # Registered handlers for all signals.
6913 10:03:38.817952 # Detected MINSTKSIGSZ:4720
6914 10:03:38.821125 # Testcase initialized.
6915 10:03:38.823957 # uc context validated.
6916 10:03:38.824666 # Handled SIG_TRIG
6917 10:03:38.833774 # SIG_OK -- SP:0xFFFFD9B869C0 si_addr@:0xffffd9b869c0 si_code:2 token@:(nil) offset:-281474334484928
6918 10:03:38.837337 # ==>> completed. PASS(1)
6919 10:03:38.843574 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
6920 10:03:38.850497 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
6921 10:03:38.853620 # selftests: arm64: mangle_pstate_invalid_daif_bits
6922 10:03:38.910068 # Registered handlers for all signals.
6923 10:03:38.910674 # Detected MINSTKSIGSZ:4720
6924 10:03:38.913326 # Testcase initialized.
6925 10:03:38.916861 # uc context validated.
6926 10:03:38.917296 # Handled SIG_TRIG
6927 10:03:38.926816 # SIG_OK -- SP:0xFFFFD086C960 si_addr@:0xffffd086c960 si_code:2 token@:(nil) offset:-281474180237664
6928 10:03:38.929925 # ==>> completed. PASS(1)
6929 10:03:38.936168 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
6930 10:03:38.939492 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
6931 10:03:38.946130 # selftests: arm64: mangle_pstate_invalid_mode_el1h
6932 10:03:39.006967 # Registered handlers for all signals.
6933 10:03:39.007559 # Detected MINSTKSIGSZ:4720
6934 10:03:39.010228 # Testcase initialized.
6935 10:03:39.013606 # uc context validated.
6936 10:03:39.014064 # Handled SIG_TRIG
6937 10:03:39.023142 # SIG_OK -- SP:0xFFFFF79FBC20 si_addr@:0xfffff79fbc20 si_code:2 token@:(nil) offset:-281474836184096
6938 10:03:39.026503 # ==>> completed. PASS(1)
6939 10:03:39.033265 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
6940 10:03:39.036541 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
6941 10:03:39.042750 # selftests: arm64: mangle_pstate_invalid_mode_el1t
6942 10:03:39.107544 # Registered handlers for all signals.
6943 10:03:39.108106 # Detected MINSTKSIGSZ:4720
6944 10:03:39.110811 # Testcase initialized.
6945 10:03:39.114301 # uc context validated.
6946 10:03:39.114853 # Handled SIG_TRIG
6947 10:03:39.124049 # SIG_OK -- SP:0xFFFFDCD6DA80 si_addr@:0xffffdcd6da80 si_code:2 token@:(nil) offset:-281474386811520
6948 10:03:39.127121 # ==>> completed. PASS(1)
6949 10:03:39.133651 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
6950 10:03:39.137352 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
6951 10:03:39.143847 # selftests: arm64: mangle_pstate_invalid_mode_el2h
6952 10:03:39.205934 # Registered handlers for all signals.
6953 10:03:39.206488 # Detected MINSTKSIGSZ:4720
6954 10:03:39.209152 # Testcase initialized.
6955 10:03:39.212153 # uc context validated.
6956 10:03:39.212703 # Handled SIG_TRIG
6957 10:03:39.222480 # SIG_OK -- SP:0xFFFFF13D2FF0 si_addr@:0xfffff13d2ff0 si_code:2 token@:(nil) offset:-281474729062384
6958 10:03:39.225588 # ==>> completed. PASS(1)
6959 10:03:39.231834 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
6960 10:03:39.235292 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
6961 10:03:39.242192 # selftests: arm64: mangle_pstate_invalid_mode_el2t
6962 10:03:39.305902 # Registered handlers for all signals.
6963 10:03:39.306520 # Detected MINSTKSIGSZ:4720
6964 10:03:39.309622 # Testcase initialized.
6965 10:03:39.312450 # uc context validated.
6966 10:03:39.312931 # Handled SIG_TRIG
6967 10:03:39.322151 # SIG_OK -- SP:0xFFFFCE58EFA0 si_addr@:0xffffce58efa0 si_code:2 token@:(nil) offset:-281474143678368
6968 10:03:39.326001 # ==>> completed. PASS(1)
6969 10:03:39.332584 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
6970 10:03:39.335692 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
6971 10:03:39.342299 # selftests: arm64: mangle_pstate_invalid_mode_el3h
6972 10:03:39.397730 # Registered handlers for all signals.
6973 10:03:39.398242 # Detected MINSTKSIGSZ:4720
6974 10:03:39.400810 # Testcase initialized.
6975 10:03:39.403934 # uc context validated.
6976 10:03:39.404352 # Handled SIG_TRIG
6977 10:03:39.413984 # SIG_OK -- SP:0xFFFFDC105E10 si_addr@:0xffffdc105e10 si_code:2 token@:(nil) offset:-281474373803536
6978 10:03:39.416987 # ==>> completed. PASS(1)
6979 10:03:39.424289 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
6980 10:03:39.427429 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
6981 10:03:39.433906 # selftests: arm64: mangle_pstate_invalid_mode_el3t
6982 10:03:39.483600 # Registered handlers for all signals.
6983 10:03:39.484116 # Detected MINSTKSIGSZ:4720
6984 10:03:39.486620 # Testcase initialized.
6985 10:03:39.490392 # uc context validated.
6986 10:03:39.490810 # Handled SIG_TRIG
6987 10:03:39.499933 # SIG_OK -- SP:0xFFFFF9F35960 si_addr@:0xfffff9f35960 si_code:2 token@:(nil) offset:-281474875218272
6988 10:03:39.503699 # ==>> completed. PASS(1)
6989 10:03:39.509987 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
6990 10:03:39.513099 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
6991 10:03:39.516318 # selftests: arm64: sme_trap_no_sm
6992 10:03:39.575753 # Registered handlers for all signals.
6993 10:03:39.576375 # Detected MINSTKSIGSZ:4720
6994 10:03:39.578650 # ==>> completed. SKIP.
6995 10:03:39.588678 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
6996 10:03:39.592351 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
6997 10:03:39.595511 # selftests: arm64: sme_trap_non_streaming
6998 10:03:39.669317 # Registered handlers for all signals.
6999 10:03:39.669957 # Detected MINSTKSIGSZ:4720
7000 10:03:39.672084 # ==>> completed. SKIP.
7001 10:03:39.681928 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
7002 10:03:39.688563 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
7003 10:03:39.691961 # selftests: arm64: sme_trap_za
7004 10:03:39.763607 # Registered handlers for all signals.
7005 10:03:39.764215 # Detected MINSTKSIGSZ:4720
7006 10:03:39.766949 # Testcase initialized.
7007 10:03:39.776650 # SIG_OK -- SP:0xFFFFDB092B00 si_addr@:0xaaaab4a72510 si_code:1 token@:(nil) offset:-187650152015120
7008 10:03:39.779896 # ==>> completed. PASS(1)
7009 10:03:39.786486 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
7010 10:03:39.789997 ok 21 selftests: arm64: sme_trap_za
7011 10:03:39.790615 # selftests: arm64: sme_vl
7012 10:03:39.886268 # Registered handlers for all signals.
7013 10:03:39.886947 # Detected MINSTKSIGSZ:4720
7014 10:03:39.890205 # ==>> completed. SKIP.
7015 10:03:39.893211 # # SME VL :: Check that we get the right SME VL reported
7016 10:03:39.896524 ok 22 selftests: arm64: sme_vl # SKIP
7017 10:03:39.905521 # selftests: arm64: ssve_regs
7018 10:03:39.996243 # Registered handlers for all signals.
7019 10:03:39.996773 # Detected MINSTKSIGSZ:4720
7020 10:03:39.999161 # ==>> completed. SKIP.
7021 10:03:40.005361 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
7022 10:03:40.012133 ok 23 selftests: arm64: ssve_regs # SKIP
7023 10:03:40.016417 # selftests: arm64: sve_regs
7024 10:03:40.087614 # Registered handlers for all signals.
7025 10:03:40.088159 # Detected MINSTKSIGSZ:4720
7026 10:03:40.091858 # ==>> completed. SKIP.
7027 10:03:40.097597 # # SVE registers :: Check that we get the right SVE registers reported
7028 10:03:40.100484 ok 24 selftests: arm64: sve_regs # SKIP
7029 10:03:40.106955 # selftests: arm64: sve_vl
7030 10:03:40.190347 # Registered handlers for all signals.
7031 10:03:40.191013 # Detected MINSTKSIGSZ:4720
7032 10:03:40.193847 # ==>> completed. SKIP.
7033 10:03:40.200303 # # SVE VL :: Check that we get the right SVE VL reported
7034 10:03:40.204099 ok 25 selftests: arm64: sve_vl # SKIP
7035 10:03:40.209322 # selftests: arm64: za_no_regs
7036 10:03:40.304082 # Registered handlers for all signals.
7037 10:03:40.304681 # Detected MINSTKSIGSZ:4720
7038 10:03:40.307633 # ==>> completed. SKIP.
7039 10:03:40.314081 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
7040 10:03:40.317329 ok 26 selftests: arm64: za_no_regs # SKIP
7041 10:03:40.324874 # selftests: arm64: za_regs
7042 10:03:40.407172 # Registered handlers for all signals.
7043 10:03:40.407860 # Detected MINSTKSIGSZ:4720
7044 10:03:40.410722 # ==>> completed. SKIP.
7045 10:03:40.416960 # # ZA register :: Check that we get the right ZA registers reported
7046 10:03:40.420126 ok 27 selftests: arm64: za_regs # SKIP
7047 10:03:40.424104 # selftests: arm64: pac
7048 10:03:40.484740 # TAP version 13
7049 10:03:40.485307 # 1..7
7050 10:03:40.488166 # # Starting 7 tests from 1 test cases.
7051 10:03:40.491863 # # RUN global.corrupt_pac ...
7052 10:03:40.494971 # # SKIP PAUTH not enabled
7053 10:03:40.498315 # # OK global.corrupt_pac
7054 10:03:40.501122 # ok 1 # SKIP PAUTH not enabled
7055 10:03:40.507954 # # RUN global.pac_instructions_not_nop ...
7056 10:03:40.511011 # # SKIP PAUTH not enabled
7057 10:03:40.514632 # # OK global.pac_instructions_not_nop
7058 10:03:40.517902 # ok 2 # SKIP PAUTH not enabled
7059 10:03:40.524257 # # RUN global.pac_instructions_not_nop_generic ...
7060 10:03:40.527878 # # SKIP Generic PAUTH not enabled
7061 10:03:40.530799 # # OK global.pac_instructions_not_nop_generic
7062 10:03:40.537517 # ok 3 # SKIP Generic PAUTH not enabled
7063 10:03:40.540910 # # RUN global.single_thread_different_keys ...
7064 10:03:40.544192 # # SKIP PAUTH not enabled
7065 10:03:40.550531 # # OK global.single_thread_different_keys
7066 10:03:40.550954 # ok 4 # SKIP PAUTH not enabled
7067 10:03:40.557764 # # RUN global.exec_changed_keys ...
7068 10:03:40.560813 # # SKIP PAUTH not enabled
7069 10:03:40.564558 # # OK global.exec_changed_keys
7070 10:03:40.567459 # ok 5 # SKIP PAUTH not enabled
7071 10:03:40.570768 # # RUN global.context_switch_keep_keys ...
7072 10:03:40.574197 # # SKIP PAUTH not enabled
7073 10:03:40.580879 # # OK global.context_switch_keep_keys
7074 10:03:40.581409 # ok 6 # SKIP PAUTH not enabled
7075 10:03:40.587175 # # RUN global.context_switch_keep_keys_generic ...
7076 10:03:40.590987 # # SKIP Generic PAUTH not enabled
7077 10:03:40.597236 # # OK global.context_switch_keep_keys_generic
7078 10:03:40.600599 # ok 7 # SKIP Generic PAUTH not enabled
7079 10:03:40.603830 # # PASSED: 7 / 7 tests passed.
7080 10:03:40.607569 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
7081 10:03:40.610610 ok 28 selftests: arm64: pac
7082 10:03:40.613786 # selftests: arm64: fp-stress
7083 10:03:48.820174 <6>[ 35.942329] vaux18: disabling
7084 10:03:48.823321 <6>[ 35.945704] vio28: disabling
7085 10:03:50.558979 # TAP version 13
7086 10:03:50.559600 # 1..16
7087 10:03:50.562189 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
7088 10:03:50.565145 # # Will run for 10s
7089 10:03:50.565606 # # Started FPSIMD-0-0
7090 10:03:50.568654 # # Started FPSIMD-0-1
7091 10:03:50.572431 # # Started FPSIMD-1-0
7092 10:03:50.573106 # # Started FPSIMD-1-1
7093 10:03:50.575111 # # Started FPSIMD-2-0
7094 10:03:50.575615 # # Started FPSIMD-2-1
7095 10:03:50.578622 # # Started FPSIMD-3-0
7096 10:03:50.581701 # # Started FPSIMD-3-1
7097 10:03:50.582161 # # Started FPSIMD-4-0
7098 10:03:50.584878 # # Started FPSIMD-4-1
7099 10:03:50.588070 # # Started FPSIMD-5-0
7100 10:03:50.588487 # # Started FPSIMD-5-1
7101 10:03:50.591872 # # Started FPSIMD-6-0
7102 10:03:50.594864 # # Started FPSIMD-6-1
7103 10:03:50.595282 # # Started FPSIMD-7-0
7104 10:03:50.598496 # # Started FPSIMD-7-1
7105 10:03:50.601743 # # FPSIMD-1-1: Vector length: 128 bits
7106 10:03:50.605201 # # FPSIMD-1-1: PID: 1190
7107 10:03:50.608146 # # FPSIMD-1-0: Vector length: 128 bits
7108 10:03:50.608562 # # FPSIMD-1-0: PID: 1189
7109 10:03:50.611662 # # FPSIMD-0-0: Vector length: 128 bits
7110 10:03:50.615085 # # FPSIMD-0-0: PID: 1187
7111 10:03:50.618557 # # FPSIMD-2-1: Vector length: 128 bits
7112 10:03:50.621657 # # FPSIMD-2-1: PID: 1192
7113 10:03:50.624740 # # FPSIMD-0-1: Vector length: 128 bits
7114 10:03:50.628725 # # FPSIMD-0-1: PID: 1188
7115 10:03:50.631904 # # FPSIMD-4-1: Vector length: 128 bits
7116 10:03:50.632327 # # FPSIMD-4-1: PID: 1196
7117 10:03:50.635106 # # FPSIMD-2-0: Vector length: 128 bits
7118 10:03:50.638328 # # FPSIMD-2-0: PID: 1191
7119 10:03:50.641833 # # FPSIMD-5-0: Vector length: 128 bits
7120 10:03:50.645360 # # FPSIMD-5-0: PID: 1197
7121 10:03:50.648667 # # FPSIMD-5-1: Vector length: 128 bits
7122 10:03:50.651570 # # FPSIMD-5-1: PID: 1198
7123 10:03:50.655065 # # FPSIMD-4-0: Vector length: 128 bits
7124 10:03:50.658285 # # FPSIMD-4-0: PID: 1195
7125 10:03:50.661463 # # FPSIMD-7-1: Vector length: 128 bits
7126 10:03:50.661981 # # FPSIMD-7-1: PID: 1202
7127 10:03:50.668209 # # FPSIMD-3-0: Vector length: 128 bits
7128 10:03:50.668697 # # FPSIMD-3-0: PID: 1193
7129 10:03:50.671509 # # FPSIMD-7-0: Vector length: 128 bits
7130 10:03:50.674879 # # FPSIMD-7-0: PID: 1201
7131 10:03:50.678152 # # FPSIMD-3-1: Vector length: 128 bits
7132 10:03:50.681368 # # FPSIMD-3-1: PID: 1194
7133 10:03:50.684576 # # FPSIMD-6-0: Vector length: 128 bits
7134 10:03:50.687833 # # FPSIMD-6-0: PID: 1199
7135 10:03:50.691218 # # FPSIMD-6-1: Vector length: 128 bits
7136 10:03:50.691789 # # FPSIMD-6-1: PID: 1200
7137 10:03:50.694975 # # Finishing up...
7138 10:03:50.701537 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=826171, signals=10
7139 10:03:50.707330 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1001870, signals=10
7140 10:03:50.717554 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=868104, signals=10
7141 10:03:50.723852 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=694436, signals=10
7142 10:03:50.730878 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=770537, signals=10
7143 10:03:50.737307 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=718884, signals=9
7144 10:03:50.743948 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=813072, signals=10
7145 10:03:50.747386 # ok 1 FPSIMD-0-0
7146 10:03:50.747932 # ok 2 FPSIMD-0-1
7147 10:03:50.750698 # ok 3 FPSIMD-1-0
7148 10:03:50.751110 # ok 4 FPSIMD-1-1
7149 10:03:50.754031 # ok 5 FPSIMD-2-0
7150 10:03:50.754550 # ok 6 FPSIMD-2-1
7151 10:03:50.757024 # ok 7 FPSIMD-3-0
7152 10:03:50.757483 # ok 8 FPSIMD-3-1
7153 10:03:50.760474 # ok 9 FPSIMD-4-0
7154 10:03:50.760982 # ok 10 FPSIMD-4-1
7155 10:03:50.764072 # ok 11 FPSIMD-5-0
7156 10:03:50.764485 # ok 12 FPSIMD-5-1
7157 10:03:50.767204 # ok 13 FPSIMD-6-0
7158 10:03:50.767646 # ok 14 FPSIMD-6-1
7159 10:03:50.770412 # ok 15 FPSIMD-7-0
7160 10:03:50.770891 # ok 16 FPSIMD-7-1
7161 10:03:50.777283 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=773548, signals=9
7162 10:03:50.787259 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=715270, signals=10
7163 10:03:50.793424 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=986024, signals=10
7164 10:03:50.800261 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=784515, signals=10
7165 10:03:50.807021 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=705487, signals=10
7166 10:03:50.813297 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=810297, signals=10
7167 10:03:50.819644 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=704190, signals=9
7168 10:03:50.829853 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=880072, signals=10
7169 10:03:50.836592 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=765687, signals=10
7170 10:03:50.839868 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
7171 10:03:50.843296 ok 29 selftests: arm64: fp-stress
7172 10:03:50.846552 # selftests: arm64: sve-ptrace
7173 10:03:50.846964 # TAP version 13
7174 10:03:50.849980 # 1..4104
7175 10:03:50.852988 # ok 2 # SKIP SVE not available
7176 10:03:50.856813 # # Planned tests != run tests (4104 != 1)
7177 10:03:50.859657 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7178 10:03:50.863190 ok 30 selftests: arm64: sve-ptrace # SKIP
7179 10:03:50.866678 # selftests: arm64: sve-probe-vls
7180 10:03:50.870007 # TAP version 13
7181 10:03:50.870545 # 1..2
7182 10:03:50.873178 # ok 2 # SKIP SVE not available
7183 10:03:50.876439 # # Planned tests != run tests (2 != 1)
7184 10:03:50.879519 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7185 10:03:50.886620 ok 31 selftests: arm64: sve-probe-vls # SKIP
7186 10:03:50.889991 # selftests: arm64: vec-syscfg
7187 10:03:50.893436 # TAP version 13
7188 10:03:50.893944 # 1..20
7189 10:03:50.896641 # ok 1 # SKIP SVE not supported
7190 10:03:50.897196 # ok 2 # SKIP SVE not supported
7191 10:03:50.899904 # ok 3 # SKIP SVE not supported
7192 10:03:50.902928 # ok 4 # SKIP SVE not supported
7193 10:03:50.906491 # ok 5 # SKIP SVE not supported
7194 10:03:50.909514 # ok 6 # SKIP SVE not supported
7195 10:03:50.912900 # ok 7 # SKIP SVE not supported
7196 10:03:50.916531 # ok 8 # SKIP SVE not supported
7197 10:03:50.919765 # ok 9 # SKIP SVE not supported
7198 10:03:50.920179 # ok 10 # SKIP SVE not supported
7199 10:03:50.922809 # ok 11 # SKIP SME not supported
7200 10:03:50.926071 # ok 12 # SKIP SME not supported
7201 10:03:50.929812 # ok 13 # SKIP SME not supported
7202 10:03:50.933050 # ok 14 # SKIP SME not supported
7203 10:03:50.936039 # ok 15 # SKIP SME not supported
7204 10:03:50.939529 # ok 16 # SKIP SME not supported
7205 10:03:50.942958 # ok 17 # SKIP SME not supported
7206 10:03:50.946254 # ok 18 # SKIP SME not supported
7207 10:03:50.946671 # ok 19 # SKIP SME not supported
7208 10:03:50.949630 # ok 20 # SKIP SME not supported
7209 10:03:50.955960 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
7210 10:03:50.959228 ok 32 selftests: arm64: vec-syscfg
7211 10:03:50.962638 # selftests: arm64: za-fork
7212 10:03:51.000052 # TAP version 13
7213 10:03:51.000598 # 1..1
7214 10:03:51.002882 # # PID: 1279
7215 10:03:51.003546 # # SME support not present
7216 10:03:51.006482 # ok 0 skipped
7217 10:03:51.009505 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7218 10:03:51.012540 ok 33 selftests: arm64: za-fork
7219 10:03:51.022198 # selftests: arm64: za-ptrace
7220 10:03:51.103851 # TAP version 13
7221 10:03:51.104402 # 1..1
7222 10:03:51.107235 # ok 2 # SKIP SME not available
7223 10:03:51.114135 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7224 10:03:51.116894 ok 34 selftests: arm64: za-ptrace # SKIP
7225 10:03:51.135122 # selftests: arm64: check_buffer_fill
7226 10:03:51.198281 # # SKIP: MTE features unavailable
7227 10:03:51.206661 ok 35 selftests: arm64: check_buffer_fill # SKIP
7228 10:03:51.223036 # selftests: arm64: check_child_memory
7229 10:03:51.299303 # # SKIP: MTE features unavailable
7230 10:03:51.308753 ok 36 selftests: arm64: check_child_memory # SKIP
7231 10:03:51.328678 # selftests: arm64: check_gcr_el1_cswitch
7232 10:03:51.406815 # # SKIP: MTE features unavailable
7233 10:03:51.415029 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
7234 10:03:51.430046 # selftests: arm64: check_ksm_options
7235 10:03:51.502937 # # SKIP: MTE features unavailable
7236 10:03:51.510821 ok 38 selftests: arm64: check_ksm_options # SKIP
7237 10:03:51.530977 # selftests: arm64: check_mmap_options
7238 10:03:51.612066 # # SKIP: MTE features unavailable
7239 10:03:51.620299 ok 39 selftests: arm64: check_mmap_options # SKIP
7240 10:03:51.635091 # selftests: arm64: check_prctl
7241 10:03:51.706742 # TAP version 13
7242 10:03:51.707292 # 1..5
7243 10:03:51.710307 # ok 1 check_basic_read
7244 10:03:51.710912 # ok 2 NONE
7245 10:03:51.713399 # ok 3 # SKIP SYNC
7246 10:03:51.713813 # ok 4 # SKIP ASYNC
7247 10:03:51.716560 # ok 5 # SKIP SYNC+ASYNC
7248 10:03:51.720079 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
7249 10:03:51.723054 ok 40 selftests: arm64: check_prctl
7250 10:03:51.729664 # selftests: arm64: check_tags_inclusion
7251 10:03:51.780717 # # SKIP: MTE features unavailable
7252 10:03:51.790578 ok 41 selftests: arm64: check_tags_inclusion # SKIP
7253 10:03:51.807845 # selftests: arm64: check_user_mem
7254 10:03:51.894910 # # SKIP: MTE features unavailable
7255 10:03:51.904328 ok 42 selftests: arm64: check_user_mem # SKIP
7256 10:03:51.917095 # selftests: arm64: btitest
7257 10:03:51.993222 # TAP version 13
7258 10:03:51.993790 # 1..18
7259 10:03:51.996205 # # HWCAP_PACA not present
7260 10:03:51.999613 # # HWCAP2_BTI not present
7261 10:03:52.000165 # # Test binary built for BTI
7262 10:03:52.005880 # ok 1 nohint_func/call_using_br_x0 # SKIP
7263 10:03:52.009686 # ok 1 nohint_func/call_using_br_x16 # SKIP
7264 10:03:52.012640 # ok 1 nohint_func/call_using_blr # SKIP
7265 10:03:52.016181 # ok 1 bti_none_func/call_using_br_x0 # SKIP
7266 10:03:52.019513 # ok 1 bti_none_func/call_using_br_x16 # SKIP
7267 10:03:52.025735 # ok 1 bti_none_func/call_using_blr # SKIP
7268 10:03:52.029406 # ok 1 bti_c_func/call_using_br_x0 # SKIP
7269 10:03:52.032663 # ok 1 bti_c_func/call_using_br_x16 # SKIP
7270 10:03:52.035951 # ok 1 bti_c_func/call_using_blr # SKIP
7271 10:03:52.039370 # ok 1 bti_j_func/call_using_br_x0 # SKIP
7272 10:03:52.042373 # ok 1 bti_j_func/call_using_br_x16 # SKIP
7273 10:03:52.046054 # ok 1 bti_j_func/call_using_blr # SKIP
7274 10:03:52.049284 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
7275 10:03:52.055705 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
7276 10:03:52.058816 # ok 1 bti_jc_func/call_using_blr # SKIP
7277 10:03:52.062620 # ok 1 paciasp_func/call_using_br_x0 # SKIP
7278 10:03:52.066260 # ok 1 paciasp_func/call_using_br_x16 # SKIP
7279 10:03:52.068937 # ok 1 paciasp_func/call_using_blr # SKIP
7280 10:03:52.075595 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
7281 10:03:52.079227 # # WARNING - EXPECTED TEST COUNT WRONG
7282 10:03:52.082335 ok 43 selftests: arm64: btitest
7283 10:03:52.082767 # selftests: arm64: nobtitest
7284 10:03:52.100256 # TAP version 13
7285 10:03:52.100772 # 1..18
7286 10:03:52.103527 # # HWCAP_PACA not present
7287 10:03:52.106958 # # HWCAP2_BTI not present
7288 10:03:52.110535 # # Test binary not built for BTI
7289 10:03:52.113336 # ok 1 nohint_func/call_using_br_x0 # SKIP
7290 10:03:52.117505 # ok 1 nohint_func/call_using_br_x16 # SKIP
7291 10:03:52.120411 # ok 1 nohint_func/call_using_blr # SKIP
7292 10:03:52.123246 # ok 1 bti_none_func/call_using_br_x0 # SKIP
7293 10:03:52.126663 # ok 1 bti_none_func/call_using_br_x16 # SKIP
7294 10:03:52.133340 # ok 1 bti_none_func/call_using_blr # SKIP
7295 10:03:52.136618 # ok 1 bti_c_func/call_using_br_x0 # SKIP
7296 10:03:52.140324 # ok 1 bti_c_func/call_using_br_x16 # SKIP
7297 10:03:52.143740 # ok 1 bti_c_func/call_using_blr # SKIP
7298 10:03:52.146845 # ok 1 bti_j_func/call_using_br_x0 # SKIP
7299 10:03:52.150569 # ok 1 bti_j_func/call_using_br_x16 # SKIP
7300 10:03:52.153635 # ok 1 bti_j_func/call_using_blr # SKIP
7301 10:03:52.156822 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
7302 10:03:52.163513 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
7303 10:03:52.167089 # ok 1 bti_jc_func/call_using_blr # SKIP
7304 10:03:52.170061 # ok 1 paciasp_func/call_using_br_x0 # SKIP
7305 10:03:52.173395 # ok 1 paciasp_func/call_using_br_x16 # SKIP
7306 10:03:52.176780 # ok 1 paciasp_func/call_using_blr # SKIP
7307 10:03:52.183341 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
7308 10:03:52.187100 # # WARNING - EXPECTED TEST COUNT WRONG
7309 10:03:52.190400 ok 44 selftests: arm64: nobtitest
7310 10:03:52.193555 # selftests: arm64: hwcap
7311 10:03:52.216838 # TAP version 13
7312 10:03:52.217432 # 1..28
7313 10:03:52.220075 # ok 1 cpuinfo_match_RNG
7314 10:03:52.223319 # # SIGILL reported for RNG
7315 10:03:52.223827 # ok 2 # SKIP sigill_RNG
7316 10:03:52.226626 # ok 3 cpuinfo_match_SME
7317 10:03:52.229517 # ok 4 sigill_SME
7318 10:03:52.229963 # ok 5 cpuinfo_match_SVE
7319 10:03:52.233253 # ok 6 sigill_SVE
7320 10:03:52.233700 # ok 7 cpuinfo_match_SVE 2
7321 10:03:52.236272 # # SIGILL reported for SVE 2
7322 10:03:52.239627 # ok 8 # SKIP sigill_SVE 2
7323 10:03:52.243401 # ok 9 cpuinfo_match_SVE AES
7324 10:03:52.246649 # # SIGILL reported for SVE AES
7325 10:03:52.247165 # ok 10 # SKIP sigill_SVE AES
7326 10:03:52.249642 # ok 11 cpuinfo_match_SVE2 PMULL
7327 10:03:52.253093 # # SIGILL reported for SVE2 PMULL
7328 10:03:52.256554 # ok 12 # SKIP sigill_SVE2 PMULL
7329 10:03:52.259574 # ok 13 cpuinfo_match_SVE2 BITPERM
7330 10:03:52.262989 # # SIGILL reported for SVE2 BITPERM
7331 10:03:52.266266 # ok 14 # SKIP sigill_SVE2 BITPERM
7332 10:03:52.269402 # ok 15 cpuinfo_match_SVE2 SHA3
7333 10:03:52.272875 # # SIGILL reported for SVE2 SHA3
7334 10:03:52.276234 # ok 16 # SKIP sigill_SVE2 SHA3
7335 10:03:52.276652 # ok 17 cpuinfo_match_SVE2 SM4
7336 10:03:52.280104 # # SIGILL reported for SVE2 SM4
7337 10:03:52.283215 # ok 18 # SKIP sigill_SVE2 SM4
7338 10:03:52.286317 # ok 19 cpuinfo_match_SVE2 I8MM
7339 10:03:52.289923 # # SIGILL reported for SVE2 I8MM
7340 10:03:52.292777 # ok 20 # SKIP sigill_SVE2 I8MM
7341 10:03:52.296678 # ok 21 cpuinfo_match_SVE2 F32MM
7342 10:03:52.299977 # # SIGILL reported for SVE2 F32MM
7343 10:03:52.303254 # ok 22 # SKIP sigill_SVE2 F32MM
7344 10:03:52.303729 # ok 23 cpuinfo_match_SVE2 F64MM
7345 10:03:52.306512 # # SIGILL reported for SVE2 F64MM
7346 10:03:52.309667 # ok 24 # SKIP sigill_SVE2 F64MM
7347 10:03:52.312790 # ok 25 cpuinfo_match_SVE2 BF16
7348 10:03:52.316198 # # SIGILL reported for SVE2 BF16
7349 10:03:52.319384 # ok 26 # SKIP sigill_SVE2 BF16
7350 10:03:52.322863 # ok 27 cpuinfo_match_SVE2 EBF16
7351 10:03:52.326605 # ok 28 # SKIP sigill_SVE2 EBF16
7352 10:03:52.329605 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
7353 10:03:52.332753 ok 45 selftests: arm64: hwcap
7354 10:03:52.335972 # selftests: arm64: ptrace
7355 10:03:52.336386 # TAP version 13
7356 10:03:52.339713 # 1..7
7357 10:03:52.343171 # # Parent is 1522, child is 1523
7358 10:03:52.343671 # ok 1 read_tpidr_one
7359 10:03:52.345880 # ok 2 write_tpidr_one
7360 10:03:52.346298 # ok 3 verify_tpidr_one
7361 10:03:52.349512 # ok 4 count_tpidrs
7362 10:03:52.352840 # ok 5 tpidr2_write
7363 10:03:52.353259 # ok 6 tpidr2_read
7364 10:03:52.356100 # ok 7 write_tpidr_only
7365 10:03:52.359362 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
7366 10:03:52.362453 ok 46 selftests: arm64: ptrace
7367 10:03:52.366205 # selftests: arm64: syscall-abi
7368 10:03:52.408954 # TAP version 13
7369 10:03:52.409463 # 1..2
7370 10:03:52.411938 # ok 1 getpid() FPSIMD
7371 10:03:52.414967 # ok 2 sched_yield() FPSIMD
7372 10:03:52.418717 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
7373 10:03:52.421941 ok 47 selftests: arm64: syscall-abi
7374 10:03:52.428799 # selftests: arm64: tpidr2
7375 10:03:52.485978 # TAP version 13
7376 10:03:52.486515 # 1..5
7377 10:03:52.488861 # # PID: 1559
7378 10:03:52.489322 # # SME support not present
7379 10:03:52.492144 # ok 0 skipped, TPIDR2 not supported
7380 10:03:52.495493 # ok 1 skipped, TPIDR2 not supported
7381 10:03:52.498683 # ok 2 skipped, TPIDR2 not supported
7382 10:03:52.501773 # ok 3 skipped, TPIDR2 not supported
7383 10:03:52.505227 # ok 4 skipped, TPIDR2 not supported
7384 10:03:52.511646 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
7385 10:03:52.514882 ok 48 selftests: arm64: tpidr2
7386 10:03:54.150850 arm64_tags_test pass
7387 10:03:54.154370 arm64_run_tags_test_sh pass
7388 10:03:54.157519 arm64_fake_sigreturn_bad_magic pass
7389 10:03:54.160764 arm64_fake_sigreturn_bad_size pass
7390 10:03:54.164273 arm64_fake_sigreturn_bad_size_for_magic0 pass
7391 10:03:54.167580 arm64_fake_sigreturn_duplicated_fpsimd pass
7392 10:03:54.171170 arm64_fake_sigreturn_misaligned_sp pass
7393 10:03:54.174058 arm64_fake_sigreturn_missing_fpsimd pass
7394 10:03:54.177759 arm64_fake_sigreturn_sme_change_vl skip
7395 10:03:54.180638 arm64_fake_sigreturn_sve_change_vl skip
7396 10:03:54.187556 arm64_mangle_pstate_invalid_compat_toggle pass
7397 10:03:54.190807 arm64_mangle_pstate_invalid_daif_bits pass
7398 10:03:54.193805 arm64_mangle_pstate_invalid_mode_el1h pass
7399 10:03:54.197083 arm64_mangle_pstate_invalid_mode_el1t pass
7400 10:03:54.200247 arm64_mangle_pstate_invalid_mode_el2h pass
7401 10:03:54.207325 arm64_mangle_pstate_invalid_mode_el2t pass
7402 10:03:54.210827 arm64_mangle_pstate_invalid_mode_el3h pass
7403 10:03:54.213802 arm64_mangle_pstate_invalid_mode_el3t pass
7404 10:03:54.217316 arm64_sme_trap_no_sm skip
7405 10:03:54.220419 arm64_sme_trap_non_streaming skip
7406 10:03:54.220834 arm64_sme_trap_za pass
7407 10:03:54.223569 arm64_sme_vl skip
7408 10:03:54.223986 arm64_ssve_regs skip
7409 10:03:54.226703 arm64_sve_regs skip
7410 10:03:54.227121 arm64_sve_vl skip
7411 10:03:54.230521 arm64_za_no_regs skip
7412 10:03:54.233682 arm64_za_regs skip
7413 10:03:54.234210 arm64_pac_PAUTH_not_enabled skip
7414 10:03:54.237113 arm64_pac_PAUTH_not_enabled_dup2 skip
7415 10:03:54.243682 arm64_pac_Generic_PAUTH_not_enabled skip
7416 10:03:54.246850 arm64_pac_PAUTH_not_enabled_dup3 skip
7417 10:03:54.250499 arm64_pac_PAUTH_not_enabled_dup4 skip
7418 10:03:54.254110 arm64_pac_PAUTH_not_enabled_dup5 skip
7419 10:03:54.256948 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
7420 10:03:54.257370 arm64_pac pass
7421 10:03:54.260328 arm64_fp-stress_FPSIMD-0-0 pass
7422 10:03:54.264034 arm64_fp-stress_FPSIMD-0-1 pass
7423 10:03:54.267096 arm64_fp-stress_FPSIMD-1-0 pass
7424 10:03:54.270707 arm64_fp-stress_FPSIMD-1-1 pass
7425 10:03:54.273391 arm64_fp-stress_FPSIMD-2-0 pass
7426 10:03:54.276746 arm64_fp-stress_FPSIMD-2-1 pass
7427 10:03:54.280127 arm64_fp-stress_FPSIMD-3-0 pass
7428 10:03:54.283373 arm64_fp-stress_FPSIMD-3-1 pass
7429 10:03:54.286364 arm64_fp-stress_FPSIMD-4-0 pass
7430 10:03:54.289949 arm64_fp-stress_FPSIMD-4-1 pass
7431 10:03:54.292939 arm64_fp-stress_FPSIMD-5-0 pass
7432 10:03:54.296811 arm64_fp-stress_FPSIMD-5-1 pass
7433 10:03:54.300041 arm64_fp-stress_FPSIMD-6-0 pass
7434 10:03:54.300457 arm64_fp-stress_FPSIMD-6-1 pass
7435 10:03:54.302863 arm64_fp-stress_FPSIMD-7-0 pass
7436 10:03:54.306348 arm64_fp-stress_FPSIMD-7-1 pass
7437 10:03:54.309861 arm64_fp-stress pass
7438 10:03:54.313439 arm64_sve-ptrace_SVE_not_available skip
7439 10:03:54.316258 arm64_sve-ptrace skip
7440 10:03:54.319496 arm64_sve-probe-vls_SVE_not_available skip
7441 10:03:54.319911 arm64_sve-probe-vls skip
7442 10:03:54.326451 arm64_vec-syscfg_SVE_not_supported skip
7443 10:03:54.329990 arm64_vec-syscfg_SVE_not_supported_dup2 skip
7444 10:03:54.333172 arm64_vec-syscfg_SVE_not_supported_dup3 skip
7445 10:03:54.336218 arm64_vec-syscfg_SVE_not_supported_dup4 skip
7446 10:03:54.343124 arm64_vec-syscfg_SVE_not_supported_dup5 skip
7447 10:03:54.346254 arm64_vec-syscfg_SVE_not_supported_dup6 skip
7448 10:03:54.350104 arm64_vec-syscfg_SVE_not_supported_dup7 skip
7449 10:03:54.352787 arm64_vec-syscfg_SVE_not_supported_dup8 skip
7450 10:03:54.356128 arm64_vec-syscfg_SVE_not_supported_dup9 skip
7451 10:03:54.363247 arm64_vec-syscfg_SVE_not_supported_dup10 skip
7452 10:03:54.366481 arm64_vec-syscfg_SME_not_supported skip
7453 10:03:54.369754 arm64_vec-syscfg_SME_not_supported_dup2 skip
7454 10:03:54.372837 arm64_vec-syscfg_SME_not_supported_dup3 skip
7455 10:03:54.379836 arm64_vec-syscfg_SME_not_supported_dup4 skip
7456 10:03:54.383009 arm64_vec-syscfg_SME_not_supported_dup5 skip
7457 10:03:54.386442 arm64_vec-syscfg_SME_not_supported_dup6 skip
7458 10:03:54.389694 arm64_vec-syscfg_SME_not_supported_dup7 skip
7459 10:03:54.393261 arm64_vec-syscfg_SME_not_supported_dup8 skip
7460 10:03:54.399313 arm64_vec-syscfg_SME_not_supported_dup9 skip
7461 10:03:54.402682 arm64_vec-syscfg_SME_not_supported_dup10 skip
7462 10:03:54.406033 arm64_vec-syscfg pass
7463 10:03:54.406489 arm64_za-fork_skipped pass
7464 10:03:54.409184 arm64_za-fork pass
7465 10:03:54.413323 arm64_za-ptrace_SME_not_available skip
7466 10:03:54.413887 arm64_za-ptrace skip
7467 10:03:54.415974 arm64_check_buffer_fill skip
7468 10:03:54.418986 arm64_check_child_memory skip
7469 10:03:54.423267 arm64_check_gcr_el1_cswitch skip
7470 10:03:54.426096 arm64_check_ksm_options skip
7471 10:03:54.426556 arm64_check_mmap_options skip
7472 10:03:54.432819 arm64_check_prctl_check_basic_read pass
7473 10:03:54.433311 arm64_check_prctl_NONE pass
7474 10:03:54.435895 arm64_check_prctl_SYNC skip
7475 10:03:54.439358 arm64_check_prctl_ASYNC skip
7476 10:03:54.442434 arm64_check_prctl_SYNC_ASYNC skip
7477 10:03:54.442848 arm64_check_prctl pass
7478 10:03:54.445443 arm64_check_tags_inclusion skip
7479 10:03:54.449236 arm64_check_user_mem skip
7480 10:03:54.452085 arm64_btitest_nohint_func_call_using_br_x0 skip
7481 10:03:54.459288 arm64_btitest_nohint_func_call_using_br_x16 skip
7482 10:03:54.462422 arm64_btitest_nohint_func_call_using_blr skip
7483 10:03:54.465696 arm64_btitest_bti_none_func_call_using_br_x0 skip
7484 10:03:54.472594 arm64_btitest_bti_none_func_call_using_br_x16 skip
7485 10:03:54.475937 arm64_btitest_bti_none_func_call_using_blr skip
7486 10:03:54.479548 arm64_btitest_bti_c_func_call_using_br_x0 skip
7487 10:03:54.485692 arm64_btitest_bti_c_func_call_using_br_x16 skip
7488 10:03:54.489103 arm64_btitest_bti_c_func_call_using_blr skip
7489 10:03:54.492493 arm64_btitest_bti_j_func_call_using_br_x0 skip
7490 10:03:54.495575 arm64_btitest_bti_j_func_call_using_br_x16 skip
7491 10:03:54.502107 arm64_btitest_bti_j_func_call_using_blr skip
7492 10:03:54.505684 arm64_btitest_bti_jc_func_call_using_br_x0 skip
7493 10:03:54.508897 arm64_btitest_bti_jc_func_call_using_br_x16 skip
7494 10:03:54.511979 arm64_btitest_bti_jc_func_call_using_blr skip
7495 10:03:54.518851 arm64_btitest_paciasp_func_call_using_br_x0 skip
7496 10:03:54.522190 arm64_btitest_paciasp_func_call_using_br_x16 skip
7497 10:03:54.525260 arm64_btitest_paciasp_func_call_using_blr skip
7498 10:03:54.528878 arm64_btitest pass
7499 10:03:54.531861 arm64_nobtitest_nohint_func_call_using_br_x0 skip
7500 10:03:54.538898 arm64_nobtitest_nohint_func_call_using_br_x16 skip
7501 10:03:54.541996 arm64_nobtitest_nohint_func_call_using_blr skip
7502 10:03:54.545230 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
7503 10:03:54.552203 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
7504 10:03:54.555361 arm64_nobtitest_bti_none_func_call_using_blr skip
7505 10:03:54.558485 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
7506 10:03:54.565100 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
7507 10:03:54.568633 arm64_nobtitest_bti_c_func_call_using_blr skip
7508 10:03:54.571689 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
7509 10:03:54.578531 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
7510 10:03:54.581827 arm64_nobtitest_bti_j_func_call_using_blr skip
7511 10:03:54.585075 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
7512 10:03:54.588911 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
7513 10:03:54.594889 arm64_nobtitest_bti_jc_func_call_using_blr skip
7514 10:03:54.598356 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
7515 10:03:54.605098 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
7516 10:03:54.608102 arm64_nobtitest_paciasp_func_call_using_blr skip
7517 10:03:54.608395 arm64_nobtitest pass
7518 10:03:54.611716 arm64_hwcap_cpuinfo_match_RNG pass
7519 10:03:54.615014 arm64_hwcap_sigill_RNG skip
7520 10:03:54.618010 arm64_hwcap_cpuinfo_match_SME pass
7521 10:03:54.621909 arm64_hwcap_sigill_SME pass
7522 10:03:54.624753 arm64_hwcap_cpuinfo_match_SVE pass
7523 10:03:54.628083 arm64_hwcap_sigill_SVE pass
7524 10:03:54.628223 arm64_hwcap_cpuinfo_match_SVE_2 pass
7525 10:03:54.631239 arm64_hwcap_sigill_SVE_2 skip
7526 10:03:54.635018 arm64_hwcap_cpuinfo_match_SVE_AES pass
7527 10:03:54.638073 arm64_hwcap_sigill_SVE_AES skip
7528 10:03:54.641112 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
7529 10:03:54.644759 arm64_hwcap_sigill_SVE2_PMULL skip
7530 10:03:54.647936 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
7531 10:03:54.651194 arm64_hwcap_sigill_SVE2_BITPERM skip
7532 10:03:54.657602 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
7533 10:03:54.657682 arm64_hwcap_sigill_SVE2_SHA3 skip
7534 10:03:54.664291 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
7535 10:03:54.664412 arm64_hwcap_sigill_SVE2_SM4 skip
7536 10:03:54.670815 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
7537 10:03:54.670923 arm64_hwcap_sigill_SVE2_I8MM skip
7538 10:03:54.677793 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
7539 10:03:54.681079 arm64_hwcap_sigill_SVE2_F32MM skip
7540 10:03:54.684149 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
7541 10:03:54.687776 arm64_hwcap_sigill_SVE2_F64MM skip
7542 10:03:54.690938 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
7543 10:03:54.694072 arm64_hwcap_sigill_SVE2_BF16 skip
7544 10:03:54.697319 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
7545 10:03:54.700564 arm64_hwcap_sigill_SVE2_EBF16 skip
7546 10:03:54.700758 arm64_hwcap pass
7547 10:03:54.704224 arm64_ptrace_read_tpidr_one pass
7548 10:03:54.707581 arm64_ptrace_write_tpidr_one pass
7549 10:03:54.710767 arm64_ptrace_verify_tpidr_one pass
7550 10:03:54.714239 arm64_ptrace_count_tpidrs pass
7551 10:03:54.717689 arm64_ptrace_tpidr2_write pass
7552 10:03:54.718065 arm64_ptrace_tpidr2_read pass
7553 10:03:54.720983 arm64_ptrace_write_tpidr_only pass
7554 10:03:54.724180 arm64_ptrace pass
7555 10:03:54.727528 arm64_syscall-abi_getpid_FPSIMD pass
7556 10:03:54.730801 arm64_syscall-abi_sched_yield_FPSIMD pass
7557 10:03:54.734358 arm64_syscall-abi pass
7558 10:03:54.737563 arm64_tpidr2_skipped_TPIDR2_not_supported pass
7559 10:03:54.740705 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
7560 10:03:54.747327 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
7561 10:03:54.751035 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
7562 10:03:54.753999 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
7563 10:03:54.757222 arm64_tpidr2 pass
7564 10:03:54.761033 + ../../utils/send-to-lava.sh ./output/result.txt
7565 10:03:54.767434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
7566 10:03:54.768205 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
7568 10:03:54.773345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
7569 10:03:54.773609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
7571 10:03:54.780119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
7572 10:03:54.780402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
7574 10:03:54.786730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
7575 10:03:54.786994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
7577 10:03:54.792948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
7578 10:03:54.793210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
7580 10:03:54.812426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
7581 10:03:54.812692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
7583 10:03:54.856798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
7584 10:03:54.857140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
7586 10:03:54.905561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
7587 10:03:54.905920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
7589 10:03:54.960817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
7590 10:03:54.961193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
7592 10:03:55.005944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
7593 10:03:55.006302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
7595 10:03:55.067432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
7596 10:03:55.068204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
7598 10:03:55.125873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
7599 10:03:55.126147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
7601 10:03:55.175515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
7602 10:03:55.175797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
7604 10:03:55.224615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
7605 10:03:55.224953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
7607 10:03:55.269387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
7608 10:03:55.269657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
7610 10:03:55.313498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
7611 10:03:55.314189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
7613 10:03:55.365976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
7614 10:03:55.366654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
7616 10:03:55.412810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
7617 10:03:55.413172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
7619 10:03:55.460789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
7620 10:03:55.461464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
7622 10:03:55.502089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
7623 10:03:55.502401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
7625 10:03:55.544703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
7626 10:03:55.545113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
7628 10:03:55.585142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
7629 10:03:55.585962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
7631 10:03:55.634271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
7632 10:03:55.635205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
7634 10:03:55.671235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
7635 10:03:55.671567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
7637 10:03:55.716163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
7638 10:03:55.717026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
7640 10:03:55.764206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
7641 10:03:55.765067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
7643 10:03:55.815131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
7644 10:03:55.815878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
7646 10:03:55.860648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
7647 10:03:55.861519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
7649 10:03:55.929027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
7650 10:03:55.929821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
7652 10:03:55.979257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
7653 10:03:55.979537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
7655 10:03:56.025442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
7656 10:03:56.026114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
7658 10:03:56.082546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
7659 10:03:56.083217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
7661 10:03:56.139611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
7662 10:03:56.140285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
7664 10:03:56.189256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
7665 10:03:56.189528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
7667 10:03:56.232707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
7668 10:03:56.233051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
7670 10:03:56.274424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
7671 10:03:56.274701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
7673 10:03:56.319335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
7674 10:03:56.319623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
7676 10:03:56.366091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
7677 10:03:56.366431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
7679 10:03:56.406346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
7680 10:03:56.406616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
7682 10:03:56.447573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
7683 10:03:56.447897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
7685 10:03:56.493118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
7686 10:03:56.493799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
7688 10:03:56.544119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
7689 10:03:56.544938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
7691 10:03:56.589676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
7693 10:03:56.592156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
7694 10:03:56.625265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
7695 10:03:56.625542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
7697 10:03:56.670499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
7698 10:03:56.671533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
7700 10:03:56.715232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
7701 10:03:56.715995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
7703 10:03:56.762340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
7704 10:03:56.762713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
7706 10:03:56.802834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
7707 10:03:56.803121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
7709 10:03:56.849480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
7710 10:03:56.849757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
7712 10:03:56.890027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
7713 10:03:56.890360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
7715 10:03:56.935599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
7716 10:03:56.935882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
7718 10:03:56.982228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
7719 10:03:56.982502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
7721 10:03:57.027633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
7722 10:03:57.028001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
7724 10:03:57.083501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
7725 10:03:57.084347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
7727 10:03:57.136916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
7728 10:03:57.137739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
7730 10:03:57.198637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
7731 10:03:57.199465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
7733 10:03:57.254567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
7734 10:03:57.255256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
7736 10:03:57.314060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
7737 10:03:57.314735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
7739 10:03:57.371203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
7740 10:03:57.371914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
7742 10:03:57.427679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
7743 10:03:57.428354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
7745 10:03:57.479837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
7746 10:03:57.480510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
7748 10:03:57.535109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
7749 10:03:57.535810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
7751 10:03:57.591652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
7752 10:03:57.592436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
7754 10:03:57.645720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
7755 10:03:57.646420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
7757 10:03:57.697281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
7758 10:03:57.698047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
7760 10:03:57.745640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
7761 10:03:57.746481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
7763 10:03:57.785503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
7764 10:03:57.786498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
7766 10:03:57.830186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
7767 10:03:57.830468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
7769 10:03:57.875851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
7770 10:03:57.876140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
7772 10:03:57.916664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
7773 10:03:57.916950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
7775 10:03:57.961638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
7776 10:03:57.962069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
7778 10:03:58.011771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
7779 10:03:58.012496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
7781 10:03:58.065818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
7782 10:03:58.066583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
7784 10:03:58.117344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
7785 10:03:58.118187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
7787 10:03:58.166350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
7788 10:03:58.167108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
7790 10:03:58.214398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
7791 10:03:58.214665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
7793 10:03:58.257396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
7794 10:03:58.257666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
7796 10:03:58.299177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
7797 10:03:58.299512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
7799 10:03:58.341420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
7800 10:03:58.341695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
7802 10:03:58.384706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
7803 10:03:58.385155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
7805 10:03:58.435618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
7806 10:03:58.436307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
7808 10:03:58.478761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
7809 10:03:58.479519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
7811 10:03:58.530158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
7812 10:03:58.531041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
7814 10:03:58.578370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
7815 10:03:58.579042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
7817 10:03:58.626950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
7819 10:03:58.629761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
7820 10:03:58.673100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
7821 10:03:58.673380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
7823 10:03:58.712581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
7824 10:03:58.712965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
7826 10:03:58.755261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
7827 10:03:58.755537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
7829 10:03:58.792471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
7830 10:03:58.792737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
7832 10:03:58.829916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
7833 10:03:58.830206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
7835 10:03:58.869643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
7836 10:03:58.869945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
7838 10:03:58.907717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
7840 10:03:58.910485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
7841 10:03:58.951470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
7842 10:03:58.952152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
7844 10:03:58.998566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
7845 10:03:58.999240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
7847 10:03:59.046586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
7848 10:03:59.047487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
7850 10:03:59.101736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
7851 10:03:59.102477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
7853 10:03:59.156318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
7854 10:03:59.157076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
7856 10:03:59.209213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
7857 10:03:59.209892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
7859 10:03:59.259031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
7860 10:03:59.259761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
7862 10:03:59.308232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
7863 10:03:59.308901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
7865 10:03:59.354404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
7866 10:03:59.355100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
7868 10:03:59.402283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
7869 10:03:59.402958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
7871 10:03:59.454588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
7872 10:03:59.455265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
7874 10:03:59.502192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
7875 10:03:59.502866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
7877 10:03:59.549423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
7878 10:03:59.550121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
7880 10:03:59.595636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
7881 10:03:59.596403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
7883 10:03:59.647822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
7884 10:03:59.648492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
7886 10:03:59.700602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
7887 10:03:59.701264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
7889 10:03:59.753469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
7890 10:03:59.754142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
7892 10:03:59.801017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
7893 10:03:59.801913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
7895 10:03:59.848567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
7896 10:03:59.849355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
7898 10:03:59.893647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
7899 10:03:59.894362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
7901 10:03:59.935362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
7902 10:03:59.936129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
7904 10:03:59.982498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
7905 10:03:59.983362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
7907 10:04:00.038132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
7908 10:04:00.038853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
7910 10:04:00.088596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
7911 10:04:00.089286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
7913 10:04:00.135011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
7914 10:04:00.135723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
7916 10:04:00.183328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
7917 10:04:00.184089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
7919 10:04:00.233391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
7920 10:04:00.234065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
7922 10:04:00.277175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
7923 10:04:00.277507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
7925 10:04:00.320503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
7926 10:04:00.321180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
7928 10:04:00.373911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
7929 10:04:00.374577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
7931 10:04:00.424254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
7932 10:04:00.424926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
7934 10:04:00.475916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
7935 10:04:00.476590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
7937 10:04:00.524797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
7938 10:04:00.525548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
7940 10:04:00.580230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
7941 10:04:00.580903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
7943 10:04:00.626069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
7944 10:04:00.626887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
7946 10:04:00.678201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
7947 10:04:00.678475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
7949 10:04:00.717287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
7950 10:04:00.717566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
7952 10:04:00.759249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
7953 10:04:00.759555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
7955 10:04:00.806800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
7956 10:04:00.807529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
7958 10:04:00.853983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
7959 10:04:00.854312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
7961 10:04:00.892578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
7962 10:04:00.892875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
7964 10:04:00.939425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
7965 10:04:00.939936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
7967 10:04:00.977099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
7968 10:04:00.977385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
7970 10:04:01.017550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
7972 10:04:01.020717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
7973 10:04:01.056089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
7974 10:04:01.056369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
7976 10:04:01.107825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
7977 10:04:01.108513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
7979 10:04:01.163923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
7980 10:04:01.164716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
7982 10:04:01.220697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
7983 10:04:01.221520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
7985 10:04:01.276216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
7986 10:04:01.277029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
7988 10:04:01.337033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
7989 10:04:01.337799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
7991 10:04:01.386604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
7992 10:04:01.387275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
7994 10:04:01.449228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
7995 10:04:01.449998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
7997 10:04:01.507970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
7998 10:04:01.508841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
8000 10:04:01.557812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
8001 10:04:01.558488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
8003 10:04:01.601698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
8004 10:04:01.602398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
8006 10:04:01.650276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
8007 10:04:01.651027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
8009 10:04:01.698701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
8011 10:04:01.701746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
8012 10:04:01.757659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
8013 10:04:01.758566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
8015 10:04:01.810901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
8017 10:04:01.813951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
8018 10:04:01.869715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
8019 10:04:01.870464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
8021 10:04:01.918163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
8023 10:04:01.921340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
8024 10:04:01.966148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
8025 10:04:01.966584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
8027 10:04:02.008270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
8028 10:04:02.008572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
8030 10:04:02.047929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
8031 10:04:02.048819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
8033 10:04:02.097533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
8034 10:04:02.098278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
8036 10:04:02.148412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
8037 10:04:02.149126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
8039 10:04:02.202715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
8040 10:04:02.203471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
8042 10:04:02.258041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
8043 10:04:02.258371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
8045 10:04:02.302163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
8046 10:04:02.302453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
8048 10:04:02.343729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
8049 10:04:02.344455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
8051 10:04:02.388860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
8053 10:04:02.391679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
8054 10:04:02.433066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
8056 10:04:02.435691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
8057 10:04:02.481706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
8058 10:04:02.482045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
8060 10:04:02.530209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
8061 10:04:02.530567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
8063 10:04:02.573810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
8064 10:04:02.574417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
8066 10:04:02.626489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
8067 10:04:02.627260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
8069 10:04:02.676253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
8070 10:04:02.676927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
8072 10:04:02.719076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
8073 10:04:02.719782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
8075 10:04:02.768922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
8076 10:04:02.769593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
8078 10:04:02.815143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
8079 10:04:02.815855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
8081 10:04:02.859197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
8082 10:04:02.859908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
8084 10:04:02.911070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
8085 10:04:02.911773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
8087 10:04:02.957710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
8088 10:04:02.958395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
8090 10:04:03.008150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
8091 10:04:03.008919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
8093 10:04:03.057650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
8094 10:04:03.058622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
8096 10:04:03.100106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
8097 10:04:03.100395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
8099 10:04:03.137480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
8100 10:04:03.137900 + set +x
8101 10:04:03.138485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
8103 10:04:03.143969 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14407643_1.6.2.3.5>
8104 10:04:03.144633 Received signal: <ENDRUN> 1_kselftest-arm64 14407643_1.6.2.3.5
8105 10:04:03.144998 Ending use of test pattern.
8106 10:04:03.145313 Ending test lava.1_kselftest-arm64 (14407643_1.6.2.3.5), duration 32.57
8108 10:04:03.146996 <LAVA_TEST_RUNNER EXIT>
8109 10:04:03.147686 ok: lava_test_shell seems to have completed
8110 10:04:03.153110 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
8111 10:04:03.153971 end: 3.1 lava-test-shell (duration 00:00:33) [common]
8112 10:04:03.154496 end: 3 lava-test-retry (duration 00:00:33) [common]
8113 10:04:03.154932 start: 4 finalize (timeout 00:07:31) [common]
8114 10:04:03.155374 start: 4.1 power-off (timeout 00:00:30) [common]
8115 10:04:03.156194 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0', '--port=1', '--command=off']
8116 10:04:04.420862 >> Command sent successfully.
8117 10:04:04.431341 Returned 0 in 1 seconds
8118 10:04:04.532688 end: 4.1 power-off (duration 00:00:01) [common]
8120 10:04:04.534251 start: 4.2 read-feedback (timeout 00:07:29) [common]
8121 10:04:04.535681 Listened to connection for namespace 'common' for up to 1s
8122 10:04:05.535812 Finalising connection for namespace 'common'
8123 10:04:05.536585 Disconnecting from shell: Finalise
8124 10:04:05.537009 / #
8125 10:04:05.637993 end: 4.2 read-feedback (duration 00:00:01) [common]
8126 10:04:05.638755 end: 4 finalize (duration 00:00:02) [common]
8127 10:04:05.639372 Cleaning after the job
8128 10:04:05.639941 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/ramdisk
8129 10:04:05.650351 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/kernel
8130 10:04:05.683207 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/dtb
8131 10:04:05.683589 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/nfsrootfs
8132 10:04:05.755191 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407643/tftp-deploy-suje0j50/modules
8133 10:04:05.761250 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407643
8134 10:04:06.374254 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407643
8135 10:04:06.374448 Job finished correctly