Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 09:28:14.596056 lava-dispatcher, installed at version: 2024.03
2 09:28:14.596261 start: 0 validate
3 09:28:14.596396 Start time: 2024-06-18 09:28:14.596388+00:00 (UTC)
4 09:28:14.596514 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:28:14.596644 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:28:14.856926 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:28:14.857100 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:28:15.120298 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:28:15.120471 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:28:15.372290 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:28:15.372448 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:28:15.622381 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:28:15.622557 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:28:15.873594 validate duration: 1.28
16 09:28:15.873876 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:28:15.873980 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:28:15.874066 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:28:15.874190 Not decompressing ramdisk as can be used compressed.
20 09:28:15.874273 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 09:28:15.874336 saving as /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/ramdisk/initrd.cpio.gz
22 09:28:15.874400 total size: 5628169 (5 MB)
23 09:28:15.875425 progress 0 % (0 MB)
24 09:28:15.877018 progress 5 % (0 MB)
25 09:28:15.878621 progress 10 % (0 MB)
26 09:28:15.880021 progress 15 % (0 MB)
27 09:28:15.881743 progress 20 % (1 MB)
28 09:28:15.883203 progress 25 % (1 MB)
29 09:28:15.884756 progress 30 % (1 MB)
30 09:28:15.886330 progress 35 % (1 MB)
31 09:28:15.887723 progress 40 % (2 MB)
32 09:28:15.889253 progress 45 % (2 MB)
33 09:28:15.890650 progress 50 % (2 MB)
34 09:28:15.892173 progress 55 % (2 MB)
35 09:28:15.893891 progress 60 % (3 MB)
36 09:28:15.895280 progress 65 % (3 MB)
37 09:28:15.896874 progress 70 % (3 MB)
38 09:28:15.898337 progress 75 % (4 MB)
39 09:28:15.899855 progress 80 % (4 MB)
40 09:28:15.901206 progress 85 % (4 MB)
41 09:28:15.902802 progress 90 % (4 MB)
42 09:28:15.904333 progress 95 % (5 MB)
43 09:28:15.905796 progress 100 % (5 MB)
44 09:28:15.906006 5 MB downloaded in 0.03 s (169.83 MB/s)
45 09:28:15.906159 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:28:15.906401 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:28:15.906487 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:28:15.906571 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:28:15.906708 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:28:15.906780 saving as /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/kernel/Image
52 09:28:15.906841 total size: 54813184 (52 MB)
53 09:28:15.906902 No compression specified
54 09:28:15.908058 progress 0 % (0 MB)
55 09:28:15.921892 progress 5 % (2 MB)
56 09:28:15.935992 progress 10 % (5 MB)
57 09:28:15.950101 progress 15 % (7 MB)
58 09:28:15.964484 progress 20 % (10 MB)
59 09:28:15.978700 progress 25 % (13 MB)
60 09:28:15.992888 progress 30 % (15 MB)
61 09:28:16.006988 progress 35 % (18 MB)
62 09:28:16.021206 progress 40 % (20 MB)
63 09:28:16.035181 progress 45 % (23 MB)
64 09:28:16.049346 progress 50 % (26 MB)
65 09:28:16.063655 progress 55 % (28 MB)
66 09:28:16.077894 progress 60 % (31 MB)
67 09:28:16.092109 progress 65 % (34 MB)
68 09:28:16.106009 progress 70 % (36 MB)
69 09:28:16.120042 progress 75 % (39 MB)
70 09:28:16.134217 progress 80 % (41 MB)
71 09:28:16.148127 progress 85 % (44 MB)
72 09:28:16.162254 progress 90 % (47 MB)
73 09:28:16.176456 progress 95 % (49 MB)
74 09:28:16.190208 progress 100 % (52 MB)
75 09:28:16.190484 52 MB downloaded in 0.28 s (184.30 MB/s)
76 09:28:16.190638 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:28:16.190870 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:28:16.190958 start: 1.3 download-retry (timeout 00:10:00) [common]
80 09:28:16.191042 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 09:28:16.191178 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:28:16.191246 saving as /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/dtb/mt8192-asurada-spherion-r0.dtb
83 09:28:16.191306 total size: 47258 (0 MB)
84 09:28:16.191367 No compression specified
85 09:28:16.192535 progress 69 % (0 MB)
86 09:28:16.192824 progress 100 % (0 MB)
87 09:28:16.193010 0 MB downloaded in 0.00 s (26.50 MB/s)
88 09:28:16.193180 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:28:16.193473 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:28:16.193560 start: 1.4 download-retry (timeout 00:10:00) [common]
92 09:28:16.193644 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 09:28:16.193758 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 09:28:16.193825 saving as /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/nfsrootfs/full.rootfs.tar
95 09:28:16.193886 total size: 120894716 (115 MB)
96 09:28:16.193948 Using unxz to decompress xz
97 09:28:16.198073 progress 0 % (0 MB)
98 09:28:16.549566 progress 5 % (5 MB)
99 09:28:16.909901 progress 10 % (11 MB)
100 09:28:17.264722 progress 15 % (17 MB)
101 09:28:17.602850 progress 20 % (23 MB)
102 09:28:17.903145 progress 25 % (28 MB)
103 09:28:18.280794 progress 30 % (34 MB)
104 09:28:18.632776 progress 35 % (40 MB)
105 09:28:18.803920 progress 40 % (46 MB)
106 09:28:18.986105 progress 45 % (51 MB)
107 09:28:19.309402 progress 50 % (57 MB)
108 09:28:19.703773 progress 55 % (63 MB)
109 09:28:20.064832 progress 60 % (69 MB)
110 09:28:20.425446 progress 65 % (74 MB)
111 09:28:20.786163 progress 70 % (80 MB)
112 09:28:21.158310 progress 75 % (86 MB)
113 09:28:21.512054 progress 80 % (92 MB)
114 09:28:21.866883 progress 85 % (98 MB)
115 09:28:22.225837 progress 90 % (103 MB)
116 09:28:22.563159 progress 95 % (109 MB)
117 09:28:22.929591 progress 100 % (115 MB)
118 09:28:22.935023 115 MB downloaded in 6.74 s (17.10 MB/s)
119 09:28:22.935289 end: 1.4.1 http-download (duration 00:00:07) [common]
121 09:28:22.935559 end: 1.4 download-retry (duration 00:00:07) [common]
122 09:28:22.935655 start: 1.5 download-retry (timeout 00:09:53) [common]
123 09:28:22.935742 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 09:28:22.935896 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:28:22.935969 saving as /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/modules/modules.tar
126 09:28:22.936031 total size: 8619356 (8 MB)
127 09:28:22.936096 Using unxz to decompress xz
128 09:28:22.940343 progress 0 % (0 MB)
129 09:28:22.961100 progress 5 % (0 MB)
130 09:28:22.987330 progress 10 % (0 MB)
131 09:28:23.014224 progress 15 % (1 MB)
132 09:28:23.040437 progress 20 % (1 MB)
133 09:28:23.067641 progress 25 % (2 MB)
134 09:28:23.093752 progress 30 % (2 MB)
135 09:28:23.119971 progress 35 % (2 MB)
136 09:28:23.145342 progress 40 % (3 MB)
137 09:28:23.171088 progress 45 % (3 MB)
138 09:28:23.195901 progress 50 % (4 MB)
139 09:28:23.221673 progress 55 % (4 MB)
140 09:28:23.246944 progress 60 % (4 MB)
141 09:28:23.272227 progress 65 % (5 MB)
142 09:28:23.301974 progress 70 % (5 MB)
143 09:28:23.328183 progress 75 % (6 MB)
144 09:28:23.352558 progress 80 % (6 MB)
145 09:28:23.377896 progress 85 % (7 MB)
146 09:28:23.402846 progress 90 % (7 MB)
147 09:28:23.433240 progress 95 % (7 MB)
148 09:28:23.465923 progress 100 % (8 MB)
149 09:28:23.470876 8 MB downloaded in 0.53 s (15.37 MB/s)
150 09:28:23.471210 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:28:23.471635 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:28:23.471764 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 09:28:23.471891 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 09:28:27.036731 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14407666/extract-nfsrootfs-m2jz1nta
156 09:28:27.036923 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 09:28:27.037030 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 09:28:27.037208 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm
159 09:28:27.037349 makedir: /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin
160 09:28:27.037454 makedir: /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/tests
161 09:28:27.037554 makedir: /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/results
162 09:28:27.037654 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-add-keys
163 09:28:27.037812 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-add-sources
164 09:28:27.037957 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-background-process-start
165 09:28:27.038102 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-background-process-stop
166 09:28:27.038228 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-common-functions
167 09:28:27.038354 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-echo-ipv4
168 09:28:27.038477 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-install-packages
169 09:28:27.038602 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-installed-packages
170 09:28:27.038729 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-os-build
171 09:28:27.038855 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-probe-channel
172 09:28:27.038980 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-probe-ip
173 09:28:27.039101 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-target-ip
174 09:28:27.039222 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-target-mac
175 09:28:27.039342 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-target-storage
176 09:28:27.039465 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-test-case
177 09:28:27.039588 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-test-event
178 09:28:27.039709 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-test-feedback
179 09:28:27.039831 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-test-raise
180 09:28:27.040006 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-test-reference
181 09:28:27.040137 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-test-runner
182 09:28:27.040260 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-test-set
183 09:28:27.040385 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-test-shell
184 09:28:27.040509 Updating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-add-keys (debian)
185 09:28:27.040655 Updating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-add-sources (debian)
186 09:28:27.040792 Updating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-install-packages (debian)
187 09:28:27.040928 Updating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-installed-packages (debian)
188 09:28:27.041062 Updating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/bin/lava-os-build (debian)
189 09:28:27.041178 Creating /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/environment
190 09:28:27.041388 LAVA metadata
191 09:28:27.041461 - LAVA_JOB_ID=14407666
192 09:28:27.041524 - LAVA_DISPATCHER_IP=192.168.201.1
193 09:28:27.041626 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 09:28:27.041694 skipped lava-vland-overlay
195 09:28:27.041770 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 09:28:27.041850 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 09:28:27.041911 skipped lava-multinode-overlay
198 09:28:27.041993 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 09:28:27.042071 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 09:28:27.042145 Loading test definitions
201 09:28:27.042235 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 09:28:27.042305 Using /lava-14407666 at stage 0
203 09:28:27.042586 uuid=14407666_1.6.2.3.1 testdef=None
204 09:28:27.042675 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 09:28:27.042759 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 09:28:27.043211 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 09:28:27.043431 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 09:28:27.043980 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 09:28:27.044212 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 09:28:27.044744 runner path: /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/0/tests/0_timesync-off test_uuid 14407666_1.6.2.3.1
213 09:28:27.044903 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 09:28:27.045129 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 09:28:27.045201 Using /lava-14407666 at stage 0
217 09:28:27.045304 Fetching tests from https://github.com/kernelci/test-definitions.git
218 09:28:27.045392 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/0/tests/1_kselftest-arm64'
219 09:28:29.879383 Running '/usr/bin/git checkout kernelci.org
220 09:28:30.027661 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 09:28:30.028389 uuid=14407666_1.6.2.3.5 testdef=None
222 09:28:30.028555 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 09:28:30.028802 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 09:28:30.029577 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 09:28:30.029810 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 09:28:30.030808 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 09:28:30.031122 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 09:28:30.032030 runner path: /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/0/tests/1_kselftest-arm64 test_uuid 14407666_1.6.2.3.5
232 09:28:30.032122 BOARD='mt8192-asurada-spherion-r0'
233 09:28:30.032185 BRANCH='cip'
234 09:28:30.032244 SKIPFILE='/dev/null'
235 09:28:30.032302 SKIP_INSTALL='True'
236 09:28:30.032357 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 09:28:30.032414 TST_CASENAME=''
238 09:28:30.032468 TST_CMDFILES='arm64'
239 09:28:30.032606 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 09:28:30.032810 Creating lava-test-runner.conf files
242 09:28:30.032876 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407666/lava-overlay-17ha44hm/lava-14407666/0 for stage 0
243 09:28:30.032967 - 0_timesync-off
244 09:28:30.033033 - 1_kselftest-arm64
245 09:28:30.033126 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 09:28:30.033216 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 09:28:37.554268 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 09:28:37.554429 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 09:28:37.554522 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 09:28:37.554622 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 09:28:37.554712 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 09:28:37.725465 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 09:28:37.725871 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 09:28:37.725985 extracting modules file /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407666/extract-nfsrootfs-m2jz1nta
255 09:28:37.940298 extracting modules file /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407666/extract-overlay-ramdisk-316mhmnc/ramdisk
256 09:28:38.162764 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 09:28:38.162941 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 09:28:38.163039 [common] Applying overlay to NFS
259 09:28:38.163111 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407666/compress-overlay-ksj9_emw/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407666/extract-nfsrootfs-m2jz1nta
260 09:28:39.110374 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 09:28:39.110546 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 09:28:39.110642 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 09:28:39.110731 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 09:28:39.110813 Building ramdisk /var/lib/lava/dispatcher/tmp/14407666/extract-overlay-ramdisk-316mhmnc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407666/extract-overlay-ramdisk-316mhmnc/ramdisk
265 09:28:39.418815 >> 130466 blocks
266 09:28:41.452547 rename /var/lib/lava/dispatcher/tmp/14407666/extract-overlay-ramdisk-316mhmnc/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/ramdisk/ramdisk.cpio.gz
267 09:28:41.452986 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 09:28:41.453109 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 09:28:41.453211 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 09:28:41.453357 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/kernel/Image']
271 09:28:54.956216 Returned 0 in 13 seconds
272 09:28:55.057185 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/kernel/image.itb
273 09:28:55.408482 output: FIT description: Kernel Image image with one or more FDT blobs
274 09:28:55.408871 output: Created: Tue Jun 18 10:28:55 2024
275 09:28:55.408956 output: Image 0 (kernel-1)
276 09:28:55.409020 output: Description:
277 09:28:55.409085 output: Created: Tue Jun 18 10:28:55 2024
278 09:28:55.409150 output: Type: Kernel Image
279 09:28:55.409211 output: Compression: lzma compressed
280 09:28:55.409276 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
281 09:28:55.409335 output: Architecture: AArch64
282 09:28:55.409393 output: OS: Linux
283 09:28:55.409451 output: Load Address: 0x00000000
284 09:28:55.409511 output: Entry Point: 0x00000000
285 09:28:55.409568 output: Hash algo: crc32
286 09:28:55.409623 output: Hash value: 4137a6e7
287 09:28:55.409675 output: Image 1 (fdt-1)
288 09:28:55.409730 output: Description: mt8192-asurada-spherion-r0
289 09:28:55.409784 output: Created: Tue Jun 18 10:28:55 2024
290 09:28:55.409840 output: Type: Flat Device Tree
291 09:28:55.409895 output: Compression: uncompressed
292 09:28:55.409947 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 09:28:55.410000 output: Architecture: AArch64
294 09:28:55.410052 output: Hash algo: crc32
295 09:28:55.410105 output: Hash value: 0f8e4d2e
296 09:28:55.410156 output: Image 2 (ramdisk-1)
297 09:28:55.410208 output: Description: unavailable
298 09:28:55.410260 output: Created: Tue Jun 18 10:28:55 2024
299 09:28:55.410314 output: Type: RAMDisk Image
300 09:28:55.410366 output: Compression: Unknown Compression
301 09:28:55.410418 output: Data Size: 18734933 Bytes = 18295.83 KiB = 17.87 MiB
302 09:28:55.410471 output: Architecture: AArch64
303 09:28:55.410523 output: OS: Linux
304 09:28:55.410575 output: Load Address: unavailable
305 09:28:55.410627 output: Entry Point: unavailable
306 09:28:55.410679 output: Hash algo: crc32
307 09:28:55.410730 output: Hash value: abc67ee1
308 09:28:55.410783 output: Default Configuration: 'conf-1'
309 09:28:55.410835 output: Configuration 0 (conf-1)
310 09:28:55.410887 output: Description: mt8192-asurada-spherion-r0
311 09:28:55.410940 output: Kernel: kernel-1
312 09:28:55.410992 output: Init Ramdisk: ramdisk-1
313 09:28:55.411044 output: FDT: fdt-1
314 09:28:55.411096 output: Loadables: kernel-1
315 09:28:55.411147 output:
316 09:28:55.411352 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 09:28:55.411447 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 09:28:55.411600 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 09:28:55.411697 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 09:28:55.411778 No LXC device requested
321 09:28:55.411854 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 09:28:55.411940 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 09:28:55.412017 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 09:28:55.412084 Checking files for TFTP limit of 4294967296 bytes.
325 09:28:55.412579 end: 1 tftp-deploy (duration 00:00:40) [common]
326 09:28:55.412684 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 09:28:55.412775 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 09:28:55.412901 substitutions:
329 09:28:55.412967 - {DTB}: 14407666/tftp-deploy-j8twixqu/dtb/mt8192-asurada-spherion-r0.dtb
330 09:28:55.413032 - {INITRD}: 14407666/tftp-deploy-j8twixqu/ramdisk/ramdisk.cpio.gz
331 09:28:55.413091 - {KERNEL}: 14407666/tftp-deploy-j8twixqu/kernel/Image
332 09:28:55.413148 - {LAVA_MAC}: None
333 09:28:55.413223 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14407666/extract-nfsrootfs-m2jz1nta
334 09:28:55.413304 - {NFS_SERVER_IP}: 192.168.201.1
335 09:28:55.413359 - {PRESEED_CONFIG}: None
336 09:28:55.413414 - {PRESEED_LOCAL}: None
337 09:28:55.413468 - {RAMDISK}: 14407666/tftp-deploy-j8twixqu/ramdisk/ramdisk.cpio.gz
338 09:28:55.413540 - {ROOT_PART}: None
339 09:28:55.413705 - {ROOT}: None
340 09:28:55.413806 - {SERVER_IP}: 192.168.201.1
341 09:28:55.413879 - {TEE}: None
342 09:28:55.413935 Parsed boot commands:
343 09:28:55.413990 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 09:28:55.414181 Parsed boot commands: tftpboot 192.168.201.1 14407666/tftp-deploy-j8twixqu/kernel/image.itb 14407666/tftp-deploy-j8twixqu/kernel/cmdline
345 09:28:55.414271 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 09:28:55.414356 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 09:28:55.414455 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 09:28:55.414547 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 09:28:55.414624 Not connected, no need to disconnect.
350 09:28:55.414699 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 09:28:55.414784 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 09:28:55.414853 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 09:28:55.418684 Setting prompt string to ['lava-test: # ']
354 09:28:55.419057 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 09:28:55.419167 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 09:28:55.419267 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 09:28:55.419362 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 09:28:55.419536 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
359 09:29:09.512160 Returned 0 in 14 seconds
360 09:29:09.613494 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 09:29:09.615399 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 09:29:09.615949 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 09:29:09.616443 Setting prompt string to 'Starting depthcharge on Spherion...'
365 09:29:09.616827 Changing prompt to 'Starting depthcharge on Spherion...'
366 09:29:09.617206 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 09:29:09.618277 [Enter `^Ec?' for help]
368 09:29:09.618357
369 09:29:09.618426
370 09:29:09.618492 F0: 102B 0000
371 09:29:09.618553
372 09:29:09.618612 F3: 1001 0000 [0200]
373 09:29:09.618669
374 09:29:09.618726 F3: 1001 0000
375 09:29:09.618781
376 09:29:09.618834 F7: 102D 0000
377 09:29:09.618888
378 09:29:09.618940 F1: 0000 0000
379 09:29:09.618993
380 09:29:09.619046 V0: 0000 0000 [0001]
381 09:29:09.619098
382 09:29:09.619151 00: 0007 8000
383 09:29:09.619206
384 09:29:09.619259 01: 0000 0000
385 09:29:09.619313
386 09:29:09.619367 BP: 0C00 0209 [0000]
387 09:29:09.619420
388 09:29:09.619473 G0: 1182 0000
389 09:29:09.619525
390 09:29:09.619577 EC: 0000 0021 [4000]
391 09:29:09.619630
392 09:29:09.619683 S7: 0000 0000 [0000]
393 09:29:09.619735
394 09:29:09.619787 CC: 0000 0000 [0001]
395 09:29:09.619839
396 09:29:09.619892 T0: 0000 0040 [010F]
397 09:29:09.619945
398 09:29:09.619997 Jump to BL
399 09:29:09.620048
400 09:29:09.620100
401 09:29:09.620152
402 09:29:09.620204 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 09:29:09.620260 ARM64: Exception handlers installed.
404 09:29:09.620317 ARM64: Testing exception
405 09:29:09.620370 ARM64: Done test exception
406 09:29:09.620423 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 09:29:09.620476 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 09:29:09.620530 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 09:29:09.620598 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 09:29:09.620655 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 09:29:09.620711 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 09:29:09.620766 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 09:29:09.620820 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 09:29:09.620873 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 09:29:09.620926 WDT: Last reset was cold boot
416 09:29:09.620979 SPI1(PAD0) initialized at 2873684 Hz
417 09:29:09.621032 SPI5(PAD0) initialized at 992727 Hz
418 09:29:09.621085 VBOOT: Loading verstage.
419 09:29:09.621137 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 09:29:09.621190 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 09:29:09.621243 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 09:29:09.621328 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 09:29:09.621396 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 09:29:09.621450 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 09:29:09.621502 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 09:29:09.621556
427 09:29:09.621608
428 09:29:09.621661 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 09:29:09.621715 ARM64: Exception handlers installed.
430 09:29:09.621768 ARM64: Testing exception
431 09:29:09.621821 ARM64: Done test exception
432 09:29:09.621873 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 09:29:09.621926 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 09:29:09.621979 Probing TPM: . done!
435 09:29:09.622032 TPM ready after 0 ms
436 09:29:09.622085 Connected to device vid:did:rid of 1ae0:0028:00
437 09:29:09.622138 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
438 09:29:09.622191 Initialized TPM device CR50 revision 0
439 09:29:09.622244 tlcl_send_startup: Startup return code is 0
440 09:29:09.622297 TPM: setup succeeded
441 09:29:09.622351 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 09:29:09.622404 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 09:29:09.622457 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 09:29:09.622510 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 09:29:09.622564 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 09:29:09.622617 in-header: 03 07 00 00 08 00 00 00
447 09:29:09.622670 in-data: aa e4 47 04 13 02 00 00
448 09:29:09.622727 Chrome EC: UHEPI supported
449 09:29:09.622780 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 09:29:09.622834 in-header: 03 a9 00 00 08 00 00 00
451 09:29:09.622887 in-data: 84 60 60 08 00 00 00 00
452 09:29:09.622939 Phase 1
453 09:29:09.622992 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 09:29:09.623046 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 09:29:09.623099 VB2:vb2_check_recovery() Recovery was requested manually
456 09:29:09.623152 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 09:29:09.623205 Recovery requested (1009000e)
458 09:29:09.623258 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 09:29:09.623311 tlcl_extend: response is 0
460 09:29:09.623364 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 09:29:09.623418 tlcl_extend: response is 0
462 09:29:09.623470 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 09:29:09.623523 read SPI 0x210d4 0x2173b: 15139 us, 9050 KB/s, 72.400 Mbps
464 09:29:09.623577 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 09:29:09.623629
466 09:29:09.623681
467 09:29:09.623733 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 09:29:09.623787 ARM64: Exception handlers installed.
469 09:29:09.623840 ARM64: Testing exception
470 09:29:09.623893 ARM64: Done test exception
471 09:29:09.623946 pmic_efuse_setting: Set efuses in 11 msecs
472 09:29:09.623999 pmwrap_interface_init: Select PMIF_VLD_RDY
473 09:29:09.624051 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 09:29:09.624104 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 09:29:09.624344 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 09:29:09.624404 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 09:29:09.624458 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 09:29:09.624511 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 09:29:09.624564 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 09:29:09.624635 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 09:29:09.624689 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 09:29:09.624772 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 09:29:09.624839 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 09:29:09.624891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 09:29:09.624944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 09:29:09.624997 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 09:29:09.625050 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 09:29:09.625103 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 09:29:09.625156 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 09:29:09.625209 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 09:29:09.625270 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 09:29:09.625325 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 09:29:09.625377 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 09:29:09.625430 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 09:29:09.625483 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 09:29:09.625535 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 09:29:09.625588 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 09:29:09.625641 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 09:29:09.625693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 09:29:09.625746 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 09:29:09.625799 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 09:29:09.625851 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 09:29:09.625904 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 09:29:09.625957 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 09:29:09.626010 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 09:29:09.626062 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 09:29:09.626114 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 09:29:09.626167 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 09:29:09.626220 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 09:29:09.626272 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 09:29:09.626324 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 09:29:09.626377 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 09:29:09.626430 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 09:29:09.626483 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 09:29:09.626535 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 09:29:09.626588 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 09:29:09.626641 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 09:29:09.626693 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 09:29:09.626749 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 09:29:09.626804 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 09:29:09.626857 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 09:29:09.626910 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 09:29:09.626962 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 09:29:09.627014 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 09:29:09.627068 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 09:29:09.627121 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 09:29:09.627175 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 09:29:09.627228 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 09:29:09.627282 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 09:29:09.627334 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 09:29:09.627388 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 09:29:09.627441 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
533 09:29:09.627493 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 09:29:09.627546 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
535 09:29:09.627599 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 09:29:09.627652 [RTC]rtc_get_frequency_meter,154: input=15, output=853
537 09:29:09.627704 [RTC]rtc_get_frequency_meter,154: input=7, output=724
538 09:29:09.627757 [RTC]rtc_get_frequency_meter,154: input=11, output=790
539 09:29:09.627810 [RTC]rtc_get_frequency_meter,154: input=13, output=821
540 09:29:09.627863 [RTC]rtc_get_frequency_meter,154: input=12, output=806
541 09:29:09.627915 [RTC]rtc_get_frequency_meter,154: input=11, output=789
542 09:29:09.627967 [RTC]rtc_get_frequency_meter,154: input=12, output=805
543 09:29:09.628020 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
544 09:29:09.628073 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
545 09:29:09.628311 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 09:29:09.628372 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 09:29:09.628427 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 09:29:09.628480 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 09:29:09.628533 ADC[4]: Raw value=905172 ID=7
550 09:29:09.628587 ADC[3]: Raw value=213916 ID=1
551 09:29:09.628639 RAM Code: 0x71
552 09:29:09.628691 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 09:29:09.628814 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 09:29:09.628893 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 09:29:09.628981 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 09:29:09.629035 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 09:29:09.629089 in-header: 03 07 00 00 08 00 00 00
558 09:29:09.629142 in-data: aa e4 47 04 13 02 00 00
559 09:29:09.629195 Chrome EC: UHEPI supported
560 09:29:09.629248 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 09:29:09.629342 in-header: 03 a9 00 00 08 00 00 00
562 09:29:09.629396 in-data: 84 60 60 08 00 00 00 00
563 09:29:09.629448 MRC: failed to locate region type 0.
564 09:29:09.629502 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 09:29:09.629555 DRAM-K: Running full calibration
566 09:29:09.629608 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 09:29:09.629662 header.status = 0x0
568 09:29:09.629714 header.version = 0x6 (expected: 0x6)
569 09:29:09.629767 header.size = 0xd00 (expected: 0xd00)
570 09:29:09.629820 header.flags = 0x0
571 09:29:09.629872 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 09:29:09.629926 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
573 09:29:09.629979 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 09:29:09.630033 dram_init: ddr_geometry: 2
575 09:29:09.630086 [EMI] MDL number = 2
576 09:29:09.630138 [EMI] Get MDL freq = 0
577 09:29:09.630191 dram_init: ddr_type: 0
578 09:29:09.630243 is_discrete_lpddr4: 1
579 09:29:09.630296 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 09:29:09.630348
581 09:29:09.630400
582 09:29:09.630452 [Bian_co] ETT version 0.0.0.1
583 09:29:09.630505 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 09:29:09.630558
585 09:29:09.630610 dramc_set_vcore_voltage set vcore to 650000
586 09:29:09.630663 Read voltage for 800, 4
587 09:29:09.630715 Vio18 = 0
588 09:29:09.630768 Vcore = 650000
589 09:29:09.630820 Vdram = 0
590 09:29:09.630873 Vddq = 0
591 09:29:09.630925 Vmddr = 0
592 09:29:09.630976 dram_init: config_dvfs: 1
593 09:29:09.631029 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 09:29:09.631082 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 09:29:09.631135 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 09:29:09.631187 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 09:29:09.631240 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 09:29:09.631292 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 09:29:09.631345 MEM_TYPE=3, freq_sel=18
600 09:29:09.631397 sv_algorithm_assistance_LP4_1600
601 09:29:09.631450 ============ PULL DRAM RESETB DOWN ============
602 09:29:09.631505 ========== PULL DRAM RESETB DOWN end =========
603 09:29:09.631558 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 09:29:09.631610 ===================================
605 09:29:09.631664 LPDDR4 DRAM CONFIGURATION
606 09:29:09.631716 ===================================
607 09:29:09.631769 EX_ROW_EN[0] = 0x0
608 09:29:09.631821 EX_ROW_EN[1] = 0x0
609 09:29:09.631872 LP4Y_EN = 0x0
610 09:29:09.631925 WORK_FSP = 0x0
611 09:29:09.631977 WL = 0x2
612 09:29:09.632029 RL = 0x2
613 09:29:09.632081 BL = 0x2
614 09:29:09.632133 RPST = 0x0
615 09:29:09.632185 RD_PRE = 0x0
616 09:29:09.632237 WR_PRE = 0x1
617 09:29:09.632289 WR_PST = 0x0
618 09:29:09.632341 DBI_WR = 0x0
619 09:29:09.632393 DBI_RD = 0x0
620 09:29:09.632445 OTF = 0x1
621 09:29:09.632497 ===================================
622 09:29:09.632550 ===================================
623 09:29:09.632603 ANA top config
624 09:29:09.632654 ===================================
625 09:29:09.632746 DLL_ASYNC_EN = 0
626 09:29:09.632827 ALL_SLAVE_EN = 1
627 09:29:09.632880 NEW_RANK_MODE = 1
628 09:29:09.632932 DLL_IDLE_MODE = 1
629 09:29:09.632985 LP45_APHY_COMB_EN = 1
630 09:29:09.633037 TX_ODT_DIS = 1
631 09:29:09.633089 NEW_8X_MODE = 1
632 09:29:09.633142 ===================================
633 09:29:09.633195 ===================================
634 09:29:09.633275 data_rate = 1600
635 09:29:09.633343 CKR = 1
636 09:29:09.633395 DQ_P2S_RATIO = 8
637 09:29:09.633448 ===================================
638 09:29:09.633501 CA_P2S_RATIO = 8
639 09:29:09.633553 DQ_CA_OPEN = 0
640 09:29:09.633605 DQ_SEMI_OPEN = 0
641 09:29:09.633657 CA_SEMI_OPEN = 0
642 09:29:09.633709 CA_FULL_RATE = 0
643 09:29:09.633761 DQ_CKDIV4_EN = 1
644 09:29:09.633813 CA_CKDIV4_EN = 1
645 09:29:09.633865 CA_PREDIV_EN = 0
646 09:29:09.633917 PH8_DLY = 0
647 09:29:09.633969 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 09:29:09.634033 DQ_AAMCK_DIV = 4
649 09:29:09.634088 CA_AAMCK_DIV = 4
650 09:29:09.634141 CA_ADMCK_DIV = 4
651 09:29:09.634193 DQ_TRACK_CA_EN = 0
652 09:29:09.634245 CA_PICK = 800
653 09:29:09.634326 CA_MCKIO = 800
654 09:29:09.634378 MCKIO_SEMI = 0
655 09:29:09.634431 PLL_FREQ = 3068
656 09:29:09.634483 DQ_UI_PI_RATIO = 32
657 09:29:09.634536 CA_UI_PI_RATIO = 0
658 09:29:09.634588 ===================================
659 09:29:09.634641 ===================================
660 09:29:09.634694 memory_type:LPDDR4
661 09:29:09.634746 GP_NUM : 10
662 09:29:09.634798 SRAM_EN : 1
663 09:29:09.634871 MD32_EN : 0
664 09:29:09.634925 ===================================
665 09:29:09.635186 [ANA_INIT] >>>>>>>>>>>>>>
666 09:29:09.635249 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 09:29:09.635306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 09:29:09.635359 ===================================
669 09:29:09.635412 data_rate = 1600,PCW = 0X7600
670 09:29:09.635465 ===================================
671 09:29:09.635518 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 09:29:09.635571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 09:29:09.635624 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 09:29:09.635677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 09:29:09.635730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 09:29:09.635783 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 09:29:09.635836 [ANA_INIT] flow start
678 09:29:09.635888 [ANA_INIT] PLL >>>>>>>>
679 09:29:09.635941 [ANA_INIT] PLL <<<<<<<<
680 09:29:09.635993 [ANA_INIT] MIDPI >>>>>>>>
681 09:29:09.636045 [ANA_INIT] MIDPI <<<<<<<<
682 09:29:09.636096 [ANA_INIT] DLL >>>>>>>>
683 09:29:09.636181 [ANA_INIT] flow end
684 09:29:09.636234 ============ LP4 DIFF to SE enter ============
685 09:29:09.636287 ============ LP4 DIFF to SE exit ============
686 09:29:09.636340 [ANA_INIT] <<<<<<<<<<<<<
687 09:29:09.636393 [Flow] Enable top DCM control >>>>>
688 09:29:09.636446 [Flow] Enable top DCM control <<<<<
689 09:29:09.636498 Enable DLL master slave shuffle
690 09:29:09.636550 ==============================================================
691 09:29:09.636603 Gating Mode config
692 09:29:09.636655 ==============================================================
693 09:29:09.636709 Config description:
694 09:29:09.636796 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 09:29:09.636850 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 09:29:09.636904 SELPH_MODE 0: By rank 1: By Phase
697 09:29:09.636957 ==============================================================
698 09:29:09.637010 GAT_TRACK_EN = 1
699 09:29:09.637063 RX_GATING_MODE = 2
700 09:29:09.637115 RX_GATING_TRACK_MODE = 2
701 09:29:09.637167 SELPH_MODE = 1
702 09:29:09.637219 PICG_EARLY_EN = 1
703 09:29:09.637309 VALID_LAT_VALUE = 1
704 09:29:09.637364 ==============================================================
705 09:29:09.637417 Enter into Gating configuration >>>>
706 09:29:09.637469 Exit from Gating configuration <<<<
707 09:29:09.637521 Enter into DVFS_PRE_config >>>>>
708 09:29:09.637574 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 09:29:09.637629 Exit from DVFS_PRE_config <<<<<
710 09:29:09.637682 Enter into PICG configuration >>>>
711 09:29:09.637734 Exit from PICG configuration <<<<
712 09:29:09.637786 [RX_INPUT] configuration >>>>>
713 09:29:09.637839 [RX_INPUT] configuration <<<<<
714 09:29:09.637891 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 09:29:09.637944 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 09:29:09.637997 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 09:29:09.638050 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 09:29:09.638157 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 09:29:09.638211 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 09:29:09.638265 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 09:29:09.638332 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 09:29:09.638385 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 09:29:09.638437 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 09:29:09.638490 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 09:29:09.638543 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 09:29:09.638596 ===================================
727 09:29:09.638648 LPDDR4 DRAM CONFIGURATION
728 09:29:09.638700 ===================================
729 09:29:09.638791 EX_ROW_EN[0] = 0x0
730 09:29:09.638844 EX_ROW_EN[1] = 0x0
731 09:29:09.638896 LP4Y_EN = 0x0
732 09:29:09.638948 WORK_FSP = 0x0
733 09:29:09.639001 WL = 0x2
734 09:29:09.639053 RL = 0x2
735 09:29:09.639105 BL = 0x2
736 09:29:09.639157 RPST = 0x0
737 09:29:09.639209 RD_PRE = 0x0
738 09:29:09.639261 WR_PRE = 0x1
739 09:29:09.639313 WR_PST = 0x0
740 09:29:09.639365 DBI_WR = 0x0
741 09:29:09.639417 DBI_RD = 0x0
742 09:29:09.639470 OTF = 0x1
743 09:29:09.639607 ===================================
744 09:29:09.639663 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 09:29:09.639716 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 09:29:09.639769 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 09:29:09.639822 ===================================
748 09:29:09.639875 LPDDR4 DRAM CONFIGURATION
749 09:29:09.639927 ===================================
750 09:29:09.639980 EX_ROW_EN[0] = 0x10
751 09:29:09.640032 EX_ROW_EN[1] = 0x0
752 09:29:09.640084 LP4Y_EN = 0x0
753 09:29:09.640137 WORK_FSP = 0x0
754 09:29:09.640189 WL = 0x2
755 09:29:09.640241 RL = 0x2
756 09:29:09.640293 BL = 0x2
757 09:29:09.640345 RPST = 0x0
758 09:29:09.640397 RD_PRE = 0x0
759 09:29:09.640449 WR_PRE = 0x1
760 09:29:09.640501 WR_PST = 0x0
761 09:29:09.640552 DBI_WR = 0x0
762 09:29:09.640604 DBI_RD = 0x0
763 09:29:09.640656 OTF = 0x1
764 09:29:09.640737 ===================================
765 09:29:09.640834 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 09:29:09.640934 nWR fixed to 40
767 09:29:09.641058 [ModeRegInit_LP4] CH0 RK0
768 09:29:09.641178 [ModeRegInit_LP4] CH0 RK1
769 09:29:09.641274 [ModeRegInit_LP4] CH1 RK0
770 09:29:09.641376 [ModeRegInit_LP4] CH1 RK1
771 09:29:09.641462 match AC timing 13
772 09:29:09.641549 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 09:29:09.641834 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 09:29:09.641932 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 09:29:09.642021 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 09:29:09.642109 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 09:29:09.642232 [EMI DOE] emi_dcm 0
778 09:29:09.642349 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 09:29:09.642435 ==
780 09:29:09.642522 Dram Type= 6, Freq= 0, CH_0, rank 0
781 09:29:09.642609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 09:29:09.642697 ==
783 09:29:09.642831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 09:29:09.642921 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 09:29:09.643008 [CA 0] Center 37 (7~68) winsize 62
786 09:29:09.643139 [CA 1] Center 37 (6~68) winsize 63
787 09:29:09.643241 [CA 2] Center 34 (4~65) winsize 62
788 09:29:09.643328 [CA 3] Center 35 (4~66) winsize 63
789 09:29:09.643413 [CA 4] Center 33 (3~64) winsize 62
790 09:29:09.643531 [CA 5] Center 33 (3~64) winsize 62
791 09:29:09.643616
792 09:29:09.643702 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 09:29:09.643788
794 09:29:09.643905 [CATrainingPosCal] consider 1 rank data
795 09:29:09.643992 u2DelayCellTimex100 = 270/100 ps
796 09:29:09.644079 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
797 09:29:09.644196 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
798 09:29:09.644283 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 09:29:09.644369 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
800 09:29:09.644456 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
801 09:29:09.644542 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 09:29:09.644628
803 09:29:09.644714 CA PerBit enable=1, Macro0, CA PI delay=33
804 09:29:09.644799
805 09:29:09.644915 [CBTSetCACLKResult] CA Dly = 33
806 09:29:09.645027 CS Dly: 6 (0~37)
807 09:29:09.645113 ==
808 09:29:09.645199 Dram Type= 6, Freq= 0, CH_0, rank 1
809 09:29:09.645324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 09:29:09.645449 ==
811 09:29:09.645532 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 09:29:09.645649 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 09:29:09.645733 [CA 0] Center 38 (7~69) winsize 63
814 09:29:09.645816 [CA 1] Center 37 (7~68) winsize 62
815 09:29:09.645899 [CA 2] Center 35 (5~66) winsize 62
816 09:29:09.646006 [CA 3] Center 35 (4~66) winsize 63
817 09:29:09.646132 [CA 4] Center 34 (3~65) winsize 63
818 09:29:09.646244 [CA 5] Center 33 (3~64) winsize 62
819 09:29:09.646326
820 09:29:09.646409 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 09:29:09.646491
822 09:29:09.646574 [CATrainingPosCal] consider 2 rank data
823 09:29:09.646656 u2DelayCellTimex100 = 270/100 ps
824 09:29:09.646797 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
825 09:29:09.646880 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 09:29:09.646962 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
827 09:29:09.647045 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
828 09:29:09.647128 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 09:29:09.647210 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 09:29:09.647292
831 09:29:09.647374 CA PerBit enable=1, Macro0, CA PI delay=33
832 09:29:09.647456
833 09:29:09.647567 [CBTSetCACLKResult] CA Dly = 33
834 09:29:09.647650 CS Dly: 6 (0~37)
835 09:29:09.647732
836 09:29:09.647814 ----->DramcWriteLeveling(PI) begin...
837 09:29:09.647900 ==
838 09:29:09.647984 Dram Type= 6, Freq= 0, CH_0, rank 0
839 09:29:09.648067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 09:29:09.648150 ==
841 09:29:09.648232 Write leveling (Byte 0): 30 => 30
842 09:29:09.648315 Write leveling (Byte 1): 26 => 26
843 09:29:09.648398 DramcWriteLeveling(PI) end<-----
844 09:29:09.648480
845 09:29:09.648561 ==
846 09:29:09.648644 Dram Type= 6, Freq= 0, CH_0, rank 0
847 09:29:09.648727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 09:29:09.648810 ==
849 09:29:09.648892 [Gating] SW mode calibration
850 09:29:09.648976 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 09:29:09.649060 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 09:29:09.649143 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 09:29:09.649226 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 09:29:09.649332 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 09:29:09.649387 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 09:29:09.649440 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 09:29:09.649493 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 09:29:09.649546 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 09:29:09.649599 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 09:29:09.649651 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 09:29:09.649763 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 09:29:09.649815 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 09:29:09.649868 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 09:29:09.649920 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 09:29:09.649973 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 09:29:09.650026 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 09:29:09.650078 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 09:29:09.650131 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 09:29:09.650184 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 09:29:09.650236 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
871 09:29:09.650289 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 09:29:09.650342 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 09:29:09.650394 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 09:29:09.650447 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 09:29:09.650499 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 09:29:09.650552 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 09:29:09.650604 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 09:29:09.650657 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
879 09:29:09.650710 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (1 1) (1 1)
880 09:29:09.650762 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 09:29:09.651007 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 09:29:09.651069 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 09:29:09.651124 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 09:29:09.651177 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 09:29:09.651230 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
886 09:29:09.651283 0 10 8 | B1->B0 | 3232 2626 | 0 0 | (0 1) (0 0)
887 09:29:09.651336 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
888 09:29:09.651389 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 09:29:09.651441 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 09:29:09.651494 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 09:29:09.651546 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 09:29:09.651598 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 09:29:09.651651 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
894 09:29:09.651704 0 11 8 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
895 09:29:09.651756 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
896 09:29:09.651808 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 09:29:09.651860 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 09:29:09.651913 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 09:29:09.651969 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 09:29:09.652160 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 09:29:09.652287 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 09:29:09.652340 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
903 09:29:09.652394 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 09:29:09.652446 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 09:29:09.652499 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 09:29:09.652552 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 09:29:09.652604 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 09:29:09.652657 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 09:29:09.652709 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 09:29:09.652762 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 09:29:09.652814 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 09:29:09.652871 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 09:29:09.652924 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 09:29:09.652976 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 09:29:09.653028 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 09:29:09.653080 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 09:29:09.653147 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
918 09:29:09.653201 Total UI for P1: 0, mck2ui 16
919 09:29:09.653261 best dqsien dly found for B0: ( 0, 14, 2)
920 09:29:09.653329 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
921 09:29:09.653382 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
922 09:29:09.653435 Total UI for P1: 0, mck2ui 16
923 09:29:09.653488 best dqsien dly found for B1: ( 0, 14, 8)
924 09:29:09.653541 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
925 09:29:09.653593 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
926 09:29:09.653646
927 09:29:09.653698 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
928 09:29:09.653750 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 09:29:09.653803 [Gating] SW calibration Done
930 09:29:09.653856 ==
931 09:29:09.653914 Dram Type= 6, Freq= 0, CH_0, rank 0
932 09:29:09.653966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 09:29:09.654019 ==
934 09:29:09.654071 RX Vref Scan: 0
935 09:29:09.654124
936 09:29:09.654176 RX Vref 0 -> 0, step: 1
937 09:29:09.654228
938 09:29:09.654280 RX Delay -130 -> 252, step: 16
939 09:29:09.654333 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
940 09:29:09.654385 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
941 09:29:09.654437 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
942 09:29:09.654490 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
943 09:29:09.654543 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
944 09:29:09.654595 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
945 09:29:09.654647 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
946 09:29:09.654699 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
947 09:29:09.654751 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
948 09:29:09.654803 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
949 09:29:09.654856 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
950 09:29:09.654908 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
951 09:29:09.654961 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
952 09:29:09.655012 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
953 09:29:09.655065 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
954 09:29:09.655117 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
955 09:29:09.655169 ==
956 09:29:09.655221 Dram Type= 6, Freq= 0, CH_0, rank 0
957 09:29:09.655273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 09:29:09.655326 ==
959 09:29:09.655394 DQS Delay:
960 09:29:09.655447 DQS0 = 0, DQS1 = 0
961 09:29:09.655515 DQM Delay:
962 09:29:09.655567 DQM0 = 91, DQM1 = 76
963 09:29:09.655619 DQ Delay:
964 09:29:09.655671 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
965 09:29:09.655723 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
966 09:29:09.655775 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
967 09:29:09.655828 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
968 09:29:09.655879
969 09:29:09.655930
970 09:29:09.655982 ==
971 09:29:09.656034 Dram Type= 6, Freq= 0, CH_0, rank 0
972 09:29:09.656086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 09:29:09.656138 ==
974 09:29:09.656190
975 09:29:09.656242
976 09:29:09.656293 TX Vref Scan disable
977 09:29:09.656345 == TX Byte 0 ==
978 09:29:09.656413 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
979 09:29:09.656481 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
980 09:29:09.656533 == TX Byte 1 ==
981 09:29:09.656585 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
982 09:29:09.656637 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
983 09:29:09.656690 ==
984 09:29:09.656742 Dram Type= 6, Freq= 0, CH_0, rank 0
985 09:29:09.656794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 09:29:09.656847 ==
987 09:29:09.656898 TX Vref=22, minBit 7, minWin=26, winSum=438
988 09:29:09.656951 TX Vref=24, minBit 0, minWin=27, winSum=442
989 09:29:09.657218 TX Vref=26, minBit 3, minWin=27, winSum=446
990 09:29:09.657299 TX Vref=28, minBit 2, minWin=27, winSum=449
991 09:29:09.657354 TX Vref=30, minBit 2, minWin=27, winSum=448
992 09:29:09.657406 TX Vref=32, minBit 6, minWin=27, winSum=450
993 09:29:09.657460 [TxChooseVref] Worse bit 6, Min win 27, Win sum 450, Final Vref 32
994 09:29:09.657513
995 09:29:09.657565 Final TX Range 1 Vref 32
996 09:29:09.657618
997 09:29:09.657671 ==
998 09:29:09.657723 Dram Type= 6, Freq= 0, CH_0, rank 0
999 09:29:09.657776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 09:29:09.657828 ==
1001 09:29:09.657881
1002 09:29:09.657932
1003 09:29:09.658011 TX Vref Scan disable
1004 09:29:09.658097 == TX Byte 0 ==
1005 09:29:09.658194 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1006 09:29:09.658247 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1007 09:29:09.658299 == TX Byte 1 ==
1008 09:29:09.658351 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1009 09:29:09.658404 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1010 09:29:09.658456
1011 09:29:09.658509 [DATLAT]
1012 09:29:09.658561 Freq=800, CH0 RK0
1013 09:29:09.658614
1014 09:29:09.658666 DATLAT Default: 0xa
1015 09:29:09.658718 0, 0xFFFF, sum = 0
1016 09:29:09.658772 1, 0xFFFF, sum = 0
1017 09:29:09.658826 2, 0xFFFF, sum = 0
1018 09:29:09.658879 3, 0xFFFF, sum = 0
1019 09:29:09.658932 4, 0xFFFF, sum = 0
1020 09:29:09.658985 5, 0xFFFF, sum = 0
1021 09:29:09.659038 6, 0xFFFF, sum = 0
1022 09:29:09.659091 7, 0xFFFF, sum = 0
1023 09:29:09.659144 8, 0xFFFF, sum = 0
1024 09:29:09.659197 9, 0x0, sum = 1
1025 09:29:09.659259 10, 0x0, sum = 2
1026 09:29:09.659318 11, 0x0, sum = 3
1027 09:29:09.659373 12, 0x0, sum = 4
1028 09:29:09.659426 best_step = 10
1029 09:29:09.659479
1030 09:29:09.659530 ==
1031 09:29:09.659582 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 09:29:09.659635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 09:29:09.659688 ==
1034 09:29:09.659740 RX Vref Scan: 1
1035 09:29:09.659792
1036 09:29:09.659844 Set Vref Range= 32 -> 127
1037 09:29:09.659896
1038 09:29:09.659947 RX Vref 32 -> 127, step: 1
1039 09:29:09.659999
1040 09:29:09.660050 RX Delay -95 -> 252, step: 8
1041 09:29:09.660102
1042 09:29:09.660153 Set Vref, RX VrefLevel [Byte0]: 32
1043 09:29:09.660205 [Byte1]: 32
1044 09:29:09.660257
1045 09:29:09.660309 Set Vref, RX VrefLevel [Byte0]: 33
1046 09:29:09.660361 [Byte1]: 33
1047 09:29:09.660413
1048 09:29:09.660464 Set Vref, RX VrefLevel [Byte0]: 34
1049 09:29:09.660515 [Byte1]: 34
1050 09:29:09.660567
1051 09:29:09.660618 Set Vref, RX VrefLevel [Byte0]: 35
1052 09:29:09.660669 [Byte1]: 35
1053 09:29:09.660721
1054 09:29:09.660773 Set Vref, RX VrefLevel [Byte0]: 36
1055 09:29:09.660824 [Byte1]: 36
1056 09:29:09.660877
1057 09:29:09.660927 Set Vref, RX VrefLevel [Byte0]: 37
1058 09:29:09.660979 [Byte1]: 37
1059 09:29:09.661031
1060 09:29:09.661082 Set Vref, RX VrefLevel [Byte0]: 38
1061 09:29:09.661133 [Byte1]: 38
1062 09:29:09.661185
1063 09:29:09.661236 Set Vref, RX VrefLevel [Byte0]: 39
1064 09:29:09.661310 [Byte1]: 39
1065 09:29:09.661375
1066 09:29:09.661427 Set Vref, RX VrefLevel [Byte0]: 40
1067 09:29:09.661479 [Byte1]: 40
1068 09:29:09.661530
1069 09:29:09.661581 Set Vref, RX VrefLevel [Byte0]: 41
1070 09:29:09.661633 [Byte1]: 41
1071 09:29:09.661684
1072 09:29:09.661736 Set Vref, RX VrefLevel [Byte0]: 42
1073 09:29:09.661788 [Byte1]: 42
1074 09:29:09.661839
1075 09:29:09.661890 Set Vref, RX VrefLevel [Byte0]: 43
1076 09:29:09.661942 [Byte1]: 43
1077 09:29:09.661993
1078 09:29:09.662044 Set Vref, RX VrefLevel [Byte0]: 44
1079 09:29:09.662096 [Byte1]: 44
1080 09:29:09.662147
1081 09:29:09.662198 Set Vref, RX VrefLevel [Byte0]: 45
1082 09:29:09.662249 [Byte1]: 45
1083 09:29:09.662301
1084 09:29:09.662352 Set Vref, RX VrefLevel [Byte0]: 46
1085 09:29:09.662404 [Byte1]: 46
1086 09:29:09.662455
1087 09:29:09.662506 Set Vref, RX VrefLevel [Byte0]: 47
1088 09:29:09.662558 [Byte1]: 47
1089 09:29:09.662609
1090 09:29:09.662660 Set Vref, RX VrefLevel [Byte0]: 48
1091 09:29:09.662711 [Byte1]: 48
1092 09:29:09.662763
1093 09:29:09.662814 Set Vref, RX VrefLevel [Byte0]: 49
1094 09:29:09.662866 [Byte1]: 49
1095 09:29:09.662917
1096 09:29:09.662968 Set Vref, RX VrefLevel [Byte0]: 50
1097 09:29:09.663020 [Byte1]: 50
1098 09:29:09.663071
1099 09:29:09.663123 Set Vref, RX VrefLevel [Byte0]: 51
1100 09:29:09.663175 [Byte1]: 51
1101 09:29:09.663226
1102 09:29:09.663278 Set Vref, RX VrefLevel [Byte0]: 52
1103 09:29:09.663329 [Byte1]: 52
1104 09:29:09.663380
1105 09:29:09.663432 Set Vref, RX VrefLevel [Byte0]: 53
1106 09:29:09.663483 [Byte1]: 53
1107 09:29:09.663534
1108 09:29:09.663585 Set Vref, RX VrefLevel [Byte0]: 54
1109 09:29:09.663636 [Byte1]: 54
1110 09:29:09.663688
1111 09:29:09.663739 Set Vref, RX VrefLevel [Byte0]: 55
1112 09:29:09.663791 [Byte1]: 55
1113 09:29:09.663843
1114 09:29:09.663894 Set Vref, RX VrefLevel [Byte0]: 56
1115 09:29:09.663946 [Byte1]: 56
1116 09:29:09.663998
1117 09:29:09.664066 Set Vref, RX VrefLevel [Byte0]: 57
1118 09:29:09.664119 [Byte1]: 57
1119 09:29:09.664184
1120 09:29:09.664235 Set Vref, RX VrefLevel [Byte0]: 58
1121 09:29:09.664287 [Byte1]: 58
1122 09:29:09.664338
1123 09:29:09.664389 Set Vref, RX VrefLevel [Byte0]: 59
1124 09:29:09.664441 [Byte1]: 59
1125 09:29:09.664492
1126 09:29:09.664544 Set Vref, RX VrefLevel [Byte0]: 60
1127 09:29:09.664596 [Byte1]: 60
1128 09:29:09.664647
1129 09:29:09.664699 Set Vref, RX VrefLevel [Byte0]: 61
1130 09:29:09.664750 [Byte1]: 61
1131 09:29:09.664802
1132 09:29:09.664853 Set Vref, RX VrefLevel [Byte0]: 62
1133 09:29:09.664905 [Byte1]: 62
1134 09:29:09.664957
1135 09:29:09.665008 Set Vref, RX VrefLevel [Byte0]: 63
1136 09:29:09.665060 [Byte1]: 63
1137 09:29:09.665112
1138 09:29:09.665163 Set Vref, RX VrefLevel [Byte0]: 64
1139 09:29:09.665214 [Byte1]: 64
1140 09:29:09.665308
1141 09:29:09.665363 Set Vref, RX VrefLevel [Byte0]: 65
1142 09:29:09.665416 [Byte1]: 65
1143 09:29:09.665467
1144 09:29:09.665519 Set Vref, RX VrefLevel [Byte0]: 66
1145 09:29:09.665570 [Byte1]: 66
1146 09:29:09.665623
1147 09:29:09.665675 Set Vref, RX VrefLevel [Byte0]: 67
1148 09:29:09.665727 [Byte1]: 67
1149 09:29:09.665779
1150 09:29:09.665830 Set Vref, RX VrefLevel [Byte0]: 68
1151 09:29:09.665882 [Byte1]: 68
1152 09:29:09.665949
1153 09:29:09.666016 Set Vref, RX VrefLevel [Byte0]: 69
1154 09:29:09.666068 [Byte1]: 69
1155 09:29:09.666119
1156 09:29:09.666171 Set Vref, RX VrefLevel [Byte0]: 70
1157 09:29:09.666420 [Byte1]: 70
1158 09:29:09.666507
1159 09:29:09.666561 Set Vref, RX VrefLevel [Byte0]: 71
1160 09:29:09.666614 [Byte1]: 71
1161 09:29:09.666666
1162 09:29:09.666718 Set Vref, RX VrefLevel [Byte0]: 72
1163 09:29:09.666770 [Byte1]: 72
1164 09:29:09.666823
1165 09:29:09.666874 Set Vref, RX VrefLevel [Byte0]: 73
1166 09:29:09.666927 [Byte1]: 73
1167 09:29:09.666979
1168 09:29:09.667030 Final RX Vref Byte 0 = 55 to rank0
1169 09:29:09.667082 Final RX Vref Byte 1 = 60 to rank0
1170 09:29:09.667134 Final RX Vref Byte 0 = 55 to rank1
1171 09:29:09.667186 Final RX Vref Byte 1 = 60 to rank1==
1172 09:29:09.667239 Dram Type= 6, Freq= 0, CH_0, rank 0
1173 09:29:09.667291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1174 09:29:09.667344 ==
1175 09:29:09.667396 DQS Delay:
1176 09:29:09.667448 DQS0 = 0, DQS1 = 0
1177 09:29:09.667500 DQM Delay:
1178 09:29:09.667551 DQM0 = 88, DQM1 = 77
1179 09:29:09.667603 DQ Delay:
1180 09:29:09.667654 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1181 09:29:09.667706 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1182 09:29:09.667757 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1183 09:29:09.667809 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1184 09:29:09.667861
1185 09:29:09.667912
1186 09:29:09.667963 [DQSOSCAuto] RK0, (LSB)MR18= 0x312b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1187 09:29:09.668017 CH0 RK0: MR19=606, MR18=312B
1188 09:29:09.668069 CH0_RK0: MR19=0x606, MR18=0x312B, DQSOSC=397, MR23=63, INC=93, DEC=62
1189 09:29:09.668121
1190 09:29:09.668173 ----->DramcWriteLeveling(PI) begin...
1191 09:29:09.668225 ==
1192 09:29:09.668277 Dram Type= 6, Freq= 0, CH_0, rank 1
1193 09:29:09.668329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1194 09:29:09.668382 ==
1195 09:29:09.668433 Write leveling (Byte 0): 33 => 33
1196 09:29:09.668485 Write leveling (Byte 1): 27 => 27
1197 09:29:09.668537 DramcWriteLeveling(PI) end<-----
1198 09:29:09.668588
1199 09:29:09.668640 ==
1200 09:29:09.668691 Dram Type= 6, Freq= 0, CH_0, rank 1
1201 09:29:09.668744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1202 09:29:09.668795 ==
1203 09:29:09.668847 [Gating] SW mode calibration
1204 09:29:09.668899 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1205 09:29:09.668954 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1206 09:29:09.669006 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1207 09:29:09.669058 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1208 09:29:09.669110 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1209 09:29:09.669162 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 09:29:09.669214 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 09:29:09.669296 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 09:29:09.669364 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 09:29:09.669416 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 09:29:09.669468 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 09:29:09.669520 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 09:29:09.669571 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 09:29:09.669623 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 09:29:09.669675 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 09:29:09.669727 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 09:29:09.669779 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 09:29:09.669831 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 09:29:09.669883 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 09:29:09.669934 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1224 09:29:09.669986 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1225 09:29:09.670037 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 09:29:09.670089 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 09:29:09.670141 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 09:29:09.670192 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 09:29:09.670244 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 09:29:09.670296 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 09:29:09.670347 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 09:29:09.670400 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1233 09:29:09.670452 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 09:29:09.670503 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 09:29:09.670555 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 09:29:09.670606 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 09:29:09.670658 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 09:29:09.670710 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 09:29:09.670761 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1240 09:29:09.670813 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
1241 09:29:09.670864 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1242 09:29:09.670916 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 09:29:09.670968 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 09:29:09.671020 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 09:29:09.671071 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 09:29:09.671123 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 09:29:09.671175 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1248 09:29:09.671227 0 11 8 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
1249 09:29:09.671279 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 09:29:09.671331 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 09:29:09.671382 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 09:29:09.671434 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 09:29:09.671486 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 09:29:09.671539 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1255 09:29:09.671590 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 09:29:09.671642 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1257 09:29:09.671694 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 09:29:09.671938 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 09:29:09.671999 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 09:29:09.672052 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 09:29:09.672104 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 09:29:09.672157 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 09:29:09.672209 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 09:29:09.672260 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 09:29:09.672312 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 09:29:09.672364 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 09:29:09.672416 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 09:29:09.672468 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 09:29:09.672520 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 09:29:09.672572 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1271 09:29:09.672623 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 09:29:09.672675 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1273 09:29:09.672727 Total UI for P1: 0, mck2ui 16
1274 09:29:09.672780 best dqsien dly found for B0: ( 0, 14, 6)
1275 09:29:09.672832 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 09:29:09.672884 Total UI for P1: 0, mck2ui 16
1277 09:29:09.672936 best dqsien dly found for B1: ( 0, 14, 8)
1278 09:29:09.672988 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1279 09:29:09.673040 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1280 09:29:09.673091
1281 09:29:09.673143 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1282 09:29:09.673195 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1283 09:29:09.673247 [Gating] SW calibration Done
1284 09:29:09.673353 ==
1285 09:29:09.673406 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 09:29:09.673458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 09:29:09.673511 ==
1288 09:29:09.673562 RX Vref Scan: 0
1289 09:29:09.673614
1290 09:29:09.673666 RX Vref 0 -> 0, step: 1
1291 09:29:09.673718
1292 09:29:09.673769 RX Delay -130 -> 252, step: 16
1293 09:29:09.673822 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1294 09:29:09.673875 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1295 09:29:09.673927 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1296 09:29:09.673979 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1297 09:29:09.674031 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1298 09:29:09.674083 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1299 09:29:09.674134 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1300 09:29:09.674186 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1301 09:29:09.674237 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1302 09:29:09.674289 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1303 09:29:09.674341 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1304 09:29:09.674393 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1305 09:29:09.674445 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1306 09:29:09.674497 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1307 09:29:09.674549 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1308 09:29:09.674601 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1309 09:29:09.674652 ==
1310 09:29:09.674704 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 09:29:09.674756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 09:29:09.674808 ==
1313 09:29:09.674860 DQS Delay:
1314 09:29:09.674911 DQS0 = 0, DQS1 = 0
1315 09:29:09.674963 DQM Delay:
1316 09:29:09.675015 DQM0 = 86, DQM1 = 77
1317 09:29:09.675067 DQ Delay:
1318 09:29:09.675119 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1319 09:29:09.675171 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1320 09:29:09.675222 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1321 09:29:09.675274 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1322 09:29:09.675326
1323 09:29:09.675377
1324 09:29:09.675428 ==
1325 09:29:09.675480 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 09:29:09.675532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 09:29:09.675584 ==
1328 09:29:09.675635
1329 09:29:09.675687
1330 09:29:09.675737 TX Vref Scan disable
1331 09:29:09.675789 == TX Byte 0 ==
1332 09:29:09.675841 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1333 09:29:09.675893 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1334 09:29:09.675945 == TX Byte 1 ==
1335 09:29:09.675996 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1336 09:29:09.676048 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1337 09:29:09.676100 ==
1338 09:29:09.676152 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 09:29:09.676203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 09:29:09.676256 ==
1341 09:29:09.676308 TX Vref=22, minBit 1, minWin=27, winSum=440
1342 09:29:09.676361 TX Vref=24, minBit 2, minWin=27, winSum=445
1343 09:29:09.676413 TX Vref=26, minBit 2, minWin=27, winSum=449
1344 09:29:09.676466 TX Vref=28, minBit 0, minWin=28, winSum=452
1345 09:29:09.676518 TX Vref=30, minBit 1, minWin=27, winSum=449
1346 09:29:09.676570 TX Vref=32, minBit 1, minWin=27, winSum=449
1347 09:29:09.676623 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 28
1348 09:29:09.676675
1349 09:29:09.676726 Final TX Range 1 Vref 28
1350 09:29:09.676778
1351 09:29:09.676829 ==
1352 09:29:09.676881 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 09:29:09.676934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 09:29:09.676986 ==
1355 09:29:09.677038
1356 09:29:09.677089
1357 09:29:09.677140 TX Vref Scan disable
1358 09:29:09.677192 == TX Byte 0 ==
1359 09:29:09.677244 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1360 09:29:09.677333 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1361 09:29:09.677385 == TX Byte 1 ==
1362 09:29:09.677436 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1363 09:29:09.677488 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1364 09:29:09.677539
1365 09:29:09.677590 [DATLAT]
1366 09:29:09.677641 Freq=800, CH0 RK1
1367 09:29:09.677693
1368 09:29:09.677743 DATLAT Default: 0xa
1369 09:29:09.677794 0, 0xFFFF, sum = 0
1370 09:29:09.677847 1, 0xFFFF, sum = 0
1371 09:29:09.677899 2, 0xFFFF, sum = 0
1372 09:29:09.677951 3, 0xFFFF, sum = 0
1373 09:29:09.678004 4, 0xFFFF, sum = 0
1374 09:29:09.678056 5, 0xFFFF, sum = 0
1375 09:29:09.678108 6, 0xFFFF, sum = 0
1376 09:29:09.678160 7, 0xFFFF, sum = 0
1377 09:29:09.678212 8, 0xFFFF, sum = 0
1378 09:29:09.678264 9, 0x0, sum = 1
1379 09:29:09.678316 10, 0x0, sum = 2
1380 09:29:09.678368 11, 0x0, sum = 3
1381 09:29:09.678420 12, 0x0, sum = 4
1382 09:29:09.678472 best_step = 10
1383 09:29:09.678523
1384 09:29:09.678574 ==
1385 09:29:09.678626 Dram Type= 6, Freq= 0, CH_0, rank 1
1386 09:29:09.678677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1387 09:29:09.678730 ==
1388 09:29:09.678780 RX Vref Scan: 0
1389 09:29:09.678831
1390 09:29:09.678881 RX Vref 0 -> 0, step: 1
1391 09:29:09.678933
1392 09:29:09.678983 RX Delay -95 -> 252, step: 8
1393 09:29:09.679035 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1394 09:29:09.679278 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1395 09:29:09.679337 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1396 09:29:09.679390 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1397 09:29:09.679442 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1398 09:29:09.679493 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1399 09:29:09.679545 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1400 09:29:09.679596 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1401 09:29:09.679676 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1402 09:29:09.679728 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1403 09:29:09.679781 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1404 09:29:09.679833 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1405 09:29:09.679884 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1406 09:29:09.679935 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1407 09:29:09.679986 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1408 09:29:09.680037 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1409 09:29:09.680088 ==
1410 09:29:09.680140 Dram Type= 6, Freq= 0, CH_0, rank 1
1411 09:29:09.680191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 09:29:09.680242 ==
1413 09:29:09.680293 DQS Delay:
1414 09:29:09.680344 DQS0 = 0, DQS1 = 0
1415 09:29:09.680396 DQM Delay:
1416 09:29:09.680447 DQM0 = 86, DQM1 = 76
1417 09:29:09.680498 DQ Delay:
1418 09:29:09.680549 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1419 09:29:09.680601 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1420 09:29:09.680651 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1421 09:29:09.680703 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1422 09:29:09.680757
1423 09:29:09.680809
1424 09:29:09.680860 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1425 09:29:09.680913 CH0 RK1: MR19=606, MR18=2A26
1426 09:29:09.680965 CH0_RK1: MR19=0x606, MR18=0x2A26, DQSOSC=399, MR23=63, INC=92, DEC=61
1427 09:29:09.681017 [RxdqsGatingPostProcess] freq 800
1428 09:29:09.681069 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1429 09:29:09.681120 Pre-setting of DQS Precalculation
1430 09:29:09.681195 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1431 09:29:09.681247 ==
1432 09:29:09.681319 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 09:29:09.681371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 09:29:09.681423 ==
1435 09:29:09.681474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1436 09:29:09.681526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1437 09:29:09.681577 [CA 0] Center 36 (6~67) winsize 62
1438 09:29:09.681629 [CA 1] Center 36 (6~67) winsize 62
1439 09:29:09.681679 [CA 2] Center 35 (5~65) winsize 61
1440 09:29:09.681731 [CA 3] Center 34 (4~65) winsize 62
1441 09:29:09.681783 [CA 4] Center 34 (4~65) winsize 62
1442 09:29:09.681834 [CA 5] Center 34 (3~65) winsize 63
1443 09:29:09.681885
1444 09:29:09.681936 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1445 09:29:09.681988
1446 09:29:09.682038 [CATrainingPosCal] consider 1 rank data
1447 09:29:09.682089 u2DelayCellTimex100 = 270/100 ps
1448 09:29:09.682140 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1449 09:29:09.682192 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1450 09:29:09.682243 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1451 09:29:09.682294 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1452 09:29:09.682345 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1453 09:29:09.682396 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1454 09:29:09.682447
1455 09:29:09.682498 CA PerBit enable=1, Macro0, CA PI delay=34
1456 09:29:09.682549
1457 09:29:09.682600 [CBTSetCACLKResult] CA Dly = 34
1458 09:29:09.682651 CS Dly: 4 (0~35)
1459 09:29:09.682702 ==
1460 09:29:09.682753 Dram Type= 6, Freq= 0, CH_1, rank 1
1461 09:29:09.682804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 09:29:09.682856 ==
1463 09:29:09.682907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1464 09:29:09.682958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1465 09:29:09.683009 [CA 0] Center 36 (6~67) winsize 62
1466 09:29:09.683060 [CA 1] Center 36 (6~67) winsize 62
1467 09:29:09.683111 [CA 2] Center 34 (4~65) winsize 62
1468 09:29:09.683162 [CA 3] Center 33 (3~64) winsize 62
1469 09:29:09.683212 [CA 4] Center 34 (4~65) winsize 62
1470 09:29:09.683263 [CA 5] Center 34 (3~65) winsize 63
1471 09:29:09.683314
1472 09:29:09.683364 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1473 09:29:09.683415
1474 09:29:09.683466 [CATrainingPosCal] consider 2 rank data
1475 09:29:09.683517 u2DelayCellTimex100 = 270/100 ps
1476 09:29:09.683568 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1477 09:29:09.683619 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1478 09:29:09.683671 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1479 09:29:09.683722 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1480 09:29:09.683774 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1481 09:29:09.683825 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1482 09:29:09.683876
1483 09:29:09.683927 CA PerBit enable=1, Macro0, CA PI delay=34
1484 09:29:09.683978
1485 09:29:09.684029 [CBTSetCACLKResult] CA Dly = 34
1486 09:29:09.684080 CS Dly: 5 (0~37)
1487 09:29:09.684131
1488 09:29:09.684182 ----->DramcWriteLeveling(PI) begin...
1489 09:29:09.684234 ==
1490 09:29:09.684285 Dram Type= 6, Freq= 0, CH_1, rank 0
1491 09:29:09.684336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1492 09:29:09.684388 ==
1493 09:29:09.684439 Write leveling (Byte 0): 26 => 26
1494 09:29:09.684490 Write leveling (Byte 1): 27 => 27
1495 09:29:09.684540 DramcWriteLeveling(PI) end<-----
1496 09:29:09.684591
1497 09:29:09.684642 ==
1498 09:29:09.684693 Dram Type= 6, Freq= 0, CH_1, rank 0
1499 09:29:09.684744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1500 09:29:09.684796 ==
1501 09:29:09.684847 [Gating] SW mode calibration
1502 09:29:09.684899 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1503 09:29:09.684950 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1504 09:29:09.685002 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1505 09:29:09.685053 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1506 09:29:09.685105 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 09:29:09.685156 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 09:29:09.685207 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 09:29:09.685262 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 09:29:09.685344 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 09:29:09.685590 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 09:29:09.685648 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 09:29:09.685700 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 09:29:09.685752 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 09:29:09.685804 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 09:29:09.685856 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 09:29:09.685907 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 09:29:09.685959 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 09:29:09.686011 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 09:29:09.686062 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1521 09:29:09.686113 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1522 09:29:09.686165 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 09:29:09.686217 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 09:29:09.686268 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 09:29:09.686319 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 09:29:09.686370 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 09:29:09.686421 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 09:29:09.686473 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 09:29:09.686524 0 9 4 | B1->B0 | 2322 2323 | 1 1 | (0 0) (0 0)
1530 09:29:09.686575 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1531 09:29:09.686626 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 09:29:09.686677 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 09:29:09.686728 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 09:29:09.686780 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 09:29:09.686831 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 09:29:09.686882 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 09:29:09.686933 0 10 4 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (1 0)
1538 09:29:09.686984 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 09:29:09.687035 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 09:29:09.687087 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 09:29:09.687138 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 09:29:09.687189 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 09:29:09.687241 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 09:29:09.687292 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 09:29:09.687343 0 11 4 | B1->B0 | 2b2b 3232 | 0 1 | (0 0) (0 0)
1546 09:29:09.687395 0 11 8 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
1547 09:29:09.687446 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 09:29:09.687497 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 09:29:09.687549 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 09:29:09.687599 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 09:29:09.687652 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 09:29:09.687703 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 09:29:09.687755 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1554 09:29:09.687806 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1555 09:29:09.687858 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 09:29:09.687909 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 09:29:09.687961 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 09:29:09.688012 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 09:29:09.688062 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 09:29:09.688113 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 09:29:09.688164 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 09:29:09.688215 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 09:29:09.688267 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 09:29:09.688318 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 09:29:09.688369 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 09:29:09.688420 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 09:29:09.688472 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 09:29:09.688523 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 09:29:09.688574 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1570 09:29:09.688625 Total UI for P1: 0, mck2ui 16
1571 09:29:09.688677 best dqsien dly found for B0: ( 0, 14, 2)
1572 09:29:09.688729 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1573 09:29:09.688780 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 09:29:09.688831 Total UI for P1: 0, mck2ui 16
1575 09:29:09.688883 best dqsien dly found for B1: ( 0, 14, 6)
1576 09:29:09.688935 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1577 09:29:09.688986 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1578 09:29:09.689037
1579 09:29:09.689088 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1580 09:29:09.689139 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1581 09:29:09.689191 [Gating] SW calibration Done
1582 09:29:09.689277 ==
1583 09:29:09.689387 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 09:29:09.689474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 09:29:09.689526 ==
1586 09:29:09.689578 RX Vref Scan: 0
1587 09:29:09.689630
1588 09:29:09.689685 RX Vref 0 -> 0, step: 1
1589 09:29:09.689783
1590 09:29:09.689846 RX Delay -130 -> 252, step: 16
1591 09:29:09.689898 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1592 09:29:09.689950 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1593 09:29:09.690002 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1594 09:29:09.690054 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1595 09:29:09.690105 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1596 09:29:09.690156 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1597 09:29:09.690207 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1598 09:29:09.690258 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1599 09:29:09.690309 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1600 09:29:09.690360 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1601 09:29:09.690607 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1602 09:29:09.690668 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1603 09:29:09.690720 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1604 09:29:09.690772 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1605 09:29:09.690823 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1606 09:29:09.690875 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1607 09:29:09.690926 ==
1608 09:29:09.690978 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 09:29:09.691029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 09:29:09.691081 ==
1611 09:29:09.691133 DQS Delay:
1612 09:29:09.691184 DQS0 = 0, DQS1 = 0
1613 09:29:09.691235 DQM Delay:
1614 09:29:09.691287 DQM0 = 88, DQM1 = 84
1615 09:29:09.691338 DQ Delay:
1616 09:29:09.691389 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1617 09:29:09.691440 DQ4 =77, DQ5 =101, DQ6 =101, DQ7 =85
1618 09:29:09.691491 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1619 09:29:09.691542 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1620 09:29:09.691593
1621 09:29:09.691644
1622 09:29:09.691694 ==
1623 09:29:09.691745 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 09:29:09.691797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 09:29:09.691849 ==
1626 09:29:09.691899
1627 09:29:09.691951
1628 09:29:09.692001 TX Vref Scan disable
1629 09:29:09.692052 == TX Byte 0 ==
1630 09:29:09.692103 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1631 09:29:09.692155 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1632 09:29:09.692206 == TX Byte 1 ==
1633 09:29:09.692258 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1634 09:29:09.692309 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1635 09:29:09.692361 ==
1636 09:29:09.692412 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 09:29:09.692463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 09:29:09.692532 ==
1639 09:29:09.692597 TX Vref=22, minBit 1, minWin=27, winSum=444
1640 09:29:09.692649 TX Vref=24, minBit 2, minWin=27, winSum=445
1641 09:29:09.692701 TX Vref=26, minBit 2, minWin=27, winSum=450
1642 09:29:09.692752 TX Vref=28, minBit 2, minWin=27, winSum=454
1643 09:29:09.692803 TX Vref=30, minBit 2, minWin=27, winSum=456
1644 09:29:09.692854 TX Vref=32, minBit 0, minWin=27, winSum=449
1645 09:29:09.692906 [TxChooseVref] Worse bit 2, Min win 27, Win sum 456, Final Vref 30
1646 09:29:09.692958
1647 09:29:09.693008 Final TX Range 1 Vref 30
1648 09:29:09.693060
1649 09:29:09.693110 ==
1650 09:29:09.693162 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 09:29:09.693212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 09:29:09.693290 ==
1653 09:29:09.693358
1654 09:29:09.693409
1655 09:29:09.693459 TX Vref Scan disable
1656 09:29:09.693510 == TX Byte 0 ==
1657 09:29:09.693561 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1658 09:29:09.693613 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1659 09:29:09.693664 == TX Byte 1 ==
1660 09:29:09.693716 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1661 09:29:09.693767 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1662 09:29:09.693818
1663 09:29:09.693869 [DATLAT]
1664 09:29:09.693920 Freq=800, CH1 RK0
1665 09:29:09.694007
1666 09:29:09.694058 DATLAT Default: 0xa
1667 09:29:09.694109 0, 0xFFFF, sum = 0
1668 09:29:09.694162 1, 0xFFFF, sum = 0
1669 09:29:09.694215 2, 0xFFFF, sum = 0
1670 09:29:09.694267 3, 0xFFFF, sum = 0
1671 09:29:09.694320 4, 0xFFFF, sum = 0
1672 09:29:09.694371 5, 0xFFFF, sum = 0
1673 09:29:09.694423 6, 0xFFFF, sum = 0
1674 09:29:09.694475 7, 0xFFFF, sum = 0
1675 09:29:09.694527 8, 0xFFFF, sum = 0
1676 09:29:09.694579 9, 0x0, sum = 1
1677 09:29:09.694630 10, 0x0, sum = 2
1678 09:29:09.694683 11, 0x0, sum = 3
1679 09:29:09.694735 12, 0x0, sum = 4
1680 09:29:09.694787 best_step = 10
1681 09:29:09.694838
1682 09:29:09.694889 ==
1683 09:29:09.694940 Dram Type= 6, Freq= 0, CH_1, rank 0
1684 09:29:09.694991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1685 09:29:09.695043 ==
1686 09:29:09.695094 RX Vref Scan: 1
1687 09:29:09.695145
1688 09:29:09.695196 Set Vref Range= 32 -> 127
1689 09:29:09.695246
1690 09:29:09.695297 RX Vref 32 -> 127, step: 1
1691 09:29:09.695348
1692 09:29:09.695399 RX Delay -95 -> 252, step: 8
1693 09:29:09.695451
1694 09:29:09.695501 Set Vref, RX VrefLevel [Byte0]: 32
1695 09:29:09.695553 [Byte1]: 32
1696 09:29:09.695628
1697 09:29:09.695693 Set Vref, RX VrefLevel [Byte0]: 33
1698 09:29:09.695744 [Byte1]: 33
1699 09:29:09.695795
1700 09:29:09.695845 Set Vref, RX VrefLevel [Byte0]: 34
1701 09:29:09.695896 [Byte1]: 34
1702 09:29:09.695948
1703 09:29:09.695998 Set Vref, RX VrefLevel [Byte0]: 35
1704 09:29:09.696050 [Byte1]: 35
1705 09:29:09.696101
1706 09:29:09.696152 Set Vref, RX VrefLevel [Byte0]: 36
1707 09:29:09.696203 [Byte1]: 36
1708 09:29:09.696254
1709 09:29:09.696305 Set Vref, RX VrefLevel [Byte0]: 37
1710 09:29:09.696356 [Byte1]: 37
1711 09:29:09.696407
1712 09:29:09.696458 Set Vref, RX VrefLevel [Byte0]: 38
1713 09:29:09.696509 [Byte1]: 38
1714 09:29:09.696561
1715 09:29:09.696612 Set Vref, RX VrefLevel [Byte0]: 39
1716 09:29:09.696664 [Byte1]: 39
1717 09:29:09.696715
1718 09:29:09.696765 Set Vref, RX VrefLevel [Byte0]: 40
1719 09:29:09.696816 [Byte1]: 40
1720 09:29:09.696867
1721 09:29:09.696918 Set Vref, RX VrefLevel [Byte0]: 41
1722 09:29:09.696994 [Byte1]: 41
1723 09:29:09.697089
1724 09:29:09.697140 Set Vref, RX VrefLevel [Byte0]: 42
1725 09:29:09.697190 [Byte1]: 42
1726 09:29:09.697242
1727 09:29:09.697328 Set Vref, RX VrefLevel [Byte0]: 43
1728 09:29:09.697380 [Byte1]: 43
1729 09:29:09.697431
1730 09:29:09.697482 Set Vref, RX VrefLevel [Byte0]: 44
1731 09:29:09.697533 [Byte1]: 44
1732 09:29:09.697584
1733 09:29:09.697635 Set Vref, RX VrefLevel [Byte0]: 45
1734 09:29:09.697686 [Byte1]: 45
1735 09:29:09.697737
1736 09:29:09.697787 Set Vref, RX VrefLevel [Byte0]: 46
1737 09:29:09.697838 [Byte1]: 46
1738 09:29:09.697889
1739 09:29:09.697940 Set Vref, RX VrefLevel [Byte0]: 47
1740 09:29:09.697991 [Byte1]: 47
1741 09:29:09.698042
1742 09:29:09.698092 Set Vref, RX VrefLevel [Byte0]: 48
1743 09:29:09.698144 [Byte1]: 48
1744 09:29:09.698195
1745 09:29:09.698246 Set Vref, RX VrefLevel [Byte0]: 49
1746 09:29:09.698297 [Byte1]: 49
1747 09:29:09.698348
1748 09:29:09.698398 Set Vref, RX VrefLevel [Byte0]: 50
1749 09:29:09.698449 [Byte1]: 50
1750 09:29:09.698500
1751 09:29:09.698551 Set Vref, RX VrefLevel [Byte0]: 51
1752 09:29:09.698602 [Byte1]: 51
1753 09:29:09.698654
1754 09:29:09.698705 Set Vref, RX VrefLevel [Byte0]: 52
1755 09:29:09.698756 [Byte1]: 52
1756 09:29:09.698807
1757 09:29:09.698859 Set Vref, RX VrefLevel [Byte0]: 53
1758 09:29:09.698925 [Byte1]: 53
1759 09:29:09.698991
1760 09:29:09.699078 Set Vref, RX VrefLevel [Byte0]: 54
1761 09:29:09.699129 [Byte1]: 54
1762 09:29:09.699180
1763 09:29:09.699231 Set Vref, RX VrefLevel [Byte0]: 55
1764 09:29:09.699509 [Byte1]: 55
1765 09:29:09.699567
1766 09:29:09.699620 Set Vref, RX VrefLevel [Byte0]: 56
1767 09:29:09.699686 [Byte1]: 56
1768 09:29:09.699739
1769 09:29:09.699791 Set Vref, RX VrefLevel [Byte0]: 57
1770 09:29:09.699857 [Byte1]: 57
1771 09:29:09.699923
1772 09:29:09.699975 Set Vref, RX VrefLevel [Byte0]: 58
1773 09:29:09.700028 [Byte1]: 58
1774 09:29:09.700080
1775 09:29:09.700132 Set Vref, RX VrefLevel [Byte0]: 59
1776 09:29:09.700184 [Byte1]: 59
1777 09:29:09.700237
1778 09:29:09.700302 Set Vref, RX VrefLevel [Byte0]: 60
1779 09:29:09.700353 [Byte1]: 60
1780 09:29:09.700434
1781 09:29:09.700484 Set Vref, RX VrefLevel [Byte0]: 61
1782 09:29:09.700535 [Byte1]: 61
1783 09:29:09.700586
1784 09:29:09.700638 Set Vref, RX VrefLevel [Byte0]: 62
1785 09:29:09.700689 [Byte1]: 62
1786 09:29:09.700740
1787 09:29:09.700791 Set Vref, RX VrefLevel [Byte0]: 63
1788 09:29:09.700842 [Byte1]: 63
1789 09:29:09.700892
1790 09:29:09.700943 Set Vref, RX VrefLevel [Byte0]: 64
1791 09:29:09.700994 [Byte1]: 64
1792 09:29:09.701060
1793 09:29:09.701112 Set Vref, RX VrefLevel [Byte0]: 65
1794 09:29:09.701165 [Byte1]: 65
1795 09:29:09.701217
1796 09:29:09.701277 Set Vref, RX VrefLevel [Byte0]: 66
1797 09:29:09.701332 [Byte1]: 66
1798 09:29:09.701384
1799 09:29:09.701437 Set Vref, RX VrefLevel [Byte0]: 67
1800 09:29:09.701489 [Byte1]: 67
1801 09:29:09.701541
1802 09:29:09.701593 Set Vref, RX VrefLevel [Byte0]: 68
1803 09:29:09.701645 [Byte1]: 68
1804 09:29:09.701698
1805 09:29:09.701749 Set Vref, RX VrefLevel [Byte0]: 69
1806 09:29:09.701802 [Byte1]: 69
1807 09:29:09.701854
1808 09:29:09.701920 Set Vref, RX VrefLevel [Byte0]: 70
1809 09:29:09.701987 [Byte1]: 70
1810 09:29:09.702067
1811 09:29:09.702134 Set Vref, RX VrefLevel [Byte0]: 71
1812 09:29:09.702185 [Byte1]: 71
1813 09:29:09.702236
1814 09:29:09.702302 Set Vref, RX VrefLevel [Byte0]: 72
1815 09:29:09.702368 [Byte1]: 72
1816 09:29:09.702419
1817 09:29:09.702499 Set Vref, RX VrefLevel [Byte0]: 73
1818 09:29:09.702550 [Byte1]: 73
1819 09:29:09.702601
1820 09:29:09.702652 Set Vref, RX VrefLevel [Byte0]: 74
1821 09:29:09.702703 [Byte1]: 74
1822 09:29:09.702754
1823 09:29:09.702820 Set Vref, RX VrefLevel [Byte0]: 75
1824 09:29:09.702886 [Byte1]: 75
1825 09:29:09.702937
1826 09:29:09.702987 Final RX Vref Byte 0 = 60 to rank0
1827 09:29:09.703039 Final RX Vref Byte 1 = 53 to rank0
1828 09:29:09.703090 Final RX Vref Byte 0 = 60 to rank1
1829 09:29:09.703142 Final RX Vref Byte 1 = 53 to rank1==
1830 09:29:09.703211 Dram Type= 6, Freq= 0, CH_1, rank 0
1831 09:29:09.703278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1832 09:29:09.703330 ==
1833 09:29:09.703381 DQS Delay:
1834 09:29:09.703432 DQS0 = 0, DQS1 = 0
1835 09:29:09.703483 DQM Delay:
1836 09:29:09.703534 DQM0 = 86, DQM1 = 79
1837 09:29:09.703600 DQ Delay:
1838 09:29:09.703666 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
1839 09:29:09.703717 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1840 09:29:09.703769 DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =76
1841 09:29:09.703820 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1842 09:29:09.703871
1843 09:29:09.703922
1844 09:29:09.703988 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c2f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1845 09:29:09.704055 CH1 RK0: MR19=606, MR18=1C2F
1846 09:29:09.704106 CH1_RK0: MR19=0x606, MR18=0x1C2F, DQSOSC=397, MR23=63, INC=93, DEC=62
1847 09:29:09.704158
1848 09:29:09.704208 ----->DramcWriteLeveling(PI) begin...
1849 09:29:09.704260 ==
1850 09:29:09.704311 Dram Type= 6, Freq= 0, CH_1, rank 1
1851 09:29:09.704377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1852 09:29:09.704444 ==
1853 09:29:09.704496 Write leveling (Byte 0): 24 => 24
1854 09:29:09.704547 Write leveling (Byte 1): 30 => 30
1855 09:29:09.704627 DramcWriteLeveling(PI) end<-----
1856 09:29:09.704678
1857 09:29:09.704728 ==
1858 09:29:09.704779 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 09:29:09.704830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 09:29:09.704881 ==
1861 09:29:09.704932 [Gating] SW mode calibration
1862 09:29:09.704983 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1863 09:29:09.705035 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1864 09:29:09.705086 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1865 09:29:09.705138 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1866 09:29:09.705189 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1867 09:29:09.705240 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 09:29:09.705332 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 09:29:09.705384 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 09:29:09.705435 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 09:29:09.705485 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 09:29:09.705537 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 09:29:09.705588 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 09:29:09.705640 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 09:29:09.705690 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 09:29:09.705741 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 09:29:09.705793 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 09:29:09.705844 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 09:29:09.705895 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 09:29:09.705946 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1881 09:29:09.705997 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1882 09:29:09.706048 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1883 09:29:09.706100 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 09:29:09.706150 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 09:29:09.706202 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 09:29:09.706253 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 09:29:09.706304 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 09:29:09.706354 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 09:29:09.706406 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1890 09:29:09.706457 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1891 09:29:09.706698 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 09:29:09.706756 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 09:29:09.706808 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 09:29:09.706860 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 09:29:09.706911 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 09:29:09.706962 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1897 09:29:09.707013 0 10 4 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (0 0)
1898 09:29:09.707065 0 10 8 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
1899 09:29:09.707116 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 09:29:09.707167 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 09:29:09.707219 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 09:29:09.707271 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 09:29:09.707322 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 09:29:09.707374 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1905 09:29:09.707426 0 11 4 | B1->B0 | 2525 3f3f | 0 0 | (0 0) (0 0)
1906 09:29:09.707477 0 11 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1907 09:29:09.707529 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 09:29:09.707580 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 09:29:09.707631 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 09:29:09.707684 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 09:29:09.707736 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 09:29:09.707786 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1913 09:29:09.707837 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1914 09:29:09.707889 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 09:29:09.707940 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 09:29:09.707991 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 09:29:09.708043 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 09:29:09.708093 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 09:29:09.708145 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 09:29:09.708196 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 09:29:09.708247 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 09:29:09.708297 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 09:29:09.708348 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 09:29:09.708399 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 09:29:09.708450 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 09:29:09.708501 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 09:29:09.708553 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 09:29:09.708604 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1929 09:29:09.708656 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1930 09:29:09.708707 Total UI for P1: 0, mck2ui 16
1931 09:29:09.708759 best dqsien dly found for B0: ( 0, 14, 0)
1932 09:29:09.708810 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 09:29:09.708862 Total UI for P1: 0, mck2ui 16
1934 09:29:09.708913 best dqsien dly found for B1: ( 0, 14, 4)
1935 09:29:09.708965 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1936 09:29:09.709016 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1937 09:29:09.709067
1938 09:29:09.709118 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1939 09:29:09.709169 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1940 09:29:09.709221 [Gating] SW calibration Done
1941 09:29:09.709312 ==
1942 09:29:09.709365 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 09:29:09.709417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 09:29:09.709469 ==
1945 09:29:09.709520 RX Vref Scan: 0
1946 09:29:09.709572
1947 09:29:09.709624 RX Vref 0 -> 0, step: 1
1948 09:29:09.709675
1949 09:29:09.709725 RX Delay -130 -> 252, step: 16
1950 09:29:09.709777 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1951 09:29:09.709828 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1952 09:29:09.709880 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1953 09:29:09.709931 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1954 09:29:09.709982 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1955 09:29:09.710033 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1956 09:29:09.710085 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1957 09:29:09.710136 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1958 09:29:09.710188 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1959 09:29:09.710239 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1960 09:29:09.710290 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1961 09:29:09.710341 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1962 09:29:09.710392 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1963 09:29:09.710443 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1964 09:29:09.710495 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1965 09:29:09.710546 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1966 09:29:09.710597 ==
1967 09:29:09.710648 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 09:29:09.710700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 09:29:09.710751 ==
1970 09:29:09.710802 DQS Delay:
1971 09:29:09.710852 DQS0 = 0, DQS1 = 0
1972 09:29:09.710904 DQM Delay:
1973 09:29:09.710955 DQM0 = 80, DQM1 = 80
1974 09:29:09.711007 DQ Delay:
1975 09:29:09.711058 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1976 09:29:09.711109 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1977 09:29:09.711160 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1978 09:29:09.711211 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1979 09:29:09.711262
1980 09:29:09.711312
1981 09:29:09.711363 ==
1982 09:29:09.711414 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 09:29:09.711466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 09:29:09.711517 ==
1985 09:29:09.711568
1986 09:29:09.845383
1987 09:29:09.845513 TX Vref Scan disable
1988 09:29:09.845577 == TX Byte 0 ==
1989 09:29:09.845637 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1990 09:29:09.845730 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1991 09:29:09.845786 == TX Byte 1 ==
1992 09:29:09.845841 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1993 09:29:09.845896 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1994 09:29:09.845950 ==
1995 09:29:09.846003 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 09:29:09.846056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 09:29:09.846110 ==
1998 09:29:09.846366 TX Vref=22, minBit 1, minWin=27, winSum=446
1999 09:29:09.846427 TX Vref=24, minBit 1, minWin=27, winSum=445
2000 09:29:09.846573 TX Vref=26, minBit 6, minWin=27, winSum=453
2001 09:29:09.846702 TX Vref=28, minBit 6, minWin=27, winSum=452
2002 09:29:09.846762 TX Vref=30, minBit 5, minWin=27, winSum=453
2003 09:29:09.846818 TX Vref=32, minBit 4, minWin=27, winSum=450
2004 09:29:09.846872 [TxChooseVref] Worse bit 6, Min win 27, Win sum 453, Final Vref 26
2005 09:29:09.846927
2006 09:29:09.846980 Final TX Range 1 Vref 26
2007 09:29:09.847034
2008 09:29:09.847086 ==
2009 09:29:09.847140 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 09:29:09.847194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 09:29:09.847248 ==
2012 09:29:09.847300
2013 09:29:09.847353
2014 09:29:09.847405 TX Vref Scan disable
2015 09:29:09.847472 == TX Byte 0 ==
2016 09:29:09.847524 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2017 09:29:09.847576 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2018 09:29:09.847628 == TX Byte 1 ==
2019 09:29:09.847695 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2020 09:29:09.847763 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2021 09:29:09.847814
2022 09:29:09.847865 [DATLAT]
2023 09:29:09.847945 Freq=800, CH1 RK1
2024 09:29:09.848026
2025 09:29:09.848077 DATLAT Default: 0xa
2026 09:29:09.848128 0, 0xFFFF, sum = 0
2027 09:29:09.848182 1, 0xFFFF, sum = 0
2028 09:29:09.848235 2, 0xFFFF, sum = 0
2029 09:29:09.848286 3, 0xFFFF, sum = 0
2030 09:29:09.848338 4, 0xFFFF, sum = 0
2031 09:29:09.848391 5, 0xFFFF, sum = 0
2032 09:29:09.848467 6, 0xFFFF, sum = 0
2033 09:29:09.848534 7, 0xFFFF, sum = 0
2034 09:29:09.848586 8, 0xFFFF, sum = 0
2035 09:29:09.848638 9, 0x0, sum = 1
2036 09:29:09.848691 10, 0x0, sum = 2
2037 09:29:09.848744 11, 0x0, sum = 3
2038 09:29:09.848796 12, 0x0, sum = 4
2039 09:29:09.848848 best_step = 10
2040 09:29:09.848899
2041 09:29:09.848950 ==
2042 09:29:09.849001 Dram Type= 6, Freq= 0, CH_1, rank 1
2043 09:29:09.849054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2044 09:29:09.849106 ==
2045 09:29:09.849157 RX Vref Scan: 0
2046 09:29:09.849223
2047 09:29:09.849301 RX Vref 0 -> 0, step: 1
2048 09:29:09.849355
2049 09:29:09.849406 RX Delay -95 -> 252, step: 8
2050 09:29:09.849458 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2051 09:29:09.849511 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
2052 09:29:09.849563 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2053 09:29:09.849615 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2054 09:29:09.849667 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2055 09:29:09.849718 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2056 09:29:09.849770 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2057 09:29:09.849822 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2058 09:29:09.849873 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2059 09:29:09.849925 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2060 09:29:09.849976 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2061 09:29:09.850028 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2062 09:29:09.850080 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2063 09:29:09.850132 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2064 09:29:09.850219 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2065 09:29:09.850270 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2066 09:29:09.850322 ==
2067 09:29:09.850374 Dram Type= 6, Freq= 0, CH_1, rank 1
2068 09:29:09.850426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2069 09:29:09.850500 ==
2070 09:29:09.850567 DQS Delay:
2071 09:29:09.850619 DQS0 = 0, DQS1 = 0
2072 09:29:09.850671 DQM Delay:
2073 09:29:09.850723 DQM0 = 86, DQM1 = 82
2074 09:29:09.850774 DQ Delay:
2075 09:29:09.850826 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2076 09:29:09.850878 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2077 09:29:09.850929 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
2078 09:29:09.850981 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =88
2079 09:29:09.851032
2080 09:29:09.851083
2081 09:29:09.851134 [DQSOSCAuto] RK1, (LSB)MR18= 0x2440, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2082 09:29:09.851187 CH1 RK1: MR19=606, MR18=2440
2083 09:29:09.851239 CH1_RK1: MR19=0x606, MR18=0x2440, DQSOSC=393, MR23=63, INC=95, DEC=63
2084 09:29:09.851291 [RxdqsGatingPostProcess] freq 800
2085 09:29:09.851343 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2086 09:29:09.851395 Pre-setting of DQS Precalculation
2087 09:29:09.851446 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2088 09:29:09.851498 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2089 09:29:09.851550 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2090 09:29:09.851602
2091 09:29:09.851652
2092 09:29:09.851703 [Calibration Summary] 1600 Mbps
2093 09:29:09.851754 CH 0, Rank 0
2094 09:29:09.851806 SW Impedance : PASS
2095 09:29:09.851858 DUTY Scan : NO K
2096 09:29:09.851910 ZQ Calibration : PASS
2097 09:29:09.851961 Jitter Meter : NO K
2098 09:29:09.852013 CBT Training : PASS
2099 09:29:09.852065 Write leveling : PASS
2100 09:29:09.852116 RX DQS gating : PASS
2101 09:29:09.852168 RX DQ/DQS(RDDQC) : PASS
2102 09:29:09.852218 TX DQ/DQS : PASS
2103 09:29:09.852270 RX DATLAT : PASS
2104 09:29:09.852321 RX DQ/DQS(Engine): PASS
2105 09:29:09.852373 TX OE : NO K
2106 09:29:09.852424 All Pass.
2107 09:29:09.852476
2108 09:29:09.852527 CH 0, Rank 1
2109 09:29:09.852578 SW Impedance : PASS
2110 09:29:09.852629 DUTY Scan : NO K
2111 09:29:09.852681 ZQ Calibration : PASS
2112 09:29:09.852732 Jitter Meter : NO K
2113 09:29:09.852784 CBT Training : PASS
2114 09:29:09.852835 Write leveling : PASS
2115 09:29:09.852886 RX DQS gating : PASS
2116 09:29:09.852938 RX DQ/DQS(RDDQC) : PASS
2117 09:29:09.852989 TX DQ/DQS : PASS
2118 09:29:09.853040 RX DATLAT : PASS
2119 09:29:09.853091 RX DQ/DQS(Engine): PASS
2120 09:29:09.853142 TX OE : NO K
2121 09:29:09.853193 All Pass.
2122 09:29:09.853244
2123 09:29:09.853333 CH 1, Rank 0
2124 09:29:09.853385 SW Impedance : PASS
2125 09:29:09.853437 DUTY Scan : NO K
2126 09:29:09.853489 ZQ Calibration : PASS
2127 09:29:09.853541 Jitter Meter : NO K
2128 09:29:09.853592 CBT Training : PASS
2129 09:29:09.853643 Write leveling : PASS
2130 09:29:09.853694 RX DQS gating : PASS
2131 09:29:09.853746 RX DQ/DQS(RDDQC) : PASS
2132 09:29:09.853797 TX DQ/DQS : PASS
2133 09:29:09.853848 RX DATLAT : PASS
2134 09:29:09.853899 RX DQ/DQS(Engine): PASS
2135 09:29:09.853950 TX OE : NO K
2136 09:29:09.854002 All Pass.
2137 09:29:09.854053
2138 09:29:09.854104 CH 1, Rank 1
2139 09:29:09.854155 SW Impedance : PASS
2140 09:29:09.854236 DUTY Scan : NO K
2141 09:29:09.854287 ZQ Calibration : PASS
2142 09:29:09.854338 Jitter Meter : NO K
2143 09:29:09.854389 CBT Training : PASS
2144 09:29:09.854440 Write leveling : PASS
2145 09:29:09.854498 RX DQS gating : PASS
2146 09:29:09.854550 RX DQ/DQS(RDDQC) : PASS
2147 09:29:09.854601 TX DQ/DQS : PASS
2148 09:29:09.854880 RX DATLAT : PASS
2149 09:29:09.854968 RX DQ/DQS(Engine): PASS
2150 09:29:09.855022 TX OE : NO K
2151 09:29:09.855076 All Pass.
2152 09:29:09.855130
2153 09:29:09.855183 DramC Write-DBI off
2154 09:29:09.855238 PER_BANK_REFRESH: Hybrid Mode
2155 09:29:09.855291 TX_TRACKING: ON
2156 09:29:09.855345 [GetDramInforAfterCalByMRR] Vendor 6.
2157 09:29:09.855398 [GetDramInforAfterCalByMRR] Revision 606.
2158 09:29:09.855466 [GetDramInforAfterCalByMRR] Revision 2 0.
2159 09:29:09.855517 MR0 0x3b3b
2160 09:29:09.855583 MR8 0x5151
2161 09:29:09.855649 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2162 09:29:09.855701
2163 09:29:09.855751 MR0 0x3b3b
2164 09:29:09.855803 MR8 0x5151
2165 09:29:09.855883 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 09:29:09.855935
2167 09:29:09.855986 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2168 09:29:09.856038 [FAST_K] Save calibration result to emmc
2169 09:29:09.856090 [FAST_K] Save calibration result to emmc
2170 09:29:09.856142 dram_init: config_dvfs: 1
2171 09:29:09.856208 dramc_set_vcore_voltage set vcore to 662500
2172 09:29:09.856275 Read voltage for 1200, 2
2173 09:29:09.856327 Vio18 = 0
2174 09:29:09.856379 Vcore = 662500
2175 09:29:09.856430 Vdram = 0
2176 09:29:09.856532 Vddq = 0
2177 09:29:09.856632 Vmddr = 0
2178 09:29:09.856718 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2179 09:29:09.856774 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2180 09:29:09.856828 MEM_TYPE=3, freq_sel=15
2181 09:29:09.856880 sv_algorithm_assistance_LP4_1600
2182 09:29:09.856933 ============ PULL DRAM RESETB DOWN ============
2183 09:29:09.856985 ========== PULL DRAM RESETB DOWN end =========
2184 09:29:09.857038 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2185 09:29:09.857090 ===================================
2186 09:29:09.857142 LPDDR4 DRAM CONFIGURATION
2187 09:29:09.857194 ===================================
2188 09:29:09.857246 EX_ROW_EN[0] = 0x0
2189 09:29:09.857376 EX_ROW_EN[1] = 0x0
2190 09:29:09.857430 LP4Y_EN = 0x0
2191 09:29:09.857481 WORK_FSP = 0x0
2192 09:29:09.857533 WL = 0x4
2193 09:29:09.857585 RL = 0x4
2194 09:29:09.857637 BL = 0x2
2195 09:29:09.857688 RPST = 0x0
2196 09:29:09.857740 RD_PRE = 0x0
2197 09:29:09.857791 WR_PRE = 0x1
2198 09:29:09.857843 WR_PST = 0x0
2199 09:29:09.857895 DBI_WR = 0x0
2200 09:29:09.857946 DBI_RD = 0x0
2201 09:29:09.857998 OTF = 0x1
2202 09:29:09.858050 ===================================
2203 09:29:09.858103 ===================================
2204 09:29:09.858155 ANA top config
2205 09:29:09.858207 ===================================
2206 09:29:09.858259 DLL_ASYNC_EN = 0
2207 09:29:09.858311 ALL_SLAVE_EN = 0
2208 09:29:09.858363 NEW_RANK_MODE = 1
2209 09:29:09.858415 DLL_IDLE_MODE = 1
2210 09:29:09.858467 LP45_APHY_COMB_EN = 1
2211 09:29:09.858518 TX_ODT_DIS = 1
2212 09:29:09.858571 NEW_8X_MODE = 1
2213 09:29:09.858623 ===================================
2214 09:29:09.858676 ===================================
2215 09:29:09.858728 data_rate = 2400
2216 09:29:09.858780 CKR = 1
2217 09:29:09.858867 DQ_P2S_RATIO = 8
2218 09:29:09.858918 ===================================
2219 09:29:09.858971 CA_P2S_RATIO = 8
2220 09:29:09.859023 DQ_CA_OPEN = 0
2221 09:29:09.859075 DQ_SEMI_OPEN = 0
2222 09:29:09.859127 CA_SEMI_OPEN = 0
2223 09:29:09.859210 CA_FULL_RATE = 0
2224 09:29:09.859262 DQ_CKDIV4_EN = 0
2225 09:29:09.859314 CA_CKDIV4_EN = 0
2226 09:29:09.859365 CA_PREDIV_EN = 0
2227 09:29:09.859418 PH8_DLY = 17
2228 09:29:09.859470 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2229 09:29:09.859522 DQ_AAMCK_DIV = 4
2230 09:29:09.859574 CA_AAMCK_DIV = 4
2231 09:29:09.859626 CA_ADMCK_DIV = 4
2232 09:29:09.859678 DQ_TRACK_CA_EN = 0
2233 09:29:09.859730 CA_PICK = 1200
2234 09:29:09.859782 CA_MCKIO = 1200
2235 09:29:09.859834 MCKIO_SEMI = 0
2236 09:29:09.859886 PLL_FREQ = 2366
2237 09:29:09.859939 DQ_UI_PI_RATIO = 32
2238 09:29:09.859991 CA_UI_PI_RATIO = 0
2239 09:29:09.860043 ===================================
2240 09:29:09.860095 ===================================
2241 09:29:09.860147 memory_type:LPDDR4
2242 09:29:09.860229 GP_NUM : 10
2243 09:29:09.860296 SRAM_EN : 1
2244 09:29:09.860362 MD32_EN : 0
2245 09:29:09.860414 ===================================
2246 09:29:09.860481 [ANA_INIT] >>>>>>>>>>>>>>
2247 09:29:09.860547 <<<<<< [CONFIGURE PHASE]: ANA_TX
2248 09:29:09.860634 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2249 09:29:09.860686 ===================================
2250 09:29:09.860739 data_rate = 2400,PCW = 0X5b00
2251 09:29:09.860791 ===================================
2252 09:29:09.860843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2253 09:29:09.860902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2254 09:29:09.860959 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2255 09:29:09.861012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2256 09:29:09.861065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2257 09:29:09.861116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2258 09:29:09.861169 [ANA_INIT] flow start
2259 09:29:09.861221 [ANA_INIT] PLL >>>>>>>>
2260 09:29:09.861296 [ANA_INIT] PLL <<<<<<<<
2261 09:29:09.861363 [ANA_INIT] MIDPI >>>>>>>>
2262 09:29:09.861415 [ANA_INIT] MIDPI <<<<<<<<
2263 09:29:09.861467 [ANA_INIT] DLL >>>>>>>>
2264 09:29:09.861519 [ANA_INIT] DLL <<<<<<<<
2265 09:29:09.861570 [ANA_INIT] flow end
2266 09:29:09.861622 ============ LP4 DIFF to SE enter ============
2267 09:29:09.861676 ============ LP4 DIFF to SE exit ============
2268 09:29:09.861729 [ANA_INIT] <<<<<<<<<<<<<
2269 09:29:09.861781 [Flow] Enable top DCM control >>>>>
2270 09:29:09.861862 [Flow] Enable top DCM control <<<<<
2271 09:29:09.861914 Enable DLL master slave shuffle
2272 09:29:09.861967 ==============================================================
2273 09:29:09.862019 Gating Mode config
2274 09:29:09.862071 ==============================================================
2275 09:29:09.862124 Config description:
2276 09:29:09.862369 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2277 09:29:09.862430 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2278 09:29:09.862507 SELPH_MODE 0: By rank 1: By Phase
2279 09:29:09.862567 ==============================================================
2280 09:29:09.862672 GAT_TRACK_EN = 1
2281 09:29:09.862759 RX_GATING_MODE = 2
2282 09:29:09.862832 RX_GATING_TRACK_MODE = 2
2283 09:29:09.862887 SELPH_MODE = 1
2284 09:29:09.862955 PICG_EARLY_EN = 1
2285 09:29:09.863024 VALID_LAT_VALUE = 1
2286 09:29:09.863077 ==============================================================
2287 09:29:09.863130 Enter into Gating configuration >>>>
2288 09:29:09.863182 Exit from Gating configuration <<<<
2289 09:29:09.863234 Enter into DVFS_PRE_config >>>>>
2290 09:29:09.863287 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2291 09:29:09.863340 Exit from DVFS_PRE_config <<<<<
2292 09:29:09.863392 Enter into PICG configuration >>>>
2293 09:29:09.863443 Exit from PICG configuration <<<<
2294 09:29:09.863496 [RX_INPUT] configuration >>>>>
2295 09:29:09.863548 [RX_INPUT] configuration <<<<<
2296 09:29:09.863600 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2297 09:29:09.863652 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2298 09:29:09.863705 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2299 09:29:09.863757 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2300 09:29:09.863809 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 09:29:09.863861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 09:29:09.863913 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2303 09:29:09.863964 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2304 09:29:09.864017 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2305 09:29:09.864070 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2306 09:29:09.864122 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2307 09:29:09.864174 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2308 09:29:09.864227 ===================================
2309 09:29:09.864279 LPDDR4 DRAM CONFIGURATION
2310 09:29:09.864331 ===================================
2311 09:29:09.864384 EX_ROW_EN[0] = 0x0
2312 09:29:09.864436 EX_ROW_EN[1] = 0x0
2313 09:29:09.864488 LP4Y_EN = 0x0
2314 09:29:09.864540 WORK_FSP = 0x0
2315 09:29:09.864592 WL = 0x4
2316 09:29:09.864643 RL = 0x4
2317 09:29:09.864695 BL = 0x2
2318 09:29:09.864747 RPST = 0x0
2319 09:29:09.864798 RD_PRE = 0x0
2320 09:29:09.864850 WR_PRE = 0x1
2321 09:29:09.864902 WR_PST = 0x0
2322 09:29:09.864953 DBI_WR = 0x0
2323 09:29:09.865006 DBI_RD = 0x0
2324 09:29:09.865057 OTF = 0x1
2325 09:29:09.865109 ===================================
2326 09:29:09.865162 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2327 09:29:09.865214 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2328 09:29:09.865293 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2329 09:29:09.865362 ===================================
2330 09:29:09.865415 LPDDR4 DRAM CONFIGURATION
2331 09:29:09.865467 ===================================
2332 09:29:09.865519 EX_ROW_EN[0] = 0x10
2333 09:29:09.865571 EX_ROW_EN[1] = 0x0
2334 09:29:09.865623 LP4Y_EN = 0x0
2335 09:29:09.865675 WORK_FSP = 0x0
2336 09:29:09.865727 WL = 0x4
2337 09:29:09.865778 RL = 0x4
2338 09:29:09.865830 BL = 0x2
2339 09:29:09.865882 RPST = 0x0
2340 09:29:09.865934 RD_PRE = 0x0
2341 09:29:09.865985 WR_PRE = 0x1
2342 09:29:09.866037 WR_PST = 0x0
2343 09:29:09.866089 DBI_WR = 0x0
2344 09:29:09.866141 DBI_RD = 0x0
2345 09:29:09.866192 OTF = 0x1
2346 09:29:09.866259 ===================================
2347 09:29:09.866312 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2348 09:29:09.866365 ==
2349 09:29:09.866417 Dram Type= 6, Freq= 0, CH_0, rank 0
2350 09:29:09.866485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2351 09:29:09.866567 ==
2352 09:29:09.866651 [Duty_Offset_Calibration]
2353 09:29:09.866738 B0:2 B1:0 CA:4
2354 09:29:09.866802
2355 09:29:09.866855 [DutyScan_Calibration_Flow] k_type=0
2356 09:29:09.866908
2357 09:29:09.866997 ==CLK 0==
2358 09:29:09.867049 Final CLK duty delay cell = 0
2359 09:29:09.867101 [0] MAX Duty = 5156%(X100), DQS PI = 14
2360 09:29:09.867154 [0] MIN Duty = 4969%(X100), DQS PI = 8
2361 09:29:09.867206 [0] AVG Duty = 5062%(X100)
2362 09:29:09.867257
2363 09:29:09.867309 CH0 CLK Duty spec in!! Max-Min= 187%
2364 09:29:09.867361 [DutyScan_Calibration_Flow] ====Done====
2365 09:29:09.867413
2366 09:29:09.867464 [DutyScan_Calibration_Flow] k_type=1
2367 09:29:09.867515
2368 09:29:09.867567 ==DQS 0 ==
2369 09:29:09.867618 Final DQS duty delay cell = 0
2370 09:29:09.867670 [0] MAX Duty = 5156%(X100), DQS PI = 18
2371 09:29:09.867722 [0] MIN Duty = 5093%(X100), DQS PI = 0
2372 09:29:09.867774 [0] AVG Duty = 5124%(X100)
2373 09:29:09.867825
2374 09:29:09.867876 ==DQS 1 ==
2375 09:29:09.867928 Final DQS duty delay cell = 0
2376 09:29:09.867979 [0] MAX Duty = 5125%(X100), DQS PI = 50
2377 09:29:09.868031 [0] MIN Duty = 4969%(X100), DQS PI = 62
2378 09:29:09.868082 [0] AVG Duty = 5047%(X100)
2379 09:29:09.868133
2380 09:29:09.868184 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2381 09:29:09.868236
2382 09:29:09.868287 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2383 09:29:09.868338 [DutyScan_Calibration_Flow] ====Done====
2384 09:29:09.868389
2385 09:29:09.868440 [DutyScan_Calibration_Flow] k_type=3
2386 09:29:09.868562
2387 09:29:09.868648 ==DQM 0 ==
2388 09:29:09.868701 Final DQM duty delay cell = 0
2389 09:29:09.868768 [0] MAX Duty = 5125%(X100), DQS PI = 20
2390 09:29:09.868820 [0] MIN Duty = 4844%(X100), DQS PI = 50
2391 09:29:09.868871 [0] AVG Duty = 4984%(X100)
2392 09:29:09.868923
2393 09:29:09.868974 ==DQM 1 ==
2394 09:29:09.869025 Final DQM duty delay cell = 0
2395 09:29:09.869077 [0] MAX Duty = 4969%(X100), DQS PI = 2
2396 09:29:09.869129 [0] MIN Duty = 4875%(X100), DQS PI = 18
2397 09:29:09.869180 [0] AVG Duty = 4922%(X100)
2398 09:29:09.869231
2399 09:29:09.869309 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2400 09:29:09.869376
2401 09:29:09.869427 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2402 09:29:09.869478 [DutyScan_Calibration_Flow] ====Done====
2403 09:29:09.869531
2404 09:29:09.869583 [DutyScan_Calibration_Flow] k_type=2
2405 09:29:09.869634
2406 09:29:09.869685 ==DQ 0 ==
2407 09:29:09.869929 Final DQ duty delay cell = 0
2408 09:29:09.869988 [0] MAX Duty = 5156%(X100), DQS PI = 18
2409 09:29:09.870040 [0] MIN Duty = 4969%(X100), DQS PI = 58
2410 09:29:09.870092 [0] AVG Duty = 5062%(X100)
2411 09:29:09.870144
2412 09:29:09.870196 ==DQ 1 ==
2413 09:29:09.870248 Final DQ duty delay cell = 0
2414 09:29:09.870300 [0] MAX Duty = 5125%(X100), DQS PI = 4
2415 09:29:09.870352 [0] MIN Duty = 4938%(X100), DQS PI = 14
2416 09:29:09.870404 [0] AVG Duty = 5031%(X100)
2417 09:29:09.870520
2418 09:29:09.870609 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2419 09:29:09.870693
2420 09:29:09.870772 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2421 09:29:09.870827 [DutyScan_Calibration_Flow] ====Done====
2422 09:29:09.870880 ==
2423 09:29:09.870933 Dram Type= 6, Freq= 0, CH_1, rank 0
2424 09:29:09.870986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2425 09:29:09.871038 ==
2426 09:29:09.871090 [Duty_Offset_Calibration]
2427 09:29:09.871142 B0:0 B1:-1 CA:3
2428 09:29:09.871193
2429 09:29:09.871244 [DutyScan_Calibration_Flow] k_type=0
2430 09:29:09.871295
2431 09:29:09.871346 ==CLK 0==
2432 09:29:09.871398 Final CLK duty delay cell = -4
2433 09:29:09.871450 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2434 09:29:09.871502 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2435 09:29:09.871553 [-4] AVG Duty = 4938%(X100)
2436 09:29:09.871605
2437 09:29:09.871656 CH1 CLK Duty spec in!! Max-Min= 124%
2438 09:29:09.871708 [DutyScan_Calibration_Flow] ====Done====
2439 09:29:09.871760
2440 09:29:09.871810 [DutyScan_Calibration_Flow] k_type=1
2441 09:29:09.871861
2442 09:29:09.871912 ==DQS 0 ==
2443 09:29:09.871963 Final DQS duty delay cell = 0
2444 09:29:09.872015 [0] MAX Duty = 5187%(X100), DQS PI = 18
2445 09:29:09.872067 [0] MIN Duty = 4907%(X100), DQS PI = 38
2446 09:29:09.872119 [0] AVG Duty = 5047%(X100)
2447 09:29:09.872171
2448 09:29:09.872222 ==DQS 1 ==
2449 09:29:09.872273 Final DQS duty delay cell = 0
2450 09:29:09.872326 [0] MAX Duty = 5156%(X100), DQS PI = 8
2451 09:29:09.872377 [0] MIN Duty = 5031%(X100), DQS PI = 18
2452 09:29:09.872428 [0] AVG Duty = 5093%(X100)
2453 09:29:09.872480
2454 09:29:09.872531 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2455 09:29:09.872583
2456 09:29:09.872634 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2457 09:29:09.872685 [DutyScan_Calibration_Flow] ====Done====
2458 09:29:09.872736
2459 09:29:09.872787 [DutyScan_Calibration_Flow] k_type=3
2460 09:29:09.872838
2461 09:29:09.872889 ==DQM 0 ==
2462 09:29:09.872941 Final DQM duty delay cell = 0
2463 09:29:09.872994 [0] MAX Duty = 5031%(X100), DQS PI = 30
2464 09:29:09.873045 [0] MIN Duty = 4782%(X100), DQS PI = 38
2465 09:29:09.873097 [0] AVG Duty = 4906%(X100)
2466 09:29:09.873148
2467 09:29:09.873199 ==DQM 1 ==
2468 09:29:09.873251 Final DQM duty delay cell = 4
2469 09:29:09.873349 [4] MAX Duty = 5187%(X100), DQS PI = 32
2470 09:29:09.873402 [4] MIN Duty = 5062%(X100), DQS PI = 18
2471 09:29:09.873454 [4] AVG Duty = 5124%(X100)
2472 09:29:09.873506
2473 09:29:09.873557 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2474 09:29:09.873609
2475 09:29:09.873660 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2476 09:29:09.873712 [DutyScan_Calibration_Flow] ====Done====
2477 09:29:09.873763
2478 09:29:09.873814 [DutyScan_Calibration_Flow] k_type=2
2479 09:29:09.873865
2480 09:29:09.873917 ==DQ 0 ==
2481 09:29:09.873968 Final DQ duty delay cell = -4
2482 09:29:09.874020 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2483 09:29:09.874072 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2484 09:29:09.874124 [-4] AVG Duty = 4922%(X100)
2485 09:29:09.874175
2486 09:29:09.874226 ==DQ 1 ==
2487 09:29:09.874278 Final DQ duty delay cell = 4
2488 09:29:09.874329 [4] MAX Duty = 5156%(X100), DQS PI = 10
2489 09:29:09.874382 [4] MIN Duty = 5031%(X100), DQS PI = 0
2490 09:29:09.874433 [4] AVG Duty = 5093%(X100)
2491 09:29:09.874520
2492 09:29:09.874632 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2493 09:29:09.874740
2494 09:29:09.874798 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2495 09:29:09.874851 [DutyScan_Calibration_Flow] ====Done====
2496 09:29:09.874903 nWR fixed to 30
2497 09:29:09.874956 [ModeRegInit_LP4] CH0 RK0
2498 09:29:09.875009 [ModeRegInit_LP4] CH0 RK1
2499 09:29:09.875061 [ModeRegInit_LP4] CH1 RK0
2500 09:29:09.875112 [ModeRegInit_LP4] CH1 RK1
2501 09:29:09.875163 match AC timing 7
2502 09:29:09.875216 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2503 09:29:09.875268 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2504 09:29:09.875320 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2505 09:29:09.875372 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2506 09:29:09.875424 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2507 09:29:09.875476 ==
2508 09:29:09.875528 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 09:29:09.875580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 09:29:09.875632 ==
2511 09:29:09.875683 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2512 09:29:09.875735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2513 09:29:09.875787 [CA 0] Center 39 (9~70) winsize 62
2514 09:29:09.875839 [CA 1] Center 38 (8~69) winsize 62
2515 09:29:09.875890 [CA 2] Center 35 (5~66) winsize 62
2516 09:29:09.875942 [CA 3] Center 35 (5~66) winsize 62
2517 09:29:09.875993 [CA 4] Center 33 (3~64) winsize 62
2518 09:29:09.876044 [CA 5] Center 33 (3~63) winsize 61
2519 09:29:09.876095
2520 09:29:09.876147 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2521 09:29:09.876198
2522 09:29:09.876249 [CATrainingPosCal] consider 1 rank data
2523 09:29:09.876300 u2DelayCellTimex100 = 270/100 ps
2524 09:29:09.876352 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2525 09:29:09.876404 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2526 09:29:09.876455 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2527 09:29:09.876506 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2528 09:29:09.876559 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2529 09:29:09.876634 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2530 09:29:09.876701
2531 09:29:09.876751 CA PerBit enable=1, Macro0, CA PI delay=33
2532 09:29:09.876803
2533 09:29:09.876854 [CBTSetCACLKResult] CA Dly = 33
2534 09:29:09.876905 CS Dly: 7 (0~38)
2535 09:29:09.876956 ==
2536 09:29:09.877007 Dram Type= 6, Freq= 0, CH_0, rank 1
2537 09:29:09.877059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 09:29:09.877111 ==
2539 09:29:09.877162 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2540 09:29:09.877214 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2541 09:29:09.877298 [CA 0] Center 39 (9~70) winsize 62
2542 09:29:09.877368 [CA 1] Center 39 (9~70) winsize 62
2543 09:29:09.877419 [CA 2] Center 35 (5~66) winsize 62
2544 09:29:09.877471 [CA 3] Center 35 (5~66) winsize 62
2545 09:29:09.877522 [CA 4] Center 34 (4~65) winsize 62
2546 09:29:09.877573 [CA 5] Center 33 (3~64) winsize 62
2547 09:29:09.877624
2548 09:29:09.877675 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2549 09:29:09.877726
2550 09:29:09.877983 [CATrainingPosCal] consider 2 rank data
2551 09:29:09.878046 u2DelayCellTimex100 = 270/100 ps
2552 09:29:09.878101 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2553 09:29:09.878154 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2554 09:29:09.878206 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2555 09:29:09.878258 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2556 09:29:09.878310 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2557 09:29:09.878362 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2558 09:29:09.878413
2559 09:29:09.878463 CA PerBit enable=1, Macro0, CA PI delay=33
2560 09:29:09.878515
2561 09:29:09.878567 [CBTSetCACLKResult] CA Dly = 33
2562 09:29:09.878618 CS Dly: 8 (0~41)
2563 09:29:09.878670
2564 09:29:09.878722 ----->DramcWriteLeveling(PI) begin...
2565 09:29:09.878775 ==
2566 09:29:09.878827 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 09:29:09.878879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 09:29:09.878932 ==
2569 09:29:09.878984 Write leveling (Byte 0): 30 => 30
2570 09:29:09.879036 Write leveling (Byte 1): 26 => 26
2571 09:29:09.879087 DramcWriteLeveling(PI) end<-----
2572 09:29:09.879139
2573 09:29:09.879191 ==
2574 09:29:09.879242 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 09:29:09.879294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 09:29:09.879346 ==
2577 09:29:09.879398 [Gating] SW mode calibration
2578 09:29:09.879449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2579 09:29:09.879502 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2580 09:29:09.879553 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2581 09:29:09.879605 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
2582 09:29:09.879657 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 09:29:09.879709 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 09:29:09.879761 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 09:29:09.879813 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2586 09:29:09.879864 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2587 09:29:09.879916 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
2588 09:29:09.879967 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2589 09:29:09.880019 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2590 09:29:09.880070 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 09:29:09.880121 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 09:29:09.880173 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 09:29:09.880225 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 09:29:09.880277 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2595 09:29:09.880328 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2596 09:29:09.880379 1 1 0 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2597 09:29:09.880431 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 09:29:09.880482 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 09:29:09.880533 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 09:29:09.880585 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 09:29:09.880671 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 09:29:09.880723 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 09:29:09.880775 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2604 09:29:09.880827 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2605 09:29:09.880878 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2606 09:29:09.880930 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 09:29:09.880981 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 09:29:09.881033 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 09:29:09.881084 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 09:29:09.881136 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 09:29:09.881187 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 09:29:09.881238 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 09:29:09.881364 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 09:29:09.881419 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 09:29:09.881471 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 09:29:09.881523 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 09:29:09.881575 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 09:29:09.881627 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2619 09:29:09.881679 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2620 09:29:09.881730 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2621 09:29:09.881781 Total UI for P1: 0, mck2ui 16
2622 09:29:09.881834 best dqsien dly found for B0: ( 1, 3, 26)
2623 09:29:09.881887 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2624 09:29:09.881939 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 09:29:09.881990 Total UI for P1: 0, mck2ui 16
2626 09:29:09.882042 best dqsien dly found for B1: ( 1, 4, 2)
2627 09:29:09.882094 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2628 09:29:09.882146 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2629 09:29:09.882198
2630 09:29:09.882250 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2631 09:29:09.882302 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2632 09:29:09.882353 [Gating] SW calibration Done
2633 09:29:09.882405 ==
2634 09:29:09.882456 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 09:29:09.882508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 09:29:09.882561 ==
2637 09:29:09.882612 RX Vref Scan: 0
2638 09:29:09.882664
2639 09:29:09.882733 RX Vref 0 -> 0, step: 1
2640 09:29:09.882800
2641 09:29:09.882851 RX Delay -40 -> 252, step: 8
2642 09:29:09.882903 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2643 09:29:09.882955 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2644 09:29:09.883007 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2645 09:29:09.883058 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2646 09:29:09.883110 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2647 09:29:09.883161 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2648 09:29:09.883212 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2649 09:29:09.883263 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2650 09:29:09.883314 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2651 09:29:09.883366 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2652 09:29:09.883611 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2653 09:29:09.883671 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2654 09:29:09.883724 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2655 09:29:09.883776 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2656 09:29:09.883828 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2657 09:29:09.883880 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2658 09:29:09.883932 ==
2659 09:29:09.883984 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 09:29:09.884036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 09:29:09.884088 ==
2662 09:29:09.884140 DQS Delay:
2663 09:29:09.884191 DQS0 = 0, DQS1 = 0
2664 09:29:09.884243 DQM Delay:
2665 09:29:09.884295 DQM0 = 119, DQM1 = 107
2666 09:29:09.884346 DQ Delay:
2667 09:29:09.884397 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2668 09:29:09.884449 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2669 09:29:09.884501 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2670 09:29:09.884552 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2671 09:29:09.884604
2672 09:29:09.884655
2673 09:29:09.884706 ==
2674 09:29:09.884757 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 09:29:09.884809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 09:29:09.884861 ==
2677 09:29:09.884912
2678 09:29:09.884983
2679 09:29:09.885050 TX Vref Scan disable
2680 09:29:09.885102 == TX Byte 0 ==
2681 09:29:09.885153 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2682 09:29:09.885205 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2683 09:29:09.885278 == TX Byte 1 ==
2684 09:29:09.885348 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2685 09:29:09.885400 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2686 09:29:09.885468 ==
2687 09:29:09.885530 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 09:29:09.885606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 09:29:09.885689 ==
2690 09:29:09.885778 TX Vref=22, minBit 5, minWin=24, winSum=410
2691 09:29:09.885838 TX Vref=24, minBit 10, minWin=24, winSum=413
2692 09:29:09.885891 TX Vref=26, minBit 1, minWin=25, winSum=419
2693 09:29:09.885945 TX Vref=28, minBit 4, minWin=25, winSum=422
2694 09:29:09.885998 TX Vref=30, minBit 2, minWin=26, winSum=426
2695 09:29:09.886050 TX Vref=32, minBit 0, minWin=26, winSum=424
2696 09:29:09.886103 [TxChooseVref] Worse bit 2, Min win 26, Win sum 426, Final Vref 30
2697 09:29:09.886156
2698 09:29:09.886208 Final TX Range 1 Vref 30
2699 09:29:09.886260
2700 09:29:09.886311 ==
2701 09:29:09.886363 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 09:29:09.886415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 09:29:09.886468 ==
2704 09:29:09.886520
2705 09:29:09.886571
2706 09:29:09.886623 TX Vref Scan disable
2707 09:29:09.886674 == TX Byte 0 ==
2708 09:29:09.886801 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2709 09:29:09.886853 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2710 09:29:09.886905 == TX Byte 1 ==
2711 09:29:09.886975 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2712 09:29:09.887041 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2713 09:29:09.887093
2714 09:29:09.887144 [DATLAT]
2715 09:29:09.887210 Freq=1200, CH0 RK0
2716 09:29:09.887277
2717 09:29:09.887328 DATLAT Default: 0xd
2718 09:29:09.887380 0, 0xFFFF, sum = 0
2719 09:29:09.887448 1, 0xFFFF, sum = 0
2720 09:29:09.887516 2, 0xFFFF, sum = 0
2721 09:29:09.887569 3, 0xFFFF, sum = 0
2722 09:29:09.887621 4, 0xFFFF, sum = 0
2723 09:29:09.887674 5, 0xFFFF, sum = 0
2724 09:29:09.887727 6, 0xFFFF, sum = 0
2725 09:29:09.887780 7, 0xFFFF, sum = 0
2726 09:29:09.887832 8, 0xFFFF, sum = 0
2727 09:29:09.887884 9, 0xFFFF, sum = 0
2728 09:29:09.887951 10, 0xFFFF, sum = 0
2729 09:29:09.888017 11, 0xFFFF, sum = 0
2730 09:29:09.888070 12, 0x0, sum = 1
2731 09:29:09.888122 13, 0x0, sum = 2
2732 09:29:09.888175 14, 0x0, sum = 3
2733 09:29:09.888228 15, 0x0, sum = 4
2734 09:29:09.888280 best_step = 13
2735 09:29:09.888332
2736 09:29:09.888383 ==
2737 09:29:09.888434 Dram Type= 6, Freq= 0, CH_0, rank 0
2738 09:29:09.888515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2739 09:29:09.888567 ==
2740 09:29:09.888619 RX Vref Scan: 1
2741 09:29:09.888684
2742 09:29:09.888750 Set Vref Range= 32 -> 127
2743 09:29:09.888802
2744 09:29:09.888854 RX Vref 32 -> 127, step: 1
2745 09:29:09.888905
2746 09:29:09.889009 RX Delay -21 -> 252, step: 4
2747 09:29:09.889062
2748 09:29:09.889114 Set Vref, RX VrefLevel [Byte0]: 32
2749 09:29:09.889168 [Byte1]: 32
2750 09:29:09.889221
2751 09:29:09.889296 Set Vref, RX VrefLevel [Byte0]: 33
2752 09:29:09.889349 [Byte1]: 33
2753 09:29:09.889402
2754 09:29:09.889507 Set Vref, RX VrefLevel [Byte0]: 34
2755 09:29:09.889572 [Byte1]: 34
2756 09:29:09.889624
2757 09:29:09.889704 Set Vref, RX VrefLevel [Byte0]: 35
2758 09:29:09.889772 [Byte1]: 35
2759 09:29:09.889864
2760 09:29:09.889949 Set Vref, RX VrefLevel [Byte0]: 36
2761 09:29:09.890038 [Byte1]: 36
2762 09:29:09.890125
2763 09:29:09.890181 Set Vref, RX VrefLevel [Byte0]: 37
2764 09:29:09.890234 [Byte1]: 37
2765 09:29:09.890288
2766 09:29:09.890340 Set Vref, RX VrefLevel [Byte0]: 38
2767 09:29:09.890392 [Byte1]: 38
2768 09:29:09.890444
2769 09:29:09.890495 Set Vref, RX VrefLevel [Byte0]: 39
2770 09:29:09.890548 [Byte1]: 39
2771 09:29:09.890600
2772 09:29:09.890651 Set Vref, RX VrefLevel [Byte0]: 40
2773 09:29:09.890703 [Byte1]: 40
2774 09:29:09.890755
2775 09:29:09.890807 Set Vref, RX VrefLevel [Byte0]: 41
2776 09:29:09.890858 [Byte1]: 41
2777 09:29:09.890910
2778 09:29:09.890960 Set Vref, RX VrefLevel [Byte0]: 42
2779 09:29:09.891012 [Byte1]: 42
2780 09:29:09.891064
2781 09:29:09.891115 Set Vref, RX VrefLevel [Byte0]: 43
2782 09:29:09.891167 [Byte1]: 43
2783 09:29:09.891219
2784 09:29:09.891270 Set Vref, RX VrefLevel [Byte0]: 44
2785 09:29:09.891322 [Byte1]: 44
2786 09:29:09.891373
2787 09:29:09.891424 Set Vref, RX VrefLevel [Byte0]: 45
2788 09:29:09.891476 [Byte1]: 45
2789 09:29:09.891527
2790 09:29:09.891578 Set Vref, RX VrefLevel [Byte0]: 46
2791 09:29:09.891629 [Byte1]: 46
2792 09:29:09.891680
2793 09:29:09.891731 Set Vref, RX VrefLevel [Byte0]: 47
2794 09:29:09.891783 [Byte1]: 47
2795 09:29:09.891835
2796 09:29:09.891886 Set Vref, RX VrefLevel [Byte0]: 48
2797 09:29:09.891938 [Byte1]: 48
2798 09:29:09.891989
2799 09:29:09.892040 Set Vref, RX VrefLevel [Byte0]: 49
2800 09:29:09.892092 [Byte1]: 49
2801 09:29:09.892143
2802 09:29:09.892194 Set Vref, RX VrefLevel [Byte0]: 50
2803 09:29:09.892246 [Byte1]: 50
2804 09:29:09.892297
2805 09:29:09.892349 Set Vref, RX VrefLevel [Byte0]: 51
2806 09:29:09.892400 [Byte1]: 51
2807 09:29:09.892452
2808 09:29:09.892503 Set Vref, RX VrefLevel [Byte0]: 52
2809 09:29:09.892555 [Byte1]: 52
2810 09:29:09.892607
2811 09:29:09.892658 Set Vref, RX VrefLevel [Byte0]: 53
2812 09:29:09.892709 [Byte1]: 53
2813 09:29:09.892761
2814 09:29:09.892812 Set Vref, RX VrefLevel [Byte0]: 54
2815 09:29:09.893062 [Byte1]: 54
2816 09:29:09.893121
2817 09:29:09.893173 Set Vref, RX VrefLevel [Byte0]: 55
2818 09:29:09.893225 [Byte1]: 55
2819 09:29:09.893318
2820 09:29:09.893370 Set Vref, RX VrefLevel [Byte0]: 56
2821 09:29:09.893470 [Byte1]: 56
2822 09:29:09.893542
2823 09:29:09.893594 Set Vref, RX VrefLevel [Byte0]: 57
2824 09:29:09.893646 [Byte1]: 57
2825 09:29:09.893698
2826 09:29:09.893749 Set Vref, RX VrefLevel [Byte0]: 58
2827 09:29:09.893801 [Byte1]: 58
2828 09:29:09.893853
2829 09:29:09.893904 Set Vref, RX VrefLevel [Byte0]: 59
2830 09:29:09.893956 [Byte1]: 59
2831 09:29:09.894008
2832 09:29:09.894059 Set Vref, RX VrefLevel [Byte0]: 60
2833 09:29:09.894110 [Byte1]: 60
2834 09:29:09.894162
2835 09:29:09.894214 Set Vref, RX VrefLevel [Byte0]: 61
2836 09:29:09.894266 [Byte1]: 61
2837 09:29:09.894317
2838 09:29:09.894368 Set Vref, RX VrefLevel [Byte0]: 62
2839 09:29:09.894420 [Byte1]: 62
2840 09:29:09.894471
2841 09:29:09.894522 Set Vref, RX VrefLevel [Byte0]: 63
2842 09:29:09.894574 [Byte1]: 63
2843 09:29:09.894625
2844 09:29:09.894677 Set Vref, RX VrefLevel [Byte0]: 64
2845 09:29:09.894728 [Byte1]: 64
2846 09:29:09.894779
2847 09:29:09.894830 Set Vref, RX VrefLevel [Byte0]: 65
2848 09:29:09.894881 [Byte1]: 65
2849 09:29:09.894934
2850 09:29:09.894985 Set Vref, RX VrefLevel [Byte0]: 66
2851 09:29:09.895036 [Byte1]: 66
2852 09:29:09.895088
2853 09:29:09.895139 Set Vref, RX VrefLevel [Byte0]: 67
2854 09:29:09.895191 [Byte1]: 67
2855 09:29:09.895242
2856 09:29:09.895293 Set Vref, RX VrefLevel [Byte0]: 68
2857 09:29:09.895345 [Byte1]: 68
2858 09:29:09.895396
2859 09:29:09.895446 Final RX Vref Byte 0 = 58 to rank0
2860 09:29:09.895498 Final RX Vref Byte 1 = 49 to rank0
2861 09:29:09.895549 Final RX Vref Byte 0 = 58 to rank1
2862 09:29:09.895601 Final RX Vref Byte 1 = 49 to rank1==
2863 09:29:09.895653 Dram Type= 6, Freq= 0, CH_0, rank 0
2864 09:29:09.895704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2865 09:29:09.895756 ==
2866 09:29:09.895807 DQS Delay:
2867 09:29:09.895858 DQS0 = 0, DQS1 = 0
2868 09:29:09.895910 DQM Delay:
2869 09:29:09.895961 DQM0 = 119, DQM1 = 105
2870 09:29:09.896013 DQ Delay:
2871 09:29:09.896064 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =116
2872 09:29:09.896115 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =122
2873 09:29:09.896166 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =100
2874 09:29:09.896218 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =114
2875 09:29:09.896268
2876 09:29:09.896319
2877 09:29:09.896370 [DQSOSCAuto] RK0, (LSB)MR18= 0x500, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2878 09:29:09.896422 CH0 RK0: MR19=404, MR18=500
2879 09:29:09.896474 CH0_RK0: MR19=0x404, MR18=0x500, DQSOSC=408, MR23=63, INC=39, DEC=26
2880 09:29:09.896526
2881 09:29:09.896577 ----->DramcWriteLeveling(PI) begin...
2882 09:29:09.896630 ==
2883 09:29:09.896681 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 09:29:09.896733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 09:29:09.896785 ==
2886 09:29:09.896836 Write leveling (Byte 0): 29 => 29
2887 09:29:09.896887 Write leveling (Byte 1): 26 => 26
2888 09:29:09.896939 DramcWriteLeveling(PI) end<-----
2889 09:29:09.896990
2890 09:29:09.897041 ==
2891 09:29:09.897093 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 09:29:09.897145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 09:29:09.897196 ==
2894 09:29:09.897247 [Gating] SW mode calibration
2895 09:29:09.897345 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2896 09:29:09.897398 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2897 09:29:09.897450 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2898 09:29:09.897502 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 09:29:09.897553 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 09:29:09.897605 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 09:29:09.897656 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 09:29:09.897707 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2903 09:29:09.897759 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2904 09:29:09.897810 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
2905 09:29:09.897876 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2906 09:29:09.897979 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 09:29:09.898065 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 09:29:09.898150 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 09:29:09.898216 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 09:29:09.898270 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 09:29:09.898323 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2912 09:29:09.898376 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2913 09:29:09.898428 1 1 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2914 09:29:09.898480 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 09:29:09.898531 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 09:29:09.898583 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 09:29:09.898635 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 09:29:09.898687 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 09:29:09.898738 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2920 09:29:09.898790 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2921 09:29:09.898842 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2922 09:29:09.898894 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 09:29:09.898946 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 09:29:09.898998 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 09:29:09.899050 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 09:29:09.899102 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 09:29:09.899154 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 09:29:09.899206 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 09:29:09.899257 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 09:29:09.899308 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 09:29:09.899359 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 09:29:09.899603 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 09:29:09.899665 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 09:29:09.899718 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 09:29:09.899771 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2936 09:29:09.899823 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2937 09:29:09.899875 Total UI for P1: 0, mck2ui 16
2938 09:29:09.899928 best dqsien dly found for B0: ( 1, 3, 24)
2939 09:29:09.899981 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 09:29:09.900033 Total UI for P1: 0, mck2ui 16
2941 09:29:09.900085 best dqsien dly found for B1: ( 1, 3, 28)
2942 09:29:09.900137 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2943 09:29:09.900189 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2944 09:29:09.900240
2945 09:29:09.900307 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2946 09:29:09.900374 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2947 09:29:09.900425 [Gating] SW calibration Done
2948 09:29:09.900477 ==
2949 09:29:09.900528 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 09:29:09.900580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 09:29:09.900632 ==
2952 09:29:09.900715 RX Vref Scan: 0
2953 09:29:09.900767
2954 09:29:09.900818 RX Vref 0 -> 0, step: 1
2955 09:29:09.900870
2956 09:29:09.900920 RX Delay -40 -> 252, step: 8
2957 09:29:09.900972 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2958 09:29:09.901024 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2959 09:29:09.901075 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2960 09:29:09.901127 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2961 09:29:09.901178 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2962 09:29:09.901230 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2963 09:29:09.901321 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2964 09:29:09.901374 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2965 09:29:09.901434 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2966 09:29:09.901509 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2967 09:29:09.901596 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2968 09:29:09.901680 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2969 09:29:09.901758 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2970 09:29:09.901812 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2971 09:29:09.901864 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2972 09:29:09.901917 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2973 09:29:09.901968 ==
2974 09:29:09.902020 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 09:29:09.902072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 09:29:09.902125 ==
2977 09:29:09.902176 DQS Delay:
2978 09:29:09.902227 DQS0 = 0, DQS1 = 0
2979 09:29:09.902278 DQM Delay:
2980 09:29:09.902330 DQM0 = 119, DQM1 = 106
2981 09:29:09.902381 DQ Delay:
2982 09:29:09.902433 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2983 09:29:09.902484 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2984 09:29:09.902536 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2985 09:29:09.902587 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2986 09:29:09.902639
2987 09:29:09.902719
2988 09:29:09.902770 ==
2989 09:29:09.902822 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 09:29:09.902873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 09:29:09.902925 ==
2992 09:29:09.902977
2993 09:29:09.903028
2994 09:29:09.903079 TX Vref Scan disable
2995 09:29:09.903131 == TX Byte 0 ==
2996 09:29:09.903182 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2997 09:29:09.903235 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2998 09:29:09.903287 == TX Byte 1 ==
2999 09:29:09.903338 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3000 09:29:09.903390 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3001 09:29:09.903442 ==
3002 09:29:10.041580 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 09:29:10.041721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 09:29:10.041787 ==
3005 09:29:10.041847 TX Vref=22, minBit 3, minWin=25, winSum=415
3006 09:29:10.041907 TX Vref=24, minBit 4, minWin=25, winSum=415
3007 09:29:10.041964 TX Vref=26, minBit 0, minWin=26, winSum=422
3008 09:29:10.042019 TX Vref=28, minBit 0, minWin=26, winSum=422
3009 09:29:10.042073 TX Vref=30, minBit 1, minWin=26, winSum=424
3010 09:29:10.042127 TX Vref=32, minBit 0, minWin=26, winSum=425
3011 09:29:10.042181 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 32
3012 09:29:10.042235
3013 09:29:10.042288 Final TX Range 1 Vref 32
3014 09:29:10.042342
3015 09:29:10.042394 ==
3016 09:29:10.042447 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 09:29:10.042500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 09:29:10.042553 ==
3019 09:29:10.042604
3020 09:29:10.042655
3021 09:29:10.042707 TX Vref Scan disable
3022 09:29:10.042759 == TX Byte 0 ==
3023 09:29:10.042811 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3024 09:29:10.042864 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3025 09:29:10.042917 == TX Byte 1 ==
3026 09:29:10.042968 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3027 09:29:10.043020 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3028 09:29:10.043072
3029 09:29:10.043124 [DATLAT]
3030 09:29:10.043175 Freq=1200, CH0 RK1
3031 09:29:10.043227
3032 09:29:10.043279 DATLAT Default: 0xd
3033 09:29:10.043331 0, 0xFFFF, sum = 0
3034 09:29:10.043385 1, 0xFFFF, sum = 0
3035 09:29:10.043437 2, 0xFFFF, sum = 0
3036 09:29:10.043490 3, 0xFFFF, sum = 0
3037 09:29:10.043542 4, 0xFFFF, sum = 0
3038 09:29:10.043595 5, 0xFFFF, sum = 0
3039 09:29:10.043647 6, 0xFFFF, sum = 0
3040 09:29:10.043699 7, 0xFFFF, sum = 0
3041 09:29:10.043752 8, 0xFFFF, sum = 0
3042 09:29:10.043805 9, 0xFFFF, sum = 0
3043 09:29:10.043857 10, 0xFFFF, sum = 0
3044 09:29:10.043910 11, 0xFFFF, sum = 0
3045 09:29:10.043962 12, 0x0, sum = 1
3046 09:29:10.044015 13, 0x0, sum = 2
3047 09:29:10.044067 14, 0x0, sum = 3
3048 09:29:10.044120 15, 0x0, sum = 4
3049 09:29:10.044172 best_step = 13
3050 09:29:10.044223
3051 09:29:10.044275 ==
3052 09:29:10.044326 Dram Type= 6, Freq= 0, CH_0, rank 1
3053 09:29:10.044377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 09:29:10.044430 ==
3055 09:29:10.044481 RX Vref Scan: 0
3056 09:29:10.044533
3057 09:29:10.044584 RX Vref 0 -> 0, step: 1
3058 09:29:10.044636
3059 09:29:10.044687 RX Delay -21 -> 252, step: 4
3060 09:29:10.044738 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3061 09:29:10.044796 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3062 09:29:10.044884 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3063 09:29:10.044969 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3064 09:29:10.045047 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3065 09:29:10.045102 iDelay=195, Bit 5, Center 112 (47 ~ 178) 132
3066 09:29:10.045155 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3067 09:29:10.045207 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
3068 09:29:10.045264 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3069 09:29:10.045360 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3070 09:29:10.045412 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3071 09:29:10.045667 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3072 09:29:10.045727 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3073 09:29:10.045781 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3074 09:29:10.045833 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3075 09:29:10.045886 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3076 09:29:10.045937 ==
3077 09:29:10.045989 Dram Type= 6, Freq= 0, CH_0, rank 1
3078 09:29:10.046041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 09:29:10.046093 ==
3080 09:29:10.046145 DQS Delay:
3081 09:29:10.046197 DQS0 = 0, DQS1 = 0
3082 09:29:10.046248 DQM Delay:
3083 09:29:10.046300 DQM0 = 118, DQM1 = 106
3084 09:29:10.046352 DQ Delay:
3085 09:29:10.046403 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3086 09:29:10.046455 DQ4 =120, DQ5 =112, DQ6 =128, DQ7 =124
3087 09:29:10.046506 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3088 09:29:10.046558 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =114
3089 09:29:10.046609
3090 09:29:10.046660
3091 09:29:10.046711 [DQSOSCAuto] RK1, (LSB)MR18= 0x1ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3092 09:29:10.046763 CH0 RK1: MR19=403, MR18=1FF
3093 09:29:10.046815 CH0_RK1: MR19=0x403, MR18=0x1FF, DQSOSC=409, MR23=63, INC=39, DEC=26
3094 09:29:10.046868 [RxdqsGatingPostProcess] freq 1200
3095 09:29:10.046920 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3096 09:29:10.046972 best DQS0 dly(2T, 0.5T) = (0, 11)
3097 09:29:10.047024 best DQS1 dly(2T, 0.5T) = (0, 12)
3098 09:29:10.047076 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3099 09:29:10.047127 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3100 09:29:10.047179 best DQS0 dly(2T, 0.5T) = (0, 11)
3101 09:29:10.047231 best DQS1 dly(2T, 0.5T) = (0, 11)
3102 09:29:10.047282 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3103 09:29:10.047334 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3104 09:29:10.047385 Pre-setting of DQS Precalculation
3105 09:29:10.047436 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3106 09:29:10.047489 ==
3107 09:29:10.047540 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 09:29:10.047591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 09:29:10.047643 ==
3110 09:29:10.047695 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3111 09:29:10.047747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3112 09:29:10.047798 [CA 0] Center 38 (8~68) winsize 61
3113 09:29:10.047850 [CA 1] Center 38 (8~68) winsize 61
3114 09:29:10.047902 [CA 2] Center 35 (5~65) winsize 61
3115 09:29:10.047953 [CA 3] Center 34 (4~64) winsize 61
3116 09:29:10.048005 [CA 4] Center 34 (4~65) winsize 62
3117 09:29:10.048056 [CA 5] Center 33 (3~64) winsize 62
3118 09:29:10.048107
3119 09:29:10.048158 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3120 09:29:10.048210
3121 09:29:10.048261 [CATrainingPosCal] consider 1 rank data
3122 09:29:10.048344 u2DelayCellTimex100 = 270/100 ps
3123 09:29:10.048416 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3124 09:29:10.048500 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3125 09:29:10.048587 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3126 09:29:10.048651 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3127 09:29:10.048705 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3128 09:29:10.048756 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3129 09:29:10.048807
3130 09:29:10.048859 CA PerBit enable=1, Macro0, CA PI delay=33
3131 09:29:10.048911
3132 09:29:10.048962 [CBTSetCACLKResult] CA Dly = 33
3133 09:29:10.049014 CS Dly: 5 (0~36)
3134 09:29:10.049066 ==
3135 09:29:10.049117 Dram Type= 6, Freq= 0, CH_1, rank 1
3136 09:29:10.049169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 09:29:10.049221 ==
3138 09:29:10.049302 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3139 09:29:10.049368 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3140 09:29:10.049420 [CA 0] Center 37 (7~68) winsize 62
3141 09:29:10.049471 [CA 1] Center 38 (8~68) winsize 61
3142 09:29:10.049523 [CA 2] Center 35 (5~65) winsize 61
3143 09:29:10.049574 [CA 3] Center 33 (3~64) winsize 62
3144 09:29:10.049626 [CA 4] Center 34 (4~64) winsize 61
3145 09:29:10.049677 [CA 5] Center 33 (3~64) winsize 62
3146 09:29:10.049728
3147 09:29:10.049779 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3148 09:29:10.049831
3149 09:29:10.049882 [CATrainingPosCal] consider 2 rank data
3150 09:29:10.049933 u2DelayCellTimex100 = 270/100 ps
3151 09:29:10.049985 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3152 09:29:10.050037 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3153 09:29:10.050089 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3154 09:29:10.050140 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 09:29:10.050192 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3156 09:29:10.050243 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3157 09:29:10.050294
3158 09:29:10.050345 CA PerBit enable=1, Macro0, CA PI delay=33
3159 09:29:10.050396
3160 09:29:10.050447 [CBTSetCACLKResult] CA Dly = 33
3161 09:29:10.050498 CS Dly: 6 (0~39)
3162 09:29:10.050550
3163 09:29:10.050601 ----->DramcWriteLeveling(PI) begin...
3164 09:29:10.050654 ==
3165 09:29:10.050706 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 09:29:10.050758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 09:29:10.050810 ==
3168 09:29:10.050861 Write leveling (Byte 0): 25 => 25
3169 09:29:10.050913 Write leveling (Byte 1): 27 => 27
3170 09:29:10.050964 DramcWriteLeveling(PI) end<-----
3171 09:29:10.051015
3172 09:29:10.051066 ==
3173 09:29:10.051118 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 09:29:10.051170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 09:29:10.051221 ==
3176 09:29:10.051272 [Gating] SW mode calibration
3177 09:29:10.051324 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3178 09:29:10.051376 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3179 09:29:10.051429 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3180 09:29:10.051480 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 09:29:10.051532 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 09:29:10.051583 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 09:29:10.051635 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 09:29:10.051686 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 09:29:10.051738 0 15 24 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
3186 09:29:10.051789 0 15 28 | B1->B0 | 2c2c 2424 | 0 0 | (0 1) (1 0)
3187 09:29:10.051840 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 09:29:10.051891 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 09:29:10.052143 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 09:29:10.052228 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 09:29:10.052311 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 09:29:10.052398 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 09:29:10.052457 1 0 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
3194 09:29:10.052511 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3195 09:29:10.052564 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 09:29:10.052616 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 09:29:10.052668 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 09:29:10.052720 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 09:29:10.052772 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 09:29:10.052824 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3201 09:29:10.052876 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3202 09:29:10.052928 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3203 09:29:10.052981 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 09:29:10.053033 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 09:29:10.053086 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 09:29:10.053138 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 09:29:10.053189 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 09:29:10.053241 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 09:29:10.053299 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 09:29:10.053352 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 09:29:10.053403 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 09:29:10.053455 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 09:29:10.053507 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 09:29:10.053560 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 09:29:10.053612 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 09:29:10.053664 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 09:29:10.053715 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3218 09:29:10.053768 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3219 09:29:10.053819 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 09:29:10.053871 Total UI for P1: 0, mck2ui 16
3221 09:29:10.053924 best dqsien dly found for B0: ( 1, 3, 26)
3222 09:29:10.053976 Total UI for P1: 0, mck2ui 16
3223 09:29:10.054028 best dqsien dly found for B1: ( 1, 3, 28)
3224 09:29:10.054081 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3225 09:29:10.054133 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3226 09:29:10.054185
3227 09:29:10.054236 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3228 09:29:10.054288 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3229 09:29:10.054340 [Gating] SW calibration Done
3230 09:29:10.054392 ==
3231 09:29:10.054444 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 09:29:10.054496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 09:29:10.054548 ==
3234 09:29:10.054600 RX Vref Scan: 0
3235 09:29:10.054652
3236 09:29:10.054703 RX Vref 0 -> 0, step: 1
3237 09:29:10.054769
3238 09:29:10.054823 RX Delay -40 -> 252, step: 8
3239 09:29:10.054876 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3240 09:29:10.054928 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3241 09:29:10.054980 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3242 09:29:10.055032 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3243 09:29:10.055084 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3244 09:29:10.055136 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3245 09:29:10.055187 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3246 09:29:10.055239 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3247 09:29:10.055290 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3248 09:29:10.055342 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3249 09:29:10.055393 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3250 09:29:10.055445 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3251 09:29:10.055496 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3252 09:29:10.055548 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3253 09:29:10.055600 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3254 09:29:10.055652 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3255 09:29:10.055703 ==
3256 09:29:10.055755 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 09:29:10.055807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 09:29:10.055860 ==
3259 09:29:10.055912 DQS Delay:
3260 09:29:10.055964 DQS0 = 0, DQS1 = 0
3261 09:29:10.056016 DQM Delay:
3262 09:29:10.056067 DQM0 = 116, DQM1 = 112
3263 09:29:10.056120 DQ Delay:
3264 09:29:10.056172 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =119
3265 09:29:10.056224 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3266 09:29:10.056276 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3267 09:29:10.056328 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3268 09:29:10.056379
3269 09:29:10.056467
3270 09:29:10.056525 ==
3271 09:29:10.056612 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 09:29:10.056697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 09:29:10.056774 ==
3274 09:29:10.056828
3275 09:29:10.056881
3276 09:29:10.056934 TX Vref Scan disable
3277 09:29:10.056987 == TX Byte 0 ==
3278 09:29:10.057038 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3279 09:29:10.057091 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3280 09:29:10.057143 == TX Byte 1 ==
3281 09:29:10.057195 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3282 09:29:10.057247 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3283 09:29:10.057360 ==
3284 09:29:10.057413 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 09:29:10.057466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 09:29:10.057519 ==
3287 09:29:10.057572 TX Vref=22, minBit 3, minWin=24, winSum=412
3288 09:29:10.057624 TX Vref=24, minBit 3, minWin=25, winSum=416
3289 09:29:10.057677 TX Vref=26, minBit 1, minWin=26, winSum=423
3290 09:29:10.057729 TX Vref=28, minBit 1, minWin=26, winSum=425
3291 09:29:10.057781 TX Vref=30, minBit 2, minWin=26, winSum=429
3292 09:29:10.057834 TX Vref=32, minBit 8, minWin=26, winSum=428
3293 09:29:10.057886 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 30
3294 09:29:10.057939
3295 09:29:10.057990 Final TX Range 1 Vref 30
3296 09:29:10.058043
3297 09:29:10.058094 ==
3298 09:29:10.058147 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 09:29:10.058198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 09:29:10.058251 ==
3301 09:29:10.058302
3302 09:29:10.058354
3303 09:29:10.058596 TX Vref Scan disable
3304 09:29:10.058655 == TX Byte 0 ==
3305 09:29:10.058708 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3306 09:29:10.058761 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3307 09:29:10.058814 == TX Byte 1 ==
3308 09:29:10.058866 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3309 09:29:10.058919 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3310 09:29:10.058971
3311 09:29:10.059023 [DATLAT]
3312 09:29:10.059075 Freq=1200, CH1 RK0
3313 09:29:10.059128
3314 09:29:10.059180 DATLAT Default: 0xd
3315 09:29:10.059231 0, 0xFFFF, sum = 0
3316 09:29:10.059285 1, 0xFFFF, sum = 0
3317 09:29:10.059338 2, 0xFFFF, sum = 0
3318 09:29:10.059390 3, 0xFFFF, sum = 0
3319 09:29:10.059443 4, 0xFFFF, sum = 0
3320 09:29:10.059496 5, 0xFFFF, sum = 0
3321 09:29:10.059549 6, 0xFFFF, sum = 0
3322 09:29:10.059602 7, 0xFFFF, sum = 0
3323 09:29:10.059655 8, 0xFFFF, sum = 0
3324 09:29:10.059708 9, 0xFFFF, sum = 0
3325 09:29:10.059761 10, 0xFFFF, sum = 0
3326 09:29:10.059813 11, 0xFFFF, sum = 0
3327 09:29:10.059866 12, 0x0, sum = 1
3328 09:29:10.059919 13, 0x0, sum = 2
3329 09:29:10.059971 14, 0x0, sum = 3
3330 09:29:10.060024 15, 0x0, sum = 4
3331 09:29:10.060076 best_step = 13
3332 09:29:10.060128
3333 09:29:10.060181 ==
3334 09:29:10.060233 Dram Type= 6, Freq= 0, CH_1, rank 0
3335 09:29:10.060285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3336 09:29:10.060338 ==
3337 09:29:10.060390 RX Vref Scan: 1
3338 09:29:10.060442
3339 09:29:10.060493 Set Vref Range= 32 -> 127
3340 09:29:10.060544
3341 09:29:10.060599 RX Vref 32 -> 127, step: 1
3342 09:29:10.060688
3343 09:29:10.060776 RX Delay -13 -> 252, step: 4
3344 09:29:10.060854
3345 09:29:10.060908 Set Vref, RX VrefLevel [Byte0]: 32
3346 09:29:10.060962 [Byte1]: 32
3347 09:29:10.061015
3348 09:29:10.061067 Set Vref, RX VrefLevel [Byte0]: 33
3349 09:29:10.061119 [Byte1]: 33
3350 09:29:10.061171
3351 09:29:10.061223 Set Vref, RX VrefLevel [Byte0]: 34
3352 09:29:10.061298 [Byte1]: 34
3353 09:29:10.061365
3354 09:29:10.061417 Set Vref, RX VrefLevel [Byte0]: 35
3355 09:29:10.061469 [Byte1]: 35
3356 09:29:10.061521
3357 09:29:10.061573 Set Vref, RX VrefLevel [Byte0]: 36
3358 09:29:10.061624 [Byte1]: 36
3359 09:29:10.061676
3360 09:29:10.061728 Set Vref, RX VrefLevel [Byte0]: 37
3361 09:29:10.061779 [Byte1]: 37
3362 09:29:10.061831
3363 09:29:10.061882 Set Vref, RX VrefLevel [Byte0]: 38
3364 09:29:10.061934 [Byte1]: 38
3365 09:29:10.061985
3366 09:29:10.062036 Set Vref, RX VrefLevel [Byte0]: 39
3367 09:29:10.062087 [Byte1]: 39
3368 09:29:10.062138
3369 09:29:10.062189 Set Vref, RX VrefLevel [Byte0]: 40
3370 09:29:10.062241 [Byte1]: 40
3371 09:29:10.062292
3372 09:29:10.062343 Set Vref, RX VrefLevel [Byte0]: 41
3373 09:29:10.062395 [Byte1]: 41
3374 09:29:10.062447
3375 09:29:10.062498 Set Vref, RX VrefLevel [Byte0]: 42
3376 09:29:10.062549 [Byte1]: 42
3377 09:29:10.062601
3378 09:29:10.062652 Set Vref, RX VrefLevel [Byte0]: 43
3379 09:29:10.062704 [Byte1]: 43
3380 09:29:10.062755
3381 09:29:10.062805 Set Vref, RX VrefLevel [Byte0]: 44
3382 09:29:10.062857 [Byte1]: 44
3383 09:29:10.062908
3384 09:29:10.062959 Set Vref, RX VrefLevel [Byte0]: 45
3385 09:29:10.063011 [Byte1]: 45
3386 09:29:10.063062
3387 09:29:10.063113 Set Vref, RX VrefLevel [Byte0]: 46
3388 09:29:10.063164 [Byte1]: 46
3389 09:29:10.063215
3390 09:29:10.063266 Set Vref, RX VrefLevel [Byte0]: 47
3391 09:29:10.063318 [Byte1]: 47
3392 09:29:10.063369
3393 09:29:10.063420 Set Vref, RX VrefLevel [Byte0]: 48
3394 09:29:10.063472 [Byte1]: 48
3395 09:29:10.063523
3396 09:29:10.063574 Set Vref, RX VrefLevel [Byte0]: 49
3397 09:29:10.063626 [Byte1]: 49
3398 09:29:10.063676
3399 09:29:10.063727 Set Vref, RX VrefLevel [Byte0]: 50
3400 09:29:10.063778 [Byte1]: 50
3401 09:29:10.063898
3402 09:29:10.063949 Set Vref, RX VrefLevel [Byte0]: 51
3403 09:29:10.064002 [Byte1]: 51
3404 09:29:10.064054
3405 09:29:10.064105 Set Vref, RX VrefLevel [Byte0]: 52
3406 09:29:10.064157 [Byte1]: 52
3407 09:29:10.064208
3408 09:29:10.064259 Set Vref, RX VrefLevel [Byte0]: 53
3409 09:29:10.064310 [Byte1]: 53
3410 09:29:10.064362
3411 09:29:10.064412 Set Vref, RX VrefLevel [Byte0]: 54
3412 09:29:10.064464 [Byte1]: 54
3413 09:29:10.064516
3414 09:29:10.064567 Set Vref, RX VrefLevel [Byte0]: 55
3415 09:29:10.064618 [Byte1]: 55
3416 09:29:10.064670
3417 09:29:10.064746 Set Vref, RX VrefLevel [Byte0]: 56
3418 09:29:10.064815 [Byte1]: 56
3419 09:29:10.064867
3420 09:29:10.064918 Set Vref, RX VrefLevel [Byte0]: 57
3421 09:29:10.064972 [Byte1]: 57
3422 09:29:10.065024
3423 09:29:10.065076 Set Vref, RX VrefLevel [Byte0]: 58
3424 09:29:10.065128 [Byte1]: 58
3425 09:29:10.065179
3426 09:29:10.065231 Set Vref, RX VrefLevel [Byte0]: 59
3427 09:29:10.065312 [Byte1]: 59
3428 09:29:10.065378
3429 09:29:10.065429 Set Vref, RX VrefLevel [Byte0]: 60
3430 09:29:10.065481 [Byte1]: 60
3431 09:29:10.065533
3432 09:29:10.065585 Set Vref, RX VrefLevel [Byte0]: 61
3433 09:29:10.065637 [Byte1]: 61
3434 09:29:10.065689
3435 09:29:10.065740 Set Vref, RX VrefLevel [Byte0]: 62
3436 09:29:10.065792 [Byte1]: 62
3437 09:29:10.065844
3438 09:29:10.065895 Set Vref, RX VrefLevel [Byte0]: 63
3439 09:29:10.065946 [Byte1]: 63
3440 09:29:10.065998
3441 09:29:10.066049 Set Vref, RX VrefLevel [Byte0]: 64
3442 09:29:10.066101 [Byte1]: 64
3443 09:29:10.066152
3444 09:29:10.066203 Set Vref, RX VrefLevel [Byte0]: 65
3445 09:29:10.066256 [Byte1]: 65
3446 09:29:10.066308
3447 09:29:10.066359 Final RX Vref Byte 0 = 50 to rank0
3448 09:29:10.066410 Final RX Vref Byte 1 = 53 to rank0
3449 09:29:10.066462 Final RX Vref Byte 0 = 50 to rank1
3450 09:29:10.066514 Final RX Vref Byte 1 = 53 to rank1==
3451 09:29:10.066565 Dram Type= 6, Freq= 0, CH_1, rank 0
3452 09:29:10.066617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3453 09:29:10.066669 ==
3454 09:29:10.066720 DQS Delay:
3455 09:29:10.066771 DQS0 = 0, DQS1 = 0
3456 09:29:10.066823 DQM Delay:
3457 09:29:10.066874 DQM0 = 114, DQM1 = 113
3458 09:29:10.066926 DQ Delay:
3459 09:29:10.066977 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3460 09:29:10.067028 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3461 09:29:10.067079 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =108
3462 09:29:10.067131 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3463 09:29:10.067182
3464 09:29:10.067233
3465 09:29:10.067284 [DQSOSCAuto] RK0, (LSB)MR18= 0xf703, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3466 09:29:10.067336 CH1 RK0: MR19=304, MR18=F703
3467 09:29:10.067580 CH1_RK0: MR19=0x304, MR18=0xF703, DQSOSC=408, MR23=63, INC=39, DEC=26
3468 09:29:10.067638
3469 09:29:10.067691 ----->DramcWriteLeveling(PI) begin...
3470 09:29:10.067745 ==
3471 09:29:10.067797 Dram Type= 6, Freq= 0, CH_1, rank 1
3472 09:29:10.067850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3473 09:29:10.067902 ==
3474 09:29:10.067954 Write leveling (Byte 0): 25 => 25
3475 09:29:10.068006 Write leveling (Byte 1): 28 => 28
3476 09:29:10.068058 DramcWriteLeveling(PI) end<-----
3477 09:29:10.068109
3478 09:29:10.068161 ==
3479 09:29:10.068212 Dram Type= 6, Freq= 0, CH_1, rank 1
3480 09:29:10.068310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3481 09:29:10.068408 ==
3482 09:29:10.068460 [Gating] SW mode calibration
3483 09:29:10.068512 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3484 09:29:10.068564 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3485 09:29:10.068617 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3486 09:29:10.068669 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 09:29:10.068741 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 09:29:10.068808 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 09:29:10.068860 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 09:29:10.068911 0 15 20 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
3491 09:29:10.068963 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
3492 09:29:10.069014 0 15 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
3493 09:29:10.069065 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 09:29:10.069117 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 09:29:10.069169 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 09:29:10.069220 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 09:29:10.069313 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 09:29:10.069366 1 0 20 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
3499 09:29:10.069417 1 0 24 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
3500 09:29:10.069469 1 0 28 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
3501 09:29:10.069520 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 09:29:10.069572 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 09:29:10.069624 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 09:29:10.069675 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 09:29:10.069727 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 09:29:10.069779 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3507 09:29:10.069830 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3508 09:29:10.069881 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3509 09:29:10.069933 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 09:29:10.069984 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 09:29:10.070035 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 09:29:10.070087 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 09:29:10.070138 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 09:29:10.070190 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 09:29:10.070241 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 09:29:10.070292 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 09:29:10.070343 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 09:29:10.070395 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 09:29:10.070447 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 09:29:10.070499 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 09:29:10.070550 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 09:29:10.070602 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3523 09:29:10.070654 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3524 09:29:10.070709 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3525 09:29:10.070833 Total UI for P1: 0, mck2ui 16
3526 09:29:10.070888 best dqsien dly found for B0: ( 1, 3, 22)
3527 09:29:10.070940 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 09:29:10.070992 Total UI for P1: 0, mck2ui 16
3529 09:29:10.071045 best dqsien dly found for B1: ( 1, 3, 28)
3530 09:29:10.071097 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3531 09:29:10.071149 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3532 09:29:10.071201
3533 09:29:10.071252 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3534 09:29:10.071304 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3535 09:29:10.071356 [Gating] SW calibration Done
3536 09:29:10.071408 ==
3537 09:29:10.071460 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 09:29:10.071512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 09:29:10.071564 ==
3540 09:29:10.071616 RX Vref Scan: 0
3541 09:29:10.071667
3542 09:29:10.071719 RX Vref 0 -> 0, step: 1
3543 09:29:10.071771
3544 09:29:10.071822 RX Delay -40 -> 252, step: 8
3545 09:29:10.071875 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3546 09:29:10.071927 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3547 09:29:10.071978 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3548 09:29:10.072030 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3549 09:29:10.072081 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3550 09:29:10.072132 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3551 09:29:10.072184 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3552 09:29:10.072235 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3553 09:29:10.072287 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3554 09:29:10.072338 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3555 09:29:10.072390 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3556 09:29:10.072442 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3557 09:29:10.072493 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3558 09:29:10.072544 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3559 09:29:10.072595 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3560 09:29:10.072646 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3561 09:29:10.072697 ==
3562 09:29:10.072771 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 09:29:10.072859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 09:29:10.072915 ==
3565 09:29:10.072968 DQS Delay:
3566 09:29:10.073021 DQS0 = 0, DQS1 = 0
3567 09:29:10.073073 DQM Delay:
3568 09:29:10.073124 DQM0 = 114, DQM1 = 111
3569 09:29:10.073176 DQ Delay:
3570 09:29:10.073227 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3571 09:29:10.073535 DQ4 =119, DQ5 =123, DQ6 =119, DQ7 =111
3572 09:29:10.073635 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3573 09:29:10.073688 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3574 09:29:10.073741
3575 09:29:10.073792
3576 09:29:10.073843 ==
3577 09:29:10.073894 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 09:29:10.073946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 09:29:10.073998 ==
3580 09:29:10.074049
3581 09:29:10.074100
3582 09:29:10.074151 TX Vref Scan disable
3583 09:29:10.074203 == TX Byte 0 ==
3584 09:29:10.074255 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3585 09:29:10.074307 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3586 09:29:10.074359 == TX Byte 1 ==
3587 09:29:10.074411 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3588 09:29:10.074463 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3589 09:29:10.074514 ==
3590 09:29:10.074566 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 09:29:10.074618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 09:29:10.074670 ==
3593 09:29:10.074721 TX Vref=22, minBit 1, minWin=26, winSum=424
3594 09:29:10.074774 TX Vref=24, minBit 1, minWin=26, winSum=424
3595 09:29:10.074826 TX Vref=26, minBit 1, minWin=26, winSum=428
3596 09:29:10.074879 TX Vref=28, minBit 3, minWin=26, winSum=434
3597 09:29:10.074931 TX Vref=30, minBit 1, minWin=26, winSum=433
3598 09:29:10.074984 TX Vref=32, minBit 8, minWin=26, winSum=434
3599 09:29:10.075035 [TxChooseVref] Worse bit 3, Min win 26, Win sum 434, Final Vref 28
3600 09:29:10.075088
3601 09:29:10.075139 Final TX Range 1 Vref 28
3602 09:29:10.075191
3603 09:29:10.075242 ==
3604 09:29:10.075293 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 09:29:10.075345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 09:29:10.075397 ==
3607 09:29:10.075448
3608 09:29:10.075499
3609 09:29:10.075550 TX Vref Scan disable
3610 09:29:10.075602 == TX Byte 0 ==
3611 09:29:10.075654 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3612 09:29:10.075706 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3613 09:29:10.075758 == TX Byte 1 ==
3614 09:29:10.075809 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3615 09:29:10.075860 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3616 09:29:10.075911
3617 09:29:10.075962 [DATLAT]
3618 09:29:10.076013 Freq=1200, CH1 RK1
3619 09:29:10.076065
3620 09:29:10.076117 DATLAT Default: 0xd
3621 09:29:10.076168 0, 0xFFFF, sum = 0
3622 09:29:10.076222 1, 0xFFFF, sum = 0
3623 09:29:10.076275 2, 0xFFFF, sum = 0
3624 09:29:10.076328 3, 0xFFFF, sum = 0
3625 09:29:10.076380 4, 0xFFFF, sum = 0
3626 09:29:10.076433 5, 0xFFFF, sum = 0
3627 09:29:10.076486 6, 0xFFFF, sum = 0
3628 09:29:10.076538 7, 0xFFFF, sum = 0
3629 09:29:10.076590 8, 0xFFFF, sum = 0
3630 09:29:10.076642 9, 0xFFFF, sum = 0
3631 09:29:10.076694 10, 0xFFFF, sum = 0
3632 09:29:10.076767 11, 0xFFFF, sum = 0
3633 09:29:10.076843 12, 0x0, sum = 1
3634 09:29:10.076922 13, 0x0, sum = 2
3635 09:29:10.076978 14, 0x0, sum = 3
3636 09:29:10.077030 15, 0x0, sum = 4
3637 09:29:10.077083 best_step = 13
3638 09:29:10.077135
3639 09:29:10.077207 ==
3640 09:29:10.077315 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 09:29:10.077369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 09:29:10.077421 ==
3643 09:29:10.077473 RX Vref Scan: 0
3644 09:29:10.077525
3645 09:29:10.077576 RX Vref 0 -> 0, step: 1
3646 09:29:10.077627
3647 09:29:10.077678 RX Delay -13 -> 252, step: 4
3648 09:29:10.077730 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3649 09:29:10.077782 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3650 09:29:10.077834 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3651 09:29:10.077886 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3652 09:29:10.077937 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3653 09:29:10.077989 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3654 09:29:10.078041 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3655 09:29:10.078093 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3656 09:29:10.078144 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3657 09:29:10.078197 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3658 09:29:10.078248 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3659 09:29:10.078300 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3660 09:29:10.078351 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3661 09:29:10.078403 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3662 09:29:10.078454 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3663 09:29:10.078507 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3664 09:29:10.078559 ==
3665 09:29:10.078610 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 09:29:10.078663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 09:29:10.078715 ==
3668 09:29:10.078766 DQS Delay:
3669 09:29:10.078817 DQS0 = 0, DQS1 = 0
3670 09:29:10.078869 DQM Delay:
3671 09:29:10.078921 DQM0 = 114, DQM1 = 112
3672 09:29:10.078972 DQ Delay:
3673 09:29:10.079024 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3674 09:29:10.079077 DQ4 =112, DQ5 =122, DQ6 =122, DQ7 =112
3675 09:29:10.079128 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3676 09:29:10.079180 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3677 09:29:10.079231
3678 09:29:10.079282
3679 09:29:10.079334 [DQSOSCAuto] RK1, (LSB)MR18= 0xf90b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3680 09:29:10.079387 CH1 RK1: MR19=304, MR18=F90B
3681 09:29:10.079439 CH1_RK1: MR19=0x304, MR18=0xF90B, DQSOSC=405, MR23=63, INC=39, DEC=26
3682 09:29:10.079491 [RxdqsGatingPostProcess] freq 1200
3683 09:29:10.079544 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3684 09:29:10.079596 best DQS0 dly(2T, 0.5T) = (0, 11)
3685 09:29:10.079647 best DQS1 dly(2T, 0.5T) = (0, 11)
3686 09:29:10.079699 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3687 09:29:10.079750 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3688 09:29:10.079801 best DQS0 dly(2T, 0.5T) = (0, 11)
3689 09:29:10.079853 best DQS1 dly(2T, 0.5T) = (0, 11)
3690 09:29:10.079904 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3691 09:29:10.079955 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3692 09:29:10.080006 Pre-setting of DQS Precalculation
3693 09:29:10.080057 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3694 09:29:10.080109 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3695 09:29:10.080162 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3696 09:29:10.080214
3697 09:29:10.080265
3698 09:29:10.080316 [Calibration Summary] 2400 Mbps
3699 09:29:10.080368 CH 0, Rank 0
3700 09:29:10.080420 SW Impedance : PASS
3701 09:29:10.080472 DUTY Scan : NO K
3702 09:29:10.080523 ZQ Calibration : PASS
3703 09:29:10.080575 Jitter Meter : NO K
3704 09:29:10.080627 CBT Training : PASS
3705 09:29:10.080678 Write leveling : PASS
3706 09:29:10.080729 RX DQS gating : PASS
3707 09:29:10.080780 RX DQ/DQS(RDDQC) : PASS
3708 09:29:10.080832 TX DQ/DQS : PASS
3709 09:29:10.080884 RX DATLAT : PASS
3710 09:29:10.081128 RX DQ/DQS(Engine): PASS
3711 09:29:10.081187 TX OE : NO K
3712 09:29:10.081240 All Pass.
3713 09:29:10.081335
3714 09:29:10.081388 CH 0, Rank 1
3715 09:29:10.081439 SW Impedance : PASS
3716 09:29:10.081492 DUTY Scan : NO K
3717 09:29:10.081543 ZQ Calibration : PASS
3718 09:29:10.081595 Jitter Meter : NO K
3719 09:29:10.081648 CBT Training : PASS
3720 09:29:10.081699 Write leveling : PASS
3721 09:29:10.081750 RX DQS gating : PASS
3722 09:29:10.081802 RX DQ/DQS(RDDQC) : PASS
3723 09:29:10.081854 TX DQ/DQS : PASS
3724 09:29:10.081906 RX DATLAT : PASS
3725 09:29:10.081957 RX DQ/DQS(Engine): PASS
3726 09:29:10.082009 TX OE : NO K
3727 09:29:10.082061 All Pass.
3728 09:29:10.082113
3729 09:29:10.082164 CH 1, Rank 0
3730 09:29:10.082216 SW Impedance : PASS
3731 09:29:10.082268 DUTY Scan : NO K
3732 09:29:10.082320 ZQ Calibration : PASS
3733 09:29:10.082371 Jitter Meter : NO K
3734 09:29:10.082423 CBT Training : PASS
3735 09:29:10.082475 Write leveling : PASS
3736 09:29:10.082526 RX DQS gating : PASS
3737 09:29:10.082578 RX DQ/DQS(RDDQC) : PASS
3738 09:29:10.082629 TX DQ/DQS : PASS
3739 09:29:10.082681 RX DATLAT : PASS
3740 09:29:10.082732 RX DQ/DQS(Engine): PASS
3741 09:29:10.082783 TX OE : NO K
3742 09:29:10.082835 All Pass.
3743 09:29:10.082886
3744 09:29:10.082938 CH 1, Rank 1
3745 09:29:10.082989 SW Impedance : PASS
3746 09:29:10.083041 DUTY Scan : NO K
3747 09:29:10.083093 ZQ Calibration : PASS
3748 09:29:10.083144 Jitter Meter : NO K
3749 09:29:10.083195 CBT Training : PASS
3750 09:29:10.083246 Write leveling : PASS
3751 09:29:10.083297 RX DQS gating : PASS
3752 09:29:10.083349 RX DQ/DQS(RDDQC) : PASS
3753 09:29:10.083400 TX DQ/DQS : PASS
3754 09:29:10.083451 RX DATLAT : PASS
3755 09:29:10.083503 RX DQ/DQS(Engine): PASS
3756 09:29:10.083554 TX OE : NO K
3757 09:29:10.083606 All Pass.
3758 09:29:10.083657
3759 09:29:10.083708 DramC Write-DBI off
3760 09:29:10.083759 PER_BANK_REFRESH: Hybrid Mode
3761 09:29:10.083811 TX_TRACKING: ON
3762 09:29:10.083864 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3763 09:29:10.083917 [FAST_K] Save calibration result to emmc
3764 09:29:10.083969 dramc_set_vcore_voltage set vcore to 650000
3765 09:29:10.084020 Read voltage for 600, 5
3766 09:29:10.084072 Vio18 = 0
3767 09:29:10.084123 Vcore = 650000
3768 09:29:10.084174 Vdram = 0
3769 09:29:10.084224 Vddq = 0
3770 09:29:10.084275 Vmddr = 0
3771 09:29:10.084326 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3772 09:29:10.084378 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3773 09:29:10.084430 MEM_TYPE=3, freq_sel=19
3774 09:29:10.084482 sv_algorithm_assistance_LP4_1600
3775 09:29:10.084534 ============ PULL DRAM RESETB DOWN ============
3776 09:29:10.084586 ========== PULL DRAM RESETB DOWN end =========
3777 09:29:10.084638 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3778 09:29:10.084691 ===================================
3779 09:29:10.084743 LPDDR4 DRAM CONFIGURATION
3780 09:29:10.084794 ===================================
3781 09:29:10.084846 EX_ROW_EN[0] = 0x0
3782 09:29:10.084898 EX_ROW_EN[1] = 0x0
3783 09:29:10.084949 LP4Y_EN = 0x0
3784 09:29:10.085001 WORK_FSP = 0x0
3785 09:29:10.085052 WL = 0x2
3786 09:29:10.085104 RL = 0x2
3787 09:29:10.085155 BL = 0x2
3788 09:29:10.085206 RPST = 0x0
3789 09:29:10.085282 RD_PRE = 0x0
3790 09:29:10.085350 WR_PRE = 0x1
3791 09:29:10.085401 WR_PST = 0x0
3792 09:29:10.085453 DBI_WR = 0x0
3793 09:29:10.085504 DBI_RD = 0x0
3794 09:29:10.085555 OTF = 0x1
3795 09:29:10.085607 ===================================
3796 09:29:10.085660 ===================================
3797 09:29:10.085711 ANA top config
3798 09:29:10.085763 ===================================
3799 09:29:10.085814 DLL_ASYNC_EN = 0
3800 09:29:10.085866 ALL_SLAVE_EN = 1
3801 09:29:10.085917 NEW_RANK_MODE = 1
3802 09:29:10.085971 DLL_IDLE_MODE = 1
3803 09:29:10.086023 LP45_APHY_COMB_EN = 1
3804 09:29:10.086074 TX_ODT_DIS = 1
3805 09:29:10.086126 NEW_8X_MODE = 1
3806 09:29:10.086178 ===================================
3807 09:29:10.086230 ===================================
3808 09:29:10.086282 data_rate = 1200
3809 09:29:10.086333 CKR = 1
3810 09:29:10.086385 DQ_P2S_RATIO = 8
3811 09:29:10.086436 ===================================
3812 09:29:10.086488 CA_P2S_RATIO = 8
3813 09:29:10.086540 DQ_CA_OPEN = 0
3814 09:29:10.086591 DQ_SEMI_OPEN = 0
3815 09:29:10.086642 CA_SEMI_OPEN = 0
3816 09:29:10.086694 CA_FULL_RATE = 0
3817 09:29:10.086771 DQ_CKDIV4_EN = 1
3818 09:29:10.086855 CA_CKDIV4_EN = 1
3819 09:29:10.086921 CA_PREDIV_EN = 0
3820 09:29:10.086973 PH8_DLY = 0
3821 09:29:10.087024 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3822 09:29:10.087075 DQ_AAMCK_DIV = 4
3823 09:29:10.087126 CA_AAMCK_DIV = 4
3824 09:29:10.087178 CA_ADMCK_DIV = 4
3825 09:29:10.087229 DQ_TRACK_CA_EN = 0
3826 09:29:10.087281 CA_PICK = 600
3827 09:29:10.087332 CA_MCKIO = 600
3828 09:29:10.087383 MCKIO_SEMI = 0
3829 09:29:10.087434 PLL_FREQ = 2288
3830 09:29:10.087486 DQ_UI_PI_RATIO = 32
3831 09:29:10.087538 CA_UI_PI_RATIO = 0
3832 09:29:10.087590 ===================================
3833 09:29:10.087642 ===================================
3834 09:29:10.087694 memory_type:LPDDR4
3835 09:29:10.087746 GP_NUM : 10
3836 09:29:10.087797 SRAM_EN : 1
3837 09:29:10.087849 MD32_EN : 0
3838 09:29:10.087900 ===================================
3839 09:29:10.087952 [ANA_INIT] >>>>>>>>>>>>>>
3840 09:29:10.088003 <<<<<< [CONFIGURE PHASE]: ANA_TX
3841 09:29:10.088056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3842 09:29:10.088108 ===================================
3843 09:29:10.088161 data_rate = 1200,PCW = 0X5800
3844 09:29:10.088212 ===================================
3845 09:29:10.088264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3846 09:29:10.088316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3847 09:29:10.088368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3848 09:29:10.088420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3849 09:29:10.088472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3850 09:29:10.088524 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3851 09:29:10.088576 [ANA_INIT] flow start
3852 09:29:10.088627 [ANA_INIT] PLL >>>>>>>>
3853 09:29:10.088679 [ANA_INIT] PLL <<<<<<<<
3854 09:29:10.088926 [ANA_INIT] MIDPI >>>>>>>>
3855 09:29:10.089005 [ANA_INIT] MIDPI <<<<<<<<
3856 09:29:10.089060 [ANA_INIT] DLL >>>>>>>>
3857 09:29:10.089130 [ANA_INIT] flow end
3858 09:29:10.089184 ============ LP4 DIFF to SE enter ============
3859 09:29:10.089238 ============ LP4 DIFF to SE exit ============
3860 09:29:10.089322 [ANA_INIT] <<<<<<<<<<<<<
3861 09:29:10.089376 [Flow] Enable top DCM control >>>>>
3862 09:29:10.089428 [Flow] Enable top DCM control <<<<<
3863 09:29:10.089480 Enable DLL master slave shuffle
3864 09:29:10.089533 ==============================================================
3865 09:29:10.089608 Gating Mode config
3866 09:29:10.093566 ==============================================================
3867 09:29:10.093678 Config description:
3868 09:29:10.103464 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3869 09:29:10.110092 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3870 09:29:10.116705 SELPH_MODE 0: By rank 1: By Phase
3871 09:29:10.123607 ==============================================================
3872 09:29:10.123689 GAT_TRACK_EN = 1
3873 09:29:10.126622 RX_GATING_MODE = 2
3874 09:29:10.130405 RX_GATING_TRACK_MODE = 2
3875 09:29:10.133529 SELPH_MODE = 1
3876 09:29:10.136529 PICG_EARLY_EN = 1
3877 09:29:10.139638 VALID_LAT_VALUE = 1
3878 09:29:10.146458 ==============================================================
3879 09:29:10.149665 Enter into Gating configuration >>>>
3880 09:29:10.152794 Exit from Gating configuration <<<<
3881 09:29:10.156464 Enter into DVFS_PRE_config >>>>>
3882 09:29:10.166278 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3883 09:29:10.169397 Exit from DVFS_PRE_config <<<<<
3884 09:29:10.172833 Enter into PICG configuration >>>>
3885 09:29:10.176162 Exit from PICG configuration <<<<
3886 09:29:10.179113 [RX_INPUT] configuration >>>>>
3887 09:29:10.182376 [RX_INPUT] configuration <<<<<
3888 09:29:10.186209 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3889 09:29:10.192873 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3890 09:29:10.199225 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3891 09:29:10.205816 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3892 09:29:10.208848 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3893 09:29:10.215699 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3894 09:29:10.218810 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3895 09:29:10.225472 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3896 09:29:10.228900 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3897 09:29:10.231914 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3898 09:29:10.235564 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3899 09:29:10.241826 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3900 09:29:10.245536 ===================================
3901 09:29:10.248652 LPDDR4 DRAM CONFIGURATION
3902 09:29:10.251732 ===================================
3903 09:29:10.251813 EX_ROW_EN[0] = 0x0
3904 09:29:10.254872 EX_ROW_EN[1] = 0x0
3905 09:29:10.254953 LP4Y_EN = 0x0
3906 09:29:10.258383 WORK_FSP = 0x0
3907 09:29:10.258464 WL = 0x2
3908 09:29:10.261489 RL = 0x2
3909 09:29:10.261613 BL = 0x2
3910 09:29:10.264962 RPST = 0x0
3911 09:29:10.268123 RD_PRE = 0x0
3912 09:29:10.268203 WR_PRE = 0x1
3913 09:29:10.271198 WR_PST = 0x0
3914 09:29:10.271312 DBI_WR = 0x0
3915 09:29:10.274733 DBI_RD = 0x0
3916 09:29:10.274814 OTF = 0x1
3917 09:29:10.277788 ===================================
3918 09:29:10.281198 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3919 09:29:10.288008 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3920 09:29:10.291402 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3921 09:29:10.294468 ===================================
3922 09:29:10.298020 LPDDR4 DRAM CONFIGURATION
3923 09:29:10.301471 ===================================
3924 09:29:10.301586 EX_ROW_EN[0] = 0x10
3925 09:29:10.304591 EX_ROW_EN[1] = 0x0
3926 09:29:10.304693 LP4Y_EN = 0x0
3927 09:29:10.307507 WORK_FSP = 0x0
3928 09:29:10.307614 WL = 0x2
3929 09:29:10.310931 RL = 0x2
3930 09:29:10.314333 BL = 0x2
3931 09:29:10.314439 RPST = 0x0
3932 09:29:10.317548 RD_PRE = 0x0
3933 09:29:10.317649 WR_PRE = 0x1
3934 09:29:10.320748 WR_PST = 0x0
3935 09:29:10.320858 DBI_WR = 0x0
3936 09:29:10.324279 DBI_RD = 0x0
3937 09:29:10.324382 OTF = 0x1
3938 09:29:10.327325 ===================================
3939 09:29:10.333980 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3940 09:29:10.337929 nWR fixed to 30
3941 09:29:10.341396 [ModeRegInit_LP4] CH0 RK0
3942 09:29:10.341519 [ModeRegInit_LP4] CH0 RK1
3943 09:29:10.344682 [ModeRegInit_LP4] CH1 RK0
3944 09:29:10.347556 [ModeRegInit_LP4] CH1 RK1
3945 09:29:10.347667 match AC timing 17
3946 09:29:10.354423 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3947 09:29:10.357661 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3948 09:29:10.360708 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3949 09:29:10.367398 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3950 09:29:10.370505 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3951 09:29:10.370613 ==
3952 09:29:10.373712 Dram Type= 6, Freq= 0, CH_0, rank 0
3953 09:29:10.377436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3954 09:29:10.380500 ==
3955 09:29:10.383958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3956 09:29:10.390476 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3957 09:29:10.393836 [CA 0] Center 36 (6~67) winsize 62
3958 09:29:10.396904 [CA 1] Center 36 (6~66) winsize 61
3959 09:29:10.400371 [CA 2] Center 34 (4~65) winsize 62
3960 09:29:10.403675 [CA 3] Center 34 (3~65) winsize 63
3961 09:29:10.407446 [CA 4] Center 33 (3~64) winsize 62
3962 09:29:10.410414 [CA 5] Center 33 (3~64) winsize 62
3963 09:29:10.410505
3964 09:29:10.414024 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3965 09:29:10.414108
3966 09:29:10.417230 [CATrainingPosCal] consider 1 rank data
3967 09:29:10.420513 u2DelayCellTimex100 = 270/100 ps
3968 09:29:10.423800 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3969 09:29:10.427036 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3970 09:29:10.430119 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3971 09:29:10.436770 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3972 09:29:10.440214 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 09:29:10.443317 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3974 09:29:10.443466
3975 09:29:10.446523 CA PerBit enable=1, Macro0, CA PI delay=33
3976 09:29:10.446604
3977 09:29:10.449959 [CBTSetCACLKResult] CA Dly = 33
3978 09:29:10.450040 CS Dly: 5 (0~36)
3979 09:29:10.450104 ==
3980 09:29:10.453389 Dram Type= 6, Freq= 0, CH_0, rank 1
3981 09:29:10.459908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 09:29:10.460009 ==
3983 09:29:10.462873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3984 09:29:10.469861 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3985 09:29:10.473518 [CA 0] Center 36 (6~67) winsize 62
3986 09:29:10.476494 [CA 1] Center 36 (6~67) winsize 62
3987 09:29:10.480112 [CA 2] Center 34 (4~65) winsize 62
3988 09:29:10.483274 [CA 3] Center 34 (3~65) winsize 63
3989 09:29:10.486317 [CA 4] Center 34 (3~65) winsize 63
3990 09:29:10.489833 [CA 5] Center 33 (3~64) winsize 62
3991 09:29:10.489915
3992 09:29:10.493278 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3993 09:29:10.493392
3994 09:29:10.496338 [CATrainingPosCal] consider 2 rank data
3995 09:29:10.499555 u2DelayCellTimex100 = 270/100 ps
3996 09:29:10.502943 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3997 09:29:10.509490 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3998 09:29:10.512483 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3999 09:29:10.516116 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4000 09:29:10.519296 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 09:29:10.522278 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4002 09:29:10.522361
4003 09:29:10.525755 CA PerBit enable=1, Macro0, CA PI delay=33
4004 09:29:10.525842
4005 09:29:10.529424 [CBTSetCACLKResult] CA Dly = 33
4006 09:29:10.532567 CS Dly: 5 (0~37)
4007 09:29:10.532648
4008 09:29:10.535762 ----->DramcWriteLeveling(PI) begin...
4009 09:29:10.535845 ==
4010 09:29:10.539079 Dram Type= 6, Freq= 0, CH_0, rank 0
4011 09:29:10.542462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 09:29:10.542544 ==
4013 09:29:10.546065 Write leveling (Byte 0): 33 => 33
4014 09:29:10.549011 Write leveling (Byte 1): 27 => 27
4015 09:29:10.552087 DramcWriteLeveling(PI) end<-----
4016 09:29:10.552169
4017 09:29:10.552262 ==
4018 09:29:10.555270 Dram Type= 6, Freq= 0, CH_0, rank 0
4019 09:29:10.558972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4020 09:29:10.559054 ==
4021 09:29:10.562033 [Gating] SW mode calibration
4022 09:29:10.568889 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4023 09:29:10.575580 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4024 09:29:10.578756 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 09:29:10.582398 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 09:29:10.588437 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4027 09:29:10.592140 0 9 12 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
4028 09:29:10.595180 0 9 16 | B1->B0 | 2c2c 2424 | 0 0 | (1 1) (0 0)
4029 09:29:10.601853 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 09:29:10.605531 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 09:29:10.608423 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 09:29:10.615267 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 09:29:10.618437 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 09:29:10.622054 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 09:29:10.628226 0 10 12 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (1 1)
4036 09:29:10.631260 0 10 16 | B1->B0 | 3a3a 3d3d | 0 0 | (0 0) (0 0)
4037 09:29:10.634936 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 09:29:10.641295 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 09:29:10.644816 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 09:29:10.648076 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 09:29:10.654436 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 09:29:10.657865 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 09:29:10.661395 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4044 09:29:10.667486 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 09:29:10.671215 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 09:29:10.674251 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 09:29:10.680601 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 09:29:10.683989 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 09:29:10.687135 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 09:29:10.694051 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 09:29:10.697073 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 09:29:10.700674 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 09:29:10.707333 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 09:29:10.710454 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 09:29:10.713502 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 09:29:10.720452 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 09:29:10.723711 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 09:29:10.726781 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 09:29:10.733551 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4060 09:29:10.737202 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4061 09:29:10.740435 Total UI for P1: 0, mck2ui 16
4062 09:29:10.743285 best dqsien dly found for B0: ( 0, 13, 12)
4063 09:29:10.746752 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 09:29:10.749755 Total UI for P1: 0, mck2ui 16
4065 09:29:10.753472 best dqsien dly found for B1: ( 0, 13, 16)
4066 09:29:10.756842 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4067 09:29:10.763027 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4068 09:29:10.763109
4069 09:29:10.766457 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4070 09:29:10.770156 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4071 09:29:10.773560 [Gating] SW calibration Done
4072 09:29:10.773668 ==
4073 09:29:10.776687 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 09:29:10.779934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 09:29:10.780016 ==
4076 09:29:10.782980 RX Vref Scan: 0
4077 09:29:10.783061
4078 09:29:10.783164 RX Vref 0 -> 0, step: 1
4079 09:29:10.783249
4080 09:29:10.786106 RX Delay -230 -> 252, step: 16
4081 09:29:10.789673 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4082 09:29:10.796370 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4083 09:29:10.799293 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4084 09:29:10.802915 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4085 09:29:10.805849 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4086 09:29:10.812631 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4087 09:29:10.815666 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4088 09:29:10.819479 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4089 09:29:10.822578 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4090 09:29:10.829124 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4091 09:29:10.832464 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4092 09:29:10.836119 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4093 09:29:10.838997 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4094 09:29:10.845683 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4095 09:29:10.849232 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4096 09:29:10.852316 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4097 09:29:10.852397 ==
4098 09:29:10.855579 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 09:29:10.859081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 09:29:10.859163 ==
4101 09:29:10.862301 DQS Delay:
4102 09:29:10.862382 DQS0 = 0, DQS1 = 0
4103 09:29:10.865413 DQM Delay:
4104 09:29:10.865493 DQM0 = 45, DQM1 = 35
4105 09:29:10.865557 DQ Delay:
4106 09:29:10.868951 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4107 09:29:10.871897 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4108 09:29:10.875363 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4109 09:29:10.878641 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4110 09:29:10.878731
4111 09:29:10.881803
4112 09:29:10.881884 ==
4113 09:29:10.885112 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 09:29:10.888307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 09:29:10.888389 ==
4116 09:29:10.888453
4117 09:29:10.888511
4118 09:29:10.891942 TX Vref Scan disable
4119 09:29:10.892023 == TX Byte 0 ==
4120 09:29:10.898676 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4121 09:29:10.901672 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4122 09:29:10.901754 == TX Byte 1 ==
4123 09:29:10.907973 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4124 09:29:10.911295 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4125 09:29:10.911398 ==
4126 09:29:10.914509 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 09:29:10.918039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 09:29:10.918121 ==
4129 09:29:10.918185
4130 09:29:10.918244
4131 09:29:10.921100 TX Vref Scan disable
4132 09:29:10.924903 == TX Byte 0 ==
4133 09:29:10.927957 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4134 09:29:10.934762 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4135 09:29:10.934853 == TX Byte 1 ==
4136 09:29:10.938312 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4137 09:29:10.944625 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4138 09:29:10.944707
4139 09:29:10.944770 [DATLAT]
4140 09:29:10.944829 Freq=600, CH0 RK0
4141 09:29:10.944886
4142 09:29:10.947730 DATLAT Default: 0x9
4143 09:29:10.947812 0, 0xFFFF, sum = 0
4144 09:29:10.951246 1, 0xFFFF, sum = 0
4145 09:29:10.954780 2, 0xFFFF, sum = 0
4146 09:29:10.954886 3, 0xFFFF, sum = 0
4147 09:29:10.957912 4, 0xFFFF, sum = 0
4148 09:29:10.957996 5, 0xFFFF, sum = 0
4149 09:29:10.960879 6, 0xFFFF, sum = 0
4150 09:29:10.960961 7, 0xFFFF, sum = 0
4151 09:29:10.964088 8, 0x0, sum = 1
4152 09:29:10.964171 9, 0x0, sum = 2
4153 09:29:10.967793 10, 0x0, sum = 3
4154 09:29:10.967875 11, 0x0, sum = 4
4155 09:29:10.967941 best_step = 9
4156 09:29:10.968000
4157 09:29:10.970919 ==
4158 09:29:10.974402 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 09:29:10.977254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 09:29:10.977359 ==
4161 09:29:10.977423 RX Vref Scan: 1
4162 09:29:10.977482
4163 09:29:10.981013 RX Vref 0 -> 0, step: 1
4164 09:29:10.981094
4165 09:29:10.984057 RX Delay -195 -> 252, step: 8
4166 09:29:10.984139
4167 09:29:10.987381 Set Vref, RX VrefLevel [Byte0]: 58
4168 09:29:10.990488 [Byte1]: 49
4169 09:29:10.990579
4170 09:29:10.993760 Final RX Vref Byte 0 = 58 to rank0
4171 09:29:10.997462 Final RX Vref Byte 1 = 49 to rank0
4172 09:29:11.000610 Final RX Vref Byte 0 = 58 to rank1
4173 09:29:11.003783 Final RX Vref Byte 1 = 49 to rank1==
4174 09:29:11.006818 Dram Type= 6, Freq= 0, CH_0, rank 0
4175 09:29:11.013781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 09:29:11.013882 ==
4177 09:29:11.013979 DQS Delay:
4178 09:29:11.014054 DQS0 = 0, DQS1 = 0
4179 09:29:11.016871 DQM Delay:
4180 09:29:11.016969 DQM0 = 44, DQM1 = 36
4181 09:29:11.020341 DQ Delay:
4182 09:29:11.023219 DQ0 =48, DQ1 =44, DQ2 =40, DQ3 =40
4183 09:29:11.026899 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4184 09:29:11.030238 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4185 09:29:11.033328 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4186 09:29:11.033409
4187 09:29:11.033472
4188 09:29:11.039760 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a41, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4189 09:29:11.043515 CH0 RK0: MR19=808, MR18=4A41
4190 09:29:11.049622 CH0_RK0: MR19=0x808, MR18=0x4A41, DQSOSC=395, MR23=63, INC=168, DEC=112
4191 09:29:11.049704
4192 09:29:11.052943 ----->DramcWriteLeveling(PI) begin...
4193 09:29:11.053043 ==
4194 09:29:11.056500 Dram Type= 6, Freq= 0, CH_0, rank 1
4195 09:29:11.059460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 09:29:11.059560 ==
4197 09:29:11.062994 Write leveling (Byte 0): 34 => 34
4198 09:29:11.066285 Write leveling (Byte 1): 29 => 29
4199 09:29:11.069540 DramcWriteLeveling(PI) end<-----
4200 09:29:11.069622
4201 09:29:11.069685 ==
4202 09:29:11.072626 Dram Type= 6, Freq= 0, CH_0, rank 1
4203 09:29:11.076340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 09:29:11.079431 ==
4205 09:29:11.079512 [Gating] SW mode calibration
4206 09:29:11.089095 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4207 09:29:11.092943 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4208 09:29:11.095982 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 09:29:11.102433 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4210 09:29:11.105714 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4211 09:29:11.109391 0 9 12 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
4212 09:29:11.116169 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4213 09:29:11.119187 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 09:29:11.122366 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 09:29:11.128600 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 09:29:11.132311 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 09:29:11.135212 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 09:29:11.141992 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4219 09:29:11.145327 0 10 12 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0)
4220 09:29:11.148830 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4221 09:29:11.155221 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 09:29:11.158711 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 09:29:11.161659 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 09:29:11.168443 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 09:29:11.171618 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 09:29:11.175259 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 09:29:11.181394 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4228 09:29:11.184897 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 09:29:11.188468 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 09:29:11.194693 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 09:29:11.198353 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 09:29:11.201456 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 09:29:11.208302 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 09:29:11.211264 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 09:29:11.214675 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 09:29:11.221075 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 09:29:11.224544 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 09:29:11.227531 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 09:29:11.234325 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 09:29:11.237846 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 09:29:11.240865 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 09:29:11.247700 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4243 09:29:11.250604 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4244 09:29:11.253854 Total UI for P1: 0, mck2ui 16
4245 09:29:11.257319 best dqsien dly found for B0: ( 0, 13, 8)
4246 09:29:11.260647 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 09:29:11.264245 Total UI for P1: 0, mck2ui 16
4248 09:29:11.267199 best dqsien dly found for B1: ( 0, 13, 12)
4249 09:29:11.270675 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4250 09:29:11.273696 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4251 09:29:11.277244
4252 09:29:11.280692 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4253 09:29:11.283786 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4254 09:29:11.286861 [Gating] SW calibration Done
4255 09:29:11.286942 ==
4256 09:29:11.290382 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 09:29:11.293480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 09:29:11.293562 ==
4259 09:29:11.293627 RX Vref Scan: 0
4260 09:29:11.293687
4261 09:29:11.297204 RX Vref 0 -> 0, step: 1
4262 09:29:11.297323
4263 09:29:11.300295 RX Delay -230 -> 252, step: 16
4264 09:29:11.303469 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4265 09:29:11.310471 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4266 09:29:11.313638 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4267 09:29:11.316680 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4268 09:29:11.320300 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4269 09:29:11.323330 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4270 09:29:11.329647 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4271 09:29:11.332846 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4272 09:29:11.336606 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4273 09:29:11.339806 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4274 09:29:11.346222 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4275 09:29:11.349858 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4276 09:29:11.353020 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4277 09:29:11.356247 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4278 09:29:11.362753 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4279 09:29:11.366089 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4280 09:29:11.366181 ==
4281 09:29:11.369396 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 09:29:11.372960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 09:29:11.373043 ==
4284 09:29:11.376039 DQS Delay:
4285 09:29:11.376120 DQS0 = 0, DQS1 = 0
4286 09:29:11.379405 DQM Delay:
4287 09:29:11.379486 DQM0 = 45, DQM1 = 38
4288 09:29:11.379549 DQ Delay:
4289 09:29:11.383092 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4290 09:29:11.385962 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4291 09:29:11.389180 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4292 09:29:11.392243 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4293 09:29:11.392328
4294 09:29:11.392406
4295 09:29:11.395953 ==
4296 09:29:11.396035 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 09:29:11.402683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 09:29:11.402783 ==
4299 09:29:11.402880
4300 09:29:11.402954
4301 09:29:11.405809 TX Vref Scan disable
4302 09:29:11.405890 == TX Byte 0 ==
4303 09:29:11.412220 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4304 09:29:11.415797 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4305 09:29:11.415879 == TX Byte 1 ==
4306 09:29:11.422033 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4307 09:29:11.425192 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4308 09:29:11.425298 ==
4309 09:29:11.428264 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 09:29:11.432257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 09:29:11.432339 ==
4312 09:29:11.432436
4313 09:29:11.432527
4314 09:29:11.435001 TX Vref Scan disable
4315 09:29:11.438390 == TX Byte 0 ==
4316 09:29:11.441639 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4317 09:29:11.445374 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4318 09:29:11.448338 == TX Byte 1 ==
4319 09:29:11.451848 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4320 09:29:11.454787 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4321 09:29:11.458507
4322 09:29:11.458588 [DATLAT]
4323 09:29:11.458652 Freq=600, CH0 RK1
4324 09:29:11.458712
4325 09:29:11.461439 DATLAT Default: 0x9
4326 09:29:11.461537 0, 0xFFFF, sum = 0
4327 09:29:11.465105 1, 0xFFFF, sum = 0
4328 09:29:11.465205 2, 0xFFFF, sum = 0
4329 09:29:11.468267 3, 0xFFFF, sum = 0
4330 09:29:11.468349 4, 0xFFFF, sum = 0
4331 09:29:11.472377 5, 0xFFFF, sum = 0
4332 09:29:11.472513 6, 0xFFFF, sum = 0
4333 09:29:11.474750 7, 0xFFFF, sum = 0
4334 09:29:11.474848 8, 0x0, sum = 1
4335 09:29:11.478102 9, 0x0, sum = 2
4336 09:29:11.478184 10, 0x0, sum = 3
4337 09:29:11.481427 11, 0x0, sum = 4
4338 09:29:11.481509 best_step = 9
4339 09:29:11.481573
4340 09:29:11.481632 ==
4341 09:29:11.484955 Dram Type= 6, Freq= 0, CH_0, rank 1
4342 09:29:11.491775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 09:29:11.491884 ==
4344 09:29:11.491976 RX Vref Scan: 0
4345 09:29:11.492073
4346 09:29:11.494645 RX Vref 0 -> 0, step: 1
4347 09:29:11.494726
4348 09:29:11.497963 RX Delay -179 -> 252, step: 8
4349 09:29:11.501350 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4350 09:29:11.508557 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4351 09:29:11.511579 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4352 09:29:11.514710 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4353 09:29:11.517673 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4354 09:29:11.524448 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4355 09:29:11.527517 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4356 09:29:11.531072 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4357 09:29:11.534217 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4358 09:29:11.537855 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4359 09:29:11.544042 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4360 09:29:11.547397 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4361 09:29:11.550865 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4362 09:29:11.553963 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4363 09:29:11.560586 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4364 09:29:11.564217 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4365 09:29:11.564299 ==
4366 09:29:11.567273 Dram Type= 6, Freq= 0, CH_0, rank 1
4367 09:29:11.570610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 09:29:11.570705 ==
4369 09:29:11.573827 DQS Delay:
4370 09:29:11.573955 DQS0 = 0, DQS1 = 0
4371 09:29:11.577105 DQM Delay:
4372 09:29:11.577186 DQM0 = 44, DQM1 = 37
4373 09:29:11.577249 DQ Delay:
4374 09:29:11.580195 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4375 09:29:11.583777 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =52
4376 09:29:11.586653 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =32
4377 09:29:11.590289 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4378 09:29:11.590373
4379 09:29:11.590437
4380 09:29:11.599733 [DQSOSCAuto] RK1, (LSB)MR18= 0x403b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4381 09:29:11.603366 CH0 RK1: MR19=808, MR18=403B
4382 09:29:11.609891 CH0_RK1: MR19=0x808, MR18=0x403B, DQSOSC=397, MR23=63, INC=166, DEC=110
4383 09:29:11.609986 [RxdqsGatingPostProcess] freq 600
4384 09:29:11.616997 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4385 09:29:11.619652 Pre-setting of DQS Precalculation
4386 09:29:11.623412 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4387 09:29:11.626225 ==
4388 09:29:11.629854 Dram Type= 6, Freq= 0, CH_1, rank 0
4389 09:29:11.632953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 09:29:11.633034 ==
4391 09:29:11.639777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4392 09:29:11.642658 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4393 09:29:11.646975 [CA 0] Center 35 (5~66) winsize 62
4394 09:29:11.650073 [CA 1] Center 35 (5~66) winsize 62
4395 09:29:11.653592 [CA 2] Center 34 (4~65) winsize 62
4396 09:29:11.656921 [CA 3] Center 34 (4~65) winsize 62
4397 09:29:11.660121 [CA 4] Center 34 (4~65) winsize 62
4398 09:29:11.663474 [CA 5] Center 34 (3~65) winsize 63
4399 09:29:11.663556
4400 09:29:11.666585 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4401 09:29:11.666672
4402 09:29:11.670319 [CATrainingPosCal] consider 1 rank data
4403 09:29:11.673448 u2DelayCellTimex100 = 270/100 ps
4404 09:29:11.677144 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4405 09:29:11.680276 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4406 09:29:11.686377 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4407 09:29:11.690072 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4408 09:29:11.693169 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4409 09:29:11.696695 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4410 09:29:11.696776
4411 09:29:11.699657 CA PerBit enable=1, Macro0, CA PI delay=34
4412 09:29:11.699737
4413 09:29:11.703125 [CBTSetCACLKResult] CA Dly = 34
4414 09:29:11.703206 CS Dly: 4 (0~35)
4415 09:29:11.706255 ==
4416 09:29:11.709866 Dram Type= 6, Freq= 0, CH_1, rank 1
4417 09:29:11.712799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 09:29:11.712880 ==
4419 09:29:11.719518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4420 09:29:11.722549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4421 09:29:11.726681 [CA 0] Center 35 (5~66) winsize 62
4422 09:29:11.730062 [CA 1] Center 35 (5~66) winsize 62
4423 09:29:11.733435 [CA 2] Center 34 (4~65) winsize 62
4424 09:29:11.736963 [CA 3] Center 34 (3~65) winsize 63
4425 09:29:11.739796 [CA 4] Center 34 (4~65) winsize 62
4426 09:29:11.743331 [CA 5] Center 33 (3~64) winsize 62
4427 09:29:11.743412
4428 09:29:11.746740 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4429 09:29:11.746848
4430 09:29:11.749818 [CATrainingPosCal] consider 2 rank data
4431 09:29:11.753424 u2DelayCellTimex100 = 270/100 ps
4432 09:29:11.756485 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4433 09:29:11.763265 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4434 09:29:11.766175 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 09:29:11.769473 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4436 09:29:11.772563 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4437 09:29:11.776180 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4438 09:29:11.776263
4439 09:29:11.779214 CA PerBit enable=1, Macro0, CA PI delay=33
4440 09:29:11.779294
4441 09:29:11.782908 [CBTSetCACLKResult] CA Dly = 33
4442 09:29:11.786228 CS Dly: 5 (0~37)
4443 09:29:11.786309
4444 09:29:11.789375 ----->DramcWriteLeveling(PI) begin...
4445 09:29:11.789457 ==
4446 09:29:11.792428 Dram Type= 6, Freq= 0, CH_1, rank 0
4447 09:29:11.796117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4448 09:29:11.796198 ==
4449 09:29:11.799160 Write leveling (Byte 0): 28 => 28
4450 09:29:11.802832 Write leveling (Byte 1): 31 => 31
4451 09:29:11.805820 DramcWriteLeveling(PI) end<-----
4452 09:29:11.805896
4453 09:29:11.805960 ==
4454 09:29:11.808945 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 09:29:11.812561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 09:29:11.812662 ==
4457 09:29:11.815990 [Gating] SW mode calibration
4458 09:29:11.822380 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4459 09:29:11.828573 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4460 09:29:11.832284 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 09:29:11.835303 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4462 09:29:11.842132 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 09:29:11.845097 0 9 12 | B1->B0 | 2e2e 2d2d | 0 1 | (0 1) (1 0)
4464 09:29:11.851701 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 09:29:11.855116 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 09:29:11.858558 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 09:29:11.861510 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 09:29:11.868628 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 09:29:11.871755 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 09:29:11.874900 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4471 09:29:11.881280 0 10 12 | B1->B0 | 3232 3b3b | 1 1 | (0 0) (0 0)
4472 09:29:11.884920 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 09:29:11.888011 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 09:29:11.894631 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 09:29:11.897672 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 09:29:11.901857 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 09:29:11.908243 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 09:29:11.911411 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 09:29:11.917528 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4480 09:29:11.921296 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4481 09:29:11.924279 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 09:29:11.930948 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 09:29:11.934320 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 09:29:11.937225 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 09:29:11.944141 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 09:29:11.947347 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 09:29:11.950382 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 09:29:11.957300 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 09:29:11.960306 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 09:29:11.964056 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 09:29:11.970325 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 09:29:11.973868 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 09:29:11.977036 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 09:29:11.983494 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 09:29:11.987081 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4496 09:29:11.990478 Total UI for P1: 0, mck2ui 16
4497 09:29:11.993465 best dqsien dly found for B0: ( 0, 13, 10)
4498 09:29:11.996802 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 09:29:12.000319 Total UI for P1: 0, mck2ui 16
4500 09:29:12.003398 best dqsien dly found for B1: ( 0, 13, 14)
4501 09:29:12.006472 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4502 09:29:12.010029 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4503 09:29:12.010111
4504 09:29:12.016898 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4505 09:29:12.019904 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4506 09:29:12.019979 [Gating] SW calibration Done
4507 09:29:12.022954 ==
4508 09:29:12.023029 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 09:29:12.029861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 09:29:12.029940 ==
4511 09:29:12.030002 RX Vref Scan: 0
4512 09:29:12.030064
4513 09:29:12.033019 RX Vref 0 -> 0, step: 1
4514 09:29:12.033113
4515 09:29:12.036575 RX Delay -230 -> 252, step: 16
4516 09:29:12.039977 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4517 09:29:12.043324 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4518 09:29:12.049747 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4519 09:29:12.052914 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4520 09:29:12.056122 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4521 09:29:12.059264 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4522 09:29:12.066429 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4523 09:29:12.069675 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4524 09:29:12.072735 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4525 09:29:12.075830 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4526 09:29:12.079654 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4527 09:29:12.086120 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4528 09:29:12.088946 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4529 09:29:12.092210 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4530 09:29:12.098917 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4531 09:29:12.102377 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4532 09:29:12.102484 ==
4533 09:29:12.105663 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 09:29:12.108785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 09:29:12.108885 ==
4536 09:29:12.108977 DQS Delay:
4537 09:29:12.112140 DQS0 = 0, DQS1 = 0
4538 09:29:12.112243 DQM Delay:
4539 09:29:12.115539 DQM0 = 44, DQM1 = 39
4540 09:29:12.115616 DQ Delay:
4541 09:29:12.118794 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4542 09:29:12.121996 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4543 09:29:12.125569 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4544 09:29:12.128614 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4545 09:29:12.128694
4546 09:29:12.128757
4547 09:29:12.128815 ==
4548 09:29:12.132396 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 09:29:12.138405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 09:29:12.138488 ==
4551 09:29:12.138556
4552 09:29:12.138617
4553 09:29:12.138675 TX Vref Scan disable
4554 09:29:12.142171 == TX Byte 0 ==
4555 09:29:12.145800 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4556 09:29:12.151933 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4557 09:29:12.152014 == TX Byte 1 ==
4558 09:29:12.155310 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4559 09:29:12.162037 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4560 09:29:12.162114 ==
4561 09:29:12.165251 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 09:29:12.168786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 09:29:12.168886 ==
4564 09:29:12.168979
4565 09:29:12.169066
4566 09:29:12.171765 TX Vref Scan disable
4567 09:29:12.174909 == TX Byte 0 ==
4568 09:29:12.178505 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4569 09:29:12.181658 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4570 09:29:12.184822 == TX Byte 1 ==
4571 09:29:12.188369 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4572 09:29:12.191508 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4573 09:29:12.191607
4574 09:29:12.191698 [DATLAT]
4575 09:29:12.194730 Freq=600, CH1 RK0
4576 09:29:12.194848
4577 09:29:12.198242 DATLAT Default: 0x9
4578 09:29:12.198313 0, 0xFFFF, sum = 0
4579 09:29:12.201151 1, 0xFFFF, sum = 0
4580 09:29:12.201255 2, 0xFFFF, sum = 0
4581 09:29:12.205189 3, 0xFFFF, sum = 0
4582 09:29:12.205310 4, 0xFFFF, sum = 0
4583 09:29:12.207967 5, 0xFFFF, sum = 0
4584 09:29:12.208068 6, 0xFFFF, sum = 0
4585 09:29:12.211448 7, 0xFFFF, sum = 0
4586 09:29:12.211552 8, 0x0, sum = 1
4587 09:29:12.215007 9, 0x0, sum = 2
4588 09:29:12.215108 10, 0x0, sum = 3
4589 09:29:12.217803 11, 0x0, sum = 4
4590 09:29:12.217874 best_step = 9
4591 09:29:12.217934
4592 09:29:12.217990 ==
4593 09:29:12.221077 Dram Type= 6, Freq= 0, CH_1, rank 0
4594 09:29:12.224468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 09:29:12.224543 ==
4596 09:29:12.227689 RX Vref Scan: 1
4597 09:29:12.227763
4598 09:29:12.231273 RX Vref 0 -> 0, step: 1
4599 09:29:12.231350
4600 09:29:12.231412 RX Delay -179 -> 252, step: 8
4601 09:29:12.234132
4602 09:29:12.234229 Set Vref, RX VrefLevel [Byte0]: 50
4603 09:29:12.237696 [Byte1]: 53
4604 09:29:12.242353
4605 09:29:12.242458 Final RX Vref Byte 0 = 50 to rank0
4606 09:29:12.245900 Final RX Vref Byte 1 = 53 to rank0
4607 09:29:12.248984 Final RX Vref Byte 0 = 50 to rank1
4608 09:29:12.252724 Final RX Vref Byte 1 = 53 to rank1==
4609 09:29:12.255840 Dram Type= 6, Freq= 0, CH_1, rank 0
4610 09:29:12.262136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 09:29:12.262255 ==
4612 09:29:12.262351 DQS Delay:
4613 09:29:12.265542 DQS0 = 0, DQS1 = 0
4614 09:29:12.265640 DQM Delay:
4615 09:29:12.265729 DQM0 = 42, DQM1 = 33
4616 09:29:12.268571 DQ Delay:
4617 09:29:12.272067 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4618 09:29:12.275682 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4619 09:29:12.278796 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4620 09:29:12.281852 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4621 09:29:12.281927
4622 09:29:12.281989
4623 09:29:12.288590 [DQSOSCAuto] RK0, (LSB)MR18= 0x344e, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4624 09:29:12.291591 CH1 RK0: MR19=808, MR18=344E
4625 09:29:12.298451 CH1_RK0: MR19=0x808, MR18=0x344E, DQSOSC=395, MR23=63, INC=168, DEC=112
4626 09:29:12.298537
4627 09:29:12.301646 ----->DramcWriteLeveling(PI) begin...
4628 09:29:12.301725 ==
4629 09:29:12.304716 Dram Type= 6, Freq= 0, CH_1, rank 1
4630 09:29:12.308376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 09:29:12.308481 ==
4632 09:29:12.311401 Write leveling (Byte 0): 29 => 29
4633 09:29:12.314988 Write leveling (Byte 1): 30 => 30
4634 09:29:12.317971 DramcWriteLeveling(PI) end<-----
4635 09:29:12.318046
4636 09:29:12.318108 ==
4637 09:29:12.321093 Dram Type= 6, Freq= 0, CH_1, rank 1
4638 09:29:12.327846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 09:29:12.327927 ==
4640 09:29:12.328019 [Gating] SW mode calibration
4641 09:29:12.337648 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4642 09:29:12.341044 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4643 09:29:12.347442 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4644 09:29:12.351029 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4645 09:29:12.354214 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 09:29:12.360639 0 9 12 | B1->B0 | 3030 2929 | 1 1 | (1 0) (1 0)
4647 09:29:12.364353 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4648 09:29:12.367312 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 09:29:12.374040 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 09:29:12.377468 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 09:29:12.380908 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 09:29:12.384019 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 09:29:12.390510 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 09:29:12.394057 0 10 12 | B1->B0 | 2e2e 3d3d | 0 0 | (0 0) (0 0)
4655 09:29:12.400273 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4656 09:29:12.403390 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 09:29:12.407083 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 09:29:12.413557 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 09:29:12.416601 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 09:29:12.420381 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 09:29:12.427065 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 09:29:12.430301 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4663 09:29:12.433101 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 09:29:12.440072 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 09:29:12.443127 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 09:29:12.446793 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 09:29:12.452884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 09:29:12.456351 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 09:29:12.459603 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 09:29:12.466102 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 09:29:12.469316 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 09:29:12.472900 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 09:29:12.479479 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 09:29:12.482305 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 09:29:12.485653 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 09:29:12.492795 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 09:29:12.495592 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 09:29:12.499323 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 09:29:12.502514 Total UI for P1: 0, mck2ui 16
4680 09:29:12.505633 best dqsien dly found for B0: ( 0, 13, 10)
4681 09:29:12.509195 Total UI for P1: 0, mck2ui 16
4682 09:29:12.512425 best dqsien dly found for B1: ( 0, 13, 10)
4683 09:29:12.515441 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4684 09:29:12.518898 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4685 09:29:12.518983
4686 09:29:12.525415 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4687 09:29:12.529099 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4688 09:29:12.529180 [Gating] SW calibration Done
4689 09:29:12.532226 ==
4690 09:29:12.535250 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 09:29:12.538677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 09:29:12.538748 ==
4693 09:29:12.538810 RX Vref Scan: 0
4694 09:29:12.538867
4695 09:29:12.541943 RX Vref 0 -> 0, step: 1
4696 09:29:12.542039
4697 09:29:12.545671 RX Delay -230 -> 252, step: 16
4698 09:29:12.548788 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4699 09:29:12.551994 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4700 09:29:12.558264 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4701 09:29:12.561955 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4702 09:29:12.565042 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4703 09:29:12.568408 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4704 09:29:12.574946 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4705 09:29:12.578170 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4706 09:29:12.581725 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4707 09:29:12.584801 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4708 09:29:12.591638 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4709 09:29:12.594452 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4710 09:29:12.597979 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4711 09:29:12.601282 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4712 09:29:12.608101 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4713 09:29:12.611148 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4714 09:29:12.611249 ==
4715 09:29:12.614963 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 09:29:12.618064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 09:29:12.618146 ==
4718 09:29:12.621530 DQS Delay:
4719 09:29:12.621636 DQS0 = 0, DQS1 = 0
4720 09:29:12.621728 DQM Delay:
4721 09:29:12.624520 DQM0 = 41, DQM1 = 39
4722 09:29:12.624616 DQ Delay:
4723 09:29:12.627618 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4724 09:29:12.631400 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4725 09:29:12.634429 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4726 09:29:12.638147 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4727 09:29:12.638249
4728 09:29:12.638338
4729 09:29:12.638424 ==
4730 09:29:12.641518 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 09:29:12.648013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 09:29:12.648094 ==
4733 09:29:12.648157
4734 09:29:12.648216
4735 09:29:12.648272 TX Vref Scan disable
4736 09:29:12.650937 == TX Byte 0 ==
4737 09:29:12.654521 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4738 09:29:12.661245 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4739 09:29:12.661388 == TX Byte 1 ==
4740 09:29:12.664402 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4741 09:29:12.671268 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4742 09:29:12.671347 ==
4743 09:29:12.673936 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 09:29:12.677516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 09:29:12.677592 ==
4746 09:29:12.677655
4747 09:29:12.677724
4748 09:29:12.680649 TX Vref Scan disable
4749 09:29:12.684410 == TX Byte 0 ==
4750 09:29:12.687147 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4751 09:29:12.690459 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4752 09:29:12.693892 == TX Byte 1 ==
4753 09:29:12.697493 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4754 09:29:12.700406 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4755 09:29:12.700488
4756 09:29:12.703720 [DATLAT]
4757 09:29:12.703825 Freq=600, CH1 RK1
4758 09:29:12.703966
4759 09:29:12.706930 DATLAT Default: 0x9
4760 09:29:12.707030 0, 0xFFFF, sum = 0
4761 09:29:12.710159 1, 0xFFFF, sum = 0
4762 09:29:12.710258 2, 0xFFFF, sum = 0
4763 09:29:12.713825 3, 0xFFFF, sum = 0
4764 09:29:12.713956 4, 0xFFFF, sum = 0
4765 09:29:12.716768 5, 0xFFFF, sum = 0
4766 09:29:12.716871 6, 0xFFFF, sum = 0
4767 09:29:12.719963 7, 0xFFFF, sum = 0
4768 09:29:12.720062 8, 0x0, sum = 1
4769 09:29:12.723597 9, 0x0, sum = 2
4770 09:29:12.723705 10, 0x0, sum = 3
4771 09:29:12.726654 11, 0x0, sum = 4
4772 09:29:12.726754 best_step = 9
4773 09:29:12.726854
4774 09:29:12.726941 ==
4775 09:29:12.730295 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 09:29:12.733419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 09:29:12.733495 ==
4778 09:29:12.736496 RX Vref Scan: 0
4779 09:29:12.736604
4780 09:29:12.740004 RX Vref 0 -> 0, step: 1
4781 09:29:12.740112
4782 09:29:12.743138 RX Delay -179 -> 252, step: 8
4783 09:29:12.746855 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4784 09:29:12.750147 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4785 09:29:12.756609 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4786 09:29:12.759500 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4787 09:29:12.762953 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4788 09:29:12.766074 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4789 09:29:12.772829 iDelay=205, Bit 6, Center 40 (-115 ~ 196) 312
4790 09:29:12.776208 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4791 09:29:12.779696 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4792 09:29:12.782840 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4793 09:29:12.789038 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4794 09:29:12.792784 iDelay=205, Bit 11, Center 32 (-123 ~ 188) 312
4795 09:29:12.796167 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4796 09:29:12.799262 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4797 09:29:12.805610 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4798 09:29:12.809326 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4799 09:29:12.809441 ==
4800 09:29:12.812277 Dram Type= 6, Freq= 0, CH_1, rank 1
4801 09:29:12.815722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4802 09:29:12.815830 ==
4803 09:29:12.818969 DQS Delay:
4804 09:29:12.819043 DQS0 = 0, DQS1 = 0
4805 09:29:12.819105 DQM Delay:
4806 09:29:12.822261 DQM0 = 36, DQM1 = 35
4807 09:29:12.822334 DQ Delay:
4808 09:29:12.825850 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4809 09:29:12.828871 DQ4 =36, DQ5 =44, DQ6 =40, DQ7 =32
4810 09:29:12.831920 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =32
4811 09:29:12.835342 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4812 09:29:12.835454
4813 09:29:12.835547
4814 09:29:12.845388 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e62, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4815 09:29:12.848450 CH1 RK1: MR19=808, MR18=3E62
4816 09:29:12.851634 CH1_RK1: MR19=0x808, MR18=0x3E62, DQSOSC=391, MR23=63, INC=171, DEC=114
4817 09:29:12.855225 [RxdqsGatingPostProcess] freq 600
4818 09:29:12.861548 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4819 09:29:12.865146 Pre-setting of DQS Precalculation
4820 09:29:12.868451 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4821 09:29:12.878378 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4822 09:29:12.884771 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4823 09:29:12.884872
4824 09:29:12.884966
4825 09:29:12.888102 [Calibration Summary] 1200 Mbps
4826 09:29:12.888206 CH 0, Rank 0
4827 09:29:12.891198 SW Impedance : PASS
4828 09:29:12.891296 DUTY Scan : NO K
4829 09:29:12.894435 ZQ Calibration : PASS
4830 09:29:12.898167 Jitter Meter : NO K
4831 09:29:12.898245 CBT Training : PASS
4832 09:29:12.901212 Write leveling : PASS
4833 09:29:12.904273 RX DQS gating : PASS
4834 09:29:12.904371 RX DQ/DQS(RDDQC) : PASS
4835 09:29:12.907453 TX DQ/DQS : PASS
4836 09:29:12.911094 RX DATLAT : PASS
4837 09:29:12.911198 RX DQ/DQS(Engine): PASS
4838 09:29:12.914347 TX OE : NO K
4839 09:29:12.914424 All Pass.
4840 09:29:12.914515
4841 09:29:12.917661 CH 0, Rank 1
4842 09:29:12.917762 SW Impedance : PASS
4843 09:29:12.920983 DUTY Scan : NO K
4844 09:29:12.924226 ZQ Calibration : PASS
4845 09:29:12.924303 Jitter Meter : NO K
4846 09:29:12.927250 CBT Training : PASS
4847 09:29:12.930779 Write leveling : PASS
4848 09:29:12.930853 RX DQS gating : PASS
4849 09:29:12.934237 RX DQ/DQS(RDDQC) : PASS
4850 09:29:12.937518 TX DQ/DQS : PASS
4851 09:29:12.937592 RX DATLAT : PASS
4852 09:29:12.940630 RX DQ/DQS(Engine): PASS
4853 09:29:12.944069 TX OE : NO K
4854 09:29:12.944146 All Pass.
4855 09:29:12.944213
4856 09:29:12.944272 CH 1, Rank 0
4857 09:29:12.947121 SW Impedance : PASS
4858 09:29:12.950748 DUTY Scan : NO K
4859 09:29:12.950825 ZQ Calibration : PASS
4860 09:29:12.953756 Jitter Meter : NO K
4861 09:29:12.956866 CBT Training : PASS
4862 09:29:12.956970 Write leveling : PASS
4863 09:29:12.960056 RX DQS gating : PASS
4864 09:29:12.963832 RX DQ/DQS(RDDQC) : PASS
4865 09:29:12.963934 TX DQ/DQS : PASS
4866 09:29:12.966877 RX DATLAT : PASS
4867 09:29:12.966954 RX DQ/DQS(Engine): PASS
4868 09:29:12.970477 TX OE : NO K
4869 09:29:12.970551 All Pass.
4870 09:29:12.970614
4871 09:29:12.973160 CH 1, Rank 1
4872 09:29:12.976541 SW Impedance : PASS
4873 09:29:12.976622 DUTY Scan : NO K
4874 09:29:12.979960 ZQ Calibration : PASS
4875 09:29:12.980041 Jitter Meter : NO K
4876 09:29:12.983577 CBT Training : PASS
4877 09:29:12.986664 Write leveling : PASS
4878 09:29:12.986744 RX DQS gating : PASS
4879 09:29:12.989738 RX DQ/DQS(RDDQC) : PASS
4880 09:29:12.993029 TX DQ/DQS : PASS
4881 09:29:12.993147 RX DATLAT : PASS
4882 09:29:12.996427 RX DQ/DQS(Engine): PASS
4883 09:29:12.999646 TX OE : NO K
4884 09:29:12.999753 All Pass.
4885 09:29:12.999844
4886 09:29:13.003176 DramC Write-DBI off
4887 09:29:13.003256 PER_BANK_REFRESH: Hybrid Mode
4888 09:29:13.006380 TX_TRACKING: ON
4889 09:29:13.016208 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4890 09:29:13.019863 [FAST_K] Save calibration result to emmc
4891 09:29:13.022837 dramc_set_vcore_voltage set vcore to 662500
4892 09:29:13.022942 Read voltage for 933, 3
4893 09:29:13.026257 Vio18 = 0
4894 09:29:13.026356 Vcore = 662500
4895 09:29:13.026448 Vdram = 0
4896 09:29:13.029592 Vddq = 0
4897 09:29:13.029663 Vmddr = 0
4898 09:29:13.035957 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4899 09:29:13.039216 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4900 09:29:13.042726 MEM_TYPE=3, freq_sel=17
4901 09:29:13.045784 sv_algorithm_assistance_LP4_1600
4902 09:29:13.049205 ============ PULL DRAM RESETB DOWN ============
4903 09:29:13.052646 ========== PULL DRAM RESETB DOWN end =========
4904 09:29:13.059312 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4905 09:29:13.062480 ===================================
4906 09:29:13.062558 LPDDR4 DRAM CONFIGURATION
4907 09:29:13.065914 ===================================
4908 09:29:13.069037 EX_ROW_EN[0] = 0x0
4909 09:29:13.072193 EX_ROW_EN[1] = 0x0
4910 09:29:13.072263 LP4Y_EN = 0x0
4911 09:29:13.075835 WORK_FSP = 0x0
4912 09:29:13.075916 WL = 0x3
4913 09:29:13.078928 RL = 0x3
4914 09:29:13.079008 BL = 0x2
4915 09:29:13.082443 RPST = 0x0
4916 09:29:13.082524 RD_PRE = 0x0
4917 09:29:13.085403 WR_PRE = 0x1
4918 09:29:13.085483 WR_PST = 0x0
4919 09:29:13.088871 DBI_WR = 0x0
4920 09:29:13.088954 DBI_RD = 0x0
4921 09:29:13.091984 OTF = 0x1
4922 09:29:13.095721 ===================================
4923 09:29:13.098717 ===================================
4924 09:29:13.098825 ANA top config
4925 09:29:13.102120 ===================================
4926 09:29:13.105479 DLL_ASYNC_EN = 0
4927 09:29:13.108653 ALL_SLAVE_EN = 1
4928 09:29:13.111706 NEW_RANK_MODE = 1
4929 09:29:13.111805 DLL_IDLE_MODE = 1
4930 09:29:13.115302 LP45_APHY_COMB_EN = 1
4931 09:29:13.118421 TX_ODT_DIS = 1
4932 09:29:13.122052 NEW_8X_MODE = 1
4933 09:29:13.125215 ===================================
4934 09:29:13.128178 ===================================
4935 09:29:13.131827 data_rate = 1866
4936 09:29:13.131929 CKR = 1
4937 09:29:13.134789 DQ_P2S_RATIO = 8
4938 09:29:13.138633 ===================================
4939 09:29:13.141568 CA_P2S_RATIO = 8
4940 09:29:13.144932 DQ_CA_OPEN = 0
4941 09:29:13.148580 DQ_SEMI_OPEN = 0
4942 09:29:13.151640 CA_SEMI_OPEN = 0
4943 09:29:13.151740 CA_FULL_RATE = 0
4944 09:29:13.154732 DQ_CKDIV4_EN = 1
4945 09:29:13.158274 CA_CKDIV4_EN = 1
4946 09:29:13.161230 CA_PREDIV_EN = 0
4947 09:29:13.164832 PH8_DLY = 0
4948 09:29:13.168211 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4949 09:29:13.168312 DQ_AAMCK_DIV = 4
4950 09:29:13.171192 CA_AAMCK_DIV = 4
4951 09:29:13.174334 CA_ADMCK_DIV = 4
4952 09:29:13.177891 DQ_TRACK_CA_EN = 0
4953 09:29:13.180894 CA_PICK = 933
4954 09:29:13.184154 CA_MCKIO = 933
4955 09:29:13.187710 MCKIO_SEMI = 0
4956 09:29:13.191433 PLL_FREQ = 3732
4957 09:29:13.191534 DQ_UI_PI_RATIO = 32
4958 09:29:13.194025 CA_UI_PI_RATIO = 0
4959 09:29:13.197538 ===================================
4960 09:29:13.200602 ===================================
4961 09:29:13.204205 memory_type:LPDDR4
4962 09:29:13.207709 GP_NUM : 10
4963 09:29:13.207781 SRAM_EN : 1
4964 09:29:13.210505 MD32_EN : 0
4965 09:29:13.214098 ===================================
4966 09:29:13.217177 [ANA_INIT] >>>>>>>>>>>>>>
4967 09:29:13.217282 <<<<<< [CONFIGURE PHASE]: ANA_TX
4968 09:29:13.220941 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4969 09:29:13.224007 ===================================
4970 09:29:13.227230 data_rate = 1866,PCW = 0X8f00
4971 09:29:13.230196 ===================================
4972 09:29:13.233823 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4973 09:29:13.240477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4974 09:29:13.246582 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4975 09:29:13.249836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4976 09:29:13.253686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4977 09:29:13.256498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4978 09:29:13.260344 [ANA_INIT] flow start
4979 09:29:13.260425 [ANA_INIT] PLL >>>>>>>>
4980 09:29:13.263233 [ANA_INIT] PLL <<<<<<<<
4981 09:29:13.266383 [ANA_INIT] MIDPI >>>>>>>>
4982 09:29:13.270168 [ANA_INIT] MIDPI <<<<<<<<
4983 09:29:13.270276 [ANA_INIT] DLL >>>>>>>>
4984 09:29:13.273217 [ANA_INIT] flow end
4985 09:29:13.276781 ============ LP4 DIFF to SE enter ============
4986 09:29:13.279684 ============ LP4 DIFF to SE exit ============
4987 09:29:13.282913 [ANA_INIT] <<<<<<<<<<<<<
4988 09:29:13.286315 [Flow] Enable top DCM control >>>>>
4989 09:29:13.289484 [Flow] Enable top DCM control <<<<<
4990 09:29:13.293164 Enable DLL master slave shuffle
4991 09:29:13.300010 ==============================================================
4992 09:29:13.300116 Gating Mode config
4993 09:29:13.306504 ==============================================================
4994 09:29:13.306613 Config description:
4995 09:29:13.316228 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4996 09:29:13.322762 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4997 09:29:13.329033 SELPH_MODE 0: By rank 1: By Phase
4998 09:29:13.335863 ==============================================================
4999 09:29:13.335945 GAT_TRACK_EN = 1
5000 09:29:13.339477 RX_GATING_MODE = 2
5001 09:29:13.342449 RX_GATING_TRACK_MODE = 2
5002 09:29:13.345776 SELPH_MODE = 1
5003 09:29:13.349368 PICG_EARLY_EN = 1
5004 09:29:13.352340 VALID_LAT_VALUE = 1
5005 09:29:13.358971 ==============================================================
5006 09:29:13.362363 Enter into Gating configuration >>>>
5007 09:29:13.365653 Exit from Gating configuration <<<<
5008 09:29:13.368925 Enter into DVFS_PRE_config >>>>>
5009 09:29:13.378290 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5010 09:29:13.382157 Exit from DVFS_PRE_config <<<<<
5011 09:29:13.384995 Enter into PICG configuration >>>>
5012 09:29:13.388694 Exit from PICG configuration <<<<
5013 09:29:13.391669 [RX_INPUT] configuration >>>>>
5014 09:29:13.395334 [RX_INPUT] configuration <<<<<
5015 09:29:13.398250 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5016 09:29:13.404900 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5017 09:29:13.411244 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5018 09:29:13.418092 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5019 09:29:13.421108 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5020 09:29:13.427837 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5021 09:29:13.431012 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5022 09:29:13.437750 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5023 09:29:13.441408 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5024 09:29:13.444314 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5025 09:29:13.447533 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5026 09:29:13.454188 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5027 09:29:13.457790 ===================================
5028 09:29:13.460743 LPDDR4 DRAM CONFIGURATION
5029 09:29:13.464463 ===================================
5030 09:29:13.464544 EX_ROW_EN[0] = 0x0
5031 09:29:13.467535 EX_ROW_EN[1] = 0x0
5032 09:29:13.467615 LP4Y_EN = 0x0
5033 09:29:13.470971 WORK_FSP = 0x0
5034 09:29:13.471078 WL = 0x3
5035 09:29:13.473932 RL = 0x3
5036 09:29:13.474012 BL = 0x2
5037 09:29:13.477317 RPST = 0x0
5038 09:29:13.477397 RD_PRE = 0x0
5039 09:29:13.480703 WR_PRE = 0x1
5040 09:29:13.480816 WR_PST = 0x0
5041 09:29:13.483654 DBI_WR = 0x0
5042 09:29:13.487459 DBI_RD = 0x0
5043 09:29:13.487539 OTF = 0x1
5044 09:29:13.490401 ===================================
5045 09:29:13.493961 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5046 09:29:13.497000 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5047 09:29:13.503714 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5048 09:29:13.506707 ===================================
5049 09:29:13.510153 LPDDR4 DRAM CONFIGURATION
5050 09:29:13.513386 ===================================
5051 09:29:13.513489 EX_ROW_EN[0] = 0x10
5052 09:29:13.516959 EX_ROW_EN[1] = 0x0
5053 09:29:13.517055 LP4Y_EN = 0x0
5054 09:29:13.519878 WORK_FSP = 0x0
5055 09:29:13.519951 WL = 0x3
5056 09:29:13.523439 RL = 0x3
5057 09:29:13.523537 BL = 0x2
5058 09:29:13.526453 RPST = 0x0
5059 09:29:13.530067 RD_PRE = 0x0
5060 09:29:13.530139 WR_PRE = 0x1
5061 09:29:13.533105 WR_PST = 0x0
5062 09:29:13.533204 DBI_WR = 0x0
5063 09:29:13.536277 DBI_RD = 0x0
5064 09:29:13.536347 OTF = 0x1
5065 09:29:13.539642 ===================================
5066 09:29:13.546338 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5067 09:29:13.550030 nWR fixed to 30
5068 09:29:13.553187 [ModeRegInit_LP4] CH0 RK0
5069 09:29:13.553290 [ModeRegInit_LP4] CH0 RK1
5070 09:29:13.556885 [ModeRegInit_LP4] CH1 RK0
5071 09:29:13.559931 [ModeRegInit_LP4] CH1 RK1
5072 09:29:13.560027 match AC timing 9
5073 09:29:13.566655 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5074 09:29:13.569709 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5075 09:29:13.573460 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5076 09:29:13.579748 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5077 09:29:13.583375 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5078 09:29:13.583450 ==
5079 09:29:13.586643 Dram Type= 6, Freq= 0, CH_0, rank 0
5080 09:29:13.589845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 09:29:13.589944 ==
5082 09:29:13.596158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5083 09:29:13.603004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5084 09:29:13.606078 [CA 0] Center 38 (7~69) winsize 63
5085 09:29:13.609847 [CA 1] Center 37 (7~68) winsize 62
5086 09:29:13.613028 [CA 2] Center 34 (4~65) winsize 62
5087 09:29:13.616470 [CA 3] Center 34 (4~65) winsize 62
5088 09:29:13.619306 [CA 4] Center 33 (3~64) winsize 62
5089 09:29:13.622745 [CA 5] Center 32 (2~63) winsize 62
5090 09:29:13.622820
5091 09:29:13.626142 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5092 09:29:13.626219
5093 09:29:13.629458 [CATrainingPosCal] consider 1 rank data
5094 09:29:13.632936 u2DelayCellTimex100 = 270/100 ps
5095 09:29:13.636096 CA0 delay=38 (7~69),Diff = 6 PI (37 cell)
5096 09:29:13.639618 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5097 09:29:13.642894 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5098 09:29:13.646100 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5099 09:29:13.652425 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5100 09:29:13.655873 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5101 09:29:13.655974
5102 09:29:13.658925 CA PerBit enable=1, Macro0, CA PI delay=32
5103 09:29:13.659020
5104 09:29:13.662657 [CBTSetCACLKResult] CA Dly = 32
5105 09:29:13.662755 CS Dly: 6 (0~37)
5106 09:29:13.662846 ==
5107 09:29:13.665653 Dram Type= 6, Freq= 0, CH_0, rank 1
5108 09:29:13.672445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 09:29:13.672548 ==
5110 09:29:13.675528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5111 09:29:13.682231 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5112 09:29:13.685329 [CA 0] Center 38 (8~68) winsize 61
5113 09:29:13.689006 [CA 1] Center 37 (7~68) winsize 62
5114 09:29:13.692125 [CA 2] Center 35 (5~65) winsize 61
5115 09:29:13.695627 [CA 3] Center 34 (4~65) winsize 62
5116 09:29:13.698918 [CA 4] Center 33 (3~64) winsize 62
5117 09:29:13.701857 [CA 5] Center 33 (3~64) winsize 62
5118 09:29:13.701926
5119 09:29:13.705023 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5120 09:29:13.705134
5121 09:29:13.708503 [CATrainingPosCal] consider 2 rank data
5122 09:29:13.711579 u2DelayCellTimex100 = 270/100 ps
5123 09:29:13.715340 CA0 delay=38 (8~68),Diff = 5 PI (31 cell)
5124 09:29:13.721482 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5125 09:29:13.725053 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5126 09:29:13.728101 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5127 09:29:13.731655 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5128 09:29:13.734805 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5129 09:29:13.734874
5130 09:29:13.738309 CA PerBit enable=1, Macro0, CA PI delay=33
5131 09:29:13.738377
5132 09:29:13.741689 [CBTSetCACLKResult] CA Dly = 33
5133 09:29:13.745033 CS Dly: 7 (0~39)
5134 09:29:13.745129
5135 09:29:13.747846 ----->DramcWriteLeveling(PI) begin...
5136 09:29:13.747922 ==
5137 09:29:13.751403 Dram Type= 6, Freq= 0, CH_0, rank 0
5138 09:29:13.754541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5139 09:29:13.754659 ==
5140 09:29:13.757720 Write leveling (Byte 0): 30 => 30
5141 09:29:13.761004 Write leveling (Byte 1): 29 => 29
5142 09:29:13.764668 DramcWriteLeveling(PI) end<-----
5143 09:29:13.764769
5144 09:29:13.764865 ==
5145 09:29:13.767527 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 09:29:13.771061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 09:29:13.771130 ==
5148 09:29:13.774429 [Gating] SW mode calibration
5149 09:29:13.781135 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5150 09:29:13.787392 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5151 09:29:13.791007 0 14 0 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
5152 09:29:13.797069 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 09:29:13.800604 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 09:29:13.803586 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 09:29:13.807313 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 09:29:13.813569 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 09:29:13.816999 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 09:29:13.820293 0 14 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
5159 09:29:13.826892 0 15 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
5160 09:29:13.830491 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 09:29:13.833448 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 09:29:13.840163 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 09:29:13.843324 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 09:29:13.847000 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 09:29:13.853345 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 09:29:13.856618 0 15 28 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
5167 09:29:13.860499 1 0 0 | B1->B0 | 3434 4444 | 0 0 | (1 1) (0 0)
5168 09:29:13.866687 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 09:29:13.869922 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 09:29:13.873192 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 09:29:13.880524 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 09:29:13.883083 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 09:29:13.886461 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5174 09:29:13.892986 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5175 09:29:13.896132 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5176 09:29:13.899608 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 09:29:13.906409 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 09:29:13.909437 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 09:29:13.913056 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 09:29:13.919609 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 09:29:13.922985 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 09:29:13.926058 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 09:29:13.932875 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 09:29:13.935889 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 09:29:13.939320 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 09:29:13.946195 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 09:29:13.949305 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 09:29:13.952403 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 09:29:13.959139 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5190 09:29:13.962049 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5191 09:29:13.969057 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5192 09:29:13.969170 Total UI for P1: 0, mck2ui 16
5193 09:29:13.972131 best dqsien dly found for B0: ( 1, 2, 26)
5194 09:29:13.978803 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5195 09:29:13.982052 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 09:29:13.985528 Total UI for P1: 0, mck2ui 16
5197 09:29:13.988389 best dqsien dly found for B1: ( 1, 3, 2)
5198 09:29:13.992059 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5199 09:29:13.995052 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5200 09:29:13.995133
5201 09:29:13.998533 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5202 09:29:14.004828 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5203 09:29:14.004907 [Gating] SW calibration Done
5204 09:29:14.004971 ==
5205 09:29:14.008624 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 09:29:14.015389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 09:29:14.015499 ==
5208 09:29:14.015593 RX Vref Scan: 0
5209 09:29:14.015683
5210 09:29:14.018292 RX Vref 0 -> 0, step: 1
5211 09:29:14.018378
5212 09:29:14.021224 RX Delay -80 -> 252, step: 8
5213 09:29:14.024891 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5214 09:29:14.028379 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5215 09:29:14.031116 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5216 09:29:14.034693 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5217 09:29:14.041473 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5218 09:29:14.044737 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5219 09:29:14.047900 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5220 09:29:14.051027 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5221 09:29:14.054088 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5222 09:29:14.060762 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5223 09:29:14.064540 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5224 09:29:14.067509 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5225 09:29:14.070844 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5226 09:29:14.074302 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5227 09:29:14.080525 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5228 09:29:14.083978 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5229 09:29:14.084061 ==
5230 09:29:14.087647 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 09:29:14.090769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 09:29:14.090853 ==
5233 09:29:14.093706 DQS Delay:
5234 09:29:14.093789 DQS0 = 0, DQS1 = 0
5235 09:29:14.093854 DQM Delay:
5236 09:29:14.097439 DQM0 = 102, DQM1 = 88
5237 09:29:14.097523 DQ Delay:
5238 09:29:14.100727 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5239 09:29:14.103660 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =107
5240 09:29:14.106853 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5241 09:29:14.110047 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5242 09:29:14.110131
5243 09:29:14.110196
5244 09:29:14.113407 ==
5245 09:29:14.116770 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 09:29:14.120429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 09:29:14.120513 ==
5248 09:29:14.120596
5249 09:29:14.120674
5250 09:29:14.123518 TX Vref Scan disable
5251 09:29:14.123601 == TX Byte 0 ==
5252 09:29:14.126730 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5253 09:29:14.133386 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5254 09:29:14.133485 == TX Byte 1 ==
5255 09:29:14.140054 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5256 09:29:14.143043 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5257 09:29:14.143127 ==
5258 09:29:14.146808 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 09:29:14.149789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 09:29:14.149879 ==
5261 09:29:14.149962
5262 09:29:14.150040
5263 09:29:14.153186 TX Vref Scan disable
5264 09:29:14.156212 == TX Byte 0 ==
5265 09:29:14.159856 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5266 09:29:14.162904 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5267 09:29:14.166505 == TX Byte 1 ==
5268 09:29:14.169715 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5269 09:29:14.173415 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5270 09:29:14.173496
5271 09:29:14.176293 [DATLAT]
5272 09:29:14.176374 Freq=933, CH0 RK0
5273 09:29:14.176438
5274 09:29:14.179562 DATLAT Default: 0xd
5275 09:29:14.179667 0, 0xFFFF, sum = 0
5276 09:29:14.182620 1, 0xFFFF, sum = 0
5277 09:29:14.182741 2, 0xFFFF, sum = 0
5278 09:29:14.186529 3, 0xFFFF, sum = 0
5279 09:29:14.186627 4, 0xFFFF, sum = 0
5280 09:29:14.189562 5, 0xFFFF, sum = 0
5281 09:29:14.189662 6, 0xFFFF, sum = 0
5282 09:29:14.193032 7, 0xFFFF, sum = 0
5283 09:29:14.193181 8, 0xFFFF, sum = 0
5284 09:29:14.196165 9, 0xFFFF, sum = 0
5285 09:29:14.196280 10, 0x0, sum = 1
5286 09:29:14.199900 11, 0x0, sum = 2
5287 09:29:14.200039 12, 0x0, sum = 3
5288 09:29:14.202955 13, 0x0, sum = 4
5289 09:29:14.203081 best_step = 11
5290 09:29:14.203205
5291 09:29:14.203321 ==
5292 09:29:14.206223 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 09:29:14.212957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 09:29:14.213191 ==
5295 09:29:14.213385 RX Vref Scan: 1
5296 09:29:14.213546
5297 09:29:14.215988 RX Vref 0 -> 0, step: 1
5298 09:29:14.216168
5299 09:29:14.219382 RX Delay -61 -> 252, step: 4
5300 09:29:14.219592
5301 09:29:14.223199 Set Vref, RX VrefLevel [Byte0]: 58
5302 09:29:14.226041 [Byte1]: 49
5303 09:29:14.226285
5304 09:29:14.229187 Final RX Vref Byte 0 = 58 to rank0
5305 09:29:14.232720 Final RX Vref Byte 1 = 49 to rank0
5306 09:29:14.236242 Final RX Vref Byte 0 = 58 to rank1
5307 09:29:14.239264 Final RX Vref Byte 1 = 49 to rank1==
5308 09:29:14.242924 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 09:29:14.245829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 09:29:14.246259 ==
5311 09:29:14.249396 DQS Delay:
5312 09:29:14.249911 DQS0 = 0, DQS1 = 0
5313 09:29:14.252847 DQM Delay:
5314 09:29:14.253307 DQM0 = 102, DQM1 = 89
5315 09:29:14.253738 DQ Delay:
5316 09:29:14.255837 DQ0 =102, DQ1 =102, DQ2 =98, DQ3 =98
5317 09:29:14.259305 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5318 09:29:14.262906 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =86
5319 09:29:14.265903 DQ12 =98, DQ13 =92, DQ14 =96, DQ15 =96
5320 09:29:14.269054
5321 09:29:14.269524
5322 09:29:14.275969 [DQSOSCAuto] RK0, (LSB)MR18= 0x1813, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5323 09:29:14.279283 CH0 RK0: MR19=505, MR18=1813
5324 09:29:14.285972 CH0_RK0: MR19=0x505, MR18=0x1813, DQSOSC=414, MR23=63, INC=63, DEC=42
5325 09:29:14.286399
5326 09:29:14.289244 ----->DramcWriteLeveling(PI) begin...
5327 09:29:14.289792 ==
5328 09:29:14.291982 Dram Type= 6, Freq= 0, CH_0, rank 1
5329 09:29:14.295372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 09:29:14.295806 ==
5331 09:29:14.298758 Write leveling (Byte 0): 32 => 32
5332 09:29:14.301804 Write leveling (Byte 1): 30 => 30
5333 09:29:14.304959 DramcWriteLeveling(PI) end<-----
5334 09:29:14.305504
5335 09:29:14.305836 ==
5336 09:29:14.308583 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 09:29:14.311743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 09:29:14.312162 ==
5339 09:29:14.314720 [Gating] SW mode calibration
5340 09:29:14.321588 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5341 09:29:14.328285 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5342 09:29:14.332128 0 14 0 | B1->B0 | 2929 3434 | 1 0 | (1 1) (0 0)
5343 09:29:14.338414 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 09:29:14.341842 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 09:29:14.344707 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 09:29:14.351325 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 09:29:14.354409 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5348 09:29:14.357470 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5349 09:29:14.364246 0 14 28 | B1->B0 | 3434 2d2d | 0 0 | (0 1) (0 1)
5350 09:29:14.367799 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
5351 09:29:14.370716 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5352 09:29:14.377853 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 09:29:14.380971 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 09:29:14.384633 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 09:29:14.390837 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 09:29:14.394353 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 09:29:14.397425 0 15 28 | B1->B0 | 2b2a 4141 | 1 0 | (0 0) (0 0)
5358 09:29:14.404289 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5359 09:29:14.407137 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 09:29:14.410790 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 09:29:14.417382 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 09:29:14.420512 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 09:29:14.424196 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 09:29:14.430318 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 09:29:14.433596 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5366 09:29:14.437370 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 09:29:14.443526 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 09:29:14.447080 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 09:29:14.450067 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 09:29:14.456660 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 09:29:14.460149 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 09:29:14.463247 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 09:29:14.469635 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 09:29:14.473110 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 09:29:14.476250 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 09:29:14.483071 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 09:29:14.486320 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 09:29:14.489935 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 09:29:14.496590 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 09:29:14.499681 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5381 09:29:14.502785 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5382 09:29:14.509185 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5383 09:29:14.509660 Total UI for P1: 0, mck2ui 16
5384 09:29:14.516121 best dqsien dly found for B0: ( 1, 2, 26)
5385 09:29:14.519153 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 09:29:14.522702 Total UI for P1: 0, mck2ui 16
5387 09:29:14.525762 best dqsien dly found for B1: ( 1, 2, 30)
5388 09:29:14.529493 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5389 09:29:14.532489 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5390 09:29:14.532906
5391 09:29:14.535560 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5392 09:29:14.539252 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5393 09:29:14.542414 [Gating] SW calibration Done
5394 09:29:14.542826 ==
5395 09:29:14.545558 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 09:29:14.552199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 09:29:14.552616 ==
5398 09:29:14.552941 RX Vref Scan: 0
5399 09:29:14.553244
5400 09:29:14.555312 RX Vref 0 -> 0, step: 1
5401 09:29:14.555723
5402 09:29:14.558812 RX Delay -80 -> 252, step: 8
5403 09:29:14.561907 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5404 09:29:14.565202 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5405 09:29:14.568806 iDelay=200, Bit 2, Center 95 (8 ~ 183) 176
5406 09:29:14.571864 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5407 09:29:14.578387 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5408 09:29:14.581849 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5409 09:29:14.585134 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5410 09:29:14.588415 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5411 09:29:14.591793 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5412 09:29:14.594926 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5413 09:29:14.601572 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5414 09:29:14.605168 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5415 09:29:14.608130 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5416 09:29:14.611196 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5417 09:29:14.614852 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5418 09:29:14.621206 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5419 09:29:14.621659 ==
5420 09:29:14.624644 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 09:29:14.628104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 09:29:14.628526 ==
5423 09:29:14.628858 DQS Delay:
5424 09:29:14.631157 DQS0 = 0, DQS1 = 0
5425 09:29:14.631575 DQM Delay:
5426 09:29:14.634579 DQM0 = 100, DQM1 = 89
5427 09:29:14.635102 DQ Delay:
5428 09:29:14.637904 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5429 09:29:14.640998 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5430 09:29:14.644111 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5431 09:29:14.648183 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5432 09:29:14.648692
5433 09:29:14.649014
5434 09:29:14.649342 ==
5435 09:29:14.651233 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 09:29:14.657531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 09:29:14.658043 ==
5438 09:29:14.658371
5439 09:29:14.658669
5440 09:29:14.658958 TX Vref Scan disable
5441 09:29:14.660837 == TX Byte 0 ==
5442 09:29:14.664265 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5443 09:29:14.670882 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5444 09:29:14.671378 == TX Byte 1 ==
5445 09:29:14.673958 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5446 09:29:14.680883 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5447 09:29:14.681441 ==
5448 09:29:14.684360 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 09:29:14.687820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 09:29:14.688391 ==
5451 09:29:14.688735
5452 09:29:14.689034
5453 09:29:14.690549 TX Vref Scan disable
5454 09:29:14.690958 == TX Byte 0 ==
5455 09:29:14.697075 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5456 09:29:14.700553 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5457 09:29:14.703978 == TX Byte 1 ==
5458 09:29:14.707391 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5459 09:29:14.710321 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5460 09:29:14.710746
5461 09:29:14.711079 [DATLAT]
5462 09:29:14.713363 Freq=933, CH0 RK1
5463 09:29:14.713787
5464 09:29:14.716678 DATLAT Default: 0xb
5465 09:29:14.717210 0, 0xFFFF, sum = 0
5466 09:29:14.720240 1, 0xFFFF, sum = 0
5467 09:29:14.720812 2, 0xFFFF, sum = 0
5468 09:29:14.723879 3, 0xFFFF, sum = 0
5469 09:29:14.724462 4, 0xFFFF, sum = 0
5470 09:29:14.726452 5, 0xFFFF, sum = 0
5471 09:29:14.726880 6, 0xFFFF, sum = 0
5472 09:29:14.730108 7, 0xFFFF, sum = 0
5473 09:29:14.730534 8, 0xFFFF, sum = 0
5474 09:29:14.733500 9, 0xFFFF, sum = 0
5475 09:29:14.733925 10, 0x0, sum = 1
5476 09:29:14.736481 11, 0x0, sum = 2
5477 09:29:14.736908 12, 0x0, sum = 3
5478 09:29:14.739637 13, 0x0, sum = 4
5479 09:29:14.740077 best_step = 11
5480 09:29:14.740406
5481 09:29:14.740714 ==
5482 09:29:14.743361 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 09:29:14.746327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 09:29:14.749600 ==
5485 09:29:14.750023 RX Vref Scan: 0
5486 09:29:14.750356
5487 09:29:14.753170 RX Vref 0 -> 0, step: 1
5488 09:29:14.753656
5489 09:29:14.756173 RX Delay -61 -> 252, step: 4
5490 09:29:14.759309 iDelay=199, Bit 0, Center 100 (15 ~ 186) 172
5491 09:29:14.762938 iDelay=199, Bit 1, Center 102 (15 ~ 190) 176
5492 09:29:14.769144 iDelay=199, Bit 2, Center 98 (15 ~ 182) 168
5493 09:29:14.772856 iDelay=199, Bit 3, Center 98 (11 ~ 186) 176
5494 09:29:14.775845 iDelay=199, Bit 4, Center 102 (15 ~ 190) 176
5495 09:29:14.783009 iDelay=199, Bit 5, Center 92 (7 ~ 178) 172
5496 09:29:14.783801 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5497 09:29:14.789122 iDelay=199, Bit 7, Center 108 (23 ~ 194) 172
5498 09:29:14.792252 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5499 09:29:14.796014 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5500 09:29:14.799077 iDelay=199, Bit 10, Center 90 (3 ~ 178) 176
5501 09:29:14.802203 iDelay=199, Bit 11, Center 84 (3 ~ 166) 164
5502 09:29:14.806042 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5503 09:29:14.812214 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5504 09:29:14.815610 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5505 09:29:14.819020 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5506 09:29:14.819445 ==
5507 09:29:14.822192 Dram Type= 6, Freq= 0, CH_0, rank 1
5508 09:29:14.825217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 09:29:14.825677 ==
5510 09:29:14.828707 DQS Delay:
5511 09:29:14.829127 DQS0 = 0, DQS1 = 0
5512 09:29:14.831843 DQM Delay:
5513 09:29:14.832263 DQM0 = 101, DQM1 = 89
5514 09:29:14.835343 DQ Delay:
5515 09:29:14.838413 DQ0 =100, DQ1 =102, DQ2 =98, DQ3 =98
5516 09:29:14.841670 DQ4 =102, DQ5 =92, DQ6 =110, DQ7 =108
5517 09:29:14.845283 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5518 09:29:14.848797 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =96
5519 09:29:14.849218
5520 09:29:14.849650
5521 09:29:14.855132 [DQSOSCAuto] RK1, (LSB)MR18= 0x1918, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5522 09:29:14.858307 CH0 RK1: MR19=505, MR18=1918
5523 09:29:14.865094 CH0_RK1: MR19=0x505, MR18=0x1918, DQSOSC=413, MR23=63, INC=63, DEC=42
5524 09:29:14.868227 [RxdqsGatingPostProcess] freq 933
5525 09:29:14.871665 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5526 09:29:14.874450 best DQS0 dly(2T, 0.5T) = (0, 10)
5527 09:29:14.877949 best DQS1 dly(2T, 0.5T) = (0, 11)
5528 09:29:14.881717 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5529 09:29:14.884710 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5530 09:29:14.888259 best DQS0 dly(2T, 0.5T) = (0, 10)
5531 09:29:14.891169 best DQS1 dly(2T, 0.5T) = (0, 10)
5532 09:29:14.894730 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5533 09:29:14.897846 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5534 09:29:14.901092 Pre-setting of DQS Precalculation
5535 09:29:14.905058 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5536 09:29:14.907906 ==
5537 09:29:14.911063 Dram Type= 6, Freq= 0, CH_1, rank 0
5538 09:29:14.914216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 09:29:14.914643 ==
5540 09:29:14.921126 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5541 09:29:14.924021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5542 09:29:14.927882 [CA 0] Center 37 (6~68) winsize 63
5543 09:29:14.931603 [CA 1] Center 37 (6~68) winsize 63
5544 09:29:14.934699 [CA 2] Center 35 (5~65) winsize 61
5545 09:29:14.937873 [CA 3] Center 34 (4~64) winsize 61
5546 09:29:14.941504 [CA 4] Center 34 (4~65) winsize 62
5547 09:29:14.944412 [CA 5] Center 33 (3~64) winsize 62
5548 09:29:14.944879
5549 09:29:14.948032 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5550 09:29:14.948457
5551 09:29:14.951247 [CATrainingPosCal] consider 1 rank data
5552 09:29:14.954278 u2DelayCellTimex100 = 270/100 ps
5553 09:29:14.957566 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5554 09:29:14.963967 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5555 09:29:14.967361 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5556 09:29:14.971147 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5557 09:29:14.974359 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5558 09:29:14.977408 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5559 09:29:14.977844
5560 09:29:14.980840 CA PerBit enable=1, Macro0, CA PI delay=33
5561 09:29:14.981311
5562 09:29:14.984039 [CBTSetCACLKResult] CA Dly = 33
5563 09:29:14.987665 CS Dly: 5 (0~36)
5564 09:29:14.988098 ==
5565 09:29:14.990611 Dram Type= 6, Freq= 0, CH_1, rank 1
5566 09:29:14.993661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 09:29:14.994100 ==
5568 09:29:15.000315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5569 09:29:15.004074 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5570 09:29:15.008307 [CA 0] Center 36 (6~67) winsize 62
5571 09:29:15.011518 [CA 1] Center 37 (7~67) winsize 61
5572 09:29:15.014923 [CA 2] Center 34 (4~65) winsize 62
5573 09:29:15.017674 [CA 3] Center 33 (3~64) winsize 62
5574 09:29:15.021233 [CA 4] Center 34 (3~65) winsize 63
5575 09:29:15.024443 [CA 5] Center 33 (3~64) winsize 62
5576 09:29:15.024867
5577 09:29:15.028133 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5578 09:29:15.028555
5579 09:29:15.031134 [CATrainingPosCal] consider 2 rank data
5580 09:29:15.034648 u2DelayCellTimex100 = 270/100 ps
5581 09:29:15.037734 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5582 09:29:15.044252 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5583 09:29:15.047312 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5584 09:29:15.050856 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5585 09:29:15.054218 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5586 09:29:15.057097 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5587 09:29:15.057566
5588 09:29:15.060761 CA PerBit enable=1, Macro0, CA PI delay=33
5589 09:29:15.061180
5590 09:29:15.063747 [CBTSetCACLKResult] CA Dly = 33
5591 09:29:15.067431 CS Dly: 6 (0~38)
5592 09:29:15.067850
5593 09:29:15.070820 ----->DramcWriteLeveling(PI) begin...
5594 09:29:15.071246 ==
5595 09:29:15.073551 Dram Type= 6, Freq= 0, CH_1, rank 0
5596 09:29:15.076706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5597 09:29:15.077005 ==
5598 09:29:15.080103 Write leveling (Byte 0): 25 => 25
5599 09:29:15.083279 Write leveling (Byte 1): 29 => 29
5600 09:29:15.086826 DramcWriteLeveling(PI) end<-----
5601 09:29:15.087011
5602 09:29:15.087197 ==
5603 09:29:15.090164 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 09:29:15.093643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 09:29:15.093799 ==
5606 09:29:15.096312 [Gating] SW mode calibration
5607 09:29:15.103176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5608 09:29:15.109915 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5609 09:29:15.112875 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 09:29:15.119825 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 09:29:15.122795 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 09:29:15.125927 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 09:29:15.132726 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 09:29:15.135947 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 09:29:15.139166 0 14 24 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 1)
5616 09:29:15.146050 0 14 28 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
5617 09:29:15.149736 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 09:29:15.152357 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 09:29:15.159051 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 09:29:15.162442 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 09:29:15.165501 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 09:29:15.172036 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 09:29:15.175750 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5624 09:29:15.178991 0 15 28 | B1->B0 | 3939 3e3e | 0 0 | (0 0) (0 0)
5625 09:29:15.185318 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 09:29:15.189201 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 09:29:15.192540 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 09:29:15.199032 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 09:29:15.202181 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 09:29:15.205527 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 09:29:15.212166 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5632 09:29:15.215635 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5633 09:29:15.218717 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5634 09:29:15.225543 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 09:29:15.228608 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 09:29:15.231853 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 09:29:15.238773 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 09:29:15.241898 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 09:29:15.244782 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 09:29:15.251671 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 09:29:15.254726 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 09:29:15.257883 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 09:29:15.264694 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 09:29:15.267863 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 09:29:15.271227 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 09:29:15.278042 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 09:29:15.281025 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5648 09:29:15.284088 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5649 09:29:15.290908 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 09:29:15.291332 Total UI for P1: 0, mck2ui 16
5651 09:29:15.297429 best dqsien dly found for B0: ( 1, 2, 26)
5652 09:29:15.297905 Total UI for P1: 0, mck2ui 16
5653 09:29:15.303841 best dqsien dly found for B1: ( 1, 2, 26)
5654 09:29:15.307321 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5655 09:29:15.310674 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5656 09:29:15.311282
5657 09:29:15.313748 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5658 09:29:15.317005 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5659 09:29:15.320446 [Gating] SW calibration Done
5660 09:29:15.320922 ==
5661 09:29:15.323866 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 09:29:15.327436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 09:29:15.328043 ==
5664 09:29:15.330383 RX Vref Scan: 0
5665 09:29:15.330798
5666 09:29:15.331122 RX Vref 0 -> 0, step: 1
5667 09:29:15.334040
5668 09:29:15.334451 RX Delay -80 -> 252, step: 8
5669 09:29:15.340337 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5670 09:29:15.343556 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5671 09:29:15.346681 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5672 09:29:15.350067 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5673 09:29:15.353342 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5674 09:29:15.357012 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5675 09:29:15.363129 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5676 09:29:15.366857 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5677 09:29:15.369865 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5678 09:29:15.373516 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5679 09:29:15.376399 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5680 09:29:15.383199 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5681 09:29:15.386414 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5682 09:29:15.389814 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5683 09:29:15.392701 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5684 09:29:15.395775 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5685 09:29:15.396354 ==
5686 09:29:15.399416 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 09:29:15.405820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 09:29:15.406257 ==
5689 09:29:15.406585 DQS Delay:
5690 09:29:15.409501 DQS0 = 0, DQS1 = 0
5691 09:29:15.409916 DQM Delay:
5692 09:29:15.410247 DQM0 = 98, DQM1 = 93
5693 09:29:15.412436 DQ Delay:
5694 09:29:15.415808 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5695 09:29:15.419239 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5696 09:29:15.422569 DQ8 =79, DQ9 =87, DQ10 =91, DQ11 =87
5697 09:29:15.425561 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5698 09:29:15.425951
5699 09:29:15.426266
5700 09:29:15.426560 ==
5701 09:29:15.429173 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 09:29:15.432292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 09:29:15.432714 ==
5704 09:29:15.433187
5705 09:29:15.433574
5706 09:29:15.435629 TX Vref Scan disable
5707 09:29:15.438986 == TX Byte 0 ==
5708 09:29:15.442352 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5709 09:29:15.445495 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5710 09:29:15.449224 == TX Byte 1 ==
5711 09:29:15.452566 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5712 09:29:15.455914 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5713 09:29:15.456435 ==
5714 09:29:15.459169 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 09:29:15.465807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 09:29:15.466564 ==
5717 09:29:15.467053
5718 09:29:15.467510
5719 09:29:15.467955 TX Vref Scan disable
5720 09:29:15.468990 == TX Byte 0 ==
5721 09:29:15.472272 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5722 09:29:15.479114 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5723 09:29:15.479532 == TX Byte 1 ==
5724 09:29:15.482292 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5725 09:29:15.489076 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5726 09:29:15.489571
5727 09:29:15.489901 [DATLAT]
5728 09:29:15.490206 Freq=933, CH1 RK0
5729 09:29:15.490501
5730 09:29:15.492396 DATLAT Default: 0xd
5731 09:29:15.492930 0, 0xFFFF, sum = 0
5732 09:29:15.495956 1, 0xFFFF, sum = 0
5733 09:29:15.498877 2, 0xFFFF, sum = 0
5734 09:29:15.499298 3, 0xFFFF, sum = 0
5735 09:29:15.502069 4, 0xFFFF, sum = 0
5736 09:29:15.502490 5, 0xFFFF, sum = 0
5737 09:29:15.505840 6, 0xFFFF, sum = 0
5738 09:29:15.506261 7, 0xFFFF, sum = 0
5739 09:29:15.508846 8, 0xFFFF, sum = 0
5740 09:29:15.509313 9, 0xFFFF, sum = 0
5741 09:29:15.512397 10, 0x0, sum = 1
5742 09:29:15.512851 11, 0x0, sum = 2
5743 09:29:15.515452 12, 0x0, sum = 3
5744 09:29:15.515875 13, 0x0, sum = 4
5745 09:29:15.516204 best_step = 11
5746 09:29:15.518580
5747 09:29:15.518994 ==
5748 09:29:15.522312 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 09:29:15.525175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 09:29:15.525640 ==
5751 09:29:15.525972 RX Vref Scan: 1
5752 09:29:15.526283
5753 09:29:15.528246 RX Vref 0 -> 0, step: 1
5754 09:29:15.528660
5755 09:29:15.531879 RX Delay -61 -> 252, step: 4
5756 09:29:15.532295
5757 09:29:15.534913 Set Vref, RX VrefLevel [Byte0]: 50
5758 09:29:15.538529 [Byte1]: 53
5759 09:29:15.541471
5760 09:29:15.541894 Final RX Vref Byte 0 = 50 to rank0
5761 09:29:15.545175 Final RX Vref Byte 1 = 53 to rank0
5762 09:29:15.548402 Final RX Vref Byte 0 = 50 to rank1
5763 09:29:15.551319 Final RX Vref Byte 1 = 53 to rank1==
5764 09:29:15.554603 Dram Type= 6, Freq= 0, CH_1, rank 0
5765 09:29:15.561290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 09:29:15.561720 ==
5767 09:29:15.562048 DQS Delay:
5768 09:29:15.564875 DQS0 = 0, DQS1 = 0
5769 09:29:15.565330 DQM Delay:
5770 09:29:15.565673 DQM0 = 96, DQM1 = 93
5771 09:29:15.568007 DQ Delay:
5772 09:29:15.571492 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =96
5773 09:29:15.574580 DQ4 =90, DQ5 =106, DQ6 =106, DQ7 =92
5774 09:29:15.577644 DQ8 =78, DQ9 =82, DQ10 =90, DQ11 =86
5775 09:29:15.581230 DQ12 =104, DQ13 =102, DQ14 =102, DQ15 =102
5776 09:29:15.581696
5777 09:29:15.582024
5778 09:29:15.587541 [DQSOSCAuto] RK0, (LSB)MR18= 0xa1a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5779 09:29:15.590997 CH1 RK0: MR19=505, MR18=A1A
5780 09:29:15.597711 CH1_RK0: MR19=0x505, MR18=0xA1A, DQSOSC=413, MR23=63, INC=63, DEC=42
5781 09:29:15.598136
5782 09:29:15.600691 ----->DramcWriteLeveling(PI) begin...
5783 09:29:15.601114 ==
5784 09:29:15.604430 Dram Type= 6, Freq= 0, CH_1, rank 1
5785 09:29:15.607306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5786 09:29:15.610474 ==
5787 09:29:15.610890 Write leveling (Byte 0): 29 => 29
5788 09:29:15.613676 Write leveling (Byte 1): 29 => 29
5789 09:29:15.617201 DramcWriteLeveling(PI) end<-----
5790 09:29:15.617647
5791 09:29:15.617970 ==
5792 09:29:15.620397 Dram Type= 6, Freq= 0, CH_1, rank 1
5793 09:29:15.627324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 09:29:15.627803 ==
5795 09:29:15.630354 [Gating] SW mode calibration
5796 09:29:15.636936 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5797 09:29:15.640526 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5798 09:29:15.647154 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 09:29:15.650216 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 09:29:15.653315 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 09:29:15.660014 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 09:29:15.663620 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 09:29:15.667338 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 09:29:15.673234 0 14 24 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 0)
5805 09:29:15.676341 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
5806 09:29:15.679821 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 09:29:15.686129 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 09:29:15.689393 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 09:29:15.692500 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 09:29:15.699248 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 09:29:15.702657 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 09:29:15.706053 0 15 24 | B1->B0 | 2525 3838 | 1 1 | (1 1) (0 0)
5813 09:29:15.712628 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5814 09:29:15.716180 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 09:29:15.719136 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 09:29:15.726192 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 09:29:15.729359 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 09:29:15.732498 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 09:29:15.739343 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 09:29:15.742226 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5821 09:29:15.745898 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5822 09:29:15.752088 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 09:29:15.755740 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 09:29:15.758822 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 09:29:15.765450 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 09:29:15.768466 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 09:29:15.772112 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 09:29:15.779045 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 09:29:15.782115 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 09:29:15.785087 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 09:29:15.791908 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 09:29:15.795029 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 09:29:15.798311 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 09:29:15.804805 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 09:29:15.808331 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 09:29:15.811717 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5837 09:29:15.818631 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 09:29:15.819085 Total UI for P1: 0, mck2ui 16
5839 09:29:15.824703 best dqsien dly found for B0: ( 1, 2, 24)
5840 09:29:15.825142 Total UI for P1: 0, mck2ui 16
5841 09:29:15.831286 best dqsien dly found for B1: ( 1, 2, 26)
5842 09:29:15.834658 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5843 09:29:15.838366 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5844 09:29:15.838804
5845 09:29:15.841133 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5846 09:29:15.844581 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5847 09:29:15.847576 [Gating] SW calibration Done
5848 09:29:15.848015 ==
5849 09:29:15.851285 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 09:29:15.854344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 09:29:15.854783 ==
5852 09:29:15.857151 RX Vref Scan: 0
5853 09:29:15.857266
5854 09:29:15.857352 RX Vref 0 -> 0, step: 1
5855 09:29:15.857431
5856 09:29:15.860857 RX Delay -80 -> 252, step: 8
5857 09:29:15.867019 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5858 09:29:15.870440 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5859 09:29:15.873589 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5860 09:29:15.876780 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5861 09:29:15.880429 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5862 09:29:15.883416 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5863 09:29:15.889939 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5864 09:29:15.893634 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5865 09:29:15.896849 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5866 09:29:15.900109 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5867 09:29:15.903496 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5868 09:29:15.906459 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5869 09:29:15.913166 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5870 09:29:15.916608 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5871 09:29:15.919897 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5872 09:29:15.922853 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5873 09:29:15.922929 ==
5874 09:29:15.925997 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 09:29:15.932885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 09:29:15.932961 ==
5877 09:29:15.933026 DQS Delay:
5878 09:29:15.933087 DQS0 = 0, DQS1 = 0
5879 09:29:15.936391 DQM Delay:
5880 09:29:15.936457 DQM0 = 96, DQM1 = 92
5881 09:29:15.939525 DQ Delay:
5882 09:29:15.943098 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5883 09:29:15.945998 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5884 09:29:15.949488 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5885 09:29:15.952827 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5886 09:29:15.952893
5887 09:29:15.952952
5888 09:29:15.953007 ==
5889 09:29:15.955842 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 09:29:15.959363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 09:29:15.959529 ==
5892 09:29:15.959607
5893 09:29:15.959691
5894 09:29:15.962686 TX Vref Scan disable
5895 09:29:15.966129 == TX Byte 0 ==
5896 09:29:15.969407 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5897 09:29:15.972491 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5898 09:29:15.975958 == TX Byte 1 ==
5899 09:29:15.979167 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5900 09:29:15.982705 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5901 09:29:15.982919 ==
5902 09:29:15.985674 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 09:29:15.989173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 09:29:15.992139 ==
5905 09:29:15.992310
5906 09:29:15.992442
5907 09:29:15.992565 TX Vref Scan disable
5908 09:29:15.996042 == TX Byte 0 ==
5909 09:29:15.999025 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5910 09:29:16.005771 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5911 09:29:16.006413 == TX Byte 1 ==
5912 09:29:16.009237 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5913 09:29:16.015665 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5914 09:29:16.016141
5915 09:29:16.016475 [DATLAT]
5916 09:29:16.016800 Freq=933, CH1 RK1
5917 09:29:16.017092
5918 09:29:16.019046 DATLAT Default: 0xb
5919 09:29:16.022637 0, 0xFFFF, sum = 0
5920 09:29:16.023068 1, 0xFFFF, sum = 0
5921 09:29:16.025354 2, 0xFFFF, sum = 0
5922 09:29:16.025826 3, 0xFFFF, sum = 0
5923 09:29:16.028879 4, 0xFFFF, sum = 0
5924 09:29:16.029419 5, 0xFFFF, sum = 0
5925 09:29:16.032031 6, 0xFFFF, sum = 0
5926 09:29:16.032586 7, 0xFFFF, sum = 0
5927 09:29:16.035669 8, 0xFFFF, sum = 0
5928 09:29:16.036131 9, 0xFFFF, sum = 0
5929 09:29:16.038760 10, 0x0, sum = 1
5930 09:29:16.039141 11, 0x0, sum = 2
5931 09:29:16.041966 12, 0x0, sum = 3
5932 09:29:16.042417 13, 0x0, sum = 4
5933 09:29:16.045700 best_step = 11
5934 09:29:16.046254
5935 09:29:16.046617 ==
5936 09:29:16.048742 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 09:29:16.051808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 09:29:16.052241 ==
5939 09:29:16.052598 RX Vref Scan: 0
5940 09:29:16.055572
5941 09:29:16.056015 RX Vref 0 -> 0, step: 1
5942 09:29:16.056344
5943 09:29:16.058496 RX Delay -61 -> 252, step: 4
5944 09:29:16.065192 iDelay=199, Bit 0, Center 100 (7 ~ 194) 188
5945 09:29:16.068305 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5946 09:29:16.071426 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5947 09:29:16.074875 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5948 09:29:16.078015 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5949 09:29:16.084842 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5950 09:29:16.087997 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5951 09:29:16.091332 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5952 09:29:16.094898 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5953 09:29:16.097948 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5954 09:29:16.101380 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5955 09:29:16.107567 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5956 09:29:16.111245 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5957 09:29:16.114194 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5958 09:29:16.117320 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5959 09:29:16.124182 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5960 09:29:16.124781 ==
5961 09:29:16.127636 Dram Type= 6, Freq= 0, CH_1, rank 1
5962 09:29:16.130758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5963 09:29:16.131198 ==
5964 09:29:16.131634 DQS Delay:
5965 09:29:16.134340 DQS0 = 0, DQS1 = 0
5966 09:29:16.134775 DQM Delay:
5967 09:29:16.137306 DQM0 = 96, DQM1 = 92
5968 09:29:16.137752 DQ Delay:
5969 09:29:16.140672 DQ0 =100, DQ1 =94, DQ2 =84, DQ3 =96
5970 09:29:16.143685 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =92
5971 09:29:16.146917 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5972 09:29:16.150589 DQ12 =102, DQ13 =98, DQ14 =98, DQ15 =102
5973 09:29:16.151029
5974 09:29:16.151462
5975 09:29:16.160609 [DQSOSCAuto] RK1, (LSB)MR18= 0x1128, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5976 09:29:16.161058 CH1 RK1: MR19=505, MR18=1128
5977 09:29:16.166731 CH1_RK1: MR19=0x505, MR18=0x1128, DQSOSC=409, MR23=63, INC=64, DEC=43
5978 09:29:16.170544 [RxdqsGatingPostProcess] freq 933
5979 09:29:16.176611 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5980 09:29:16.179962 best DQS0 dly(2T, 0.5T) = (0, 10)
5981 09:29:16.183223 best DQS1 dly(2T, 0.5T) = (0, 10)
5982 09:29:16.186392 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5983 09:29:16.189689 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5984 09:29:16.193196 best DQS0 dly(2T, 0.5T) = (0, 10)
5985 09:29:16.196201 best DQS1 dly(2T, 0.5T) = (0, 10)
5986 09:29:16.199568 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5987 09:29:16.203135 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5988 09:29:16.203559 Pre-setting of DQS Precalculation
5989 09:29:16.209471 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5990 09:29:16.216327 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5991 09:29:16.222572 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5992 09:29:16.223294
5993 09:29:16.223842
5994 09:29:16.226183 [Calibration Summary] 1866 Mbps
5995 09:29:16.229792 CH 0, Rank 0
5996 09:29:16.230330 SW Impedance : PASS
5997 09:29:16.232579 DUTY Scan : NO K
5998 09:29:16.235980 ZQ Calibration : PASS
5999 09:29:16.236434 Jitter Meter : NO K
6000 09:29:16.239145 CBT Training : PASS
6001 09:29:16.242690 Write leveling : PASS
6002 09:29:16.243137 RX DQS gating : PASS
6003 09:29:16.245716 RX DQ/DQS(RDDQC) : PASS
6004 09:29:16.249219 TX DQ/DQS : PASS
6005 09:29:16.249714 RX DATLAT : PASS
6006 09:29:16.252250 RX DQ/DQS(Engine): PASS
6007 09:29:16.255407 TX OE : NO K
6008 09:29:16.255855 All Pass.
6009 09:29:16.256286
6010 09:29:16.256698 CH 0, Rank 1
6011 09:29:16.259298 SW Impedance : PASS
6012 09:29:16.262378 DUTY Scan : NO K
6013 09:29:16.262813 ZQ Calibration : PASS
6014 09:29:16.265454 Jitter Meter : NO K
6015 09:29:16.269110 CBT Training : PASS
6016 09:29:16.269591 Write leveling : PASS
6017 09:29:16.272197 RX DQS gating : PASS
6018 09:29:16.272632 RX DQ/DQS(RDDQC) : PASS
6019 09:29:16.275342 TX DQ/DQS : PASS
6020 09:29:16.278900 RX DATLAT : PASS
6021 09:29:16.279336 RX DQ/DQS(Engine): PASS
6022 09:29:16.281936 TX OE : NO K
6023 09:29:16.282373 All Pass.
6024 09:29:16.282806
6025 09:29:16.285048 CH 1, Rank 0
6026 09:29:16.285539 SW Impedance : PASS
6027 09:29:16.288558 DUTY Scan : NO K
6028 09:29:16.291887 ZQ Calibration : PASS
6029 09:29:16.292323 Jitter Meter : NO K
6030 09:29:16.295230 CBT Training : PASS
6031 09:29:16.298683 Write leveling : PASS
6032 09:29:16.299307 RX DQS gating : PASS
6033 09:29:16.301633 RX DQ/DQS(RDDQC) : PASS
6034 09:29:16.305105 TX DQ/DQS : PASS
6035 09:29:16.305605 RX DATLAT : PASS
6036 09:29:16.308288 RX DQ/DQS(Engine): PASS
6037 09:29:16.311596 TX OE : NO K
6038 09:29:16.312015 All Pass.
6039 09:29:16.312340
6040 09:29:16.312777 CH 1, Rank 1
6041 09:29:16.314991 SW Impedance : PASS
6042 09:29:16.318049 DUTY Scan : NO K
6043 09:29:16.318469 ZQ Calibration : PASS
6044 09:29:16.321581 Jitter Meter : NO K
6045 09:29:16.324756 CBT Training : PASS
6046 09:29:16.325349 Write leveling : PASS
6047 09:29:16.328447 RX DQS gating : PASS
6048 09:29:16.331341 RX DQ/DQS(RDDQC) : PASS
6049 09:29:16.331760 TX DQ/DQS : PASS
6050 09:29:16.334551 RX DATLAT : PASS
6051 09:29:16.338288 RX DQ/DQS(Engine): PASS
6052 09:29:16.338710 TX OE : NO K
6053 09:29:16.341067 All Pass.
6054 09:29:16.341540
6055 09:29:16.341875 DramC Write-DBI off
6056 09:29:16.344663 PER_BANK_REFRESH: Hybrid Mode
6057 09:29:16.345082 TX_TRACKING: ON
6058 09:29:16.354339 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6059 09:29:16.357853 [FAST_K] Save calibration result to emmc
6060 09:29:16.361038 dramc_set_vcore_voltage set vcore to 650000
6061 09:29:16.364201 Read voltage for 400, 6
6062 09:29:16.364618 Vio18 = 0
6063 09:29:16.367785 Vcore = 650000
6064 09:29:16.368398 Vdram = 0
6065 09:29:16.368933 Vddq = 0
6066 09:29:16.371027 Vmddr = 0
6067 09:29:16.374314 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6068 09:29:16.380418 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6069 09:29:16.380839 MEM_TYPE=3, freq_sel=20
6070 09:29:16.384035 sv_algorithm_assistance_LP4_800
6071 09:29:16.390853 ============ PULL DRAM RESETB DOWN ============
6072 09:29:16.393851 ========== PULL DRAM RESETB DOWN end =========
6073 09:29:16.396955 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6074 09:29:16.400655 ===================================
6075 09:29:16.404090 LPDDR4 DRAM CONFIGURATION
6076 09:29:16.407644 ===================================
6077 09:29:16.410193 EX_ROW_EN[0] = 0x0
6078 09:29:16.410822 EX_ROW_EN[1] = 0x0
6079 09:29:16.413581 LP4Y_EN = 0x0
6080 09:29:16.414148 WORK_FSP = 0x0
6081 09:29:16.417147 WL = 0x2
6082 09:29:16.417629 RL = 0x2
6083 09:29:16.420378 BL = 0x2
6084 09:29:16.420801 RPST = 0x0
6085 09:29:16.423569 RD_PRE = 0x0
6086 09:29:16.424020 WR_PRE = 0x1
6087 09:29:16.426837 WR_PST = 0x0
6088 09:29:16.427307 DBI_WR = 0x0
6089 09:29:16.430172 DBI_RD = 0x0
6090 09:29:16.430595 OTF = 0x1
6091 09:29:16.433787 ===================================
6092 09:29:16.436943 ===================================
6093 09:29:16.439783 ANA top config
6094 09:29:16.443252 ===================================
6095 09:29:16.446800 DLL_ASYNC_EN = 0
6096 09:29:16.447222 ALL_SLAVE_EN = 1
6097 09:29:16.449742 NEW_RANK_MODE = 1
6098 09:29:16.453335 DLL_IDLE_MODE = 1
6099 09:29:16.456435 LP45_APHY_COMB_EN = 1
6100 09:29:16.456858 TX_ODT_DIS = 1
6101 09:29:16.460030 NEW_8X_MODE = 1
6102 09:29:16.462910 ===================================
6103 09:29:16.466715 ===================================
6104 09:29:16.469810 data_rate = 800
6105 09:29:16.472890 CKR = 1
6106 09:29:16.476028 DQ_P2S_RATIO = 4
6107 09:29:16.479761 ===================================
6108 09:29:16.482790 CA_P2S_RATIO = 4
6109 09:29:16.485845 DQ_CA_OPEN = 0
6110 09:29:16.486266 DQ_SEMI_OPEN = 1
6111 09:29:16.489368 CA_SEMI_OPEN = 1
6112 09:29:16.492428 CA_FULL_RATE = 0
6113 09:29:16.496180 DQ_CKDIV4_EN = 0
6114 09:29:16.499242 CA_CKDIV4_EN = 1
6115 09:29:16.502190 CA_PREDIV_EN = 0
6116 09:29:16.502613 PH8_DLY = 0
6117 09:29:16.505943 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6118 09:29:16.508870 DQ_AAMCK_DIV = 0
6119 09:29:16.512123 CA_AAMCK_DIV = 0
6120 09:29:16.515786 CA_ADMCK_DIV = 4
6121 09:29:16.519043 DQ_TRACK_CA_EN = 0
6122 09:29:16.521888 CA_PICK = 800
6123 09:29:16.522537 CA_MCKIO = 400
6124 09:29:16.525359 MCKIO_SEMI = 400
6125 09:29:16.528804 PLL_FREQ = 3016
6126 09:29:16.532130 DQ_UI_PI_RATIO = 32
6127 09:29:16.535434 CA_UI_PI_RATIO = 32
6128 09:29:16.538865 ===================================
6129 09:29:16.542095 ===================================
6130 09:29:16.545419 memory_type:LPDDR4
6131 09:29:16.545850 GP_NUM : 10
6132 09:29:16.548290 SRAM_EN : 1
6133 09:29:16.551631 MD32_EN : 0
6134 09:29:16.555246 ===================================
6135 09:29:16.555673 [ANA_INIT] >>>>>>>>>>>>>>
6136 09:29:16.558557 <<<<<< [CONFIGURE PHASE]: ANA_TX
6137 09:29:16.561688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6138 09:29:16.564736 ===================================
6139 09:29:16.568318 data_rate = 800,PCW = 0X7400
6140 09:29:16.571301 ===================================
6141 09:29:16.575086 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6142 09:29:16.581129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6143 09:29:16.591018 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6144 09:29:16.597677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6145 09:29:16.601242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6146 09:29:16.604261 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6147 09:29:16.604681 [ANA_INIT] flow start
6148 09:29:16.607383 [ANA_INIT] PLL >>>>>>>>
6149 09:29:16.610634 [ANA_INIT] PLL <<<<<<<<
6150 09:29:16.611057 [ANA_INIT] MIDPI >>>>>>>>
6151 09:29:16.614293 [ANA_INIT] MIDPI <<<<<<<<
6152 09:29:16.617359 [ANA_INIT] DLL >>>>>>>>
6153 09:29:16.617779 [ANA_INIT] flow end
6154 09:29:16.624012 ============ LP4 DIFF to SE enter ============
6155 09:29:16.627279 ============ LP4 DIFF to SE exit ============
6156 09:29:16.630721 [ANA_INIT] <<<<<<<<<<<<<
6157 09:29:16.633951 [Flow] Enable top DCM control >>>>>
6158 09:29:16.637282 [Flow] Enable top DCM control <<<<<
6159 09:29:16.640756 Enable DLL master slave shuffle
6160 09:29:16.643608 ==============================================================
6161 09:29:16.647167 Gating Mode config
6162 09:29:16.650183 ==============================================================
6163 09:29:16.653708 Config description:
6164 09:29:16.663625 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6165 09:29:16.669912 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6166 09:29:16.673404 SELPH_MODE 0: By rank 1: By Phase
6167 09:29:16.679933 ==============================================================
6168 09:29:16.683599 GAT_TRACK_EN = 0
6169 09:29:16.686726 RX_GATING_MODE = 2
6170 09:29:16.689772 RX_GATING_TRACK_MODE = 2
6171 09:29:16.692953 SELPH_MODE = 1
6172 09:29:16.696422 PICG_EARLY_EN = 1
6173 09:29:16.699468 VALID_LAT_VALUE = 1
6174 09:29:16.703177 ==============================================================
6175 09:29:16.706245 Enter into Gating configuration >>>>
6176 09:29:16.709204 Exit from Gating configuration <<<<
6177 09:29:16.712860 Enter into DVFS_PRE_config >>>>>
6178 09:29:16.725591 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6179 09:29:16.729397 Exit from DVFS_PRE_config <<<<<
6180 09:29:16.732761 Enter into PICG configuration >>>>
6181 09:29:16.733351 Exit from PICG configuration <<<<
6182 09:29:16.736124 [RX_INPUT] configuration >>>>>
6183 09:29:16.738960 [RX_INPUT] configuration <<<<<
6184 09:29:16.745900 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6185 09:29:16.748744 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6186 09:29:16.755183 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 09:29:16.762312 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 09:29:16.768402 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6189 09:29:16.775224 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6190 09:29:16.778811 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6191 09:29:16.781796 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6192 09:29:16.788501 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6193 09:29:16.791574 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6194 09:29:16.795320 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6195 09:29:16.798425 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6196 09:29:16.801436 ===================================
6197 09:29:16.804901 LPDDR4 DRAM CONFIGURATION
6198 09:29:16.808003 ===================================
6199 09:29:16.811897 EX_ROW_EN[0] = 0x0
6200 09:29:16.812317 EX_ROW_EN[1] = 0x0
6201 09:29:16.814977 LP4Y_EN = 0x0
6202 09:29:16.815390 WORK_FSP = 0x0
6203 09:29:16.818113 WL = 0x2
6204 09:29:16.821578 RL = 0x2
6205 09:29:16.822091 BL = 0x2
6206 09:29:16.824787 RPST = 0x0
6207 09:29:16.825200 RD_PRE = 0x0
6208 09:29:16.827977 WR_PRE = 0x1
6209 09:29:16.828497 WR_PST = 0x0
6210 09:29:16.831272 DBI_WR = 0x0
6211 09:29:16.831687 DBI_RD = 0x0
6212 09:29:16.834419 OTF = 0x1
6213 09:29:16.838239 ===================================
6214 09:29:16.841199 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6215 09:29:16.844584 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6216 09:29:16.851279 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6217 09:29:16.854398 ===================================
6218 09:29:16.854957 LPDDR4 DRAM CONFIGURATION
6219 09:29:16.857919 ===================================
6220 09:29:16.860838 EX_ROW_EN[0] = 0x10
6221 09:29:16.861338 EX_ROW_EN[1] = 0x0
6222 09:29:16.864019 LP4Y_EN = 0x0
6223 09:29:16.867057 WORK_FSP = 0x0
6224 09:29:16.867512 WL = 0x2
6225 09:29:16.870570 RL = 0x2
6226 09:29:16.870988 BL = 0x2
6227 09:29:16.873833 RPST = 0x0
6228 09:29:16.874252 RD_PRE = 0x0
6229 09:29:16.877371 WR_PRE = 0x1
6230 09:29:16.877797 WR_PST = 0x0
6231 09:29:16.880605 DBI_WR = 0x0
6232 09:29:16.881027 DBI_RD = 0x0
6233 09:29:16.883441 OTF = 0x1
6234 09:29:16.887363 ===================================
6235 09:29:16.893610 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6236 09:29:16.896718 nWR fixed to 30
6237 09:29:16.897137 [ModeRegInit_LP4] CH0 RK0
6238 09:29:16.900429 [ModeRegInit_LP4] CH0 RK1
6239 09:29:16.903455 [ModeRegInit_LP4] CH1 RK0
6240 09:29:16.907005 [ModeRegInit_LP4] CH1 RK1
6241 09:29:16.907481 match AC timing 19
6242 09:29:16.913115 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6243 09:29:16.916938 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6244 09:29:16.919938 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6245 09:29:16.926682 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6246 09:29:16.929690 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6247 09:29:16.930109 ==
6248 09:29:16.933236 Dram Type= 6, Freq= 0, CH_0, rank 0
6249 09:29:16.936339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 09:29:16.936758 ==
6251 09:29:16.943163 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 09:29:16.949350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6253 09:29:16.953488 [CA 0] Center 36 (8~64) winsize 57
6254 09:29:16.956084 [CA 1] Center 36 (8~64) winsize 57
6255 09:29:16.959496 [CA 2] Center 36 (8~64) winsize 57
6256 09:29:16.959976 [CA 3] Center 36 (8~64) winsize 57
6257 09:29:16.962637 [CA 4] Center 36 (8~64) winsize 57
6258 09:29:16.966451 [CA 5] Center 36 (8~64) winsize 57
6259 09:29:16.966868
6260 09:29:16.972967 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6261 09:29:16.973529
6262 09:29:16.976132 [CATrainingPosCal] consider 1 rank data
6263 09:29:16.979378 u2DelayCellTimex100 = 270/100 ps
6264 09:29:16.982353 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 09:29:16.985888 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 09:29:16.989373 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 09:29:16.992718 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 09:29:16.995948 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 09:29:16.998768 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 09:29:16.999187
6271 09:29:17.002461 CA PerBit enable=1, Macro0, CA PI delay=36
6272 09:29:17.002896
6273 09:29:17.005442 [CBTSetCACLKResult] CA Dly = 36
6274 09:29:17.009024 CS Dly: 1 (0~32)
6275 09:29:17.009548 ==
6276 09:29:17.012184 Dram Type= 6, Freq= 0, CH_0, rank 1
6277 09:29:17.015277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 09:29:17.015697 ==
6279 09:29:17.022133 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6280 09:29:17.028872 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6281 09:29:17.031994 [CA 0] Center 36 (8~64) winsize 57
6282 09:29:17.032414 [CA 1] Center 36 (8~64) winsize 57
6283 09:29:17.035788 [CA 2] Center 36 (8~64) winsize 57
6284 09:29:17.038600 [CA 3] Center 36 (8~64) winsize 57
6285 09:29:17.041702 [CA 4] Center 36 (8~64) winsize 57
6286 09:29:17.045447 [CA 5] Center 36 (8~64) winsize 57
6287 09:29:17.045868
6288 09:29:17.048512 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6289 09:29:17.048940
6290 09:29:17.055206 [CATrainingPosCal] consider 2 rank data
6291 09:29:17.055628 u2DelayCellTimex100 = 270/100 ps
6292 09:29:17.061467 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 09:29:17.065049 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 09:29:17.068581 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 09:29:17.071444 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 09:29:17.074598 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 09:29:17.078235 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 09:29:17.078657
6299 09:29:17.081832 CA PerBit enable=1, Macro0, CA PI delay=36
6300 09:29:17.082347
6301 09:29:17.084588 [CBTSetCACLKResult] CA Dly = 36
6302 09:29:17.088641 CS Dly: 1 (0~32)
6303 09:29:17.089159
6304 09:29:17.091601 ----->DramcWriteLeveling(PI) begin...
6305 09:29:17.092029 ==
6306 09:29:17.094434 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 09:29:17.097792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 09:29:17.098236 ==
6309 09:29:17.101037 Write leveling (Byte 0): 40 => 8
6310 09:29:17.104565 Write leveling (Byte 1): 40 => 8
6311 09:29:17.107798 DramcWriteLeveling(PI) end<-----
6312 09:29:17.108222
6313 09:29:17.108555 ==
6314 09:29:17.110794 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 09:29:17.114332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 09:29:17.114754 ==
6317 09:29:17.117711 [Gating] SW mode calibration
6318 09:29:17.124332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6319 09:29:17.130513 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6320 09:29:17.133810 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6321 09:29:17.140548 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6322 09:29:17.143986 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 09:29:17.147007 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 09:29:17.154025 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 09:29:17.157248 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 09:29:17.160227 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 09:29:17.167100 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 09:29:17.170199 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 09:29:17.173624 Total UI for P1: 0, mck2ui 16
6330 09:29:17.176635 best dqsien dly found for B0: ( 0, 14, 24)
6331 09:29:17.180325 Total UI for P1: 0, mck2ui 16
6332 09:29:17.183605 best dqsien dly found for B1: ( 0, 14, 24)
6333 09:29:17.186781 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6334 09:29:17.189748 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6335 09:29:17.190251
6336 09:29:17.193332 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6337 09:29:17.196451 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6338 09:29:17.199590 [Gating] SW calibration Done
6339 09:29:17.200008 ==
6340 09:29:17.203200 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 09:29:17.206190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 09:29:17.209332 ==
6343 09:29:17.209784 RX Vref Scan: 0
6344 09:29:17.210152
6345 09:29:17.212902 RX Vref 0 -> 0, step: 1
6346 09:29:17.213357
6347 09:29:17.215879 RX Delay -410 -> 252, step: 16
6348 09:29:17.219382 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6349 09:29:17.222863 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6350 09:29:17.226147 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6351 09:29:17.232614 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6352 09:29:17.235822 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6353 09:29:17.239422 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6354 09:29:17.242481 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6355 09:29:17.249075 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6356 09:29:17.252175 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6357 09:29:17.255775 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6358 09:29:17.262296 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6359 09:29:17.265355 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6360 09:29:17.269173 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6361 09:29:17.272239 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6362 09:29:17.278886 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6363 09:29:17.282209 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6364 09:29:17.282655 ==
6365 09:29:17.285359 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 09:29:17.288491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 09:29:17.288907 ==
6368 09:29:17.292451 DQS Delay:
6369 09:29:17.293001 DQS0 = 35, DQS1 = 59
6370 09:29:17.295260 DQM Delay:
6371 09:29:17.295673 DQM0 = 4, DQM1 = 17
6372 09:29:17.296010 DQ Delay:
6373 09:29:17.298486 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6374 09:29:17.301647 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6375 09:29:17.305459 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6376 09:29:17.308288 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6377 09:29:17.308700
6378 09:29:17.309025
6379 09:29:17.309373 ==
6380 09:29:17.312019 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 09:29:17.318470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 09:29:17.318886 ==
6383 09:29:17.319209
6384 09:29:17.319562
6385 09:29:17.319854 TX Vref Scan disable
6386 09:29:17.321308 == TX Byte 0 ==
6387 09:29:17.324810 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 09:29:17.327730 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 09:29:17.331132 == TX Byte 1 ==
6390 09:29:17.334567 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6391 09:29:17.337708 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6392 09:29:17.341354 ==
6393 09:29:17.344188 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 09:29:17.347374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 09:29:17.347794 ==
6396 09:29:17.348121
6397 09:29:17.348420
6398 09:29:17.350691 TX Vref Scan disable
6399 09:29:17.351100 == TX Byte 0 ==
6400 09:29:17.353857 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 09:29:17.360783 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 09:29:17.361254 == TX Byte 1 ==
6403 09:29:17.363924 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6404 09:29:17.370759 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6405 09:29:17.371177
6406 09:29:17.371497 [DATLAT]
6407 09:29:17.371811 Freq=400, CH0 RK0
6408 09:29:17.372105
6409 09:29:17.374005 DATLAT Default: 0xf
6410 09:29:17.376821 0, 0xFFFF, sum = 0
6411 09:29:17.377461 1, 0xFFFF, sum = 0
6412 09:29:17.380598 2, 0xFFFF, sum = 0
6413 09:29:17.381176 3, 0xFFFF, sum = 0
6414 09:29:17.383772 4, 0xFFFF, sum = 0
6415 09:29:17.384195 5, 0xFFFF, sum = 0
6416 09:29:17.387036 6, 0xFFFF, sum = 0
6417 09:29:17.387456 7, 0xFFFF, sum = 0
6418 09:29:17.390180 8, 0xFFFF, sum = 0
6419 09:29:17.390600 9, 0xFFFF, sum = 0
6420 09:29:17.393956 10, 0xFFFF, sum = 0
6421 09:29:17.394417 11, 0xFFFF, sum = 0
6422 09:29:17.396971 12, 0xFFFF, sum = 0
6423 09:29:17.397422 13, 0x0, sum = 1
6424 09:29:17.400614 14, 0x0, sum = 2
6425 09:29:17.401131 15, 0x0, sum = 3
6426 09:29:17.403733 16, 0x0, sum = 4
6427 09:29:17.404156 best_step = 14
6428 09:29:17.404483
6429 09:29:17.404786 ==
6430 09:29:17.406843 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 09:29:17.413599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 09:29:17.414028 ==
6433 09:29:17.414355 RX Vref Scan: 1
6434 09:29:17.414664
6435 09:29:17.417395 RX Vref 0 -> 0, step: 1
6436 09:29:17.417811
6437 09:29:17.420504 RX Delay -359 -> 252, step: 8
6438 09:29:17.420918
6439 09:29:17.423369 Set Vref, RX VrefLevel [Byte0]: 58
6440 09:29:17.426668 [Byte1]: 49
6441 09:29:17.427084
6442 09:29:17.430111 Final RX Vref Byte 0 = 58 to rank0
6443 09:29:17.433349 Final RX Vref Byte 1 = 49 to rank0
6444 09:29:17.436532 Final RX Vref Byte 0 = 58 to rank1
6445 09:29:17.439648 Final RX Vref Byte 1 = 49 to rank1==
6446 09:29:17.443365 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 09:29:17.449933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 09:29:17.450352 ==
6449 09:29:17.450676 DQS Delay:
6450 09:29:17.453005 DQS0 = 44, DQS1 = 56
6451 09:29:17.453464 DQM Delay:
6452 09:29:17.453793 DQM0 = 10, DQM1 = 14
6453 09:29:17.456536 DQ Delay:
6454 09:29:17.459431 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6455 09:29:17.463039 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6456 09:29:17.463555 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6457 09:29:17.466390 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6458 09:29:17.469735
6459 09:29:17.470150
6460 09:29:17.475939 [DQSOSCAuto] RK0, (LSB)MR18= 0x9a8d, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6461 09:29:17.479707 CH0 RK0: MR19=C0C, MR18=9A8D
6462 09:29:17.486290 CH0_RK0: MR19=0xC0C, MR18=0x9A8D, DQSOSC=390, MR23=63, INC=388, DEC=258
6463 09:29:17.486715 ==
6464 09:29:17.489331 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 09:29:17.492910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 09:29:17.493597 ==
6467 09:29:17.495761 [Gating] SW mode calibration
6468 09:29:17.502700 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6469 09:29:17.509117 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6470 09:29:17.512189 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6471 09:29:17.515652 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6472 09:29:17.522167 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 09:29:17.525099 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 09:29:17.529006 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 09:29:17.535125 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 09:29:17.538759 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 09:29:17.541890 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 09:29:17.548331 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 09:29:17.551333 Total UI for P1: 0, mck2ui 16
6480 09:29:17.554704 best dqsien dly found for B0: ( 0, 14, 24)
6481 09:29:17.558375 Total UI for P1: 0, mck2ui 16
6482 09:29:17.562080 best dqsien dly found for B1: ( 0, 14, 24)
6483 09:29:17.564475 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6484 09:29:17.568101 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6485 09:29:17.568520
6486 09:29:17.570979 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6487 09:29:17.574366 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6488 09:29:17.577629 [Gating] SW calibration Done
6489 09:29:17.578046 ==
6490 09:29:17.581013 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 09:29:17.584813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 09:29:17.585368 ==
6493 09:29:17.587867 RX Vref Scan: 0
6494 09:29:17.588283
6495 09:29:17.591070 RX Vref 0 -> 0, step: 1
6496 09:29:17.591486
6497 09:29:17.591810 RX Delay -410 -> 252, step: 16
6498 09:29:17.598333 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6499 09:29:17.601179 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6500 09:29:17.604688 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6501 09:29:17.611499 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6502 09:29:17.615153 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6503 09:29:17.618019 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6504 09:29:17.620887 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6505 09:29:17.627766 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6506 09:29:17.630653 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6507 09:29:17.633796 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6508 09:29:17.637746 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6509 09:29:17.643817 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6510 09:29:17.647367 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6511 09:29:17.650434 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6512 09:29:17.657234 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6513 09:29:17.660349 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6514 09:29:17.660846 ==
6515 09:29:17.663677 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 09:29:17.666971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 09:29:17.667452 ==
6518 09:29:17.670299 DQS Delay:
6519 09:29:17.670731 DQS0 = 35, DQS1 = 59
6520 09:29:17.671059 DQM Delay:
6521 09:29:17.673087 DQM0 = 5, DQM1 = 17
6522 09:29:17.673654 DQ Delay:
6523 09:29:17.676893 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6524 09:29:17.680073 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6525 09:29:17.683522 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6526 09:29:17.686531 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6527 09:29:17.686950
6528 09:29:17.687278
6529 09:29:17.687637 ==
6530 09:29:17.689945 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 09:29:17.693324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 09:29:17.696373 ==
6533 09:29:17.696791
6534 09:29:17.697336
6535 09:29:17.697665 TX Vref Scan disable
6536 09:29:17.699441 == TX Byte 0 ==
6537 09:29:17.703225 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6538 09:29:17.706250 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6539 09:29:17.709470 == TX Byte 1 ==
6540 09:29:17.713137 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6541 09:29:17.716361 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6542 09:29:17.716841 ==
6543 09:29:17.719745 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 09:29:17.725840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 09:29:17.726262 ==
6546 09:29:17.726586
6547 09:29:17.726889
6548 09:29:17.727180 TX Vref Scan disable
6549 09:29:17.729768 == TX Byte 0 ==
6550 09:29:17.732806 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6551 09:29:17.735969 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6552 09:29:17.738888 == TX Byte 1 ==
6553 09:29:17.742754 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6554 09:29:17.745848 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6555 09:29:17.746526
6556 09:29:17.749022 [DATLAT]
6557 09:29:17.749538 Freq=400, CH0 RK1
6558 09:29:17.750019
6559 09:29:17.752106 DATLAT Default: 0xe
6560 09:29:17.752653 0, 0xFFFF, sum = 0
6561 09:29:17.755678 1, 0xFFFF, sum = 0
6562 09:29:17.756153 2, 0xFFFF, sum = 0
6563 09:29:17.759304 3, 0xFFFF, sum = 0
6564 09:29:17.759729 4, 0xFFFF, sum = 0
6565 09:29:17.762420 5, 0xFFFF, sum = 0
6566 09:29:17.762842 6, 0xFFFF, sum = 0
6567 09:29:17.765529 7, 0xFFFF, sum = 0
6568 09:29:17.765954 8, 0xFFFF, sum = 0
6569 09:29:17.769328 9, 0xFFFF, sum = 0
6570 09:29:17.772395 10, 0xFFFF, sum = 0
6571 09:29:17.772839 11, 0xFFFF, sum = 0
6572 09:29:17.775622 12, 0xFFFF, sum = 0
6573 09:29:17.776046 13, 0x0, sum = 1
6574 09:29:17.778861 14, 0x0, sum = 2
6575 09:29:17.779286 15, 0x0, sum = 3
6576 09:29:17.782072 16, 0x0, sum = 4
6577 09:29:17.782492 best_step = 14
6578 09:29:17.782825
6579 09:29:17.783129 ==
6580 09:29:17.785697 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 09:29:17.788820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 09:29:17.789248 ==
6583 09:29:17.792085 RX Vref Scan: 0
6584 09:29:17.792498
6585 09:29:17.795506 RX Vref 0 -> 0, step: 1
6586 09:29:17.795938
6587 09:29:17.796267 RX Delay -359 -> 252, step: 8
6588 09:29:17.803789 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6589 09:29:17.807433 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6590 09:29:17.810332 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6591 09:29:17.817362 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6592 09:29:17.820321 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6593 09:29:17.823958 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6594 09:29:17.827065 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6595 09:29:17.833922 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6596 09:29:17.836962 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6597 09:29:17.840170 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6598 09:29:17.843896 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6599 09:29:17.849990 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6600 09:29:17.853561 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6601 09:29:17.856633 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6602 09:29:17.860349 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6603 09:29:17.866417 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6604 09:29:17.866891 ==
6605 09:29:17.869933 Dram Type= 6, Freq= 0, CH_0, rank 1
6606 09:29:17.873355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 09:29:17.873775 ==
6608 09:29:17.874103 DQS Delay:
6609 09:29:17.876456 DQS0 = 40, DQS1 = 60
6610 09:29:17.876877 DQM Delay:
6611 09:29:17.879702 DQM0 = 6, DQM1 = 14
6612 09:29:17.880192 DQ Delay:
6613 09:29:17.883239 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =0
6614 09:29:17.886194 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6615 09:29:17.889635 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6616 09:29:17.892694 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6617 09:29:17.893112
6618 09:29:17.893490
6619 09:29:17.899309 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e89, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6620 09:29:17.902757 CH0 RK1: MR19=C0C, MR18=8E89
6621 09:29:17.909318 CH0_RK1: MR19=0xC0C, MR18=0x8E89, DQSOSC=392, MR23=63, INC=384, DEC=256
6622 09:29:17.912562 [RxdqsGatingPostProcess] freq 400
6623 09:29:17.919451 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6624 09:29:17.922281 best DQS0 dly(2T, 0.5T) = (0, 10)
6625 09:29:17.925647 best DQS1 dly(2T, 0.5T) = (0, 10)
6626 09:29:17.928677 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6627 09:29:17.932709 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6628 09:29:17.935572 best DQS0 dly(2T, 0.5T) = (0, 10)
6629 09:29:17.936057 best DQS1 dly(2T, 0.5T) = (0, 10)
6630 09:29:17.939024 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6631 09:29:17.942122 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6632 09:29:17.945782 Pre-setting of DQS Precalculation
6633 09:29:17.952085 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6634 09:29:17.952502 ==
6635 09:29:17.956018 Dram Type= 6, Freq= 0, CH_1, rank 0
6636 09:29:17.958997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 09:29:17.959420 ==
6638 09:29:17.966022 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 09:29:17.972094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6640 09:29:17.975672 [CA 0] Center 36 (8~64) winsize 57
6641 09:29:17.978684 [CA 1] Center 36 (8~64) winsize 57
6642 09:29:17.979123 [CA 2] Center 36 (8~64) winsize 57
6643 09:29:17.981668 [CA 3] Center 36 (8~64) winsize 57
6644 09:29:17.985492 [CA 4] Center 36 (8~64) winsize 57
6645 09:29:17.988765 [CA 5] Center 36 (8~64) winsize 57
6646 09:29:17.989182
6647 09:29:17.995245 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6648 09:29:17.995814
6649 09:29:17.998751 [CATrainingPosCal] consider 1 rank data
6650 09:29:18.001817 u2DelayCellTimex100 = 270/100 ps
6651 09:29:18.004903 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 09:29:18.008129 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 09:29:18.011514 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 09:29:18.015001 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 09:29:18.018352 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 09:29:18.021044 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 09:29:18.021516
6658 09:29:18.024590 CA PerBit enable=1, Macro0, CA PI delay=36
6659 09:29:18.025138
6660 09:29:18.028264 [CBTSetCACLKResult] CA Dly = 36
6661 09:29:18.031338 CS Dly: 1 (0~32)
6662 09:29:18.031759 ==
6663 09:29:18.034944 Dram Type= 6, Freq= 0, CH_1, rank 1
6664 09:29:18.038360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 09:29:18.038782 ==
6666 09:29:18.044455 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6667 09:29:18.051223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6668 09:29:18.054152 [CA 0] Center 36 (8~64) winsize 57
6669 09:29:18.054696 [CA 1] Center 36 (8~64) winsize 57
6670 09:29:18.057549 [CA 2] Center 36 (8~64) winsize 57
6671 09:29:18.060812 [CA 3] Center 36 (8~64) winsize 57
6672 09:29:18.064541 [CA 4] Center 36 (8~64) winsize 57
6673 09:29:18.067484 [CA 5] Center 36 (8~64) winsize 57
6674 09:29:18.067890
6675 09:29:18.070678 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6676 09:29:18.071118
6677 09:29:18.077730 [CATrainingPosCal] consider 2 rank data
6678 09:29:18.078146 u2DelayCellTimex100 = 270/100 ps
6679 09:29:18.081196 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 09:29:18.087825 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 09:29:18.091188 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 09:29:18.093896 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 09:29:18.097789 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 09:29:18.100786 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 09:29:18.101203
6686 09:29:18.104152 CA PerBit enable=1, Macro0, CA PI delay=36
6687 09:29:18.104572
6688 09:29:18.107111 [CBTSetCACLKResult] CA Dly = 36
6689 09:29:18.110898 CS Dly: 1 (0~32)
6690 09:29:18.111314
6691 09:29:18.113748 ----->DramcWriteLeveling(PI) begin...
6692 09:29:18.114171 ==
6693 09:29:18.117405 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 09:29:18.120521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 09:29:18.120943 ==
6696 09:29:18.123699 Write leveling (Byte 0): 40 => 8
6697 09:29:18.127014 Write leveling (Byte 1): 40 => 8
6698 09:29:18.130759 DramcWriteLeveling(PI) end<-----
6699 09:29:18.131204
6700 09:29:18.131535 ==
6701 09:29:18.133686 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 09:29:18.136792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 09:29:18.137213 ==
6704 09:29:18.140551 [Gating] SW mode calibration
6705 09:29:18.146862 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6706 09:29:18.153091 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6707 09:29:18.156663 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6708 09:29:18.160264 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6709 09:29:18.166459 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 09:29:18.169947 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 09:29:18.173069 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 09:29:18.179851 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 09:29:18.183158 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 09:29:18.186346 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 09:29:18.192998 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 09:29:18.196528 Total UI for P1: 0, mck2ui 16
6717 09:29:18.199667 best dqsien dly found for B0: ( 0, 14, 24)
6718 09:29:18.202686 Total UI for P1: 0, mck2ui 16
6719 09:29:18.206252 best dqsien dly found for B1: ( 0, 14, 24)
6720 09:29:18.209245 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6721 09:29:18.212658 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6722 09:29:18.213081
6723 09:29:18.215663 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6724 09:29:18.219487 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6725 09:29:18.222445 [Gating] SW calibration Done
6726 09:29:18.222863 ==
6727 09:29:18.225742 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 09:29:18.228836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 09:29:18.229366 ==
6730 09:29:18.232425 RX Vref Scan: 0
6731 09:29:18.232937
6732 09:29:18.235519 RX Vref 0 -> 0, step: 1
6733 09:29:18.236009
6734 09:29:18.238863 RX Delay -410 -> 252, step: 16
6735 09:29:18.242222 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6736 09:29:18.245634 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6737 09:29:18.249196 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6738 09:29:18.255304 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6739 09:29:18.258473 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6740 09:29:18.261788 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6741 09:29:18.265412 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6742 09:29:18.272222 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6743 09:29:18.274949 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6744 09:29:18.278257 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6745 09:29:18.281423 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6746 09:29:18.288611 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6747 09:29:18.291305 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6748 09:29:18.294503 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6749 09:29:18.301436 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6750 09:29:18.304657 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6751 09:29:18.305188 ==
6752 09:29:18.308034 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 09:29:18.311535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 09:29:18.311954 ==
6755 09:29:18.314205 DQS Delay:
6756 09:29:18.314623 DQS0 = 35, DQS1 = 51
6757 09:29:18.317733 DQM Delay:
6758 09:29:18.318146 DQM0 = 6, DQM1 = 13
6759 09:29:18.318470 DQ Delay:
6760 09:29:18.320866 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6761 09:29:18.324324 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6762 09:29:18.327372 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6763 09:29:18.331229 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6764 09:29:18.331642
6765 09:29:18.331962
6766 09:29:18.332261 ==
6767 09:29:18.334297 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 09:29:18.341313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 09:29:18.341805 ==
6770 09:29:18.342198
6771 09:29:18.342507
6772 09:29:18.342796 TX Vref Scan disable
6773 09:29:18.344281 == TX Byte 0 ==
6774 09:29:18.347266 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 09:29:18.350607 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 09:29:18.354105 == TX Byte 1 ==
6777 09:29:18.357217 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6778 09:29:18.360735 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6779 09:29:18.361148 ==
6780 09:29:18.364194 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 09:29:18.370010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 09:29:18.370466 ==
6783 09:29:18.370797
6784 09:29:18.371101
6785 09:29:18.371391 TX Vref Scan disable
6786 09:29:18.373895 == TX Byte 0 ==
6787 09:29:18.376859 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 09:29:18.380781 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 09:29:18.384052 == TX Byte 1 ==
6790 09:29:18.386773 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6791 09:29:18.390127 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6792 09:29:18.393702
6793 09:29:18.394227 [DATLAT]
6794 09:29:18.394559 Freq=400, CH1 RK0
6795 09:29:18.394959
6796 09:29:18.396468 DATLAT Default: 0xf
6797 09:29:18.396879 0, 0xFFFF, sum = 0
6798 09:29:18.400073 1, 0xFFFF, sum = 0
6799 09:29:18.400521 2, 0xFFFF, sum = 0
6800 09:29:18.403579 3, 0xFFFF, sum = 0
6801 09:29:18.406527 4, 0xFFFF, sum = 0
6802 09:29:18.407067 5, 0xFFFF, sum = 0
6803 09:29:18.409969 6, 0xFFFF, sum = 0
6804 09:29:18.410401 7, 0xFFFF, sum = 0
6805 09:29:18.413230 8, 0xFFFF, sum = 0
6806 09:29:18.413728 9, 0xFFFF, sum = 0
6807 09:29:18.416454 10, 0xFFFF, sum = 0
6808 09:29:18.416871 11, 0xFFFF, sum = 0
6809 09:29:18.419931 12, 0xFFFF, sum = 0
6810 09:29:18.420359 13, 0x0, sum = 1
6811 09:29:18.423294 14, 0x0, sum = 2
6812 09:29:18.423713 15, 0x0, sum = 3
6813 09:29:18.426737 16, 0x0, sum = 4
6814 09:29:18.427184 best_step = 14
6815 09:29:18.427508
6816 09:29:18.427808 ==
6817 09:29:18.429788 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 09:29:18.433397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 09:29:18.436849 ==
6820 09:29:18.437431 RX Vref Scan: 1
6821 09:29:18.437773
6822 09:29:18.439685 RX Vref 0 -> 0, step: 1
6823 09:29:18.440098
6824 09:29:18.442903 RX Delay -343 -> 252, step: 8
6825 09:29:18.443400
6826 09:29:18.446469 Set Vref, RX VrefLevel [Byte0]: 50
6827 09:29:18.449457 [Byte1]: 53
6828 09:29:18.449871
6829 09:29:18.452811 Final RX Vref Byte 0 = 50 to rank0
6830 09:29:18.456580 Final RX Vref Byte 1 = 53 to rank0
6831 09:29:18.459395 Final RX Vref Byte 0 = 50 to rank1
6832 09:29:18.462761 Final RX Vref Byte 1 = 53 to rank1==
6833 09:29:18.466057 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 09:29:18.469416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 09:29:18.469845 ==
6836 09:29:18.472604 DQS Delay:
6837 09:29:18.473023 DQS0 = 44, DQS1 = 52
6838 09:29:18.475490 DQM Delay:
6839 09:29:18.475911 DQM0 = 11, DQM1 = 10
6840 09:29:18.479355 DQ Delay:
6841 09:29:18.479776 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6842 09:29:18.482455 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6843 09:29:18.485937 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6844 09:29:18.489114 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =16
6845 09:29:18.489568
6846 09:29:18.489898
6847 09:29:18.498750 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d94, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6848 09:29:18.502411 CH1 RK0: MR19=C0C, MR18=6D94
6849 09:29:18.505597 CH1_RK0: MR19=0xC0C, MR18=0x6D94, DQSOSC=391, MR23=63, INC=386, DEC=257
6850 09:29:18.509241 ==
6851 09:29:18.512379 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 09:29:18.515348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 09:29:18.515804 ==
6854 09:29:18.518959 [Gating] SW mode calibration
6855 09:29:18.525227 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6856 09:29:18.528781 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6857 09:29:18.535921 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6858 09:29:18.538552 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6859 09:29:18.541735 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 09:29:18.548359 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 09:29:18.552246 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 09:29:18.555259 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 09:29:18.562024 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 09:29:18.565067 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 09:29:18.568167 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 09:29:18.571758 Total UI for P1: 0, mck2ui 16
6867 09:29:18.575146 best dqsien dly found for B0: ( 0, 14, 24)
6868 09:29:18.577816 Total UI for P1: 0, mck2ui 16
6869 09:29:18.581365 best dqsien dly found for B1: ( 0, 14, 24)
6870 09:29:18.584690 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6871 09:29:18.591420 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6872 09:29:18.591839
6873 09:29:18.594581 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6874 09:29:18.597612 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6875 09:29:18.601101 [Gating] SW calibration Done
6876 09:29:18.601575 ==
6877 09:29:18.604264 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 09:29:18.607814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 09:29:18.608235 ==
6880 09:29:18.610946 RX Vref Scan: 0
6881 09:29:18.611366
6882 09:29:18.611697 RX Vref 0 -> 0, step: 1
6883 09:29:18.612007
6884 09:29:18.614024 RX Delay -410 -> 252, step: 16
6885 09:29:18.620883 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6886 09:29:18.624116 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6887 09:29:18.627293 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6888 09:29:18.631014 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6889 09:29:18.637110 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6890 09:29:18.640938 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6891 09:29:18.644225 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6892 09:29:18.646772 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6893 09:29:18.653679 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6894 09:29:18.656815 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6895 09:29:18.660268 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6896 09:29:18.663524 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6897 09:29:18.670558 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6898 09:29:18.673388 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6899 09:29:18.677156 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6900 09:29:18.683605 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6901 09:29:18.684080 ==
6902 09:29:18.686490 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 09:29:18.689948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 09:29:18.690370 ==
6905 09:29:18.690699 DQS Delay:
6906 09:29:18.693419 DQS0 = 43, DQS1 = 51
6907 09:29:18.693832 DQM Delay:
6908 09:29:18.696639 DQM0 = 9, DQM1 = 13
6909 09:29:18.697055 DQ Delay:
6910 09:29:18.700222 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6911 09:29:18.703158 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6912 09:29:18.706168 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6913 09:29:18.710022 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6914 09:29:18.710511
6915 09:29:18.710839
6916 09:29:18.711141 ==
6917 09:29:18.713142 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 09:29:18.716276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 09:29:18.716718 ==
6920 09:29:18.717075
6921 09:29:18.717539
6922 09:29:18.719395 TX Vref Scan disable
6923 09:29:18.719808 == TX Byte 0 ==
6924 09:29:18.726358 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6925 09:29:18.729648 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6926 09:29:18.730061 == TX Byte 1 ==
6927 09:29:18.735753 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6928 09:29:18.738736 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6929 09:29:18.739168 ==
6930 09:29:18.742520 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 09:29:18.745647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 09:29:18.746196 ==
6933 09:29:18.746664
6934 09:29:18.747106
6935 09:29:18.749013 TX Vref Scan disable
6936 09:29:18.752334 == TX Byte 0 ==
6937 09:29:18.756037 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6938 09:29:18.758945 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6939 09:29:18.762015 == TX Byte 1 ==
6940 09:29:18.765375 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6941 09:29:18.768670 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6942 09:29:18.769087
6943 09:29:18.769468 [DATLAT]
6944 09:29:18.771997 Freq=400, CH1 RK1
6945 09:29:18.772414
6946 09:29:18.772735 DATLAT Default: 0xe
6947 09:29:18.775070 0, 0xFFFF, sum = 0
6948 09:29:18.778685 1, 0xFFFF, sum = 0
6949 09:29:18.779245 2, 0xFFFF, sum = 0
6950 09:29:18.782131 3, 0xFFFF, sum = 0
6951 09:29:18.782562 4, 0xFFFF, sum = 0
6952 09:29:18.784994 5, 0xFFFF, sum = 0
6953 09:29:18.785575 6, 0xFFFF, sum = 0
6954 09:29:18.788376 7, 0xFFFF, sum = 0
6955 09:29:18.788953 8, 0xFFFF, sum = 0
6956 09:29:18.791618 9, 0xFFFF, sum = 0
6957 09:29:18.792196 10, 0xFFFF, sum = 0
6958 09:29:18.795240 11, 0xFFFF, sum = 0
6959 09:29:18.795878 12, 0xFFFF, sum = 0
6960 09:29:18.798341 13, 0x0, sum = 1
6961 09:29:18.798996 14, 0x0, sum = 2
6962 09:29:18.801239 15, 0x0, sum = 3
6963 09:29:18.801843 16, 0x0, sum = 4
6964 09:29:18.804692 best_step = 14
6965 09:29:18.805294
6966 09:29:18.805710 ==
6967 09:29:18.807661 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 09:29:18.811546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 09:29:18.812126 ==
6970 09:29:18.814530 RX Vref Scan: 0
6971 09:29:18.814957
6972 09:29:18.815280 RX Vref 0 -> 0, step: 1
6973 09:29:18.815585
6974 09:29:18.817760 RX Delay -343 -> 252, step: 8
6975 09:29:18.825962 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6976 09:29:18.829430 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6977 09:29:18.832470 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6978 09:29:18.839335 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6979 09:29:18.842681 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6980 09:29:18.845853 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6981 09:29:18.849202 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6982 09:29:18.855708 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6983 09:29:18.858929 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6984 09:29:18.862024 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6985 09:29:18.865107 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6986 09:29:18.871969 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6987 09:29:18.875422 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6988 09:29:18.878848 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6989 09:29:18.882073 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6990 09:29:18.888437 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6991 09:29:18.888862 ==
6992 09:29:18.891752 Dram Type= 6, Freq= 0, CH_1, rank 1
6993 09:29:18.894914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6994 09:29:18.895337 ==
6995 09:29:18.898012 DQS Delay:
6996 09:29:18.898435 DQS0 = 48, DQS1 = 52
6997 09:29:18.898765 DQM Delay:
6998 09:29:18.901694 DQM0 = 12, DQM1 = 10
6999 09:29:18.902169 DQ Delay:
7000 09:29:18.904995 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
7001 09:29:18.908159 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
7002 09:29:18.911604 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7003 09:29:18.914515 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7004 09:29:18.914885
7005 09:29:18.915214
7006 09:29:18.924305 [DQSOSCAuto] RK1, (LSB)MR18= 0x77b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
7007 09:29:18.924739 CH1 RK1: MR19=C0C, MR18=77B0
7008 09:29:18.931115 CH1_RK1: MR19=0xC0C, MR18=0x77B0, DQSOSC=387, MR23=63, INC=394, DEC=262
7009 09:29:18.934148 [RxdqsGatingPostProcess] freq 400
7010 09:29:18.941125 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7011 09:29:18.944184 best DQS0 dly(2T, 0.5T) = (0, 10)
7012 09:29:18.947906 best DQS1 dly(2T, 0.5T) = (0, 10)
7013 09:29:18.950939 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7014 09:29:18.953926 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7015 09:29:18.957771 best DQS0 dly(2T, 0.5T) = (0, 10)
7016 09:29:18.960742 best DQS1 dly(2T, 0.5T) = (0, 10)
7017 09:29:18.964460 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7018 09:29:18.967873 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7019 09:29:18.970486 Pre-setting of DQS Precalculation
7020 09:29:18.973966 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7021 09:29:18.980643 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7022 09:29:18.987218 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7023 09:29:18.987799
7024 09:29:18.991053
7025 09:29:18.991589 [Calibration Summary] 800 Mbps
7026 09:29:18.993984 CH 0, Rank 0
7027 09:29:18.994407 SW Impedance : PASS
7028 09:29:18.996918 DUTY Scan : NO K
7029 09:29:19.000535 ZQ Calibration : PASS
7030 09:29:19.000958 Jitter Meter : NO K
7031 09:29:19.003893 CBT Training : PASS
7032 09:29:19.006843 Write leveling : PASS
7033 09:29:19.007265 RX DQS gating : PASS
7034 09:29:19.010129 RX DQ/DQS(RDDQC) : PASS
7035 09:29:19.013820 TX DQ/DQS : PASS
7036 09:29:19.014241 RX DATLAT : PASS
7037 09:29:19.017173 RX DQ/DQS(Engine): PASS
7038 09:29:19.020613 TX OE : NO K
7039 09:29:19.021036 All Pass.
7040 09:29:19.021415
7041 09:29:19.021734 CH 0, Rank 1
7042 09:29:19.023247 SW Impedance : PASS
7043 09:29:19.026940 DUTY Scan : NO K
7044 09:29:19.027360 ZQ Calibration : PASS
7045 09:29:19.029802 Jitter Meter : NO K
7046 09:29:19.033171 CBT Training : PASS
7047 09:29:19.033631 Write leveling : NO K
7048 09:29:19.036374 RX DQS gating : PASS
7049 09:29:19.039617 RX DQ/DQS(RDDQC) : PASS
7050 09:29:19.040036 TX DQ/DQS : PASS
7051 09:29:19.043241 RX DATLAT : PASS
7052 09:29:19.046667 RX DQ/DQS(Engine): PASS
7053 09:29:19.047087 TX OE : NO K
7054 09:29:19.047423 All Pass.
7055 09:29:19.049494
7056 09:29:19.049912 CH 1, Rank 0
7057 09:29:19.052773 SW Impedance : PASS
7058 09:29:19.053193 DUTY Scan : NO K
7059 09:29:19.056357 ZQ Calibration : PASS
7060 09:29:19.059357 Jitter Meter : NO K
7061 09:29:19.059777 CBT Training : PASS
7062 09:29:19.062730 Write leveling : PASS
7063 09:29:19.063151 RX DQS gating : PASS
7064 09:29:19.066683 RX DQ/DQS(RDDQC) : PASS
7065 09:29:19.069403 TX DQ/DQS : PASS
7066 09:29:19.069828 RX DATLAT : PASS
7067 09:29:19.072660 RX DQ/DQS(Engine): PASS
7068 09:29:19.075590 TX OE : NO K
7069 09:29:19.076012 All Pass.
7070 09:29:19.076345
7071 09:29:19.076657 CH 1, Rank 1
7072 09:29:19.079299 SW Impedance : PASS
7073 09:29:19.082342 DUTY Scan : NO K
7074 09:29:19.083007 ZQ Calibration : PASS
7075 09:29:19.085666 Jitter Meter : NO K
7076 09:29:19.089107 CBT Training : PASS
7077 09:29:19.089554 Write leveling : NO K
7078 09:29:19.092565 RX DQS gating : PASS
7079 09:29:19.095671 RX DQ/DQS(RDDQC) : PASS
7080 09:29:19.096089 TX DQ/DQS : PASS
7081 09:29:19.099320 RX DATLAT : PASS
7082 09:29:19.102738 RX DQ/DQS(Engine): PASS
7083 09:29:19.103159 TX OE : NO K
7084 09:29:19.105671 All Pass.
7085 09:29:19.106093
7086 09:29:19.106420 DramC Write-DBI off
7087 09:29:19.109068 PER_BANK_REFRESH: Hybrid Mode
7088 09:29:19.109540 TX_TRACKING: ON
7089 09:29:19.118622 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7090 09:29:19.122020 [FAST_K] Save calibration result to emmc
7091 09:29:19.125678 dramc_set_vcore_voltage set vcore to 725000
7092 09:29:19.128819 Read voltage for 1600, 0
7093 09:29:19.129365 Vio18 = 0
7094 09:29:19.132209 Vcore = 725000
7095 09:29:19.132639 Vdram = 0
7096 09:29:19.133069 Vddq = 0
7097 09:29:19.135206 Vmddr = 0
7098 09:29:19.138787 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7099 09:29:19.145705 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7100 09:29:19.146239 MEM_TYPE=3, freq_sel=13
7101 09:29:19.148565 sv_algorithm_assistance_LP4_3733
7102 09:29:19.154904 ============ PULL DRAM RESETB DOWN ============
7103 09:29:19.158903 ========== PULL DRAM RESETB DOWN end =========
7104 09:29:19.161659 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7105 09:29:19.165321 ===================================
7106 09:29:19.168422 LPDDR4 DRAM CONFIGURATION
7107 09:29:19.171736 ===================================
7108 09:29:19.174808 EX_ROW_EN[0] = 0x0
7109 09:29:19.175236 EX_ROW_EN[1] = 0x0
7110 09:29:19.177792 LP4Y_EN = 0x0
7111 09:29:19.178207 WORK_FSP = 0x1
7112 09:29:19.181427 WL = 0x5
7113 09:29:19.181848 RL = 0x5
7114 09:29:19.184395 BL = 0x2
7115 09:29:19.184812 RPST = 0x0
7116 09:29:19.187601 RD_PRE = 0x0
7117 09:29:19.188019 WR_PRE = 0x1
7118 09:29:19.191275 WR_PST = 0x1
7119 09:29:19.191691 DBI_WR = 0x0
7120 09:29:19.194204 DBI_RD = 0x0
7121 09:29:19.194623 OTF = 0x1
7122 09:29:19.197845 ===================================
7123 09:29:19.200727 ===================================
7124 09:29:19.204461 ANA top config
7125 09:29:19.207500 ===================================
7126 09:29:19.210643 DLL_ASYNC_EN = 0
7127 09:29:19.211059 ALL_SLAVE_EN = 0
7128 09:29:19.214281 NEW_RANK_MODE = 1
7129 09:29:19.217811 DLL_IDLE_MODE = 1
7130 09:29:19.220897 LP45_APHY_COMB_EN = 1
7131 09:29:19.223852 TX_ODT_DIS = 0
7132 09:29:19.224371 NEW_8X_MODE = 1
7133 09:29:19.227629 ===================================
7134 09:29:19.230682 ===================================
7135 09:29:19.234060 data_rate = 3200
7136 09:29:19.237935 CKR = 1
7137 09:29:19.240589 DQ_P2S_RATIO = 8
7138 09:29:19.244059 ===================================
7139 09:29:19.246897 CA_P2S_RATIO = 8
7140 09:29:19.250374 DQ_CA_OPEN = 0
7141 09:29:19.250802 DQ_SEMI_OPEN = 0
7142 09:29:19.254039 CA_SEMI_OPEN = 0
7143 09:29:19.257075 CA_FULL_RATE = 0
7144 09:29:19.260406 DQ_CKDIV4_EN = 0
7145 09:29:19.263722 CA_CKDIV4_EN = 0
7146 09:29:19.266771 CA_PREDIV_EN = 0
7147 09:29:19.267192 PH8_DLY = 12
7148 09:29:19.270423 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7149 09:29:19.273380 DQ_AAMCK_DIV = 4
7150 09:29:19.277026 CA_AAMCK_DIV = 4
7151 09:29:19.280483 CA_ADMCK_DIV = 4
7152 09:29:19.283559 DQ_TRACK_CA_EN = 0
7153 09:29:19.286691 CA_PICK = 1600
7154 09:29:19.287109 CA_MCKIO = 1600
7155 09:29:19.290354 MCKIO_SEMI = 0
7156 09:29:19.293368 PLL_FREQ = 3068
7157 09:29:19.296618 DQ_UI_PI_RATIO = 32
7158 09:29:19.299733 CA_UI_PI_RATIO = 0
7159 09:29:19.303336 ===================================
7160 09:29:19.306812 ===================================
7161 09:29:19.309866 memory_type:LPDDR4
7162 09:29:19.310282 GP_NUM : 10
7163 09:29:19.312892 SRAM_EN : 1
7164 09:29:19.313469 MD32_EN : 0
7165 09:29:19.316587 ===================================
7166 09:29:19.319624 [ANA_INIT] >>>>>>>>>>>>>>
7167 09:29:19.323279 <<<<<< [CONFIGURE PHASE]: ANA_TX
7168 09:29:19.326347 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7169 09:29:19.329815 ===================================
7170 09:29:19.332787 data_rate = 3200,PCW = 0X7600
7171 09:29:19.336503 ===================================
7172 09:29:19.339586 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7173 09:29:19.346117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7174 09:29:19.349904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7175 09:29:19.355969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7176 09:29:19.359445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7177 09:29:19.362962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7178 09:29:19.363470 [ANA_INIT] flow start
7179 09:29:19.366022 [ANA_INIT] PLL >>>>>>>>
7180 09:29:19.369084 [ANA_INIT] PLL <<<<<<<<
7181 09:29:19.372715 [ANA_INIT] MIDPI >>>>>>>>
7182 09:29:19.373132 [ANA_INIT] MIDPI <<<<<<<<
7183 09:29:19.376069 [ANA_INIT] DLL >>>>>>>>
7184 09:29:19.379297 [ANA_INIT] DLL <<<<<<<<
7185 09:29:19.379713 [ANA_INIT] flow end
7186 09:29:19.382322 ============ LP4 DIFF to SE enter ============
7187 09:29:19.388694 ============ LP4 DIFF to SE exit ============
7188 09:29:19.389115 [ANA_INIT] <<<<<<<<<<<<<
7189 09:29:19.392581 [Flow] Enable top DCM control >>>>>
7190 09:29:19.395744 [Flow] Enable top DCM control <<<<<
7191 09:29:19.398891 Enable DLL master slave shuffle
7192 09:29:19.405597 ==============================================================
7193 09:29:19.408825 Gating Mode config
7194 09:29:19.412466 ==============================================================
7195 09:29:19.415528 Config description:
7196 09:29:19.424905 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7197 09:29:19.432172 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7198 09:29:19.435056 SELPH_MODE 0: By rank 1: By Phase
7199 09:29:19.441553 ==============================================================
7200 09:29:19.445200 GAT_TRACK_EN = 1
7201 09:29:19.448304 RX_GATING_MODE = 2
7202 09:29:19.451404 RX_GATING_TRACK_MODE = 2
7203 09:29:19.454942 SELPH_MODE = 1
7204 09:29:19.455430 PICG_EARLY_EN = 1
7205 09:29:19.458662 VALID_LAT_VALUE = 1
7206 09:29:19.464531 ==============================================================
7207 09:29:19.467869 Enter into Gating configuration >>>>
7208 09:29:19.471487 Exit from Gating configuration <<<<
7209 09:29:19.474994 Enter into DVFS_PRE_config >>>>>
7210 09:29:19.484016 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7211 09:29:19.487701 Exit from DVFS_PRE_config <<<<<
7212 09:29:19.490782 Enter into PICG configuration >>>>
7213 09:29:19.494172 Exit from PICG configuration <<<<
7214 09:29:19.497454 [RX_INPUT] configuration >>>>>
7215 09:29:19.500950 [RX_INPUT] configuration <<<<<
7216 09:29:19.507296 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7217 09:29:19.510919 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7218 09:29:19.517466 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 09:29:19.523978 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 09:29:19.530667 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7221 09:29:19.536872 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7222 09:29:19.540614 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7223 09:29:19.543624 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7224 09:29:19.546726 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7225 09:29:19.553719 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7226 09:29:19.556793 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7227 09:29:19.560528 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7228 09:29:19.563405 ===================================
7229 09:29:19.567000 LPDDR4 DRAM CONFIGURATION
7230 09:29:19.570400 ===================================
7231 09:29:19.573371 EX_ROW_EN[0] = 0x0
7232 09:29:19.573794 EX_ROW_EN[1] = 0x0
7233 09:29:19.576818 LP4Y_EN = 0x0
7234 09:29:19.577233 WORK_FSP = 0x1
7235 09:29:19.580245 WL = 0x5
7236 09:29:19.580715 RL = 0x5
7237 09:29:19.583445 BL = 0x2
7238 09:29:19.583862 RPST = 0x0
7239 09:29:19.586631 RD_PRE = 0x0
7240 09:29:19.587046 WR_PRE = 0x1
7241 09:29:19.589689 WR_PST = 0x1
7242 09:29:19.590107 DBI_WR = 0x0
7243 09:29:19.593464 DBI_RD = 0x0
7244 09:29:19.593878 OTF = 0x1
7245 09:29:19.596529 ===================================
7246 09:29:19.603233 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7247 09:29:19.606250 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7248 09:29:19.610145 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7249 09:29:19.612679 ===================================
7250 09:29:19.616708 LPDDR4 DRAM CONFIGURATION
7251 09:29:19.619278 ===================================
7252 09:29:19.622904 EX_ROW_EN[0] = 0x10
7253 09:29:19.623322 EX_ROW_EN[1] = 0x0
7254 09:29:19.625693 LP4Y_EN = 0x0
7255 09:29:19.626133 WORK_FSP = 0x1
7256 09:29:19.629230 WL = 0x5
7257 09:29:19.629683 RL = 0x5
7258 09:29:19.632843 BL = 0x2
7259 09:29:19.633289 RPST = 0x0
7260 09:29:19.635735 RD_PRE = 0x0
7261 09:29:19.636152 WR_PRE = 0x1
7262 09:29:19.639735 WR_PST = 0x1
7263 09:29:19.640152 DBI_WR = 0x0
7264 09:29:19.642496 DBI_RD = 0x0
7265 09:29:19.642913 OTF = 0x1
7266 09:29:19.646082 ===================================
7267 09:29:19.652087 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7268 09:29:19.652509 ==
7269 09:29:19.655957 Dram Type= 6, Freq= 0, CH_0, rank 0
7270 09:29:19.662127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7271 09:29:19.662613 ==
7272 09:29:19.662947 [Duty_Offset_Calibration]
7273 09:29:19.665826 B0:2 B1:0 CA:4
7274 09:29:19.666244
7275 09:29:19.668627 [DutyScan_Calibration_Flow] k_type=0
7276 09:29:19.677792
7277 09:29:19.678232 ==CLK 0==
7278 09:29:19.680592 Final CLK duty delay cell = -4
7279 09:29:19.684051 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7280 09:29:19.687469 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7281 09:29:19.690594 [-4] AVG Duty = 4937%(X100)
7282 09:29:19.691012
7283 09:29:19.693786 CH0 CLK Duty spec in!! Max-Min= 187%
7284 09:29:19.697319 [DutyScan_Calibration_Flow] ====Done====
7285 09:29:19.697739
7286 09:29:19.700509 [DutyScan_Calibration_Flow] k_type=1
7287 09:29:19.717965
7288 09:29:19.718445 ==DQS 0 ==
7289 09:29:19.720808 Final DQS duty delay cell = 0
7290 09:29:19.724566 [0] MAX Duty = 5218%(X100), DQS PI = 38
7291 09:29:19.727638 [0] MIN Duty = 5093%(X100), DQS PI = 6
7292 09:29:19.731270 [0] AVG Duty = 5155%(X100)
7293 09:29:19.731685
7294 09:29:19.732084 ==DQS 1 ==
7295 09:29:19.734028 Final DQS duty delay cell = 0
7296 09:29:19.737696 [0] MAX Duty = 5156%(X100), DQS PI = 0
7297 09:29:19.740870 [0] MIN Duty = 4938%(X100), DQS PI = 58
7298 09:29:19.744411 [0] AVG Duty = 5047%(X100)
7299 09:29:19.744826
7300 09:29:19.747722 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7301 09:29:19.748167
7302 09:29:19.751047 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7303 09:29:19.754184 [DutyScan_Calibration_Flow] ====Done====
7304 09:29:19.754632
7305 09:29:19.757206 [DutyScan_Calibration_Flow] k_type=3
7306 09:29:19.774888
7307 09:29:19.775369 ==DQM 0 ==
7308 09:29:19.777872 Final DQM duty delay cell = 0
7309 09:29:19.781407 [0] MAX Duty = 5124%(X100), DQS PI = 20
7310 09:29:19.784533 [0] MIN Duty = 4844%(X100), DQS PI = 54
7311 09:29:19.788007 [0] AVG Duty = 4984%(X100)
7312 09:29:19.788520
7313 09:29:19.788853 ==DQM 1 ==
7314 09:29:19.791464 Final DQM duty delay cell = 0
7315 09:29:19.794571 [0] MAX Duty = 4969%(X100), DQS PI = 2
7316 09:29:19.798116 [0] MIN Duty = 4844%(X100), DQS PI = 16
7317 09:29:19.801169 [0] AVG Duty = 4906%(X100)
7318 09:29:19.801745
7319 09:29:19.804228 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7320 09:29:19.804644
7321 09:29:19.807832 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7322 09:29:19.810916 [DutyScan_Calibration_Flow] ====Done====
7323 09:29:19.811334
7324 09:29:19.814064 [DutyScan_Calibration_Flow] k_type=2
7325 09:29:19.831780
7326 09:29:19.832194 ==DQ 0 ==
7327 09:29:19.835588 Final DQ duty delay cell = 0
7328 09:29:19.838710 [0] MAX Duty = 5124%(X100), DQS PI = 20
7329 09:29:19.841907 [0] MIN Duty = 4938%(X100), DQS PI = 12
7330 09:29:19.842327 [0] AVG Duty = 5031%(X100)
7331 09:29:19.844943
7332 09:29:19.845499 ==DQ 1 ==
7333 09:29:19.848793 Final DQ duty delay cell = 0
7334 09:29:19.852267 [0] MAX Duty = 5187%(X100), DQS PI = 2
7335 09:29:19.855461 [0] MIN Duty = 4907%(X100), DQS PI = 34
7336 09:29:19.855878 [0] AVG Duty = 5047%(X100)
7337 09:29:19.858070
7338 09:29:19.861853 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7339 09:29:19.862270
7340 09:29:19.864756 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7341 09:29:19.867853 [DutyScan_Calibration_Flow] ====Done====
7342 09:29:19.868274 ==
7343 09:29:19.871693 Dram Type= 6, Freq= 0, CH_1, rank 0
7344 09:29:19.874848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7345 09:29:19.875269 ==
7346 09:29:19.878284 [Duty_Offset_Calibration]
7347 09:29:19.878868 B0:0 B1:-1 CA:3
7348 09:29:19.879226
7349 09:29:19.881356 [DutyScan_Calibration_Flow] k_type=0
7350 09:29:19.891520
7351 09:29:19.891936 ==CLK 0==
7352 09:29:19.894655 Final CLK duty delay cell = -4
7353 09:29:19.898283 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7354 09:29:19.901128 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7355 09:29:19.904325 [-4] AVG Duty = 4906%(X100)
7356 09:29:19.904743
7357 09:29:19.908045 CH1 CLK Duty spec in!! Max-Min= 187%
7358 09:29:19.911120 [DutyScan_Calibration_Flow] ====Done====
7359 09:29:19.911537
7360 09:29:19.914210 [DutyScan_Calibration_Flow] k_type=1
7361 09:29:19.930249
7362 09:29:19.930675 ==DQS 0 ==
7363 09:29:19.934045 Final DQS duty delay cell = 0
7364 09:29:19.937015 [0] MAX Duty = 5250%(X100), DQS PI = 30
7365 09:29:19.940084 [0] MIN Duty = 4907%(X100), DQS PI = 56
7366 09:29:19.943265 [0] AVG Duty = 5078%(X100)
7367 09:29:19.943558
7368 09:29:19.943787 ==DQS 1 ==
7369 09:29:19.946874 Final DQS duty delay cell = -4
7370 09:29:19.950097 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7371 09:29:19.953544 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7372 09:29:19.956423 [-4] AVG Duty = 4906%(X100)
7373 09:29:19.956719
7374 09:29:19.959782 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7375 09:29:19.960081
7376 09:29:19.963294 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7377 09:29:19.966280 [DutyScan_Calibration_Flow] ====Done====
7378 09:29:19.966574
7379 09:29:19.969804 [DutyScan_Calibration_Flow] k_type=3
7380 09:29:19.987801
7381 09:29:19.988113 ==DQM 0 ==
7382 09:29:19.990660 Final DQM duty delay cell = 0
7383 09:29:19.994275 [0] MAX Duty = 5031%(X100), DQS PI = 30
7384 09:29:19.997295 [0] MIN Duty = 4782%(X100), DQS PI = 40
7385 09:29:20.000548 [0] AVG Duty = 4906%(X100)
7386 09:29:20.000880
7387 09:29:20.001139 ==DQM 1 ==
7388 09:29:20.004156 Final DQM duty delay cell = 0
7389 09:29:20.007656 [0] MAX Duty = 4969%(X100), DQS PI = 30
7390 09:29:20.010863 [0] MIN Duty = 4844%(X100), DQS PI = 0
7391 09:29:20.013904 [0] AVG Duty = 4906%(X100)
7392 09:29:20.014200
7393 09:29:20.017022 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7394 09:29:20.017402
7395 09:29:20.020810 CH1 DQM 1 Duty spec in!! Max-Min= 125%
7396 09:29:20.024036 [DutyScan_Calibration_Flow] ====Done====
7397 09:29:20.024333
7398 09:29:20.026990 [DutyScan_Calibration_Flow] k_type=2
7399 09:29:20.043672
7400 09:29:20.043973 ==DQ 0 ==
7401 09:29:20.046705 Final DQ duty delay cell = -4
7402 09:29:20.050200 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7403 09:29:20.053698 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7404 09:29:20.056769 [-4] AVG Duty = 4891%(X100)
7405 09:29:20.057064
7406 09:29:20.057428 ==DQ 1 ==
7407 09:29:20.059898 Final DQ duty delay cell = 0
7408 09:29:20.063278 [0] MAX Duty = 5031%(X100), DQS PI = 30
7409 09:29:20.066757 [0] MIN Duty = 4844%(X100), DQS PI = 60
7410 09:29:20.069965 [0] AVG Duty = 4937%(X100)
7411 09:29:20.070263
7412 09:29:20.073382 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7413 09:29:20.073783
7414 09:29:20.076627 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7415 09:29:20.079546 [DutyScan_Calibration_Flow] ====Done====
7416 09:29:20.082999 nWR fixed to 30
7417 09:29:20.086240 [ModeRegInit_LP4] CH0 RK0
7418 09:29:20.086523 [ModeRegInit_LP4] CH0 RK1
7419 09:29:20.089736 [ModeRegInit_LP4] CH1 RK0
7420 09:29:20.093301 [ModeRegInit_LP4] CH1 RK1
7421 09:29:20.093616 match AC timing 5
7422 09:29:20.099688 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7423 09:29:20.102753 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7424 09:29:20.105844 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7425 09:29:20.113075 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7426 09:29:20.116191 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7427 09:29:20.119358 [MiockJmeterHQA]
7428 09:29:20.119740
7429 09:29:20.123074 [DramcMiockJmeter] u1RxGatingPI = 0
7430 09:29:20.123370 0 : 4365, 4138
7431 09:29:20.123607 4 : 4253, 4027
7432 09:29:20.126135 8 : 4363, 4137
7433 09:29:20.126434 12 : 4363, 4137
7434 09:29:20.129138 16 : 4253, 4027
7435 09:29:20.129219 20 : 4253, 4026
7436 09:29:20.132750 24 : 4252, 4027
7437 09:29:20.132832 28 : 4252, 4027
7438 09:29:20.132901 32 : 4252, 4027
7439 09:29:20.135593 36 : 4252, 4027
7440 09:29:20.135675 40 : 4363, 4137
7441 09:29:20.139224 44 : 4363, 4138
7442 09:29:20.139305 48 : 4363, 4137
7443 09:29:20.142363 52 : 4253, 4026
7444 09:29:20.142449 56 : 4252, 4027
7445 09:29:20.145926 60 : 4253, 4026
7446 09:29:20.146000 64 : 4361, 4137
7447 09:29:20.146065 68 : 4361, 4137
7448 09:29:20.148939 72 : 4361, 4137
7449 09:29:20.149046 76 : 4250, 4027
7450 09:29:20.152126 80 : 4250, 4026
7451 09:29:20.152202 84 : 4250, 4026
7452 09:29:20.155174 88 : 4249, 4027
7453 09:29:20.155246 92 : 4360, 4137
7454 09:29:20.158817 96 : 4250, 2484
7455 09:29:20.158888 100 : 4249, 0
7456 09:29:20.158951 104 : 4249, 0
7457 09:29:20.162037 108 : 4257, 0
7458 09:29:20.162125 112 : 4252, 0
7459 09:29:20.162188 116 : 4250, 0
7460 09:29:20.165105 120 : 4250, 0
7461 09:29:20.165201 124 : 4361, 0
7462 09:29:20.168746 128 : 4249, 0
7463 09:29:20.168830 132 : 4250, 0
7464 09:29:20.168895 136 : 4250, 0
7465 09:29:20.171888 140 : 4250, 0
7466 09:29:20.171997 144 : 4360, 0
7467 09:29:20.174872 148 : 4250, 0
7468 09:29:20.174952 152 : 4360, 0
7469 09:29:20.175020 156 : 4250, 0
7470 09:29:20.178361 160 : 4250, 0
7471 09:29:20.178538 164 : 4361, 0
7472 09:29:20.181734 168 : 4250, 0
7473 09:29:20.181836 172 : 4250, 0
7474 09:29:20.181929 176 : 4250, 0
7475 09:29:20.185055 180 : 4249, 0
7476 09:29:20.185164 184 : 4250, 0
7477 09:29:20.188429 188 : 4250, 0
7478 09:29:20.188502 192 : 4249, 0
7479 09:29:20.188562 196 : 4360, 0
7480 09:29:20.194029 200 : 4250, 0
7481 09:29:20.194162 204 : 4360, 0
7482 09:29:20.194732 208 : 4250, 0
7483 09:29:20.194835 212 : 4250, 0
7484 09:29:20.194927 216 : 4250, 0
7485 09:29:20.198454 220 : 4253, 530
7486 09:29:20.198533 224 : 4250, 4014
7487 09:29:20.201828 228 : 4250, 4027
7488 09:29:20.201943 232 : 4250, 4027
7489 09:29:20.204765 236 : 4250, 4027
7490 09:29:20.204843 240 : 4250, 4027
7491 09:29:20.208531 244 : 4363, 4140
7492 09:29:20.208619 248 : 4361, 4137
7493 09:29:20.211633 252 : 4250, 4027
7494 09:29:20.211730 256 : 4250, 4027
7495 09:29:20.211827 260 : 4252, 4029
7496 09:29:20.214716 264 : 4250, 4026
7497 09:29:20.214813 268 : 4250, 4027
7498 09:29:20.218140 272 : 4361, 4138
7499 09:29:20.218245 276 : 4250, 4026
7500 09:29:20.221170 280 : 4250, 4026
7501 09:29:20.221299 284 : 4360, 4138
7502 09:29:20.224888 288 : 4250, 4027
7503 09:29:20.225058 292 : 4250, 4026
7504 09:29:20.228062 296 : 4361, 4137
7505 09:29:20.228189 300 : 4361, 4137
7506 09:29:20.231093 304 : 4250, 4027
7507 09:29:20.231237 308 : 4250, 4027
7508 09:29:20.235093 312 : 4252, 4029
7509 09:29:20.235328 316 : 4250, 4026
7510 09:29:20.238093 320 : 4252, 4027
7511 09:29:20.238281 324 : 4361, 4138
7512 09:29:20.238438 328 : 4250, 4026
7513 09:29:20.241032 332 : 4250, 3897
7514 09:29:20.241211 336 : 4360, 1234
7515 09:29:20.241408
7516 09:29:20.244750 MIOCK jitter meter ch=0
7517 09:29:20.245022
7518 09:29:20.248430 1T = (336-100) = 236 dly cells
7519 09:29:20.254337 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7520 09:29:20.254653 ==
7521 09:29:20.257523 Dram Type= 6, Freq= 0, CH_0, rank 0
7522 09:29:20.261510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7523 09:29:20.261986 ==
7524 09:29:20.268190 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7525 09:29:20.270759 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7526 09:29:20.274623 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7527 09:29:20.280724 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7528 09:29:20.290323 [CA 0] Center 43 (13~74) winsize 62
7529 09:29:20.293722 [CA 1] Center 42 (12~73) winsize 62
7530 09:29:20.297222 [CA 2] Center 37 (8~67) winsize 60
7531 09:29:20.300292 [CA 3] Center 37 (8~67) winsize 60
7532 09:29:20.303765 [CA 4] Center 36 (6~66) winsize 61
7533 09:29:20.307502 [CA 5] Center 35 (5~66) winsize 62
7534 09:29:20.308013
7535 09:29:20.310027 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7536 09:29:20.310446
7537 09:29:20.313903 [CATrainingPosCal] consider 1 rank data
7538 09:29:20.317063 u2DelayCellTimex100 = 275/100 ps
7539 09:29:20.320053 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7540 09:29:20.326868 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7541 09:29:20.330666 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7542 09:29:20.333750 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7543 09:29:20.336753 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7544 09:29:20.339887 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7545 09:29:20.340302
7546 09:29:20.343751 CA PerBit enable=1, Macro0, CA PI delay=35
7547 09:29:20.344326
7548 09:29:20.346747 [CBTSetCACLKResult] CA Dly = 35
7549 09:29:20.349469 CS Dly: 11 (0~42)
7550 09:29:20.353069 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7551 09:29:20.356423 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7552 09:29:20.357088 ==
7553 09:29:20.360183 Dram Type= 6, Freq= 0, CH_0, rank 1
7554 09:29:20.366106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 09:29:20.366533 ==
7556 09:29:20.369522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7557 09:29:20.376280 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7558 09:29:20.379341 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7559 09:29:20.386146 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7560 09:29:20.393865 [CA 0] Center 44 (14~75) winsize 62
7561 09:29:20.397114 [CA 1] Center 44 (14~74) winsize 61
7562 09:29:20.400512 [CA 2] Center 39 (10~69) winsize 60
7563 09:29:20.403577 [CA 3] Center 39 (10~68) winsize 59
7564 09:29:20.407017 [CA 4] Center 37 (7~67) winsize 61
7565 09:29:20.410718 [CA 5] Center 36 (7~66) winsize 60
7566 09:29:20.411379
7567 09:29:20.413703 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7568 09:29:20.414274
7569 09:29:20.419850 [CATrainingPosCal] consider 2 rank data
7570 09:29:20.420267 u2DelayCellTimex100 = 275/100 ps
7571 09:29:20.426891 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7572 09:29:20.430111 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7573 09:29:20.433357 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7574 09:29:20.436464 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7575 09:29:20.439895 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7576 09:29:20.443199 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7577 09:29:20.443616
7578 09:29:20.446503 CA PerBit enable=1, Macro0, CA PI delay=36
7579 09:29:20.449945
7580 09:29:20.450361 [CBTSetCACLKResult] CA Dly = 36
7581 09:29:20.453017 CS Dly: 11 (0~43)
7582 09:29:20.456194 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7583 09:29:20.459777 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7584 09:29:20.460191
7585 09:29:20.466071 ----->DramcWriteLeveling(PI) begin...
7586 09:29:20.466549 ==
7587 09:29:20.469727 Dram Type= 6, Freq= 0, CH_0, rank 0
7588 09:29:20.472724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7589 09:29:20.473422 ==
7590 09:29:20.475669 Write leveling (Byte 0): 34 => 34
7591 09:29:20.479466 Write leveling (Byte 1): 26 => 26
7592 09:29:20.482571 DramcWriteLeveling(PI) end<-----
7593 09:29:20.483105
7594 09:29:20.483550 ==
7595 09:29:20.485821 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 09:29:20.489572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 09:29:20.490213 ==
7598 09:29:20.492441 [Gating] SW mode calibration
7599 09:29:20.499201 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7600 09:29:20.505576 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7601 09:29:20.509036 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 09:29:20.512386 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 09:29:20.518771 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 09:29:20.522170 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7605 09:29:20.525231 1 4 16 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
7606 09:29:20.532278 1 4 20 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
7607 09:29:20.535275 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 09:29:20.538696 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 09:29:20.545311 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 09:29:20.548623 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 09:29:20.551546 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7612 09:29:20.558579 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
7613 09:29:20.561720 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7614 09:29:20.564605 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
7615 09:29:20.571522 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
7616 09:29:20.575240 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 09:29:20.578234 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 09:29:20.585102 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 09:29:20.588188 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7620 09:29:20.591410 1 6 12 | B1->B0 | 2323 4444 | 0 1 | (0 0) (0 0)
7621 09:29:20.597926 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7622 09:29:20.601454 1 6 20 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
7623 09:29:20.604410 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 09:29:20.611005 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 09:29:20.614415 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 09:29:20.617756 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 09:29:20.624382 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7628 09:29:20.628187 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7629 09:29:20.631334 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7630 09:29:20.637439 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7631 09:29:20.641241 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7632 09:29:20.644071 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 09:29:20.650629 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 09:29:20.654022 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 09:29:20.657108 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 09:29:20.664173 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 09:29:20.667378 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 09:29:20.670976 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 09:29:20.677201 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 09:29:20.680314 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 09:29:20.683996 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 09:29:20.690266 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 09:29:20.693476 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7644 09:29:20.697340 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7645 09:29:20.699920 Total UI for P1: 0, mck2ui 16
7646 09:29:20.703021 best dqsien dly found for B0: ( 1, 9, 8)
7647 09:29:20.710319 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7648 09:29:20.713612 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7649 09:29:20.716423 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 09:29:20.719988 Total UI for P1: 0, mck2ui 16
7651 09:29:20.723048 best dqsien dly found for B1: ( 1, 9, 20)
7652 09:29:20.726473 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7653 09:29:20.729845 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7654 09:29:20.730258
7655 09:29:20.736359 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7656 09:29:20.739297 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7657 09:29:20.742534 [Gating] SW calibration Done
7658 09:29:20.743033 ==
7659 09:29:20.746115 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 09:29:20.749123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 09:29:20.749716 ==
7662 09:29:20.750191 RX Vref Scan: 0
7663 09:29:20.752683
7664 09:29:20.753092 RX Vref 0 -> 0, step: 1
7665 09:29:20.753532
7666 09:29:20.755680 RX Delay 0 -> 252, step: 8
7667 09:29:20.759183 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7668 09:29:20.762875 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7669 09:29:20.769436 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7670 09:29:20.772219 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7671 09:29:20.775607 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7672 09:29:20.778778 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7673 09:29:20.782340 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7674 09:29:20.788419 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7675 09:29:20.792184 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7676 09:29:20.795229 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7677 09:29:20.798894 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7678 09:29:20.802064 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7679 09:29:20.809069 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7680 09:29:20.811837 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7681 09:29:20.815553 iDelay=192, Bit 14, Center 139 (88 ~ 191) 104
7682 09:29:20.818630 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7683 09:29:20.819147 ==
7684 09:29:20.822180 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 09:29:20.828177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 09:29:20.828597 ==
7687 09:29:20.828924 DQS Delay:
7688 09:29:20.831820 DQS0 = 0, DQS1 = 0
7689 09:29:20.832237 DQM Delay:
7690 09:29:20.835442 DQM0 = 131, DQM1 = 127
7691 09:29:20.835952 DQ Delay:
7692 09:29:20.838491 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =123
7693 09:29:20.841714 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7694 09:29:20.844941 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
7695 09:29:20.848684 DQ12 =135, DQ13 =131, DQ14 =139, DQ15 =131
7696 09:29:20.849094
7697 09:29:20.849479
7698 09:29:20.849784 ==
7699 09:29:20.851731 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 09:29:20.857953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 09:29:20.858457 ==
7702 09:29:20.858839
7703 09:29:20.859155
7704 09:29:20.859443 TX Vref Scan disable
7705 09:29:20.861391 == TX Byte 0 ==
7706 09:29:20.865130 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7707 09:29:20.871768 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7708 09:29:20.872288 == TX Byte 1 ==
7709 09:29:20.874749 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7710 09:29:20.881505 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7711 09:29:20.881926 ==
7712 09:29:20.885181 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 09:29:20.888379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 09:29:20.888883 ==
7715 09:29:20.901413
7716 09:29:20.904723 TX Vref early break, caculate TX vref
7717 09:29:20.907930 TX Vref=16, minBit 8, minWin=22, winSum=370
7718 09:29:20.911049 TX Vref=18, minBit 7, minWin=22, winSum=381
7719 09:29:20.914199 TX Vref=20, minBit 1, minWin=24, winSum=393
7720 09:29:20.917694 TX Vref=22, minBit 6, minWin=24, winSum=401
7721 09:29:20.920821 TX Vref=24, minBit 7, minWin=24, winSum=406
7722 09:29:20.927789 TX Vref=26, minBit 3, minWin=25, winSum=419
7723 09:29:20.930882 TX Vref=28, minBit 1, minWin=25, winSum=420
7724 09:29:20.934127 TX Vref=30, minBit 4, minWin=25, winSum=416
7725 09:29:20.937654 TX Vref=32, minBit 0, minWin=24, winSum=406
7726 09:29:20.940803 TX Vref=34, minBit 0, minWin=24, winSum=398
7727 09:29:20.947825 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 28
7728 09:29:20.948337
7729 09:29:20.950821 Final TX Range 0 Vref 28
7730 09:29:20.951239
7731 09:29:20.951565 ==
7732 09:29:20.954102 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 09:29:20.957814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 09:29:20.958341 ==
7735 09:29:20.958676
7736 09:29:20.958984
7737 09:29:20.960819 TX Vref Scan disable
7738 09:29:20.967447 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7739 09:29:20.967882 == TX Byte 0 ==
7740 09:29:20.970325 u2DelayCellOfst[0]=14 cells (4 PI)
7741 09:29:20.973697 u2DelayCellOfst[1]=17 cells (5 PI)
7742 09:29:20.977339 u2DelayCellOfst[2]=14 cells (4 PI)
7743 09:29:20.980375 u2DelayCellOfst[3]=14 cells (4 PI)
7744 09:29:20.983584 u2DelayCellOfst[4]=10 cells (3 PI)
7745 09:29:20.987184 u2DelayCellOfst[5]=0 cells (0 PI)
7746 09:29:20.990441 u2DelayCellOfst[6]=21 cells (6 PI)
7747 09:29:20.993723 u2DelayCellOfst[7]=17 cells (5 PI)
7748 09:29:20.997035 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7749 09:29:21.000122 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7750 09:29:21.003848 == TX Byte 1 ==
7751 09:29:21.006685 u2DelayCellOfst[8]=0 cells (0 PI)
7752 09:29:21.009859 u2DelayCellOfst[9]=0 cells (0 PI)
7753 09:29:21.013459 u2DelayCellOfst[10]=3 cells (1 PI)
7754 09:29:21.013877 u2DelayCellOfst[11]=0 cells (0 PI)
7755 09:29:21.016716 u2DelayCellOfst[12]=10 cells (3 PI)
7756 09:29:21.019649 u2DelayCellOfst[13]=7 cells (2 PI)
7757 09:29:21.023579 u2DelayCellOfst[14]=14 cells (4 PI)
7758 09:29:21.026765 u2DelayCellOfst[15]=10 cells (3 PI)
7759 09:29:21.033357 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7760 09:29:21.036442 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7761 09:29:21.036861 DramC Write-DBI on
7762 09:29:21.039611 ==
7763 09:29:21.042696 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 09:29:21.046259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 09:29:21.046686 ==
7766 09:29:21.047107
7767 09:29:21.047504
7768 09:29:21.049213 TX Vref Scan disable
7769 09:29:21.049687 == TX Byte 0 ==
7770 09:29:21.056427 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7771 09:29:21.056856 == TX Byte 1 ==
7772 09:29:21.059495 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7773 09:29:21.063215 DramC Write-DBI off
7774 09:29:21.063639
7775 09:29:21.064063 [DATLAT]
7776 09:29:21.066543 Freq=1600, CH0 RK0
7777 09:29:21.067073
7778 09:29:21.067406 DATLAT Default: 0xf
7779 09:29:21.069458 0, 0xFFFF, sum = 0
7780 09:29:21.069885 1, 0xFFFF, sum = 0
7781 09:29:21.072490 2, 0xFFFF, sum = 0
7782 09:29:21.072909 3, 0xFFFF, sum = 0
7783 09:29:21.075970 4, 0xFFFF, sum = 0
7784 09:29:21.076394 5, 0xFFFF, sum = 0
7785 09:29:21.079520 6, 0xFFFF, sum = 0
7786 09:29:21.082506 7, 0xFFFF, sum = 0
7787 09:29:21.082928 8, 0xFFFF, sum = 0
7788 09:29:21.086441 9, 0xFFFF, sum = 0
7789 09:29:21.086965 10, 0xFFFF, sum = 0
7790 09:29:21.089413 11, 0xFFFF, sum = 0
7791 09:29:21.089924 12, 0xFFFF, sum = 0
7792 09:29:21.092364 13, 0xFFFF, sum = 0
7793 09:29:21.092789 14, 0x0, sum = 1
7794 09:29:21.095501 15, 0x0, sum = 2
7795 09:29:21.095924 16, 0x0, sum = 3
7796 09:29:21.098982 17, 0x0, sum = 4
7797 09:29:21.099403 best_step = 15
7798 09:29:21.099730
7799 09:29:21.100031 ==
7800 09:29:21.102218 Dram Type= 6, Freq= 0, CH_0, rank 0
7801 09:29:21.105413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7802 09:29:21.108979 ==
7803 09:29:21.109417 RX Vref Scan: 1
7804 09:29:21.109742
7805 09:29:21.112215 Set Vref Range= 24 -> 127
7806 09:29:21.112632
7807 09:29:21.115445 RX Vref 24 -> 127, step: 1
7808 09:29:21.115858
7809 09:29:21.116184 RX Delay 19 -> 252, step: 4
7810 09:29:21.116489
7811 09:29:21.119122 Set Vref, RX VrefLevel [Byte0]: 24
7812 09:29:21.122114 [Byte1]: 24
7813 09:29:21.125847
7814 09:29:21.126261 Set Vref, RX VrefLevel [Byte0]: 25
7815 09:29:21.128959 [Byte1]: 25
7816 09:29:21.133408
7817 09:29:21.133833 Set Vref, RX VrefLevel [Byte0]: 26
7818 09:29:21.137199 [Byte1]: 26
7819 09:29:21.141584
7820 09:29:21.142092 Set Vref, RX VrefLevel [Byte0]: 27
7821 09:29:21.144669 [Byte1]: 27
7822 09:29:21.149203
7823 09:29:21.149782 Set Vref, RX VrefLevel [Byte0]: 28
7824 09:29:21.151874 [Byte1]: 28
7825 09:29:21.156568
7826 09:29:21.157108 Set Vref, RX VrefLevel [Byte0]: 29
7827 09:29:21.159870 [Byte1]: 29
7828 09:29:21.164119
7829 09:29:21.164648 Set Vref, RX VrefLevel [Byte0]: 30
7830 09:29:21.167303 [Byte1]: 30
7831 09:29:21.171507
7832 09:29:21.172007 Set Vref, RX VrefLevel [Byte0]: 31
7833 09:29:21.174681 [Byte1]: 31
7834 09:29:21.178793
7835 09:29:21.179221 Set Vref, RX VrefLevel [Byte0]: 32
7836 09:29:21.182253 [Byte1]: 32
7837 09:29:21.186512
7838 09:29:21.187079 Set Vref, RX VrefLevel [Byte0]: 33
7839 09:29:21.190091 [Byte1]: 33
7840 09:29:21.194251
7841 09:29:21.194700 Set Vref, RX VrefLevel [Byte0]: 34
7842 09:29:21.197558 [Byte1]: 34
7843 09:29:21.201703
7844 09:29:21.202151 Set Vref, RX VrefLevel [Byte0]: 35
7845 09:29:21.204888 [Byte1]: 35
7846 09:29:21.209069
7847 09:29:21.209584 Set Vref, RX VrefLevel [Byte0]: 36
7848 09:29:21.212312 [Byte1]: 36
7849 09:29:21.216283
7850 09:29:21.216364 Set Vref, RX VrefLevel [Byte0]: 37
7851 09:29:21.219762 [Byte1]: 37
7852 09:29:21.223860
7853 09:29:21.223945 Set Vref, RX VrefLevel [Byte0]: 38
7854 09:29:21.227417 [Byte1]: 38
7855 09:29:21.231640
7856 09:29:21.231724 Set Vref, RX VrefLevel [Byte0]: 39
7857 09:29:21.234971 [Byte1]: 39
7858 09:29:21.239018
7859 09:29:21.239100 Set Vref, RX VrefLevel [Byte0]: 40
7860 09:29:21.242660 [Byte1]: 40
7861 09:29:21.246959
7862 09:29:21.247039 Set Vref, RX VrefLevel [Byte0]: 41
7863 09:29:21.250083 [Byte1]: 41
7864 09:29:21.254457
7865 09:29:21.254538 Set Vref, RX VrefLevel [Byte0]: 42
7866 09:29:21.257424 [Byte1]: 42
7867 09:29:21.261599
7868 09:29:21.261680 Set Vref, RX VrefLevel [Byte0]: 43
7869 09:29:21.265432 [Byte1]: 43
7870 09:29:21.269133
7871 09:29:21.269214 Set Vref, RX VrefLevel [Byte0]: 44
7872 09:29:21.272736 [Byte1]: 44
7873 09:29:21.277031
7874 09:29:21.277126 Set Vref, RX VrefLevel [Byte0]: 45
7875 09:29:21.280425 [Byte1]: 45
7876 09:29:21.284352
7877 09:29:21.284433 Set Vref, RX VrefLevel [Byte0]: 46
7878 09:29:21.287978 [Byte1]: 46
7879 09:29:21.292051
7880 09:29:21.292132 Set Vref, RX VrefLevel [Byte0]: 47
7881 09:29:21.295523 [Byte1]: 47
7882 09:29:21.300047
7883 09:29:21.300157 Set Vref, RX VrefLevel [Byte0]: 48
7884 09:29:21.303012 [Byte1]: 48
7885 09:29:21.307448
7886 09:29:21.307530 Set Vref, RX VrefLevel [Byte0]: 49
7887 09:29:21.310366 [Byte1]: 49
7888 09:29:21.314865
7889 09:29:21.314946 Set Vref, RX VrefLevel [Byte0]: 50
7890 09:29:21.317910 [Byte1]: 50
7891 09:29:21.322609
7892 09:29:21.322691 Set Vref, RX VrefLevel [Byte0]: 51
7893 09:29:21.325502 [Byte1]: 51
7894 09:29:21.330276
7895 09:29:21.330362 Set Vref, RX VrefLevel [Byte0]: 52
7896 09:29:21.333410 [Byte1]: 52
7897 09:29:21.337629
7898 09:29:21.337710 Set Vref, RX VrefLevel [Byte0]: 53
7899 09:29:21.340943 [Byte1]: 53
7900 09:29:21.345194
7901 09:29:21.345289 Set Vref, RX VrefLevel [Byte0]: 54
7902 09:29:21.348825 [Byte1]: 54
7903 09:29:21.353097
7904 09:29:21.353251 Set Vref, RX VrefLevel [Byte0]: 55
7905 09:29:21.356258 [Byte1]: 55
7906 09:29:21.360563
7907 09:29:21.360754 Set Vref, RX VrefLevel [Byte0]: 56
7908 09:29:21.363722 [Byte1]: 56
7909 09:29:21.367921
7910 09:29:21.368100 Set Vref, RX VrefLevel [Byte0]: 57
7911 09:29:21.371841 [Byte1]: 57
7912 09:29:21.375734
7913 09:29:21.376243 Set Vref, RX VrefLevel [Byte0]: 58
7914 09:29:21.379213 [Byte1]: 58
7915 09:29:21.383524
7916 09:29:21.383942 Set Vref, RX VrefLevel [Byte0]: 59
7917 09:29:21.386421 [Byte1]: 59
7918 09:29:21.390992
7919 09:29:21.391408 Set Vref, RX VrefLevel [Byte0]: 60
7920 09:29:21.394171 [Byte1]: 60
7921 09:29:21.398453
7922 09:29:21.398867 Set Vref, RX VrefLevel [Byte0]: 61
7923 09:29:21.401986 [Byte1]: 61
7924 09:29:21.405909
7925 09:29:21.406323 Set Vref, RX VrefLevel [Byte0]: 62
7926 09:29:21.409720 [Byte1]: 62
7927 09:29:21.413805
7928 09:29:21.414220 Set Vref, RX VrefLevel [Byte0]: 63
7929 09:29:21.416967 [Byte1]: 63
7930 09:29:21.421608
7931 09:29:21.422140 Set Vref, RX VrefLevel [Byte0]: 64
7932 09:29:21.424475 [Byte1]: 64
7933 09:29:21.428634
7934 09:29:21.429076 Set Vref, RX VrefLevel [Byte0]: 65
7935 09:29:21.432260 [Byte1]: 65
7936 09:29:21.436699
7937 09:29:21.437116 Set Vref, RX VrefLevel [Byte0]: 66
7938 09:29:21.439983 [Byte1]: 66
7939 09:29:21.444273
7940 09:29:21.444690 Set Vref, RX VrefLevel [Byte0]: 67
7941 09:29:21.447195 [Byte1]: 67
7942 09:29:21.451805
7943 09:29:21.452254 Set Vref, RX VrefLevel [Byte0]: 68
7944 09:29:21.454841 [Byte1]: 68
7945 09:29:21.459271
7946 09:29:21.459784 Set Vref, RX VrefLevel [Byte0]: 69
7947 09:29:21.462794 [Byte1]: 69
7948 09:29:21.466878
7949 09:29:21.467627 Set Vref, RX VrefLevel [Byte0]: 70
7950 09:29:21.470247 [Byte1]: 70
7951 09:29:21.474544
7952 09:29:21.474955 Set Vref, RX VrefLevel [Byte0]: 71
7953 09:29:21.477567 [Byte1]: 71
7954 09:29:21.481803
7955 09:29:21.482213 Set Vref, RX VrefLevel [Byte0]: 72
7956 09:29:21.485425 [Byte1]: 72
7957 09:29:21.489812
7958 09:29:21.490328 Set Vref, RX VrefLevel [Byte0]: 73
7959 09:29:21.492815 [Byte1]: 73
7960 09:29:21.497019
7961 09:29:21.497554 Set Vref, RX VrefLevel [Byte0]: 74
7962 09:29:21.500430 [Byte1]: 74
7963 09:29:21.504766
7964 09:29:21.505177 Set Vref, RX VrefLevel [Byte0]: 75
7965 09:29:21.507994 [Byte1]: 75
7966 09:29:21.511977
7967 09:29:21.512427 Set Vref, RX VrefLevel [Byte0]: 76
7968 09:29:21.515576 [Byte1]: 76
7969 09:29:21.519687
7970 09:29:21.520157 Final RX Vref Byte 0 = 56 to rank0
7971 09:29:21.522729 Final RX Vref Byte 1 = 62 to rank0
7972 09:29:21.525905 Final RX Vref Byte 0 = 56 to rank1
7973 09:29:21.529175 Final RX Vref Byte 1 = 62 to rank1==
7974 09:29:21.532239 Dram Type= 6, Freq= 0, CH_0, rank 0
7975 09:29:21.539107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7976 09:29:21.539191 ==
7977 09:29:21.539255 DQS Delay:
7978 09:29:21.542198 DQS0 = 0, DQS1 = 0
7979 09:29:21.542280 DQM Delay:
7980 09:29:21.542345 DQM0 = 128, DQM1 = 123
7981 09:29:21.546091 DQ Delay:
7982 09:29:21.549280 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7983 09:29:21.552348 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =132
7984 09:29:21.555265 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7985 09:29:21.559032 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
7986 09:29:21.559114
7987 09:29:21.559177
7988 09:29:21.559235
7989 09:29:21.562388 [DramC_TX_OE_Calibration] TA2
7990 09:29:21.565224 Original DQ_B0 (3 6) =30, OEN = 27
7991 09:29:21.568432 Original DQ_B1 (3 6) =30, OEN = 27
7992 09:29:21.571902 24, 0x0, End_B0=24 End_B1=24
7993 09:29:21.574914 25, 0x0, End_B0=25 End_B1=25
7994 09:29:21.574996 26, 0x0, End_B0=26 End_B1=26
7995 09:29:21.578587 27, 0x0, End_B0=27 End_B1=27
7996 09:29:21.581770 28, 0x0, End_B0=28 End_B1=28
7997 09:29:21.584764 29, 0x0, End_B0=29 End_B1=29
7998 09:29:21.584846 30, 0x0, End_B0=30 End_B1=30
7999 09:29:21.588343 31, 0x5151, End_B0=30 End_B1=30
8000 09:29:21.591343 Byte0 end_step=30 best_step=27
8001 09:29:21.595000 Byte1 end_step=30 best_step=27
8002 09:29:21.598252 Byte0 TX OE(2T, 0.5T) = (3, 3)
8003 09:29:21.601283 Byte1 TX OE(2T, 0.5T) = (3, 3)
8004 09:29:21.601378
8005 09:29:21.601441
8006 09:29:21.608410 [DQSOSCAuto] RK0, (LSB)MR18= 0x1613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
8007 09:29:21.611423 CH0 RK0: MR19=303, MR18=1613
8008 09:29:21.618291 CH0_RK0: MR19=0x303, MR18=0x1613, DQSOSC=398, MR23=63, INC=23, DEC=15
8009 09:29:21.618373
8010 09:29:21.621503 ----->DramcWriteLeveling(PI) begin...
8011 09:29:21.621585 ==
8012 09:29:21.624443 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 09:29:21.628447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 09:29:21.628529 ==
8015 09:29:21.631335 Write leveling (Byte 0): 34 => 34
8016 09:29:21.635054 Write leveling (Byte 1): 27 => 27
8017 09:29:21.638052 DramcWriteLeveling(PI) end<-----
8018 09:29:21.638143
8019 09:29:21.638215 ==
8020 09:29:21.641209 Dram Type= 6, Freq= 0, CH_0, rank 1
8021 09:29:21.647908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 09:29:21.648023 ==
8023 09:29:21.648112 [Gating] SW mode calibration
8024 09:29:21.657889 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8025 09:29:21.661222 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8026 09:29:21.664729 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 09:29:21.671176 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 09:29:21.674234 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8029 09:29:21.677663 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8030 09:29:21.684505 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8031 09:29:21.687799 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8032 09:29:21.690939 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8033 09:29:21.697738 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8034 09:29:21.700874 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8035 09:29:21.704553 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8036 09:29:21.710866 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8037 09:29:21.714268 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8038 09:29:21.717287 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8039 09:29:21.724025 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8040 09:29:21.727300 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 09:29:21.730705 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 09:29:21.737192 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 09:29:21.740645 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8044 09:29:21.743802 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
8045 09:29:21.750964 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8046 09:29:21.753776 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8047 09:29:21.756802 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8048 09:29:21.763677 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 09:29:21.766593 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 09:29:21.772842 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 09:29:21.776218 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 09:29:21.779436 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8053 09:29:21.786323 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8054 09:29:21.789646 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8055 09:29:21.792463 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8056 09:29:21.799526 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 09:29:21.802988 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 09:29:21.806300 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 09:29:21.812616 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 09:29:21.815640 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 09:29:21.819189 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 09:29:21.825857 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 09:29:21.829028 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 09:29:21.832708 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 09:29:21.839549 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 09:29:21.842869 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 09:29:21.845951 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8068 09:29:21.852487 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8069 09:29:21.855572 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8070 09:29:21.859197 Total UI for P1: 0, mck2ui 16
8071 09:29:21.862375 best dqsien dly found for B0: ( 1, 9, 6)
8072 09:29:21.865382 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8073 09:29:21.872029 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 09:29:21.872447 Total UI for P1: 0, mck2ui 16
8075 09:29:21.875180 best dqsien dly found for B1: ( 1, 9, 18)
8076 09:29:21.881752 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8077 09:29:21.885476 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8078 09:29:21.885893
8079 09:29:21.888504 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8080 09:29:21.891701 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8081 09:29:21.895292 [Gating] SW calibration Done
8082 09:29:21.895704 ==
8083 09:29:21.898330 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 09:29:21.901314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 09:29:21.901744 ==
8086 09:29:21.905089 RX Vref Scan: 0
8087 09:29:21.905551
8088 09:29:21.905884 RX Vref 0 -> 0, step: 1
8089 09:29:21.906192
8090 09:29:21.908354 RX Delay 0 -> 252, step: 8
8091 09:29:21.911061 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8092 09:29:21.917995 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8093 09:29:21.921380 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8094 09:29:21.924411 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8095 09:29:21.928454 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8096 09:29:21.931215 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8097 09:29:21.937902 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8098 09:29:21.941147 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8099 09:29:21.944214 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8100 09:29:21.947688 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8101 09:29:21.950554 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8102 09:29:21.957494 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8103 09:29:21.960935 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8104 09:29:21.963977 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8105 09:29:21.967098 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8106 09:29:21.973856 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8107 09:29:21.973973 ==
8108 09:29:21.976993 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 09:29:21.980418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 09:29:21.980533 ==
8111 09:29:21.980624 DQS Delay:
8112 09:29:21.983884 DQS0 = 0, DQS1 = 0
8113 09:29:21.984000 DQM Delay:
8114 09:29:21.987147 DQM0 = 131, DQM1 = 127
8115 09:29:21.987263 DQ Delay:
8116 09:29:21.990423 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8117 09:29:21.993297 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8118 09:29:21.997013 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8119 09:29:22.000117 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8120 09:29:22.000249
8121 09:29:22.003584
8122 09:29:22.003714 ==
8123 09:29:22.006552 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 09:29:22.010032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 09:29:22.010197 ==
8126 09:29:22.010362
8127 09:29:22.010518
8128 09:29:22.013285 TX Vref Scan disable
8129 09:29:22.013449 == TX Byte 0 ==
8130 09:29:22.020154 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8131 09:29:22.023607 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8132 09:29:22.024045 == TX Byte 1 ==
8133 09:29:22.029832 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8134 09:29:22.033347 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8135 09:29:22.033867 ==
8136 09:29:22.036726 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 09:29:22.039904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 09:29:22.040321 ==
8139 09:29:22.055415
8140 09:29:22.058477 TX Vref early break, caculate TX vref
8141 09:29:22.062033 TX Vref=16, minBit 9, minWin=22, winSum=382
8142 09:29:22.065718 TX Vref=18, minBit 8, minWin=23, winSum=391
8143 09:29:22.068791 TX Vref=20, minBit 3, minWin=24, winSum=397
8144 09:29:22.072033 TX Vref=22, minBit 9, minWin=24, winSum=407
8145 09:29:22.075055 TX Vref=24, minBit 1, minWin=25, winSum=414
8146 09:29:22.081801 TX Vref=26, minBit 2, minWin=25, winSum=414
8147 09:29:22.085379 TX Vref=28, minBit 2, minWin=25, winSum=423
8148 09:29:22.088276 TX Vref=30, minBit 8, minWin=24, winSum=414
8149 09:29:22.092107 TX Vref=32, minBit 7, minWin=24, winSum=408
8150 09:29:22.095018 TX Vref=34, minBit 4, minWin=24, winSum=401
8151 09:29:22.098108 TX Vref=36, minBit 0, minWin=24, winSum=390
8152 09:29:22.105117 [TxChooseVref] Worse bit 2, Min win 25, Win sum 423, Final Vref 28
8153 09:29:22.105581
8154 09:29:22.108279 Final TX Range 0 Vref 28
8155 09:29:22.108707
8156 09:29:22.109028 ==
8157 09:29:22.111630 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 09:29:22.115254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 09:29:22.115672 ==
8160 09:29:22.118099
8161 09:29:22.118627
8162 09:29:22.118962 TX Vref Scan disable
8163 09:29:22.124673 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8164 09:29:22.125182 == TX Byte 0 ==
8165 09:29:22.128020 u2DelayCellOfst[0]=10 cells (3 PI)
8166 09:29:22.131554 u2DelayCellOfst[1]=14 cells (4 PI)
8167 09:29:22.134423 u2DelayCellOfst[2]=7 cells (2 PI)
8168 09:29:22.137572 u2DelayCellOfst[3]=10 cells (3 PI)
8169 09:29:22.141102 u2DelayCellOfst[4]=7 cells (2 PI)
8170 09:29:22.144723 u2DelayCellOfst[5]=0 cells (0 PI)
8171 09:29:22.147702 u2DelayCellOfst[6]=14 cells (4 PI)
8172 09:29:22.150949 u2DelayCellOfst[7]=14 cells (4 PI)
8173 09:29:22.154698 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8174 09:29:22.157638 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8175 09:29:22.161334 == TX Byte 1 ==
8176 09:29:22.164716 u2DelayCellOfst[8]=0 cells (0 PI)
8177 09:29:22.167581 u2DelayCellOfst[9]=0 cells (0 PI)
8178 09:29:22.170711 u2DelayCellOfst[10]=3 cells (1 PI)
8179 09:29:22.173990 u2DelayCellOfst[11]=3 cells (1 PI)
8180 09:29:22.177309 u2DelayCellOfst[12]=7 cells (2 PI)
8181 09:29:22.180807 u2DelayCellOfst[13]=10 cells (3 PI)
8182 09:29:22.181234 u2DelayCellOfst[14]=14 cells (4 PI)
8183 09:29:22.184025 u2DelayCellOfst[15]=10 cells (3 PI)
8184 09:29:22.190944 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8185 09:29:22.193955 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8186 09:29:22.196967 DramC Write-DBI on
8187 09:29:22.197442 ==
8188 09:29:22.200682 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 09:29:22.203958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 09:29:22.204484 ==
8191 09:29:22.204860
8192 09:29:22.205163
8193 09:29:22.206953 TX Vref Scan disable
8194 09:29:22.207397 == TX Byte 0 ==
8195 09:29:22.213882 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8196 09:29:22.214322 == TX Byte 1 ==
8197 09:29:22.217174 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8198 09:29:22.220668 DramC Write-DBI off
8199 09:29:22.221170
8200 09:29:22.221581 [DATLAT]
8201 09:29:22.223559 Freq=1600, CH0 RK1
8202 09:29:22.224076
8203 09:29:22.224400 DATLAT Default: 0xf
8204 09:29:22.226705 0, 0xFFFF, sum = 0
8205 09:29:22.230239 1, 0xFFFF, sum = 0
8206 09:29:22.230669 2, 0xFFFF, sum = 0
8207 09:29:22.233187 3, 0xFFFF, sum = 0
8208 09:29:22.233657 4, 0xFFFF, sum = 0
8209 09:29:22.237325 5, 0xFFFF, sum = 0
8210 09:29:22.237848 6, 0xFFFF, sum = 0
8211 09:29:22.240015 7, 0xFFFF, sum = 0
8212 09:29:22.240438 8, 0xFFFF, sum = 0
8213 09:29:22.243740 9, 0xFFFF, sum = 0
8214 09:29:22.244262 10, 0xFFFF, sum = 0
8215 09:29:22.246145 11, 0xFFFF, sum = 0
8216 09:29:22.246568 12, 0xFFFF, sum = 0
8217 09:29:22.249757 13, 0xFFFF, sum = 0
8218 09:29:22.250176 14, 0x0, sum = 1
8219 09:29:22.252845 15, 0x0, sum = 2
8220 09:29:22.253365 16, 0x0, sum = 3
8221 09:29:22.256092 17, 0x0, sum = 4
8222 09:29:22.256514 best_step = 15
8223 09:29:22.256838
8224 09:29:22.257185 ==
8225 09:29:22.259422 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 09:29:22.266483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 09:29:22.266997 ==
8228 09:29:22.267326 RX Vref Scan: 0
8229 09:29:22.267628
8230 09:29:22.269247 RX Vref 0 -> 0, step: 1
8231 09:29:22.269692
8232 09:29:22.273111 RX Delay 19 -> 252, step: 4
8233 09:29:22.276309 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8234 09:29:22.279729 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8235 09:29:22.285961 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8236 09:29:22.289004 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8237 09:29:22.292510 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8238 09:29:22.295664 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8239 09:29:22.299578 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8240 09:29:22.306086 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8241 09:29:22.309014 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8242 09:29:22.312243 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8243 09:29:22.315806 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8244 09:29:22.318708 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8245 09:29:22.326086 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8246 09:29:22.328971 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8247 09:29:22.332035 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8248 09:29:22.335232 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8249 09:29:22.335769 ==
8250 09:29:22.338796 Dram Type= 6, Freq= 0, CH_0, rank 1
8251 09:29:22.345036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 09:29:22.345509 ==
8253 09:29:22.345843 DQS Delay:
8254 09:29:22.348899 DQS0 = 0, DQS1 = 0
8255 09:29:22.349465 DQM Delay:
8256 09:29:22.351619 DQM0 = 128, DQM1 = 123
8257 09:29:22.352094 DQ Delay:
8258 09:29:22.355352 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8259 09:29:22.358176 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
8260 09:29:22.361635 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8261 09:29:22.364776 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =128
8262 09:29:22.365193
8263 09:29:22.365623
8264 09:29:22.366090
8265 09:29:22.368029 [DramC_TX_OE_Calibration] TA2
8266 09:29:22.371520 Original DQ_B0 (3 6) =30, OEN = 27
8267 09:29:22.374758 Original DQ_B1 (3 6) =30, OEN = 27
8268 09:29:22.377847 24, 0x0, End_B0=24 End_B1=24
8269 09:29:22.381466 25, 0x0, End_B0=25 End_B1=25
8270 09:29:22.381892 26, 0x0, End_B0=26 End_B1=26
8271 09:29:22.384661 27, 0x0, End_B0=27 End_B1=27
8272 09:29:22.387990 28, 0x0, End_B0=28 End_B1=28
8273 09:29:22.391417 29, 0x0, End_B0=29 End_B1=29
8274 09:29:22.394367 30, 0x0, End_B0=30 End_B1=30
8275 09:29:22.394793 31, 0x4141, End_B0=30 End_B1=30
8276 09:29:22.397966 Byte0 end_step=30 best_step=27
8277 09:29:22.401524 Byte1 end_step=30 best_step=27
8278 09:29:22.404127 Byte0 TX OE(2T, 0.5T) = (3, 3)
8279 09:29:22.407504 Byte1 TX OE(2T, 0.5T) = (3, 3)
8280 09:29:22.407922
8281 09:29:22.408247
8282 09:29:22.414764 [DQSOSCAuto] RK1, (LSB)MR18= 0x1412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8283 09:29:22.417809 CH0 RK1: MR19=303, MR18=1412
8284 09:29:22.424900 CH0_RK1: MR19=0x303, MR18=0x1412, DQSOSC=399, MR23=63, INC=23, DEC=15
8285 09:29:22.427683 [RxdqsGatingPostProcess] freq 1600
8286 09:29:22.434457 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8287 09:29:22.437199 best DQS0 dly(2T, 0.5T) = (1, 1)
8288 09:29:22.437664 best DQS1 dly(2T, 0.5T) = (1, 1)
8289 09:29:22.440836 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8290 09:29:22.444418 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8291 09:29:22.447350 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 09:29:22.450620 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 09:29:22.454025 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 09:29:22.457025 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 09:29:22.460614 Pre-setting of DQS Precalculation
8296 09:29:22.463824 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8297 09:29:22.466812 ==
8298 09:29:22.470352 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 09:29:22.473392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 09:29:22.473815 ==
8301 09:29:22.480024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8302 09:29:22.483492 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8303 09:29:22.486618 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8304 09:29:22.493382 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8305 09:29:22.501530 [CA 0] Center 41 (11~71) winsize 61
8306 09:29:22.504726 [CA 1] Center 42 (12~72) winsize 61
8307 09:29:22.508168 [CA 2] Center 38 (9~67) winsize 59
8308 09:29:22.511530 [CA 3] Center 37 (8~66) winsize 59
8309 09:29:22.515343 [CA 4] Center 37 (7~68) winsize 62
8310 09:29:22.518451 [CA 5] Center 36 (7~66) winsize 60
8311 09:29:22.518876
8312 09:29:22.521248 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8313 09:29:22.521716
8314 09:29:22.524826 [CATrainingPosCal] consider 1 rank data
8315 09:29:22.528004 u2DelayCellTimex100 = 275/100 ps
8316 09:29:22.534966 CA0 delay=41 (11~71),Diff = 5 PI (17 cell)
8317 09:29:22.538151 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8318 09:29:22.541204 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8319 09:29:22.544875 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8320 09:29:22.548182 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8321 09:29:22.551083 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8322 09:29:22.551509
8323 09:29:22.554713 CA PerBit enable=1, Macro0, CA PI delay=36
8324 09:29:22.555230
8325 09:29:22.557927 [CBTSetCACLKResult] CA Dly = 36
8326 09:29:22.561398 CS Dly: 8 (0~39)
8327 09:29:22.564447 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8328 09:29:22.568059 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8329 09:29:22.568484 ==
8330 09:29:22.571179 Dram Type= 6, Freq= 0, CH_1, rank 1
8331 09:29:22.574223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 09:29:22.577739 ==
8333 09:29:22.581145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8334 09:29:22.584334 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8335 09:29:22.591114 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8336 09:29:22.597130 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8337 09:29:22.605125 [CA 0] Center 42 (12~72) winsize 61
8338 09:29:22.608121 [CA 1] Center 43 (14~72) winsize 59
8339 09:29:22.611277 [CA 2] Center 38 (9~68) winsize 60
8340 09:29:22.614769 [CA 3] Center 37 (8~66) winsize 59
8341 09:29:22.618067 [CA 4] Center 38 (8~68) winsize 61
8342 09:29:22.621402 [CA 5] Center 37 (8~67) winsize 60
8343 09:29:22.621913
8344 09:29:22.624855 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8345 09:29:22.625424
8346 09:29:22.631193 [CATrainingPosCal] consider 2 rank data
8347 09:29:22.631615 u2DelayCellTimex100 = 275/100 ps
8348 09:29:22.637629 CA0 delay=41 (12~71),Diff = 4 PI (14 cell)
8349 09:29:22.641305 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8350 09:29:22.644494 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8351 09:29:22.647463 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8352 09:29:22.651228 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8353 09:29:22.654058 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8354 09:29:22.654601
8355 09:29:22.657623 CA PerBit enable=1, Macro0, CA PI delay=37
8356 09:29:22.658049
8357 09:29:22.660545 [CBTSetCACLKResult] CA Dly = 37
8358 09:29:22.664328 CS Dly: 9 (0~42)
8359 09:29:22.667711 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8360 09:29:22.671064 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8361 09:29:22.671487
8362 09:29:22.673928 ----->DramcWriteLeveling(PI) begin...
8363 09:29:22.674480 ==
8364 09:29:22.677636 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 09:29:22.683711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 09:29:22.684149 ==
8367 09:29:22.687148 Write leveling (Byte 0): 26 => 26
8368 09:29:22.690625 Write leveling (Byte 1): 26 => 26
8369 09:29:22.691044 DramcWriteLeveling(PI) end<-----
8370 09:29:22.693729
8371 09:29:22.694148 ==
8372 09:29:22.697166 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 09:29:22.700326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 09:29:22.700815 ==
8375 09:29:22.703550 [Gating] SW mode calibration
8376 09:29:22.710447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8377 09:29:22.713634 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8378 09:29:22.720627 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 09:29:22.723262 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 09:29:22.726902 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 09:29:22.733372 1 4 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8382 09:29:22.736368 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8383 09:29:22.739860 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 09:29:22.746667 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 09:29:22.749755 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 09:29:22.753020 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 09:29:22.760563 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 09:29:22.763080 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8389 09:29:22.766041 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (0 0) (1 0)
8390 09:29:22.772938 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8391 09:29:22.776680 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 09:29:22.779456 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 09:29:22.785913 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 09:29:22.789114 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 09:29:22.792574 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 09:29:22.799096 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8397 09:29:22.802387 1 6 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8398 09:29:22.805920 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 09:29:22.812799 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 09:29:22.815970 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 09:29:22.819047 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 09:29:22.825737 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 09:29:22.829322 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 09:29:22.832012 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8405 09:29:22.838803 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8406 09:29:22.842285 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8407 09:29:22.848432 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 09:29:22.851711 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 09:29:22.855298 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 09:29:22.861605 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 09:29:22.864850 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 09:29:22.868690 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 09:29:22.874648 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 09:29:22.878037 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 09:29:22.881527 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 09:29:22.888207 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 09:29:22.892128 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 09:29:22.894686 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 09:29:22.901338 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 09:29:22.904634 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8421 09:29:22.908057 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8422 09:29:22.914469 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8423 09:29:22.914938 Total UI for P1: 0, mck2ui 16
8424 09:29:22.921402 best dqsien dly found for B0: ( 1, 9, 10)
8425 09:29:22.924507 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 09:29:22.927555 Total UI for P1: 0, mck2ui 16
8427 09:29:22.930866 best dqsien dly found for B1: ( 1, 9, 14)
8428 09:29:22.934113 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8429 09:29:22.937324 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8430 09:29:22.937792
8431 09:29:22.940755 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8432 09:29:22.943936 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8433 09:29:22.947834 [Gating] SW calibration Done
8434 09:29:22.948347 ==
8435 09:29:22.951010 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 09:29:22.953971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 09:29:22.957494 ==
8438 09:29:22.958040 RX Vref Scan: 0
8439 09:29:22.958402
8440 09:29:22.960631 RX Vref 0 -> 0, step: 1
8441 09:29:22.961087
8442 09:29:22.961494 RX Delay 0 -> 252, step: 8
8443 09:29:22.967634 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8444 09:29:22.970485 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8445 09:29:22.973795 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8446 09:29:22.977455 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8447 09:29:22.980294 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8448 09:29:22.986960 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8449 09:29:22.990292 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8450 09:29:22.993763 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8451 09:29:22.997220 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8452 09:29:23.000538 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8453 09:29:23.006545 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8454 09:29:23.009871 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8455 09:29:23.013518 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8456 09:29:23.017136 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8457 09:29:23.023242 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8458 09:29:23.027105 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8459 09:29:23.027625 ==
8460 09:29:23.029839 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 09:29:23.032945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 09:29:23.033459 ==
8463 09:29:23.036008 DQS Delay:
8464 09:29:23.036474 DQS0 = 0, DQS1 = 0
8465 09:29:23.036844 DQM Delay:
8466 09:29:23.040061 DQM0 = 135, DQM1 = 132
8467 09:29:23.040579 DQ Delay:
8468 09:29:23.043174 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8469 09:29:23.046728 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8470 09:29:23.053058 DQ8 =115, DQ9 =123, DQ10 =131, DQ11 =127
8471 09:29:23.056738 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8472 09:29:23.057303
8473 09:29:23.057661
8474 09:29:23.057968 ==
8475 09:29:23.059740 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 09:29:23.062717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 09:29:23.063155 ==
8478 09:29:23.063488
8479 09:29:23.063795
8480 09:29:23.066482 TX Vref Scan disable
8481 09:29:23.069211 == TX Byte 0 ==
8482 09:29:23.072807 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8483 09:29:23.076185 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8484 09:29:23.079473 == TX Byte 1 ==
8485 09:29:23.082474 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8486 09:29:23.085966 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8487 09:29:23.086432 ==
8488 09:29:23.088890 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 09:29:23.092821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 09:29:23.095967 ==
8491 09:29:23.107987
8492 09:29:23.110975 TX Vref early break, caculate TX vref
8493 09:29:23.113874 TX Vref=16, minBit 8, minWin=22, winSum=371
8494 09:29:23.117481 TX Vref=18, minBit 8, minWin=22, winSum=376
8495 09:29:23.120869 TX Vref=20, minBit 9, minWin=22, winSum=385
8496 09:29:23.123915 TX Vref=22, minBit 8, minWin=23, winSum=394
8497 09:29:23.127463 TX Vref=24, minBit 13, minWin=24, winSum=406
8498 09:29:23.133876 TX Vref=26, minBit 8, minWin=25, winSum=416
8499 09:29:23.137434 TX Vref=28, minBit 3, minWin=25, winSum=413
8500 09:29:23.140878 TX Vref=30, minBit 9, minWin=25, winSum=414
8501 09:29:23.144549 TX Vref=32, minBit 0, minWin=24, winSum=406
8502 09:29:23.147186 TX Vref=34, minBit 9, minWin=23, winSum=396
8503 09:29:23.154022 TX Vref=36, minBit 9, minWin=22, winSum=384
8504 09:29:23.157122 [TxChooseVref] Worse bit 8, Min win 25, Win sum 416, Final Vref 26
8505 09:29:23.157582
8506 09:29:23.160411 Final TX Range 0 Vref 26
8507 09:29:23.160929
8508 09:29:23.161295 ==
8509 09:29:23.164228 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 09:29:23.167236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 09:29:23.170184 ==
8512 09:29:23.170739
8513 09:29:23.171101
8514 09:29:23.171435 TX Vref Scan disable
8515 09:29:23.177616 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8516 09:29:23.178174 == TX Byte 0 ==
8517 09:29:23.180338 u2DelayCellOfst[0]=14 cells (4 PI)
8518 09:29:23.183400 u2DelayCellOfst[1]=10 cells (3 PI)
8519 09:29:23.187107 u2DelayCellOfst[2]=0 cells (0 PI)
8520 09:29:23.190265 u2DelayCellOfst[3]=7 cells (2 PI)
8521 09:29:23.193859 u2DelayCellOfst[4]=7 cells (2 PI)
8522 09:29:23.196680 u2DelayCellOfst[5]=14 cells (4 PI)
8523 09:29:23.200496 u2DelayCellOfst[6]=14 cells (4 PI)
8524 09:29:23.203350 u2DelayCellOfst[7]=7 cells (2 PI)
8525 09:29:23.206949 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8526 09:29:23.209798 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8527 09:29:23.213508 == TX Byte 1 ==
8528 09:29:23.216687 u2DelayCellOfst[8]=0 cells (0 PI)
8529 09:29:23.220371 u2DelayCellOfst[9]=3 cells (1 PI)
8530 09:29:23.223058 u2DelayCellOfst[10]=10 cells (3 PI)
8531 09:29:23.226607 u2DelayCellOfst[11]=7 cells (2 PI)
8532 09:29:23.230028 u2DelayCellOfst[12]=14 cells (4 PI)
8533 09:29:23.233008 u2DelayCellOfst[13]=14 cells (4 PI)
8534 09:29:23.236525 u2DelayCellOfst[14]=17 cells (5 PI)
8535 09:29:23.237011 u2DelayCellOfst[15]=17 cells (5 PI)
8536 09:29:23.242812 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8537 09:29:23.246160 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8538 09:29:23.249554 DramC Write-DBI on
8539 09:29:23.250109 ==
8540 09:29:23.253086 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 09:29:23.255909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 09:29:23.256380 ==
8543 09:29:23.256811
8544 09:29:23.257345
8545 09:29:23.259164 TX Vref Scan disable
8546 09:29:23.259647 == TX Byte 0 ==
8547 09:29:23.265641 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8548 09:29:23.266059 == TX Byte 1 ==
8549 09:29:23.269316 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8550 09:29:23.272402 DramC Write-DBI off
8551 09:29:23.272816
8552 09:29:23.273226 [DATLAT]
8553 09:29:23.275390 Freq=1600, CH1 RK0
8554 09:29:23.275806
8555 09:29:23.276132 DATLAT Default: 0xf
8556 09:29:23.279118 0, 0xFFFF, sum = 0
8557 09:29:23.282240 1, 0xFFFF, sum = 0
8558 09:29:23.282665 2, 0xFFFF, sum = 0
8559 09:29:23.285156 3, 0xFFFF, sum = 0
8560 09:29:23.285636 4, 0xFFFF, sum = 0
8561 09:29:23.288690 5, 0xFFFF, sum = 0
8562 09:29:23.289114 6, 0xFFFF, sum = 0
8563 09:29:23.292263 7, 0xFFFF, sum = 0
8564 09:29:23.292752 8, 0xFFFF, sum = 0
8565 09:29:23.295375 9, 0xFFFF, sum = 0
8566 09:29:23.295798 10, 0xFFFF, sum = 0
8567 09:29:23.298781 11, 0xFFFF, sum = 0
8568 09:29:23.299326 12, 0xFFFF, sum = 0
8569 09:29:23.301706 13, 0xFFFF, sum = 0
8570 09:29:23.302131 14, 0x0, sum = 1
8571 09:29:23.305144 15, 0x0, sum = 2
8572 09:29:23.305607 16, 0x0, sum = 3
8573 09:29:23.308998 17, 0x0, sum = 4
8574 09:29:23.309574 best_step = 15
8575 09:29:23.309914
8576 09:29:23.310219 ==
8577 09:29:23.312082 Dram Type= 6, Freq= 0, CH_1, rank 0
8578 09:29:23.318392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8579 09:29:23.318816 ==
8580 09:29:23.319146 RX Vref Scan: 1
8581 09:29:23.319455
8582 09:29:23.322358 Set Vref Range= 24 -> 127
8583 09:29:23.322890
8584 09:29:23.325456 RX Vref 24 -> 127, step: 1
8585 09:29:23.325965
8586 09:29:23.326293 RX Delay 19 -> 252, step: 4
8587 09:29:23.328362
8588 09:29:23.328778 Set Vref, RX VrefLevel [Byte0]: 24
8589 09:29:23.332243 [Byte1]: 24
8590 09:29:23.335888
8591 09:29:23.336477 Set Vref, RX VrefLevel [Byte0]: 25
8592 09:29:23.339329 [Byte1]: 25
8593 09:29:23.343998
8594 09:29:23.344553 Set Vref, RX VrefLevel [Byte0]: 26
8595 09:29:23.346667 [Byte1]: 26
8596 09:29:23.351309
8597 09:29:23.351734 Set Vref, RX VrefLevel [Byte0]: 27
8598 09:29:23.354051 [Byte1]: 27
8599 09:29:23.359153
8600 09:29:23.359663 Set Vref, RX VrefLevel [Byte0]: 28
8601 09:29:23.362034 [Byte1]: 28
8602 09:29:23.365903
8603 09:29:23.366526 Set Vref, RX VrefLevel [Byte0]: 29
8604 09:29:23.369377 [Byte1]: 29
8605 09:29:23.373719
8606 09:29:23.374140 Set Vref, RX VrefLevel [Byte0]: 30
8607 09:29:23.377331 [Byte1]: 30
8608 09:29:23.381708
8609 09:29:23.382280 Set Vref, RX VrefLevel [Byte0]: 31
8610 09:29:23.384769 [Byte1]: 31
8611 09:29:23.389070
8612 09:29:23.389637 Set Vref, RX VrefLevel [Byte0]: 32
8613 09:29:23.392466 [Byte1]: 32
8614 09:29:23.396970
8615 09:29:23.397643 Set Vref, RX VrefLevel [Byte0]: 33
8616 09:29:23.399712 [Byte1]: 33
8617 09:29:23.404132
8618 09:29:23.404554 Set Vref, RX VrefLevel [Byte0]: 34
8619 09:29:23.407815 [Byte1]: 34
8620 09:29:23.412037
8621 09:29:23.412685 Set Vref, RX VrefLevel [Byte0]: 35
8622 09:29:23.415281 [Byte1]: 35
8623 09:29:23.419741
8624 09:29:23.420299 Set Vref, RX VrefLevel [Byte0]: 36
8625 09:29:23.422633 [Byte1]: 36
8626 09:29:23.427445
8627 09:29:23.428000 Set Vref, RX VrefLevel [Byte0]: 37
8628 09:29:23.430345 [Byte1]: 37
8629 09:29:23.434620
8630 09:29:23.435086 Set Vref, RX VrefLevel [Byte0]: 38
8631 09:29:23.437715 [Byte1]: 38
8632 09:29:23.442489
8633 09:29:23.443045 Set Vref, RX VrefLevel [Byte0]: 39
8634 09:29:23.445104 [Byte1]: 39
8635 09:29:23.449667
8636 09:29:23.450220 Set Vref, RX VrefLevel [Byte0]: 40
8637 09:29:23.453349 [Byte1]: 40
8638 09:29:23.457300
8639 09:29:23.457858 Set Vref, RX VrefLevel [Byte0]: 41
8640 09:29:23.460795 [Byte1]: 41
8641 09:29:23.464673
8642 09:29:23.465137 Set Vref, RX VrefLevel [Byte0]: 42
8643 09:29:23.468279 [Byte1]: 42
8644 09:29:23.472622
8645 09:29:23.473182 Set Vref, RX VrefLevel [Byte0]: 43
8646 09:29:23.476058 [Byte1]: 43
8647 09:29:23.480299
8648 09:29:23.480874 Set Vref, RX VrefLevel [Byte0]: 44
8649 09:29:23.483073 [Byte1]: 44
8650 09:29:23.487348
8651 09:29:23.487837 Set Vref, RX VrefLevel [Byte0]: 45
8652 09:29:23.491345 [Byte1]: 45
8653 09:29:23.494843
8654 09:29:23.495308 Set Vref, RX VrefLevel [Byte0]: 46
8655 09:29:23.498584 [Byte1]: 46
8656 09:29:23.502881
8657 09:29:23.503440 Set Vref, RX VrefLevel [Byte0]: 47
8658 09:29:23.506178 [Byte1]: 47
8659 09:29:23.509876
8660 09:29:23.510291 Set Vref, RX VrefLevel [Byte0]: 48
8661 09:29:23.513202 [Byte1]: 48
8662 09:29:23.518109
8663 09:29:23.518624 Set Vref, RX VrefLevel [Byte0]: 49
8664 09:29:23.520751 [Byte1]: 49
8665 09:29:23.524945
8666 09:29:23.525386 Set Vref, RX VrefLevel [Byte0]: 50
8667 09:29:23.528860 [Byte1]: 50
8668 09:29:23.533203
8669 09:29:23.533661 Set Vref, RX VrefLevel [Byte0]: 51
8670 09:29:23.536269 [Byte1]: 51
8671 09:29:23.540466
8672 09:29:23.540907 Set Vref, RX VrefLevel [Byte0]: 52
8673 09:29:23.543948 [Byte1]: 52
8674 09:29:23.548157
8675 09:29:23.548692 Set Vref, RX VrefLevel [Byte0]: 53
8676 09:29:23.551467 [Byte1]: 53
8677 09:29:23.555863
8678 09:29:23.556311 Set Vref, RX VrefLevel [Byte0]: 54
8679 09:29:23.558712 [Byte1]: 54
8680 09:29:23.563603
8681 09:29:23.564118 Set Vref, RX VrefLevel [Byte0]: 55
8682 09:29:23.566402 [Byte1]: 55
8683 09:29:23.570473
8684 09:29:23.570890 Set Vref, RX VrefLevel [Byte0]: 56
8685 09:29:23.574493 [Byte1]: 56
8686 09:29:23.577941
8687 09:29:23.578358 Set Vref, RX VrefLevel [Byte0]: 57
8688 09:29:23.581714 [Byte1]: 57
8689 09:29:23.585708
8690 09:29:23.586178 Set Vref, RX VrefLevel [Byte0]: 58
8691 09:29:23.589150 [Byte1]: 58
8692 09:29:23.593359
8693 09:29:23.593777 Set Vref, RX VrefLevel [Byte0]: 59
8694 09:29:23.596704 [Byte1]: 59
8695 09:29:23.600752
8696 09:29:23.601170 Set Vref, RX VrefLevel [Byte0]: 60
8697 09:29:23.604440 [Byte1]: 60
8698 09:29:23.608724
8699 09:29:23.609140 Set Vref, RX VrefLevel [Byte0]: 61
8700 09:29:23.611616 [Byte1]: 61
8701 09:29:23.616455
8702 09:29:23.616975 Set Vref, RX VrefLevel [Byte0]: 62
8703 09:29:23.619432 [Byte1]: 62
8704 09:29:23.623435
8705 09:29:23.623855 Set Vref, RX VrefLevel [Byte0]: 63
8706 09:29:23.627188 [Byte1]: 63
8707 09:29:23.631026
8708 09:29:23.631530 Set Vref, RX VrefLevel [Byte0]: 64
8709 09:29:23.634779 [Byte1]: 64
8710 09:29:23.638747
8711 09:29:23.639175 Set Vref, RX VrefLevel [Byte0]: 65
8712 09:29:23.641876 [Byte1]: 65
8713 09:29:23.646407
8714 09:29:23.646926 Set Vref, RX VrefLevel [Byte0]: 66
8715 09:29:23.649943 [Byte1]: 66
8716 09:29:23.653808
8717 09:29:23.654221 Set Vref, RX VrefLevel [Byte0]: 67
8718 09:29:23.657244 [Byte1]: 67
8719 09:29:23.661348
8720 09:29:23.661771 Set Vref, RX VrefLevel [Byte0]: 68
8721 09:29:23.664975 [Byte1]: 68
8722 09:29:23.668821
8723 09:29:23.669237 Set Vref, RX VrefLevel [Byte0]: 69
8724 09:29:23.672732 [Byte1]: 69
8725 09:29:23.676520
8726 09:29:23.676939 Set Vref, RX VrefLevel [Byte0]: 70
8727 09:29:23.679872 [Byte1]: 70
8728 09:29:23.684281
8729 09:29:23.684755 Set Vref, RX VrefLevel [Byte0]: 71
8730 09:29:23.687897 [Byte1]: 71
8731 09:29:23.691975
8732 09:29:23.692389 Final RX Vref Byte 0 = 52 to rank0
8733 09:29:23.694981 Final RX Vref Byte 1 = 62 to rank0
8734 09:29:23.698130 Final RX Vref Byte 0 = 52 to rank1
8735 09:29:23.701961 Final RX Vref Byte 1 = 62 to rank1==
8736 09:29:23.704941 Dram Type= 6, Freq= 0, CH_1, rank 0
8737 09:29:23.711778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 09:29:23.712199 ==
8739 09:29:23.712526 DQS Delay:
8740 09:29:23.712829 DQS0 = 0, DQS1 = 0
8741 09:29:23.715104 DQM Delay:
8742 09:29:23.715624 DQM0 = 132, DQM1 = 130
8743 09:29:23.718364 DQ Delay:
8744 09:29:23.721889 DQ0 =140, DQ1 =130, DQ2 =118, DQ3 =132
8745 09:29:23.725138 DQ4 =126, DQ5 =142, DQ6 =146, DQ7 =126
8746 09:29:23.728059 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8747 09:29:23.731564 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8748 09:29:23.731981
8749 09:29:23.732308
8750 09:29:23.732612
8751 09:29:23.735069 [DramC_TX_OE_Calibration] TA2
8752 09:29:23.737944 Original DQ_B0 (3 6) =30, OEN = 27
8753 09:29:23.741471 Original DQ_B1 (3 6) =30, OEN = 27
8754 09:29:23.745019 24, 0x0, End_B0=24 End_B1=24
8755 09:29:23.745580 25, 0x0, End_B0=25 End_B1=25
8756 09:29:23.747973 26, 0x0, End_B0=26 End_B1=26
8757 09:29:23.751620 27, 0x0, End_B0=27 End_B1=27
8758 09:29:23.754882 28, 0x0, End_B0=28 End_B1=28
8759 09:29:23.758005 29, 0x0, End_B0=29 End_B1=29
8760 09:29:23.758428 30, 0x0, End_B0=30 End_B1=30
8761 09:29:23.761701 31, 0x4141, End_B0=30 End_B1=30
8762 09:29:23.764835 Byte0 end_step=30 best_step=27
8763 09:29:23.768293 Byte1 end_step=30 best_step=27
8764 09:29:23.771288 Byte0 TX OE(2T, 0.5T) = (3, 3)
8765 09:29:23.774516 Byte1 TX OE(2T, 0.5T) = (3, 3)
8766 09:29:23.774933
8767 09:29:23.775257
8768 09:29:23.781428 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8769 09:29:23.784606 CH1 RK0: MR19=303, MR18=D17
8770 09:29:23.791454 CH1_RK0: MR19=0x303, MR18=0xD17, DQSOSC=398, MR23=63, INC=23, DEC=15
8771 09:29:23.791877
8772 09:29:23.794649 ----->DramcWriteLeveling(PI) begin...
8773 09:29:23.795075 ==
8774 09:29:23.797613 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 09:29:23.801324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 09:29:23.801746 ==
8777 09:29:23.804248 Write leveling (Byte 0): 24 => 24
8778 09:29:23.807604 Write leveling (Byte 1): 26 => 26
8779 09:29:23.811057 DramcWriteLeveling(PI) end<-----
8780 09:29:23.811473
8781 09:29:23.811799 ==
8782 09:29:23.814509 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 09:29:23.817989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 09:29:23.818415 ==
8785 09:29:23.820956 [Gating] SW mode calibration
8786 09:29:23.827763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8787 09:29:23.833845 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8788 09:29:23.837508 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 09:29:23.843792 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 09:29:23.847641 1 4 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
8791 09:29:23.850597 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8792 09:29:23.857483 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 09:29:23.861150 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 09:29:23.863783 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 09:29:23.870686 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 09:29:23.873793 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 09:29:23.876853 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8798 09:29:23.883710 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 1)
8799 09:29:23.887238 1 5 12 | B1->B0 | 3232 2323 | 0 0 | (0 1) (1 0)
8800 09:29:23.889669 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 09:29:23.896216 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 09:29:23.899772 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 09:29:23.903386 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 09:29:23.909654 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 09:29:23.912683 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8806 09:29:23.916194 1 6 8 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8807 09:29:23.923075 1 6 12 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
8808 09:29:23.926393 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 09:29:23.929732 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 09:29:23.936164 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 09:29:23.939746 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 09:29:23.942685 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 09:29:23.949449 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 09:29:23.952392 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8815 09:29:23.955711 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8816 09:29:23.962325 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8817 09:29:23.965382 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 09:29:23.969486 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 09:29:23.975426 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 09:29:23.978452 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 09:29:23.982282 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 09:29:23.988334 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 09:29:23.991912 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 09:29:23.995623 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 09:29:24.002146 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 09:29:24.004792 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 09:29:24.008413 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 09:29:24.014765 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 09:29:24.018225 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 09:29:24.021822 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8831 09:29:24.028104 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8832 09:29:24.031266 Total UI for P1: 0, mck2ui 16
8833 09:29:24.035242 best dqsien dly found for B0: ( 1, 9, 8)
8834 09:29:24.038152 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8835 09:29:24.041103 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 09:29:24.045252 Total UI for P1: 0, mck2ui 16
8837 09:29:24.048191 best dqsien dly found for B1: ( 1, 9, 12)
8838 09:29:24.050974 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8839 09:29:24.054578 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8840 09:29:24.054998
8841 09:29:24.060985 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8842 09:29:24.064835 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8843 09:29:24.067822 [Gating] SW calibration Done
8844 09:29:24.068246 ==
8845 09:29:24.071267 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 09:29:24.074668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 09:29:24.075111 ==
8848 09:29:24.075459 RX Vref Scan: 0
8849 09:29:24.075789
8850 09:29:24.077677 RX Vref 0 -> 0, step: 1
8851 09:29:24.078114
8852 09:29:24.080697 RX Delay 0 -> 252, step: 8
8853 09:29:24.084399 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8854 09:29:24.087713 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8855 09:29:24.093916 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8856 09:29:24.097112 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8857 09:29:24.100869 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8858 09:29:24.103870 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8859 09:29:24.107548 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8860 09:29:24.114119 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8861 09:29:24.117175 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8862 09:29:24.120826 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8863 09:29:24.123985 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8864 09:29:24.127601 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8865 09:29:24.133930 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8866 09:29:24.136761 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8867 09:29:24.140517 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8868 09:29:24.143706 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8869 09:29:24.144150 ==
8870 09:29:24.146833 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 09:29:24.153612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 09:29:24.154027 ==
8873 09:29:24.154354 DQS Delay:
8874 09:29:24.156965 DQS0 = 0, DQS1 = 0
8875 09:29:24.157546 DQM Delay:
8876 09:29:24.160261 DQM0 = 136, DQM1 = 129
8877 09:29:24.160675 DQ Delay:
8878 09:29:24.163225 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8879 09:29:24.166543 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8880 09:29:24.170392 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8881 09:29:24.173539 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8882 09:29:24.173957
8883 09:29:24.174286
8884 09:29:24.174587 ==
8885 09:29:24.176907 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 09:29:24.183215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 09:29:24.183655 ==
8888 09:29:24.183983
8889 09:29:24.184282
8890 09:29:24.184573 TX Vref Scan disable
8891 09:29:24.186410 == TX Byte 0 ==
8892 09:29:24.189608 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8893 09:29:24.196851 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8894 09:29:24.197452 == TX Byte 1 ==
8895 09:29:24.199642 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8896 09:29:24.203342 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8897 09:29:24.206934 ==
8898 09:29:24.209897 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 09:29:24.212759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 09:29:24.213181 ==
8901 09:29:24.226157
8902 09:29:24.229816 TX Vref early break, caculate TX vref
8903 09:29:24.232931 TX Vref=16, minBit 9, minWin=20, winSum=376
8904 09:29:24.236252 TX Vref=18, minBit 9, minWin=22, winSum=387
8905 09:29:24.239740 TX Vref=20, minBit 9, minWin=22, winSum=394
8906 09:29:24.242722 TX Vref=22, minBit 9, minWin=22, winSum=400
8907 09:29:24.246105 TX Vref=24, minBit 9, minWin=23, winSum=410
8908 09:29:24.253125 TX Vref=26, minBit 9, minWin=23, winSum=411
8909 09:29:24.256186 TX Vref=28, minBit 9, minWin=25, winSum=420
8910 09:29:24.259803 TX Vref=30, minBit 3, minWin=25, winSum=418
8911 09:29:24.262731 TX Vref=32, minBit 9, minWin=24, winSum=407
8912 09:29:24.265858 TX Vref=34, minBit 9, minWin=23, winSum=404
8913 09:29:24.272784 TX Vref=36, minBit 8, minWin=23, winSum=389
8914 09:29:24.275812 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 28
8915 09:29:24.276227
8916 09:29:24.279374 Final TX Range 0 Vref 28
8917 09:29:24.279841
8918 09:29:24.280167 ==
8919 09:29:24.282467 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 09:29:24.285789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 09:29:24.289131 ==
8922 09:29:24.289613
8923 09:29:24.289942
8924 09:29:24.290246 TX Vref Scan disable
8925 09:29:24.295779 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8926 09:29:24.296327 == TX Byte 0 ==
8927 09:29:24.299007 u2DelayCellOfst[0]=14 cells (4 PI)
8928 09:29:24.301890 u2DelayCellOfst[1]=10 cells (3 PI)
8929 09:29:24.305671 u2DelayCellOfst[2]=0 cells (0 PI)
8930 09:29:24.308680 u2DelayCellOfst[3]=7 cells (2 PI)
8931 09:29:24.312209 u2DelayCellOfst[4]=7 cells (2 PI)
8932 09:29:24.315183 u2DelayCellOfst[5]=14 cells (4 PI)
8933 09:29:24.318844 u2DelayCellOfst[6]=14 cells (4 PI)
8934 09:29:24.322027 u2DelayCellOfst[7]=7 cells (2 PI)
8935 09:29:24.325081 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8936 09:29:24.329006 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8937 09:29:24.331334 == TX Byte 1 ==
8938 09:29:24.334821 u2DelayCellOfst[8]=0 cells (0 PI)
8939 09:29:24.338538 u2DelayCellOfst[9]=7 cells (2 PI)
8940 09:29:24.341531 u2DelayCellOfst[10]=14 cells (4 PI)
8941 09:29:24.344380 u2DelayCellOfst[11]=7 cells (2 PI)
8942 09:29:24.347935 u2DelayCellOfst[12]=17 cells (5 PI)
8943 09:29:24.351182 u2DelayCellOfst[13]=17 cells (5 PI)
8944 09:29:24.354346 u2DelayCellOfst[14]=21 cells (6 PI)
8945 09:29:24.357772 u2DelayCellOfst[15]=21 cells (6 PI)
8946 09:29:24.361333 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8947 09:29:24.364388 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8948 09:29:24.368146 DramC Write-DBI on
8949 09:29:24.368689 ==
8950 09:29:24.371247 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 09:29:24.374492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 09:29:24.374931 ==
8953 09:29:24.375301
8954 09:29:24.375702
8955 09:29:24.377668 TX Vref Scan disable
8956 09:29:24.378092 == TX Byte 0 ==
8957 09:29:24.384493 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8958 09:29:24.384914 == TX Byte 1 ==
8959 09:29:24.390634 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8960 09:29:24.391080 DramC Write-DBI off
8961 09:29:24.391516
8962 09:29:24.392093 [DATLAT]
8963 09:29:24.393585 Freq=1600, CH1 RK1
8964 09:29:24.394022
8965 09:29:24.397324 DATLAT Default: 0xf
8966 09:29:24.397764 0, 0xFFFF, sum = 0
8967 09:29:24.400832 1, 0xFFFF, sum = 0
8968 09:29:24.401250 2, 0xFFFF, sum = 0
8969 09:29:24.404325 3, 0xFFFF, sum = 0
8970 09:29:24.404744 4, 0xFFFF, sum = 0
8971 09:29:24.407054 5, 0xFFFF, sum = 0
8972 09:29:24.407471 6, 0xFFFF, sum = 0
8973 09:29:24.410553 7, 0xFFFF, sum = 0
8974 09:29:24.410978 8, 0xFFFF, sum = 0
8975 09:29:24.414279 9, 0xFFFF, sum = 0
8976 09:29:24.414698 10, 0xFFFF, sum = 0
8977 09:29:24.417337 11, 0xFFFF, sum = 0
8978 09:29:24.417761 12, 0xFFFF, sum = 0
8979 09:29:24.420990 13, 0xFFFF, sum = 0
8980 09:29:24.421666 14, 0x0, sum = 1
8981 09:29:24.423801 15, 0x0, sum = 2
8982 09:29:24.424507 16, 0x0, sum = 3
8983 09:29:24.426850 17, 0x0, sum = 4
8984 09:29:24.427321 best_step = 15
8985 09:29:24.427838
8986 09:29:24.428328 ==
8987 09:29:24.429985 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 09:29:24.436710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 09:29:24.437191 ==
8990 09:29:24.437615 RX Vref Scan: 0
8991 09:29:24.437959
8992 09:29:24.440036 RX Vref 0 -> 0, step: 1
8993 09:29:24.440457
8994 09:29:24.443128 RX Delay 11 -> 252, step: 4
8995 09:29:24.446632 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8996 09:29:24.449605 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8997 09:29:24.456472 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8998 09:29:24.459972 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8999 09:29:24.463054 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
9000 09:29:24.466204 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9001 09:29:24.469352 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
9002 09:29:24.476379 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
9003 09:29:24.479407 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
9004 09:29:24.482527 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9005 09:29:24.486304 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9006 09:29:24.489368 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9007 09:29:24.495847 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9008 09:29:24.498972 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9009 09:29:24.502979 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9010 09:29:24.505815 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9011 09:29:24.505968 ==
9012 09:29:24.509421 Dram Type= 6, Freq= 0, CH_1, rank 1
9013 09:29:24.515714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9014 09:29:24.515949 ==
9015 09:29:24.516085 DQS Delay:
9016 09:29:24.519224 DQS0 = 0, DQS1 = 0
9017 09:29:24.519381 DQM Delay:
9018 09:29:24.522088 DQM0 = 132, DQM1 = 127
9019 09:29:24.522238 DQ Delay:
9020 09:29:24.525767 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
9021 09:29:24.528762 DQ4 =132, DQ5 =142, DQ6 =140, DQ7 =130
9022 09:29:24.532366 DQ8 =112, DQ9 =118, DQ10 =128, DQ11 =120
9023 09:29:24.535742 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9024 09:29:24.536023
9025 09:29:24.536192
9026 09:29:24.536345
9027 09:29:24.538644 [DramC_TX_OE_Calibration] TA2
9028 09:29:24.542341 Original DQ_B0 (3 6) =30, OEN = 27
9029 09:29:24.545587 Original DQ_B1 (3 6) =30, OEN = 27
9030 09:29:24.548961 24, 0x0, End_B0=24 End_B1=24
9031 09:29:24.552134 25, 0x0, End_B0=25 End_B1=25
9032 09:29:24.552629 26, 0x0, End_B0=26 End_B1=26
9033 09:29:24.556088 27, 0x0, End_B0=27 End_B1=27
9034 09:29:24.558871 28, 0x0, End_B0=28 End_B1=28
9035 09:29:24.562154 29, 0x0, End_B0=29 End_B1=29
9036 09:29:24.565612 30, 0x0, End_B0=30 End_B1=30
9037 09:29:24.566037 31, 0x5151, End_B0=30 End_B1=30
9038 09:29:24.568588 Byte0 end_step=30 best_step=27
9039 09:29:24.572020 Byte1 end_step=30 best_step=27
9040 09:29:24.575526 Byte0 TX OE(2T, 0.5T) = (3, 3)
9041 09:29:24.578299 Byte1 TX OE(2T, 0.5T) = (3, 3)
9042 09:29:24.578722
9043 09:29:24.579050
9044 09:29:24.585338 [DQSOSCAuto] RK1, (LSB)MR18= 0x1220, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
9045 09:29:24.588561 CH1 RK1: MR19=303, MR18=1220
9046 09:29:24.595066 CH1_RK1: MR19=0x303, MR18=0x1220, DQSOSC=393, MR23=63, INC=23, DEC=15
9047 09:29:24.598132 [RxdqsGatingPostProcess] freq 1600
9048 09:29:24.604971 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9049 09:29:24.608663 best DQS0 dly(2T, 0.5T) = (1, 1)
9050 09:29:24.609252 best DQS1 dly(2T, 0.5T) = (1, 1)
9051 09:29:24.611131 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9052 09:29:24.614979 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9053 09:29:24.618311 best DQS0 dly(2T, 0.5T) = (1, 1)
9054 09:29:24.621778 best DQS1 dly(2T, 0.5T) = (1, 1)
9055 09:29:24.624759 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9056 09:29:24.628378 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9057 09:29:24.631944 Pre-setting of DQS Precalculation
9058 09:29:24.638096 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9059 09:29:24.644198 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9060 09:29:24.651041 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9061 09:29:24.651610
9062 09:29:24.651975
9063 09:29:24.654187 [Calibration Summary] 3200 Mbps
9064 09:29:24.654655 CH 0, Rank 0
9065 09:29:24.657878 SW Impedance : PASS
9066 09:29:24.661084 DUTY Scan : NO K
9067 09:29:24.661688 ZQ Calibration : PASS
9068 09:29:24.664256 Jitter Meter : NO K
9069 09:29:24.667154 CBT Training : PASS
9070 09:29:24.667630 Write leveling : PASS
9071 09:29:24.670993 RX DQS gating : PASS
9072 09:29:24.673980 RX DQ/DQS(RDDQC) : PASS
9073 09:29:24.674441 TX DQ/DQS : PASS
9074 09:29:24.677164 RX DATLAT : PASS
9075 09:29:24.677767 RX DQ/DQS(Engine): PASS
9076 09:29:24.681022 TX OE : PASS
9077 09:29:24.681653 All Pass.
9078 09:29:24.682027
9079 09:29:24.684021 CH 0, Rank 1
9080 09:29:24.686926 SW Impedance : PASS
9081 09:29:24.687388 DUTY Scan : NO K
9082 09:29:24.690342 ZQ Calibration : PASS
9083 09:29:24.690805 Jitter Meter : NO K
9084 09:29:24.693566 CBT Training : PASS
9085 09:29:24.697019 Write leveling : PASS
9086 09:29:24.697566 RX DQS gating : PASS
9087 09:29:24.700524 RX DQ/DQS(RDDQC) : PASS
9088 09:29:24.703794 TX DQ/DQS : PASS
9089 09:29:24.704334 RX DATLAT : PASS
9090 09:29:24.706886 RX DQ/DQS(Engine): PASS
9091 09:29:24.709901 TX OE : PASS
9092 09:29:24.710324 All Pass.
9093 09:29:24.710655
9094 09:29:24.710966 CH 1, Rank 0
9095 09:29:24.713609 SW Impedance : PASS
9096 09:29:24.717002 DUTY Scan : NO K
9097 09:29:24.717598 ZQ Calibration : PASS
9098 09:29:24.720610 Jitter Meter : NO K
9099 09:29:24.723390 CBT Training : PASS
9100 09:29:24.723813 Write leveling : PASS
9101 09:29:24.726715 RX DQS gating : PASS
9102 09:29:24.729710 RX DQ/DQS(RDDQC) : PASS
9103 09:29:24.730132 TX DQ/DQS : PASS
9104 09:29:24.733327 RX DATLAT : PASS
9105 09:29:24.736461 RX DQ/DQS(Engine): PASS
9106 09:29:24.736885 TX OE : PASS
9107 09:29:24.740263 All Pass.
9108 09:29:24.740788
9109 09:29:24.741120 CH 1, Rank 1
9110 09:29:24.742938 SW Impedance : PASS
9111 09:29:24.743358 DUTY Scan : NO K
9112 09:29:24.746752 ZQ Calibration : PASS
9113 09:29:24.749979 Jitter Meter : NO K
9114 09:29:24.750400 CBT Training : PASS
9115 09:29:24.753175 Write leveling : PASS
9116 09:29:24.756470 RX DQS gating : PASS
9117 09:29:24.756992 RX DQ/DQS(RDDQC) : PASS
9118 09:29:24.759335 TX DQ/DQS : PASS
9119 09:29:24.762953 RX DATLAT : PASS
9120 09:29:24.763377 RX DQ/DQS(Engine): PASS
9121 09:29:24.766009 TX OE : PASS
9122 09:29:24.766434 All Pass.
9123 09:29:24.766766
9124 09:29:24.769292 DramC Write-DBI on
9125 09:29:24.773383 PER_BANK_REFRESH: Hybrid Mode
9126 09:29:24.773910 TX_TRACKING: ON
9127 09:29:24.782885 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9128 09:29:24.789060 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9129 09:29:24.795867 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9130 09:29:24.799226 [FAST_K] Save calibration result to emmc
9131 09:29:24.802257 sync common calibartion params.
9132 09:29:24.805803 sync cbt_mode0:1, 1:1
9133 09:29:24.809123 dram_init: ddr_geometry: 2
9134 09:29:24.809595 dram_init: ddr_geometry: 2
9135 09:29:24.812708 dram_init: ddr_geometry: 2
9136 09:29:24.815508 0:dram_rank_size:100000000
9137 09:29:24.818822 1:dram_rank_size:100000000
9138 09:29:24.822102 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9139 09:29:24.825173 DFS_SHUFFLE_HW_MODE: ON
9140 09:29:24.828808 dramc_set_vcore_voltage set vcore to 725000
9141 09:29:24.831735 Read voltage for 1600, 0
9142 09:29:24.832231 Vio18 = 0
9143 09:29:24.832586 Vcore = 725000
9144 09:29:24.834871 Vdram = 0
9145 09:29:24.835306 Vddq = 0
9146 09:29:24.835637 Vmddr = 0
9147 09:29:24.838660 switch to 3200 Mbps bootup
9148 09:29:24.841794 [DramcRunTimeConfig]
9149 09:29:24.842215 PHYPLL
9150 09:29:24.842548 DPM_CONTROL_AFTERK: ON
9151 09:29:24.845413 PER_BANK_REFRESH: ON
9152 09:29:24.848664 REFRESH_OVERHEAD_REDUCTION: ON
9153 09:29:24.849192 CMD_PICG_NEW_MODE: OFF
9154 09:29:24.852559 XRTWTW_NEW_MODE: ON
9155 09:29:24.855307 XRTRTR_NEW_MODE: ON
9156 09:29:24.855829 TX_TRACKING: ON
9157 09:29:24.858171 RDSEL_TRACKING: OFF
9158 09:29:24.858591 DQS Precalculation for DVFS: ON
9159 09:29:24.861676 RX_TRACKING: OFF
9160 09:29:24.862130 HW_GATING DBG: ON
9161 09:29:24.865363 ZQCS_ENABLE_LP4: ON
9162 09:29:24.865929 RX_PICG_NEW_MODE: ON
9163 09:29:24.868495 TX_PICG_NEW_MODE: ON
9164 09:29:24.871634 ENABLE_RX_DCM_DPHY: ON
9165 09:29:24.874947 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9166 09:29:24.875370 DUMMY_READ_FOR_TRACKING: OFF
9167 09:29:24.877947 !!! SPM_CONTROL_AFTERK: OFF
9168 09:29:24.881422 !!! SPM could not control APHY
9169 09:29:24.885197 IMPEDANCE_TRACKING: ON
9170 09:29:24.885650 TEMP_SENSOR: ON
9171 09:29:24.888094 HW_SAVE_FOR_SR: OFF
9172 09:29:24.888517 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9173 09:29:24.895313 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9174 09:29:24.895841 Read ODT Tracking: ON
9175 09:29:24.898147 Refresh Rate DeBounce: ON
9176 09:29:24.901358 DFS_NO_QUEUE_FLUSH: ON
9177 09:29:24.904759 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9178 09:29:24.905181 ENABLE_DFS_RUNTIME_MRW: OFF
9179 09:29:24.907770 DDR_RESERVE_NEW_MODE: ON
9180 09:29:24.910893 MR_CBT_SWITCH_FREQ: ON
9181 09:29:24.911341 =========================
9182 09:29:24.930828 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9183 09:29:24.934315 dram_init: ddr_geometry: 2
9184 09:29:24.952920 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9185 09:29:24.956022 dram_init: dram init end (result: 0)
9186 09:29:24.962225 DRAM-K: Full calibration passed in 24426 msecs
9187 09:29:24.965663 MRC: failed to locate region type 0.
9188 09:29:24.966091 DRAM rank0 size:0x100000000,
9189 09:29:24.968923 DRAM rank1 size=0x100000000
9190 09:29:24.978613 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9191 09:29:24.985223 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9192 09:29:24.991609 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9193 09:29:25.001887 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9194 09:29:25.002026 DRAM rank0 size:0x100000000,
9195 09:29:25.004848 DRAM rank1 size=0x100000000
9196 09:29:25.004978 CBMEM:
9197 09:29:25.007873 IMD: root @ 0xfffff000 254 entries.
9198 09:29:25.011506 IMD: root @ 0xffffec00 62 entries.
9199 09:29:25.014424 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9200 09:29:25.021054 WARNING: RO_VPD is uninitialized or empty.
9201 09:29:25.024322 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9202 09:29:25.032072 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9203 09:29:25.045006 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9204 09:29:25.056451 BS: romstage times (exec / console): total (unknown) / 23955 ms
9205 09:29:25.056561
9206 09:29:25.056632
9207 09:29:25.066351 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9208 09:29:25.069295 ARM64: Exception handlers installed.
9209 09:29:25.073103 ARM64: Testing exception
9210 09:29:25.076012 ARM64: Done test exception
9211 09:29:25.076162 Enumerating buses...
9212 09:29:25.079330 Show all devs... Before device enumeration.
9213 09:29:25.082944 Root Device: enabled 1
9214 09:29:25.086098 CPU_CLUSTER: 0: enabled 1
9215 09:29:25.086250 CPU: 00: enabled 1
9216 09:29:25.089050 Compare with tree...
9217 09:29:25.089201 Root Device: enabled 1
9218 09:29:25.092728 CPU_CLUSTER: 0: enabled 1
9219 09:29:25.095927 CPU: 00: enabled 1
9220 09:29:25.096128 Root Device scanning...
9221 09:29:25.099605 scan_static_bus for Root Device
9222 09:29:25.102731 CPU_CLUSTER: 0 enabled
9223 09:29:25.105870 scan_static_bus for Root Device done
9224 09:29:25.109440 scan_bus: bus Root Device finished in 8 msecs
9225 09:29:25.109745 done
9226 09:29:25.115595 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9227 09:29:25.119461 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9228 09:29:25.125934 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9229 09:29:25.129208 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9230 09:29:25.132220 Allocating resources...
9231 09:29:25.135734 Reading resources...
9232 09:29:25.138928 Root Device read_resources bus 0 link: 0
9233 09:29:25.141996 DRAM rank0 size:0x100000000,
9234 09:29:25.142150 DRAM rank1 size=0x100000000
9235 09:29:25.148330 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9236 09:29:25.148467 CPU: 00 missing read_resources
9237 09:29:25.155181 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9238 09:29:25.158500 Root Device read_resources bus 0 link: 0 done
9239 09:29:25.161894 Done reading resources.
9240 09:29:25.164994 Show resources in subtree (Root Device)...After reading.
9241 09:29:25.168159 Root Device child on link 0 CPU_CLUSTER: 0
9242 09:29:25.171801 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 09:29:25.181589 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 09:29:25.181694 CPU: 00
9245 09:29:25.187953 Root Device assign_resources, bus 0 link: 0
9246 09:29:25.191342 CPU_CLUSTER: 0 missing set_resources
9247 09:29:25.194595 Root Device assign_resources, bus 0 link: 0 done
9248 09:29:25.194707 Done setting resources.
9249 09:29:25.201223 Show resources in subtree (Root Device)...After assigning values.
9250 09:29:25.204430 Root Device child on link 0 CPU_CLUSTER: 0
9251 09:29:25.211383 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 09:29:25.218013 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 09:29:25.218220 CPU: 00
9254 09:29:25.221105 Done allocating resources.
9255 09:29:25.227803 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9256 09:29:25.228204 Enabling resources...
9257 09:29:25.231509 done.
9258 09:29:25.234607 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9259 09:29:25.237955 Initializing devices...
9260 09:29:25.238383 Root Device init
9261 09:29:25.240780 init hardware done!
9262 09:29:25.241201 0x00000018: ctrlr->caps
9263 09:29:25.244435 52.000 MHz: ctrlr->f_max
9264 09:29:25.247555 0.400 MHz: ctrlr->f_min
9265 09:29:25.251101 0x40ff8080: ctrlr->voltages
9266 09:29:25.251534 sclk: 390625
9267 09:29:25.251869 Bus Width = 1
9268 09:29:25.254185 sclk: 390625
9269 09:29:25.254622 Bus Width = 1
9270 09:29:25.257779 Early init status = 3
9271 09:29:25.260621 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9272 09:29:25.264103 in-header: 03 fc 00 00 01 00 00 00
9273 09:29:25.267346 in-data: 00
9274 09:29:25.270654 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9275 09:29:25.275140 in-header: 03 fd 00 00 00 00 00 00
9276 09:29:25.278764 in-data:
9277 09:29:25.281920 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9278 09:29:25.285698 in-header: 03 fc 00 00 01 00 00 00
9279 09:29:25.288666 in-data: 00
9280 09:29:25.292379 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9281 09:29:25.297255 in-header: 03 fd 00 00 00 00 00 00
9282 09:29:25.300254 in-data:
9283 09:29:25.303683 [SSUSB] Setting up USB HOST controller...
9284 09:29:25.306970 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9285 09:29:25.310095 [SSUSB] phy power-on done.
9286 09:29:25.313707 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9287 09:29:25.320426 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9288 09:29:25.323508 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9289 09:29:25.330161 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9290 09:29:25.336859 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9291 09:29:25.342991 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9292 09:29:25.349924 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9293 09:29:25.356593 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9294 09:29:25.359569 SPM: binary array size = 0x9dc
9295 09:29:25.363333 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9296 09:29:25.369352 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9297 09:29:25.376152 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9298 09:29:25.382516 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9299 09:29:25.385775 configure_display: Starting display init
9300 09:29:25.420291 anx7625_power_on_init: Init interface.
9301 09:29:25.423713 anx7625_disable_pd_protocol: Disabled PD feature.
9302 09:29:25.426921 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9303 09:29:25.454659 anx7625_start_dp_work: Secure OCM version=00
9304 09:29:25.458067 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9305 09:29:25.472622 sp_tx_get_edid_block: EDID Block = 1
9306 09:29:25.575373 Extracted contents:
9307 09:29:25.578473 header: 00 ff ff ff ff ff ff 00
9308 09:29:25.582238 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9309 09:29:25.585233 version: 01 04
9310 09:29:25.588313 basic params: 95 1f 11 78 0a
9311 09:29:25.592157 chroma info: 76 90 94 55 54 90 27 21 50 54
9312 09:29:25.595313 established: 00 00 00
9313 09:29:25.601815 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9314 09:29:25.608362 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9315 09:29:25.611835 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9316 09:29:25.618321 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9317 09:29:25.624560 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9318 09:29:25.628298 extensions: 00
9319 09:29:25.628713 checksum: fb
9320 09:29:25.629040
9321 09:29:25.634364 Manufacturer: IVO Model 57d Serial Number 0
9322 09:29:25.634788 Made week 0 of 2020
9323 09:29:25.638018 EDID version: 1.4
9324 09:29:25.638435 Digital display
9325 09:29:25.640952 6 bits per primary color channel
9326 09:29:25.644423 DisplayPort interface
9327 09:29:25.644842 Maximum image size: 31 cm x 17 cm
9328 09:29:25.647829 Gamma: 220%
9329 09:29:25.648484 Check DPMS levels
9330 09:29:25.654428 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9331 09:29:25.657667 First detailed timing is preferred timing
9332 09:29:25.661218 Established timings supported:
9333 09:29:25.661680 Standard timings supported:
9334 09:29:25.664402 Detailed timings
9335 09:29:25.667321 Hex of detail: 383680a07038204018303c0035ae10000019
9336 09:29:25.674317 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9337 09:29:25.677951 0780 0798 07c8 0820 hborder 0
9338 09:29:25.680525 0438 043b 0447 0458 vborder 0
9339 09:29:25.684066 -hsync -vsync
9340 09:29:25.684486 Did detailed timing
9341 09:29:25.690697 Hex of detail: 000000000000000000000000000000000000
9342 09:29:25.693802 Manufacturer-specified data, tag 0
9343 09:29:25.696871 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9344 09:29:25.700603 ASCII string: InfoVision
9345 09:29:25.703767 Hex of detail: 000000fe00523134304e574635205248200a
9346 09:29:25.706882 ASCII string: R140NWF5 RH
9347 09:29:25.707301 Checksum
9348 09:29:25.709939 Checksum: 0xfb (valid)
9349 09:29:25.713671 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9350 09:29:25.716679 DSI data_rate: 832800000 bps
9351 09:29:25.723816 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9352 09:29:25.726484 anx7625_parse_edid: pixelclock(138800).
9353 09:29:25.730103 hactive(1920), hsync(48), hfp(24), hbp(88)
9354 09:29:25.733294 vactive(1080), vsync(12), vfp(3), vbp(17)
9355 09:29:25.736671 anx7625_dsi_config: config dsi.
9356 09:29:25.743649 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9357 09:29:25.757144 anx7625_dsi_config: success to config DSI
9358 09:29:25.760754 anx7625_dp_start: MIPI phy setup OK.
9359 09:29:25.764168 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9360 09:29:25.767264 mtk_ddp_mode_set invalid vrefresh 60
9361 09:29:25.770530 main_disp_path_setup
9362 09:29:25.771165 ovl_layer_smi_id_en
9363 09:29:25.774112 ovl_layer_smi_id_en
9364 09:29:25.774735 ccorr_config
9365 09:29:25.775314 aal_config
9366 09:29:25.776961 gamma_config
9367 09:29:25.777491 postmask_config
9368 09:29:25.780650 dither_config
9369 09:29:25.783542 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9370 09:29:25.790467 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9371 09:29:25.793848 Root Device init finished in 552 msecs
9372 09:29:25.796801 CPU_CLUSTER: 0 init
9373 09:29:25.803918 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9374 09:29:25.810009 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9375 09:29:25.810427 APU_MBOX 0x190000b0 = 0x10001
9376 09:29:25.813793 APU_MBOX 0x190001b0 = 0x10001
9377 09:29:25.816690 APU_MBOX 0x190005b0 = 0x10001
9378 09:29:25.820736 APU_MBOX 0x190006b0 = 0x10001
9379 09:29:25.826551 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9380 09:29:25.836985 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9381 09:29:25.849018 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9382 09:29:25.855786 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9383 09:29:25.867617 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9384 09:29:25.876393 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9385 09:29:25.879747 CPU_CLUSTER: 0 init finished in 81 msecs
9386 09:29:25.882777 Devices initialized
9387 09:29:25.885985 Show all devs... After init.
9388 09:29:25.886400 Root Device: enabled 1
9389 09:29:25.890096 CPU_CLUSTER: 0: enabled 1
9390 09:29:25.892540 CPU: 00: enabled 1
9391 09:29:25.895936 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9392 09:29:25.899668 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9393 09:29:25.902821 ELOG: NV offset 0x57f000 size 0x1000
9394 09:29:25.909446 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9395 09:29:25.916298 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9396 09:29:25.919831 ELOG: Event(17) added with size 13 at 2024-06-18 09:29:25 UTC
9397 09:29:25.922574 out: cmd=0x121: 03 db 21 01 00 00 00 00
9398 09:29:25.926435 in-header: 03 ed 00 00 2c 00 00 00
9399 09:29:25.939859 in-data: 50 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9400 09:29:25.946780 ELOG: Event(A1) added with size 10 at 2024-06-18 09:29:25 UTC
9401 09:29:25.953159 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9402 09:29:25.959319 ELOG: Event(A0) added with size 9 at 2024-06-18 09:29:25 UTC
9403 09:29:25.962742 elog_add_boot_reason: Logged dev mode boot
9404 09:29:25.965942 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9405 09:29:25.969691 Finalize devices...
9406 09:29:25.970218 Devices finalized
9407 09:29:25.976201 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9408 09:29:25.979385 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9409 09:29:25.983021 in-header: 03 07 00 00 08 00 00 00
9410 09:29:25.985679 in-data: aa e4 47 04 13 02 00 00
9411 09:29:25.989166 Chrome EC: UHEPI supported
9412 09:29:25.996255 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9413 09:29:25.999153 in-header: 03 a9 00 00 08 00 00 00
9414 09:29:26.002844 in-data: 84 60 60 08 00 00 00 00
9415 09:29:26.008915 ELOG: Event(91) added with size 10 at 2024-06-18 09:29:25 UTC
9416 09:29:26.012584 Chrome EC: clear events_b mask to 0x0000000020004000
9417 09:29:26.019706 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9418 09:29:26.022721 in-header: 03 fd 00 00 00 00 00 00
9419 09:29:26.025898 in-data:
9420 09:29:26.029636 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9421 09:29:26.032724 Writing coreboot table at 0xffe64000
9422 09:29:26.035949 0. 000000000010a000-0000000000113fff: RAMSTAGE
9423 09:29:26.043082 1. 0000000040000000-00000000400fffff: RAM
9424 09:29:26.045914 2. 0000000040100000-000000004032afff: RAMSTAGE
9425 09:29:26.049142 3. 000000004032b000-00000000545fffff: RAM
9426 09:29:26.052273 4. 0000000054600000-000000005465ffff: BL31
9427 09:29:26.055963 5. 0000000054660000-00000000ffe63fff: RAM
9428 09:29:26.062223 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9429 09:29:26.065157 7. 0000000100000000-000000023fffffff: RAM
9430 09:29:26.068809 Passing 5 GPIOs to payload:
9431 09:29:26.072299 NAME | PORT | POLARITY | VALUE
9432 09:29:26.078609 EC in RW | 0x000000aa | low | undefined
9433 09:29:26.081855 EC interrupt | 0x00000005 | low | undefined
9434 09:29:26.088595 TPM interrupt | 0x000000ab | high | undefined
9435 09:29:26.091932 SD card detect | 0x00000011 | high | undefined
9436 09:29:26.095076 speaker enable | 0x00000093 | high | undefined
9437 09:29:26.098273 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9438 09:29:26.101925 in-header: 03 f9 00 00 02 00 00 00
9439 09:29:26.104838 in-data: 02 00
9440 09:29:26.108483 ADC[4]: Raw value=902955 ID=7
9441 09:29:26.111735 ADC[3]: Raw value=213916 ID=1
9442 09:29:26.112159 RAM Code: 0x71
9443 09:29:26.115256 ADC[6]: Raw value=75000 ID=0
9444 09:29:26.118568 ADC[5]: Raw value=213546 ID=1
9445 09:29:26.119082 SKU Code: 0x1
9446 09:29:26.125342 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7f3c
9447 09:29:26.125866 coreboot table: 964 bytes.
9448 09:29:26.128138 IMD ROOT 0. 0xfffff000 0x00001000
9449 09:29:26.131609 IMD SMALL 1. 0xffffe000 0x00001000
9450 09:29:26.134510 RO MCACHE 2. 0xffffc000 0x00001104
9451 09:29:26.138254 CONSOLE 3. 0xfff7c000 0x00080000
9452 09:29:26.141494 FMAP 4. 0xfff7b000 0x00000452
9453 09:29:26.145524 TIME STAMP 5. 0xfff7a000 0x00000910
9454 09:29:26.148048 VBOOT WORK 6. 0xfff66000 0x00014000
9455 09:29:26.151467 RAMOOPS 7. 0xffe66000 0x00100000
9456 09:29:26.154864 COREBOOT 8. 0xffe64000 0x00002000
9457 09:29:26.157852 IMD small region:
9458 09:29:26.161196 IMD ROOT 0. 0xffffec00 0x00000400
9459 09:29:26.164683 VPD 1. 0xffffeb80 0x0000006c
9460 09:29:26.167963 MMC STATUS 2. 0xffffeb60 0x00000004
9461 09:29:26.174236 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9462 09:29:26.180747 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9463 09:29:26.220123 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9464 09:29:26.222437 Checking segment from ROM address 0x40100000
9465 09:29:26.226434 Checking segment from ROM address 0x4010001c
9466 09:29:26.232803 Loading segment from ROM address 0x40100000
9467 09:29:26.233561 code (compression=0)
9468 09:29:26.242392 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9469 09:29:26.248639 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9470 09:29:26.252332 it's not compressed!
9471 09:29:26.255432 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9472 09:29:26.261728 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9473 09:29:26.279550 Loading segment from ROM address 0x4010001c
9474 09:29:26.280065 Entry Point 0x80000000
9475 09:29:26.283115 Loaded segments
9476 09:29:26.286222 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9477 09:29:26.293130 Jumping to boot code at 0x80000000(0xffe64000)
9478 09:29:26.299415 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9479 09:29:26.306244 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9480 09:29:26.313996 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9481 09:29:26.317203 Checking segment from ROM address 0x40100000
9482 09:29:26.320756 Checking segment from ROM address 0x4010001c
9483 09:29:26.327139 Loading segment from ROM address 0x40100000
9484 09:29:26.327577 code (compression=1)
9485 09:29:26.334153 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9486 09:29:26.343731 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9487 09:29:26.344152 using LZMA
9488 09:29:26.352262 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9489 09:29:26.359188 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9490 09:29:26.362380 Loading segment from ROM address 0x4010001c
9491 09:29:26.362793 Entry Point 0x54601000
9492 09:29:26.365374 Loaded segments
9493 09:29:26.368579 NOTICE: MT8192 bl31_setup
9494 09:29:26.375975 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9495 09:29:26.379598 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9496 09:29:26.382991 WARNING: region 0:
9497 09:29:26.385915 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 09:29:26.386342 WARNING: region 1:
9499 09:29:26.392399 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9500 09:29:26.395953 WARNING: region 2:
9501 09:29:26.399367 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9502 09:29:26.402171 WARNING: region 3:
9503 09:29:26.408844 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9504 09:29:26.409309 WARNING: region 4:
9505 09:29:26.415427 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9506 09:29:26.415853 WARNING: region 5:
9507 09:29:26.419116 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 09:29:26.422048 WARNING: region 6:
9509 09:29:26.425691 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 09:29:26.428725 WARNING: region 7:
9511 09:29:26.431775 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 09:29:26.438476 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9513 09:29:26.442280 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9514 09:29:26.448928 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9515 09:29:26.451735 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9516 09:29:26.455710 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9517 09:29:26.461588 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9518 09:29:26.465439 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9519 09:29:26.468162 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9520 09:29:26.475034 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9521 09:29:26.477906 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9522 09:29:26.484595 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9523 09:29:26.487793 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9524 09:29:26.490994 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9525 09:29:26.497824 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9526 09:29:26.501244 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9527 09:29:26.507260 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9528 09:29:26.510586 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9529 09:29:26.514339 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9530 09:29:26.520625 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9531 09:29:26.524082 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9532 09:29:26.530802 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9533 09:29:26.533976 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9534 09:29:26.537540 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9535 09:29:26.543888 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9536 09:29:26.547381 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9537 09:29:26.553911 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9538 09:29:26.557309 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9539 09:29:26.560427 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9540 09:29:26.566729 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9541 09:29:26.570605 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9542 09:29:26.576352 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9543 09:29:26.580293 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9544 09:29:26.583571 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9545 09:29:26.589902 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9546 09:29:26.593215 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9547 09:29:26.596445 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9548 09:29:26.600230 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9549 09:29:26.606362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9550 09:29:26.609626 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9551 09:29:26.612845 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9552 09:29:26.616231 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9553 09:29:26.622800 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9554 09:29:26.626050 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9555 09:29:26.629669 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9556 09:29:26.632992 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9557 09:29:26.639435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9558 09:29:26.642916 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9559 09:29:26.645932 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9560 09:29:26.652915 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9561 09:29:26.655933 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9562 09:29:26.662555 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9563 09:29:26.666197 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9564 09:29:26.669049 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9565 09:29:26.676249 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9566 09:29:26.679703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9567 09:29:26.685664 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9568 09:29:26.688999 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9569 09:29:26.696270 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9570 09:29:26.699008 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9571 09:29:26.705471 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9572 09:29:26.709413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9573 09:29:26.715620 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9574 09:29:26.718375 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9575 09:29:26.721985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9576 09:29:26.728779 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9577 09:29:26.731539 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9578 09:29:26.738279 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9579 09:29:26.741687 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9580 09:29:26.747987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9581 09:29:26.751628 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9582 09:29:26.757771 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9583 09:29:26.761317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9584 09:29:26.764488 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9585 09:29:26.771664 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9586 09:29:26.774740 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9587 09:29:26.781117 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9588 09:29:26.784401 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9589 09:29:26.791056 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9590 09:29:26.794255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9591 09:29:26.800841 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9592 09:29:26.804552 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9593 09:29:26.810953 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9594 09:29:26.813816 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9595 09:29:26.817757 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9596 09:29:26.823682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9597 09:29:26.827533 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9598 09:29:26.834288 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9599 09:29:26.837369 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9600 09:29:26.844272 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9601 09:29:26.846912 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9602 09:29:26.853997 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9603 09:29:26.857335 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9604 09:29:26.860638 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9605 09:29:26.866932 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9606 09:29:26.870889 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9607 09:29:26.877115 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9608 09:29:26.880375 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9609 09:29:26.883504 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9610 09:29:26.890194 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9611 09:29:26.893093 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9612 09:29:26.896055 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9613 09:29:26.903537 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9614 09:29:26.907043 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9615 09:29:26.909675 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9616 09:29:26.916190 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9617 09:29:26.919453 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9618 09:29:26.926178 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9619 09:29:26.929967 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9620 09:29:26.932827 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9621 09:29:26.939871 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9622 09:29:26.942763 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9623 09:29:26.949117 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9624 09:29:26.952852 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9625 09:29:26.959486 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9626 09:29:26.962121 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9627 09:29:26.965699 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9628 09:29:26.969086 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9629 09:29:26.975698 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9630 09:29:26.979048 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9631 09:29:26.985614 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9632 09:29:26.988770 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9633 09:29:26.991861 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9634 09:29:26.995163 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9635 09:29:27.002161 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9636 09:29:27.005359 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9637 09:29:27.008440 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9638 09:29:27.014899 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9639 09:29:27.018150 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9640 09:29:27.024952 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9641 09:29:27.027906 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9642 09:29:27.031390 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9643 09:29:27.037853 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9644 09:29:27.041415 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9645 09:29:27.048173 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9646 09:29:27.050659 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9647 09:29:27.054450 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9648 09:29:27.061130 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9649 09:29:27.064190 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9650 09:29:27.070554 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9651 09:29:27.073677 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9652 09:29:27.077181 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9653 09:29:27.083626 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9654 09:29:27.086680 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9655 09:29:27.093284 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9656 09:29:27.096628 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9657 09:29:27.099789 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9658 09:29:27.106394 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9659 09:29:27.110013 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9660 09:29:27.116157 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9661 09:29:27.119890 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9662 09:29:27.133861 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9663 09:29:27.134040 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9664 09:29:27.134134 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9665 09:29:27.139704 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9666 09:29:27.142529 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9667 09:29:27.149490 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9668 09:29:27.152703 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9669 09:29:27.156003 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9670 09:29:27.162451 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9671 09:29:27.165998 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9672 09:29:27.169063 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9673 09:29:27.175917 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9674 09:29:27.179444 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9675 09:29:27.186105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9676 09:29:27.189187 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9677 09:29:27.192318 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9678 09:29:27.199005 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9679 09:29:27.202132 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9680 09:29:27.209080 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9681 09:29:27.212692 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9682 09:29:27.215357 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9683 09:29:27.221835 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9684 09:29:27.225110 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9685 09:29:27.232047 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9686 09:29:27.235141 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9687 09:29:27.238249 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9688 09:29:27.244951 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9689 09:29:27.248732 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9690 09:29:27.255038 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9691 09:29:27.258550 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9692 09:29:27.261950 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9693 09:29:27.268286 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9694 09:29:27.271628 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9695 09:29:27.278523 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9696 09:29:27.281928 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9697 09:29:27.285388 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9698 09:29:27.292203 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9699 09:29:27.295505 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9700 09:29:27.301989 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9701 09:29:27.305227 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9702 09:29:27.308167 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9703 09:29:27.315061 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9704 09:29:27.318600 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9705 09:29:27.325136 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9706 09:29:27.328831 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9707 09:29:27.334486 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9708 09:29:27.337837 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9709 09:29:27.341400 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9710 09:29:27.348313 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9711 09:29:27.351397 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9712 09:29:27.358124 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9713 09:29:27.360915 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9714 09:29:27.367577 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9715 09:29:27.370578 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9716 09:29:27.377217 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9717 09:29:27.380651 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9718 09:29:27.384196 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9719 09:29:27.390599 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9720 09:29:27.393475 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9721 09:29:27.399991 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9722 09:29:27.403704 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9723 09:29:27.406818 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9724 09:29:27.413635 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9725 09:29:27.416677 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9726 09:29:27.423409 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9727 09:29:27.426383 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9728 09:29:27.433214 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9729 09:29:27.436281 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9730 09:29:27.439842 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9731 09:29:27.446445 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9732 09:29:27.449606 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9733 09:29:27.456247 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9734 09:29:27.459595 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9735 09:29:27.466210 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9736 09:29:27.469733 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9737 09:29:27.473057 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9738 09:29:27.480293 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9739 09:29:27.483132 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9740 09:29:27.489321 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9741 09:29:27.493050 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9742 09:29:27.496011 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9743 09:29:27.499426 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9744 09:29:27.505745 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9745 09:29:27.509197 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9746 09:29:27.512441 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9747 09:29:27.519354 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9748 09:29:27.522535 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9749 09:29:27.529085 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9750 09:29:27.532440 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9751 09:29:27.535702 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9752 09:29:27.541995 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9753 09:29:27.545766 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9754 09:29:27.548862 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9755 09:29:27.555059 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9756 09:29:27.558585 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9757 09:29:27.561789 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9758 09:29:27.568527 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9759 09:29:27.571773 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9760 09:29:27.575390 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9761 09:29:27.581777 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9762 09:29:27.585026 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9763 09:29:27.592104 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9764 09:29:27.594999 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9765 09:29:27.597982 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9766 09:29:27.604893 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9767 09:29:27.608170 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9768 09:29:27.614839 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9769 09:29:27.617825 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9770 09:29:27.621468 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9771 09:29:27.628270 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9772 09:29:27.631303 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9773 09:29:27.634679 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9774 09:29:27.641032 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9775 09:29:27.644125 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9776 09:29:27.650803 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9777 09:29:27.654502 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9778 09:29:27.657747 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9779 09:29:27.663963 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9780 09:29:27.667789 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9781 09:29:27.670837 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9782 09:29:27.674041 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9783 09:29:27.680697 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9784 09:29:27.683764 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9785 09:29:27.687176 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9786 09:29:27.690577 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9787 09:29:27.697381 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9788 09:29:27.701148 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9789 09:29:27.704194 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9790 09:29:27.707010 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9791 09:29:27.714135 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9792 09:29:27.717034 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9793 09:29:27.720057 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9794 09:29:27.726701 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9795 09:29:27.730638 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9796 09:29:27.737197 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9797 09:29:27.739879 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9798 09:29:27.746506 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9799 09:29:27.749894 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9800 09:29:27.753190 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9801 09:29:27.760070 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9802 09:29:27.763120 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9803 09:29:27.769632 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9804 09:29:27.773361 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9805 09:29:27.776381 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9806 09:29:27.783219 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9807 09:29:27.785924 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9808 09:29:27.792949 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9809 09:29:27.796050 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9810 09:29:27.799464 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9811 09:29:27.805766 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9812 09:29:27.809035 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9813 09:29:27.815814 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9814 09:29:27.819011 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9815 09:29:27.826093 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9816 09:29:27.829057 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9817 09:29:27.832726 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9818 09:29:27.838645 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9819 09:29:27.842092 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9820 09:29:27.848972 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9821 09:29:27.852304 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9822 09:29:27.858822 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9823 09:29:27.861679 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9824 09:29:27.865243 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9825 09:29:27.872382 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9826 09:29:27.875069 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9827 09:29:27.882084 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9828 09:29:27.885416 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9829 09:29:27.888458 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9830 09:29:27.894896 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9831 09:29:27.898557 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9832 09:29:27.905102 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9833 09:29:27.907937 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9834 09:29:27.911243 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9835 09:29:27.917996 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9836 09:29:27.921467 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9837 09:29:27.928013 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9838 09:29:27.931655 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9839 09:29:27.938166 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9840 09:29:27.941066 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9841 09:29:27.944434 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9842 09:29:27.951225 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9843 09:29:27.954295 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9844 09:29:27.960704 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9845 09:29:27.964241 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9846 09:29:27.971261 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9847 09:29:27.974471 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9848 09:29:27.977713 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9849 09:29:27.984398 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9850 09:29:27.987488 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9851 09:29:27.994284 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9852 09:29:27.997438 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9853 09:29:28.001042 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9854 09:29:28.007055 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9855 09:29:28.010460 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9856 09:29:28.016759 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9857 09:29:28.020297 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9858 09:29:28.026612 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9859 09:29:28.029983 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9860 09:29:28.033567 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9861 09:29:28.040187 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9862 09:29:28.043241 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9863 09:29:28.049862 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9864 09:29:28.053559 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9865 09:29:28.056252 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9866 09:29:28.063012 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9867 09:29:28.066261 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9868 09:29:28.073167 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9869 09:29:28.076597 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9870 09:29:28.082706 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9871 09:29:28.086444 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9872 09:29:28.092680 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9873 09:29:28.096355 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9874 09:29:28.099346 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9875 09:29:28.106033 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9876 09:29:28.108968 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9877 09:29:28.115845 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9878 09:29:28.119253 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9879 09:29:28.125719 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9880 09:29:28.129057 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9881 09:29:28.135299 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9882 09:29:28.138718 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9883 09:29:28.141767 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9884 09:29:28.148549 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9885 09:29:28.152114 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9886 09:29:28.158292 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9887 09:29:28.161799 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9888 09:29:28.168664 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9889 09:29:28.171526 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9890 09:29:28.178224 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9891 09:29:28.181076 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9892 09:29:28.187570 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9893 09:29:28.190974 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9894 09:29:28.194115 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9895 09:29:28.200956 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9896 09:29:28.204092 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9897 09:29:28.211400 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9898 09:29:28.214232 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9899 09:29:28.220870 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9900 09:29:28.224910 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9901 09:29:28.231037 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9902 09:29:28.234181 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9903 09:29:28.237233 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9904 09:29:28.243889 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9905 09:29:28.247795 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9906 09:29:28.254193 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9907 09:29:28.257118 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9908 09:29:28.264189 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9909 09:29:28.267950 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9910 09:29:28.274185 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9911 09:29:28.277161 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9912 09:29:28.280813 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9913 09:29:28.287806 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9914 09:29:28.290562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9915 09:29:28.296672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9916 09:29:28.300267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9917 09:29:28.307061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9918 09:29:28.310340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9919 09:29:28.314013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9920 09:29:28.320876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9921 09:29:28.323729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9922 09:29:28.330311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9923 09:29:28.333823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9924 09:29:28.340286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9925 09:29:28.343449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9926 09:29:28.349704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9927 09:29:28.353235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9928 09:29:28.360289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9929 09:29:28.363285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9930 09:29:28.369692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9931 09:29:28.372965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9932 09:29:28.380248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9933 09:29:28.382640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9934 09:29:28.389961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9935 09:29:28.393003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9936 09:29:28.399629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9937 09:29:28.403090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9938 09:29:28.409824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9939 09:29:28.412736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9940 09:29:28.419541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9941 09:29:28.422932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9942 09:29:28.429759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9943 09:29:28.432727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9944 09:29:28.439475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9945 09:29:28.442863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9946 09:29:28.449028 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9947 09:29:28.449474 INFO: [APUAPC] vio 0
9948 09:29:28.455657 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9949 09:29:28.459662 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9950 09:29:28.462773 INFO: [APUAPC] D0_APC_0: 0x400510
9951 09:29:28.465676 INFO: [APUAPC] D0_APC_1: 0x0
9952 09:29:28.469376 INFO: [APUAPC] D0_APC_2: 0x1540
9953 09:29:28.472412 INFO: [APUAPC] D0_APC_3: 0x0
9954 09:29:28.475963 INFO: [APUAPC] D1_APC_0: 0xffffffff
9955 09:29:28.479328 INFO: [APUAPC] D1_APC_1: 0xffffffff
9956 09:29:28.482710 INFO: [APUAPC] D1_APC_2: 0x3fffff
9957 09:29:28.485463 INFO: [APUAPC] D1_APC_3: 0x0
9958 09:29:28.489323 INFO: [APUAPC] D2_APC_0: 0xffffffff
9959 09:29:28.492462 INFO: [APUAPC] D2_APC_1: 0xffffffff
9960 09:29:28.495639 INFO: [APUAPC] D2_APC_2: 0x3fffff
9961 09:29:28.499359 INFO: [APUAPC] D2_APC_3: 0x0
9962 09:29:28.502309 INFO: [APUAPC] D3_APC_0: 0xffffffff
9963 09:29:28.505840 INFO: [APUAPC] D3_APC_1: 0xffffffff
9964 09:29:28.509050 INFO: [APUAPC] D3_APC_2: 0x3fffff
9965 09:29:28.512315 INFO: [APUAPC] D3_APC_3: 0x0
9966 09:29:28.515418 INFO: [APUAPC] D4_APC_0: 0xffffffff
9967 09:29:28.518842 INFO: [APUAPC] D4_APC_1: 0xffffffff
9968 09:29:28.521943 INFO: [APUAPC] D4_APC_2: 0x3fffff
9969 09:29:28.525390 INFO: [APUAPC] D4_APC_3: 0x0
9970 09:29:28.528866 INFO: [APUAPC] D5_APC_0: 0xffffffff
9971 09:29:28.532286 INFO: [APUAPC] D5_APC_1: 0xffffffff
9972 09:29:28.535530 INFO: [APUAPC] D5_APC_2: 0x3fffff
9973 09:29:28.538591 INFO: [APUAPC] D5_APC_3: 0x0
9974 09:29:28.542152 INFO: [APUAPC] D6_APC_0: 0xffffffff
9975 09:29:28.545336 INFO: [APUAPC] D6_APC_1: 0xffffffff
9976 09:29:28.548733 INFO: [APUAPC] D6_APC_2: 0x3fffff
9977 09:29:28.549358 INFO: [APUAPC] D6_APC_3: 0x0
9978 09:29:28.555092 INFO: [APUAPC] D7_APC_0: 0xffffffff
9979 09:29:28.558025 INFO: [APUAPC] D7_APC_1: 0xffffffff
9980 09:29:28.561626 INFO: [APUAPC] D7_APC_2: 0x3fffff
9981 09:29:28.562297 INFO: [APUAPC] D7_APC_3: 0x0
9982 09:29:28.565195 INFO: [APUAPC] D8_APC_0: 0xffffffff
9983 09:29:28.571609 INFO: [APUAPC] D8_APC_1: 0xffffffff
9984 09:29:28.572032 INFO: [APUAPC] D8_APC_2: 0x3fffff
9985 09:29:28.574953 INFO: [APUAPC] D8_APC_3: 0x0
9986 09:29:28.578335 INFO: [APUAPC] D9_APC_0: 0xffffffff
9987 09:29:28.581546 INFO: [APUAPC] D9_APC_1: 0xffffffff
9988 09:29:28.584816 INFO: [APUAPC] D9_APC_2: 0x3fffff
9989 09:29:28.587959 INFO: [APUAPC] D9_APC_3: 0x0
9990 09:29:28.591669 INFO: [APUAPC] D10_APC_0: 0xffffffff
9991 09:29:28.594451 INFO: [APUAPC] D10_APC_1: 0xffffffff
9992 09:29:28.600651 INFO: [APUAPC] D10_APC_2: 0x3fffff
9993 09:29:28.601078 INFO: [APUAPC] D10_APC_3: 0x0
9994 09:29:28.604304 INFO: [APUAPC] D11_APC_0: 0xffffffff
9995 09:29:28.610593 INFO: [APUAPC] D11_APC_1: 0xffffffff
9996 09:29:28.614050 INFO: [APUAPC] D11_APC_2: 0x3fffff
9997 09:29:28.614495 INFO: [APUAPC] D11_APC_3: 0x0
9998 09:29:28.620470 INFO: [APUAPC] D12_APC_0: 0xffffffff
9999 09:29:28.623976 INFO: [APUAPC] D12_APC_1: 0xffffffff
10000 09:29:28.627211 INFO: [APUAPC] D12_APC_2: 0x3fffff
10001 09:29:28.630253 INFO: [APUAPC] D12_APC_3: 0x0
10002 09:29:28.633816 INFO: [APUAPC] D13_APC_0: 0xffffffff
10003 09:29:28.636621 INFO: [APUAPC] D13_APC_1: 0xffffffff
10004 09:29:28.640415 INFO: [APUAPC] D13_APC_2: 0x3fffff
10005 09:29:28.643462 INFO: [APUAPC] D13_APC_3: 0x0
10006 09:29:28.646674 INFO: [APUAPC] D14_APC_0: 0xffffffff
10007 09:29:28.650062 INFO: [APUAPC] D14_APC_1: 0xffffffff
10008 09:29:28.653693 INFO: [APUAPC] D14_APC_2: 0x3fffff
10009 09:29:28.656962 INFO: [APUAPC] D14_APC_3: 0x0
10010 09:29:28.659956 INFO: [APUAPC] D15_APC_0: 0xffffffff
10011 09:29:28.663680 INFO: [APUAPC] D15_APC_1: 0xffffffff
10012 09:29:28.666640 INFO: [APUAPC] D15_APC_2: 0x3fffff
10013 09:29:28.669495 INFO: [APUAPC] D15_APC_3: 0x0
10014 09:29:28.673120 INFO: [APUAPC] APC_CON: 0x4
10015 09:29:28.673427 INFO: [NOCDAPC] D0_APC_0: 0x0
10016 09:29:28.676609 INFO: [NOCDAPC] D0_APC_1: 0x0
10017 09:29:28.679625 INFO: [NOCDAPC] D1_APC_0: 0x0
10018 09:29:28.683311 INFO: [NOCDAPC] D1_APC_1: 0xfff
10019 09:29:28.686401 INFO: [NOCDAPC] D2_APC_0: 0x0
10020 09:29:28.689634 INFO: [NOCDAPC] D2_APC_1: 0xfff
10021 09:29:28.692747 INFO: [NOCDAPC] D3_APC_0: 0x0
10022 09:29:28.696547 INFO: [NOCDAPC] D3_APC_1: 0xfff
10023 09:29:28.699621 INFO: [NOCDAPC] D4_APC_0: 0x0
10024 09:29:28.702700 INFO: [NOCDAPC] D4_APC_1: 0xfff
10025 09:29:28.706004 INFO: [NOCDAPC] D5_APC_0: 0x0
10026 09:29:28.709382 INFO: [NOCDAPC] D5_APC_1: 0xfff
10027 09:29:28.709799 INFO: [NOCDAPC] D6_APC_0: 0x0
10028 09:29:28.712895 INFO: [NOCDAPC] D6_APC_1: 0xfff
10029 09:29:28.716304 INFO: [NOCDAPC] D7_APC_0: 0x0
10030 09:29:28.719354 INFO: [NOCDAPC] D7_APC_1: 0xfff
10031 09:29:28.722821 INFO: [NOCDAPC] D8_APC_0: 0x0
10032 09:29:28.726019 INFO: [NOCDAPC] D8_APC_1: 0xfff
10033 09:29:28.729436 INFO: [NOCDAPC] D9_APC_0: 0x0
10034 09:29:28.732688 INFO: [NOCDAPC] D9_APC_1: 0xfff
10035 09:29:28.735888 INFO: [NOCDAPC] D10_APC_0: 0x0
10036 09:29:28.739250 INFO: [NOCDAPC] D10_APC_1: 0xfff
10037 09:29:28.742752 INFO: [NOCDAPC] D11_APC_0: 0x0
10038 09:29:28.745785 INFO: [NOCDAPC] D11_APC_1: 0xfff
10039 09:29:28.746202 INFO: [NOCDAPC] D12_APC_0: 0x0
10040 09:29:28.748751 INFO: [NOCDAPC] D12_APC_1: 0xfff
10041 09:29:28.752618 INFO: [NOCDAPC] D13_APC_0: 0x0
10042 09:29:28.755599 INFO: [NOCDAPC] D13_APC_1: 0xfff
10043 09:29:28.758634 INFO: [NOCDAPC] D14_APC_0: 0x0
10044 09:29:28.762208 INFO: [NOCDAPC] D14_APC_1: 0xfff
10045 09:29:28.765616 INFO: [NOCDAPC] D15_APC_0: 0x0
10046 09:29:28.768708 INFO: [NOCDAPC] D15_APC_1: 0xfff
10047 09:29:28.772319 INFO: [NOCDAPC] APC_CON: 0x4
10048 09:29:28.775602 INFO: [APUAPC] set_apusys_apc done
10049 09:29:28.778631 INFO: [DEVAPC] devapc_init done
10050 09:29:28.781984 INFO: GICv3 without legacy support detected.
10051 09:29:28.785153 INFO: ARM GICv3 driver initialized in EL3
10052 09:29:28.791992 INFO: Maximum SPI INTID supported: 639
10053 09:29:28.795418 INFO: BL31: Initializing runtime services
10054 09:29:28.802047 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10055 09:29:28.802576 INFO: SPM: enable CPC mode
10056 09:29:28.808475 INFO: mcdi ready for mcusys-off-idle and system suspend
10057 09:29:28.811653 INFO: BL31: Preparing for EL3 exit to normal world
10058 09:29:28.817777 INFO: Entry point address = 0x80000000
10059 09:29:28.818197 INFO: SPSR = 0x8
10060 09:29:28.824105
10061 09:29:28.824521
10062 09:29:28.824849
10063 09:29:28.827591 Starting depthcharge on Spherion...
10064 09:29:28.828008
10065 09:29:28.828333 Wipe memory regions:
10066 09:29:28.828637
10067 09:29:28.830879 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10068 09:29:28.831406 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10069 09:29:28.831822 Setting prompt string to ['asurada:']
10070 09:29:28.832219 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10071 09:29:28.832931 [0x00000040000000, 0x00000054600000)
10072 09:29:28.953163
10073 09:29:28.953717 [0x00000054660000, 0x00000080000000)
10074 09:29:29.213419
10075 09:29:29.213928 [0x000000821a7280, 0x000000ffe64000)
10076 09:29:29.958252
10077 09:29:29.958736 [0x00000100000000, 0x00000240000000)
10078 09:29:31.848112
10079 09:29:31.851324 Initializing XHCI USB controller at 0x11200000.
10080 09:29:32.891121
10081 09:29:32.893967 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10082 09:29:32.894436
10083 09:29:32.894812
10084 09:29:32.895876 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 09:29:32.997319 asurada: tftpboot 192.168.201.1 14407666/tftp-deploy-j8twixqu/kernel/image.itb 14407666/tftp-deploy-j8twixqu/kernel/cmdline
10087 09:29:32.997938 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10088 09:29:32.998476 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10089 09:29:33.003120 tftpboot 192.168.201.1 14407666/tftp-deploy-j8twixqu/kernel/image.ittp-deploy-j8twixqu/kernel/cmdline
10090 09:29:33.003550
10091 09:29:33.003880 Waiting for link
10092 09:29:33.161810
10093 09:29:33.162355 R8152: Initializing
10094 09:29:33.162687
10095 09:29:33.164393 Version 6 (ocp_data = 5c30)
10096 09:29:33.164808
10097 09:29:33.168129 R8152: Done initializing
10098 09:29:33.168547
10099 09:29:33.168877 Adding net device
10100 09:29:35.068843
10101 09:29:35.069406 done.
10102 09:29:35.069749
10103 09:29:35.070083 MAC: 00:24:32:30:7c:7b
10104 09:29:35.070381
10105 09:29:35.072295 Sending DHCP discover... done.
10106 09:29:35.072713
10107 09:29:35.075415 Waiting for reply... done.
10108 09:29:35.075945
10109 09:29:35.078630 Sending DHCP request... done.
10110 09:29:35.079167
10111 09:29:35.085180 Waiting for reply... done.
10112 09:29:35.085914
10113 09:29:35.086386 My ip is 192.168.201.14
10114 09:29:35.086848
10115 09:29:35.088646 The DHCP server ip is 192.168.201.1
10116 09:29:35.089072
10117 09:29:35.095398 TFTP server IP predefined by user: 192.168.201.1
10118 09:29:35.095955
10119 09:29:35.101454 Bootfile predefined by user: 14407666/tftp-deploy-j8twixqu/kernel/image.itb
10120 09:29:35.101881
10121 09:29:35.105342 Sending tftp read request... done.
10122 09:29:35.105770
10123 09:29:35.111487 Waiting for the transfer...
10124 09:29:35.112010
10125 09:29:35.666895 00000000 ################################################################
10126 09:29:35.667050
10127 09:29:36.268936 00080000 ################################################################
10128 09:29:36.269077
10129 09:29:36.877030 00100000 ################################################################
10130 09:29:36.877180
10131 09:29:37.467119 00180000 ################################################################
10132 09:29:37.467270
10133 09:29:38.049776 00200000 ################################################################
10134 09:29:38.049924
10135 09:29:38.621696 00280000 ################################################################
10136 09:29:38.621846
10137 09:29:39.227239 00300000 ################################################################
10138 09:29:39.227793
10139 09:29:39.900027 00380000 ################################################################
10140 09:29:39.900784
10141 09:29:40.548772 00400000 ################################################################
10142 09:29:40.548952
10143 09:29:41.127005 00480000 ################################################################
10144 09:29:41.127154
10145 09:29:41.770787 00500000 ################################################################
10146 09:29:41.771401
10147 09:29:42.401295 00580000 ################################################################
10148 09:29:42.401450
10149 09:29:43.034563 00600000 ################################################################
10150 09:29:43.035074
10151 09:29:43.711397 00680000 ################################################################
10152 09:29:43.711943
10153 09:29:44.270287 00700000 ################################################################
10154 09:29:44.270440
10155 09:29:44.799296 00780000 ################################################################
10156 09:29:44.799442
10157 09:29:45.335283 00800000 ################################################################
10158 09:29:45.335466
10159 09:29:45.867894 00880000 ################################################################
10160 09:29:45.868044
10161 09:29:46.403333 00900000 ################################################################
10162 09:29:46.403481
10163 09:29:46.967344 00980000 ################################################################
10164 09:29:46.967500
10165 09:29:47.537021 00a00000 ################################################################
10166 09:29:47.537273
10167 09:29:48.165227 00a80000 ################################################################
10168 09:29:48.165782
10169 09:29:48.839851 00b00000 ################################################################
10170 09:29:48.840374
10171 09:29:49.501145 00b80000 ################################################################
10172 09:29:49.501691
10173 09:29:50.143370 00c00000 ################################################################
10174 09:29:50.143951
10175 09:29:50.758945 00c80000 ################################################################
10176 09:29:50.759079
10177 09:29:51.284702 00d00000 ################################################################
10178 09:29:51.284850
10179 09:29:51.851384 00d80000 ################################################################
10180 09:29:51.851531
10181 09:29:52.447046 00e00000 ################################################################
10182 09:29:52.447191
10183 09:29:53.050736 00e80000 ################################################################
10184 09:29:53.051249
10185 09:29:53.719993 00f00000 ################################################################
10186 09:29:53.720510
10187 09:29:54.372750 00f80000 ################################################################
10188 09:29:54.372890
10189 09:29:55.004650 01000000 ################################################################
10190 09:29:55.005202
10191 09:29:55.665874 01080000 ################################################################
10192 09:29:55.666396
10193 09:29:56.253541 01100000 ################################################################
10194 09:29:56.254088
10195 09:29:56.915872 01180000 ################################################################
10196 09:29:56.916391
10197 09:29:57.576419 01200000 ################################################################
10198 09:29:57.576936
10199 09:29:58.216549 01280000 ################################################################
10200 09:29:58.216700
10201 09:29:58.802164 01300000 ################################################################
10202 09:29:58.802311
10203 09:29:59.416186 01380000 ################################################################
10204 09:29:59.416711
10205 09:30:00.036391 01400000 ################################################################
10206 09:30:00.036547
10207 09:30:00.593174 01480000 ################################################################
10208 09:30:00.593373
10209 09:30:01.135438 01500000 ################################################################
10210 09:30:01.135608
10211 09:30:01.660992 01580000 ################################################################
10212 09:30:01.661147
10213 09:30:02.251791 01600000 ################################################################
10214 09:30:02.252324
10215 09:30:02.908399 01680000 ################################################################
10216 09:30:02.909057
10217 09:30:03.559228 01700000 ################################################################
10218 09:30:03.559851
10219 09:30:04.182789 01780000 ################################################################
10220 09:30:04.183300
10221 09:30:04.841658 01800000 ################################################################
10222 09:30:04.842203
10223 09:30:05.495797 01880000 ################################################################
10224 09:30:05.495943
10225 09:30:06.131931 01900000 ################################################################
10226 09:30:06.132465
10227 09:30:06.812693 01980000 ################################################################
10228 09:30:06.813215
10229 09:30:07.493780 01a00000 ################################################################
10230 09:30:07.494460
10231 09:30:08.164390 01a80000 ################################################################
10232 09:30:08.164906
10233 09:30:08.834860 01b00000 ################################################################
10234 09:30:08.835425
10235 09:30:09.513691 01b80000 ################################################################
10236 09:30:09.514206
10237 09:30:10.193068 01c00000 ################################################################
10238 09:30:10.193609
10239 09:30:10.770458 01c80000 ################################################################
10240 09:30:10.770633
10241 09:30:11.447643 01d00000 ################################################################
10242 09:30:11.447811
10243 09:30:12.081929 01d80000 ################################################################
10244 09:30:12.082447
10245 09:30:12.659967 01e00000 ######################################################## done.
10246 09:30:12.660697
10247 09:30:12.663218 The bootfile was 31910954 bytes long.
10248 09:30:12.663748
10249 09:30:12.666526 Sending tftp read request... done.
10250 09:30:12.667157
10251 09:30:12.670147 Waiting for the transfer...
10252 09:30:12.670762
10253 09:30:12.671235 00000000 # done.
10254 09:30:12.671702
10255 09:30:12.677060 Command line loaded dynamically from TFTP file: 14407666/tftp-deploy-j8twixqu/kernel/cmdline
10256 09:30:12.677730
10257 09:30:12.700161 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407666/extract-nfsrootfs-m2jz1nta,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10258 09:30:12.700814
10259 09:30:12.701391 Loading FIT.
10260 09:30:12.704210
10261 09:30:12.704600 Image ramdisk-1 has 18734933 bytes.
10262 09:30:12.704964
10263 09:30:12.707121 Image fdt-1 has 47258 bytes.
10264 09:30:12.707503
10265 09:30:12.710241 Image kernel-1 has 13126726 bytes.
10266 09:30:12.710557
10267 09:30:12.719881 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10268 09:30:12.720134
10269 09:30:12.736498 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10270 09:30:12.736759
10271 09:30:12.742872 Choosing best match conf-1 for compat google,spherion-rev2.
10272 09:30:12.746558
10273 09:30:12.750940 Connected to device vid:did:rid of 1ae0:0028:00
10274 09:30:12.757640
10275 09:30:12.761374 tpm_get_response: command 0x17b, return code 0x0
10276 09:30:12.761458
10277 09:30:12.764537 ec_init: CrosEC protocol v3 supported (256, 248)
10278 09:30:12.769478
10279 09:30:12.772572 tpm_cleanup: add release locality here.
10280 09:30:12.772655
10281 09:30:12.772720 Shutting down all USB controllers.
10282 09:30:12.776479
10283 09:30:12.776561 Removing current net device
10284 09:30:12.776626
10285 09:30:12.782505 Exiting depthcharge with code 4 at timestamp: 73200075
10286 09:30:12.782588
10287 09:30:12.785898 LZMA decompressing kernel-1 to 0x821a6718
10288 09:30:12.785980
10289 09:30:12.789160 LZMA decompressing kernel-1 to 0x40000000
10290 09:30:14.407449
10291 09:30:14.407951 jumping to kernel
10292 09:30:14.409568 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10293 09:30:14.410060 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10294 09:30:14.410438 Setting prompt string to ['Linux version [0-9]']
10295 09:30:14.410775 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10296 09:30:14.411112 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10297 09:30:14.489342
10298 09:30:14.492859 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10299 09:30:14.496441 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10300 09:30:14.497011 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10301 09:30:14.497567 Setting prompt string to []
10302 09:30:14.498149 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10303 09:30:14.498530 Using line separator: #'\n'#
10304 09:30:14.498931 No login prompt set.
10305 09:30:14.499265 Parsing kernel messages
10306 09:30:14.499556 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10307 09:30:14.500086 [login-action] Waiting for messages, (timeout 00:03:41)
10308 09:30:14.500423 Waiting using forced prompt support (timeout 00:01:50)
10309 09:30:14.516041 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
10310 09:30:14.519635 [ 0.000000] random: crng init done
10311 09:30:14.526332 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10312 09:30:14.526834 [ 0.000000] efi: UEFI not found.
10313 09:30:14.535994 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10314 09:30:14.543099 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10315 09:30:14.552647 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10316 09:30:14.563412 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10317 09:30:14.569169 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10318 09:30:14.572887 [ 0.000000] printk: bootconsole [mtk8250] enabled
10319 09:30:14.581381 [ 0.000000] NUMA: No NUMA configuration found
10320 09:30:14.588101 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10321 09:30:14.594735 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10322 09:30:14.595240 [ 0.000000] Zone ranges:
10323 09:30:14.601535 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10324 09:30:14.604823 [ 0.000000] DMA32 empty
10325 09:30:14.611348 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10326 09:30:14.614470 [ 0.000000] Movable zone start for each node
10327 09:30:14.618008 [ 0.000000] Early memory node ranges
10328 09:30:14.624922 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10329 09:30:14.631361 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10330 09:30:14.637730 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10331 09:30:14.644192 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10332 09:30:14.651183 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10333 09:30:14.657927 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10334 09:30:14.714053 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10335 09:30:14.720738 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10336 09:30:14.727236 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10337 09:30:14.730961 [ 0.000000] psci: probing for conduit method from DT.
10338 09:30:14.737687 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10339 09:30:14.740778 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10340 09:30:14.747049 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10341 09:30:14.750897 [ 0.000000] psci: SMC Calling Convention v1.2
10342 09:30:14.757649 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10343 09:30:14.760410 [ 0.000000] Detected VIPT I-cache on CPU0
10344 09:30:14.767230 [ 0.000000] CPU features: detected: GIC system register CPU interface
10345 09:30:14.774191 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10346 09:30:14.781139 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10347 09:30:14.786969 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10348 09:30:14.793706 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10349 09:30:14.800582 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10350 09:30:14.807246 [ 0.000000] alternatives: applying boot alternatives
10351 09:30:14.810983 [ 0.000000] Fallback order for Node 0: 0
10352 09:30:14.817306 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10353 09:30:14.820827 [ 0.000000] Policy zone: Normal
10354 09:30:14.847356 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407666/extract-nfsrootfs-m2jz1nta,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10355 09:30:14.856838 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10356 09:30:14.867094 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10357 09:30:14.877228 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10358 09:30:14.883787 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10359 09:30:14.886900 <6>[ 0.000000] software IO TLB: area num 8.
10360 09:30:14.943748 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10361 09:30:15.093699 <6>[ 0.000000] Memory: 7945764K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407004K reserved, 32768K cma-reserved)
10362 09:30:15.100921 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10363 09:30:15.106658 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10364 09:30:15.110006 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10365 09:30:15.117130 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10366 09:30:15.123801 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10367 09:30:15.126677 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10368 09:30:15.136514 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10369 09:30:15.143633 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10370 09:30:15.146573 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10371 09:30:15.154741 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10372 09:30:15.158280 <6>[ 0.000000] GICv3: 608 SPIs implemented
10373 09:30:15.163989 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10374 09:30:15.167702 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10375 09:30:15.170913 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10376 09:30:15.181051 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10377 09:30:15.191017 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10378 09:30:15.204231 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10379 09:30:15.210842 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10380 09:30:15.219938 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10381 09:30:15.233079 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10382 09:30:15.239557 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10383 09:30:15.246011 <6>[ 0.009232] Console: colour dummy device 80x25
10384 09:30:15.255938 <6>[ 0.013963] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10385 09:30:15.262889 <6>[ 0.024403] pid_max: default: 32768 minimum: 301
10386 09:30:15.266041 <6>[ 0.029275] LSM: Security Framework initializing
10387 09:30:15.272887 <6>[ 0.034213] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10388 09:30:15.282932 <6>[ 0.042074] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10389 09:30:15.292699 <6>[ 0.051537] cblist_init_generic: Setting adjustable number of callback queues.
10390 09:30:15.295618 <6>[ 0.059006] cblist_init_generic: Setting shift to 3 and lim to 1.
10391 09:30:15.306144 <6>[ 0.065345] cblist_init_generic: Setting adjustable number of callback queues.
10392 09:30:15.312574 <6>[ 0.072772] cblist_init_generic: Setting shift to 3 and lim to 1.
10393 09:30:15.315770 <6>[ 0.079211] rcu: Hierarchical SRCU implementation.
10394 09:30:15.322215 <6>[ 0.084257] rcu: Max phase no-delay instances is 1000.
10395 09:30:15.328893 <6>[ 0.091291] EFI services will not be available.
10396 09:30:15.331937 <6>[ 0.096249] smp: Bringing up secondary CPUs ...
10397 09:30:15.340365 <6>[ 0.101301] Detected VIPT I-cache on CPU1
10398 09:30:15.346737 <6>[ 0.101373] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10399 09:30:15.353646 <6>[ 0.101404] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10400 09:30:15.357187 <6>[ 0.101744] Detected VIPT I-cache on CPU2
10401 09:30:15.363840 <6>[ 0.101797] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10402 09:30:15.370265 <6>[ 0.101816] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10403 09:30:15.377235 <6>[ 0.102073] Detected VIPT I-cache on CPU3
10404 09:30:15.383489 <6>[ 0.102120] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10405 09:30:15.390439 <6>[ 0.102134] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10406 09:30:15.393528 <6>[ 0.102436] CPU features: detected: Spectre-v4
10407 09:30:15.400486 <6>[ 0.102441] CPU features: detected: Spectre-BHB
10408 09:30:15.403612 <6>[ 0.102446] Detected PIPT I-cache on CPU4
10409 09:30:15.410220 <6>[ 0.102504] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10410 09:30:15.416589 <6>[ 0.102521] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10411 09:30:15.423167 <6>[ 0.102815] Detected PIPT I-cache on CPU5
10412 09:30:15.429849 <6>[ 0.102877] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10413 09:30:15.436859 <6>[ 0.102893] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10414 09:30:15.439992 <6>[ 0.103158] Detected PIPT I-cache on CPU6
10415 09:30:15.446581 <6>[ 0.103216] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10416 09:30:15.453137 <6>[ 0.103232] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10417 09:30:15.459966 <6>[ 0.103521] Detected PIPT I-cache on CPU7
10418 09:30:15.466763 <6>[ 0.103585] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10419 09:30:15.473444 <6>[ 0.103601] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10420 09:30:15.476441 <6>[ 0.103648] smp: Brought up 1 node, 8 CPUs
10421 09:30:15.483005 <6>[ 0.244868] SMP: Total of 8 processors activated.
10422 09:30:15.486223 <6>[ 0.249789] CPU features: detected: 32-bit EL0 Support
10423 09:30:15.496602 <6>[ 0.255153] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10424 09:30:15.502920 <6>[ 0.263954] CPU features: detected: Common not Private translations
10425 09:30:15.506579 <6>[ 0.270429] CPU features: detected: CRC32 instructions
10426 09:30:15.513525 <6>[ 0.275781] CPU features: detected: RCpc load-acquire (LDAPR)
10427 09:30:15.519386 <6>[ 0.281741] CPU features: detected: LSE atomic instructions
10428 09:30:15.526613 <6>[ 0.287522] CPU features: detected: Privileged Access Never
10429 09:30:15.529398 <6>[ 0.293302] CPU features: detected: RAS Extension Support
10430 09:30:15.539199 <6>[ 0.298911] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10431 09:30:15.542996 <6>[ 0.306130] CPU: All CPU(s) started at EL2
10432 09:30:15.549070 <6>[ 0.310446] alternatives: applying system-wide alternatives
10433 09:30:15.558360 <6>[ 0.321230] devtmpfs: initialized
10434 09:30:15.573782 <6>[ 0.330049] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10435 09:30:15.580225 <6>[ 0.340010] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10436 09:30:15.586666 <6>[ 0.348041] pinctrl core: initialized pinctrl subsystem
10437 09:30:15.590211 <6>[ 0.354672] DMI not present or invalid.
10438 09:30:15.596729 <6>[ 0.359083] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10439 09:30:15.606974 <6>[ 0.365965] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10440 09:30:15.613166 <6>[ 0.373553] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10441 09:30:15.623130 <6>[ 0.381775] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10442 09:30:15.626318 <6>[ 0.390016] audit: initializing netlink subsys (disabled)
10443 09:30:15.636525 <5>[ 0.395711] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10444 09:30:15.642914 <6>[ 0.396419] thermal_sys: Registered thermal governor 'step_wise'
10445 09:30:15.649454 <6>[ 0.403676] thermal_sys: Registered thermal governor 'power_allocator'
10446 09:30:15.653210 <6>[ 0.409932] cpuidle: using governor menu
10447 09:30:15.659550 <6>[ 0.420891] NET: Registered PF_QIPCRTR protocol family
10448 09:30:15.666033 <6>[ 0.426379] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10449 09:30:15.669212 <6>[ 0.433481] ASID allocator initialised with 32768 entries
10450 09:30:15.677201 <6>[ 0.440056] Serial: AMBA PL011 UART driver
10451 09:30:15.685714 <4>[ 0.448890] Trying to register duplicate clock ID: 134
10452 09:30:15.744145 <6>[ 0.510427] KASLR enabled
10453 09:30:15.759058 <6>[ 0.518117] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10454 09:30:15.765465 <6>[ 0.525133] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10455 09:30:15.772059 <6>[ 0.531622] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10456 09:30:15.778315 <6>[ 0.538625] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10457 09:30:15.785401 <6>[ 0.545113] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10458 09:30:15.791766 <6>[ 0.552116] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10459 09:30:15.798646 <6>[ 0.558602] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10460 09:30:15.804933 <6>[ 0.565605] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10461 09:30:15.808179 <6>[ 0.573022] ACPI: Interpreter disabled.
10462 09:30:15.816390 <6>[ 0.579446] iommu: Default domain type: Translated
10463 09:30:15.823629 <6>[ 0.584558] iommu: DMA domain TLB invalidation policy: strict mode
10464 09:30:15.826587 <5>[ 0.591222] SCSI subsystem initialized
10465 09:30:15.833476 <6>[ 0.595386] usbcore: registered new interface driver usbfs
10466 09:30:15.839626 <6>[ 0.601120] usbcore: registered new interface driver hub
10467 09:30:15.842753 <6>[ 0.606672] usbcore: registered new device driver usb
10468 09:30:15.849979 <6>[ 0.612772] pps_core: LinuxPPS API ver. 1 registered
10469 09:30:15.859845 <6>[ 0.617964] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10470 09:30:15.862773 <6>[ 0.627308] PTP clock support registered
10471 09:30:15.866250 <6>[ 0.631552] EDAC MC: Ver: 3.0.0
10472 09:30:15.873798 <6>[ 0.636704] FPGA manager framework
10473 09:30:15.877540 <6>[ 0.640389] Advanced Linux Sound Architecture Driver Initialized.
10474 09:30:15.880742 <6>[ 0.647158] vgaarb: loaded
10475 09:30:15.887593 <6>[ 0.650310] clocksource: Switched to clocksource arch_sys_counter
10476 09:30:15.893901 <5>[ 0.656750] VFS: Disk quotas dquot_6.6.0
10477 09:30:15.900972 <6>[ 0.660939] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10478 09:30:15.904442 <6>[ 0.668125] pnp: PnP ACPI: disabled
10479 09:30:15.911792 <6>[ 0.674780] NET: Registered PF_INET protocol family
10480 09:30:15.921597 <6>[ 0.680373] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10481 09:30:15.933128 <6>[ 0.692693] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10482 09:30:15.942857 <6>[ 0.701509] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10483 09:30:15.949208 <6>[ 0.709482] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10484 09:30:15.959095 <6>[ 0.718183] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10485 09:30:15.966189 <6>[ 0.727938] TCP: Hash tables configured (established 65536 bind 65536)
10486 09:30:15.972745 <6>[ 0.734801] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10487 09:30:15.982599 <6>[ 0.742003] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10488 09:30:15.988863 <6>[ 0.749703] NET: Registered PF_UNIX/PF_LOCAL protocol family
10489 09:30:15.995781 <6>[ 0.755852] RPC: Registered named UNIX socket transport module.
10490 09:30:15.998906 <6>[ 0.762006] RPC: Registered udp transport module.
10491 09:30:16.005330 <6>[ 0.766938] RPC: Registered tcp transport module.
10492 09:30:16.011949 <6>[ 0.771871] RPC: Registered tcp NFSv4.1 backchannel transport module.
10493 09:30:16.015565 <6>[ 0.778537] PCI: CLS 0 bytes, default 64
10494 09:30:16.018515 <6>[ 0.782958] Unpacking initramfs...
10495 09:30:16.028522 <6>[ 0.786689] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10496 09:30:16.034732 <6>[ 0.795316] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10497 09:30:16.041645 <6>[ 0.804110] kvm [1]: IPA Size Limit: 40 bits
10498 09:30:16.044712 <6>[ 0.808637] kvm [1]: GICv3: no GICV resource entry
10499 09:30:16.051701 <6>[ 0.813659] kvm [1]: disabling GICv2 emulation
10500 09:30:16.058489 <6>[ 0.818345] kvm [1]: GIC system register CPU interface enabled
10501 09:30:16.061352 <6>[ 0.824511] kvm [1]: vgic interrupt IRQ18
10502 09:30:16.068070 <6>[ 0.830357] kvm [1]: VHE mode initialized successfully
10503 09:30:16.074758 <5>[ 0.836776] Initialise system trusted keyrings
10504 09:30:16.081331 <6>[ 0.841566] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10505 09:30:16.088886 <6>[ 0.851707] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10506 09:30:16.095223 <5>[ 0.858092] NFS: Registering the id_resolver key type
10507 09:30:16.098431 <5>[ 0.863393] Key type id_resolver registered
10508 09:30:16.105094 <5>[ 0.867808] Key type id_legacy registered
10509 09:30:16.111696 <6>[ 0.872088] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10510 09:30:16.118572 <6>[ 0.879009] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10511 09:30:16.124995 <6>[ 0.886718] 9p: Installing v9fs 9p2000 file system support
10512 09:30:16.161424 <5>[ 0.924485] Key type asymmetric registered
10513 09:30:16.165133 <5>[ 0.928817] Asymmetric key parser 'x509' registered
10514 09:30:16.174987 <6>[ 0.933957] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10515 09:30:16.178188 <6>[ 0.941568] io scheduler mq-deadline registered
10516 09:30:16.181435 <6>[ 0.946331] io scheduler kyber registered
10517 09:30:16.199580 <6>[ 0.963251] EINJ: ACPI disabled.
10518 09:30:16.233040 <4>[ 0.989530] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10519 09:30:16.242499 <4>[ 1.000155] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10520 09:30:16.257223 <6>[ 1.021066] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10521 09:30:16.265266 <6>[ 1.029003] printk: console [ttyS0] disabled
10522 09:30:16.293642 <6>[ 1.053645] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10523 09:30:16.300037 <6>[ 1.063124] printk: console [ttyS0] enabled
10524 09:30:16.303435 <6>[ 1.063124] printk: console [ttyS0] enabled
10525 09:30:16.309659 <6>[ 1.072014] printk: bootconsole [mtk8250] disabled
10526 09:30:16.313438 <6>[ 1.072014] printk: bootconsole [mtk8250] disabled
10527 09:30:16.320083 <6>[ 1.083060] SuperH (H)SCI(F) driver initialized
10528 09:30:16.323108 <6>[ 1.088311] msm_serial: driver initialized
10529 09:30:16.337252 <6>[ 1.097260] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10530 09:30:16.347197 <6>[ 1.105803] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10531 09:30:16.353486 <6>[ 1.114345] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10532 09:30:16.363802 <6>[ 1.122972] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10533 09:30:16.373603 <6>[ 1.131679] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10534 09:30:16.379900 <6>[ 1.140392] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10535 09:30:16.390199 <6>[ 1.148933] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10536 09:30:16.396282 <6>[ 1.157729] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10537 09:30:16.406354 <6>[ 1.166270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10538 09:30:16.418514 <6>[ 1.181833] loop: module loaded
10539 09:30:16.424676 <6>[ 1.187748] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10540 09:30:16.447668 <4>[ 1.211063] mtk-pmic-keys: Failed to locate of_node [id: -1]
10541 09:30:16.454472 <6>[ 1.217777] megasas: 07.719.03.00-rc1
10542 09:30:16.463704 <6>[ 1.227278] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10543 09:30:16.474240 <6>[ 1.237686] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10544 09:30:16.490843 <6>[ 1.254190] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10545 09:30:16.547082 <6>[ 1.304028] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10546 09:30:16.816697 <6>[ 1.580092] Freeing initrd memory: 18292K
10547 09:30:16.828209 <6>[ 1.591789] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10548 09:30:16.839117 <6>[ 1.602728] tun: Universal TUN/TAP device driver, 1.6
10549 09:30:16.842663 <6>[ 1.608781] thunder_xcv, ver 1.0
10550 09:30:16.845581 <6>[ 1.612286] thunder_bgx, ver 1.0
10551 09:30:16.849207 <6>[ 1.615782] nicpf, ver 1.0
10552 09:30:16.859934 <6>[ 1.619806] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10553 09:30:16.863439 <6>[ 1.627281] hns3: Copyright (c) 2017 Huawei Corporation.
10554 09:30:16.869439 <6>[ 1.632868] hclge is initializing
10555 09:30:16.872652 <6>[ 1.636442] e1000: Intel(R) PRO/1000 Network Driver
10556 09:30:16.879384 <6>[ 1.641571] e1000: Copyright (c) 1999-2006 Intel Corporation.
10557 09:30:16.883078 <6>[ 1.647584] e1000e: Intel(R) PRO/1000 Network Driver
10558 09:30:16.889689 <6>[ 1.652800] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10559 09:30:16.896434 <6>[ 1.658987] igb: Intel(R) Gigabit Ethernet Network Driver
10560 09:30:16.903179 <6>[ 1.664637] igb: Copyright (c) 2007-2014 Intel Corporation.
10561 09:30:16.909366 <6>[ 1.670473] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10562 09:30:16.916476 <6>[ 1.676991] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10563 09:30:16.919453 <6>[ 1.683449] sky2: driver version 1.30
10564 09:30:16.926119 <6>[ 1.688381] usbcore: registered new device driver r8152-cfgselector
10565 09:30:16.932553 <6>[ 1.694915] usbcore: registered new interface driver r8152
10566 09:30:16.938993 <6>[ 1.700742] VFIO - User Level meta-driver version: 0.3
10567 09:30:16.945722 <6>[ 1.708988] usbcore: registered new interface driver usb-storage
10568 09:30:16.952301 <6>[ 1.715431] usbcore: registered new device driver onboard-usb-hub
10569 09:30:16.961375 <6>[ 1.724610] mt6397-rtc mt6359-rtc: registered as rtc0
10570 09:30:16.971511 <6>[ 1.730078] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-18T09:30:16 UTC (1718703016)
10571 09:30:16.974204 <6>[ 1.739666] i2c_dev: i2c /dev entries driver
10572 09:30:16.988175 <4>[ 1.751635] cpu cpu0: supply cpu not found, using dummy regulator
10573 09:30:16.995017 <4>[ 1.758063] cpu cpu1: supply cpu not found, using dummy regulator
10574 09:30:17.001170 <4>[ 1.764467] cpu cpu2: supply cpu not found, using dummy regulator
10575 09:30:17.007982 <4>[ 1.770875] cpu cpu3: supply cpu not found, using dummy regulator
10576 09:30:17.014658 <4>[ 1.777272] cpu cpu4: supply cpu not found, using dummy regulator
10577 09:30:17.020732 <4>[ 1.783685] cpu cpu5: supply cpu not found, using dummy regulator
10578 09:30:17.027444 <4>[ 1.790085] cpu cpu6: supply cpu not found, using dummy regulator
10579 09:30:17.034248 <4>[ 1.796484] cpu cpu7: supply cpu not found, using dummy regulator
10580 09:30:17.054545 <6>[ 1.818120] cpu cpu0: EM: created perf domain
10581 09:30:17.057935 <6>[ 1.823040] cpu cpu4: EM: created perf domain
10582 09:30:17.065197 <6>[ 1.828598] sdhci: Secure Digital Host Controller Interface driver
10583 09:30:17.071505 <6>[ 1.835030] sdhci: Copyright(c) Pierre Ossman
10584 09:30:17.078786 <6>[ 1.839984] Synopsys Designware Multimedia Card Interface Driver
10585 09:30:17.085026 <6>[ 1.846623] sdhci-pltfm: SDHCI platform and OF driver helper
10586 09:30:17.088632 <6>[ 1.846656] mmc0: CQHCI version 5.10
10587 09:30:17.095105 <6>[ 1.856569] ledtrig-cpu: registered to indicate activity on CPUs
10588 09:30:17.101378 <6>[ 1.863372] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10589 09:30:17.108166 <6>[ 1.870451] usbcore: registered new interface driver usbhid
10590 09:30:17.111243 <6>[ 1.876283] usbhid: USB HID core driver
10591 09:30:17.118059 <6>[ 1.880484] spi_master spi0: will run message pump with realtime priority
10592 09:30:17.167245 <6>[ 1.924237] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10593 09:30:17.186838 <6>[ 1.940336] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10594 09:30:17.189864 <6>[ 1.947515] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16014
10595 09:30:17.197208 <6>[ 1.960695] cros-ec-spi spi0.0: Chrome EC device registered
10596 09:30:17.203961 <6>[ 1.966734] mmc0: Command Queue Engine enabled
10597 09:30:17.210930 <6>[ 1.971494] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10598 09:30:17.213907 <6>[ 1.979233] mmcblk0: mmc0:0001 DA4128 116 GiB
10599 09:30:17.225314 <6>[ 1.988776] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10600 09:30:17.233382 <6>[ 1.996583] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10601 09:30:17.243352 <6>[ 2.000480] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10602 09:30:17.246973 <6>[ 2.002497] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10603 09:30:17.253469 <6>[ 2.012496] NET: Registered PF_PACKET protocol family
10604 09:30:17.260309 <6>[ 2.016983] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10605 09:30:17.263279 <6>[ 2.021729] 9pnet: Installing 9P2000 support
10606 09:30:17.269644 <5>[ 2.032712] Key type dns_resolver registered
10607 09:30:17.273499 <6>[ 2.037673] registered taskstats version 1
10608 09:30:17.279617 <5>[ 2.042054] Loading compiled-in X.509 certificates
10609 09:30:17.309196 <4>[ 2.065530] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 09:30:17.319278 <4>[ 2.076450] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 09:30:17.334413 <6>[ 2.096994] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10612 09:30:17.341050 <6>[ 2.103969] xhci-mtk 11200000.usb: xHCI Host Controller
10613 09:30:17.347537 <6>[ 2.109490] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10614 09:30:17.357895 <6>[ 2.117381] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10615 09:30:17.363960 <6>[ 2.126847] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10616 09:30:17.370541 <6>[ 2.133039] xhci-mtk 11200000.usb: xHCI Host Controller
10617 09:30:17.377499 <6>[ 2.138546] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10618 09:30:17.383740 <6>[ 2.146198] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10619 09:30:17.391300 <6>[ 2.154008] hub 1-0:1.0: USB hub found
10620 09:30:17.394145 <6>[ 2.158048] hub 1-0:1.0: 1 port detected
10621 09:30:17.404235 <6>[ 2.162336] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10622 09:30:17.407364 <6>[ 2.171066] hub 2-0:1.0: USB hub found
10623 09:30:17.410740 <6>[ 2.175107] hub 2-0:1.0: 1 port detected
10624 09:30:17.419051 <6>[ 2.182173] mtk-msdc 11f70000.mmc: Got CD GPIO
10625 09:30:17.436452 <6>[ 2.195913] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10626 09:30:17.446148 <6>[ 2.204314] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10627 09:30:17.453015 <6>[ 2.212655] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10628 09:30:17.462629 <6>[ 2.220993] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10629 09:30:17.469408 <6>[ 2.229331] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10630 09:30:17.478767 <6>[ 2.237669] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10631 09:30:17.485991 <6>[ 2.246016] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10632 09:30:17.495307 <6>[ 2.254356] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10633 09:30:17.502066 <6>[ 2.262694] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10634 09:30:17.512271 <6>[ 2.271031] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10635 09:30:17.518307 <6>[ 2.279369] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10636 09:30:17.529318 <6>[ 2.287713] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10637 09:30:17.535555 <6>[ 2.296050] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10638 09:30:17.545169 <6>[ 2.304390] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10639 09:30:17.552216 <6>[ 2.312728] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10640 09:30:17.558258 <6>[ 2.321438] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10641 09:30:17.565187 <6>[ 2.328589] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10642 09:30:17.572362 <6>[ 2.335392] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10643 09:30:17.579049 <6>[ 2.342161] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10644 09:30:17.585869 <6>[ 2.349101] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10645 09:30:17.596292 <6>[ 2.356000] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10646 09:30:17.606275 <6>[ 2.365131] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10647 09:30:17.616175 <6>[ 2.374250] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10648 09:30:17.626066 <6>[ 2.383545] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10649 09:30:17.635846 <6>[ 2.393012] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10650 09:30:17.642219 <6>[ 2.402479] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10651 09:30:17.652407 <6>[ 2.411599] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10652 09:30:17.662111 <6>[ 2.421065] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10653 09:30:17.671985 <6>[ 2.430185] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10654 09:30:17.681878 <6>[ 2.439483] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10655 09:30:17.692136 <6>[ 2.449644] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10656 09:30:17.701611 <6>[ 2.461325] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10657 09:30:17.709427 <6>[ 2.472488] Trying to probe devices needed for running init ...
10658 09:30:17.719735 <3>[ 2.479775] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10659 09:30:17.822376 <6>[ 2.582577] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10660 09:30:17.977644 <6>[ 2.740564] hub 1-1:1.0: USB hub found
10661 09:30:17.980580 <6>[ 2.744940] hub 1-1:1.0: 4 ports detected
10662 09:30:17.990826 <6>[ 2.754202] hub 1-1:1.0: USB hub found
10663 09:30:17.994786 <6>[ 2.758654] hub 1-1:1.0: 4 ports detected
10664 09:30:18.102393 <6>[ 2.862583] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10665 09:30:18.128249 <6>[ 2.891612] hub 2-1:1.0: USB hub found
10666 09:30:18.131914 <6>[ 2.896078] hub 2-1:1.0: 3 ports detected
10667 09:30:18.143467 <6>[ 2.906471] hub 2-1:1.0: USB hub found
10668 09:30:18.146478 <6>[ 2.910985] hub 2-1:1.0: 3 ports detected
10669 09:30:18.319168 <6>[ 3.078627] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10670 09:30:18.451117 <6>[ 3.214137] hub 1-1.4:1.0: USB hub found
10671 09:30:18.454295 <6>[ 3.218747] hub 1-1.4:1.0: 2 ports detected
10672 09:30:18.469082 <6>[ 3.232041] hub 1-1.4:1.0: USB hub found
10673 09:30:18.472607 <6>[ 3.236722] hub 1-1.4:1.0: 2 ports detected
10674 09:30:18.530991 <6>[ 3.290837] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10675 09:30:18.639127 <6>[ 3.399267] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10676 09:30:18.676153 <4>[ 3.435486] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10677 09:30:18.685663 <4>[ 3.444581] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10678 09:30:18.724701 <6>[ 3.487928] r8152 2-1.3:1.0 eth0: v1.12.13
10679 09:30:18.770488 <6>[ 3.530558] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10680 09:30:18.966464 <6>[ 3.726478] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10681 09:30:20.337098 <6>[ 5.100313] r8152 2-1.3:1.0 eth0: carrier on
10682 09:30:22.590703 <5>[ 5.122425] Sending DHCP requests .., OK
10683 09:30:22.597928 <6>[ 7.358753] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10684 09:30:22.601142 <6>[ 7.367053] IP-Config: Complete:
10685 09:30:22.614048 <6>[ 7.370547] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10686 09:30:22.621040 <6>[ 7.381259] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10687 09:30:22.627258 <6>[ 7.389878] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10688 09:30:22.633860 <6>[ 7.389887] nameserver0=192.168.201.1
10689 09:30:22.637102 <6>[ 7.402039] clk: Disabling unused clocks
10690 09:30:22.640719 <6>[ 7.407807] ALSA device list:
10691 09:30:22.647394 <6>[ 7.411051] No soundcards found.
10692 09:30:22.655089 <6>[ 7.418613] Freeing unused kernel memory: 8512K
10693 09:30:22.658442 <6>[ 7.423611] Run /init as init process
10694 09:30:22.667874 Loading, please wait...
10695 09:30:22.693046 Starting systemd-udevd version 252.22-1~deb12u1
10696 09:30:22.990552 <6>[ 7.750896] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10697 09:30:23.000230 <6>[ 7.759022] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10698 09:30:23.006985 <6>[ 7.767786] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10699 09:30:23.025331 <6>[ 7.785719] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10700 09:30:23.031704 <3>[ 7.787211] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 09:30:23.041766 <3>[ 7.801932] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 09:30:23.048495 <6>[ 7.806241] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10703 09:30:23.055212 <6>[ 7.809477] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10704 09:30:23.064689 <6>[ 7.809485] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10705 09:30:23.074721 <4>[ 7.809764] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10706 09:30:23.081710 <3>[ 7.810033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 09:30:23.091136 <3>[ 7.810228] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 09:30:23.097969 <6>[ 7.810488] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10709 09:30:23.104292 <6>[ 7.810497] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10710 09:30:23.114503 <6>[ 7.810837] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10711 09:30:23.120997 <6>[ 7.810873] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10712 09:30:23.130949 <6>[ 7.810882] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10713 09:30:23.141066 <6>[ 7.810896] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10714 09:30:23.143926 <6>[ 7.826133] mc: Linux media interface: v0.10
10715 09:30:23.150762 <4>[ 7.826961] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10716 09:30:23.157302 <4>[ 7.827109] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10717 09:30:23.168458 <3>[ 7.833262] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 09:30:23.171742 <6>[ 7.844952] remoteproc remoteproc0: scp is available
10719 09:30:23.178521 <3>[ 7.850563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 09:30:23.184824 <6>[ 7.858639] remoteproc remoteproc0: powering up scp
10721 09:30:23.191423 <3>[ 7.866892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 09:30:23.201946 <6>[ 7.874918] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10723 09:30:23.208774 <3>[ 7.883236] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 09:30:23.218908 <6>[ 7.883754] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10725 09:30:23.222065 <6>[ 7.890671] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10726 09:30:23.231442 <3>[ 7.899025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 09:30:23.237876 <6>[ 7.899630] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10728 09:30:23.244298 <6>[ 7.899634] pci_bus 0000:00: root bus resource [bus 00-ff]
10729 09:30:23.251084 <6>[ 7.899639] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10730 09:30:23.261527 <6>[ 7.899641] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10731 09:30:23.267493 <6>[ 7.899672] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10732 09:30:23.274237 <6>[ 7.899686] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10733 09:30:23.277716 <6>[ 7.899757] pci 0000:00:00.0: supports D1 D2
10734 09:30:23.284311 <6>[ 7.899759] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10735 09:30:23.294153 <6>[ 7.900751] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10736 09:30:23.301108 <6>[ 7.900818] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10737 09:30:23.307264 <6>[ 7.900843] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10738 09:30:23.314114 <6>[ 7.900858] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10739 09:30:23.323884 <6>[ 7.900873] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10740 09:30:23.327003 <6>[ 7.900973] pci 0000:01:00.0: supports D1 D2
10741 09:30:23.333193 <6>[ 7.900975] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10742 09:30:23.343335 <4>[ 7.911892] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10743 09:30:23.346985 <4>[ 7.911892] Fallback method does not support PEC.
10744 09:30:23.356833 <3>[ 7.912767] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 09:30:23.363375 <6>[ 7.914899] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10746 09:30:23.370108 <6>[ 7.914955] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10747 09:30:23.379937 <6>[ 7.914964] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10748 09:30:23.386308 <6>[ 7.915001] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10749 09:30:23.393095 <6>[ 7.915046] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10750 09:30:23.402881 <6>[ 7.915089] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10751 09:30:23.406559 <6>[ 7.915131] pci 0000:00:00.0: PCI bridge to [bus 01]
10752 09:30:23.416032 <6>[ 7.915164] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10753 09:30:23.422821 <6>[ 7.915328] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10754 09:30:23.429145 <6>[ 7.916501] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10755 09:30:23.432750 <6>[ 7.917062] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10756 09:30:23.442342 <3>[ 7.935587] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10757 09:30:23.452322 <3>[ 7.940431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 09:30:23.458914 <6>[ 7.955218] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10759 09:30:23.468890 <6>[ 7.955303] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10760 09:30:23.478611 <6>[ 7.955743] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10761 09:30:23.489009 <3>[ 7.961726] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 09:30:23.495285 <3>[ 7.970796] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10763 09:30:23.505518 <3>[ 7.978353] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 09:30:23.508653 <6>[ 7.987547] videodev: Linux video capture interface: v2.00
10765 09:30:23.518770 <3>[ 7.991543] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 09:30:23.525199 <3>[ 7.991549] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 09:30:23.535304 <3>[ 7.991558] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 09:30:23.541716 <3>[ 7.991561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 09:30:23.551598 <3>[ 7.991618] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 09:30:23.558021 <5>[ 7.997245] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10771 09:30:23.561701 <6>[ 8.012962] Bluetooth: Core ver 2.22
10772 09:30:23.568225 <5>[ 8.015940] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10773 09:30:23.578073 <5>[ 8.016177] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10774 09:30:23.588026 <4>[ 8.016245] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10775 09:30:23.591155 <6>[ 8.016250] cfg80211: failed to load regulatory.db
10776 09:30:23.597680 <6>[ 8.033273] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10777 09:30:23.607440 <6>[ 8.035611] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10778 09:30:23.614415 <6>[ 8.035623] remoteproc remoteproc0: remote processor scp is now up
10779 09:30:23.617990 <6>[ 8.035707] NET: Registered PF_BLUETOOTH protocol family
10780 09:30:23.623977 <6>[ 8.035713] Bluetooth: HCI device and connection manager initialized
10781 09:30:23.631086 <6>[ 8.035750] Bluetooth: HCI socket layer initialized
10782 09:30:23.637798 <6>[ 8.035754] Bluetooth: L2CAP socket layer initialized
10783 09:30:23.641148 <6>[ 8.035763] Bluetooth: SCO socket layer initialized
10784 09:30:23.647975 <6>[ 8.049361] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10785 09:30:23.657097 <6>[ 8.051140] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10786 09:30:23.663952 <6>[ 8.052768] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10787 09:30:23.670663 <6>[ 8.086201] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10788 09:30:23.683522 <6>[ 8.093490] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10789 09:30:23.690010 <6>[ 8.097244] usbcore: registered new interface driver btusb
10790 09:30:23.700464 <4>[ 8.097918] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10791 09:30:23.706931 <3>[ 8.097934] Bluetooth: hci0: Failed to load firmware file (-2)
10792 09:30:23.710110 <3>[ 8.097938] Bluetooth: hci0: Failed to set up firmware (-2)
10793 09:30:23.723400 <4>[ 8.097942] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10794 09:30:23.726227 <6>[ 8.103277] usbcore: registered new interface driver uvcvideo
10795 09:30:23.736538 <6>[ 8.112353] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10796 09:30:23.743057 <6>[ 8.112445] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10797 09:30:23.746003 <6>[ 8.130525] mt7921e 0000:01:00.0: ASIC revision: 79610010
10798 09:30:23.850233 <6>[ 8.610553] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10799 09:30:23.853712 <6>[ 8.610553]
10800 09:30:23.856969 Begin: Loading essential drivers ... done.
10801 09:30:23.860372 Begin: Running /scripts/init-premount ... done.
10802 09:30:23.866429 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10803 09:30:23.876124 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10804 09:30:23.879684 Device /sys/class/net/eth0 found
10805 09:30:23.880115 done.
10806 09:30:23.889668 Begin: Waiting up to 180 secs for any network device to become available ... done.
10807 09:30:23.930615 IP-Config: eth0 hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10808 09:30:23.939494 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10809 09:30:23.945812 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10810 09:30:23.952318 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10811 09:30:23.959179 host : mt8192-asurada-spherion-r0-cbg-2
10812 09:30:23.965840 domain : lava-rack
10813 09:30:23.968965 rootserver: 192.168.201.1 rootpath:
10814 09:30:23.972163 filename :
10815 09:30:24.120273 <6>[ 8.881609] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10816 09:30:24.132534 done.
10817 09:30:24.141295 Begin: Running /scripts/nfs-bottom ... done.
10818 09:30:24.158873 Begin: Running /scripts/init-bottom ... done.
10819 09:30:25.545331 <6>[ 10.309384] NET: Registered PF_INET6 protocol family
10820 09:30:25.552997 <6>[ 10.317110] Segment Routing with IPv6
10821 09:30:25.556152 <6>[ 10.321053] In-situ OAM (IOAM) with IPv6
10822 09:30:25.732950 <30>[ 10.470682] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10823 09:30:25.739439 <30>[ 10.503811] systemd[1]: Detected architecture arm64.
10824 09:30:25.750520
10825 09:30:25.752879 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10826 09:30:25.753329
10827 09:30:25.776630 <30>[ 10.541182] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10828 09:30:26.972381 <30>[ 11.733463] systemd[1]: Queued start job for default target graphical.target.
10829 09:30:27.014406 <30>[ 11.775504] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10830 09:30:27.021121 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10831 09:30:27.043428 <30>[ 11.804343] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10832 09:30:27.053540 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10833 09:30:27.070991 <30>[ 11.832332] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10834 09:30:27.081420 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10835 09:30:27.098734 <30>[ 11.859916] systemd[1]: Created slice user.slice - User and Session Slice.
10836 09:30:27.105530 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10837 09:30:27.129920 <30>[ 11.887385] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10838 09:30:27.139604 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10839 09:30:27.157024 <30>[ 11.914839] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10840 09:30:27.163490 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10841 09:30:27.192474 <30>[ 11.943258] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10842 09:30:27.202054 <30>[ 11.963169] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10843 09:30:27.208823 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10844 09:30:27.226519 <30>[ 11.986975] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10845 09:30:27.236013 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10846 09:30:27.254510 <30>[ 12.015044] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10847 09:30:27.263807 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10848 09:30:27.278989 <30>[ 12.043120] systemd[1]: Reached target paths.target - Path Units.
10849 09:30:27.288772 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10850 09:30:27.306195 <30>[ 12.067077] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10851 09:30:27.313058 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10852 09:30:27.326256 <30>[ 12.090583] systemd[1]: Reached target slices.target - Slice Units.
10853 09:30:27.337166 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10854 09:30:27.350566 <30>[ 12.114481] systemd[1]: Reached target swap.target - Swaps.
10855 09:30:27.357123 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10856 09:30:27.373903 <30>[ 12.134664] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10857 09:30:27.383963 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10858 09:30:27.402742 <30>[ 12.163575] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10859 09:30:27.412497 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10860 09:30:27.433905 <30>[ 12.194952] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10861 09:30:27.443803 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10862 09:30:27.463883 <30>[ 12.224359] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10863 09:30:27.473228 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10864 09:30:27.489956 <30>[ 12.251269] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10865 09:30:27.496673 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10866 09:30:27.515570 <30>[ 12.276444] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10867 09:30:27.525507 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10868 09:30:27.545956 <30>[ 12.307020] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10869 09:30:27.555832 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10870 09:30:27.573820 <30>[ 12.335122] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10871 09:30:27.584503 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10872 09:30:27.649966 <30>[ 12.410988] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10873 09:30:27.656609 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10874 09:30:27.676738 <30>[ 12.437439] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10875 09:30:27.683090 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10876 09:30:27.706293 <30>[ 12.467408] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10877 09:30:27.712856 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10878 09:30:27.740548 <30>[ 12.495244] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10879 09:30:27.802654 <30>[ 12.563433] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10880 09:30:27.812575 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10881 09:30:27.834492 <30>[ 12.595712] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10882 09:30:27.840958 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10883 09:30:27.867180 <30>[ 12.628091] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10884 09:30:27.876896 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10885 09:30:27.899179 <30>[ 12.660297] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10886 09:30:27.905292 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10887 09:30:27.915419 <6>[ 12.676585] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10888 09:30:27.931201 <30>[ 12.692776] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10889 09:30:27.941506 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10890 09:30:27.963516 <30>[ 12.724411] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10891 09:30:27.969965 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10892 09:30:27.995481 <30>[ 12.756348] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10893 09:30:28.001690 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10894 09:30:28.008082 <6>[ 12.771834] fuse: init (API version 7.37)
10895 09:30:28.050559 <30>[ 12.811440] systemd[1]: Starting systemd-journald.service - Journal Service...
10896 09:30:28.057327 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10897 09:30:28.092331 <30>[ 12.853258] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10898 09:30:28.098473 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10899 09:30:28.126852 <30>[ 12.884274] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10900 09:30:28.132947 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10901 09:30:28.158134 <30>[ 12.919498] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10902 09:30:28.168435 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10903 09:30:28.231316 <30>[ 12.991682] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10904 09:30:28.241035 <3>[ 12.998085] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 09:30:28.248014 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10906 09:30:28.270483 <30>[ 13.031320] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10907 09:30:28.276952 <3>[ 13.032422] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 09:30:28.286932 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10909 09:30:28.306639 <30>[ 13.067031] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10910 09:30:28.313445 <3>[ 13.074151] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 09:30:28.322925 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10912 09:30:28.341768 <30>[ 13.102751] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10913 09:30:28.351585 <3>[ 13.104207] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 09:30:28.358480 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10915 09:30:28.378048 <30>[ 13.139343] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10916 09:30:28.388068 <3>[ 13.139755] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 09:30:28.395213 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10918 09:30:28.415071 <30>[ 13.175560] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10919 09:30:28.421180 <3>[ 13.178134] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 09:30:28.431577 <30>[ 13.183498] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10921 09:30:28.438104 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10922 09:30:28.452299 <3>[ 13.213185] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 09:30:28.461969 <30>[ 13.223339] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10924 09:30:28.469043 <30>[ 13.230939] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10925 09:30:28.482945 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m <3>[ 13.243894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 09:30:28.485954 - Load Kernel Module dm_mod.
10927 09:30:28.504132 <30>[ 13.267657] systemd[1]: modprobe@drm.service: Deactivated successfully.
10928 09:30:28.513982 <3>[ 13.274078] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 09:30:28.520162 <30>[ 13.275425] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10930 09:30:28.530525 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10931 09:30:28.543129 <3>[ 13.304158] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 09:30:28.554146 <30>[ 13.314871] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10933 09:30:28.564305 <30>[ 13.323316] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10934 09:30:28.570963 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10935 09:30:28.588090 <30>[ 13.351960] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10936 09:30:28.598438 <30>[ 13.359684] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10937 09:30:28.604958 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10938 09:30:28.626581 <30>[ 13.387580] systemd[1]: Started systemd-journald.service - Journal Service.
10939 09:30:28.633305 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10940 09:30:28.652477 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10941 09:30:28.673886 <4>[ 13.427612] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10942 09:30:28.680463 <3>[ 13.443273] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10943 09:30:28.690194 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10944 09:30:28.708881 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10945 09:30:28.726401 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10946 09:30:28.742841 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10947 09:30:28.764609 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10948 09:30:28.818262 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10949 09:30:28.843592 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10950 09:30:28.868703 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10951 09:30:28.894655 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10952 09:30:28.932897 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10953 09:30:28.939506 <46>[ 13.700940] systemd-journald[308]: Received client request to flush runtime journal.
10954 09:30:28.957557 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10955 09:30:28.999340 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10956 09:30:29.022368 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10957 09:30:29.047651 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10958 09:30:30.090925 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10959 09:30:30.114510 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10960 09:30:30.162416 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10961 09:30:30.406903 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10962 09:30:30.522253 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10963 09:30:30.538204 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10964 09:30:30.557628 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10965 09:30:30.601561 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10966 09:30:30.622775 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10967 09:30:30.921970 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10968 09:30:30.984397 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10969 09:30:31.054964 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10970 09:30:31.333354 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10971 09:30:31.357998 <6>[ 16.123018] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10972 09:30:31.383408 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10973 09:30:31.455176 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10974 09:30:31.545510 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10975 09:30:31.568625 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10976 09:30:31.586675 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10977 09:30:31.606363 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10978 09:30:31.712331 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10979 09:30:31.732328 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10980 09:30:31.745721 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10981 09:30:31.765850 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10982 09:30:31.826330 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10983 09:30:31.845014 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10984 09:30:31.861546 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10985 09:30:31.881426 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10986 09:30:31.897632 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10987 09:30:31.923705 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10988 09:30:31.945293 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10989 09:30:31.961879 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10990 09:30:31.981798 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10991 09:30:32.001526 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10992 09:30:32.017218 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10993 09:30:32.036147 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10994 09:30:32.053239 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10995 09:30:32.069670 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10996 09:30:32.110815 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10997 09:30:32.145514 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10998 09:30:32.192116 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10999 09:30:32.215544 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11000 09:30:32.234160 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11001 09:30:32.288812 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11002 09:30:32.341863 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11003 09:30:32.392050 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11004 09:30:32.415314 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11005 09:30:32.514001 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11006 09:30:32.557178 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11007 09:30:32.584066 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11008 09:30:32.604158 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11009 09:30:32.622542 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11010 09:30:32.680445 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11011 09:30:32.729317 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11012 09:30:32.817137
11013 09:30:32.820797 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11014 09:30:32.820883
11015 09:30:32.823856 debian-bookworm-arm64 login: root (automatic login)
11016 09:30:32.823938
11017 09:30:33.151212 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
11018 09:30:33.151352
11019 09:30:33.157238 The programs included with the Debian GNU/Linux system are free software;
11020 09:30:33.164323 the exact distribution terms for each program are described in the
11021 09:30:33.167229 individual files in /usr/share/doc/*/copyright.
11022 09:30:33.167311
11023 09:30:33.173604 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11024 09:30:33.176772 permitted by applicable law.
11025 09:30:34.312103 Matched prompt #10: / #
11027 09:30:34.313234 Setting prompt string to ['/ #']
11028 09:30:34.313716 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11030 09:30:34.314704 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11031 09:30:34.315149 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
11032 09:30:34.315502 Setting prompt string to ['/ #']
11033 09:30:34.315809 Forcing a shell prompt, looking for ['/ #']
11035 09:30:34.366427 / #
11036 09:30:34.367017 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11037 09:30:34.367385 Waiting using forced prompt support (timeout 00:02:30)
11038 09:30:34.372787
11039 09:30:34.373548 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11040 09:30:34.374031 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
11042 09:30:34.475106 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407666/extract-nfsrootfs-m2jz1nta'
11043 09:30:34.480283 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407666/extract-nfsrootfs-m2jz1nta'
11045 09:30:34.581184 / # export NFS_SERVER_IP='192.168.201.1'
11046 09:30:34.587479 export NFS_SERVER_IP='192.168.201.1'
11047 09:30:34.588283 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11048 09:30:34.588779 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
11049 09:30:34.589224 end: 2 depthcharge-action (duration 00:01:39) [common]
11050 09:30:34.589727 start: 3 lava-test-retry (timeout 00:07:41) [common]
11051 09:30:34.590166 start: 3.1 lava-test-shell (timeout 00:07:41) [common]
11052 09:30:34.590550 Using namespace: common
11054 09:30:34.691428 / # #
11055 09:30:34.691665 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11056 09:30:34.697799 #
11057 09:30:34.698197 Using /lava-14407666
11059 09:30:34.798833 / # export SHELL=/bin/bash
11060 09:30:34.805636 export SHELL=/bin/bash
11062 09:30:34.907078 / # . /lava-14407666/environment
11063 09:30:34.913556 . /lava-14407666/environment
11065 09:30:35.021864 / # /lava-14407666/bin/lava-test-runner /lava-14407666/0
11066 09:30:35.022453 Test shell timeout: 10s (minimum of the action and connection timeout)
11067 09:30:35.028170 /lava-14407666/bin/lava-test-runner /lava-14407666/0
11068 09:30:35.333172 + export TESTRUN_ID=0_timesync-off
11069 09:30:35.336606 + TESTRUN_ID=0_timesync-off
11070 09:30:35.340107 + cd /lava-14407666/0/tests/0_timesync-off
11071 09:30:35.343293 ++ cat uuid
11072 09:30:35.352282 + UUID=14407666_1.6.2.3.1
11073 09:30:35.352366 + set +x
11074 09:30:35.358357 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14407666_1.6.2.3.1>
11075 09:30:35.358620 Received signal: <STARTRUN> 0_timesync-off 14407666_1.6.2.3.1
11076 09:30:35.358696 Starting test lava.0_timesync-off (14407666_1.6.2.3.1)
11077 09:30:35.358782 Skipping test definition patterns.
11078 09:30:35.361512 + systemctl stop systemd-timesyncd
11079 09:30:35.429703 + set +x
11080 09:30:35.432889 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14407666_1.6.2.3.1>
11081 09:30:35.433611 Received signal: <ENDRUN> 0_timesync-off 14407666_1.6.2.3.1
11082 09:30:35.434054 Ending use of test pattern.
11083 09:30:35.434389 Ending test lava.0_timesync-off (14407666_1.6.2.3.1), duration 0.08
11085 09:30:35.530648 + export TESTRUN_ID=1_kselftest-arm64
11086 09:30:35.531150 + TESTRUN_ID=1_kselftest-arm64
11087 09:30:35.537052 + cd /lava-14407666/0/tests/1_kselftest-arm64
11088 09:30:35.537534 ++ cat uuid
11089 09:30:35.545083 + UUID=14407666_1.6.2.3.5
11090 09:30:35.545166 + set +x
11091 09:30:35.551569 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14407666_1.6.2.3.5>
11092 09:30:35.551826 Received signal: <STARTRUN> 1_kselftest-arm64 14407666_1.6.2.3.5
11093 09:30:35.551899 Starting test lava.1_kselftest-arm64 (14407666_1.6.2.3.5)
11094 09:30:35.551980 Skipping test definition patterns.
11095 09:30:35.554616 + cd ./automated/linux/kselftest/
11096 09:30:35.581420 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11097 09:30:35.622216 INFO: install_deps skipped
11098 09:30:36.128491 --2024-06-18 09:30:35-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11099 09:30:36.143357 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11100 09:30:36.272647 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11101 09:30:36.402503 HTTP request sent, awaiting response... 200 OK
11102 09:30:36.405571 Length: 1642672 (1.6M) [application/octet-stream]
11103 09:30:36.409216 Saving to: 'kselftest_armhf.tar.gz'
11104 09:30:36.409664
11105 09:30:36.409991
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11108 09:30:37.225897 kselftest_armhf.tar 13%[=> ] 217.50K 421KB/s
11109 09:30:37.357127 kselftest_armhf.tar 51%[=========> ] 829.78K 1009KB/s
11110 09:30:37.363368 kselftest_armhf.tar 100%[===================>] 1.57M 1.64MB/s in 1.0s
11111 09:30:37.363486
11112 09:30:37.514242 2024-06-18 09:30:36 (1.64 MB/s) - 'kselftest_armhf.tar.gz' saved [1642672/1642672]
11113 09:30:37.514419
11114 09:30:43.270196 skiplist:
11115 09:30:43.274123 ========================================
11116 09:30:43.277122 ========================================
11117 09:30:43.336467 arm64:tags_test
11118 09:30:43.339960 arm64:run_tags_test.sh
11119 09:30:43.340226 arm64:fake_sigreturn_bad_magic
11120 09:30:43.343105 arm64:fake_sigreturn_bad_size
11121 09:30:43.346273 arm64:fake_sigreturn_bad_size_for_magic0
11122 09:30:43.349680 arm64:fake_sigreturn_duplicated_fpsimd
11123 09:30:43.353121 arm64:fake_sigreturn_misaligned_sp
11124 09:30:43.356145 arm64:fake_sigreturn_missing_fpsimd
11125 09:30:43.359887 arm64:fake_sigreturn_sme_change_vl
11126 09:30:43.363205 arm64:fake_sigreturn_sve_change_vl
11127 09:30:43.366197 arm64:mangle_pstate_invalid_compat_toggle
11128 09:30:43.369678 arm64:mangle_pstate_invalid_daif_bits
11129 09:30:43.372719 arm64:mangle_pstate_invalid_mode_el1h
11130 09:30:43.376354 arm64:mangle_pstate_invalid_mode_el1t
11131 09:30:43.379497 arm64:mangle_pstate_invalid_mode_el2h
11132 09:30:43.382579 arm64:mangle_pstate_invalid_mode_el2t
11133 09:30:43.389253 arm64:mangle_pstate_invalid_mode_el3h
11134 09:30:43.392950 arm64:mangle_pstate_invalid_mode_el3t
11135 09:30:43.393428 arm64:sme_trap_no_sm
11136 09:30:43.395843 arm64:sme_trap_non_streaming
11137 09:30:43.396252 arm64:sme_trap_za
11138 09:30:43.399571 arm64:sme_vl
11139 09:30:43.399983 arm64:ssve_regs
11140 09:30:43.402560 arm64:sve_regs
11141 09:30:43.402973 arm64:sve_vl
11142 09:30:43.403294 arm64:za_no_regs
11143 09:30:43.405684 arm64:za_regs
11144 09:30:43.406096 arm64:pac
11145 09:30:43.409369 arm64:fp-stress
11146 09:30:43.409781 arm64:sve-ptrace
11147 09:30:43.412456 arm64:sve-probe-vls
11148 09:30:43.412866 arm64:vec-syscfg
11149 09:30:43.416035 arm64:za-fork
11150 09:30:43.416445 arm64:za-ptrace
11151 09:30:43.418937 arm64:check_buffer_fill
11152 09:30:43.419347 arm64:check_child_memory
11153 09:30:43.422700 arm64:check_gcr_el1_cswitch
11154 09:30:43.425692 arm64:check_ksm_options
11155 09:30:43.426105 arm64:check_mmap_options
11156 09:30:43.428916 arm64:check_prctl
11157 09:30:43.432074 arm64:check_tags_inclusion
11158 09:30:43.432485 arm64:check_user_mem
11159 09:30:43.435849 arm64:btitest
11160 09:30:43.436261 arm64:nobtitest
11161 09:30:43.436583 arm64:hwcap
11162 09:30:43.439160 arm64:ptrace
11163 09:30:43.439572 arm64:syscall-abi
11164 09:30:43.442060 arm64:tpidr2
11165 09:30:43.445538 ============== Tests to run ===============
11166 09:30:43.445955 arm64:tags_test
11167 09:30:43.449057 arm64:run_tags_test.sh
11168 09:30:43.452018 arm64:fake_sigreturn_bad_magic
11169 09:30:43.455117 arm64:fake_sigreturn_bad_size
11170 09:30:43.459262 arm64:fake_sigreturn_bad_size_for_magic0
11171 09:30:43.461930 arm64:fake_sigreturn_duplicated_fpsimd
11172 09:30:43.465172 arm64:fake_sigreturn_misaligned_sp
11173 09:30:43.468378 arm64:fake_sigreturn_missing_fpsimd
11174 09:30:43.471886 arm64:fake_sigreturn_sme_change_vl
11175 09:30:43.475097 arm64:fake_sigreturn_sve_change_vl
11176 09:30:43.478323 arm64:mangle_pstate_invalid_compat_toggle
11177 09:30:43.481748 arm64:mangle_pstate_invalid_daif_bits
11178 09:30:43.485119 arm64:mangle_pstate_invalid_mode_el1h
11179 09:30:43.488291 arm64:mangle_pstate_invalid_mode_el1t
11180 09:30:43.491404 arm64:mangle_pstate_invalid_mode_el2h
11181 09:30:43.494960 arm64:mangle_pstate_invalid_mode_el2t
11182 09:30:43.498876 arm64:mangle_pstate_invalid_mode_el3h
11183 09:30:43.501475 arm64:mangle_pstate_invalid_mode_el3t
11184 09:30:43.501882 arm64:sme_trap_no_sm
11185 09:30:43.505110 arm64:sme_trap_non_streaming
11186 09:30:43.508199 arm64:sme_trap_za
11187 09:30:43.508609 arm64:sme_vl
11188 09:30:43.511461 arm64:ssve_regs
11189 09:30:43.511871 arm64:sve_regs
11190 09:30:43.512191 arm64:sve_vl
11191 09:30:43.514922 arm64:za_no_regs
11192 09:30:43.515365 arm64:za_regs
11193 09:30:43.515700 arm64:pac
11194 09:30:43.518234 arm64:fp-stress
11195 09:30:43.518646 arm64:sve-ptrace
11196 09:30:43.521141 arm64:sve-probe-vls
11197 09:30:43.521628 arm64:vec-syscfg
11198 09:30:43.524624 arm64:za-fork
11199 09:30:43.525036 arm64:za-ptrace
11200 09:30:43.527706 arm64:check_buffer_fill
11201 09:30:43.531348 arm64:check_child_memory
11202 09:30:43.531761 arm64:check_gcr_el1_cswitch
11203 09:30:43.534591 arm64:check_ksm_options
11204 09:30:43.537653 arm64:check_mmap_options
11205 09:30:43.538073 arm64:check_prctl
11206 09:30:43.541337 arm64:check_tags_inclusion
11207 09:30:43.544440 arm64:check_user_mem
11208 09:30:43.544958 arm64:btitest
11209 09:30:43.545407 arm64:nobtitest
11210 09:30:43.547974 arm64:hwcap
11211 09:30:43.548417 arm64:ptrace
11212 09:30:43.550989 arm64:syscall-abi
11213 09:30:43.551401 arm64:tpidr2
11214 09:30:43.554118 ===========End Tests to run ===============
11215 09:30:43.557721 shardfile-arm64 pass
11216 09:30:43.845611 <12>[ 28.611637] kselftest: Running tests in arm64
11217 09:30:43.856822 TAP version 13
11218 09:30:43.874527 1..48
11219 09:30:43.893473 # selftests: arm64: tags_test
11220 09:30:44.382036 ok 1 selftests: arm64: tags_test
11221 09:30:44.401186 # selftests: arm64: run_tags_test.sh
11222 09:30:44.470059 # --------------------
11223 09:30:44.473703 # running tags test
11224 09:30:44.473960 # --------------------
11225 09:30:44.477028 # [PASS]
11226 09:30:44.480021 ok 2 selftests: arm64: run_tags_test.sh
11227 09:30:44.496461 # selftests: arm64: fake_sigreturn_bad_magic
11228 09:30:44.566149 # Registered handlers for all signals.
11229 09:30:44.566712 # Detected MINSTKSIGSZ:4720
11230 09:30:44.569090 # Testcase initialized.
11231 09:30:44.572675 # uc context validated.
11232 09:30:44.575810 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11233 09:30:44.578992 # Handled SIG_COPYCTX
11234 09:30:44.579407 # Available space:3568
11235 09:30:44.585840 # Using badly built context - ERR: BAD MAGIC !
11236 09:30:44.592031 # SIG_OK -- SP:0xFFFFE802DD40 si_addr@:0xffffe802dd40 si_code:2 token@:0xffffe802cae0 offset:-4704
11237 09:30:44.595442 # ==>> completed. PASS(1)
11238 09:30:44.602035 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11239 09:30:44.608556 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE802CAE0
11240 09:30:44.615334 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11241 09:30:44.618946 # selftests: arm64: fake_sigreturn_bad_size
11242 09:30:44.676542 # Registered handlers for all signals.
11243 09:30:44.677180 # Detected MINSTKSIGSZ:4720
11244 09:30:44.680204 # Testcase initialized.
11245 09:30:44.683215 # uc context validated.
11246 09:30:44.686178 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11247 09:30:44.689988 # Handled SIG_COPYCTX
11248 09:30:44.690563 # Available space:3568
11249 09:30:44.692978 # uc context validated.
11250 09:30:44.699778 # Using badly built context - ERR: Bad size for esr_context
11251 09:30:44.706303 # SIG_OK -- SP:0xFFFFF7707140 si_addr@:0xfffff7707140 si_code:2 token@:0xfffff7705ee0 offset:-4704
11252 09:30:44.709396 # ==>> completed. PASS(1)
11253 09:30:44.715795 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11254 09:30:44.721863 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF7705EE0
11255 09:30:44.725623 ok 4 selftests: arm64: fake_sigreturn_bad_size
11256 09:30:44.732017 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11257 09:30:44.751623 # Registered handlers for all signals.
11258 09:30:44.751823 # Detected MINSTKSIGSZ:4720
11259 09:30:44.755042 # Testcase initialized.
11260 09:30:44.758369 # uc context validated.
11261 09:30:44.761715 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11262 09:30:44.765022 # Handled SIG_COPYCTX
11263 09:30:44.765193 # Available space:3568
11264 09:30:44.771483 # Using badly built context - ERR: Bad size for terminator
11265 09:30:44.781472 # SIG_OK -- SP:0xFFFFF3B706E0 si_addr@:0xfffff3b706e0 si_code:2 token@:0xfffff3b6f480 offset:-4704
11266 09:30:44.781771 # ==>> completed. PASS(1)
11267 09:30:44.791594 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11268 09:30:44.798345 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF3B6F480
11269 09:30:44.801410 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11270 09:30:44.808448 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11271 09:30:44.840456 # Registered handlers for all signals.
11272 09:30:44.841020 # Detected MINSTKSIGSZ:4720
11273 09:30:44.843548 # Testcase initialized.
11274 09:30:44.847128 # uc context validated.
11275 09:30:44.850508 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11276 09:30:44.853658 # Handled SIG_COPYCTX
11277 09:30:44.854075 # Available space:3568
11278 09:30:44.860333 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11279 09:30:44.870125 # SIG_OK -- SP:0xFFFFD560EAC0 si_addr@:0xffffd560eac0 si_code:2 token@:0xffffd560d860 offset:-4704
11280 09:30:44.870637 # ==>> completed. PASS(1)
11281 09:30:44.879740 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11282 09:30:44.886486 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD560D860
11283 09:30:44.889732 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11284 09:30:44.893390 # selftests: arm64: fake_sigreturn_misaligned_sp
11285 09:30:44.937427 # Registered handlers for all signals.
11286 09:30:44.937980 # Detected MINSTKSIGSZ:4720
11287 09:30:44.941064 # Testcase initialized.
11288 09:30:44.944045 # uc context validated.
11289 09:30:44.947241 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11290 09:30:44.950879 # Handled SIG_COPYCTX
11291 09:30:44.957429 # SIG_OK -- SP:0xFFFFF8C23543 si_addr@:0xfffff8c23543 si_code:2 token@:0xfffff8c23543 offset:0
11292 09:30:44.960650 # ==>> completed. PASS(1)
11293 09:30:44.967304 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11294 09:30:44.973976 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF8C23543
11295 09:30:44.980230 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11296 09:30:44.983384 # selftests: arm64: fake_sigreturn_missing_fpsimd
11297 09:30:45.032600 # Registered handlers for all signals.
11298 09:30:45.033151 # Detected MINSTKSIGSZ:4720
11299 09:30:45.035586 # Testcase initialized.
11300 09:30:45.039159 # uc context validated.
11301 09:30:45.042139 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11302 09:30:45.045414 # Handled SIG_COPYCTX
11303 09:30:45.048541 # Mangling template header. Spare space:4096
11304 09:30:45.052166 # Using badly built context - ERR: Missing FPSIMD
11305 09:30:45.062205 # SIG_OK -- SP:0xFFFFF040C7B0 si_addr@:0xfffff040c7b0 si_code:2 token@:0xfffff040b550 offset:-4704
11306 09:30:45.065534 # ==>> completed. PASS(1)
11307 09:30:45.072040 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11308 09:30:45.078202 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF040B550
11309 09:30:45.081864 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11310 09:30:45.088035 # selftests: arm64: fake_sigreturn_sme_change_vl
11311 09:30:45.138212 # Registered handlers for all signals.
11312 09:30:45.138753 # Detected MINSTKSIGSZ:4720
11313 09:30:45.141445 # ==>> completed. SKIP.
11314 09:30:45.148777 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11315 09:30:45.151311 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11316 09:30:45.167506 # selftests: arm64: fake_sigreturn_sve_change_vl
11317 09:30:45.242015 # Registered handlers for all signals.
11318 09:30:45.242574 # Detected MINSTKSIGSZ:4720
11319 09:30:45.245519 # ==>> completed. SKIP.
11320 09:30:45.252188 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11321 09:30:45.255049 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11322 09:30:45.267010 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11323 09:30:45.332477 # Registered handlers for all signals.
11324 09:30:45.333023 # Detected MINSTKSIGSZ:4720
11325 09:30:45.335550 # Testcase initialized.
11326 09:30:45.339140 # uc context validated.
11327 09:30:45.339598 # Handled SIG_TRIG
11328 09:30:45.348905 # SIG_OK -- SP:0xFFFFE24C1050 si_addr@:0xffffe24c1050 si_code:2 token@:(nil) offset:-281474478379088
11329 09:30:45.352111 # ==>> completed. PASS(1)
11330 09:30:45.358753 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11331 09:30:45.365031 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11332 09:30:45.368488 # selftests: arm64: mangle_pstate_invalid_daif_bits
11333 09:30:45.423648 # Registered handlers for all signals.
11334 09:30:45.423872 # Detected MINSTKSIGSZ:4720
11335 09:30:45.426696 # Testcase initialized.
11336 09:30:45.430366 # uc context validated.
11337 09:30:45.430496 # Handled SIG_TRIG
11338 09:30:45.439968 # SIG_OK -- SP:0xFFFFEE506940 si_addr@:0xffffee506940 si_code:2 token@:(nil) offset:-281474679990592
11339 09:30:45.443659 # ==>> completed. PASS(1)
11340 09:30:45.450118 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11341 09:30:45.453869 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11342 09:30:45.460340 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11343 09:30:45.519644 # Registered handlers for all signals.
11344 09:30:45.520146 # Detected MINSTKSIGSZ:4720
11345 09:30:45.523085 # Testcase initialized.
11346 09:30:45.525953 # uc context validated.
11347 09:30:45.526380 # Handled SIG_TRIG
11348 09:30:45.535692 # SIG_OK -- SP:0xFFFFD0A16AA0 si_addr@:0xffffd0a16aa0 si_code:2 token@:(nil) offset:-281474181982880
11349 09:30:45.539296 # ==>> completed. PASS(1)
11350 09:30:45.545970 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11351 09:30:45.549070 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11352 09:30:45.555151 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11353 09:30:45.615430 # Registered handlers for all signals.
11354 09:30:45.615996 # Detected MINSTKSIGSZ:4720
11355 09:30:45.618658 # Testcase initialized.
11356 09:30:45.622035 # uc context validated.
11357 09:30:45.622454 # Handled SIG_TRIG
11358 09:30:45.632087 # SIG_OK -- SP:0xFFFFD7D1A980 si_addr@:0xffffd7d1a980 si_code:2 token@:(nil) offset:-281474302585216
11359 09:30:45.634941 # ==>> completed. PASS(1)
11360 09:30:45.641672 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11361 09:30:45.645330 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11362 09:30:45.651283 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11363 09:30:45.705690 # Registered handlers for all signals.
11364 09:30:45.706199 # Detected MINSTKSIGSZ:4720
11365 09:30:45.709110 # Testcase initialized.
11366 09:30:45.712526 # uc context validated.
11367 09:30:45.712942 # Handled SIG_TRIG
11368 09:30:45.722330 # SIG_OK -- SP:0xFFFFF9EB0A10 si_addr@:0xfffff9eb0a10 si_code:2 token@:(nil) offset:-281474874673680
11369 09:30:45.725611 # ==>> completed. PASS(1)
11370 09:30:45.732043 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11371 09:30:45.735748 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11372 09:30:45.742224 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11373 09:30:45.787652 # Registered handlers for all signals.
11374 09:30:45.788190 # Detected MINSTKSIGSZ:4720
11375 09:30:45.790415 # Testcase initialized.
11376 09:30:45.793512 # uc context validated.
11377 09:30:45.793935 # Handled SIG_TRIG
11378 09:30:45.803443 # SIG_OK -- SP:0xFFFFD9DC1170 si_addr@:0xffffd9dc1170 si_code:2 token@:(nil) offset:-281474336821616
11379 09:30:45.807000 # ==>> completed. PASS(1)
11380 09:30:45.813733 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11381 09:30:45.816639 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11382 09:30:45.823558 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11383 09:30:45.872390 # Registered handlers for all signals.
11384 09:30:45.872966 # Detected MINSTKSIGSZ:4720
11385 09:30:45.875443 # Testcase initialized.
11386 09:30:45.879125 # uc context validated.
11387 09:30:45.879543 # Handled SIG_TRIG
11388 09:30:45.888812 # SIG_OK -- SP:0xFFFFEFA8C6E0 si_addr@:0xffffefa8c6e0 si_code:2 token@:(nil) offset:-281474702558944
11389 09:30:45.892026 # ==>> completed. PASS(1)
11390 09:30:45.898616 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11391 09:30:45.901767 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11392 09:30:45.908120 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11393 09:30:45.970080 # Registered handlers for all signals.
11394 09:30:45.970588 # Detected MINSTKSIGSZ:4720
11395 09:30:45.973712 # Testcase initialized.
11396 09:30:45.976566 # uc context validated.
11397 09:30:45.976985 # Handled SIG_TRIG
11398 09:30:45.986770 # SIG_OK -- SP:0xFFFFEBD52DD0 si_addr@:0xffffebd52dd0 si_code:2 token@:(nil) offset:-281474638360016
11399 09:30:45.989754 # ==>> completed. PASS(1)
11400 09:30:45.996587 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11401 09:30:45.999795 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11402 09:30:46.003462 # selftests: arm64: sme_trap_no_sm
11403 09:30:46.091656 # Registered handlers for all signals.
11404 09:30:46.092220 # Detected MINSTKSIGSZ:4720
11405 09:30:46.094811 # ==>> completed. SKIP.
11406 09:30:46.104552 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11407 09:30:46.107588 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11408 09:30:46.114498 # selftests: arm64: sme_trap_non_streaming
11409 09:30:46.202420 # Registered handlers for all signals.
11410 09:30:46.202920 # Detected MINSTKSIGSZ:4720
11411 09:30:46.205431 # ==>> completed. SKIP.
11412 09:30:46.215386 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11413 09:30:46.222176 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11414 09:30:46.225357 # selftests: arm64: sme_trap_za
11415 09:30:46.298640 # Registered handlers for all signals.
11416 09:30:46.299169 # Detected MINSTKSIGSZ:4720
11417 09:30:46.302225 # Testcase initialized.
11418 09:30:46.312124 # SIG_OK -- SP:0xFFFFF5D54F50 si_addr@:0xaaaac9e52510 si_code:1 token@:(nil) offset:-187650508399888
11419 09:30:46.312572 # ==>> completed. PASS(1)
11420 09:30:46.322093 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11421 09:30:46.325171 ok 21 selftests: arm64: sme_trap_za
11422 09:30:46.325645 # selftests: arm64: sme_vl
11423 09:30:46.394800 # Registered handlers for all signals.
11424 09:30:46.395342 # Detected MINSTKSIGSZ:4720
11425 09:30:46.398412 # ==>> completed. SKIP.
11426 09:30:46.404888 # # SME VL :: Check that we get the right SME VL reported
11427 09:30:46.407960 ok 22 selftests: arm64: sme_vl # SKIP
11428 09:30:46.416284 # selftests: arm64: ssve_regs
11429 09:30:46.504377 # Registered handlers for all signals.
11430 09:30:46.504949 # Detected MINSTKSIGSZ:4720
11431 09:30:46.507958 # ==>> completed. SKIP.
11432 09:30:46.514638 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11433 09:30:46.520991 ok 23 selftests: arm64: ssve_regs # SKIP
11434 09:30:46.526542 # selftests: arm64: sve_regs
11435 09:30:46.591748 # Registered handlers for all signals.
11436 09:30:46.592084 # Detected MINSTKSIGSZ:4720
11437 09:30:46.594664 # ==>> completed. SKIP.
11438 09:30:46.601245 # # SVE registers :: Check that we get the right SVE registers reported
11439 09:30:46.604368 ok 24 selftests: arm64: sve_regs # SKIP
11440 09:30:46.612565 # selftests: arm64: sve_vl
11441 09:30:46.687786 # Registered handlers for all signals.
11442 09:30:46.688292 # Detected MINSTKSIGSZ:4720
11443 09:30:46.690682 # ==>> completed. SKIP.
11444 09:30:46.694151 # # SVE VL :: Check that we get the right SVE VL reported
11445 09:30:46.700525 ok 25 selftests: arm64: sve_vl # SKIP
11446 09:30:46.708369 # selftests: arm64: za_no_regs
11447 09:30:46.779400 # Registered handlers for all signals.
11448 09:30:46.779888 # Detected MINSTKSIGSZ:4720
11449 09:30:46.782989 # ==>> completed. SKIP.
11450 09:30:46.789491 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11451 09:30:46.792627 ok 26 selftests: arm64: za_no_regs # SKIP
11452 09:30:46.798906 # selftests: arm64: za_regs
11453 09:30:46.864782 # Registered handlers for all signals.
11454 09:30:46.865404 # Detected MINSTKSIGSZ:4720
11455 09:30:46.868191 # ==>> completed. SKIP.
11456 09:30:46.874528 # # ZA register :: Check that we get the right ZA registers reported
11457 09:30:46.877821 ok 27 selftests: arm64: za_regs # SKIP
11458 09:30:46.885731 # selftests: arm64: pac
11459 09:30:46.948229 # TAP version 13
11460 09:30:46.948448 # 1..7
11461 09:30:46.951466 # # Starting 7 tests from 1 test cases.
11462 09:30:46.954967 # # RUN global.corrupt_pac ...
11463 09:30:46.958402 # # SKIP PAUTH not enabled
11464 09:30:46.961733 # # OK global.corrupt_pac
11465 09:30:46.965068 # ok 1 # SKIP PAUTH not enabled
11466 09:30:46.971850 # # RUN global.pac_instructions_not_nop ...
11467 09:30:46.975044 # # SKIP PAUTH not enabled
11468 09:30:46.978032 # # OK global.pac_instructions_not_nop
11469 09:30:46.981893 # ok 2 # SKIP PAUTH not enabled
11470 09:30:46.987869 # # RUN global.pac_instructions_not_nop_generic ...
11471 09:30:46.991382 # # SKIP Generic PAUTH not enabled
11472 09:30:46.998104 # # OK global.pac_instructions_not_nop_generic
11473 09:30:47.001222 # ok 3 # SKIP Generic PAUTH not enabled
11474 09:30:47.004577 # # RUN global.single_thread_different_keys ...
11475 09:30:47.007762 # # SKIP PAUTH not enabled
11476 09:30:47.014795 # # OK global.single_thread_different_keys
11477 09:30:47.017750 # ok 4 # SKIP PAUTH not enabled
11478 09:30:47.021225 # # RUN global.exec_changed_keys ...
11479 09:30:47.024283 # # SKIP PAUTH not enabled
11480 09:30:47.027720 # # OK global.exec_changed_keys
11481 09:30:47.031373 # ok 5 # SKIP PAUTH not enabled
11482 09:30:47.034332 # # RUN global.context_switch_keep_keys ...
11483 09:30:47.037438 # # SKIP PAUTH not enabled
11484 09:30:47.043789 # # OK global.context_switch_keep_keys
11485 09:30:47.047661 # ok 6 # SKIP PAUTH not enabled
11486 09:30:47.050583 # # RUN global.context_switch_keep_keys_generic ...
11487 09:30:47.054008 # # SKIP Generic PAUTH not enabled
11488 09:30:47.060886 # # OK global.context_switch_keep_keys_generic
11489 09:30:47.063930 # ok 7 # SKIP Generic PAUTH not enabled
11490 09:30:47.067853 # # PASSED: 7 / 7 tests passed.
11491 09:30:47.073805 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11492 09:30:47.074334 ok 28 selftests: arm64: pac
11493 09:30:47.077149 # selftests: arm64: fp-stress
11494 09:30:53.196199 <6>[ 37.966411] vpu: disabling
11495 09:30:53.199268 <6>[ 37.969461] vproc2: disabling
11496 09:30:53.202605 <6>[ 37.972940] vproc1: disabling
11497 09:30:53.205981 <6>[ 37.976221] vaud18: disabling
11498 09:30:53.212204 <6>[ 37.979659] vsram_others: disabling
11499 09:30:53.216203 <6>[ 37.983553] va09: disabling
11500 09:30:53.219106 <6>[ 37.986674] vsram_md: disabling
11501 09:30:53.222024 <6>[ 37.990173] Vgpu: disabling
11502 09:30:57.035961 # TAP version 13
11503 09:30:57.036520 # 1..16
11504 09:30:57.039562 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11505 09:30:57.042678 # # Will run for 10s
11506 09:30:57.043140 # # Started FPSIMD-0-0
11507 09:30:57.046168 # # Started FPSIMD-0-1
11508 09:30:57.049621 # # Started FPSIMD-1-0
11509 09:30:57.050089 # # Started FPSIMD-1-1
11510 09:30:57.052512 # # Started FPSIMD-2-0
11511 09:30:57.052932 # # Started FPSIMD-2-1
11512 09:30:57.056123 # # Started FPSIMD-3-0
11513 09:30:57.059366 # # Started FPSIMD-3-1
11514 09:30:57.059849 # # Started FPSIMD-4-0
11515 09:30:57.062571 # # Started FPSIMD-4-1
11516 09:30:57.065618 # # Started FPSIMD-5-0
11517 09:30:57.066065 # # Started FPSIMD-5-1
11518 09:30:57.069355 # # Started FPSIMD-6-0
11519 09:30:57.069802 # # Started FPSIMD-6-1
11520 09:30:57.072465 # # Started FPSIMD-7-0
11521 09:30:57.075932 # # Started FPSIMD-7-1
11522 09:30:57.078979 # # FPSIMD-0-0: Vector length: 128 bits
11523 09:30:57.082262 # # FPSIMD-0-0: PID: 1170
11524 09:30:57.085688 # # FPSIMD-0-1: Vector length: 128 bits
11525 09:30:57.086189 # # FPSIMD-0-1: PID: 1171
11526 09:30:57.089175 # # FPSIMD-2-1: Vector length: 128 bits
11527 09:30:57.092394 # # FPSIMD-2-1: PID: 1175
11528 09:30:57.095211 # # FPSIMD-1-1: Vector length: 128 bits
11529 09:30:57.098982 # # FPSIMD-1-1: PID: 1173
11530 09:30:57.102054 # # FPSIMD-3-0: Vector length: 128 bits
11531 09:30:57.105931 # # FPSIMD-3-0: PID: 1176
11532 09:30:57.108829 # # FPSIMD-1-0: Vector length: 128 bits
11533 09:30:57.109428 # # FPSIMD-1-0: PID: 1172
11534 09:30:57.115228 # # FPSIMD-5-0: Vector length: 128 bits
11535 09:30:57.115754 # # FPSIMD-5-0: PID: 1180
11536 09:30:57.118995 # # FPSIMD-7-1: Vector length: 128 bits
11537 09:30:57.122029 # # FPSIMD-7-1: PID: 1185
11538 09:30:57.125621 # # FPSIMD-6-1: Vector length: 128 bits
11539 09:30:57.128772 # # FPSIMD-6-1: PID: 1183
11540 09:30:57.131922 # # FPSIMD-4-0: Vector length: 128 bits
11541 09:30:57.135460 # # FPSIMD-4-0: PID: 1178
11542 09:30:57.138780 # # FPSIMD-4-1: Vector length: 128 bits
11543 09:30:57.139191 # # FPSIMD-4-1: PID: 1179
11544 09:30:57.141797 # # FPSIMD-6-0: Vector length: 128 bits
11545 09:30:57.145339 # # FPSIMD-6-0: PID: 1182
11546 09:30:57.148625 # # FPSIMD-3-1: Vector length: 128 bits
11547 09:30:57.152417 # # FPSIMD-3-1: PID: 1177
11548 09:30:57.155286 # # FPSIMD-5-1: Vector length: 128 bits
11549 09:30:57.158833 # # FPSIMD-5-1: PID: 1181
11550 09:30:57.161816 # # FPSIMD-7-0: Vector length: 128 bits
11551 09:30:57.165212 # # FPSIMD-7-0: PID: 1184
11552 09:30:57.168139 # # FPSIMD-2-0: Vector length: 128 bits
11553 09:30:57.168687 # # FPSIMD-2-0: PID: 1174
11554 09:30:57.172015 # # Finishing up...
11555 09:30:57.178056 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=894295, signals=10
11556 09:30:57.184839 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1189229, signals=10
11557 09:30:57.191302 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1362143, signals=10
11558 09:30:57.201532 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1289820, signals=10
11559 09:30:57.208223 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1180192, signals=10
11560 09:30:57.214296 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1103958, signals=10
11561 09:30:57.221454 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=2097708, signals=10
11562 09:30:57.224644 # ok 1 FPSIMD-0-0
11563 09:30:57.225146 # ok 2 FPSIMD-0-1
11564 09:30:57.227424 # ok 3 FPSIMD-1-0
11565 09:30:57.227839 # ok 4 FPSIMD-1-1
11566 09:30:57.231489 # ok 5 FPSIMD-2-0
11567 09:30:57.232005 # ok 6 FPSIMD-2-1
11568 09:30:57.234622 # ok 7 FPSIMD-3-0
11569 09:30:57.235146 # ok 8 FPSIMD-3-1
11570 09:30:57.237437 # ok 9 FPSIMD-4-0
11571 09:30:57.237852 # ok 10 FPSIMD-4-1
11572 09:30:57.241225 # ok 11 FPSIMD-5-0
11573 09:30:57.241682 # ok 12 FPSIMD-5-1
11574 09:30:57.244224 # ok 13 FPSIMD-6-0
11575 09:30:57.244634 # ok 14 FPSIMD-6-1
11576 09:30:57.247796 # ok 15 FPSIMD-7-0
11577 09:30:57.248310 # ok 16 FPSIMD-7-1
11578 09:30:57.254270 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1238432, signals=9
11579 09:30:57.264208 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1113429, signals=10
11580 09:30:57.270495 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=826994, signals=10
11581 09:30:57.276979 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1155443, signals=10
11582 09:30:57.283601 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1354789, signals=10
11583 09:30:57.290452 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=931772, signals=10
11584 09:30:57.300465 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=924469, signals=10
11585 09:30:57.307002 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1329986, signals=10
11586 09:30:57.313395 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1214182, signals=9
11587 09:30:57.317081 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11588 09:30:57.320031 ok 29 selftests: arm64: fp-stress
11589 09:30:57.323072 # selftests: arm64: sve-ptrace
11590 09:30:57.326595 # TAP version 13
11591 09:30:57.327009 # 1..4104
11592 09:30:57.329839 # ok 2 # SKIP SVE not available
11593 09:30:57.332762 # # Planned tests != run tests (4104 != 1)
11594 09:30:57.339717 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11595 09:30:57.342647 ok 30 selftests: arm64: sve-ptrace # SKIP
11596 09:30:57.346067 # selftests: arm64: sve-probe-vls
11597 09:30:57.346489 # TAP version 13
11598 09:30:57.346819 # 1..2
11599 09:30:57.349795 # ok 2 # SKIP SVE not available
11600 09:30:57.352807 # # Planned tests != run tests (2 != 1)
11601 09:30:57.359368 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11602 09:30:57.362333 ok 31 selftests: arm64: sve-probe-vls # SKIP
11603 09:30:57.365571 # selftests: arm64: vec-syscfg
11604 09:30:57.366005 # TAP version 13
11605 09:30:57.368893 # 1..20
11606 09:30:57.369344 # ok 1 # SKIP SVE not supported
11607 09:30:57.372484 # ok 2 # SKIP SVE not supported
11608 09:30:57.375416 # ok 3 # SKIP SVE not supported
11609 09:30:57.378664 # ok 4 # SKIP SVE not supported
11610 09:30:57.382046 # ok 5 # SKIP SVE not supported
11611 09:30:57.385338 # ok 6 # SKIP SVE not supported
11612 09:30:57.388874 # ok 7 # SKIP SVE not supported
11613 09:30:57.392040 # ok 8 # SKIP SVE not supported
11614 09:30:57.392496 # ok 9 # SKIP SVE not supported
11615 09:30:57.395791 # ok 10 # SKIP SVE not supported
11616 09:30:57.398815 # ok 11 # SKIP SME not supported
11617 09:30:57.402240 # ok 12 # SKIP SME not supported
11618 09:30:57.405390 # ok 13 # SKIP SME not supported
11619 09:30:57.408425 # ok 14 # SKIP SME not supported
11620 09:30:57.411493 # ok 15 # SKIP SME not supported
11621 09:30:57.415030 # ok 16 # SKIP SME not supported
11622 09:30:57.418554 # ok 17 # SKIP SME not supported
11623 09:30:57.419002 # ok 18 # SKIP SME not supported
11624 09:30:57.421907 # ok 19 # SKIP SME not supported
11625 09:30:57.425373 # ok 20 # SKIP SME not supported
11626 09:30:57.431731 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11627 09:30:57.434540 ok 32 selftests: arm64: vec-syscfg
11628 09:30:57.438165 # selftests: arm64: za-fork
11629 09:30:57.438606 # TAP version 13
11630 09:30:57.438944 # 1..1
11631 09:30:57.441237 # # PID: 1262
11632 09:30:57.441845 # # SME support not present
11633 09:30:57.444939 # ok 0 skipped
11634 09:30:57.447931 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11635 09:30:57.451244 ok 33 selftests: arm64: za-fork
11636 09:30:57.454340 # selftests: arm64: za-ptrace
11637 09:30:57.518262 # TAP version 13
11638 09:30:57.518388 # 1..1
11639 09:30:57.521197 # ok 2 # SKIP SME not available
11640 09:30:57.527793 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11641 09:30:57.531186 ok 34 selftests: arm64: za-ptrace # SKIP
11642 09:30:57.544361 # selftests: arm64: check_buffer_fill
11643 09:30:57.625324 # # SKIP: MTE features unavailable
11644 09:30:57.632595 ok 35 selftests: arm64: check_buffer_fill # SKIP
11645 09:30:57.652001 # selftests: arm64: check_child_memory
11646 09:30:57.731752 # # SKIP: MTE features unavailable
11647 09:30:57.739156 ok 36 selftests: arm64: check_child_memory # SKIP
11648 09:30:57.755616 # selftests: arm64: check_gcr_el1_cswitch
11649 09:30:57.816328 # # SKIP: MTE features unavailable
11650 09:30:57.823590 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11651 09:30:57.840770 # selftests: arm64: check_ksm_options
11652 09:30:57.901439 # # SKIP: MTE features unavailable
11653 09:30:57.909249 ok 38 selftests: arm64: check_ksm_options # SKIP
11654 09:30:57.927625 # selftests: arm64: check_mmap_options
11655 09:30:57.981356 # # SKIP: MTE features unavailable
11656 09:30:57.988715 ok 39 selftests: arm64: check_mmap_options # SKIP
11657 09:30:58.004084 # selftests: arm64: check_prctl
11658 09:30:58.070165 # TAP version 13
11659 09:30:58.070604 # 1..5
11660 09:30:58.073788 # ok 1 check_basic_read
11661 09:30:58.074202 # ok 2 NONE
11662 09:30:58.076972 # ok 3 # SKIP SYNC
11663 09:30:58.077478 # ok 4 # SKIP ASYNC
11664 09:30:58.079874 # ok 5 # SKIP SYNC+ASYNC
11665 09:30:58.083488 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11666 09:30:58.086527 ok 40 selftests: arm64: check_prctl
11667 09:30:58.103527 # selftests: arm64: check_tags_inclusion
11668 09:30:58.162973 # # SKIP: MTE features unavailable
11669 09:30:58.170725 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11670 09:30:58.186133 # selftests: arm64: check_user_mem
11671 09:30:58.255928 # # SKIP: MTE features unavailable
11672 09:30:58.262728 ok 42 selftests: arm64: check_user_mem # SKIP
11673 09:30:58.276963 # selftests: arm64: btitest
11674 09:30:58.334836 # TAP version 13
11675 09:30:58.335355 # 1..18
11676 09:30:58.338551 # # HWCAP_PACA not present
11677 09:30:58.341483 # # HWCAP2_BTI not present
11678 09:30:58.341900 # # Test binary built for BTI
11679 09:30:58.348319 # ok 1 nohint_func/call_using_br_x0 # SKIP
11680 09:30:58.351169 # ok 1 nohint_func/call_using_br_x16 # SKIP
11681 09:30:58.354756 # ok 1 nohint_func/call_using_blr # SKIP
11682 09:30:58.358095 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11683 09:30:58.361244 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11684 09:30:58.367958 # ok 1 bti_none_func/call_using_blr # SKIP
11685 09:30:58.370865 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11686 09:30:58.374383 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11687 09:30:58.377954 # ok 1 bti_c_func/call_using_blr # SKIP
11688 09:30:58.380861 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11689 09:30:58.384546 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11690 09:30:58.388031 # ok 1 bti_j_func/call_using_blr # SKIP
11691 09:30:58.390814 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11692 09:30:58.397814 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11693 09:30:58.400892 # ok 1 bti_jc_func/call_using_blr # SKIP
11694 09:30:58.404388 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11695 09:30:58.407573 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11696 09:30:58.410512 # ok 1 paciasp_func/call_using_blr # SKIP
11697 09:30:58.417166 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11698 09:30:58.420791 # # WARNING - EXPECTED TEST COUNT WRONG
11699 09:30:58.424121 ok 43 selftests: arm64: btitest
11700 09:30:58.427272 # selftests: arm64: nobtitest
11701 09:30:58.437654 # TAP version 13
11702 09:30:58.438165 # 1..18
11703 09:30:58.440924 # # HWCAP_PACA not present
11704 09:30:58.443976 # # HWCAP2_BTI not present
11705 09:30:58.446942 # # Test binary not built for BTI
11706 09:30:58.450822 # ok 1 nohint_func/call_using_br_x0 # SKIP
11707 09:30:58.453795 # ok 1 nohint_func/call_using_br_x16 # SKIP
11708 09:30:58.456872 # ok 1 nohint_func/call_using_blr # SKIP
11709 09:30:58.460652 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11710 09:30:58.463600 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11711 09:30:58.470568 # ok 1 bti_none_func/call_using_blr # SKIP
11712 09:30:58.473854 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11713 09:30:58.476899 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11714 09:30:58.480480 # ok 1 bti_c_func/call_using_blr # SKIP
11715 09:30:58.483492 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11716 09:30:58.486899 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11717 09:30:58.490246 # ok 1 bti_j_func/call_using_blr # SKIP
11718 09:30:58.496719 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11719 09:30:58.500201 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11720 09:30:58.503358 # ok 1 bti_jc_func/call_using_blr # SKIP
11721 09:30:58.506838 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11722 09:30:58.510233 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11723 09:30:58.513619 # ok 1 paciasp_func/call_using_blr # SKIP
11724 09:30:58.519567 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11725 09:30:58.523307 # # WARNING - EXPECTED TEST COUNT WRONG
11726 09:30:58.526470 ok 44 selftests: arm64: nobtitest
11727 09:30:58.529366 # selftests: arm64: hwcap
11728 09:30:58.543752 # TAP version 13
11729 09:30:58.544163 # 1..28
11730 09:30:58.547251 # ok 1 cpuinfo_match_RNG
11731 09:30:58.550245 # # SIGILL reported for RNG
11732 09:30:58.550657 # ok 2 # SKIP sigill_RNG
11733 09:30:58.553301 # ok 3 cpuinfo_match_SME
11734 09:30:58.557107 # ok 4 sigill_SME
11735 09:30:58.557564 # ok 5 cpuinfo_match_SVE
11736 09:30:58.560159 # ok 6 sigill_SVE
11737 09:30:58.560566 # ok 7 cpuinfo_match_SVE 2
11738 09:30:58.563224 # # SIGILL reported for SVE 2
11739 09:30:58.566812 # ok 8 # SKIP sigill_SVE 2
11740 09:30:58.569814 # ok 9 cpuinfo_match_SVE AES
11741 09:30:58.573358 # # SIGILL reported for SVE AES
11742 09:30:58.573777 # ok 10 # SKIP sigill_SVE AES
11743 09:30:58.576686 # ok 11 cpuinfo_match_SVE2 PMULL
11744 09:30:58.580148 # # SIGILL reported for SVE2 PMULL
11745 09:30:58.583035 # ok 12 # SKIP sigill_SVE2 PMULL
11746 09:30:58.586750 # ok 13 cpuinfo_match_SVE2 BITPERM
11747 09:30:58.589774 # # SIGILL reported for SVE2 BITPERM
11748 09:30:58.593412 # ok 14 # SKIP sigill_SVE2 BITPERM
11749 09:30:58.597148 # ok 15 cpuinfo_match_SVE2 SHA3
11750 09:30:58.599716 # # SIGILL reported for SVE2 SHA3
11751 09:30:58.602969 # ok 16 # SKIP sigill_SVE2 SHA3
11752 09:30:58.606695 # ok 17 cpuinfo_match_SVE2 SM4
11753 09:30:58.607106 # # SIGILL reported for SVE2 SM4
11754 09:30:58.609500 # ok 18 # SKIP sigill_SVE2 SM4
11755 09:30:58.612840 # ok 19 cpuinfo_match_SVE2 I8MM
11756 09:30:58.616436 # # SIGILL reported for SVE2 I8MM
11757 09:30:58.619703 # ok 20 # SKIP sigill_SVE2 I8MM
11758 09:30:58.622705 # ok 21 cpuinfo_match_SVE2 F32MM
11759 09:30:58.626058 # # SIGILL reported for SVE2 F32MM
11760 09:30:58.629455 # ok 22 # SKIP sigill_SVE2 F32MM
11761 09:30:58.632567 # ok 23 cpuinfo_match_SVE2 F64MM
11762 09:30:58.635865 # # SIGILL reported for SVE2 F64MM
11763 09:30:58.636276 # ok 24 # SKIP sigill_SVE2 F64MM
11764 09:30:58.639648 # ok 25 cpuinfo_match_SVE2 BF16
11765 09:30:58.642757 # # SIGILL reported for SVE2 BF16
11766 09:30:58.645779 # ok 26 # SKIP sigill_SVE2 BF16
11767 09:30:58.649303 # ok 27 cpuinfo_match_SVE2 EBF16
11768 09:30:58.653006 # ok 28 # SKIP sigill_SVE2 EBF16
11769 09:30:58.655858 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11770 09:30:58.659081 ok 45 selftests: arm64: hwcap
11771 09:30:58.662108 # selftests: arm64: ptrace
11772 09:30:58.665718 # TAP version 13
11773 09:30:58.666131 # 1..7
11774 09:30:58.668865 # # Parent is 1504, child is 1505
11775 09:30:58.669315 # ok 1 read_tpidr_one
11776 09:30:58.672457 # ok 2 write_tpidr_one
11777 09:30:58.675545 # ok 3 verify_tpidr_one
11778 09:30:58.675956 # ok 4 count_tpidrs
11779 09:30:58.678721 # ok 5 tpidr2_write
11780 09:30:58.679131 # ok 6 tpidr2_read
11781 09:30:58.682148 # ok 7 write_tpidr_only
11782 09:30:58.685518 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11783 09:30:58.688732 ok 46 selftests: arm64: ptrace
11784 09:30:58.691908 # selftests: arm64: syscall-abi
11785 09:30:58.728760 # TAP version 13
11786 09:30:58.729438 # 1..2
11787 09:30:58.731671 # ok 1 getpid() FPSIMD
11788 09:30:58.735029 # ok 2 sched_yield() FPSIMD
11789 09:30:58.738477 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11790 09:30:58.741489 ok 47 selftests: arm64: syscall-abi
11791 09:30:58.753013 # selftests: arm64: tpidr2
11792 09:30:58.813713 # TAP version 13
11793 09:30:58.814233 # 1..5
11794 09:30:58.817154 # # PID: 1541
11795 09:30:58.817695 # # SME support not present
11796 09:30:58.820536 # ok 0 skipped, TPIDR2 not supported
11797 09:30:58.823858 # ok 1 skipped, TPIDR2 not supported
11798 09:30:58.826942 # ok 2 skipped, TPIDR2 not supported
11799 09:30:58.830646 # ok 3 skipped, TPIDR2 not supported
11800 09:30:58.833605 # ok 4 skipped, TPIDR2 not supported
11801 09:30:58.840237 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11802 09:30:58.843656 ok 48 selftests: arm64: tpidr2
11803 09:31:00.439903 arm64_tags_test pass
11804 09:31:00.442929 arm64_run_tags_test_sh pass
11805 09:31:00.445763 arm64_fake_sigreturn_bad_magic pass
11806 09:31:00.448963 arm64_fake_sigreturn_bad_size pass
11807 09:31:00.453183 arm64_fake_sigreturn_bad_size_for_magic0 pass
11808 09:31:00.456365 arm64_fake_sigreturn_duplicated_fpsimd pass
11809 09:31:00.459520 arm64_fake_sigreturn_misaligned_sp pass
11810 09:31:00.462340 arm64_fake_sigreturn_missing_fpsimd pass
11811 09:31:00.466097 arm64_fake_sigreturn_sme_change_vl skip
11812 09:31:00.472546 arm64_fake_sigreturn_sve_change_vl skip
11813 09:31:00.475872 arm64_mangle_pstate_invalid_compat_toggle pass
11814 09:31:00.479031 arm64_mangle_pstate_invalid_daif_bits pass
11815 09:31:00.482669 arm64_mangle_pstate_invalid_mode_el1h pass
11816 09:31:00.485852 arm64_mangle_pstate_invalid_mode_el1t pass
11817 09:31:00.489168 arm64_mangle_pstate_invalid_mode_el2h pass
11818 09:31:00.495708 arm64_mangle_pstate_invalid_mode_el2t pass
11819 09:31:00.499400 arm64_mangle_pstate_invalid_mode_el3h pass
11820 09:31:00.502045 arm64_mangle_pstate_invalid_mode_el3t pass
11821 09:31:00.505606 arm64_sme_trap_no_sm skip
11822 09:31:00.508806 arm64_sme_trap_non_streaming skip
11823 09:31:00.509323 arm64_sme_trap_za pass
11824 09:31:00.512147 arm64_sme_vl skip
11825 09:31:00.512605 arm64_ssve_regs skip
11826 09:31:00.515280 arm64_sve_regs skip
11827 09:31:00.515740 arm64_sve_vl skip
11828 09:31:00.518791 arm64_za_no_regs skip
11829 09:31:00.519265 arm64_za_regs skip
11830 09:31:00.521711 arm64_pac_PAUTH_not_enabled skip
11831 09:31:00.525401 arm64_pac_PAUTH_not_enabled_dup2 skip
11832 09:31:00.528798 arm64_pac_Generic_PAUTH_not_enabled skip
11833 09:31:00.531718 arm64_pac_PAUTH_not_enabled_dup3 skip
11834 09:31:00.538725 arm64_pac_PAUTH_not_enabled_dup4 skip
11835 09:31:00.541959 arm64_pac_PAUTH_not_enabled_dup5 skip
11836 09:31:00.544903 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11837 09:31:00.545346 arm64_pac pass
11838 09:31:00.548395 arm64_fp-stress_FPSIMD-0-0 pass
11839 09:31:00.551887 arm64_fp-stress_FPSIMD-0-1 pass
11840 09:31:00.555220 arm64_fp-stress_FPSIMD-1-0 pass
11841 09:31:00.558408 arm64_fp-stress_FPSIMD-1-1 pass
11842 09:31:00.561464 arm64_fp-stress_FPSIMD-2-0 pass
11843 09:31:00.561986 arm64_fp-stress_FPSIMD-2-1 pass
11844 09:31:00.564594 arm64_fp-stress_FPSIMD-3-0 pass
11845 09:31:00.567983 arm64_fp-stress_FPSIMD-3-1 pass
11846 09:31:00.571414 arm64_fp-stress_FPSIMD-4-0 pass
11847 09:31:00.574644 arm64_fp-stress_FPSIMD-4-1 pass
11848 09:31:00.578179 arm64_fp-stress_FPSIMD-5-0 pass
11849 09:31:00.581126 arm64_fp-stress_FPSIMD-5-1 pass
11850 09:31:00.584909 arm64_fp-stress_FPSIMD-6-0 pass
11851 09:31:00.585477 arm64_fp-stress_FPSIMD-6-1 pass
11852 09:31:00.587511 arm64_fp-stress_FPSIMD-7-0 pass
11853 09:31:00.591439 arm64_fp-stress_FPSIMD-7-1 pass
11854 09:31:00.594880 arm64_fp-stress pass
11855 09:31:00.597952 arm64_sve-ptrace_SVE_not_available skip
11856 09:31:00.598458 arm64_sve-ptrace skip
11857 09:31:00.604016 arm64_sve-probe-vls_SVE_not_available skip
11858 09:31:00.604431 arm64_sve-probe-vls skip
11859 09:31:00.607706 arm64_vec-syscfg_SVE_not_supported skip
11860 09:31:00.614022 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11861 09:31:00.617660 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11862 09:31:00.620576 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11863 09:31:00.623849 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11864 09:31:00.627398 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11865 09:31:00.633773 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11866 09:31:00.637570 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11867 09:31:00.640608 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11868 09:31:00.644400 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11869 09:31:00.647209 arm64_vec-syscfg_SME_not_supported skip
11870 09:31:00.654166 arm64_vec-syscfg_SME_not_supported_dup2 skip
11871 09:31:00.657248 arm64_vec-syscfg_SME_not_supported_dup3 skip
11872 09:31:00.660446 arm64_vec-syscfg_SME_not_supported_dup4 skip
11873 09:31:00.663804 arm64_vec-syscfg_SME_not_supported_dup5 skip
11874 09:31:00.666705 arm64_vec-syscfg_SME_not_supported_dup6 skip
11875 09:31:00.673684 arm64_vec-syscfg_SME_not_supported_dup7 skip
11876 09:31:00.676652 arm64_vec-syscfg_SME_not_supported_dup8 skip
11877 09:31:00.679832 arm64_vec-syscfg_SME_not_supported_dup9 skip
11878 09:31:00.683678 arm64_vec-syscfg_SME_not_supported_dup10 skip
11879 09:31:00.686738 arm64_vec-syscfg pass
11880 09:31:00.689882 arm64_za-fork_skipped pass
11881 09:31:00.690294 arm64_za-fork pass
11882 09:31:00.693189 arm64_za-ptrace_SME_not_available skip
11883 09:31:00.696621 arm64_za-ptrace skip
11884 09:31:00.699828 arm64_check_buffer_fill skip
11885 09:31:00.700238 arm64_check_child_memory skip
11886 09:31:00.702945 arm64_check_gcr_el1_cswitch skip
11887 09:31:00.706401 arm64_check_ksm_options skip
11888 09:31:00.709832 arm64_check_mmap_options skip
11889 09:31:00.712934 arm64_check_prctl_check_basic_read pass
11890 09:31:00.716317 arm64_check_prctl_NONE pass
11891 09:31:00.716728 arm64_check_prctl_SYNC skip
11892 09:31:00.719521 arm64_check_prctl_ASYNC skip
11893 09:31:00.722594 arm64_check_prctl_SYNC_ASYNC skip
11894 09:31:00.726313 arm64_check_prctl pass
11895 09:31:00.729383 arm64_check_tags_inclusion skip
11896 09:31:00.729796 arm64_check_user_mem skip
11897 09:31:00.735926 arm64_btitest_nohint_func_call_using_br_x0 skip
11898 09:31:00.739286 arm64_btitest_nohint_func_call_using_br_x16 skip
11899 09:31:00.742844 arm64_btitest_nohint_func_call_using_blr skip
11900 09:31:00.749483 arm64_btitest_bti_none_func_call_using_br_x0 skip
11901 09:31:00.752646 arm64_btitest_bti_none_func_call_using_br_x16 skip
11902 09:31:00.755794 arm64_btitest_bti_none_func_call_using_blr skip
11903 09:31:00.758624 arm64_btitest_bti_c_func_call_using_br_x0 skip
11904 09:31:00.765413 arm64_btitest_bti_c_func_call_using_br_x16 skip
11905 09:31:00.768503 arm64_btitest_bti_c_func_call_using_blr skip
11906 09:31:00.772183 arm64_btitest_bti_j_func_call_using_br_x0 skip
11907 09:31:00.778401 arm64_btitest_bti_j_func_call_using_br_x16 skip
11908 09:31:00.781912 arm64_btitest_bti_j_func_call_using_blr skip
11909 09:31:00.785344 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11910 09:31:00.788442 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11911 09:31:00.795101 arm64_btitest_bti_jc_func_call_using_blr skip
11912 09:31:00.798562 arm64_btitest_paciasp_func_call_using_br_x0 skip
11913 09:31:00.801644 arm64_btitest_paciasp_func_call_using_br_x16 skip
11914 09:31:00.805054 arm64_btitest_paciasp_func_call_using_blr skip
11915 09:31:00.808040 arm64_btitest pass
11916 09:31:00.811813 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11917 09:31:00.818375 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11918 09:31:00.821800 arm64_nobtitest_nohint_func_call_using_blr skip
11919 09:31:00.824925 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11920 09:31:00.831464 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11921 09:31:00.835068 arm64_nobtitest_bti_none_func_call_using_blr skip
11922 09:31:00.838082 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11923 09:31:00.844817 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11924 09:31:00.847582 arm64_nobtitest_bti_c_func_call_using_blr skip
11925 09:31:00.851379 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11926 09:31:00.857748 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11927 09:31:00.861163 arm64_nobtitest_bti_j_func_call_using_blr skip
11928 09:31:00.864430 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11929 09:31:00.870804 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11930 09:31:00.874051 arm64_nobtitest_bti_jc_func_call_using_blr skip
11931 09:31:00.877744 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11932 09:31:00.883985 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11933 09:31:00.887818 arm64_nobtitest_paciasp_func_call_using_blr skip
11934 09:31:00.890852 arm64_nobtitest pass
11935 09:31:00.893894 arm64_hwcap_cpuinfo_match_RNG pass
11936 09:31:00.894061 arm64_hwcap_sigill_RNG skip
11937 09:31:00.897445 arm64_hwcap_cpuinfo_match_SME pass
11938 09:31:00.901084 arm64_hwcap_sigill_SME pass
11939 09:31:00.904429 arm64_hwcap_cpuinfo_match_SVE pass
11940 09:31:00.907524 arm64_hwcap_sigill_SVE pass
11941 09:31:00.910966 arm64_hwcap_cpuinfo_match_SVE_2 pass
11942 09:31:00.914352 arm64_hwcap_sigill_SVE_2 skip
11943 09:31:00.917627 arm64_hwcap_cpuinfo_match_SVE_AES pass
11944 09:31:00.921161 arm64_hwcap_sigill_SVE_AES skip
11945 09:31:00.924097 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11946 09:31:00.927182 arm64_hwcap_sigill_SVE2_PMULL skip
11947 09:31:00.930630 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11948 09:31:00.934079 arm64_hwcap_sigill_SVE2_BITPERM skip
11949 09:31:00.937090 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11950 09:31:00.940899 arm64_hwcap_sigill_SVE2_SHA3 skip
11951 09:31:00.944013 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11952 09:31:00.946996 arm64_hwcap_sigill_SVE2_SM4 skip
11953 09:31:00.950513 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11954 09:31:00.953774 arm64_hwcap_sigill_SVE2_I8MM skip
11955 09:31:00.956817 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11956 09:31:00.960647 arm64_hwcap_sigill_SVE2_F32MM skip
11957 09:31:00.963747 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11958 09:31:00.966697 arm64_hwcap_sigill_SVE2_F64MM skip
11959 09:31:00.970275 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11960 09:31:00.973552 arm64_hwcap_sigill_SVE2_BF16 skip
11961 09:31:00.977154 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11962 09:31:00.980016 arm64_hwcap_sigill_SVE2_EBF16 skip
11963 09:31:00.983608 arm64_hwcap pass
11964 09:31:00.984087 arm64_ptrace_read_tpidr_one pass
11965 09:31:00.987005 arm64_ptrace_write_tpidr_one pass
11966 09:31:00.990164 arm64_ptrace_verify_tpidr_one pass
11967 09:31:00.993222 arm64_ptrace_count_tpidrs pass
11968 09:31:00.996440 arm64_ptrace_tpidr2_write pass
11969 09:31:01.000240 arm64_ptrace_tpidr2_read pass
11970 09:31:01.003627 arm64_ptrace_write_tpidr_only pass
11971 09:31:01.004043 arm64_ptrace pass
11972 09:31:01.006375 arm64_syscall-abi_getpid_FPSIMD pass
11973 09:31:01.010092 arm64_syscall-abi_sched_yield_FPSIMD pass
11974 09:31:01.013108 arm64_syscall-abi pass
11975 09:31:01.016831 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11976 09:31:01.022825 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
11977 09:31:01.026544 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
11978 09:31:01.029659 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
11979 09:31:01.036137 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
11980 09:31:01.036569 arm64_tpidr2 pass
11981 09:31:01.042734 + ../../utils/send-to-lava.sh ./output/result.txt
11982 09:31:01.046003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11983 09:31:01.046786 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11985 09:31:01.052637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11986 09:31:01.053436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11988 09:31:01.059233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11989 09:31:01.059904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11991 09:31:01.066032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11992 09:31:01.066704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11994 09:31:01.132693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11995 09:31:01.133633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11997 09:31:01.197678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11998 09:31:01.198519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12000 09:31:01.264931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12001 09:31:01.265858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12003 09:31:01.331326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12004 09:31:01.332040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12006 09:31:01.393181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12007 09:31:01.393556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12009 09:31:01.458567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12010 09:31:01.459310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12012 09:31:01.523374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12013 09:31:01.524097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12015 09:31:01.583889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12016 09:31:01.584585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12018 09:31:01.649656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12019 09:31:01.649929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12021 09:31:01.711232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12022 09:31:01.712034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12024 09:31:01.779354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12025 09:31:01.780050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12027 09:31:01.847074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12028 09:31:01.847343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12030 09:31:01.906658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12031 09:31:01.906994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12033 09:31:01.973690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12034 09:31:01.974032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12036 09:31:02.038518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12037 09:31:02.039504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12039 09:31:02.105361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12040 09:31:02.106235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12042 09:31:02.171065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12044 09:31:02.174417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12045 09:31:02.240632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12046 09:31:02.241362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12048 09:31:02.306760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12049 09:31:02.307083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12051 09:31:02.374317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12052 09:31:02.375179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12054 09:31:02.439056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12055 09:31:02.439929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12057 09:31:02.503958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12058 09:31:02.504670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12060 09:31:02.569811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12061 09:31:02.570707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12063 09:31:02.636495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12064 09:31:02.637368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12066 09:31:02.702425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12068 09:31:02.705748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12069 09:31:02.771341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
12070 09:31:02.772266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
12072 09:31:02.835285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12073 09:31:02.836135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12075 09:31:02.902883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
12076 09:31:02.903644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
12078 09:31:02.977416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
12079 09:31:02.978170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
12081 09:31:03.039210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
12082 09:31:03.040153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
12084 09:31:03.102634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
12085 09:31:03.102908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
12087 09:31:03.167415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12088 09:31:03.167737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12090 09:31:03.225058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12091 09:31:03.225378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12093 09:31:03.286652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12094 09:31:03.286945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12096 09:31:03.344978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12097 09:31:03.345317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12099 09:31:03.400293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12100 09:31:03.400556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12102 09:31:03.459267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12103 09:31:03.459563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12105 09:31:03.524746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12106 09:31:03.525057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12108 09:31:03.584005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12109 09:31:03.584298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12111 09:31:03.637566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12112 09:31:03.637876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12114 09:31:03.700010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12115 09:31:03.700858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12117 09:31:03.769924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12118 09:31:03.770856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12120 09:31:03.838656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12121 09:31:03.839718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12123 09:31:03.906892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12124 09:31:03.907864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12126 09:31:03.973054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12127 09:31:03.973814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12129 09:31:04.032665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12130 09:31:04.033384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12132 09:31:04.099261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12133 09:31:04.099966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12135 09:31:04.164348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12136 09:31:04.165055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12138 09:31:04.231387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12139 09:31:04.232074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12141 09:31:04.306857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12142 09:31:04.307564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12144 09:31:04.366454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12145 09:31:04.367185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12147 09:31:04.437199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12148 09:31:04.437942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12150 09:31:04.501341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12151 09:31:04.502104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12153 09:31:04.572343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12154 09:31:04.573139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12156 09:31:04.638101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
12157 09:31:04.638834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
12159 09:31:04.706329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
12160 09:31:04.707147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
12162 09:31:04.771147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
12163 09:31:04.772037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
12165 09:31:04.831115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
12166 09:31:04.831878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
12168 09:31:04.893445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
12169 09:31:04.894153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
12171 09:31:04.954351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
12172 09:31:04.955096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
12174 09:31:05.024311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
12175 09:31:05.025076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
12177 09:31:05.093423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
12178 09:31:05.094151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
12180 09:31:05.160206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
12181 09:31:05.160952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
12183 09:31:05.228335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12184 09:31:05.229131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12186 09:31:05.302759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
12187 09:31:05.303480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
12189 09:31:05.367048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
12190 09:31:05.367351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
12192 09:31:05.427067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
12193 09:31:05.427340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
12195 09:31:05.488319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
12196 09:31:05.488741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
12198 09:31:05.551867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
12199 09:31:05.552696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
12201 09:31:05.618890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
12202 09:31:05.619630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
12204 09:31:05.690496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
12205 09:31:05.691242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
12207 09:31:05.755564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
12208 09:31:05.756279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
12210 09:31:05.825403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
12211 09:31:05.826189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
12213 09:31:05.884527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12214 09:31:05.885317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12216 09:31:05.948053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12217 09:31:05.948781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12219 09:31:06.011963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12220 09:31:06.012738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12222 09:31:06.084770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12223 09:31:06.085731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12225 09:31:06.147803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12226 09:31:06.148602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12228 09:31:06.204766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12229 09:31:06.205298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12231 09:31:06.264871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12232 09:31:06.265192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12234 09:31:06.322451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12236 09:31:06.325688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12237 09:31:06.379780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12238 09:31:06.380524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12240 09:31:06.447977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12241 09:31:06.448708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12243 09:31:06.517847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12244 09:31:06.518537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12246 09:31:06.572295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12247 09:31:06.572997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12249 09:31:06.637189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12250 09:31:06.637529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12252 09:31:06.698457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12253 09:31:06.698774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12255 09:31:06.760196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12257 09:31:06.763248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12258 09:31:06.825600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12259 09:31:06.826292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12261 09:31:06.895215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12262 09:31:06.895914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12264 09:31:06.956404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12265 09:31:06.957117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12267 09:31:07.022261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12268 09:31:07.023001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12270 09:31:07.086492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12271 09:31:07.086973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12273 09:31:07.148301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12274 09:31:07.149156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12276 09:31:07.219619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12277 09:31:07.220350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12279 09:31:07.290020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12280 09:31:07.290749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12282 09:31:07.357836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12283 09:31:07.358147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12285 09:31:07.413732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12286 09:31:07.414008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12288 09:31:07.474905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12289 09:31:07.475197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12291 09:31:07.536964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12292 09:31:07.537287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12294 09:31:07.597363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12295 09:31:07.598082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12297 09:31:07.668308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12298 09:31:07.669020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12300 09:31:07.733115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12301 09:31:07.733887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12303 09:31:07.795976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12304 09:31:07.796677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12306 09:31:07.860490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12307 09:31:07.861283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12309 09:31:07.927856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12310 09:31:07.928567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12312 09:31:07.985944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12313 09:31:07.986645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12315 09:31:08.049736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12316 09:31:08.050153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12318 09:31:08.115104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12319 09:31:08.115885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12321 09:31:08.170751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12322 09:31:08.171662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12324 09:31:08.237753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12325 09:31:08.238559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12327 09:31:08.299375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12328 09:31:08.300089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12330 09:31:08.369073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12331 09:31:08.369841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12333 09:31:08.440572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12334 09:31:08.441377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12336 09:31:08.507799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12337 09:31:08.508492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12339 09:31:08.574047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12340 09:31:08.574763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12342 09:31:08.638703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12343 09:31:08.639431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12345 09:31:08.705991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12346 09:31:08.706702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12348 09:31:08.769286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12349 09:31:08.769989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12351 09:31:08.833796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12352 09:31:08.834477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12354 09:31:08.898014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12355 09:31:08.898769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12357 09:31:08.962431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12358 09:31:08.963165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12360 09:31:09.029331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12361 09:31:09.030126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12363 09:31:09.095537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12364 09:31:09.096269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12366 09:31:09.161420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12367 09:31:09.162159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12369 09:31:09.224619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12370 09:31:09.225356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12372 09:31:09.291674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12373 09:31:09.292476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12375 09:31:09.361135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12376 09:31:09.362052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12378 09:31:09.421450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12379 09:31:09.421726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12381 09:31:09.485726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12382 09:31:09.486417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12384 09:31:09.541150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12385 09:31:09.541411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12387 09:31:09.605110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12388 09:31:09.605452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12390 09:31:09.674884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12391 09:31:09.675569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12393 09:31:09.736395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12394 09:31:09.736736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12396 09:31:09.796755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12397 09:31:09.797461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12399 09:31:09.860917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12400 09:31:09.861225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12402 09:31:09.922995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12403 09:31:09.923689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12405 09:31:09.992047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12406 09:31:09.992748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12408 09:31:10.059486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12409 09:31:10.060253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12411 09:31:10.125072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12412 09:31:10.125887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12414 09:31:10.191058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12415 09:31:10.191776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12417 09:31:10.258041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12418 09:31:10.258843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12420 09:31:10.323699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12421 09:31:10.324556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12423 09:31:10.392726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12424 09:31:10.393530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12426 09:31:10.458008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12428 09:31:10.460954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12429 09:31:10.532353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12430 09:31:10.533248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12432 09:31:10.596579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12434 09:31:10.600025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12435 09:31:10.664654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12436 09:31:10.665450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12438 09:31:10.729620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12440 09:31:10.732251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12441 09:31:10.793120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12442 09:31:10.793843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12444 09:31:10.854334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12445 09:31:10.855030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12447 09:31:10.919859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12448 09:31:10.920570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12450 09:31:10.981853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12451 09:31:10.982131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12453 09:31:11.037087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12454 09:31:11.037845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12456 09:31:11.101922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12458 09:31:11.104747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12459 09:31:11.171047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12460 09:31:11.171753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12462 09:31:11.235342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12463 09:31:11.236024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12465 09:31:11.286841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12466 09:31:11.287114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12468 09:31:11.336209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12470 09:31:11.339483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12471 09:31:11.384133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12473 09:31:11.387243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12474 09:31:11.438090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12475 09:31:11.438360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12477 09:31:11.486761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12478 09:31:11.487034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12480 09:31:11.540470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12481 09:31:11.540744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12483 09:31:11.594448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12484 09:31:11.594725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12486 09:31:11.645193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12487 09:31:11.645507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12489 09:31:11.693505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12490 09:31:11.693779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12492 09:31:11.754006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12493 09:31:11.754281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12495 09:31:11.811732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12496 09:31:11.811991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12498 09:31:11.871545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12499 09:31:11.871823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12501 09:31:11.936052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12502 09:31:11.936331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12504 09:31:11.991036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12505 09:31:11.991742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12507 09:31:12.053398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12508 09:31:12.054149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12510 09:31:12.118694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12511 09:31:12.119388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12513 09:31:12.182898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12514 09:31:12.183593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12516 09:31:12.243829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12517 09:31:12.244276 + set +x
12518 09:31:12.244876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12520 09:31:12.250692 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14407666_1.6.2.3.5>
12521 09:31:12.251598 Received signal: <ENDRUN> 1_kselftest-arm64 14407666_1.6.2.3.5
12522 09:31:12.252162 Ending use of test pattern.
12523 09:31:12.252496 Ending test lava.1_kselftest-arm64 (14407666_1.6.2.3.5), duration 36.70
12525 09:31:12.253915 <LAVA_TEST_RUNNER EXIT>
12526 09:31:12.254519 ok: lava_test_shell seems to have completed
12527 09:31:12.261603 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12528 09:31:12.262386 end: 3.1 lava-test-shell (duration 00:00:38) [common]
12529 09:31:12.262828 end: 3 lava-test-retry (duration 00:00:38) [common]
12530 09:31:12.263266 start: 4 finalize (timeout 00:07:04) [common]
12531 09:31:12.263719 start: 4.1 power-off (timeout 00:00:30) [common]
12532 09:31:12.264435 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
12533 09:31:12.523880 >> Command sent successfully.
12534 09:31:12.533897 Returned 0 in 0 seconds
12535 09:31:12.635206 end: 4.1 power-off (duration 00:00:00) [common]
12537 09:31:12.636705 start: 4.2 read-feedback (timeout 00:07:03) [common]
12538 09:31:12.638003 Listened to connection for namespace 'common' for up to 1s
12539 09:31:13.638628 Finalising connection for namespace 'common'
12540 09:31:13.639315 Disconnecting from shell: Finalise
12541 09:31:13.639709 / #
12542 09:31:13.740733 end: 4.2 read-feedback (duration 00:00:01) [common]
12543 09:31:13.741535 end: 4 finalize (duration 00:00:01) [common]
12544 09:31:13.742189 Cleaning after the job
12545 09:31:13.742742 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/ramdisk
12546 09:31:13.752570 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/kernel
12547 09:31:13.784728 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/dtb
12548 09:31:13.785038 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/nfsrootfs
12549 09:31:13.852638 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407666/tftp-deploy-j8twixqu/modules
12550 09:31:13.858187 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407666
12551 09:31:14.410404 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407666
12552 09:31:14.410588 Job finished correctly